Merge tag 'v3.15-rc1' into perf/urgent

Pick up the latest fixes. Signed-off-by: Ingo Molnar <mingo@kernel.org>
author: Ingo Molnar <mingo@kernel.org> 2014-04-14 10:44:42 -0400
committer: Ingo Molnar <mingo@kernel.org> 2014-04-14 10:44:42 -0400
commit: 740c699a8d316c8bf8593f19e2ca47795e690622 (patch)
tree: a78886955770a477945c5d84e06b2e7678733b54 /arch
parent: e69af4657e7764d03ad555f0b583d9c4217bcefa (diff)
parent: c9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff)
1851 files changed, 71627 insertions, 32252 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index 80bbb8ccd0d1..97ff872c7acc 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -86,9 +86,7 @@ config KPROBES_ON_FTRACE
         optimize on top of function tracing.
 config UPROBES
-        bool "Transparent user-space probes (EXPERIMENTAL)"
+        def_bool n
-        depends on UPROBE_EVENT && PERF_EVENTS
-        default n
        select PERCPU_RWSEM
        help
          Uprobes is the user-space counterpart to kprobes: they
@@ -101,8 +99,6 @@ config UPROBES
            managed by the kernel and kept transparent to the probed
            application. )
-          If in doubt, say "N".
 config HAVE_64BIT_ALIGNED_ACCESS
        def_bool 64BIT && !HAVE_EFFICIENT_UNALIGNED_ACCESS
        help
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index f6c6b345388c..b7ff9a318c31 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -22,6 +22,7 @@ config ALPHA
        select GENERIC_SMP_IDLE_THREAD
        select GENERIC_STRNCPY_FROM_USER
        select GENERIC_STRNLEN_USER
+        select HAVE_ARCH_AUDITSYSCALL
        select HAVE_MOD_ARCH_SPECIFIC
        select MODULES_USE_ELF_RELA
        select ODD_RT_SIGACTION
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index edb4e0097b75..076c35cd6cde 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -254,12 +254,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
        }
 }
-int
-pcibios_enable_device(struct pci_dev *dev, int mask)
-{
-        return pci_enable_resources(dev, mask);
-}
 /*
 *  If we set up a device for bus mastering, we need to check the latency
 *  timer as certain firmware forgets to set it properly, as seen
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 9be30c8cb0c2..9596b0ab108d 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -57,7 +57,7 @@ config ARCH_FLATMEM_ENABLE
 config MMU
        def_bool y
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool y
 config GENERIC_CALIBRATE_DELAY
@@ -356,7 +356,6 @@ config ARC_CURR_IN_REG
 config ARC_MISALIGN_ACCESS
        bool "Emulate unaligned memory access (userspace only)"
-        default N
        select SYSCTL_ARCH_UNALIGN_NO_WARN
        select SYSCTL_ARCH_UNALIGN_ALLOW
        help
diff --git a/arch/arc/boot/.gitignore b/arch/arc/boot/.gitignore
index 5d65b54bf17a..5246969a20c5 100644
--- a/arch/arc/boot/.gitignore
+++ b/arch/arc/boot/.gitignore
@@ -1 +1,2 @@
 *.dtb*
+uImage
diff --git a/arch/arc/boot/dts/nsimosci.dts b/arch/arc/boot/dts/nsimosci.dts
index ea16d782af58..4f31b2eb5cdf 100644
--- a/arch/arc/boot/dts/nsimosci.dts
+++ b/arch/arc/boot/dts/nsimosci.dts
@@ -11,13 +11,16 @@
 / {
        compatible = "snps,nsimosci";
-        clock-frequency = <80000000>;   /* 80 MHZ */
+        clock-frequency = <20000000>;   /* 20 MHZ */
        #address-cells = <1>;
        #size-cells = <1>;
        interrupt-parent = <&intc>;
        chosen {
-                bootargs = "console=tty0 consoleblank=0";
+                /* this is for console on PGU */
+                /* bootargs = "console=tty0 consoleblank=0"; */
+                /* this is for console on serial */
+                bootargs = "earlycon=uart8250,mmio32,0xc0000000,115200n8 console=ttyS0,115200n8 consoleblank=0 debug";
        };
        aliases {
@@ -44,15 +47,14 @@
                };
                uart0: serial@c0000000 {
-                        compatible = "snps,dw-apb-uart";
+                        compatible = "ns8250";
                        reg = <0xc0000000 0x2000>;
                        interrupts = <11>;
-                        #clock-frequency = <80000000>;
                        clock-frequency = <3686400>;
                        baud = <115200>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                        status = "okay";
+                        no-loopback-test = <1>;
                };
                pgu0: pgu@c9000000 {
diff --git a/arch/arc/boot/dts/skeleton.dts b/arch/arc/boot/dts/skeleton.dts
deleted file mode 100644
index 25a84fb5b3dc..000000000000
--- a/arch/arc/boot/dts/skeleton.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-/include/ "skeleton.dtsi"
diff --git a/arch/arc/configs/nsimosci_defconfig b/arch/arc/configs/nsimosci_defconfig
index 451af30914f6..c01ba35a4eff 100644
--- a/arch/arc/configs/nsimosci_defconfig
+++ b/arch/arc/configs/nsimosci_defconfig
@@ -54,6 +54,7 @@ CONFIG_SERIO_ARC_PS2=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_ARC=y
 CONFIG_SERIAL_ARC_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h
index 66ee5527aefc..5faad17118b4 100644
--- a/arch/arc/include/asm/linkage.h
+++ b/arch/arc/include/asm/linkage.h
@@ -13,20 +13,6 @@
 #define ASM_NL           `      /* use '`' to mark new line in macro */
-/* Can't use the ENTRY macro in linux/linkage.h
- * gas considers ';' as comment vs. newline
- */
-.macro ARC_ENTRY name
-        .global \name
-        .align 4
-        \name:
-.endm
-.macro ARC_EXIT name
-#define ASM_PREV_SYM_ADDR(name)  .-##name
-        .size \ name, ASM_PREV_SYM_ADDR(\name)
-.endm
 /* annotation for data we want in DCCM - if enabled in .config */
 .macro ARCFP_DATA nm
 #ifdef CONFIG_ARC_HAS_DCCM
diff --git a/arch/arc/kernel/ctx_sw_asm.S b/arch/arc/kernel/ctx_sw_asm.S
index 65690e7fcc8c..2ff0347a2fd7 100644
--- a/arch/arc/kernel/ctx_sw_asm.S
+++ b/arch/arc/kernel/ctx_sw_asm.S
@@ -62,4 +62,4 @@ __switch_to:
        ld.ab   blink, [sp, 4]
        j       [blink]
-ARC_EXIT __switch_to
+END(__switch_to)
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 47d09d07f093..819dd5f7eb05 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -141,7 +141,7 @@ VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)
 VECTOR   reserved                ; Reserved Exceptions
 .endr
-#include <linux/linkage.h>   /* ARC_{EXTRY,EXIT} */
+#include <linux/linkage.h>   /* {EXTRY,EXIT} */
 #include <asm/entry.h>       /* SAVE_ALL_{INT1,INT2,SYS...} */
 #include <asm/errno.h>
 #include <asm/arcregs.h>
@@ -184,7 +184,7 @@ reserved:		; processor restart
 ; ---------------------------------------------
 ;  Level 2 ISR: Can interrupt a Level 1 ISR
 ; ---------------------------------------------
-ARC_ENTRY handle_interrupt_level2
+ENTRY(handle_interrupt_level2)
        ; TODO-vineetg for SMP this wont work
        ; free up r9 as scratchpad
@@ -225,14 +225,14 @@ ARC_ENTRY handle_interrupt_level2
        b   ret_from_exception
-ARC_EXIT handle_interrupt_level2
+END(handle_interrupt_level2)
 #endif
 ; ---------------------------------------------
 ;  Level 1 ISR
 ; ---------------------------------------------
-ARC_ENTRY handle_interrupt_level1
+ENTRY(handle_interrupt_level1)
        /* free up r9 as scratchpad */
 #ifdef CONFIG_SMP
@@ -265,7 +265,7 @@ ARC_ENTRY handle_interrupt_level1
        sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg
        b   ret_from_exception
-ARC_EXIT handle_interrupt_level1
+END(handle_interrupt_level1)
 ;################### Non TLB Exception Handling #############################
@@ -273,7 +273,7 @@ ARC_EXIT handle_interrupt_level1
 ; Instruction Error Exception Handler
 ; ---------------------------------------------
-ARC_ENTRY instr_service
+ENTRY(instr_service)
        EXCEPTION_PROLOGUE
@@ -284,13 +284,13 @@ ARC_ENTRY instr_service
        bl  do_insterror_or_kprobe
        b   ret_from_exception
-ARC_EXIT instr_service
+END(instr_service)
 ; ---------------------------------------------
 ; Memory Error Exception Handler
 ; ---------------------------------------------
-ARC_ENTRY mem_service
+ENTRY(mem_service)
        EXCEPTION_PROLOGUE
@@ -301,13 +301,13 @@ ARC_ENTRY mem_service
        bl  do_memory_error
        b   ret_from_exception
-ARC_EXIT mem_service
+END(mem_service)
 ; ---------------------------------------------
 ; Machine Check Exception Handler
 ; ---------------------------------------------
-ARC_ENTRY EV_MachineCheck
+ENTRY(EV_MachineCheck)
        EXCEPTION_PROLOGUE
@@ -331,13 +331,13 @@ ARC_ENTRY EV_MachineCheck
        j  do_machine_check_fault
-ARC_EXIT EV_MachineCheck
+END(EV_MachineCheck)
 ; ---------------------------------------------
 ; Protection Violation Exception Handler
 ; ---------------------------------------------
-ARC_ENTRY EV_TLBProtV
+ENTRY(EV_TLBProtV)
        EXCEPTION_PROLOGUE
@@ -385,12 +385,12 @@ ARC_ENTRY EV_TLBProtV
        b   ret_from_exception
-ARC_EXIT EV_TLBProtV
+END(EV_TLBProtV)
 ; ---------------------------------------------
 ; Privilege Violation Exception Handler
 ; ---------------------------------------------
-ARC_ENTRY EV_PrivilegeV
+ENTRY(EV_PrivilegeV)
        EXCEPTION_PROLOGUE
@@ -401,12 +401,12 @@ ARC_ENTRY EV_PrivilegeV
        bl  do_privilege_fault
        b   ret_from_exception
-ARC_EXIT EV_PrivilegeV
+END(EV_PrivilegeV)
 ; ---------------------------------------------
 ; Extension Instruction Exception Handler
 ; ---------------------------------------------
-ARC_ENTRY EV_Extension
+ENTRY(EV_Extension)
        EXCEPTION_PROLOGUE
@@ -417,7 +417,7 @@ ARC_ENTRY EV_Extension
        bl  do_extension_fault
        b   ret_from_exception
-ARC_EXIT EV_Extension
+END(EV_Extension)
 ;######################### System Call Tracing #########################
@@ -504,7 +504,7 @@ trap_with_param:
 ;   (2) Break Points
 ;------------------------------------------------------------------
-ARC_ENTRY EV_Trap
+ENTRY(EV_Trap)
        EXCEPTION_PROLOGUE
@@ -534,9 +534,9 @@ ARC_ENTRY EV_Trap
        jl      [r9]        ; Entry into Sys Call Handler
        ; fall through to ret_from_system_call
-ARC_EXIT EV_Trap
+END(EV_Trap)
-ARC_ENTRY ret_from_system_call
+ENTRY(ret_from_system_call)
        st  r0, [sp, PT_r0]     ; sys call return value in pt_regs
@@ -546,7 +546,7 @@ ARC_ENTRY ret_from_system_call
 ;
 ; If ret to user mode do we need to handle signals, schedule() et al.
-ARC_ENTRY ret_from_exception
+ENTRY(ret_from_exception)
        ; Pre-{IRQ,Trap,Exception} K/U mode from pt_regs->status32
        ld  r8, [sp, PT_status32]   ; returning to User/Kernel Mode
@@ -726,9 +726,9 @@ not_level1_interrupt:
 debug_marker_syscall:
        rtie
-ARC_EXIT ret_from_exception
+END(ret_from_exception)
-ARC_ENTRY ret_from_fork
+ENTRY(ret_from_fork)
        ; when the forked child comes here from the __switch_to function
        ; r0 has the last task pointer.
        ; put last task in scheduler queue
@@ -745,11 +745,11 @@ ARC_ENTRY ret_from_fork
        ; special case of kernel_thread entry point returning back due to
        ; kernel_execve() - pretend return from syscall to ret to userland
        b    ret_from_exception
-ARC_EXIT ret_from_fork
+END(ret_from_fork)
 ;################### Special Sys Call Wrappers ##########################
-ARC_ENTRY sys_clone_wrapper
+ENTRY(sys_clone_wrapper)
        SAVE_CALLEE_SAVED_USER
        bl  @sys_clone
        DISCARD_CALLEE_SAVED_USER
@@ -759,7 +759,7 @@ ARC_ENTRY sys_clone_wrapper
        bnz  tracesys_exit
        b ret_from_system_call
-ARC_EXIT sys_clone_wrapper
+END(sys_clone_wrapper)
 #ifdef CONFIG_ARC_DW2_UNWIND
 ; Workaround for bug 94179 (STAR ):
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 991997269d02..4ad04915dc6b 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -24,13 +24,13 @@
        .globl stext
 stext:
        ;-------------------------------------------------------------------
-        ; Don't clobber r0-r4 yet. It might have bootloader provided info
+        ; Don't clobber r0-r2 yet. It might have bootloader provided info
        ;-------------------------------------------------------------------
        sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
 #ifdef CONFIG_SMP
-        ; Only Boot (Master) proceeds. Others wait in platform dependent way
+        ; Ensure Boot (Master) proceeds. Others wait in platform dependent way
        ;       IDENTITY Reg [ 3  2  1  0 ]
        ;       (cpu-id)             ^^^        => Zero for UP ARC700
        ;                                       => #Core-ID if SMP (Master 0)
@@ -39,7 +39,8 @@ stext:
        ; need to make sure only boot cpu takes this path.
        GET_CPU_ID  r5
        cmp     r5, 0
-        jnz     arc_platform_smp_wait_to_boot
+        mov.ne  r0, r5
+        jne     arc_platform_smp_wait_to_boot
 #endif
        ; Clear BSS before updating any globals
        ; XXX: use ZOL here
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index e5f3a837fb35..71c42521c77f 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -155,22 +155,6 @@ static void arc_timer_event_setup(unsigned int limit)
        write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
 }
-/*
- * Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic)
- * -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted)
- * -Rearming is done by setting the IE bit
- *
- * Small optimisation: Normal code would have been
- *   if (irq_reenable)
- *     CTRL_REG = (IE | NH);
- *   else
- *     CTRL_REG = NH;
- * However since IE is BIT0 we can fold the branch
- */
-static void arc_timer_event_ack(unsigned int irq_reenable)
-{
-        write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
-}
 static int arc_clkevent_set_next_event(unsigned long delta,
                                       struct clock_event_device *dev)
@@ -207,10 +191,22 @@ static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
 static irqreturn_t timer_irq_handler(int irq, void *dev_id)
 {
-        struct clock_event_device *clk = this_cpu_ptr(&arc_clockevent_device);
+        /*
+         * Note that generic IRQ core could have passed @evt for @dev_id if
+         * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
+         */
+        struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
+        int irq_reenable = evt->mode == CLOCK_EVT_MODE_PERIODIC;
+        /*
+         * Any write to CTRL reg ACks the interrupt, we rewrite the
+         * Count when [N]ot [H]alted bit.
+         * And re-arm it if perioid by [I]nterrupt [E]nable bit
+         */
+        write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
+        evt->event_handler(evt);
-        arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC);
-        clk->event_handler(clk);
        return IRQ_HANDLED;
 }
@@ -222,9 +218,8 @@ static struct irqaction arc_timer_irq = {
 /*
 * Setup the local event timer for @cpu
- * N.B. weak so that some exotic ARC SoCs can completely override it
 */
-void __weak arc_local_timer_setup(unsigned int cpu)
+void arc_local_timer_setup(unsigned int cpu)
 {
        struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);
diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S
index bc813d55b6c3..978bf8314dfb 100644
--- a/arch/arc/lib/memcmp.S
+++ b/arch/arc/lib/memcmp.S
@@ -6,7 +6,7 @@
 * published by the Free Software Foundation.
 */
-#include <asm/linkage.h>
+#include <linux/linkage.h>
 #ifdef __LITTLE_ENDIAN__
 #define WORD2 r2
@@ -16,7 +16,7 @@
 #define SHIFT r2
 #endif
-ARC_ENTRY memcmp
+ENTRY(memcmp)
        or      r12,r0,r1
        asl_s   r12,r12,30
        sub     r3,r2,1
@@ -121,4 +121,4 @@ ARC_ENTRY memcmp
 .Lnil:
        j_s.d   [blink]
        mov     r0,0
-ARC_EXIT memcmp
+END(memcmp)
diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S
index b64cc10ac918..3222573e50de 100644
--- a/arch/arc/lib/memcpy-700.S
+++ b/arch/arc/lib/memcpy-700.S
@@ -6,9 +6,9 @@
 * published by the Free Software Foundation.
 */
-#include <asm/linkage.h>
+#include <linux/linkage.h>
-ARC_ENTRY memcpy
+ENTRY(memcpy)
        or      r3,r0,r1
        asl_s   r3,r3,30
        mov_s   r5,r0
@@ -63,4 +63,4 @@ ARC_ENTRY memcpy
 .Lendbloop:
        j_s.d   [blink]
        stb     r12,[r5,0]
-ARC_EXIT memcpy
+END(memcpy)
diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S
index 9b2d88d2e141..d36bd43fc98d 100644
--- a/arch/arc/lib/memset.S
+++ b/arch/arc/lib/memset.S
@@ -6,11 +6,11 @@
 * published by the Free Software Foundation.
 */
-#include <asm/linkage.h>
+#include <linux/linkage.h>
 #define SMALL   7 /* Must be at least 6 to deal with alignment/loop issues.  */
-ARC_ENTRY memset
+ENTRY(memset)
        mov_s   r4,r0
        or      r12,r0,r2
        bmsk.f  r12,r12,1
@@ -46,14 +46,14 @@ ARC_ENTRY memset
        stb.ab  r1,[r4,1]
 .Ltiny_end:
        j_s     [blink]
-ARC_EXIT memset
+END(memset)
 ; memzero: @r0 = mem, @r1 = size_t
 ; memset:  @r0 = mem, @r1 = char, @r2 = size_t
-ARC_ENTRY memzero
+ENTRY(memzero)
    ; adjust bzero args to memset args
    mov r2, r1
    mov r1, 0
    b  memset    ;tail call so need to tinker with blink
-ARC_EXIT memzero
+END(memzero)
diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S
index 9c548c7cf001..b725d5862107 100644
--- a/arch/arc/lib/strchr-700.S
+++ b/arch/arc/lib/strchr-700.S
@@ -11,9 +11,9 @@
   presence of the norm instruction makes it easier to operate on whole
   words branch-free.  */
-#include <asm/linkage.h>
+#include <linux/linkage.h>
-ARC_ENTRY strchr
+ENTRY(strchr)
        extb_s  r1,r1
        asl     r5,r1,8
        bmsk    r2,r0,1
@@ -130,4 +130,4 @@ ARC_ENTRY strchr
        j_s.d   [blink]
        mov.mi  r0,0
 #endif /* ENDIAN */
-ARC_EXIT strchr
+END(strchr)
diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S
index 5dc802b45cf3..3544600fefe6 100644
--- a/arch/arc/lib/strcmp.S
+++ b/arch/arc/lib/strcmp.S
@@ -13,9 +13,9 @@
   source 1; however, that would increase the overhead for loop setup / finish,
   and strcmp might often terminate early.  */
-#include <asm/linkage.h>
+#include <linux/linkage.h>
-ARC_ENTRY strcmp
+ENTRY(strcmp)
        or      r2,r0,r1
        bmsk_s  r2,r2,1
        brne    r2,0,.Lcharloop
@@ -93,4 +93,4 @@ ARC_ENTRY strcmp
 .Lcmpend:
        j_s.d   [blink]
        sub     r0,r2,r3
-ARC_EXIT strcmp
+END(strcmp)
diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S
index b7ca4ae81d88..8422f38e1218 100644
--- a/arch/arc/lib/strcpy-700.S
+++ b/arch/arc/lib/strcpy-700.S
@@ -16,9 +16,9 @@
   there, but the it is not likely to be taken often, and it
   would also be likey to cost an unaligned mispredict at the next call.  */
-#include <asm/linkage.h>
+#include <linux/linkage.h>
-ARC_ENTRY strcpy
+ENTRY(strcpy)
        or      r2,r0,r1
        bmsk_s  r2,r2,1
        brne.d  r2,0,charloop
@@ -67,4 +67,4 @@ charloop:
        brne.d  r3,0,charloop
        stb.ab  r3,[r10,1]
        j       [blink]
-ARC_EXIT strcpy
+END(strcpy)
diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S
index 39759e099696..53cfd5685a5f 100644
--- a/arch/arc/lib/strlen.S
+++ b/arch/arc/lib/strlen.S
@@ -6,9 +6,9 @@
 * published by the Free Software Foundation.
 */
-#include <asm/linkage.h>
+#include <linux/linkage.h>
-ARC_ENTRY strlen
+ENTRY(strlen)
        or      r3,r0,7
        ld      r2,[r3,-7]
        ld.a    r6,[r3,-3]
@@ -80,4 +80,4 @@ ARC_ENTRY strlen
 .Learly_end:
        b.d     .Lend
        sub_s.ne r1,r1,r1
-ARC_EXIT strlen
+END(strlen)
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 400c663b21c2..89edf7961a2f 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -100,10 +100,9 @@
 #define DC_CTRL_INV_MODE_FLUSH  0x40
 #define DC_CTRL_FLUSH_STATUS    0x100
-char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
+char *arc_cache_mumbojumbo(int c, char *buf, int len)
 {
        int n = 0;
-        unsigned int c = smp_processor_id();
 #define PR_CACHE(p, enb, str)                                           \
 {                                                                       \
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 55e0a85bea78..523412369f70 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -10,6 +10,9 @@
 #include <linux/mm.h>
 #include <linux/bootmem.h>
 #include <linux/memblock.h>
+#ifdef CONFIG_BLK_DEV_INITRD
+#include <linux/initrd.h>
+#endif
 #include <linux/swap.h>
 #include <linux/module.h>
 #include <asm/page.h>
@@ -42,6 +45,24 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
        pr_info("Memory size set via devicetree %ldM\n", TO_MB(arc_mem_sz));
 }
+#ifdef CONFIG_BLK_DEV_INITRD
+static int __init early_initrd(char *p)
+{
+        unsigned long start, size;
+        char *endp;
+        start = memparse(p, &endp);
+        if (*endp == ',') {
+                size = memparse(endp + 1, NULL);
+                initrd_start = (unsigned long)__va(start);
+                initrd_end = (unsigned long)__va(start + size);
+        }
+        return 0;
+}
+early_param("initrd", early_initrd);
+#endif
 /*
 * First memory setup routine called from setup_arch()
 * 1. setup swapper's mm @init_mm
@@ -80,6 +101,12 @@ void __init setup_arch_memory(void)
        memblock_reserve(CONFIG_LINUX_LINK_BASE,
                         __pa(_end) - CONFIG_LINUX_LINK_BASE);
+#ifdef CONFIG_BLK_DEV_INITRD
+        /*------------- reserve initrd image -----------------------*/
+        if (initrd_start)
+                memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
+#endif
        memblock_dump_all();
        /*-------------- node setup --------------------------------*/
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index 3fcfdb38d242..79bfc81358c9 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -260,7 +260,7 @@ ARCFP_CODE	;Fast Path Code, candidate for ICCM
 ; I-TLB Miss Exception Handler
 ;-----------------------------------------------------------------------------
-ARC_ENTRY EV_TLBMissI
+ENTRY(EV_TLBMissI)
        TLBMISS_FREEUP_REGS
@@ -293,13 +293,13 @@ ARC_ENTRY EV_TLBMissI
        TLBMISS_RESTORE_REGS
        rtie
-ARC_EXIT EV_TLBMissI
+END(EV_TLBMissI)
 ;-----------------------------------------------------------------------------
 ; D-TLB Miss Exception Handler
 ;-----------------------------------------------------------------------------
-ARC_ENTRY EV_TLBMissD
+ENTRY(EV_TLBMissD)
        TLBMISS_FREEUP_REGS
@@ -381,6 +381,4 @@ do_slow_path_pf:
        bl  do_page_fault
        b   ret_from_exception
-ARC_EXIT EV_TLBMissD
+END(EV_TLBMissD)
-ARC_ENTRY EV_TLBMissB   ; Bogus entry to measure sz of DTLBMiss hdlr
diff --git a/arch/arc/plat-arcfpga/Kconfig b/arch/arc/plat-arcfpga/Kconfig
index 295cefeb25d3..33058aa40e77 100644
--- a/arch/arc/plat-arcfpga/Kconfig
+++ b/arch/arc/plat-arcfpga/Kconfig
@@ -33,7 +33,6 @@ config ISS_SMP_EXTN
        bool "ARC SMP Extensions (ISS Models only)"
        default n
        depends on SMP
-        select ARC_HAS_COH_RTSC
        help
          SMP Extensions to ARC700, in a "simulation only" Model, supported in
          ARC ISS (Instruction Set Simulator).
diff --git a/arch/arc/plat-arcfpga/platform.c b/arch/arc/plat-arcfpga/platform.c
index d71f3c3bcf24..19b76b61f44b 100644
--- a/arch/arc/plat-arcfpga/platform.c
+++ b/arch/arc/plat-arcfpga/platform.c
@@ -201,7 +201,7 @@ static void __init plat_fpga_populate_dev(void)
 * callback set, by matching the DT compatible name.
 */
-static const char *aa4_compat[] __initdata = {
+static const char *aa4_compat[] __initconst = {
        "snps,arc-angel4",
        NULL,
 };
@@ -216,7 +216,7 @@ MACHINE_START(ANGEL4, "angel4")
 #endif
 MACHINE_END
-static const char *ml509_compat[] __initdata = {
+static const char *ml509_compat[] __initconst = {
        "snps,arc-ml509",
        NULL,
 };
@@ -231,7 +231,7 @@ MACHINE_START(ML509, "ml509")
 #endif
 MACHINE_END
-static const char *nsimosci_compat[] __initdata = {
+static const char *nsimosci_compat[] __initconst = {
        "snps,nsimosci",
        NULL,
 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 15949459611f..ab438cb5af55 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -24,6 +24,7 @@ config ARM
        select GENERIC_STRNCPY_FROM_USER
        select GENERIC_STRNLEN_USER
        select HARDIRQS_SW_RESEND
+        select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
        select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
        select HAVE_ARCH_KGDB
        select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
@@ -113,9 +114,6 @@ config ARM_DMA_IOMMU_ALIGNMENT
 endif
-config HAVE_PWM
-        bool
 config MIGHT_HAVE_PCI
        bool
@@ -129,7 +127,7 @@ config HAVE_TCM
 config HAVE_PROC_CPU
        bool
-config NO_IOPORT
+config NO_IOPORT_MAP
        bool
 config EISA
@@ -207,6 +205,9 @@ config ZONE_DMA
 config NEED_DMA_MAP_STATE
       def_bool y
+config ARCH_SUPPORTS_UPROBES
+        def_bool y
 config ARCH_HAS_DMA_SET_COHERENT_MASK
        bool
@@ -306,9 +307,12 @@ choice
 config ARCH_MULTIPLATFORM
        bool "Allow multiple platforms to be selected"
        depends on MMU
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_HAS_SG_CHAIN
        select ARM_PATCH_PHYS_VIRT
        select AUTO_ZRELADDR
        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
        select MULTI_IRQ_HANDLER
        select SPARSE_IRQ
        select USE_OF
@@ -388,8 +392,6 @@ config ARCH_CLPS711X
        select CPU_ARM720T
        select GENERIC_CLOCKEVENTS
        select MFD_SYSCON
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
        help
          Support for Cirrus Logic 711x/721x/731x based boards.
@@ -409,7 +411,7 @@ config ARCH_EBSA110
        select ISA
        select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        help
          This is an evaluation board for the StrongARM processor available
          from Digital. It has limited hardware on-board, including an
@@ -420,16 +422,14 @@ config ARCH_EFM32
        bool "Energy Micro efm32"
        depends on !MMU
        select ARCH_REQUIRE_GPIOLIB
+        select AUTO_ZRELADDR
        select ARM_NVIC
-        # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
-        # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
-        select CLKSRC_MMIO
        select CLKSRC_OF
        select COMMON_CLK
        select CPU_V7M
        select GENERIC_CLOCKEVENTS
        select NO_DMA
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        select SPARSE_IRQ
        select USE_OF
        help
@@ -534,7 +534,6 @@ config ARCH_DOVE
        select PINCTRL
        select PINCTRL_DOVE
        select PLAT_ORION_LEGACY
-        select USB_ARCH_HAS_EHCI
        help
          Support for the Marvell Dove SoC 88AP510
@@ -632,8 +631,6 @@ config ARCH_LPC32XX
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
        select HAVE_IDE
-        select HAVE_PWM
-        select USB_ARCH_HAS_OHCI
        select USE_OF
        help
          Support for the NXP LPC32XX family of processors
@@ -657,9 +654,8 @@ config ARCH_PXA
        help
          Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
-config ARCH_MSM_NODT
+config ARCH_MSM
-        bool "Qualcomm MSM"
+        bool "Qualcomm MSM (non-multiplatform)"
-        select ARCH_MSM
        select ARCH_REQUIRE_GPIOLIB
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
@@ -682,7 +678,7 @@ config ARCH_SHMOBILE_LEGACY
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        select MULTI_IRQ_HANDLER
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        select PINCTRL
        select PM_GENERIC_DOMAINS if PM
        select SPARSE_IRQ
@@ -697,13 +693,14 @@ config ARCH_RPC
        select ARCH_MAY_HAVE_PC_FDC
        select ARCH_SPARSEMEM_ENABLE
        select ARCH_USES_GETTIMEOFFSET
+        select CPU_SA110
        select FIQ
        select HAVE_IDE
        select HAVE_PATA_PLATFORM
        select ISA_DMA_API
        select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        select VIRT_TO_BUS
        help
          On the Acorn Risc-PC, Linux can support the internal IDE disk and
@@ -731,6 +728,7 @@ config ARCH_S3C24XX
        bool "Samsung S3C24XX SoCs"
        select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
+        select ATAGS
        select CLKDEV_LOOKUP
        select CLKSRC_SAMSUNG_PWM
        select GENERIC_CLOCKEVENTS
@@ -753,6 +751,7 @@ config ARCH_S3C64XX
        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
        select ARM_VIC
+        select ATAGS
        select CLKDEV_LOOKUP
        select CLKSRC_SAMSUNG_PWM
        select COMMON_CLK
@@ -762,20 +761,20 @@ config ARCH_S3C64XX
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
        select HAVE_TCM
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        select PLAT_SAMSUNG
-        select PM_GENERIC_DOMAINS
+        select PM_GENERIC_DOMAINS if PM
        select S3C_DEV_NAND
        select S3C_GPIO_TRACK
        select SAMSUNG_ATAGS
        select SAMSUNG_WAKEMASK
        select SAMSUNG_WDT_RESET
-        select USB_ARCH_HAS_OHCI
        help
          Samsung S3C64XX series based systems
 config ARCH_S5P64X0
        bool "Samsung S5P6440 S5P6450"
+        select ATAGS
        select CLKDEV_LOOKUP
        select CLKSRC_SAMSUNG_PWM
        select CPU_V6
@@ -794,6 +793,7 @@ config ARCH_S5P64X0
 config ARCH_S5PC100
        bool "Samsung S5PC100"
        select ARCH_REQUIRE_GPIOLIB
+        select ATAGS
        select CLKDEV_LOOKUP
        select CLKSRC_SAMSUNG_PWM
        select CPU_V7
@@ -813,6 +813,7 @@ config ARCH_S5PV210
        select ARCH_HAS_CPUFREQ
        select ARCH_HAS_HOLES_MEMORYMODEL
        select ARCH_SPARSEMEM_ENABLE
+        select ATAGS
        select CLKDEV_LOOKUP
        select CLKSRC_SAMSUNG_PWM
        select CPU_V7
@@ -886,6 +887,12 @@ menu "Multiple platform selection"
 comment "CPU Core family selection"
+config ARCH_MULTI_V4
+        bool "ARMv4 based platforms (FA526)"
+        depends on !ARCH_MULTI_V6_V7
+        select ARCH_MULTI_V4_V5
+        select CPU_FA526
 config ARCH_MULTI_V4T
        bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
        depends on !ARCH_MULTI_V6_V7
@@ -898,7 +905,7 @@ config ARCH_MULTI_V5
        bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
        depends on !ARCH_MULTI_V6_V7
        select ARCH_MULTI_V4_V5
-        select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
+        select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
                CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
                CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
@@ -908,16 +915,18 @@ config ARCH_MULTI_V4_V5
 config ARCH_MULTI_V6
        bool "ARMv6 based platforms (ARM11)"
        select ARCH_MULTI_V6_V7
-        select CPU_V6
+        select CPU_V6K
 config ARCH_MULTI_V7
        bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
        default y
        select ARCH_MULTI_V6_V7
        select CPU_V7
+        select HAVE_SMP
 config ARCH_MULTI_V6_V7
        bool
+        select MIGHT_HAVE_CACHE_L2X0
 config ARCH_MULTI_CPU_AUTO
        def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
@@ -925,6 +934,13 @@ config ARCH_MULTI_CPU_AUTO
 endmenu
+config ARCH_VIRT
+        bool "Dummy Virtual Machine" if ARCH_MULTI_V7
+        select ARM_AMBA
+        select ARM_GIC
+        select ARM_PSCI
+        select HAVE_ARM_ARCH_TIMER
 #
 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 # Kconfigs may be included either alphabetically (according to the
@@ -936,8 +952,6 @@ source "arch/arm/mach-at91/Kconfig"
 source "arch/arm/mach-bcm/Kconfig"
-source "arch/arm/mach-bcm2835/Kconfig"
 source "arch/arm/mach-berlin/Kconfig"
 source "arch/arm/mach-clps711x/Kconfig"
@@ -1005,6 +1019,8 @@ source "arch/arm/plat-pxa/Kconfig"
 source "arch/arm/mach-mmp/Kconfig"
+source "arch/arm/mach-qcom/Kconfig"
 source "arch/arm/mach-realview/Kconfig"
 source "arch/arm/mach-rockchip/Kconfig"
@@ -1048,8 +1064,6 @@ source "arch/arm/mach-versatile/Kconfig"
 source "arch/arm/mach-vexpress/Kconfig"
 source "arch/arm/plat-versatile/Kconfig"
-source "arch/arm/mach-virt/Kconfig"
 source "arch/arm/mach-vt8500/Kconfig"
 source "arch/arm/mach-w90x900/Kconfig"
@@ -1921,6 +1935,7 @@ config USE_OF
        select IRQ_DOMAIN
        select OF
        select OF_EARLY_FLATTREE
+        select OF_RESERVED_MEM
        help
          Include support for flattened device tree machine descriptions.
@@ -2273,7 +2288,7 @@ source "kernel/power/Kconfig"
 config ARCH_SUSPEND_POSSIBLE
        depends on !ARCH_S5PC100
        depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
-                CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
+                CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
        def_bool y
 config ARM_CPU_SUSPEND
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 0531da8e5216..4a2fc0bf6fc9 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -106,9 +106,14 @@ choice
                depends on ARCH_BCM2835
                select DEBUG_UART_PL01X
+        config DEBUG_BCM_5301X
+                bool "Kernel low-level debugging on BCM5301X UART1"
+                depends on ARCH_BCM_5301X
+                select DEBUG_UART_PL01X
        config DEBUG_BCM_KONA_UART
                bool "Kernel low-level debugging messages via BCM KONA UART"
-                depends on ARCH_BCM
+                depends on ARCH_BCM_MOBILE
                select DEBUG_UART_8250
                help
                  Say Y here if you want kernel low-level debugging support
@@ -171,15 +176,6 @@ choice
                  Say Y here if you want the debug print routines to direct
                  their output to UART0 serial port on DaVinci DMx devices.
-        config DEBUG_DAVINCI_TNETV107X_UART1
-                bool "Kernel low-level debugging on DaVinci TNETV107x using UART1"
-                depends on ARCH_DAVINCI_TNETV107X
-                select DEBUG_UART_8250
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to UART1 serial port on DaVinci TNETV107X
-                  devices.
        config DEBUG_ZYNQ_UART0
                bool "Kernel low-level debugging on Xilinx Zynq using UART0"
                depends on ARCH_ZYNQ
@@ -956,7 +952,7 @@ config DEBUG_STI_UART
 config DEBUG_MSM_UART
        bool
-        depends on ARCH_MSM
+        depends on ARCH_MSM || ARCH_QCOM
 config DEBUG_LL_INCLUDE
        string
@@ -1014,7 +1010,6 @@ config DEBUG_UART_PHYS
        default 0x02530c00 if DEBUG_KEYSTONE_UART0
        default 0x02531000 if DEBUG_KEYSTONE_UART1
        default 0x03010fe0 if ARCH_RPC
-        default 0x08108300 if DEBUG_DAVINCI_TNETV107X_UART1
        default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \
                                DEBUG_VEXPRESS_UART0_CA9
        default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
@@ -1023,6 +1018,7 @@ config DEBUG_UART_PHYS
        default 0x101f1000 if ARCH_VERSATILE
        default 0x101fb000 if DEBUG_NOMADIK_UART
        default 0x16000000 if ARCH_INTEGRATOR
+        default 0x18000300 if DEBUG_BCM_5301X
        default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
        default 0x20060000 if DEBUG_RK29_UART0
        default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
@@ -1071,6 +1067,7 @@ config DEBUG_UART_VIRT
        default 0xf0009000 if DEBUG_CNS3XXX
        default 0xf01fb000 if DEBUG_NOMADIK_UART
        default 0xf0201000 if DEBUG_BCM2835
+        default 0xf1000300 if DEBUG_BCM_5301X
        default 0xf11f1000 if ARCH_VERSATILE
        default 0xf1600000 if ARCH_INTEGRATOR
        default 0xf1c28000 if DEBUG_SUNXI_UART0
@@ -1110,7 +1107,6 @@ config DEBUG_UART_VIRT
        default 0xfed12000 if ARCH_KIRKWOOD
        default 0xfedc0000 if ARCH_EP93XX
        default 0xfee003f8 if FOOTBRIDGE
-        default 0xfee08300 if DEBUG_DAVINCI_TNETV107X_UART1
        default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
        default 0xfef36000 if DEBUG_HIGHBANK_UART
        default 0xfee82340 if ARCH_IOP13XX
@@ -1135,7 +1131,7 @@ config DEBUG_UART_8250_WORD
        default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
                ARCH_KEYSTONE || \
                DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
-                DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
+                DEBUG_DAVINCI_DA8XX_UART2 || \
                DEBUG_BCM_KONA_UART
 config DEBUG_UART_8250_FLOW_CONTROL
@@ -1145,7 +1141,7 @@ config DEBUG_UART_8250_FLOW_CONTROL
 config DEBUG_UNCOMPRESS
        bool
-        depends on ARCH_MULTIPLATFORM || ARCH_MSM
+        depends on ARCH_MULTIPLATFORM || ARCH_MSM || PLAT_SAMSUNG
        default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
                     (!DEBUG_TEGRA_UART || !ZBOOT_ROM)
        help
@@ -1161,7 +1157,8 @@ config DEBUG_UNCOMPRESS
 config UNCOMPRESS_INCLUDE
        string
-        default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM
+        default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
+                                        PLAT_SAMSUNG || ARCH_EFM32
        default "mach/uncompress.h"
 config EARLY_PRINTK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 08a9ef58d9c3..41c1931f0155 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -143,7 +143,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)             += at91
 machine-$(CONFIG_ARCH_BCM)              += bcm
-machine-$(CONFIG_ARCH_BCM2835)          += bcm2835
 machine-$(CONFIG_ARCH_BERLIN)           += berlin
 machine-$(CONFIG_ARCH_CLPS711X)         += clps711x
 machine-$(CONFIG_ARCH_CNS3XXX)          += cns3xxx
@@ -180,6 +179,7 @@ machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
 machine-$(CONFIG_ARCH_ORION5X)          += orion5x
 machine-$(CONFIG_ARCH_PICOXCELL)        += picoxcell
 machine-$(CONFIG_ARCH_PXA)              += pxa
+machine-$(CONFIG_ARCH_QCOM)             += qcom
 machine-$(CONFIG_ARCH_REALVIEW)         += realview
 machine-$(CONFIG_ARCH_ROCKCHIP)         += rockchip
 machine-$(CONFIG_ARCH_RPC)              += rpc
@@ -199,7 +199,6 @@ machine-$(CONFIG_ARCH_U300)		+= u300
 machine-$(CONFIG_ARCH_U8500)            += ux500
 machine-$(CONFIG_ARCH_VERSATILE)        += versatile
 machine-$(CONFIG_ARCH_VEXPRESS)         += vexpress
-machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_VT8500)           += vt8500
 machine-$(CONFIG_ARCH_W90X900)          += w90x900
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
@@ -310,9 +309,9 @@ $(INSTALL_TARGETS):
 %.dtb: | scripts
        $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
-PHONY += dtbs
+PHONY += dtbs dtbs_install
-dtbs: scripts
+dtbs dtbs_install: prepare scripts
-        $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) dtbs
+        $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $@
 # We use MRPROPER_FILES and CLEAN_FILES now
 archclean:
@@ -331,6 +330,7 @@ define archhelp
  echo  '  bootpImage    - Combined zImage and initial RAM disk'
  echo  '                  (supply initrd image via make variable INITRD=<path>)'
  echo  '* dtbs          - Build device tree blobs for enabled boards'
+  echo  '  dtbs_install  - Install dtbs to $(INSTALL_DTBS_PATH)'
  echo  '  install       - Install uncompressed kernel'
  echo  '  zinstall      - Install compressed kernel'
  echo  '  uinstall      - Install U-Boot wrapped compressed kernel'
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 032030361bef..35c146f31e46 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -12,6 +12,8 @@ dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
 dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
+# sam9261
+dtb-$(CONFIG_ARCH_AT91) += at91sam9261ek.dtb
 # sam9263
 dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
@@ -29,6 +31,8 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
 # sam9n12
 dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
+# sam9rl
+dtb-$(CONFIG_ARCH_AT91) += at91sam9rlek.dtb
 # sam9x5
 dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb
@@ -47,19 +51,15 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d36ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
-dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
+dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
-        bcm28155-ap.dtb
+        bcm21664-garnet.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
        berlin2-sony-nsz-gs7.dtb        \
        berlin2cd-google-chromecast.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
        da850-evm.dtb
-dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
-        dove-cubox.dtb \
-        dove-d2plug.dtb \
-        dove-d3plug.dtb \
-        dove-dove-db.dtb
 dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
        exynos4210-smdkv310.dtb \
@@ -82,14 +82,30 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
        ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
        integratorcp.dtb
-dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
+dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
-dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
+        k2l-evm.dtb \
+        k2e-evm.dtb
+kirkwood := \
+        kirkwood-b3.dtb \
+        kirkwood-cloudbox.dtb \
        kirkwood-db-88f6281.dtb \
        kirkwood-db-88f6282.dtb \
        kirkwood-dns320.dtb \
        kirkwood-dns325.dtb \
        kirkwood-dockstar.dtb \
        kirkwood-dreamplug.dtb \
+        kirkwood-ds109.dtb \
+        kirkwood-ds110jv10.dtb \
+        kirkwood-ds111.dtb \
+        kirkwood-ds209.dtb \
+        kirkwood-ds210.dtb \
+        kirkwood-ds212.dtb \
+        kirkwood-ds212j.dtb \
+        kirkwood-ds409.dtb \
+        kirkwood-ds409slim.dtb \
+        kirkwood-ds411.dtb \
+        kirkwood-ds411j.dtb \
+        kirkwood-ds411slim.dtb \
        kirkwood-goflexnet.dtb \
        kirkwood-guruplug-server-plus.dtb \
        kirkwood-ib62x0.dtb \
@@ -112,54 +128,74 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
        kirkwood-nsa310a.dtb \
        kirkwood-openblocks_a6.dtb \
        kirkwood-openblocks_a7.dtb \
+        kirkwood-rd88f6192.dtb \
+        kirkwood-rd88f6281-a0.dtb \
+        kirkwood-rd88f6281-a1.dtb \
+        kirkwood-rs212.dtb \
+        kirkwood-rs409.dtb \
+        kirkwood-rs411.dtb \
        kirkwood-sheevaplug.dtb \
        kirkwood-sheevaplug-esata.dtb \
+        kirkwood-t5325.dtb \
        kirkwood-topkick.dtb \
        kirkwood-ts219-6281.dtb \
-        kirkwood-ts219-6282.dtb
+        kirkwood-ts219-6282.dtb \
+        kirkwood-ts419-6281.dtb \
+        kirkwood-ts419-6282.dtb
+dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood)
+dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood)
+dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
 dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
-dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
-        qcom-msm8960-cdp.dtb \
-        qcom-apq8074-dragonboard.dtb
-dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
-        armada-370-mirabox.dtb \
-        armada-370-netgear-rn102.dtb \
-        armada-370-netgear-rn104.dtb \
-        armada-370-rd.dtb \
-        armada-xp-axpwifiap.dtb \
-        armada-xp-db.dtb \
-        armada-xp-gp.dtb \
-        armada-xp-netgear-rn2120.dtb \
-        armada-xp-matrix.dtb \
-        armada-xp-openblocks-ax3-4.dtb
 dtb-$(CONFIG_ARCH_MXC) += \
+        imx25-eukrea-mbimxsd25-baseboard.dtb \
        imx25-karo-tx25.dtb \
        imx25-pdk.dtb \
        imx27-apf27.dtb \
        imx27-apf27dev.dtb \
        imx27-pdk.dtb \
-        imx27-phytec-phycore-som.dtb \
        imx27-phytec-phycore-rdk.dtb \
-        imx27-phytec-phycard-s-som.dtb \
        imx27-phytec-phycard-s-rdk.dtb \
        imx31-bug.dtb \
+        imx35-eukrea-mbimxsd35-baseboard.dtb \
+        imx50-evk.dtb \
        imx51-apf51.dtb \
        imx51-apf51dev.dtb \
        imx51-babbage.dtb \
+        imx51-eukrea-mbimxsd51-baseboard.dtb \
        imx53-ard.dtb \
-        imx53-evk.dtb \
        imx53-m53evk.dtb \
        imx53-mba53.dtb \
        imx53-qsb.dtb \
+        imx53-qsrb.dtb \
        imx53-smd.dtb \
+        imx53-tx53-x03x.dtb \
+        imx53-tx53-x13x.dtb \
+        imx53-voipac-bsb.dtb \
        imx6dl-cubox-i.dtb \
+        imx6dl-dfi-fs700-m60.dtb \
+        imx6dl-gw51xx.dtb \
+        imx6dl-gw52xx.dtb \
+        imx6dl-gw53xx.dtb \
+        imx6dl-gw54xx.dtb \
        imx6dl-hummingboard.dtb \
+        imx6dl-nitrogen6x.dtb \
        imx6dl-sabreauto.dtb \
+        imx6dl-sabrelite.dtb \
        imx6dl-sabresd.dtb \
        imx6dl-wandboard.dtb \
        imx6q-arm2.dtb \
+        imx6q-cm-fx6.dtb \
        imx6q-cubox-i.dtb \
+        imx6q-dfi-fs700-m60.dtb \
+        imx6q-dmo-edmqmx6.dtb \
+        imx6q-gk802.dtb \
+        imx6q-gw51xx.dtb \
+        imx6q-gw52xx.dtb \
+        imx6q-gw53xx.dtb \
+        imx6q-gw5400-a.dtb \
+        imx6q-gw54xx.dtb \
+        imx6q-nitrogen6x.dtb \
        imx6q-phytec-pbab01.dtb \
        imx6q-sabreauto.dtb \
        imx6q-sabrelite.dtb \
@@ -183,6 +219,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
        imx28-cfa10056.dtb \
        imx28-cfa10057.dtb \
        imx28-cfa10058.dtb \
+        imx28-duckbill.dtb \
+        imx28-eukrea-mbmx283lc.dtb \
+        imx28-eukrea-mbmx287lc.dtb \
        imx28-evk.dtb \
        imx28-m28cu3.dtb \
        imx28-m28evk.dtb \
@@ -199,6 +238,10 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
        omap2420-n810-wimax.dtb \
        omap3430-sdp.dtb \
        omap3-beagle.dtb \
+        omap3-cm-t3517.dtb \
+        omap3-sbc-t3517.dtb \
+        omap3-cm-t3530.dtb \
+        omap3-sbc-t3530.dtb \
        omap3-cm-t3730.dtb \
        omap3-sbc-t3730.dtb \
        omap3-devkit8000.dtb \
@@ -209,12 +252,24 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
        omap3-n900.dtb \
        omap3-n9.dtb \
        omap3-n950.dtb \
+        omap3-overo-alto35.dtb \
+        omap3-overo-storm-alto35.dtb \
+        omap3-overo-chestnut43.dtb \
+        omap3-overo-storm-chestnut43.dtb \
+        omap3-overo-gallop43.dtb \
+        omap3-overo-storm-gallop43.dtb \
+        omap3-overo-palo43.dtb \
+        omap3-overo-storm-palo43.dtb \
+        omap3-overo-summit.dtb \
+        omap3-overo-storm-summit.dtb \
        omap3-overo-tobi.dtb \
        omap3-overo-storm-tobi.dtb \
        omap3-gta04.dtb \
        omap3-igep0020.dtb \
        omap3-igep0030.dtb \
+        omap3-lilly-dbb056.dtb \
        omap3-zoom3.dtb \
+        omap4-duovero-parlor.dtb \
        omap4-panda.dtb \
        omap4-panda-a4.dtb \
        omap4-panda-es.dtb \
@@ -228,12 +283,17 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
        am335x-boneblack.dtb \
        am335x-nano.dtb \
        am335x-base0033.dtb \
+        am3517-craneboard.dtb \
        am3517-evm.dtb \
        am3517_mt_ventoux.dtb \
        am43x-epos-evm.dtb \
+        am437x-gp-evm.dtb \
        dra7-evm.dtb
 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
+        qcom-msm8960-cdp.dtb \
+        qcom-apq8074-dragonboard.dtb
 dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
        ste-hrefprev60-stuib.dtb \
        ste-hrefprev60-tvk.dtb \
@@ -284,6 +344,9 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
        sun4i-a10-cubieboard.dtb \
        sun4i-a10-mini-xplus.dtb \
        sun4i-a10-hackberry.dtb \
+        sun4i-a10-inet97fv2.dtb \
+        sun4i-a10-olinuxino-lime.dtb \
+        sun4i-a10-pcduino.dtb \
        sun5i-a10s-olinuxino-micro.dtb \
        sun5i-a13-olinuxino.dtb \
        sun5i-a13-olinuxino-micro.dtb \
@@ -322,8 +385,31 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
        zynq-zc706.dtb \
        zynq-zed.dtb
+dtb-$(CONFIG_MACH_ARMADA_370) += \
+        armada-370-db.dtb \
+        armada-370-mirabox.dtb \
+        armada-370-netgear-rn102.dtb \
+        armada-370-netgear-rn104.dtb \
+        armada-370-rd.dtb
+dtb-$(CONFIG_MACH_ARMADA_375) += \
+        armada-375-db.dtb
+dtb-$(CONFIG_MACH_ARMADA_38X) += \
+        armada-385-db.dtb \
+        armada-385-rd.dtb
+dtb-$(CONFIG_MACH_ARMADA_XP) += \
+        armada-xp-axpwifiap.dtb \
+        armada-xp-db.dtb \
+        armada-xp-gp.dtb \
+        armada-xp-netgear-rn2120.dtb \
+        armada-xp-matrix.dtb \
+        armada-xp-openblocks-ax3-4.dtb
+dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
+        dove-cubox.dtb \
+        dove-d2plug.dtb \
+        dove-d3plug.dtb \
+        dove-dove-db.dtb
-targets += dtbs
+targets += dtbs dtbs_install
 targets += $(dtb-y)
 endif
@@ -333,3 +419,5 @@ dtbs: $(addprefix $(obj)/, $(dtb-y))
        $(Q)rm -f $(obj)/../*.dtb
 clean-files := *.dtb
+dtbs_install: $(addsuffix _dtbinst_, $(dtb-y))
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 7e6c64ed966d..28ae040e7c3d 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -260,6 +260,12 @@
                >;
        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                >;
+        };
        lcd_pins_s0: lcd_pins_s0 {
                pinctrl-single,pins = <
                        0x20 0x01       /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
@@ -434,9 +440,9 @@
        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
        nand@0,0 {
                reg = <0 0 0>; /* CS0, offset 0 */
-                nand-bus-width = <8>;
                ti,nand-ecc-opt = "bch8";
-                gpmc,device-nand = "true";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <8>;
                gpmc,device-width = <1>;
                gpmc,sync-clk-ps = <0>;
                gpmc,cs-on-ns = <0>;
@@ -460,50 +466,51 @@
                gpmc,wait-monitoring-ns = <0>;
                gpmc,wr-access-ns = <40>;
                gpmc,wr-data-mux-bus-ns = <0>;
+                /* MTD partition table */
+                /* All SPL-* partitions are sized to minimal length
+                 * which can be independently programmable. For
+                 * NAND flash this is equal to size of erase-block */
                #address-cells = <1>;
                #size-cells = <1>;
-                elm_id = <&elm>;
-                /* MTD partition table */
                partition@0 {
-                        label = "SPL1";
+                        label = "NAND.SPL";
                        reg = <0x00000000 0x000020000>;
                };
                partition@1 {
-                        label = "SPL2";
+                        label = "NAND.SPL.backup1";
                        reg = <0x00020000 0x00020000>;
                };
                partition@2 {
-                        label = "SPL3";
+                        label = "NAND.SPL.backup2";
                        reg = <0x00040000 0x00020000>;
                };
                partition@3 {
-                        label = "SPL4";
+                        label = "NAND.SPL.backup3";
                        reg = <0x00060000 0x00020000>;
                };
                partition@4 {
-                        label = "U-boot";
+                        label = "NAND.u-boot-spl";
-                        reg = <0x00080000 0x001e0000>;
+                        reg = <0x00080000 0x00040000>;
                };
                partition@5 {
-                        label = "environment";
+                        label = "NAND.u-boot";
-                        reg = <0x00260000 0x00020000>;
+                        reg = <0x000C0000 0x00100000>;
                };
                partition@6 {
-                        label = "Kernel";
+                        label = "NAND.u-boot-env";
-                        reg = <0x00280000 0x00500000>;
+                        reg = <0x001C0000 0x00020000>;
                };
                partition@7 {
-                        label = "File-System";
+                        label = "NAND.u-boot-env.backup1";
-                        reg = <0x00780000 0x0F880000>;
+                        reg = <0x001E0000 0x00020000>;
+                };
+                partition@8 {
+                        label = "NAND.kernel";
+                        reg = <0x00200000 0x00800000>;
+                };
+                partition@9 {
+                        label = "NAND.file-system";
+                        reg = <0x00A00000 0x0F600000>;
                };
        };
 };
@@ -643,6 +650,9 @@
        status = "okay";
        vmmc-supply = <&vmmc_reg>;
        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 };
 &sham {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 486880b74831..ec08f6f677c3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -45,6 +45,18 @@
                regulator-boot-on;
        };
+        wl12xx_vmmc: fixedregulator@2 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&wl12xx_gpio>;
+                compatible = "regulator-fixed";
+                regulator-name = "vwl1271";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                gpio = <&gpio1 29 0>;
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
        leds {
                pinctrl-names = "default";
                pinctrl-0 = <&user_leds_s0>;
@@ -270,6 +282,24 @@
                        0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
                >;
        };
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
+                        0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+                        0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+                        0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+                        0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+                        0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+                        0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+                >;
+        };
+        wl12xx_gpio: pinmux_wl12xx_gpio {
+                pinctrl-single,pins = <
+                        0x7c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
+                >;
+        };
 };
 &uart0 {
@@ -342,9 +372,22 @@
                status = "okay";
        };
+        usb-phy@47401b00 {
+                status = "okay";
+        };
        usb@47401000 {
                status = "okay";
        };
+        usb@47401800 {
+                status = "okay";
+                dr_mode = "host";
+        };
+        dma-controller@07402000  {
+                status = "okay";
+        };
 };
 &epwmss2 {
@@ -440,6 +483,7 @@
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
+        dual_emac = <1>;
 };
 &davinci_mdio {
@@ -451,11 +495,13 @@
 &cpsw_emac0 {
        phy_id = <&davinci_mdio>, <0>;
        phy-mode = "rgmii-txid";
+        dual_emac_res_vlan = <1>;
 };
 &cpsw_emac1 {
        phy_id = <&davinci_mdio>, <1>;
        phy-mode = "rgmii-txid";
+        dual_emac_res_vlan = <2>;
 };
 &mmc1 {
@@ -479,6 +525,16 @@
        ti,no-reset-on-init;
 };
+&mmc2 {
+        status = "okay";
+        vmmc-supply = <&wl12xx_vmmc>;
+        ti,non-removable;
+        bus-width = <4>;
+        cap-power-off-card;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+};
 &mcasp1 {
                pinctrl-names = "default";
                pinctrl-0 = <&mcasp1_pins>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 6d95d3df33c7..9770e35f2536 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -58,6 +58,10 @@
                                275000  1125000
                        >;
                        voltage-tolerance = <2>; /* 2 percentage */
+                        clocks = <&dpll_mpu_ck>;
+                        clock-names = "cpu";
                        clock-latency = <300000>; /* From omap-cpufreq driver */
                };
        };
@@ -318,6 +322,7 @@
                        compatible = "ti,omap4-hwspinlock";
                        reg = <0x480ca000 0x1000>;
                        ti,hwmods = "spinlock";
+                        #hwlock-cells = <1>;
                };
                wdt2: wdt@44e35000 {
@@ -399,7 +404,7 @@
                        ti,timer-pwm;
                };
-                rtc@44e3e000 {
+                rtc: rtc@44e3e000 {
                        compatible = "ti,da830-rtc";
                        reg = <0x44e3e000 0x1000>;
                        interrupts = <75
@@ -448,7 +453,7 @@
                        ti,hwmods = "usb_otg_hs";
                        status = "disabled";
-                        usb_ctrl_mod: control@44e10000 {
+                        usb_ctrl_mod: control@44e10620 {
                                compatible = "ti,am335x-usb-ctrl-module";
                                reg = <0x44e10620 0x10
                                        0x44e10648 0x4>;
@@ -551,7 +556,7 @@
                                        "tx14", "tx15";
                        };
-                        cppi41dma: dma-controller@07402000 {
+                        cppi41dma: dma-controller@47402000 {
                                compatible = "ti,am3359-cppi41";
                                reg =  <0x47400000 0x1000
                                        0x47402000 0x1000
@@ -582,6 +587,8 @@
                                compatible = "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48300100 0x80>;
+                                interrupts = <31>;
+                                interrupt-names = "ecap0";
                                ti,hwmods = "ecap0";
                                status = "disabled";
                        };
@@ -610,6 +617,8 @@
                                compatible = "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48302100 0x80>;
+                                interrupts = <47>;
+                                interrupt-names = "ecap1";
                                ti,hwmods = "ecap1";
                                status = "disabled";
                        };
@@ -638,6 +647,8 @@
                                compatible = "ti,am33xx-ecap";
                                #pwm-cells = <3>;
                                reg = <0x48304100 0x80>;
+                                interrupts = <61>;
+                                interrupt-names = "ecap2";
                                ti,hwmods = "ecap2";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts
new file mode 100644
index 000000000000..2d40b3f241cd
--- /dev/null
+++ b/arch/arm/boot/dts/am3517-craneboard.dts
@@ -0,0 +1,174 @@
+/*
+ * See craneboard.org for more details
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "am3517.dtsi"
+/ {
+        model = "TI AM3517 CraneBoard (TMDSEVM3517)";
+        compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3";
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>;  /* 256 MB */
+        };
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+};
+&davinci_emac {
+        status = "okay";
+};
+&davinci_mdio {
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <2600000>;
+        tps: tps@2d {
+                reg = <0x2d>;
+        };
+};
+&i2c2 {
+        clock-frequency = <400000>;
+        /* goes to expansion connector */
+        status = "disabled";
+};
+&i2c3 {
+        clock-frequency = <400000>;
+        /* goes to expansion connector */
+        status = "disabled";
+};
+&mmc1 {
+        vmmc-supply = <&vdd2_reg>;
+        bus-width = <8>;
+};
+&mmc2 {
+        /* goes to expansion connector */
+        status = "disabled";
+};
+&mmc3 {
+        /* goes to expansion connector */
+        status = "disabled";
+};
+#include "tps65910.dtsi"
+&omap3_pmx_core {
+        tps_pins: pinmux_tps_pins {
+                pinctrl-single,pins = <
+                        0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */
+                >;
+        };
+};
+&tps {
+        pinctrl-names = "default";
+        pinctrl-0 = <&tps_pins>;
+        interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+        interrupt-parent = <&intc>;
+        ti,en-ck32k-xtal;
+        vcc1-supply = <&vbat>;
+        vcc2-supply = <&vbat>;
+        vcc3-supply = <&vbat>;
+        vcc4-supply = <&vbat>;
+        vcc5-supply = <&vbat>;
+        vcc6-supply = <&vbat>;
+        vcc7-supply = <&vbat>;
+        vccio-supply = <&vbat>;
+        regulators {
+                vrtc_reg: regulator@0 {
+                        regulator-always-on;
+                };
+                vio_reg: regulator@1 {
+                        regulator-always-on;
+                };
+                /*
+                 * Unused:
+                 * VDIG1=2.7V,300mA max
+                 * VDIG2=1.8V,300mA max
+                 */
+                vpll_reg: regulator@7 {
+                        /* VDDS_DPLL_1V8 */
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+                vaux1_reg: regulator@9 {
+                        /* VDDS_SRAM_1V8 */
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+                vaux2_reg: regulator@10 {
+                        /* VDDA1P8V_USBPHY */
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+                /* VAUX33 unused */
+                vdac_reg: regulator@8 {
+                        /* VDDA_DAC_1V8 */
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+                vmmc_reg: regulator@12 {
+                        /* VDDA3P3V_USBPHY */
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                vdd1_reg: regulator@2 {
+                        /* VDD_CORE */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+                vdd2_reg: regulator@3 {
+                        /* VDDSHV_3V3 */
+                        regulator-name = "vdd_shv";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                /* VDD3 unused */
+        };
+};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index c6bd4d986c29..36d523a26831 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -8,6 +8,7 @@
 * kind, whether express or implied.
 */
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "skeleton.dtsi"
@@ -33,6 +34,11 @@
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <0>;
+                        clocks = <&dpll_mpu_ck>;
+                        clock-names = "cpu";
+                        clock-latency = <300000>; /* From omap-cpufreq driver */
                };
        };
@@ -351,6 +357,13 @@
                        status = "disabled";
                };
+                hwspinlock: spinlock@480ca000 {
+                        compatible = "ti,omap4-hwspinlock";
+                        reg = <0x480ca000 0x1000>;
+                        ti,hwmods = "spinlock";
+                        #hwlock-cells = <1>;
+                };
                i2c0: i2c@44e0b000 {
                        compatible = "ti,am4372-i2c","ti,omap4-i2c";
                        reg = <0x44e0b000 0x1000>;
@@ -521,6 +534,7 @@
                        ecap0: ecap@48300100 {
                                compatible = "ti,am4372-ecap","ti,am33xx-ecap";
+                                #pwm-cells = <3>;
                                reg = <0x48300100 0x80>;
                                ti,hwmods = "ecap0";
                                status = "disabled";
@@ -528,6 +542,7 @@
                        ehrpwm0: ehrpwm@48300200 {
                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
                                reg = <0x48300200 0x80>;
                                ti,hwmods = "ehrpwm0";
                                status = "disabled";
@@ -545,6 +560,7 @@
                        ecap1: ecap@48302100 {
                                compatible = "ti,am4372-ecap","ti,am33xx-ecap";
+                                #pwm-cells = <3>;
                                reg = <0x48302100 0x80>;
                                ti,hwmods = "ecap1";
                                status = "disabled";
@@ -552,6 +568,7 @@
                        ehrpwm1: ehrpwm@48302200 {
                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
                                reg = <0x48302200 0x80>;
                                ti,hwmods = "ehrpwm1";
                                status = "disabled";
@@ -569,6 +586,7 @@
                        ecap2: ecap@48304100 {
                                compatible = "ti,am4372-ecap","ti,am33xx-ecap";
+                                #pwm-cells = <3>;
                                reg = <0x48304100 0x80>;
                                ti,hwmods = "ecap2";
                                status = "disabled";
@@ -576,6 +594,7 @@
                        ehrpwm2: ehrpwm@48304200 {
                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
                                reg = <0x48304200 0x80>;
                                ti,hwmods = "ehrpwm2";
                                status = "disabled";
@@ -593,6 +612,7 @@
                        ehrpwm3: ehrpwm@48306200 {
                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
                                reg = <0x48306200 0x80>;
                                ti,hwmods = "ehrpwm3";
                                status = "disabled";
@@ -610,6 +630,7 @@
                        ehrpwm4: ehrpwm@48308200 {
                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
                                reg = <0x48308200 0x80>;
                                ti,hwmods = "ehrpwm4";
                                status = "disabled";
@@ -627,6 +648,7 @@
                        ehrpwm5: ehrpwm@4830a200 {
                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
                                reg = <0x4830a200 0x80>;
                                ti,hwmods = "ehrpwm5";
                                status = "disabled";
@@ -689,6 +711,30 @@
                               <&edma 11>;
                        dma-names = "tx", "rx";
                };
+                elm: elm@48080000 {
+                        compatible = "ti,am3352-elm";
+                        reg = <0x48080000 0x2000>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "elm";
+                        clocks = <&l4ls_gclk>;
+                        clock-names = "fck";
+                        status = "disabled";
+                };
+                gpmc: gpmc@50000000 {
+                        compatible = "ti,am3352-gpmc";
+                        ti,hwmods = "gpmc";
+                        clocks = <&l3s_gclk>;
+                        clock-names = "fck";
+                        reg = <0x50000000 0x2000>;
+                        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+                        gpmc,num-cs = <7>;
+                        gpmc,num-waitpins = <2>;
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
new file mode 100644
index 000000000000..df8798e8bd25
--- /dev/null
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/* AM437x GP EVM */
+/dts-v1/;
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+/ {
+        model = "TI AM437x GP EVM";
+        compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
+        vmmcsd_fixed: fixedregulator-sd {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+                brightness-levels = <0 51 53 56 62 75 101 152 255>;
+                default-brightness-level = <8>;
+        };
+        matrix_keypad: matrix_keypad@0 {
+                compatible = "gpio-matrix-keypad";
+                debounce-delay-ms = <5>;
+                col-scan-delay-us = <2>;
+                row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
+                                &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
+                                &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
+                col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
+                                &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
+                linux,keymap = <0x00000201      /* P1 */
+                                0x00010202      /* P2 */
+                                0x01000067      /* UP */
+                                0x0101006a      /* RIGHT */
+                                0x02000069      /* LEFT */
+                                0x0201006c>;      /* DOWN */
+                };
+};
+&am43xx_pinmux {
+        i2c0_pins: i2c0_pins {
+                pinctrl-single,pins = <
+                        0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
+                        0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
+                >;
+        };
+        i2c1_pins: i2c1_pins {
+                pinctrl-single,pins = <
+                        0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
+                        0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
+                >;
+        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                >;
+        };
+        ecap0_pins: backlight_pins {
+                pinctrl-single,pins = <
+                        0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+                >;
+        };
+};
+&i2c0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+};
+&i2c1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+};
+&epwmss0 {
+        status = "okay";
+};
+&ecap0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&ecap0_pins>;
+};
+&gpio0 {
+        status = "okay";
+};
+&gpio3 {
+        status = "okay";
+};
+&gpio4 {
+        status = "okay";
+};
+&mmc1 {
+        status = "okay";
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c7a94f..167dbc8494de 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -13,6 +13,7 @@
 #include "am4372.dtsi"
 #include <dt-bindings/pinctrl/am43xx.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
 / {
        model = "TI AM43x EPOS EVM";
@@ -79,6 +80,64 @@
                                0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
                        >;
                };
+                nand_flash_x8: nand_flash_x8 {
+                        pinctrl-single,pins = <
+                                0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a0.SELQSPIorNAND/GPIO */
+                                0x0  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
+                                0x4  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
+                                0x8  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
+                                0xc  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
+                                0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
+                                0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
+                                0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
+                                0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
+                                0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                                0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
+                                0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
+                                0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
+                                0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
+                                0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
+                                0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
+                        >;
+                };
+                ecap0_pins: backlight_pins {
+                        pinctrl-single,pins = <
+                                0x164 MUX_MODE0         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+                        >;
+                };
+                i2c2_pins: pinmux_i2c2_pins {
+                        pinctrl-single,pins = <
+                                0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
+                                0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
+                        >;
+                };
+                spi0_pins: pinmux_spi0_pins {
+                        pinctrl-single,pins = <
+                                0x150 (PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
+                                0x154 (PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
+                                0x158 (PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
+                                0x15c (PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
+                        >;
+                };
+                spi1_pins: pinmux_spi1_pins {
+                        pinctrl-single,pins = <
+                                0x190 (PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
+                                0x194 (PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
+                                0x198 (PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
+                                0x19c (PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
+                        >;
+                };
+                mmc1_pins: pinmux_mmc1_pins {
+                        pinctrl-single,pins = <
+                                0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                        >;
+                };
        };
        matrix_keypad: matrix_keypad@0 {
@@ -113,12 +172,22 @@
                                0x0203006c      /* DOWN */
                                0x03030069>;    /* LEFT */
                };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+                brightness-levels = <0 51 53 56 62 75 101 152 255>;
+                default-brightness-level = <8>;
+        };
 };
 &mmc1 {
        status = "okay";
        vmmc-supply = <&vmmcsd_fixed>;
        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 };
 &mac {
@@ -169,6 +238,12 @@
        };
 };
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+        status = "okay";
+};
 &gpio0 {
        status = "okay";
 };
@@ -184,3 +259,111 @@
 &gpio3 {
        status = "okay";
 };
+&elm {
+        status = "okay";
+};
+&gpmc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&nand_flash_x8>;
+        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+        nand@0,0 {
+                reg = <0 0 0>; /* CS0, offset 0 */
+                ti,nand-ecc-opt = "bch8";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <8>;
+                gpmc,device-width = <1>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
+                gpmc,cs-wr-off-ns = <40>;
+                gpmc,adv-on-ns = <0>;  /* cs-on-ns */
+                gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
+                gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
+                gpmc,we-on-ns = <0>;   /* cs-on-ns */
+                gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
+                gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
+                gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
+                gpmc,access-ns = <30>; /* tCEA + 4*/
+                gpmc,rd-cycle-ns = <40>;
+                gpmc,wr-cycle-ns = <40>;
+                gpmc,wait-on-read = "true";
+                gpmc,wait-on-write = "true";
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                /* MTD partition table */
+                /* All SPL-* partitions are sized to minimal length
+                 * which can be independently programmable. For
+                 * NAND flash this is equal to size of erase-block */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "NAND.SPL";
+                        reg = <0x00000000 0x00040000>;
+                };
+                partition@1 {
+                        label = "NAND.SPL.backup1";
+                        reg = <0x00040000 0x00040000>;
+                };
+                partition@2 {
+                        label = "NAND.SPL.backup2";
+                        reg = <0x00080000 0x00040000>;
+                };
+                partition@3 {
+                        label = "NAND.SPL.backup3";
+                        reg = <0x000C0000 0x00040000>;
+                };
+                partition@4 {
+                        label = "NAND.u-boot-spl-os";
+                        reg = <0x00100000 0x00080000>;
+                };
+                partition@5 {
+                        label = "NAND.u-boot";
+                        reg = <0x00180000 0x00100000>;
+                };
+                partition@6 {
+                        label = "NAND.u-boot-env";
+                        reg = <0x00280000 0x00040000>;
+                };
+                partition@7 {
+                        label = "NAND.u-boot-env.backup1";
+                        reg = <0x002C0000 0x00040000>;
+                };
+                partition@8 {
+                        label = "NAND.kernel";
+                        reg = <0x00300000 0x00700000>;
+                };
+                partition@9 {
+                        label = "NAND.file-system";
+                        reg = <0x00800000 0x1F600000>;
+                };
+        };
+};
+&epwmss0 {
+        status = "okay";
+};
+&ecap0 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&ecap0_pins>;
+};
+&spi0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi0_pins>;
+        status = "okay";
+};
+&spi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi1_pins>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 08a56bcfc724..82f238a9063f 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -64,6 +64,22 @@
                                phy-mode = "rgmii-id";
                        };
+                        i2c@11000 {
+                                pinctrl-0 = <&i2c0_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                audio_codec: audio-codec@4a {
+                                        compatible = "cirrus,cs42l51";
+                                        reg = <0x4a>;
+                                };
+                        };
+                        audio-controller@30000 {
+                                pinctrl-0 = <&i2s_pins2>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                        };
                        mvsdio@d4000 {
                                pinctrl-0 = <&sdio_pins1>;
                                pinctrl-names = "default";
@@ -80,6 +96,30 @@
                                broken-cd;
                        };
+                        pinctrl {
+                                /*
+                                 * These pins might be muxed as I2S by
+                                 * the bootloader, but it conflicts
+                                 * with the real I2S pins that are
+                                 * muxed using i2s_pins. We must mux
+                                 * those pins to a function other than
+                                 * I2S.
+                                 */
+                                pinctrl-0 = <&hog_pins1 &hog_pins2>;
+                                pinctrl-names = "default";
+                                hog_pins1: hog-pins1 {
+                                        marvell,pins = "mpp6",  "mpp8", "mpp10",
+                                                       "mpp12", "mpp13";
+                                        marvell,function = "gpio";
+                                };
+                                hog_pins2: hog-pins2 {
+                                        marvell,pins = "mpp5", "mpp7", "mpp9";
+                                        marvell,function = "gpo";
+                                };
+                        };
                        usb@50000 {
                                status = "okay";
                        };
@@ -112,10 +152,26 @@
                                /* Port 0, Lane 0 */
                                status = "okay";
                        };
                        pcie@2,0 {
                                /* Port 1, Lane 0 */
                                status = "okay";
                        };
                };
        };
+        sound {
+              compatible = "marvell,a370db-audio";
+              marvell,audio-controller = <&audio_controller>;
+              marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>;
+              status = "okay";
+        };
+        spdif_out: spdif-out {
+              compatible = "linux,spdif-dit";
+        };
+        spdif_in: spdif-in {
+              compatible = "linux,spdif-dir";
+        };
 };
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 944e8785b308..2354fe023ee0 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -9,6 +9,7 @@
 */
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "armada-370.dtsi"
 / {
@@ -73,19 +74,19 @@
                                green_pwr_led {
                                        label = "mirabox:green:pwr";
-                                        gpios = <&gpio1 31 1>;
+                                        gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
                                        default-state = "keep";
                                };
                                blue_stat_led {
                                        label = "mirabox:blue:stat";
-                                        gpios = <&gpio2 0 1>;
+                                        gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
                                        default-state = "off";
                                };
                                green_stat_led {
                                        label = "mirabox:green:stat";
-                                        gpios = <&gpio2 1 1>;
+                                        gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
                                        default-state = "off";
                                };
                        };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index abbb807459d2..3e2c857d6000 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -12,6 +12,8 @@
 */
 /dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "armada-370.dtsi"
 / {
@@ -100,8 +102,8 @@
                                #size-cells = <0>;
                                button@1 {
                                        label = "Software Button";
-                                        linux,code = <116>;
+                                        linux,code = <KEY_POWER>;
-                                        gpios = <&gpio0 6 1>;
+                                        gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
                                };
                        };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 74b5964430ac..bbb40f62037d 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -44,8 +44,8 @@
                #size-cells = <1>;
                controller = <&mbusc>;
                interrupt-parent = <&mpic>;
-                pcie-mem-aperture = <0xe0000000 0x8000000>;
+                pcie-mem-aperture = <0xf8000000 0x7e00000>;
-                pcie-io-aperture  = <0xe8000000 0x100000>;
+                pcie-io-aperture  = <0xffe00000 0x100000>;
                devbus-bootcs {
                        compatible = "marvell,mvebu-devbus";
@@ -199,6 +199,10 @@
                                interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
                        };
+                        watchdog@20300 {
+                                reg = <0x20300 0x34>, <0x20704 0x4>;
+                        };
                        usb@50000 {
                                compatible = "marvell,orion-ehci";
                                reg = <0x50000 0x500>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 0d8530c98cf5..af1f11e9e5a0 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -132,6 +132,25 @@
                                                        "mpp51", "mpp52", "mpp53";
                                        marvell,function = "sd0";
                                };
+                                i2c0_pins: i2c0-pins {
+                                        marvell,pins = "mpp2", "mpp3";
+                                        marvell,function = "i2c0";
+                                };
+                                i2s_pins1: i2s-pins1 {
+                                        marvell,pins = "mpp5", "mpp6", "mpp7",
+                                                       "mpp8", "mpp9", "mpp10",
+                                                       "mpp12", "mpp13";
+                                        marvell,function = "audio";
+                                };
+                                i2s_pins2: i2s-pins2 {
+                                        marvell,pins = "mpp49", "mpp47", "mpp50",
+                                                       "mpp59", "mpp57", "mpp61",
+                                                       "mpp62", "mpp60", "mpp58";
+                                        marvell,function = "audio";
+                                };
                        };
                        gpio0: gpio@18100 {
@@ -196,6 +215,20 @@
                                clocks = <&coreclk 2>;
                        };
+                        watchdog@20300 {
+                                compatible = "marvell,armada-370-wdt";
+                                clocks = <&coreclk 2>;
+                        };
+                        audio_controller: audio-controller@30000 {
+                                compatible = "marvell,armada370-audio";
+                                reg = <0x30000 0x4000>;
+                                interrupts = <93>;
+                                clocks = <&gateclk 0>;
+                                clock-names = "internal";
+                                status = "disabled";
+                        };
                        usb@50000 {
                                clocks = <&coreclk 0>;
                        };
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
new file mode 100644
index 000000000000..9378d3136b41
--- /dev/null
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -0,0 +1,130 @@
+/*
+ * Device Tree file for Marvell Armada 375 evaluation board
+ * (DB-88F6720)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-375.dtsi"
+/ {
+        model = "Marvell Armada 375 Development Board";
+        compatible = "marvell,a375-db", "marvell,armada375";
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>; /* 1 GB */
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+                internal-regs {
+                        spi@10600 {
+                                pinctrl-0 = <&spi0_pins>;
+                                pinctrl-names = "default";
+                                /*
+                                 * SPI conflicts with NAND, so we disable it
+                                 * here, and select NAND as the enabled device
+                                 * by default.
+                                 */
+                                status = "disabled";
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "n25q128a13";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <108000000>;
+                                };
+                        };
+                        i2c@11000 {
+                                status = "okay";
+                                clock-frequency = <100000>;
+                                pinctrl-0 = <&i2c0_pins>;
+                                pinctrl-names = "default";
+                        };
+                        i2c@11100 {
+                                status = "okay";
+                                clock-frequency = <100000>;
+                                pinctrl-0 = <&i2c1_pins>;
+                                pinctrl-names = "default";
+                        };
+                        serial@12000 {
+                                clock-frequency = <200000000>;
+                                status = "okay";
+                        };
+                        pinctrl {
+                                sdio_st_pins: sdio-st-pins {
+                                        marvell,pins = "mpp44", "mpp45";
+                                        marvell,function = "gpio";
+                                };
+                        };
+                        nand: nand@d0000 {
+                                pinctrl-0 = <&nand_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                                partition@0 {
+                                        label = "U-Boot";
+                                        reg = <0 0x800000>;
+                                };
+                                partition@800000 {
+                                        label = "Linux";
+                                        reg = <0x800000 0x800000>;
+                                };
+                                partition@1000000 {
+                                        label = "Filesystem";
+                                        reg = <0x1000000 0x3f000000>;
+                                };
+                        };
+                        mvsdio@d4000 {
+                                pinctrl-0 = <&sdio_pins &sdio_st_pins>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                                wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                        };
+                };
+                pcie-controller {
+                        status = "okay";
+                        /*
+                         * The two PCIe units are accessible through
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
new file mode 100644
index 000000000000..3877693fb2d8
--- /dev/null
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -0,0 +1,464 @@
+/*
+ * Device Tree Include file for Marvell Armada 375 family SoC
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+/ {
+        model = "Marvell Armada 375 family SoC";
+        compatible = "marvell,armada375";
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+        clocks {
+                /* 2 GHz fixed main PLL */
+                mainpll: mainpll {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <2000000000>;
+                };
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
+        soc {
+                compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+                interrupt-parent = <&gic>;
+                pcie-mem-aperture = <0xe0000000 0x8000000>;
+                pcie-io-aperture  = <0xe8000000 0x100000>;
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+                };
+                devbus-bootcs {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                devbus-cs0 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                devbus-cs1 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                devbus-cs2 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                devbus-cs3 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                internal-regs {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+                        L2: cache-controller@8000 {
+                                compatible = "arm,pl310-cache";
+                                reg = <0x8000 0x1000>;
+                                cache-unified;
+                                cache-level = <2>;
+                        };
+                        timer@c600 {
+                                compatible = "arm,cortex-a9-twd-timer";
+                                reg = <0xc600 0x20>;
+                                interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+                                clocks = <&coreclk 2>;
+                        };
+                        gic: interrupt-controller@d000 {
+                                compatible = "arm,cortex-a9-gic";
+                                #interrupt-cells = <3>;
+                                #size-cells = <0>;
+                                interrupt-controller;
+                                reg = <0xd000 0x1000>,
+                                      <0xc100 0x100>;
+                        };
+                        spi0: spi@10600 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10600 0x50>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        spi1: spi@10680 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10680 0x50>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        i2c0: i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11000 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@11100 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11100 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        serial@12000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12000 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                status = "disabled";
+                        };
+                        serial@12100 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12100 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                status = "disabled";
+                        };
+                        pinctrl {
+                                compatible = "marvell,mv88f6720-pinctrl";
+                                reg = <0x18000 0x24>;
+                                i2c0_pins: i2c0-pins {
+                                        marvell,pins = "mpp14",  "mpp15";
+                                        marvell,function = "i2c0";
+                                };
+                                i2c1_pins: i2c1-pins {
+                                        marvell,pins = "mpp61",  "mpp62";
+                                        marvell,function = "i2c1";
+                                };
+                                nand_pins: nand-pins {
+                                        marvell,pins = "mpp0", "mpp1", "mpp2",
+                                                "mpp3", "mpp4", "mpp5",
+                                                "mpp6", "mpp7", "mpp8",
+                                                "mpp9", "mpp10", "mpp11",
+                                                "mpp12", "mpp13";
+                                        marvell,function = "nand";
+                                };
+                                sdio_pins: sdio-pins {
+                                        marvell,pins = "mpp24",  "mpp25", "mpp26",
+                                                     "mpp27", "mpp28", "mpp29";
+                                        marvell,function = "sd";
+                                };
+                                spi0_pins: spi0-pins {
+                                        marvell,pins = "mpp0",  "mpp1", "mpp4",
+                                                     "mpp5", "mpp8", "mpp9";
+                                        marvell,function = "spi0";
+                                };
+                        };
+                        gpio0: gpio@18100 {
+                                compatible = "marvell,orion-gpio";
+                                reg = <0x18100 0x40>;
+                                ngpios = <32>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        gpio1: gpio@18140 {
+                                compatible = "marvell,orion-gpio";
+                                reg = <0x18140 0x40>;
+                                ngpios = <32>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        gpio2: gpio@18180 {
+                                compatible = "marvell,orion-gpio";
+                                reg = <0x18180 0x40>;
+                                ngpios = <3>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        system-controller@18200 {
+                                compatible = "marvell,armada-375-system-controller";
+                                reg = <0x18200 0x100>;
+                        };
+                        gateclk: clock-gating-control@18220 {
+                                compatible = "marvell,armada-375-gating-clock";
+                                reg = <0x18220 0x4>;
+                                clocks = <&coreclk 0>;
+                                #clock-cells = <1>;
+                        };
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+                        mpic: interrupt-controller@20000 {
+                                compatible = "marvell,mpic";
+                                reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+                                #interrupt-cells = <1>;
+                                #size-cells = <1>;
+                                interrupt-controller;
+                                msi-controller;
+                                interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        timer@20300 {
+                                compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
+                                reg = <0x20300 0x30>, <0x21040 0x30>;
+                                interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&mpic 5>,
+                                                      <&mpic 6>;
+                                clocks = <&coreclk 0>;
+                        };
+                        xor@60800 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60800 0x100
+                                       0x60A00 0x100>;
+                                clocks = <&gateclk 22>;
+                                status = "okay";
+                                xor00 {
+                                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                                xor01 {
+                                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                        dmacap,memset;
+                                };
+                        };
+                        xor@60900 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60900 0x100
+                                       0x60b00 0x100>;
+                                clocks = <&gateclk 23>;
+                                status = "okay";
+                                xor10 {
+                                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                                xor11 {
+                                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                        dmacap,memset;
+                                };
+                        };
+                        sata@a0000 {
+                                compatible = "marvell,orion-sata";
+                                reg = <0xa0000 0x5000>;
+                                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 14>, <&gateclk 20>;
+                                clock-names = "0", "1";
+                                status = "disabled";
+                        };
+                        nand@d0000 {
+                                compatible = "marvell,armada370-nand";
+                                reg = <0xd0000 0x54>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 11>;
+                                status = "disabled";
+                        };
+                        mvsdio@d4000 {
+                                compatible = "marvell,orion-sdio";
+                                reg = <0xd4000 0x200>;
+                                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 17>;
+                                bus-width = <4>;
+                                cap-sdio-irq;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                status = "disabled";
+                        };
+                        coreclk: mvebu-sar@e8204 {
+                                compatible = "marvell,armada-375-core-clock";
+                                reg = <0xe8204 0x04>;
+                                #clock-cells = <1>;
+                        };
+                        coredivclk: corediv-clock@e8250 {
+                                compatible = "marvell,armada-375-corediv-clock";
+                                reg = <0xe8250 0xc>;
+                                #clock-cells = <1>;
+                                clocks = <&mainpll>;
+                                clock-output-names = "nand";
+                        };
+                };
+                pcie-controller {
+                        compatible = "marvell,armada-370-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        msi-parent = <&mpic>;
+                        bus-range = <0x00 0xff>;
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+                                0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
+                                0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
+                                0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
+                                0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
new file mode 100644
index 000000000000..068031f0f263
--- /dev/null
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -0,0 +1,117 @@
+/*
+ * Device Tree Include file for Marvell Armada 380 SoC.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include "armada-38x.dtsi"
+/ {
+        model = "Marvell Armada 380 family SoC";
+        compatible = "marvell,armada380", "marvell,armada38x";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+        };
+        soc {
+                internal-regs {
+                        pinctrl {
+                                compatible = "marvell,mv88f6810-pinctrl";
+                                reg = <0x18000 0x20>;
+                        };
+                };
+                pcie-controller {
+                        compatible = "marvell,armada-370-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        msi-parent = <&mpic>;
+                        bus-range = <0x00 0xff>;
+                        ranges =
+                               <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                                0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
+                                0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+                                0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */>;
+                        /* x1 port */
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+                        /* x1 port */
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+                        /* x1 port */
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
new file mode 100644
index 000000000000..6828d77696a6
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -0,0 +1,122 @@
+/*
+ * Device Tree file for Marvell Armada 385 evaluation board
+ * (DB-88F6820)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "armada-385.dtsi"
+/ {
+        model = "Marvell Armada 385 Development Board";
+        compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>; /* 256 MB */
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+                internal-regs {
+                        spi@10600 {
+                                status = "okay";
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "w25q32";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <108000000>;
+                                };
+                        };
+                        i2c@11000 {
+                                status = "okay";
+                                clock-frequency = <100000>;
+                        };
+                        i2c@11100 {
+                                status = "okay";
+                                clock-frequency = <100000>;
+                        };
+                        serial@12000 {
+                                clock-frequency = <200000000>;
+                                status = "okay";
+                        };
+                        ethernet@30000 {
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@70000 {
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+                        mdio {
+                                phy0: ethernet-phy@0 {
+                                        reg = <0>;
+                                };
+                                phy1: ethernet-phy@1 {
+                                        reg = <1>;
+                                };
+                        };
+                        flash@d0000 {
+                                status = "okay";
+                                num-cs = <1>;
+                                marvell,nand-keep-config;
+                                marvell,nand-enable-arbiter;
+                                nand-on-flash-bbt;
+                                partition@0 {
+                                        label = "U-Boot";
+                                        reg = <0 0x800000>;
+                                };
+                                partition@800000 {
+                                        label = "Linux";
+                                        reg = <0x800000 0x800000>;
+                                };
+                                partition@1000000 {
+                                        label = "Filesystem";
+                                        reg = <0x1000000 0x3f000000>;
+                                };
+                        };
+                };
+                pcie-controller {
+                        status = "okay";
+                        /*
+                         * The two PCIe units are accessible through
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts
new file mode 100644
index 000000000000..45250c88814b
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-rd.dts
@@ -0,0 +1,94 @@
+/*
+ * Device Tree file for Marvell Armada 385 Reference Design board
+ * (RD-88F6820-AP)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "armada-385.dtsi"
+/ {
+        model = "Marvell Armada 385 Reference Design";
+        compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>; /* 256 MB */
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+                internal-regs {
+                        spi@10600 {
+                                status = "okay";
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "st,m25p128";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <108000000>;
+                                };
+                        };
+                        i2c@11000 {
+                                status = "okay";
+                                clock-frequency = <100000>;
+                        };
+                        serial@12000 {
+                                clock-frequency = <200000000>;
+                                status = "okay";
+                        };
+                        ethernet@30000 {
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@70000 {
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+                        mdio {
+                                phy0: ethernet-phy@0 {
+                                        reg = <0>;
+                                };
+                                phy1: ethernet-phy@1 {
+                                        reg = <1>;
+                                };
+                        };
+                };
+                pcie-controller {
+                        status = "okay";
+                        /*
+                         * One PCIe units is accessible through
+                         * standard PCIe slot on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
new file mode 100644
index 000000000000..e2919f02e1d4
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -0,0 +1,149 @@
+/*
+ * Device Tree Include file for Marvell Armada 385 SoC.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include "armada-38x.dtsi"
+/ {
+        model = "Marvell Armada 385 family SoC";
+        compatible = "marvell,armada385", "marvell,armada38x";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
+        soc {
+                internal-regs {
+                        pinctrl {
+                                compatible = "marvell,mv88f6820-pinctrl";
+                                reg = <0x18000 0x20>;
+                        };
+                };
+                pcie-controller {
+                        compatible = "marvell,armada-370-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        msi-parent = <&mpic>;
+                        bus-range = <0x00 0xff>;
+                        ranges =
+                               <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                                0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
+                                0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+                                0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
+                                0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
+                                0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
+                        /*
+                         * This port can be either x4 or x1. When
+                         * configured in x4 by the bootloader, then
+                         * pcie@4,0 is not available.
+                         */
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+                        /* x1 port */
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+                        /* x1 port */
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+                        /*
+                         * x1 port only available when pcie@1,0 is
+                         * configured as a x1 port
+                         */
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
new file mode 100644
index 000000000000..a064f59da02d
--- /dev/null
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -0,0 +1,376 @@
+/*
+ * Device Tree Include file for Marvell Armada 38x family of SoCs.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+/ {
+        model = "Marvell Armada 38x family SoC";
+        compatible = "marvell,armada38x";
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                eth0 = &eth0;
+                eth1 = &eth1;
+                eth2 = &eth2;
+        };
+        soc {
+                compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
+                             "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+                interrupt-parent = <&gic>;
+                pcie-mem-aperture = <0xe0000000 0x8000000>;
+                pcie-io-aperture  = <0xe8000000 0x100000>;
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
+                };
+                devbus-bootcs {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                devbus-cs0 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                devbus-cs1 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                devbus-cs2 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                devbus-cs3 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+                internal-regs {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+                        L2: cache-controller@8000 {
+                                compatible = "arm,pl310-cache";
+                                reg = <0x8000 0x1000>;
+                                cache-unified;
+                                cache-level = <2>;
+                        };
+                        timer@c600 {
+                                compatible = "arm,cortex-a9-twd-timer";
+                                reg = <0xc600 0x20>;
+                                interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+                                clocks = <&coreclk 2>;
+                        };
+                        gic: interrupt-controller@d000 {
+                                compatible = "arm,cortex-a9-gic";
+                                #interrupt-cells = <3>;
+                                #size-cells = <0>;
+                                interrupt-controller;
+                                reg = <0xd000 0x1000>,
+                                      <0xc100 0x100>;
+                        };
+                        spi0: spi@10600 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10600 0x50>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        spi1: spi@10680 {
+                                compatible = "marvell,orion-spi";
+                                reg = <0x10680 0x50>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <1>;
+                                interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        i2c0: i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11000 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@11100 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                reg = <0x11100 0x20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-ms = <1000>;
+                                clocks = <&coreclk 0>;
+                                status = "disabled";
+                        };
+                        serial@12000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12000 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                status = "disabled";
+                        };
+                        serial@12100 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x12100 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-io-width = <1>;
+                                status = "disabled";
+                        };
+                        pinctrl {
+                                compatible = "marvell,mv88f6820-pinctrl";
+                                reg = <0x18000 0x20>;
+                        };
+                        gpio0: gpio@18100 {
+                                compatible = "marvell,orion-gpio";
+                                reg = <0x18100 0x40>;
+                                ngpios = <32>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        gpio1: gpio@18140 {
+                                compatible = "marvell,orion-gpio";
+                                reg = <0x18140 0x40>;
+                                ngpios = <28>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        system-controller@18200 {
+                                compatible = "marvell,armada-380-system-controller",
+                                             "marvell,armada-370-xp-system-controller";
+                                reg = <0x18200 0x100>;
+                        };
+                        gateclk: clock-gating-control@18220 {
+                                compatible = "marvell,armada-380-gating-clock";
+                                reg = <0x18220 0x4>;
+                                clocks = <&coreclk 0>;
+                                #clock-cells = <1>;
+                        };
+                        coreclk: mvebu-sar@18600 {
+                                compatible = "marvell,armada-380-core-clock";
+                                reg = <0x18600 0x04>;
+                                #clock-cells = <1>;
+                        };
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+                        mpic: interrupt-controller@20000 {
+                                compatible = "marvell,mpic";
+                                reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+                                #interrupt-cells = <1>;
+                                #size-cells = <1>;
+                                interrupt-controller;
+                                msi-controller;
+                                interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        timer@20300 {
+                                compatible = "marvell,armada-380-timer",
+                                             "marvell,armada-xp-timer";
+                                reg = <0x20300 0x30>, <0x21040 0x30>;
+                                interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                                                      <&mpic 5>,
+                                                      <&mpic 6>;
+                                clocks = <&coreclk 2>, <&refclk>;
+                                clock-names = "nbclk", "fixed";
+                        };
+                        eth1: ethernet@30000 {
+                                compatible = "marvell,armada-370-neta";
+                                reg = <0x30000 0x4000>;
+                                interrupts-extended = <&mpic 10>;
+                                clocks = <&gateclk 3>;
+                                status = "disabled";
+                        };
+                        eth2: ethernet@34000 {
+                                compatible = "marvell,armada-370-neta";
+                                reg = <0x34000 0x4000>;
+                                interrupts-extended = <&mpic 12>;
+                                clocks = <&gateclk 2>;
+                                status = "disabled";
+                        };
+                        xor@60800 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60800 0x100
+                                       0x60a00 0x100>;
+                                clocks = <&gateclk 22>;
+                                status = "okay";
+                                xor00 {
+                                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                                xor01 {
+                                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                        dmacap,memset;
+                                };
+                        };
+                        xor@60900 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60900 0x100
+                                       0x60b00 0x100>;
+                                clocks = <&gateclk 28>;
+                                status = "okay";
+                                xor10 {
+                                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                };
+                                xor11 {
+                                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmacap,memcpy;
+                                        dmacap,xor;
+                                        dmacap,memset;
+                                };
+                        };
+                        eth0: ethernet@70000 {
+                                compatible = "marvell,armada-370-neta";
+                                reg = <0x70000 0x4000>;
+                                interrupts-extended = <&mpic 8>;
+                                clocks = <&gateclk 4>;
+                                status = "disabled";
+                        };
+                        mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "marvell,orion-mdio";
+                                reg = <0x72004 0x4>;
+                        };
+                        coredivclk: clock@e4250 {
+                                compatible = "marvell,armada-380-corediv-clock";
+                                reg = <0xe4250 0xc>;
+                                #clock-cells = <1>;
+                                clocks = <&mainpll>;
+                                clock-output-names = "nand";
+                        };
+                        flash@d0000 {
+                                compatible = "marvell,armada370-nand";
+                                reg = <0xd0000 0x54>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&coredivclk 0>;
+                                status = "disabled";
+                        };
+                };
+        };
+        clocks {
+                /* 2 GHz fixed main PLL */
+                mainpll: mainpll {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <2000000000>;
+                };
+                /* 25 MHz reference crystal */
+                refclk: oscillator {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index c5fe57269f5a..d83d7d69ac01 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -16,6 +16,8 @@
 */
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include "armada-xp-mv78230.dtsi"
 / {
@@ -157,8 +159,8 @@
                button@1 {
                        label = "Factory Reset Button";
-                        linux,code = <141>; /* KEY_SETUP */
+                        linux,code = <KEY_SETUP>;
-                        gpios = <&gpio1 1 1>;
+                        gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index bcf6d79a57ec..448373c4b0e5 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -2,7 +2,7 @@
 * Device Tree file for Marvell Armada XP evaluation board
 * (DB-78460-BP)
 *
- * Copyright (C) 2012 Marvell
+ * Copyright (C) 2012-2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
@@ -11,6 +11,15 @@
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
+  *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
 */
 /dts-v1/;
@@ -30,7 +39,7 @@
        };
        soc {
-                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 274e2ad5f51c..61bda687f782 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -2,7 +2,7 @@
 * Device Tree file for Marvell Armada XP development board
 * (DB-MV784MP-GP)
 *
- * Copyright (C) 2013 Marvell
+ * Copyright (C) 2013-2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
@@ -11,6 +11,15 @@
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
 */
 /dts-v1/;
@@ -30,16 +39,17 @@
                 * 8 GB of plug-in RAM modules by default.The amount
                 * of memory available can be changed by the
                 * bootloader according the size of the module
-                 * actually plugged. Only 7GB are usable because
+                 * actually plugged. However, memory between
-                 * addresses from 0xC0000000 to 0xffffffff are used by
+                 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
-                 * the internal registers of the SoC.
+                 * the address range used for I/O (internal registers,
+                 * MBus windows).
                 */
-                reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
+                reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
                      <0x00000001 0x00000000 0x00000001 0x00000000>;
        };
        soc {
-                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index e47c49ecd55c..c2242745b9b8 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -23,7 +23,12 @@
        memory {
                device_type = "memory";
-                reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
+                /*
+                 * This board has 4 GB of RAM, but the last 256 MB of
+                 * RAM are not usable due to the overlap with the MBus
+                 * Window address range
+                 */
+                reg = <0 0x00000000 0 0xf0000000>;
        };
        soc {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 99bcf76e6953..985948ce67b3 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -11,6 +11,8 @@
 */
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include "armada-xp-mv78260.dtsi"
 / {
@@ -90,19 +92,19 @@
                                red_led {
                                        label = "red_led";
-                                        gpios = <&gpio1 17 1>;
+                                        gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
                                        default-state = "off";
                                };
                                yellow_led {
                                        label = "yellow_led";
-                                        gpios = <&gpio1 19 1>;
+                                        gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
                                        default-state = "off";
                                };
                                green_led {
                                        label = "green_led";
-                                        gpios = <&gpio1 21 1>;
+                                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
                                        default-state = "keep";
                                };
                        };
@@ -114,8 +116,8 @@
                                button@1 {
                                        label = "Init Button";
-                                        linux,code = <116>;
+                                        linux,code = <KEY_POWER>;
-                                        gpios = <&gpio1 28 0>;
+                                        gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
                                };
                        };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index b8b84a22f0f3..abb9f9dcc525 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -111,6 +111,12 @@
                                clock-names = "nbclk", "fixed";
                        };
+                        watchdog@20300 {
+                                compatible = "marvell,armada-xp-wdt";
+                                clocks = <&coreclk 2>, <&refclk>;
+                                clock-names = "nbclk", "fixed";
+                        };
                        armada-370-xp-pmsu@22000 {
                                compatible = "marvell,armada-370-xp-pmsu";
                                reg = <0x22100 0x400>, <0x20800 0x20>;
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index cce45f5177f9..55ab6180e350 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -129,7 +129,6 @@
                        adc0: adc@f804c000 {
                                status = "okay";
                                atmel,adc-channels-used = <0xf>;
-                                atmel,adc-num-channels = <4>;
                        };
                        dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi
index 2093c4d7cd6a..df4b78695695 100644
--- a/arch/arm/boot/dts/at91-cosino.dtsi
+++ b/arch/arm/boot/dts/at91-cosino.dtsi
@@ -64,7 +64,6 @@
                        };
                        adc0: adc@f804c000 {
-                                atmel,adc-clock-rate = <1000000>;
                                atmel,adc-ts-wires = <4>;
                                atmel,adc-ts-pressure-threshold = <10000>;
                                status = "okay";
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts
index f9415dd11f17..a542d5837a17 100644
--- a/arch/arm/boot/dts/at91-cosino_mega2560.dts
+++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts
@@ -27,7 +27,6 @@
                        };
                        adc0: adc@f804c000 {
-                                atmel,adc-clock-rate = <1000000>;
                                atmel,adc-ts-wires = <4>;
                                atmel,adc-ts-pressure-threshold = <10000>;
                                status = "okay";
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 997901f7ed73..366fc2cbcd64 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -608,37 +608,38 @@
                        };
                        adc0: adc@fffe0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xfffe0000 0x100>;
                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
                                atmel,adc-use-external-triggers;
                                atmel,adc-channels-used = <0xf>;
                                atmel,adc-vref = <3300>;
-                                atmel,adc-num-channels = <4>;
                                atmel,adc-startup-time = <15>;
-                                atmel,adc-channel-base = <0x30>;
-                                atmel,adc-drdy-mask = <0x10000>;
-                                atmel,adc-status-register = <0x1c>;
-                                atmel,adc-trigger-register = <0x04>;
                                atmel,adc-res = <8 10>;
                                atmel,adc-res-names = "lowres", "highres";
                                atmel,adc-use-res = "highres";
                                trigger@0 {
+                                        reg = <0>;
                                        trigger-name = "timer-counter-0";
                                        trigger-value = <0x1>;
                                };
                                trigger@1 {
+                                        reg = <1>;
                                        trigger-name = "timer-counter-1";
                                        trigger-value = <0x3>;
                                };
                                trigger@2 {
+                                        reg = <2>;
                                        trigger-name = "timer-counter-2";
                                        trigger-value = <0x5>;
                                };
                                trigger@3 {
+                                        reg = <3>;
                                        trigger-name = "external";
                                        trigger-value = <0x13>;
                                        trigger-external;
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
new file mode 100644
index 000000000000..e21dda0e8986
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -0,0 +1,735 @@
+/*
+ * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
+ *
+ *  Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/at91.h>
+/ {
+        model = "Atmel AT91SAM9261 family SoC";
+        compatible = "atmel,at91sam9261";
+        interrupt-parent = <&aic>;
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                tcb0 = &tcb0;
+                i2c0 = &i2c0;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
+        };
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
+                };
+        };
+        memory {
+                reg = <0x20000000 0x08000000>;
+        };
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                usb0: ohci@00500000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00500000 0x100000>;
+                        interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&usb>, <&ohci_clk>, <&hclk0>, <&uhpck>;
+                        clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
+                        status = "disabled";
+                };
+                fb0: fb@0x00600000 {
+                        compatible = "atmel,at91sam9261-lcdc";
+                        reg = <0x00600000 0x1000>;
+                        interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_fb>;
+                        clocks = <&lcd_clk>, <&hclk1>;
+                        clock-names = "lcdc_clk", "hclk";
+                        status = "disabled";
+                };
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000>;
+                        atmel,nand-addr-offset = <22>;
+                        atmel,nand-cmd-offset = <21>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand>;
+                        gpios = <&pioC 15 GPIO_ACTIVE_HIGH>,
+                                <&pioC 14 GPIO_ACTIVE_HIGH>,
+                                <0>;
+                        status = "disabled";
+                };
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        tcb0: timer@fffa0000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffa0000 0x100>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
+                                             <18 IRQ_TYPE_LEVEL_HIGH 0>,
+                                             <19 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
+                                clock-names = "t0_clk", "t1_clk", "t2_clk";
+                        };
+                        usb1: gadget@fffa4000 {
+                                compatible = "atmel,at91rm9200-udc";
+                                reg = <0xfffa4000 0x4000>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+                                clocks = <&usb>, <&udc_clk>, <&udpck>;
+                                clock-names = "usb_clk", "udc_clk", "udpck";
+                                status = "disabled";
+                        };
+                        mmc0: mmc@fffa8000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xfffa8000 0x600>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&mci0_clk>;
+                                clock-names = "mci_clk";
+                                status = "disabled";
+                        };
+                        i2c0: i2c@fffac000 {
+                                compatible = "atmel,at91sam9261-i2c";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c_twi>;
+                                reg = <0xfffac000 0x100>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&twi0_clk>;
+                                status = "disabled";
+                        };
+                        usart0: serial@fffb0000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb0000 0x200>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
+                                clocks = <&usart0_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+                        usart1: serial@fffb4000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb4000 0x200>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
+                                clocks = <&usart1_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+                        usart2: serial@fffb8000{
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb8000 0x200>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
+                                clocks = <&usart2_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+                        ssc0: ssc@fffbc000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfffbc000 0x4000>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                status = "disabled";
+                        };
+                        ssc1: ssc@fffc0000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfffc0000 0x4000>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                status = "disabled";
+                        };
+                        spi0: spi@fffc8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffc8000 0x200>;
+                                cs-gpios = <0>, <0>, <0>, <0>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                clocks = <&spi0_clk>;
+                                clock-names = "spi_clk";
+                                status = "disabled";
+                        };
+                        spi1: spi@fffcc000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffcc000 0x200>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi1>;
+                                clocks = <&spi1_clk>;
+                                clock-names = "spi_clk";
+                                status = "disabled";
+                        };
+                        ramc: ramc@ffffea00 {
+                                compatible = "atmel,at91sam9260-sdramc";
+                                reg = <0xffffea00 0x200>;
+                        };
+                        matrix: matrix@ffffee00 {
+                                compatible = "atmel,at91sam9260-bus-matrix";
+                                reg = <0xffffee00 0x200>;
+                        };
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <3>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <29 30 31>;
+                        };
+                        dbgu: serial@fffff200 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffff200 0x200>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
+                                clocks = <&mck>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+                        pinctrl@fffff400 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+                                ranges = <0xfffff400 0xfffff400 0x600>;
+                                atmel,mux-mask =
+                                      /*    A         B     */
+                                      <0xffffffff 0xfffffff7>,  /* pioA */
+                                      <0xffffffff 0xfffffff4>,  /* pioB */
+                                      <0xffffffff 0xffffff07>;  /* pioC */
+                                /* shared pinctrl settings */
+                                dbgu {
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 9  AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+                                        };
+                                };
+                                usart0 {
+                                        pinctrl_usart0: usart0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart0_rts: usart0_rts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart0_cts: usart0_cts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                usart1 {
+                                        pinctrl_usart1: usart1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart1_rts: usart1_rts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart1_cts: usart1_cts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart2_rts: usart2_rts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart2_cts: usart2_cts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                nand {
+                                        pinctrl_nand: nand-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+                                        };
+                                };
+                                mmc0 {
+                                        pinctrl_mmc0_clk: mmc0_clk-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+                                        };
+                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+                                        };
+                                        };
+                                ssc0 {
+                                        pinctrl_ssc0_tx: ssc0_tx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_ssc0_rx: ssc0_rx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                ssc1 {
+                                        pinctrl_ssc1_tx: ssc1_tx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_ssc1_rx: ssc1_rx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        };
+                                spi1 {
+                                        pinctrl_spi1: spi1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                i2c0 {
+                                        pinctrl_i2c_bitbang: i2c-0-bitbang {
+                                                atmel,pins =
+                                                        <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_i2c_twi: i2c-0-twi {
+                                                atmel,pins =
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                fb {
+                                        pinctrl_fb: fb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                pioA: gpio@fffff400 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x200>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioA_clk>;
+                                };
+                                pioB: gpio@fffff600 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x200>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioB_clk>;
+                                };
+                                pioC: gpio@fffff800 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x200>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioC_clk>;
+                                };
+                        };
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                interrupt-controller;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                #interrupt-cells = <1>;
+                                clk32k: slck {
+                                        compatible = "fixed-clock";
+                                        #clock-cells = <0>;
+                                        clock-frequency = <32768>;
+                                };
+                                main: mainck {
+                                        compatible = "atmel,at91rm9200-clk-main";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+                                        clocks = <&clk32k>;
+                                };
+                                plla: pllack {
+                                        compatible = "atmel,at91rm9200-clk-pll";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+                                        clocks = <&main>;
+                                        reg = <0>;
+                                        atmel,clk-input-range = <1000000 32000000>;
+                                        #atmel,pll-clk-output-range-cells = <4>;
+                                        atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
+                                };
+                                pllb: pllbck {
+                                        compatible = "atmel,at91rm9200-clk-pll";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_LOCKB>;
+                                        clocks = <&main>;
+                                        reg = <1>;
+                                        atmel,clk-input-range = <1000000 32000000>;
+                                        #atmel,pll-clk-output-range-cells = <4>;
+                                        atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
+                                };
+                                mck: masterck {
+                                        compatible = "atmel,at91rm9200-clk-master";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+                                        clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+                                        atmel,clk-output-range = <0 94000000>;
+                                        atmel,clk-divisors = <1 2 4 3>;
+                                };
+                                usb: usbck {
+                                        compatible = "atmel,at91rm9200-clk-usb";
+                                        #clock-cells = <0>;
+                                        atmel,clk-divisors = <1 2 4 3>;
+                                        clocks = <&pllb>;
+                                };
+                                systemck {
+                                        compatible = "atmel,at91rm9200-clk-system";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        uhpck: uhpck {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                                clocks = <&usb>;
+                                        };
+                                        udpck: udpck {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                                clocks = <&usb>;
+                                        };
+                                        hclk0: hclk0 {
+                                                #clock-cells = <0>;
+                                                reg = <16>;
+                                                clocks = <&mck>;
+                                        };
+                                        hclk1: hclk1 {
+                                                #clock-cells = <0>;
+                                                reg = <17>;
+                                                clocks = <&mck>;
+                                        };
+                                };
+                                periphck {
+                                        compatible = "atmel,at91rm9200-clk-peripheral";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        clocks = <&mck>;
+                                        pioA_clk: pioA_clk {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                        };
+                                        pioB_clk: pioB_clk {
+                                                #clock-cells = <0>;
+                                                reg = <3>;
+                                        };
+                                        pioC_clk: pioC_clk {
+                                                #clock-cells = <0>;
+                                                reg = <4>;
+                                        };
+                                        usart0_clk: usart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                        };
+                                        usart1_clk: usart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                        };
+                                        usart2_clk: usart2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                        };
+                                        mci0_clk: mci0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                        };
+                                        udc_clk: udc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <10>;
+                                        };
+                                        twi0_clk: twi0_clk {
+                                                reg = <11>;
+                                                #clock-cells = <0>;
+                                        };
+                                        spi0_clk: spi0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <12>;
+                                        };
+                                        spi1_clk: spi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <13>;
+                                        };
+                                        tc0_clk: tc0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <17>;
+                                        };
+                                        tc1_clk: tc1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <18>;
+                                        };
+                                        tc2_clk: tc2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <19>;
+                                        };
+                                        ohci_clk: ohci_clk {
+                                                #clock-cells = <0>;
+                                                reg = <20>;
+                                        };
+                                        lcd_clk: lcd_clk {
+                                                #clock-cells = <0>;
+                                                reg = <21>;
+                                        };
+                                };
+                        };
+                        rstc@fffffd00 {
+                                compatible = "atmel,at91sam9260-rstc";
+                                reg = <0xfffffd00 0x10>;
+                        };
+                        shdwc@fffffd10 {
+                                compatible = "atmel,at91sam9260-shdwc";
+                                reg = <0xfffffd10 0x10>;
+                        };
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                clocks = <&mck>;
+                        };
+                        watchdog@fffffd40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffd40 0x10>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                status = "disabled";
+                        };
+                };
+        };
+        i2c@0 {
+                compatible = "i2c-gpio";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_bitbang>;
+                gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */
+                        <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
new file mode 100644
index 000000000000..2ce527e70c7a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -0,0 +1,211 @@
+/*
+ * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board
+ *
+ *  Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+/dts-v1/;
+#include "at91sam9261.dtsi"
+/ {
+        model = "Atmel at91sam9261ek";
+        compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9";
+        chosen {
+                bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+        ahb {
+                usb0: ohci@00500000 {
+                        status = "okay";
+                };
+                fb0: fb@0x00600000 {
+                        display = <&display0>;
+                        atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
+                        status = "okay";
+                        display0: display {
+                                bits-per-pixel = <16>;
+                                atmel,lcdcon-backlight;
+                                atmel,dmacon = <0x1>;
+                                atmel,lcdcon2 = <0x80008002>;
+                                atmel,guard-time = <1>;
+                                atmel,lcd-wiring-mode = "BRG";
+                                display-timings {
+                                        native-mode = <&timing0>;
+                                        timing0: timing0 {
+                                                clock-frequency = <4965000>;
+                                                hactive = <240>;
+                                                vactive = <320>;
+                                                hback-porch = <1>;
+                                                hfront-porch = <33>;
+                                                vback-porch = <1>;
+                                                vfront-porch = <0>;
+                                                hsync-len = <5>;
+                                                vsync-len = <1>;
+                                                hsync-active = <1>;
+                                                vsync-active = <1>;
+                                        };
+                                };
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+                        bootloader@40000 {
+                                label = "bootloader";
+                                reg = <0x40000 0x80000>;
+                        };
+                        bootloaderenv@c0000 {
+                                label = "bootloader env";
+                                reg = <0xc0000 0xc0000>;
+                        };
+                        dtb@180000 {
+                                label = "device tree";
+                                reg = <0x180000 0x80000>;
+                        };
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+                apb {
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+                        spi0: spi@fffc8000 {
+                                cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>;
+                                status = "okay";
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        reg = <0>;
+                                        spi-max-frequency = <15000000>;
+                                };
+                                tsc2046@0 {
+                                        reg = <2>;
+                                        compatible = "ti,ads7843";
+                                        interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>;
+                                        spi-max-frequency = <3000000>;
+                                        pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>;
+                                        ti,x-min = /bits/ 16 <150>;
+                                        ti,x-max = /bits/ 16 <3830>;
+                                        ti,y-min = /bits/ 16 <190>;
+                                        ti,y-max = /bits/ 16 <3830>;
+                                        ti,vref-delay-usecs = /bits/ 16 <450>;
+                                        ti,x-plate-ohms = /bits/ 16 <450>;
+                                        ti,y-plate-ohms = /bits/ 16 <250>;
+                                        ti,pressure-max = /bits/ 16 <15000>;
+                                        ti,debounce-rep = /bits/ 16 <0>;
+                                        ti,debounce-tol = /bits/ 16 <65535>;
+                                        ti,debounce-max = /bits/ 16 <1>;
+                                        linux,wakeup;
+                                };
+                        };
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                ds8 {
+                        label = "ds8";
+                        gpios = <&pioA 13 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "none";
+                };
+                ds7 {
+                        label = "ds7";
+                        gpios = <&pioA 14 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "nand-disk";
+                };
+                ds1 {
+                        label = "ds1";
+                        gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                button_0 {
+                        label = "button_0";
+                        gpios = <&pioA 27 GPIO_ACTIVE_LOW>;
+                        linux,code = <256>;
+                        gpio-key,wakeup;
+                };
+                button_1 {
+                        label = "button_1";
+                        gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
+                        linux,code = <257>;
+                        gpio-key,wakeup;
+                };
+                button_2 {
+                        label = "button_2";
+                        gpios = <&pioA 25 GPIO_ACTIVE_LOW>;
+                        linux,code = <258>;
+                        gpio-key,wakeup;
+                };
+                button_3 {
+                        label = "button_3";
+                        gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
+                        linux,code = <259>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index cbcc058b26b4..9cdaecff13b3 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -632,40 +632,41 @@
                        };
                        adc0: adc@fffb0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xfffb0000 0x100>;
                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
                                atmel,adc-use-external-triggers;
                                atmel,adc-channels-used = <0xff>;
                                atmel,adc-vref = <3300>;
-                                atmel,adc-num-channels = <8>;
                                atmel,adc-startup-time = <40>;
-                                atmel,adc-channel-base = <0x30>;
-                                atmel,adc-drdy-mask = <0x10000>;
-                                atmel,adc-status-register = <0x1c>;
-                                atmel,adc-trigger-register = <0x08>;
                                atmel,adc-res = <8 10>;
                                atmel,adc-res-names = "lowres", "highres";
                                atmel,adc-use-res = "highres";
                                trigger@0 {
+                                        reg = <0>;
                                        trigger-name = "external-rising";
                                        trigger-value = <0x1>;
                                        trigger-external;
                                };
                                trigger@1 {
+                                        reg = <1>;
                                        trigger-name = "external-falling";
                                        trigger-value = <0x2>;
                                        trigger-external;
                                };
                                trigger@2 {
+                                        reg = <2>;
                                        trigger-name = "external-any";
                                        trigger-value = <0x3>;
                                        trigger-external;
                                };
                                trigger@3 {
+                                        reg = <3>;
                                        trigger-name = "continuous";
                                        trigger-value = <0x6>;
                                };
@@ -817,6 +818,7 @@
                              >;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                        atmel,nand-has-dma;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioC 8 GPIO_ACTIVE_HIGH
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 394e6ce2afb7..9f04808fc697 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -570,6 +570,7 @@
                        atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                        atmel,nand-has-dma;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioD 5 GPIO_ACTIVE_HIGH
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
new file mode 100644
index 000000000000..63e1784d272c
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -0,0 +1,802 @@
+/*
+ * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
+ *
+ *  Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/clk/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+/ {
+        model = "Atmel AT91SAM9RL family SoC";
+        compatible = "atmel,at91sam9rl", "atmel,at91sam9";
+        interrupt-parent = <&aic>;
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                tcb0 = &tcb0;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
+        };
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
+                };
+        };
+        memory {
+                reg = <0x20000000 0x04000000>;
+        };
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000>,
+                              <0xffffe800 0x200>;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand>;
+                        gpios = <&pioD 17 GPIO_ACTIVE_HIGH>,
+                                <&pioB 6 GPIO_ACTIVE_HIGH>,
+                                <0>;
+                        status = "disabled";
+                };
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        tcb0: timer@fffa0000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffa0000 0x100>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
+                                             <17 IRQ_TYPE_LEVEL_HIGH 0>,
+                                             <18 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
+                                clock-names = "t0_clk", "t1_clk", "t2_clk";
+                        };
+                        mmc0: mmc@fffa4000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xfffa4000 0x600>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                pinctrl-names = "default";
+                                clocks = <&mci0_clk>;
+                                clock-names = "mci_clk";
+                                status = "disabled";
+                        };
+                        i2c0: i2c@fffa8000 {
+                                compatible = "atmel,at91sam9260-i2c";
+                                reg = <0xfffa8000 0x100>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&twi0_clk>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@fffac000 {
+                                compatible = "atmel,at91sam9260-i2c";
+                                reg = <0xfffac000 0x100>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+                        usart0: serial@fffb0000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb0000 0x200>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
+                                clocks = <&usart0_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+                        usart1: serial@fffb4000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb4000 0x200>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
+                                clocks = <&usart1_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+                        usart2: serial@fffb8000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb8000 0x200>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
+                                clocks = <&usart2_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+                        usart3: serial@fffbc000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffbc000 0x200>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3>;
+                                clocks = <&usart3_clk>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+                        ssc0: ssc@fffc0000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfffc0000 0x4000>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                status = "disabled";
+                        };
+                        ssc1: ssc@fffc4000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfffc4000 0x4000>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                status = "disabled";
+                        };
+                        spi0: spi@fffcc000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffcc000 0x200>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                clocks = <&spi0_clk>;
+                                clock-names = "spi_clk";
+                                status = "disabled";
+                        };
+                        ramc0: ramc@ffffea00 {
+                                compatible = "atmel,at91sam9260-sdramc";
+                                reg = <0xffffea00 0x200>;
+                        };
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <3>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <31>;
+                        };
+                        dbgu: serial@fffff200 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffff200 0x200>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
+                                clocks = <&mck>;
+                                clock-names = "usart";
+                                status = "disabled";
+                        };
+                        pinctrl@fffff400 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+                                ranges = <0xfffff400 0xfffff400 0x800>;
+                                atmel,mux-mask =
+                                        /*    A         B     */
+                                        <0xffffffff 0xe05c6738>,  /* pioA */
+                                        <0xffffffff 0x0000c780>,  /* pioB */
+                                        <0xffffffff 0xe3ffff0e>,  /* pioC */
+                                        <0x003fffff 0x0001ff3c>;  /* pioD */
+                                /* shared pinctrl settings */
+                                dbgu {
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+                                        };
+                                };
+                                i2c_gpio0 {
+                                        pinctrl_i2c_gpio0: i2c_gpio0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
+                                                        <AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+                                        };
+                                };
+                                i2c_gpio1 {
+                                        pinctrl_i2c_gpio1: i2c_gpio1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
+                                                        <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+                                        };
+                                };
+                                mmc0 {
+                                        pinctrl_mmc0_clk: mmc0_clk-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+                                        };
+                                        pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+                                        };
+                                };
+                                nand {
+                                        pinctrl_nand: nand-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+                                        };
+                                        pinctrl_nand0_ale_cle: nand_ale_cle-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_nand0_oe_we: nand_oe_we-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_nand0_cs: nand_cs-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                ssc0 {
+                                        pinctrl_ssc0_tx: ssc0_tx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_ssc0_rx: ssc0_rx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                ssc1 {
+                                        pinctrl_ssc1_tx: ssc1_tx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_ssc1_rx: ssc1_rx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOD 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                usart0 {
+                                        pinctrl_usart0: usart0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+                                        };
+                                        pinctrl_usart0_rts: usart0_rts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart0_cts: usart0_cts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart0_dcd: usart0_dcd-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart0_ri: usart0_ri-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart0_sck: usart0_sck-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                usart1 {
+                                        pinctrl_usart1: usart1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart1_rts: usart1_rts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart1_cts: usart1_cts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart1_sck: usart1_sck-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart2_rts: usart2_rts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart2_cts: usart2_cts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart2_sck: usart2_sck-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                usart3 {
+                                        pinctrl_usart3: usart3-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart3_rts: usart3_rts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart3_cts: usart3_cts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_usart3_sck: usart3_sck-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                pioA: gpio@fffff400 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x200>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioA_clk>;
+                                };
+                                pioB: gpio@fffff600 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x200>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioB_clk>;
+                                };
+                                pioC: gpio@fffff800 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x200>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioC_clk>;
+                                };
+                                pioD: gpio@fffffa00 {
+                                        compatible = "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x200>;
+                                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        clocks = <&pioD_clk>;
+                                };
+                        };
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91sam9g45-pmc";
+                                reg = <0xfffffc00 0x100>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                interrupt-controller;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                #interrupt-cells = <1>;
+                                clk32k: slck {
+                                        compatible = "fixed-clock";
+                                        #clock-cells = <0>;
+                                        clock-frequency = <32768>;
+                                };
+                                main: mainck {
+                                        compatible = "atmel,at91rm9200-clk-main";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+                                        clocks = <&clk32k>;
+                                };
+                                plla: pllack {
+                                        compatible = "atmel,at91rm9200-clk-pll";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+                                        clocks = <&main>;
+                                        reg = <0>;
+                                        atmel,clk-input-range = <1000000 32000000>;
+                                        #atmel,pll-clk-output-range-cells = <4>;
+                                        atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
+                                };
+                                utmi: utmick {
+                                        compatible = "atmel,at91sam9x5-clk-utmi";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_LOCKU>;
+                                        clocks = <&main>;
+                                };
+                                mck: masterck {
+                                        compatible = "atmel,at91rm9200-clk-master";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+                                        clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
+                                        atmel,clk-output-range = <0 94000000>;
+                                        atmel,clk-divisors = <1 2 4 3>;
+                                };
+                                prog: progck {
+                                        compatible = "atmel,at91rm9200-clk-programmable";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
+                                        prog0: prog0 {
+                                                #clock-cells = <0>;
+                                                reg = <0>;
+                                                interrupts = <AT91_PMC_PCKRDY(0)>;
+                                        };
+                                        prog1: prog1 {
+                                                #clock-cells = <0>;
+                                                reg = <1>;
+                                                interrupts = <AT91_PMC_PCKRDY(1)>;
+                                        };
+                                };
+                                systemck {
+                                        compatible = "atmel,at91rm9200-clk-system";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pck0: pck0 {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                                clocks = <&prog0>;
+                                        };
+                                        pck1: pck1 {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                                clocks = <&prog1>;
+                                        };
+                                };
+                                periphck {
+                                        compatible = "atmel,at91rm9200-clk-peripheral";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        clocks = <&mck>;
+                                        pioA_clk: pioA_clk {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                        };
+                                        pioB_clk: pioB_clk {
+                                                #clock-cells = <0>;
+                                                reg = <3>;
+                                        };
+                                        pioC_clk: pioC_clk {
+                                                #clock-cells = <0>;
+                                                reg = <4>;
+                                        };
+                                        pioD_clk: pioD_clk {
+                                                #clock-cells = <0>;
+                                                reg = <5>;
+                                        };
+                                        usart0_clk: usart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                        };
+                                        usart1_clk: usart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                        };
+                                        usart2_clk: usart2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                        };
+                                        usart3_clk: usart3_clk {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                        };
+                                        mci0_clk: mci0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <10>;
+                                        };
+                                        twi0_clk: twi0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <11>;
+                                        };
+                                        twi1_clk: twi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <12>;
+                                        };
+                                        spi0_clk: spi0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <13>;
+                                        };
+                                        ssc0_clk: ssc0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <14>;
+                                        };
+                                        ssc1_clk: ssc1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <15>;
+                                        };
+                                        tc0_clk: tc0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <16>;
+                                        };
+                                        tc1_clk: tc1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <17>;
+                                        };
+                                        tc2_clk: tc2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <18>;
+                                        };
+                                        pwm_clk: pwm_clk {
+                                                #clock-cells = <0>;
+                                                reg = <19>;
+                                        };
+                                        adc_clk: adc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <20>;
+                                        };
+                                        dma0_clk: dma0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <21>;
+                                        };
+                                        udphs_clk: udphs_clk {
+                                                #clock-cells = <0>;
+                                                reg = <22>;
+                                        };
+                                        lcd_clk: lcd_clk {
+                                                #clock-cells = <0>;
+                                                reg = <23>;
+                                        };
+                                };
+                        };
+                        rstc@fffffd00 {
+                                compatible = "atmel,at91sam9260-rstc";
+                                reg = <0xfffffd00 0x10>;
+                        };
+                        shdwc@fffffd10 {
+                                compatible = "atmel,at91sam9260-shdwc";
+                                reg = <0xfffffd10 0x10>;
+                        };
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                clocks = <&mck>;
+                        };
+                        watchdog@fffffd40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffd40 0x10>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                status = "disabled";
+                        };
+                };
+        };
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */
+                        <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio0>;
+                status = "disabled";
+        };
+        i2c@1 {
+                compatible = "i2c-gpio";
+                gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */
+                        <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio1>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
new file mode 100644
index 000000000000..cddb37825fad
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -0,0 +1,157 @@
+/*
+ * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board
+ *
+ *  Copyright (C) 2014  Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+#include "at91sam9rl.dtsi"
+/ {
+        model = "Atmel at91sam9rlek";
+        compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9";
+        chosen {
+                bootargs = "console=ttyS0,115200 rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+        ahb {
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt = <1>;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+                        bootloader@40000 {
+                                label = "bootloader";
+                                reg = <0x40000 0x80000>;
+                        };
+                        bootloaderenv@c0000 {
+                                label = "bootloader env";
+                                reg = <0xc0000 0xc0000>;
+                        };
+                        dtb@180000 {
+                                label = "device tree";
+                                reg = <0x180000 0x80000>;
+                        };
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+                apb {
+                        mmc0: mmc@fffa4000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0
+                                        &pinctrl_mmc0_clk
+                                        &pinctrl_mmc0_slot0_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
+                                };
+                        };
+                        usart0: serial@fffb0000 {
+                                pinctrl-0 = <
+                                        &pinctrl_usart0
+                                        &pinctrl_usart0_rts
+                                        &pinctrl_usart0_cts>;
+                                status = "okay";
+                        };
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                        pinctrl@fffff400 {
+                                mmc0 {
+                                        pinctrl_board_mmc0: mmc0-board {
+                                                atmel,pins =
+                                                        <AT91_PIOA 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+                                };
+                        };
+                        pmc: pmc@fffffc00 {
+                                main: mainck {
+                                        clock-frequency = <12000000>;
+                                };
+                        };
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                ds1 {
+                        label = "ds1";
+                        gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
+                };
+                ds2 {
+                        label = "ds2";
+                        gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
+                };
+                ds3 {
+                        label = "ds3";
+                        gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                right_click {
+                        label = "right_click";
+                        gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
+                        linux,code = <273>;
+                        gpio-key,wakeup;
+                };
+                left_click {
+                        label = "left_click";
+                        gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
+                        linux,code = <272>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 174219de92fa..fc13c9240da8 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -621,41 +621,42 @@
                        };
                        adc0: adc@f804c000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xf804c000 0x100>;
                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
-                                atmel,adc-use-external;
+                                atmel,adc-use-external-triggers;
                                atmel,adc-channels-used = <0xffff>;
                                atmel,adc-vref = <3300>;
-                                atmel,adc-num-channels = <12>;
                                atmel,adc-startup-time = <40>;
-                                atmel,adc-channel-base = <0x50>;
-                                atmel,adc-drdy-mask = <0x1000000>;
-                                atmel,adc-status-register = <0x30>;
-                                atmel,adc-trigger-register = <0xc0>;
                                atmel,adc-res = <8 10>;
                                atmel,adc-res-names = "lowres", "highres";
                                atmel,adc-use-res = "highres";
                                trigger@0 {
+                                        reg = <0>;
                                        trigger-name = "external-rising";
                                        trigger-value = <0x1>;
                                        trigger-external;
                                };
                                trigger@1 {
+                                        reg = <1>;
                                        trigger-name = "external-falling";
                                        trigger-value = <0x2>;
                                        trigger-external;
                                };
                                trigger@2 {
+                                        reg = <2>;
                                        trigger-name = "external-any";
                                        trigger-value = <0x3>;
                                        trigger-external;
                                };
                                trigger@3 {
+                                        reg = <3>;
                                        trigger-name = "continuous";
                                        trigger-value = <0x6>;
                                };
@@ -790,6 +791,7 @@
                        atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                        atmel,nand-has-dma;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
                        gpios = <&pioD 5 GPIO_ACTIVE_HIGH
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index f8674bcc4489..9d72674049d6 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -65,9 +65,10 @@
                                #clock-cells = <1>;
                        };
-                        reset-controller@88010000 {
+                        rstc: reset-controller@88010000 {
                                compatible = "sirf,prima2-rstc";
                                reg = <0x88010000 0x1000>;
+                                #reset-cells = <1>;
                        };
                        rsc-controller@88020000 {
@@ -217,8 +218,8 @@
                                interrupts = <17>;
                                fifosize = <128>;
                                clocks = <&clks 13>;
-                                sirf,uart-dma-rx-channel = <21>;
+                                dmas = <&dmac1 5>, <&dmac0 2>;
-                                sirf,uart-dma-tx-channel = <2>;
+                                dma-names = "rx", "tx";
                        };
                        uart1: uart@b0060000 {
@@ -228,6 +229,7 @@
                                interrupts = <18>;
                                fifosize = <32>;
                                clocks = <&clks 14>;
+                                dma-names = "no-rx", "no-tx";
                        };
                        uart2: uart@b0070000 {
@@ -237,8 +239,8 @@
                                interrupts = <19>;
                                fifosize = <128>;
                                clocks = <&clks 15>;
-                                sirf,uart-dma-rx-channel = <6>;
+                                dmas = <&dmac0 6>, <&dmac0 7>;
-                                sirf,uart-dma-tx-channel = <7>;
+                                dma-names = "rx", "tx";
                        };
                        usp0: usp@b0080000 {
@@ -248,8 +250,8 @@
                                interrupts = <20>;
                                fifosize = <128>;
                                clocks = <&clks 28>;
-                                sirf,usp-dma-rx-channel = <17>;
+                                dmas = <&dmac1 1>, <&dmac1 2>;
-                                sirf,usp-dma-tx-channel = <18>;
+                                dma-names = "rx", "tx";
                        };
                        usp1: usp@b0090000 {
@@ -259,8 +261,8 @@
                                interrupts = <21>;
                                fifosize = <128>;
                                clocks = <&clks 29>;
-                                sirf,usp-dma-rx-channel = <14>;
+                                dmas = <&dmac0 14>, <&dmac0 15>;
-                                sirf,usp-dma-tx-channel = <15>;
+                                dma-names = "rx", "tx";
                        };
                        dmac0: dma-controller@b00b0000 {
@@ -269,6 +271,7 @@
                                reg = <0xb00b0000 0x10000>;
                                interrupts = <12>;
                                clocks = <&clks 24>;
+                                #dma-cells = <1>;
                        };
                        dmac1: dma-controller@b0160000 {
@@ -277,6 +280,7 @@
                                reg = <0xb0160000 0x10000>;
                                interrupts = <13>;
                                clocks = <&clks 25>;
+                                #dma-cells = <1>;
                        };
                        vip@b00C0000 {
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 792fde1b7f75..64d069bcc409 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -14,6 +14,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include "dt-bindings/clock/bcm281xx.h"
 #include "skeleton.dtsi"
 / {
@@ -43,7 +45,7 @@
                compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
                status = "disabled";
                reg = <0x3e000000 0x1000>;
-                clocks = <&uartb_clk>;
+                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -53,7 +55,7 @@
                compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
                status = "disabled";
                reg = <0x3e001000 0x1000>;
-                clocks = <&uartb2_clk>;
+                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
                interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -63,7 +65,7 @@
                compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
                status = "disabled";
                reg = <0x3e002000 0x1000>;
-                clocks = <&uartb3_clk>;
+                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -73,7 +75,7 @@
                compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
                status = "disabled";
                reg = <0x3e003000 0x1000>;
-                clocks = <&uartb4_clk>;
+                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
                interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -95,7 +97,7 @@
                compatible = "brcm,kona-timer";
                reg = <0x35006000 0x1000>;
                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&hub_timer_clk>;
+                clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
        };
        gpio: gpio@35003000 {
@@ -118,7 +120,7 @@
                compatible = "brcm,kona-sdhci";
                reg = <0x3f180000 0x10000>;
                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&sdio1_clk>;
+                clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
                status = "disabled";
        };
@@ -126,7 +128,7 @@
                compatible = "brcm,kona-sdhci";
                reg = <0x3f190000 0x10000>;
                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&sdio2_clk>;
+                clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
                status = "disabled";
        };
@@ -134,7 +136,7 @@
                compatible = "brcm,kona-sdhci";
                reg = <0x3f1a0000 0x10000>;
                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&sdio3_clk>;
+                clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
                status = "disabled";
        };
@@ -142,7 +144,7 @@
                compatible = "brcm,kona-sdhci";
                reg = <0x3f1b0000 0x10000>;
                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&sdio4_clk>;
+                clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
                status = "disabled";
        };
@@ -157,7 +159,7 @@
                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&bsc1_clk>;
+                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
                status = "disabled";
        };
@@ -167,7 +169,7 @@
                interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&bsc2_clk>;
+                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>;
                status = "disabled";
        };
@@ -177,7 +179,7 @@
                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&bsc3_clk>;
+                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>;
                status = "disabled";
        };
@@ -187,105 +189,191 @@
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&pmu_bsc_clk>;
+                clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>;
                status = "disabled";
        };
        clocks {
-                bsc1_clk: bsc1 {
+                #address-cells = <1>;
-                        compatible = "fixed-clock";
+                #size-cells = <1>;
-                        clock-frequency = <13000000>;
+                ranges;
+                root_ccu: root_ccu {
+                        compatible = "brcm,bcm11351-root-ccu";
+                        reg = <0x35001000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "frac_1m";
+                };
+                hub_ccu: hub_ccu {
+                        compatible = "brcm,bcm11351-hub-ccu";
+                        reg = <0x34000000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "tmon_1m";
+                };
+                aon_ccu: aon_ccu {
+                        compatible = "brcm,bcm11351-aon-ccu";
+                        reg = <0x35002000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "hub_timer",
+                                             "pmu_bsc",
+                                             "pmu_bsc_var";
+                };
+                master_ccu: master_ccu {
+                        compatible = "brcm,bcm11351-master-ccu";
+                        reg = <0x3f001000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "sdio1",
+                                             "sdio2",
+                                             "sdio3",
+                                             "sdio4",
+                                             "usb_ic",
+                                             "hsic2_48m",
+                                             "hsic2_12m";
+                };
+                slave_ccu: slave_ccu {
+                        compatible = "brcm,bcm11351-slave-ccu";
+                        reg = <0x3e011000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "uartb",
+                                             "uartb2",
+                                             "uartb3",
+                                             "uartb4",
+                                             "ssp0",
+                                             "ssp2",
+                                             "bsc1",
+                                             "bsc2",
+                                             "bsc3",
+                                             "pwm";
+                };
+                ref_1m_clk: ref_1m {
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <1000000>;
                };
-                bsc2_clk: bsc2 {
+                ref_32k_clk: ref_32k {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                        clock-frequency = <13000000>;
+                        clock-frequency = <32768>;
+                };
+                bbl_32k_clk: bbl_32k {
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
                };
-                bsc3_clk: bsc3 {
+                ref_13m_clk: ref_13m {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <13000000>;
-                        #clock-cells = <0>;
                };
-                pmu_bsc_clk: pmu_bsc {
+                var_13m_clk: var_13m {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <13000000>;
-                        #clock-cells = <0>;
                };
-                hub_timer_clk: hub_timer {
+                dft_19_5m_clk: dft_19_5m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <32768>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <19500000>;
                };
-                pwm_clk: pwm {
+                ref_crystal_clk: ref_crystal {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <26000000>;
-                        #clock-cells = <0>;
                };
-                sdio1_clk: sdio1 {
+                ref_cx40_clk: ref_cx40 {
-                        compatible = "fixed-clock";
-                        clock-frequency = <48000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <40000000>;
                };
-                sdio2_clk: sdio2 {
+                ref_52m_clk: ref_52m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <48000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
                };
-                sdio3_clk: sdio3 {
+                var_52m_clk: var_52m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <48000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
                };
-                sdio4_clk: sdio4 {
+                usb_otg_ahb_clk: usb_otg_ahb {
                        compatible = "fixed-clock";
-                        clock-frequency = <48000000>;
+                        clock-frequency = <52000000>;
                        #clock-cells = <0>;
                };
-                tmon_1m_clk: tmon_1m {
+                ref_96m_clk: ref_96m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <1000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <96000000>;
                };
-                uartb_clk: uartb {
+                var_96m_clk: var_96m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <13000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <96000000>;
                };
-                uartb2_clk: uartb2 {
+                ref_104m_clk: ref_104m {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                        clock-frequency = <13000000>;
+                        clock-frequency = <104000000>;
+                };
+                var_104m_clk: var_104m {
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <104000000>;
                };
-                uartb3_clk: uartb3 {
+                ref_156m_clk: ref_156m {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                        clock-frequency = <13000000>;
+                        clock-frequency = <156000000>;
+                };
+                var_156m_clk: var_156m {
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <156000000>;
                };
-                uartb4_clk: uartb4 {
+                ref_208m_clk: ref_208m {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                        clock-frequency = <13000000>;
+                        clock-frequency = <208000000>;
+                };
+                var_208m_clk: var_208m {
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <208000000>;
                };
-                usb_otg_ahb_clk: usb_otg_ahb {
+                ref_312m_clk: ref_312m {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                        clock-frequency = <52000000>;
+                        clock-frequency = <312000000>;
+                };
+                var_312m_clk: var_312m {
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <312000000>;
                };
        };
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm21664-garnet.dts
index 396b70459cdc..e87cb26ddf84 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm21664-garnet.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Broadcom Corporation
+ * Copyright (C) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
@@ -13,11 +13,13 @@
 /dts-v1/;
-#include "bcm11351.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include "bcm21664.dtsi"
 / {
-        model = "BCM11351 BRT board";
+        model = "BCM21664 Garnet board";
-        compatible = "brcm,bcm11351-brt", "brcm,bcm11351";
+        compatible = "brcm,bcm21664-garnet", "brcm,bcm21664";
        memory {
                reg = <0x80000000 0x40000000>; /* 1 GB */
@@ -40,7 +42,7 @@
        sdio4: sdio@3f1b0000 {
                max-frequency = <48000000>;
-                cd-gpios = <&gpio 14 0>;
+                cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>;
                status = "okay";
        };
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
new file mode 100644
index 000000000000..08a44d41b672
--- /dev/null
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -0,0 +1,292 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
+/ {
+        model = "BCM21664 SoC";
+        compatible = "brcm,bcm21664";
+        interrupt-parent = <&gic>;
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gic: interrupt-controller@3ff00100 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x3ff01000 0x1000>,
+                      <0x3ff00100 0x100>;
+        };
+        smc@0x3404e000 {
+                compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
+                reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
+        };
+        uart@3e000000 {
+                compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
+                status = "disabled";
+                reg = <0x3e000000 0x118>;
+                clocks = <&uartb_clk>;
+                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+        };
+        uart@3e001000 {
+                compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
+                status = "disabled";
+                reg = <0x3e001000 0x118>;
+                clocks = <&uartb2_clk>;
+                interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+        };
+        uart@3e002000 {
+                compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
+                status = "disabled";
+                reg = <0x3e002000 0x118>;
+                clocks = <&uartb3_clk>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+        };
+        L2: l2-cache {
+                compatible = "arm,pl310-cache";
+                reg = <0x3ff20000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+        };
+        brcm,resetmgr@35001f00 {
+                compatible = "brcm,bcm21664-resetmgr";
+                reg = <0x35001f00 0x24>;
+        };
+        timer@35006000 {
+                compatible = "brcm,kona-timer";
+                reg = <0x35006000 0x1c>;
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&hub_timer_clk>;
+        };
+        gpio: gpio@35003000 {
+                compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
+                reg = <0x35003000 0x524>;
+                interrupts =
+                       <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
+                        GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
+                        GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
+                        GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                #gpio-cells = <2>;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                interrupt-controller;
+        };
+        sdio1: sdio@3f180000 {
+                compatible = "brcm,kona-sdhci";
+                reg = <0x3f180000 0x801c>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sdio1_clk>;
+                status = "disabled";
+        };
+        sdio2: sdio@3f190000 {
+                compatible = "brcm,kona-sdhci";
+                reg = <0x3f190000 0x801c>;
+                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sdio2_clk>;
+                status = "disabled";
+        };
+        sdio3: sdio@3f1a0000 {
+                compatible = "brcm,kona-sdhci";
+                reg = <0x3f1a0000 0x801c>;
+                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sdio3_clk>;
+                status = "disabled";
+        };
+        sdio4: sdio@3f1b0000 {
+                compatible = "brcm,kona-sdhci";
+                reg = <0x3f1b0000 0x801c>;
+                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&sdio4_clk>;
+                status = "disabled";
+        };
+        i2c@3e016000 {
+                compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
+                reg = <0x3e016000 0x70>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&bsc1_clk>;
+                status = "disabled";
+        };
+        i2c@3e017000 {
+                compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
+                reg = <0x3e017000 0x70>;
+                interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&bsc2_clk>;
+                status = "disabled";
+        };
+        i2c@3e018000 {
+                compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
+                reg = <0x3e018000 0x70>;
+                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&bsc3_clk>;
+                status = "disabled";
+        };
+        i2c@3e01c000 {
+                compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
+                reg = <0x3e01c000 0x70>;
+                interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&bsc4_clk>;
+                status = "disabled";
+        };
+        clocks {
+                bsc1_clk: bsc1 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                bsc2_clk: bsc2 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                bsc3_clk: bsc3 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                bsc4_clk: bsc4 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                pmu_bsc_clk: pmu_bsc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                hub_timer_clk: hub_timer {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                        #clock-cells = <0>;
+                };
+                pwm_clk: pwm {
+                        compatible = "fixed-clock";
+                        clock-frequency = <26000000>;
+                        #clock-cells = <0>;
+                };
+                sdio1_clk: sdio1 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+                sdio2_clk: sdio2 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+                sdio3_clk: sdio3 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+                sdio4_clk: sdio4 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+                tmon_1m_clk: tmon_1m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <1000000>;
+                        #clock-cells = <0>;
+                };
+                uartb_clk: uartb {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                uartb2_clk: uartb2 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                uartb3_clk: uartb3 {
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                        #clock-cells = <0>;
+                };
+                usb_otg_ahb_clk: usb_otg_ahb {
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
+                        #clock-cells = <0>;
+                };
+        };
+        usbotg: usb@3f120000 {
+                compatible = "snps,dwc2";
+                reg = <0x3f120000 0x10000>;
+                interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&usb_otg_ahb_clk>;
+                clock-names = "otg";
+                phys = <&usbphy>;
+                phy-names = "usb2-phy";
+                status = "disabled";
+        };
+        usbphy: usb-phy@3f130000 {
+                compatible = "brcm,kona-usb2-phy";
+                reg = <0x3f130000 0x28>;
+                #phy-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index 5ff2382a49e4..af3da55eef49 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -46,27 +46,32 @@
        i2c@3500d000 {
                status="okay";
-                clock-frequency = <400000>;
+                clock-frequency = <100000>;
-        };
-        sdio1: sdio@3f180000 {
+                pmu: pmu@8 {
-                max-frequency = <48000000>;
+                        reg = <0x08>;
-                status = "okay";
+                };
        };
        sdio2: sdio@3f190000 {
                non-removable;
                max-frequency = <48000000>;
+                vmmc-supply = <&camldo1_reg>;
+                vqmmc-supply = <&iosr1_reg>;
                status = "okay";
        };
        sdio4: sdio@3f1b0000 {
                max-frequency = <48000000>;
                cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+                vmmc-supply = <&sdldo_reg>;
+                vqmmc-supply = <&sdxldo_reg>;
                status = "okay";
        };
        usbotg: usb@3f120000 {
+                vusb_d-supply = <&usbldo_reg>;
+                vusb_a-supply = <&iosr1_reg>;
                status = "okay";
        };
@@ -74,3 +79,39 @@
                status = "okay";
        };
 };
+#include "bcm59056.dtsi"
+&pmu {
+        compatible = "brcm,bcm59056";
+        interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+        regulators {
+                camldo1_reg: camldo1 {
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                sdldo_reg: sdldo {
+                        regulator-min-microvolt = <3000000>;
+                        regulator-max-microvolt = <3000000>;
+                };
+                sdxldo_reg: sdxldo {
+                        regulator-min-microvolt = <2700000>;
+                        regulator-max-microvolt = <3300000>;
+                };
+                usbldo_reg: usbldo {
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                iosr1_reg: iosr1 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index b021c96d3ba1..b8473c43e888 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -15,39 +15,52 @@
                #size-cells = <1>;
                ranges = <0x7e000000 0x20000000 0x02000000>;
-                timer {
+                timer@7e003000 {
                        compatible = "brcm,bcm2835-system-timer";
                        reg = <0x7e003000 0x1000>;
                        interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
                        clock-frequency = <1000000>;
                };
-                intc: interrupt-controller {
+                dma: dma@7e007000 {
+                        compatible = "brcm,bcm2835-dma";
+                        reg = <0x7e007000 0xf00>;
+                        interrupts = <1 16>,
+                                     <1 17>,
+                                     <1 18>,
+                                     <1 19>,
+                                     <1 20>,
+                                     <1 21>,
+                                     <1 22>,
+                                     <1 23>,
+                                     <1 24>,
+                                     <1 25>,
+                                     <1 26>,
+                                     <1 27>,
+                                     <1 28>;
+                        #dma-cells = <1>;
+                        brcm,dma-channel-mask = <0x7f35>;
+                };
+                intc: interrupt-controller@7e00b200 {
                        compatible = "brcm,bcm2835-armctrl-ic";
                        reg = <0x7e00b200 0x200>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
                };
-                watchdog {
+                watchdog@7e100000 {
                        compatible = "brcm,bcm2835-pm-wdt";
                        reg = <0x7e100000 0x28>;
                };
-                rng {
+                rng@7e104000 {
                        compatible = "brcm,bcm2835-rng";
                        reg = <0x7e104000 0x10>;
                };
-                uart@20201000 {
+                gpio: gpio@7e200000 {
-                        compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
-                        reg = <0x7e201000 0x1000>;
-                        interrupts = <2 25>;
-                        clock-frequency = <3000000>;
-                        arm,primecell-periphid = <0x00241011>;
-                };
-                gpio: gpio {
                        compatible = "brcm,bcm2835-gpio";
                        reg = <0x7e200000 0xb4>;
                        /*
@@ -70,7 +83,25 @@
                        #interrupt-cells = <2>;
                };
-                spi: spi@20204000 {
+                uart@7e201000 {
+                        compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+                        reg = <0x7e201000 0x1000>;
+                        interrupts = <2 25>;
+                        clock-frequency = <3000000>;
+                        arm,primecell-periphid = <0x00241011>;
+                };
+                i2s: i2s@7e203000 {
+                        compatible = "brcm,bcm2835-i2s";
+                        reg = <0x7e203000 0x20>,
+                              <0x7e101098 0x02>;
+                        dmas = <&dma 2>,
+                               <&dma 3>;
+                        dma-names = "tx", "rx";
+                };
+                spi: spi@7e204000 {
                        compatible = "brcm,bcm2835-spi";
                        reg = <0x7e204000 0x1000>;
                        interrupts = <2 22>;
@@ -90,7 +121,15 @@
                        status = "disabled";
                };
-                i2c1: i2c@20804000 {
+                sdhci: sdhci@7e300000 {
+                        compatible = "brcm,bcm2835-sdhci";
+                        reg = <0x7e300000 0x100>;
+                        interrupts = <2 30>;
+                        clocks = <&clk_mmc>;
+                        status = "disabled";
+                };
+                i2c1: i2c@7e804000 {
                        compatible = "brcm,bcm2835-i2c";
                        reg = <0x7e804000 0x1000>;
                        interrupts = <2 21>;
@@ -100,19 +139,15 @@
                        status = "disabled";
                };
-                sdhci: sdhci {
+                usb@7e980000 {
-                        compatible = "brcm,bcm2835-sdhci";
-                        reg = <0x7e300000 0x100>;
-                        interrupts = <2 30>;
-                        clocks = <&clk_mmc>;
-                        status = "disabled";
-                };
-                usb {
                        compatible = "brcm,bcm2835-usb";
                        reg = <0x7e980000 0x10000>;
                        interrupts = <1 9>;
                };
+                arm-pmu {
+                        compatible = "arm,arm1176-pmu";
+                };
        };
        clocks {
@@ -120,24 +155,27 @@
                #address-cells = <1>;
                #size-cells = <0>;
-                clk_mmc: mmc {
+                clk_mmc: clock@0 {
                        compatible = "fixed-clock";
                        reg = <0>;
                        #clock-cells = <0>;
+                        clock-output-names = "mmc";
                        clock-frequency = <100000000>;
                };
-                clk_i2c: i2c {
+                clk_i2c: clock@1 {
                        compatible = "fixed-clock";
                        reg = <1>;
                        #clock-cells = <0>;
+                        clock-output-names = "i2c";
                        clock-frequency = <250000000>;
                };
-                clk_spi: spi {
+                clk_spi: clock@2 {
                        compatible = "fixed-clock";
                        reg = <2>;
                        #clock-cells = <0>;
+                        clock-output-names = "spi";
                        clock-frequency = <250000000>;
                };
        };
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
new file mode 100644
index 000000000000..3b5259de5a38
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -0,0 +1,35 @@
+/*
+ * Broadcom BCM470X / BCM5301X arm platform code.
+ * DTS for Netgear R6250 V1
+ *
+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+/dts-v1/;
+#include "bcm4708.dtsi"
+/ {
+        compatible = "netgear,r6250v1", "brcm,bcm4708";
+        model = "Netgear R6250 V1 (BCM4708)";
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+        memory {
+                reg = <0x00000000 0x08000000>;
+        };
+        chipcommonA {
+                uart0: serial@0300 {
+                        status = "okay";
+                };
+                uart1: serial@0400 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
new file mode 100644
index 000000000000..31141e83fedd
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for BCM4708 SoC.
+ *
+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+#include "bcm5301x.dtsi"
+/ {
+        compatible = "brcm,bcm4708";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
new file mode 100644
index 000000000000..53c624f766b4
--- /dev/null
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -0,0 +1,95 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
+ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
+ *
+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+/ {
+        interrupt-parent = <&gic>;
+        chipcommonA {
+                compatible = "simple-bus";
+                ranges = <0x00000000 0x18000000 0x00001000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                uart0: serial@0300 {
+                        compatible = "ns16550";
+                        reg = <0x0300 0x100>;
+                        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <100000000>;
+                        status = "disabled";
+                };
+                uart1: serial@0400 {
+                        compatible = "ns16550";
+                        reg = <0x0400 0x100>;
+                        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <100000000>;
+                        status = "disabled";
+                };
+        };
+        mpcore {
+                compatible = "simple-bus";
+                ranges = <0x00000000 0x19020000 0x00003000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                scu@0000 {
+                        compatible = "arm,cortex-a9-scu";
+                        reg = <0x0000 0x100>;
+                };
+                timer@0200 {
+                        compatible = "arm,cortex-a9-global-timer";
+                        reg = <0x0200 0x100>;
+                        interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_periph>;
+                };
+                local-timer@0600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x0600 0x100>;
+                        interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_periph>;
+                };
+                gic: interrupt-controller@1000 {
+                        compatible = "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0x1000 0x1000>,
+                              <0x0100 0x100>;
+                };
+                L2: cache-controller@2000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x2000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                /* As long as we do not have a real clock driver us this
+                 * fixed clock */
+                clk_periph: periph {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <400000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm59056.dtsi b/arch/arm/boot/dts/bcm59056.dtsi
new file mode 100644
index 000000000000..dfadaaa89b05
--- /dev/null
+++ b/arch/arm/boot/dts/bcm59056.dtsi
@@ -0,0 +1,74 @@
+/*
+* Copyright 2014 Linaro Limited
+* Author: Matt Porter <mporter@linaro.org>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under  the terms of the GNU General  Public License as published by the
+* Free Software Foundation;  either version 2 of the License, or (at your
+* option) any later version.
+*/
+&pmu {
+        compatible = "brcm,bcm59056";
+        regulators {
+                rfldo_reg: rfldo {
+                };
+                camldo1_reg: camldo1 {
+                };
+                camldo2_reg: camldo2 {
+                };
+                simldo1_reg: simldo1 {
+                };
+                simldo2_reg: simldo2 {
+                };
+                sdldo_reg: sdldo {
+                };
+                sdxldo_reg: sdxldo {
+                };
+                mmcldo1_reg: mmcldo1 {
+                };
+                mmcldo2_reg: mmcldo2 {
+                };
+                audldo_reg: audldo {
+                };
+                micldo_reg: micldo {
+                };
+                usbldo_reg: usbldo {
+                };
+                vibldo_reg: vibldo {
+                };
+                csr_reg: csr {
+                };
+                iosr1_reg: iosr1 {
+                };
+                iosr2_reg: iosr2 {
+                };
+                msr_reg: msr {
+                };
+                sdsr1_reg: sdsr1 {
+                };
+                sdsr2_reg: sdsr2 {
+                };
+                vsr_reg: vsr {
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 187fd46b7b5e..3b891dd20993 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -186,6 +186,11 @@
                                reg = <0x20000 0x80>, <0x800100 0x8>;
                        };
+                        sysc: system-ctrl@20000 {
+                                compatible = "marvell,orion-system-controller";
+                                reg = <0x20000 0x110>;
+                        };
                        bridge_intc: bridge-interrupt-ctrl@20110 {
                                compatible = "marvell,orion-bridge-intc";
                                interrupt-controller;
@@ -210,6 +215,14 @@
                                clocks = <&core_clk 0>;
                        };
+                        watchdog@20300 {
+                                compatible = "marvell,orion-wdt";
+                                reg = <0x20300 0x28>, <0x20108 0x4>;
+                                interrupt-parent = <&bridge_intc>;
+                                interrupts = <3>;
+                                clocks = <&core_clk 0>;
+                        };
                        crypto: crypto-engine@30000 {
                                compatible = "marvell,orion-crypto";
                                reg = <0x30000 0x10000>,
@@ -381,7 +394,8 @@
                        pinctrl: pin-ctrl@d0200 {
                                compatible = "marvell,dove-pinctrl";
-                                reg = <0xd0200 0x10>;
+                                reg = <0xd0200 0x14>,
+                                      <0xd0440 0x04>;
                                clocks = <&gate_clk 22>;
                                pmx_gpio_0: pmx-gpio-0 {
@@ -603,6 +617,12 @@
                                reg = <0xd8500 0x20>;
                        };
+                        gconf: global-config@e802c {
+                                compatible = "marvell,dove-global-config",
+                                             "syscon";
+                                reg = <0xe802c 0x14>;
+                        };
                        gpio2: gpio-ctrl@e8400 {
                                compatible = "marvell,orion-gpio";
                                #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1fd75aa4639d..1c0f8e1893ae 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -47,6 +47,11 @@
                                1000000 1060000
                                1176000 1160000
                                >;
+                        clocks = <&dpll_mpu_ck>;
+                        clock-names = "cpu";
+                        clock-latency = <300000>; /* From omap-cpufreq driver */
                };
                cpu@1 {
                        device_type = "cpu";
@@ -149,6 +154,22 @@
                        ti,hwmods = "counter_32k";
                };
+                dra7_ctrl_general: tisyscon@4a002e00 {
+                        compatible = "syscon";
+                        reg = <0x4a002e00 0x7c>;
+                };
+                pbias_regulator: pbias_regulator {
+                        compatible = "ti,pbias-omap";
+                        reg = <0 0x4>;
+                        syscon = <&dra7_ctrl_general>;
+                        pbias_mmc_reg: pbias_mmc_omap5 {
+                                regulator-name = "pbias_mmc_omap5";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                };
                dra7_pmx_core: pinmux@4a003400 {
                        compatible = "pinctrl-single";
                        reg = <0x4a003400 0x0464>;
@@ -464,6 +485,20 @@
                        ti,hwmods = "wd_timer2";
                };
+                hwspinlock: spinlock@4a0f6000 {
+                        compatible = "ti,omap4-hwspinlock";
+                        reg = <0x4a0f6000 0x1000>;
+                        ti,hwmods = "spinlock";
+                        #hwlock-cells = <1>;
+                };
+                dmm@4e000000 {
+                        compatible = "ti,omap5-dmm";
+                        reg = <0x4e000000 0x800>;
+                        interrupts = <0 113 0x4>;
+                        ti,hwmods = "dmm";
+                };
                i2c1: i2c@48070000 {
                        compatible = "ti,omap4-i2c";
                        reg = <0x48070000 0x100>;
@@ -524,6 +559,7 @@
                        dmas = <&sdma 61>, <&sdma 62>;
                        dma-names = "tx", "rx";
                        status = "disabled";
+                        pbias-supply = <&pbias_mmc_reg>;
                };
                mmc2: mmc@480b4000 {
@@ -559,6 +595,138 @@
                        status = "disabled";
                };
+                abb_mpu: regulator-abb-mpu {
+                        compatible = "ti,abb-v3";
+                        regulator-name = "abb_mpu";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        clocks = <&sys_clkin1>;
+                        ti,settling-time = <50>;
+                        ti,clock-cycles = <16>;
+                        reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
+                              <0x4ae06014 0x4>, <0x4a003b20 0x8>,
+                              <0x4ae0c158 0x4>;
+                        reg-names = "setup-address", "control-address",
+                                    "int-address", "efuse-address",
+                                    "ldo-address";
+                        ti,tranxdone-status-mask = <0x80>;
+                        /* LDOVBBMPU_FBB_MUX_CTRL */
+                        ti,ldovbb-override-mask = <0x400>;
+                        /* LDOVBBMPU_FBB_VSET_OUT */
+                        ti,ldovbb-vset-mask = <0x1F>;
+                        /*
+                         * NOTE: only FBB mode used but actual vset will
+                         * determine final biasing
+                         */
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
+                        1060000         0       0x0     0 0x02000000 0x01F00000
+                        1160000         0       0x4     0 0x02000000 0x01F00000
+                        1210000         0       0x8     0 0x02000000 0x01F00000
+                        >;
+                };
+                abb_ivahd: regulator-abb-ivahd {
+                        compatible = "ti,abb-v3";
+                        regulator-name = "abb_ivahd";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        clocks = <&sys_clkin1>;
+                        ti,settling-time = <50>;
+                        ti,clock-cycles = <16>;
+                        reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
+                              <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
+                              <0x4a002470 0x4>;
+                        reg-names = "setup-address", "control-address",
+                                    "int-address", "efuse-address",
+                                    "ldo-address";
+                        ti,tranxdone-status-mask = <0x40000000>;
+                        /* LDOVBBIVA_FBB_MUX_CTRL */
+                        ti,ldovbb-override-mask = <0x400>;
+                        /* LDOVBBIVA_FBB_VSET_OUT */
+                        ti,ldovbb-vset-mask = <0x1F>;
+                        /*
+                         * NOTE: only FBB mode used but actual vset will
+                         * determine final biasing
+                         */
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
+                        1055000         0       0x0     0 0x02000000 0x01F00000
+                        1150000         0       0x4     0 0x02000000 0x01F00000
+                        1250000         0       0x8     0 0x02000000 0x01F00000
+                        >;
+                };
+                abb_dspeve: regulator-abb-dspeve {
+                        compatible = "ti,abb-v3";
+                        regulator-name = "abb_dspeve";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        clocks = <&sys_clkin1>;
+                        ti,settling-time = <50>;
+                        ti,clock-cycles = <16>;
+                        reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
+                              <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
+                              <0x4a00246c 0x4>;
+                        reg-names = "setup-address", "control-address",
+                                    "int-address", "efuse-address",
+                                    "ldo-address";
+                        ti,tranxdone-status-mask = <0x20000000>;
+                        /* LDOVBBDSPEVE_FBB_MUX_CTRL */
+                        ti,ldovbb-override-mask = <0x400>;
+                        /* LDOVBBDSPEVE_FBB_VSET_OUT */
+                        ti,ldovbb-vset-mask = <0x1F>;
+                        /*
+                         * NOTE: only FBB mode used but actual vset will
+                         * determine final biasing
+                         */
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
+                        1055000         0       0x0     0 0x02000000 0x01F00000
+                        1150000         0       0x4     0 0x02000000 0x01F00000
+                        1250000         0       0x8     0 0x02000000 0x01F00000
+                        >;
+                };
+                abb_gpu: regulator-abb-gpu {
+                        compatible = "ti,abb-v3";
+                        regulator-name = "abb_gpu";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        clocks = <&sys_clkin1>;
+                        ti,settling-time = <50>;
+                        ti,clock-cycles = <16>;
+                        reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
+                              <0x4ae06010 0x4>, <0x4a003b08 0x8>,
+                              <0x4ae0c154 0x4>;
+                        reg-names = "setup-address", "control-address",
+                                    "int-address", "efuse-address",
+                                    "ldo-address";
+                        ti,tranxdone-status-mask = <0x10000000>;
+                        /* LDOVBBGPU_FBB_MUX_CTRL */
+                        ti,ldovbb-override-mask = <0x400>;
+                        /* LDOVBBGPU_FBB_VSET_OUT */
+                        ti,ldovbb-vset-mask = <0x1F>;
+                        /*
+                         * NOTE: only FBB mode used but actual vset will
+                         * determine final biasing
+                         */
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
+                        1090000         0       0x0     0 0x02000000 0x01F00000
+                        1210000         0       0x4     0 0x02000000 0x01F00000
+                        1280000         0       0x8     0 0x02000000 0x01F00000
+                        >;
+                };
                mcspi1: spi@48098000 {
                        compatible = "ti,omap4-mcspi";
                        reg = <0x48098000 0x200>;
diff --git a/arch/arm/boot/dts/efm32gg-dk3750.dts b/arch/arm/boot/dts/efm32gg-dk3750.dts
index aa5c0f6363d6..b4031fa4a567 100644
--- a/arch/arm/boot/dts/efm32gg-dk3750.dts
+++ b/arch/arm/boot/dts/efm32gg-dk3750.dts
@@ -26,7 +26,7 @@
                };
                i2c@4000a000 {
-                        location = <3>;
+                        efm32,location = <3>;
                        status = "ok";
                        temp@48 {
diff --git a/arch/arm/boot/dts/efm32gg.dtsi b/arch/arm/boot/dts/efm32gg.dtsi
index a342ab0e6e4f..106d505c5d3d 100644
--- a/arch/arm/boot/dts/efm32gg.dtsi
+++ b/arch/arm/boot/dts/efm32gg.dtsi
@@ -84,7 +84,7 @@
                        status = "disabled";
                };
-                spi2: spi@40x4000c800 { /* USART2 */
+                spi2: spi@4000c800 { /* USART2 */
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "efm32,spi";
@@ -110,7 +110,7 @@
                        status = "disabled";
                };
-                uart2: uart@40x4000c800 { /* USART2 */
+                uart2: uart@4000c800 { /* USART2 */
                        compatible = "efm32,uart";
                        reg = <0x4000c800 0x400>;
                        interrupts = <18 19>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 08452e183b57..2f8bcd068d17 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,6 +19,7 @@
 * published by the Free Software Foundation.
 */
+#include <dt-bindings/clock/exynos4.h>
 #include "skeleton.dtsi"
 / {
@@ -85,6 +86,11 @@
                reg = <0x10023CE0 0x20>;
        };
+        pd_gps_alive: gps-alive-power-domain@10023D00 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10023D00 0x20>;
+        };
        gic: interrupt-controller@10490000 {
                compatible = "arm,cortex-a9-gic";
                #interrupt-cells = <3>;
@@ -104,6 +110,20 @@
                reg = <0x10010000 0x400>;
        };
+        dsi_0: dsi@11C80000 {
+                compatible = "samsung,exynos4210-mipi-dsi";
+                reg = <0x11C80000 0x10000>;
+                interrupts = <0 79 0>;
+                samsung,power-domain = <&pd_lcd0>;
+                phys = <&mipi_phy 1>;
+                phy-names = "dsim";
+                clocks = <&clock 286>, <&clock 143>;
+                clock-names = "bus_clk", "pll_clk";
+                status = "disabled";
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
        camera {
                compatible = "samsung,fimc", "simple-bus";
                status = "disabled";
@@ -119,7 +139,7 @@
                        compatible = "samsung,exynos4210-fimc";
                        reg = <0x11800000 0x1000>;
                        interrupts = <0 84 0>;
-                        clocks = <&clock 256>, <&clock 128>;
+                        clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
                        clock-names = "fimc", "sclk_fimc";
                        samsung,power-domain = <&pd_cam>;
                        samsung,sysreg = <&sys_reg>;
@@ -130,7 +150,7 @@
                        compatible = "samsung,exynos4210-fimc";
                        reg = <0x11810000 0x1000>;
                        interrupts = <0 85 0>;
-                        clocks = <&clock 257>, <&clock 129>;
+                        clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
                        clock-names = "fimc", "sclk_fimc";
                        samsung,power-domain = <&pd_cam>;
                        samsung,sysreg = <&sys_reg>;
@@ -141,7 +161,7 @@
                        compatible = "samsung,exynos4210-fimc";
                        reg = <0x11820000 0x1000>;
                        interrupts = <0 86 0>;
-                        clocks = <&clock 258>, <&clock 130>;
+                        clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
                        clock-names = "fimc", "sclk_fimc";
                        samsung,power-domain = <&pd_cam>;
                        samsung,sysreg = <&sys_reg>;
@@ -152,7 +172,7 @@
                        compatible = "samsung,exynos4210-fimc";
                        reg = <0x11830000 0x1000>;
                        interrupts = <0 87 0>;
-                        clocks = <&clock 259>, <&clock 131>;
+                        clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
                        clock-names = "fimc", "sclk_fimc";
                        samsung,power-domain = <&pd_cam>;
                        samsung,sysreg = <&sys_reg>;
@@ -163,7 +183,7 @@
                        compatible = "samsung,exynos4210-csis";
                        reg = <0x11880000 0x4000>;
                        interrupts = <0 78 0>;
-                        clocks = <&clock 260>, <&clock 134>;
+                        clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
                        clock-names = "csis", "sclk_csis";
                        bus-width = <4>;
                        samsung,power-domain = <&pd_cam>;
@@ -178,7 +198,7 @@
                        compatible = "samsung,exynos4210-csis";
                        reg = <0x11890000 0x4000>;
                        interrupts = <0 80 0>;
-                        clocks = <&clock 261>, <&clock 135>;
+                        clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
                        clock-names = "csis", "sclk_csis";
                        bus-width = <2>;
                        samsung,power-domain = <&pd_cam>;
@@ -194,7 +214,7 @@
                compatible = "samsung,s3c2410-wdt";
                reg = <0x10060000 0x100>;
                interrupts = <0 43 0>;
-                clocks = <&clock 345>;
+                clocks = <&clock CLK_WDT>;
                clock-names = "watchdog";
                status = "disabled";
        };
@@ -203,7 +223,7 @@
                compatible = "samsung,s3c6410-rtc";
                reg = <0x10070000 0x100>;
                interrupts = <0 44 0>, <0 45 0>;
-                clocks = <&clock 346>;
+                clocks = <&clock CLK_RTC>;
                clock-names = "rtc";
                status = "disabled";
        };
@@ -212,7 +232,7 @@
                compatible = "samsung,s5pv210-keypad";
                reg = <0x100A0000 0x100>;
                interrupts = <0 109 0>;
-                clocks = <&clock 347>;
+                clocks = <&clock CLK_KEYIF>;
                clock-names = "keypad";
                status = "disabled";
        };
@@ -221,7 +241,7 @@
                compatible = "samsung,exynos4210-sdhci";
                reg = <0x12510000 0x100>;
                interrupts = <0 73 0>;
-                clocks = <&clock 297>, <&clock 145>;
+                clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
                clock-names = "hsmmc", "mmc_busclk.2";
                status = "disabled";
        };
@@ -230,7 +250,7 @@
                compatible = "samsung,exynos4210-sdhci";
                reg = <0x12520000 0x100>;
                interrupts = <0 74 0>;
-                clocks = <&clock 298>, <&clock 146>;
+                clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
                clock-names = "hsmmc", "mmc_busclk.2";
                status = "disabled";
        };
@@ -239,7 +259,7 @@
                compatible = "samsung,exynos4210-sdhci";
                reg = <0x12530000 0x100>;
                interrupts = <0 75 0>;
-                clocks = <&clock 299>, <&clock 147>;
+                clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
                clock-names = "hsmmc", "mmc_busclk.2";
                status = "disabled";
        };
@@ -248,7 +268,7 @@
                compatible = "samsung,exynos4210-sdhci";
                reg = <0x12540000 0x100>;
                interrupts = <0 76 0>;
-                clocks = <&clock 300>, <&clock 148>;
+                clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
                clock-names = "hsmmc", "mmc_busclk.2";
                status = "disabled";
        };
@@ -257,7 +277,7 @@
                compatible = "samsung,exynos4210-ehci";
                reg = <0x12580000 0x100>;
                interrupts = <0 70 0>;
-                clocks = <&clock 304>;
+                clocks = <&clock CLK_USB_HOST>;
                clock-names = "usbhost";
                status = "disabled";
        };
@@ -266,7 +286,7 @@
                compatible = "samsung,exynos4210-ohci";
                reg = <0x12590000 0x100>;
                interrupts = <0 70 0>;
-                clocks = <&clock 304>;
+                clocks = <&clock CLK_USB_HOST>;
                clock-names = "usbhost";
                status = "disabled";
        };
@@ -276,7 +296,7 @@
                reg = <0x13400000 0x10000>;
                interrupts = <0 94 0>;
                samsung,power-domain = <&pd_mfc>;
-                clocks = <&clock 273>;
+                clocks = <&clock CLK_MFC>;
                clock-names = "mfc";
                status = "disabled";
        };
@@ -285,7 +305,7 @@
                compatible = "samsung,exynos4210-uart";
                reg = <0x13800000 0x100>;
                interrupts = <0 52 0>;
-                clocks = <&clock 312>, <&clock 151>;
+                clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
                clock-names = "uart", "clk_uart_baud0";
                status = "disabled";
        };
@@ -294,7 +314,7 @@
                compatible = "samsung,exynos4210-uart";
                reg = <0x13810000 0x100>;
                interrupts = <0 53 0>;
-                clocks = <&clock 313>, <&clock 152>;
+                clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
                clock-names = "uart", "clk_uart_baud0";
                status = "disabled";
        };
@@ -303,7 +323,7 @@
                compatible = "samsung,exynos4210-uart";
                reg = <0x13820000 0x100>;
                interrupts = <0 54 0>;
-                clocks = <&clock 314>, <&clock 153>;
+                clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
                clock-names = "uart", "clk_uart_baud0";
                status = "disabled";
        };
@@ -312,7 +332,7 @@
                compatible = "samsung,exynos4210-uart";
                reg = <0x13830000 0x100>;
                interrupts = <0 55 0>;
-                clocks = <&clock 315>, <&clock 154>;
+                clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
                clock-names = "uart", "clk_uart_baud0";
                status = "disabled";
        };
@@ -323,7 +343,7 @@
                compatible = "samsung,s3c2440-i2c";
                reg = <0x13860000 0x100>;
                interrupts = <0 58 0>;
-                clocks = <&clock 317>;
+                clocks = <&clock CLK_I2C0>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c0_bus>;
@@ -336,7 +356,7 @@
                compatible = "samsung,s3c2440-i2c";
                reg = <0x13870000 0x100>;
                interrupts = <0 59 0>;
-                clocks = <&clock 318>;
+                clocks = <&clock CLK_I2C1>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c1_bus>;
@@ -349,7 +369,7 @@
                compatible = "samsung,s3c2440-i2c";
                reg = <0x13880000 0x100>;
                interrupts = <0 60 0>;
-                clocks = <&clock 319>;
+                clocks = <&clock CLK_I2C2>;
                clock-names = "i2c";
                status = "disabled";
        };
@@ -360,7 +380,7 @@
                compatible = "samsung,s3c2440-i2c";
                reg = <0x13890000 0x100>;
                interrupts = <0 61 0>;
-                clocks = <&clock 320>;
+                clocks = <&clock CLK_I2C3>;
                clock-names = "i2c";
                status = "disabled";
        };
@@ -371,7 +391,7 @@
                compatible = "samsung,s3c2440-i2c";
                reg = <0x138A0000 0x100>;
                interrupts = <0 62 0>;
-                clocks = <&clock 321>;
+                clocks = <&clock CLK_I2C4>;
                clock-names = "i2c";
                status = "disabled";
        };
@@ -382,7 +402,7 @@
                compatible = "samsung,s3c2440-i2c";
                reg = <0x138B0000 0x100>;
                interrupts = <0 63 0>;
-                clocks = <&clock 322>;
+                clocks = <&clock CLK_I2C5>;
                clock-names = "i2c";
                status = "disabled";
        };
@@ -393,7 +413,7 @@
                compatible = "samsung,s3c2440-i2c";
                reg = <0x138C0000 0x100>;
                interrupts = <0 64 0>;
-                clocks = <&clock 323>;
+                clocks = <&clock CLK_I2C6>;
                clock-names = "i2c";
                status = "disabled";
        };
@@ -404,7 +424,7 @@
                compatible = "samsung,s3c2440-i2c";
                reg = <0x138D0000 0x100>;
                interrupts = <0 65 0>;
-                clocks = <&clock 324>;
+                clocks = <&clock CLK_I2C7>;
                clock-names = "i2c";
                status = "disabled";
        };
@@ -417,7 +437,7 @@
                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 327>, <&clock 159>;
+                clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
                clock-names = "spi", "spi_busclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&spi0_bus>;
@@ -432,7 +452,7 @@
                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 328>, <&clock 160>;
+                clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
                clock-names = "spi", "spi_busclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&spi1_bus>;
@@ -447,7 +467,7 @@
                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 329>, <&clock 161>;
+                clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
                clock-names = "spi", "spi_busclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&spi2_bus>;
@@ -458,7 +478,7 @@
                compatible = "samsung,exynos4210-pwm";
                reg = <0x139D0000 0x1000>;
                interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
-                clocks = <&clock 336>;
+                clocks = <&clock CLK_PWM>;
                clock-names = "timers";
                #pwm-cells = <2>;
                status = "disabled";
@@ -475,7 +495,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x12680000 0x1000>;
                        interrupts = <0 35 0>;
-                        clocks = <&clock 292>;
+                        clocks = <&clock CLK_PDMA0>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -486,7 +506,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x12690000 0x1000>;
                        interrupts = <0 36 0>;
-                        clocks = <&clock 293>;
+                        clocks = <&clock CLK_PDMA1>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -497,7 +517,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x12850000 0x1000>;
                        interrupts = <0 34 0>;
-                        clocks = <&clock 279>;
+                        clocks = <&clock CLK_MDMA>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -511,7 +531,7 @@
                reg = <0x11c00000 0x20000>;
                interrupt-names = "fifo", "vsync", "lcd_sys";
                interrupts = <11 0>, <11 1>, <11 2>;
-                clocks = <&clock 140>, <&clock 283>;
+                clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
                clock-names = "sclk_fimd", "fimd";
                samsung,power-domain = <&pd_lcd0>;
                status = "disabled";
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 2aa13cb3bbed..72fb11f7ea21 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -19,7 +19,7 @@
 / {
        model = "Insignal Origen evaluation board based on Exynos4210";
-        compatible = "insignal,origen", "samsung,exynos4210";
+        compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x10000000
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 9c01b718d29d..636d16684750 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -19,7 +19,7 @@
 / {
        model = "Samsung smdkv310 evaluation board based on Exynos4210";
-        compatible = "samsung,smdkv310", "samsung,exynos4210";
+        compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x80000000>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 63cc571ca307..63aa2bb24a4b 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -17,7 +17,7 @@
 / {
        model = "Samsung Trats based on Exynos4210";
-        compatible = "samsung,trats", "samsung,exynos4210";
+        compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4";
        memory {
                reg =  <0x40000000 0x10000000
@@ -353,6 +353,67 @@
                };
        };
+        dsi_0: dsi@11C80000 {
+                vddcore-supply = <&vusb_reg>;
+                vddio-supply = <&vmipi_reg>;
+                samsung,pll-clock-frequency = <24000000>;
+                status = "okay";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@1 {
+                                reg = <1>;
+                                dsi_out: endpoint {
+                                        remote-endpoint = <&dsi_in>;
+                                        samsung,burst-clock-frequency = <500000000>;
+                                        samsung,esc-clock-frequency = <20000000>;
+                                };
+                        };
+                };
+                panel@0 {
+                        reg = <0>;
+                        compatible = "samsung,s6e8aa0";
+                        vdd3-supply = <&vcclcd_reg>;
+                        vci-supply = <&vlcd_reg>;
+                        reset-gpios = <&gpy4 5 0>;
+                        power-on-delay= <50>;
+                        reset-delay = <100>;
+                        init-delay = <100>;
+                        flip-horizontal;
+                        flip-vertical;
+                        panel-width-mm = <58>;
+                        panel-height-mm = <103>;
+                        display-timings {
+                                timing-0 {
+                                        clock-frequency = <57153600>;
+                                        hactive = <720>;
+                                        vactive = <1280>;
+                                        hfront-porch = <5>;
+                                        hback-porch = <5>;
+                                        hsync-len = <5>;
+                                        vfront-porch = <13>;
+                                        vback-porch = <1>;
+                                        vsync-len = <2>;
+                                };
+                        };
+                        port {
+                                dsi_in: endpoint {
+                                        remote-endpoint = <&dsi_out>;
+                                };
+                        };
+                };
+        };
+        fimd@11c00000 {
+                status = "okay";
+        };
        camera {
                pinctrl-names = "default";
                pinctrl-0 = <>;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d2e3f5f5916d..63e34b24b04f 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -17,7 +17,7 @@
 / {
        model = "Samsung Universal C210 based on Exynos4210 rev0";
-        compatible = "samsung,universal_c210", "samsung,exynos4210";
+        compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4";
        memory {
                reg =  <0x40000000 0x10000000
@@ -345,6 +345,70 @@
                };
        };
+        spi-lcd {
+                compatible = "spi-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                gpio-sck = <&gpy3 1 0>;
+                gpio-mosi = <&gpy3 3 0>;
+                num-chipselects = <1>;
+                cs-gpios = <&gpy4 3 0>;
+                lcd@0 {
+                        compatible = "samsung,ld9040";
+                        reg = <0>;
+                        vdd3-supply = <&ldo7_reg>;
+                        vci-supply = <&ldo17_reg>;
+                        reset-gpios = <&gpy4 5 0>;
+                        spi-max-frequency = <1200000>;
+                        spi-cpol;
+                        spi-cpha;
+                        power-on-delay = <10>;
+                        reset-delay = <10>;
+                        panel-width-mm = <90>;
+                        panel-height-mm = <154>;
+                        display-timings {
+                                timing {
+                                        clock-frequency = <23492370>;
+                                        hactive = <480>;
+                                        vactive = <800>;
+                                        hback-porch = <16>;
+                                        hfront-porch = <16>;
+                                        vback-porch = <2>;
+                                        vfront-porch = <28>;
+                                        hsync-len = <2>;
+                                        vsync-len = <1>;
+                                        hsync-active = <0>;
+                                        vsync-active = <0>;
+                                        de-active = <0>;
+                                        pixelclk-active = <0>;
+                                };
+                        };
+                        port {
+                                lcd_ep: endpoint {
+                                        remote-endpoint = <&fimd_dpi_ep>;
+                                };
+                        };
+                };
+        };
+        fimd: fimd@11c00000 {
+                pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
+                pinctrl-names = "default";
+                status = "okay";
+                samsung,invert-vden;
+                samsung,invert-vclk;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@3 {
+                        reg = <3>;
+                        fimd_dpi_ep: endpoint {
+                                remote-endpoint = <&lcd_ep>;
+                        };
+                };
+        };
        pwm@139D0000 {
                compatible = "samsung,s5p6440-pwm";
                status = "okay";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 48ecd7a755ab..cacf6140dd2f 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -23,7 +23,7 @@
 #include "exynos4210-pinctrl.dtsi"
 / {
-        compatible = "samsung,exynos4210";
+        compatible = "samsung,exynos4210", "samsung,exynos4";
        aliases {
                pinctrl0 = &pinctrl_0;
@@ -53,7 +53,7 @@
                reg = <0x10050000 0x800>;
                interrupt-parent = <&mct_map>;
                interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
-                clocks = <&clock 3>, <&clock 344>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
                clock-names = "fin_pll", "mct";
                mct_map: mct-map {
@@ -109,7 +109,7 @@
                interrupt-parent = <&combiner>;
                reg = <0x100C0000 0x100>;
                interrupts = <2 4>;
-                clocks = <&clock 383>;
+                clocks = <&clock CLK_TMU_APBIF>;
                clock-names = "tmu_apbif";
                status = "disabled";
        };
@@ -118,13 +118,14 @@
                compatible = "samsung,s5pv210-g2d";
                reg = <0x12800000 0x1000>;
                interrupts = <0 89 0>;
-                clocks = <&clock 177>, <&clock 277>;
+                clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
                clock-names = "sclk_fimg2d", "fimg2d";
                status = "disabled";
        };
        camera {
-                clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
+                clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
+                         <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
                clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
                fimc_0: fimc@11800000 {
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 94a43f9a05e2..3c00e6ec9302 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -20,18 +20,13 @@
 #include "exynos4x12.dtsi"
 / {
-        compatible = "samsung,exynos4212";
+        compatible = "samsung,exynos4212", "samsung,exynos4";
-        gic: interrupt-controller@10490000 {
+        combiner: interrupt-controller@10440000 {
-                cpu-offset = <0x8000>;
+                samsung,combiner-nr = <18>;
        };
-        interrupt-controller@10440000 {
+        gic: interrupt-controller@10490000 {
-                samsung,combiner-nr = <18>;
+                cpu-offset = <0x8000>;
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                             <0 107 0>, <0 108 0>;
        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 9804fcb71f8c..31db28a4bb33 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -16,7 +16,7 @@
 / {
        model = "Hardkernel ODROID-X board based on Exynos4412";
-        compatible = "hardkernel,odroid-x", "samsung,exynos4412";
+        compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x40000000>;
@@ -251,7 +251,7 @@
                                buck2_reg: BUCK2 {
                                        regulator-name = "vdd_arm";
                                        regulator-min-microvolt = <900000>;
-                                        regulator-max-microvolt = <1300000>;
+                                        regulator-max-microvolt = <1350000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                };
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 6bc053924e9e..e2c0dcab4d81 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -17,7 +17,7 @@
 / {
        model = "Insignal Origen evaluation board based on Exynos4412";
-        compatible = "insignal,origen4412", "samsung,exynos4412";
+        compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x40000000>;
@@ -459,8 +459,8 @@
                                buck2_reg: BUCK2 {
                                        regulator-name = "vdd_arm";
-                                        regulator-min-microvolt = <925000>;
+                                        regulator-min-microvolt = <900000>;
-                                        regulator-max-microvolt = <1300000>;
+                                        regulator-max-microvolt = <1350000>;
                                        regulator-always-on;
                                        regulator-boot-on;
                                        op_mode = <1>; /* Normal Mode */
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index ad316a1ee9e0..ded0b70f7644 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -17,7 +17,7 @@
 / {
        model = "Samsung SMDK evaluation board based on Exynos4412";
-        compatible = "samsung,smdk4412", "samsung,exynos4412";
+        compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x40000000>;
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
index 0a9831256b33..ea6929d9c621 100644
--- a/arch/arm/boot/dts/exynos4412-tiny4412.dts
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -16,7 +16,7 @@
 / {
        model = "FriendlyARM TINY4412 board based on Exynos4412";
-        compatible = "friendlyarm,tiny4412", "samsung,exynos4412";
+        compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4";
        memory {
                reg = <0x40000000 0x40000000>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 4f851ccf40eb..9583563dd0ef 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -17,7 +17,7 @@
 / {
        model = "Samsung Trats 2 based on Exynos4412";
-        compatible = "samsung,trats2", "samsung,exynos4412";
+        compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
        aliases {
                i2c8 = &i2c_ak8975;
@@ -71,6 +71,15 @@
                        enable-active-high;
                };
+                lcd_vdd3_reg: voltage-regulator-2 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "LCD_VDD_2.2V";
+                        regulator-min-microvolt = <2200000>;
+                        regulator-max-microvolt = <2200000>;
+                        gpio = <&gpc0 1 0>;
+                        enable-active-high;
+                };
                /* More to come */
        };
@@ -106,6 +115,11 @@
                };
        };
+        adc: adc@126C0000 {
+                vdd-supply = <&ldo3_reg>;
+                status = "okay";
+        };
        i2c@13890000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-slave-addr = <0x10>;
@@ -511,6 +525,67 @@
                };
        };
+        dsi_0: dsi@11C80000 {
+                vddcore-supply = <&ldo8_reg>;
+                vddio-supply = <&ldo10_reg>;
+                samsung,pll-clock-frequency = <24000000>;
+                status = "okay";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@1 {
+                                reg = <1>;
+                                dsi_out: endpoint {
+                                        remote-endpoint = <&dsi_in>;
+                                        samsung,burst-clock-frequency = <500000000>;
+                                        samsung,esc-clock-frequency = <20000000>;
+                                };
+                        };
+                };
+                panel@0 {
+                        compatible = "samsung,s6e8aa0";
+                        reg = <0>;
+                        vdd3-supply = <&lcd_vdd3_reg>;
+                        vci-supply = <&ldo25_reg>;
+                        reset-gpios = <&gpy4 5 0>;
+                        power-on-delay= <50>;
+                        reset-delay = <100>;
+                        init-delay = <100>;
+                        flip-horizontal;
+                        flip-vertical;
+                        panel-width-mm = <58>;
+                        panel-height-mm = <103>;
+                        display-timings {
+                                timing-0 {
+                                        clock-frequency = <0>;
+                                        hactive = <720>;
+                                        vactive = <1280>;
+                                        hfront-porch = <5>;
+                                        hback-porch = <5>;
+                                        hsync-len = <5>;
+                                        vfront-porch = <13>;
+                                        vback-porch = <1>;
+                                        vsync-len = <2>;
+                                };
+                        };
+                        port {
+                                dsi_in: endpoint {
+                                        remote-endpoint = <&dsi_out>;
+                                };
+                        };
+                };
+        };
+        fimd@11c00000 {
+                status = "okay";
+        };
        camera {
                pinctrl-0 = <&cam_port_b_clk_active>;
                pinctrl-names = "default";
@@ -589,4 +664,20 @@
                        };
                };
        };
+        thermistor-ap@0 {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;   /* VCC_1.8V_AP */
+                pullup-ohm = <100000>;   /* 100K */
+                pulldown-ohm = <100000>; /* 100K */
+                io-channels = <&adc 1>;  /* AP temperature */
+        };
+        thermistor-battery@1 {
+                compatible = "ntc,ncp15wb473";
+                pullup-uv = <1800000>;   /* VCC_1.8V_AP */
+                pullup-ohm = <100000>;   /* 100K */
+                pulldown-ohm = <100000>; /* 100K */
+                io-channels = <&adc 2>;  /* Battery temperature */
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 87b339c739de..15d3c0ac2f5f 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -20,19 +20,13 @@
 #include "exynos4x12.dtsi"
 / {
-        compatible = "samsung,exynos4412";
+        compatible = "samsung,exynos4412", "samsung,exynos4";
-        gic: interrupt-controller@10490000 {
+        combiner: interrupt-controller@10440000 {
-                cpu-offset = <0x4000>;
-        };
-        interrupt-controller@10440000 {
                samsung,combiner-nr = <20>;
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                             <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
        };
+        gic: interrupt-controller@10490000 {
+                cpu-offset = <0x4000>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 5c412aa14738..c4a9306f8529 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -31,6 +31,12 @@
                mshc0 = &mshc_0;
        };
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
+        };
        pd_isp: isp-power-domain@10023CA0 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10023CA0 0x20>;
@@ -47,7 +53,7 @@
                reg = <0x10050000 0x800>;
                interrupt-parent = <&mct_map>;
                interrupts = <0>, <1>, <2>, <3>, <4>;
-                clocks = <&clock 3>, <&clock 344>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
                clock-names = "fin_pll", "mct";
                mct_map: mct-map {
@@ -62,6 +68,14 @@
                };
        };
+        combiner: interrupt-controller@10440000 {
+                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                             <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
+        };
        pinctrl_0: pinctrl@11400000 {
                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x11400000 0x1000>;
@@ -80,6 +94,18 @@
                };
        };
+        adc: adc@126C0000 {
+                compatible = "samsung,exynos-adc-v1";
+                reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+                interrupt-parent = <&combiner>;
+                interrupts = <10 3>;
+                clocks = <&clock CLK_TSADC>;
+                clock-names = "adc";
+                #io-channel-cells = <1>;
+                io-channel-ranges;
+                status = "disabled";
+        };
        pinctrl_2: pinctrl@03860000 {
                compatible = "samsung,exynos4x12-pinctrl";
                reg = <0x03860000 0x1000>;
@@ -97,13 +123,14 @@
                compatible = "samsung,exynos4212-g2d";
                reg = <0x10800000 0x1000>;
                interrupts = <0 89 0>;
-                clocks = <&clock 177>, <&clock 277>;
+                clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
                clock-names = "sclk_fimg2d", "fimg2d";
                status = "disabled";
        };
        camera {
-                clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
+                clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
+                         <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
                clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
                fimc_0: fimc@11800000 {
@@ -145,7 +172,7 @@
                        reg = <0x12390000 0x1000>;
                        interrupts = <0 105 0>;
                        samsung,power-domain = <&pd_isp>;
-                        clocks = <&clock 353>;
+                        clocks = <&clock CLK_FIMC_LITE0>;
                        clock-names = "flite";
                        status = "disabled";
                };
@@ -155,7 +182,7 @@
                        reg = <0x123A0000 0x1000>;
                        interrupts = <0 106 0>;
                        samsung,power-domain = <&pd_isp>;
-                        clocks = <&clock 354>;
+                        clocks = <&clock CLK_FIMC_LITE1>;
                        clock-names = "flite";
                        status = "disabled";
                };
@@ -165,12 +192,19 @@
                        reg = <0x12000000 0x260000>;
                        interrupts = <0 90 0>, <0 95 0>;
                        samsung,power-domain = <&pd_isp>;
-                        clocks = <&clock 353>, <&clock 354>, <&clock 355>,
+                        clocks = <&clock CLK_FIMC_LITE0>,
-                                <&clock 356>, <&clock 17>, <&clock 357>,
+                                 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
-                                <&clock 358>, <&clock 359>, <&clock 360>,
+                                 <&clock CLK_PPMUISPMX>,
-                                <&clock 450>,<&clock 451>, <&clock 452>,
+                                 <&clock CLK_MOUT_MPLL_USER_T>,
-                                <&clock 453>, <&clock 176>, <&clock 13>,
+                                 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
-                                <&clock 454>, <&clock 395>, <&clock 455>;
+                                 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
+                                 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
+                                 <&clock CLK_DIV_MCUISP0>,
+                                 <&clock CLK_DIV_MCUISP1>,
+                                 <&clock CLK_SCLK_UART_ISP>,
+                                 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
+                                 <&clock CLK_ACLK400_MCUISP>,
+                                 <&clock CLK_DIV_ACLK400_MCUISP>;
                        clock-names = "lite0", "lite1", "ppmuispx",
                                      "ppmuispmx", "mpll", "isp",
                                      "drc", "fd", "mcuisp",
@@ -190,7 +224,7 @@
                        i2c1_isp: i2c-isp@12140000 {
                                compatible = "samsung,exynos4212-i2c-isp";
                                reg = <0x12140000 0x100>;
-                                clocks = <&clock 370>;
+                                clocks = <&clock CLK_I2C1_ISP>;
                                clock-names = "i2c_isp";
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -205,7 +239,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                fifo-depth = <0x80>;
-                clocks = <&clock 301>, <&clock 149>;
+                clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
                clock-names = "biu", "ciu";
                status = "disabled";
        };
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 258dca441f36..79d0608d6dcc 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -81,13 +81,6 @@
                status = "disabled";
        };
-        watchdog {
-                compatible = "samsung,s3c2410-wdt";
-                reg = <0x101D0000 0x100>;
-                interrupts = <0 42 0>;
-                status = "disabled";
-        };
        fimd@14400000 {
                compatible = "samsung,exynos5250-fimd";
                interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index b42e658876e5..090f9830b129 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -15,7 +15,7 @@
 / {
        model = "Insignal Arndale evaluation board based on EXYNOS5250";
-        compatible = "insignal,arndale", "samsung,exynos5250";
+        compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";
        memory {
                reg = <0x40000000 0x80000000>;
@@ -25,6 +25,10 @@
                bootargs = "console=ttySAC2,115200";
        };
+        rtc@101E0000 {
+                status = "okay";
+        };
        codec@11000000 {
                samsung,mfc-r = <0x43000000 0x800000>;
                samsung,mfc-l = <0x51000000 0x800000>;
@@ -287,6 +291,7 @@
                                        regulator-name = "vdd_g3d";
                                        regulator-min-microvolt = <1000000>;
                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
                                        regulator-boot-on;
                                        op_mode = <1>;
                                };
@@ -370,6 +375,27 @@
                };
        };
+        i2c@121D0000 {
+                status = "okay";
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <40000>;
+                samsung,i2c-slave-addr = <0x38>;
+                sata_phy_i2c:sata-phy@38 {
+                        compatible = "samsung,exynos-sataphy-i2c";
+                        reg = <0x38>;
+                };
+        };
+        sata@122F0000 {
+                status = "okay";
+        };
+        sata-phy@12170000 {
+                status = "okay";
+                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+        };
        mmc_0: mmc@12200000 {
                status = "okay";
                num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e69837c435c..a794a705d404 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -14,7 +14,7 @@
 / {
        model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
-        compatible = "samsung,smdk5250", "samsung,exynos5250";
+        compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
        aliases {
        };
@@ -27,6 +27,10 @@
                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
        };
+        rtc@101E0000 {
+                status = "okay";
+        };
        i2c@12C60000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-max-bus-freq = <20000>;
@@ -36,6 +40,148 @@
                        compatible = "samsung,s524ad0xd1";
                        reg = <0x50>;
                };
+                max77686@09 {
+                        compatible = "maxim,max77686";
+                        reg = <0x09>;
+                        voltage-regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "P1.0V_LDO_OUT1";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "P1.2V_LDO_OUT2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "P1.8V_LDO_OUT3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "P2.8V_LDO_OUT4";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "P1.8V_LDO_OUT5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "P1.1V_LDO_OUT6";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "P1.1V_LDO_OUT7";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "P1.0V_LDO_OUT8";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                };
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "P1.8V_LDO_OUT10";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "P1.8V_LDO_OUT11";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "P3.0V_LDO_OUT12";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                };
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "P1.8V_LDO_OUT13";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "P1.8V_LDO_OUT14";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "P1.0V_LDO_OUT15";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                };
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "P1.8V_LDO_OUT16";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "P1.8V_BUCK_OUT5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
        };
        vdd: fixed-regulator@0 {
@@ -96,16 +242,12 @@
                samsung,i2c-slave-addr = <0x38>;
                status = "okay";
-                sata-phy {
+                sata_phy_i2c:sata-phy@38 {
-                        compatible = "samsung,sata-phy";
+                        compatible = "samsung,exynos-sataphy-i2c";
                        reg = <0x38>;
                };
        };
-        sata@122F0000 {
-                samsung,sata-freq = <66>;
-        };
        i2c@12C80000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-max-bus-freq = <66000>;
@@ -128,6 +270,15 @@
                };
        };
+        sata@122F0000 {
+                status = "okay";
+        };
+        sata-phy@12170000 {
+                status = "okay";
+                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+        };
        mmc@12200000 {
                status = "okay";
                num-slots = <1>;
@@ -164,10 +315,6 @@
                };
        };
-        spi_0: spi@12d20000 {
-                status = "disabled";
-        };
        spi_1: spi@12d30000 {
                status = "okay";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 7e45eea2d78f..1ce1088a00fb 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -14,12 +14,16 @@
 / {
        model = "Google Snow";
-        compatible = "google,snow", "samsung,exynos5250";
+        compatible = "google,snow", "samsung,exynos5250", "samsung,exynos5";
        aliases {
                i2c104 = &i2c_104;
        };
+        rtc@101E0000 {
+                status = "okay";
+        };
        pinctrl@11400000 {
                sd3_clk: sd3-clk {
                        samsung,pin-drv = <0>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b7dec41e32af..37423314a028 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,13 +17,14 @@
 * published by the Free Software Foundation.
 */
+#include <dt-bindings/clock/exynos5250.h>
 #include "exynos5.dtsi"
 #include "exynos5250-pinctrl.dtsi"
-#include <dt-bindings/clk/exynos-audss-clk.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
 / {
-        compatible = "samsung,exynos5250";
+        compatible = "samsung,exynos5250", "samsung,exynos5";
        aliases {
                spi0 = &spi_0;
@@ -46,6 +47,7 @@
                i2c6 = &i2c_6;
                i2c7 = &i2c_7;
                i2c8 = &i2c_8;
+                i2c9 = &i2c_9;
                pinctrl0 = &pinctrl_0;
                pinctrl1 = &pinctrl_1;
                pinctrl2 = &pinctrl_2;
@@ -90,7 +92,8 @@
                compatible = "samsung,exynos5250-audss-clock";
                reg = <0x03810000 0x0C>;
                #clock-cells = <1>;
-                clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+                         <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
                clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
        };
@@ -115,7 +118,7 @@
                interrupt-parent = <&mct_map>;
                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
                             <4 0>, <5 0>;
-                clocks = <&clock 1>, <&clock 335>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
                clock-names = "fin_pll", "mct";
                mct_map: mct-map {
@@ -167,16 +170,25 @@
                interrupts = <0 47 0>;
        };
-        watchdog {
+        pmu_system_controller: system-controller@10040000 {
-                clocks = <&clock 336>;
+                compatible = "samsung,exynos5250-pmu", "syscon";
+                reg = <0x10040000 0x5000>;
+        };
+        watchdog@101D0000 {
+                compatible = "samsung,exynos5250-wdt";
+                reg = <0x101D0000 0x100>;
+                interrupts = <0 42 0>;
+                clocks = <&clock CLK_WDT>;
                clock-names = "watchdog";
+                samsung,syscon-phandle = <&pmu_system_controller>;
        };
        g2d@10850000 {
                compatible = "samsung,exynos5250-g2d";
                reg = <0x10850000 0x1000>;
                interrupts = <0 91 0>;
-                clocks = <&clock 345>;
+                clocks = <&clock CLK_G2D>;
                clock-names = "fimg2d";
        };
@@ -185,55 +197,64 @@
                reg = <0x11000000 0x10000>;
                interrupts = <0 96 0>;
                samsung,power-domain = <&pd_mfc>;
-                clocks = <&clock 266>;
+                clocks = <&clock CLK_MFC>;
                clock-names = "mfc";
        };
        rtc@101E0000 {
-                clocks = <&clock 337>;
+                clocks = <&clock CLK_RTC>;
                clock-names = "rtc";
-                status = "okay";
+                status = "disabled";
        };
        tmu@10060000 {
                compatible = "samsung,exynos5250-tmu";
                reg = <0x10060000 0x100>;
                interrupts = <0 65 0>;
-                clocks = <&clock 338>;
+                clocks = <&clock CLK_TMU>;
                clock-names = "tmu_apbif";
        };
        serial@12C00000 {
-                clocks = <&clock 289>, <&clock 146>;
+                clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
                clock-names = "uart", "clk_uart_baud0";
        };
        serial@12C10000 {
-                clocks = <&clock 290>, <&clock 147>;
+                clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
                clock-names = "uart", "clk_uart_baud0";
        };
        serial@12C20000 {
-                clocks = <&clock 291>, <&clock 148>;
+                clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
                clock-names = "uart", "clk_uart_baud0";
        };
        serial@12C30000 {
-                clocks = <&clock 292>, <&clock 149>;
+                clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
                clock-names = "uart", "clk_uart_baud0";
        };
        sata@122F0000 {
-                compatible = "samsung,exynos5-sata-ahci";
+                compatible = "snps,dwc-ahci";
+                samsung,sata-freq = <66>;
                reg = <0x122F0000 0x1ff>;
                interrupts = <0 115 0>;
-                clocks = <&clock 277>, <&clock 143>;
+                clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
                clock-names = "sata", "sclk_sata";
+                phys = <&sata_phy>;
+                phy-names = "sata-phy";
+                status = "disabled";
        };
-        sata-phy@12170000 {
+        sata_phy: sata-phy@12170000 {
-                compatible = "samsung,exynos5-sata-phy";
+                compatible = "samsung,exynos5250-sata-phy";
                reg = <0x12170000 0x1ff>;
+                clocks = <&clock 287>;
+                clock-names = "sata_phyctrl";
+                #phy-cells = <0>;
+                samsung,syscon-phandle = <&pmu_system_controller>;
+                status = "disabled";
        };
        i2c_0: i2c@12C60000 {
@@ -242,7 +263,7 @@
                interrupts = <0 56 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 294>;
+                clocks = <&clock CLK_I2C0>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c0_bus>;
@@ -255,7 +276,7 @@
                interrupts = <0 57 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 295>;
+                clocks = <&clock CLK_I2C1>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c1_bus>;
@@ -268,7 +289,7 @@
                interrupts = <0 58 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 296>;
+                clocks = <&clock CLK_I2C2>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c2_bus>;
@@ -281,7 +302,7 @@
                interrupts = <0 59 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 297>;
+                clocks = <&clock CLK_I2C3>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c3_bus>;
@@ -294,7 +315,7 @@
                interrupts = <0 60 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 298>;
+                clocks = <&clock CLK_I2C4>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c4_bus>;
@@ -307,7 +328,7 @@
                interrupts = <0 61 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 299>;
+                clocks = <&clock CLK_I2C5>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c5_bus>;
@@ -320,7 +341,7 @@
                interrupts = <0 62 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 300>;
+                clocks = <&clock CLK_I2C6>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c6_bus>;
@@ -333,7 +354,7 @@
                interrupts = <0 63 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 301>;
+                clocks = <&clock CLK_I2C7>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c7_bus>;
@@ -346,17 +367,17 @@
                interrupts = <0 64 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 302>;
+                clocks = <&clock CLK_I2C_HDMI>;
                clock-names = "i2c";
                status = "disabled";
        };
-        i2c@121D0000 {
+        i2c_9: i2c@121D0000 {
                compatible = "samsung,exynos5-sata-phy-i2c";
                reg = <0x121D0000 0x100>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 288>;
+                clocks = <&clock CLK_SATA_PHYI2C>;
                clock-names = "i2c";
                status = "disabled";
        };
@@ -371,7 +392,7 @@
                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 304>, <&clock 154>;
+                clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
                clock-names = "spi", "spi_busclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&spi0_bus>;
@@ -387,7 +408,7 @@
                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 305>, <&clock 155>;
+                clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
                clock-names = "spi", "spi_busclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&spi1_bus>;
@@ -403,7 +424,7 @@
                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 306>, <&clock 156>;
+                clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
                clock-names = "spi", "spi_busclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&spi2_bus>;
@@ -415,7 +436,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0x12200000 0x1000>;
-                clocks = <&clock 280>, <&clock 139>;
+                clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x80>;
                status = "disabled";
@@ -427,7 +448,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0x12210000 0x1000>;
-                clocks = <&clock 281>, <&clock 140>;
+                clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x80>;
                status = "disabled";
@@ -439,7 +460,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0x12220000 0x1000>;
-                clocks = <&clock 282>, <&clock 141>;
+                clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x80>;
                status = "disabled";
@@ -451,7 +472,7 @@
                interrupts = <0 78 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 283>, <&clock 142>;
+                clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x80>;
                status = "disabled";
@@ -481,7 +502,7 @@
                dmas = <&pdma1 12
                        &pdma1 11>;
                dma-names = "tx", "rx";
-                clocks = <&clock 307>, <&clock 157>;
+                clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
                clock-names = "iis", "i2s_opclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&i2s1_bus>;
@@ -494,7 +515,7 @@
                dmas = <&pdma0 12
                        &pdma0 11>;
                dma-names = "tx", "rx";
-                clocks = <&clock 308>, <&clock 158>;
+                clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
                clock-names = "iis", "i2s_opclk0";
                pinctrl-names = "default";
                pinctrl-0 = <&i2s2_bus>;
@@ -502,7 +523,7 @@
        usb@12000000 {
                compatible = "samsung,exynos5250-dwusb3";
-                clocks = <&clock 286>;
+                clocks = <&clock CLK_USB3>;
                clock-names = "usbdrd30";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -519,7 +540,7 @@
        usb3_phy: usbphy@12100000 {
                compatible = "samsung,exynos5250-usb3phy";
                reg = <0x12100000 0x100>;
-                clocks = <&clock 1>, <&clock 286>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>;
                clock-names = "ext_xtal", "usbdrd30";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -535,7 +556,7 @@
                reg = <0x12110000 0x100>;
                interrupts = <0 71 0>;
-                clocks = <&clock 285>;
+                clocks = <&clock CLK_USB2>;
                clock-names = "usbhost";
        };
@@ -544,14 +565,14 @@
                reg = <0x12120000 0x100>;
                interrupts = <0 71 0>;
-                clocks = <&clock 285>;
+                clocks = <&clock CLK_USB2>;
                clock-names = "usbhost";
        };
        usb2_phy: usbphy@12130000 {
                compatible = "samsung,exynos5250-usb2phy";
                reg = <0x12130000 0x100>;
-                clocks = <&clock 1>, <&clock 285>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
                clock-names = "ext_xtal", "usbhost";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -568,7 +589,7 @@
                reg = <0x12dd0000 0x100>;
                samsung,pwm-outputs = <0>, <1>, <2>, <3>;
                #pwm-cells = <3>;
-                clocks = <&clock 311>;
+                clocks = <&clock CLK_PWM>;
                clock-names = "timers";
        };
@@ -583,7 +604,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x121A0000 0x1000>;
                        interrupts = <0 34 0>;
-                        clocks = <&clock 275>;
+                        clocks = <&clock CLK_PDMA0>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -594,7 +615,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x121B0000 0x1000>;
                        interrupts = <0 35 0>;
-                        clocks = <&clock 276>;
+                        clocks = <&clock CLK_PDMA1>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -605,7 +626,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x10800000 0x1000>;
                        interrupts = <0 33 0>;
-                        clocks = <&clock 346>;
+                        clocks = <&clock CLK_MDMA0>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -616,7 +637,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x11C10000 0x1000>;
                        interrupts = <0 124 0>;
-                        clocks = <&clock 271>;
+                        clocks = <&clock CLK_MDMA1>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -629,7 +650,7 @@
                reg = <0x13e00000 0x1000>;
                interrupts = <0 85 0>;
                samsung,power-domain = <&pd_gsc>;
-                clocks = <&clock 256>;
+                clocks = <&clock CLK_GSCL0>;
                clock-names = "gscl";
        };
@@ -638,7 +659,7 @@
                reg = <0x13e10000 0x1000>;
                interrupts = <0 86 0>;
                samsung,power-domain = <&pd_gsc>;
-                clocks = <&clock 257>;
+                clocks = <&clock CLK_GSCL1>;
                clock-names = "gscl";
        };
@@ -647,7 +668,7 @@
                reg = <0x13e20000 0x1000>;
                interrupts = <0 87 0>;
                samsung,power-domain = <&pd_gsc>;
-                clocks = <&clock 258>;
+                clocks = <&clock CLK_GSCL2>;
                clock-names = "gscl";
        };
@@ -656,7 +677,7 @@
                reg = <0x13e30000 0x1000>;
                interrupts = <0 88 0>;
                samsung,power-domain = <&pd_gsc>;
-                clocks = <&clock 259>;
+                clocks = <&clock CLK_GSCL3>;
                clock-names = "gscl";
        };
@@ -664,8 +685,9 @@
                compatible = "samsung,exynos4212-hdmi";
                reg = <0x14530000 0x70000>;
                interrupts = <0 95 0>;
-                clocks = <&clock 344>, <&clock 136>, <&clock 137>,
+                clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
-                                <&clock 159>, <&clock 1024>;
+                         <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
+                         <&clock CLK_MOUT_HDMI>;
                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
                                "sclk_hdmiphy", "mout_hdmi";
        };
@@ -674,7 +696,7 @@
                compatible = "samsung,exynos5250-mixer";
                reg = <0x14450000 0x10000>;
                interrupts = <0 94 0>;
-                clocks = <&clock 343>, <&clock 136>;
+                clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
                clock-names = "mixer", "sclk_hdmi";
        };
@@ -685,14 +707,14 @@
        };
        dp-controller@145B0000 {
-                clocks = <&clock 342>;
+                clocks = <&clock CLK_DP>;
                clock-names = "dp";
                phys = <&dp_phy>;
                phy-names = "dp";
        };
        fimd@14400000 {
-                clocks = <&clock 133>, <&clock 339>;
+                clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
                clock-names = "sclk_fimd", "fimd";
        };
@@ -700,10 +722,18 @@
                compatible = "samsung,exynos-adc-v1";
                reg = <0x12D10000 0x100>, <0x10040718 0x4>;
                interrupts = <0 106 0>;
-                clocks = <&clock 303>;
+                clocks = <&clock CLK_ADC>;
                clock-names = "adc";
                #io-channel-cells = <1>;
                io-channel-ranges;
                status = "disabled";
        };
+        sss@10830000 {
+                compatible = "samsung,exynos4210-secss";
+                reg = <0x10830000 0x10000>;
+                interrupts = <0 112 0>;
+                clocks = <&clock 348>;
+                clock-names = "secss";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 7340745ff979..80a3bf4c5986 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -11,10 +11,12 @@
 /dts-v1/;
 #include "exynos5420.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
 / {
        model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
-        compatible = "insignal,arndale-octa", "samsung,exynos5420";
+        compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
        memory {
                reg = <0x20000000 0x80000000>;
@@ -31,6 +33,10 @@
                };
        };
+        rtc@101E0000 {
+                status = "okay";
+        };
        mmc@12200000 {
                status = "okay";
                broken-cd;
@@ -41,6 +47,7 @@
                samsung,dw-mshc-ddr-timing = <0 2>;
                pinctrl-names = "default";
                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+                vmmc-supply = <&ldo10_reg>;
                slot@0 {
                        reg = <0>;
@@ -57,10 +64,316 @@
                samsung,dw-mshc-ddr-timing = <1 2>;
                pinctrl-names = "default";
                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                vmmc-supply = <&ldo10_reg>;
                slot@0 {
                        reg = <0>;
                        bus-width = <4>;
                };
        };
+        hsi2c_4: i2c@12CA0000 {
+                status = "okay";
+                s2mps11_pmic@66 {
+                        compatible = "samsung,s2mps11-pmic";
+                        reg = <0x66>;
+                        s2mps11,buck2-ramp-delay = <12>;
+                        s2mps11,buck34-ramp-delay = <12>;
+                        s2mps11,buck16-ramp-delay = <12>;
+                        s2mps11,buck6-ramp-enable = <1>;
+                        s2mps11,buck2-ramp-enable = <1>;
+                        s2mps11,buck3-ramp-enable = <1>;
+                        s2mps11,buck4-ramp-enable = <1>;
+                        interrupt-parent = <&gpx3>;
+                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+                        s2mps11_osc: clocks {
+                                #clock-cells = <1>;
+                                clock-output-names = "s2mps11_ap",
+                                                "s2mps11_cp", "s2mps11_bt";
+                        };
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "PVDD_ALIVE_1V0";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "PVDD_APIO_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "PVDD_APIO_MMCON_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "PVDD_ADC_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "PVDD_PLL_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "PVDD_ANAIP_1V0";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                };
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "PVDD_ANAIP_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "PVDD_ABB_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "PVDD_USB_3V3";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "PVDD_PRE_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "PVDD_USB_1V0";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "PVDD_HSIC_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "PVDD_APIO_MMCOFF_2V8";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "PVDD_PERI_2V8";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "PVDD_PERI_3V3";
+                                        regulator-min-microvolt = <2200000>;
+                                        regulator-max-microvolt = <2200000>;
+                                };
+                                ldo18_reg: LDO18 {
+                                        regulator-name = "PVDD_EMMC_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo19_reg: LDO19 {
+                                        regulator-name = "PVDD_TFLASH_2V8";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo20_reg: LDO20 {
+                                        regulator-name = "PVDD_BTWIFI_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "PVDD_CAM1IO_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo23_reg: LDO23 {
+                                        regulator-name = "PVDD_MIFS_1V1";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                ldo24_reg: LDO24 {
+                                        regulator-name = "PVDD_CAM1_AVDD_2V8";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo26_reg: LDO26 {
+                                        regulator-name = "PVDD_CAM0_AF_2V8";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                };
+                                ldo27_reg: LDO27 {
+                                        regulator-name = "PVDD_G3DS_1V0";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                ldo28_reg: LDO28 {
+                                        regulator-name = "PVDD_TSP_3V3";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                ldo29_reg: LDO29 {
+                                        regulator-name = "PVDD_AUDIO_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo31_reg: LDO31 {
+                                        regulator-name = "PVDD_PERI_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo32_reg: LDO32 {
+                                        regulator-name = "PVDD_LCD_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo33_reg: LDO33 {
+                                        regulator-name = "PVDD_CAM0IO_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo35_reg: LDO35 {
+                                        regulator-name = "PVDD_CAM0_DVDD_1V2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                ldo38_reg: LDO38 {
+                                        regulator-name = "PVDD_CAM0_AVDD_2V8";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "PVDD_MIF_1V1";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "PVDD_INT_1V0";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "PVDD_G3D_1V0";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1000000>;
+                                };
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "PVDD_LPDDR3_1V2";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "PVDD_KFC_1V0";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "VIN_LLDO_1V4";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        regulator-always-on;
+                                };
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "VIN_MLDO_2V0";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        regulator-always-on;
+                                };
+                                buck9_reg: BUCK9 {
+                                        regulator-name = "VIN_HLDO_3V5";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3500000>;
+                                        regulator-always-on;
+                                };
+                                buck10_reg: BUCK10 {
+                                        regulator-name = "PVDD_EMMCF_2V8";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                        };
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                wakeup {
+                        label = "SW-TACT1";
+                        gpios = <&gpx2 7 1>;
+                        linux,code = <KEY_WAKEUP>;
+                        gpio-key,wakeup;
+                };
+        };
+        amba {
+                mdma1: mdma@11C10000 {
+                        /*
+                         * MDMA1 can support both secure and non-secure
+                         * AXI transactions. When this is enabled in the kernel
+                         * for boards that run in secure mode, we are getting
+                         * imprecise external aborts causing the kernel to oops.
+                         */
+                        status = "disabled";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index fb5a1e25c632..69104850eb5e 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -14,7 +14,7 @@
 / {
        model = "Samsung SMDK5420 board based on EXYNOS5420";
-        compatible = "samsung,smdk5420", "samsung,exynos5420";
+        compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5";
        memory {
                reg = <0x20000000 0x80000000>;
@@ -31,6 +31,43 @@
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd: fixed-regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd-supply";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+                dbvdd: fixed-regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "dbvdd-supply";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                spkvdd: fixed-regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "spkvdd-supply";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
+        rtc@101E0000 {
+                status = "okay";
+        };
        mmc@12200000 {
                status = "okay";
                broken-cd;
@@ -120,4 +157,220 @@
                        reg = <0x50>;
                };
        };
+        hsi2c_4: i2c@12CA0000 {
+                status = "okay";
+                s2mps11_pmic@66 {
+                        compatible = "samsung,s2mps11-pmic";
+                        reg = <0x66>;
+                        s2mps11,buck2-ramp-delay = <12>;
+                        s2mps11,buck34-ramp-delay = <12>;
+                        s2mps11,buck16-ramp-delay = <12>;
+                        s2mps11,buck6-ramp-enable = <1>;
+                        s2mps11,buck2-ramp-enable = <1>;
+                        s2mps11,buck3-ramp-enable = <1>;
+                        s2mps11,buck4-ramp-enable = <1>;
+                        s2mps11_osc: clocks {
+                                #clock-cells = <1>;
+                                clock-output-names = "s2mps11_ap",
+                                                "s2mps11_cp", "s2mps11_bt";
+                        };
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "vdd_ldo1";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "vdd_ldo3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "vdd_ldo5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "vdd_ldo6";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "vdd_ldo7";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "vdd_ldo8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "vdd_ldo9";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "vdd_ldo10";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "vdd_ldo11";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "vdd_ldo12";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "vdd_ldo13";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "vdd_ldo15";
+                                        regulator-min-microvolt = <3100000>;
+                                        regulator-max-microvolt = <3100000>;
+                                        regulator-always-on;
+                                };
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "vdd_ldo16";
+                                        regulator-min-microvolt = <2200000>;
+                                        regulator-max-microvolt = <2200000>;
+                                        regulator-always-on;
+                                };
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "tsp_avdd";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                ldo19_reg: LDO19 {
+                                        regulator-name = "vdd_sd";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                                ldo24_reg: LDO24 {
+                                        regulator-name = "tsp_io";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "vdd_mem";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "vdd_kfc";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "vdd_1.0v_ldo";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "vdd_1.8v_ldo";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck9_reg: BUCK9 {
+                                        regulator-name = "vdd_2.8v_ldo";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3750000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                buck10_reg: BUCK10 {
+                                        regulator-name = "vdd_vmem";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8db792b26f79..c3a9a66c5767 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -13,13 +13,14 @@
 * published by the Free Software Foundation.
 */
+#include <dt-bindings/clock/exynos5420.h>
 #include "exynos5.dtsi"
 #include "exynos5420-pinctrl.dtsi"
-#include <dt-bindings/clk/exynos-audss-clk.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
 / {
-        compatible = "samsung,exynos5420";
+        compatible = "samsung,exynos5420", "samsung,exynos5";
        aliases {
                mshc0 = &mmc_0;
@@ -119,7 +120,8 @@
                compatible = "samsung,exynos5420-audss-clock";
                reg = <0x03810000 0x0C>;
                #clock-cells = <1>;
-                clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+                         <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
                clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
        };
@@ -127,7 +129,7 @@
                compatible = "samsung,mfc-v7";
                reg = <0x11000000 0x10000>;
                interrupts = <0 96 0>;
-                clocks = <&clock 401>;
+                clocks = <&clock CLK_MFC>;
                clock-names = "mfc";
        };
@@ -137,7 +139,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0x12200000 0x2000>;
-                clocks = <&clock 351>, <&clock 132>;
+                clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x40>;
                status = "disabled";
@@ -149,7 +151,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0x12210000 0x2000>;
-                clocks = <&clock 352>, <&clock 133>;
+                clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x40>;
                status = "disabled";
@@ -161,7 +163,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0x12220000 0x1000>;
-                clocks = <&clock 353>, <&clock 134>;
+                clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x40>;
                status = "disabled";
@@ -175,7 +177,7 @@
                interrupt-parent = <&mct_map>;
                interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
                                <8>, <9>, <10>, <11>;
-                clocks = <&clock 1>, <&clock 315>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
                clock-names = "fin_pll", "mct";
                mct_map: mct-map {
@@ -269,9 +271,9 @@
        };
        rtc@101E0000 {
-                clocks = <&clock 317>;
+                clocks = <&clock CLK_RTC>;
                clock-names = "rtc";
-                status = "okay";
+                status = "disabled";
        };
        amba {
@@ -281,11 +283,22 @@
                interrupt-parent = <&gic>;
                ranges;
+                adma: adma@03880000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x03880000 0x1000>;
+                        interrupts = <0 110 0>;
+                        clocks = <&clock_audss EXYNOS_ADMA>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                        #dma-channels = <6>;
+                        #dma-requests = <16>;
+                };
                pdma0: pdma@121A0000 {
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x121A0000 0x1000>;
                        interrupts = <0 34 0>;
-                        clocks = <&clock 362>;
+                        clocks = <&clock CLK_PDMA0>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -296,7 +309,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x121B0000 0x1000>;
                        interrupts = <0 35 0>;
-                        clocks = <&clock 363>;
+                        clocks = <&clock CLK_PDMA1>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -307,7 +320,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x10800000 0x1000>;
                        interrupts = <0 33 0>;
-                        clocks = <&clock 473>;
+                        clocks = <&clock CLK_MDMA0>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -318,7 +331,7 @@
                        compatible = "arm,pl330", "arm,primecell";
                        reg = <0x11C10000 0x1000>;
                        interrupts = <0 124 0>;
-                        clocks = <&clock 442>;
+                        clocks = <&clock CLK_MDMA1>;
                        clock-names = "apb_pclk";
                        #dma-cells = <1>;
                        #dma-channels = <8>;
@@ -326,6 +339,49 @@
                };
        };
+        i2s0: i2s@03830000 {
+                compatible = "samsung,exynos5420-i2s";
+                reg = <0x03830000 0x100>;
+                dmas = <&adma 0
+                        &adma 2
+                        &adma 1>;
+                dma-names = "tx", "rx", "tx-sec";
+                clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                        <&clock_audss EXYNOS_I2S_BUS>,
+                        <&clock_audss EXYNOS_SCLK_I2S>;
+                clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+                samsung,idma-addr = <0x03000000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s0_bus>;
+                status = "disabled";
+        };
+        i2s1: i2s@12D60000 {
+                compatible = "samsung,exynos5420-i2s";
+                reg = <0x12D60000 0x100>;
+                dmas = <&pdma1 12
+                        &pdma1 11>;
+                dma-names = "tx", "rx";
+                clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
+                clock-names = "iis", "i2s_opclk0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s1_bus>;
+                status = "disabled";
+        };
+        i2s2: i2s@12D70000 {
+                compatible = "samsung,exynos5420-i2s";
+                reg = <0x12D70000 0x100>;
+                dmas = <&pdma0 12
+                        &pdma0 11>;
+                dma-names = "tx", "rx";
+                clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
+                clock-names = "iis", "i2s_opclk0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s2_bus>;
+                status = "disabled";
+        };
        spi_0: spi@12d20000 {
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d20000 0x100>;
@@ -337,7 +393,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi0_bus>;
-                clocks = <&clock 271>, <&clock 135>;
+                clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
                clock-names = "spi", "spi_busclk0";
                status = "disabled";
        };
@@ -353,7 +409,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi1_bus>;
-                clocks = <&clock 272>, <&clock 136>;
+                clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
                clock-names = "spi", "spi_busclk0";
                status = "disabled";
        };
@@ -369,28 +425,28 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&spi2_bus>;
-                clocks = <&clock 273>, <&clock 137>;
+                clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
                clock-names = "spi", "spi_busclk0";
                status = "disabled";
        };
        serial@12C00000 {
-                clocks = <&clock 257>, <&clock 128>;
+                clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
                clock-names = "uart", "clk_uart_baud0";
        };
        serial@12C10000 {
-                clocks = <&clock 258>, <&clock 129>;
+                clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
                clock-names = "uart", "clk_uart_baud0";
        };
        serial@12C20000 {
-                clocks = <&clock 259>, <&clock 130>;
+                clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
                clock-names = "uart", "clk_uart_baud0";
        };
        serial@12C30000 {
-                clocks = <&clock 260>, <&clock 131>;
+                clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
                clock-names = "uart", "clk_uart_baud0";
        };
@@ -399,7 +455,7 @@
                reg = <0x12dd0000 0x100>;
                samsung,pwm-outputs = <0>, <1>, <2>, <3>;
                #pwm-cells = <3>;
-                clocks = <&clock 279>;
+                clocks = <&clock CLK_PWM>;
                clock-names = "timers";
        };
@@ -410,7 +466,7 @@
        };
        dp-controller@145B0000 {
-                clocks = <&clock 412>;
+                clocks = <&clock CLK_DP1>;
                clock-names = "dp";
                phys = <&dp_phy>;
                phy-names = "dp";
@@ -418,7 +474,7 @@
        fimd@14400000 {
                samsung,power-domain = <&disp_pd>;
-                clocks = <&clock 147>, <&clock 421>;
+                clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
                clock-names = "sclk_fimd", "fimd";
        };
@@ -426,7 +482,7 @@
                compatible = "samsung,exynos-adc-v2";
                reg = <0x12D10000 0x100>, <0x10040720 0x4>;
                interrupts = <0 106 0>;
-                clocks = <&clock 270>;
+                clocks = <&clock CLK_TSADC>;
                clock-names = "adc";
                #io-channel-cells = <1>;
                io-channel-ranges;
@@ -439,7 +495,7 @@
                interrupts = <0 56 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 261>;
+                clocks = <&clock CLK_I2C0>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c0_bus>;
@@ -452,7 +508,7 @@
                interrupts = <0 57 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 262>;
+                clocks = <&clock CLK_I2C1>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c1_bus>;
@@ -465,7 +521,7 @@
                interrupts = <0 58 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 263>;
+                clocks = <&clock CLK_I2C2>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c2_bus>;
@@ -478,7 +534,7 @@
                interrupts = <0 59 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 264>;
+                clocks = <&clock CLK_I2C3>;
                clock-names = "i2c";
                pinctrl-names = "default";
                pinctrl-0 = <&i2c3_bus>;
@@ -493,7 +549,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c4_hs_bus>;
-                clocks = <&clock 265>;
+                clocks = <&clock CLK_I2C4>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -506,7 +562,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c5_hs_bus>;
-                clocks = <&clock 266>;
+                clocks = <&clock CLK_I2C5>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -519,7 +575,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c6_hs_bus>;
-                clocks = <&clock 267>;
+                clocks = <&clock CLK_I2C6>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -532,7 +588,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c7_hs_bus>;
-                clocks = <&clock 268>;
+                clocks = <&clock CLK_I2C7>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -545,7 +601,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c8_hs_bus>;
-                clocks = <&clock 281>;
+                clocks = <&clock CLK_I2C8>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -558,7 +614,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c9_hs_bus>;
-                clocks = <&clock 282>;
+                clocks = <&clock CLK_I2C9>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -571,7 +627,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c10_hs_bus>;
-                clocks = <&clock 283>;
+                clocks = <&clock CLK_I2C10>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -580,8 +636,9 @@
                compatible = "samsung,exynos4212-hdmi";
                reg = <0x14530000 0x70000>;
                interrupts = <0 95 0>;
-                clocks = <&clock 413>, <&clock 143>, <&clock 768>,
+                clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
-                        <&clock 158>, <&clock 640>;
+                         <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
+                         <&clock CLK_MOUT_HDMI>;
                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
                        "sclk_hdmiphy", "mout_hdmi";
                status = "disabled";
@@ -591,7 +648,7 @@
                compatible = "samsung,exynos5420-mixer";
                reg = <0x14450000 0x10000>;
                interrupts = <0 94 0>;
-                clocks = <&clock 431>, <&clock 143>;
+                clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
                clock-names = "mixer", "sclk_hdmi";
        };
@@ -599,7 +656,7 @@
                compatible = "samsung,exynos5-gsc";
                reg = <0x13e00000 0x1000>;
                interrupts = <0 85 0>;
-                clocks = <&clock 465>;
+                clocks = <&clock CLK_GSCL0>;
                clock-names = "gscl";
                samsung,power-domain = <&gsc_pd>;
        };
@@ -608,16 +665,21 @@
                compatible = "samsung,exynos5-gsc";
                reg = <0x13e10000 0x1000>;
                interrupts = <0 86 0>;
-                clocks = <&clock 466>;
+                clocks = <&clock CLK_GSCL1>;
                clock-names = "gscl";
                samsung,power-domain = <&gsc_pd>;
        };
+        pmu_system_controller: system-controller@10040000 {
+                compatible = "samsung,exynos5420-pmu", "syscon";
+                reg = <0x10040000 0x5000>;
+        };
        tmu_cpu0: tmu@10060000 {
                compatible = "samsung,exynos5420-tmu";
                reg = <0x10060000 0x100>;
                interrupts = <0 65 0>;
-                clocks = <&clock 318>;
+                clocks = <&clock CLK_TMU>;
                clock-names = "tmu_apbif";
        };
@@ -625,7 +687,7 @@
                compatible = "samsung,exynos5420-tmu";
                reg = <0x10064000 0x100>;
                interrupts = <0 183 0>;
-                clocks = <&clock 318>;
+                clocks = <&clock CLK_TMU>;
                clock-names = "tmu_apbif";
        };
@@ -633,7 +695,7 @@
                compatible = "samsung,exynos5420-tmu-ext-triminfo";
                reg = <0x10068000 0x100>, <0x1006c000 0x4>;
                interrupts = <0 184 0>;
-                clocks = <&clock 318>, <&clock 318>;
+                clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
        };
@@ -641,7 +703,7 @@
                compatible = "samsung,exynos5420-tmu-ext-triminfo";
                reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
                interrupts = <0 185 0>;
-                clocks = <&clock 318>, <&clock 319>;
+                clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
        };
@@ -649,7 +711,25 @@
                compatible = "samsung,exynos5420-tmu-ext-triminfo";
                reg = <0x100a0000 0x100>, <0x10068000 0x4>;
                interrupts = <0 215 0>;
-                clocks = <&clock 319>, <&clock 318>;
+                clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
        };
+        watchdog@101D0000 {
+                compatible = "samsung,exynos5420-wdt";
+                reg = <0x101D0000 0x100>;
+                interrupts = <0 42 0>;
+                clocks = <&clock CLK_WDT>;
+                clock-names = "watchdog";
+                samsung,syscon-phandle = <&pmu_system_controller>;
+        };
+        sss@10830000 {
+                compatible = "samsung,exynos4210-secss";
+                reg = <0x10830000 0x10000>;
+                interrupts = <0 112 0>;
+                clocks = <&clock 471>;
+                clock-names = "secss";
+                samsung,power-domain = <&g2d_pd>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index 777fb1c2c70f..268609a42b2c 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -14,7 +14,7 @@
 / {
        model = "SAMSUNG SD5v1 board based on EXYNOS5440";
-        compatible = "samsung,sd5v1", "samsung,exynos5440";
+        compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5";
        chosen {
                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d58cb787061a..ff55dac6e219 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -14,7 +14,7 @@
 / {
        model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
-        compatible = "samsung,ssdk5440", "samsung,exynos5440";
+        compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5";
        chosen {
                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 02a0a1226cef..84f77c2fe4d4 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,10 +9,11 @@
 * published by the Free Software Foundation.
 */
+#include <dt-bindings/clock/exynos5440.h>
 #include "skeleton.dtsi"
 / {
-        compatible = "samsung,exynos5440";
+        compatible = "samsung,exynos5440", "samsung,exynos5";
        interrupt-parent = <&gic>;
@@ -105,7 +106,7 @@
                compatible = "samsung,exynos4210-uart";
                reg = <0xB0000 0x1000>;
                interrupts = <0 2 0>;
-                clocks = <&clock 21>, <&clock 21>;
+                clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
                clock-names = "uart", "clk_uart_baud0";
        };
@@ -113,7 +114,7 @@
                compatible = "samsung,exynos4210-uart";
                reg = <0xC0000 0x1000>;
                interrupts = <0 3 0>;
-                clocks = <&clock 21>, <&clock 21>;
+                clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
                clock-names = "uart", "clk_uart_baud0";
        };
@@ -125,7 +126,7 @@
                #size-cells = <0>;
                samsung,spi-src-clk = <0>;
                num-cs = <1>;
-                clocks = <&clock 21>, <&clock 16>;
+                clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
                clock-names = "spi", "spi_busclk0";
        };
@@ -161,7 +162,7 @@
                interrupts = <0 5 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 21>;
+                clocks = <&clock CLK_B_125>;
                clock-names = "i2c";
        };
@@ -171,7 +172,7 @@
                interrupts = <0 6 0>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&clock 21>;
+                clocks = <&clock CLK_B_125>;
                clock-names = "i2c";
        };
@@ -179,7 +180,7 @@
                compatible = "samsung,s3c2410-wdt";
                reg = <0x110000 0x1000>;
                interrupts = <0 1 0>;
-                clocks = <&clock 21>;
+                clocks = <&clock CLK_B_125>;
                clock-names = "watchdog";
        };
@@ -190,7 +191,7 @@
                interrupts = <0 31 4>;
                interrupt-names = "macirq";
                phy-mode = "sgmii";
-                clocks = <&clock 25>;
+                clocks = <&clock CLK_GMAC0>;
                clock-names = "stmmaceth";
        };
@@ -206,7 +207,7 @@
                compatible = "samsung,s3c6410-rtc";
                reg = <0x130000 0x1000>;
                interrupts = <0 17 0>, <0 16 0>;
-                clocks = <&clock 21>;
+                clocks = <&clock CLK_B_125>;
                clock-names = "rtc";
        };
@@ -214,7 +215,7 @@
                compatible = "samsung,exynos5440-tmu";
                reg = <0x160118 0x230>, <0x160368 0x10>;
                interrupts = <0 58 0>;
-                clocks = <&clock 21>;
+                clocks = <&clock CLK_B_125>;
                clock-names = "tmu_apbif";
        };
@@ -222,7 +223,7 @@
                compatible = "samsung,exynos5440-tmu";
                reg = <0x16011C 0x230>, <0x160368 0x10>;
                interrupts = <0 58 0>;
-                clocks = <&clock 21>;
+                clocks = <&clock CLK_B_125>;
                clock-names = "tmu_apbif";
        };
@@ -230,7 +231,7 @@
                compatible = "samsung,exynos5440-tmu";
                reg = <0x160120 0x230>, <0x160368 0x10>;
                interrupts = <0 58 0>;
-                clocks = <&clock 21>;
+                clocks = <&clock CLK_B_125>;
                clock-names = "tmu_apbif";
        };
@@ -238,7 +239,7 @@
                compatible = "snps,exynos5440-ahci";
                reg = <0x210000 0x10000>;
                interrupts = <0 30 0>;
-                clocks = <&clock 23>;
+                clocks = <&clock CLK_SATA>;
                clock-names = "sata";
        };
@@ -246,7 +247,7 @@
                compatible = "samsung,exynos5440-ohci";
                reg = <0x220000 0x1000>;
                interrupts = <0 29 0>;
-                clocks = <&clock 24>;
+                clocks = <&clock CLK_USB>;
                clock-names = "usbhost";
        };
@@ -254,7 +255,7 @@
                compatible = "samsung,exynos5440-ehci";
                reg = <0x221000 0x1000>;
                interrupts = <0 29 0>;
-                clocks = <&clock 24>;
+                clocks = <&clock CLK_USB>;
                clock-names = "usbhost";
        };
@@ -264,7 +265,7 @@
                        0x270000 0x1000
                        0x271000 0x40>;
                interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
-                clocks = <&clock 28>, <&clock 27>;
+                clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
                clock-names = "pcie", "pcie_bus";
                #address-cells = <3>;
                #size-cells = <2>;
@@ -285,7 +286,7 @@
                        0x272000 0x1000
                        0x271040 0x40>;
                interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
-                clocks = <&clock 29>, <&clock 27>;
+                clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
                clock-names = "pcie", "pcie_bus";
                #address-cells = <3>;
                #size-cells = <2>;
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 1f026adefd45..a33f66c11b73 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -127,17 +127,21 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_vddio_sd0: vddio-sd0 {
+                reg_vddio_sd0: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "vddio-sd0";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        gpio = <&gpio1 29 0>;
                };
-                reg_lcd_3v3: lcd-3v3 {
+                reg_lcd_3v3: regulator@1 {
                        compatible = "regulator-fixed";
+                        reg = <1>;
                        regulator-name = "lcd-3v3";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 526bfdbd87f9..7e6eef2488e8 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -100,9 +100,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb0_vbus: usb0_vbus {
+                reg_usb0_vbus: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "usb0_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index cb64e2b191ea..455169e99d49 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -66,9 +66,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_vddio_sd0: vddio-sd0 {
+                reg_vddio_sd0: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "vddio-sd0";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 581b75433be6..bbcfb5a19c77 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,6 +23,7 @@
                serial1 = &auart1;
                spi0 = &ssp0;
                spi1 = &ssp1;
+                usbphy0 = &usbphy0;
        };
        cpus {
@@ -428,7 +429,7 @@
                                status = "disabled";
                        };
-                        lradc@80050000 {
+                        lradc: lradc@80050000 {
                                compatible = "fsl,imx23-lradc";
                                reg = <0x80050000 0x2000>;
                                interrupts = <36 37 38 39 40 41 42 43 44>;
@@ -526,4 +527,9 @@
                        status = "disabled";
                };
        };
+        iio_hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&lradc 8>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
new file mode 100644
index 000000000000..d6f27641c0ef
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include "imx25.dtsi"
+/ {
+        model = "Eukrea CPUIMX25";
+        compatible = "eukrea,cpuimx25", "fsl,imx25";
+        memory {
+                reg = <0x80000000 0x4000000>; /* 64M */
+        };
+};
+&fec {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        status = "okay";
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        pcf8563@51 {
+                compatible = "nxp,pcf8563";
+                reg = <0x51>;
+        };
+};
+&iomuxc {
+        imx25-eukrea-cpuimx25 {
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX25_PAD_FEC_MDC__FEC_MDC               0x80000000
+                                MX25_PAD_FEC_MDIO__FEC_MDIO             0x400001e0
+                                MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x80000000
+                                MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x80000000
+                                MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                                MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x80000000
+                                MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x80000000
+                                MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x80000000
+                                MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1c0
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX25_PAD_I2C1_CLK__I2C1_CLK             0x80000000
+                                MX25_PAD_I2C1_DAT__I2C1_DAT             0x80000000
+                        >;
+                };
+        };
+};
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
new file mode 100644
index 000000000000..62fb3da50bdb
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx25-eukrea-cpuimx25.dtsi"
+/ {
+        model = "Eukrea MBIMXSD25";
+        compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpiokeys>;
+                bp1 {
+                        label = "BP1";
+                        gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+                        linux,code = <BTN_MISC>;
+                        gpio-key,wakeup;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpioled>;
+                led1 {
+                        label = "led1";
+                        gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        sound {
+                compatible = "eukrea,asoc-tlv320";
+                eukrea,model = "imx25-eukrea-tlv320aic23";
+                ssi-controller = <&ssi1>;
+                fsl,mux-int-port = <1>;
+                fsl,mux-ext-port = <5>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        cd-gpios = <&gpio1 20>;
+        status = "okay";
+};
+&i2c1 {
+        tlv320aic23: codec@1a {
+                compatible = "ti,tlv320aic23";
+                reg = <0x1a>;
+        };
+};
+&iomuxc {
+        imx25-eukrea-mbimxsd25-baseboard {
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX25_PAD_KPP_COL3__AUD5_TXFS            0xe0
+                                MX25_PAD_KPP_COL2__AUD5_TXC             0xe0
+                                MX25_PAD_KPP_COL1__AUD5_RXD             0xe0
+                                MX25_PAD_KPP_COL0__AUD5_TXD             0xe0
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX25_PAD_SD1_CMD__SD1_CMD               0x400000c0
+                                MX25_PAD_SD1_CLK__SD1_CLK               0x400000c0
+                                MX25_PAD_SD1_DATA0__SD1_DATA0           0x400000c0
+                                MX25_PAD_SD1_DATA1__SD1_DATA1           0x400000c0
+                                MX25_PAD_SD1_DATA2__SD1_DATA2           0x400000c0
+                                MX25_PAD_SD1_DATA3__SD1_DATA3           0x400000c0
+                        >;
+                };
+                pinctrl_gpiokeys: gpiokeysgrp {
+                        fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
+                };
+                pinctrl_gpioled: gpioledgrp {
+                        fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
+                };
+                pinctrl_lcdc: lcdcgrp {
+                        fsl,pins = <
+                                MX25_PAD_LD0__LD0                       0x1
+                                MX25_PAD_LD1__LD1                       0x1
+                                MX25_PAD_LD2__LD2                       0x1
+                                MX25_PAD_LD3__LD3                       0x1
+                                MX25_PAD_LD4__LD4                       0x1
+                                MX25_PAD_LD5__LD5                       0x1
+                                MX25_PAD_LD6__LD6                       0x1
+                                MX25_PAD_LD7__LD7                       0x1
+                                MX25_PAD_LD8__LD8                       0x1
+                                MX25_PAD_LD9__LD9                       0x1
+                                MX25_PAD_LD10__LD10                     0x1
+                                MX25_PAD_LD11__LD11                     0x1
+                                MX25_PAD_LD12__LD12                     0x1
+                                MX25_PAD_LD13__LD13                     0x1
+                                MX25_PAD_LD14__LD14                     0x1
+                                MX25_PAD_LD15__LD15                     0x1
+                                MX25_PAD_GPIO_E__LD16                   0x1
+                                MX25_PAD_GPIO_F__LD17                   0x1
+                                MX25_PAD_HSYNC__HSYNC                   0x80000000
+                                MX25_PAD_VSYNC__VSYNC                   0x80000000
+                                MX25_PAD_LSCLK__LSCLK                   0x80000000
+                                MX25_PAD_OE_ACD__OE_ACD                 0x80000000
+                                MX25_PAD_CONTRAST__CONTRAST             0x80000000
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX25_PAD_UART1_RTS__UART1_RTS           0xe0
+                                MX25_PAD_UART1_CTS__UART1_CTS           0xe0
+                                MX25_PAD_UART1_TXD__UART1_TXD           0x80000000
+                                MX25_PAD_UART1_RXD__UART1_RXD           0xc0
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX25_PAD_UART2_RXD__UART2_RXD           0x80000000
+                                MX25_PAD_UART2_TXD__UART2_TXD           0x80000000
+                                MX25_PAD_UART2_RTS__UART2_RTS           0x80000000
+                                MX25_PAD_UART2_CTS__UART2_CTS           0x80000000
+                        >;
+                };
+        };
+};
+&ssi1 {
+        codec-handle = <&tlv320aic23>;
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
new file mode 100644
index 000000000000..9238a95d8e62
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -0,0 +1,494 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ * Based on imx35-pinfunc.h in the same directory Which is:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __DTS_IMX25_PINFUNC_H
+#define __DTS_IMX25_PINFUNC_H
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX25_PAD_A10__A10                       0x008 0x000 0x000 0x00 0x000
+#define MX25_PAD_A10__GPIO_4_0                  0x008 0x000 0x000 0x05 0x000
+#define MX25_PAD_A13__A13                       0x00c 0x22C 0x000 0x00 0x000
+#define MX25_PAD_A13__GPIO_4_1                  0x00c 0x22C 0x000 0x05 0x000
+#define MX25_PAD_A14__A14                       0x010 0x230 0x000 0x10 0x000
+#define MX25_PAD_A14__GPIO_2_0                  0x010 0x230 0x000 0x15 0x000
+#define MX25_PAD_A15__A15                       0x014 0x234 0x000 0x10 0x000
+#define MX25_PAD_A15__GPIO_2_1                  0x014 0x234 0x000 0x15 0x000
+#define MX25_PAD_A16__A16                       0x018 0x000 0x000 0x10 0x000
+#define MX25_PAD_A16__GPIO_2_2                  0x018 0x000 0x000 0x15 0x000
+#define MX25_PAD_A17__A17                       0x01c 0x238 0x000 0x10 0x000
+#define MX25_PAD_A17__GPIO_2_3                  0x01c 0x238 0x000 0x15 0x000
+#define MX25_PAD_A18__A18                       0x020 0x23c 0x000 0x10 0x000
+#define MX25_PAD_A18__GPIO_2_4                  0x020 0x23c 0x000 0x15 0x000
+#define MX25_PAD_A18__FEC_COL                   0x020 0x23c 0x504 0x17 0x000
+#define MX25_PAD_A19__A19                       0x024 0x240 0x000 0x10 0x000
+#define MX25_PAD_A19__FEC_RX_ER                 0x024 0x240 0x518 0x17 0x000
+#define MX25_PAD_A19__GPIO_2_5                  0x024 0x240 0x000 0x15 0x000
+#define MX25_PAD_A20__A20                       0x028 0x244 0x000 0x10 0x000
+#define MX25_PAD_A20__GPIO_2_6                  0x028 0x244 0x000 0x15 0x000
+#define MX25_PAD_A20__FEC_RDATA2                0x028 0x244 0x50c 0x17 0x000
+#define MX25_PAD_A21__A21                       0x02c 0x248 0x000 0x10 0x000
+#define MX25_PAD_A21__GPIO_2_7                  0x02c 0x248 0x000 0x15 0x000
+#define MX25_PAD_A21__FEC_RDATA3                0x02c 0x248 0x510 0x17 0x000
+#define MX25_PAD_A22__A22                       0x030 0x000 0x000 0x10 0x000
+#define MX25_PAD_A22__GPIO_2_8                  0x030 0x000 0x000 0x15 0x000
+#define MX25_PAD_A23__A23                       0x034 0x24c 0x000 0x10 0x000
+#define MX25_PAD_A23__GPIO_2_9                  0x034 0x24c 0x000 0x15 0x000
+#define MX25_PAD_A24__A24                       0x038 0x250 0x000 0x10 0x000
+#define MX25_PAD_A24__GPIO_2_10                 0x038 0x250 0x000 0x15 0x000
+#define MX25_PAD_A24__FEC_RX_CLK                0x038 0x250 0x514 0x17 0x000
+#define MX25_PAD_A25__A25                       0x03c 0x254 0x000 0x10 0x000
+#define MX25_PAD_A25__GPIO_2_11                 0x03c 0x254 0x000 0x15 0x000
+#define MX25_PAD_A25__FEC_CRS                   0x03c 0x254 0x508 0x17 0x000
+#define MX25_PAD_EB0__EB0                       0x040 0x258 0x000 0x10 0x000
+#define MX25_PAD_EB0__AUD4_TXD                  0x040 0x258 0x464 0x14 0x000
+#define MX25_PAD_EB0__GPIO_2_12                 0x040 0x258 0x000 0x15 0x000
+#define MX25_PAD_EB1__EB1                       0x044 0x25c 0x000 0x10 0x000
+#define MX25_PAD_EB1__AUD4_RXD                  0x044 0x25c 0x460 0x14 0x000
+#define MX25_PAD_EB1__GPIO_2_13                 0x044 0x25c 0x000 0x15 0x000
+#define MX25_PAD_OE__OE                         0x048 0x260 0x000 0x10 0x000
+#define MX25_PAD_OE__AUD4_TXC                   0x048 0x260 0x000 0x14 0x000
+#define MX25_PAD_OE__GPIO_2_14                  0x048 0x260 0x000 0x15 0x000
+#define MX25_PAD_CS0__CS0                       0x04c 0x000 0x000 0x00 0x000
+#define MX25_PAD_CS0__GPIO_4_2                  0x04c 0x000 0x000 0x05 0x000
+#define MX25_PAD_CS1__CS1                       0x050 0x000 0x000 0x00 0x000
+#define MX25_PAD_CS1__NF_CE3                    0x050 0x000 0x000 0x01 0x000
+#define MX25_PAD_CS1__GPIO_4_3                  0x050 0x000 0x000 0x05 0x000
+#define MX25_PAD_CS4__CS4                       0x054 0x264 0x000 0x10 0x000
+#define MX25_PAD_CS4__NF_CE1                    0x054 0x264 0x000 0x01 0x000
+#define MX25_PAD_CS4__UART5_CTS                 0x054 0x264 0x000 0x13 0x000
+#define MX25_PAD_CS4__GPIO_3_20                 0x054 0x264 0x000 0x15 0x000
+#define MX25_PAD_CS5__CS5                       0x058 0x268 0x000 0x10 0x000
+#define MX25_PAD_CS5__NF_CE2                    0x058 0x268 0x000 0x01 0x000
+#define MX25_PAD_CS5__UART5_RTS                 0x058 0x268 0x574 0x13 0x000
+#define MX25_PAD_CS5__GPIO_3_21                 0x058 0x268 0x000 0x15 0x000
+#define MX25_PAD_NF_CE0__NF_CE0                 0x05c 0x26c 0x000 0x10 0x000
+#define MX25_PAD_NF_CE0__GPIO_3_22              0x05c 0x26c 0x000 0x15 0x000
+#define MX25_PAD_ECB__ECB                       0x060 0x270 0x000 0x10 0x000
+#define MX25_PAD_ECB__UART5_TXD_MUX             0x060 0x270 0x000 0x13 0x000
+#define MX25_PAD_ECB__GPIO_3_23                 0x060 0x270 0x000 0x15 0x000
+#define MX25_PAD_LBA__LBA                       0x064 0x274 0x000 0x10 0x000
+#define MX25_PAD_LBA__UART5_RXD_MUX             0x064 0x274 0x578 0x13 0x000
+#define MX25_PAD_LBA__GPIO_3_24                 0x064 0x274 0x000 0x15 0x000
+#define MX25_PAD_BCLK__BCLK                     0x068 0x000 0x000 0x00 0x000
+#define MX25_PAD_BCLK__GPIO_4_4                 0x068 0x000 0x000 0x05 0x000
+#define MX25_PAD_RW__RW                         0x06c 0x278 0x000 0x10 0x000
+#define MX25_PAD_RW__AUD4_TXFS                  0x06c 0x278 0x474 0x14 0x000
+#define MX25_PAD_RW__GPIO_3_25                  0x06c 0x278 0x000 0x15 0x000
+#define MX25_PAD_NFWE_B__NFWE_B                 0x070 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFWE_B__GPIO_3_26              0x070 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFRE_B__NFRE_B                 0x074 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFRE_B__GPIO_3_27              0x074 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFALE__NFALE                   0x078 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFALE__GPIO_3_28               0x078 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFCLE__NFCLE                   0x07c 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFCLE__GPIO_3_29               0x07c 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFWP_B__NFWP_B                 0x080 0x000 0x000 0x10 0x000
+#define MX25_PAD_NFWP_B__GPIO_3_30              0x080 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFRB__NFRB                     0x084 0x27c 0x000 0x10 0x000
+#define MX25_PAD_NFRB__GPIO_3_31                0x084 0x27c 0x000 0x15 0x000
+#define MX25_PAD_D15__D15                       0x088 0x280 0x000 0x00 0x000
+#define MX25_PAD_D15__LD16                      0x088 0x280 0x000 0x01 0x000
+#define MX25_PAD_D15__GPIO_4_5                  0x088 0x280 0x000 0x05 0x000
+#define MX25_PAD_D14__D14                       0x08c 0x284 0x000 0x00 0x000
+#define MX25_PAD_D14__LD17                      0x08c 0x284 0x000 0x01 0x000
+#define MX25_PAD_D14__GPIO_4_6                  0x08c 0x284 0x000 0x05 0x000
+#define MX25_PAD_D13__D13                       0x090 0x288 0x000 0x00 0x000
+#define MX25_PAD_D13__LD18                      0x090 0x288 0x000 0x01 0x000
+#define MX25_PAD_D13__GPIO_4_7                  0x090 0x288 0x000 0x05 0x000
+#define MX25_PAD_D12__D12                       0x094 0x28c 0x000 0x00 0x000
+#define MX25_PAD_D12__GPIO_4_8                  0x094 0x28c 0x000 0x05 0x000
+#define MX25_PAD_D11__D11                       0x098 0x290 0x000 0x00 0x000
+#define MX25_PAD_D11__GPIO_4_9                  0x098 0x290 0x000 0x05 0x000
+#define MX25_PAD_D10__D10                       0x09c 0x294 0x000 0x00 0x000
+#define MX25_PAD_D10__GPIO_4_10                 0x09c 0x294 0x000 0x05 0x000
+#define MX25_PAD_D10__USBOTG_OC                 0x09c 0x294 0x57c 0x06 0x000
+#define MX25_PAD_D9__D9                         0x0a0 0x298 0x000 0x00 0x000
+#define MX25_PAD_D9__GPIO_4_11                  0x0a0 0x298 0x000 0x05 0x000
+#define MX25_PAD_D9__USBH2_PWR                  0x0a0 0x298 0x000 0x06 0x000
+#define MX25_PAD_D8__D8                         0x0a4 0x29c 0x000 0x00 0x000
+#define MX25_PAD_D8__GPIO_4_12                  0x0a4 0x29c 0x000 0x05 0x000
+#define MX25_PAD_D8__USBH2_OC                   0x0a4 0x29c 0x580 0x06 0x000
+#define MX25_PAD_D7__D7                         0x0a8 0x2a0 0x000 0x00 0x000
+#define MX25_PAD_D7__GPIO_4_13                  0x0a8 0x2a0 0x000 0x05 0x000
+#define MX25_PAD_D6__D6                         0x0ac 0x2a4 0x000 0x00 0x000
+#define MX25_PAD_D6__GPIO_4_14                  0x0ac 0x2a4 0x000 0x05 0x000
+#define MX25_PAD_D5__D5                         0x0b0 0x2a8 0x000 0x00 0x000
+#define MX25_PAD_D5__GPIO_4_15                  0x0b0 0x2a8 0x000 0x05 0x000
+#define MX25_PAD_D4__D4                         0x0b4 0x2ac 0x000 0x00 0x000
+#define MX25_PAD_D4__GPIO_4_16                  0x0b4 0x2ac 0x000 0x05 0x000
+#define MX25_PAD_D3__D3                         0x0b8 0x2b0 0x000 0x00 0x000
+#define MX25_PAD_D3__GPIO_4_17                  0x0b8 0x2b0 0x000 0x05 0x000
+#define MX25_PAD_D2__D2                         0x0bc 0x2b4 0x000 0x00 0x000
+#define MX25_PAD_D2__GPIO_4_18                  0x0bc 0x2b4 0x000 0x05 0x000
+#define MX25_PAD_D1__D1                         0x0c0 0x2b8 0x000 0x00 0x000
+#define MX25_PAD_D1__GPIO_4_19                  0x0c0 0x2b8 0x000 0x05 0x000
+#define MX25_PAD_D0__D0                         0x0c4 0x2bc 0x000 0x00 0x000
+#define MX25_PAD_D0__GPIO_4_20                  0x0c4 0x2bc 0x000 0x05 0x000
+#define MX25_PAD_LD0__LD0                       0x0c8 0x2c0 0x000 0x10 0x000
+#define MX25_PAD_LD0__CSI_D0                    0x0c8 0x2c0 0x488 0x12 0x000
+#define MX25_PAD_LD0__GPIO_2_15                 0x0c8 0x2c0 0x000 0x15 0x000
+#define MX25_PAD_LD1__LD1                       0x0cc 0x2c4 0x000 0x10 0x000
+#define MX25_PAD_LD1__CSI_D1                    0x0cc 0x2c4 0x48c 0x12 0x000
+#define MX25_PAD_LD1__GPIO_2_16                 0x0cc 0x2c4 0x000 0x15 0x000
+#define MX25_PAD_LD2__LD2                       0x0d0 0x2c8 0x000 0x10 0x000
+#define MX25_PAD_LD2__GPIO_2_17                 0x0d0 0x2c8 0x000 0x15 0x000
+#define MX25_PAD_LD3__LD3                       0x0d4 0x2cc 0x000 0x10 0x000
+#define MX25_PAD_LD3__GPIO_2_18                 0x0d4 0x2cc 0x000 0x15 0x000
+#define MX25_PAD_LD4__LD4                       0x0d8 0x2d0 0x000 0x10 0x000
+#define MX25_PAD_LD4__GPIO_2_19                 0x0d8 0x2d0 0x000 0x15 0x000
+#define MX25_PAD_LD5__LD5                       0x0dc 0x2d4 0x000 0x10 0x000
+#define MX25_PAD_LD5__GPIO_1_19                 0x0dc 0x2d4 0x000 0x15 0x000
+#define MX25_PAD_LD6__LD6                       0x0e0 0x2d8 0x000 0x10 0x000
+#define MX25_PAD_LD6__GPIO_1_20                 0x0e0 0x2d8 0x000 0x15 0x000
+#define MX25_PAD_LD7__LD7                       0x0e4 0x2dc 0x000 0x10 0x000
+#define MX25_PAD_LD7__GPIO_1_21                 0x0e4 0x2dc 0x000 0x15 0x000
+#define MX25_PAD_LD8__LD8                       0x0e8 0x2e0 0x000 0x10 0x000
+#define MX25_PAD_LD8__FEC_TX_ERR                0x0e8 0x2e0 0x000 0x15 0x000
+#define MX25_PAD_LD9__LD9                       0x0ec 0x2e4 0x000 0x10 0x000
+#define MX25_PAD_LD9__FEC_COL                   0x0ec 0x2e4 0x504 0x15 0x001
+#define MX25_PAD_LD10__LD10                     0x0f0 0x2e8 0x000 0x10 0x000
+#define MX25_PAD_LD10__FEC_RX_ER                0x0f0 0x2e8 0x518 0x15 0x001
+#define MX25_PAD_LD11__LD11                     0x0f4 0x2ec 0x000 0x10 0x000
+#define MX25_PAD_LD11__FEC_RDATA2               0x0f4 0x2ec 0x50c 0x15 0x001
+#define MX25_PAD_LD12__LD12                     0x0f8 0x2f0 0x000 0x10 0x000
+#define MX25_PAD_LD12__FEC_RDATA3               0x0f8 0x2f0 0x510 0x15 0x001
+#define MX25_PAD_LD13__LD13                     0x0fc 0x2f4 0x000 0x10 0x000
+#define MX25_PAD_LD13__FEC_TDATA2               0x0fc 0x2f4 0x000 0x15 0x000
+#define MX25_PAD_LD14__LD14                     0x100 0x2f8 0x000 0x10 0x000
+#define MX25_PAD_LD14__FEC_TDATA3               0x100 0x2f8 0x000 0x15 0x000
+#define MX25_PAD_LD15__LD15                     0x104 0x2fc 0x000 0x10 0x000
+#define MX25_PAD_LD15__FEC_RX_CLK               0x104 0x2fc 0x514 0x15 0x001
+#define MX25_PAD_HSYNC__HSYNC                   0x108 0x300 0x000 0x10 0x000
+#define MX25_PAD_HSYNC__GPIO_1_22               0x108 0x300 0x000 0x15 0x000
+#define MX25_PAD_VSYNC__VSYNC                   0x10c 0x304 0x000 0x10 0x000
+#define MX25_PAD_VSYNC__GPIO_1_23               0x10c 0x304 0x000 0x15 0x000
+#define MX25_PAD_LSCLK__LSCLK                   0x110 0x308 0x000 0x10 0x000
+#define MX25_PAD_LSCLK__GPIO_1_24               0x110 0x308 0x000 0x15 0x000
+#define MX25_PAD_OE_ACD__OE_ACD                 0x114 0x30c 0x000 0x10 0x000
+#define MX25_PAD_OE_ACD__GPIO_1_25              0x114 0x30c 0x000 0x15 0x000
+#define MX25_PAD_CONTRAST__CONTRAST             0x118 0x310 0x000 0x10 0x000
+#define MX25_PAD_CONTRAST__PWM4_PWMO            0x118 0x310 0x000 0x14 0x000
+#define MX25_PAD_CONTRAST__FEC_CRS              0x118 0x310 0x508 0x15 0x001
+#define MX25_PAD_PWM__PWM                       0x11c 0x314 0x000 0x10 0x000
+#define MX25_PAD_PWM__GPIO_1_26                 0x11c 0x314 0x000 0x15 0x000
+#define MX25_PAD_PWM__USBH2_OC                  0x11c 0x314 0x580 0x16 0x001
+#define MX25_PAD_CSI_D2__CSI_D2                 0x120 0x318 0x000 0x10 0x000
+#define MX25_PAD_CSI_D2__UART5_RXD_MUX          0x120 0x318 0x578 0x11 0x001
+#define MX25_PAD_CSI_D2__GPIO_1_27              0x120 0x318 0x000 0x15 0x000
+#define MX25_PAD_CSI_D2__CSPI3_MOSI             0x120 0x318 0x000 0x17 0x000
+#define MX25_PAD_CSI_D3__CSI_D3                 0x124 0x31c 0x000 0x10 0x000
+#define MX25_PAD_CSI_D3__GPIO_1_28              0x124 0x31c 0x000 0x15 0x000
+#define MX25_PAD_CSI_D3__CSPI3_MISO             0x124 0x31c 0x4b4 0x17 0x001
+#define MX25_PAD_CSI_D4__CSI_D4                 0x128 0x320 0x000 0x10 0x000
+#define MX25_PAD_CSI_D4__UART5_RTS              0x128 0x320 0x574 0x11 0x001
+#define MX25_PAD_CSI_D4__GPIO_1_29              0x128 0x320 0x000 0x15 0x000
+#define MX25_PAD_CSI_D4__CSPI3_SCLK             0x128 0x320 0x000 0x17 0x000
+#define MX25_PAD_CSI_D5__CSI_D5                 0x12c 0x324 0x000 0x10 0x000
+#define MX25_PAD_CSI_D5__GPIO_1_30              0x12c 0x324 0x000 0x15 0x000
+#define MX25_PAD_CSI_D5__CSPI3_RDY              0x12c 0x324 0x000 0x17 0x000
+#define MX25_PAD_CSI_D6__CSI_D6                 0x130 0x328 0x000 0x10 0x000
+#define MX25_PAD_CSI_D6__GPIO_1_31              0x130 0x328 0x000 0x15 0x000
+#define MX25_PAD_CSI_D7__CSI_D7                 0x134 0x32c 0x000 0x10 0x000
+#define MX25_PAD_CSI_D7__GPIO_1_6               0x134 0x32c 0x000 0x15 0x000
+#define MX25_PAD_CSI_D8__CSI_D8                 0x138 0x330 0x000 0x10 0x000
+#define MX25_PAD_CSI_D8__GPIO_1_7               0x138 0x330 0x000 0x15 0x000
+#define MX25_PAD_CSI_D9__CSI_D9                 0x13c 0x334 0x000 0x10 0x000
+#define MX25_PAD_CSI_D9__GPIO_4_21              0x13c 0x334 0x000 0x15 0x000
+#define MX25_PAD_CSI_MCLK__CSI_MCLK             0x140 0x338 0x000 0x10 0x000
+#define MX25_PAD_CSI_MCLK__GPIO_1_8             0x140 0x338 0x000 0x15 0x000
+#define MX25_PAD_CSI_VSYNC__CSI_VSYNC           0x144 0x33c 0x000 0x10 0x000
+#define MX25_PAD_CSI_VSYNC__GPIO_1_9            0x144 0x33c 0x000 0x15 0x000
+#define MX25_PAD_CSI_HSYNC__CSI_HSYNC           0x148 0x340 0x000 0x10 0x000
+#define MX25_PAD_CSI_HSYNC__GPIO_1_10           0x148 0x340 0x000 0x15 0x000
+#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK         0x14c 0x344 0x000 0x10 0x000
+#define MX25_PAD_CSI_PIXCLK__GPIO_1_11          0x14c 0x344 0x000 0x15 0x000
+#define MX25_PAD_I2C1_CLK__I2C1_CLK             0x150 0x348 0x000 0x10 0x000
+#define MX25_PAD_I2C1_CLK__GPIO_1_12            0x150 0x348 0x000 0x15 0x000
+#define MX25_PAD_I2C1_DAT__I2C1_DAT             0x154 0x34c 0x000 0x10 0x000
+#define MX25_PAD_I2C1_DAT__GPIO_1_13            0x154 0x34c 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI         0x158 0x350 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_MOSI__GPIO_1_14          0x158 0x350 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_MISO__CSPI1_MISO         0x15c 0x354 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_MISO__GPIO_1_15          0x15c 0x354 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_SS0__CSPI1_SS0           0x160 0x358 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SS0__GPIO_1_16           0x160 0x358 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_SS1__CSPI1_SS1           0x164 0x35c 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SS1__GPIO_1_17           0x164 0x35c 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK         0x168 0x360 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_SCLK__GPIO_1_18          0x168 0x360 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_RDY__CSPI1_RDY           0x16c 0x364 0x000 0x10 0x000
+#define MX25_PAD_CSPI1_RDY__GPIO_2_22           0x16c 0x364 0x000 0x15 0x000
+#define MX25_PAD_UART1_RXD__UART1_RXD           0x170 0x368 0x000 0x10 0x000
+#define MX25_PAD_UART1_RXD__GPIO_4_22           0x170 0x368 0x000 0x15 0x000
+#define MX25_PAD_UART1_TXD__UART1_TXD           0x174 0x36c 0x000 0x10 0x000
+#define MX25_PAD_UART1_TXD__GPIO_4_23           0x174 0x36c 0x000 0x15 0x000
+#define MX25_PAD_UART1_RTS__UART1_RTS           0x178 0x370 0x000 0x10 0x000
+#define MX25_PAD_UART1_RTS__CSI_D0              0x178 0x370 0x488 0x11 0x001
+#define MX25_PAD_UART1_RTS__GPIO_4_24           0x178 0x370 0x000 0x15 0x000
+#define MX25_PAD_UART1_CTS__UART1_CTS           0x17c 0x374 0x000 0x10 0x000
+#define MX25_PAD_UART1_CTS__CSI_D1              0x17c 0x374 0x48c 0x11 0x001
+#define MX25_PAD_UART1_CTS__GPIO_4_25           0x17c 0x374 0x000 0x15 0x000
+#define MX25_PAD_UART2_RXD__UART2_RXD           0x180 0x378 0x000 0x10 0x000
+#define MX25_PAD_UART2_RXD__GPIO_4_26           0x180 0x378 0x000 0x15 0x000
+#define MX25_PAD_UART2_TXD__UART2_TXD           0x184 0x37c 0x000 0x10 0x000
+#define MX25_PAD_UART2_TXD__GPIO_4_27           0x184 0x37c 0x000 0x15 0x000
+#define MX25_PAD_UART2_RTS__UART2_RTS           0x188 0x380 0x000 0x10 0x000
+#define MX25_PAD_UART2_RTS__FEC_COL             0x188 0x380 0x504 0x12 0x002
+#define MX25_PAD_UART2_RTS__GPIO_4_28           0x188 0x380 0x000 0x15 0x000
+#define MX25_PAD_UART2_CTS__FEC_RX_ER           0x18c 0x384 0x518 0x12 0x002
+#define MX25_PAD_UART2_CTS__UART2_CTS           0x18c 0x384 0x000 0x10 0x000
+#define MX25_PAD_UART2_CTS__GPIO_4_29           0x18c 0x384 0x000 0x15 0x000
+#define MX25_PAD_SD1_CMD__SD1_CMD               0x190 0x388 0x000 0x10 0x000
+#define MX25_PAD_SD1_CMD__FEC_RDATA2            0x190 0x388 0x50c 0x12 0x002
+#define MX25_PAD_SD1_CMD__GPIO_2_23             0x190 0x388 0x000 0x15 0x000
+#define MX25_PAD_SD1_CLK__SD1_CLK               0x194 0x38c 0x000 0x10 0x000
+#define MX25_PAD_SD1_CLK__FEC_RDATA3            0x194 0x38c 0x510 0x12 0x002
+#define MX25_PAD_SD1_CLK__GPIO_2_24             0x194 0x38c 0x000 0x15 0x000
+#define MX25_PAD_SD1_DATA0__SD1_DATA0           0x198 0x390 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA0__GPIO_2_25           0x198 0x390 0x000 0x15 0x000
+#define MX25_PAD_SD1_DATA1__SD1_DATA1           0x19c 0x394 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA1__AUD7_RXD            0x19c 0x394 0x478 0x13 0x000
+#define MX25_PAD_SD1_DATA1__GPIO_2_26           0x19c 0x394 0x000 0x15 0x000
+#define MX25_PAD_SD1_DATA2__SD1_DATA2           0x1a0 0x398 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x15 0x002
+#define MX25_PAD_SD1_DATA2__GPIO_2_27           0x1a0 0x398 0x000 0x15 0x000
+#define MX25_PAD_SD1_DATA3__SD1_DATA3           0x1a4 0x39c 0x000 0x10 0x000
+#define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x10 0x002
+#define MX25_PAD_SD1_DATA3__GPIO_2_28           0x1a4 0x39c 0x000 0x15 0x000
+#define MX25_PAD_KPP_ROW0__KPP_ROW0             0x1a8 0x3a0 0x000 0x10 0x000
+#define MX25_PAD_KPP_ROW0__GPIO_2_29            0x1a8 0x3a0 0x000 0x15 0x000
+#define MX25_PAD_KPP_ROW1__KPP_ROW1             0x1ac 0x3a4 0x000 0x10 0x000
+#define MX25_PAD_KPP_ROW1__GPIO_2_30            0x1ac 0x3a4 0x000 0x15 0x000
+#define MX25_PAD_KPP_ROW2__KPP_ROW2             0x1b0 0x3a8 0x000 0x10 0x000
+#define MX25_PAD_KPP_ROW2__CSI_D0               0x1b0 0x3a8 0x488 0x13 0x002
+#define MX25_PAD_KPP_ROW2__GPIO_2_31            0x1b0 0x3a8 0x000 0x15 0x000
+#define MX25_PAD_KPP_ROW3__KPP_ROW3             0x1b4 0x3ac 0x000 0x10 0x000
+#define MX25_PAD_KPP_ROW3__CSI_LD1              0x1b4 0x3ac 0x48c 0x13 0x002
+#define MX25_PAD_KPP_ROW3__GPIO_3_0             0x1b4 0x3ac 0x000 0x15 0x000
+#define MX25_PAD_KPP_COL0__KPP_COL0             0x1b8 0x3b0 0x000 0x10 0x000
+#define MX25_PAD_KPP_COL0__UART4_RXD_MUX        0x1b8 0x3b0 0x570 0x11 0x001
+#define MX25_PAD_KPP_COL0__AUD5_TXD             0x1b8 0x3b0 0x000 0x12 0x000
+#define MX25_PAD_KPP_COL0__GPIO_3_1             0x1b8 0x3b0 0x000 0x15 0x000
+#define MX25_PAD_KPP_COL1__KPP_COL1             0x1bc 0x3b4 0x000 0x10 0x000
+#define MX25_PAD_KPP_COL1__UART4_TXD_MUX        0x1bc 0x3b4 0x000 0x11 0x000
+#define MX25_PAD_KPP_COL1__AUD5_RXD             0x1bc 0x3b4 0x000 0x12 0x000
+#define MX25_PAD_KPP_COL1__GPIO_3_2             0x1bc 0x3b4 0x000 0x15 0x000
+#define MX25_PAD_KPP_COL2__KPP_COL2             0x1c0 0x3b8 0x000 0x10 0x000
+#define MX25_PAD_KPP_COL2__UART4_RTS            0x1c0 0x3b8 0x000 0x11 0x000
+#define MX25_PAD_KPP_COL2__AUD5_TXC             0x1c0 0x3b8 0x000 0x12 0x000
+#define MX25_PAD_KPP_COL2__GPIO_3_3             0x1c0 0x3b8 0x000 0x15 0x000
+#define MX25_PAD_KPP_COL3__KPP_COL3             0x1c4 0x3bc 0x000 0x10 0x000
+#define MX25_PAD_KPP_COL3__UART4_CTS            0x1c4 0x3bc 0x000 0x11 0x000
+#define MX25_PAD_KPP_COL3__AUD5_TXFS            0x1c4 0x3bc 0x000 0x12 0x000
+#define MX25_PAD_KPP_COL3__GPIO_3_4             0x1c4 0x3bc 0x000 0x15 0x000
+#define MX25_PAD_FEC_MDC__FEC_MDC               0x1c8 0x3c0 0x000 0x10 0x000
+#define MX25_PAD_FEC_MDC__AUD4_TXD              0x1c8 0x3c0 0x464 0x12 0x001
+#define MX25_PAD_FEC_MDC__GPIO_3_5              0x1c8 0x3c0 0x000 0x15 0x000
+#define MX25_PAD_FEC_MDIO__FEC_MDIO             0x1cc 0x3c4 0x000 0x10 0x000
+#define MX25_PAD_FEC_MDIO__AUD4_RXD             0x1cc 0x3c4 0x460 0x12 0x001
+#define MX25_PAD_FEC_MDIO__GPIO_3_6             0x1cc 0x3c4 0x000 0x15 0x000
+#define MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x1d0 0x3c8 0x000 0x10 0x000
+#define MX25_PAD_FEC_TDATA0__GPIO_3_7           0x1d0 0x3c8 0x000 0x15 0x000
+#define MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x1d4 0x3cc 0x000 0x10 0x000
+#define MX25_PAD_FEC_TDATA1__AUD4_TXFS          0x1d4 0x3cc 0x474 0x12 0x001
+#define MX25_PAD_FEC_TDATA1__GPIO_3_8           0x1d4 0x3cc 0x000 0x15 0x000
+#define MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x1d8 0x3d0 0x000 0x10 0x000
+#define MX25_PAD_FEC_TX_EN__GPIO_3_9            0x1d8 0x3d0 0x000 0x15 0x000
+#define MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x1dc 0x3d4 0x000 0x10 0x000
+#define MX25_PAD_FEC_RDATA0__GPIO_3_10          0x1dc 0x3d4 0x000 0x15 0x000
+#define MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x1e0 0x3d8 0x000 0x10 0x000
+#define MX25_PAD_FEC_RDATA1__GPIO_3_11          0x1e0 0x3d8 0x000 0x15 0x000
+#define MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x1e4 0x3dc 0x000 0x10 0x000
+#define MX25_PAD_FEC_RX_DV__CAN2_RX             0x1e4 0x3dc 0x484 0x14 0x000
+#define MX25_PAD_FEC_RX_DV__GPIO_3_12           0x1e4 0x3dc 0x000 0x15 0x000
+#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1e8 0x3e0 0x000 0x10 0x000
+#define MX25_PAD_FEC_TX_CLK__GPIO_3_13          0x1e8 0x3e0 0x000 0x15 0x000
+#define MX25_PAD_RTCK__RTCK                     0x1ec 0x3e4 0x000 0x10 0x000
+#define MX25_PAD_RTCK__OWIRE                    0x1ec 0x3e4 0x000 0x11 0x000
+#define MX25_PAD_RTCK__GPIO_3_14                0x1ec 0x3e4 0x000 0x15 0x000
+#define MX25_PAD_DE_B__DE_B                     0x1f0 0x3ec 0x000 0x10 0x000
+#define MX25_PAD_DE_B__GPIO_2_20                0x1f0 0x3ec 0x000 0x15 0x000
+#define MX25_PAD_TDO__TDO                       0x000 0x3e8 0x000 0x00 0x000
+#define MX25_PAD_GPIO_A__GPIO_A                 0x1f4 0x3f0 0x000 0x10 0x000
+#define MX25_PAD_GPIO_A__CAN1_TX                0x1f4 0x3f0 0x000 0x16 0x000
+#define MX25_PAD_GPIO_A__USBOTG_PWR             0x1f4 0x3f0 0x000 0x12 0x000
+#define MX25_PAD_GPIO_B__GPIO_B                 0x1f8 0x3f4 0x000 0x10 0x000
+#define MX25_PAD_GPIO_B__CAN1_RX                0x1f8 0x3f4 0x480 0x16 0x001
+#define MX25_PAD_GPIO_B__USBOTG_OC              0x1f8 0x3f4 0x57c 0x12 0x001
+#define MX25_PAD_GPIO_C__GPIO_C                 0x1fc 0x3f8 0x000 0x10 0x000
+#define MX25_PAD_GPIO_C__CAN2_TX                0x1fc 0x3f8 0x000 0x16 0x000
+#define MX25_PAD_GPIO_D__GPIO_D                 0x200 0x3fc 0x000 0x10 0x000
+#define MX25_PAD_GPIO_E__LD16                   0x204 0x400 0x000 0x02 0x000
+#define MX25_PAD_GPIO_D__CAN2_RX                0x200 0x3fc 0x484 0x16 0x001
+#define MX25_PAD_GPIO_E__GPIO_E                 0x204 0x400 0x000 0x10 0x000
+#define MX25_PAD_GPIO_F__LD17                   0x208 0x404 0x000 0x02 0x000
+#define MX25_PAD_GPIO_E__AUD7_TXD               0x204 0x400 0x000 0x14 0x000
+#define MX25_PAD_GPIO_F__GPIO_F                 0x208 0x404 0x000 0x10 0x000
+#define MX25_PAD_GPIO_F__AUD7_TXC               0x208 0x404 0x000 0x14 0x000
+#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK         0x20c 0x000 0x000 0x10 0x000
+#define MX25_PAD_EXT_ARMCLK__GPIO_3_15          0x20c 0x000 0x000 0x15 0x000
+#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK       0x210 0x000 0x000 0x10 0x000
+#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16         0x210 0x000 0x000 0x15 0x000
+#define MX25_PAD_VSTBY_REQ__VSTBY_REQ           0x214 0x408 0x000 0x10 0x000
+#define MX25_PAD_VSTBY_REQ__AUD7_TXFS           0x214 0x408 0x000 0x14 0x000
+#define MX25_PAD_VSTBY_REQ__GPIO_3_17           0x214 0x408 0x000 0x15 0x000
+#define MX25_PAD_VSTBY_ACK__VSTBY_ACK           0x218 0x40c 0x000 0x10 0x000
+#define MX25_PAD_VSTBY_ACK__GPIO_3_18           0x218 0x40c 0x000 0x15 0x000
+#define MX25_PAD_POWER_FAIL__POWER_FAIL         0x21c 0x410 0x000 0x10 0x000
+#define MX25_PAD_POWER_FAIL__AUD7_RXD           0x21c 0x410 0x478 0x14 0x001
+#define MX25_PAD_POWER_FAIL__GPIO_3_19          0x21c 0x410 0x000 0x15 0x000
+#define MX25_PAD_CLKO__CLKO                     0x220 0x414 0x000 0x10 0x000
+#define MX25_PAD_CLKO__GPIO_2_21                0x220 0x414 0x000 0x15 0x000
+#define MX25_PAD_BOOT_MODE0__BOOT_MODE0         0x224 0x000 0x000 0x00 0x000
+#define MX25_PAD_BOOT_MODE0__GPIO_4_30          0x224 0x000 0x000 0x05 0x000
+#define MX25_PAD_BOOT_MODE1__BOOT_MODE1         0x228 0x000 0x000 0x00 0x000
+#define MX25_PAD_BOOT_MODE1__GPIO_4_31          0x228 0x000 0x000 0x05 0x000
+#endif /* __DTS_IMX25_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 737ed5da8f71..32f760e24898 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -10,6 +10,7 @@
 */
 #include "skeleton.dtsi"
+#include "imx25-pinfunc.h"
 / {
        aliases {
@@ -173,12 +174,12 @@
                                status = "disabled";
                        };
-                        iomuxc@43fac000{
+                        iomuxc: iomuxc@43fac000 {
                                compatible = "fsl,imx25-iomuxc";
                                reg = <0x43fac000 0x4000>;
                        };
-                        audmux@43fb0000 {
+                        audmux: audmux@43fb0000 {
                                compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
                                reg = <0x43fb0000 0x4000>;
                                status = "disabled";
@@ -236,6 +237,11 @@
                                compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
                                reg = <0x50014000 0x4000>;
                                interrupts = <11>;
+                                clocks = <&clks 118>;
+                                clock-names = "ipg";
+                                dmas = <&sdma 24 1 0>,
+                                       <&sdma 25 1 0>;
+                                dma-names = "rx", "tx";
                                status = "disabled";
                        };
@@ -266,6 +272,11 @@
                                compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
                                reg = <0x50034000 0x4000>;
                                interrupts = <12>;
+                                clocks = <&clks 117>;
+                                clock-names = "ipg";
+                                dmas = <&sdma 28 1 0>,
+                                       <&sdma 29 1 0>;
+                                dma-names = "rx", "tx";
                                status = "disabled";
                        };
@@ -436,13 +447,14 @@
                                #interrupt-cells = <2>;
                        };
-                        sdma@53fd4000 {
+                        sdma: sdma@53fd4000 {
                                compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
                                reg = <0x53fd4000 0x4000>;
                                clocks = <&clks 112>, <&clks 68>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
                                interrupts = <34>;
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
                        };
                        wdog@53fdc000 {
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index ba4c6df08ece..09f57b39e3ef 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -34,11 +34,49 @@
        };
 };
+&iomuxc {
+        imx27-apf27 {
+                pinctrl_fec1: fec1grp {
+                        fsl,pins = <
+                                MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+                                MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+                                MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+                                MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+                                MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+                                MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+                                MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+                                MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+                                MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+                                MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+                                MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+                                MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+                                MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+                                MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+                                MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+                                MX27_PAD_ATA_DATA13__FEC_COL 0x0
+                                MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+                                MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX27_PAD_UART1_TXD__UART1_TXD 0x0
+                                MX27_PAD_UART1_RXD__UART1_RXD 0x0
+                        >;
+                };
+        };
+};
 &uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 &fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 47c8c26012e4..2b6d489dae69 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -22,10 +22,10 @@
                bits-per-pixel = <16>;  /* non-standard but required */
                fsl,pcr = <0xfae80083>; /* non-standard but required */
                display-timings {
-                        timing0: 640x480 {
+                        timing0: 800x480 {
                                clock-frequency = <33000033>;
                                hactive = <800>;
-                                vactive = <640>;
+                                vactive = <480>;
                                hback-porch = <96>;
                                hfront-porch = <96>;
                                vback-porch = <20>;
@@ -38,20 +38,24 @@
        gpio-keys {
                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
                user-key {
                        label = "user";
-                        gpios = <&gpio6 13 0>;
+                        gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
                        linux,code = <276>; /* BTN_EXTRA */
                };
        };
        leds {
                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
                user {
                        label = "Heartbeat";
-                        gpios = <&gpio6 14 0>;
+                        gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
        };
@@ -59,25 +63,34 @@
 &cspi1 {
        fsl,spi-num-chipselects = <1>;
-        cs-gpios = <&gpio4 28 1>;
+        cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
        status = "okay";
 };
 &cspi2 {
        fsl,spi-num-chipselects = <3>;
-        cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>,
+        cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>,
-                        <&gpio2 17 1>;
+                   <&gpio4 27 GPIO_ACTIVE_LOW>,
+                   <&gpio2 17 GPIO_ACTIVE_LOW>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>;
        status = "okay";
 };
 &fb {
        display = <&display>;
        fsl,dmacr = <0x00020010>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_imxfb1>;
        status = "okay";
 };
 &i2c1 {
        clock-frequency = <400000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";
        rtc@68 {
@@ -87,5 +100,127 @@
 };
 &i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
 };
+&iomuxc {
+        imx27-apf27dev {
+                pinctrl_cspi1: cspi1grp {
+                        fsl,pins = <
+                                MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
+                                MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
+                                MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
+                        >;
+                };
+                pinctrl_cspi1_cs: cspi1csgrp {
+                        fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
+                };
+                pinctrl_cspi2: cspi2grp {
+                        fsl,pins = <
+                                MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
+                                MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
+                                MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
+                        >;
+                };
+                pinctrl_cspi2_cs: cspi2csgrp {
+                        fsl,pins = <
+                                MX27_PAD_CSI_D5__GPIO2_17 0x0
+                                MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
+                                MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
+                        >;
+                };
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
+                };
+                pinctrl_gpio_keys: gpiokeysgrp {
+                        fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
+                };
+                pinctrl_imxfb1: imxfbgrp {
+                        fsl,pins = <
+                                MX27_PAD_CLS__CLS 0x0
+                                MX27_PAD_CONTRAST__CONTRAST 0x0
+                                MX27_PAD_LD0__LD0 0x0
+                                MX27_PAD_LD1__LD1 0x0
+                                MX27_PAD_LD2__LD2 0x0
+                                MX27_PAD_LD3__LD3 0x0
+                                MX27_PAD_LD4__LD4 0x0
+                                MX27_PAD_LD5__LD5 0x0
+                                MX27_PAD_LD6__LD6 0x0
+                                MX27_PAD_LD7__LD7 0x0
+                                MX27_PAD_LD8__LD8 0x0
+                                MX27_PAD_LD9__LD9 0x0
+                                MX27_PAD_LD10__LD10 0x0
+                                MX27_PAD_LD11__LD11 0x0
+                                MX27_PAD_LD12__LD12 0x0
+                                MX27_PAD_LD13__LD13 0x0
+                                MX27_PAD_LD14__LD14 0x0
+                                MX27_PAD_LD15__LD15 0x0
+                                MX27_PAD_LD16__LD16 0x0
+                                MX27_PAD_LD17__LD17 0x0
+                                MX27_PAD_LSCLK__LSCLK 0x0
+                                MX27_PAD_OE_ACD__OE_ACD 0x0
+                                MX27_PAD_PS__PS 0x0
+                                MX27_PAD_REV__REV 0x0
+                                MX27_PAD_SPL_SPR__SPL_SPR 0x0
+                                MX27_PAD_HSYNC__HSYNC 0x0
+                                MX27_PAD_VSYNC__VSYNC 0x0
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX27_PAD_I2C_DATA__I2C_DATA 0x0
+                                MX27_PAD_I2C_CLK__I2C_CLK 0x0
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+                                MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+                        >;
+                };
+                pinctrl_pwm: pwmgrp {
+                        fsl,pins = <
+                                MX27_PAD_PWMO__PWMO 0x0
+                        >;
+                };
+                pinctrl_sdhc2: sdhc2grp {
+                        fsl,pins = <
+                                MX27_PAD_SD2_CLK__SD2_CLK 0x0
+                                MX27_PAD_SD2_CMD__SD2_CMD 0x0
+                                MX27_PAD_SD2_D0__SD2_D0 0x0
+                                MX27_PAD_SD2_D1__SD2_D1 0x0
+                                MX27_PAD_SD2_D2__SD2_D2 0x0
+                                MX27_PAD_SD2_D3__SD2_D3 0x0
+                        >;
+                };
+                pinctrl_sdhc2_cd: sdhc2cdgrp {
+                        fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
+                };
+        };
+};
+&sdhci2 {
+        bus-width = <4>;
+        cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>;
+        status = "okay";
+};
+&pwm {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm>;
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 5a31c776513f..3c3964a99637 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -9,7 +9,7 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
-#include "imx27-phytec-phycard-s-som.dts"
+#include "imx27-phytec-phycard-s-som.dtsi"
 / {
        model = "Phytec pca100 rapid development kit";
@@ -37,9 +37,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3v3: 3v3 {
+                reg_3v3: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "3V3";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
@@ -54,6 +57,8 @@
 };
 &i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";
        rtc@51 {
@@ -68,26 +73,92 @@
        };
 };
+&iomuxc {
+        imx27-phycard-s-rdk {
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+                                MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+                        >;
+                };
+                pinctrl_owire1: owire1grp {
+                        fsl,pins = <
+                                MX27_PAD_RTCK__OWIRE 0x0
+                        >;
+                };
+                pinctrl_sdhc2: sdhc2grp {
+                        fsl,pins = <
+                                MX27_PAD_SD2_CLK__SD2_CLK 0x0
+                                MX27_PAD_SD2_CMD__SD2_CMD 0x0
+                                MX27_PAD_SD2_D0__SD2_D0 0x0
+                                MX27_PAD_SD2_D1__SD2_D1 0x0
+                                MX27_PAD_SD2_D2__SD2_D2 0x0
+                                MX27_PAD_SD2_D3__SD2_D3 0x0
+                                MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX27_PAD_UART1_TXD__UART1_TXD 0x0
+                                MX27_PAD_UART1_RXD__UART1_RXD 0x0
+                                MX27_PAD_UART1_CTS__UART1_CTS 0x0
+                                MX27_PAD_UART1_RTS__UART1_RTS 0x0
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX27_PAD_UART2_TXD__UART2_TXD 0x0
+                                MX27_PAD_UART2_RXD__UART2_RXD 0x0
+                                MX27_PAD_UART2_CTS__UART2_CTS 0x0
+                                MX27_PAD_UART2_RTS__UART2_RTS 0x0
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX27_PAD_UART3_TXD__UART3_TXD 0x0
+                                MX27_PAD_UART3_RXD__UART3_RXD 0x0
+                                MX27_PAD_UART3_CTS__UART3_CTS 0x0
+                                MX27_PAD_UART3_RTS__UART3_RTS 0x0
+                        >;
+                };
+        };
+};
 &owire {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_owire1>;
        status = "okay";
 };
 &sdhci2 {
-        cd-gpios = <&gpio3 29 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sdhc2>;
+        cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
        status = "okay";
 };
 &uart1 {
        fsl,uart-has-rtscts;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 &uart2 {
        fsl,uart-has-rtscts;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
        status = "okay";
 };
 &uart3 {
        fsl,uart-has-rtscts;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
deleted file mode 100644
index c8d57d1d0743..000000000000
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
- * and Markus Pargmann, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-/dts-v1/;
-#include "imx27.dtsi"
-/ {
-        model = "Phytec pca100";
-        compatible = "phytec,imx27-pca100", "fsl,imx27";
-        memory {
-                reg = <0xa0000000 0x08000000>; /* 128MB */
-        };
-};
-&cspi1 {
-        fsl,spi-num-chipselects = <2>;
-        cs-gpios = <&gpio4 28 0>,
-                <&gpio4 27 0>;
-        status = "okay";
-};
-&fec {
-        status = "okay";
-};
-&i2c2 {
-        status = "okay";
-        at24@52 {
-                compatible = "at,24c32";
-                pagesize = <32>;
-                reg = <0x52>;
-        };
-};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
new file mode 100644
index 000000000000..1b6248079682
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
+ * and Markus Pargmann, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx27.dtsi"
+/ {
+        model = "Phytec pca100";
+        compatible = "phytec,imx27-pca100", "fsl,imx27";
+        memory {
+                reg = <0xa0000000 0x08000000>; /* 128MB */
+        };
+};
+&cspi1 {
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
+                   <&gpio4 27 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
+        status = "okay";
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        at24@52 {
+                compatible = "at,24c32";
+                pagesize = <32>;
+                reg = <0x52>;
+        };
+};
+&iomuxc {
+        imx27-phycard-s-som {
+                pinctrl_fec1: fec1grp {
+                        fsl,pins = <
+                                MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+                                MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+                                MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+                                MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+                                MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+                                MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+                                MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+                                MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+                                MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+                                MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+                                MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+                                MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+                                MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+                                MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+                                MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+                                MX27_PAD_ATA_DATA13__FEC_COL 0x0
+                                MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+                                MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+                                MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+                        >;
+                };
+                pinctrl_nfc: nfcgrp {
+                        fsl,pins = <
+                                MX27_PAD_NFRB__NFRB 0x0
+                                MX27_PAD_NFCLE__NFCLE 0x0
+                                MX27_PAD_NFWP_B__NFWP_B 0x0
+                                MX27_PAD_NFCE_B__NFCE_B 0x0
+                                MX27_PAD_NFALE__NFALE 0x0
+                                MX27_PAD_NFRE_B__NFRE_B 0x0
+                                MX27_PAD_NFWE_B__NFWE_B 0x0
+                        >;
+                };
+        };
+};
+&nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nfc>;
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index 0fc6551786c6..df3b2e731835 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -7,7 +7,7 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
-#include "imx27-phytec-phycore-som.dts"
+#include "imx27-phytec-phycore-som.dtsi"
 / {
        model = "Phytec pcm970";
@@ -16,32 +16,200 @@
 &cspi1 {
        fsl,spi-num-chipselects = <2>;
-        cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
+        cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
+                   <&gpio4 27 GPIO_ACTIVE_LOW>;
+};
+&i2c1 {
+        clock-frequency = <400000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        camgpio: pca9536@41 {
+                compatible = "nxp,pca9536";
+                reg = <0x41>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
+&iomuxc {
+        imx27_phycore_rdk {
+                pinctrl_i2c1: i2c1grp {
+                        /* Add pullup to DATA line */
+                        fsl,pins = <
+                                MX27_PAD_I2C_DATA__I2C_DATA     0x1
+                                MX27_PAD_I2C_CLK__I2C_CLK       0x0
+                        >;
+                };
+                pinctrl_owire1: owire1grp {
+                        fsl,pins = <
+                                MX27_PAD_RTCK__OWIRE 0x0
+                        >;
+                };
+                pinctrl_sdhc2: sdhc2grp {
+                        fsl,pins = <
+                                MX27_PAD_SD2_CLK__SD2_CLK 0x0
+                                MX27_PAD_SD2_CMD__SD2_CMD 0x0
+                                MX27_PAD_SD2_D0__SD2_D0 0x0
+                                MX27_PAD_SD2_D1__SD2_D1 0x0
+                                MX27_PAD_SD2_D2__SD2_D2 0x0
+                                MX27_PAD_SD2_D3__SD2_D3 0x0
+                                MX27_PAD_SSI3_FS__GPIO3_28      0x0 /* WP */
+                                MX27_PAD_SSI3_RXDAT__GPIO3_29   0x0 /* CD */
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX27_PAD_UART1_TXD__UART1_TXD 0x0
+                                MX27_PAD_UART1_RXD__UART1_RXD 0x0
+                                MX27_PAD_UART1_CTS__UART1_CTS 0x0
+                                MX27_PAD_UART1_RTS__UART1_RTS 0x0
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX27_PAD_UART2_TXD__UART2_TXD 0x0
+                                MX27_PAD_UART2_RXD__UART2_RXD 0x0
+                                MX27_PAD_UART2_CTS__UART2_CTS 0x0
+                                MX27_PAD_UART2_RTS__UART2_RTS 0x0
+                        >;
+                };
+                pinctrl_usbh2: usbh2grp {
+                        fsl,pins = <
+                                MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
+                                MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
+                                MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
+                                MX27_PAD_USBH2_STP__USBH2_STP 0x0
+                                MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
+                                MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
+                                MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
+                                MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
+                                MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
+                                MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
+                                MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
+                                MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
+                        >;
+                };
+                pinctrl_weim: weimgrp {
+                        fsl,pins = <
+                                MX27_PAD_CS4_B__CS4_B           0x0 /* CS4 */
+                                MX27_PAD_SD1_D1__GPIO5_19       0x0 /* CAN IRQ */
+                        >;
+                };
+        };
+};
+&owire {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_owire1>;
+        status = "okay";
+};
+&pmicleds {
+        ledr1: led@3 {
+                reg = <3>;
+                label = "system:red1:user";
+        };
+        ledg1: led@4 {
+                reg = <4>;
+                label = "system:green1:user";
+        };
+        ledb1: led@5 {
+                reg = <5>;
+                label = "system:blue1:user";
+        };
+        ledr2: led@6 {
+                reg = <6>;
+                label = "system:red2:user";
+        };
+        ledg2: led@7 {
+                reg = <7>;
+                label = "system:green2:user";
+        };
+        ledb2: led@8 {
+                reg = <8>;
+                label = "system:blue2:user";
+        };
+        ledr3: led@9 {
+                reg = <9>;
+                label = "system:red3:nand";
+                linux,default-trigger = "nand-disk";
+        };
+        ledg3: led@10 {
+                reg = <10>;
+                label = "system:green3:live";
+                linux,default-trigger = "heartbeat";
+        };
+        ledb3: led@11 {
+                reg = <11>;
+                label = "system:blue3:cpu";
+                linux,default-trigger = "cpu0";
+        };
 };
 &sdhci2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sdhc2>;
        bus-width = <4>;
-        cd-gpios = <&gpio3 29 0>;
+        cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
-        wp-gpios = <&gpio3 28 0>;
+        wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
        vmmc-supply = <&vmmc1_reg>;
        status = "okay";
 };
 &uart1 {
        fsl,uart-has-rtscts;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
 };
 &uart2 {
        fsl,uart-has-rtscts;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&usbh2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh2>;
+        dr_mode = "host";
+        phy_type = "ulpi";
+        vbus-supply = <&reg_5v0>;
+        disable-over-current;
        status = "okay";
 };
+&usbphy2 {
+        vcc-supply = <&reg_5v0>;
+};
 &weim {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_weim>;
        can@d4000000 {
                compatible = "nxp,sja1000";
                reg = <4 0x00000000 0x00000100>;
                interrupt-parent = <&gpio5>;
-                interrupts = <19 0x2>;
+                interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
                nxp,external-clock-frequency = <16000000>;
                nxp,tx-output-config = <0x16>;
                nxp,no-comparator-bypass;
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index 4ec402c38945..cefaa6994623 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -19,6 +19,28 @@
        memory {
                reg = <0xa0000000 0x08000000>;
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_3v3: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "3V3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                };
+                reg_5v0: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "5V0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+        };
 };
 &audmux {
@@ -37,21 +59,30 @@
 };
 &cspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cspi1>;
        fsl,spi-num-chipselects = <1>;
-        cs-gpios = <&gpio4 28 0>;
+        cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
        status = "okay";
        pmic: mc13783@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "fsl,mc13783";
-                spi-max-frequency = <20000000>;
                reg = <0>;
+                spi-cs-high;
+                spi-max-frequency = <20000000>;
                interrupt-parent = <&gpio2>;
-                interrupts = <23 0x4>;
+                interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
                fsl,mc13xxx-uses-adc;
                fsl,mc13xxx-uses-rtc;
+                pmicleds: leds {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        led-control = <0x001 0x000 0x000 0x000 0x000 0x000>;
+                };
                regulators {
                        /* SW1A and SW1B joined operation */
                        sw1_reg: sw1a {
@@ -134,12 +165,18 @@
 };
 &fec {
-        phy-reset-gpios = <&gpio3 30 0>;
+        phy-mode = "mii";
+        phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+        phy-supply = <&reg_3v3>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
        status = "okay";
 };
 &i2c2 {
        clock-frequency = <400000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
        at24@52 {
@@ -159,16 +196,102 @@
        };
 };
+&iomuxc {
+        imx27_phycore_som {
+                pinctrl_cspi1: cspi1grp {
+                        fsl,pins = <
+                                MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
+                                MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
+                                MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
+                                MX27_PAD_CSPI1_SS0__GPIO4_28    0x0 /* SPI1 CS0 */
+                                MX27_PAD_USB_PWR__GPIO2_23      0x0 /* PMIC IRQ */
+                        >;
+                };
+                pinctrl_fec1: fec1grp {
+                        fsl,pins = <
+                                MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+                                MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+                                MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+                                MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+                                MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+                                MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+                                MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+                                MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+                                MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+                                MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+                                MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+                                MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+                                MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+                                MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+                                MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+                                MX27_PAD_ATA_DATA13__FEC_COL 0x0
+                                MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+                                MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+                                MX27_PAD_SSI3_TXDAT__GPIO3_30   0x0 /* FEC RST */
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+                                MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+                        >;
+                };
+                pinctrl_nfc: nfcgrp {
+                        fsl,pins = <
+                                MX27_PAD_NFRB__NFRB 0x0
+                                MX27_PAD_NFCLE__NFCLE 0x0
+                                MX27_PAD_NFWP_B__NFWP_B 0x0
+                                MX27_PAD_NFCE_B__NFCE_B 0x0
+                                MX27_PAD_NFALE__NFALE 0x0
+                                MX27_PAD_NFRE_B__NFRE_B 0x0
+                                MX27_PAD_NFWE_B__NFWE_B 0x0
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
+                                MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
+                                MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
+                                MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
+                                MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
+                                MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
+                                MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
+                                MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
+                                MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
+                                MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
+                                MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
+                                MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
+                        >;
+                };
+        };
+};
 &nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nfc>;
        nand-bus-width = <8>;
        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
        status = "okay";
 };
-&uart1 {
+&usbotg {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        dr_mode = "otg";
+        phy_type = "ulpi";
+        vbus-supply = <&sw3_reg>;
        status = "okay";
 };
+&usbphy0 {
+        vcc-supply = <&sw3_reg>;
+};
 &weim {
        status = "okay";
diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/imx27-pinfunc.h
new file mode 100644
index 000000000000..f5387b4de577
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-pinfunc.h
@@ -0,0 +1,526 @@
+/*
+ * Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __DTS_IMX27_PINFUNC_H
+#define __DTS_IMX27_PINFUNC_H
+/*
+ * The pin function ID is a tuple of
+ * <pin mux_id>
+ * mux_id consists of
+ * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+ *
+ * function:      0 - Primary function
+ *                1 - Alternate function
+ *                2 - GPIO
+ * direction:     0 - Input
+ *                1 - Output
+ * gpio_oconf:    0 - A_IN
+ *                1 - B_IN
+ *                2 - C_IN
+ *                3 - Data Register
+ * gpio_iconfa/b: 0 - GPIO_IN
+ *                1 - Interrupt Status Register
+ *                2 - 0
+ *                3 - 1
+ *
+ * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ * number on the specific port (between 0 and 31).
+ */
+#define MX27_PAD_USBH2_CLK__USBH2_CLK                      0x00 0x000
+#define MX27_PAD_USBH2_CLK__GPIO1_0                        0x00 0x032
+#define MX27_PAD_USBH2_DIR__USBH2_DIR                      0x01 0x000
+#define MX27_PAD_USBH2_DIR__GPIO1_1                        0x01 0x032
+#define MX27_PAD_USBH2_DATA7__USBH2_DATA7                  0x02 0x004
+#define MX27_PAD_USBH2_DATA7__GPIO1_2                      0x02 0x032
+#define MX27_PAD_USBH2_NXT__USBH2_NXT                      0x03 0x000
+#define MX27_PAD_USBH2_NXT__GPIO1_3                        0x03 0x032
+#define MX27_PAD_USBH2_STP__USBH2_STP                      0x04 0x004
+#define MX27_PAD_USBH2_STP__GPIO1_4                        0x04 0x032
+#define MX27_PAD_LSCLK__LSCLK                              0x05 0x004
+#define MX27_PAD_LSCLK__GPIO1_5                            0x05 0x032
+#define MX27_PAD_LD0__LD0                                  0x06 0x004
+#define MX27_PAD_LD0__GPIO1_6                              0x06 0x032
+#define MX27_PAD_LD1__LD1                                  0x07 0x004
+#define MX27_PAD_LD1__GPIO1_7                              0x07 0x032
+#define MX27_PAD_LD2__LD2                                  0x08 0x004
+#define MX27_PAD_LD2__GPIO1_8                              0x08 0x032
+#define MX27_PAD_LD3__LD3                                  0x09 0x004
+#define MX27_PAD_LD3__GPIO1_9                              0x09 0x032
+#define MX27_PAD_LD4__LD4                                  0x0a 0x004
+#define MX27_PAD_LD4__GPIO1_10                             0x0a 0x032
+#define MX27_PAD_LD5__LD5                                  0x0b 0x004
+#define MX27_PAD_LD5__GPIO1_11                             0x0b 0x032
+#define MX27_PAD_LD6__LD6                                  0x0c 0x004
+#define MX27_PAD_LD6__GPIO1_12                             0x0c 0x032
+#define MX27_PAD_LD7__LD7                                  0x0d 0x004
+#define MX27_PAD_LD7__GPIO1_13                             0x0d 0x032
+#define MX27_PAD_LD8__LD8                                  0x0e 0x004
+#define MX27_PAD_LD8__GPIO1_14                             0x0e 0x032
+#define MX27_PAD_LD9__LD9                                  0x0f 0x004
+#define MX27_PAD_LD9__GPIO1_15                             0x0f 0x032
+#define MX27_PAD_LD10__LD10                                0x10 0x004
+#define MX27_PAD_LD10__GPIO1_16                            0x10 0x032
+#define MX27_PAD_LD11__LD11                                0x11 0x004
+#define MX27_PAD_LD11__GPIO1_17                            0x11 0x032
+#define MX27_PAD_LD12__LD12                                0x12 0x004
+#define MX27_PAD_LD12__GPIO1_18                            0x12 0x032
+#define MX27_PAD_LD13__LD13                                0x13 0x004
+#define MX27_PAD_LD13__GPIO1_19                            0x13 0x032
+#define MX27_PAD_LD14__LD14                                0x14 0x004
+#define MX27_PAD_LD14__GPIO1_20                            0x14 0x032
+#define MX27_PAD_LD15__LD15                                0x15 0x004
+#define MX27_PAD_LD15__GPIO1_21                            0x15 0x032
+#define MX27_PAD_LD16__LD16                                0x16 0x004
+#define MX27_PAD_LD16__GPIO1_22                            0x16 0x032
+#define MX27_PAD_LD17__LD17                                0x17 0x004
+#define MX27_PAD_LD17__GPIO1_23                            0x17 0x032
+#define MX27_PAD_REV__REV                                  0x18 0x004
+#define MX27_PAD_REV__GPIO1_24                             0x18 0x032
+#define MX27_PAD_CLS__CLS                                  0x19 0x004
+#define MX27_PAD_CLS__GPIO1_25                             0x19 0x032
+#define MX27_PAD_PS__PS                                    0x1a 0x004
+#define MX27_PAD_PS__GPIO1_26                              0x1a 0x032
+#define MX27_PAD_SPL_SPR__SPL_SPR                          0x1b 0x004
+#define MX27_PAD_SPL_SPR__GPIO1_27                         0x1b 0x032
+#define MX27_PAD_HSYNC__HSYNC                              0x1c 0x004
+#define MX27_PAD_HSYNC__GPIO1_28                           0x1c 0x032
+#define MX27_PAD_VSYNC__VSYNC                              0x1d 0x004
+#define MX27_PAD_VSYNC__GPIO1_29                           0x1d 0x032
+#define MX27_PAD_CONTRAST__CONTRAST                        0x1e 0x004
+#define MX27_PAD_CONTRAST__GPIO1_30                        0x1e 0x032
+#define MX27_PAD_OE_ACD__OE_ACD                            0x1f 0x004
+#define MX27_PAD_OE_ACD__GPIO1_31                          0x1f 0x032
+#define MX27_PAD_UNUSED0__UNUSED0                          0x20 0x004
+#define MX27_PAD_UNUSED0__GPIO2_0                          0x20 0x032
+#define MX27_PAD_UNUSED1__UNUSED1                          0x21 0x004
+#define MX27_PAD_UNUSED1__GPIO2_1                          0x21 0x032
+#define MX27_PAD_UNUSED2__UNUSED2                          0x22 0x004
+#define MX27_PAD_UNUSED2__GPIO2_2                          0x22 0x032
+#define MX27_PAD_UNUSED3__UNUSED3                          0x23 0x004
+#define MX27_PAD_UNUSED3__GPIO2_3                          0x23 0x032
+#define MX27_PAD_SD2_D0__SD2_D0                            0x24 0x004
+#define MX27_PAD_SD2_D0__MSHC_DATA0                        0x24 0x005
+#define MX27_PAD_SD2_D0__GPIO2_4                           0x24 0x032
+#define MX27_PAD_SD2_D1__SD2_D1                            0x25 0x004
+#define MX27_PAD_SD2_D1__MSHC_DATA1                        0x25 0x005
+#define MX27_PAD_SD2_D1__GPIO2_5                           0x25 0x032
+#define MX27_PAD_SD2_D2__SD2_D2                            0x26 0x004
+#define MX27_PAD_SD2_D2__MSHC_DATA2                        0x26 0x005
+#define MX27_PAD_SD2_D2__GPIO2_6                           0x26 0x032
+#define MX27_PAD_SD2_D3__SD2_D3                            0x27 0x004
+#define MX27_PAD_SD2_D3__MSHC_DATA3                        0x27 0x005
+#define MX27_PAD_SD2_D3__GPIO2_7                           0x27 0x032
+#define MX27_PAD_SD2_CMD__SD2_CMD                          0x28 0x004
+#define MX27_PAD_SD2_CMD__MSHC_BS                          0x28 0x005
+#define MX27_PAD_SD2_CMD__GPIO2_8                          0x28 0x032
+#define MX27_PAD_SD2_CLK__SD2_CLK                          0x29 0x004
+#define MX27_PAD_SD2_CLK__MSHC_SCLK                        0x29 0x005
+#define MX27_PAD_SD2_CLK__GPIO2_9                          0x29 0x032
+#define MX27_PAD_CSI_D0__CSI_D0                            0x2a 0x000
+#define MX27_PAD_CSI_D0__UART6_TXD                         0x2a 0x005
+#define MX27_PAD_CSI_D0__GPIO2_10                          0x2a 0x032
+#define MX27_PAD_CSI_D1__CSI_D1                            0x2b 0x000
+#define MX27_PAD_CSI_D1__UART6_RXD                         0x2b 0x001
+#define MX27_PAD_CSI_D1__GPIO2_11                          0x2b 0x032
+#define MX27_PAD_CSI_D2__CSI_D2                            0x2c 0x000
+#define MX27_PAD_CSI_D2__UART6_CTS                         0x2c 0x005
+#define MX27_PAD_CSI_D2__GPIO2_12                          0x2c 0x032
+#define MX27_PAD_CSI_D3__CSI_D3                            0x2d 0x000
+#define MX27_PAD_CSI_D3__UART6_RTS                         0x2d 0x001
+#define MX27_PAD_CSI_D3__GPIO2_13                          0x2d 0x032
+#define MX27_PAD_CSI_D4__CSI_D4                            0x2e 0x000
+#define MX27_PAD_CSI_D4__GPIO2_14                          0x2e 0x032
+#define MX27_PAD_CSI_MCLK__CSI_MCLK                        0x2f 0x004
+#define MX27_PAD_CSI_MCLK__GPIO2_15                        0x2f 0x032
+#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK                    0x30 0x000
+#define MX27_PAD_CSI_PIXCLK__GPIO2_16                      0x30 0x032
+#define MX27_PAD_CSI_D5__CSI_D5                            0x31 0x000
+#define MX27_PAD_CSI_D5__GPIO2_17                          0x31 0x032
+#define MX27_PAD_CSI_D6__CSI_D6                            0x32 0x000
+#define MX27_PAD_CSI_D6__UART5_TXD                         0x32 0x005
+#define MX27_PAD_CSI_D6__GPIO2_18                          0x32 0x032
+#define MX27_PAD_CSI_D7__CSI_D7                            0x33 0x000
+#define MX27_PAD_CSI_D7__UART5_RXD                         0x33 0x001
+#define MX27_PAD_CSI_D7__GPIO2_19                          0x33 0x032
+#define MX27_PAD_CSI_VSYNC__CSI_VSYNC                      0x34 0x000
+#define MX27_PAD_CSI_VSYNC__UART5_CTS                      0x34 0x005
+#define MX27_PAD_CSI_VSYNC__GPIO2_20                       0x34 0x032
+#define MX27_PAD_CSI_HSYNC__CSI_HSYNC                      0x35 0x000
+#define MX27_PAD_CSI_HSYNC__UART5_RTS                      0x35 0x001
+#define MX27_PAD_CSI_HSYNC__GPIO2_21                       0x35 0x032
+#define MX27_PAD_USBH1_SUSP__USBH1_SUSP                    0x36 0x004
+#define MX27_PAD_USBH1_SUSP__GPIO2_22                      0x36 0x032
+#define MX27_PAD_USB_PWR__USB_PWR                          0x37 0x004
+#define MX27_PAD_USB_PWR__GPIO2_23                         0x37 0x032
+#define MX27_PAD_USB_OC_B__USB_OC_B                        0x38 0x000
+#define MX27_PAD_USB_OC_B__GPIO2_24                        0x38 0x032
+#define MX27_PAD_USBH1_RCV__USBH1_RCV                      0x39 0x004
+#define MX27_PAD_USBH1_RCV__GPIO2_25                       0x39 0x032
+#define MX27_PAD_USBH1_FS__USBH1_FS                        0x3a 0x004
+#define MX27_PAD_USBH1_FS__UART4_RTS                       0x3a 0x001
+#define MX27_PAD_USBH1_FS__GPIO2_26                        0x3a 0x032
+#define MX27_PAD_USBH1_OE_B__USBH1_OE_B                    0x3b 0x004
+#define MX27_PAD_USBH1_OE_B__GPIO2_27                      0x3b 0x032
+#define MX27_PAD_USBH1_TXDM__USBH1_TXDM                    0x3c 0x004
+#define MX27_PAD_USBH1_TXDM__UART4_TXD                     0x3c 0x005
+#define MX27_PAD_USBH1_TXDM__GPIO2_28                      0x3c 0x032
+#define MX27_PAD_USBH1_TXDP__USBH1_TXDP                    0x3d 0x004
+#define MX27_PAD_USBH1_TXDP__UART4_CTS                     0x3d 0x005
+#define MX27_PAD_USBH1_TXDP__GPIO2_29                      0x3d 0x032
+#define MX27_PAD_USBH1_RXDM__USBH1_RXDM                    0x3e 0x004
+#define MX27_PAD_USBH1_RXDM__GPIO2_30                      0x3e 0x032
+#define MX27_PAD_USBH1_RXDP__USBH1_RXDP                    0x3f 0x004
+#define MX27_PAD_USBH1_RXDP__UART4_RXD                     0x3f 0x001
+#define MX27_PAD_USBH1_RXDP__GPIO2_31                      0x3f 0x032
+#define MX27_PAD_UNUSED4__UNUSED4                          0x40 0x004
+#define MX27_PAD_UNUSED4__GPIO3_0                          0x40 0x032
+#define MX27_PAD_UNUSED5__UNUSED5                          0x41 0x004
+#define MX27_PAD_UNUSED5__GPIO3_1                          0x41 0x032
+#define MX27_PAD_UNUSED6__UNUSED6                          0x42 0x004
+#define MX27_PAD_UNUSED6__GPIO3_2                          0x42 0x032
+#define MX27_PAD_UNUSED7__UNUSED7                          0x43 0x004
+#define MX27_PAD_UNUSED7__GPIO3_3                          0x43 0x032
+#define MX27_PAD_UNUSED8__UNUSED8                          0x44 0x004
+#define MX27_PAD_UNUSED8__GPIO3_4                          0x44 0x032
+#define MX27_PAD_I2C2_SDA__I2C2_SDA                        0x45 0x004
+#define MX27_PAD_I2C2_SDA__GPIO3_5                         0x45 0x032
+#define MX27_PAD_I2C2_SCL__I2C2_SCL                        0x46 0x004
+#define MX27_PAD_I2C2_SCL__GPIO3_6                         0x46 0x032
+#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5                0x47 0x004
+#define MX27_PAD_USBOTG_DATA5__GPIO3_7                     0x47 0x032
+#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6                0x48 0x004
+#define MX27_PAD_USBOTG_DATA6__GPIO3_8                     0x48 0x032
+#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0                0x49 0x004
+#define MX27_PAD_USBOTG_DATA0__GPIO3_9                     0x49 0x032
+#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2                0x4a 0x004
+#define MX27_PAD_USBOTG_DATA2__GPIO3_10                    0x4a 0x032
+#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1                0x4b 0x004
+#define MX27_PAD_USBOTG_DATA1__GPIO3_11                    0x4b 0x032
+#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4                0x4c 0x004
+#define MX27_PAD_USBOTG_DATA4__GPIO3_12                    0x4c 0x032
+#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3                0x4d 0x004
+#define MX27_PAD_USBOTG_DATA3__GPIO3_13                    0x4d 0x032
+#define MX27_PAD_TOUT__TOUT                                0x4e 0x004
+#define MX27_PAD_TOUT__GPIO3_14                            0x4e 0x032
+#define MX27_PAD_TIN__TIN                                  0x4f 0x000
+#define MX27_PAD_TIN__GPIO3_15                             0x4f 0x032
+#define MX27_PAD_SSI4_FS__SSI4_FS                          0x50 0x004
+#define MX27_PAD_SSI4_FS__GPIO3_16                         0x50 0x032
+#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT                    0x51 0x004
+#define MX27_PAD_SSI4_RXDAT__GPIO3_17                      0x51 0x032
+#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT                    0x52 0x004
+#define MX27_PAD_SSI4_TXDAT__GPIO3_18                      0x52 0x032
+#define MX27_PAD_SSI4_CLK__SSI4_CLK                        0x53 0x004
+#define MX27_PAD_SSI4_CLK__GPIO3_19                        0x53 0x032
+#define MX27_PAD_SSI1_FS__SSI1_FS                          0x54 0x004
+#define MX27_PAD_SSI1_FS__GPIO3_20                         0x54 0x032
+#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT                    0x55 0x004
+#define MX27_PAD_SSI1_RXDAT__GPIO3_21                      0x55 0x032
+#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT                    0x56 0x004
+#define MX27_PAD_SSI1_TXDAT__GPIO3_22                      0x56 0x032
+#define MX27_PAD_SSI1_CLK__SSI1_CLK                        0x57 0x004
+#define MX27_PAD_SSI1_CLK__GPIO3_23                        0x57 0x032
+#define MX27_PAD_SSI2_FS__SSI2_FS                          0x58 0x004
+#define MX27_PAD_SSI2_FS__GPT5_TOUT                        0x58 0x005
+#define MX27_PAD_SSI2_FS__GPIO3_24                         0x58 0x032
+#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT                    0x59 0x004
+#define MX27_PAD_SSI2_RXDAT__GPTS_TIN                      0x59 0x001
+#define MX27_PAD_SSI2_RXDAT__GPIO3_25                      0x59 0x032
+#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT                    0x5a 0x004
+#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT                     0x5a 0x005
+#define MX27_PAD_SSI2_TXDAT__GPIO3_26                      0x5a 0x032
+#define MX27_PAD_SSI2_CLK__SSI2_CLK                        0x5b 0x004
+#define MX27_PAD_SSI2_CLK__GPT4_TIN                        0x5b 0x001
+#define MX27_PAD_SSI2_CLK__GPIO3_27                        0x5b 0x032
+#define MX27_PAD_SSI3_FS__SSI3_FS                          0x5c 0x004
+#define MX27_PAD_SSI3_FS__SLCDC2_D0                        0x5c 0x001
+#define MX27_PAD_SSI3_FS__GPIO3_28                         0x5c 0x032
+#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT                    0x5d 0x004
+#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS                     0x5d 0x001
+#define MX27_PAD_SSI3_RXDAT__GPIO3_29                      0x5d 0x032
+#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT                    0x5e 0x004
+#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS                     0x5e 0x001
+#define MX27_PAD_SSI3_TXDAT__GPIO3_30                      0x5e 0x032
+#define MX27_PAD_SSI3_CLK__SSI3_CLK                        0x5f 0x004
+#define MX27_PAD_SSI3_CLK__SLCDC2_CLK                      0x5f 0x001
+#define MX27_PAD_SSI3_CLK__GPIO3_31                        0x5f 0x032
+#define MX27_PAD_SD3_CMD__SD3_CMD                          0x60 0x004
+#define MX27_PAD_SD3_CMD__FEC_TXD0                         0x60 0x006
+#define MX27_PAD_SD3_CMD__GPIO4_0                          0x60 0x032
+#define MX27_PAD_SD3_CLK__SD3_CLK                          0x61 0x004
+#define MX27_PAD_SD3_CLK__ETMTRACEPKT15                    0x61 0x005
+#define MX27_PAD_SD3_CLK__FEC_TXD1                         0x61 0x006
+#define MX27_PAD_SD3_CLK__GPIO4_1                          0x61 0x032
+#define MX27_PAD_ATA_DATA0__ATA_DATA0                      0x62 0x004
+#define MX27_PAD_ATA_DATA0__SD3_D0                         0x62 0x005
+#define MX27_PAD_ATA_DATA0__FEC_TXD2                       0x62 0x006
+#define MX27_PAD_ATA_DATA0__GPIO4_2                        0x62 0x032
+#define MX27_PAD_ATA_DATA1__ATA_DATA1                      0x63 0x004
+#define MX27_PAD_ATA_DATA1__SD3_D1                         0x63 0x005
+#define MX27_PAD_ATA_DATA1__FEC_TXD3                       0x63 0x006
+#define MX27_PAD_ATA_DATA1__GPIO4_3                        0x63 0x032
+#define MX27_PAD_ATA_DATA2__ATA_DATA2                      0x64 0x004
+#define MX27_PAD_ATA_DATA2__SD3_D2                         0x64 0x005
+#define MX27_PAD_ATA_DATA2__FEC_RX_ER                      0x64 0x002
+#define MX27_PAD_ATA_DATA2__GPIO4_4                        0x64 0x032
+#define MX27_PAD_ATA_DATA3__ATA_DATA3                      0x65 0x004
+#define MX27_PAD_ATA_DATA3__SD3_D3                         0x65 0x005
+#define MX27_PAD_ATA_DATA3__FEC_RXD1                       0x65 0x002
+#define MX27_PAD_ATA_DATA3__GPIO4_5                        0x65 0x032
+#define MX27_PAD_ATA_DATA4__ATA_DATA4                      0x66 0x004
+#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14                  0x66 0x005
+#define MX27_PAD_ATA_DATA4__FEC_RXD2                       0x66 0x002
+#define MX27_PAD_ATA_DATA4__GPIO4_6                        0x66 0x032
+#define MX27_PAD_ATA_DATA5__ATA_DATA5                      0x67 0x004
+#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13                  0x67 0x005
+#define MX27_PAD_ATA_DATA5__FEC_RXD3                       0x67 0x002
+#define MX27_PAD_ATA_DATA5__GPIO4_7                        0x67 0x032
+#define MX27_PAD_ATA_DATA6__ATA_DATA6                      0x68 0x004
+#define MX27_PAD_ATA_DATA6__FEC_MDIO                       0x68 0x005
+#define MX27_PAD_ATA_DATA6__GPIO4_8                        0x68 0x032
+#define MX27_PAD_ATA_DATA7__ATA_DATA7                      0x69 0x004
+#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12                  0x69 0x005
+#define MX27_PAD_ATA_DATA7__FEC_MDC                        0x69 0x006
+#define MX27_PAD_ATA_DATA7__GPIO4_9                        0x69 0x032
+#define MX27_PAD_ATA_DATA8__ATA_DATA8                      0x6a 0x004
+#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11                  0x6a 0x005
+#define MX27_PAD_ATA_DATA8__FEC_CRS                        0x6a 0x002
+#define MX27_PAD_ATA_DATA8__GPIO4_10                       0x6a 0x032
+#define MX27_PAD_ATA_DATA9__ATA_DATA9                      0x6b 0x004
+#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10                  0x6b 0x005
+#define MX27_PAD_ATA_DATA9__FEC_TX_CLK                     0x6b 0x002
+#define MX27_PAD_ATA_DATA9__GPIO4_11                       0x6b 0x032
+#define MX27_PAD_ATA_DATA10__ATA_DATA10                    0x6c 0x004
+#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9                  0x6c 0x005
+#define MX27_PAD_ATA_DATA10__FEC_RXD0                      0x6c 0x002
+#define MX27_PAD_ATA_DATA10__GPIO4_12                      0x6c 0x032
+#define MX27_PAD_ATA_DATA11__ATA_DATA11                    0x6d 0x004
+#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8                  0x6d 0x005
+#define MX27_PAD_ATA_DATA11__FEC_RX_DV                     0x6d 0x002
+#define MX27_PAD_ATA_DATA11__GPIO4_13                      0x6d 0x032
+#define MX27_PAD_ATA_DATA12__ATA_DATA12                    0x6e 0x004
+#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7                  0x6e 0x005
+#define MX27_PAD_ATA_DATA12__FEC_RX_CLK                    0x6e 0x002
+#define MX27_PAD_ATA_DATA12__GPIO4_14                      0x6e 0x032
+#define MX27_PAD_ATA_DATA13__ATA_DATA13                    0x6f 0x004
+#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6                  0x6f 0x005
+#define MX27_PAD_ATA_DATA13__FEC_COL                       0x6f 0x002
+#define MX27_PAD_ATA_DATA13__GPIO4_15                      0x6f 0x032
+#define MX27_PAD_ATA_DATA14__ATA_DATA14                    0x70 0x004
+#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5                  0x70 0x005
+#define MX27_PAD_ATA_DATA14__FEC_TX_ER                     0x70 0x006
+#define MX27_PAD_ATA_DATA14__GPIO4_16                      0x70 0x032
+#define MX27_PAD_I2C_DATA__I2C_DATA                        0x71 0x004
+#define MX27_PAD_I2C_DATA__GPIO4_17                        0x71 0x032
+#define MX27_PAD_I2C_CLK__I2C_CLK                          0x72 0x004
+#define MX27_PAD_I2C_CLK__GPIO4_18                         0x72 0x032
+#define MX27_PAD_CSPI2_SS2__CSPI2_SS2                      0x73 0x004
+#define MX27_PAD_CSPI2_SS2__USBH2_DATA4                    0x73 0x005
+#define MX27_PAD_CSPI2_SS2__GPIO4_19                       0x73 0x032
+#define MX27_PAD_CSPI2_SS1__CSPI2_SS1                      0x74 0x004
+#define MX27_PAD_CSPI2_SS1__USBH2_DATA3                    0x74 0x005
+#define MX27_PAD_CSPI2_SS1__GPIO4_20                       0x74 0x032
+#define MX27_PAD_CSPI2_SS0__CSPI2_SS0                      0x75 0x004
+#define MX27_PAD_CSPI2_SS0__USBH2_DATA6                    0x75 0x005
+#define MX27_PAD_CSPI2_SS0__GPIO4_21                       0x75 0x032
+#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK                    0x76 0x004
+#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0                   0x76 0x005
+#define MX27_PAD_CSPI2_SCLK__GPIO4_22                      0x76 0x032
+#define MX27_PAD_CSPI2_MISO__CSPI2_MISO                    0x77 0x004
+#define MX27_PAD_CSPI2_MISO__USBH2_DATA2                   0x77 0x005
+#define MX27_PAD_CSPI2_MISO__GPIO4_23                      0x77 0x032
+#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI                    0x78 0x004
+#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1                   0x78 0x005
+#define MX27_PAD_CSPI2_MOSI__GPIO4_24                      0x78 0x032
+#define MX27_PAD_CSPI1_RDY__CSPI1_RDY                      0x79 0x000
+#define MX27_PAD_CSPI1_RDY__GPIO4_25                       0x79 0x032
+#define MX27_PAD_CSPI1_SS2__CSPI1_SS2                      0x7a 0x004
+#define MX27_PAD_CSPI1_SS2__USBH2_DATA5                    0x7a 0x005
+#define MX27_PAD_CSPI1_SS2__GPIO4_26                       0x7a 0x032
+#define MX27_PAD_CSPI1_SS1__CSPI1_SS1                      0x7b 0x004
+#define MX27_PAD_CSPI1_SS1__GPIO4_27                       0x7b 0x032
+#define MX27_PAD_CSPI1_SS0__CSPI1_SS0                      0x7c 0x004
+#define MX27_PAD_CSPI1_SS0__GPIO4_28                       0x7c 0x032
+#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK                    0x7d 0x004
+#define MX27_PAD_CSPI1_SCLK__GPIO4_29                      0x7d 0x032
+#define MX27_PAD_CSPI1_MISO__CSPI1_MISO                    0x7e 0x004
+#define MX27_PAD_CSPI1_MISO__GPIO4_30                      0x7e 0x032
+#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI                    0x7f 0x004
+#define MX27_PAD_CSPI1_MOSI__GPIO4_31                      0x7f 0x032
+#define MX27_PAD_USBOTG_NXT__USBOTG_NXT                    0x80 0x000
+#define MX27_PAD_USBOTG_NXT__KP_COL6A                      0x80 0x005
+#define MX27_PAD_USBOTG_NXT__GPIO5_0                       0x80 0x032
+#define MX27_PAD_USBOTG_STP__USBOTG_STP                    0x81 0x004
+#define MX27_PAD_USBOTG_STP__KP_ROW6A                      0x81 0x005
+#define MX27_PAD_USBOTG_STP__GPIO5_1                       0x81 0x032
+#define MX27_PAD_USBOTG_DIR__USBOTG_DIR                    0x82 0x000
+#define MX27_PAD_USBOTG_DIR__KP_ROW7A                      0x82 0x005
+#define MX27_PAD_USBOTG_DIR__GPIO5_2                       0x82 0x032
+#define MX27_PAD_UART2_CTS__UART2_CTS                      0x83 0x004
+#define MX27_PAD_UART2_CTS__KP_COL7                        0x83 0x005
+#define MX27_PAD_UART2_CTS__GPIO5_3                        0x83 0x032
+#define MX27_PAD_UART2_RTS__UART2_RTS                      0x84 0x000
+#define MX27_PAD_UART2_RTS__KP_ROW7                        0x84 0x005
+#define MX27_PAD_UART2_RTS__GPIO5_4                        0x84 0x032
+#define MX27_PAD_PWMO__PWMO                                0x85 0x004
+#define MX27_PAD_PWMO__GPIO5_5                             0x85 0x032
+#define MX27_PAD_UART2_TXD__UART2_TXD                      0x86 0x004
+#define MX27_PAD_UART2_TXD__KP_COL6                        0x86 0x005
+#define MX27_PAD_UART2_TXD__GPIO5_6                        0x86 0x032
+#define MX27_PAD_UART2_RXD__UART2_RXD                      0x87 0x000
+#define MX27_PAD_UART2_RXD__KP_ROW6                        0x87 0x005
+#define MX27_PAD_UART2_RXD__GPIO5_7                        0x87 0x032
+#define MX27_PAD_UART3_TXD__UART3_TXD                      0x88 0x004
+#define MX27_PAD_UART3_TXD__GPIO5_8                        0x88 0x032
+#define MX27_PAD_UART3_RXD__UART3_RXD                      0x89 0x000
+#define MX27_PAD_UART3_RXD__GPIO5_9                        0x89 0x032
+#define MX27_PAD_UART3_CTS__UART3_CTS                      0x8a 0x004
+#define MX27_PAD_UART3_CTS__GPIO5_10                       0x8a 0x032
+#define MX27_PAD_UART3_RTS__UART3_RTS                      0x8b 0x000
+#define MX27_PAD_UART3_RTS__GPIO5_11                       0x8b 0x032
+#define MX27_PAD_UART1_TXD__UART1_TXD                      0x8c 0x004
+#define MX27_PAD_UART1_TXD__GPIO5_12                       0x8c 0x032
+#define MX27_PAD_UART1_RXD__UART1_RXD                      0x8d 0x000
+#define MX27_PAD_UART1_RXD__GPIO5_13                       0x8d 0x032
+#define MX27_PAD_UART1_CTS__UART1_CTS                      0x8e 0x004
+#define MX27_PAD_UART1_CTS__GPIO5_14                       0x8e 0x032
+#define MX27_PAD_UART1_RTS__UART1_RTS                      0x8f 0x000
+#define MX27_PAD_UART1_RTS__GPIO5_15                       0x8f 0x032
+#define MX27_PAD_RTCK__RTCK                                0x90 0x004
+#define MX27_PAD_RTCK__OWIRE                               0x90 0x005
+#define MX27_PAD_RTCK__GPIO5_16                            0x90 0x032
+#define MX27_PAD_RESET_OUT_B__RESET_OUT_B                  0x91 0x004
+#define MX27_PAD_RESET_OUT_B__GPIO5_17                     0x91 0x032
+#define MX27_PAD_SD1_D0__SD1_D0                            0x92 0x004
+#define MX27_PAD_SD1_D0__CSPI3_MISO                        0x92 0x001
+#define MX27_PAD_SD1_D0__GPIO5_18                          0x92 0x032
+#define MX27_PAD_SD1_D1__SD1_D1                            0x93 0x004
+#define MX27_PAD_SD1_D1__GPIO5_19                          0x93 0x032
+#define MX27_PAD_SD1_D2__SD1_D2                            0x94 0x004
+#define MX27_PAD_SD1_D2__GPIO5_20                          0x94 0x032
+#define MX27_PAD_SD1_D3__SD1_D3                            0x95 0x004
+#define MX27_PAD_SD1_D3__CSPI3_SS                          0x95 0x005
+#define MX27_PAD_SD1_D3__GPIO5_21                          0x95 0x032
+#define MX27_PAD_SD1_CMD__SD1_CMD                          0x96 0x004
+#define MX27_PAD_SD1_CMD__CSPI3_MOSI                       0x96 0x005
+#define MX27_PAD_SD1_CMD__GPIO5_22                         0x96 0x032
+#define MX27_PAD_SD1_CLK__SD1_CLK                          0x97 0x004
+#define MX27_PAD_SD1_CLK__CSPI3_SCLK                       0x97 0x005
+#define MX27_PAD_SD1_CLK__GPIO5_23                         0x97 0x032
+#define MX27_PAD_USBOTG_CLK__USBOTG_CLK                    0x98 0x000
+#define MX27_PAD_USBOTG_CLK__GPIO5_24                      0x98 0x032
+#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7                0x99 0x004
+#define MX27_PAD_USBOTG_DATA7__GPIO5_25                    0x99 0x032
+#define MX27_PAD_UNUSED9__UNUSED9                          0x9a 0x004
+#define MX27_PAD_UNUSED9__GPIO5_26                         0x9a 0x032
+#define MX27_PAD_UNUSED10__UNUSED10                        0x9b 0x004
+#define MX27_PAD_UNUSED10__GPIO5_27                        0x9b 0x032
+#define MX27_PAD_UNUSED11__UNUSED11                        0x9c 0x004
+#define MX27_PAD_UNUSED11__GPIO5_28                        0x9c 0x032
+#define MX27_PAD_UNUSED12__UNUSED12                        0x9d 0x004
+#define MX27_PAD_UNUSED12__GPIO5_29                        0x9d 0x032
+#define MX27_PAD_UNUSED13__UNUSED13                        0x9e 0x004
+#define MX27_PAD_UNUSED13__GPIO5_30                        0x9e 0x032
+#define MX27_PAD_UNUSED14__UNUSED14                        0x9f 0x004
+#define MX27_PAD_UNUSED14__GPIO5_31                        0x9f 0x032
+#define MX27_PAD_NFRB__NFRB                                0xa0 0x000
+#define MX27_PAD_NFRB__ETMTRACEPKT3                        0xa0 0x005
+#define MX27_PAD_NFRB__GPIO6_0                             0xa0 0x032
+#define MX27_PAD_NFCLE__NFCLE                              0xa1 0x004
+#define MX27_PAD_NFCLE__ETMTRACEPKT0                       0xa1 0x005
+#define MX27_PAD_NFCLE__GPIO6_1                            0xa1 0x032
+#define MX27_PAD_NFWP_B__NFWP_B                            0xa2 0x004
+#define MX27_PAD_NFWP_B__ETMTRACEPKT1                      0xa2 0x005
+#define MX27_PAD_NFWP_B__GPIO6_2                           0xa2 0x032
+#define MX27_PAD_NFCE_B__NFCE_B                            0xa3 0x004
+#define MX27_PAD_NFCE_B__ETMTRACEPKT2                      0xa3 0x005
+#define MX27_PAD_NFCE_B__GPIO6_3                           0xa3 0x032
+#define MX27_PAD_NFALE__NFALE                              0xa4 0x004
+#define MX27_PAD_NFALE__ETMPIPESTAT0                       0xa4 0x005
+#define MX27_PAD_NFALE__GPIO6_4                            0xa4 0x032
+#define MX27_PAD_NFRE_B__NFRE_B                            0xa5 0x004
+#define MX27_PAD_NFRE_B__ETMPIPESTAT1                      0xa5 0x005
+#define MX27_PAD_NFRE_B__GPIO6_5                           0xa5 0x032
+#define MX27_PAD_NFWE_B__NFWE_B                            0xa6 0x004
+#define MX27_PAD_NFWE_B__ETMPIPESTAT2                      0xa6 0x005
+#define MX27_PAD_NFWE_B__GPIO6_6                           0xa6 0x032
+#define MX27_PAD_PC_POE__PC_POE                            0xa7 0x004
+#define MX27_PAD_PC_POE__ATA_BUFFER_EN                     0xa7 0x005
+#define MX27_PAD_PC_POE__GPIO6_7                           0xa7 0x032
+#define MX27_PAD_PC_RW_B__PC_RW_B                          0xa8 0x004
+#define MX27_PAD_PC_RW_B__ATA_IORDY                        0xa8 0x001
+#define MX27_PAD_PC_RW_B__GPIO6_8                          0xa8 0x032
+#define MX27_PAD_IOIS16__IOIS16                            0xa9 0x000
+#define MX27_PAD_IOIS16__ATA_INTRQ                         0xa9 0x001
+#define MX27_PAD_IOIS16__GPIO6_9                           0xa9 0x032
+#define MX27_PAD_PC_RST__PC_RST                            0xaa 0x004
+#define MX27_PAD_PC_RST__ATA_RESET_B                       0xaa 0x005
+#define MX27_PAD_PC_RST__GPIO6_10                          0xaa 0x032
+#define MX27_PAD_PC_BVD2__PC_BVD2                          0xab 0x000
+#define MX27_PAD_PC_BVD2__ATA_DMACK                        0xab 0x005
+#define MX27_PAD_PC_BVD2__GPIO6_11                         0xab 0x032
+#define MX27_PAD_PC_BVD1__PC_BVD1                          0xac 0x000
+#define MX27_PAD_PC_BVD1__ATA_DMARQ                        0xac 0x001
+#define MX27_PAD_PC_BVD1__GPIO6_12                         0xac 0x032
+#define MX27_PAD_PC_VS2__PC_VS2                            0xad 0x000
+#define MX27_PAD_PC_VS2__ATA_DA0                           0xad 0x005
+#define MX27_PAD_PC_VS2__GPIO6_13                          0xad 0x032
+#define MX27_PAD_PC_VS1__PC_VS1                            0xae 0x000
+#define MX27_PAD_PC_VS1__ATA_DA1                           0xae 0x005
+#define MX27_PAD_PC_VS1__GPIO6_14                          0xae 0x032
+#define MX27_PAD_CLKO__CLKO                                0xaf 0x004
+#define MX27_PAD_CLKO__GPIO6_15                            0xaf 0x032
+#define MX27_PAD_PC_PWRON__PC_PWRON                        0xb0 0x000
+#define MX27_PAD_PC_PWRON__ATA_DA2                         0xb0 0x005
+#define MX27_PAD_PC_PWRON__GPIO6_16                        0xb0 0x032
+#define MX27_PAD_PC_READY__PC_READY                        0xb1 0x000
+#define MX27_PAD_PC_READY__ATA_CS0                         0xb1 0x005
+#define MX27_PAD_PC_READY__GPIO6_17                        0xb1 0x032
+#define MX27_PAD_PC_WAIT_B__PC_WAIT_B                      0xb2 0x000
+#define MX27_PAD_PC_WAIT_B__ATA_CS1                        0xb2 0x005
+#define MX27_PAD_PC_WAIT_B__GPIO6_18                       0xb2 0x032
+#define MX27_PAD_PC_CD2_B__PC_CD2_B                        0xb3 0x000
+#define MX27_PAD_PC_CD2_B__ATA_DIOW                        0xb3 0x005
+#define MX27_PAD_PC_CD2_B__GPIO6_19                        0xb3 0x032
+#define MX27_PAD_PC_CD1_B__PC_CD1_B                        0xb4 0x000
+#define MX27_PAD_PC_CD1_B__ATA_DIOR                        0xb4 0x005
+#define MX27_PAD_PC_CD1_B__GPIO6_20                        0xb4 0x032
+#define MX27_PAD_CS4_B__CS4_B                              0xb5 0x004
+#define MX27_PAD_CS4_B__ETMTRACESYNC                       0xb5 0x005
+#define MX27_PAD_CS4_B__GPIO6_21                           0xb5 0x032
+#define MX27_PAD_CS5_B__CS5_B                              0xb6 0x004
+#define MX27_PAD_CS5_B__ETMTRACECLK                        0xb6 0x005
+#define MX27_PAD_CS5_B__GPIO6_22                           0xb6 0x032
+#define MX27_PAD_ATA_DATA15__ATA_DATA15                    0xb7 0x004
+#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4                  0xb7 0x005
+#define MX27_PAD_ATA_DATA15__FEC_TX_EN                     0xb7 0x006
+#define MX27_PAD_ATA_DATA15__GPIO6_23                      0xb7 0x032
+#define MX27_PAD_UNUSED15__UNUSED15                        0xb8 0x004
+#define MX27_PAD_UNUSED15__GPIO6_24                        0xb8 0x032
+#define MX27_PAD_UNUSED16__UNUSED16                        0xb9 0x004
+#define MX27_PAD_UNUSED16__GPIO6_25                        0xb9 0x032
+#define MX27_PAD_UNUSED17__UNUSED17                        0xba 0x004
+#define MX27_PAD_UNUSED17__GPIO6_26                        0xba 0x032
+#define MX27_PAD_UNUSED18__UNUSED18                        0xbb 0x004
+#define MX27_PAD_UNUSED18__GPIO6_27                        0xbb 0x032
+#define MX27_PAD_UNUSED19__UNUSED19                        0xbc 0x004
+#define MX27_PAD_UNUSED19__GPIO6_28                        0xbc 0x032
+#define MX27_PAD_UNUSED20__UNUSED20                        0xbd 0x004
+#define MX27_PAD_UNUSED20__GPIO6_29                        0xbd 0x032
+#define MX27_PAD_UNUSED21__UNUSED21                        0xbe 0x004
+#define MX27_PAD_UNUSED21__GPIO6_30                        0xbe 0x032
+#define MX27_PAD_UNUSED22__UNUSED22                        0xbf 0x004
+#define MX27_PAD_UNUSED22__GPIO6_31                        0xbf 0x032
+#endif /* __DTS_IMX27_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 826231eb4446..6279e0b4f768 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -10,6 +10,9 @@
 */
 #include "skeleton.dtsi"
+#include "imx27-pinfunc.h"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        aliases {
@@ -67,6 +70,26 @@
                };
        };
+        usbphy {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usbphy0: usbphy@0 {
+                        compatible = "usb-nop-xceiv";
+                        reg = <0>;
+                        clocks = <&clks 75>;
+                        clock-names = "main_clk";
+                };
+                usbphy2: usbphy@2 {
+                        compatible = "usb-nop-xceiv";
+                        reg = <2>;
+                        clocks = <&clks 75>;
+                        clock-names = "main_clk";
+                };
+        };
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -204,6 +227,30 @@
                                status = "disabled";
                        };
+                        ssi1: ssi@10010000 {
+                                #sound-dai-cells = <0>;
+                                compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
+                                reg = <0x10010000 0x1000>;
+                                interrupts = <14>;
+                                clocks = <&clks 26>;
+                                dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
+                                dma-names = "rx0", "tx0", "rx1", "tx1";
+                                fsl,fifo-depth = <8>;
+                                status = "disabled";
+                        };
+                        ssi2: ssi@10011000 {
+                                #sound-dai-cells = <0>;
+                                compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
+                                reg = <0x10011000 0x1000>;
+                                interrupts = <13>;
+                                clocks = <&clks 25>;
+                                dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
+                                dma-names = "rx0", "tx0", "rx1", "tx1";
+                                fsl,fifo-depth = <8>;
+                                status = "disabled";
+                        };
                        i2c1: i2c@10012000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -236,64 +283,72 @@
                                status = "disabled";
                        };
-                        gpio1: gpio@10015000 {
+                        iomuxc: iomuxc@10015000 {
-                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                compatible = "fsl,imx27-iomuxc";
-                                reg = <0x10015000 0x100>;
+                                reg = <0x10015000 0x600>;
-                                interrupts = <8>;
+                                #address-cells = <1>;
-                                gpio-controller;
+                                #size-cells = <1>;
-                                #gpio-cells = <2>;
+                                ranges;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                gpio1: gpio@10015000 {
-                        };
+                                        compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        reg = <0x10015000 0x100>;
-                        gpio2: gpio@10015100 {
+                                        interrupts = <8>;
-                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        gpio-controller;
-                                reg = <0x10015100 0x100>;
+                                        #gpio-cells = <2>;
-                                interrupts = <8>;
+                                        interrupt-controller;
-                                gpio-controller;
+                                        #interrupt-cells = <2>;
-                                #gpio-cells = <2>;
+                                };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                gpio2: gpio@10015100 {
-                        };
+                                        compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        reg = <0x10015100 0x100>;
-                        gpio3: gpio@10015200 {
+                                        interrupts = <8>;
-                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        gpio-controller;
-                                reg = <0x10015200 0x100>;
+                                        #gpio-cells = <2>;
-                                interrupts = <8>;
+                                        interrupt-controller;
-                                gpio-controller;
+                                        #interrupt-cells = <2>;
-                                #gpio-cells = <2>;
+                                };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                gpio3: gpio@10015200 {
-                        };
+                                        compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        reg = <0x10015200 0x100>;
-                        gpio4: gpio@10015300 {
+                                        interrupts = <8>;
-                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        gpio-controller;
-                                reg = <0x10015300 0x100>;
+                                        #gpio-cells = <2>;
-                                interrupts = <8>;
+                                        interrupt-controller;
-                                gpio-controller;
+                                        #interrupt-cells = <2>;
-                                #gpio-cells = <2>;
+                                };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                gpio4: gpio@10015300 {
-                        };
+                                        compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        reg = <0x10015300 0x100>;
-                        gpio5: gpio@10015400 {
+                                        interrupts = <8>;
-                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        gpio-controller;
-                                reg = <0x10015400 0x100>;
+                                        #gpio-cells = <2>;
-                                interrupts = <8>;
+                                        interrupt-controller;
-                                gpio-controller;
+                                        #interrupt-cells = <2>;
-                                #gpio-cells = <2>;
+                                };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                gpio5: gpio@10015400 {
-                        };
+                                        compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        reg = <0x10015400 0x100>;
-                        gpio6: gpio@10015500 {
+                                        interrupts = <8>;
-                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        gpio-controller;
-                                reg = <0x10015500 0x100>;
+                                        #gpio-cells = <2>;
-                                interrupts = <8>;
+                                        interrupt-controller;
-                                gpio-controller;
+                                        #interrupt-cells = <2>;
-                                #gpio-cells = <2>;
+                                };
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
+                                gpio6: gpio@10015500 {
+                                        compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                        reg = <0x10015500 0x100>;
+                                        interrupts = <8>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
                        };
                        audmux: audmux@10016000 {
@@ -404,6 +459,42 @@
                                iram = <&iram>;
                        };
+                        usbotg: usb@10024000 {
+                                compatible = "fsl,imx27-usb";
+                                reg = <0x10024000 0x200>;
+                                interrupts = <56>;
+                                clocks = <&clks 15>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                fsl,usbphy = <&usbphy0>;
+                                status = "disabled";
+                        };
+                        usbh1: usb@10024200 {
+                                compatible = "fsl,imx27-usb";
+                                reg = <0x10024200 0x200>;
+                                interrupts = <54>;
+                                clocks = <&clks 15>;
+                                fsl,usbmisc = <&usbmisc 1>;
+                                status = "disabled";
+                        };
+                        usbh2: usb@10024400 {
+                                compatible = "fsl,imx27-usb";
+                                reg = <0x10024400 0x200>;
+                                interrupts = <55>;
+                                clocks = <&clks 15>;
+                                fsl,usbmisc = <&usbmisc 2>;
+                                fsl,usbphy = <&usbphy2>;
+                                status = "disabled";
+                        };
+                        usbmisc: usbmisc@10024600 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx27-usbmisc";
+                                reg = <0x10024600 0x200>;
+                                clocks = <&clks 62>;
+                        };
                        sahara2: sahara@10025000 {
                                compatible = "fsl,imx27-sahara";
                                reg = <0x10025000 0x1000>;
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index e2efd8d89c4f..221cac4fb2cd 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -48,6 +48,7 @@
                                                MX28_PAD_LCD_D20__GPIO_1_20
                                                MX28_PAD_LCD_D21__GPIO_1_21
                                                MX28_PAD_LCD_D22__GPIO_1_22
+                                                MX28_PAD_GPMI_CE1N__GPIO_0_17
                                        >;
                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
@@ -66,6 +67,16 @@
                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
                                        fsl,pull-up = <MXS_PULL_DISABLE>;
                                };
+                                usb0_otg_apf28dev: otg-apf28dev@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_LCD_D23__GPIO_1_23
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
                        };
                        lcdif@80030000 {
@@ -131,6 +142,8 @@
        ahb@80080000 {
                usb0: usb@80080000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usb0_otg_apf28dev>;
                        vbus-supply = <&reg_usb0_vbus>;
                        status = "okay";
                };
@@ -150,13 +163,17 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb0_vbus: usb0_vbus {
+                reg_usb0_vbus: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "usb0_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        gpio = <&gpio1 23 1>;
+                        enable-active-high;
                };
        };
@@ -177,4 +194,14 @@
                brightness-levels = <0 4 8 16 32 64 128 255>;
                default-brightness-level = <6>;
        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                user-button {
+                        label = "User button";
+                        gpios = <&gpio0 17 0>;
+                        linux,code = <0x100>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index 6f254ca816cb..e1ce9179db63 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -193,9 +193,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3p3v: 3p3v {
+                reg_3p3v: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index cabb6171a19d..ae7c3390e65a 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -100,6 +100,8 @@
                usb0: usb@80080000 {
                        pinctrl-names = "default";
                        pinctrl-0 = <&usb0_otg_cfa10036>;
+                        dr_mode = "peripheral";
+                        phy_type = "utmi";
                        status = "okay";
                };
        };
diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts
index f93e9a700e52..e5beaa58bb40 100644
--- a/arch/arm/boot/dts/imx28-cfa10037.dts
+++ b/arch/arm/boot/dts/imx28-cfa10037.dts
@@ -54,7 +54,7 @@
        ahb@80080000 {
                usb1: usb@80090000 {
                        vbus-supply = <&reg_usb1_vbus>;
-                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-0 = <&usb1_pins_a>;
                        pinctrl-names = "default";
                        status = "okay";
                };
@@ -72,9 +72,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb1_vbus: usb1_vbus {
+                reg_usb1_vbus: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&usb_pins_cfa10037>;
                        regulator-name = "usb1_vbus";
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 7087b4bf6a8f..7d51459de5e8 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -229,15 +229,39 @@
                                i2c-parent = <&i2c1>;
                                i2c@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
                                        reg = <0>;
+                                        adc0: nau7802@2a {
+                                                compatible = "nuvoton,nau7802";
+                                                reg = <0x2a>;
+                                                nuvoton,vldo = <3000>;
+                                        };
                                };
                                i2c@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
                                        reg = <1>;
+                                        adc1: nau7802@2a {
+                                                compatible = "nuvoton,nau7802";
+                                                reg = <0x2a>;
+                                                nuvoton,vldo = <3000>;
+                                        };
                                };
                                i2c@2 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
                                        reg = <2>;
+                                        adc2: nau7802@2a {
+                                                compatible = "nuvoton,nau7802";
+                                                reg = <0x2a>;
+                                                nuvoton,vldo = <3000>;
+                                        };
                                };
                                i2c@3 {
@@ -274,7 +298,7 @@
        ahb@80080000 {
                usb1: usb@80090000 {
                        vbus-supply = <&reg_usb1_vbus>;
-                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-0 = <&usb1_pins_a>;
                        pinctrl-names = "default";
                        status = "okay";
                };
@@ -282,9 +306,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb1_vbus: usb1_vbus {
+                reg_usb1_vbus: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&usb_pins_cfa10049>;
                        regulator-name = "usb1_vbus";
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
index 3c1312885ae0..c4e00ce4b6da 100644
--- a/arch/arm/boot/dts/imx28-cfa10057.dts
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -134,7 +134,7 @@
        ahb@80080000 {
                usb1: usb@80090000 {
                        vbus-supply = <&reg_usb1_vbus>;
-                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-0 = <&usb1_pins_a>;
                        pinctrl-names = "default";
                        status = "okay";
                };
@@ -142,9 +142,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb1_vbus: usb1_vbus {
+                reg_usb1_vbus: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&usb_pins_cfa10057>;
                        regulator-name = "usb1_vbus";
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts
index 2469d34df0ae..7c9cc783f0d1 100644
--- a/arch/arm/boot/dts/imx28-cfa10058.dts
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -101,7 +101,7 @@
        ahb@80080000 {
                usb1: usb@80090000 {
                        vbus-supply = <&reg_usb1_vbus>;
-                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-0 = <&usb1_pins_a>;
                        pinctrl-names = "default";
                        status = "okay";
                };
@@ -109,11 +109,14 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb1_vbus: usb1_vbus {
+                reg_usb1_vbus: regulator@0 {
                        pinctrl-names = "default";
                        pinctrl-0 = <&usb_pins_cfa10058>;
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "usb1_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
new file mode 100644
index 000000000000..5f326c1c1850
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2013 Michael Heimpold <mhei@heimpold.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx28.dtsi"
+/ {
+        model = "I2SE Duckbill";
+        compatible = "i2se,duckbill", "fsl,imx28";
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_8bit_pins_a
+                                        &mmc0_cd_cfg &mmc0_sck_cfg>;
+                                bus-width = <8>;
+                                vmmc-supply = <&reg_3p3v>;
+                                status = "okay";
+                        };
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+                                led_pins_a: led_gpio@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_AUART1_RX__GPIO_3_4
+                                                MX28_PAD_AUART1_TX__GPIO_3_5
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+                        };
+                };
+                apbx@80040000 {
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        status = "okay";
+                };
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        phy-supply = <&reg_3p3v>;
+                        phy-reset-gpios = <&gpio4 13 0>;
+                        phy-reset-duration = <100>;
+                        status = "okay";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_3p3v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_a>;
+                status {
+                        label = "duckbill:green:status";
+                        gpios = <&gpio3 5 0>;
+                };
+                failure {
+                        label = "duckbill:red:status";
+                        gpios = <&gpio3 4 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
new file mode 100644
index 000000000000..7c1572c5a4fb
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <eric@eukrea.com>
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC
+ */
+/dts-v1/;
+#include "imx28-eukrea-mbmx28lc.dtsi"
+/ {
+        model = "Eukrea Electromatique MBMX283LC";
+        compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
+        memory {
+                reg = <0x40000000 0x04000000>;
+        };
+};
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpmi_pins_a>;
+        status = "okay";
+};
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins_a>;
+        status = "okay";
+        pcf8563: rtc@51 {
+                compatible = "nxp,pcf8563";
+                reg = <0x51>;
+        };
+};
+&mac0 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mac0_pins_a>;
+        phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+&pinctrl{
+        pinctrl-names = "default";
+        pinctrl-0 = <&hog_pins_cpuimx283>;
+        hog_pins_cpuimx283: hog-cpuimx283@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_ENET0_RX_CLK__GPIO_4_13
+                        MX28_PAD_ENET0_TX_CLK__GPIO_4_5
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_ENABLE>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
new file mode 100644
index 000000000000..e773144e1e03
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <eric@eukrea.com>
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC
+ */
+#include "imx28-eukrea-mbmx283lc.dts"
+/ {
+        model = "Eukrea Electromatique MBMX287LC";
+        compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+};
+&mac1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mac1_pins_a>;
+        phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&pinctrl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>;
+        hog_pins_cpuimx287: hog-cpuimx287@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_SPDIF__GPIO_3_27
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_ENABLE>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
new file mode 100644
index 000000000000..927b391d2058
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
@@ -0,0 +1,326 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <eric@eukrea.com>
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx28.dtsi"
+/ {
+        model = "Eukrea Electromatique MBMX28LC";
+        compatible = "eukrea,mbmx28lc", "fsl,imx28";
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 4 1000000>;
+                brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>;
+                default-brightness-level = <10>;
+        };
+        button-sw3 {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>;
+                sw3 {
+                        label = "SW3";
+                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+                        linux,code = <BTN_MISC>;
+                        gpio-key,wakeup;
+                };
+        };
+        button-sw4 {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>;
+                sw4 {
+                        label = "SW4";
+                        gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+                        linux,code = <BTN_MISC>;
+                        gpio-key,wakeup;
+                };
+        };
+        led-d6 {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_d6_pins_mbmx28lc>;
+                led1 {
+                        label = "d6";
+                        gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        led-d7 {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_d7_pins_mbmx28lc>;
+                led1 {
+                        label = "d7";
+                        gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_3p3v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_lcd_3v3: regulator@1 {
+                        compatible = "regulator-fixed";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&reg_lcd_3v3_pins_mbmx28lc>;
+                        regulator-name = "lcd-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usb0_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&reg_usb0_vbus_pins_mbmx28lc>;
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usb1_vbus: regulator@3 {
+                        compatible = "regulator-fixed";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&reg_usb1_vbus_pins_mbmx28lc>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+        };
+        sound {
+                compatible = "fsl,imx28-mbmx28lc-sgtl5000",
+                             "fsl,mxs-audio-sgtl5000";
+                model = "imx28-mbmx28lc-sgtl5000";
+                saif-controllers = <&saif0 &saif1>;
+                audio-codec = <&sgtl5000>;
+        };
+};
+&duart {
+        pinctrl-names = "default";
+        pinctrl-0 = <&duart_4pins_a>;
+        status = "okay";
+};
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins_a>;
+        status = "okay";
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p3v>;
+                VDDIO-supply = <&reg_3p3v>;
+                clocks = <&saif0>;
+        };
+};
+&lcdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>;
+        lcd-supply = <&reg_lcd_3v3>;
+        display = <&display0>;
+        status = "okay";
+        display0: display0 {
+                model = "43WVF1G-0";
+                bits-per-pixel = <16>;
+                bus-width = <18>;
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <9072000>;
+                                hactive = <480>;
+                                vactive = <272>;
+                                hback-porch = <10>;
+                                hfront-porch = <5>;
+                                vback-porch = <8>;
+                                vfront-porch = <8>;
+                                hsync-len = <40>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <1>;
+                        };
+                };
+        };
+};
+&lradc {
+        fsl,lradc-touchscreen-wires = <4>;
+        status = "okay";
+};
+&pinctrl {
+        gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_LCD_D21__GPIO_1_21
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_DISABLE>;
+        };
+        gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_LCD_D20__GPIO_1_20
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_DISABLE>;
+        };
+        lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_LCD_VSYNC__LCD_VSYNC
+                        MX28_PAD_LCD_HSYNC__LCD_HSYNC
+                        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
+                        MX28_PAD_LCD_ENABLE__LCD_ENABLE
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_DISABLE>;
+        };
+        led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_LCD_D23__GPIO_1_23
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_DISABLE>;
+        };
+        led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_LCD_D22__GPIO_1_22
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_DISABLE>;
+        };
+        reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_LCD_RESET__GPIO_3_30
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_DISABLE>;
+        };
+        reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_LCD_D18__GPIO_1_18
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_DISABLE>;
+        };
+        reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 {
+                reg = <0>;
+                fsl,pinmux-ids = <
+                        MX28_PAD_LCD_D19__GPIO_1_19
+                >;
+                fsl,drive-strength = <MXS_DRIVE_4mA>;
+                fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                fsl,pull-up = <MXS_PULL_DISABLE>;
+        };
+};
+&pwm {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pwm4_pins_a>;
+        status = "okay";
+};
+&saif0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&saif0_pins_a>;
+        status = "okay";
+};
+&saif1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&saif1_pins_a>;
+        fsl,saif-master = <&saif0>;
+        status = "okay";
+};
+&ssp0 {
+        compatible = "fsl,imx28-mmc";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>;
+        bus-width = <4>;
+        cd-inverted;
+        status = "okay";
+};
+&usb0 {
+        disable-over-current;
+        vbus-supply = <&reg_usb0_vbus>;
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb0_id_pins_b>;
+};
+&usb1 {
+        vbus-supply = <&reg_usb1_vbus>;
+        status = "okay";
+};
+&usbphy0 {
+        status = "okay";
+};
+&usbphy1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 4267c2b05d60..e4cc44c98585 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -193,6 +193,7 @@
                        i2c0: i2c@80058000 {
                                pinctrl-names = "default";
                                pinctrl-0 = <&i2c0_pins_a>;
+                                clock-frequency = <400000>;
                                status = "okay";
                                sgtl5000: codec@0a {
@@ -278,33 +279,39 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3p3v: 3p3v {
+                reg_3p3v: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };
-                reg_vddio_sd0: vddio-sd0 {
+                reg_vddio_sd0: regulator@1 {
                        compatible = "regulator-fixed";
+                        reg = <1>;
                        regulator-name = "vddio-sd0";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        gpio = <&gpio3 28 0>;
                };
-                reg_fec_3v3: fec-3v3 {
+                reg_fec_3v3: regulator@2 {
                        compatible = "regulator-fixed";
+                        reg = <2>;
                        regulator-name = "fec-3v3";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        gpio = <&gpio2 15 0>;
                };
-                reg_usb0_vbus: usb0_vbus {
+                reg_usb0_vbus: regulator@3 {
                        compatible = "regulator-fixed";
+                        reg = <3>;
                        regulator-name = "usb0_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
@@ -312,8 +319,9 @@
                        enable-active-high;
                };
-                reg_usb1_vbus: usb1_vbus {
+                reg_usb1_vbus: regulator@4 {
                        compatible = "regulator-fixed";
+                        reg = <4>;
                        regulator-name = "usb1_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
@@ -321,8 +329,9 @@
                        enable-active-high;
                };
-                reg_lcd_3v3: lcd-3v3 {
+                reg_lcd_3v3: regulator@5 {
                        compatible = "regulator-fixed";
+                        reg = <5>;
                        regulator-name = "lcd-3v3";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
@@ -330,8 +339,9 @@
                        enable-active-high;
                };
-                reg_can_3v3: can-3v3 {
+                reg_can_3v3: regulator@6 {
                        compatible = "regulator-fixed";
+                        reg = <6>;
                        regulator-name = "can-3v3";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index d3958da60bd7..9348ce59dda4 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -116,7 +116,6 @@
                                pinctrl-0 = <&lcdif_24bit_pins_a
                                             &lcdif_pins_m28>;
                                display = <&display>;
-                                reset-active-high;
                                status = "okay";
                                display: display0 {
@@ -180,7 +179,7 @@
                usb1: usb@80090000 {
                        vbus-supply = <&reg_usb1_vbus>;
                        pinctrl-names = "default";
-                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-0 = <&usb1_pins_a>;
                        disable-over-current;
                        status = "okay";
                };
@@ -229,33 +228,39 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3p3v: 3p3v {
+                reg_3p3v: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };
-                reg_vddio_sd0: vddio-sd0 {
+                reg_vddio_sd0: regulator@1 {
                        compatible = "regulator-fixed";
+                        reg = <1>;
                        regulator-name = "vddio-sd0";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        gpio = <&gpio3 29 0>;
                };
-                reg_vddio_sd1: vddio-sd1 {
+                reg_vddio_sd1: regulator@2 {
                        compatible = "regulator-fixed";
+                        reg = <2>;
                        regulator-name = "vddio-sd1";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        gpio = <&gpio2 19 0>;
                };
-                reg_usb1_vbus: usb1_vbus {
+                reg_usb1_vbus: regulator@3 {
                        compatible = "regulator-fixed";
+                        reg = <3>;
                        regulator-name = "usb1_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 8e2477fbe1d7..f0ad7b9b9d9a 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -194,7 +194,7 @@
                                };
                                rtc: rtc@68 {
-                                        compatible = "stm,mt41t62";
+                                        compatible = "stm,m41t62";
                                        reg = <0x68>;
                                };
                        };
@@ -248,14 +248,14 @@
                usb0: usb@80080000 {
                        vbus-supply = <&reg_usb0_vbus>;
                        pinctrl-names = "default";
-                        pinctrl-0 = <&usbphy0_pins_a>;
+                        pinctrl-0 = <&usb0_pins_a>;
                        status = "okay";
                };
                usb1: usb@80090000 {
                        vbus-supply = <&reg_usb1_vbus>;
                        pinctrl-names = "default";
-                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-0 = <&usb1_pins_a>;
                        status = "okay";
                };
@@ -285,33 +285,39 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3p3v: 3p3v {
+                reg_3p3v: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };
-                reg_vddio_sd0: vddio-sd0 {
+                reg_vddio_sd0: regulator@1 {
                        compatible = "regulator-fixed";
+                        reg = <1>;
                        regulator-name = "vddio-sd0";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        gpio = <&gpio3 28 0>;
                };
-                reg_usb0_vbus: usb0_vbus {
+                reg_usb0_vbus: regulator@2 {
                        compatible = "regulator-fixed";
+                        reg = <2>;
                        regulator-name = "usb0_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        gpio = <&gpio3 12 0>;
                };
-                reg_usb1_vbus: usb1_vbus {
+                reg_usb1_vbus: regulator@3 {
                        compatible = "regulator-fixed";
+                        reg = <3>;
                        regulator-name = "usb1_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 4870f07bf56a..0ce3cb8e7914 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -106,7 +106,7 @@
                usb0: usb@80080000 {
                        vbus-supply = <&reg_usb0_vbus>;
                        pinctrl-names = "default";
-                        pinctrl-0 = <&usbphy0_pins_b>;
+                        pinctrl-0 = <&usb0_pins_b>;
                        status = "okay";
                };
@@ -127,9 +127,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb0_vbus: usb0_vbus {
+                reg_usb0_vbus: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "usb0_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index be5a0550d58c..e14bd86f3e99 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -43,9 +43,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb0_vbus: usb0_vbus {
+                reg_usb0_vbus: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "usb0_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
@@ -53,8 +56,9 @@
                        enable-active-high;
                };
-                reg_usb1_vbus: usb1_vbus {
+                reg_usb1_vbus: regulator@1 {
                        compatible = "regulator-fixed";
+                        reg = <1>;
                        regulator-name = "usb1_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
@@ -62,35 +66,38 @@
                        enable-active-high;
                };
-                reg_2p5v: 2p5v {
+                reg_2p5v: regulator@2 {
                        compatible = "regulator-fixed";
+                        reg = <2>;
                        regulator-name = "2P5V";
                        regulator-min-microvolt = <2500000>;
                        regulator-max-microvolt = <2500000>;
                        regulator-always-on;
                };
-                reg_3p3v: 3p3v {
+                reg_3p3v: regulator@3 {
                        compatible = "regulator-fixed";
+                        reg = <3>;
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };
-                reg_can_xcvr: can-xcvr {
+                reg_can_xcvr: regulator@4 {
                        compatible = "regulator-fixed";
+                        reg = <4>;
                        regulator-name = "CAN XCVR";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        gpio = <&gpio1 0 0>;
-                        enable-active-low;
                        pinctrl-names = "default";
                        pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
                };
-                reg_lcd: lcd-power {
+                reg_lcd: regulator@5 {
                        compatible = "regulator-fixed";
+                        reg = <5>;
                        regulator-name = "LCD POWER";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
@@ -98,8 +105,9 @@
                        enable-active-high;
                };
-                reg_lcd_reset: lcd-reset {
+                reg_lcd_reset: regulator@6 {
                        compatible = "regulator-fixed";
+                        reg = <6>;
                        regulator-name = "LCD RESET";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index f8e9b20f6982..90a579532b8b 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,6 +32,8 @@
                serial4 = &auart4;
                spi0 = &ssp1;
                spi1 = &ssp2;
+                usbphy0 = &usbphy0;
+                usbphy1 = &usbphy1;
        };
        cpus {
@@ -343,6 +345,19 @@
                                        fsl,pull-up = <MXS_PULL_DISABLE>;
                                };
+                                auart2_pins_a: auart2-pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_AUART2_RX__AUART2_RX
+                                                MX28_PAD_AUART2_TX__AUART2_TX
+                                                MX28_PAD_AUART2_CTS__AUART2_CTS
+                                                MX28_PAD_AUART2_RTS__AUART2_RTS
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
                                auart3_pins_a: auart3@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -655,6 +670,33 @@
                                        fsl,pull-up = <MXS_PULL_DISABLE>;
                                };
+                                lcdif_18bit_pins_a: lcdif-18bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_LCD_D00__LCD_D0
+                                                MX28_PAD_LCD_D01__LCD_D1
+                                                MX28_PAD_LCD_D02__LCD_D2
+                                                MX28_PAD_LCD_D03__LCD_D3
+                                                MX28_PAD_LCD_D04__LCD_D4
+                                                MX28_PAD_LCD_D05__LCD_D5
+                                                MX28_PAD_LCD_D06__LCD_D6
+                                                MX28_PAD_LCD_D07__LCD_D7
+                                                MX28_PAD_LCD_D08__LCD_D8
+                                                MX28_PAD_LCD_D09__LCD_D9
+                                                MX28_PAD_LCD_D10__LCD_D10
+                                                MX28_PAD_LCD_D11__LCD_D11
+                                                MX28_PAD_LCD_D12__LCD_D12
+                                                MX28_PAD_LCD_D13__LCD_D13
+                                                MX28_PAD_LCD_D14__LCD_D14
+                                                MX28_PAD_LCD_D15__LCD_D15
+                                                MX28_PAD_LCD_D16__LCD_D16
+                                                MX28_PAD_LCD_D17__LCD_D17
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
                                lcdif_16bit_pins_a: lcdif-16bit@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -743,7 +785,7 @@
                                        fsl,pull-up = <MXS_PULL_DISABLE>;
                                };
-                                usbphy0_pins_a: usbphy0@0 {
+                                usb0_pins_a: usb0@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
                                                MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
@@ -753,7 +795,7 @@
                                        fsl,pull-up = <MXS_PULL_DISABLE>;
                                };
-                                usbphy0_pins_b: usbphy0@1 {
+                                usb0_pins_b: usb0@1 {
                                        reg = <1>;
                                        fsl,pinmux-ids = <
                                                MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
@@ -763,7 +805,7 @@
                                        fsl,pull-up = <MXS_PULL_DISABLE>;
                                };
-                                usbphy1_pins_a: usbphy1@0 {
+                                usb1_pins_a: usb1@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
                                                MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
@@ -782,6 +824,17 @@
                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
                                        fsl,pull-up = <MXS_PULL_ENABLE>;
                                };
+                                usb0_id_pins_b: usb0id1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_PWM2__USB0_ID
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_12mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_ENABLE>;
+                                };
                        };
                        digctl: digctl@8001c000 {
@@ -946,6 +999,7 @@
                                                20 21 22 23 24 25>;
                                status = "disabled";
                                clocks = <&clks 41>;
+                                #io-channel-cells = <1>;
                        };
                        spdif: spdif@80054000 {
@@ -1130,4 +1184,9 @@
                        status = "disabled";
                };
        };
+        iio_hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&lradc 8>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
new file mode 100644
index 000000000000..906ae937b013
--- /dev/null
+++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include "imx35.dtsi"
+/ {
+        model = "Eukrea CPUIMX35";
+        compatible = "eukrea,cpuimx35", "fsl,imx35";
+        memory {
+                reg = <0x80000000 0x8000000>; /* 128M */
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        status = "okay";
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        pcf8563@51 {
+                compatible = "nxp,pcf8563";
+                reg = <0x51>;
+        };
+};
+&iomuxc {
+        imx35-eukrea {
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX35_PAD_FEC_TX_CLK__FEC_TX_CLK         0x80000000
+                                MX35_PAD_FEC_RX_CLK__FEC_RX_CLK         0x80000000
+                                MX35_PAD_FEC_RX_DV__FEC_RX_DV           0x80000000
+                                MX35_PAD_FEC_COL__FEC_COL               0x80000000
+                                MX35_PAD_FEC_RDATA0__FEC_RDATA_0        0x80000000
+                                MX35_PAD_FEC_TDATA0__FEC_TDATA_0        0x80000000
+                                MX35_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                                MX35_PAD_FEC_MDC__FEC_MDC               0x80000000
+                                MX35_PAD_FEC_MDIO__FEC_MDIO             0x80000000
+                                MX35_PAD_FEC_TX_ERR__FEC_TX_ERR         0x80000000
+                                MX35_PAD_FEC_RX_ERR__FEC_RX_ERR         0x80000000
+                                MX35_PAD_FEC_CRS__FEC_CRS               0x80000000
+                                MX35_PAD_FEC_RDATA1__FEC_RDATA_1        0x80000000
+                                MX35_PAD_FEC_TDATA1__FEC_TDATA_1        0x80000000
+                                MX35_PAD_FEC_RDATA2__FEC_RDATA_2        0x80000000
+                                MX35_PAD_FEC_TDATA2__FEC_TDATA_2        0x80000000
+                                MX35_PAD_FEC_RDATA3__FEC_RDATA_3        0x80000000
+                                MX35_PAD_FEC_TDATA3__FEC_TDATA_3        0x80000000
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX35_PAD_I2C1_CLK__I2C1_SCL             0x80000000
+                                MX35_PAD_I2C1_DAT__I2C1_SDA             0x80000000
+                        >;
+                };
+        };
+};
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
new file mode 100644
index 000000000000..1bdec21f4533
--- /dev/null
+++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx35-eukrea-cpuimx35.dtsi"
+/ {
+        model = "Eukrea CPUIMX35";
+        compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35";
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_bp1>;
+                bp1 {
+                        label = "BP1";
+                        gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+                        linux,code = <BTN_MISC>;
+                        gpio-key,wakeup;
+                        linux,input-type = <1>;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_led1>;
+                led1 {
+                        label = "led1";
+                        gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        cd-gpios = <&gpio3 24>;
+        status = "okay";
+};
+&i2c1 {
+        tlv320aic23: codec@1a {
+                compatible = "ti,tlv320aic23";
+                reg = <0x1a>;
+        };
+};
+&iomuxc {
+        imx35-eukrea {
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS       0x80000000
+                                MX35_PAD_STXD4__AUDMUX_AUD4_TXD         0x80000000
+                                MX35_PAD_SRXD4__AUDMUX_AUD4_RXD         0x80000000
+                                MX35_PAD_SCK4__AUDMUX_AUD4_TXC          0x80000000
+                        >;
+                };
+                pinctrl_bp1: bp1grp {
+                        fsl,pins = <MX35_PAD_LD19__GPIO3_25  0x80000000>;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX35_PAD_SD1_CMD__ESDHC1_CMD            0x80000000
+                                MX35_PAD_SD1_CLK__ESDHC1_CLK            0x80000000
+                                MX35_PAD_SD1_DATA0__ESDHC1_DAT0         0x80000000
+                                MX35_PAD_SD1_DATA1__ESDHC1_DAT1         0x80000000
+                                MX35_PAD_SD1_DATA2__ESDHC1_DAT2         0x80000000
+                                MX35_PAD_SD1_DATA3__ESDHC1_DAT3         0x80000000
+                                MX35_PAD_LD18__GPIO3_24                 0x80000000 /* CD */
+                        >;
+                };
+                pinctrl_led1: led1grp {
+                        fsl,pins = <MX35_PAD_LD23__GPIO3_29  0x80000000>;
+                };
+                pinctrl_reg_lcd_3v3: reg-lcd-3v3 {
+                        fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX35_PAD_TXD1__UART1_TXD_MUX            0x1c5
+                                MX35_PAD_RXD1__UART1_RXD_MUX            0x1c5
+                                MX35_PAD_CTS1__UART1_CTS                0x1c5
+                                MX35_PAD_RTS1__UART1_RTS                0x1c5
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX35_PAD_RXD2__UART2_RXD_MUX            0x1c5
+                                MX35_PAD_TXD2__UART2_TXD_MUX            0x1c5
+                                MX35_PAD_RTS2__UART2_RTS                0x1c5
+                                MX35_PAD_CTS2__UART2_CTS                0x1c5
+                        >;
+                };
+        };
+};
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
new file mode 100644
index 000000000000..88b218f8f810
--- /dev/null
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -0,0 +1,359 @@
+/*
+ * Copyright 2012 Steffen Trumtrar, Pengutronix
+ *
+ * based on imx27.dtsi
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include "skeleton.dtsi"
+#include "imx35-pinfunc.h"
+/ {
+        aliases {
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                spi0 = &spi1;
+                spi1 = &spi2;
+        };
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
+                        compatible = "arm,arm1136";
+                        device_type = "cpu";
+                };
+        };
+        avic: avic-interrupt-controller@68000000 {
+                compatible = "fsl,imx35-avic", "fsl,avic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x68000000 0x10000000>;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&avic>;
+                ranges;
+                L2: l2-cache@30000000 {
+                        compatible = "arm,l210-cache";
+                        reg = <0x30000000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+                aips1: aips@43f00000 {
+                        compatible = "fsl,aips", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x43f00000 0x100000>;
+                        ranges;
+                        i2c1: i2c@43f80000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
+                                reg = <0x43f80000 0x4000>;
+                                clocks = <&clks 51>;
+                                clock-names = "ipg_per";
+                                interrupts = <10>;
+                                status = "disabled";
+                        };
+                        i2c3: i2c@43f84000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
+                                reg = <0x43f84000 0x4000>;
+                                clocks = <&clks 53>;
+                                clock-names = "ipg_per";
+                                interrupts = <3>;
+                                status = "disabled";
+                        };
+                        uart1: serial@43f90000 {
+                                compatible = "fsl,imx35-uart", "fsl,imx21-uart";
+                                reg = <0x43f90000 0x4000>;
+                                clocks = <&clks 9>, <&clks 70>;
+                                clock-names = "ipg", "per";
+                                interrupts = <45>;
+                                status = "disabled";
+                        };
+                        uart2: serial@43f94000 {
+                                compatible = "fsl,imx35-uart", "fsl,imx21-uart";
+                                reg = <0x43f94000 0x4000>;
+                                clocks = <&clks 9>, <&clks 71>;
+                                clock-names = "ipg", "per";
+                                interrupts = <32>;
+                                status = "disabled";
+                        };
+                        i2c2: i2c@43f98000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
+                                reg = <0x43f98000 0x4000>;
+                                clocks = <&clks 52>;
+                                clock-names = "ipg_per";
+                                interrupts = <4>;
+                                status = "disabled";
+                        };
+                        ssi1: ssi@43fa0000 {
+                                compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
+                                reg = <0x43fa0000 0x4000>;
+                                interrupts = <11>;
+                                clocks = <&clks 68>;
+                                dmas = <&sdma 28 0 0>,
+                                       <&sdma 29 0 0>;
+                                dma-names = "rx", "tx";
+                                fsl,fifo-depth = <15>;
+                                status = "disabled";
+                        };
+                        spi1: cspi@43fa4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx35-cspi";
+                                reg = <0x43fa4000 0x4000>;
+                                clocks = <&clks 35 &clks 35>;
+                                clock-names = "ipg", "per";
+                                interrupts = <14>;
+                                status = "disabled";
+                        };
+                        iomuxc: iomuxc@43fac000 {
+                                compatible = "fsl,imx35-iomuxc";
+                                reg = <0x43fac000 0x4000>;
+                        };
+                };
+                spba: spba-bus@50000000 {
+                        compatible = "fsl,spba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x50000000 0x100000>;
+                        ranges;
+                        uart3: serial@5000c000 {
+                                compatible = "fsl,imx35-uart", "fsl,imx21-uart";
+                                reg = <0x5000c000 0x4000>;
+                                clocks = <&clks 9>, <&clks 72>;
+                                clock-names = "ipg", "per";
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+                        spi2: cspi@50010000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx35-cspi";
+                                reg = <0x50010000 0x4000>;
+                                interrupts = <13>;
+                                clocks = <&clks 36 &clks 36>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        fec: fec@50038000 {
+                                compatible = "fsl,imx35-fec", "fsl,imx27-fec";
+                                reg = <0x50038000 0x4000>;
+                                clocks = <&clks 46>, <&clks 8>;
+                                clock-names = "ipg", "ahb";
+                                interrupts = <57>;
+                                status = "disabled";
+                        };
+                };
+                aips2: aips@53f00000 {
+                        compatible = "fsl,aips", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x53f00000 0x100000>;
+                        ranges;
+                        clks: ccm@53f80000 {
+                                compatible = "fsl,imx35-ccm";
+                                reg = <0x53f80000 0x4000>;
+                                interrupts = <31>;
+                                #clock-cells = <1>;
+                        };
+                        gpio3: gpio@53fa4000 {
+                                compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
+                                reg = <0x53fa4000 0x4000>;
+                                interrupts = <56>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        esdhc1: esdhc@53fb4000 {
+                                compatible = "fsl,imx35-esdhc";
+                                reg = <0x53fb4000 0x4000>;
+                                interrupts = <7>;
+                                clocks = <&clks 9>, <&clks 8>, <&clks 43>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+                        esdhc2: esdhc@53fb8000 {
+                                compatible = "fsl,imx35-esdhc";
+                                reg = <0x53fb8000 0x4000>;
+                                interrupts = <8>;
+                                clocks = <&clks 9>, <&clks 8>, <&clks 44>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+                        esdhc3: esdhc@53fbc000 {
+                                compatible = "fsl,imx35-esdhc";
+                                reg = <0x53fbc000 0x4000>;
+                                interrupts = <9>;
+                                clocks = <&clks 9>, <&clks 8>, <&clks 45>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+                        audmux: audmux@53fc4000 {
+                                compatible = "fsl,imx35-audmux", "fsl,imx31-audmux";
+                                reg = <0x53fc4000 0x4000>;
+                                status = "disabled";
+                        };
+                        gpio1: gpio@53fcc000 {
+                                compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
+                                reg = <0x53fcc000 0x4000>;
+                                interrupts = <52>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio2: gpio@53fd0000 {
+                                compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
+                                reg = <0x53fd0000 0x4000>;
+                                interrupts = <51>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        sdma: sdma@53fd4000 {
+                                compatible = "fsl,imx35-sdma";
+                                reg = <0x53fd4000 0x4000>;
+                                clocks = <&clks 9>, <&clks 65>;
+                                clock-names = "ipg", "ahb";
+                                #dma-cells = <3>;
+                                interrupts = <34>;
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin";
+                        };
+                        wdog: wdog@53fdc000 {
+                                compatible = "fsl,imx35-wdt", "fsl,imx21-wdt";
+                                reg = <0x53fdc000 0x4000>;
+                                clocks = <&clks 74>;
+                                clock-names = "";
+                                interrupts = <55>;
+                        };
+                        can1: can@53fe4000 {
+                                compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x53fe4000 0x1000>;
+                                clocks = <&clks 33>;
+                                clock-names = "ipg";
+                                interrupts = <43>;
+                                status = "disabled";
+                        };
+                        can2: can@53fe8000 {
+                                compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x53fe8000 0x1000>;
+                                clocks = <&clks 34>;
+                                clock-names = "ipg";
+                                interrupts = <44>;
+                                status = "disabled";
+                        };
+                        usbotg: usb@53ff4000 {
+                                compatible = "fsl,imx35-usb", "fsl,imx27-usb";
+                                reg = <0x53ff4000 0x0200>;
+                                interrupts = <37>;
+                                clocks = <&clks 9>, <&clks 73>, <&clks 28>;
+                                clock-names = "ipg", "ahb", "per";
+                                fsl,usbmisc = <&usbmisc 0>;
+                                status = "disabled";
+                        };
+                        usbhost1: usb@53ff4400 {
+                                compatible = "fsl,imx35-usb", "fsl,imx27-usb";
+                                reg = <0x53ff4400 0x0200>;
+                                interrupts = <35>;
+                                clocks = <&clks 9>, <&clks 73>, <&clks 28>;
+                                clock-names = "ipg", "ahb", "per";
+                                fsl,usbmisc = <&usbmisc 1>;
+                                status = "disabled";
+                        };
+                        usbmisc: usbmisc@53ff4600 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx35-usbmisc";
+                                clocks = <&clks 9>, <&clks 73>, <&clks 28>;
+                                clock-names = "ipg", "ahb", "per";
+                                reg = <0x53ff4600 0x00f>;
+                        };
+                };
+                emi@80000000 { /* External Memory Interface */
+                        compatible = "fsl,emi", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x80000000 0x40000000>;
+                        ranges;
+                        nfc: nand@bb000000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "fsl,imx35-nand", "fsl,imx25-nand";
+                                reg = <0xbb000000 0x2000>;
+                                clocks = <&clks 29>;
+                                clock-names = "";
+                                interrupts = <33>;
+                                status = "disabled";
+                        };
+                        weim: weim@b8002000 {
+                                #address-cells = <2>;
+                                #size-cells = <1>;
+                                clocks = <&clks 0>;
+                                compatible = "fsl,imx35-weim", "fsl,imx27-weim";
+                                reg = <0xb8002000 0x1000>;
+                                ranges = <
+                                        0 0 0xa0000000 0x8000000
+                                        1 0 0xa8000000 0x8000000
+                                        2 0 0xb0000000 0x2000000
+                                        3 0 0xb2000000 0x2000000
+                                        4 0 0xb4000000 0x2000000
+                                        5 0 0xb6000000 0x2000000
+                                >;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
new file mode 100644
index 000000000000..1b22512c91bd
--- /dev/null
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx50.dtsi"
+/ {
+        model = "Freescale i.MX50 Evaluation Kit";
+        compatible = "fsl,imx50-evk", "fsl,imx50";
+        memory {
+                reg = <0x70000000 0x80000000>;
+        };
+};
+&cspi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cspi>;
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
+        status = "okay";
+        flash: m25p32@1 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "m25p32", "m25p80";
+                spi-max-frequency = <25000000>;
+                reg = <1>;
+                partition@0 {
+                        label = "bootloader";
+                        reg = <0x0 0x100000>;
+                        read-only;
+                };
+                partition@100000 {
+                        label = "kernel";
+                        reg = <0x100000 0x300000>;
+                };
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        phy-mode = "rmii";
+        phy-reset-gpios = <&gpio4 12 0>;
+        status = "okay";
+};
+&iomuxc {
+        imx50-evk {
+                pinctrl_cspi: cspigrp {
+                        fsl,pins = <
+                                MX50_PAD_CSPI_SCLK__CSPI_SCLK           0x00
+                                MX50_PAD_CSPI_MISO__CSPI_MISO           0x00
+                                MX50_PAD_CSPI_MOSI__CSPI_MOSI           0x00
+                                MX50_PAD_CSPI_SS0__GPIO4_11             0xc4
+                                MX50_PAD_ECSPI1_MOSI__CSPI_SS1          0xf4
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX50_PAD_SSI_RXFS__FEC_MDC              0x80
+                                MX50_PAD_SSI_RXC__FEC_MDIO              0x80
+                                MX50_PAD_DISP_D0__FEC_TX_CLK            0x80
+                                MX50_PAD_DISP_D1__FEC_RX_ERR            0x80
+                                MX50_PAD_DISP_D2__FEC_RX_DV             0x80
+                                MX50_PAD_DISP_D3__FEC_RDATA_1           0x80
+                                MX50_PAD_DISP_D4__FEC_RDATA_0           0x80
+                                MX50_PAD_DISP_D5__FEC_TX_EN             0x80
+                                MX50_PAD_DISP_D6__FEC_TDATA_1           0x80
+                                MX50_PAD_DISP_D7__FEC_TDATA_0           0x80
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX50_PAD_UART1_TXD__UART1_TXD_MUX       0x1e4
+                                MX50_PAD_UART1_RXD__UART1_RXD_MUX       0x1e4
+                                MX50_PAD_UART1_RTS__UART1_RTS           0x1e4
+                                MX50_PAD_UART1_CTS__UART1_CTS           0x1e4
+                        >;
+                };
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&usbh1 {
+        status = "okay";
+};
+&usbh2 {
+        status = "okay";
+};
+&usbh3 {
+        status = "okay";
+};
+&usbotg {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/imx50-pinfunc.h
new file mode 100644
index 000000000000..97e6e7f4ebdd
--- /dev/null
+++ b/arch/arm/boot/dts/imx50-pinfunc.h
@@ -0,0 +1,923 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __DTS_IMX50_PINFUNC_H
+#define __DTS_IMX50_PINFUNC_H
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX50_PAD_KEY_COL0__KPP_COL_0                            0x020 0x2cc 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL0__GPIO4_0                              0x020 0x2cc 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE                        0x020 0x2cc 0x000 0x2 0x0
+#define MX50_PAD_KEY_COL0__CTI_TRIGIN7                          0x020 0x2cc 0x000 0x6 0x0
+#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY                      0x020 0x2cc 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW0__KPP_ROW_0                            0x024 0x2d0 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW0__GPIO4_1                              0x024 0x2d0 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE                        0x024 0x2d0 0x000 0x2 0x0
+#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7                      0x024 0x2d0 0x000 0x6 0x0
+#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID                      0x024 0x2d0 0x000 0x7 0x0
+#define MX50_PAD_KEY_COL1__KPP_COL_1                            0x028 0x2d4 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL1__GPIO4_2                              0x028 0x2d4 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0                      0x028 0x2d4 0x000 0x2 0x0
+#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6                     0x028 0x2d4 0x000 0x6 0x0
+#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE                     0x028 0x2d4 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW1__KPP_ROW_1                            0x02c 0x2d8 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW1__GPIO4_3                              0x02c 0x2d8 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1                      0x02c 0x2d8 0x000 0x2 0x0
+#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7                     0x02c 0x2d8 0x000 0x6 0x0
+#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR                      0x02c 0x2d8 0x000 0x7 0x0
+#define MX50_PAD_KEY_COL2__KPP_COL_1                            0x030 0x2dc 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL2__GPIO4_4                              0x030 0x2dc 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2                      0x030 0x2dc 0x000 0x2 0x0
+#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6                         0x030 0x2dc 0x000 0x6 0x0
+#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK                     0x030 0x2dc 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW2__KPP_ROW_2                            0x034 0x2e0 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW2__GPIO4_5                              0x034 0x2e0 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3                      0x034 0x2e0 0x000 0x2 0x0
+#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7                         0x034 0x2e0 0x000 0x6 0x0
+#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0                  0x034 0x2e0 0x000 0x7 0x0
+#define MX50_PAD_KEY_COL3__KPP_COL_2                            0x038 0x2e4 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL3__GPIO4_6                              0x038 0x2e4 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0                     0x038 0x2e4 0x7b4 0x2 0x0
+#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0                     0x038 0x2e4 0x7b8 0x6 0x0
+#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1                  0x038 0x2e4 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW3__KPP_ROW_3                            0x03c 0x2e8 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW3__GPIO4_7                              0x03c 0x2e8 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS                        0x03c 0x2e8 0x7b0 0x2 0x0
+#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1                     0x03c 0x2e8 0x7bc 0x6 0x0
+#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID                    0x03c 0x2e8 0x000 0x7 0x0
+#define MX50_PAD_I2C1_SCL__I2C1_SCL                             0x040 0x2ec 0x000 0x0 0x0
+#define MX50_PAD_I2C1_SCL__GPIO6_18                             0x040 0x2ec 0x000 0x1 0x0
+#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX                        0x040 0x2ec 0x7cc 0x2 0x0
+#define MX50_PAD_I2C1_SDA__I2C1_SDA                             0x044 0x2f0 0x000 0x0 0x0
+#define MX50_PAD_I2C1_SDA__GPIO6_19                             0x044 0x2f0 0x000 0x1 0x0
+#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX                        0x044 0x2f0 0x7cc 0x2 0x1
+#define MX50_PAD_I2C2_SCL__I2C2_SCL                             0x048 0x2f4 0x000 0x0 0x0
+#define MX50_PAD_I2C2_SCL__GPIO6_20                             0x048 0x2f4 0x000 0x1 0x0
+#define MX50_PAD_I2C2_SCL__UART2_CTS                            0x048 0x2f4 0x000 0x2 0x0
+#define MX50_PAD_I2C2_SDA__I2C2_SDA                             0x04c 0x2f8 0x000 0x0 0x0
+#define MX50_PAD_I2C2_SDA__GPIO6_21                             0x04c 0x2f8 0x000 0x1 0x0
+#define MX50_PAD_I2C2_SDA__UART2_RTS                            0x04c 0x2f8 0x7c8 0x2 0x1
+#define MX50_PAD_I2C3_SCL__I2C3_SCL                             0x050 0x2fc 0x000 0x0 0x0
+#define MX50_PAD_I2C3_SCL__GPIO6_22                             0x050 0x2fc 0x000 0x1 0x0
+#define MX50_PAD_I2C3_SCL__FEC_MDC                              0x050 0x2fc 0x000 0x2 0x0
+#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY                         0x050 0x2fc 0x000 0x3 0x0
+#define MX50_PAD_I2C3_SCL__GPT_CAPIN1                           0x050 0x2fc 0x000 0x5 0x0
+#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0           0x050 0x2fc 0x000 0x6 0x0
+#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC                     0x050 0x2fc 0x7e8 0x7 0x0
+#define MX50_PAD_I2C3_SDA__I2C3_SDA                             0x054 0x300 0x000 0x0 0x0
+#define MX50_PAD_I2C3_SDA__GPIO6_23                             0x054 0x300 0x000 0x1 0x0
+#define MX50_PAD_I2C3_SDA__FEC_MDIO                             0x054 0x300 0x774 0x2 0x0
+#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT                     0x054 0x300 0x000 0x3 0x0
+#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB                       0x054 0x300 0x000 0x4 0x0
+#define MX50_PAD_I2C3_SDA__GPT_CAPIN2                           0x054 0x300 0x000 0x5 0x0
+#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1           0x054 0x300 0x000 0x6 0x0
+#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR                    0x054 0x300 0x000 0x7 0x0
+#define MX50_PAD_PWM1__PWM1_PWMO                                0x058 0x304 0x000 0x0 0x0
+#define MX50_PAD_PWM1__GPIO6_24                                 0x058 0x304 0x000 0x1 0x0
+#define MX50_PAD_PWM1__USBOH1_USBOTG_OC                         0x058 0x304 0x7e8 0x2 0x1
+#define MX50_PAD_PWM1__GPT_CMPOUT1                              0x058 0x304 0x000 0x5 0x0
+#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2               0x058 0x304 0x000 0x6 0x0
+#define MX50_PAD_PWM1__SJC_FAIL                                 0x058 0x304 0x000 0x7 0x0
+#define MX50_PAD_PWM2__PWM2_PWMO                                0x05c 0x308 0x000 0x0 0x0
+#define MX50_PAD_PWM2__GPIO6_25                                 0x05c 0x308 0x000 0x1 0x0
+#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR                        0x05c 0x308 0x000 0x2 0x0
+#define MX50_PAD_PWM2__GPT_CMPOUT2                              0x05c 0x308 0x000 0x5 0x0
+#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3               0x05c 0x308 0x000 0x6 0x0
+#define MX50_PAD_PWM2__SRC_ANY_PU_RST                           0x05c 0x308 0x000 0x7 0x0
+#define MX50_PAD_OWIRE__OWIRE_LINE                              0x060 0x30c 0x000 0x0 0x0
+#define MX50_PAD_OWIRE__GPIO6_26                                0x060 0x30c 0x000 0x1 0x0
+#define MX50_PAD_OWIRE__USBOH1_USBH1_OC                         0x060 0x30c 0x000 0x2 0x0
+#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK                        0x060 0x30c 0x000 0x3 0x0
+#define MX50_PAD_OWIRE__EPDC_PWRIRQ                             0x060 0x30c 0x000 0x4 0x0
+#define MX50_PAD_OWIRE__GPT_CMPOUT3                             0x060 0x30c 0x000 0x5 0x0
+#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4              0x060 0x30c 0x000 0x6 0x0
+#define MX50_PAD_OWIRE__SJC_JTAG_ACT                            0x060 0x30c 0x000 0x7 0x0
+#define MX50_PAD_EPITO__EPIT1_EPITO                             0x064 0x310 0x000 0x0 0x0
+#define MX50_PAD_EPITO__GPIO6_27                                0x064 0x310 0x000 0x1 0x0
+#define MX50_PAD_EPITO__USBOH1_USBH1_PWR                        0x064 0x310 0x000 0x2 0x0
+#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK                        0x064 0x310 0x000 0x3 0x0
+#define MX50_PAD_EPITO__DPLLIP1_TOG_EN                          0x064 0x310 0x000 0x4 0x0
+#define MX50_PAD_EPITO__GPT_CLK_IN                              0x064 0x310 0x000 0x5 0x0
+#define MX50_PAD_EPITO__PMU_IRQ_B                               0x064 0x310 0x000 0x6 0x0
+#define MX50_PAD_EPITO__SJC_DE_B                                0x064 0x310 0x000 0x7 0x0
+#define MX50_PAD_WDOG__WDOG1_WDOG_B                             0x068 0x314 0x000 0x0 0x0
+#define MX50_PAD_WDOG__GPIO6_28                                 0x068 0x314 0x000 0x1 0x0
+#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB                     0x068 0x314 0x000 0x2 0x0
+#define MX50_PAD_WDOG__CCM_XTAL32K                              0x068 0x314 0x000 0x6 0x0
+#define MX50_PAD_WDOG__SJC_DONE                                 0x068 0x314 0x000 0x7 0x0
+#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS                     0x06c 0x318 0x000 0x0 0x0
+#define MX50_PAD_SSI_TXFS__GPIO6_0                              0x06c 0x318 0x000 0x1 0x0
+#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1                    0x06c 0x318 0x000 0x6 0x0
+#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8                    0x06c 0x318 0x000 0x7 0x0
+#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC                       0x070 0x31c 0x000 0x0 0x0
+#define MX50_PAD_SSI_TXC__GPIO6_1                               0x070 0x31c 0x000 0x1 0x0
+#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0                     0x070 0x31c 0x000 0x6 0x0
+#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9                     0x070 0x31c 0x000 0x7 0x0
+#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD                       0x074 0x320 0x000 0x0 0x0
+#define MX50_PAD_SSI_TXD__GPIO6_2                               0x074 0x320 0x000 0x1 0x0
+#define MX50_PAD_SSI_TXD__CSPI_RDY                              0x074 0x320 0x6e8 0x4 0x0
+#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10                    0x074 0x320 0x000 0x7 0x0
+#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD                       0x078 0x324 0x000 0x0 0x0
+#define MX50_PAD_SSI_RXD__GPIO6_3                               0x078 0x324 0x000 0x1 0x0
+#define MX50_PAD_SSI_RXD__CSPI_SS3                              0x078 0x324 0x6f4 0x4 0x0
+#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11                    0x078 0x324 0x000 0x7 0x0
+#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS                     0x07c 0x328 0x000 0x0 0x0
+#define MX50_PAD_SSI_RXFS__GPIO6_4                              0x07c 0x328 0x000 0x1 0x0
+#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX                        0x07c 0x328 0x7e4 0x2 0x0
+#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6                         0x07c 0x328 0x804 0x3 0x0
+#define MX50_PAD_SSI_RXFS__CSPI_SS2                             0x07c 0x328 0x6f0 0x4 0x0
+#define MX50_PAD_SSI_RXFS__FEC_COL                              0x07c 0x328 0x770 0x5 0x0
+#define MX50_PAD_SSI_RXFS__FEC_MDC                              0x07c 0x328 0x000 0x6 0x0
+#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12                   0x07c 0x328 0x000 0x7 0x0
+#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC                       0x080 0x32c 0x000 0x0 0x0
+#define MX50_PAD_SSI_RXC__GPIO6_5                               0x080 0x32c 0x000 0x1 0x0
+#define MX50_PAD_SSI_RXC__UART5_RXD_MUX                         0x080 0x32c 0x7e4 0x2 0x1
+#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7                          0x080 0x32c 0x808 0x3 0x0
+#define MX50_PAD_SSI_RXC__CSPI_SS1                              0x080 0x32c 0x6ec 0x4 0x0
+#define MX50_PAD_SSI_RXC__FEC_RX_CLK                            0x080 0x32c 0x780 0x5 0x0
+#define MX50_PAD_SSI_RXC__FEC_MDIO                              0x080 0x32c 0x774 0x6 0x1
+#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13                    0x080 0x32c 0x000 0x7 0x0
+#define MX50_PAD_UART1_TXD__UART1_TXD_MUX                       0x084 0x330 0x7c4 0x0 0x0
+#define MX50_PAD_UART1_TXD__GPIO6_6                             0x084 0x330 0x000 0x1 0x0
+#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14                  0x084 0x330 0x000 0x7 0x0
+#define MX50_PAD_UART1_RXD__UART1_RXD_MUX                       0x088 0x334 0x7c4 0x0 0x1
+#define MX50_PAD_UART1_RXD__GPIO6_7                             0x088 0x334 0x000 0x1 0x0
+#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15                  0x088 0x334 0x000 0x7 0x0
+#define MX50_PAD_UART1_CTS__UART1_CTS                           0x08c 0x338 0x000 0x0 0x0
+#define MX50_PAD_UART1_CTS__GPIO6_8                             0x08c 0x338 0x000 0x1 0x0
+#define MX50_PAD_UART1_CTS__UART5_TXD_MUX                       0x08c 0x338 0x7e4 0x2 0x2
+#define MX50_PAD_UART1_CTS__ESDHC4_DAT4                         0x08c 0x338 0x760 0x4 0x0
+#define MX50_PAD_UART1_CTS__ESDHC4_CMD                          0x08c 0x338 0x74c 0x5 0x0
+#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8                   0x08c 0x338 0x000 0x7 0x0
+#define MX50_PAD_UART1_RTS__UART1_RTS                           0x090 0x33c 0x7c0 0x0 0x3
+#define MX50_PAD_UART1_RTS__GPIO6_9                             0x090 0x33c 0x000 0x1 0x0
+#define MX50_PAD_UART1_RTS__UART5_RXD_MUX                       0x090 0x33c 0x7e4 0x2 0x3
+#define MX50_PAD_UART1_RTS__ESDHC4_DAT5                         0x090 0x33c 0x764 0x4 0x0
+#define MX50_PAD_UART1_RTS__ESDHC4_CLK                          0x090 0x33c 0x748 0x5 0x0
+#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9                   0x090 0x33c 0x000 0x7 0x0
+#define MX50_PAD_UART2_TXD__UART2_TXD_MUX                       0x094 0x340 0x7cc 0x0 0x2
+#define MX50_PAD_UART2_TXD__GPIO6_10                            0x094 0x340 0x000 0x1 0x0
+#define MX50_PAD_UART2_TXD__ESDHC4_DAT6                         0x094 0x340 0x768 0x4 0x0
+#define MX50_PAD_UART2_TXD__ESDHC4_DAT4                         0x094 0x340 0x760 0x5 0x1
+#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10                  0x094 0x340 0x000 0x7 0x0
+#define MX50_PAD_UART2_RXD__UART2_RXD_MUX                       0x098 0x344 0x7cc 0x0 0x3
+#define MX50_PAD_UART2_RXD__GPIO6_11                            0x098 0x344 0x000 0x1 0x0
+#define MX50_PAD_UART2_RXD__ESDHC4_DAT7                         0x098 0x344 0x76c 0x4 0x0
+#define MX50_PAD_UART2_RXD__ESDHC4_DAT5                         0x098 0x344 0x764 0x5 0x1
+#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11                  0x098 0x344 0x000 0x7 0x0
+#define MX50_PAD_UART2_CTS__UART2_CTS                           0x09c 0x348 0x000 0x0 0x0
+#define MX50_PAD_UART2_CTS__GPIO6_12                            0x09c 0x348 0x000 0x1 0x0
+#define MX50_PAD_UART2_CTS__ESDHC4_CMD                          0x09c 0x348 0x74c 0x4 0x1
+#define MX50_PAD_UART2_CTS__ESDHC4_DAT6                         0x09c 0x348 0x768 0x5 0x1
+#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12                  0x09c 0x348 0x000 0x7 0x0
+#define MX50_PAD_UART2_RTS__UART2_RTS                           0x0a0 0x34c 0x7c8 0x0 0x2
+#define MX50_PAD_UART2_RTS__GPIO6_13                            0x0a0 0x34c 0x000 0x1 0x0
+#define MX50_PAD_UART2_RTS__ESDHC4_CLK                          0x0a0 0x34c 0x748 0x4 0x1
+#define MX50_PAD_UART2_RTS__ESDHC4_DAT7                         0x0a0 0x34c 0x76c 0x5 0x1
+#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13                  0x0a0 0x34c 0x000 0x7 0x0
+#define MX50_PAD_UART3_TXD__UART3_TXD_MUX                       0x0a4 0x350 0x7d4 0x0 0x0
+#define MX50_PAD_UART3_TXD__GPIO6_14                            0x0a4 0x350 0x000 0x1 0x0
+#define MX50_PAD_UART3_TXD__ESDHC1_DAT4                         0x0a4 0x350 0x000 0x3 0x0
+#define MX50_PAD_UART3_TXD__ESDHC4_DAT0                         0x0a4 0x350 0x000 0x4 0x0
+#define MX50_PAD_UART3_TXD__ESDHC2_WP                           0x0a4 0x350 0x744 0x5 0x0
+#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12                       0x0a4 0x350 0x81c 0x6 0x0
+#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14                  0x0a4 0x350 0x000 0x7 0x0
+#define MX50_PAD_UART3_RXD__UART3_RXD_MUX                       0x0a8 0x354 0x7d4 0x0 0x1
+#define MX50_PAD_UART3_RXD__GPIO6_15                            0x0a8 0x354 0x000 0x1 0x0
+#define MX50_PAD_UART3_RXD__ESDHC1_DAT5                         0x0a8 0x354 0x000 0x3 0x0
+#define MX50_PAD_UART3_RXD__ESDHC4_DAT1                         0x0a8 0x354 0x754 0x4 0x0
+#define MX50_PAD_UART3_RXD__ESDHC2_CD                           0x0a8 0x354 0x740 0x5 0x0
+#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13                       0x0a8 0x354 0x820 0x6 0x0
+#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15                  0x0a8 0x354 0x000 0x7 0x0
+#define MX50_PAD_UART4_TXD__UART4_TXD_MUX                       0x0ac 0x358 0x7dc 0x0 0x0
+#define MX50_PAD_UART4_TXD__GPIO6_16                            0x0ac 0x358 0x000 0x1 0x0
+#define MX50_PAD_UART4_TXD__UART3_CTS                           0x0ac 0x358 0x7d0 0x2 0x0
+#define MX50_PAD_UART4_TXD__ESDHC1_DAT6                         0x0ac 0x358 0x000 0x3 0x0
+#define MX50_PAD_UART4_TXD__ESDHC4_DAT2                         0x0ac 0x358 0x758 0x4 0x0
+#define MX50_PAD_UART4_TXD__ESDHC2_LCTL                         0x0ac 0x358 0x000 0x5 0x0
+#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14                       0x0ac 0x358 0x824 0x6 0x0
+#define MX50_PAD_UART4_RXD__UART4_RXD_MUX                       0x0b0 0x35c 0x7dc 0x0 0x1
+#define MX50_PAD_UART4_RXD__GPIO6_17                            0x0b0 0x35c 0x000 0x1 0x0
+#define MX50_PAD_UART4_RXD__UART3_RTS                           0x0b0 0x35c 0x7d0 0x2 0x1
+#define MX50_PAD_UART4_RXD__ESDHC1_DAT7                         0x0b0 0x35c 0x000 0x3 0x0
+#define MX50_PAD_UART4_RXD__ESDHC4_DAT3                         0x0b0 0x35c 0x75c 0x4 0x0
+#define MX50_PAD_UART4_RXD__ESDHC1_LCTL                         0x0b0 0x35c 0x000 0x5 0x0
+#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15                       0x0b0 0x35c 0x828 0x6 0x0
+#define MX50_PAD_CSPI_SCLK__CSPI_SCLK                           0x0b4 0x360 0x000 0x0 0x0
+#define MX50_PAD_CSPI_SCLK__GPIO4_8                             0x0b4 0x360 0x000 0x1 0x0
+#define MX50_PAD_CSPI_MOSI__CSPI_MOSI                           0x0b8 0x364 0x000 0x0 0x0
+#define MX50_PAD_CSPI_MOSI__GPIO4_9                             0x0b8 0x364 0x000 0x1 0x0
+#define MX50_PAD_CSPI_MISO__CSPI_MISO                           0x0bc 0x368 0x000 0x0 0x0
+#define MX50_PAD_CSPI_MISO__GPIO4_10                            0x0bc 0x368 0x000 0x1 0x0
+#define MX50_PAD_CSPI_SS0__CSPI_SS0                             0x0c0 0x36c 0x000 0x0 0x0
+#define MX50_PAD_CSPI_SS0__GPIO4_11                             0x0c0 0x36c 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK                       0x0c4 0x370 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_SCLK__GPIO4_12                          0x0c4 0x370 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY                          0x0c4 0x370 0x6e8 0x2 0x1
+#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY                        0x0c4 0x370 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_SCLK__UART3_RTS                         0x0c4 0x370 0x7d0 0x4 0x2
+#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6                       0x0c4 0x370 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8                      0x0c4 0x370 0x80c 0x7 0x0
+#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI                       0x0c8 0x374 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_MOSI__GPIO4_13                          0x0c8 0x374 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1                          0x0c8 0x374 0x6ec 0x2 0x1
+#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1                        0x0c8 0x374 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_MOSI__UART3_CTS                         0x0c8 0x374 0x000 0x4 0x0
+#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7                       0x0c8 0x374 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9                      0x0c8 0x374 0x810 0x7 0x0
+#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO                       0x0cc 0x378 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_MISO__GPIO4_14                          0x0cc 0x378 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_MISO__CSPI_SS2                          0x0cc 0x378 0x6f0 0x2 0x1
+#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2                        0x0cc 0x378 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_MISO__UART4_RTS                         0x0cc 0x378 0x7d8 0x4 0x0
+#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8                       0x0cc 0x378 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10                     0x0cc 0x378 0x814 0x7 0x0
+#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0                         0x0d0 0x37c 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_SS0__GPIO4_15                           0x0d0 0x37c 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_SS0__CSPI_SS3                           0x0d0 0x37c 0x6f4 0x2 0x1
+#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3                         0x0d0 0x37c 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_SS0__UART4_CTS                          0x0d0 0x37c 0x000 0x4 0x0
+#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9                        0x0d0 0x37c 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11                      0x0d0 0x37c 0x818 0x7 0x0
+#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK                       0x0d4 0x380 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_SCLK__GPIO4_16                          0x0d4 0x380 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN                     0x0d4 0x380 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY                        0x0d4 0x380 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_SCLK__UART5_RTS                         0x0d4 0x380 0x7e0 0x4 0x0
+#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK                     0x0d4 0x380 0x000 0x5 0x0
+#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4                   0x0d4 0x380 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8                      0x0d4 0x380 0x80c 0x7 0x1
+#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI                       0x0d8 0x384 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_MOSI__GPIO4_17                          0x0d8 0x384 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E                       0x0d8 0x384 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1                        0x0d8 0x384 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_MOSI__UART5_CTS                         0x0d8 0x384 0x7e0 0x4 0x1
+#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE                     0x0d8 0x384 0x000 0x5 0x0
+#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5                   0x0d8 0x384 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9                      0x0d8 0x384 0x810 0x7 0x1
+#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO                       0x0dc 0x388 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_MISO__GPIO4_18                          0x0dc 0x388 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS                         0x0dc 0x388 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2                        0x0dc 0x388 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX                     0x0dc 0x388 0x7e4 0x4 0x4
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC                      0x0dc 0x388 0x73c 0x5 0x0
+#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6                   0x0dc 0x388 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10                     0x0dc 0x388 0x814 0x7 0x1
+#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0                         0x0e0 0x38c 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_SS0__GPIO4_19                           0x0e0 0x38c 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS                          0x0e0 0x38c 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3                         0x0e0 0x38c 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX                      0x0e0 0x38c 0x7e4 0x4 0x5
+#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC                       0x0e0 0x38c 0x6f8 0x5 0x0
+#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7                    0x0e0 0x38c 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11                      0x0e0 0x38c 0x818 0x7 0x1
+#define MX50_PAD_SD1_CLK__ESDHC1_CLK                            0x0e4 0x390 0x000 0x0 0x0
+#define MX50_PAD_SD1_CLK__GPIO5_0                               0x0e4 0x390 0x000 0x1 0x0
+#define MX50_PAD_SD1_CLK__CCM_CLKO                              0x0e4 0x390 0x000 0x7 0x0
+#define MX50_PAD_SD1_CMD__ESDHC1_CMD                            0x0e8 0x394 0x000 0x0 0x0
+#define MX50_PAD_SD1_CMD__GPIO5_1                               0x0e8 0x394 0x000 0x1 0x0
+#define MX50_PAD_SD1_CMD__CCM_CLKO2                             0x0e8 0x394 0x000 0x7 0x0
+#define MX50_PAD_SD1_D0__ESDHC1_DAT0                            0x0ec 0x398 0x000 0x0 0x0
+#define MX50_PAD_SD1_D0__GPIO5_2                                0x0ec 0x398 0x000 0x1 0x0
+#define MX50_PAD_SD1_D0__CCM_PLL1_BYP                           0x0ec 0x398 0x6dc 0x7 0x0
+#define MX50_PAD_SD1_D1__ESDHC1_DAT1                            0x0f0 0x39c 0x000 0x0 0x0
+#define MX50_PAD_SD1_D1__GPIO5_3                                0x0f0 0x39c 0x000 0x1 0x0
+#define MX50_PAD_SD1_D1__CCM_PLL2_BYP                           0x0f0 0x39c 0x000 0x7 0x0
+#define MX50_PAD_SD1_D2__ESDHC1_DAT2                            0x0f4 0x3a0 0x000 0x0 0x0
+#define MX50_PAD_SD1_D2__GPIO5_4                                0x0f4 0x3a0 0x000 0x1 0x0
+#define MX50_PAD_SD1_D2__CCM_PLL3_BYP                           0x0f4 0x3a0 0x6e4 0x7 0x0
+#define MX50_PAD_SD1_D3__ESDHC1_DAT3                            0x0f8 0x3a4 0x000 0x0 0x0
+#define MX50_PAD_SD1_D3__GPIO5_5                                0x0f8 0x3a4 0x000 0x1 0x0
+#define MX50_PAD_SD2_CLK__ESDHC2_CLK                            0x0fc 0x3a8 0x000 0x0 0x0
+#define MX50_PAD_SD2_CLK__GPIO5_6                               0x0fc 0x3a8 0x000 0x1 0x0
+#define MX50_PAD_SD2_CLK__MSHC_SCLK                             0x0fc 0x3a8 0x000 0x2 0x0
+#define MX50_PAD_SD2_CMD__ESDHC2_CMD                            0x100 0x3ac 0x000 0x0 0x0
+#define MX50_PAD_SD2_CMD__GPIO5_7                               0x100 0x3ac 0x000 0x1 0x0
+#define MX50_PAD_SD2_CMD__MSHC_BS                               0x100 0x3ac 0x000 0x2 0x0
+#define MX50_PAD_SD2_D0__ESDHC2_DAT0                            0x104 0x3b0 0x000 0x0 0x0
+#define MX50_PAD_SD2_D0__GPIO5_8                                0x104 0x3b0 0x000 0x1 0x0
+#define MX50_PAD_SD2_D0__MSHC_DATA_0                            0x104 0x3b0 0x000 0x2 0x0
+#define MX50_PAD_SD2_D0__KPP_COL_4                              0x104 0x3b0 0x790 0x3 0x0
+#define MX50_PAD_SD2_D1__ESDHC2_DAT1                            0x108 0x3b4 0x000 0x0 0x0
+#define MX50_PAD_SD2_D1__GPIO5_9                                0x108 0x3b4 0x000 0x1 0x0
+#define MX50_PAD_SD2_D1__MSHC_DATA_1                            0x108 0x3b4 0x000 0x2 0x0
+#define MX50_PAD_SD2_D1__KPP_ROW_4                              0x108 0x3b4 0x7a0 0x3 0x0
+#define MX50_PAD_SD2_D2__ESDHC2_DAT2                            0x10c 0x3b8 0x000 0x0 0x0
+#define MX50_PAD_SD2_D2__GPIO5_10                               0x10c 0x3b8 0x000 0x1 0x0
+#define MX50_PAD_SD2_D2__MSHC_DATA_2                            0x10c 0x3b8 0x000 0x2 0x0
+#define MX50_PAD_SD2_D2__KPP_COL_5                              0x10c 0x3b8 0x794 0x3 0x0
+#define MX50_PAD_SD2_D3__ESDHC2_DAT3                            0x110 0x3bc 0x000 0x0 0x0
+#define MX50_PAD_SD2_D3__GPIO5_11                               0x110 0x3bc 0x000 0x1 0x0
+#define MX50_PAD_SD2_D3__MSHC_DATA_3                            0x110 0x3bc 0x000 0x2 0x0
+#define MX50_PAD_SD2_D3__KPP_ROW_5                              0x110 0x3bc 0x7a4 0x3 0x0
+#define MX50_PAD_SD2_D4__ESDHC2_DAT4                            0x114 0x3c0 0x000 0x0 0x0
+#define MX50_PAD_SD2_D4__GPIO5_12                               0x114 0x3c0 0x000 0x1 0x0
+#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS                       0x114 0x3c0 0x6d0 0x2 0x0
+#define MX50_PAD_SD2_D4__KPP_COL_6                              0x114 0x3c0 0x798 0x3 0x0
+#define MX50_PAD_SD2_D4__EIM_WEIM_D_0                           0x114 0x3c0 0x7ec 0x4 0x0
+#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0                          0x114 0x3c0 0x000 0x7 0x0
+#define MX50_PAD_SD2_D5__ESDHC2_DAT5                            0x118 0x3c4 0x000 0x0 0x0
+#define MX50_PAD_SD2_D5__GPIO5_13                               0x118 0x3c4 0x000 0x1 0x0
+#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC                        0x118 0x3c4 0x6cc 0x2 0x0
+#define MX50_PAD_SD2_D5__KPP_ROW_6                              0x118 0x3c4 0x7a8 0x3 0x0
+#define MX50_PAD_SD2_D5__EIM_WEIM_D_1                           0x118 0x3c4 0x7f0 0x4 0x0
+#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1                          0x118 0x3c4 0x000 0x7 0x0
+#define MX50_PAD_SD2_D6__ESDHC2_DAT6                            0x11c 0x3c8 0x000 0x0 0x0
+#define MX50_PAD_SD2_D6__GPIO5_14                               0x11c 0x3c8 0x000 0x1 0x0
+#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD                        0x11c 0x3c8 0x6c4 0x2 0x0
+#define MX50_PAD_SD2_D6__KPP_COL_7                              0x11c 0x3c8 0x79c 0x3 0x0
+#define MX50_PAD_SD2_D6__EIM_WEIM_D_2                           0x11c 0x3c8 0x7f4 0x4 0x0
+#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2                          0x11c 0x3c8 0x000 0x7 0x0
+#define MX50_PAD_SD2_D7__ESDHC2_DAT7                            0x120 0x3cc 0x000 0x0 0x0
+#define MX50_PAD_SD2_D7__GPIO5_15                               0x120 0x3cc 0x000 0x1 0x0
+#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS                       0x120 0x3cc 0x6d8 0x2 0x0
+#define MX50_PAD_SD2_D7__KPP_ROW_7                              0x120 0x3cc 0x7ac 0x3 0x0
+#define MX50_PAD_SD2_D7__EIM_WEIM_D_3                           0x120 0x3cc 0x7f8 0x4 0x0
+#define MX50_PAD_SD2_D7__CCM_STOP                               0x120 0x3cc 0x000 0x7 0x0
+#define MX50_PAD_SD2_WP__ESDHC2_WP                              0x124 0x3d0 0x744 0x0 0x1
+#define MX50_PAD_SD2_WP__GPIO5_16                               0x124 0x3d0 0x000 0x1 0x0
+#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD                        0x124 0x3d0 0x6c8 0x2 0x0
+#define MX50_PAD_SD2_WP__EIM_WEIM_D_4                           0x124 0x3d0 0x7fc 0x4 0x0
+#define MX50_PAD_SD2_WP__CCM_WAIT                               0x124 0x3d0 0x000 0x7 0x0
+#define MX50_PAD_SD2_CD__ESDHC2_CD                              0x128 0x3d4 0x740 0x0 0x1
+#define MX50_PAD_SD2_CD__GPIO5_17                               0x128 0x3d4 0x000 0x1 0x0
+#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC                        0x128 0x3d4 0x6d4 0x2 0x0
+#define MX50_PAD_SD2_CD__EIM_WEIM_D_5                           0x128 0x3d4 0x800 0x4 0x0
+#define MX50_PAD_SD2_CD__CCM_REF_EN_B                           0x128 0x3d4 0x000 0x7 0x0
+#define MX50_PAD_DISP_D0__ELCDIF_DAT_0                          0x12c 0x40c 0x6fc 0x0 0x0
+#define MX50_PAD_DISP_D0__GPIO2_0                               0x12c 0x40c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D0__FEC_TX_CLK                            0x12c 0x40c 0x78c 0x2 0x0
+#define MX50_PAD_DISP_D0__EIM_WEIM_A_16                         0x12c 0x40c 0x000 0x3 0x0
+#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0                       0x12c 0x40c 0x000 0x6 0x0
+#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0                     0x12c 0x40c 0x000 0x7 0x0
+#define MX50_PAD_DISP_D1__ELCDIF_DAT_1                          0x130 0x410 0x700 0x0 0x0
+#define MX50_PAD_DISP_D1__GPIO2_1                               0x130 0x410 0x000 0x1 0x0
+#define MX50_PAD_DISP_D1__FEC_RX_ERR                            0x130 0x410 0x788 0x2 0x0
+#define MX50_PAD_DISP_D1__EIM_WEIM_A_17                         0x130 0x410 0x000 0x3 0x0
+#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1                       0x130 0x410 0x000 0x6 0x0
+#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1                     0x130 0x410 0x000 0x7 0x0
+#define MX50_PAD_DISP_D2__ELCDIF_DAT_2                          0x134 0x414 0x704 0x0 0x0
+#define MX50_PAD_DISP_D2__GPIO2_2                               0x134 0x414 0x000 0x1 0x0
+#define MX50_PAD_DISP_D2__FEC_RX_DV                             0x134 0x414 0x784 0x2 0x0
+#define MX50_PAD_DISP_D2__EIM_WEIM_A_18                         0x134 0x414 0x000 0x3 0x0
+#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2                       0x134 0x414 0x000 0x6 0x0
+#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2                     0x134 0x414 0x000 0x7 0x0
+#define MX50_PAD_DISP_D3__ELCDIF_DAT_3                          0x138 0x418 0x708 0x0 0x0
+#define MX50_PAD_DISP_D3__GPIO2_3                               0x138 0x418 0x000 0x1 0x0
+#define MX50_PAD_DISP_D3__FEC_RDATA_1                           0x138 0x418 0x77c 0x2 0x0
+#define MX50_PAD_DISP_D3__EIM_WEIM_A_19                         0x138 0x418 0x000 0x3 0x0
+#define MX50_PAD_DISP_D3__FEC_COL                               0x138 0x418 0x770 0x4 0x1
+#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3                       0x138 0x418 0x000 0x6 0x0
+#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3                     0x138 0x418 0x000 0x7 0x0
+#define MX50_PAD_DISP_D4__ELCDIF_DAT_4                          0x13c 0x41c 0x70c 0x0 0x0
+#define MX50_PAD_DISP_D4__GPIO2_4                               0x13c 0x41c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D4__FEC_RDATA_0                           0x13c 0x41c 0x778 0x2 0x0
+#define MX50_PAD_DISP_D4__EIM_WEIM_A_20                         0x13c 0x41c 0x000 0x3 0x0
+#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4                       0x13c 0x41c 0x000 0x6 0x0
+#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4                     0x13c 0x41c 0x000 0x7 0x0
+#define MX50_PAD_DISP_D5__ELCDIF_DAT_5                          0x140 0x420 0x710 0x0 0x0
+#define MX50_PAD_DISP_D5__GPIO2_5                               0x140 0x420 0x000 0x1 0x0
+#define MX50_PAD_DISP_D5__FEC_TX_EN                             0x140 0x420 0x000 0x2 0x0
+#define MX50_PAD_DISP_D5__EIM_WEIM_A_21                         0x140 0x420 0x000 0x3 0x0
+#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5                       0x140 0x420 0x000 0x6 0x0
+#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5                     0x140 0x420 0x000 0x7 0x0
+#define MX50_PAD_DISP_D6__ELCDIF_DAT_6                          0x144 0x424 0x714 0x0 0x0
+#define MX50_PAD_DISP_D6__GPIO2_6                               0x144 0x424 0x000 0x1 0x0
+#define MX50_PAD_DISP_D6__FEC_TDATA_1                           0x144 0x424 0x000 0x2 0x0
+#define MX50_PAD_DISP_D6__EIM_WEIM_A_22                         0x144 0x424 0x000 0x3 0x0
+#define MX50_PAD_DISP_D6__FEC_RX_CLK                            0x144 0x424 0x780 0x4 0x1
+#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6                       0x144 0x424 0x000 0x6 0x0
+#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6                     0x144 0x424 0x000 0x7 0x0
+#define MX50_PAD_DISP_D7__ELCDIF_DAT_7                          0x148 0x428 0x718 0x0 0x0
+#define MX50_PAD_DISP_D7__GPIO2_7                               0x148 0x428 0x000 0x1 0x0
+#define MX50_PAD_DISP_D7__FEC_TDATA_0                           0x148 0x428 0x000 0x2 0x0
+#define MX50_PAD_DISP_D7__EIM_WEIM_A_23                         0x148 0x428 0x000 0x3 0x0
+#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7                       0x148 0x428 0x000 0x6 0x0
+#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7                     0x148 0x428 0x000 0x7 0x0
+#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN                         0x14c 0x42c 0x000 0x0 0x0
+#define MX50_PAD_DISP_WR__GPIO2_16                              0x14c 0x42c 0x000 0x1 0x0
+#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK                         0x14c 0x42c 0x000 0x2 0x0
+#define MX50_PAD_DISP_WR__EIM_WEIM_A_24                         0x14c 0x42c 0x000 0x3 0x0
+#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8                       0x14c 0x42c 0x000 0x6 0x0
+#define MX50_PAD_DISP_WR__USBPHY1_AVALID                        0x14c 0x42c 0x000 0x7 0x0
+#define MX50_PAD_DISP_RD__ELCDIF_RD_E                           0x150 0x430 0x000 0x0 0x0
+#define MX50_PAD_DISP_RD__GPIO2_19                              0x150 0x430 0x000 0x1 0x0
+#define MX50_PAD_DISP_RD__ELCDIF_ENABLE                         0x150 0x430 0x000 0x2 0x0
+#define MX50_PAD_DISP_RD__EIM_WEIM_A_25                         0x150 0x430 0x000 0x3 0x0
+#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9                       0x150 0x430 0x000 0x6 0x0
+#define MX50_PAD_DISP_RD__USBPHY1_BVALID                        0x150 0x430 0x000 0x7 0x0
+#define MX50_PAD_DISP_RS__ELCDIF_RS                             0x154 0x434 0x000 0x0 0x0
+#define MX50_PAD_DISP_RS__GPIO2_17                              0x154 0x434 0x000 0x1 0x0
+#define MX50_PAD_DISP_RS__ELCDIF_VSYNC                          0x154 0x434 0x73c 0x2 0x1
+#define MX50_PAD_DISP_RS__EIM_WEIM_A_26                         0x154 0x434 0x000 0x3 0x0
+#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10                      0x154 0x434 0x000 0x6 0x0
+#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION                    0x154 0x434 0x000 0x7 0x0
+#define MX50_PAD_DISP_CS__ELCDIF_CS                             0x158 0x438 0x000 0x0 0x0
+#define MX50_PAD_DISP_CS__GPIO2_21                              0x158 0x438 0x000 0x1 0x0
+#define MX50_PAD_DISP_CS__ELCDIF_HSYNC                          0x158 0x438 0x6f8 0x2 0x1
+#define MX50_PAD_DISP_CS__EIM_WEIM_A_27                         0x158 0x438 0x000 0x3 0x0
+#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3                         0x158 0x438 0x000 0x4 0x0
+#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11                      0x158 0x438 0x000 0x6 0x0
+#define MX50_PAD_DISP_CS__USBPHY1_IDDIG                         0x158 0x438 0x000 0x7 0x0
+#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY                         0x15c 0x43c 0x6f8 0x0 0x2
+#define MX50_PAD_DISP_BUSY__GPIO2_18                            0x15c 0x43c 0x000 0x1 0x0
+#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3                       0x15c 0x43c 0x000 0x4 0x0
+#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12                    0x15c 0x43c 0x000 0x6 0x0
+#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT              0x15c 0x43c 0x000 0x7 0x0
+#define MX50_PAD_DISP_RESET__ELCDIF_RESET                       0x160 0x440 0x000 0x0 0x0
+#define MX50_PAD_DISP_RESET__GPIO2_20                           0x160 0x440 0x000 0x1 0x0
+#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3                      0x160 0x440 0x000 0x4 0x0
+#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13                   0x160 0x440 0x000 0x6 0x0
+#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK                     0x160 0x440 0x000 0x7 0x0
+#define MX50_PAD_SD3_CMD__ESDHC3_CMD                            0x164 0x444 0x000 0x0 0x0
+#define MX50_PAD_SD3_CMD__GPIO5_18                              0x164 0x444 0x000 0x1 0x0
+#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN                         0x164 0x444 0x000 0x2 0x0
+#define MX50_PAD_SD3_CMD__SSP_CMD                               0x164 0x444 0x000 0x3 0x0
+#define MX50_PAD_SD3_CLK__ESDHC3_CLK                            0x168 0x448 0x000 0x0 0x0
+#define MX50_PAD_SD3_CLK__GPIO5_19                              0x168 0x448 0x000 0x1 0x0
+#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN                         0x168 0x448 0x000 0x2 0x0
+#define MX50_PAD_SD3_CLK__SSP_CLK                               0x168 0x448 0x000 0x3 0x0
+#define MX50_PAD_SD3_D0__ESDHC3_DAT0                            0x16c 0x44c 0x000 0x0 0x0
+#define MX50_PAD_SD3_D0__GPIO5_20                               0x16c 0x44c 0x000 0x1 0x0
+#define MX50_PAD_SD3_D0__EIM_NANDF_D_4                          0x16c 0x44c 0x000 0x2 0x0
+#define MX50_PAD_SD3_D0__SSP_D0                                 0x16c 0x44c 0x000 0x3 0x0
+#define MX50_PAD_SD3_D0__CCM_PLL1_BYP                           0x16c 0x44c 0x6dc 0x7 0x1
+#define MX50_PAD_SD3_D1__ESDHC3_DAT1                            0x170 0x450 0x000 0x0 0x0
+#define MX50_PAD_SD3_D1__GPIO5_21                               0x170 0x450 0x000 0x1 0x0
+#define MX50_PAD_SD3_D1__EIM_NANDF_D_5                          0x170 0x450 0x000 0x2 0x0
+#define MX50_PAD_SD3_D1__SSP_D1                                 0x170 0x450 0x000 0x3 0x0
+#define MX50_PAD_SD3_D1__CCM_PLL2_BYP                           0x170 0x450 0x000 0x7 0x0
+#define MX50_PAD_SD3_D2__ESDHC3_DAT2                            0x174 0x454 0x000 0x0 0x0
+#define MX50_PAD_SD3_D2__GPIO5_22                               0x174 0x454 0x000 0x1 0x0
+#define MX50_PAD_SD3_D2__EIM_NANDF_D_6                          0x174 0x454 0x000 0x2 0x0
+#define MX50_PAD_SD3_D2__SSP_D2                                 0x174 0x454 0x000 0x3 0x0
+#define MX50_PAD_SD3_D2__CCM_PLL3_BYP                           0x174 0x454 0x6e4 0x7 0x1
+#define MX50_PAD_SD3_D3__ESDHC3_DAT3                            0x178 0x458 0x000 0x0 0x0
+#define MX50_PAD_SD3_D3__GPIO5_23                               0x178 0x458 0x000 0x1 0x0
+#define MX50_PAD_SD3_D3__EIM_NANDF_D_7                          0x178 0x458 0x000 0x2 0x0
+#define MX50_PAD_SD3_D3__SSP_D3                                 0x178 0x458 0x000 0x3 0x0
+#define MX50_PAD_SD3_D4__ESDHC3_DAT4                            0x17c 0x45c 0x000 0x0 0x0
+#define MX50_PAD_SD3_D4__GPIO5_24                               0x17c 0x45c 0x000 0x1 0x0
+#define MX50_PAD_SD3_D4__EIM_NANDF_D_0                          0x17c 0x45c 0x000 0x2 0x0
+#define MX50_PAD_SD3_D4__SSP_D4                                 0x17c 0x45c 0x000 0x3 0x0
+#define MX50_PAD_SD3_D5__ESDHC3_DAT5                            0x180 0x460 0x000 0x0 0x0
+#define MX50_PAD_SD3_D5__GPIO5_25                               0x180 0x460 0x000 0x1 0x0
+#define MX50_PAD_SD3_D5__EIM_NANDF_D_1                          0x180 0x460 0x000 0x2 0x0
+#define MX50_PAD_SD3_D5__SSP_D5                                 0x180 0x460 0x000 0x3 0x0
+#define MX50_PAD_SD3_D6__ESDHC3_DAT6                            0x184 0x464 0x000 0x0 0x0
+#define MX50_PAD_SD3_D6__GPIO5_26                               0x184 0x464 0x000 0x1 0x0
+#define MX50_PAD_SD3_D6__EIM_NANDF_D_2                          0x184 0x464 0x000 0x2 0x0
+#define MX50_PAD_SD3_D6__SSP_D6                                 0x184 0x464 0x000 0x3 0x0
+#define MX50_PAD_SD3_D7__ESDHC3_DAT7                            0x188 0x468 0x000 0x0 0x0
+#define MX50_PAD_SD3_D7__GPIO5_27                               0x188 0x468 0x000 0x1 0x0
+#define MX50_PAD_SD3_D7__EIM_NANDF_D_3                          0x188 0x468 0x000 0x2 0x0
+#define MX50_PAD_SD3_D7__SSP_D7                                 0x188 0x468 0x000 0x3 0x0
+#define MX50_PAD_SD3_WP__ESDHC3_WP                              0x18c 0x46C 0x000 0x0 0x0
+#define MX50_PAD_SD3_WP__GPIO5_28                               0x18c 0x46C 0x000 0x1 0x0
+#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN                       0x18c 0x46C 0x000 0x2 0x0
+#define MX50_PAD_SD3_WP__SSP_CD                                 0x18c 0x46C 0x000 0x3 0x0
+#define MX50_PAD_SD3_WP__ESDHC4_LCTL                            0x18c 0x46C 0x000 0x4 0x0
+#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3                          0x18c 0x46C 0x000 0x5 0x0
+#define MX50_PAD_DISP_D8__ELCDIF_DAT_8                          0x190 0x470 0x71c 0x0 0x0
+#define MX50_PAD_DISP_D8__GPIO2_8                               0x190 0x470 0x000 0x1 0x0
+#define MX50_PAD_DISP_D8__EIM_NANDF_CLE                         0x190 0x470 0x000 0x2 0x0
+#define MX50_PAD_DISP_D8__ESDHC1_LCTL                           0x190 0x470 0x000 0x3 0x0
+#define MX50_PAD_DISP_D8__ESDHC4_CMD                            0x190 0x470 0x74c 0x4 0x2
+#define MX50_PAD_DISP_D8__KPP_COL_4                             0x190 0x470 0x790 0x5 0x1
+#define MX50_PAD_DISP_D8__FEC_TX_CLK                            0x190 0x470 0x78c 0x6 0x1
+#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0                     0x190 0x470 0x000 0x7 0x0
+#define MX50_PAD_DISP_D9__ELCDIF_DAT_9                          0x194 0x474 0x720 0x0 0x0
+#define MX50_PAD_DISP_D9__GPIO2_9                               0x194 0x474 0x000 0x1 0x0
+#define MX50_PAD_DISP_D9__EIM_NANDF_ALE                         0x194 0x474 0x000 0x2 0x0
+#define MX50_PAD_DISP_D9__ESDHC2_LCTL                           0x194 0x474 0x000 0x3 0x0
+#define MX50_PAD_DISP_D9__ESDHC4_CLK                            0x194 0x474 0x748 0x4 0x2
+#define MX50_PAD_DISP_D9__KPP_ROW_4                             0x194 0x474 0x7a0 0x5 0x1
+#define MX50_PAD_DISP_D9__FEC_RX_ER                             0x194 0x474 0x788 0x6 0x1
+#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1                     0x194 0x474 0x000 0x7 0x0
+#define MX50_PAD_DISP_D10__ELCDIF_DAT_10                        0x198 0x478 0x724 0x0 0x0
+#define MX50_PAD_DISP_D10__GPIO2_10                             0x198 0x478 0x000 0x1 0x0
+#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0                      0x198 0x478 0x000 0x2 0x0
+#define MX50_PAD_DISP_D10__ESDHC3_LCTL                          0x198 0x478 0x000 0x3 0x0
+#define MX50_PAD_DISP_D10__ESDHC4_DAT0                          0x198 0x478 0x000 0x4 0x0
+#define MX50_PAD_DISP_D10__KPP_COL_5                            0x198 0x478 0x794 0x5 0x1
+#define MX50_PAD_DISP_D10__FEC_RX_DV                            0x198 0x478 0x784 0x6 0x1
+#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2                    0x198 0x478 0x000 0x7 0x0
+#define MX50_PAD_DISP_D11__ELCDIF_DAT_11                        0x19c 0x47c 0x728 0x0 0x0
+#define MX50_PAD_DISP_D11__GPIO2_11                             0x19c 0x47c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1                      0x19c 0x47c 0x000 0x2 0x0
+#define MX50_PAD_DISP_D11__ESDHC4_DAT1                          0x19c 0x47c 0x754 0x4 0x1
+#define MX50_PAD_DISP_D11__KPP_ROW_5                            0x19c 0x47c 0x7a4 0x5 0x1
+#define MX50_PAD_DISP_D11__FEC_RDATA_1                          0x19c 0x47c 0x77c 0x6 0x1
+#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3                    0x19c 0x47c 0x000 0x7 0x0
+#define MX50_PAD_DISP_D12__ELCDIF_DAT_12                        0x1a0 0x480 0x72c 0x0 0x0
+#define MX50_PAD_DISP_D12__GPIO2_12                             0x1a0 0x480 0x000 0x1 0x0
+#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2                      0x1a0 0x480 0x000 0x2 0x0
+#define MX50_PAD_DISP_D12__ESDHC1_CD                            0x1a0 0x480 0x000 0x3 0x0
+#define MX50_PAD_DISP_D12__ESDHC4_DAT2                          0x1a0 0x480 0x758 0x4 0x1
+#define MX50_PAD_DISP_D12__KPP_COL_6                            0x1a0 0x480 0x798 0x5 0x1
+#define MX50_PAD_DISP_D12__FEC_RDATA_0                          0x1a0 0x480 0x778 0x6 0x1
+#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4                    0x1a0 0x480 0x000 0x7 0x0
+#define MX50_PAD_DISP_D13__ELCDIF_DAT_13                        0x1a4 0x484 0x730 0x0 0x0
+#define MX50_PAD_DISP_D13__GPIO2_13                             0x1a4 0x484 0x000 0x1 0x0
+#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3                      0x1a4 0x484 0x000 0x2 0x0
+#define MX50_PAD_DISP_D13__ESDHC3_CD                            0x1a4 0x484 0x000 0x3 0x0
+#define MX50_PAD_DISP_D13__ESDHC4_DAT3                          0x1a4 0x484 0x75c 0x4 0x1
+#define MX50_PAD_DISP_D13__KPP_ROW_6                            0x1a4 0x484 0x7a8 0x5 0x1
+#define MX50_PAD_DISP_D13__FEC_TX_EN                            0x1a4 0x484 0x000 0x6 0x0
+#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5                    0x1a4 0x484 0x000 0x7 0x0
+#define MX50_PAD_DISP_D14__ELCDIF_DAT_14                        0x1a8 0x488 0x734 0x0 0x0
+#define MX50_PAD_DISP_D14__GPIO2_14                             0x1a8 0x488 0x000 0x1 0x0
+#define MX50_PAD_DISP_D14__EIM_NANDF_READY0                     0x1a8 0x488 0x7b4 0x2 0x1
+#define MX50_PAD_DISP_D14__ESDHC1_WP                            0x1a8 0x488 0x000 0x3 0x0
+#define MX50_PAD_DISP_D14__ESDHC4_WP                            0x1a8 0x488 0x000 0x4 0x0
+#define MX50_PAD_DISP_D14__KPP_COL_7                            0x1a8 0x488 0x79c 0x5 0x1
+#define MX50_PAD_DISP_D14__FEC_TDATA_1                          0x1a8 0x488 0x000 0x6 0x0
+#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6                    0x1a8 0x488 0x000 0x7 0x0
+#define MX50_PAD_DISP_D15__ELCDIF_DAT_15                        0x1ac 0x48c 0x738 0x0 0x0
+#define MX50_PAD_DISP_D15__GPIO2_15                             0x1ac 0x48c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D15__EIM_NANDF_DQS                        0x1ac 0x48c 0x7b0 0x2 0x1
+#define MX50_PAD_DISP_D15__ESDHC3_RST                           0x1ac 0x48c 0x000 0x3 0x0
+#define MX50_PAD_DISP_D15__ESDHC4_CD                            0x1ac 0x48c 0x000 0x4 0x0
+#define MX50_PAD_DISP_D15__KPP_ROW_7                            0x1ac 0x48c 0x7ac 0x5 0x1
+#define MX50_PAD_DISP_D15__FEC_TDATA_0                          0x1ac 0x48c 0x000 0x6 0x0
+#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7                    0x1ac 0x48c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D0__EPDC_SDDO_0                           0x1b0 0x54c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D0__GPIO3_0                               0x1b0 0x54c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0                          0x1b0 0x54c 0x7ec 0x2 0x1
+#define MX50_PAD_EPDC_D0__ELCDIF_RS                             0x1b0 0x54c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK                         0x1b0 0x54c 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0            0x1b0 0x54c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0                     0x1b0 0x54c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D1__EPDC_SDDO_1                           0x1b4 0x550 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D1__GPIO3_1                               0x1b4 0x550 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1                          0x1b4 0x550 0x7f0 0x2 0x1
+#define MX50_PAD_EPDC_D1__ELCDIF_CS                             0x1b4 0x550 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE                         0x1b4 0x550 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1            0x1b4 0x550 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1                     0x1b4 0x550 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D2__EPDC_SDDO_2                           0x1b8 0x554 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D2__GPIO3_2                               0x1b8 0x554 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2                          0x1b8 0x554 0x7f4 0x2 0x1
+#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN                         0x1b8 0x554 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC                          0x1b8 0x554 0x73c 0x4 0x2
+#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2            0x1b8 0x554 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2                     0x1b8 0x554 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D3__EPDC_SDDO_3                           0x1bc 0x558 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D3__GPIO3_3                               0x1bc 0x558 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3                          0x1bc 0x558 0x7f8 0x2 0x1
+#define MX50_PAD_EPDC_D3__ELCDIF_RD_E                           0x1bc 0x558 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC                          0x1bc 0x558 0x6f8 0x4 0x3
+#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3            0x1bc 0x558 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3                     0x1bc 0x558 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D4__EPDC_SDDO_4                           0x1c0 0x55c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D4__GPIO3_4                               0x1c0 0x55c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4                          0x1c0 0x55c 0x7fc 0x2 0x1
+#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4            0x1c0 0x55c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4                     0x1c0 0x55c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D5__EPDC_SDDO_5                           0x1c4 0x560 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D5__GPIO3_5                               0x1c4 0x560 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5                          0x1c4 0x560 0x800 0x2 0x1
+#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5            0x1c4 0x560 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5                     0x1c4 0x560 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D6__EPDC_SDDO_6                           0x1c8 0x564 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D6__GPIO3_6                               0x1c8 0x564 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6                          0x1c8 0x564 0x804 0x2 0x1
+#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6            0x1c8 0x564 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6                     0x1c8 0x564 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D7__EPDC_SDDO_7                           0x1cc 0x568 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D7__GPIO3_7                               0x1cc 0x568 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7                          0x1cc 0x568 0x808 0x2 0x1
+#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7            0x1cc 0x568 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7                     0x1cc 0x568 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D8__EPDC_SDDO_8                           0x1d0 0x56c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D8__GPIO3_8                               0x1d0 0x56c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8                          0x1d0 0x56c 0x80c 0x2 0x2
+#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24                         0x1d0 0x56c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS              0x1d0 0x56c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0                     0x1d0 0x56c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D9__EPDC_SDDO_9                           0x1d4 0x570 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D9__GPIO3_9                               0x1d4 0x570 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9                          0x1d4 0x570 0x810 0x2 0x2
+#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25                         0x1d4 0x570 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL          0x1d4 0x570 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1                     0x1d4 0x570 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D10__EPDC_SDDO_10                         0x1d8 0x574 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D10__GPIO3_10                             0x1d8 0x574 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10                        0x1d8 0x574 0x814 0x2 0x2
+#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26                        0x1d8 0x574 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0           0x1d8 0x574 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2                    0x1d8 0x574 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D11__EPDC_SDDO_11                         0x1dc 0x578 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D11__GPIO3_11                             0x1dc 0x578 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11                        0x1dc 0x578 0x818 0x2 0x2
+#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27                        0x1dc 0x578 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1           0x1dc 0x578 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3                    0x1dc 0x578 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D12__EPDC_SDDO_12                         0x1e0 0x57c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D12__GPIO3_12                             0x1e0 0x57c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12                        0x1e0 0x57c 0x81c 0x2 0x1
+#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28                        0x1e0 0x57c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2           0x1e0 0x57c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4                    0x1e0 0x57c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D13__EPDC_SDDO_13                         0x1e4 0x580 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D13__GPIO3_13                             0x1e4 0x580 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13                        0x1e4 0x580 0x820 0x2 0x1
+#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29                        0x1e4 0x580 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3           0x1e4 0x580 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5                    0x1e4 0x580 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D14__EPDC_SDDO_14                         0x1e8 0x584 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D14__GPIO3_14                             0x1e8 0x584 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14                        0x1e8 0x584 0x824 0x2 0x1
+#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30                        0x1e8 0x584 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD                      0x1e8 0x584 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4           0x1e8 0x584 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6                    0x1e8 0x584 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D15__EPDC_SDDO_15                         0x1ec 0x588 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D15__GPIO3_15                             0x1ec 0x588 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15                        0x1ec 0x588 0x828 0x2 0x1
+#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31                        0x1ec 0x588 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC                      0x1ec 0x588 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5           0x1ec 0x588 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7                    0x1ec 0x588 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK                         0x1f0 0x58c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDCLK__GPIO3_16                           0x1f0 0x58c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16                      0x1f0 0x58c 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16                      0x1f0 0x58c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS                   0x1f0 0x58c 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0            0x1f0 0x58c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK                     0x1f0 0x58c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDSP__EPCD_GDSP                           0x1f4 0x590 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDSP__GPIO3_17                            0x1f4 0x590 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17                       0x1f4 0x590 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17                       0x1f4 0x590 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD                     0x1f4 0x590 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1             0x1f4 0x590 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID                      0x1f4 0x590 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDOE__EPCD_GDOE                           0x1f8 0x594 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDOE__GPIO3_18                            0x1f8 0x594 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18                       0x1f8 0x594 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18                       0x1f8 0x594 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC                     0x1f8 0x594 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2             0x1f8 0x594 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION                  0x1f8 0x594 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDRL__EPCD_GDRL                           0x1fc 0x598 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDRL__GPIO3_19                            0x1fc 0x598 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19                       0x1f8 0x598 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19                       0x1fc 0x598 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS                    0x1fc 0x598 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3             0x1fc 0x598 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG                       0x1fc 0x598 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK                         0x200 0x59c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCLK__GPIO3_20                           0x200 0x59c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20                      0x200 0x59c 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20                      0x200 0x59c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD                    0x200 0x59c 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0            0x200 0x59c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT             0x200 0x59c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ                         0x204 0x5a0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDOEZ__GPIO3_21                           0x204 0x5a0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21                      0x204 0x5a0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21                      0x204 0x5a0 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC                    0x204 0x5a0 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1            0x204 0x5a0 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY                    0x204 0x5a0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDOED__EPCD_SDOED                         0x208 0x5a4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDOED__GPIO3_22                           0x208 0x5a4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22                      0x208 0x5a4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22                      0x208 0x5a4 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS                   0x208 0x5a4 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2            0x208 0x5a4 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID                    0x208 0x5a4 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDOE__EPCD_SDOE                           0x20c 0x5a8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDOE__GPIO3_23                            0x20c 0x5a8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23                       0x20c 0x5a8 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23                       0x20c 0x5a8 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD                     0x20c 0x5a8 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3             0x20c 0x5a8 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE                    0x20c 0x5a8 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDLE__EPCD_SDLE                           0x210 0x5ac 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDLE__GPIO3_24                            0x210 0x5ac 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24                       0x210 0x5ac 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8                        0x210 0x5ac 0x71c 0x3 0x1
+#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC                     0x210 0x5ac 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4             0x210 0x5ac 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR                     0x210 0x5ac 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN                       0x214 0x5b0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCLKN__GPIO3_25                          0x214 0x5b0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25                     0x214 0x5b0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9                      0x214 0x5b0 0x720 0x3 0x1
+#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS                  0x214 0x5b0 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR              0x214 0x5b0 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK                  0x214 0x5b0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR                         0x218 0x5b4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDSHR__GPIO3_26                           0x218 0x5b4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26                      0x218 0x5b4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10                      0x218 0x5b4 0x724 0x3 0x1
+#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD                    0x218 0x5b4 0x6c8 0x4 0x1
+#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB                 0x218 0x5b4 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0                0x218 0x5b4 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM                       0x21c 0x5b8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCOM__GPIO3_27                          0x21c 0x5b8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27                     0x21c 0x5b8 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11                     0x21c 0x5b8 0x728 0x3 0x1
+#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC                   0x21c 0x5b8 0x6d4 0x4 0x1
+#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN               0x21c 0x5b8 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1               0x21c 0x5b8 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT                     0x220 0x5bc 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28                         0x220 0x5bc 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28                    0x220 0x5bc 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12                    0x220 0x5bc 0x72c 0x3 0x1
+#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS                 0x220 0x5bc 0x6d8 0x4 0x1
+#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE                  0x220 0x5bc 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID                0x220 0x5bc 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0                   0x224 0x5c0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29                        0x224 0x5c0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29                   0x224 0x5c0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13                   0x224 0x5c0 0x730 0x3 0x1
+#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD                 0x224 0x5c0 0x6c4 0x4 0x1
+#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE       0x224 0x5c0 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID                  0x224 0x5c0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1                   0x228 0x5c4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30                        0x228 0x5c4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30                   0x228 0x5c4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14                   0x228 0x5c4 0x734 0x3 0x1
+#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC                 0x228 0x5c4 0x6cc 0x4 0x1
+#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD                0x228 0x5c4 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST                  0x228 0x5c4 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2                   0x22c 0x5c8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31                        0x22c 0x5c8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31                   0x22c 0x5c8 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15                   0x22c 0x5c8 0x738 0x3 0x1
+#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS                0x22c 0x5c8 0x6d0 0x4 0x1
+#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0                0x22c 0x5c8 0x7b8 0x6 0x1
+#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST                  0x22c 0x5c8 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3                   0x230 0x5cc 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20                        0x230 0x5cc 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2                   0x230 0x5cc 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1                0x230 0x5cc 0x7bc 0x6 0x1
+#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK                  0x230 0x5cc 0x000 0x7 0x0
+#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0                        0x234 0x5d0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_VCOM0__GPIO4_21                           0x234 0x5d0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3                      0x234 0x5d0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK                     0x234 0x5d0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1                        0x238 0x5d4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_VCOM1__GPIO4_22                           0x238 0x5d4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3                      0x238 0x5d4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0                          0x23c 0x5d8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_BDR0__GPIO4_23                            0x23c 0x5d8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7                        0x23c 0x5d8 0x718 0x3 0x1
+#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1                          0x240 0x5dc 0x000 0x0 0x0
+#define MX50_PAD_EPDC_BDR1__GPIO4_24                            0x240 0x5dc 0x000 0x1 0x0
+#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6                        0x240 0x5dc 0x714 0x3 0x1
+#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0                        0x244 0x5e0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE0__GPIO4_25                           0x244 0x5e0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5                       0x244 0x5e0 0x710 0x3 0x1
+#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1                        0x248 0x5e4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE1__GPIO4_26                           0x248 0x5e4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4                       0x248 0x5e4 0x70c 0x3 0x0
+#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2                        0x24c 0x5e8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE2__GPIO4_27                           0x24c 0x5e8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3                       0x24c 0x5e8 0x708 0x3 0x1
+#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3                        0x250 0x5ec 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE3__GPIO4_28                           0x250 0x5ec 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2                       0x250 0x5ec 0x704 0x3 0x1
+#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4                        0x254 0x5f0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE4__GPIO4_29                           0x254 0x5f0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1                       0x254 0x5f0 0x700 0x3 0x1
+#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5                        0x258 0x5f4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE5__GPIO4_30                           0x258 0x5f4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0                       0x258 0x5f4 0x6fc 0x3 0x1
+#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0                          0x25c 0x5f8 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA0__GPIO1_0                               0x25c 0x5f8 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA0__KPP_COL_4                             0x25c 0x5f8 0x790 0x3 0x2
+#define MX50_PAD_EIM_DA0__TPIU_TRACE_0                          0x25c 0x5f8 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0                         0x25c 0x5f8 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1                          0x260 0x5fc 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA1__GPIO1_1                               0x260 0x5fc 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA1__KPP_ROW_4                             0x260 0x5fc 0x7a0 0x3 0x2
+#define MX50_PAD_EIM_DA1__TPIU_TRACE_1                          0x260 0x5fc 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1                         0x260 0x5fc 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2                          0x264 0x600 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA2__GPIO1_2                               0x264 0x600 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA2__KPP_COL_5                             0x264 0x600 0x794 0x3 0x2
+#define MX50_PAD_EIM_DA2__TPIU_TRACE_2                          0x264 0x600 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2                         0x264 0x600 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3                          0x268 0x604 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA3__GPIO1_3                               0x268 0x604 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA3__KPP_ROW_5                             0x268 0x604 0x7a4 0x3 0x2
+#define MX50_PAD_EIM_DA3__TPIU_TRACE_3                          0x268 0x604 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3                         0x268 0x604 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4                          0x26c 0x608 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA4__GPIO1_4                               0x26c 0x608 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA4__KPP_COL_6                             0x26c 0x608 0x798 0x3 0x2
+#define MX50_PAD_EIM_DA4__TPIU_TRACE_4                          0x26c 0x608 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4                         0x26c 0x608 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5                          0x270 0x60c 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA5__GPIO1_5                               0x270 0x60c 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA5__KPP_ROW_6                             0x270 0x60c 0x7a8 0x3 0x2
+#define MX50_PAD_EIM_DA5__TPIU_TRACE_5                          0x270 0x60c 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5                         0x270 0x60c 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6                          0x274 0x610 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA6__GPIO1_6                               0x274 0x610 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA6__KPP_COL_7                             0x274 0x610 0x79c 0x3 0x2
+#define MX50_PAD_EIM_DA6__TPIU_TRACE_6                          0x274 0x610 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6                         0x274 0x610 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7                          0x278 0x614 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA7__GPIO1_7                               0x278 0x614 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA7__KPP_ROW_7                             0x278 0x614 0x7ac 0x3 0x2
+#define MX50_PAD_EIM_DA7__TPIU_TRACE_7                          0x278 0x614 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7                         0x278 0x614 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8                          0x27c 0x618 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA8__GPIO1_8                               0x27c 0x618 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE                         0x27c 0x618 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA8__TPIU_TRACE_8                          0x27c 0x618 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0                         0x27c 0x618 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9                          0x280 0x61c 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA9__GPIO1_9                               0x280 0x61c 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE                         0x280 0x61c 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA9__TPIU_TRACE_9                          0x280 0x61c 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1                         0x280 0x61c 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10                        0x284 0x620 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA10__GPIO1_10                             0x284 0x620 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0                      0x284 0x620 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA10__TPIU_TRACE_10                        0x284 0x620 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2                        0x284 0x620 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11                        0x288 0x624 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA11__GPIO1_11                             0x288 0x624 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1                      0x288 0x624 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA11__TPIU_TRACE_11                        0x288 0x624 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3                        0x288 0x624 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12                        0x28c 0x628 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA12__GPIO1_12                             0x28c 0x628 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2                      0x28c 0x628 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA12__EPDC_SDCE_6                          0x28c 0x628 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA12__TPIU_TRACE_12                        0x28c 0x628 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4                        0x28c 0x628 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13                        0x290 0x62c 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA13__GPIO1_13                             0x290 0x62c 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3                      0x290 0x62c 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA13__EPDC_SDCE_7                          0x290 0x62c 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA13__TPIU_TRACE_13                        0x290 0x62c 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5                        0x290 0x62c 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14                        0x294 0x630 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA14__GPIO1_14                             0x294 0x630 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0                     0x294 0x630 0x7b4 0x2 0x2
+#define MX50_PAD_EIM_DA14__EPDC_SDCE_8                          0x294 0x630 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA14__TPIU_TRACE_14                        0x294 0x630 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6                        0x294 0x630 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15                        0x298 0x634 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA15__GPIO1_15                             0x298 0x634 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS                        0x298 0x634 0x7b0 0x2 0x2
+#define MX50_PAD_EIM_DA15__EPDC_SDCE_9                          0x298 0x634 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA15__TPIU_TRACE_15                        0x298 0x634 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7                        0x298 0x634 0x000 0x7 0x0
+#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2                         0x29c 0x638 0x000 0x0 0x0
+#define MX50_PAD_EIM_CS2__GPIO1_16                              0x29c 0x638 0x000 0x1 0x0
+#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27                         0x29c 0x638 0x000 0x2 0x0
+#define MX50_PAD_EIM_CS2__TPIU_TRCLK                            0x29c 0x638 0x000 0x6 0x0
+#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0                         0x29c 0x638 0x000 0x7 0x0
+#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1                         0x2a0 0x63c 0x000 0x0 0x0
+#define MX50_PAD_EIM_CS1__GPIO1_17                              0x2a0 0x63c 0x000 0x1 0x0
+#define MX50_PAD_EIM_CS1__TPIU_TRCTL                            0x2a0 0x63c 0x000 0x6 0x0
+#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1                         0x2a0 0x63c 0x000 0x7 0x0
+#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0                         0x2a4 0x640 0x000 0x0 0x0
+#define MX50_PAD_EIM_CS0__GPIO1_18                              0x2a4 0x640 0x000 0x1 0x0
+#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2                         0x2a4 0x640 0x000 0x7 0x0
+#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0                         0x2a8 0x644 0x000 0x0 0x0
+#define MX50_PAD_EIM_EB0__GPIO1_19                              0x2a8 0x644 0x000 0x1 0x0
+#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3                         0x2a8 0x644 0x000 0x7 0x0
+#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1                         0x2ac 0x648 0x000 0x0 0x0
+#define MX50_PAD_EIM_EB1__GPIO1_20                              0x2ac 0x648 0x000 0x1 0x0
+#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4                         0x2ac 0x648 0x000 0x7 0x0
+#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT                        0x2b0 0x64c 0x000 0x0 0x0
+#define MX50_PAD_EIM_WAIT__GPIO1_21                             0x2b0 0x64c 0x000 0x1 0x0
+#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B                     0x2b0 0x64c 0x000 0x2 0x0
+#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5                        0x2b0 0x64c 0x000 0x7 0x0
+#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK                        0x2b4 0x650 0x000 0x0 0x0
+#define MX50_PAD_EIM_BCLK__GPIO1_22                             0x2b4 0x650 0x000 0x1 0x0
+#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6                        0x2b4 0x650 0x000 0x7 0x0
+#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY                          0x2b8 0x654 0x000 0x0 0x0
+#define MX50_PAD_EIM_RDY__GPIO1_23                              0x2b8 0x654 0x000 0x1 0x0
+#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7                         0x2b8 0x654 0x000 0x7 0x0
+#define MX50_PAD_EIM_OE__EIM_WEIM_OE                            0x2bc 0x658 0x000 0x0 0x0
+#define MX50_PAD_EIM_OE__GPIO1_24                               0x2bc 0x658 0x000 0x1 0x0
+#define MX50_PAD_EIM_OE__INT_BOOT                               0x2bc 0x658 0x000 0x7 0x0
+#define MX50_PAD_EIM_RW__EIM_WEIM_RW                            0x2c0 0x65c 0x000 0x0 0x0
+#define MX50_PAD_EIM_RW__GPIO1_25                               0x2c0 0x65c 0x000 0x1 0x0
+#define MX50_PAD_EIM_RW__SYSTEM_RST                             0x2c0 0x65c 0x000 0x7 0x0
+#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA                          0x2c4 0x660 0x000 0x0 0x0
+#define MX50_PAD_EIM_LBA__GPIO1_26                              0x2c4 0x660 0x000 0x1 0x0
+#define MX50_PAD_EIM_LBA__TESTER_ACK                            0x2c4 0x660 0x000 0x7 0x0
+#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE                          0x2c8 0x664 0x000 0x0 0x0
+#define MX50_PAD_EIM_CRE__GPIO1_27                              0x2c8 0x664 0x000 0x1 0x0
+#endif /* __DTS_IMX50_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
new file mode 100644
index 000000000000..0c75fe3deb35
--- /dev/null
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -0,0 +1,478 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include "skeleton.dtsi"
+#include "imx50-pinfunc.h"
+#include <dt-bindings/clock/imx5-clock.h>
+/ {
+        aliases {
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+                gpio5 = &gpio6;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a8";
+                        reg = <0x0>;
+                };
+        };
+        tzic: tz-interrupt-controller@0fffc000 {
+                compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x0fffc000 0x4000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ckil {
+                        compatible = "fsl,imx-ckil", "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                ckih1 {
+                        compatible = "fsl,imx-ckih1", "fixed-clock";
+                        clock-frequency = <22579200>;
+                };
+                ckih2 {
+                        compatible = "fsl,imx-ckih2", "fixed-clock";
+                        clock-frequency = <0>;
+                };
+                osc {
+                        compatible = "fsl,imx-osc", "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&tzic>;
+                ranges;
+                aips@50000000 { /* AIPS1 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x50000000 0x10000000>;
+                        ranges;
+                        spba@50000000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x50000000 0x40000>;
+                                ranges;
+                                esdhc1: esdhc@50004000 {
+                                        compatible = "fsl,imx50-esdhc";
+                                        reg = <0x50004000 0x4000>;
+                                        interrupts = <1>;
+                                        clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
+                                        status = "disabled";
+                                };
+                                esdhc2: esdhc@50008000 {
+                                        compatible = "fsl,imx50-esdhc";
+                                        reg = <0x50008000 0x4000>;
+                                        interrupts = <2>;
+                                        clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
+                                        status = "disabled";
+                                };
+                                uart3: serial@5000c000 {
+                                        compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                                        reg = <0x5000c000 0x4000>;
+                                        interrupts = <33>;
+                                        clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
+                                                 <&clks IMX5_CLK_UART3_PER_GATE>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                ecspi1: ecspi@50010000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x50010000 0x4000>;
+                                        interrupts = <36>;
+                                        clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
+                                                 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                                ssi2: ssi@50014000 {
+                                        compatible = "fsl,imx50-ssi",
+                                                        "fsl,imx51-ssi",
+                                                        "fsl,imx21-ssi";
+                                        reg = <0x50014000 0x4000>;
+                                        interrupts = <30>;
+                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
+                                        fsl,fifo-depth = <15>;
+                                        fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
+                                        status = "disabled";
+                                };
+                                esdhc3: esdhc@50020000 {
+                                        compatible = "fsl,imx50-esdhc";
+                                        reg = <0x50020000 0x4000>;
+                                        interrupts = <3>;
+                                        clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
+                                        status = "disabled";
+                                };
+                                esdhc4: esdhc@50024000 {
+                                        compatible = "fsl,imx50-esdhc";
+                                        reg = <0x50024000 0x4000>;
+                                        interrupts = <4>;
+                                        clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
+                                        clock-names = "ipg", "ahb", "per";
+                                        bus-width = <4>;
+                                        status = "disabled";
+                                };
+                        };
+                        usbotg: usb@53f80000 {
+                                compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+                                reg = <0x53f80000 0x0200>;
+                                interrupts = <18>;
+                                clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
+                                status = "disabled";
+                        };
+                        usbh1: usb@53f80200 {
+                                compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+                                reg = <0x53f80200 0x0200>;
+                                interrupts = <14>;
+                                clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
+                                status = "disabled";
+                        };
+                        usbh2: usb@53f80400 {
+                                compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+                                reg = <0x53f80400 0x0200>;
+                                interrupts = <16>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+                                status = "disabled";
+                        };
+                        usbh3: usb@53f80600 {
+                                compatible = "fsl,imx50-usb", "fsl,imx27-usb";
+                                reg = <0x53f80600 0x0200>;
+                                interrupts = <17>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+                                status = "disabled";
+                        };
+                        gpio1: gpio@53f84000 {
+                                compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                                reg = <0x53f84000 0x4000>;
+                                interrupts = <50 51>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio2: gpio@53f88000 {
+                                compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                                reg = <0x53f88000 0x4000>;
+                                interrupts = <52 53>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio3: gpio@53f8c000 {
+                                compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                                reg = <0x53f8c000 0x4000>;
+                                interrupts = <54 55>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio4: gpio@53f90000 {
+                                compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                                reg = <0x53f90000 0x4000>;
+                                interrupts = <56 57>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        wdog1: wdog@53f98000 {
+                                compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
+                                reg = <0x53f98000 0x4000>;
+                                interrupts = <58>;
+                                clocks = <&clks IMX5_CLK_DUMMY>;
+                        };
+                        gpt: timer@53fa0000 {
+                                compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
+                                reg = <0x53fa0000 0x4000>;
+                                interrupts = <39>;
+                                clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
+                                         <&clks IMX5_CLK_GPT_HF_GATE>;
+                                clock-names = "ipg", "per";
+                        };
+                        iomuxc: iomuxc@53fa8000 {
+                                compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
+                                reg = <0x53fa8000 0x4000>;
+                        };
+                        gpr: iomuxc-gpr@53fa8000 {
+                                compatible = "fsl,imx50-iomuxc-gpr", "syscon";
+                                reg = <0x53fa8000 0xc>;
+                        };
+                        pwm1: pwm@53fb4000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
+                                reg = <0x53fb4000 0x4000>;
+                                clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
+                                         <&clks IMX5_CLK_PWM1_HF_GATE>;
+                                clock-names = "ipg", "per";
+                                interrupts = <61>;
+                        };
+                        pwm2: pwm@53fb8000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
+                                reg = <0x53fb8000 0x4000>;
+                                clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
+                                         <&clks IMX5_CLK_PWM2_HF_GATE>;
+                                clock-names = "ipg", "per";
+                                interrupts = <94>;
+                        };
+                        uart1: serial@53fbc000 {
+                                compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                                reg = <0x53fbc000 0x4000>;
+                                interrupts = <31>;
+                                clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART1_PER_GATE>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        uart2: serial@53fc0000 {
+                                compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                                reg = <0x53fc0000 0x4000>;
+                                interrupts = <32>;
+                                clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART2_PER_GATE>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        src: src@53fd0000 {
+                                compatible = "fsl,imx50-src", "fsl,imx51-src";
+                                reg = <0x53fd0000 0x4000>;
+                                #reset-cells = <1>;
+                        };
+                        clks: ccm@53fd4000{
+                                compatible = "fsl,imx50-ccm";
+                                reg = <0x53fd4000 0x4000>;
+                                interrupts = <0 71 0x04 0 72 0x04>;
+                                #clock-cells = <1>;
+                        };
+                        gpio5: gpio@53fdc000 {
+                                compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                                reg = <0x53fdc000 0x4000>;
+                                interrupts = <103 104>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        gpio6: gpio@53fe0000 {
+                                compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
+                                reg = <0x53fe0000 0x4000>;
+                                interrupts = <105 106>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+                        i2c3: i2c@53fec000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
+                                reg = <0x53fec000 0x4000>;
+                                interrupts = <64>;
+                                clocks = <&clks IMX5_CLK_I2C3_GATE>;
+                                status = "disabled";
+                        };
+                        uart4: serial@53ff0000 {
+                                compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                                reg = <0x53ff0000 0x4000>;
+                                interrupts = <13>;
+                                clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART4_PER_GATE>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                };
+                aips@60000000 { /* AIPS2 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x60000000 0x10000000>;
+                        ranges;
+                        uart5: serial@63f90000 {
+                                compatible = "fsl,imx50-uart", "fsl,imx21-uart";
+                                reg = <0x63f90000 0x4000>;
+                                interrupts = <86>;
+                                clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART5_PER_GATE>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        owire: owire@63fa4000 {
+                                compatible = "fsl,imx50-owire", "fsl,imx21-owire";
+                                reg = <0x63fa4000 0x4000>;
+                                clocks = <&clks IMX5_CLK_OWIRE_GATE>;
+                                status = "disabled";
+                        };
+                        ecspi2: ecspi@63fac000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
+                                reg = <0x63fac000 0x4000>;
+                                interrupts = <37>;
+                                clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
+                                         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        sdma: sdma@63fb0000 {
+                                compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
+                                reg = <0x63fb0000 0x4000>;
+                                interrupts = <6>;
+                                clocks = <&clks IMX5_CLK_SDMA_GATE>,
+                                         <&clks IMX5_CLK_SDMA_GATE>;
+                                clock-names = "ipg", "ahb";
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
+                        };
+                        cspi: cspi@63fc0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
+                                reg = <0x63fc0000 0x4000>;
+                                interrupts = <38>;
+                                clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
+                                         <&clks IMX5_CLK_CSPI_IPG_GATE>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                        i2c2: i2c@63fc4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
+                                reg = <0x63fc4000 0x4000>;
+                                interrupts = <63>;
+                                clocks = <&clks IMX5_CLK_I2C2_GATE>;
+                                status = "disabled";
+                        };
+                        i2c1: i2c@63fc8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
+                                reg = <0x63fc8000 0x4000>;
+                                interrupts = <62>;
+                                clocks = <&clks IMX5_CLK_I2C1_GATE>;
+                                status = "disabled";
+                        };
+                        ssi1: ssi@63fcc000 {
+                                compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
+                                                        "fsl,imx21-ssi";
+                                reg = <0x63fcc000 0x4000>;
+                                interrupts = <29>;
+                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
+                                fsl,fifo-depth = <15>;
+                                fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
+                                status = "disabled";
+                        };
+                        audmux: audmux@63fd0000 {
+                                compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
+                                reg = <0x63fd0000 0x4000>;
+                                status = "disabled";
+                        };
+                        fec: ethernet@63fec000 {
+                                compatible = "fsl,imx53-fec", "fsl,imx25-fec";
+                                reg = <0x63fec000 0x4000>;
+                                interrupts = <87>;
+                                clocks = <&clks IMX5_CLK_FEC_GATE>,
+                                         <&clks IMX5_CLK_FEC_GATE>,
+                                         <&clks IMX5_CLK_FEC_GATE>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index b3606993f2e8..e88b2a6be079 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -34,13 +34,47 @@
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec_2>;
+        pinctrl-0 = <&pinctrl_fec>;
        phy-mode = "mii";
-        phy-reset-gpios = <&gpio3 0 0>;
+        phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
        phy-reset-duration = <1>;
        status = "okay";
 };
+&iomuxc {
+        imx51-apf51 {
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX51_PAD_DI_GP3__FEC_TX_ER              0x80000000
+                                MX51_PAD_DI2_PIN4__FEC_CRS              0x80000000
+                                MX51_PAD_DI2_PIN2__FEC_MDC              0x80000000
+                                MX51_PAD_DI2_PIN3__FEC_MDIO             0x80000000
+                                MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       0x80000000
+                                MX51_PAD_DI_GP4__FEC_RDATA2             0x80000000
+                                MX51_PAD_DISP2_DAT0__FEC_RDATA3         0x80000000
+                                MX51_PAD_DISP2_DAT1__FEC_RX_ER          0x80000000
+                                MX51_PAD_DISP2_DAT6__FEC_TDATA1         0x80000000
+                                MX51_PAD_DISP2_DAT7__FEC_TDATA2         0x80000000
+                                MX51_PAD_DISP2_DAT8__FEC_TDATA3         0x80000000
+                                MX51_PAD_DISP2_DAT9__FEC_TX_EN          0x80000000
+                                MX51_PAD_DISP2_DAT10__FEC_COL           0x80000000
+                                MX51_PAD_DISP2_DAT11__FEC_RX_CLK        0x80000000
+                                MX51_PAD_DISP2_DAT12__FEC_RX_DV         0x80000000
+                                MX51_PAD_DISP2_DAT13__FEC_TX_CLK        0x80000000
+                                MX51_PAD_DISP2_DAT14__FEC_RDATA0        0x80000000
+                                MX51_PAD_DISP2_DAT15__FEC_TDATA0        0x80000000
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX51_PAD_UART3_RXD__UART3_RXD           0x1c5
+                                MX51_PAD_UART3_TXD__UART3_TXD           0x1c5
+                        >;
+                };
+        };
+};
 &nfc {
        nand-bus-width = <8>;
        nand-ecc-mode = "hw";
@@ -50,6 +84,6 @@
 &uart3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart3_2>;
+        pinctrl-0 = <&pinctrl_uart3>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index 5a7f552786a1..c5a9a24c280a 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -18,10 +18,9 @@
        display@di1 {
                compatible = "fsl,imx-parallel-display";
-                crtcs = <&ipu 0>;
                interface-pix-fmt = "bgr666";
                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_ipu_disp1_1>;
+                pinctrl-0 = <&pinctrl_ipu_disp1>;
                display-timings {
                        lw700 {
@@ -41,6 +40,12 @@
                                pixelclk-active = <0>;
                        };
                };
+                port {
+                        display_in: endpoint {
+                                remote-endpoint = <&ipu_di0_disp0>;
+                        };
+                };
        };
        gpio-keys {
@@ -48,7 +53,7 @@
                user-key {
                        label = "user";
-                        gpios = <&gpio1 3 0>;
+                        gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
                        linux,code = <256>; /* BTN_0 */
                };
        };
@@ -58,7 +63,7 @@
                user {
                        label = "Heartbeat";
-                        gpios = <&gpio1 2 0>;
+                        gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
        };
@@ -66,31 +71,33 @@
 &ecspi1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        pinctrl-0 = <&pinctrl_ecspi1>;
        fsl,spi-num-chipselects = <2>;
-        cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
+        cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
+                   <&gpio4 25 GPIO_ACTIVE_HIGH>;
        status = "okay";
 };
 &ecspi2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi2_1>;
+        pinctrl-0 = <&pinctrl_ecspi2>;
        fsl,spi-num-chipselects = <2>;
-        cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>;
+        cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
+                   <&gpio3 27 GPIO_ACTIVE_LOW>;
        status = "okay";
 };
 &esdhc1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        pinctrl-0 = <&pinctrl_esdhc1>;
-        cd-gpios = <&gpio2 29 0>;
+        cd-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
        bus-width = <4>;
        status = "okay";
 };
 &esdhc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        pinctrl-0 = <&pinctrl_esdhc2>;
        bus-width = <4>;
        non-removable;
        status = "okay";
@@ -98,7 +105,7 @@
 &i2c2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2_2>;
+        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
 };
@@ -106,7 +113,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx51-apf51dev {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX51_PAD_EIM_EB2__GPIO2_22   0x0C5
@@ -120,5 +127,85 @@
                                MX51_PAD_GPIO1_3__GPIO1_3    0x0C5
                        >;
                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
+                                MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
+                                MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
+                        >;
+                };
+                pinctrl_ecspi2: ecspi2grp {
+                        fsl,pins = <
+                                MX51_PAD_NANDF_RB3__ECSPI2_MISO         0x185
+                                MX51_PAD_NANDF_D15__ECSPI2_MOSI         0x185
+                                MX51_PAD_NANDF_RB2__ECSPI2_SCLK         0x185
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
+                                MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
+                                MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
+                                MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
+                                MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
+                                MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
+                        >;
+                };
+                pinctrl_esdhc2: esdhc2grp {
+                        fsl,pins = <
+                                MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
+                                MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
+                                MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
+                                MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
+                                MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
+                                MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX51_PAD_EIM_D27__I2C2_SCL              0x400001ed
+                                MX51_PAD_EIM_D24__I2C2_SDA              0x400001ed
+                        >;
+                };
+                pinctrl_ipu_disp1: ipudisp1grp {
+                        fsl,pins = <
+                                MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
+                                MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
+                                MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
+                                MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
+                                MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
+                                MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
+                                MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
+                                MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
+                                MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
+                                MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
+                                MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
+                                MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
+                                MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
+                                MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
+                                MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
+                                MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
+                                MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
+                                MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
+                                MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
+                                MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
+                                MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
+                                MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
+                                MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
+                                MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
+                                MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
+                                MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
+                        >;
+                };
        };
 };
+&ipu_di0_disp0 {
+        remote-endpoint = <&display_in>;
+};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index be1407cf5abd..9e9deb244b76 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -21,12 +21,11 @@
                reg = <0x90000000 0x20000000>;
        };
-        display@di0 {
+        display0: display@di0 {
                compatible = "fsl,imx-parallel-display";
-                crtcs = <&ipu 0>;
                interface-pix-fmt = "rgb24";
                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_ipu_disp1_1>;
+                pinctrl-0 = <&pinctrl_ipu_disp1>;
                display-timings {
                        native-mode = <&timing0>;
                        timing0: dvi {
@@ -41,14 +40,19 @@
                                vsync-len = <10>;
                        };
                };
+                port {
+                        display0_in: endpoint {
+                                remote-endpoint = <&ipu_di0_disp0>;
+                        };
+                };
        };
-        display@di1 {
+        display1: display@di1 {
                compatible = "fsl,imx-parallel-display";
-                crtcs = <&ipu 1>;
                interface-pix-fmt = "rgb565";
                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_ipu_disp2_1>;
+                pinctrl-0 = <&pinctrl_ipu_disp2>;
                status = "disabled";
                display-timings {
                        native-mode = <&timing1>;
@@ -68,6 +72,12 @@
                                pixelclk-active = <0>;
                        };
                };
+                port {
+                        display1_in: endpoint {
+                                remote-endpoint = <&ipu_di1_disp1>;
+                        };
+                };
        };
        gpio-keys {
@@ -75,12 +85,23 @@
                power {
                        label = "Power Button";
-                        gpios = <&gpio2 21 0>;
+                        gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
                        linux,code = <116>; /* KEY_POWER */
                        gpio-key,wakeup;
                };
        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
+                led-diagnostic {
+                        label = "diagnostic";
+                        gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+                };
+        };
        sound {
                compatible = "fsl,imx51-babbage-sgtl5000",
                             "fsl,imx-audio-sgtl5000";
@@ -105,14 +126,14 @@
                        reg=<0>;
                        #clock-cells = <0>;
                        clock-frequency = <26000000>;
-                        gpios = <&gpio4 26 1>;
+                        gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
                };
        };
 };
 &esdhc1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        pinctrl-0 = <&pinctrl_esdhc1>;
        fsl,cd-controller;
        fsl,wp-controller;
        status = "okay";
@@ -120,24 +141,25 @@
 &esdhc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        pinctrl-0 = <&pinctrl_esdhc2>;
-        cd-gpios = <&gpio1 6 0>;
+        cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
-        wp-gpios = <&gpio1 5 0>;
+        wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
        status = "okay";
 };
 &uart3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>;
+        pinctrl-0 = <&pinctrl_uart3>;
        fsl,uart-has-rtscts;
        status = "okay";
 };
 &ecspi1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        pinctrl-0 = <&pinctrl_ecspi1>;
        fsl,spi-num-chipselects = <2>;
-        cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
+        cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
+                   <&gpio4 25 GPIO_ACTIVE_LOW>;
        status = "okay";
        pmic: mc13892@0 {
@@ -148,7 +170,7 @@
                spi-cs-high;
                reg = <0>;
                interrupt-parent = <&gpio1>;
-                interrupts = <8 0x4>;
+                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
                regulators {
                        sw1_reg: sw1 {
@@ -258,6 +280,14 @@
        };
 };
+&ipu_di0_disp0 {
+        remote-endpoint = <&display0_in>;
+};
+&ipu_di1_disp1 {
+        remote-endpoint = <&display1_in>;
+};
 &ssi2 {
        fsl,mode = "i2s-slave";
        status = "okay";
@@ -267,7 +297,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx51-babbage {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX51_PAD_GPIO1_0__SD1_CD     0x20d5
@@ -280,25 +310,194 @@
                                MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
                        >;
                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0x80000000
+                                MX51_PAD_AUD3_BB_RXD__AUD3_RXD          0x80000000
+                                MX51_PAD_AUD3_BB_CK__AUD3_TXC           0x80000000
+                                MX51_PAD_AUD3_BB_FS__AUD3_TXFS          0x80000000
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
+                                MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
+                                MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
+                                MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
+                                MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
+                                MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
+                                MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
+                                MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
+                        >;
+                };
+                pinctrl_esdhc2: esdhc2grp {
+                        fsl,pins = <
+                                MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
+                                MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
+                                MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
+                                MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
+                                MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
+                                MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX51_PAD_EIM_EB2__FEC_MDIO              0x80000000
+                                MX51_PAD_EIM_EB3__FEC_RDATA1            0x80000000
+                                MX51_PAD_EIM_CS2__FEC_RDATA2            0x80000000
+                                MX51_PAD_EIM_CS3__FEC_RDATA3            0x80000000
+                                MX51_PAD_EIM_CS4__FEC_RX_ER             0x80000000
+                                MX51_PAD_EIM_CS5__FEC_CRS               0x80000000
+                                MX51_PAD_NANDF_RB2__FEC_COL             0x80000000
+                                MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x80000000
+                                MX51_PAD_NANDF_D9__FEC_RDATA0           0x80000000
+                                MX51_PAD_NANDF_D8__FEC_TDATA0           0x80000000
+                                MX51_PAD_NANDF_CS2__FEC_TX_ER           0x80000000
+                                MX51_PAD_NANDF_CS3__FEC_MDC             0x80000000
+                                MX51_PAD_NANDF_CS4__FEC_TDATA1          0x80000000
+                                MX51_PAD_NANDF_CS5__FEC_TDATA2          0x80000000
+                                MX51_PAD_NANDF_CS6__FEC_TDATA3          0x80000000
+                                MX51_PAD_NANDF_CS7__FEC_TX_EN           0x80000000
+                                MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      0x80000000
+                                MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
+                        >;
+                };
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX51_PAD_EIM_D22__GPIO2_6               0x80000000
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
+                                MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
+                        >;
+                };
+                pinctrl_ipu_disp1: ipudisp1grp {
+                        fsl,pins = <
+                                MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
+                                MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
+                                MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
+                                MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
+                                MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
+                                MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
+                                MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
+                                MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
+                                MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
+                                MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
+                                MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
+                                MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
+                                MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
+                                MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
+                                MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
+                                MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
+                                MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
+                                MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
+                                MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
+                                MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
+                                MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
+                                MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
+                                MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
+                                MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
+                                MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
+                                MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
+                        >;
+                };
+                pinctrl_ipu_disp2: ipudisp2grp {
+                        fsl,pins = <
+                                MX51_PAD_DISP2_DAT0__DISP2_DAT0         0x5
+                                MX51_PAD_DISP2_DAT1__DISP2_DAT1         0x5
+                                MX51_PAD_DISP2_DAT2__DISP2_DAT2         0x5
+                                MX51_PAD_DISP2_DAT3__DISP2_DAT3         0x5
+                                MX51_PAD_DISP2_DAT4__DISP2_DAT4         0x5
+                                MX51_PAD_DISP2_DAT5__DISP2_DAT5         0x5
+                                MX51_PAD_DISP2_DAT6__DISP2_DAT6         0x5
+                                MX51_PAD_DISP2_DAT7__DISP2_DAT7         0x5
+                                MX51_PAD_DISP2_DAT8__DISP2_DAT8         0x5
+                                MX51_PAD_DISP2_DAT9__DISP2_DAT9         0x5
+                                MX51_PAD_DISP2_DAT10__DISP2_DAT10       0x5
+                                MX51_PAD_DISP2_DAT11__DISP2_DAT11       0x5
+                                MX51_PAD_DISP2_DAT12__DISP2_DAT12       0x5
+                                MX51_PAD_DISP2_DAT13__DISP2_DAT13       0x5
+                                MX51_PAD_DISP2_DAT14__DISP2_DAT14       0x5
+                                MX51_PAD_DISP2_DAT15__DISP2_DAT15       0x5
+                                MX51_PAD_DI2_PIN2__DI2_PIN2             0x5
+                                MX51_PAD_DI2_PIN3__DI2_PIN3             0x5
+                                MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     0x5
+                                MX51_PAD_DI_GP4__DI2_PIN15              0x5
+                        >;
+                };
+                pinctrl_kpp: kppgrp {
+                        fsl,pins = <
+                                MX51_PAD_KEY_ROW0__KEY_ROW0             0xe0
+                                MX51_PAD_KEY_ROW1__KEY_ROW1             0xe0
+                                MX51_PAD_KEY_ROW2__KEY_ROW2             0xe0
+                                MX51_PAD_KEY_ROW3__KEY_ROW3             0xe0
+                                MX51_PAD_KEY_COL0__KEY_COL0             0xe8
+                                MX51_PAD_KEY_COL1__KEY_COL1             0xe8
+                                MX51_PAD_KEY_COL2__KEY_COL2             0xe8
+                                MX51_PAD_KEY_COL3__KEY_COL3             0xe8
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
+                                MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
+                                MX51_PAD_UART1_RTS__UART1_RTS           0x1c5
+                                MX51_PAD_UART1_CTS__UART1_CTS           0x1c5
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX51_PAD_UART2_RXD__UART2_RXD           0x1c5
+                                MX51_PAD_UART2_TXD__UART2_TXD           0x1c5
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX51_PAD_EIM_D25__UART3_RXD             0x1c5
+                                MX51_PAD_EIM_D26__UART3_TXD             0x1c5
+                                MX51_PAD_EIM_D27__UART3_RTS             0x1c5
+                                MX51_PAD_EIM_D24__UART3_CTS             0x1c5
+                        >;
+                };
        };
 };
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
+        pinctrl-0 = <&pinctrl_uart1>;
        fsl,uart-has-rtscts;
        status = "okay";
 };
 &uart2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2_1>;
+        pinctrl-0 = <&pinctrl_uart2>;
        status = "okay";
 };
 &i2c2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2_1>;
+        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
        sgtl5000: codec@0a {
@@ -312,35 +511,39 @@
 &audmux {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux_1>;
+        pinctrl-0 = <&pinctrl_audmux>;
        status = "okay";
 };
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec_1>;
+        pinctrl-0 = <&pinctrl_fec>;
        phy-mode = "mii";
+        phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+        phy-reset-duration = <1>;
        status = "okay";
 };
 &kpp {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_kpp_1>;
+        pinctrl-0 = <&pinctrl_kpp>;
-        linux,keymap = <0x00000067      /* KEY_UP */
+        linux,keymap = <
-                        0x0001006c      /* KEY_DOWN */
+                MATRIX_KEY(0, 0, KEY_UP)
-                        0x00020072      /* KEY_VOLUMEDOWN */
+                MATRIX_KEY(0, 1, KEY_DOWN)
-                        0x00030066      /* KEY_HOME */
+                MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
-                        0x0100006a      /* KEY_RIGHT */
+                MATRIX_KEY(0, 3, KEY_HOME)
-                        0x01010069      /* KEY_LEFT */
+                MATRIX_KEY(1, 0, KEY_RIGHT)
-                        0x0102001c      /* KEY_ENTER */
+                MATRIX_KEY(1, 1, KEY_LEFT)
-                        0x01030073      /* KEY_VOLUMEUP */
+                MATRIX_KEY(1, 2, KEY_ENTER)
-                        0x02000040      /* KEY_F6 */
+                MATRIX_KEY(1, 3, KEY_VOLUMEUP)
-                        0x02010042      /* KEY_F8 */
+                MATRIX_KEY(2, 0, KEY_F6)
-                        0x02020043      /* KEY_F9 */
+                MATRIX_KEY(2, 1, KEY_F8)
-                        0x02030044      /* KEY_F10 */
+                MATRIX_KEY(2, 2, KEY_F9)
-                        0x0300003b      /* KEY_F1 */
+                MATRIX_KEY(2, 3, KEY_F10)
-                        0x0301003c      /* KEY_F2 */
+                MATRIX_KEY(3, 0, KEY_F1)
-                        0x0302003d      /* KEY_F3 */
+                MATRIX_KEY(3, 1, KEY_F2)
-                        0x03030074>;    /* KEY_POWER */
+                MATRIX_KEY(3, 2, KEY_F3)
+                MATRIX_KEY(3, 3, KEY_POWER)
+                >;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
new file mode 100644
index 000000000000..9b3acf6e4282
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include "imx51.dtsi"
+/ {
+        model = "Eukrea CPUIMX51";
+        compatible = "eukrea,cpuimx51", "fsl,imx51";
+        memory {
+                reg = <0x90000000 0x10000000>; /* 256M */
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        status = "okay";
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        pcf8563@51 {
+                compatible = "nxp,pcf8563";
+                reg = <0x51>;
+        };
+};
+&iomuxc {
+        imx51-eukrea {
+                pinctrl_tsc2007_1: tsc2007grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
+                                MX51_PAD_NANDF_D8__GPIO4_0 0x1f5
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX51_PAD_DI_GP3__FEC_TX_ER              0x80000000
+                                MX51_PAD_DI2_PIN4__FEC_CRS              0x80000000
+                                MX51_PAD_DI2_PIN2__FEC_MDC              0x80000000
+                                MX51_PAD_DI2_PIN3__FEC_MDIO             0x80000000
+                                MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       0x80000000
+                                MX51_PAD_DI_GP4__FEC_RDATA2             0x80000000
+                                MX51_PAD_DISP2_DAT0__FEC_RDATA3         0x80000000
+                                MX51_PAD_DISP2_DAT1__FEC_RX_ER          0x80000000
+                                MX51_PAD_DISP2_DAT6__FEC_TDATA1         0x80000000
+                                MX51_PAD_DISP2_DAT7__FEC_TDATA2         0x80000000
+                                MX51_PAD_DISP2_DAT8__FEC_TDATA3         0x80000000
+                                MX51_PAD_DISP2_DAT9__FEC_TX_EN          0x80000000
+                                MX51_PAD_DISP2_DAT10__FEC_COL           0x80000000
+                                MX51_PAD_DISP2_DAT11__FEC_RX_CLK        0x80000000
+                                MX51_PAD_DISP2_DAT12__FEC_RX_DV         0x80000000
+                                MX51_PAD_DISP2_DAT13__FEC_TX_CLK        0x80000000
+                                MX51_PAD_DISP2_DAT14__FEC_RDATA0        0x80000000
+                                MX51_PAD_DISP2_DAT15__FEC_TDATA0        0x80000000
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX51_PAD_SD2_CMD__I2C1_SCL              0x400001ed
+                                MX51_PAD_SD2_CLK__I2C1_SDA              0x400001ed
+                        >;
+                };
+        };
+};
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
new file mode 100644
index 000000000000..5cec4f322096
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+/dts-v1/;
+#include "imx51-eukrea-cpuimx51.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+/ {
+        model = "Eukrea CPUIMX51";
+        compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51";
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpiokeys_1>;
+                button-1 {
+                        label = "BP1";
+                        gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+                        linux,code = <256>;
+                        gpio-key,wakeup;
+                        linux,input-type = <1>;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpioled>;
+                led1 {
+                        label = "led1";
+                        gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        sound {
+                compatible = "eukrea,asoc-tlv320";
+                eukrea,model = "imx51-eukrea-tlv320aic23";
+                ssi-controller = <&ssi2>;
+                fsl,mux-int-port = <2>;
+                fsl,mux-ext-port = <3>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>;
+        fsl,cd-controller;
+        status = "okay";
+};
+&i2c1 {
+        tlv320aic23: codec@1a {
+                compatible = "ti,tlv320aic23";
+                reg = <0x1a>;
+        };
+};
+&iomuxc {
+        imx51-eukrea {
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0x80000000
+                                MX51_PAD_AUD3_BB_RXD__AUD3_RXD          0x80000000
+                                MX51_PAD_AUD3_BB_CK__AUD3_TXC           0x80000000
+                                MX51_PAD_AUD3_BB_FS__AUD3_TXFS          0x80000000
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
+                                MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
+                                MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
+                                MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
+                                MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
+                                MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
+                                MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX51_PAD_UART3_RXD__UART3_RXD           0x1c5
+                                MX51_PAD_UART3_TXD__UART3_TXD           0x1c5
+                        >;
+                };
+                pinctrl_uart3_rtscts: uart3rtsctsgrp {
+                        fsl,pins = <
+                                MX51_PAD_KEY_COL4__UART3_RTS            0x1c5
+                                MX51_PAD_KEY_COL5__UART3_CTS            0x1c5
+                        >;
+                };
+                pinctrl_backlight_1: backlightgrp-1 {
+                        fsl,pins = <
+                                MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5
+                        >;
+                };
+                pinctrl_esdhc1_cd: esdhc1_cd {
+                        fsl,pins = <
+                                MX51_PAD_GPIO1_0__SD1_CD 0x20d5
+                        >;
+                };
+                pinctrl_gpiokeys_1: gpiokeysgrp-1 {
+                        fsl,pins = <
+                                MX51_PAD_NANDF_D9__GPIO3_31 0x1f5
+                        >;
+                };
+                pinctrl_gpioled: gpioledgrp-1 {
+                        fsl,pins = <
+                                MX51_PAD_NANDF_D10__GPIO3_30 0x80000000
+                        >;
+                };
+                pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
+                        fsl,pins = <
+                                MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
+                        >;
+                };
+        };
+};
+&ssi2 {
+        codec-handle = <&tlv320aic23>;
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 4bcdd3ad15e5..5f8216d08f6b 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -12,6 +12,10 @@
 #include "skeleton.dtsi"
 #include "imx51-pinfunc.h"
+#include <dt-bindings/clock/imx5-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 / {
        aliases {
@@ -21,6 +25,10 @@
                gpio3 = &gpio4;
                i2c0 = &i2c1;
                i2c1 = &i2c2;
+                mmc0 = &esdhc1;
+                mmc1 = &esdhc2;
+                mmc2 = &esdhc3;
+                mmc3 = &esdhc4;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
@@ -64,21 +72,40 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-                cpu@0 {
+                cpu: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a8";
                        reg = <0>;
-                        clock-latency = <61036>; /* two CLK32 periods */
+                        clock-latency = <62500>;
-                        clocks = <&clks 24>;
+                        clocks = <&clks IMX5_CLK_CPU_PODF>;
                        clock-names = "cpu";
                        operating-points = <
-                                /* kHz  uV (No regulator support) */
+                                166000  1000000
-                                160000  0
+                                600000  1050000
-                                800000  0
+                                800000  1100000
                        >;
+                        voltage-tolerance = <5>;
                };
        };
+        usbphy {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "simple-bus";
+                usbphy0: usbphy@0 {
+                        compatible = "usb-nop-xceiv";
+                        reg = <0>;
+                        clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
+                        clock-names = "main_clk";
+                };
+        };
+        display-subsystem {
+                compatible = "fsl,imx-display-subsystem";
+                ports = <&ipu_di0>, <&ipu_di1>;
+        };
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -92,13 +119,30 @@
                };
                ipu: ipu@40000000 {
-                        #crtc-cells = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                        compatible = "fsl,imx51-ipu";
                        reg = <0x40000000 0x20000000>;
                        interrupts = <11 10>;
-                        clocks = <&clks 59>, <&clks 110>, <&clks 61>;
+                        clocks = <&clks IMX5_CLK_IPU_GATE>,
+                                 <&clks IMX5_CLK_IPU_DI0_GATE>,
+                                 <&clks IMX5_CLK_IPU_DI1_GATE>;
                        clock-names = "bus", "di0", "di1";
                        resets = <&src 2>;
+                        ipu_di0: port@2 {
+                                reg = <2>;
+                                ipu_di0_disp0: endpoint {
+                                };
+                        };
+                        ipu_di1: port@3 {
+                                reg = <3>;
+                                ipu_di1_disp1: endpoint {
+                                };
+                        };
                };
                aips@70000000 { /* AIPS1 */
@@ -119,7 +163,9 @@
                                        compatible = "fsl,imx51-esdhc";
                                        reg = <0x70004000 0x4000>;
                                        interrupts = <1>;
-                                        clocks = <&clks 44>, <&clks 0>, <&clks 71>;
+                                        clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
                                        clock-names = "ipg", "ahb", "per";
                                        status = "disabled";
                                };
@@ -128,7 +174,9 @@
                                        compatible = "fsl,imx51-esdhc";
                                        reg = <0x70008000 0x4000>;
                                        interrupts = <2>;
-                                        clocks = <&clks 45>, <&clks 0>, <&clks 72>;
+                                        clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
                                        clock-names = "ipg", "ahb", "per";
                                        bus-width = <4>;
                                        status = "disabled";
@@ -138,7 +186,8 @@
                                        compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                        reg = <0x7000c000 0x4000>;
                                        interrupts = <33>;
-                                        clocks = <&clks 32>, <&clks 33>;
+                                        clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
+                                                 <&clks IMX5_CLK_UART3_PER_GATE>;
                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -149,7 +198,8 @@
                                        compatible = "fsl,imx51-ecspi";
                                        reg = <0x70010000 0x4000>;
                                        interrupts = <36>;
-                                        clocks = <&clks 51>, <&clks 52>;
+                                        clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
+                                                 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -158,7 +208,7 @@
                                        compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                        reg = <0x70014000 0x4000>;
                                        interrupts = <30>;
-                                        clocks = <&clks 49>;
+                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
                                        dmas = <&sdma 24 1 0>,
                                               <&sdma 25 1 0>;
                                        dma-names = "rx", "tx";
@@ -171,7 +221,9 @@
                                        compatible = "fsl,imx51-esdhc";
                                        reg = <0x70020000 0x4000>;
                                        interrupts = <3>;
-                                        clocks = <&clks 46>, <&clks 0>, <&clks 73>;
+                                        clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
                                        clock-names = "ipg", "ahb", "per";
                                        bus-width = <4>;
                                        status = "disabled";
@@ -181,25 +233,20 @@
                                        compatible = "fsl,imx51-esdhc";
                                        reg = <0x70024000 0x4000>;
                                        interrupts = <4>;
-                                        clocks = <&clks 47>, <&clks 0>, <&clks 74>;
+                                        clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
                                        clock-names = "ipg", "ahb", "per";
                                        bus-width = <4>;
                                        status = "disabled";
                                };
                        };
-                        usbphy0: usbphy@0 {
-                                compatible = "usb-nop-xceiv";
-                                clocks = <&clks 75>;
-                                clock-names = "main_clk";
-                                status = "okay";
-                        };
                        usbotg: usb@73f80000 {
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80000 0x0200>;
                                interrupts = <18>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 0>;
                                fsl,usbphy = <&usbphy0>;
                                status = "disabled";
@@ -209,7 +256,7 @@
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80200 0x0200>;
                                interrupts = <14>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 1>;
                                status = "disabled";
                        };
@@ -218,7 +265,7 @@
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80400 0x0200>;
                                interrupts = <16>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 2>;
                                status = "disabled";
                        };
@@ -227,7 +274,7 @@
                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                reg = <0x73f80600 0x0200>;
                                interrupts = <17>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 3>;
                                status = "disabled";
                        };
@@ -236,7 +283,7 @@
                                #index-cells = <1>;
                                compatible = "fsl,imx51-usbmisc";
                                reg = <0x73f80800 0x200>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                        };
                        gpio1: gpio@73f84000 {
@@ -283,7 +330,7 @@
                                compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
                                reg = <0x73f94000 0x4000>;
                                interrupts = <60>;
-                                clocks = <&clks 0>;
+                                clocks = <&clks IMX5_CLK_DUMMY>;
                                status = "disabled";
                        };
@@ -291,14 +338,14 @@
                                compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                reg = <0x73f98000 0x4000>;
                                interrupts = <58>;
-                                clocks = <&clks 0>;
+                                clocks = <&clks IMX5_CLK_DUMMY>;
                        };
                        wdog2: wdog@73f9c000 {
                                compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                reg = <0x73f9c000 0x4000>;
                                interrupts = <59>;
-                                clocks = <&clks 0>;
+                                clocks = <&clks IMX5_CLK_DUMMY>;
                                status = "disabled";
                        };
@@ -306,7 +353,8 @@
                                compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
                                reg = <0x73fa0000 0x4000>;
                                interrupts = <39>;
-                                clocks = <&clks 36>, <&clks 41>;
+                                clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
+                                         <&clks IMX5_CLK_GPT_HF_GATE>;
                                clock-names = "ipg", "per";
                        };
@@ -319,7 +367,8 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
                                reg = <0x73fb4000 0x4000>;
-                                clocks = <&clks 37>, <&clks 38>;
+                                clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
+                                         <&clks IMX5_CLK_PWM1_HF_GATE>;
                                clock-names = "ipg", "per";
                                interrupts = <61>;
                        };
@@ -328,7 +377,8 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
                                reg = <0x73fb8000 0x4000>;
-                                clocks = <&clks 39>, <&clks 40>;
+                                clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
+                                         <&clks IMX5_CLK_PWM2_HF_GATE>;
                                clock-names = "ipg", "per";
                                interrupts = <94>;
                        };
@@ -337,7 +387,8 @@
                                compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                reg = <0x73fbc000 0x4000>;
                                interrupts = <31>;
-                                clocks = <&clks 28>, <&clks 29>;
+                                clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART1_PER_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -346,7 +397,8 @@
                                compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                reg = <0x73fc0000 0x4000>;
                                interrupts = <32>;
-                                clocks = <&clks 30>, <&clks 31>;
+                                clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART2_PER_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -376,14 +428,14 @@
                                compatible = "fsl,imx51-iim", "fsl,imx27-iim";
                                reg = <0x83f98000 0x4000>;
                                interrupts = <69>;
-                                clocks = <&clks 107>;
+                                clocks = <&clks IMX5_CLK_IIM_GATE>;
                        };
                        owire: owire@83fa4000 {
                                compatible = "fsl,imx51-owire", "fsl,imx21-owire";
                                reg = <0x83fa4000 0x4000>;
                                interrupts = <88>;
-                                clocks = <&clks 159>;
+                                clocks = <&clks IMX5_CLK_OWIRE_GATE>;
                                status = "disabled";
                        };
@@ -393,7 +445,8 @@
                                compatible = "fsl,imx51-ecspi";
                                reg = <0x83fac000 0x4000>;
                                interrupts = <37>;
-                                clocks = <&clks 53>, <&clks 54>;
+                                clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
+                                         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -402,7 +455,8 @@
                                compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
                                reg = <0x83fb0000 0x4000>;
                                interrupts = <6>;
-                                clocks = <&clks 56>, <&clks 56>;
+                                clocks = <&clks IMX5_CLK_SDMA_GATE>,
+                                         <&clks IMX5_CLK_SDMA_GATE>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
@@ -414,7 +468,8 @@
                                compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
                                reg = <0x83fc0000 0x4000>;
                                interrupts = <38>;
-                                clocks = <&clks 55>, <&clks 55>;
+                                clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
+                                         <&clks IMX5_CLK_CSPI_IPG_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -425,7 +480,7 @@
                                compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
                                reg = <0x83fc4000 0x4000>;
                                interrupts = <63>;
-                                clocks = <&clks 35>;
+                                clocks = <&clks IMX5_CLK_I2C2_GATE>;
                                status = "disabled";
                        };
@@ -435,7 +490,7 @@
                                compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
                                reg = <0x83fc8000 0x4000>;
                                interrupts = <62>;
-                                clocks = <&clks 34>;
+                                clocks = <&clks IMX5_CLK_I2C1_GATE>;
                                status = "disabled";
                        };
@@ -443,7 +498,7 @@
                                compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                reg = <0x83fcc000 0x4000>;
                                interrupts = <29>;
-                                clocks = <&clks 48>;
+                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
                                dmas = <&sdma 28 0 0>,
                                       <&sdma 29 0 0>;
                                dma-names = "rx", "tx";
@@ -455,6 +510,8 @@
                        audmux: audmux@83fd0000 {
                                compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
                                reg = <0x83fd0000 0x4000>;
+                                clocks = <&clks IMX5_CLK_DUMMY>;
+                                clock-names = "audmux";
                                status = "disabled";
                        };
@@ -463,7 +520,7 @@
                                #size-cells = <1>;
                                compatible = "fsl,imx51-weim";
                                reg = <0x83fda000 0x1000>;
-                                clocks = <&clks 57>;
+                                clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
                                ranges = <
                                        0 0 0xb0000000 0x08000000
                                        1 0 0xb8000000 0x08000000
@@ -479,7 +536,7 @@
                                compatible = "fsl,imx51-nand";
                                reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
                                interrupts = <8>;
-                                clocks = <&clks 60>;
+                                clocks = <&clks IMX5_CLK_NFC_GATE>;
                                status = "disabled";
                        };
@@ -487,7 +544,7 @@
                                compatible = "fsl,imx51-pata", "fsl,imx27-pata";
                                reg = <0x83fe0000 0x4000>;
                                interrupts = <70>;
-                                clocks = <&clks 172>;
+                                clocks = <&clks IMX5_CLK_PATA_GATE>;
                                status = "disabled";
                        };
@@ -495,7 +552,7 @@
                                compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                reg = <0x83fe8000 0x4000>;
                                interrupts = <96>;
-                                clocks = <&clks 50>;
+                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
                                dmas = <&sdma 46 0 0>,
                                       <&sdma 47 0 0>;
                                dma-names = "rx", "tx";
@@ -508,336 +565,12 @@
                                compatible = "fsl,imx51-fec", "fsl,imx27-fec";
                                reg = <0x83fec000 0x4000>;
                                interrupts = <87>;
-                                clocks = <&clks 42>, <&clks 42>, <&clks 42>;
+                                clocks = <&clks IMX5_CLK_FEC_GATE>,
+                                         <&clks IMX5_CLK_FEC_GATE>,
+                                         <&clks IMX5_CLK_FEC_GATE>;
                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
                        };
                };
        };
 };
-&iomuxc {
-        audmux {
-                pinctrl_audmux_1: audmuxgrp-1 {
-                        fsl,pins = <
-                                MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
-                                MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
-                                MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
-                                MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
-                        >;
-                };
-        };
-        fec {
-                pinctrl_fec_1: fecgrp-1 {
-                        fsl,pins = <
-                                MX51_PAD_EIM_EB2__FEC_MDIO         0x80000000
-                                MX51_PAD_EIM_EB3__FEC_RDATA1       0x80000000
-                                MX51_PAD_EIM_CS2__FEC_RDATA2       0x80000000
-                                MX51_PAD_EIM_CS3__FEC_RDATA3       0x80000000
-                                MX51_PAD_EIM_CS4__FEC_RX_ER        0x80000000
-                                MX51_PAD_EIM_CS5__FEC_CRS          0x80000000
-                                MX51_PAD_NANDF_RB2__FEC_COL        0x80000000
-                                MX51_PAD_NANDF_RB3__FEC_RX_CLK     0x80000000
-                                MX51_PAD_NANDF_D9__FEC_RDATA0      0x80000000
-                                MX51_PAD_NANDF_D8__FEC_TDATA0      0x80000000
-                                MX51_PAD_NANDF_CS2__FEC_TX_ER      0x80000000
-                                MX51_PAD_NANDF_CS3__FEC_MDC        0x80000000
-                                MX51_PAD_NANDF_CS4__FEC_TDATA1     0x80000000
-                                MX51_PAD_NANDF_CS5__FEC_TDATA2     0x80000000
-                                MX51_PAD_NANDF_CS6__FEC_TDATA3     0x80000000
-                                MX51_PAD_NANDF_CS7__FEC_TX_EN      0x80000000
-                                MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
-                        >;
-                };
-                pinctrl_fec_2: fecgrp-2 {
-                        fsl,pins = <
-                                MX51_PAD_DI_GP3__FEC_TX_ER        0x80000000
-                                MX51_PAD_DI2_PIN4__FEC_CRS        0x80000000
-                                MX51_PAD_DI2_PIN2__FEC_MDC        0x80000000
-                                MX51_PAD_DI2_PIN3__FEC_MDIO       0x80000000
-                                MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
-                                MX51_PAD_DI_GP4__FEC_RDATA2       0x80000000
-                                MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
-                                MX51_PAD_DISP2_DAT1__FEC_RX_ER    0x80000000
-                                MX51_PAD_DISP2_DAT6__FEC_TDATA1   0x80000000
-                                MX51_PAD_DISP2_DAT7__FEC_TDATA2   0x80000000
-                                MX51_PAD_DISP2_DAT8__FEC_TDATA3   0x80000000
-                                MX51_PAD_DISP2_DAT9__FEC_TX_EN    0x80000000
-                                MX51_PAD_DISP2_DAT10__FEC_COL     0x80000000
-                                MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
-                                MX51_PAD_DISP2_DAT12__FEC_RX_DV   0x80000000
-                                MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
-                                MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
-                                MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
-                        >;
-                };
-        };
-        ecspi1 {
-                pinctrl_ecspi1_1: ecspi1grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
-                                MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
-                                MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
-                        >;
-                };
-        };
-        ecspi2 {
-                pinctrl_ecspi2_1: ecspi2grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
-                                MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
-                                MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
-                        >;
-                };
-        };
-        esdhc1 {
-                pinctrl_esdhc1_1: esdhc1grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
-                                MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
-                                MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
-                                MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
-                                MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
-                                MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
-                        >;
-                };
-        };
-        esdhc2 {
-                pinctrl_esdhc2_1: esdhc2grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
-                                MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
-                                MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
-                                MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
-                                MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
-                                MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
-                        >;
-                };
-        };
-        i2c2 {
-                pinctrl_i2c2_1: i2c2grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
-                                MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
-                        >;
-                };
-                pinctrl_i2c2_2: i2c2grp-2 {
-                        fsl,pins = <
-                                MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
-                                MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
-                        >;
-                };
-                pinctrl_i2c2_3: i2c2grp-3 {
-                        fsl,pins = <
-                                MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
-                                MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
-                        >;
-                };
-        };
-        ipu_disp1 {
-                pinctrl_ipu_disp1_1: ipudisp1grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_DISP1_DAT0__DISP1_DAT0   0x5
-                                MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
-                                MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
-                                MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
-                                MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
-                                MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
-                                MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
-                                MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
-                                MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
-                                MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
-                                MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
-                                MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
-                                MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
-                                MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
-                                MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
-                                MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
-                                MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
-                                MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
-                                MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
-                                MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
-                                MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
-                                MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
-                                MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
-                                MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
-                                MX51_PAD_DI1_PIN2__DI1_PIN2       0x5 /* hsync */
-                                MX51_PAD_DI1_PIN3__DI1_PIN3       0x5 /* vsync */
-                        >;
-                };
-        };
-        ipu_disp2 {
-                pinctrl_ipu_disp2_1: ipudisp2grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
-                                MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
-                                MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
-                                MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
-                                MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
-                                MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
-                                MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
-                                MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
-                                MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
-                                MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
-                                MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
-                                MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
-                                MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
-                                MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
-                                MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
-                                MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
-                                MX51_PAD_DI2_PIN2__DI2_PIN2         0x5 /* hsync */
-                                MX51_PAD_DI2_PIN3__DI2_PIN3         0x5 /* vsync */
-                                MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
-                                MX51_PAD_DI_GP4__DI2_PIN15          0x5 /* DE */
-                        >;
-                };
-        };
-        kpp {
-                pinctrl_kpp_1: kppgrp-1 {
-                        fsl,pins = <
-                                MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
-                                MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
-                                MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
-                                MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
-                                MX51_PAD_KEY_COL0__KEY_COL0 0xe8
-                                MX51_PAD_KEY_COL1__KEY_COL1 0xe8
-                                MX51_PAD_KEY_COL2__KEY_COL2 0xe8
-                                MX51_PAD_KEY_COL3__KEY_COL3 0xe8
-                        >;
-                };
-        };
-        pata {
-                pinctrl_pata_1: patagrp-1 {
-                        fsl,pins = <
-                                MX51_PAD_NANDF_WE_B__PATA_DIOW     0x2004
-                                MX51_PAD_NANDF_RE_B__PATA_DIOR     0x2004
-                                MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
-                                MX51_PAD_NANDF_CLE__PATA_RESET_B   0x2004
-                                MX51_PAD_NANDF_WP_B__PATA_DMACK    0x2004
-                                MX51_PAD_NANDF_RB0__PATA_DMARQ     0x2004
-                                MX51_PAD_NANDF_RB1__PATA_IORDY     0x2004
-                                MX51_PAD_GPIO_NAND__PATA_INTRQ     0x2004
-                                MX51_PAD_NANDF_CS2__PATA_CS_0      0x2004
-                                MX51_PAD_NANDF_CS3__PATA_CS_1      0x2004
-                                MX51_PAD_NANDF_CS4__PATA_DA_0      0x2004
-                                MX51_PAD_NANDF_CS5__PATA_DA_1      0x2004
-                                MX51_PAD_NANDF_CS6__PATA_DA_2      0x2004
-                                MX51_PAD_NANDF_D15__PATA_DATA15    0x2004
-                                MX51_PAD_NANDF_D14__PATA_DATA14    0x2004
-                                MX51_PAD_NANDF_D13__PATA_DATA13    0x2004
-                                MX51_PAD_NANDF_D12__PATA_DATA12    0x2004
-                                MX51_PAD_NANDF_D11__PATA_DATA11    0x2004
-                                MX51_PAD_NANDF_D10__PATA_DATA10    0x2004
-                                MX51_PAD_NANDF_D9__PATA_DATA9      0x2004
-                                MX51_PAD_NANDF_D8__PATA_DATA8      0x2004
-                                MX51_PAD_NANDF_D7__PATA_DATA7      0x2004
-                                MX51_PAD_NANDF_D6__PATA_DATA6     0x2004
-                                MX51_PAD_NANDF_D5__PATA_DATA5     0x2004
-                                MX51_PAD_NANDF_D4__PATA_DATA4     0x2004
-                                MX51_PAD_NANDF_D3__PATA_DATA3     0x2004
-                                MX51_PAD_NANDF_D2__PATA_DATA2     0x2004
-                                MX51_PAD_NANDF_D1__PATA_DATA1     0x2004
-                                MX51_PAD_NANDF_D0__PATA_DATA0     0x2004
-                        >;
-                };
-        };
-        uart1 {
-                pinctrl_uart1_1: uart1grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
-                                MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
-                        >;
-                };
-                pinctrl_uart1_rtscts_1: uart1rtscts-1 {
-                        fsl,pins = <
-                                MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
-                                MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
-                        >;
-                };
-        };
-        uart2 {
-                pinctrl_uart2_1: uart2grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
-                                MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
-                        >;
-                };
-        };
-        uart3 {
-                pinctrl_uart3_1: uart3grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_EIM_D25__UART3_RXD 0x1c5
-                                MX51_PAD_EIM_D26__UART3_TXD 0x1c5
-                        >;
-                };
-                pinctrl_uart3_rtscts_1: uart3rtscts-1 {
-                        fsl,pins = <
-                                MX51_PAD_EIM_D27__UART3_RTS 0x1c5
-                                MX51_PAD_EIM_D24__UART3_CTS 0x1c5
-                        >;
-                };
-                pinctrl_uart3_2: uart3grp-2 {
-                        fsl,pins = <
-                                MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
-                                MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
-                        >;
-                };
-        };
-        usbh1 {
-                pinctrl_usbh1_1: usbh1grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
-                                MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
-                                MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
-                                MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
-                                MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
-                                MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
-                                MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
-                                MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
-                                MX51_PAD_USBH1_CLK__USBH1_CLK     0x1e5
-                                MX51_PAD_USBH1_DIR__USBH1_DIR     0x1e5
-                                MX51_PAD_USBH1_NXT__USBH1_NXT     0x1e5
-                                MX51_PAD_USBH1_STP__USBH1_STP     0x1e5
-                        >;
-                };
-        };
-        usbh2 {
-                pinctrl_usbh2_1: usbh2grp-1 {
-                        fsl,pins = <
-                                MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
-                                MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
-                                MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
-                                MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
-                                MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
-                                MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
-                                MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
-                                MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
-                                MX51_PAD_EIM_A24__USBH2_CLK   0x1e5
-                                MX51_PAD_EIM_A25__USBH2_DIR   0x1e5
-                                MX51_PAD_EIM_A27__USBH2_NXT   0x1e5
-                                MX51_PAD_EIM_A26__USBH2_STP   0x1e5
-                        >;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 174f86938c89..e9337ad52f59 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -49,9 +49,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3p3v: 3p3v {
+                reg_3p3v: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
@@ -99,7 +102,7 @@
 &esdhc1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1_2>;
+        pinctrl-0 = <&pinctrl_esdhc1>;
        cd-gpios = <&gpio1 1 0>;
        wp-gpios = <&gpio1 9 0>;
        status = "okay";
@@ -109,7 +112,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx53-ard {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX53_PAD_GPIO_1__GPIO1_1             0x80000000
@@ -148,11 +151,33 @@
                                MX53_PAD_EIM_CS1__EMI_WEIM_CS_1      0x80000000
                        >;
                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
+                                MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
+                                MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
+                                MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
+                                MX53_PAD_PATA_DATA8__ESDHC1_DAT4        0x1d5
+                                MX53_PAD_PATA_DATA9__ESDHC1_DAT5        0x1d5
+                                MX53_PAD_PATA_DATA10__ESDHC1_DAT6       0x1d5
+                                MX53_PAD_PATA_DATA11__ESDHC1_DAT7       0x1d5
+                                MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
+                                MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DIOW__UART1_TXD_MUX       0x1e4
+                                MX53_PAD_PATA_DMACK__UART1_RXD_MUX      0x1e4
+                        >;
+                };
        };
 };
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_2>;
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
deleted file mode 100644
index 801fda728ed6..000000000000
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-/dts-v1/;
-#include "imx53.dtsi"
-/ {
-        model = "Freescale i.MX53 Evaluation Kit";
-        compatible = "fsl,imx53-evk", "fsl,imx53";
-        memory {
-                reg = <0x70000000 0x80000000>;
-        };
-        leds {
-                compatible = "gpio-leds";
-                green {
-                        label = "Heartbeat";
-                        gpios = <&gpio7 7 0>;
-                        linux,default-trigger = "heartbeat";
-                };
-        };
-};
-&esdhc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1_1>;
-        cd-gpios = <&gpio3 13 0>;
-        wp-gpios = <&gpio3 14 0>;
-        status = "okay";
-};
-&ecspi1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_1>;
-        fsl,spi-num-chipselects = <2>;
-        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
-        status = "okay";
-        flash: at45db321d@1 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
-                spi-max-frequency = <25000000>;
-                reg = <1>;
-                partition@0 {
-                        label = "U-Boot";
-                        reg = <0x0 0x40000>;
-                        read-only;
-                };
-                partition@40000 {
-                        label = "Kernel";
-                        reg = <0x40000 0x3c0000>;
-                };
-        };
-};
-&esdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc3_1>;
-        cd-gpios = <&gpio3 11 0>;
-        wp-gpios = <&gpio3 12 0>;
-        status = "okay";
-};
-&iomuxc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
-        hog {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX53_PAD_EIM_EB2__GPIO2_30  0x80000000
-                                MX53_PAD_EIM_D19__GPIO3_19  0x80000000
-                                MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
-                                MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
-                                MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
-                                MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
-                                MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
-                                MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
-                        >;
-                };
-        };
-};
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
-        status = "okay";
-};
-&i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2_1>;
-        status = "okay";
-        pmic: mc13892@08 {
-                compatible = "fsl,mc13892", "fsl,mc13xxx";
-                reg = <0x08>;
-        };
-        codec: sgtl5000@0a {
-                compatible = "fsl,sgtl5000";
-                reg = <0x0a>;
-        };
-};
-&fec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec_1>;
-        phy-mode = "rmii";
-        phy-reset-gpios = <&gpio7 6 0>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index 7d304d02ed38..f6d3ac3e5587 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -21,12 +21,11 @@
        };
        soc {
-                display@di1 {
+                display1: display@di1 {
                        compatible = "fsl,imx-parallel-display";
-                        crtcs = <&ipu 1>;
                        interface-pix-fmt = "bgr666";
                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_ipu_disp2_1>;
+                        pinctrl-0 = <&pinctrl_ipu_disp1>;
                        display-timings {
                                800x480p60 {
@@ -44,6 +43,12 @@
                                };
                        };
                };
+                port {
+                        display1_in: endpoint {
+                                remote-endpoint = <&ipu_di1_disp1>;
+                        };
+                };
        };
        backlight {
@@ -51,6 +56,7 @@
                pwms = <&pwm1 0 3000>;
                brightness-levels = <0 4 8 16 32 64 128 255>;
                default-brightness-level = <6>;
+                power-supply = <&reg_backlight>;
        };
        leds {
@@ -73,14 +79,36 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3p2v: 3p2v {
+                reg_3p2v: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "3P2V";
                        regulator-min-microvolt = <3200000>;
                        regulator-max-microvolt = <3200000>;
                        regulator-always-on;
                };
+                reg_backlight: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "lcd-supply";
+                        regulator-min-microvolt = <3200000>;
+                        regulator-max-microvolt = <3200000>;
+                        regulator-always-on;
+                };
+                reg_usbh1_vbus: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 2 0>;
+                };
        };
        sound {
@@ -102,25 +130,25 @@
 &audmux {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux_2>;
+        pinctrl-0 = <&pinctrl_audmux>;
        status = "okay";
 };
 &can1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_can1_3>;
+        pinctrl-0 = <&pinctrl_can1>;
        status = "okay";
 };
 &can2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_can2_1>;
+        pinctrl-0 = <&pinctrl_can2>;
        status = "okay";
 };
 &esdhc1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        pinctrl-0 = <&pinctrl_esdhc1>;
        cd-gpios = <&gpio1 1 0>;
        wp-gpios = <&gpio1 9 0>;
        status = "okay";
@@ -128,14 +156,14 @@
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec_1>;
+        pinctrl-0 = <&pinctrl_fec>;
        phy-mode = "rmii";
        status = "okay";
 };
 &i2c1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1_2>;
+        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";
        sgtl5000: codec@0a {
@@ -143,13 +171,13 @@
                reg = <0x0a>;
                VDDA-supply = <&reg_3p2v>;
                VDDIO-supply = <&reg_3p2v>;
-                clocks = <&clks 150>;
+                clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
        };
 };
 &i2c2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2_2>;
+        pinctrl-0 = <&pinctrl_i2c2>;
        clock-frequency = <400000>;
        status = "okay";
@@ -193,7 +221,7 @@
 &i2c3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c3_1>;
+        pinctrl-0 = <&pinctrl_i2c3>;
        status = "okay";
 };
@@ -201,14 +229,14 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx53-m53evk {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x80000000
                                MX53_PAD_EIM_EB3__GPIO2_31              0x80000000
                                MX53_PAD_PATA_DA_0__GPIO7_6             0x80000000
-                                MX53_PAD_DISP0_DAT8__PWM1_PWMO          0x5
+                                MX53_PAD_GPIO_2__GPIO1_2                0x80000000
+                                MX53_PAD_GPIO_3__USBOH3_USBH1_OC        0x80000000
                        >;
                };
@@ -218,12 +246,172 @@
                                MX53_PAD_PATA_DATA9__GPIO2_9            0x80000000
                        >;
                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
+                                MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
+                                MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
+                                MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
+                        >;
+                };
+                pinctrl_can1: can1grp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_7__CAN1_TXCAN             0x80000000
+                                MX53_PAD_GPIO_8__CAN1_RXCAN             0x80000000
+                        >;
+                };
+                pinctrl_can2: can2grp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_COL4__CAN2_TXCAN           0x80000000
+                                MX53_PAD_KEY_ROW4__CAN2_RXCAN           0x80000000
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
+                                MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
+                                MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
+                                MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
+                                MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
+                                MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
+                                MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
+                                MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
+                                MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
+                                MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
+                                MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
+                                MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
+                                MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                                MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
+                                MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D21__I2C1_SCL              0xc0000000
+                                MX53_PAD_EIM_D28__I2C1_SDA              0xc0000000
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D16__I2C2_SDA              0xc0000000
+                                MX53_PAD_EIM_EB2__I2C2_SCL              0xc0000000
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_6__I2C3_SDA               0xc0000000
+                                MX53_PAD_GPIO_5__I2C3_SCL               0xc0000000
+                        >;
+                };
+                pinctrl_ipu_disp1: ipudisp1grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
+                                MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
+                                MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
+                                MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
+                                MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
+                                MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
+                                MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
+                                MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
+                                MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
+                                MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
+                                MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
+                                MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
+                                MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
+                                MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
+                                MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
+                                MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
+                                MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
+                                MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
+                                MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
+                                MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
+                                MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
+                                MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
+                                MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
+                                MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
+                                MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
+                                MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
+                                MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
+                                MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
+                                MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
+                                MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
+                                MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
+                                MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
+                        >;
+                };
+                pinctrl_nand: nandgrp {
+                        fsl,pins = <
+                                MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
+                                MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
+                                MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
+                                MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
+                                MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
+                                MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
+                                MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
+                                MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
+                                MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
+                                MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
+                                MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
+                                MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
+                                MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
+                                MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
+                                MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
+                        >;
+                };
+                pinctrl_pwm1: pwm1grp {
+                        fsl,pins = <
+                                MX53_PAD_DISP0_DAT8__PWM1_PWMO          0x5
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DIOW__UART1_TXD_MUX       0x1e4
+                                MX53_PAD_PATA_DMACK__UART1_RXD_MUX      0x1e4
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1e4
+                                MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1e4
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_CS_0__UART3_TXD_MUX       0x1e4
+                                MX53_PAD_PATA_CS_1__UART3_RXD_MUX       0x1e4
+                                MX53_PAD_PATA_DA_1__UART3_CTS           0x1e4
+                                MX53_PAD_PATA_DA_2__UART3_RTS           0x1e4
+                        >;
+                };
        };
 };
+&ipu_di1_disp1 {
+        remote-endpoint = <&display1_in>;
+};
 &nfc {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_nand_1>;
+        pinctrl-0 = <&pinctrl_nand>;
        nand-bus-width = <8>;
        nand-ecc-mode = "hw";
        status = "okay";
@@ -231,7 +419,11 @@
 &pwm1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm1_1>;
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+&sata {
        status = "okay";
 };
@@ -242,18 +434,29 @@
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_2>;
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 &uart2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2_1>;
+        pinctrl-0 = <&pinctrl_uart2>;
        status = "okay";
 };
 &uart3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart3_1>;
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+&usbh1 {
+        vbus-supply = <&reg_usbh1_vbus>;
+        phy_type = "utmi";
+        status = "okay";
+};
+&usbotg {
+        dr_mode = "peripheral";
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index a63090267941..7c8c12969892 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -17,14 +17,6 @@
        model = "TQ MBa53 starter kit";
        compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
-        reg_backlight: fixed@0 {
-                compatible = "regulator-fixed";
-                regulator-name = "lcd-supply";
-                gpio = <&gpio2 5 0>;
-                startup-delay-us = <5000>;
-                enable-active-low;
-        };
        backlight {
                compatible = "pwm-backlight";
                pwms = <&pwm2 0 50000>;
@@ -38,17 +30,37 @@
                compatible = "fsl,imx-parallel-display";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_disp1_1>;
-                crtcs = <&ipu 1>;
                interface-pix-fmt = "rgb24";
                status = "disabled";
+                port {
+                        display1_in: endpoint {
+                                remote-endpoint = <&ipu_di1_disp1>;
+                        };
+                };
        };
-        reg_3p2v: 3p2v {
+        regulators {
-                compatible = "regulator-fixed";
+                compatible = "simple-bus";
-                regulator-name = "3P2V";
+                #address-cells = <1>;
-                regulator-min-microvolt = <3200000>;
+                #size-cells = <0>;
-                regulator-max-microvolt = <3200000>;
-                regulator-always-on;
+                reg_backlight: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "lcd-supply";
+                        gpio = <&gpio2 5 0>;
+                        startup-delay-us = <5000>;
+                };
+                reg_3p2v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "3P2V";
+                        regulator-min-microvolt = <3200000>;
+                        regulator-max-microvolt = <3200000>;
+                        regulator-always-on;
+                };
        };
        sound {
@@ -141,6 +153,10 @@
        };
 };
+&ipu_di1_disp1 {
+        remote-endpoint = <&display1_in>;
+};
 &cspi {
        status = "okay";
 };
@@ -148,14 +164,14 @@
 &audmux {
        status = "okay";
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux_1>;
+        pinctrl-0 = <&pinctrl_audmux>;
 };
 &i2c2 {
        codec: sgtl5000@a {
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
-                clocks = <&clks 150>;
+                clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
                VDDA-supply = <&reg_3p2v>;
                VDDIO-supply = <&reg_3p2v>;
        };
@@ -228,7 +244,7 @@
 &tve {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_vga_sync_1>;
-        ddc = <&i2c3>;
+        i2c-ddc-bus = <&i2c3>;
        fsl,tve-mode = "vga";
        fsl,hsync-pin = <4>;
        fsl,vsync-pin = <6>;
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
new file mode 100644
index 000000000000..3f825a6813da
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -0,0 +1,345 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include "imx53.dtsi"
+/ {
+        memory {
+                reg = <0x70000000 0x40000000>;
+        };
+        display0: display@di0 {
+                compatible = "fsl,imx-parallel-display";
+                interface-pix-fmt = "rgb565";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ipu_disp0>;
+                status = "disabled";
+                display-timings {
+                        claawvga {
+                                native-mode;
+                                clock-frequency = <27000000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <40>;
+                                hfront-porch = <60>;
+                                vback-porch = <10>;
+                                vfront-porch = <10>;
+                                hsync-len = <20>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+                port {
+                        display0_in: endpoint {
+                                remote-endpoint = <&ipu_di0_disp0>;
+                        };
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                power {
+                        label = "Power Button";
+                        gpios = <&gpio1 8 0>;
+                        linux,code = <116>; /* KEY_POWER */
+                };
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio2 14 0>;
+                        linux,code = <115>; /* KEY_VOLUMEUP */
+                        gpio-key,wakeup;
+                };
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio2 15 0>;
+                        linux,code = <114>; /* KEY_VOLUMEDOWN */
+                        gpio-key,wakeup;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pin_gpio7_7>;
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio7 7 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_3p2v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "3P2V";
+                        regulator-min-microvolt = <3200000>;
+                        regulator-max-microvolt = <3200000>;
+                        regulator-always-on;
+                };
+                reg_usb_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio7 8 0>;
+                        enable-active-high;
+                };
+        };
+        sound {
+                compatible = "fsl,imx53-qsb-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx53-qsb-sgtl5000";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <2>;
+                mux-ext-port = <5>;
+        };
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        status = "okay";
+};
+&ipu_di0_disp0 {
+        remote-endpoint = <&display0_in>;
+};
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&esdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc3>;
+        cd-gpios = <&gpio3 11 0>;
+        wp-gpios = <&gpio3 12 0>;
+        bus-width = <8>;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx53-qsb {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
+                                MX53_PAD_GPIO_8__GPIO1_8          0x80000000
+                                MX53_PAD_PATA_DATA14__GPIO2_14    0x80000000
+                                MX53_PAD_PATA_DATA15__GPIO2_15    0x80000000
+                                MX53_PAD_EIM_DA11__GPIO3_11       0x80000000
+                                MX53_PAD_EIM_DA12__GPIO3_12       0x80000000
+                                MX53_PAD_PATA_DA_0__GPIO7_6       0x80000000
+                                MX53_PAD_PATA_DA_2__GPIO7_8       0x80000000
+                                MX53_PAD_GPIO_16__GPIO7_11        0x80000000
+                        >;
+                };
+                led_pin_gpio7_7: led_gpio7_7@0 {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
+                        >;
+                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC      0x80000000
+                                MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD      0x80000000
+                                MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS     0x80000000
+                                MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD      0x80000000
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
+                                MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
+                                MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
+                                MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
+                                MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
+                                MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
+                        >;
+                };
+                pinctrl_esdhc3: esdhc3grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DATA8__ESDHC3_DAT0        0x1d5
+                                MX53_PAD_PATA_DATA9__ESDHC3_DAT1        0x1d5
+                                MX53_PAD_PATA_DATA10__ESDHC3_DAT2       0x1d5
+                                MX53_PAD_PATA_DATA11__ESDHC3_DAT3       0x1d5
+                                MX53_PAD_PATA_DATA0__ESDHC3_DAT4        0x1d5
+                                MX53_PAD_PATA_DATA1__ESDHC3_DAT5        0x1d5
+                                MX53_PAD_PATA_DATA2__ESDHC3_DAT6        0x1d5
+                                MX53_PAD_PATA_DATA3__ESDHC3_DAT7        0x1d5
+                                MX53_PAD_PATA_RESET_B__ESDHC3_CMD       0x1d5
+                                MX53_PAD_PATA_IORDY__ESDHC3_CLK         0x1d5
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
+                                MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
+                                MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
+                                MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
+                                MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
+                                MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
+                                MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
+                                MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                                MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
+                                MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX53_PAD_CSI0_DAT8__I2C1_SDA            0xc0000000
+                                MX53_PAD_CSI0_DAT9__I2C1_SCL            0xc0000000
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_ROW3__I2C2_SDA             0xc0000000
+                                MX53_PAD_KEY_COL3__I2C2_SCL             0xc0000000
+                        >;
+                };
+                pinctrl_ipu_disp0: ipudisp0grp {
+                        fsl,pins = <
+                                MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
+                                MX53_PAD_DI0_PIN15__IPU_DI0_PIN15       0x5
+                                MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
+                                MX53_PAD_DI0_PIN3__IPU_DI0_PIN3         0x5
+                                MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0    0x5
+                                MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1    0x5
+                                MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2    0x5
+                                MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3    0x5
+                                MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4    0x5
+                                MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5    0x5
+                                MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6    0x5
+                                MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7    0x5
+                                MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8    0x5
+                                MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9    0x5
+                                MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10  0x5
+                                MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11  0x5
+                                MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12  0x5
+                                MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13  0x5
+                                MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14  0x5
+                                MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15  0x5
+                                MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16  0x5
+                                MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17  0x5
+                                MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18  0x5
+                                MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19  0x5
+                                MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20  0x5
+                                MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21  0x5
+                                MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22  0x5
+                                MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23  0x5
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX53_PAD_CSI0_DAT10__UART1_TXD_MUX      0x1e4
+                                MX53_PAD_CSI0_DAT11__UART1_RXD_MUX      0x1e4
+                        >;
+                };
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p2v>;
+                VDDIO-supply = <&reg_3p2v>;
+                clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
+        };
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        accelerometer: mma8450@1c {
+                compatible = "fsl,mma8450";
+                reg = <0x1c>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        phy-mode = "rmii";
+        phy-reset-gpios = <&gpio7 6 0>;
+        status = "okay";
+};
+&sata {
+        status = "okay";
+};
+&vpu {
+        status = "okay";
+};
+&usbh1 {
+        vbus-supply = <&reg_usb_vbus>;
+        phy_type = "utmi";
+        status = "okay";
+};
+&usbotg {
+        dr_mode = "peripheral";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 91a5935a4aac..dec4b073ceb1 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -11,193 +11,14 @@
 */
 /dts-v1/;
-#include "imx53.dtsi"
+#include "imx53-qsb-common.dtsi"
 / {
        model = "Freescale i.MX53 Quick Start Board";
        compatible = "fsl,imx53-qsb", "fsl,imx53";
-        memory {
-                reg = <0x70000000 0x40000000>;
-        };
-        display@di0 {
-                compatible = "fsl,imx-parallel-display";
-                crtcs = <&ipu 0>;
-                interface-pix-fmt = "rgb565";
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_ipu_disp0_1>;
-                status = "disabled";
-                display-timings {
-                        claawvga {
-                                native-mode;
-                                clock-frequency = <27000000>;
-                                hactive = <800>;
-                                vactive = <480>;
-                                hback-porch = <40>;
-                                hfront-porch = <60>;
-                                vback-porch = <10>;
-                                vfront-porch = <10>;
-                                hsync-len = <20>;
-                                vsync-len = <10>;
-                                hsync-active = <0>;
-                                vsync-active = <0>;
-                                de-active = <1>;
-                                pixelclk-active = <0>;
-                        };
-                };
-        };
-        gpio-keys {
-                compatible = "gpio-keys";
-                power {
-                        label = "Power Button";
-                        gpios = <&gpio1 8 0>;
-                        linux,code = <116>; /* KEY_POWER */
-                };
-                volume-up {
-                        label = "Volume Up";
-                        gpios = <&gpio2 14 0>;
-                        linux,code = <115>; /* KEY_VOLUMEUP */
-                        gpio-key,wakeup;
-                };
-                volume-down {
-                        label = "Volume Down";
-                        gpios = <&gpio2 15 0>;
-                        linux,code = <114>; /* KEY_VOLUMEDOWN */
-                        gpio-key,wakeup;
-                };
-        };
-        leds {
-                compatible = "gpio-leds";
-                pinctrl-names = "default";
-                pinctrl-0 = <&led_pin_gpio7_7>;
-                user {
-                        label = "Heartbeat";
-                        gpios = <&gpio7 7 0>;
-                        linux,default-trigger = "heartbeat";
-                };
-        };
-        regulators {
-                compatible = "simple-bus";
-                reg_3p2v: 3p2v {
-                        compatible = "regulator-fixed";
-                        regulator-name = "3P2V";
-                        regulator-min-microvolt = <3200000>;
-                        regulator-max-microvolt = <3200000>;
-                        regulator-always-on;
-                };
-                reg_usb_vbus: usb_vbus {
-                        compatible = "regulator-fixed";
-                        regulator-name = "usb_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio7 8 0>;
-                        enable-active-high;
-                };
-        };
-        sound {
-                compatible = "fsl,imx53-qsb-sgtl5000",
-                             "fsl,imx-audio-sgtl5000";
-                model = "imx53-qsb-sgtl5000";
-                ssi-controller = <&ssi2>;
-                audio-codec = <&sgtl5000>;
-                audio-routing =
-                        "MIC_IN", "Mic Jack",
-                        "Mic Jack", "Mic Bias",
-                        "Headphone Jack", "HP_OUT";
-                mux-int-port = <2>;
-                mux-ext-port = <5>;
-        };
-};
-&esdhc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1_1>;
-        status = "okay";
-};
-&ssi2 {
-        fsl,mode = "i2s-slave";
-        status = "okay";
-};
-&esdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc3_1>;
-        cd-gpios = <&gpio3 11 0>;
-        wp-gpios = <&gpio3 12 0>;
-        bus-width = <8>;
-        status = "okay";
-};
-&iomuxc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
-        hog {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
-                                MX53_PAD_GPIO_8__GPIO1_8          0x80000000
-                                MX53_PAD_PATA_DATA14__GPIO2_14    0x80000000
-                                MX53_PAD_PATA_DATA15__GPIO2_15    0x80000000
-                                MX53_PAD_EIM_DA11__GPIO3_11       0x80000000
-                                MX53_PAD_EIM_DA12__GPIO3_12       0x80000000
-                                MX53_PAD_PATA_DA_0__GPIO7_6       0x80000000
-                                MX53_PAD_PATA_DA_2__GPIO7_8       0x80000000
-                                MX53_PAD_GPIO_16__GPIO7_11        0x80000000
-                        >;
-                };
-                led_pin_gpio7_7: led_gpio7_7@0 {
-                        fsl,pins = <
-                                MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
-                        >;
-                };
-        };
-};
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
-        status = "okay";
-};
-&i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2_1>;
-        status = "okay";
-        sgtl5000: codec@0a {
-                compatible = "fsl,sgtl5000";
-                reg = <0x0a>;
-                VDDA-supply = <&reg_3p2v>;
-                VDDIO-supply = <&reg_3p2v>;
-                clocks = <&clks 150>;
-        };
 };
 &i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1_1>;
-        status = "okay";
-        accelerometer: mma8450@1c {
-                compatible = "fsl,mma8450";
-                reg = <0x1c>;
-        };
        pmic: dialog@48 {
                compatible = "dlg,da9053-aa", "dlg,da9052";
                reg = <0x48>;
@@ -292,32 +113,3 @@
                };
        };
 };
-&audmux {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux_1>;
-        status = "okay";
-};
-&fec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec_1>;
-        phy-mode = "rmii";
-        phy-reset-gpios = <&gpio7 6 0>;
-        status = "okay";
-};
-&vpu {
-        status = "okay";
-};
-&usbh1 {
-        vbus-supply = <&reg_usb_vbus>;
-        phy_type = "utmi";
-        status = "okay";
-};
-&usbotg {
-        dr_mode = "peripheral";
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts
new file mode 100644
index 000000000000..f1bbf9a32991
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx53-qsb-common.dtsi"
+/ {
+        model = "Freescale i.MX53 Quick Start-R Board";
+        compatible = "fsl,imx53-qsrb", "fsl,imx53";
+};
+&iomuxc {
+        i2c1 {
+                /* open drain */
+                pinctrl_i2c1_qsrb: i2c1grp-1 {
+                        fsl,pins = <
+                                MX53_PAD_CSI0_DAT8__I2C1_SDA      0x400001ec
+                                MX53_PAD_CSI0_DAT9__I2C1_SCL      0x400001ec
+                        >;
+                };
+        };
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_qsrb>;
+        status = "okay";
+        pmic: mc34708@8 {
+                compatible = "fsl,mc34708";
+                reg = <0x08>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <23 0x8>;
+                regulators {
+                        sw1_reg: sw1a {
+                                regulator-name = "SW1";
+                                regulator-min-microvolt = <650000>;
+                                regulator-max-microvolt = <1437500>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw1b_reg: sw1b {
+                                regulator-name = "SW1B";
+                                regulator-min-microvolt = <650000>;
+                                regulator-max-microvolt = <1437500>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-name = "SW2";
+                                regulator-min-microvolt = <650000>;
+                                regulator-max-microvolt = <1437500>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3_reg: sw3 {
+                                regulator-name = "SW3";
+                                regulator-min-microvolt = <650000>;
+                                regulator-max-microvolt = <1425000>;
+                                regulator-boot-on;
+                        };
+                        sw4a_reg: sw4a {
+                                regulator-name = "SW4A";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4b_reg: sw4b {
+                                regulator-name = "SW4B";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw5_reg: sw5 {
+                                regulator-name = "SW5";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        swbst_reg: swbst {
+                                regulator-name = "SWBST";
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vpll_reg: vpll {
+                                regulator-name = "VPLL";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-boot-on;
+                        };
+                        vrefddr_reg: vrefddr {
+                                regulator-name = "VREFDDR";
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vusb_reg: vusb {
+                                regulator-name = "VUSB";
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vusb2_reg: vusb2 {
+                                regulator-name = "VUSB2";
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vdac_reg: vdac {
+                                regulator-name = "VDAC";
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2775000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-name = "VGEN1";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1550000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-name = "VGEN2";
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index a9b6e10de0a5..5ec1590ff7bc 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -40,7 +40,7 @@
 &esdhc1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        pinctrl-0 = <&pinctrl_esdhc1>;
        cd-gpios = <&gpio3 13 0>;
        wp-gpios = <&gpio4 11 0>;
        status = "okay";
@@ -48,21 +48,21 @@
 &esdhc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        pinctrl-0 = <&pinctrl_esdhc2>;
        non-removable;
        status = "okay";
 };
 &uart3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart3_1>;
+        pinctrl-0 = <&pinctrl_uart3>;
        fsl,uart-has-rtscts;
        status = "okay";
 };
 &ecspi1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        pinctrl-0 = <&pinctrl_ecspi1>;
        fsl,spi-num-chipselects = <2>;
        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
        status = "okay";
@@ -95,7 +95,7 @@
 &esdhc3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc3_1>;
+        pinctrl-0 = <&pinctrl_esdhc3>;
        non-removable;
        status = "okay";
 };
@@ -104,7 +104,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx53-smd {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
@@ -116,24 +116,121 @@
                                MX53_PAD_PATA_DA_0__GPIO7_6    0x80000000
                        >;
                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D16__ECSPI1_SCLK           0x80000000
+                                MX53_PAD_EIM_D17__ECSPI1_MISO           0x80000000
+                                MX53_PAD_EIM_D18__ECSPI1_MOSI           0x80000000
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
+                                MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
+                                MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
+                                MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
+                                MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
+                                MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
+                        >;
+                };
+                pinctrl_esdhc2: esdhc2grp {
+                        fsl,pins = <
+                                MX53_PAD_SD2_CMD__ESDHC2_CMD            0x1d5
+                                MX53_PAD_SD2_CLK__ESDHC2_CLK            0x1d5
+                                MX53_PAD_SD2_DATA0__ESDHC2_DAT0         0x1d5
+                                MX53_PAD_SD2_DATA1__ESDHC2_DAT1         0x1d5
+                                MX53_PAD_SD2_DATA2__ESDHC2_DAT2         0x1d5
+                                MX53_PAD_SD2_DATA3__ESDHC2_DAT3         0x1d5
+                        >;
+                };
+                pinctrl_esdhc3: esdhc3grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DATA8__ESDHC3_DAT0        0x1d5
+                                MX53_PAD_PATA_DATA9__ESDHC3_DAT1        0x1d5
+                                MX53_PAD_PATA_DATA10__ESDHC3_DAT2       0x1d5
+                                MX53_PAD_PATA_DATA11__ESDHC3_DAT3       0x1d5
+                                MX53_PAD_PATA_DATA0__ESDHC3_DAT4        0x1d5
+                                MX53_PAD_PATA_DATA1__ESDHC3_DAT5        0x1d5
+                                MX53_PAD_PATA_DATA2__ESDHC3_DAT6        0x1d5
+                                MX53_PAD_PATA_DATA3__ESDHC3_DAT7        0x1d5
+                                MX53_PAD_PATA_RESET_B__ESDHC3_CMD       0x1d5
+                                MX53_PAD_PATA_IORDY__ESDHC3_CLK         0x1d5
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
+                                MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
+                                MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
+                                MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
+                                MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
+                                MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
+                                MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
+                                MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                                MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
+                                MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX53_PAD_CSI0_DAT8__I2C1_SDA            0xc0000000
+                                MX53_PAD_CSI0_DAT9__I2C1_SCL            0xc0000000
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_ROW3__I2C2_SDA             0xc0000000
+                                MX53_PAD_KEY_COL3__I2C2_SCL             0xc0000000
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX53_PAD_CSI0_DAT10__UART1_TXD_MUX      0x1e4
+                                MX53_PAD_CSI0_DAT11__UART1_RXD_MUX      0x1e4
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1e4
+                                MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1e4
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_CS_0__UART3_TXD_MUX       0x1e4
+                                MX53_PAD_PATA_CS_1__UART3_RXD_MUX       0x1e4
+                                MX53_PAD_PATA_DA_1__UART3_CTS           0x1e4
+                                MX53_PAD_PATA_DA_2__UART3_RTS           0x1e4
+                        >;
+                };
        };
 };
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 &uart2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2_1>;
+        pinctrl-0 = <&pinctrl_uart2>;
        status = "okay";
 };
 &i2c2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2_1>;
+        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
        codec: sgtl5000@0a {
@@ -154,7 +251,7 @@
 &i2c1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1_1>;
+        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";
        accelerometer: mma8450@1c {
@@ -175,7 +272,7 @@
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec_1>;
+        pinctrl-0 = <&pinctrl_fec>;
        phy-mode = "rmii";
        phy-reset-gpios = <&gpio7 6 0>;
        status = "okay";
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index abd72af545bf..4f1f0e2868bf 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -22,9 +22,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3p3v: 3p3v {
+                reg_3p3v: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
@@ -35,8 +38,8 @@
 &esdhc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc2_1>,
+        pinctrl-0 = <&pinctrl_esdhc2>,
-                    <&pinctrl_tqma53_esdhc2_2>;
+                    <&pinctrl_esdhc2_cdwp>;
        vmmc-supply = <&reg_3p3v>;
        wp-gpios = <&gpio1 2 0>;
        cd-gpios = <&gpio1 4 0>;
@@ -45,13 +48,13 @@
 &uart3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart3_2>;
+        pinctrl-0 = <&pinctrl_uart3>;
        status = "disabled";
 };
 &ecspi1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        pinctrl-0 = <&pinctrl_ecspi1>;
        fsl,spi-num-chipselects = <4>;
        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
                   <&gpio3 24 0>, <&gpio3 25 0>;
@@ -60,7 +63,7 @@
 &esdhc3 { /* EMMC */
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc3_1>;
+        pinctrl-0 = <&pinctrl_esdhc3>;
        vmmc-supply = <&reg_3p3v>;
        non-removable;
        bus-width = <8>;
@@ -71,27 +74,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        esdhc2_2 {
+        imx53-tqma53 {
-                pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
-                        fsl,pins = <
-                                MX53_PAD_GPIO_4__GPIO1_4        0x80000000 /* SD2_CD */
-                                MX53_PAD_GPIO_2__GPIO1_2        0x80000000 /* SD2_WP */
-                        >;
-                };
-        };
-        i2s {
-                pinctrl_i2s_1: i2s-grp1 {
-                        fsl,pins = <
-                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000 /* I2S_SCLK */
-                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000 /* I2S_DOUT */
-                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
-                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000 /* I2S_DIN */
-                        >;
-                };
-        };
-        hog {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
@@ -107,43 +90,165 @@
                                 MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000 /* LCD_CONTRAST */
                        >;
                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC      0x80000000
+                                MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD      0x80000000
+                                MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS     0x80000000
+                                MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD      0x80000000
+                        >;
+                };
+                pinctrl_can1: can1grp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_COL2__CAN1_TXCAN           0x80000000
+                                MX53_PAD_KEY_ROW2__CAN1_RXCAN           0x80000000
+                        >;
+                };
+                pinctrl_can2: can2grp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_COL4__CAN2_TXCAN           0x80000000
+                                MX53_PAD_KEY_ROW4__CAN2_RXCAN           0x80000000
+                        >;
+                };
+                pinctrl_cspi: cspigrp {
+                        fsl,pins = <
+                                MX53_PAD_SD1_DATA0__CSPI_MISO           0x1d5
+                                MX53_PAD_SD1_CMD__CSPI_MOSI             0x1d5
+                                MX53_PAD_SD1_CLK__CSPI_SCLK             0x1d5
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D16__ECSPI1_SCLK           0x80000000
+                                MX53_PAD_EIM_D17__ECSPI1_MISO           0x80000000
+                                MX53_PAD_EIM_D18__ECSPI1_MOSI           0x80000000
+                        >;
+                };
+                pinctrl_esdhc2: esdhc2grp {
+                        fsl,pins = <
+                                MX53_PAD_SD2_CMD__ESDHC2_CMD            0x1d5
+                                MX53_PAD_SD2_CLK__ESDHC2_CLK            0x1d5
+                                MX53_PAD_SD2_DATA0__ESDHC2_DAT0         0x1d5
+                                MX53_PAD_SD2_DATA1__ESDHC2_DAT1         0x1d5
+                                MX53_PAD_SD2_DATA2__ESDHC2_DAT2         0x1d5
+                                MX53_PAD_SD2_DATA3__ESDHC2_DAT3         0x1d5
+                        >;
+                };
+                pinctrl_esdhc2_cdwp: esdhc2cdwp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_4__GPIO1_4        0x80000000 /* SD2_CD */
+                                MX53_PAD_GPIO_2__GPIO1_2        0x80000000 /* SD2_WP */
+                        >;
+                };
+                pinctrl_esdhc3: esdhc3grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DATA8__ESDHC3_DAT0        0x1d5
+                                MX53_PAD_PATA_DATA9__ESDHC3_DAT1        0x1d5
+                                MX53_PAD_PATA_DATA10__ESDHC3_DAT2       0x1d5
+                                MX53_PAD_PATA_DATA11__ESDHC3_DAT3       0x1d5
+                                MX53_PAD_PATA_DATA0__ESDHC3_DAT4        0x1d5
+                                MX53_PAD_PATA_DATA1__ESDHC3_DAT5        0x1d5
+                                MX53_PAD_PATA_DATA2__ESDHC3_DAT6        0x1d5
+                                MX53_PAD_PATA_DATA3__ESDHC3_DAT7        0x1d5
+                                MX53_PAD_PATA_RESET_B__ESDHC3_CMD       0x1d5
+                                MX53_PAD_PATA_IORDY__ESDHC3_CLK         0x1d5
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
+                                MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
+                                MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
+                                MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
+                                MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
+                                MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
+                                MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
+                                MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                                MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
+                                MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_ROW3__I2C2_SDA             0xc0000000
+                                MX53_PAD_KEY_COL3__I2C2_SCL             0xc0000000
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_6__I2C3_SDA               0xc0000000
+                                MX53_PAD_GPIO_5__I2C3_SCL               0xc0000000
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DIOW__UART1_TXD_MUX       0x1e4
+                                MX53_PAD_PATA_DMACK__UART1_RXD_MUX      0x1e4
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1e4
+                                MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1e4
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_CS_0__UART3_TXD_MUX       0x1e4
+                                MX53_PAD_PATA_CS_1__UART3_RXD_MUX       0x1e4
+                        >;
+                };
        };
 };
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_2>;
+        pinctrl-0 = <&pinctrl_uart1>;
        fsl,uart-has-rtscts;
        status = "disabled";
 };
 &uart2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2_1>;
+        pinctrl-0 = <&pinctrl_uart2>;
        status = "disabled";
 };
 &can1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_can1_2>;
+        pinctrl-0 = <&pinctrl_can1>;
        status = "disabled";
 };
 &can2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_can2_1>;
+        pinctrl-0 = <&pinctrl_can2>;
        status = "disabled";
 };
 &i2c3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c3_1>;
+        pinctrl-0 = <&pinctrl_i2c3>;
        status = "disabled";
 };
 &cspi {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_cspi_1>;
+        pinctrl-0 = <&pinctrl_cspi>;
        fsl,spi-num-chipselects = <3>;
        cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
                   <&gpio1 21 0>;
@@ -152,7 +257,7 @@
 &i2c2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2_1>;
+        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
        pmic: mc34708@8 {
@@ -177,7 +282,7 @@
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec_1>;
+        pinctrl-0 = <&pinctrl_fec>;
        phy-mode = "rmii";
        status = "disabled";
 };
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
new file mode 100644
index 000000000000..0217dde3b36b
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -0,0 +1,315 @@
+/*
+ * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx53-tx53.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+/ {
+        model = "Ka-Ro electronics TX53 module (LCD)";
+        compatible = "karo,tx53", "fsl,imx53";
+        aliases {
+                display = &display;
+        };
+        soc {
+                display: display@di0 {
+                        compatible = "fsl,imx-parallel-display";
+                        crtcs = <&ipu 0>;
+                        interface-pix-fmt = "rgb24";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_rgb24_vga1>;
+                        status = "okay";
+                        display-timings {
+                                VGA {
+                                        clock-frequency = <25200000>;
+                                        hactive = <640>;
+                                        vactive = <480>;
+                                        hback-porch = <48>;
+                                        hsync-len = <96>;
+                                        hfront-porch = <16>;
+                                        vback-porch = <31>;
+                                        vsync-len = <2>;
+                                        vfront-porch = <12>;
+                                        hsync-active = <0>;
+                                        vsync-active = <0>;
+                                        de-active = <1>;
+                                        pixelclk-active = <0>;
+                                };
+                                ETV570 {
+                                        clock-frequency = <25200000>;
+                                        hactive = <640>;
+                                        vactive = <480>;
+                                        hback-porch = <114>;
+                                        hsync-len = <30>;
+                                        hfront-porch = <16>;
+                                        vback-porch = <32>;
+                                        vsync-len = <3>;
+                                        vfront-porch = <10>;
+                                        hsync-active = <0>;
+                                        vsync-active = <0>;
+                                        de-active = <1>;
+                                        pixelclk-active = <0>;
+                                };
+                                ET0350 {
+                                        clock-frequency = <6413760>;
+                                        hactive = <320>;
+                                        vactive = <240>;
+                                        hback-porch = <34>;
+                                        hsync-len = <34>;
+                                        hfront-porch = <20>;
+                                        vback-porch = <15>;
+                                        vsync-len = <3>;
+                                        vfront-porch = <4>;
+                                        hsync-active = <0>;
+                                        vsync-active = <0>;
+                                        de-active = <1>;
+                                        pixelclk-active = <0>;
+                                };
+                                ET0430 {
+                                        clock-frequency = <9009000>;
+                                        hactive = <480>;
+                                        vactive = <272>;
+                                        hback-porch = <2>;
+                                        hsync-len = <41>;
+                                        hfront-porch = <2>;
+                                        vback-porch = <2>;
+                                        vsync-len = <10>;
+                                        vfront-porch = <2>;
+                                        hsync-active = <0>;
+                                        vsync-active = <0>;
+                                        de-active = <1>;
+                                        pixelclk-active = <1>;
+                                };
+                                ET0500 {
+                                        clock-frequency = <33264000>;
+                                        hactive = <800>;
+                                        vactive = <480>;
+                                        hback-porch = <88>;
+                                        hsync-len = <128>;
+                                        hfront-porch = <40>;
+                                        vback-porch = <33>;
+                                        vsync-len = <2>;
+                                        vfront-porch = <10>;
+                                        hsync-active = <0>;
+                                        vsync-active = <0>;
+                                        de-active = <1>;
+                                        pixelclk-active = <0>;
+                                };
+                                ET0700 { /* same as ET0500 */
+                                        clock-frequency = <33264000>;
+                                        hactive = <800>;
+                                        vactive = <480>;
+                                        hback-porch = <88>;
+                                        hsync-len = <128>;
+                                        hfront-porch = <40>;
+                                        vback-porch = <33>;
+                                        vsync-len = <2>;
+                                        vfront-porch = <10>;
+                                        hsync-active = <0>;
+                                        vsync-active = <0>;
+                                        de-active = <1>;
+                                        pixelclk-active = <0>;
+                                };
+                                ETQ570 {
+                                        clock-frequency = <6596040>;
+                                        hactive = <320>;
+                                        vactive = <240>;
+                                        hback-porch = <38>;
+                                        hsync-len = <30>;
+                                        hfront-porch = <30>;
+                                        vback-porch = <16>;
+                                        vsync-len = <3>;
+                                        vfront-porch = <4>;
+                                        hsync-active = <0>;
+                                        vsync-active = <0>;
+                                        de-active = <1>;
+                                        pixelclk-active = <0>;
+                                };
+                        };
+                };
+        };
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
+                power-supply = <&reg_3v3>;
+                brightness-levels = <
+                          0  1  2  3  4  5  6  7  8  9
+                         10 11 12 13 14 15 16 17 18 19
+                         20 21 22 23 24 25 26 27 28 29
+                         30 31 32 33 34 35 36 37 38 39
+                         40 41 42 43 44 45 46 47 48 49
+                         50 51 52 53 54 55 56 57 58 59
+                         60 61 62 63 64 65 66 67 68 69
+                         70 71 72 73 74 75 76 77 78 79
+                         80 81 82 83 84 85 86 87 88 89
+                         90 91 92 93 94 95 96 97 98 99
+                        100
+                >;
+                default-brightness-level = <50>;
+        };
+        regulators {
+                reg_lcd_pwr: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "LCD POWER";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        regulator-boot-on;
+                };
+                reg_lcd_reset: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "LCD RESET";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        regulator-boot-on;
+                };
+        };
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                VDDA-supply = <&reg_2v5>;
+                VDDIO-supply = <&reg_3v3>;
+                clocks = <&mclk>;
+        };
+        polytouch: edt-ft5x06@38 {
+                compatible = "edt,edt-ft5x06";
+                reg = <0x38>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <15 0>;
+                reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
+                wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+        };
+        touchscreen: tsc2007@48 {
+                compatible = "ti,tsc2007";
+                reg = <0x48>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_tsc2007>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <26 0>;
+                gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+                ti,x-plate-ohms = <660>;
+                linux,wakeup;
+        };
+};
+&iomuxc {
+        imx53-tx53-x03x {
+                pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
+                        fsl,pins = <
+                                MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */
+                                MX53_PAD_EIM_A16__GPIO2_22   0x04 /* Reset */
+                                MX53_PAD_EIM_A17__GPIO2_21   0x04 /* Wake */
+                        >;
+                };
+                pinctrl_kpp: kppgrp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_9__KPP_COL_6 0x1f4
+                                MX53_PAD_GPIO_4__KPP_COL_7 0x1f4
+                                MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4
+                                MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4
+                                MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4
+                                MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4
+                                MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4
+                                MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4
+                        >;
+                };
+                pinctrl_rgb24_vga1: rgb24-vgagrp1 {
+                        fsl,pins = <
+                                MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         0x5
+                                MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               0x5
+                                MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                 0x5
+                                MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 0x5
+                                MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            0x5
+                                MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            0x5
+                                MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            0x5
+                                MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            0x5
+                                MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            0x5
+                                MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            0x5
+                                MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            0x5
+                                MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            0x5
+                                MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            0x5
+                                MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            0x5
+                                MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          0x5
+                                MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          0x5
+                                MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          0x5
+                                MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          0x5
+                                MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          0x5
+                                MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          0x5
+                                MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          0x5
+                                MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          0x5
+                                MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          0x5
+                                MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          0x5
+                                MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          0x5
+                                MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          0x5
+                                MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          0x5
+                                MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          0x5
+                        >;
+                };
+                pinctrl_tsc2007: tsc2007grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */
+                        >;
+                };
+        };
+};
+&kpp {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_kpp>;
+        /* sample keymap */
+        /* row/col 0,1 are mapped to KPP row/col 6,7 */
+        linux,keymap = <
+                MATRIX_KEY(6, 6, KEY_POWER)
+                MATRIX_KEY(6, 7, KEY_KP0)
+                MATRIX_KEY(6, 2, KEY_KP1)
+                MATRIX_KEY(6, 3, KEY_KP2)
+                MATRIX_KEY(7, 6, KEY_KP3)
+                MATRIX_KEY(7, 7, KEY_KP4)
+                MATRIX_KEY(7, 2, KEY_KP5)
+                MATRIX_KEY(7, 3, KEY_KP6)
+                MATRIX_KEY(2, 6, KEY_KP7)
+                MATRIX_KEY(2, 7, KEY_KP8)
+                MATRIX_KEY(2, 2, KEY_KP9)
+        >;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts
new file mode 100644
index 000000000000..64804719f0f4
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx53-tx53.dtsi"
+#include <dt-bindings/input/input.h>
+/ {
+        model = "Ka-Ro electronics TX53 module (LVDS)";
+        compatible = "karo,tx53", "fsl,imx53";
+        aliases {
+                display = &lvds0;
+                lvds0 = &lvds0;
+                lvds1 = &lvds1;
+        };
+        backlight0: backlight0 {
+                compatible = "pwm-backlight";
+                pwms = <&pwm2 0 500000 0>;
+                power-supply = <&reg_3v3>;
+                brightness-levels = <
+                          0  1  2  3  4  5  6  7  8  9
+                         10 11 12 13 14 15 16 17 18 19
+                         20 21 22 23 24 25 26 27 28 29
+                         30 31 32 33 34 35 36 37 38 39
+                         40 41 42 43 44 45 46 47 48 49
+                         50 51 52 53 54 55 56 57 58 59
+                         60 61 62 63 64 65 66 67 68 69
+                         70 71 72 73 74 75 76 77 78 79
+                         80 81 82 83 84 85 86 87 88 89
+                         90 91 92 93 94 95 96 97 98 99
+                        100
+                >;
+                default-brightness-level = <50>;
+        };
+        backlight1: backlight1 {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 500000 0>;
+                power-supply = <&reg_3v3>;
+                brightness-levels = <
+                          0  1  2  3  4  5  6  7  8  9
+                         10 11 12 13 14 15 16 17 18 19
+                         20 21 22 23 24 25 26 27 28 29
+                         30 31 32 33 34 35 36 37 38 39
+                         40 41 42 43 44 45 46 47 48 49
+                         50 51 52 53 54 55 56 57 58 59
+                         60 61 62 63 64 65 66 67 68 69
+                         70 71 72 73 74 75 76 77 78 79
+                         80 81 82 83 84 85 86 87 88 89
+                         90 91 92 93 94 95 96 97 98 99
+                        100
+                >;
+                default-brightness-level = <50>;
+        };
+        regulators {
+                reg_lcd_pwr0: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "LVDS0 POWER";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        regulator-boot-on;
+                };
+                reg_lcd_pwr1: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "LVDS1 POWER";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        regulator-boot-on;
+                };
+        };
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        touchscreen2: eeti@04 {
+                compatible = "eeti,egalax_ts";
+                reg = <0x04>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_eeti2>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <23 0>;
+                wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+                linux,wakeup;
+        };
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                VDDA-supply = <&reg_2v5>;
+                VDDIO-supply = <&reg_3v3>;
+                clocks = <&mclk>;
+        };
+        touchscreen1: eeti@04 {
+                compatible = "eeti,egalax_ts";
+                reg = <0x04>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_eeti1>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <22 0>;
+                wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+                linux,wakeup;
+        };
+};
+&iomuxc {
+        imx53-tx53-x13x {
+                pinctrl_i2c2: i2c2-grp1 {
+                        fsl,pins = <
+                                MX53_PAD_KEY_ROW3__I2C2_SDA             0xc0000000
+                                MX53_PAD_KEY_COL3__I2C2_SCL             0xc0000000
+                        >;
+                };
+                pinctrl_lvds0: lvds0grp {
+                        fsl,pins = <
+                                MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
+                                MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
+                                MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
+                                MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
+                                MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
+                        >;
+                };
+                pinctrl_lvds1: lvds1grp {
+                        fsl,pins = <
+                                MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
+                                MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
+                                MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
+                                MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
+                                MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
+                        >;
+                };
+                pinctrl_pwm1: pwm1grp {
+                        fsl,pins = <MX53_PAD_GPIO_9__PWM1_PWMO 0x04>;
+                };
+                pinctrl_eeti1: eeti1grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */
+                        >;
+                };
+                pinctrl_eeti2: eeti2grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */
+                        >;
+                };
+        };
+};
+&ldb {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>;
+        status = "okay";
+        lvds0: lvds-channel@0 {
+                fsl,data-mapping = "jeida";
+                fsl,data-width = <24>;
+                status = "okay";
+                display-timings {
+                        native-mode = <&lvds_timing0>;
+                        lvds_timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hsync-len = <60>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vsync-len = <10>;
+                                vfront-porch = <7>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+        lvds1: lvds-channel@1 {
+                fsl,data-mapping = "jeida";
+                fsl,data-width = <24>;
+                status = "okay";
+                display-timings {
+                        native-mode = <&lvds_timing1>;
+                        lvds_timing1: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hsync-len = <60>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vsync-len = <10>;
+                                vfront-porch = <7>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+};
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index f494766700a3..e348796ba689 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -1,122 +1,550 @@
 /*
- * Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ * Copyright 2012 <LW@KARO-electronics.de>
+ * based on imx53-qsb.dts
+ *   Copyright 2011 Freescale Semiconductor, Inc.
+ *   Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * Version 2 at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
-/include/ "imx53.dtsi"
+#include "imx53.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 / {
-        model = "Ka-Ro TX53";
+        model = "Ka-Ro electronics TX53 module";
        compatible = "karo,tx53", "fsl,imx53";
-        memory {
+        aliases {
-                reg = <0x70000000 0x40000000>; /* Up to 1GiB */
+                can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
+                can1 = &can1;
+                ipu = &ipu;
+                reg_can_xcvr = &reg_can_xcvr;
+                usbh1 = &usbh1;
+                usbotg = &usbotg;
+        };
+        clocks {
+                ckih1 {
+                        clock-frequency = <0>;
+                };
+                mclk: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <27000000>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_key>;
+                power {
+                        label = "Power Button";
+                        gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+                        linux,code = <116>; /* KEY_POWER */
+                        gpio-key,wakeup;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_stk5led>;
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
        };
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3p3v: 3p3v {
+                reg_2v5: regulator@0 {
                        compatible = "regulator-fixed";
-                        regulator-name = "3P3V";
+                        reg = <0>;
+                        regulator-name = "2V5";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                };
+                reg_3v3: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "3V3";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
                };
+                reg_can_xcvr: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "CAN XCVR";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_can_xcvr>;
+                        gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+                };
+                reg_usbh1_vbus: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "usbh1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usbh1_vbus>;
+                        gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usbotg_vbus: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "usbotg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usbotg_vbus>;
+                        gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+        };
+        sound {
+                compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000";
+                model = "tx53-audio-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                /* '1' based port numbers according to datasheet names */
+                mux-int-port = <1>;
+                mux-ext-port = <5>;
        };
 };
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ssi1>;
+        status = "okay";
+};
 &can1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_can1_2>;
+        pinctrl-0 = <&pinctrl_can1>;
-        status = "disabled";
+        xceiver-supply = <&reg_can_xcvr>;
+        status = "okay";
 };
 &can2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_can2_1>;
+        pinctrl-0 = <&pinctrl_can2>;
-        status = "disabled";
+        xceiver-supply = <&reg_can_xcvr>;
+        status = "okay";
 };
 &ecspi1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_2>;
+        pinctrl-0 = <&pinctrl_ecspi1>;
-        status = "disabled";
+        fsl,spi-num-chipselects = <2>;
+        status = "okay";
+        cs-gpios = <
+                &gpio2 30 GPIO_ACTIVE_HIGH
+                &gpio3 19 GPIO_ACTIVE_HIGH
+        >;
+        spidev0: spi@0 {
+                compatible = "spidev";
+                reg = <0>;
+                spi-max-frequency = <54000000>;
+        };
+        spidev1: spi@1 {
+                compatible = "spidev";
+                reg = <1>;
+                spi-max-frequency = <54000000>;
+        };
 };
 &esdhc1 {
+        cd-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+        fsl,wp-controller;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1_2>;
+        pinctrl-0 = <&pinctrl_esdhc1>;
-        status = "disabled";
+        status = "okay";
 };
 &esdhc2 {
+        cd-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+        fsl,wp-controller;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        pinctrl-0 = <&pinctrl_esdhc2>;
-        status = "disabled";
+        status = "okay";
 };
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec_1>;
+        pinctrl-0 = <&pinctrl_fec>;
        phy-mode = "rmii";
-        status = "disabled";
+        phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
+        phy-handle = <&phy0>;
+        mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
+        status = "okay";
+        phy0: ethernet-phy@0 {
+                interrupt-parent = <&gpio2>;
+                interrupts = <4>;
+                device_type = "ethernet-phy";
+        };
 };
-&i2c3 {
+&i2c1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c3_2>;
+        pinctrl-0 = <&pinctrl_i2c1>;
-        status = "disabled";
+        clock-frequency = <400000>;
+        status = "okay";
+        rtc1: ds1339@68 {
+                compatible = "dallas,ds1339";
+                reg = <0x68>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ds1339>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <20 0>;
+        };
 };
-&owire {
+&iomuxc {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_owire_1>;
+        pinctrl-0 = <&pinctrl_hog>;
-        status = "disabled";
+        imx53-tx53 {
+                pinctrl_hog: hoggrp {
+                        /* pins not in use by any device on the Starterkit board series */
+                        fsl,pins = <
+                                /* CMOS Sensor Interface */
+                                MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4
+                                MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4
+                                MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4
+                                MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4
+                                MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4
+                                MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4
+                                MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4
+                                MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4
+                                MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4
+                                MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4
+                                MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4
+                                MX53_PAD_GPIO_0__GPIO1_0 0x1f4
+                                /* Module Specific Signal */
+                                /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */
+                                /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */
+                                MX53_PAD_EIM_D29__GPIO3_29 0x1f4
+                                MX53_PAD_EIM_EB3__GPIO2_31 0x1f4
+                                /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */
+                                /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */
+                                MX53_PAD_EIM_A19__GPIO2_19 0x1f4
+                                MX53_PAD_EIM_A20__GPIO2_18 0x1f4
+                                MX53_PAD_EIM_A21__GPIO2_17 0x1f4
+                                MX53_PAD_EIM_A22__GPIO2_16 0x1f4
+                                MX53_PAD_EIM_A23__GPIO6_6 0x1f4
+                                MX53_PAD_EIM_A24__GPIO5_4 0x1f4
+                                MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4
+                                MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4
+                                MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4
+                                MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4
+                                /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */
+                                /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */
+                                MX53_PAD_GPIO_13__GPIO4_3 0x1f4
+                                MX53_PAD_EIM_CS0__GPIO2_23 0x1f4
+                                MX53_PAD_EIM_CS1__GPIO2_24 0x1f4
+                                MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4
+                                MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4
+                                MX53_PAD_EIM_EB0__GPIO2_28 0x1f4
+                                MX53_PAD_EIM_EB1__GPIO2_29 0x1f4
+                                MX53_PAD_EIM_OE__GPIO2_25 0x1f4
+                                MX53_PAD_EIM_LBA__GPIO2_27 0x1f4
+                                MX53_PAD_EIM_RW__GPIO2_26 0x1f4
+                                MX53_PAD_EIM_DA8__GPIO3_8 0x1f4
+                                MX53_PAD_EIM_DA9__GPIO3_9 0x1f4
+                                MX53_PAD_EIM_DA10__GPIO3_10 0x1f4
+                                MX53_PAD_EIM_DA11__GPIO3_11 0x1f4
+                                MX53_PAD_EIM_DA12__GPIO3_12 0x1f4
+                                MX53_PAD_EIM_DA13__GPIO3_13 0x1f4
+                                MX53_PAD_EIM_DA14__GPIO3_14 0x1f4
+                                MX53_PAD_EIM_DA15__GPIO3_15 0x1f4
+                                >;
+                };
+                pinctrl_can1: can1grp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_7__CAN1_TXCAN             0x80000000
+                                MX53_PAD_GPIO_8__CAN1_RXCAN             0x80000000
+                        >;
+                };
+                pinctrl_can2: can2grp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_COL4__CAN2_TXCAN           0x80000000
+                                MX53_PAD_KEY_ROW4__CAN2_RXCAN           0x80000000
+                        >;
+                };
+                pinctrl_can_xcvr: can-xcvrgrp {
+                        fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */
+                };
+                pinctrl_ds1339: ds1339grp {
+                        fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_19__ECSPI1_RDY            0x80000000
+                                MX53_PAD_EIM_EB2__ECSPI1_SS0            0x80000000
+                                MX53_PAD_EIM_D16__ECSPI1_SCLK           0x80000000
+                                MX53_PAD_EIM_D17__ECSPI1_MISO           0x80000000
+                                MX53_PAD_EIM_D18__ECSPI1_MOSI           0x80000000
+                                MX53_PAD_EIM_D19__ECSPI1_SS1            0x80000000
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1d5
+                                MX53_PAD_SD1_DATA1__ESDHC1_DAT1         0x1d5
+                                MX53_PAD_SD1_DATA2__ESDHC1_DAT2         0x1d5
+                                MX53_PAD_SD1_DATA3__ESDHC1_DAT3         0x1d5
+                                MX53_PAD_SD1_CMD__ESDHC1_CMD            0x1d5
+                                MX53_PAD_SD1_CLK__ESDHC1_CLK            0x1d5
+                                MX53_PAD_EIM_D24__GPIO3_24 0x1f0
+                        >;
+                };
+                pinctrl_esdhc2: esdhc2grp {
+                        fsl,pins = <
+                                MX53_PAD_SD2_CMD__ESDHC2_CMD            0x1d5
+                                MX53_PAD_SD2_CLK__ESDHC2_CLK            0x1d5
+                                MX53_PAD_SD2_DATA0__ESDHC2_DAT0         0x1d5
+                                MX53_PAD_SD2_DATA1__ESDHC2_DAT1         0x1d5
+                                MX53_PAD_SD2_DATA2__ESDHC2_DAT2         0x1d5
+                                MX53_PAD_SD2_DATA3__ESDHC2_DAT3         0x1d5
+                                MX53_PAD_EIM_D25__GPIO3_25 0x1f0
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
+                                MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
+                                MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
+                                MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
+                                MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
+                                MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
+                                MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
+                                MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                                MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
+                                MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
+                        >;
+                };
+                pinctrl_gpio_key: gpio-keygrp {
+                        fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D21__I2C1_SCL              0xc0000000
+                                MX53_PAD_EIM_D28__I2C1_SDA              0xc0000000
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_3__I2C3_SCL               0xc0000000
+                                MX53_PAD_GPIO_6__I2C3_SDA               0xc0000000
+                        >;
+                };
+                pinctrl_nand: nandgrp {
+                        fsl,pins = <
+                                MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
+                                MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
+                                MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
+                                MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
+                                MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
+                                MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
+                                MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
+                                MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0    0xa4
+                                MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1    0xa4
+                                MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2    0xa4
+                                MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3    0xa4
+                                MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4    0xa4
+                                MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5    0xa4
+                                MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6    0xa4
+                                MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7    0xa4
+                        >;
+                };
+                pinctrl_pwm2: pwm2grp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_1__PWM2_PWMO              0x80000000
+                        >;
+                };
+                pinctrl_ssi1: ssi1grp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC      0x80000000
+                                MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD      0x80000000
+                                MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS     0x80000000
+                                MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD      0x80000000
+                        >;
+                };
+                pinctrl_ssi2: ssi2grp {
+                        fsl,pins = <
+                                MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC     0x80000000
+                                MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD     0x80000000
+                                MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS    0x80000000
+                                MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD     0x80000000
+                                MX53_PAD_EIM_D27__GPIO3_27 0x1f0
+                        >;
+                };
+                pinctrl_stk5led: stk5ledgrp {
+                        fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DIOW__UART1_TXD_MUX       0x1e4
+                                MX53_PAD_PATA_DMACK__UART1_RXD_MUX      0x1e4
+                                MX53_PAD_PATA_RESET_B__UART1_CTS        0x1c5
+                                MX53_PAD_PATA_IORDY__UART1_RTS          0x1c5
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1c5
+                                MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1c5
+                                MX53_PAD_PATA_DIOR__UART2_RTS           0x1c5
+                                MX53_PAD_PATA_INTRQ__UART2_CTS          0x1c5
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_CS_0__UART3_TXD_MUX       0x1e4
+                                MX53_PAD_PATA_CS_1__UART3_RXD_MUX       0x1e4
+                                MX53_PAD_PATA_DA_1__UART3_CTS           0x1e4
+                                MX53_PAD_PATA_DA_2__UART3_RTS           0x1e4
+                        >;
+                };
+                pinctrl_usbh1: usbh1grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */
+                        >;
+                };
+                pinctrl_usbh1_vbus: usbh1-vbusgrp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */
+                        >;
+                };
+                pinctrl_usbotg_vbus: usbotg-vbusgrp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */
+                                MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */
+                        >;
+                };
+        };
+};
+&ipu {
+        status = "okay";
+};
+&nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nand>;
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
 };
 &pwm2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm2_1>;
+        pinctrl-0 = <&pinctrl_pwm2>;
-        status = "disabled";
+        #pwm-cells = <3>;
+};
+&sdma {
+        fsl,sdma-ram-script-name = "sdma-imx53.bin";
 };
 &ssi1 {
-        pinctrl-names = "default";
+        fsl,mode = "i2s-slave";
-        pinctrl-0 = <&pinctrl_audmux_1>;
+        codec-handle = <&sgtl5000>;
-        status = "disabled";
+        status = "okay";
 };
 &ssi2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux_2>;
        status = "disabled";
 };
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_2>,
+        pinctrl-0 = <&pinctrl_uart1>;
-                    <&pinctrl_uart1_3>;
        fsl,uart-has-rtscts;
-        status = "disabled";
+        status = "okay";
 };
 &uart2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2_2>;
+        pinctrl-0 = <&pinctrl_uart2>;
        fsl,uart-has-rtscts;
-        status = "disabled";
+        status = "okay";
 };
 &uart3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart3_1>;
+        pinctrl-0 = <&pinctrl_uart3>;
        fsl,uart-has-rtscts;
-        status = "disabled";
+        status = "okay";
+};
+&usbh1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh1>;
+        phy_type = "utmi";
+        disable-over-current;
+        vbus-supply = <&reg_usbh1_vbus>;
+        status = "okay";
+};
+&usbotg {
+        phy_type = "utmi";
+        dr_mode = "peripheral";
+        disable-over-current;
+        vbus-supply = <&reg_usbotg_vbus>;
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts
new file mode 100644
index 000000000000..7f6711a48615
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx53-voipac-dmm-668.dtsi"
+/ {
+        sound {
+                compatible = "fsl,imx53-voipac-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx53-voipac-sgtl5000";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <2>;
+                mux-ext-port = <5>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pin_gpio>;
+                led1 {
+                        label = "led-red";
+                        gpios = <&gpio3 29 0>;
+                        default-state = "off";
+                };
+                led2 {
+                        label = "led-orange";
+                        gpios = <&gpio2 31 0>;
+                        default-state = "off";
+                };
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx53-voipac {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                /* SD2_CD */
+                                MX53_PAD_EIM_D25__GPIO3_25      0x80000000
+                                /* SD2_WP */
+                                MX53_PAD_EIM_A19__GPIO2_19      0x80000000
+                        >;
+                };
+                led_pin_gpio: led_gpio {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D29__GPIO3_29      0x80000000
+                                MX53_PAD_EIM_EB3__GPIO2_31      0x80000000
+                        >;
+                };
+                /* Keyboard controller */
+                pinctrl_kpp_1: kppgrp-1 {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_9__KPP_COL_6      0xe8
+                                MX53_PAD_GPIO_4__KPP_COL_7      0xe8
+                                MX53_PAD_KEY_COL2__KPP_COL_2    0xe8
+                                MX53_PAD_KEY_COL3__KPP_COL_3    0xe8
+                                MX53_PAD_KEY_COL4__KPP_COL_4    0xe8
+                                MX53_PAD_GPIO_2__KPP_ROW_6      0xe0
+                                MX53_PAD_GPIO_5__KPP_ROW_7      0xe0
+                                MX53_PAD_KEY_ROW2__KPP_ROW_2    0xe0
+                                MX53_PAD_KEY_ROW3__KPP_ROW_3    0xe0
+                                MX53_PAD_KEY_ROW4__KPP_ROW_4    0xe0
+                        >;
+                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC      0x80000000
+                                MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD      0x80000000
+                                MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS     0x80000000
+                                MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD      0x80000000
+                        >;
+                };
+                pinctrl_esdhc2: esdhc2grp {
+                        fsl,pins = <
+                                MX53_PAD_SD2_CMD__ESDHC2_CMD            0x1d5
+                                MX53_PAD_SD2_CLK__ESDHC2_CLK            0x1d5
+                                MX53_PAD_SD2_DATA0__ESDHC2_DAT0         0x1d5
+                                MX53_PAD_SD2_DATA1__ESDHC2_DAT1         0x1d5
+                                MX53_PAD_SD2_DATA2__ESDHC2_DAT2         0x1d5
+                                MX53_PAD_SD2_DATA3__ESDHC2_DAT3         0x1d5
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_3__I2C3_SCL               0xc0000000
+                                MX53_PAD_GPIO_6__I2C3_SDA               0xc0000000
+                        >;
+                };
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */
+        status = "okay";
+};
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2>;
+        cd-gpios = <&gpio3 25 0>;
+        wp-gpios = <&gpio2 19 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p3v>;
+                VDDIO-supply = <&reg_3p3v>;
+                clocks = <&clks 150>;
+        };
+};
+&kpp {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_kpp_1>;
+        linux,keymap = <
+                        0x0203003b      /* KEY_F1 */
+                        0x0603003c      /* KEY_F2 */
+                        0x0207003d      /* KEY_F3 */
+                        0x0607003e      /* KEY_F4 */
+                        >;
+        keypad,num-rows = <8>;
+        keypad,num-columns = <1>;
+        status = "okay";
+};
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
new file mode 100644
index 000000000000..ba689fbd0e41
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
@@ -0,0 +1,277 @@
+/*
+ * Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include "imx53.dtsi"
+/ {
+        model = "Voipac i.MX53 X53-DMM-668";
+        compatible = "voipac,imx53-dmm-668", "fsl,imx53";
+        memory@70000000 {
+                device_type = "memory";
+                reg = <0x70000000 0x20000000>;
+        };
+        memory@b0000000 {
+                device_type = "memory";
+                reg = <0xb0000000 0x20000000>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_3p3v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_usb_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 31 0>; /* PEN */
+                        enable-active-high;
+                };
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx53-voipac {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                /* Make DA9053 regulator functional */
+                                MX53_PAD_GPIO_16__GPIO7_11      0x80000000
+                                /* FEC Power enable */
+                                MX53_PAD_GPIO_11__GPIO4_1       0x80000000
+                                /* FEC RST */
+                                MX53_PAD_GPIO_12__GPIO4_2       0x80000000
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D16__ECSPI1_SCLK           0x80000000
+                                MX53_PAD_EIM_D17__ECSPI1_MISO           0x80000000
+                                MX53_PAD_EIM_D18__ECSPI1_MOSI           0x80000000
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX53_PAD_FEC_MDC__FEC_MDC               0x80000000
+                                MX53_PAD_FEC_MDIO__FEC_MDIO             0x80000000
+                                MX53_PAD_FEC_REF_CLK__FEC_TX_CLK        0x80000000
+                                MX53_PAD_FEC_RX_ER__FEC_RX_ER           0x80000000
+                                MX53_PAD_FEC_CRS_DV__FEC_RX_DV          0x80000000
+                                MX53_PAD_FEC_RXD1__FEC_RDATA_1          0x80000000
+                                MX53_PAD_FEC_RXD0__FEC_RDATA_0          0x80000000
+                                MX53_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                                MX53_PAD_FEC_TXD1__FEC_TDATA_1          0x80000000
+                                MX53_PAD_FEC_TXD0__FEC_TDATA_0          0x80000000
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX53_PAD_EIM_D21__I2C1_SCL              0xc0000000
+                                MX53_PAD_EIM_D28__I2C1_SDA              0xc0000000
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DIOW__UART1_TXD_MUX       0x1e4
+                                MX53_PAD_PATA_DMACK__UART1_RXD_MUX      0x1e4
+                        >;
+                };
+                pinctrl_nand: nandgrp {
+                        fsl,pins = <
+                                MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
+                                MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
+                                MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
+                                MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
+                                MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
+                                MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
+                                MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
+                                MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
+                                MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
+                                MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
+                                MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
+                                MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
+                                MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
+                                MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
+                                MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
+                        >;
+                };
+        };
+};
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        fsl,spi-num-chipselects = <4>;
+        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        phy-mode = "rmii";
+        phy-reset-gpios = <&gpio4 2 0>;
+        status = "okay";
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        pmic: dialog@48 {
+                compatible = "dlg,da9053-aa", "dlg,da9052";
+                reg = <0x48>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
+                regulators {
+                        buck1_reg: buck1 {
+                                regulator-name = "BUCKCORE";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1400000>;
+                                regulator-always-on;
+                        };
+                        buck2_reg: buck2 {
+                                regulator-name = "BUCKPRO";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                        };
+                        buck3_reg: buck3 {
+                                regulator-name = "BUCKMEM";
+                                regulator-min-microvolt = <1420000>;
+                                regulator-max-microvolt = <1580000>;
+                                regulator-always-on;
+                        };
+                        buck4_reg: buck4 {
+                                regulator-name = "BUCKPERI";
+                                regulator-min-microvolt = <2370000>;
+                                regulator-max-microvolt = <2630000>;
+                                regulator-always-on;
+                        };
+                        ldo1_reg: ldo1 {
+                                regulator-name = "ldo1_1v3";
+                                regulator-min-microvolt = <1250000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        ldo2_reg: ldo2 {
+                                regulator-name = "ldo2_1v3";
+                                regulator-min-microvolt = <1250000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                        };
+                        ldo3_reg: ldo3 {
+                                regulator-name = "ldo3_3v3";
+                                regulator-min-microvolt = <3250000>;
+                                regulator-max-microvolt = <3350000>;
+                                regulator-always-on;
+                        };
+                        ldo4_reg: ldo4 {
+                                regulator-name = "ldo4_2v775";
+                                regulator-min-microvolt = <2770000>;
+                                regulator-max-microvolt = <2780000>;
+                                regulator-always-on;
+                        };
+                        ldo5_reg: ldo5 {
+                                regulator-name = "ldo5_3v3";
+                                regulator-min-microvolt = <3250000>;
+                                regulator-max-microvolt = <3350000>;
+                                regulator-always-on;
+                        };
+                        ldo6_reg: ldo6 {
+                                regulator-name = "ldo6_1v3";
+                                regulator-min-microvolt = <1250000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                        };
+                        ldo7_reg: ldo7 {
+                                regulator-name = "ldo7_2v75";
+                                regulator-min-microvolt = <2700000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                        };
+                        ldo8_reg: ldo8 {
+                                regulator-name = "ldo8_1v8";
+                                regulator-min-microvolt = <1750000>;
+                                regulator-max-microvolt = <1850000>;
+                                regulator-always-on;
+                        };
+                        ldo9_reg: ldo9 {
+                                regulator-name = "ldo9_1v5";
+                                regulator-min-microvolt = <1450000>;
+                                regulator-max-microvolt = <1550000>;
+                                regulator-always-on;
+                        };
+                        ldo10_reg: ldo10 {
+                                regulator-name = "ldo10_1v3";
+                                regulator-min-microvolt = <1250000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nand>;
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&usbh1 {
+        vbus-supply = <&reg_usb_vbus>;
+        phy_type = "utmi";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 4307e80b2d2e..b57ab57740f6 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -12,6 +12,9 @@
 #include "skeleton.dtsi"
 #include "imx53-pinfunc.h"
+#include <dt-bindings/clock/imx5-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 / {
        aliases {
@@ -25,6 +28,10 @@
                i2c0 = &i2c1;
                i2c1 = &i2c2;
                i2c2 = &i2c3;
+                mmc0 = &esdhc1;
+                mmc1 = &esdhc2;
+                mmc2 = &esdhc3;
+                mmc3 = &esdhc4;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
@@ -45,6 +52,11 @@
                };
        };
+        display-subsystem {
+                compatible = "fsl,imx-display-subsystem";
+                ports = <&ipu_di0>, <&ipu_di1>;
+        };
        tzic: tz-interrupt-controller@0fffc000 {
                compatible = "fsl,imx53-tzic", "fsl,tzic";
                interrupt-controller;
@@ -84,14 +96,63 @@
                interrupt-parent = <&tzic>;
                ranges;
+                sata: sata@10000000 {
+                        compatible = "fsl,imx53-ahci";
+                        reg = <0x10000000 0x1000>;
+                        interrupts = <28>;
+                        clocks = <&clks IMX5_CLK_SATA_GATE>,
+                                 <&clks IMX5_CLK_SATA_REF>,
+                                 <&clks IMX5_CLK_AHB>;
+                        clock-names = "sata_gate", "sata_ref", "ahb";
+                        status = "disabled";
+                };
                ipu: ipu@18000000 {
-                        #crtc-cells = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                        compatible = "fsl,imx53-ipu";
                        reg = <0x18000000 0x080000000>;
                        interrupts = <11 10>;
-                        clocks = <&clks 59>, <&clks 110>, <&clks 61>;
+                        clocks = <&clks IMX5_CLK_IPU_GATE>,
+                                 <&clks IMX5_CLK_IPU_DI0_GATE>,
+                                 <&clks IMX5_CLK_IPU_DI1_GATE>;
                        clock-names = "bus", "di0", "di1";
                        resets = <&src 2>;
+                        ipu_di0: port@2 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <2>;
+                                ipu_di0_disp0: endpoint@0 {
+                                        reg = <0>;
+                                };
+                                ipu_di0_lvds0: endpoint@1 {
+                                        reg = <1>;
+                                        remote-endpoint = <&lvds0_in>;
+                                };
+                        };
+                        ipu_di1: port@3 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <3>;
+                                ipu_di1_disp1: endpoint@0 {
+                                        reg = <0>;
+                                };
+                                ipu_di1_lvds1: endpoint@1 {
+                                        reg = <1>;
+                                        remote-endpoint = <&lvds1_in>;
+                                };
+                                ipu_di1_tve: endpoint@2 {
+                                        reg = <2>;
+                                        remote-endpoint = <&tve_in>;
+                                };
+                        };
                };
                aips@50000000 { /* AIPS1 */
@@ -112,7 +173,9 @@
                                        compatible = "fsl,imx53-esdhc";
                                        reg = <0x50004000 0x4000>;
                                        interrupts = <1>;
-                                        clocks = <&clks 44>, <&clks 0>, <&clks 71>;
+                                        clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
                                        clock-names = "ipg", "ahb", "per";
                                        bus-width = <4>;
                                        status = "disabled";
@@ -122,7 +185,9 @@
                                        compatible = "fsl,imx53-esdhc";
                                        reg = <0x50008000 0x4000>;
                                        interrupts = <2>;
-                                        clocks = <&clks 45>, <&clks 0>, <&clks 72>;
+                                        clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
                                        clock-names = "ipg", "ahb", "per";
                                        bus-width = <4>;
                                        status = "disabled";
@@ -132,7 +197,8 @@
                                        compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                        reg = <0x5000c000 0x4000>;
                                        interrupts = <33>;
-                                        clocks = <&clks 32>, <&clks 33>;
+                                        clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
+                                                 <&clks IMX5_CLK_UART3_PER_GATE>;
                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
@@ -143,16 +209,19 @@
                                        compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x50010000 0x4000>;
                                        interrupts = <36>;
-                                        clocks = <&clks 51>, <&clks 52>;
+                                        clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
+                                                 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
                                        clock-names = "ipg", "per";
                                        status = "disabled";
                                };
                                ssi2: ssi@50014000 {
-                                        compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
+                                        compatible = "fsl,imx53-ssi",
+                                                        "fsl,imx51-ssi",
+                                                        "fsl,imx21-ssi";
                                        reg = <0x50014000 0x4000>;
                                        interrupts = <30>;
-                                        clocks = <&clks 49>;
+                                        clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
                                        dmas = <&sdma 24 1 0>,
                                               <&sdma 25 1 0>;
                                        dma-names = "rx", "tx";
@@ -165,7 +234,9 @@
                                        compatible = "fsl,imx53-esdhc";
                                        reg = <0x50020000 0x4000>;
                                        interrupts = <3>;
-                                        clocks = <&clks 46>, <&clks 0>, <&clks 73>;
+                                        clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
                                        clock-names = "ipg", "ahb", "per";
                                        bus-width = <4>;
                                        status = "disabled";
@@ -175,7 +246,9 @@
                                        compatible = "fsl,imx53-esdhc";
                                        reg = <0x50024000 0x4000>;
                                        interrupts = <4>;
-                                        clocks = <&clks 47>, <&clks 0>, <&clks 74>;
+                                        clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
+                                                 <&clks IMX5_CLK_DUMMY>,
+                                                 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
                                        clock-names = "ipg", "ahb", "per";
                                        bus-width = <4>;
                                        status = "disabled";
@@ -184,14 +257,14 @@
                        usbphy0: usbphy@0 {
                                compatible = "usb-nop-xceiv";
-                                clocks = <&clks 124>;
+                                clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
                                clock-names = "main_clk";
                                status = "okay";
                        };
                        usbphy1: usbphy@1 {
                                compatible = "usb-nop-xceiv";
-                                clocks = <&clks 125>;
+                                clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
                                clock-names = "main_clk";
                                status = "okay";
                        };
@@ -200,7 +273,7 @@
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80000 0x0200>;
                                interrupts = <18>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 0>;
                                fsl,usbphy = <&usbphy0>;
                                status = "disabled";
@@ -210,7 +283,7 @@
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80200 0x0200>;
                                interrupts = <14>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 1>;
                                fsl,usbphy = <&usbphy1>;
                                status = "disabled";
@@ -220,7 +293,7 @@
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80400 0x0200>;
                                interrupts = <16>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 2>;
                                status = "disabled";
                        };
@@ -229,7 +302,7 @@
                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                reg = <0x53f80600 0x0200>;
                                interrupts = <17>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 3>;
                                status = "disabled";
                        };
@@ -238,7 +311,7 @@
                                #index-cells = <1>;
                                compatible = "fsl,imx53-usbmisc";
                                reg = <0x53f80800 0x200>;
-                                clocks = <&clks 108>;
+                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                        };
                        gpio1: gpio@53f84000 {
@@ -281,18 +354,26 @@
                                #interrupt-cells = <2>;
                        };
+                        kpp: kpp@53f94000 {
+                                compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
+                                reg = <0x53f94000 0x4000>;
+                                interrupts = <60>;
+                                clocks = <&clks IMX5_CLK_DUMMY>;
+                                status = "disabled";
+                        };
                        wdog1: wdog@53f98000 {
                                compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
                                reg = <0x53f98000 0x4000>;
                                interrupts = <58>;
-                                clocks = <&clks 0>;
+                                clocks = <&clks IMX5_CLK_DUMMY>;
                        };
                        wdog2: wdog@53f9c000 {
                                compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
                                reg = <0x53f9c000 0x4000>;
                                interrupts = <59>;
-                                clocks = <&clks 0>;
+                                clocks = <&clks IMX5_CLK_DUMMY>;
                                status = "disabled";
                        };
@@ -300,521 +381,14 @@
                                compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
                                reg = <0x53fa0000 0x4000>;
                                interrupts = <39>;
-                                clocks = <&clks 36>, <&clks 41>;
+                                clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
+                                         <&clks IMX5_CLK_GPT_HF_GATE>;
                                clock-names = "ipg", "per";
                        };
                        iomuxc: iomuxc@53fa8000 {
                                compatible = "fsl,imx53-iomuxc";
                                reg = <0x53fa8000 0x4000>;
-                                audmux {
-                                        pinctrl_audmux_1: audmuxgrp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000
-                                                        MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000
-                                                        MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
-                                                        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
-                                                >;
-                                        };
-                                        pinctrl_audmux_2: audmuxgrp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
-                                                        MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
-                                                        MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
-                                                        MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
-                                                >;
-                                        };
-                                        pinctrl_audmux_3: audmuxgrp-3 {
-                                                fsl,pins = <
-                                                        MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC     0x80000000
-                                                        MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD     0x80000000
-                                                        MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS    0x80000000
-                                                        MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD     0x80000000
-                                                >;
-                                        };
-                                };
-                                fec {
-                                        pinctrl_fec_1: fecgrp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
-                                                        MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
-                                                        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
-                                                        MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
-                                                        MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
-                                                        MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
-                                                        MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
-                                                        MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
-                                                        MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
-                                                        MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
-                                                >;
-                                        };
-                                        pinctrl_fec_2: fecgrp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
-                                                        MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
-                                                        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
-                                                        MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
-                                                        MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
-                                                        MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
-                                                        MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
-                                                        MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
-                                                        MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
-                                                        MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
-                                                        MX53_PAD_KEY_ROW1__FEC_COL       0x80000000
-                                                        MX53_PAD_KEY_COL3__FEC_CRS       0x80000000
-                                                        MX53_PAD_KEY_COL2__FEC_RDATA_2   0x80000000
-                                                        MX53_PAD_KEY_COL0__FEC_RDATA_3   0x80000000
-                                                        MX53_PAD_KEY_COL1__FEC_RX_CLK    0x80000000
-                                                        MX53_PAD_KEY_ROW2__FEC_TDATA_2   0x80000000
-                                                        MX53_PAD_GPIO_19__FEC_TDATA_3    0x80000000
-                                                        MX53_PAD_KEY_ROW0__FEC_TX_ER     0x80000000
-                                                >;
-                                        };
-                                };
-                                csi {
-                                        pinctrl_csi_1: csigrp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
-                                                        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
-                                                        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
-                                                        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
-                                                        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
-                                                        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
-                                                        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
-                                                        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
-                                                        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
-                                                        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
-                                                        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
-                                                        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
-                                                        MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11      0x1d5
-                                                        MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10      0x1d5
-                                                        MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9        0x1d5
-                                                        MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8        0x1d5
-                                                        MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7        0x1d5
-                                                        MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6        0x1d5
-                                                        MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5        0x1d5
-                                                        MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4        0x1d5
-                                                        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
-                                                >;
-                                        };
-                                        pinctrl_csi_2: csigrp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
-                                                        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
-                                                        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
-                                                        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
-                                                        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
-                                                        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
-                                                        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
-                                                        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
-                                                        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
-                                                        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
-                                                        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
-                                                >;
-                                        };
-                                };
-                                cspi {
-                                        pinctrl_cspi_1: cspigrp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
-                                                        MX53_PAD_SD1_CMD__CSPI_MOSI   0x1d5
-                                                        MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
-                                                >;
-                                        };
-                                        pinctrl_cspi_2: cspigrp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
-                                                        MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
-                                                        MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
-                                                >;
-                                        };
-                                };
-                                ecspi1 {
-                                        pinctrl_ecspi1_1: ecspi1grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
-                                                        MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
-                                                        MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
-                                                >;
-                                        };
-                                        pinctrl_ecspi1_2: ecspi1grp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_GPIO_19__ECSPI1_RDY    0x80000000
-                                                        MX53_PAD_EIM_EB2__ECSPI1_SS0    0x80000000
-                                                        MX53_PAD_EIM_D16__ECSPI1_SCLK   0x80000000
-                                                        MX53_PAD_EIM_D17__ECSPI1_MISO   0x80000000
-                                                        MX53_PAD_EIM_D18__ECSPI1_MOSI   0x80000000
-                                                        MX53_PAD_EIM_D19__ECSPI1_SS1    0x80000000
-                                                >;
-                                        };
-                                };
-                                ecspi2 {
-                                        pinctrl_ecspi2_1: ecspi2grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_EIM_OE__ECSPI2_MISO  0x80000000
-                                                        MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
-                                                        MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
-                                                >;
-                                        };
-                                };
-                                esdhc1 {
-                                        pinctrl_esdhc1_1: esdhc1grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
-                                                        MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
-                                                        MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
-                                                        MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
-                                                        MX53_PAD_SD1_CMD__ESDHC1_CMD    0x1d5
-                                                        MX53_PAD_SD1_CLK__ESDHC1_CLK    0x1d5
-                                                >;
-                                        };
-                                        pinctrl_esdhc1_2: esdhc1grp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_SD1_DATA0__ESDHC1_DAT0   0x1d5
-                                                        MX53_PAD_SD1_DATA1__ESDHC1_DAT1   0x1d5
-                                                        MX53_PAD_SD1_DATA2__ESDHC1_DAT2   0x1d5
-                                                        MX53_PAD_SD1_DATA3__ESDHC1_DAT3   0x1d5
-                                                        MX53_PAD_PATA_DATA8__ESDHC1_DAT4  0x1d5
-                                                        MX53_PAD_PATA_DATA9__ESDHC1_DAT5  0x1d5
-                                                        MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
-                                                        MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
-                                                        MX53_PAD_SD1_CMD__ESDHC1_CMD      0x1d5
-                                                        MX53_PAD_SD1_CLK__ESDHC1_CLK      0x1d5
-                                                >;
-                                        };
-                                };
-                                esdhc2 {
-                                        pinctrl_esdhc2_1: esdhc2grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_SD2_CMD__ESDHC2_CMD    0x1d5
-                                                        MX53_PAD_SD2_CLK__ESDHC2_CLK    0x1d5
-                                                        MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
-                                                        MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
-                                                        MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
-                                                        MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
-                                                >;
-                                        };
-                                };
-                                esdhc3 {
-                                        pinctrl_esdhc3_1: esdhc3grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_PATA_DATA8__ESDHC3_DAT0  0x1d5
-                                                        MX53_PAD_PATA_DATA9__ESDHC3_DAT1  0x1d5
-                                                        MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
-                                                        MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
-                                                        MX53_PAD_PATA_DATA0__ESDHC3_DAT4  0x1d5
-                                                        MX53_PAD_PATA_DATA1__ESDHC3_DAT5  0x1d5
-                                                        MX53_PAD_PATA_DATA2__ESDHC3_DAT6  0x1d5
-                                                        MX53_PAD_PATA_DATA3__ESDHC3_DAT7  0x1d5
-                                                        MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
-                                                        MX53_PAD_PATA_IORDY__ESDHC3_CLK   0x1d5
-                                                >;
-                                        };
-                                };
-                                can1 {
-                                        pinctrl_can1_1: can1grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
-                                                        MX53_PAD_PATA_DIOR__CAN1_RXCAN  0x80000000
-                                                >;
-                                        };
-                                        pinctrl_can1_2: can1grp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
-                                                        MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
-                                                >;
-                                        };
-                                        pinctrl_can1_3: can1grp-3 {
-                                                fsl,pins = <
-                                                        MX53_PAD_GPIO_7__CAN1_TXCAN     0x80000000
-                                                        MX53_PAD_GPIO_8__CAN1_RXCAN     0x80000000
-                                                >;
-                                        };
-                                };
-                                can2 {
-                                        pinctrl_can2_1: can2grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
-                                                        MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
-                                                >;
-                                        };
-                                };
-                                i2c1 {
-                                        pinctrl_i2c1_1: i2c1grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
-                                                        MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
-                                                >;
-                                        };
-                                        pinctrl_i2c1_2: i2c1grp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_EIM_D21__I2C1_SCL      0xc0000000
-                                                        MX53_PAD_EIM_D28__I2C1_SDA      0xc0000000
-                                                >;
-                                        };
-                                };
-                                i2c2 {
-                                        pinctrl_i2c2_1: i2c2grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
-                                                        MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
-                                                >;
-                                        };
-                                        pinctrl_i2c2_2: i2c2grp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_EIM_D16__I2C2_SDA      0xc0000000
-                                                        MX53_PAD_EIM_EB2__I2C2_SCL      0xc0000000
-                                                >;
-                                        };
-                                };
-                                i2c3 {
-                                        pinctrl_i2c3_1: i2c3grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
-                                                        MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
-                                                >;
-                                        };
-                                };
-                                ipu_disp0 {
-                                        pinctrl_ipu_disp0_1: ipudisp0grp-1 {
-                                                fsl,pins = <
-                                                MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
-                                                MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               0x5
-                                                MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
-                                                MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 0x5
-                                                MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            0x5
-                                                MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            0x5
-                                                MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            0x5
-                                                MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            0x5
-                                                MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            0x5
-                                                MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            0x5
-                                                MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            0x5
-                                                MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            0x5
-                                                MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            0x5
-                                                MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            0x5
-                                                MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          0x5
-                                                MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          0x5
-                                                MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          0x5
-                                                MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          0x5
-                                                MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          0x5
-                                                MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          0x5
-                                                MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          0x5
-                                                MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          0x5
-                                                MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          0x5
-                                                MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          0x5
-                                                MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          0x5
-                                                MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          0x5
-                                                MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          0x5
-                                                MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          0x5
-                                                >;
-                                        };
-                                };
-                                ipu_disp1 {
-                                        pinctrl_ipu_disp1_1: ipudisp1grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
-                                                        MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
-                                                        MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
-                                                        MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
-                                                        MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
-                                                        MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
-                                                        MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
-                                                        MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
-                                                        MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
-                                                        MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
-                                                        MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
-                                                        MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
-                                                        MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
-                                                        MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
-                                                        MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
-                                                        MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
-                                                        MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
-                                                        MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
-                                                        MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
-                                                        MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
-                                                        MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
-                                                        MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
-                                                        MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
-                                                        MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
-                                                        MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
-                                                        MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
-                                                        MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
-                                                        MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
-                                                        MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
-                                                        MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
-                                                        MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
-                                                        MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
-                                                >;
-                                        };
-                                };
-                                ipu_disp2 {
-                                        pinctrl_ipu_disp2_1: ipudisp2grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0     0x80000000
-                                                        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1     0x80000000
-                                                        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2     0x80000000
-                                                        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3     0x80000000
-                                                        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK     0x80000000
-                                                        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0     0x80000000
-                                                        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1     0x80000000
-                                                        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2     0x80000000
-                                                        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3     0x80000000
-                                                        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK     0x80000000
-                                                >;
-                                        };
-                                };
-                                nand {
-                                        pinctrl_nand_1: nandgrp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
-                                                        MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
-                                                        MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
-                                                        MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
-                                                        MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
-                                                        MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
-                                                        MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
-                                                        MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
-                                                        MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
-                                                        MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
-                                                        MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
-                                                        MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
-                                                        MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
-                                                        MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
-                                                        MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
-                                                >;
-                                        };
-                                };
-                                owire {
-                                        pinctrl_owire_1: owiregrp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
-                                                >;
-                                        };
-                                };
-                                pwm1 {
-                                        pinctrl_pwm1_1: pwm1grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_DISP0_DAT8__PWM1_PWMO  0x5
-                                                >;
-                                        };
-                                };
-                                pwm2 {
-                                        pinctrl_pwm2_1: pwm2grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000
-                                                >;
-                                        };
-                                };
-                                uart1 {
-                                        pinctrl_uart1_1: uart1grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
-                                                        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
-                                                >;
-                                        };
-                                        pinctrl_uart1_2: uart1grp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1e4
-                                                        MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
-                                                >;
-                                        };
-                                        pinctrl_uart1_3: uart1grp-3 {
-                                                fsl,pins = <
-                                                        MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
-                                                        MX53_PAD_PATA_IORDY__UART1_RTS   0x1c5
-                                                >;
-                                        };
-                                };
-                                uart2 {
-                                        pinctrl_uart2_1: uart2grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
-                                                        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1e4
-                                                >;
-                                        };
-                                        pinctrl_uart2_2: uart2grp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1c5
-                                                        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1c5
-                                                        MX53_PAD_PATA_DIOR__UART2_RTS           0x1c5
-                                                        MX53_PAD_PATA_INTRQ__UART2_CTS          0x1c5
-                                                >;
-                                        };
-                                };
-                                uart3 {
-                                        pinctrl_uart3_1: uart3grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
-                                                        MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
-                                                        MX53_PAD_PATA_DA_1__UART3_CTS     0x1e4
-                                                        MX53_PAD_PATA_DA_2__UART3_RTS     0x1e4
-                                                >;
-                                        };
-                                        pinctrl_uart3_2: uart3grp-2 {
-                                                fsl,pins = <
-                                                        MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
-                                                        MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
-                                                >;
-                                        };
-                                };
-                                uart4 {
-                                        pinctrl_uart4_1: uart4grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
-                                                        MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
-                                                >;
-                                        };
-                                };
-                                uart5 {
-                                        pinctrl_uart5_1: uart5grp-1 {
-                                                fsl,pins = <
-                                                        MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
-                                                        MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
-                                                >;
-                                        };
-                                };
                        };
                        gpr: iomuxc-gpr@53fa8000 {
@@ -828,9 +402,12 @@
                                compatible = "fsl,imx53-ldb";
                                reg = <0x53fa8008 0x4>;
                                gpr = <&gpr>;
-                                clocks = <&clks 122>, <&clks 120>,
+                                clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
-                                         <&clks 115>, <&clks 116>,
+                                         <&clks IMX5_CLK_LDB_DI1_SEL>,
-                                         <&clks 123>, <&clks 85>;
+                                         <&clks IMX5_CLK_IPU_DI0_SEL>,
+                                         <&clks IMX5_CLK_IPU_DI1_SEL>,
+                                         <&clks IMX5_CLK_LDB_DI0_GATE>,
+                                         <&clks IMX5_CLK_LDB_DI1_GATE>;
                                clock-names = "di0_pll", "di1_pll",
                                              "di0_sel", "di1_sel",
                                              "di0", "di1";
@@ -838,14 +415,24 @@
                                lvds-channel@0 {
                                        reg = <0>;
-                                        crtcs = <&ipu 0>;
                                        status = "disabled";
+                                        port {
+                                                lvds0_in: endpoint {
+                                                        remote-endpoint = <&ipu_di0_lvds0>;
+                                                };
+                                        };
                                };
                                lvds-channel@1 {
                                        reg = <1>;
-                                        crtcs = <&ipu 1>;
                                        status = "disabled";
+                                        port {
+                                                lvds1_in: endpoint {
+                                                        remote-endpoint = <&ipu_di0_lvds0>;
+                                                };
+                                        };
                                };
                        };
@@ -853,7 +440,8 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
                                reg = <0x53fb4000 0x4000>;
-                                clocks = <&clks 37>, <&clks 38>;
+                                clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
+                                         <&clks IMX5_CLK_PWM1_HF_GATE>;
                                clock-names = "ipg", "per";
                                interrupts = <61>;
                        };
@@ -862,7 +450,8 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
                                reg = <0x53fb8000 0x4000>;
-                                clocks = <&clks 39>, <&clks 40>;
+                                clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
+                                         <&clks IMX5_CLK_PWM2_HF_GATE>;
                                clock-names = "ipg", "per";
                                interrupts = <94>;
                        };
@@ -871,7 +460,8 @@
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53fbc000 0x4000>;
                                interrupts = <31>;
-                                clocks = <&clks 28>, <&clks 29>;
+                                clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART1_PER_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -880,7 +470,8 @@
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53fc0000 0x4000>;
                                interrupts = <32>;
-                                clocks = <&clks 30>, <&clks 31>;
+                                clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART2_PER_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -889,7 +480,8 @@
                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
                                reg = <0x53fc8000 0x4000>;
                                interrupts = <82>;
-                                clocks = <&clks 158>, <&clks 157>;
+                                clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
+                                         <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -898,7 +490,8 @@
                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
                                reg = <0x53fcc000 0x4000>;
                                interrupts = <83>;
-                                clocks = <&clks 87>, <&clks 86>;
+                                clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
+                                         <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -952,7 +545,7 @@
                                compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
                                reg = <0x53fec000 0x4000>;
                                interrupts = <64>;
-                                clocks = <&clks 88>;
+                                clocks = <&clks IMX5_CLK_I2C3_GATE>;
                                status = "disabled";
                        };
@@ -960,7 +553,8 @@
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53ff0000 0x4000>;
                                interrupts = <13>;
-                                clocks = <&clks 65>, <&clks 66>;
+                                clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART4_PER_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -977,14 +571,15 @@
                                compatible = "fsl,imx53-iim", "fsl,imx27-iim";
                                reg = <0x63f98000 0x4000>;
                                interrupts = <69>;
-                                clocks = <&clks 107>;
+                                clocks = <&clks IMX5_CLK_IIM_GATE>;
                        };
                        uart5: serial@63f90000 {
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x63f90000 0x4000>;
                                interrupts = <86>;
-                                clocks = <&clks 67>, <&clks 68>;
+                                clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
+                                         <&clks IMX5_CLK_UART5_PER_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -992,7 +587,7 @@
                        owire: owire@63fa4000 {
                                compatible = "fsl,imx53-owire", "fsl,imx21-owire";
                                reg = <0x63fa4000 0x4000>;
-                                clocks = <&clks 159>;
+                                clocks = <&clks IMX5_CLK_OWIRE_GATE>;
                                status = "disabled";
                        };
@@ -1002,7 +597,8 @@
                                compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
                                reg = <0x63fac000 0x4000>;
                                interrupts = <37>;
-                                clocks = <&clks 53>, <&clks 54>;
+                                clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
+                                         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -1011,7 +607,8 @@
                                compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
                                reg = <0x63fb0000 0x4000>;
                                interrupts = <6>;
-                                clocks = <&clks 56>, <&clks 56>;
+                                clocks = <&clks IMX5_CLK_SDMA_GATE>,
+                                         <&clks IMX5_CLK_SDMA_GATE>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
@@ -1023,7 +620,8 @@
                                compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
                                reg = <0x63fc0000 0x4000>;
                                interrupts = <38>;
-                                clocks = <&clks 55>, <&clks 55>;
+                                clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
+                                         <&clks IMX5_CLK_CSPI_IPG_GATE>;
                                clock-names = "ipg", "per";
                                status = "disabled";
                        };
@@ -1034,7 +632,7 @@
                                compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
                                reg = <0x63fc4000 0x4000>;
                                interrupts = <63>;
-                                clocks = <&clks 35>;
+                                clocks = <&clks IMX5_CLK_I2C2_GATE>;
                                status = "disabled";
                        };
@@ -1044,15 +642,16 @@
                                compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
                                reg = <0x63fc8000 0x4000>;
                                interrupts = <62>;
-                                clocks = <&clks 34>;
+                                clocks = <&clks IMX5_CLK_I2C1_GATE>;
                                status = "disabled";
                        };
                        ssi1: ssi@63fcc000 {
-                                compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
+                                compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
+                                                "fsl,imx21-ssi";
                                reg = <0x63fcc000 0x4000>;
                                interrupts = <29>;
-                                clocks = <&clks 48>;
+                                clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
                                dmas = <&sdma 28 0 0>,
                                       <&sdma 29 0 0>;
                                dma-names = "rx", "tx";
@@ -1071,15 +670,16 @@
                                compatible = "fsl,imx53-nand";
                                reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
                                interrupts = <8>;
-                                clocks = <&clks 60>;
+                                clocks = <&clks IMX5_CLK_NFC_GATE>;
                                status = "disabled";
                        };
                        ssi3: ssi@63fe8000 {
-                                compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
+                                compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
+                                                "fsl,imx21-ssi";
                                reg = <0x63fe8000 0x4000>;
                                interrupts = <96>;
-                                clocks = <&clks 50>;
+                                clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
                                dmas = <&sdma 46 0 0>,
                                       <&sdma 47 0 0>;
                                dma-names = "rx", "tx";
@@ -1092,7 +692,9 @@
                                compatible = "fsl,imx53-fec", "fsl,imx25-fec";
                                reg = <0x63fec000 0x4000>;
                                interrupts = <87>;
-                                clocks = <&clks 42>, <&clks 42>, <&clks 42>;
+                                clocks = <&clks IMX5_CLK_FEC_GATE>,
+                                         <&clks IMX5_CLK_FEC_GATE>,
+                                         <&clks IMX5_CLK_FEC_GATE>;
                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
                        };
@@ -1101,17 +703,24 @@
                                compatible = "fsl,imx53-tve";
                                reg = <0x63ff0000 0x1000>;
                                interrupts = <92>;
-                                clocks = <&clks 69>, <&clks 116>;
+                                clocks = <&clks IMX5_CLK_TVE_GATE>,
+                                         <&clks IMX5_CLK_IPU_DI1_SEL>;
                                clock-names = "tve", "di_sel";
-                                crtcs = <&ipu 1>;
                                status = "disabled";
+                                port {
+                                        tve_in: endpoint {
+                                                remote-endpoint = <&ipu_di1_tve>;
+                                        };
+                                };
                        };
                        vpu: vpu@63ff4000 {
                                compatible = "fsl,imx53-vpu";
                                reg = <0x63ff4000 0x1000>;
                                interrupts = <9>;
-                                clocks = <&clks 63>, <&clks 63>;
+                                clocks = <&clks IMX5_CLK_VPU_GATE>,
+                                         <&clks IMX5_CLK_VPU_GATE>;
                                clock-names = "per", "ahb";
                                iram = <&ocram>;
                                status = "disabled";
@@ -1121,7 +730,7 @@
                ocram: sram@f8000000 {
                        compatible = "mmio-sram";
                        reg = <0xf8000000 0x20000>;
-                        clocks = <&clks 186>;
+                        clocks = <&clks IMX5_CLK_OCRAM>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
new file mode 100644
index 000000000000..994f96a3fb54
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __DTS_V1__
+#define __DTS_V1__
+/dts-v1/;
+#endif
+#include "imx6dl.dtsi"
+#include "imx6qdl-dfi-fs700-m60.dtsi"
+/ {
+        model = "DFI FS700-M60-6DL i.MX6dl Q7 Board";
+        compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw51xx.dts b/arch/arm/boot/dts/imx6dl-gw51xx.dts
new file mode 100644
index 000000000000..4bd055f4c930
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw51xx.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw51xx.dtsi"
+/ {
+        model = "Gateworks Ventana i.MX6 DualLite GW51XX";
+        compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/imx6dl-gw52xx.dts
new file mode 100644
index 000000000000..c9136058f15e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw52xx.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw52xx.dtsi"
+/ {
+        model = "Gateworks Ventana i.MX6 DualLite GW52XX";
+        compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/imx6dl-gw53xx.dts
new file mode 100644
index 000000000000..61818a14fde6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw53xx.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw53xx.dtsi"
+/ {
+        model = "Gateworks Ventana i.MX6 DualLite GW53XX";
+        compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/imx6dl-gw54xx.dts
new file mode 100644
index 000000000000..ab38b6770a06
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw54xx.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw54xx.dtsi"
+/ {
+        model = "Gateworks Ventana i.MX6 DualLite GW54XX";
+        compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts
new file mode 100644
index 000000000000..5f4d33ccc4b3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2013 Boundary Devices, Inc.
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-nitrogen6x.dtsi"
+/ {
+        model = "Freescale i.MX6 DualLite Nitrogen6x Board";
+        compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
index b81a7a4ebab6..0ead323fdbd2 100644
--- a/arch/arm/boot/dts/imx6dl-pinfunc.h
+++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
@@ -755,6 +755,7 @@
 #define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
 #define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__ENET_IRQ                 0x234 0x604 0x03c 0x11 0xff000609
 #define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
 #define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
@@ -950,6 +951,7 @@
 #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19            0x2d8 0x6c0 0x000 0x5 0x0
 #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x2d8 0x6c0 0x000 0x7 0x0
 #define MX6QDL_PAD_SD1_CLK__SD1_CLK                 0x2dc 0x6c4 0x928 0x0 0x1
+#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT          0x2dc 0x6c4 0x000 0x2 0x0
 #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN               0x2dc 0x6c4 0x000 0x3 0x0
 #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20              0x2dc 0x6c4 0x000 0x5 0x0
 #define MX6QDL_PAD_SD1_CMD__SD1_CMD                 0x2e0 0x6c8 0x000 0x0 0x0
diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/imx6dl-sabrelite.dts
new file mode 100644
index 000000000000..2de04479dc35
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-sabrelite.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-sabrelite.dtsi"
+/ {
+        model = "Freescale i.MX6 DualLite SABRE Lite Board";
+        compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 9e8ae118fdd4..5c5f574330f9 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -8,6 +8,7 @@
 *
 */
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "imx6dl-pinfunc.h"
 #include "imx6qdl.dtsi"
@@ -21,6 +22,26 @@
                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L2>;
+                        operating-points = <
+                                /* kHz    uV */
+                                996000  1275000
+                                792000  1175000
+                                396000  1075000
+                        >;
+                        fsl,soc-operating-points = <
+                                /* ARM kHz  SOC-PU uV */
+                                996000  1175000
+                                792000  1175000
+                                396000  1175000
+                        >;
+                        clock-latency = <61036>; /* two CLK32 periods */
+                        clocks = <&clks 104>, <&clks 6>, <&clks 16>,
+                                 <&clks 17>, <&clks 170>;
+                        clock-names = "arm", "pll2_pfd2_396m", "step",
+                                      "pll1_sw", "pll1_sys";
+                        arm-supply = <&reg_arm>;
+                        pu-supply = <&reg_pu>;
+                        soc-supply = <&reg_soc>;
                };
                cpu@1 {
@@ -45,17 +66,17 @@
                        pxp: pxp@020f0000 {
                                reg = <0x020f0000 0x4000>;
-                                interrupts = <0 98 0x04>;
+                                interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        epdc: epdc@020f4000 {
                                reg = <0x020f4000 0x4000>;
-                                interrupts = <0 97 0x04>;
+                                interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        lcdif: lcdif@020f8000 {
                                reg = <0x020f8000 0x4000>;
-                                interrupts = <0 39 0x04>;
+                                interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
@@ -65,11 +86,20 @@
                                #size-cells = <0>;
                                compatible = "fsl,imx1-i2c";
                                reg = <0x021f8000 0x4000>;
-                                interrupts = <0 35 0x04>;
+                                interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
                                status = "disabled";
                        };
                };
        };
+        display-subsystem {
+                compatible = "fsl,imx-display-subsystem";
+                ports = <&ipu1_di0>, <&ipu1_di1>;
+        };
+};
+&hdmi {
+        compatible = "fsl,imx6dl-hdmi";
 };
 &ldb {
@@ -79,12 +109,4 @@
        clock-names = "di0_pll", "di1_pll",
                      "di0_sel", "di1_sel",
                      "di0", "di1";
-        lvds-channel@0 {
-                crtcs = <&ipu1 0>, <&ipu1 1>;
-        };
-        lvds-channel@1 {
-                crtcs = <&ipu1 0>, <&ipu1 1>;
-        };
 };
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index edf1bd967164..78df05e9d1ce 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -23,14 +23,27 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_3p3v: 3p3v {
+                reg_3p3v: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };
+                reg_usb_otg_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
        };
        leds {
@@ -46,7 +59,7 @@
 &gpmi {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
        status = "disabled"; /* gpmi nand conflicts with SD */
 };
@@ -54,28 +67,131 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx6q-arm2 {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
                        >;
                };
-        };
-        arm2 {
+                pinctrl_enet: enetgrp {
-                pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
+                                MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
+                        >;
+                };
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                                MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D26__UART2_RX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D27__UART2_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B     0x1b0b1
+                                MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B     0x1b0b1
+                        >;
+                };
+                pinctrl_uart4: uart4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                                MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
+                                MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
+                                MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
+                                MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
+                        >;
+                };
+                pinctrl_usdhc3_cdwp: usdhc3cdwp {
                        fsl,pins = <
                                MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
                                MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
                        >;
                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                                MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
+                                MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
+                                MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
+                                MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
+                        >;
+                };
        };
 };
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_2>;
+        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii";
+        interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+                              <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
        status = "okay";
 };
@@ -84,8 +200,8 @@
        wp-gpios = <&gpio6 14 0>;
        vmmc-supply = <&reg_3p3v>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_1
+        pinctrl-0 = <&pinctrl_usdhc3
-                     &pinctrl_usdhc3_arm2>;
+                     &pinctrl_usdhc3_cdwp>;
        status = "okay";
 };
@@ -93,13 +209,13 @@
        non-removable;
        vmmc-supply = <&reg_3p3v>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc4_1>;
+        pinctrl-0 = <&pinctrl_usdhc4>;
        status = "okay";
 };
 &uart2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2_2>;
+        pinctrl-0 = <&pinctrl_uart2>;
        fsl,dte-mode;
        fsl,uart-has-rtscts;
        status = "okay";
@@ -107,6 +223,6 @@
 &uart4 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart4_1>;
+        pinctrl-0 = <&pinctrl_uart4>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
new file mode 100644
index 000000000000..99b46f8030ad
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2013 CompuLab Ltd.
+ *
+ * Author: Valentin Raevsky <valentin@compulab.co.il>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+/ {
+        model = "CompuLab CM-FX6";
+        compatible = "compulab,cm-fx6", "fsl,imx6q";
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+        leds {
+                compatible = "gpio-leds";
+                heartbeat-led {
+                        label = "Heartbeat";
+                        gpios = <&gpio2 31 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        status = "okay";
+};
+&iomuxc {
+        imx6q-cm-fx6 {
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                                MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
+                        >;
+                };
+                pinctrl_uart4: uart4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
+                        >;
+                };
+        };
+};
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
new file mode 100644
index 000000000000..fd0ad9a8866c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __DTS_V1__
+#define __DTS_V1__
+/dts-v1/;
+#endif
+#include "imx6q.dtsi"
+#include "imx6qdl-dfi-fs700-m60.dtsi"
+/ {
+        model = "DFI FS700-M60-6QD i.MX6qd Q7 Board";
+        compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
new file mode 100644
index 000000000000..a63bbb3d46bb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -0,0 +1,372 @@
+/*
+ * Copyright 2013 Data Modul AG
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6q.dtsi"
+/ {
+        model = "Data Modul eDM-QMX6 Board";
+        compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
+        aliases {
+                gpio7 = &stmpe_gpio;
+        };
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_3p3v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_usb_otg_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio7 12 0>;
+                };
+                reg_usb_host1: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usb_host1_en";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 31 0>;
+                        enable-active-high;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                led-blue {
+                        label = "blue";
+                        gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+                led-green {
+                        label = "green";
+                        gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>;
+                };
+                led-pink {
+                        label = "pink";
+                        gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>;
+                };
+                led-red {
+                        label = "red";
+                        gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 0>;
+        phy-supply = <&vgen2_1v2_eth>;
+        status = "okay";
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2
+                     &pinctrl_stmpe>;
+        status = "okay";
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <20 8>;
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-always-on;
+                        };
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                                regulator-always-on;
+                        };
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen2_1v2_eth: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vdd_high_in: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+        stmpe: stmpe1601@40 {
+                compatible = "st,stmpe1601";
+                reg = <0x40>;
+                interrupts = <30 0>;
+                interrupt-parent = <&gpio3>;
+                stmpe_gpio: stmpe_gpio {
+                        #gpio-cells = <2>;
+                        compatible = "st,stmpe-gpio";
+                };
+        };
+        temp1: ad7414@4c {
+                compatible = "ad,ad7414";
+                reg = <0x4c>;
+        };
+        temp2: ad7414@4d {
+                compatible = "ad,ad7414";
+                reg = <0x4d>;
+        };
+        rtc: m41t62@68 {
+                compatible = "stm,m41t62";
+                reg = <0x68>;
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6q-dmo-edmqmx6 {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
+                                MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_stmpe: stmpegrp {
+                        fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                                MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
+                                MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
+                                MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
+                                MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
+                        >;
+                };
+        };
+};
+&sata {
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&usbh1 {
+        vbus-supply = <&reg_usb_host1>;
+        disable-over-current;
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        vmmc-supply = <&reg_3p3v>;
+        non-removable;
+        bus-width = <8>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts
new file mode 100644
index 000000000000..4a9b4dc9afc0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2013 Philipp Zabel
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+/ {
+        model = "Zealz GK802";
+        compatible = "zealz,imx6q-gk802", "fsl,imx6q";
+        chosen {
+                linux,stdout-path = &uart4;
+        };
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_3p3v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                recovery-button {
+                        label = "recovery";
+                        gpios = <&gpio3 16 1>;
+                        linux,code = <0x198>; /* KEY_RESTART */
+                        gpio-key,wakeup;
+                };
+        };
+};
+/* Internal I2C */
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        clock-frequency = <100000>;
+        status = "okay";
+        /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */
+        eeprom: dm2016@51 {
+                compatible = "sdmc,dm2016";
+                reg = <0x51>;
+        };
+};
+/* External I2C via HDMI */
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        clock-frequency = <100000>;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6q-gk802 {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                /* Recovery button, active-low */
+                                MX6QDL_PAD_EIM_D16__GPIO3_IO16  0x100b1
+                                /* RTL8192CU enable GPIO, active-low */
+                                MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_16__I2C3_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_uart4: uart4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                        >;
+                };
+        };
+};
+&uart2 {
+        status = "okay";
+};
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4>;
+        status = "okay";
+};
+/* External USB-A port (USBOTG) */
+&usbotg {
+        disable-over-current;
+        status = "okay";
+};
+/* Internal USB port (USBH1), connected to RTL8192CU */
+&usbh1 {
+        disable-over-current;
+        status = "okay";
+};
+/* External microSD */
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        bus-width = <4>;
+        cd-gpios = <&gpio6 11 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+/* Internal microSD */
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <4>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/imx6q-gw51xx.dts
new file mode 100644
index 000000000000..af4929aee075
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw51xx.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw54xx.dtsi"
+/ {
+        model = "Gateworks Ventana i.MX6 Quad GW51XX";
+        compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/imx6q-gw52xx.dts
new file mode 100644
index 000000000000..5f71ddbc7f05
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw52xx.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw52xx.dtsi"
+/ {
+        model = "Gateworks Ventana i.MX6 Quad GW52XX";
+        compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
+};
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/imx6q-gw53xx.dts
new file mode 100644
index 000000000000..360c316b4740
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw53xx.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw53xx.dtsi"
+/ {
+        model = "Gateworks Ventana i.MX6 Quad GW53XX";
+        compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
+};
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
new file mode 100644
index 000000000000..902f98310481
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -0,0 +1,546 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+/ {
+        model = "Gateworks Ventana GW5400-A";
+        compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q";
+        /* these are used by bootloader for disabling nodes */
+        aliases {
+                ethernet0 = &fec;
+                ethernet1 = &eth1;
+                i2c0 = &i2c1;
+                i2c1 = &i2c2;
+                i2c2 = &i2c3;
+                led0 = &led0;
+                led1 = &led1;
+                led2 = &led2;
+                sky2 = &eth1;
+                ssi0 = &ssi1;
+                spi0 = &ecspi1;
+                usb0 = &usbh1;
+                usb1 = &usbotg;
+                usdhc2 = &usdhc3;
+        };
+        chosen {
+                bootargs = "console=ttymxc1,115200";
+        };
+        leds {
+                compatible = "gpio-leds";
+                led0: user1 {
+                        label = "user1";
+                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led1: user2 {
+                        label = "user2";
+                        gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */
+                        default-state = "off";
+                };
+                led2: user3 {
+                        label = "user3";
+                        gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
+                        default-state = "off";
+                };
+        };
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+        pps {
+                compatible = "pps-gpio";
+                gpios = <&gpio1 5 0>;
+                status = "okay";
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_1p0v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "1P0V";
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                        regulator-always-on;
+                };
+                reg_3p3v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_usb_h1_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usb_h1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                reg_usb_otg_vbus: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+        sound {
+                compatible = "fsl,imx6q-sabrelite-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx6q-sabrelite-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <4>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&ecspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio3 19 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        status = "okay";
+        flash: m25p80@0 {
+                compatible = "sst,w25q256";
+                spi-max-frequency = <30000000>;
+                reg = <0>;
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio1 30 0>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        eeprom1: eeprom@50 {
+                compatible = "atmel,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+        eeprom2: eeprom@51 {
+                compatible = "atmel,24c02";
+                reg = <0x51>;
+                pagesize = <16>;
+        };
+        eeprom3: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+                pagesize = <16>;
+        };
+        eeprom4: eeprom@53 {
+                compatible = "atmel,24c02";
+                reg = <0x53>;
+                pagesize = <16>;
+        };
+        gpio: pca9555@23 {
+                compatible = "nxp,pca9555";
+                reg = <0x23>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        hwmon: gsc@29 {
+                compatible = "gw,gsp";
+                reg = <0x29>;
+        };
+        rtc: ds1672@68 {
+                compatible = "dallas,ds1672";
+                reg = <0x68>;
+        };
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+        pciswitch: pex8609@3f {
+                compatible = "plx,pex8609";
+                reg = <0x3f>;
+        };
+        pciclkgen: si52147@6b {
+                compatible = "sil,si52147";
+                reg = <0x6b>;
+        };
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        accelerometer: mma8450@1c {
+                compatible = "fsl,mma8450";
+                reg = <0x1c>;
+        };
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 201>;
+                VDDA-supply = <&sw4_reg>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+        hdmiin: adv7611@4c {
+                compatible = "adi,adv7611";
+                reg = <0x4c>;
+        };
+        touchscreen: egalax_ts@04 {
+                compatible = "eeti,egalax_ts";
+                reg = <0x04>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <12 2>; /* gpio7_12 active low */
+                wakeup-gpios = <&gpio7 12 0>;
+        };
+        videoout: adv7393@2a {
+                compatible = "adi,adv7393";
+                reg = <0x2a>;
+        };
+        videoin: adv7180@20 {
+                compatible = "adi,adv7180";
+                reg = <0x20>;
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6q-gw5400-a {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22    0x80000000 /* OTG_PWR_EN */
+                                MX6QDL_PAD_EIM_D19__GPIO3_IO19    0x80000000 /* SPINOR_CS0# */
+                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x80000000 /* PCIE RST */
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1      0x000130b0 /* AUD4_MCK */
+                                MX6QDL_PAD_GPIO_5__GPIO1_IO05     0x80000000 /* GPS_PPS */
+                                MX6QDL_PAD_GPIO_17__GPIO7_IO12    0x80000000 /* TOUCH_IRQ# */
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x80000000 /* user1 led */
+                                MX6QDL_PAD_KEY_COL2__GPIO4_IO10   0x80000000 /* user2 led */
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x80000000 /* user3 led */
+                                MX6QDL_PAD_SD1_DAT0__GPIO1_IO16   0x80000000 /* USBHUB_RST# */
+                                MX6QDL_PAD_SD1_DAT3__GPIO1_IO21   0x80000000 /* MIPI_DIO */
+                         >;
+                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
+                                MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
+                                MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
+                                MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
+                                MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
+                                MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+        };
+};
+&ldb {
+        status = "okay";
+        lvds-channel@0 {
+                crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+        };
+};
+&pcie {
+        reset-gpio = <&gpio1 29 0>;
+        status = "okay";
+        eth1: sky2@8 { /* MAC/PHY on bus 8 */
+                compatible = "marvell,sky2";
+        };
+};
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts
new file mode 100644
index 000000000000..ab518d66a75e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw54xx.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw54xx.dtsi"
+/ {
+        model = "Gateworks Ventana i.MX6 Quad GW54XX";
+        compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
+};
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/imx6q-nitrogen6x.dts
new file mode 100644
index 000000000000..a57866b2e97e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-nitrogen6x.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2013 Boundary Devices, Inc.
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-nitrogen6x.dtsi"
+/ {
+        model = "Freescale i.MX6 Quad Nitrogen6x Board";
+        compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q";
+};
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
index 7d37ec60d58d..5607c331fca8 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
@@ -21,10 +21,26 @@
        status = "okay";
 };
+&gpmi {
+        status = "okay";
+};
+&sata {
+        status = "okay";
+};
 &uart4 {
        status = "okay";
 };
+&usbh1 {
+        status = "okay";
+};
+&usbotg {
+        status = "okay";
+};
 &usdhc2 {
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index 1a3b50d4d8fa..324f1550976b 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -18,11 +18,35 @@
        memory {
                reg = <0x10000000 0x80000000>;
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_usb_otg_vbus: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio4 15 0>;
+                };
+                reg_usb_h1_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_h1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 0 0>;
+                };
+        };
 };
 &ecspi3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi3_1>;
+        pinctrl-0 = <&pinctrl_ecspi3>;
        status = "okay";
        fsl,spi-num-chipselects = <1>;
        cs-gpios = <&gpio4 24 0>;
@@ -36,7 +60,7 @@
 &i2c1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1_1>;
+        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";
        eeprom@50 {
@@ -128,7 +152,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx6q-phytec-pfla02 {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
@@ -136,10 +160,109 @@
                                MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
                        >;
                };
-        };
-        pfla02 {
+                pinctrl_ecspi3: ecspi3grp {
-                pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
+                                MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
+                                MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
+                        >;
+                };
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                                MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_uart4: uart4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbh1: usbh1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_0__USB_H1_PWR           0x80000000
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                                MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x80000000
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+                pinctrl_usdhc3_cdwp: usdhc3cdwp {
                        fsl,pins = <
                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
@@ -150,21 +273,43 @@
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_3>;
+        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii";
        phy-reset-gpios = <&gpio3 23 0>;
        status = "disabled";
 };
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        status = "disabled";
+};
 &uart4 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart4_1>;
+        pinctrl-0 = <&pinctrl_uart4>;
+        status = "disabled";
+};
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh1>;
+        status = "disabled";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
        status = "disabled";
 };
 &usdhc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2_2>;
+        pinctrl-0 = <&pinctrl_usdhc2>;
        cd-gpios = <&gpio1 4 0>;
        wp-gpios = <&gpio1 2 0>;
        status = "disabled";
@@ -172,8 +317,8 @@
 &usdhc3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_2
+        pinctrl-0 = <&pinctrl_usdhc3
-                     &pinctrl_usdhc3_pfla02>;
+                     &pinctrl_usdhc3_cdwp>;
        cd-gpios = <&gpio1 27 0>;
        wp-gpios = <&gpio1 29 0>;
        status = "disabled";
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
index 97ed0816a6e0..9fc6120a1853 100644
--- a/arch/arm/boot/dts/imx6q-pinfunc.h
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -673,6 +673,7 @@
 #define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
 #define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__ENET_IRQ                 0x230 0x600 0x03c 0x11 0xff000609
 #define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
 #define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
@@ -1024,6 +1025,7 @@
 #define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x34c 0x734 0x000 0x6 0x0
 #define MX6QDL_PAD_SD1_CLK__SD1_CLK                 0x350 0x738 0x000 0x0 0x0
 #define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK             0x350 0x738 0x828 0x1 0x0
+#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT          0x350 0x738 0x000 0x2 0x0
 #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN               0x350 0x738 0x000 0x3 0x0
 #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20              0x350 0x738 0x000 0x5 0x0
 #define MX6QDL_PAD_SD2_CLK__SD2_CLK                 0x354 0x73c 0x000 0x0 0x0
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index f004913f7d80..96e4688be77c 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -12,189 +12,13 @@
 /dts-v1/;
 #include "imx6q.dtsi"
+#include "imx6qdl-sabrelite.dtsi"
 / {
        model = "Freescale i.MX6 Quad SABRE Lite Board";
        compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
-        memory {
-                reg = <0x10000000 0x40000000>;
-        };
-        regulators {
-                compatible = "simple-bus";
-                reg_2p5v: 2p5v {
-                        compatible = "regulator-fixed";
-                        regulator-name = "2P5V";
-                        regulator-min-microvolt = <2500000>;
-                        regulator-max-microvolt = <2500000>;
-                        regulator-always-on;
-                };
-                reg_3p3v: 3p3v {
-                        compatible = "regulator-fixed";
-                        regulator-name = "3P3V";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                };
-                reg_usb_otg_vbus: usb_otg_vbus {
-                        compatible = "regulator-fixed";
-                        regulator-name = "usb_otg_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio3 22 0>;
-                        enable-active-high;
-                };
-        };
-        sound {
-                compatible = "fsl,imx6q-sabrelite-sgtl5000",
-                             "fsl,imx-audio-sgtl5000";
-                model = "imx6q-sabrelite-sgtl5000";
-                ssi-controller = <&ssi1>;
-                audio-codec = <&codec>;
-                audio-routing =
-                        "MIC_IN", "Mic Jack",
-                        "Mic Jack", "Mic Bias",
-                        "Headphone Jack", "HP_OUT";
-                mux-int-port = <1>;
-                mux-ext-port = <4>;
-        };
-};
-&audmux {
-        status = "okay";
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux_1>;
-};
-&ecspi1 {
-        fsl,spi-num-chipselects = <1>;
-        cs-gpios = <&gpio3 19 0>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_1>;
-        status = "okay";
-        flash: m25p80@0 {
-                compatible = "sst,sst25vf016b";
-                spi-max-frequency = <20000000>;
-                reg = <0>;
-        };
-};
-&fec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_1>;
-        phy-mode = "rgmii";
-        phy-reset-gpios = <&gpio3 23 0>;
-        status = "okay";
-};
-&i2c1 {
-        status = "okay";
-        clock-frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1_1>;
-        codec: sgtl5000@0a {
-                compatible = "fsl,sgtl5000";
-                reg = <0x0a>;
-                clocks = <&clks 201>;
-                VDDA-supply = <&reg_2p5v>;
-                VDDIO-supply = <&reg_3p3v>;
-        };
-};
-&iomuxc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
-        hog {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
-                                MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
-                                MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x80000000
-                                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
-                                MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x80000000
-                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
-                                MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
-                                MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x80000000
-                                MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x80000000
-                        >;
-                };
-        };
-};
-&ldb {
-        status = "okay";
-        lvds-channel@0 {
-                fsl,data-mapping = "spwg";
-                fsl,data-width = <18>;
-                status = "okay";
-                display-timings {
-                        native-mode = <&timing0>;
-                        timing0: hsd100pxn1 {
-                                clock-frequency = <65000000>;
-                                hactive = <1024>;
-                                vactive = <768>;
-                                hback-porch = <220>;
-                                hfront-porch = <40>;
-                                vback-porch = <21>;
-                                vfront-porch = <7>;
-                                hsync-len = <60>;
-                                vsync-len = <10>;
-                        };
-                };
-        };
 };
 &sata {
        status = "okay";
 };
-&ssi1 {
-        fsl,mode = "i2s-slave";
-        status = "okay";
-};
-&uart2 {
-        status = "okay";
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2_1>;
-};
-&usbh1 {
-        status = "okay";
-};
-&usbotg {
-        vbus-supply = <&reg_usb_otg_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg_1>;
-        disable-over-current;
-        status = "okay";
-};
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_2>;
-        cd-gpios = <&gpio7 0 0>;
-        wp-gpios = <&gpio7 1 0>;
-        vmmc-supply = <&reg_3p3v>;
-        status = "okay";
-};
-&usdhc4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc4_2>;
-        cd-gpios = <&gpio2 6 0>;
-        wp-gpios = <&gpio2 7 0>;
-        vmmc-supply = <&reg_3p3v>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
index ee6addf149af..86cf09364664 100644
--- a/arch/arm/boot/dts/imx6q-sbc6x.dts
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -17,28 +17,78 @@
        };
 };
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_1>;
+        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii";
        status = "okay";
 };
+&iomuxc {
+        imx6q-sbc6x {
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
+                                MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+        };
+};
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 &usbotg {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg_1>;
+        pinctrl-0 = <&pinctrl_usbotg>;
        disable-over-current;
        status = "okay";
 };
 &usdhc3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_2>;
+        pinctrl-0 = <&pinctrl_usdhc3>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
index 6e1ccdc019a7..ed397d149ab6 100644
--- a/arch/arm/boot/dts/imx6q-udoo.dts
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -21,19 +21,69 @@
        };
 };
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+&iomuxc {
+        imx6q-udoo {
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+        };
+};
 &sata {
        status = "okay";
 };
 &uart2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2_1>;
+        pinctrl-0 = <&pinctrl_uart2>;
        status = "okay";
 };
 &usdhc3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_2>;
+        pinctrl-0 = <&pinctrl_usdhc3>;
        non-removable;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index f024ef28b34b..addd3f881ce2 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -8,10 +8,15 @@
 *
 */
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "imx6q-pinfunc.h"
 #include "imx6qdl.dtsi"
 / {
+        aliases {
+                spi4 = &ecspi5;
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -25,8 +30,17 @@
                                /* kHz    uV */
                                1200000 1275000
                                996000  1250000
+                                852000  1250000
                                792000  1150000
-                                396000  950000
+                                396000  975000
+                        >;
+                        fsl,soc-operating-points = <
+                                /* ARM kHz  SOC-PU uV */
+                                1200000 1275000
+                                996000  1250000
+                                852000  1250000
+                                792000  1175000
+                                396000  1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clks 104>, <&clks 6>, <&clks 16>,
@@ -74,7 +88,7 @@
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02018000 0x4000>;
-                                        interrupts = <0 35 0x04>;
+                                        interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks 116>, <&clks 116>;
                                        clock-names = "ipg", "per";
                                        status = "disabled";
@@ -125,20 +139,92 @@
                sata: sata@02200000 {
                        compatible = "fsl,imx6q-ahci";
                        reg = <0x02200000 0x4000>;
-                        interrupts = <0 39 0x04>;
+                        interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
                        clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
                        clock-names = "sata", "sata_ref", "ahb";
                        status = "disabled";
                };
                ipu2: ipu@02800000 {
-                        #crtc-cells = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                        compatible = "fsl,imx6q-ipu";
                        reg = <0x02800000 0x400000>;
-                        interrupts = <0 8 0x4 0 7 0x4>;
+                        interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
+                                     <0 7 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clks 133>, <&clks 134>, <&clks 137>;
                        clock-names = "bus", "di0", "di1";
                        resets = <&src 4>;
+                        ipu2_di0: port@2 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <2>;
+                                ipu2_di0_disp0: endpoint@0 {
+                                };
+                                ipu2_di0_hdmi: endpoint@1 {
+                                        remote-endpoint = <&hdmi_mux_2>;
+                                };
+                                ipu2_di0_mipi: endpoint@2 {
+                                };
+                                ipu2_di0_lvds0: endpoint@3 {
+                                        remote-endpoint = <&lvds0_mux_2>;
+                                };
+                                ipu2_di0_lvds1: endpoint@4 {
+                                        remote-endpoint = <&lvds1_mux_2>;
+                                };
+                        };
+                        ipu2_di1: port@3 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <3>;
+                                ipu2_di1_hdmi: endpoint@1 {
+                                        remote-endpoint = <&hdmi_mux_3>;
+                                };
+                                ipu2_di1_mipi: endpoint@2 {
+                                };
+                                ipu2_di1_lvds0: endpoint@3 {
+                                        remote-endpoint = <&lvds0_mux_3>;
+                                };
+                                ipu2_di1_lvds1: endpoint@4 {
+                                        remote-endpoint = <&lvds1_mux_3>;
+                                };
+                        };
+                };
+        };
+        display-subsystem {
+                compatible = "fsl,imx-display-subsystem";
+                ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
+        };
+};
+&hdmi {
+        compatible = "fsl,imx6q-hdmi";
+        port@2 {
+                reg = <2>;
+                hdmi_mux_2: endpoint {
+                        remote-endpoint = <&ipu2_di0_hdmi>;
+                };
+        };
+        port@3 {
+                reg = <3>;
+                hdmi_mux_3: endpoint {
+                        remote-endpoint = <&ipu2_di1_hdmi>;
                };
        };
 };
@@ -152,10 +238,56 @@
                      "di0", "di1";
        lvds-channel@0 {
-                crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+                port@2 {
+                        reg = <2>;
+                        lvds0_mux_2: endpoint {
+                                remote-endpoint = <&ipu2_di0_lvds0>;
+                        };
+                };
+                port@3 {
+                        reg = <3>;
+                        lvds0_mux_3: endpoint {
+                                remote-endpoint = <&ipu2_di1_lvds0>;
+                        };
+                };
        };
        lvds-channel@1 {
-                crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+                port@2 {
+                        reg = <2>;
+                        lvds1_mux_2: endpoint {
+                                remote-endpoint = <&ipu2_di0_lvds1>;
+                        };
+                };
+                port@3 {
+                        reg = <3>;
+                        lvds1_mux_3: endpoint {
+                                remote-endpoint = <&ipu2_di1_lvds1>;
+                        };
+                };
+        };
+};
+&mipi_dsi {
+        port@2 {
+                reg = <2>;
+                mipi_mux_2: endpoint {
+                        remote-endpoint = <&ipu2_di0_mipi>;
+                };
+        };
+        port@3 {
+                reg = <3>;
+                mipi_mux_3: endpoint {
+                        remote-endpoint = <&ipu2_di1_mipi>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
new file mode 100644
index 000000000000..25cf035dd36e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -0,0 +1,199 @@
+/ {
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                dummy_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "dummy-supply";
+                };
+                reg_usb_otg_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+        chosen {
+                linux,stdout-path = &uart1;
+        };
+};
+&ecspi3 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 24 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi3>;
+        status = "okay";
+        flash: m25p80@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "sst,sst25vf040b", "m25p80";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        status = "okay";
+        phy-mode = "rgmii";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6qdl-dfi-fs700-m60 {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
+                                MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */
+                                MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */
+                                MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
+                                MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
+                                MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                                MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
+                                MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
+                                MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
+                                MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
+                        >;
+                };
+                pinctrl_ecspi3: ecspi3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
+                                MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
+                                MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
+                                MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
+                        >;
+                };
+        };
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&usbh1 {
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        dr_mode = "host";
+        status = "okay";
+};
+&usdhc2 { /* module slot */
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        cd-gpios = <&gpio2 2 0>;
+        status = "okay";
+};
+&usdhc3 { /* baseboard slot */
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+};
+&usdhc4 { /* eMMC */
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
new file mode 100644
index 000000000000..98a422153ce7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -0,0 +1,374 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/ {
+        /* these are used by bootloader for disabling nodes */
+        aliases {
+                can0 = &can1;
+                ethernet0 = &fec;
+                led0 = &led0;
+                led1 = &led1;
+                nand = &gpmi;
+                usb0 = &usbh1;
+                usb1 = &usbotg;
+        };
+        chosen {
+                bootargs = "console=ttymxc1,115200";
+        };
+        leds {
+                compatible = "gpio-leds";
+                led0: user1 {
+                        label = "user1";
+                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led1: user2 {
+                        label = "user2";
+                        gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
+                        default-state = "off";
+                };
+        };
+        memory {
+                reg = <0x10000000 0x20000000>;
+        };
+        pps {
+                compatible = "pps-gpio";
+                gpios = <&gpio1 26 0>;
+                status = "okay";
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_3p3v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_5p0v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "5P0V";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                reg_usb_otg_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio1 30 0>;
+        status = "okay";
+};
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        eeprom1: eeprom@50 {
+                compatible = "atmel,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+        eeprom2: eeprom@51 {
+                compatible = "atmel,24c02";
+                reg = <0x51>;
+                pagesize = <16>;
+        };
+        eeprom3: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+                pagesize = <16>;
+        };
+        eeprom4: eeprom@53 {
+                compatible = "atmel,24c02";
+                reg = <0x53>;
+                pagesize = <16>;
+        };
+        gpio: pca9555@23 {
+                compatible = "nxp,pca9555";
+                reg = <0x23>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        hwmon: gsc@29 {
+                compatible = "gw,gsp";
+                reg = <0x29>;
+        };
+        rtc: ds1672@68 {
+                compatible = "dallas,ds1672";
+                reg = <0x68>;
+        };
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        pmic: ltc3676@3c {
+                compatible = "ltc,ltc3676";
+                reg = <0x3c>;
+                regulators {
+                        sw1_reg: ltc3676__sw1 {
+                                regulator-min-microvolt = <1175000>;
+                                regulator-max-microvolt = <1175000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw2_reg: ltc3676__sw2 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3_reg: ltc3676__sw3 {
+                                regulator-min-microvolt = <1175000>;
+                                regulator-max-microvolt = <1175000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: ltc3676__sw4 {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        ldo2_reg: ltc3676__ldo2 {
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        ldo4_reg: ltc3676__ldo4 {
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                };
+        };
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        videoin: adv7180@20 {
+                compatible = "adi,adv7180";
+                reg = <0x20>;
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6qdl-gw51xx {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
+                                MX6QDL_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
+                                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
+                                MX6QDL_PAD_GPIO_0__GPIO1_IO00    0x80000000 /* PCIE_RST# */
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
+                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
+                         >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                        >;
+                };
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        >;
+                };
+        };
+};
+&pcie {
+        reset-gpio = <&gpio1 0 0>;
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+&usbh1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
new file mode 100644
index 000000000000..8e99c9a9bc76
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -0,0 +1,490 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/ {
+        /* these are used by bootloader for disabling nodes */
+        aliases {
+                ethernet0 = &fec;
+                led0 = &led0;
+                led1 = &led1;
+                led2 = &led2;
+                nand = &gpmi;
+                ssi0 = &ssi1;
+                usb0 = &usbh1;
+                usb1 = &usbotg;
+                usdhc2 = &usdhc3;
+        };
+        chosen {
+                bootargs = "console=ttymxc1,115200";
+        };
+        leds {
+                compatible = "gpio-leds";
+                led0: user1 {
+                        label = "user1";
+                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led1: user2 {
+                        label = "user2";
+                        gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
+                        default-state = "off";
+                };
+                led2: user3 {
+                        label = "user3";
+                        gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */
+                        default-state = "off";
+                };
+        };
+        memory {
+                reg = <0x10000000 0x20000000>;
+        };
+        pps {
+                compatible = "pps-gpio";
+                gpios = <&gpio1 26 0>;
+                status = "okay";
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_1p0v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "1P0V";
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                        regulator-always-on;
+                };
+                /* remove this fixed regulator once ltc3676__sw2 driver available */
+                reg_1p8v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "1P8V";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+                reg_3p3v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_5p0v: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "5P0V";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                reg_usb_otg_vbus: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+        sound {
+                compatible = "fsl,imx6q-sabrelite-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx6q-sabrelite-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <4>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio1 30 0>;
+        status = "okay";
+};
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        eeprom1: eeprom@50 {
+                compatible = "atmel,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+        eeprom2: eeprom@51 {
+                compatible = "atmel,24c02";
+                reg = <0x51>;
+                pagesize = <16>;
+        };
+        eeprom3: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+                pagesize = <16>;
+        };
+        eeprom4: eeprom@53 {
+                compatible = "atmel,24c02";
+                reg = <0x53>;
+                pagesize = <16>;
+        };
+        gpio: pca9555@23 {
+                compatible = "nxp,pca9555";
+                reg = <0x23>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        hwmon: gsc@29 {
+                compatible = "gw,gsp";
+                reg = <0x29>;
+        };
+        rtc: ds1672@68 {
+                compatible = "dallas,ds1672";
+                reg = <0x68>;
+        };
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        pciswitch: pex8609@3f {
+                compatible = "plx,pex8609";
+                reg = <0x3f>;
+        };
+        pmic: ltc3676@3c {
+                compatible = "ltc,ltc3676";
+                reg = <0x3c>;
+                regulators {
+                        sw1_reg: ltc3676__sw1 {
+                                regulator-min-microvolt = <1175000>;
+                                regulator-max-microvolt = <1175000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw2_reg: ltc3676__sw2 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3_reg: ltc3676__sw3 {
+                                regulator-min-microvolt = <1175000>;
+                                regulator-max-microvolt = <1175000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: ltc3676__sw4 {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        ldo2_reg: ltc3676__ldo2 {
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        ldo3_reg: ltc3676__ldo3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        ldo4_reg: ltc3676__ldo4 {
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                };
+        };
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        accelerometer: fxos8700@1e {
+                compatible = "fsl,fxos8700";
+                reg = <0x13>;
+        };
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 169>;
+                VDDA-supply = <&reg_1p8v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+        touchscreen: egalax_ts@04 {
+                compatible = "eeti,egalax_ts";
+                reg = <0x04>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <12 2>; /* gpio7_12 active low */
+                wakeup-gpios = <&gpio7 12 0>;
+        };
+        videoin: adv7180@20 {
+                compatible = "adi,adv7180";
+                reg = <0x20>;
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6qdl-gw52xx {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_A19__GPIO2_IO19   0x80000000 /* MEZZ_DIO0 */
+                                MX6QDL_PAD_EIM_A20__GPIO2_IO18   0x80000000 /* MEZZ_DIO1 */
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22   0x80000000 /* OTG_PWR_EN */
+                                MX6QDL_PAD_EIM_D31__GPIO3_IO31   0x80000000 /* VIDDEC_PDN# */
+                                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */
+                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1     0x000130b0 /* AUD4_MCK */
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02    0x80000000 /* USB_SEL_PCI */
+                                MX6QDL_PAD_GPIO_17__GPIO7_IO12   0x80000000 /* TOUCH_IRQ# */
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x80000000 /* user1 led */
+                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x80000000 /* user2 led */
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x80000000 /* user3 led */
+                                MX6QDL_PAD_SD2_CMD__GPIO1_IO11   0x80000000 /* LVDS_TCH# */
+                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00  0x80000000 /* SD3_CD# */
+                                MX6QDL_PAD_SD4_DAT3__GPIO2_IO11  0x80000000 /* UART2_EN# */
+                         >;
+                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
+                                MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
+                                MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
+                                MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+        };
+};
+&ldb {
+        status = "okay";
+        lvds-channel@0 {
+                crtcs = <&ipu1 0>, <&ipu1 1>;
+        };
+};
+&pcie {
+        reset-gpio = <&gpio1 29 0>;
+        status = "okay";
+};
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+&usbh1 {
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
new file mode 100644
index 000000000000..c8e5ae06deaf
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -0,0 +1,553 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/ {
+        /* these are used by bootloader for disabling nodes */
+        aliases {
+                can0 = &can1;
+                ethernet0 = &fec;
+                ethernet1 = &eth1;
+                led0 = &led0;
+                led1 = &led1;
+                led2 = &led2;
+                nand = &gpmi;
+                sky2 = &eth1;
+                ssi0 = &ssi1;
+                usb0 = &usbh1;
+                usb1 = &usbotg;
+                usdhc2 = &usdhc3;
+        };
+        chosen {
+                bootargs = "console=ttymxc1,115200";
+        };
+        leds {
+                compatible = "gpio-leds";
+                led0: user1 {
+                        label = "user1";
+                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led1: user2 {
+                        label = "user2";
+                        gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
+                        default-state = "off";
+                };
+                led2: user3 {
+                        label = "user3";
+                        gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
+                        default-state = "off";
+                };
+        };
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+        pps {
+                compatible = "pps-gpio";
+                gpios = <&gpio1 26 0>;
+                status = "okay";
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_1p0v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "1P0V";
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                        regulator-always-on;
+                };
+                /* remove when pmic 1p8 regulator available */
+                reg_1p8v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "1P8V";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+                reg_3p3v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_usb_h1_vbus: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "usb_h1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                reg_usb_otg_vbus: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+        sound {
+                compatible = "fsl,imx6q-sabrelite-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx6q-sabrelite-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <4>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan1>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio1 30 0>;
+        status = "okay";
+};
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        eeprom1: eeprom@50 {
+                compatible = "atmel,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+        eeprom2: eeprom@51 {
+                compatible = "atmel,24c02";
+                reg = <0x51>;
+                pagesize = <16>;
+        };
+        eeprom3: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+                pagesize = <16>;
+        };
+        eeprom4: eeprom@53 {
+                compatible = "atmel,24c02";
+                reg = <0x53>;
+                pagesize = <16>;
+        };
+        gpio: pca9555@23 {
+                compatible = "nxp,pca9555";
+                reg = <0x23>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        hwmon: gsc@29 {
+                compatible = "gw,gsp";
+                reg = <0x29>;
+        };
+        rtc: ds1672@68 {
+                compatible = "dallas,ds1672";
+                reg = <0x68>;
+        };
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        pciclkgen: si53156@6b {
+                compatible = "sil,si53156";
+                reg = <0x6b>;
+        };
+        pciswitch: pex8606@3f {
+                compatible = "plx,pex8606";
+                reg = <0x3f>;
+        };
+        pmic: ltc3676@3c {
+                compatible = "ltc,ltc3676";
+                reg = <0x3c>;
+                regulators {
+                        /* VDD_SOC */
+                        sw1_reg: ltc3676__sw1 {
+                                regulator-min-microvolt = <1175000>;
+                                regulator-max-microvolt = <1175000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        /* VDD_1P8 */
+                        sw2_reg: ltc3676__sw2 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        /* VDD_ARM */
+                        sw3_reg: ltc3676__sw3 {
+                                regulator-min-microvolt = <1175000>;
+                                regulator-max-microvolt = <1175000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        /* VDD_DDR */
+                        sw4_reg: ltc3676__sw4 {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        /* VDD_2P5 */
+                        ldo2_reg: ltc3676__ldo2 {
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        /* VDD_1P8 */
+                        ldo3_reg: ltc3676__ldo3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        /* VDD_HIGH */
+                        ldo4_reg: ltc3676__ldo4 {
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                };
+        };
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        accelerometer: fxos8700@1e {
+                compatible = "fsl,fxos8700";
+                reg = <0x1e>;
+        };
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 201>;
+                VDDA-supply = <&reg_1p8v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+        hdmiin: adv7611@4c {
+                compatible = "adi,adv7611";
+                reg = <0x4c>;
+        };
+        touchscreen: egalax_ts@04 {
+                compatible = "eeti,egalax_ts";
+                reg = <0x04>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <11 2>; /* gpio1_11 active low */
+                wakeup-gpios = <&gpio1 11 0>;
+        };
+        videoout: adv7393@2a {
+                compatible = "adi,adv7393";
+                reg = <0x2a>;
+        };
+        videoin: adv7180@20 {
+                compatible = "adi,adv7180";
+                reg = <0x20>;
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6qdl-gw53xx {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_A19__GPIO2_IO19    0x80000000 /* PCIE6EXP_DIO0 */
+                                MX6QDL_PAD_EIM_A20__GPIO2_IO18    0x80000000 /* PCIE6EXP_DIO1 */
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22    0x80000000 /* OTG_PWR_EN */
+                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27  0x80000000 /* GPS_SHDN */
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26  0x80000000 /* GPS_PPS */
+                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x80000000 /* PCIE RST */
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1      0x000130b0 /* AUD4_MCK */
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02     0x80000000 /* CAN_STBY */
+                                MX6QDL_PAD_GPIO_8__GPIO1_IO08     0x80000000 /* PMIC_IRQ# */
+                                MX6QDL_PAD_GPIO_9__GPIO1_IO09     0x80000000 /* HUB_RST# */
+                                MX6QDL_PAD_GPIO_17__GPIO7_IO12    0x80000000 /* PCIE_WDIS# */
+                                MX6QDL_PAD_GPIO_19__GPIO4_IO05    0x80000000 /* ACCEL_IRQ# */
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x80000000 /* user1 led */
+                                MX6QDL_PAD_KEY_COL4__GPIO4_IO14   0x80000000 /* USBOTG_OC# */
+                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x80000000 /* user2 led */
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x80000000 /* user3 led */
+                                MX6QDL_PAD_SD2_CMD__GPIO1_IO11    0x80000000 /* TOUCH_IRQ# */
+                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00   0x80000000 /* SD3_DET# */
+                         >;
+                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
+                                MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
+                                MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
+                                MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_flexcan1: flexcan1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x80000000
+                                MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x80000000
+                        >;
+                };
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+        };
+};
+&ldb {
+        status = "okay";
+        lvds-channel@1 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
+        };
+};
+&pcie {
+        reset-gpio = <&gpio1 29 0>;
+        status = "okay";
+        eth1: sky2@8 { /* MAC/PHY on bus 8 */
+                compatible = "marvell,sky2";
+        };
+};
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
new file mode 100644
index 000000000000..2795dfc8c926
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -0,0 +1,580 @@
+/*
+ * Copyright 2013 Gateworks Corporation
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/ {
+        /* these are used by bootloader for disabling nodes */
+        aliases {
+                can0 = &can1;
+                ethernet0 = &fec;
+                ethernet1 = &eth1;
+                led0 = &led0;
+                led1 = &led1;
+                led2 = &led2;
+                nand = &gpmi;
+                sky2 = &eth1;
+                ssi0 = &ssi1;
+                usb0 = &usbh1;
+                usb1 = &usbotg;
+                usdhc2 = &usdhc3;
+        };
+        chosen {
+                bootargs = "console=ttymxc1,115200";
+        };
+        leds {
+                compatible = "gpio-leds";
+                led0: user1 {
+                        label = "user1";
+                        gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led1: user2 {
+                        label = "user2";
+                        gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
+                        default-state = "off";
+                };
+                led2: user3 {
+                        label = "user3";
+                        gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
+                        default-state = "off";
+                };
+        };
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+        pps {
+                compatible = "pps-gpio";
+                gpios = <&gpio1 26 0>;
+                status = "okay";
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_1p0v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "1P0V";
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                        regulator-always-on;
+                };
+                reg_3p3v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_usb_h1_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usb_h1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                reg_usb_otg_vbus: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+        sound {
+                compatible = "fsl,imx6q-sabrelite-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx6q-sabrelite-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <4>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
+        status = "okay";
+};
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan1>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio1 30 0>;
+        status = "okay";
+};
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        eeprom1: eeprom@50 {
+                compatible = "atmel,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+        eeprom2: eeprom@51 {
+                compatible = "atmel,24c02";
+                reg = <0x51>;
+                pagesize = <16>;
+        };
+        eeprom3: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+                pagesize = <16>;
+        };
+        eeprom4: eeprom@53 {
+                compatible = "atmel,24c02";
+                reg = <0x53>;
+                pagesize = <16>;
+        };
+        gpio: pca9555@23 {
+                compatible = "nxp,pca9555";
+                reg = <0x23>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        hwmon: gsc@29 {
+                compatible = "gw,gsp";
+                reg = <0x29>;
+        };
+        rtc: ds1672@68 {
+                compatible = "dallas,ds1672";
+                reg = <0x68>;
+        };
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+        pciswitch: pex8609@3f {
+                compatible = "plx,pex8609";
+                reg = <0x3f>;
+        };
+        pciclkgen: si52147@6b {
+                compatible = "sil,si52147";
+                reg = <0x6b>;
+        };
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        accelerometer: fxos8700@1e {
+                compatible = "fsl,fxos8700";
+                reg = <0x1e>;
+        };
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 201>;
+                VDDA-supply = <&sw4_reg>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+        hdmiin: adv7611@4c {
+                compatible = "adi,adv7611";
+                reg = <0x4c>;
+        };
+        touchscreen: egalax_ts@04 {
+                compatible = "eeti,egalax_ts";
+                reg = <0x04>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <12 2>; /* gpio7_12 active low */
+                wakeup-gpios = <&gpio7 12 0>;
+        };
+        videoout: adv7393@2a {
+                compatible = "adi,adv7393";
+                reg = <0x2a>;
+        };
+        videoin: adv7180@20 {
+                compatible = "adi,adv7180";
+                reg = <0x20>;
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6qdl-gw54xx {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22    0x80000000 /* OTG_PWR_EN */
+                                MX6QDL_PAD_EIM_D19__GPIO3_IO19    0x80000000 /* SPINOR_CS0# */
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26  0x80000000 /* GPS_PPS */
+                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x80000000 /* PCIE RST */
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1      0x000130b0 /* AUD4_MCK */
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02     0x80000000 /* CAN_STBY */
+                                MX6QDL_PAD_GPIO_17__GPIO7_IO12    0x80000000 /* TOUCH_IRQ# */
+                                MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x80000000 /* user1 led */
+                                MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x80000000 /* user2 led */
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x80000000 /* user3 led */
+                                MX6QDL_PAD_SD1_DAT0__GPIO1_IO16   0x80000000 /* USBHUB_RST# */
+                                MX6QDL_PAD_SD1_DAT3__GPIO1_IO21   0x80000000 /* MIPI_DIO */
+                         >;
+                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
+                                MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
+                                MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
+                                MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_flexcan1: flexcan1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x80000000
+                                MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x80000000
+                        >;
+                };
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+        };
+};
+&ldb {
+        status = "okay";
+        lvds-channel@1 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
+        };
+};
+&pcie {
+        reset-gpio = <&gpio1 29 0>;
+        status = "okay";
+        eth1: sky2@8 { /* MAC/PHY on bus 8 */
+                compatible = "marvell,sky2";
+        };
+};
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
new file mode 100644
index 000000000000..99be301b5232
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -0,0 +1,422 @@
+/*
+ * Copyright 2013 Boundary Devices, Inc.
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+/ {
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_2p5v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "2P5V";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                        regulator-always-on;
+                };
+                reg_3p3v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_usb_otg_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
+                power {
+                        label = "Power Button";
+                        gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+                menu {
+                        label = "Menu";
+                        gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_MENU>;
+                };
+                home {
+                        label = "Home";
+                        gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_HOME>;
+                };
+                back {
+                        label = "Back";
+                        gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_BACK>;
+                };
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEUP>;
+                };
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEDOWN>;
+                };
+        };
+        sound {
+                compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx6q-nitrogen6x-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <3>;
+        };
+        backlight_lcd {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+                power-supply = <&reg_3p3v>;
+                status = "okay";
+        };
+        backlight_lvds {
+                compatible = "pwm-backlight";
+                pwms = <&pwm4 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+                power-supply = <&reg_3p3v>;
+                status = "okay";
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&ecspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio3 19 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        status = "okay";
+        flash: m25p80@0 {
+                compatible = "sst,sst25vf016b";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio1 27 0>;
+        txen-skew-ps = <0>;
+        txc-skew-ps = <3000>;
+        rxdv-skew-ps = <0>;
+        rxc-skew-ps = <3000>;
+        rxd0-skew-ps = <0>;
+        rxd1-skew-ps = <0>;
+        rxd2-skew-ps = <0>;
+        rxd3-skew-ps = <0>;
+        txd0-skew-ps = <0>;
+        txd1-skew-ps = <0>;
+        txd2-skew-ps = <0>;
+        txd3-skew-ps = <0>;
+        interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+                              <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 201>;
+                VDDA-supply = <&reg_2p5v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6q-nitrogen6x {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                /* SGTL5000 sys_mclk */
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x030b0
+                        >;
+                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
+                                MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
+                                MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
+                                MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
+                                MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
+                                MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                                MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x000b1 /* CS */
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                /* Phy reset */
+                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x000b0
+                                MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
+                        >;
+                };
+                pinctrl_gpio_keys: gpio_keysgrp {
+                        fsl,pins = <
+                                /* Power Button */
+                                MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x1b0b0
+                                /* Menu Button */
+                                MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
+                                /* Home Button */
+                                MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x1b0b0
+                                /* Back Button */
+                                MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x1b0b0
+                                /* Volume Up Button */
+                                MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
+                                /* Volume Down Button */
+                                MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_pwm1: pwm1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+                        >;
+                };
+                pinctrl_pwm3: pwm3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
+                        >;
+                };
+                pinctrl_pwm4: pwm4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID   0x17059
+                                MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
+                                /* power enable, high active */
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x000b0
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
+                        >;
+                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                                MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
+                        >;
+                };
+        };
+};
+&ldb {
+        status = "okay";
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
+        };
+};
+&pcie {
+        status = "okay";
+};
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "okay";
+};
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&usbh1 {
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        cd-gpios = <&gpio2 6 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index ff6f1e8f2dd9..009abd69385d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -10,17 +10,46 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
+#include <dt-bindings/gpio/gpio.h>
 / {
        memory {
                reg = <0x10000000 0x80000000>;
        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
+                user {
+                        label = "debug";
+                        gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        sound-spdif {
+                compatible = "fsl,imx-audio-spdif",
+                           "fsl,imx-sabreauto-spdif";
+                model = "imx-spdif";
+                spdif-controller = <&spdif>;
+                spdif-in;
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm3 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+                status = "okay";
+        };
 };
 &ecspi1 {
        fsl,spi-num-chipselects = <1>;
        cs-gpios = <&gpio3 19 0>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
+        pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
        status = "disabled"; /* pin conflict with WEIM NOR */
        flash: m25p80@0 {
@@ -34,22 +63,130 @@
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_2>;
+        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii";
+        interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+                              <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
        status = "okay";
 };
 &gpmi {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        status = "okay";
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
 };
 &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx6qdl-sabreauto {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
@@ -57,28 +194,245 @@
                                MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
                        >;
                };
-        };
-        ecspi1 {
+                pinctrl_ecspi1: ecspi1grp {
-                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
+                                MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
+                                MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                        >;
+                };
+                pinctrl_ecspi1_cs: ecspi1cs {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
                        >;
                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
+                                MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
+                        >;
+                };
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
+                        >;
+                };
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                                MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
+                        >;
+                };
+                pinctrl_pwm3: pwm1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
+                        >;
+                };
+                pinctrl_spdif: spdifgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
+                        >;
+                };
+                pinctrl_uart4: uart4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                                MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
+                                MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
+                                MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
+                                MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
+                        >;
+                };
+                pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
+                                MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
+                                MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
+                                MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
+                                MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
+                        >;
+                };
+                pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
+                                MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
+                                MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
+                                MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
+                                MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
+                        >;
+                };
+                pinctrl_weim_cs0: weimcs0grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
+                        >;
+                };
+                pinctrl_weim_nor: weimnorgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
+                                MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
+                                MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
+                                MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
+                                MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
+                                MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
+                                MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
+                                MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
+                                MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
+                                MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
+                                MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
+                                MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
+                                MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
+                                MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
+                                MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
+                                MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
+                                MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
+                                MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
+                                MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
+                                MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
+                                MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
+                                MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
+                                MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
+                                MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
+                                MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
+                                MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
+                                MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
+                                MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
+                                MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
+                                MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
+                                MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
+                                MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
+                                MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
+                                MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
+                                MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
+                                MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
+                                MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
+                                MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
+                                MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
+                                MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
+                                MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
+                                MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
+                                MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
+                        >;
+                };
+        };
+};
+&ldb {
+        status = "okay";
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
        };
 };
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "okay";
+};
+&spdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spdif>;
+        status = "okay";
+};
 &uart4 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart4_1>;
+        pinctrl-0 = <&pinctrl_uart4>;
        status = "okay";
 };
 &usdhc3 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
-        pinctrl-0 = <&pinctrl_usdhc3_1>;
+        pinctrl-0 = <&pinctrl_usdhc3>;
-        pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-        pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
        cd-gpios = <&gpio6 15 0>;
        wp-gpios = <&gpio1 13 0>;
        status = "okay";
@@ -86,7 +440,7 @@
 &weim {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
+        pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
        #address-cells = <2>;
        #size-cells = <1>;
        ranges = <0 0 0x08000000 0x08000000>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
new file mode 100644
index 000000000000..3bec128c7971
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -0,0 +1,423 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+/ {
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_2p5v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "2P5V";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                        regulator-always-on;
+                };
+                reg_3p3v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_usb_otg_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
+                power {
+                        label = "Power Button";
+                        gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+                menu {
+                        label = "Menu";
+                        gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_MENU>;
+                };
+                home {
+                        label = "Home";
+                        gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_HOME>;
+                };
+                back {
+                        label = "Back";
+                        gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_BACK>;
+                };
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEUP>;
+                };
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEDOWN>;
+                };
+        };
+        sound {
+                compatible = "fsl,imx6q-sabrelite-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx6q-sabrelite-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <4>;
+        };
+        backlight_lcd {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+                power-supply = <&reg_3p3v>;
+                status = "okay";
+        };
+        backlight_lvds {
+                compatible = "pwm-backlight";
+                pwms = <&pwm4 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+                power-supply = <&reg_3p3v>;
+                status = "okay";
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&ecspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio3 19 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        status = "okay";
+        flash: m25p80@0 {
+                compatible = "sst,sst25vf016b";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+        txen-skew-ps = <0>;
+        txc-skew-ps = <3000>;
+        rxdv-skew-ps = <0>;
+        rxc-skew-ps = <3000>;
+        rxd0-skew-ps = <0>;
+        rxd1-skew-ps = <0>;
+        rxd2-skew-ps = <0>;
+        rxd3-skew-ps = <0>;
+        txd0-skew-ps = <0>;
+        txd1-skew-ps = <0>;
+        txd2-skew-ps = <0>;
+        txd3-skew-ps = <0>;
+        interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+                              <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 201>;
+                VDDA-supply = <&reg_2p5v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6q-sabrelite {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                /* SGTL5000 sys_mclk */
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x030b0
+                        >;
+                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
+                                MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
+                                MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
+                                MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
+                                MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
+                                MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                                MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x000b1 /* CS */
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                /* Phy reset */
+                                MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x000b0
+                                MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
+                        >;
+                };
+                pinctrl_gpio_keys: gpio_keysgrp {
+                        fsl,pins = <
+                                /* Power Button */
+                                MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x1b0b0
+                                /* Menu Button */
+                                MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
+                                /* Home Button */
+                                MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x1b0b0
+                                /* Back Button */
+                                MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x1b0b0
+                                /* Volume Up Button */
+                                MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
+                                /* Volume Down Button */
+                                MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_pwm1: pwm1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+                        >;
+                };
+                pinctrl_pwm3: pwm3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
+                        >;
+                };
+                pinctrl_pwm4: pwm4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                                MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
+                                /* power enable, high active */
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x000b0
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
+                                MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
+                        >;
+                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                                MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
+                        >;
+                };
+        };
+};
+&ldb {
+        status = "okay";
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
+        };
+};
+&pcie {
+        status = "okay";
+};
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "okay";
+};
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&usbh1 {
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 0>;
+        wp-gpios = <&gpio7 1 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        cd-gpios = <&gpio2 6 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index e75e11b36dff..0d816d3be4b6 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -10,6 +10,9 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 / {
        memory {
                reg = <0x10000000 0x40000000>;
@@ -17,9 +20,12 @@
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb_otg_vbus: usb_otg_vbus {
+                reg_usb_otg_vbus: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "usb_otg_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
@@ -27,8 +33,9 @@
                        enable-active-high;
                };
-                reg_usb_h1_vbus: usb_h1_vbus {
+                reg_usb_h1_vbus: regulator@1 {
                        compatible = "regulator-fixed";
+                        reg = <1>;
                        regulator-name = "usb_h1_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
@@ -36,8 +43,9 @@
                        enable-active-high;
                };
-                reg_audio: wm8962_supply {
+                reg_audio: regulator@2 {
                        compatible = "regulator-fixed";
+                        reg = <2>;
                        regulator-name = "wm8962-supply";
                        gpio = <&gpio4 10 0>;
                        enable-active-high;
@@ -46,19 +54,28 @@
        gpio-keys {
                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
+                power {
+                        label = "Power Button";
+                        gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+                        gpio-key,wakeup;
+                        linux,code = <KEY_POWER>;
+                };
                volume-up {
                        label = "Volume Up";
-                        gpios = <&gpio1 4 0>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
                        gpio-key,wakeup;
-                        linux,code = <115>; /* KEY_VOLUMEUP */
+                        linux,code = <KEY_VOLUMEUP>;
                };
                volume-down {
                        label = "Volume Down";
-                        gpios = <&gpio1 5 0>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
                        gpio-key,wakeup;
-                        linux,code = <114>; /* KEY_VOLUMEDOWN */
+                        linux,code = <KEY_VOLUMEDOWN>;
                };
        };
@@ -92,7 +109,7 @@
 &audmux {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux_2>;
+        pinctrl-0 = <&pinctrl_audmux>;
        status = "okay";
 };
@@ -100,7 +117,7 @@
        fsl,spi-num-chipselects = <1>;
        cs-gpios = <&gpio4 9 0>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_2>;
+        pinctrl-0 = <&pinctrl_ecspi1>;
        status = "okay";
        flash: m25p80@0 {
@@ -114,7 +131,7 @@
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_1>;
+        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii";
        phy-reset-gpios = <&gpio1 25 0>;
        status = "okay";
@@ -123,7 +140,7 @@
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1_2>;
+        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";
        codec: wm8962@1a {
@@ -149,10 +166,116 @@
       };
 };
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
 &i2c3 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c3_2>;
+        pinctrl-0 = <&pinctrl_i2c3>;
        status = "okay";
        egalax_ts@04 {
@@ -168,11 +291,9 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx6qdl-sabresd {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
-                                MX6QDL_PAD_GPIO_4__GPIO1_IO04   0x80000000
-                                MX6QDL_PAD_GPIO_5__GPIO1_IO05   0x80000000
                                MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
                                MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
                                MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
@@ -184,6 +305,122 @@
                                MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
                        >;
                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
+                                MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
+                                MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
+                                MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
+                                MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
+                                MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        >;
+                };
+                pinctrl_gpio_keys: gpio_keysgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x80000000
+                                MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x80000000
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
+                                MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        >;
+                };
+                pinctrl_pwm1: pwm1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
+                                MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
+                                MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
+                                MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
+                                MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
+                                MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                                MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
+                                MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
+                                MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
+                                MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
+                        >;
+                };
        };
 };
@@ -214,7 +451,7 @@
 &pwm1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm0_1>;
+        pinctrl-0 = <&pinctrl_pwm1>;
        status = "okay";
 };
@@ -225,7 +462,7 @@
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
@@ -237,14 +474,14 @@
 &usbotg {
        vbus-supply = <&reg_usb_otg_vbus>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg_2>;
+        pinctrl-0 = <&pinctrl_usbotg>;
        disable-over-current;
        status = "okay";
 };
 &usdhc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2_1>;
+        pinctrl-0 = <&pinctrl_usdhc2>;
        bus-width = <8>;
        cd-gpios = <&gpio2 2 0>;
        wp-gpios = <&gpio2 3 0>;
@@ -253,7 +490,7 @@
 &usdhc3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_1>;
+        pinctrl-0 = <&pinctrl_usdhc3>;
        bus-width = <8>;
        cd-gpios = <&gpio2 0 0>;
        wp-gpios = <&gpio2 1 0>;
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 35f547929167..bdfdf89d405f 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -12,17 +12,21 @@
 / {
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_2p5v: 2p5v {
+                reg_2p5v: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "2P5V";
                        regulator-min-microvolt = <2500000>;
                        regulator-max-microvolt = <2500000>;
                        regulator-always-on;
                };
-                reg_3p3v: 3p3v {
+                reg_3p3v: regulator@1 {
                        compatible = "regulator-fixed";
+                        reg = <1>;
                        regulator-name = "3P3V";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
@@ -54,14 +58,14 @@
 &audmux {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux_2>;
+        pinctrl-0 = <&pinctrl_audmux>;
        status = "okay";
 };
 &i2c2 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2_2>;
+        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
        codec: sgtl5000@0a {
@@ -77,7 +81,7 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx6qdl-wandboard {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX6QDL_PAD_GPIO_0__CCM_CLKO1     0x130b0
@@ -91,20 +95,121 @@
                                MX6QDL_PAD_EIM_D29__GPIO3_IO29   0x80000000
                        >;
                };
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
+                                MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
+                                MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
+                                MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                                MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_spdif: spdifgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RXD0__SPDIF_OUT         0x1b0b0
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
+                                MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
+                                MX6QDL_PAD_EIM_EB3__UART3_RTS_B         0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                        >;
+                };
+                pinctrl_usdhc1: usdhc1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_CMD__SD1_CMD             0x17059
+                                MX6QDL_PAD_SD1_CLK__SD1_CLK             0x10059
+                                MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x17059
+                                MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x17059
+                                MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x17059
+                                MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x17059
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
        };
 };
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_1>;
+        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii";
        phy-reset-gpios = <&gpio3 29 0>;
+        interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+                              <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
        status = "okay";
 };
 &spdif {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_spdif_3>;
+        pinctrl-0 = <&pinctrl_spdif>;
        status = "okay";
 };
@@ -115,13 +220,13 @@
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 &uart3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart3_2>;
+        pinctrl-0 = <&pinctrl_uart3>;
        fsl,uart-has-rtscts;
        status = "okay";
 };
@@ -132,7 +237,7 @@
 &usbotg {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg_1>;
+        pinctrl-0 = <&pinctrl_usbotg>;
        disable-over-current;
        dr_mode = "peripheral";
        status = "okay";
@@ -140,21 +245,21 @@
 &usdhc1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc1_2>;
+        pinctrl-0 = <&pinctrl_usdhc1>;
        cd-gpios = <&gpio1 2 0>;
        status = "okay";
 };
 &usdhc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2_2>;
+        pinctrl-0 = <&pinctrl_usdhc2>;
        non-removable;
        status = "okay";
 };
 &usdhc3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_2>;
+        pinctrl-0 = <&pinctrl_usdhc3>;
        cd-gpios = <&gpio3 9 0>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index fb28b2ecb1db..55cb926fa3f7 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -14,6 +14,8 @@
 / {
        aliases {
+                can0 = &can1;
+                can1 = &can2;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
@@ -24,6 +26,10 @@
                i2c0 = &i2c1;
                i2c1 = &i2c2;
                i2c2 = &i2c3;
+                mmc0 = &usdhc1;
+                mmc1 = &usdhc2;
+                mmc2 = &usdhc3;
+                mmc3 = &usdhc4;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
@@ -33,6 +39,8 @@
                spi1 = &ecspi2;
                spi2 = &ecspi3;
                spi3 = &ecspi4;
+                usbphy0 = &usbphy1;
+                usbphy1 = &usbphy2;
        };
        intc: interrupt-controller@00a01000 {
@@ -75,7 +83,10 @@
                dma_apbh: dma-apbh@00110000 {
                        compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
                        reg = <0x00110000 0x2000>;
-                        interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
+                        interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <0 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <0 13 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
                        #dma-cells = <1>;
                        dma-channels = <4>;
@@ -88,7 +99,7 @@
                        #size-cells = <1>;
                        reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
                        reg-names = "gpmi-nand", "bch";
-                        interrupts = <0 15 0x04>;
+                        interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "bch";
                        clocks = <&clks 152>, <&clks 153>, <&clks 151>,
                                 <&clks 150>, <&clks 149>;
@@ -109,7 +120,7 @@
                L2: l2-cache@00a02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0x00a02000 0x1000>;
-                        interrupts = <0 92 0x04>;
+                        interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
                        cache-unified;
                        cache-level = <2>;
                        arm,tag-latency = <4 2 3>;
@@ -126,7 +137,7 @@
                                  0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
                                  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
                        num-lanes = <1>;
-                        interrupts = <0 123 0x04>;
+                        interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
                        clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
                        status = "disabled";
@@ -134,7 +145,7 @@
                pmu {
                        compatible = "arm,cortex-a9-pmu";
-                        interrupts = <0 94 0x04>;
+                        interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
                };
                aips-bus@02000000 { /* AIPS1 */
@@ -154,7 +165,7 @@
                                spdif: spdif@02004000 {
                                        compatible = "fsl,imx35-spdif";
                                        reg = <0x02004000 0x4000>;
-                                        interrupts = <0 52 0x04>;
+                                        interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
                                        dmas = <&sdma 14 18 0>,
                                               <&sdma 15 18 0>;
                                        dma-names = "rx", "tx";
@@ -176,9 +187,11 @@
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02008000 0x4000>;
-                                        interrupts = <0 31 0x04>;
+                                        interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks 112>, <&clks 112>;
                                        clock-names = "ipg", "per";
+                                        dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
+                                        dma-names = "rx", "tx";
                                        status = "disabled";
                                };
@@ -187,9 +200,11 @@
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x0200c000 0x4000>;
-                                        interrupts = <0 32 0x04>;
+                                        interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks 113>, <&clks 113>;
                                        clock-names = "ipg", "per";
+                                        dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
+                                        dma-names = "rx", "tx";
                                        status = "disabled";
                                };
@@ -198,9 +213,11 @@
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02010000 0x4000>;
-                                        interrupts = <0 33 0x04>;
+                                        interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks 114>, <&clks 114>;
                                        clock-names = "ipg", "per";
+                                        dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
+                                        dma-names = "rx", "tx";
                                        status = "disabled";
                                };
@@ -209,16 +226,18 @@
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02014000 0x4000>;
-                                        interrupts = <0 34 0x04>;
+                                        interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks 115>, <&clks 115>;
                                        clock-names = "ipg", "per";
+                                        dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
+                                        dma-names = "rx", "tx";
                                        status = "disabled";
                                };
                                uart1: serial@02020000 {
                                        compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02020000 0x4000>;
-                                        interrupts = <0 26 0x04>;
+                                        interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks 160>, <&clks 161>;
                                        clock-names = "ipg", "per";
                                        dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
@@ -228,13 +247,15 @@
                                esai: esai@02024000 {
                                        reg = <0x02024000 0x4000>;
-                                        interrupts = <0 51 0x04>;
+                                        interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
                                };
                                ssi1: ssi@02028000 {
-                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+                                        compatible = "fsl,imx6q-ssi",
+                                                        "fsl,imx51-ssi",
+                                                        "fsl,imx21-ssi";
                                        reg = <0x02028000 0x4000>;
-                                        interrupts = <0 46 0x04>;
+                                        interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks 178>;
                                        dmas = <&sdma 37 1 0>,
                                               <&sdma 38 1 0>;
@@ -245,9 +266,11 @@
                                };
                                ssi2: ssi@0202c000 {
-                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+                                        compatible = "fsl,imx6q-ssi",
+                                                        "fsl,imx51-ssi",
+                                                        "fsl,imx21-ssi";
                                        reg = <0x0202c000 0x4000>;
-                                        interrupts = <0 47 0x04>;
+                                        interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks 179>;
                                        dmas = <&sdma 41 1 0>,
                                               <&sdma 42 1 0>;
@@ -258,9 +281,11 @@
                                };
                                ssi3: ssi@02030000 {
-                                        compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+                                        compatible = "fsl,imx6q-ssi",
+                                                        "fsl,imx51-ssi",
+                                                        "fsl,imx21-ssi";
                                        reg = <0x02030000 0x4000>;
-                                        interrupts = <0 48 0x04>;
+                                        interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks 180>;
                                        dmas = <&sdma 45 1 0>,
                                               <&sdma 46 1 0>;
@@ -272,7 +297,7 @@
                                asrc: asrc@02034000 {
                                        reg = <0x02034000 0x4000>;
-                                        interrupts = <0 50 0x04>;
+                                        interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
                                };
                                spba@0203c000 {
@@ -282,7 +307,8 @@
                        vpu: vpu@02040000 {
                                reg = <0x02040000 0x3c000>;
-                                interrupts = <0 3 0x04 0 12 0x04>;
+                                interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 12 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        aipstz@0207c000 { /* AIPSTZ1 */
@@ -293,7 +319,7 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                reg = <0x02080000 0x4000>;
-                                interrupts = <0 83 0x04>;
+                                interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 62>, <&clks 145>;
                                clock-names = "ipg", "per";
                        };
@@ -302,7 +328,7 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                reg = <0x02084000 0x4000>;
-                                interrupts = <0 84 0x04>;
+                                interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 62>, <&clks 146>;
                                clock-names = "ipg", "per";
                        };
@@ -311,7 +337,7 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                reg = <0x02088000 0x4000>;
-                                interrupts = <0 85 0x04>;
+                                interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 62>, <&clks 147>;
                                clock-names = "ipg", "per";
                        };
@@ -320,7 +346,7 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
                                reg = <0x0208c000 0x4000>;
-                                interrupts = <0 86 0x04>;
+                                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 62>, <&clks 148>;
                                clock-names = "ipg", "per";
                        };
@@ -328,23 +354,25 @@
                        can1: flexcan@02090000 {
                                compatible = "fsl,imx6q-flexcan";
                                reg = <0x02090000 0x4000>;
-                                interrupts = <0 110 0x04>;
+                                interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 108>, <&clks 109>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        can2: flexcan@02094000 {
                                compatible = "fsl,imx6q-flexcan";
                                reg = <0x02094000 0x4000>;
-                                interrupts = <0 111 0x04>;
+                                interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 110>, <&clks 111>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        gpt: gpt@02098000 {
                                compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
                                reg = <0x02098000 0x4000>;
-                                interrupts = <0 55 0x04>;
+                                interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 119>, <&clks 120>;
                                clock-names = "ipg", "per";
                        };
@@ -352,7 +380,8 @@
                        gpio1: gpio@0209c000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                reg = <0x0209c000 0x4000>;
-                                interrupts = <0 66 0x04 0 67 0x04>;
+                                interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 67 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -362,7 +391,8 @@
                        gpio2: gpio@020a0000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                reg = <0x020a0000 0x4000>;
-                                interrupts = <0 68 0x04 0 69 0x04>;
+                                interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 69 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -372,7 +402,8 @@
                        gpio3: gpio@020a4000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                reg = <0x020a4000 0x4000>;
-                                interrupts = <0 70 0x04 0 71 0x04>;
+                                interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 71 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -382,7 +413,8 @@
                        gpio4: gpio@020a8000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                reg = <0x020a8000 0x4000>;
-                                interrupts = <0 72 0x04 0 73 0x04>;
+                                interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 73 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -392,7 +424,8 @@
                        gpio5: gpio@020ac000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                reg = <0x020ac000 0x4000>;
-                                interrupts = <0 74 0x04 0 75 0x04>;
+                                interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 75 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -402,7 +435,8 @@
                        gpio6: gpio@020b0000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                reg = <0x020b0000 0x4000>;
-                                interrupts = <0 76 0x04 0 77 0x04>;
+                                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 77 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -412,7 +446,8 @@
                        gpio7: gpio@020b4000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                reg = <0x020b4000 0x4000>;
-                                interrupts = <0 78 0x04 0 79 0x04>;
+                                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 79 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -421,20 +456,20 @@
                        kpp: kpp@020b8000 {
                                reg = <0x020b8000 0x4000>;
-                                interrupts = <0 82 0x04>;
+                                interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        wdog1: wdog@020bc000 {
                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                reg = <0x020bc000 0x4000>;
-                                interrupts = <0 80 0x04>;
+                                interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 0>;
                        };
                        wdog2: wdog@020c0000 {
                                compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                reg = <0x020c0000 0x4000>;
-                                interrupts = <0 81 0x04>;
+                                interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 0>;
                                status = "disabled";
                        };
@@ -442,14 +477,17 @@
                        clks: ccm@020c4000 {
                                compatible = "fsl,imx6q-ccm";
                                reg = <0x020c4000 0x4000>;
-                                interrupts = <0 87 0x04 0 88 0x04>;
+                                interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 88 IRQ_TYPE_LEVEL_HIGH>;
                                #clock-cells = <1>;
                        };
                        anatop: anatop@020c8000 {
                                compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
                                reg = <0x020c8000 0x1000>;
-                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+                                interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 54 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 127 IRQ_TYPE_LEVEL_HIGH>;
                                regulator-1p1@110 {
                                        compatible = "fsl,anatop-regulator";
@@ -495,7 +533,7 @@
                                reg_arm: regulator-vddcore@140 {
                                        compatible = "fsl,anatop-regulator";
-                                        regulator-name = "cpu";
+                                        regulator-name = "vddarm";
                                        regulator-min-microvolt = <725000>;
                                        regulator-max-microvolt = <1450000>;
                                        regulator-always-on;
@@ -547,23 +585,26 @@
                        tempmon: tempmon {
                                compatible = "fsl,imx6q-tempmon";
-                                interrupts = <0 49 0x04>;
+                                interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
                                fsl,tempmon = <&anatop>;
                                fsl,tempmon-data = <&ocotp>;
+                                clocks = <&clks 172>;
                        };
                        usbphy1: usbphy@020c9000 {
                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                reg = <0x020c9000 0x1000>;
-                                interrupts = <0 44 0x04>;
+                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 182>;
+                                fsl,anatop = <&anatop>;
                        };
                        usbphy2: usbphy@020ca000 {
                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                reg = <0x020ca000 0x1000>;
-                                interrupts = <0 45 0x04>;
+                                interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 183>;
+                                fsl,anatop = <&anatop>;
                        };
                        snvs@020cc000 {
@@ -575,31 +616,34 @@
                                snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
-                                        interrupts = <0 19 0x04 0 20 0x04>;
+                                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
+                                                     <0 20 IRQ_TYPE_LEVEL_HIGH>;
                                };
                        };
                        epit1: epit@020d0000 { /* EPIT1 */
                                reg = <0x020d0000 0x4000>;
-                                interrupts = <0 56 0x04>;
+                                interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        epit2: epit@020d4000 { /* EPIT2 */
                                reg = <0x020d4000 0x4000>;
-                                interrupts = <0 57 0x04>;
+                                interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        src: src@020d8000 {
                                compatible = "fsl,imx6q-src", "fsl,imx51-src";
                                reg = <0x020d8000 0x4000>;
-                                interrupts = <0 91 0x04 0 96 0x04>;
+                                interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 96 IRQ_TYPE_LEVEL_HIGH>;
                                #reset-cells = <1>;
                        };
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
-                                interrupts = <0 89 0x04 0 90 0x04>;
+                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 90 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        gpr: iomuxc-gpr@020e0000 {
@@ -610,778 +654,103 @@
                        iomuxc: iomuxc@020e0000 {
                                compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
                                reg = <0x020e0000 0x4000>;
+                        };
-                                audmux {
+                        ldb: ldb@020e0008 {
-                                        pinctrl_audmux_1: audmux-1 {
+                                #address-cells = <1>;
-                                                fsl,pins = <
+                                #size-cells = <0>;
-                                                        MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
+                                compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
-                                                        MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
+                                gpr = <&gpr>;
-                                                        MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
+                                status = "disabled";
-                                                        MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
-                                                >;
-                                        };
-                                        pinctrl_audmux_2: audmux-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
-                                                >;
-                                        };
-                                        pinctrl_audmux_3: audmux-3 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_DISP0_DAT16__AUD5_TXC  0x80000000
-                                                        MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
-                                                        MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
-                                                >;
-                                        };
-                                };
-                                ecspi1 {
-                                        pinctrl_ecspi1_1: ecspi1grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
-                                                        MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
-                                                        MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
-                                                >;
-                                        };
-                                        pinctrl_ecspi1_2: ecspi1grp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
-                                                        MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
-                                                        MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
-                                                >;
-                                        };
-                                };
-                                ecspi3 {
-                                        pinctrl_ecspi3_1: ecspi3grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
-                                                        MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
-                                                        MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
-                                                >;
-                                        };
-                                };
-                                enet {
-                                        pinctrl_enet_1: enetgrp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
-                                                        MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-                                                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-                                                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
-                                                >;
-                                        };
-                                        pinctrl_enet_2: enetgrp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
-                                                        MX6QDL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-                                                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-                                                >;
-                                        };
-                                        pinctrl_enet_3: enetgrp-3 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
-                                                        MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-                                                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-                                                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-                                                        MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
-                                                >;
-                                        };
-                                };
-                                esai {
-                                        pinctrl_esai_1: esaigrp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
-                                                        MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK  0x1b030
-                                                        MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS     0x1b030
-                                                        MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2  0x1b030
-                                                        MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3   0x1b030
-                                                        MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1   0x1b030
-                                                        MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0    0x1b030
-                                                        MX6QDL_PAD_NANDF_CS2__ESAI_TX0       0x1b030
-                                                        MX6QDL_PAD_NANDF_CS3__ESAI_TX1       0x1b030
-                                                >;
-                                        };
-                                        pinctrl_esai_2: esaigrp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
-                                                        MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
-                                                        MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
-                                                        MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
-                                                        MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
-                                                        MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
-                                                        MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
-                                                        MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
-                                                        MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
-                                                        MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
-                                                >;
-                                        };
-                                };
-                                flexcan1 {
-                                        pinctrl_flexcan1_1: flexcan1grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
-                                                        MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
-                                                >;
-                                        };
-                                        pinctrl_flexcan1_2: flexcan1grp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
-                                                        MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
-                                                >;
-                                        };
-                                };
-                                flexcan2 {
-                                        pinctrl_flexcan2_1: flexcan2grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
-                                                        MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
-                                                >;
-                                        };
-                                };
-                                gpmi-nand {
-                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
-                                                        MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
-                                                        MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
-                                                        MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
-                                                        MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
-                                                        MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
-                                                        MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
-                                                        MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
-                                                        MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
-                                                        MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
-                                                        MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
-                                                        MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
-                                                        MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
-                                                        MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
-                                                        MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
-                                                        MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
-                                                        MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
-                                                >;
-                                        };
-                                };
-                                hdmi_hdcp {
-                                        pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
-                                                        MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                        pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
-                                                        MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                        pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL  0x4001b8b1
-                                                        MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                };
-                                hdmi_cec {
-                                        pinctrl_hdmi_cec_1: hdmicecgrp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
-                                                >;
-                                        };
-                                        pinctrl_hdmi_cec_2: hdmicecgrp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
-                                                >;
-                                        };
-                                };
-                                i2c1 {
-                                        pinctrl_i2c1_1: i2c1grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
-                                                        MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                        pinctrl_i2c1_2: i2c1grp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
-                                                        MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
-                                                >;
-                                        };
-                                };
-                                i2c2 {
-                                        pinctrl_i2c2_1: i2c2grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
-                                                        MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                        pinctrl_i2c2_2: i2c2grp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
-                                                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                        pinctrl_i2c2_3: i2c2grp-3 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
-                                                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                };
-                                i2c3 {
-                                        pinctrl_i2c3_1: i2c3grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
-                                                        MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                        pinctrl_i2c3_2: i2c3grp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
-                                                        MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                        pinctrl_i2c3_3: i2c3grp-3 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
-                                                        MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                        pinctrl_i2c3_4: i2c3grp-4 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
-                                                        MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                };
-                                ipu1 {
-                                        pinctrl_ipu1_1: ipu1grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-                                                        MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
-                                                        MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
-                                                        MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
-                                                        MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
-                                                        MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
-                                                        MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
-                                                        MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
-                                                        MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
-                                                        MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
-                                                        MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
-                                                        MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
-                                                        MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
-                                                        MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
-                                                        MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
-                                                        MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
-                                                        MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
-                                                        MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
-                                                        MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
-                                                        MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
-                                                        MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
-                                                        MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
-                                                        MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
-                                                        MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
-                                                        MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
-                                                        MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
-                                                        MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
-                                                        MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
-                                                        MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
-                                                >;
-                                        };
-                                        pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
-                                                        MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
-                                                        MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
-                                                        MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
-                                                        MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
-                                                >;
-                                        };
-                                        pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04   0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05   0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06   0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07   0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08   0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09   0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x80000000
-                                                        MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x80000000
-                                                        MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
-                                                        MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x80000000
-                                                        MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x80000000
-                                                >;
-                                        };
-                                };
-                                mlb {
-                                        pinctrl_mlb_1: mlbgrp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_GPIO_3__MLB_CLK  0x71
-                                                        MX6QDL_PAD_GPIO_6__MLB_SIG  0x71
-                                                        MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
-                                                >;
-                                        };
-                                        pinctrl_mlb_2: mlbgrp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
-                                                        MX6QDL_PAD_GPIO_6__MLB_SIG    0x71
-                                                        MX6QDL_PAD_GPIO_2__MLB_DATA   0x71
-                                                >;
-                                        };
-                                };
-                                pwm0 {
-                                        pinctrl_pwm0_1: pwm0grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
-                                                >;
-                                        };
-                                };
-                                pwm3 {
-                                        pinctrl_pwm3_1: pwm3grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
-                                                >;
-                                        };
-                                };
-                                spdif {
-                                        pinctrl_spdif_1: spdifgrp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
-                                                >;
-                                        };
-                                        pinctrl_spdif_2: spdifgrp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
-                                                        MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
-                                                >;
-                                        };
-                                        pinctrl_spdif_3: spdifgrp-3 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
-                                                >;
-                                        };
-                                };
-                                uart1 {
-                                        pinctrl_uart1_1: uart1grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
-                                                        MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
-                                                >;
-                                        };
-                                };
-                                uart2 {
-                                        pinctrl_uart2_1: uart2grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
-                                                        MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
-                                                >;
-                                        };
-                                        pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_D26__UART2_RX_DATA   0x1b0b1
-                                                        MX6QDL_PAD_EIM_D27__UART2_TX_DATA   0x1b0b1
-                                                        MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
-                                                        MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
-                                                >;
-                                        };
-                                };
-                                uart3 {
-                                        pinctrl_uart3_1: uart3grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
-                                                        MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
-                                                        MX6QDL_PAD_EIM_D30__UART3_CTS_B   0x1b0b1
-                                                        MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
-                                                >;
-                                        };
-                                        pinctrl_uart3_2: uart3grp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
-                                                        MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
-                                                        MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
-                                                        MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
-                                                >;
-                                        };
-                                };
-                                uart4 {
-                                        pinctrl_uart4_1: uart4grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
-                                                        MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
-                                                >;
-                                        };
-                                };
-                                usbotg {
-                                        pinctrl_usbotg_1: usbotggrp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usbotg_2: usbotggrp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
-                                                >;
-                                        };
-                                };
-                                usbh2 {
-                                        pinctrl_usbh2_1: usbh2grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_RGMII_TXC__USB_H2_DATA      0x40013030
-                                                        MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
-                                                >;
-                                        };
-                                        pinctrl_usbh2_2: usbh2grp-2 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
-                                                >;
-                                        };
-                                };
-                                usbh3 {
-                                        pinctrl_usbh3_1: usbh3grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
-                                                        MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE  0x40013030
-                                                >;
-                                        };
-                                        pinctrl_usbh3_2: usbh3grp-2 {
+                                lvds-channel@0 {
-                                                fsl,pins = <
+                                        #address-cells = <1>;
-                                                        MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
+                                        #size-cells = <0>;
-                                                >;
+                                        reg = <0>;
-                                        };
+                                        status = "disabled";
-                                };
-                                usdhc1 {
+                                        port@0 {
-                                        pinctrl_usdhc1_1: usdhc1grp-1 {
+                                                reg = <0>;
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
-                                                        MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
-                                                        MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
-                                                        MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
-                                                        MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
-                                                        MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
-                                                        MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
-                                                        MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
-                                                        MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
-                                                        MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usdhc1_2: usdhc1grp-2 {
+                                                lvds0_mux_0: endpoint {
-                                                fsl,pins = <
+                                                        remote-endpoint = <&ipu1_di0_lvds0>;
-                                                        MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
+                                                };
-                                                        MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
-                                                        MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
-                                                        MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
-                                                        MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
-                                                        MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
-                                                >;
                                        };
-                                };
-                                usdhc2 {
+                                        port@1 {
-                                        pinctrl_usdhc2_1: usdhc2grp-1 {
+                                                reg = <1>;
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
-                                                        MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
-                                                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
-                                                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
-                                                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
-                                                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
-                                                        MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
-                                                        MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
-                                                        MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
-                                                        MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usdhc2_2: usdhc2grp-2 {
+                                                lvds0_mux_1: endpoint {
-                                                fsl,pins = <
+                                                        remote-endpoint = <&ipu1_di1_lvds0>;
-                                                        MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                };
-                                                        MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
-                                                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
-                                                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
-                                                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
-                                                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
-                                                >;
                                        };
                                };
-                                usdhc3 {
+                                lvds-channel@1 {
-                                        pinctrl_usdhc3_1: usdhc3grp-1 {
+                                        #address-cells = <1>;
-                                                fsl,pins = <
+                                        #size-cells = <0>;
-                                                        MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                        reg = <1>;
-                                                        MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
+                                        status = "disabled";
-                                                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
-                                                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
-                                                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
-                                                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
-                                                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
-                                                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
-                                                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
-                                                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
-                                                        MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
-                                                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
-                                                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
-                                                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
-                                                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
-                                                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
-                                                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
-                                                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
-                                                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
-                                                >;
-                                        };
-                                        pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
+                                        port@0 {
-                                                fsl,pins = <
+                                                reg = <0>;
-                                                        MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
-                                                        MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
-                                                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
-                                                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
-                                                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
-                                                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
-                                                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
-                                                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
-                                                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
-                                                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
-                                                >;
-                                        };
-                                        pinctrl_usdhc3_2: usdhc3grp-2 {
+                                                lvds1_mux_0: endpoint {
-                                                fsl,pins = <
+                                                        remote-endpoint = <&ipu1_di0_lvds1>;
-                                                        MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                };
-                                                        MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
-                                                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
-                                                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
-                                                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
-                                                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
-                                                >;
                                        };
-                                };
-                                usdhc4 {
+                                        port@1 {
-                                        pinctrl_usdhc4_1: usdhc4grp-1 {
+                                                reg = <1>;
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
-                                                        MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
-                                                        MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
-                                                        MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
-                                                        MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
-                                                        MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
-                                                        MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
-                                                        MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
-                                                        MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
-                                                        MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usdhc4_2: usdhc4grp-2 {
+                                                lvds1_mux_1: endpoint {
-                                                fsl,pins = <
+                                                        remote-endpoint = <&ipu1_di1_lvds1>;
-                                                        MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
+                                                };
-                                                        MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
-                                                        MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
-                                                        MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
-                                                        MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
-                                                        MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
-                                                >;
-                                        };
-                                };
-                                weim {
-                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
-                                                >;
-                                        };
-                                        pinctrl_weim_nor_1: weim_norgrp-1 {
-                                                fsl,pins = <
-                                                        MX6QDL_PAD_EIM_OE__EIM_OE_B     0xb0b1
-                                                        MX6QDL_PAD_EIM_RW__EIM_RW       0xb0b1
-                                                        MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
-                                                        /* data */
-                                                        MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
-                                                        MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
-                                                        /* address */
-                                                        MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
-                                                        MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
-                                                        MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
-                                                        MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
-                                                        MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
-                                                        MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
-                                                        MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
-                                                        MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
-                                                        MX6QDL_PAD_EIM_DA15__EIM_AD15  0xb0b1
-                                                        MX6QDL_PAD_EIM_DA14__EIM_AD14  0xb0b1
-                                                        MX6QDL_PAD_EIM_DA13__EIM_AD13  0xb0b1
-                                                        MX6QDL_PAD_EIM_DA12__EIM_AD12  0xb0b1
-                                                        MX6QDL_PAD_EIM_DA11__EIM_AD11  0xb0b1
-                                                        MX6QDL_PAD_EIM_DA10__EIM_AD10  0xb0b1
-                                                        MX6QDL_PAD_EIM_DA9__EIM_AD09   0xb0b1
-                                                        MX6QDL_PAD_EIM_DA8__EIM_AD08   0xb0b1
-                                                        MX6QDL_PAD_EIM_DA7__EIM_AD07   0xb0b1
-                                                        MX6QDL_PAD_EIM_DA6__EIM_AD06   0xb0b1
-                                                        MX6QDL_PAD_EIM_DA5__EIM_AD05   0xb0b1
-                                                        MX6QDL_PAD_EIM_DA4__EIM_AD04   0xb0b1
-                                                        MX6QDL_PAD_EIM_DA3__EIM_AD03   0xb0b1
-                                                        MX6QDL_PAD_EIM_DA2__EIM_AD02   0xb0b1
-                                                        MX6QDL_PAD_EIM_DA1__EIM_AD01   0xb0b1
-                                                        MX6QDL_PAD_EIM_DA0__EIM_AD00   0xb0b1
-                                                >;
                                        };
                                };
                        };
-                        ldb: ldb@020e0008 {
+                        hdmi: hdmi@0120000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+                                reg = <0x00120000 0x9000>;
+                                interrupts = <0 115 0x04>;
                                gpr = <&gpr>;
+                                clocks = <&clks 123>, <&clks 124>;
+                                clock-names = "iahb", "isfr";
                                status = "disabled";
-                                lvds-channel@0 {
+                                port@0 {
                                        reg = <0>;
-                                        status = "disabled";
+                                        hdmi_mux_0: endpoint {
+                                                remote-endpoint = <&ipu1_di0_hdmi>;
+                                        };
                                };
-                                lvds-channel@1 {
+                                port@1 {
                                        reg = <1>;
-                                        status = "disabled";
+                                        hdmi_mux_1: endpoint {
+                                                remote-endpoint = <&ipu1_di1_hdmi>;
+                                        };
                                };
                        };
                        dcic1: dcic@020e4000 {
                                reg = <0x020e4000 0x4000>;
-                                interrupts = <0 124 0x04>;
+                                interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        dcic2: dcic@020e8000 {
                                reg = <0x020e8000 0x4000>;
-                                interrupts = <0 125 0x04>;
+                                interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        sdma: sdma@020ec000 {
                                compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
                                reg = <0x020ec000 0x4000>;
-                                interrupts = <0 2 0x04>;
+                                interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 155>, <&clks 155>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
@@ -1398,7 +767,8 @@
                        caam@02100000 {
                                reg = <0x02100000 0x40000>;
-                                interrupts = <0 105 0x04 0 106 0x04>;
+                                interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 106 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        aipstz@0217c000 { /* AIPSTZ2 */
@@ -1408,7 +778,7 @@
                        usbotg: usb@02184000 {
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184000 0x200>;
-                                interrupts = <0 43 0x04>;
+                                interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 162>;
                                fsl,usbphy = <&usbphy1>;
                                fsl,usbmisc = <&usbmisc 0>;
@@ -1418,7 +788,7 @@
                        usbh1: usb@02184200 {
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184200 0x200>;
-                                interrupts = <0 40 0x04>;
+                                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 162>;
                                fsl,usbphy = <&usbphy2>;
                                fsl,usbmisc = <&usbmisc 1>;
@@ -1428,7 +798,7 @@
                        usbh2: usb@02184400 {
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184400 0x200>;
-                                interrupts = <0 41 0x04>;
+                                interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 162>;
                                fsl,usbmisc = <&usbmisc 2>;
                                status = "disabled";
@@ -1437,7 +807,7 @@
                        usbh3: usb@02184600 {
                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                reg = <0x02184600 0x200>;
-                                interrupts = <0 42 0x04>;
+                                interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 162>;
                                fsl,usbmisc = <&usbmisc 3>;
                                status = "disabled";
@@ -1453,7 +823,9 @@
                        fec: ethernet@02188000 {
                                compatible = "fsl,imx6q-fec";
                                reg = <0x02188000 0x4000>;
-                                interrupts = <0 118 0x04 0 119 0x04>;
+                                interrupts-extended =
+                                        <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
+                                        <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 117>, <&clks 117>, <&clks 190>;
                                clock-names = "ipg", "ahb", "ptp";
                                status = "disabled";
@@ -1461,13 +833,15 @@
                        mlb@0218c000 {
                                reg = <0x0218c000 0x4000>;
-                                interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
+                                interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 117 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 126 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        usdhc1: usdhc@02190000 {
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x02190000 0x4000>;
-                                interrupts = <0 22 0x04>;
+                                interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 163>, <&clks 163>, <&clks 163>;
                                clock-names = "ipg", "ahb", "per";
                                bus-width = <4>;
@@ -1477,7 +851,7 @@
                        usdhc2: usdhc@02194000 {
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x02194000 0x4000>;
-                                interrupts = <0 23 0x04>;
+                                interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 164>, <&clks 164>, <&clks 164>;
                                clock-names = "ipg", "ahb", "per";
                                bus-width = <4>;
@@ -1487,7 +861,7 @@
                        usdhc3: usdhc@02198000 {
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x02198000 0x4000>;
-                                interrupts = <0 24 0x04>;
+                                interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 165>, <&clks 165>, <&clks 165>;
                                clock-names = "ipg", "ahb", "per";
                                bus-width = <4>;
@@ -1497,7 +871,7 @@
                        usdhc4: usdhc@0219c000 {
                                compatible = "fsl,imx6q-usdhc";
                                reg = <0x0219c000 0x4000>;
-                                interrupts = <0 25 0x04>;
+                                interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 166>, <&clks 166>, <&clks 166>;
                                clock-names = "ipg", "ahb", "per";
                                bus-width = <4>;
@@ -1509,7 +883,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021a0000 0x4000>;
-                                interrupts = <0 36 0x04>;
+                                interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 125>;
                                status = "disabled";
                        };
@@ -1519,7 +893,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021a4000 0x4000>;
-                                interrupts = <0 37 0x04>;
+                                interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 126>;
                                status = "disabled";
                        };
@@ -1529,7 +903,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021a8000 0x4000>;
-                                interrupts = <0 38 0x04>;
+                                interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 127>;
                                status = "disabled";
                        };
@@ -1550,7 +924,7 @@
                        weim: weim@021b8000 {
                                compatible = "fsl,imx6q-weim";
                                reg = <0x021b8000 0x4000>;
-                                interrupts = <0 14 0x04>;
+                                interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 196>;
                        };
@@ -1561,12 +935,12 @@
                        tzasc@021d0000 { /* TZASC1 */
                                reg = <0x021d0000 0x4000>;
-                                interrupts = <0 108 0x04>;
+                                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        tzasc@021d4000 { /* TZASC2 */
                                reg = <0x021d4000 0x4000>;
-                                interrupts = <0 109 0x04>;
+                                interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        audmux: audmux@021d8000 {
@@ -1575,23 +949,42 @@
                                status = "disabled";
                        };
-                        mipi@021dc000 { /* MIPI-CSI */
+                        mipi_csi: mipi@021dc000 {
                                reg = <0x021dc000 0x4000>;
                        };
-                        mipi@021e0000 { /* MIPI-DSI */
+                        mipi_dsi: mipi@021e0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                reg = <0x021e0000 0x4000>;
+                                status = "disabled";
+                                port@0 {
+                                        reg = <0>;
+                                        mipi_mux_0: endpoint {
+                                                remote-endpoint = <&ipu1_di0_mipi>;
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        mipi_mux_1: endpoint {
+                                                remote-endpoint = <&ipu1_di1_mipi>;
+                                        };
+                                };
                        };
                        vdoa@021e4000 {
                                reg = <0x021e4000 0x4000>;
-                                interrupts = <0 18 0x04>;
+                                interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        uart2: serial@021e8000 {
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021e8000 0x4000>;
-                                interrupts = <0 27 0x04>;
+                                interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 160>, <&clks 161>;
                                clock-names = "ipg", "per";
                                dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
@@ -1602,7 +995,7 @@
                        uart3: serial@021ec000 {
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021ec000 0x4000>;
-                                interrupts = <0 28 0x04>;
+                                interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 160>, <&clks 161>;
                                clock-names = "ipg", "per";
                                dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
@@ -1613,7 +1006,7 @@
                        uart4: serial@021f0000 {
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021f0000 0x4000>;
-                                interrupts = <0 29 0x04>;
+                                interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 160>, <&clks 161>;
                                clock-names = "ipg", "per";
                                dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
@@ -1624,7 +1017,7 @@
                        uart5: serial@021f4000 {
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021f4000 0x4000>;
-                                interrupts = <0 30 0x04>;
+                                interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks 160>, <&clks 161>;
                                clock-names = "ipg", "per";
                                dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
@@ -1634,13 +1027,65 @@
                };
                ipu1: ipu@02400000 {
-                        #crtc-cells = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                        compatible = "fsl,imx6q-ipu";
                        reg = <0x02400000 0x400000>;
-                        interrupts = <0 6 0x4 0 5 0x4>;
+                        interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
+                                     <0 5 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clks 130>, <&clks 131>, <&clks 132>;
                        clock-names = "bus", "di0", "di1";
                        resets = <&src 2>;
+                        ipu1_di0: port@2 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <2>;
+                                ipu1_di0_disp0: endpoint@0 {
+                                };
+                                ipu1_di0_hdmi: endpoint@1 {
+                                        remote-endpoint = <&hdmi_mux_0>;
+                                };
+                                ipu1_di0_mipi: endpoint@2 {
+                                        remote-endpoint = <&mipi_mux_0>;
+                                };
+                                ipu1_di0_lvds0: endpoint@3 {
+                                        remote-endpoint = <&lvds0_mux_0>;
+                                };
+                                ipu1_di0_lvds1: endpoint@4 {
+                                        remote-endpoint = <&lvds1_mux_0>;
+                                };
+                        };
+                        ipu1_di1: port@3 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <3>;
+                                ipu1_di0_disp1: endpoint@0 {
+                                };
+                                ipu1_di1_hdmi: endpoint@1 {
+                                        remote-endpoint = <&hdmi_mux_1>;
+                                };
+                                ipu1_di1_mipi: endpoint@2 {
+                                        remote-endpoint = <&mipi_mux_1>;
+                                };
+                                ipu1_di1_lvds0: endpoint@3 {
+                                        remote-endpoint = <&lvds0_mux_1>;
+                                };
+                                ipu1_di1_lvds1: endpoint@4 {
+                                        remote-endpoint = <&lvds1_mux_1>;
+                                };
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index cc68e19c5163..864d8dfb51ca 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -8,6 +8,8 @@
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include "imx6sl.dtsi"
 / {
@@ -18,11 +20,26 @@
                reg = <0x80000000 0x40000000>;
        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_led>;
+                user {
+                        label = "debug";
+                        gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
        regulators {
                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
-                reg_usb_otg1_vbus: usb_otg1_vbus {
+                reg_usb_otg1_vbus: regulator@0 {
                        compatible = "regulator-fixed";
+                        reg = <0>;
                        regulator-name = "usb_otg1_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
@@ -30,22 +47,63 @@
                        enable-active-high;
                };
-                reg_usb_otg2_vbus: usb_otg2_vbus {
+                reg_usb_otg2_vbus: regulator@1 {
                        compatible = "regulator-fixed";
+                        reg = <1>;
                        regulator-name = "usb_otg2_vbus";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        gpio = <&gpio4 2 0>;
                        enable-active-high;
                };
+                reg_aud3v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "wm8962-supply-3v15";
+                        regulator-min-microvolt = <3150000>;
+                        regulator-max-microvolt = <3150000>;
+                        regulator-boot-on;
+                };
+                reg_aud4v: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "wm8962-supply-4v2";
+                        regulator-min-microvolt = <4325000>;
+                        regulator-max-microvolt = <4325000>;
+                        regulator-boot-on;
+                };
+        };
+        sound {
+                compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+                model = "wm8962-audio";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "Ext Spk", "SPKOUTL",
+                        "Ext Spk", "SPKOUTR",
+                        "AMIC", "MICBIAS",
+                        "IN3R", "AMIC";
+                mux-int-port = <2>;
+                mux-ext-port = <3>;
        };
 };
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux3>;
+        status = "okay";
+};
 &ecspi1 {
        fsl,spi-num-chipselects = <1>;
        cs-gpios = <&gpio4 11 0>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        pinctrl-0 = <&pinctrl_ecspi1>;
        status = "okay";
        flash: m25p80@0 {
@@ -59,16 +117,144 @@
 &fec {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec_1>;
+        pinctrl-0 = <&pinctrl_fec>;
        phy-mode = "rmii";
        status = "okay";
 };
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                                regulator-always-on;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        codec: wm8962@1a {
+                compatible = "wlf,wm8962";
+                reg = <0x1a>;
+                clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
+                DCVDD-supply = <&vgen3_reg>;
+                DBVDD-supply = <&reg_aud3v>;
+                AVDD-supply = <&vgen3_reg>;
+                CPVDD-supply = <&vgen3_reg>;
+                MICVDD-supply = <&reg_aud3v>;
+                PLLVDD-supply = <&vgen3_reg>;
+                SPKVDD1-supply = <&reg_aud4v>;
+                SPKVDD2-supply = <&reg_aud4v>;
+        };
+};
 &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
-        hog {
+        imx6sl-evk {
                pinctrl_hog: hoggrp {
                        fsl,pins = <
                                MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
@@ -78,21 +264,230 @@
                                MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
                                MX6SL_PAD_KEY_COL4__GPIO4_IO00  0x80000000
                                MX6SL_PAD_KEY_COL5__GPIO4_IO02  0x80000000
+                                MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
+                        >;
+                };
+                pinctrl_audmux3: audmux3grp {
+                        fsl,pins = <
+                                MX6SL_PAD_AUD_RXD__AUD3_RXD       0x4130b0
+                                MX6SL_PAD_AUD_TXC__AUD3_TXC       0x4130b0
+                                MX6SL_PAD_AUD_TXD__AUD3_TXD       0x4110b0
+                                MX6SL_PAD_AUD_TXFS__AUD3_TXFS     0x4130b0
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO      0x100b1
+                                MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI      0x100b1
+                                MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK      0x100b1
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX6SL_PAD_FEC_MDC__FEC_MDC              0x1b0b0
+                                MX6SL_PAD_FEC_MDIO__FEC_MDIO            0x1b0b0
+                                MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV         0x1b0b0
+                                MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0        0x1b0b0
+                                MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1        0x1b0b0
+                                MX6SL_PAD_FEC_TX_EN__FEC_TX_EN          0x1b0b0
+                                MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0        0x1b0b0
+                                MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1        0x1b0b0
+                                MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT      0x4001b0a8
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6SL_PAD_I2C1_SCL__I2C1_SCL    0x4001b8b1
+                                MX6SL_PAD_I2C1_SDA__I2C1_SDA    0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6SL_PAD_I2C2_SCL__I2C2_SCL    0x4001b8b1
+                                MX6SL_PAD_I2C2_SDA__I2C2_SDA    0x4001b8b1
+                        >;
+                };
+                pinctrl_led: ledgrp {
+                        fsl,pins = <
+                                MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
+                        >;
+                };
+                pinctrl_kpp: kppgrp {
+                        fsl,pins = <
+                                MX6SL_PAD_KEY_ROW0__KEY_ROW0    0x1b010
+                                MX6SL_PAD_KEY_ROW1__KEY_ROW1    0x1b010
+                                MX6SL_PAD_KEY_ROW2__KEY_ROW2    0x1b0b0
+                                MX6SL_PAD_KEY_COL0__KEY_COL0    0x110b0
+                                MX6SL_PAD_KEY_COL1__KEY_COL1    0x110b0
+                                MX6SL_PAD_KEY_COL2__KEY_COL2    0x110b0
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6SL_PAD_UART1_RXD__UART1_RX_DATA      0x1b0b1
+                                MX6SL_PAD_UART1_TXD__UART1_TX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg1: usbotg1grp {
+                        fsl,pins = <
+                                MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID      0x17059
+                        >;
+                };
+                pinctrl_usdhc1: usdhc1grp {
+                        fsl,pins = <
+                                MX6SL_PAD_SD1_CMD__SD1_CMD              0x17059
+                                MX6SL_PAD_SD1_CLK__SD1_CLK              0x10059
+                                MX6SL_PAD_SD1_DAT0__SD1_DATA0           0x17059
+                                MX6SL_PAD_SD1_DAT1__SD1_DATA1           0x17059
+                                MX6SL_PAD_SD1_DAT2__SD1_DATA2           0x17059
+                                MX6SL_PAD_SD1_DAT3__SD1_DATA3           0x17059
+                                MX6SL_PAD_SD1_DAT4__SD1_DATA4           0x17059
+                                MX6SL_PAD_SD1_DAT5__SD1_DATA5           0x17059
+                                MX6SL_PAD_SD1_DAT6__SD1_DATA6           0x17059
+                                MX6SL_PAD_SD1_DAT7__SD1_DATA7           0x17059
+                        >;
+                };
+                pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD1_CMD__SD1_CMD              0x170b9
+                                MX6SL_PAD_SD1_CLK__SD1_CLK              0x100b9
+                                MX6SL_PAD_SD1_DAT0__SD1_DATA0           0x170b9
+                                MX6SL_PAD_SD1_DAT1__SD1_DATA1           0x170b9
+                                MX6SL_PAD_SD1_DAT2__SD1_DATA2           0x170b9
+                                MX6SL_PAD_SD1_DAT3__SD1_DATA3           0x170b9
+                                MX6SL_PAD_SD1_DAT4__SD1_DATA4           0x170b9
+                                MX6SL_PAD_SD1_DAT5__SD1_DATA5           0x170b9
+                                MX6SL_PAD_SD1_DAT6__SD1_DATA6           0x170b9
+                                MX6SL_PAD_SD1_DAT7__SD1_DATA7           0x170b9
+                        >;
+                };
+                pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD1_CMD__SD1_CMD              0x170f9
+                                MX6SL_PAD_SD1_CLK__SD1_CLK              0x100f9
+                                MX6SL_PAD_SD1_DAT0__SD1_DATA0           0x170f9
+                                MX6SL_PAD_SD1_DAT1__SD1_DATA1           0x170f9
+                                MX6SL_PAD_SD1_DAT2__SD1_DATA2           0x170f9
+                                MX6SL_PAD_SD1_DAT3__SD1_DATA3           0x170f9
+                                MX6SL_PAD_SD1_DAT4__SD1_DATA4           0x170f9
+                                MX6SL_PAD_SD1_DAT5__SD1_DATA5           0x170f9
+                                MX6SL_PAD_SD1_DAT6__SD1_DATA6           0x170f9
+                                MX6SL_PAD_SD1_DAT7__SD1_DATA7           0x170f9
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x17059
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x10059
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x17059
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x17059
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x17059
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x17059
+                        >;
+                };
+                pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x170b9
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x100b9
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x170b9
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x170b9
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x170b9
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x170b9
+                        >;
+                };
+                pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x170f9
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x100f9
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x170f9
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x170f9
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x170f9
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x170f9
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x17059
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x10059
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x17059
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x17059
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x17059
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x17059
+                        >;
+                };
+                pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x170b9
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x100b9
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x170b9
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x170b9
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x170b9
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x170b9
+                        >;
+                };
+                pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x170f9
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x100f9
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x170f9
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x170f9
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x170f9
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x170f9
                        >;
                };
        };
 };
+&kpp {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_kpp>;
+        linux,keymap = <
+                        MATRIX_KEY(0x0, 0x0, KEY_UP)         /* ROW0, COL0 */
+                        MATRIX_KEY(0x0, 0x1, KEY_DOWN)       /* ROW0, COL1 */
+                        MATRIX_KEY(0x0, 0x2, KEY_ENTER)      /* ROW0, COL2 */
+                        MATRIX_KEY(0x1, 0x0, KEY_HOME)       /* ROW1, COL0 */
+                        MATRIX_KEY(0x1, 0x1, KEY_RIGHT)      /* ROW1, COL1 */
+                        MATRIX_KEY(0x1, 0x2, KEY_LEFT)       /* ROW1, COL2 */
+                        MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
+                        MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP)   /* ROW2, COL1 */
+        >;
+        status = "okay";
+};
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 &usbotg1 {
        vbus-supply = <&reg_usb_otg1_vbus>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg1_1>;
+        pinctrl-0 = <&pinctrl_usbotg1>;
        disable-over-current;
        status = "okay";
 };
@@ -106,9 +501,9 @@
 &usdhc1 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
-        pinctrl-0 = <&pinctrl_usdhc1_1>;
+        pinctrl-0 = <&pinctrl_usdhc1>;
-        pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>;
+        pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-        pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>;
+        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
        bus-width = <8>;
        cd-gpios = <&gpio4 7 0>;
        wp-gpios = <&gpio4 6 0>;
@@ -117,9 +512,9 @@
 &usdhc2 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
-        pinctrl-0 = <&pinctrl_usdhc2_1>;
+        pinctrl-0 = <&pinctrl_usdhc2>;
-        pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
+        pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
-        pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
+        pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
        cd-gpios = <&gpio5 0 0>;
        wp-gpios = <&gpio4 29 0>;
        status = "okay";
@@ -127,9 +522,9 @@
 &usdhc3 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
-        pinctrl-0 = <&pinctrl_usdhc3_1>;
+        pinctrl-0 = <&pinctrl_usdhc3>;
-        pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-        pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
        cd-gpios = <&gpio3 22 0>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 28558f1aaf2d..3cb4941afeef 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -7,6 +7,7 @@
 *
 */
+#include <dt-bindings/interrupt-controller/irq.h>
 #include "skeleton.dtsi"
 #include "imx6sl-pinfunc.h"
 #include <dt-bindings/clock/imx6sl-clock.h>
@@ -27,6 +28,8 @@
                spi1 = &ecspi2;
                spi2 = &ecspi3;
                spi3 = &ecspi4;
+                usbphy0 = &usbphy1;
+                usbphy1 = &usbphy2;
        };
        cpus {
@@ -38,6 +41,27 @@
                        device_type = "cpu";
                        reg = <0x0>;
                        next-level-cache = <&L2>;
+                        operating-points = <
+                                /* kHz    uV */
+                                996000  1275000
+                                792000  1175000
+                                396000  975000
+                        >;
+                        fsl,soc-operating-points = <
+                                /* ARM kHz      SOC-PU uV */
+                                996000          1225000
+                                792000          1175000
+                                396000          1175000
+                        >;
+                        clock-latency = <61036>; /* two CLK32 periods */
+                        clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
+                                        <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
+                                        <&clks IMX6SL_CLK_PLL1_SYS>;
+                        clock-names = "arm", "pll2_pfd2_396m", "step",
+                                      "pll1_sw", "pll1_sys";
+                        arm-supply = <&reg_arm>;
+                        pu-supply = <&reg_pu>;
+                        soc-supply = <&reg_soc>;
                };
        };
@@ -73,10 +97,16 @@
                interrupt-parent = <&intc>;
                ranges;
+                ocram: sram@00900000 {
+                        compatible = "mmio-sram";
+                        reg = <0x00900000 0x20000>;
+                        clocks = <&clks IMX6SL_CLK_OCRAM>;
+                };
                L2: l2-cache@00a02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0x00a02000 0x1000>;
-                        interrupts = <0 92 0x04>;
+                        interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
                        cache-unified;
                        cache-level = <2>;
                        arm,tag-latency = <4 2 3>;
@@ -85,7 +115,7 @@
                pmu {
                        compatible = "arm,cortex-a9-pmu";
-                        interrupts = <0 94 0x04>;
+                        interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
                };
                aips1: aips-bus@02000000 {
@@ -104,7 +134,7 @@
                                spdif: spdif@02004000 {
                                        reg = <0x02004000 0x4000>;
-                                        interrupts = <0 52 0x04>;
+                                        interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
                                };
                                ecspi1: ecspi@02008000 {
@@ -112,7 +142,7 @@
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02008000 0x4000>;
-                                        interrupts = <0 31 0x04>;
+                                        interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_ECSPI1>,
                                                 <&clks IMX6SL_CLK_ECSPI1>;
                                        clock-names = "ipg", "per";
@@ -124,7 +154,7 @@
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x0200c000 0x4000>;
-                                        interrupts = <0 32 0x04>;
+                                        interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_ECSPI2>,
                                                 <&clks IMX6SL_CLK_ECSPI2>;
                                        clock-names = "ipg", "per";
@@ -136,7 +166,7 @@
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02010000 0x4000>;
-                                        interrupts = <0 33 0x04>;
+                                        interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_ECSPI3>,
                                                 <&clks IMX6SL_CLK_ECSPI3>;
                                        clock-names = "ipg", "per";
@@ -148,7 +178,7 @@
                                        #size-cells = <0>;
                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
                                        reg = <0x02014000 0x4000>;
-                                        interrupts = <0 34 0x04>;
+                                        interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_ECSPI4>,
                                                 <&clks IMX6SL_CLK_ECSPI4>;
                                        clock-names = "ipg", "per";
@@ -159,7 +189,7 @@
                                        compatible = "fsl,imx6sl-uart",
                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02018000 0x4000>;
-                                        interrupts = <0 30 0x04>;
+                                        interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_UART>,
                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
                                        clock-names = "ipg", "per";
@@ -172,7 +202,7 @@
                                        compatible = "fsl,imx6sl-uart",
                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02020000 0x4000>;
-                                        interrupts = <0 26 0x04>;
+                                        interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_UART>,
                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
                                        clock-names = "ipg", "per";
@@ -185,7 +215,7 @@
                                        compatible = "fsl,imx6sl-uart",
                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02024000 0x4000>;
-                                        interrupts = <0 27 0x04>;
+                                        interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_UART>,
                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
                                        clock-names = "ipg", "per";
@@ -195,9 +225,11 @@
                                };
                                ssi1: ssi@02028000 {
-                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        compatible = "fsl,imx6sl-ssi",
+                                                        "fsl,imx51-ssi",
+                                                        "fsl,imx21-ssi";
                                        reg = <0x02028000 0x4000>;
-                                        interrupts = <0 46 0x04>;
+                                        interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_SSI1>;
                                        dmas = <&sdma 37 1 0>,
                                               <&sdma 38 1 0>;
@@ -207,9 +239,11 @@
                                };
                                ssi2: ssi@0202c000 {
-                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        compatible = "fsl,imx6sl-ssi",
+                                                        "fsl,imx51-ssi",
+                                                        "fsl,imx21-ssi";
                                        reg = <0x0202c000 0x4000>;
-                                        interrupts = <0 47 0x04>;
+                                        interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_SSI2>;
                                        dmas = <&sdma 41 1 0>,
                                               <&sdma 42 1 0>;
@@ -219,9 +253,11 @@
                                };
                                ssi3: ssi@02030000 {
-                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        compatible = "fsl,imx6sl-ssi",
+                                                        "fsl,imx51-ssi",
+                                                        "fsl,imx21-ssi";
                                        reg = <0x02030000 0x4000>;
-                                        interrupts = <0 48 0x04>;
+                                        interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_SSI3>;
                                        dmas = <&sdma 45 1 0>,
                                               <&sdma 46 1 0>;
@@ -234,7 +270,7 @@
                                        compatible = "fsl,imx6sl-uart",
                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02034000 0x4000>;
-                                        interrupts = <0 28 0x04>;
+                                        interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_UART>,
                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
                                        clock-names = "ipg", "per";
@@ -247,7 +283,7 @@
                                        compatible = "fsl,imx6sl-uart",
                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02038000 0x4000>;
-                                        interrupts = <0 29 0x04>;
+                                        interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6SL_CLK_UART>,
                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
                                        clock-names = "ipg", "per";
@@ -261,7 +297,7 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
                                reg = <0x02080000 0x4000>;
-                                interrupts = <0 83 0x04>;
+                                interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_PWM1>,
                                         <&clks IMX6SL_CLK_PWM1>;
                                clock-names = "ipg", "per";
@@ -271,7 +307,7 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
                                reg = <0x02084000 0x4000>;
-                                interrupts = <0 84 0x04>;
+                                interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_PWM2>,
                                         <&clks IMX6SL_CLK_PWM2>;
                                clock-names = "ipg", "per";
@@ -281,7 +317,7 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
                                reg = <0x02088000 0x4000>;
-                                interrupts = <0 85 0x04>;
+                                interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_PWM3>,
                                         <&clks IMX6SL_CLK_PWM3>;
                                clock-names = "ipg", "per";
@@ -291,7 +327,7 @@
                                #pwm-cells = <2>;
                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
                                reg = <0x0208c000 0x4000>;
-                                interrupts = <0 86 0x04>;
+                                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_PWM4>,
                                         <&clks IMX6SL_CLK_PWM4>;
                                clock-names = "ipg", "per";
@@ -300,7 +336,7 @@
                        gpt: gpt@02098000 {
                                compatible = "fsl,imx6sl-gpt";
                                reg = <0x02098000 0x4000>;
-                                interrupts = <0 55 0x04>;
+                                interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_GPT>,
                                         <&clks IMX6SL_CLK_GPT_SERIAL>;
                                clock-names = "ipg", "per";
@@ -309,7 +345,8 @@
                        gpio1: gpio@0209c000 {
                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
                                reg = <0x0209c000 0x4000>;
-                                interrupts = <0 66 0x04 0 67 0x04>;
+                                interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 67 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -319,7 +356,8 @@
                        gpio2: gpio@020a0000 {
                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
                                reg = <0x020a0000 0x4000>;
-                                interrupts = <0 68 0x04 0 69 0x04>;
+                                interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 69 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -329,7 +367,8 @@
                        gpio3: gpio@020a4000 {
                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
                                reg = <0x020a4000 0x4000>;
-                                interrupts = <0 70 0x04 0 71 0x04>;
+                                interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 71 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -339,7 +378,8 @@
                        gpio4: gpio@020a8000 {
                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
                                reg = <0x020a8000 0x4000>;
-                                interrupts = <0 72 0x04 0 73 0x04>;
+                                interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 73 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -349,7 +389,8 @@
                        gpio5: gpio@020ac000 {
                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
                                reg = <0x020ac000 0x4000>;
-                                interrupts = <0 74 0x04 0 75 0x04>;
+                                interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 75 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -357,21 +398,23 @@
                        };
                        kpp: kpp@020b8000 {
+                                compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
                                reg = <0x020b8000 0x4000>;
-                                interrupts = <0 82 0x04>;
+                                interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6SL_CLK_DUMMY>;
                        };
                        wdog1: wdog@020bc000 {
                                compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
                                reg = <0x020bc000 0x4000>;
-                                interrupts = <0 80 0x04>;
+                                interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_DUMMY>;
                        };
                        wdog2: wdog@020c0000 {
                                compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
                                reg = <0x020c0000 0x4000>;
-                                interrupts = <0 81 0x04>;
+                                interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_DUMMY>;
                                status = "disabled";
                        };
@@ -379,7 +422,8 @@
                        clks: ccm@020c4000 {
                                compatible = "fsl,imx6sl-ccm";
                                reg = <0x020c4000 0x4000>;
-                                interrupts = <0 87 0x04 0 88 0x04>;
+                                interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 88 IRQ_TYPE_LEVEL_HIGH>;
                                #clock-cells = <1>;
                        };
@@ -388,7 +432,9 @@
                                             "fsl,imx6q-anatop",
                                             "syscon", "simple-bus";
                                reg = <0x020c8000 0x1000>;
-                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+                                interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 54 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 127 IRQ_TYPE_LEVEL_HIGH>;
                                regulator-1p1@110 {
                                        compatible = "fsl,anatop-regulator";
@@ -434,7 +480,7 @@
                                reg_arm: regulator-vddcore@140 {
                                        compatible = "fsl,anatop-regulator";
-                                        regulator-name = "cpu";
+                                        regulator-name = "vddarm";
                                        regulator-min-microvolt = <725000>;
                                        regulator-max-microvolt = <1450000>;
                                        regulator-always-on;
@@ -487,15 +533,17 @@
                        usbphy1: usbphy@020c9000 {
                                compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
                                reg = <0x020c9000 0x1000>;
-                                interrupts = <0 44 0x04>;
+                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBPHY1>;
+                                fsl,anatop = <&anatop>;
                        };
                        usbphy2: usbphy@020ca000 {
                                compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
                                reg = <0x020ca000 0x1000>;
-                                interrupts = <0 45 0x04>;
+                                interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBPHY2>;
+                                fsl,anatop = <&anatop>;
                        };
                        snvs@020cc000 {
@@ -507,31 +555,33 @@
                                snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
-                                        interrupts = <0 19 0x04 0 20 0x04>;
+                                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
+                                                     <0 20 IRQ_TYPE_LEVEL_HIGH>;
                                };
                        };
                        epit1: epit@020d0000 {
                                reg = <0x020d0000 0x4000>;
-                                interrupts = <0 56 0x04>;
+                                interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        epit2: epit@020d4000 {
                                reg = <0x020d4000 0x4000>;
-                                interrupts = <0 57 0x04>;
+                                interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        src: src@020d8000 {
                                compatible = "fsl,imx6sl-src", "fsl,imx51-src";
                                reg = <0x020d8000 0x4000>;
-                                interrupts = <0 91 0x04 0 96 0x04>;
+                                interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
+                                             <0 96 IRQ_TYPE_LEVEL_HIGH>;
                                #reset-cells = <1>;
                        };
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
-                                interrupts = <0 89 0x04>;
+                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        gpr: iomuxc-gpr@020e0000 {
@@ -543,235 +593,22 @@
                        iomuxc: iomuxc@020e0000 {
                                compatible = "fsl,imx6sl-iomuxc";
                                reg = <0x020e0000 0x4000>;
-                                ecspi1 {
-                                        pinctrl_ecspi1_1: ecspi1grp-1 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
-                                                        MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
-                                                        MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
-                                                >;
-                                        };
-                                };
-                                fec {
-                                        pinctrl_fec_1: fecgrp-1 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_FEC_MDC__FEC_MDC         0x1b0b0
-                                                        MX6SL_PAD_FEC_MDIO__FEC_MDIO       0x1b0b0
-                                                        MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV    0x1b0b0
-                                                        MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0   0x1b0b0
-                                                        MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1   0x1b0b0
-                                                        MX6SL_PAD_FEC_TX_EN__FEC_TX_EN     0x1b0b0
-                                                        MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0   0x1b0b0
-                                                        MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1   0x1b0b0
-                                                        MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
-                                                >;
-                                        };
-                                };
-                                uart1 {
-                                        pinctrl_uart1_1: uart1grp-1 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
-                                                        MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
-                                                >;
-                                        };
-                                };
-                                usbotg1 {
-                                        pinctrl_usbotg1_1: usbotg1grp-1 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usbotg1_2: usbotg1grp-2 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usbotg1_3: usbotg1grp-3 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usbotg1_4: usbotg1grp-4 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usbotg1_5: usbotg1grp-5 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
-                                                >;
-                                        };
-                                };
-                                usbotg2 {
-                                        pinctrl_usbotg2_1: usbotg2grp-1 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usbotg2_2: usbotg2grp-2 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usbotg2_3: usbotg2grp-3 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usbotg2_4: usbotg2grp-4 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
-                                                >;
-                                        };
-                                };
-                                usdhc1 {
-                                        pinctrl_usdhc1_1: usdhc1grp-1 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD1_CMD__SD1_CMD    0x17059
-                                                        MX6SL_PAD_SD1_CLK__SD1_CLK    0x10059
-                                                        MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
-                                                        MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
-                                                        MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
-                                                        MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
-                                                        MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
-                                                        MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
-                                                        MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
-                                                        MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
-                                                        MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
-                                                        MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
-                                                        MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
-                                                        MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
-                                                        MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
-                                                        MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
-                                                        MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
-                                                        MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
-                                                        MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
-                                                >;
-                                        };
-                                        pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
-                                                        MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
-                                                        MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
-                                                        MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
-                                                        MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
-                                                        MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
-                                                        MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
-                                                        MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
-                                                        MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
-                                                        MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
-                                                >;
-                                        };
-                                };
-                                usdhc2 {
-                                        pinctrl_usdhc2_1: usdhc2grp-1 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD2_CMD__SD2_CMD    0x17059
-                                                        MX6SL_PAD_SD2_CLK__SD2_CLK    0x10059
-                                                        MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
-                                                        MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
-                                                        MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
-                                                        MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD2_CMD__SD2_CMD    0x170b9
-                                                        MX6SL_PAD_SD2_CLK__SD2_CLK    0x100b9
-                                                        MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
-                                                        MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
-                                                        MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
-                                                        MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
-                                                >;
-                                        };
-                                        pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD2_CMD__SD2_CMD    0x170f9
-                                                        MX6SL_PAD_SD2_CLK__SD2_CLK    0x100f9
-                                                        MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
-                                                        MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
-                                                        MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
-                                                        MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
-                                                >;
-                                        };
-                                };
-                                usdhc3 {
-                                        pinctrl_usdhc3_1: usdhc3grp-1 {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD3_CMD__SD3_CMD    0x17059
-                                                        MX6SL_PAD_SD3_CLK__SD3_CLK    0x10059
-                                                        MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
-                                                        MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
-                                                        MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
-                                                        MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
-                                                >;
-                                        };
-                                        pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD3_CMD__SD3_CMD    0x170b9
-                                                        MX6SL_PAD_SD3_CLK__SD3_CLK    0x100b9
-                                                        MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
-                                                        MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
-                                                        MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
-                                                        MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
-                                                >;
-                                        };
-                                        pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
-                                                fsl,pins = <
-                                                        MX6SL_PAD_SD3_CMD__SD3_CMD    0x170f9
-                                                        MX6SL_PAD_SD3_CLK__SD3_CLK    0x100f9
-                                                        MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
-                                                        MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
-                                                        MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
-                                                        MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
-                                                >;
-                                        };
-                                };
                        };
                        csi: csi@020e4000 {
                                reg = <0x020e4000 0x4000>;
-                                interrupts = <0 7 0x04>;
+                                interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        spdc: spdc@020e8000 {
                                reg = <0x020e8000 0x4000>;
-                                interrupts = <0 6 0x04>;
+                                interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        sdma: sdma@020ec000 {
                                compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
                                reg = <0x020ec000 0x4000>;
-                                interrupts = <0 2 0x04>;
+                                interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_SDMA>,
                                         <&clks IMX6SL_CLK_SDMA>;
                                clock-names = "ipg", "ahb";
@@ -782,22 +619,22 @@
                        pxp: pxp@020f0000 {
                                reg = <0x020f0000 0x4000>;
-                                interrupts = <0 98 0x04>;
+                                interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        epdc: epdc@020f4000 {
                                reg = <0x020f4000 0x4000>;
-                                interrupts = <0 97 0x04>;
+                                interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        lcdif: lcdif@020f8000 {
                                reg = <0x020f8000 0x4000>;
-                                interrupts = <0 39 0x04>;
+                                interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        dcp: dcp@020fc000 {
                                reg = <0x020fc000 0x4000>;
-                                interrupts = <0 99 0x04>;
+                                interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
@@ -811,7 +648,7 @@
                        usbotg1: usb@02184000 {
                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
                                reg = <0x02184000 0x200>;
-                                interrupts = <0 43 0x04>;
+                                interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBOH3>;
                                fsl,usbphy = <&usbphy1>;
                                fsl,usbmisc = <&usbmisc 0>;
@@ -821,7 +658,7 @@
                        usbotg2: usb@02184200 {
                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
                                reg = <0x02184200 0x200>;
-                                interrupts = <0 42 0x04>;
+                                interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBOH3>;
                                fsl,usbphy = <&usbphy2>;
                                fsl,usbmisc = <&usbmisc 1>;
@@ -831,7 +668,7 @@
                        usbh: usb@02184400 {
                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
                                reg = <0x02184400 0x200>;
-                                interrupts = <0 40 0x04>;
+                                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBOH3>;
                                fsl,usbmisc = <&usbmisc 2>;
                                status = "disabled";
@@ -847,7 +684,7 @@
                        fec: ethernet@02188000 {
                                compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
                                reg = <0x02188000 0x4000>;
-                                interrupts = <0 114 0x04>;
+                                interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_ENET_REF>,
                                         <&clks IMX6SL_CLK_ENET_REF>;
                                clock-names = "ipg", "ahb";
@@ -857,7 +694,7 @@
                        usdhc1: usdhc@02190000 {
                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
                                reg = <0x02190000 0x4000>;
-                                interrupts = <0 22 0x04>;
+                                interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USDHC1>,
                                         <&clks IMX6SL_CLK_USDHC1>,
                                         <&clks IMX6SL_CLK_USDHC1>;
@@ -869,7 +706,7 @@
                        usdhc2: usdhc@02194000 {
                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
                                reg = <0x02194000 0x4000>;
-                                interrupts = <0 23 0x04>;
+                                interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USDHC2>,
                                         <&clks IMX6SL_CLK_USDHC2>,
                                         <&clks IMX6SL_CLK_USDHC2>;
@@ -881,7 +718,7 @@
                        usdhc3: usdhc@02198000 {
                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
                                reg = <0x02198000 0x4000>;
-                                interrupts = <0 24 0x04>;
+                                interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USDHC3>,
                                         <&clks IMX6SL_CLK_USDHC3>,
                                         <&clks IMX6SL_CLK_USDHC3>;
@@ -893,7 +730,7 @@
                        usdhc4: usdhc@0219c000 {
                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
                                reg = <0x0219c000 0x4000>;
-                                interrupts = <0 25 0x04>;
+                                interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USDHC4>,
                                         <&clks IMX6SL_CLK_USDHC4>,
                                         <&clks IMX6SL_CLK_USDHC4>;
@@ -907,7 +744,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
                                reg = <0x021a0000 0x4000>;
-                                interrupts = <0 36 0x04>;
+                                interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_I2C1>;
                                status = "disabled";
                        };
@@ -917,7 +754,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
                                reg = <0x021a4000 0x4000>;
-                                interrupts = <0 37 0x04>;
+                                interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_I2C2>;
                                status = "disabled";
                        };
@@ -927,7 +764,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
                                reg = <0x021a8000 0x4000>;
-                                interrupts = <0 38 0x04>;
+                                interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_I2C3>;
                                status = "disabled";
                        };
@@ -939,12 +776,12 @@
                        rngb: rngb@021b4000 {
                                reg = <0x021b4000 0x4000>;
-                                interrupts = <0 5 0x04>;
+                                interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        weim: weim@021b8000 {
                                reg = <0x021b8000 0x4000>;
-                                interrupts = <0 14 0x04>;
+                                interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        ocotp: ocotp@021bc000 {
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index e6be9315ff0a..b10e6351da53 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -18,6 +18,28 @@
                bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
        };
+        /* 24 MHz chrystal on the core module */
+        xtal24mhz: xtal24mhz@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+        pclk: pclk@0 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <1>;
+                clock-mult = <1>;
+                clocks = <&xtal24mhz>;
+        };
+        /* The UART clock is 14.74 MHz divided by an ICS525 */
+        uartclk: uartclk@14.74M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <14745600>;
+        };
        syscon {
                compatible = "arm,integrator-ap-syscon";
                reg = <0x11000000 0x100>;
@@ -28,14 +50,17 @@
        timer0: timer@13000000 {
                compatible = "arm,integrator-timer";
+                clocks = <&xtal24mhz>;
        };
        timer1: timer@13000100 {
                compatible = "arm,integrator-timer";
+                clocks = <&xtal24mhz>;
        };
        timer2: timer@13000200 {
                compatible = "arm,integrator-timer";
+                clocks = <&xtal24mhz>;
        };
        pic: pic@14000000 {
@@ -92,26 +117,36 @@
                rtc: rtc@15000000 {
                        compatible = "arm,pl030", "arm,primecell";
                        arm,primecell-periphid = <0x00041030>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                };
                uart0: uart@16000000 {
                        compatible = "arm,pl010", "arm,primecell";
                        arm,primecell-periphid = <0x00041010>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                };
                uart1: uart@17000000 {
                        compatible = "arm,pl010", "arm,primecell";
                        arm,primecell-periphid = <0x00041010>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                };
                kmi0: kmi@18000000 {
                        compatible = "arm,pl050", "arm,primecell";
                        arm,primecell-periphid = <0x00041050>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "KMIREFCLK", "apb_pclk";
                };
                kmi1: kmi@19000000 {
                        compatible = "arm,pl050", "arm,primecell";
                        arm,primecell-periphid = <0x00041050>;
+                        clocks = <&xtal24mhz>, <&pclk>;
+                        clock-names = "KMIREFCLK", "apb_pclk";
                };
        };
 };
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index a21c17de9a5e..d43f15b4f79a 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -13,25 +13,107 @@
                bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
        };
+        /*
+         * The Integrator/CP overall clocking architecture can be found in
+         * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
+         * appear to illustrate the layout used in most configurations.
+         */
+        /* The codec chrystal operates at 24.576 MHz */
+        xtal_codec: xtal24.576@24.576M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24576000>;
+        };
+        /* The chrystal is divided by 2 by the codec for the AACI bit clock */
+        aaci_bitclk: aaci_bitclk@12.288M {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <2>;
+                clock-mult = <1>;
+                clocks = <&xtal_codec>;
+        };
+        /* This is a 25MHz chrystal on the base board */
+        xtal25mhz: xtal25mhz@25M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <25000000>;
+        };
+        /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
+        uartclk: uartclk@14.74M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <14745600>;
+        };
+        /* Actually sysclk I think */
+        pclk: pclk@0 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+        core-module@10000000 {
+                /* 24 MHz chrystal on the core module */
+                xtal24mhz: xtal24mhz@24M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+                /*
+                 * External oscillator on the core module, usually used
+                 * to drive video circuitry. Driven from the 24MHz clock.
+                 */
+                auxosc: cm_aux_osc@25M {
+                        #clock-cells = <0>;
+                        compatible = "arm,integrator-cm-auxosc";
+                        clocks = <&xtal24mhz>;
+                };
+                /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
+                kmiclk: kmiclk@1M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clocks = <&xtal24mhz>;
+                };
+                /* The timer clock is the 24 MHz oscillator divided to 1MHz */
+                timclk: timclk@1M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clocks = <&xtal24mhz>;
+                };
+        };
        syscon {
                compatible = "arm,integrator-cp-syscon";
                reg = <0xcb000000 0x100>;
        };
        timer0: timer@13000000 {
-                /* TIMER0 runs @ 25MHz */
+                /* TIMER0 runs directly on the 25MHz chrystal */
                compatible = "arm,integrator-cp-timer";
-                status = "disabled";
+                clocks = <&xtal25mhz>;
        };
        timer1: timer@13000100 {
                /* TIMER1 runs @ 1MHz */
                compatible = "arm,integrator-cp-timer";
+                clocks = <&timclk>;
        };
        timer2: timer@13000200 {
                /* TIMER2 runs @ 1MHz */
                compatible = "arm,integrator-cp-timer";
+                clocks = <&timclk>;
        };
        pic: pic@14000000 {
@@ -74,22 +156,32 @@
                 */
                rtc@15000000 {
                        compatible = "arm,pl031", "arm,primecell";
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                };
                uart@16000000 {
                        compatible = "arm,pl011", "arm,primecell";
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                };
                uart@17000000 {
                        compatible = "arm,pl011", "arm,primecell";
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "uartclk", "apb_pclk";
                };
                kmi@18000000 {
                        compatible = "arm,pl050", "arm,primecell";
+                        clocks = <&kmiclk>, <&pclk>;
+                        clock-names = "KMIREFCLK", "apb_pclk";
                };
                kmi@19000000 {
                        compatible = "arm,pl050", "arm,primecell";
+                        clocks = <&kmiclk>, <&pclk>;
+                        clock-names = "KMIREFCLK", "apb_pclk";
                };
                /*
@@ -100,18 +192,24 @@
                        reg = <0x1c000000 0x1000>;
                        interrupts = <23 24>;
                        max-frequency = <515633>;
+                        clocks = <&uartclk>, <&pclk>;
+                        clock-names = "mclk", "apb_pclk";
                };
                aaci@1d000000 {
                        compatible = "arm,pl041", "arm,primecell";
                        reg = <0x1d000000 0x1000>;
                        interrupts = <25>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                };
                clcd@c0000000 {
                        compatible = "arm,pl110", "arm,primecell";
                        reg = <0xC0000000 0x1000>;
                        interrupts = <22>;
+                        clocks = <&auxosc>, <&pclk>;
+                        clock-names = "clcd", "apb_pclk";
                };
        };
 };
diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi
new file mode 100644
index 000000000000..90774d604bc1
--- /dev/null
+++ b/arch/arm/boot/dts/k2e-clocks.dtsi
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Edison SoC specific device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+clocks {
+        mainpllclk: mainpllclk@2310110 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,main-pll-clock";
+                clocks = <&refclksys>;
+                reg = <0x02620350 4>, <0x02310110 4>;
+                reg-names = "control", "multiplier";
+                fixed-postdiv = <2>;
+        };
+        papllclk: papllclk@2620358 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkpass>;
+                clock-output-names = "pa-pll-clk";
+                reg = <0x02620358 4>;
+                reg-names = "control";
+        };
+        ddr3apllclk: ddr3apllclk@2620360 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkddr3a>;
+                clock-output-names = "ddr-3a-pll-clk";
+                reg = <0x02620360 4>;
+                reg-names = "control";
+        };
+        clkusb1: clkusb1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk16>;
+                clock-output-names = "usb";
+                reg = <0x02350004 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+        clkhyperlink0: clkhyperlink0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "hyperlink-0";
+                reg = <0x02350030 0xb00>, <0x02350014 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <5>;
+        };
+        clkpcie1: clkpcie1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "pcie";
+                reg = <0x0235006c 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <18>;
+        };
+        clkxge: clkxge {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "xge";
+                reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <29>;
+        };
+};
diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts
new file mode 100644
index 000000000000..74b3b63e94cf
--- /dev/null
+++ b/arch/arm/boot/dts/k2e-evm.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Edison EVM device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "keystone.dtsi"
+#include "k2e.dtsi"
+/ {
+        compatible =  "ti,k2e-evm","ti,keystone";
+        model = "Texas Instruments Keystone 2 Edison EVM";
+        soc {
+                clocks {
+                        refclksys: refclksys {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <100000000>;
+                                clock-output-names = "refclk-sys";
+                        };
+                        refclkpass: refclkpass {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <100000000>;
+                                clock-output-names = "refclk-pass";
+                        };
+                        refclkddr3a: refclkddr3a {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <100000000>;
+                                clock-output-names = "refclk-ddr3a";
+                        };
+                };
+        };
+};
+&usb_phy {
+        status = "okay";
+};
+&usb {
+        status = "okay";
+};
+&usb1_phy {
+        status = "okay";
+};
+&usb1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
new file mode 100644
index 000000000000..03d01909525b
--- /dev/null
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Edison soc device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupt-parent = <&gic>;
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <2>;
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <3>;
+                };
+        };
+        soc {
+                /include/ "k2e-clocks.dtsi"
+                usb: usb@2680000 {
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
+                        dwc3@2690000 {
+                                interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
+                        };
+                };
+                usb1_phy: usb_phy@2620750 {
+                        compatible = "ti,keystone-usbphy";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x2620750 24>;
+                        status = "disabled";
+                };
+                usb1: usb@25000000 {
+                        compatible = "ti,keystone-dwc3";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x25000000 0x10000>;
+                        clocks = <&clkusb1>;
+                        clock-names = "usb";
+                        interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
+                        ranges;
+                        status = "disabled";
+                        dwc3@25010000 {
+                                compatible = "synopsys,dwc3";
+                                reg = <0x25010000 0x70000>;
+                                interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
+                                usb-phy = <&usb1_phy>, <&usb1_phy>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi
new file mode 100644
index 000000000000..96e65365afe3
--- /dev/null
+++ b/arch/arm/boot/dts/k2hk-clocks.dtsi
@@ -0,0 +1,426 @@
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Kepler/Hawking SoC clock nodes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+clocks {
+        armpllclk: armpllclk@2620370 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkarm>;
+                clock-output-names = "arm-pll-clk";
+                reg = <0x02620370 4>;
+                reg-names = "control";
+        };
+        mainpllclk: mainpllclk@2310110 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,main-pll-clock";
+                clocks = <&refclksys>;
+                reg = <0x02620350 4>, <0x02310110 4>;
+                reg-names = "control", "multiplier";
+                fixed-postdiv = <2>;
+        };
+        papllclk: papllclk@2620358 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkpass>;
+                clock-output-names = "pa-pll-clk";
+                reg = <0x02620358 4>;
+                reg-names = "control";
+        };
+        ddr3apllclk: ddr3apllclk@2620360 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkddr3a>;
+                clock-output-names = "ddr-3a-pll-clk";
+                reg = <0x02620360 4>;
+                reg-names = "control";
+        };
+        ddr3bpllclk: ddr3bpllclk@2620368 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclkddr3b>;
+                clock-output-names = "ddr-3b-pll-clk";
+                reg = <0x02620368 4>;
+                reg-names = "control";
+        };
+        clktsip: clktsip {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk16>;
+                clock-output-names = "tsip";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+        clksrio: clksrio {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1rstiso13>;
+                clock-output-names = "srio";
+                reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <4>;
+        };
+        clkhyperlink0: clkhyperlink0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "hyperlink-0";
+                reg = <0x02350030 0xb00>, <0x02350014 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <5>;
+        };
+        clkgem1: clkgem1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem1";
+                reg = <0x02350040 0xb00>, <0x02350024 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <9>;
+        };
+        clkgem2: clkgem2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem2";
+                reg = <0x02350044 0xb00>, <0x02350028 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <10>;
+        };
+        clkgem3: clkgem3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem3";
+                reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <11>;
+        };
+        clkgem4: clkgem4 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem4";
+                reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <12>;
+        };
+        clkgem5: clkgem5 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem5";
+                reg = <0x02350050 0xb00>, <0x02350034 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <13>;
+        };
+        clkgem6: clkgem6 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem6";
+                reg = <0x02350054 0xb00>, <0x02350038 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <14>;
+        };
+        clkgem7: clkgem7 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem7";
+                reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <15>;
+        };
+        clkddr31: clkddr31 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "ddr3-1";
+                reg = <0x02350060 0xb00>, <0x02350040 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <16>;
+        };
+        clktac: clktac {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tac";
+                reg = <0x02350064 0xb00>, <0x02350044 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <17>;
+        };
+        clkrac01: clkrac01 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "rac-01";
+                reg = <0x02350068 0xb00>, <0x02350044 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <17>;
+        };
+        clkrac23: clkrac23 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "rac-23";
+                reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <18>;
+        };
+        clkfftc0: clkfftc0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-0";
+                reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <19>;
+        };
+        clkfftc1: clkfftc1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-1";
+                reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <19>;
+        };
+        clkfftc2: clkfftc2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-2";
+                reg = <0x02350078 0xb00>, <0x02350050 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <20>;
+        };
+        clkfftc3: clkfftc3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-3";
+                reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <20>;
+        };
+        clkfftc4: clkfftc4 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-4";
+                reg = <0x02350080 0xb00>, <0x02350050 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <20>;
+        };
+        clkfftc5: clkfftc5 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-5";
+                reg = <0x02350084 0xb00>, <0x02350050 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <20>;
+        };
+        clkaif: clkaif {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "aif";
+                reg = <0x02350088 0xb00>, <0x02350054 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <21>;
+        };
+        clktcp3d0: clktcp3d0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-0";
+                reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <22>;
+        };
+        clktcp3d1: clktcp3d1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-1";
+                reg = <0x02350090 0xb00>, <0x02350058 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <22>;
+        };
+        clktcp3d2: clktcp3d2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-2";
+                reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <23>;
+        };
+        clktcp3d3: clktcp3d3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-3";
+                reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <23>;
+        };
+        clkvcp0: clkvcp0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-0";
+                reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+        clkvcp1: clkvcp1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-1";
+                reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+        clkvcp2: clkvcp2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-2";
+                reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+        clkvcp3: clkvcp3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-3";
+                reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+        clkvcp4: clkvcp4 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-4";
+                reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <25>;
+        };
+        clkvcp5: clkvcp5 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-5";
+                reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <25>;
+        };
+        clkvcp6: clkvcp6 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-6";
+                reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <25>;
+        };
+        clkvcp7: clkvcp7 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-7";
+                reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <25>;
+        };
+        clkbcp: clkbcp {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "bcp";
+                reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <26>;
+        };
+        clkdxb: clkdxb {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "dxb";
+                reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <27>;
+        };
+        clkhyperlink1: clkhyperlink1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "hyperlink-1";
+                reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <28>;
+        };
+        clkxge: clkxge {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "xge";
+                reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <29>;
+        };
+};
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
index eaefdfef65c3..c93d06f9f2a8 100644
--- a/arch/arm/boot/dts/k2hk-evm.dts
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Texas Instruments, Inc.
+ * Copyright 2013-2014 Texas Instruments, Inc.
 *
 * Keystone 2 Kepler/Hawking EVM device tree
 *
@@ -10,12 +10,14 @@
 /dts-v1/;
 #include "keystone.dtsi"
+#include "k2hk.dtsi"
 / {
-        compatible =  "ti,keystone-evm";
+        compatible =  "ti,k2hk-evm","ti,keystone";
+        model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
        soc {
-                clock {
+                clocks {
                        refclksys: refclksys {
                                #clock-cells = <0>;
                                compatible = "fixed-clock";
@@ -52,6 +54,29 @@
                        };
                };
        };
+        leds {
+                compatible = "gpio-leds";
+                debug1_1 {
+                        label = "keystone:green:debug1";
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
+                };
+                debug1_2 {
+                        label = "keystone:red:debug1";
+                        gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
+                };
+                debug2 {
+                        label = "keystone:blue:debug2";
+                        gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
+                };
+                debug3 {
+                        label = "keystone:blue:debug3";
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
+                };
+        };
 };
 &usb_phy {
@@ -61,3 +86,55 @@
 &usb {
        status = "okay";
 };
+&aemif {
+        cs0 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                clock-ranges;
+                ranges;
+                ti,cs-chipselect = <0>;
+                /* all timings in nanoseconds */
+                ti,cs-min-turnaround-ns = <12>;
+                ti,cs-read-hold-ns = <6>;
+                ti,cs-read-strobe-ns = <23>;
+                ti,cs-read-setup-ns = <9>;
+                ti,cs-write-hold-ns = <8>;
+                ti,cs-write-strobe-ns = <23>;
+                ti,cs-write-setup-ns = <8>;
+                nand@0,0 {
+                        compatible = "ti,keystone-nand","ti,davinci-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0 0 0x4000000
+                               1 0 0x0000100>;
+                        ti,davinci-chipselect = <0>;
+                        ti,davinci-mask-ale = <0x2000>;
+                        ti,davinci-mask-cle = <0x4000>;
+                        ti,davinci-mask-chipsel = <0>;
+                        nand-ecc-mode = "hw";
+                        ti,davinci-ecc-bits = <4>;
+                        nand-on-flash-bbt;
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0 0x100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "params";
+                                reg = <0x100000 0x80000>;
+                                read-only;
+                        };
+                        partition@180000 {
+                                label = "ubifs";
+                                reg = <0x180000 0x1fe80000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi
new file mode 100644
index 000000000000..c73899c73118
--- /dev/null
+++ b/arch/arm/boot/dts/k2hk.dtsi
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Kepler/Hawking soc specific device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupt-parent = <&gic>;
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <2>;
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <3>;
+                };
+        };
+        soc {
+                /include/ "k2hk-clocks.dtsi"
+        };
+};
diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi
new file mode 100644
index 000000000000..f584b80200f8
--- /dev/null
+++ b/arch/arm/boot/dts/k2l-clocks.dtsi
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 lamarr SoC clock nodes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+clocks {
+        armpllclk: armpllclk@2620370 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclksys>;
+                clock-output-names = "arm-pll-clk";
+                reg = <0x02620370 4>;
+                reg-names = "control";
+        };
+        mainpllclk: mainpllclk@2310110 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,main-pll-clock";
+                clocks = <&refclksys>;
+                reg = <0x02620350 4>, <0x02310110 4>;
+                reg-names = "control", "multiplier";
+                fixed-postdiv = <2>;
+        };
+        papllclk: papllclk@2620358 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclksys>;
+                clock-output-names = "pa-pll-clk";
+                reg = <0x02620358 4>;
+                reg-names = "control";
+        };
+        ddr3apllclk: ddr3apllclk@2620360 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,pll-clock";
+                clocks = <&refclksys>;
+                clock-output-names = "ddr-3a-pll-clk";
+                reg = <0x02620360 4>;
+                reg-names = "control";
+        };
+        clkdfeiqnsys: clkdfeiqnsys {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "dfe";
+                reg-names = "control", "domain";
+                reg = <0x02350004 0xb00>, <0x02350000 0x400>;
+                domain-id = <0>;
+        };
+        clkpcie1: clkpcie1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk12>;
+                clock-output-names = "pcie";
+                reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <4>;
+        };
+        clkgem1: clkgem1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem1";
+                reg = <0x02350040 0xb00>, <0x02350024 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <9>;
+        };
+        clkgem2: clkgem2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem2";
+                reg = <0x02350044 0xb00>, <0x02350028 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <10>;
+        };
+        clkgem3: clkgem3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk1>;
+                clock-output-names = "gem3";
+                reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <11>;
+        };
+        clktac: clktac {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tac";
+                reg = <0x02350064 0xb00>, <0x02350044 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <17>;
+        };
+        clkrac: clkrac {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "rac";
+                reg = <0x02350068 0xb00>, <0x02350044 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <17>;
+        };
+        clkdfepd0: clkdfepd0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "dfe-pd0";
+                reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <18>;
+        };
+        clkfftc0: clkfftc0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-0";
+                reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <19>;
+        };
+        clkosr: clkosr {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "osr";
+                reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <21>;
+        };
+        clktcp3d0: clktcp3d0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-0";
+                reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <22>;
+        };
+        clktcp3d1: clktcp3d1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "tcp3d-1";
+                reg = <0x02350094 0xb00>, <0x02350058 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <23>;
+        };
+        clkvcp0: clkvcp0 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-0";
+                reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+        clkvcp1: clkvcp1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-1";
+                reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+        clkvcp2: clkvcp2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-2";
+                reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+        clkvcp3: clkvcp3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "vcp-3";
+                reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <24>;
+        };
+        clkbcp: clkbcp {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "bcp";
+                reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <26>;
+        };
+        clkdfepd1: clkdfepd1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "dfe-pd1";
+                reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <27>;
+        };
+        clkfftc1: clkfftc1 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "fftc-1";
+                reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <28>;
+        };
+        clkiqnail: clkiqnail {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&chipclk13>;
+                clock-output-names = "iqn-ail";
+                reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <29>;
+        };
+        clkuart2: clkuart2 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "uart2";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+        clkuart3: clkuart3 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "uart3";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts
new file mode 100644
index 000000000000..50a70132ac9e
--- /dev/null
+++ b/arch/arm/boot/dts/k2l-evm.dts
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Lamarr EVM device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "keystone.dtsi"
+#include "k2l.dtsi"
+/ {
+        compatible =  "ti,k2l-evm","ti,keystone";
+        model = "Texas Instruments Keystone 2 Lamarr EVM";
+        soc {
+                clocks {
+                        refclksys: refclksys {
+                                #clock-cells = <0>;
+                                compatible = "fixed-clock";
+                                clock-frequency = <122880000>;
+                                clock-output-names = "refclk-sys";
+                        };
+                };
+        };
+};
+&usb_phy {
+        status = "okay";
+};
+&usb {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi
new file mode 100644
index 000000000000..1f7f479589e1
--- /dev/null
+++ b/arch/arm/boot/dts/k2l.dtsi
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Lamarr SoC specific device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupt-parent = <&gic>;
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+        soc {
+                /include/ "k2l-clocks.dtsi"
+                uart2: serial@02348400 {
+                        compatible = "ns16550a";
+                        current-speed = <115200>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        reg = <0x02348400 0x100>;
+                        clocks  = <&clkuart2>;
+                        interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
+                };
+                uart3:  serial@02348800 {
+                        compatible = "ns16550a";
+                        current-speed = <115200>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        reg = <0x02348800 0x100>;
+                        clocks  = <&clkuart3>;
+                        interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index ef58d1c24313..93f82c7010ab 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -13,51 +13,6 @@ clocks {
        #size-cells = <1>;
        ranges;
-        mainpllclk: mainpllclk@2310110 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,main-pll-clock";
-                clocks = <&refclksys>;
-                reg = <0x02620350 4>, <0x02310110 4>;
-                reg-names = "control", "multiplier";
-                fixed-postdiv = <2>;
-        };
-        papllclk: papllclk@2620358 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkpass>;
-                clock-output-names = "pa-pll-clk";
-                reg = <0x02620358 4>;
-                reg-names = "control";
-        };
-        ddr3apllclk: ddr3apllclk@2620360 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkddr3a>;
-                clock-output-names = "ddr-3a-pll-clk";
-                reg = <0x02620360 4>;
-                reg-names = "control";
-        };
-        ddr3bpllclk: ddr3bpllclk@2620368 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkddr3b>;
-                clock-output-names = "ddr-3b-pll-clk";
-                reg = <0x02620368 4>;
-                reg-names = "control";
-        };
-        armpllclk: armpllclk@2620370 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,pll-clock";
-                clocks = <&refclkarm>;
-                clock-output-names = "arm-pll-clk";
-                reg = <0x02620370 4>;
-                reg-names = "control";
-        };
        mainmuxclk: mainmuxclk@2310108 {
                #clock-cells = <0>;
                compatible = "ti,keystone,pll-mux-clock";
@@ -244,7 +199,7 @@ clocks {
                clock-output-names = "debugss-trc";
                reg = <0x02350014 0xb00>, <0x02350000 0x400>;
                reg-names = "control", "domain";
-                domain-id = <0>;
+                domain-id = <1>;
        };
        clktetbtrc: clktetbtrc {
@@ -297,26 +252,6 @@ clocks {
                domain-id = <3>;
        };
-        clksrio: clksrio {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk1rstiso13>;
-                clock-output-names = "srio";
-                reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <4>;
-        };
-        clkhyperlink0: clkhyperlink0 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk12>;
-                clock-output-names = "hyperlink-0";
-                reg = <0x02350030 0xb00>, <0x02350014 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <5>;
-        };
        clksr: clksr {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
@@ -327,16 +262,6 @@ clocks {
                domain-id = <6>;
        };
-        clkmsmcsram: clkmsmcsram {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk1>;
-                clock-output-names = "msmcsram";
-                reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <7>;
-        };
        clkgem0: clkgem0 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
@@ -347,76 +272,6 @@ clocks {
                domain-id = <8>;
        };
-        clkgem1: clkgem1 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk1>;
-                clock-output-names = "gem1";
-                reg = <0x02350040 0xb00>, <0x02350024 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <9>;
-        };
-        clkgem2: clkgem2 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk1>;
-                clock-output-names = "gem2";
-                reg = <0x02350044 0xb00>, <0x02350028 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <10>;
-        };
-        clkgem3: clkgem3 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk1>;
-                clock-output-names = "gem3";
-                reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <11>;
-        };
-        clkgem4: clkgem4 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk1>;
-                clock-output-names = "gem4";
-                reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <12>;
-        };
-        clkgem5: clkgem5 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk1>;
-                clock-output-names = "gem5";
-                reg = <0x02350050 0xb00>, <0x02350034 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <13>;
-        };
-        clkgem6: clkgem6 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk1>;
-                clock-output-names = "gem6";
-                reg = <0x02350054 0xb00>, <0x02350038 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <14>;
-        };
-        clkgem7: clkgem7 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk1>;
-                clock-output-names = "gem7";
-                reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <15>;
-        };
        clkddr30: clkddr30 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
@@ -427,276 +282,6 @@ clocks {
                domain-id = <16>;
        };
-        clkddr31: clkddr31 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "ddr3-1";
-                reg = <0x02350060 0xb00>, <0x02350040 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <16>;
-        };
-        clktac: clktac {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "tac";
-                reg = <0x02350064 0xb00>, <0x02350044 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <17>;
-        };
-        clkrac01: clktac01 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "rac-01";
-                reg = <0x02350068 0xb00>, <0x02350044 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <17>;
-        };
-        clkrac23: clktac23 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "rac-23";
-                reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <18>;
-        };
-        clkfftc0: clkfftc0 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "fftc-0";
-                reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <19>;
-        };
-        clkfftc1: clkfftc1 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "fftc-1";
-                reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <19>;
-        };
-        clkfftc2: clkfftc2 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "fftc-2";
-                reg = <0x02350078 0xb00>, <0x02350050 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <20>;
-        };
-        clkfftc3: clkfftc3 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "fftc-3";
-                reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <20>;
-        };
-        clkfftc4: clkfftc4 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "fftc-4";
-                reg = <0x02350080 0xb00>, <0x02350050 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <20>;
-        };
-        clkfftc5: clkfftc5 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "fftc-5";
-                reg = <0x02350084 0xb00>, <0x02350050 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <20>;
-        };
-        clkaif: clkaif {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "aif";
-                reg = <0x02350088 0xb00>, <0x02350054 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <21>;
-        };
-        clktcp3d0: clktcp3d0 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "tcp3d-0";
-                reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <22>;
-        };
-        clktcp3d1: clktcp3d1 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "tcp3d-1";
-                reg = <0x02350090 0xb00>, <0x02350058 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <22>;
-        };
-        clktcp3d2: clktcp3d2 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "tcp3d-2";
-                reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <23>;
-        };
-        clktcp3d3: clktcp3d3 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "tcp3d-3";
-                reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <23>;
-        };
-        clkvcp0: clkvcp0 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "vcp-0";
-                reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <24>;
-        };
-        clkvcp1: clkvcp1 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "vcp-1";
-                reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <24>;
-        };
-        clkvcp2: clkvcp2 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "vcp-2";
-                reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <24>;
-        };
-        clkvcp3: clkvcp3 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "vcp-3";
-                reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <24>;
-        };
-        clkvcp4: clkvcp4 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "vcp-4";
-                reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <25>;
-        };
-        clkvcp5: clkvcp5 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "vcp-5";
-                reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <25>;
-        };
-        clkvcp6: clkvcp6 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "vcp-6";
-                reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <25>;
-        };
-        clkvcp7: clkvcp7 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "vcp-7";
-                reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <25>;
-        };
-        clkbcp: clkbcp {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "bcp";
-                reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <26>;
-        };
-        clkdxb: clkdxb {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "dxb";
-                reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <27>;
-        };
-        clkhyperlink1: clkhyperlink1 {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk12>;
-                clock-output-names = "hyperlink-1";
-                reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <28>;
-        };
-        clkxge: clkxge {
-                #clock-cells = <0>;
-                compatible = "ti,keystone,psc-clock";
-                clocks = <&chipclk13>;
-                clock-output-names = "xge";
-                reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
-                reg-names = "control", "domain";
-                domain-id = <29>;
-        };
        clkwdtimer0: clkwdtimer0 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
@@ -737,6 +322,16 @@ clocks {
                domain-id = <0>;
        };
+        clktimer15: clktimer15 {
+                #clock-cells = <0>;
+                compatible = "ti,keystone,psc-clock";
+                clocks = <&clkmodrst0>;
+                clock-output-names = "timer15";
+                reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+                reg-names = "control", "domain";
+                domain-id = <0>;
+        };
        clkuart0: clkuart0 {
                #clock-cells = <0>;
                compatible = "ti,keystone,psc-clock";
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index b4202907a27b..90823eb90c1b 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -7,6 +7,7 @@
 */
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "skeleton.dtsi"
@@ -24,37 +25,6 @@
                reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                interrupt-parent = <&gic>;
-                cpu@0 {
-                        compatible = "arm,cortex-a15";
-                        device_type = "cpu";
-                        reg = <0>;
-                };
-                cpu@1 {
-                        compatible = "arm,cortex-a15";
-                        device_type = "cpu";
-                        reg = <1>;
-                };
-                cpu@2 {
-                        compatible = "arm,cortex-a15";
-                        device_type = "cpu";
-                        reg = <2>;
-                };
-                cpu@3 {
-                        compatible = "arm,cortex-a15";
-                        device_type = "cpu";
-                        reg = <3>;
-                };
-        };
        gic: interrupt-controller {
                compatible = "arm,cortex-a15-gic";
                #interrupt-cells = <3>;
@@ -208,5 +178,75 @@
                                usb-phy = <&usb_phy>, <&usb_phy>;
                        };
                };
+                wdt: wdt@022f0080 {
+                        compatible = "ti,keystone-wdt","ti,davinci-wdt";
+                        reg = <0x022f0080 0x80>;
+                        clocks = <&clkwdtimer0>;
+                };
+                clock_event: timer@22f0000 {
+                        compatible = "ti,keystone-timer";
+                        reg = <0x022f0000 0x80>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
+                        clocks = <&clktimer15>;
+                };
+                gpio0: gpio@260bf00 {
+                        compatible = "ti,keystone-gpio";
+                        reg = <0x0260bf00 0x100>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        /* HW Interrupts mapped to GPIO pins */
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+                        clocks = <&clkgpio>;
+                        clock-names = "gpio";
+                        ti,ngpio = <32>;
+                        ti,davinci-gpio-unbanked = <32>;
+                };
+                aemif: aemif@21000A00 {
+                        compatible = "ti,keystone-aemif", "ti,davinci-aemif";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        clocks = <&clkaemif>;
+                        clock-names = "aemif";
+                        clock-ranges;
+                        reg = <0x21000A00 0x00000100>;
+                        ranges = <0 0 0x30000000 0x10000000
+                                  1 0 0x21000A00 0x00000100>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts
new file mode 100644
index 000000000000..40791053106b
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-b3.dts
@@ -0,0 +1,204 @@
+/*
+ * Device Tree file for Excito Bubba B3
+ *
+ * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Note: This requires a new'ish version of u-boot, which disables the
+ * L2 cache. If your B3 silently fails to boot, u-boot is probably too
+ * old. Either upgrade, or consider the following email:
+ *
+ * http://lists.debian.org/debian-arm/2012/08/msg00128.html
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+/ {
+        model = "Excito B3";
+        compatible = "excito,b3", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory { /* 512 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        /* Wifi model has Atheros chipset on pcie port */
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pmx_button_power: pmx-button-power {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_green: pmx-led-green {
+                                marvell,pins = "mpp38";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_red: pmx-led-red {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue: pmx-led-blue {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_beeper: pmx-beeper {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
+                };
+                spi@10600 {
+                        status = "okay";
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
+                        m25p16@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "m25p16";
+                                reg = <0>;
+                                spi-max-frequency = <40000000>;
+                                mode = <0>;
+                                partition@0 {
+                                        reg = <0x0 0xc0000>;
+                                        label = "u-boot";
+                                };
+                                partition@c0000 {
+                                        reg = <0xc0000 0x20000>;
+                                        label = "u-boot env";
+                                };
+                                partition@e0000 {
+                                        reg = <0xe0000 0x120000>;
+                                        label = "data";
+                                };
+                        };
+                };
+                i2c@11000 {
+                        status = "okay";
+                        /*
+                         * There is something on the bus at address 0x64.
+                         * Not yet identified what it is, maybe the eeprom
+                         * for the Atheros WiFi chip?
+                         */
+                };
+                serial@12000 {
+                        /* Internal on test pins, 3.3v TTL
+                         * UART0_RX = Testpoint 65
+                         * UART0_TX = Testpoint 66
+                         * See the Excito Wiki for more details.
+                         */
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+                sata@80000 {
+                        /* One internal, the second as eSATA */
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+        };
+        gpio-leds {
+                /*
+                 * There is one LED "port" on the front and the colours
+                 * mix together giving some interesting combinations.
+                 */
+                compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_green &pmx_led_red
+                              &pmx_led_blue >;
+                pinctrl-names = "default";
+                programming_led {
+                        label = "bubba3:green:programming";
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+                error_led {
+                        label = "bubba3:red:error";
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                };
+                active_led {
+                        label = "bubba3:blue:active";
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pmx_button_power>;
+                pinctrl-names = "default";
+                power-button {
+                        /* On the back */
+                        label = "Power Button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+                };
+        };
+        beeper: beeper {
+                /* 4KHz Piezoelectric buzzer */
+                compatible = "gpio-beeper";
+                pinctrl-0 = <&pmx_beeper>;
+                pinctrl-names = "default";
+                gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@8 {
+                device_type = "ethernet-phy";
+                reg = <8>;
+        };
+        ethphy1: ethernet-phy@24 {
+                device_type = "ethernet-phy";
+                reg = <24>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
+&eth1 {
+        status = "okay";
+        ethernet1-port@0 {
+                phy-handle = <&ethphy1>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts
new file mode 100644
index 000000000000..772092c94ca3
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds109.dts
@@ -0,0 +1,41 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS109, DS110, DS110jv20";
+        compatible = "synology,ds109", "synology,ds110jv20",
+                     "synology,ds110", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-150-32-35 {
+                status = "okay";
+        };
+        gpio-leds-hdd-21-1 {
+                status = "okay";
+        };
+};
+&rs5c372 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
new file mode 100644
index 000000000000..aabafbe0da4c
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
@@ -0,0 +1,41 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS110j v10 and v30";
+        compatible = "synology,ds110jv10", "synology,ds110jv30",
+                     "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-150-32-35 {
+                status = "okay";
+        };
+        gpio-leds-hdd-21-1 {
+                status = "okay";
+        };
+};
+&s35390a {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts
new file mode 100644
index 000000000000..16ec7fbab573
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds111.dts
@@ -0,0 +1,44 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS111";
+        compatible = "synology,ds111", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-100-15-35-1 {
+                status = "okay";
+        };
+        gpio-leds-hdd-21-1 {
+                status = "okay";
+        };
+};
+&s35390a {
+        status = "okay";
+};
+&pcie2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts
new file mode 100644
index 000000000000..cff1b2388765
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds112.dts
@@ -0,0 +1,48 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS111";
+        compatible = "synology,ds111", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-100-15-35-1 {
+                status = "okay";
+        };
+        gpio-leds-21-2 {
+                status = "okay";
+        };
+        regulators-hdd-30 {
+                status = "okay";
+        };
+};
+&s35390a {
+        status = "okay";
+};
+&pcie2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts
new file mode 100644
index 000000000000..330411993d38
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds209.dts
@@ -0,0 +1,44 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS209";
+        compatible = "synology,ds209", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-150-32-35 {
+                status = "okay";
+        };
+        gpio-leds-hdd-21-2 {
+                status = "okay";
+        };
+        regulators-hdd-31 {
+                status = "okay";
+        };
+};
+&rs5c372 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts
new file mode 100644
index 000000000000..6052eaa37d4f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds210.dts
@@ -0,0 +1,46 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS210 v10, v20, v30, DS211j";
+        compatible = "synology,ds210jv10", "synology,ds210jv20",
+                     "synology,ds210jv30", "synology,ds211j",
+                     "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-150-32-35 {
+                status = "okay";
+        };
+        gpio-leds-hdd-21-2 {
+                status = "okay";
+        };
+        regulators-hdd-31 {
+                status = "okay";
+        };
+};
+&s35390a {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts
new file mode 100644
index 000000000000..7f76cd30e84e
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds212.dts
@@ -0,0 +1,47 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10";
+        compatible = "synology,ds212", "synology,ds212pv10",
+                     "synology,ds212pv10", "synology,ds212pv20",
+                     "synology,ds213airv10", "synology,ds213v10",
+                     "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-100-15-35-1 {
+                status = "okay";
+        };
+        gpio-leds-hdd-21-2 {
+                status = "okay";
+        };
+};
+&s35390a {
+        status = "okay";
+};
+&pcie2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts
new file mode 100644
index 000000000000..1f83a00f1f74
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds212j.dts
@@ -0,0 +1,41 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS212j v10, v20";
+        compatible = "synology,ds212jv10", "synology,ds212jv20",
+                     "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-100-32-35 {
+                status = "okay";
+        };
+        gpio-leds-hdd-21-2 {
+                status = "okay";
+        };
+};
+&s35390a {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts
new file mode 100644
index 000000000000..0a573add44a2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds409.dts
@@ -0,0 +1,48 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS409, DS410j";
+        compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-150-15-18 {
+                status = "okay";
+        };
+        gpio-leds-hdd-36 {
+                status = "okay";
+        };
+        gpio-leds-alarm-12 {
+                status = "okay";
+        };
+};
+&eth1 {
+        status = "okay";
+};
+&rs5c372 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts
new file mode 100644
index 000000000000..1848a6245fd3
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts
@@ -0,0 +1,40 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology 409slim";
+        compatible = "synology,ds409slim", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-150-32-35 {
+                status = "okay";
+        };
+        gpio-leds-hdd-20 {
+                status = "okay";
+        };
+};
+&rs5c372 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts
new file mode 100644
index 000000000000..a1737b4311c6
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds411.dts
@@ -0,0 +1,52 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS411, DS413jv10";
+        compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-100-15-35-1 {
+                status = "okay";
+        };
+        gpio-leds-hdd-36 {
+                status = "okay";
+        };
+        regulators-hdd-34 {
+                status = "okay";
+        };
+};
+&eth1 {
+        status = "okay";
+};
+&s35390a {
+        status = "okay";
+};
+&pcie2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts
new file mode 100644
index 000000000000..0cde914eceae
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds411j.dts
@@ -0,0 +1,48 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS411j";
+        compatible = "synology,ds411j", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-150-15-18 {
+                status = "okay";
+        };
+        gpio-leds-hdd-36 {
+                status = "okay";
+        };
+        gpio-leds-alarm-12 {
+                status = "okay";
+        };
+};
+&eth1 {
+        status = "okay";
+};
+&s35390a {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts
new file mode 100644
index 000000000000..aef0cadc2c78
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts
@@ -0,0 +1,48 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology DS411slim";
+        compatible = "synology,ds411slim", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-100-15-35-1 {
+                status = "okay";
+        };
+        gpio-leds-hdd-36 {
+                status = "okay";
+        };
+};
+&eth1 {
+        status = "okay";
+};
+&s35390a {
+        status = "okay";
+};
+&pcie2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index dc86429756d7..2cb0dc529165 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -122,4 +122,66 @@
                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                };
        };
+        dsa@0 {
+                compatible = "marvell,dsa";
+                #address-cells = <2>;
+                #size-cells = <0>;
+                dsa,ethernet = <&eth0>;
+                dsa,mii-bus = <&ethphy0>;
+                switch@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0>;    /* MDIO address 0, switch 0 in tree */
+                        port@0 {
+                                reg = <0>;
+                                label = "lan1";
+                        };
+                        port@1 {
+                                reg = <1>;
+                                label = "lan2";
+                        };
+                        port@2 {
+                                reg = <2>;
+                                label = "lan3";
+                        };
+                        port@3 {
+                                reg = <3>;
+                                label = "lan4";
+                        };
+                        port@4 {
+                                reg = <4>;
+                                label = "wan";
+                        };
+                        port@5 {
+                                reg = <5>;
+                                label = "cpu";
+                        };
+                };
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@ff {
+                reg = <0xff>;   /* No phy attached */
+                speed = <1000>;
+                duplex = <1>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
new file mode 100644
index 000000000000..e9dd85049297
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
@@ -0,0 +1,112 @@
+/*
+ * Marvell RD88F6192 Board descrition
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common between the three
+ * variants of the Marvell Kirkwood Development Board.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6192.dtsi"
+/ {
+        model = "Marvell RD88F6192 reference design";
+        compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = <&pmx_usb_power>;
+                        pinctrl-names = "default";
+                        pmx_usb_power: pmx-usb-power {
+                                marvell,pins = "mpp10";
+                                marvell,function = "gpo";
+                        };
+                };
+                serial@12000 {
+                        status = "okay";
+                };
+                spi@10600 {
+                        status = "okay";
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
+                        m25p128@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "st,m25p128";
+                                reg = <0>;
+                                spi-max-frequency = <20000000>;
+                                mode = <0>;
+                        };
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power>;
+                pinctrl-names = "default";
+                usb_power: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "USB VBUS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@8 {
+                reg = <8>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
+\ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts
new file mode 100644
index 000000000000..a803bbb70bc8
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts
@@ -0,0 +1,26 @@
+/*
+ * Marvell RD88F6181 A0 Board descrition
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions for the board with the A0 variant of
+ * the SoC. The ethernet switch does not have a "wan" port.
+ */
+/dts-v1/;
+#include "kirkwood-rd88f6281.dtsi"
+/ {
+        model = "Marvell RD88f6281 Reference design, with A0 SoC";
+        compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
+        dsa@0 {
+                switch@0 {
+                        reg = <10 0>;    /* MDIO address 10, switch 0 in tree */
+                };
+        };
+};
+\ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts
new file mode 100644
index 000000000000..baeebbf1d8c7
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts
@@ -0,0 +1,31 @@
+/*
+ * Marvell RD88F6181 A1 Board descrition
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions for the board with the A1 variant of
+ * the SoC. The ethernet switch has a "wan" port.
+ */
+/dts-v1/;
+#include "kirkwood-rd88f6281.dtsi"
+/ {
+        model = "Marvell RD88f6281 Reference design, with A1 SoC";
+        compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
+        dsa@0 {
+                switch@0 {
+                        reg = <0 0>;    /* MDIO address 0, switch 0 in tree */
+                        port@4 {
+                                reg = <4>;
+                                label = "wan";
+                        };
+                };
+        };
+};
+\ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
new file mode 100644
index 000000000000..d6368c39102e
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
@@ -0,0 +1,152 @@
+/*
+ * Marvell RD88F6181 Common Board descrition
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common between the two
+ * variants of the Marvell Kirkwood Development Board.
+ */
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = <&pmx_sdio_cd>;
+                        pinctrl-names = "default";
+                        pmx_sdio_cd: pmx-sdio-cd {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                };
+                serial@12000 {
+                        status = "okay";
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+                        /* No WP GPIO */
+                };
+        };
+        dsa@0 {
+                compatible = "marvell,dsa";
+                #address-cells = <2>;
+                #size-cells = <0>;
+                dsa,ethernet = <&eth0>;
+                dsa,mii-bus = <&ethphy1>;
+                switch@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                label = "lan1";
+                        };
+                        port@1 {
+                                reg = <1>;
+                                label = "lan2";
+                        };
+                        port@2 {
+                                reg = <2>;
+                                label = "lan3";
+                        };
+                        port@3 {
+                                reg = <3>;
+                                label = "lan4";
+                        };
+                        port@5 {
+                                reg = <5>;
+                                label = "cpu";
+                        };
+                };
+       };
+};
+&nand {
+        status = "okay";
+        partition@0 {
+                label = "u-boot";
+                reg = <0x0000000 0x100000>;
+                read-only;
+        };
+        partition@100000 {
+                label = "uImage";
+                reg = <0x0100000 0x200000>;
+        };
+        partition@300000 {
+                label = "data";
+                reg = <0x0300000 0x500000>;
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+        ethphy1: ethernet-phy@ff {
+                reg = <0xff>; /* No PHY attached */
+                speed = <1000>;
+                duple = <1>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
+&eth1 {
+        status = "okay";
+        ethernet1-port@0 {
+                phy-handle = <&ethphy1>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts
new file mode 100644
index 000000000000..93ec3d00c6ab
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rs212.dts
@@ -0,0 +1,48 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology RS212";
+        compatible = "synology,rs212", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-100-15-35-3 {
+                status = "okay";
+        };
+        gpio-leds-hdd-38 {
+                status = "okay";
+        };
+        regulators-hdd-30-2 {
+                status = "okay";
+        };
+};
+&s35390a {
+        status = "okay";
+};
+&pcie2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts
new file mode 100644
index 000000000000..311df4e5aa28
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rs409.dts
@@ -0,0 +1,44 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology RS409";
+        compatible = "synology,rs409", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-150-15-18 {
+                status = "okay";
+        };
+        gpio-leds-hdd-36 {
+                status = "okay";
+        };
+};
+&eth1 {
+        status = "okay";
+};
+&rs5c372 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts
new file mode 100644
index 000000000000..f90da850bb31
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rs411.dts
@@ -0,0 +1,44 @@
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-synology.dtsi"
+/ {
+        model = "Synology RS411 RS812";
+        compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        gpio-fan-100-15-35-3 {
+                status = "okay";
+        };
+        gpio-leds-hdd-36 {
+                status = "okay";
+        };
+};
+&eth1 {
+        status = "okay";
+};
+&s35390a {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi
new file mode 100644
index 000000000000..4227c974729d
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-synology.dtsi
@@ -0,0 +1,871 @@
+/*
+ * Nodes for Marvell 628x Synology devices
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/ {
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                        pcie2: pcie@2,0 {
+                                status = "disabled";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pmx_alarmled_12: pmx-alarmled-12 {
+                                marvell,pins = "mpp12";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fanctrl_15: pmx-fanctrl-15 {
+                                marvell,pins = "mpp15";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fanctrl_16: pmx-fanctrl-16 {
+                                marvell,pins = "mpp16";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fanctrl_17: pmx-fanctrl-17 {
+                                marvell,pins = "mpp17";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fanalarm_18: pmx-fanalarm-18 {
+                                marvell,pins = "mpp18";
+                                marvell,function = "gpo";
+                        };
+                        pmx_hddled_20: pmx-hddled-20 {
+                                marvell,pins = "mpp20";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_21: pmx-hddled-21 {
+                                marvell,pins = "mpp21";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_22: pmx-hddled-22 {
+                                marvell,pins = "mpp22";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_23: pmx-hddled-23 {
+                                marvell,pins = "mpp23";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_24: pmx-hddled-24 {
+                                marvell,pins = "mpp24";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_25: pmx-hddled-25 {
+                                marvell,pins = "mpp25";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_26: pmx-hddled-26 {
+                                marvell,pins = "mpp26";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_27: pmx-hddled-27 {
+                                marvell,pins = "mpp27";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_28: pmx-hddled-28 {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hdd1_pwr_30: pmx-hdd-pwr-30 {
+                                marvell,pins = "mpp30";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 {
+                                marvell,pins = "mpp31";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fanctrl_32: pmx-fanctrl-32 {
+                                marvell,pins = "mpp32";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fanctrl_33: pmx-fanctrl-33 {
+                                marvell,pins = "mpp33";
+                                marvell,function = "gpo";
+                        };
+                        pmx_fanctrl_34: pmx-fanctrl-34 {
+                                marvell,pins = "mpp34";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 {
+                                marvell,pins = "mpp34";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fanalarm_35: pmx-fanalarm-35 {
+                                marvell,pins = "mpp35";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_36: pmx-hddled-36 {
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_37: pmx-hddled-37 {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_38: pmx-hddled-38 {
+                                marvell,pins = "mpp38";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_39: pmx-hddled-39 {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_40: pmx-hddled-40 {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_41: pmx-hddled-41 {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_42: pmx-hddled-42 {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_43: pmx-hddled-43 {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_44: pmx-hddled-44 {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hddled_45: pmx-hddled-45 {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fanalarm_44: pmx-fanalarm-44 {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_fanalarm_45: pmx-fanalarm-45 {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                };
+                rtc@10300 {
+                        status = "disabled";
+                };
+                spi@10600 {
+                        status = "okay";
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
+                        m25p80@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "st,m25p80";
+                                reg = <0>;
+                                spi-max-frequency = <20000000>;
+                                mode = <0>;
+                                partition@00000000 {
+                                        reg = <0x00000000 0x00080000>;
+                                        label = "RedBoot";
+                                };
+                                partition@00080000 {
+                                        reg = <0x00080000 0x00200000>;
+                                        label = "zImage";
+                                };
+                                partition@00280000 {
+                                        reg = <0x00280000 0x00140000>;
+                                        label = "rd.gz";
+                                };
+                                partition@003c0000 {
+                                        reg = <0x003c0000 0x00010000>;
+                                        label = "vendor";
+                                };
+                                partition@003d0000 {
+                                        reg = <0x003d0000 0x00020000>;
+                                        label = "RedBoot config";
+                                };
+                                partition@003f0000 {
+                                        reg = <0x003f0000 0x00010000>;
+                                        label = "FIS directory";
+                                };
+                        };
+                };
+                i2c@11000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
+                        rs5c372: rs5c372@32 {
+                                status = "disabled";
+                                compatible = "ricoh,rs5c372";
+                                reg = <0x32>;
+                        };
+                        s35390a: s35390a@30 {
+                                status = "disabled";
+                                compatible = "ssi,s35390a";
+                                reg = <0x30>;
+                        };
+                };
+                serial@12000 {
+                        status = "okay";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                };
+                serial@12100 {
+                        status = "okay";
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
+                };
+                poweroff@12100 {
+                        compatible = "synology,power-off";
+                        reg = <0x12100 0x100>;
+                        clocks = <&gate_clk 7>;
+                };
+                sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+        };
+        gpio-fan-150-32-35 {
+                status = "disabled";
+                compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
+                             &pmx_fanalarm_35>;
+                pinctrl-names = "default";
+                gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
+                         &gpio1 1 GPIO_ACTIVE_HIGH
+                         &gpio1 2 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <    0 0
+                                       2200 1
+                                       2500 2
+                                       3000 4
+                                       3300 3
+                                       3700 5
+                                       3800 6
+                                       4200 7 >;
+        };
+        gpio-fan-150-15-18 {
+                status = "disabled";
+                compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
+                             &pmx_fanalarm_18>;
+                pinctrl-names = "default";
+                gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
+                         &gpio0 16 GPIO_ACTIVE_HIGH
+                         &gpio0 17 GPIO_ACTIVE_HIGH>;
+                alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <    0 0
+                                       2200 1
+                                       2500 2
+                                       3000 4
+                                       3300 3
+                                       3700 5
+                                       3800 6
+                                       4200 7 >;
+        };
+        gpio-fan-100-32-35 {
+                status = "disabled";
+                compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
+                             &pmx_fanalarm_35>;
+                pinctrl-names = "default";
+                gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
+                         &gpio1 1 GPIO_ACTIVE_HIGH
+                         &gpio1 2 GPIO_ACTIVE_HIGH>;
+                alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <    0 0
+                                       2500 1
+                                       3100 2
+                                       3800 3
+                                       4600 4
+                                       4800 5
+                                       4900 6
+                                       5000 7 >;
+        };
+        gpio-fan-100-15-18 {
+                status = "disabled";
+                compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
+                             &pmx_fanalarm_18>;
+                pinctrl-names = "default";
+                gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
+                         &gpio0 16 GPIO_ACTIVE_HIGH
+                         &gpio0 17 GPIO_ACTIVE_HIGH>;
+                alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <    0 0
+                                       2500 1
+                                       3100 2
+                                       3800 3
+                                       4600 4
+                                       4800 5
+                                       4900 6
+                                       5000 7 >;
+        };
+        gpio-fan-100-15-35-1 {
+                status = "disabled";
+                compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
+                             &pmx_fanalarm_35>;
+                pinctrl-names = "default";
+                gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
+                         &gpio0 16 GPIO_ACTIVE_HIGH
+                         &gpio0 17 GPIO_ACTIVE_HIGH>;
+                alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <    0 0
+                                       2500 1
+                                       3100 2
+                                       3800 3
+                                       4600 4
+                                       4800 5
+                                       4900 6
+                                       5000 7 >;
+        };
+        gpio-fan-100-15-35-3 {
+                status = "disabled";
+                compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
+                             &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>;
+                pinctrl-names = "default";
+                gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
+                         &gpio0 16 GPIO_ACTIVE_HIGH
+                         &gpio0 17 GPIO_ACTIVE_HIGH>;
+                alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH
+                               &gpio1 12 GPIO_ACTIVE_HIGH
+                               &gpio1 13 GPIO_ACTIVE_HIGH>;
+                gpio-fan,speed-map = <    0 0
+                                       2500 1
+                                       3100 2
+                                       3800 3
+                                       4600 4
+                                       4800 5
+                                       4900 6
+                                       5000 7 >;
+        };
+        gpio-leds-alarm-12 {
+                status = "disabled";
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_alarmled_12>;
+                pinctrl-names = "default";
+                hdd1-green {
+                        label = "synology:alarm";
+                        gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+                };
+        };
+        gpio-leds-hdd-20 {
+                status = "disabled";
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22
+                             &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25
+                             &pmx_hddled_26 &pmx_hddled_27>;
+                pinctrl-names = "default";
+                hdd1-green {
+                        label = "synology:green:hdd1";
+                        gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+                };
+                hdd1-amber {
+                        label = "synology:amber:hdd1";
+                        gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+                };
+                hdd2-green {
+                        label = "synology:green:hdd2";
+                        gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+                };
+                hdd2-amber {
+                        label = "synology:amber:hdd2";
+                        gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+                };
+                hdd3-green {
+                        label = "synology:green:hdd3";
+                        gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+                };
+                hdd3-amber {
+                        label = "synology:amber:hdd3";
+                        gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+                };
+                hdd4-green {
+                        label = "synology:green:hdd4";
+                        gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+                };
+                hdd4-amber {
+                        label = "synology:amber:hdd4";
+                        gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
+                };
+        };
+        gpio-leds-hdd-21-1 {
+                status = "disabled";
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>;
+                pinctrl-names = "default";
+                hdd1-green {
+                        label = "synology:green:hdd1";
+                        gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+                };
+                hdd1-amber {
+                        label = "synology:amber:hdd1";
+                        gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+                };
+        };
+        gpio-leds-hdd-21-2 {
+                status = "disabled";
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>;
+                pinctrl-names = "default";
+                hdd1-green {
+                        label = "synology:green:hdd1";
+                        gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+                };
+                hdd1-amber {
+                        label = "synology:amber:hdd1";
+                        gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+                };
+                hdd2-green {
+                        label = "synology:green:hdd2";
+                        gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+                };
+                hdd2-amber {
+                        label = "synology:amber:hdd2";
+                        gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+                };
+        };
+        gpio-leds-hdd-36 {
+                status = "disabled";
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38
+                             &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41
+                             &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44
+                             &pmx_hddled_45>;
+                pinctrl-names = "default";
+                hdd1-green {
+                        label = "synology:green:hdd1";
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+                };
+                hdd1-amber {
+                        label = "synology:amber:hdd1";
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+                };
+                hdd2-green {
+                        label = "synology:green:hdd2";
+                        gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+                };
+                hdd2-amber {
+                        label = "synology:amber:hdd2";
+                        gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+                };
+                hdd3-green {
+                        label = "synology:green:hdd3";
+                        gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+                };
+                hdd3-amber {
+                        label = "synology:amber:hdd3";
+                        gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+                };
+                hdd4-green {
+                        label = "synology:green:hdd4";
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+                };
+                hdd4-amber {
+                        label = "synology:amber:hdd4";
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+                };
+                hdd5-green {
+                        label = "synology:green:hdd5";
+                        gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+                };
+                hdd5-amber {
+                        label = "synology:amber:hdd5";
+                        gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+                };
+        };
+        gpio-leds-hdd-38 {
+                status = "disabled";
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>;
+                pinctrl-names = "default";
+                hdd1-green {
+                        label = "synology:green:hdd1";
+                        gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+                };
+                hdd1-amber {
+                        label = "synology:amber:hdd1";
+                        gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+                };
+                hdd2-green {
+                        label = "synology:green:hdd2";
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+                };
+                hdd2-amber {
+                        label = "synology:amber:hdd2";
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+                };
+        };
+        regulators-hdd-29 {
+                status = "disabled";
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>;
+                pinctrl-names = "default";
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "hdd1power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+                };
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "hdd2power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        regulators-hdd-30-1 {
+                status = "disabled";
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_hdd1_pwr_30>;
+                pinctrl-names = "default";
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "hdd1power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        regulators-hdd-30-2 {
+                status = "disabled";
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>;
+                pinctrl-names = "default";
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "hdd1power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+                };
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "hdd2power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        regulators-hdd-30-4 {
+                status = "disabled";
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34
+                             &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>;
+                pinctrl-names = "default";
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "hdd1power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+                };
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "hdd2power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+                };
+                regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "hdd3power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                };
+                regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "hdd4power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        regulators-hdd-31 {
+                status = "disabled";
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_hdd2_pwr_31>;
+                pinctrl-names = "default";
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "hdd2power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        regulators-hdd-34 {
+                status = "disabled";
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44
+                             &pmx_hdd4_pwr_45>;
+                pinctrl-names = "default";
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "hdd2power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+                };
+                regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "hdd3power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                };
+                regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "hdd4power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        startup-delay-us = <5000000>;
+                        gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@0 {
+                device_type = "ethernet-phy";
+                reg = <8>;
+        };
+        ethphy1: ethernet-phy@1 {
+                device_type = "ethernet-phy";
+                reg = <9>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
+&eth1 {
+        status = "disabled";
+        ethernet1-port@0 {
+                phy-handle = <&ethphy1>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts
new file mode 100644
index 000000000000..7d1c7677a18f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-t5325.dts
@@ -0,0 +1,208 @@
+/*
+ * Device Tree file for HP t5325 Thin Client"
+ *
+ * Copyright (C) 2014
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+/ {
+        model = "HP t5325 Thin Client";
+        compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
+                        pinctrl-names = "default";
+                        pmx_button_power: pmx-button_power {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_off: pmx-power-off {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led: pmx-led {
+                                marvell,pins = "mpp21";
+                                marvell,function = "gpio";
+                        };
+                        pmx_usb_sata_power_enable: pmx-usb-sata-power-enable {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        /*
+                         * Redefined from kirkwood-6281.dtsi, because
+                         * we don't use SPI CS on MPP0, but on MPP7.
+                         */
+                        pmx_spi: pmx-spi {
+                                marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7";
+                                marvell,function = "spi";
+                        };
+                        pmx_sysrst: pmx-sysrst {
+                                marvell,pins = "mpp6";
+                                marvell,function = "sysrst";
+                        };
+                        pmx_i2s: pmx-i2s {
+                                marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42",
+                                               "mpp43";
+                                marvell,function = "audio";
+                        };
+                };
+                spi@10600 {
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "st,m25p80";
+                                spi-max-frequency = <86000000>;
+                                reg = <0>;
+                                mode = <0>;
+                                partition@0 {
+                                        reg = <0x0 0x80000>;
+                                        label = "u-boot";
+                                };
+                                partition@1 {
+                                        reg = <0x80000 0x40000>;
+                                        label = "SSD firmware";
+                                };
+                                partition@2 {
+                                        reg = <0xc0000 0x10000>;
+                                        label = "u-boot env";
+                                };
+                                partition@3 {
+                                        reg = <0xd0000 0x10000>;
+                                        label = "permanent u-boot env";
+                                };
+                                partition@4 {
+                                        reg = <0xd0000 0x10000>;
+                                        label = "permanent u-boot env";
+                                };
+                        };
+                };
+                i2c@11000 {
+                        status = "okay";
+                        alc5621: alc5621@1a {
+                                compatible = "realtek,alc5621";
+                                reg = <0x1a>;
+                        };
+                };
+                serial@12000 {
+                        status = "okay";
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+                audio: audio-controller@a0000 {
+                        status = "okay";
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_sata_power_enable>;
+                pinctrl-names = "default";
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB-SATA Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_power>;
+                pinctrl-names = "default";
+                button@1 {
+                        label = "Power Button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_power_off>;
+                pinctrl-names = "default";
+                gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy {
+                device_type = "ethernet-phy";
+                reg = <8>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts419-6281.dts b/arch/arm/boot/dts/kirkwood-ts419-6281.dts
new file mode 100644
index 000000000000..aa22aa862857
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ts419-6281.dts
@@ -0,0 +1,20 @@
+/*
+ * Device Tree file for QNAP TS41X with 6281 SoC
+ *
+ * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-ts219.dtsi"
+#include "kirkwood-ts419.dtsi"
+&ethphy0 { reg = <8>; };
+&ethphy1 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts419-6282.dts b/arch/arm/boot/dts/kirkwood-ts419-6282.dts
new file mode 100644
index 000000000000..d7512d4cdced
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ts419-6282.dts
@@ -0,0 +1,32 @@
+/*
+ * Device Tree file for QNAP TS41X with 6282 SoC
+ *
+ * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-ts219.dtsi"
+#include "kirkwood-ts419.dtsi"
+/ {
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
+&ethphy0 { reg = <0>; };
+&ethphy1 { reg = <1>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi
new file mode 100644
index 000000000000..1a9c624c7a92
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ts419.dtsi
@@ -0,0 +1,75 @@
+/*
+ * Device Tree include file for QNAP TS41X
+ *
+ * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+/ {
+        model = "QNAP TS419 family";
+        compatible = "qnap,ts419", "marvell,kirkwood";
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-names = "default";
+                        pmx_USB_copy_button: pmx-USB-copy-button {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        pmx_reset_button: pmx-reset-button {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+                        /*
+                         * JP1 indicates if an LCD module is installed
+                         * on the serial port (0), or if the port is used
+                         * as a console (1).
+                         */
+                        pmx_jumper_jp1: pmx-jumper_jp1 {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
+                pinctrl-names = "default";
+                button@1 {
+                        label = "USB Copy";
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+                };
+                button@2 {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy1: ethernet-phy@1 {
+                device_type = "ethernet-phy";
+                /* overwrite reg property in board file */
+        };
+};
+&eth1 {
+        status = "okay";
+        ethernet1-port@0 {
+                phy-handle = <&ethphy1>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 6abf44d257df..90384587c278 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -24,6 +24,7 @@
        aliases {
               gpio0 = &gpio0;
               gpio1 = &gpio1;
+               i2c0 = &i2c0;
        };
        mbus {
@@ -111,7 +112,7 @@
                        clocks = <&gate_clk 7>;
                };
-                i2c@11000 {
+                i2c0: i2c@11000 {
                        compatible = "marvell,mv64xxx-i2c";
                        reg = <0x11000 0x20>;
                        #address-cells = <1>;
@@ -145,6 +146,11 @@
                        reg = <0x20000 0x80>, <0x1500 0x20>;
                };
+                system-controller@20000 {
+                        compatible = "marvell,orion-system-controller";
+                        reg = <0x20000 0x120>;
+                };
                bridge_intc: bridge-interrupt-ctrl@20110 {
                        compatible = "marvell,orion-bridge-intc";
                        interrupt-controller;
@@ -161,6 +167,11 @@
                        #clock-cells = <1>;
                };
+                l2: l2-cache@20128 {
+                        compatible = "marvell,kirkwood-cache";
+                        reg = <0x20128 0x4>;
+                };
                intc: main-interrupt-ctrl@20200 {
                        compatible = "marvell,orion-intc";
                        interrupt-controller;
@@ -178,7 +189,7 @@
                wdt: watchdog-timer@20300 {
                        compatible = "marvell,orion-wdt";
-                        reg = <0x20300 0x28>;
+                        reg = <0x20300 0x28>, <0x20108 0x4>;
                        interrupt-parent = <&bridge_intc>;
                        interrupts = <3>;
                        clocks = <&gate_clk 7>;
@@ -300,5 +311,14 @@
                        #phy-cells = <0>;
                        status = "ok";
                };
+                audio0: audio-controller@a0000 {
+                        compatible = "marvell,kirkwood-audio";
+                        reg = <0xa0000 0x2210>;
+                        interrupts = <24>;
+                        clocks = <&gate_clk 9>;
+                        clock-names = "internal";
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
index 1579c3491ccd..0c9647d28765 100644
--- a/arch/arm/boot/dts/marco.dtsi
+++ b/arch/arm/boot/dts/marco.dtsi
@@ -58,9 +58,10 @@
                        #size-cells = <1>;
                        ranges = <0xc2000000 0xc2000000 0x1000000>;
-                        reset-controller@c2000000 {
+                        rstc: reset-controller@c2000000 {
                                compatible = "sirf,marco-rstc";
                                reg = <0xc2000000 0x10000>;
+                                #reset-cells = <1>;
                        };
                };
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
new file mode 100644
index 000000000000..73e272fadc20
--- /dev/null
+++ b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
@@ -0,0 +1,58 @@
+/*
+ * Common file for GPMC connected smsc9221 on omaps
+ *
+ * Compared to smsc911x, smsc9221 (and others like smsc9217
+ * or smsc 9218) has faster timings, leading to higher
+ * bandwidth.
+ *
+ * Note that the board specifc DTS file needs to specify
+ * ranges, pinctrl, reg, interrupt parent and interrupts.
+ */
+/ {
+        vddvario: regulator-vddvario {
+                  compatible = "regulator-fixed";
+                  regulator-name = "vddvario";
+                  regulator-always-on;
+        };
+        vdd33a: regulator-vdd33a {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
+};
+&gpmc {
+        ethernet@gpmc {
+                compatible = "smsc,lan9221","smsc,lan9115";
+                bank-width = <2>;
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <42>;
+                gpmc,cs-wr-off-ns = <36>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <12>;
+                gpmc,adv-wr-off-ns = <12>;
+                gpmc,oe-on-ns = <0>;
+                gpmc,oe-off-ns = <42>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <36>;
+                gpmc,rd-cycle-ns = <60>;
+                gpmc,wr-cycle-ns = <54>;
+                gpmc,access-ns = <36>;
+                gpmc,page-burst-access-ns = <0>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <18>;
+                gpmc,wr-access-ns = <42>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+                vddvario-supply = <&vddvario>;
+                vdd33a-supply = <&vdd33a>;
+                reg-io-width = <4>;
+                smsc,save-mac-address;
+        };
+};
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 5377ddf83bf8..22f35ea142c1 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -271,5 +271,36 @@
                        ti,hwmods = "timer12";
                        ti,timer-pwm;
                };
+                dss: dss@48050000 {
+                        compatible = "ti,omap2-dss";
+                        reg = <0x48050000 0x400>;
+                        status = "disabled";
+                        ti,hwmods = "dss_core";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        dispc@48050400 {
+                                compatible = "ti,omap2-dispc";
+                                reg = <0x48050400 0x400>;
+                                interrupts = <25>;
+                                ti,hwmods = "dss_dispc";
+                        };
+                        rfbi: encoder@48050800 {
+                                compatible = "ti,omap2-rfbi";
+                                reg = <0x48050800 0x400>;
+                                status = "disabled";
+                                ti,hwmods = "dss_rfbi";
+                        };
+                        venc: encoder@48050c00 {
+                                compatible = "ti,omap2-venc";
+                                reg = <0x48050c00 0x400>;
+                                status = "disabled";
+                                ti,hwmods = "dss_venc";
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 60c605de22dd..85b1fb014c43 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -99,6 +99,7 @@
                        dmas = <&sdma 31>,
                               <&sdma 32>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp2: mcbsp@48076000 {
@@ -112,6 +113,7 @@
                        dmas = <&sdma 33>,
                               <&sdma 34>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                msdi1: mmc@4809c000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d624345666f5..d09697dab55e 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -29,6 +29,22 @@
                        pinctrl-single,function-mask = <0x3f>;
                };
+                omap2_scm_general: tisyscon@49002270 {
+                        compatible = "syscon";
+                        reg = <0x49002270 0x240>;
+                };
+                pbias_regulator: pbias_regulator {
+                        compatible = "ti,pbias-omap";
+                        reg = <0x230 0x4>;
+                        syscon = <&omap2_scm_general>;
+                        pbias_mmc_reg: pbias_mmc_omap2430 {
+                                regulator-name = "pbias_mmc_omap2430";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                };
                gpio1: gpio@4900c000 {
                        compatible = "ti,omap2-gpio";
                        reg = <0x4900c000 0x200>;
@@ -113,6 +129,7 @@
                        dmas = <&sdma 31>,
                               <&sdma 32>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp2: mcbsp@48076000 {
@@ -128,6 +145,7 @@
                        dmas = <&sdma 33>,
                               <&sdma 34>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp3: mcbsp@4808c000 {
@@ -143,6 +161,7 @@
                        dmas = <&sdma 17>,
                               <&sdma 18>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp4: mcbsp@4808e000 {
@@ -158,6 +177,7 @@
                        dmas = <&sdma 19>,
                               <&sdma 20>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp5: mcbsp@48096000 {
@@ -173,6 +193,7 @@
                        dmas = <&sdma 21>,
                               <&sdma 22>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mmc1: mmc@4809c000 {
@@ -183,6 +204,7 @@
                        ti,dual-volt;
                        dmas = <&sdma 61>, <&sdma 62>;
                        dma-names = "tx", "rx";
+                        pbias-supply = <&pbias_mmc_reg>;
                };
                mmc2: mmc@480b4000 {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 447e714d435b..cf0be662297e 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -24,6 +24,11 @@
                reg = <0x80000000 0x20000000>; /* 512 MB */
        };
+        aliases {
+                display0 = &dvi0;
+                display1 = &tv0;
+        };
        leds {
                compatible = "gpio-leds";
@@ -86,6 +91,60 @@
                reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
                vcc-supply = <&hsusb2_power>;
        };
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+                powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
+                /* XXX pinctrl from twl */
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+        dvi0: connector@0 {
+                compatible = "dvi-connector";
+                label = "dvi";
+                digital;
+                ddc-i2c-bus = <&i2c3>;
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
+        tv0: connector@1 {
+                compatible = "svideo-connector";
+                label = "tv";
+                port {
+                        tv_connector_in: endpoint {
+                                remote-endpoint = <&venc_out>;
+                        };
+                };
+        };
 };
 &omap3_pmx_wkup {
@@ -94,6 +153,17 @@
                        0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
                >;
        };
+        dss_dpi_pins2: pinmux_dss_dpi_pins1 {
+                pinctrl-single,pins = <
+                        0x0a (PIN_OUTPUT | MUX_MODE3)   /* sys_boot0.dss_data18 */
+                        0x0c (PIN_OUTPUT | MUX_MODE3)   /* sys_boot1.dss_data19 */
+                        0x10 (PIN_OUTPUT | MUX_MODE3)   /* sys_boot3.dss_data20 */
+                        0x12 (PIN_OUTPUT | MUX_MODE3)   /* sys_boot4.dss_data21 */
+                        0x14 (PIN_OUTPUT | MUX_MODE3)   /* sys_boot5.dss_data22 */
+                        0x16 (PIN_OUTPUT | MUX_MODE3)   /* sys_boot6.dss_data23 */
+                >;
+        };
 };
 &omap3_pmx_core {
@@ -119,6 +189,35 @@
                        OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
                >;
        };
+        dss_dpi_pins1: pinmux_dss_dpi_pins2 {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+                        OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3)   /* dss_data18.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3)   /* dss_data19.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3)   /* dss_data20.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3)   /* dss_data21.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3)   /* dss_data22.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3)   /* dss_data23.dss_data5 */
+                >;
+        };
 };
 &omap3_pmx_core2 {
@@ -164,15 +263,6 @@
 &i2c3 {
        clock-frequency = <100000>;
-        /*
-         * Display monitor features are burnt in the EEPROM
-         * as EDID data.
-         */
-        eeprom@50 {
-                compatible = "ti,eeprom";
-                reg = <0x50>;
-        };
 };
 &mmc1 {
@@ -234,3 +324,37 @@
        regulator-max-microvolt = <1800000>;
        regulator-always-on;
 };
+&mcbsp2 {
+        status = "okay";
+};
+&dss {
+        status = "ok";
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &dss_dpi_pins1
+                &dss_dpi_pins2
+        >;
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+&venc {
+        status = "ok";
+        vdda-supply = <&vdac>;
+        port {
+                venc_out: endpoint {
+                        remote-endpoint = <&tv_connector_in>;
+                        ti,channels = <2>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 5053766d369b..3c3e6da1deac 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -24,6 +24,11 @@
                reg = <0x80000000 0x10000000>; /* 256 MB */
        };
+        aliases {
+                display0 = &dvi0;
+                display1 = &tv0;
+        };
        leds {
                compatible = "gpio-leds";
                pmu_stat {
@@ -80,6 +85,61 @@
                };
        };
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+                powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;  /* gpio_170 */
+                pinctrl-names = "default";
+                pinctrl-0 = <&tfp410_pins>;
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+        dvi0: connector@0 {
+                compatible = "dvi-connector";
+                label = "dvi";
+                digital;
+                ddc-i2c-bus = <&i2c3>;
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
+        tv0: connector@1 {
+                compatible = "svideo-connector";
+                label = "tv";
+                port {
+                        tv_connector_in: endpoint {
+                                remote-endpoint = <&venc_out>;
+                        };
+                };
+        };
 };
 &omap3_pmx_wkup {
@@ -113,6 +173,45 @@
                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
                >;
        };
+        tfp410_pins: pinmux_tfp410_pins {
+                pinctrl-single,pins = <
+                        0x194 (PIN_OUTPUT | MUX_MODE4)  /* hdq_sio.gpio_170 */
+                >;
+        };
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        0x0a4 (PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+                        0x0a6 (PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+                        0x0a8 (PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+                        0x0aa (PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+                        0x0ac (PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
+                        0x0ae (PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
+                        0x0b0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
+                        0x0b2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
+                        0x0b4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
+                        0x0b6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
+                        0x0b8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+                        0x0ba (PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+                        0x0bc (PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+                        0x0be (PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+                        0x0c0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+                        0x0c2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+                        0x0c4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+                        0x0c6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+                        0x0c8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+                        0x0ca (PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+                        0x0cc (PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+                        0x0ce (PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+                        0x0d0 (PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
+                        0x0d2 (PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
+                        0x0d4 (PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
+                        0x0d6 (PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
+                        0x0d8 (PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
+                        0x0da (PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
+                >;
+        };
 };
 &omap3_pmx_core2 {
@@ -152,6 +251,10 @@
 #include "twl4030.dtsi"
 #include "twl4030_omap3.dtsi"
+&i2c3 {
+        clock-frequency = <100000>;
+};
 &mmc1 {
        vmmc-supply = <&vmmc1>;
        vmmc_aux-supply = <&vsim>;
@@ -211,3 +314,39 @@
        regulator-max-microvolt = <1800000>;
        regulator-always-on;
 };
+&mcbsp2 {
+        status = "okay";
+};
+/* Needed to power the DPI pins */
+&vpll2 {
+        regulator-always-on;
+};
+&dss {
+        status = "ok";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_dpi_pins>;
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+&venc {
+        status = "ok";
+        vdda-supply = <&vdac>;
+        port {
+                venc_out: endpoint {
+                        remote-endpoint = <&tv_connector_in>;
+                        ti,channels = <2>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
new file mode 100644
index 000000000000..d00502f4fd9b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -0,0 +1,136 @@
+/*
+ * Support for CompuLab CM-T3517
+ */
+/dts-v1/;
+#include "am3517.dtsi"
+#include "omap3-cm-t3x.dtsi"
+/ {
+        model = "CompuLab CM-T3517";
+        compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
+        vmmc:  regulator-vmmc {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        wl12xx_vmmc2: wl12xx_vmmc2 {
+                compatible = "regulator-fixed";
+                regulator-name = "vw1271";
+                pinctrl-names = "default";
+                pinctrl-0 = <
+                                &wl12xx_wkup_pins
+                                &wl12xx_core_pins
+                            >;
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                gpio = <&gpio1 6 GPIO_ACTIVE_HIGH >; /* gpio6 */
+                startup-delay-us = <20000>;
+                enable-active-high;
+        };
+        wl12xx_vaux2: wl12xx_vaux2 {
+                compatible = "regulator-fixed";
+                regulator-name = "vwl1271_vaux2";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+};
+&omap3_pmx_wkup {
+        wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
+                pinctrl-single,pins = <
+                        OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4)        /* sys_boot2.gpio_4 */
+                        OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4)        /* sys_boot4.gpio_6 */
+                >;
+        };
+};
+&omap3_pmx_core {
+        phy1_reset_pins: pinmux_hsusb1_phy_reset_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4)       /* uart2_tx.gpio_146 */
+                >;
+        };
+        phy2_reset_pins: pinmux_hsusb2_phy_reset_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4)       /* uart2_rx.gpio_147 */
+                >;
+        };
+        otg_drv_vbus: pinmux_otg_drv_vbus {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50Mhz_clk.usb0_drvvbus */
+                >;
+        };
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
+                        OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
+                        OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
+                        OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
+                        OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
+                >;
+        };
+        wl12xx_core_pins: pinmux_wl12xx_core_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4)       /* gpmc_ncs5.gpio_56 */
+                        OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */
+                >;
+        };
+        usb_hub_pins: pinmux_usb_hub_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4)       /* mcbsp4_clkx.gpio_152 - USB HUB RST */
+                >;
+        };
+};
+&hsusb1_phy {
+        pinctrl-names = "default";
+        pinctrl-0 = <&phy1_reset_pins>;
+        reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
+};
+&hsusb2_phy {
+        pinctrl-names = "default";
+        pinctrl-0 = <&phy2_reset_pins>;
+        reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>;
+};
+&davinci_emac {
+        status = "okay";
+};
+&davinci_mdio {
+        status = "okay";
+};
+&am35x_otg_hs {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&otg_drv_vbus>;
+};
+&mmc1 {
+        vmmc-supply = <&vmmc>;
+};
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&wl12xx_vmmc2>;
+        vmmc_aux-supply = <&wl12xx_vaux2>;
+        non-removable;
+        bus-width = <4>;
+        cap-power-off-card;
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts
new file mode 100644
index 000000000000..d1458496520e
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cm-t3530.dts
@@ -0,0 +1,48 @@
+/*
+ * Support for CompuLab CM-T3530
+ */
+/dts-v1/;
+#include "omap34xx.dtsi"
+#include "omap3-cm-t3x30.dtsi"
+/ {
+        model = "CompuLab CM-T3530";
+        compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+        /* Regulator to trigger the reset signal of the Wifi module */
+        mmc2_sdio_reset: regulator-mmc2-sdio-reset {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-mmc2-sdio-reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+};
+&omap3_pmx_core {
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_clk.sdmmc2_clk */
+                        OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_cmd.sdmmc2_cmd */
+                        OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat0.sdmmc2_dat0 */
+                        OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat1.sdmmc2_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat2.sdmmc2_dat2 */
+                        OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat3.sdmmc2_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1)               /* sdmmc2_dat4.sdmmc2_dir_dat0 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1)               /* sdmmc2_dat5.sdmmc2_dir_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1)               /* sdmmc2_dat6.sdmmc2_dir_cmd */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1)                /* sdmmc2_dat7.sdmmc2_clkin */
+                >;
+        };
+};
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&mmc2_sdio_reset>;
+        non-removable;
+        bus-width = <4>;
+        cap-power-off-card;
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index 486f4d6c4219..b3f9a50b3bc8 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -32,57 +32,26 @@
 };
 &omap3_pmx_core {
-        mmc1_pins: pinmux_mmc1_pins {
-                pinctrl-single,pins = <
-                        0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* sdmmc1_clk.sdmmc1_clk */
-                        0x116 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_cmd.sdmmc1_cmd */
-                        0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat0.sdmmc1_dat0 */
-                        0x11a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat1.sdmmc1_dat1 */
-                        0x11c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat2.sdmmc1_dat2 */
-                        0x11e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat3.sdmmc1_dat3 */
-                >;
-        };
        mmc2_pins: pinmux_mmc2_pins {
                pinctrl-single,pins = <
-                        0x128 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_clk.sdmmc2_clk */
+                        OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
-                        0x12a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_cmd.sdmmc2_cmd */
+                        OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
-                        0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_dat0.sdmmc2_dat0 */
+                        OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
-                        0x12e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_dat1.sdmmc2_dat1 */
+                        OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
-                        0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_dat2.sdmmc2_dat2 */
+                        OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
-                        0x132 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc2_dat3.sdmmc2_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
-                >;
-        };
-        smsc1_pins: pinmux_smsc1_pins {
-                pinctrl-single,pins = <
-                        0x88 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_ncs5.gpmc_ncs5 */
-                        0x16a (PIN_INPUT_PULLUP | MUX_MODE4)    /* uart3_cts_rctx.gpio_163 */
-                >;
-        };
-        uart3_pins: pinmux_uart3_pins {
-                pinctrl-single,pins = <
-                        0x16e (PIN_INPUT | MUX_MODE0)           /* uart3_rx_irrx.uart3_rx_irrx */
-                        0x170 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx_irtx.uart3_tx_irtx */
                >;
        };
        wl12xx_gpio: pinmux_wl12xx_gpio {
                pinctrl-single,pins = <
-                        0xb2 (PIN_OUTPUT | MUX_MODE4)           /* dss_data3.gpio_73 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4)       /* dss_data3.gpio_73 */
-                        0x134 (PIN_INPUT | MUX_MODE4)           /* sdmmc2_dat4.gpio_136 */
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4)        /* sdmmc2_dat4.gpio_136 */
                >;
        };
 };
-&mmc1 {
-        vmmc-supply = <&vmmc1>;
-        bus-width = <4>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins>;
-};
 &mmc2 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc2_pins>;
@@ -92,13 +61,3 @@
        bus-width = <4>;
        cap-power-off-card;
 };
-&smsc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&smsc1_pins>;
-};
-&uart3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&uart3_pins>;
-};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
new file mode 100644
index 000000000000..c671a2299ea8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Common support for CompuLab CM-T3x CoMs
+ */
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&green_led_pins>;
+                ledb {
+                        label = "cm-t3x:green";
+                        gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;  /* gpio186 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        /* HS USB Port 1 Power */
+        hsusb1_power: hsusb1_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb1_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <70000>;
+        };
+        /* HS USB Port 2 Power */
+        hsusb2_power: hsusb2_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <70000>;
+        };
+        /* HS USB Host PHY on PORT 1 */
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+                vcc-supply = <&hsusb1_power>;
+        };
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                vcc-supply = <&hsusb2_power>;
+        };
+};
+&omap3_pmx_core {
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT  | MUX_MODE0)       /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)       /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
+                >;
+        };
+        green_led_pins: pinmux_green_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4)       /* sys_clkout2.gpio_186 */
+                >;
+        };
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        bus-width = <4>;
+};
+&mmc3 {
+        status = "disabled";
+};
+&i2c1 {
+        clock-frequency = <400000>;
+};
+&i2c3 {
+        clock-frequency = <400000>;
+};
+&usbhshost {
+        port1-mode = "ehci-phy";
+        port2-mode = "ehci-phy";
+};
+&usbhsehci {
+        phys = <&hsusb1_phy &hsusb2_phy>;
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index 3a9f004d8924..d00055809e31 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -1,28 +1,16 @@
 /*
- * Common support for CompuLab CM-T3530 and  CM-T3730
+ * Common support for CompuLab CM-T3x30 CoMs
 */
-/ {
+#include "omap3-cm-t3x.dtsi"
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x10000000>; /* 256 MB */
-        };
+/ {
        cpus {
                cpu@0 {
                        cpu0-supply = <&vcc>;
                };
        };
-        leds {
-                compatible = "gpio-leds";
-                ledb {
-                        label = "cm-t35:green";
-                        gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;  /* gpio186 */
-                        linux,default-trigger = "heartbeat";
-                };
-        };
        vddvario: regulator-vddvario {
                compatible = "regulator-fixed";
                regulator-name = "vddvario";
@@ -36,11 +24,40 @@
        };
 };
+&omap3_pmx_core {
+        smsc1_pins: pinmux_smsc1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0)       /* gpmc_ncs5.gpmc_ncs5 */
+                        OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */
+                >;
+        };
+        hsusb0_pins: pinmux_hsusb0_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)               /* hsusb0_clk.hsusb0_clk */
+                        OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0)               /* hsusb0_stp.hsusb0_stp */
+                        OMAP3_CORE1_IOPAD(0x21a4, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_dir.hsusb0_dir */
+                        OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_nxt.hsusb0_nxt */
+                        OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data0.hsusb2_data0 */
+                        OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data1.hsusb0_data1 */
+                        OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data2.hsusb0_data2 */
+                        OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data3 */
+                        OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data4 */
+                        OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data5 */
+                        OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data6 */
+                        OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data7 */
+                >;
+        };
+};
 &gpmc {
        ranges = <5 0 0x2c000000 0x01000000>;
        smsc1: ethernet@5,0 {
                compatible = "smsc,lan9221", "smsc,lan9115";
+                pinctrl-names = "default";
+                pinctrl-0 = <&smsc1_pins>;
                interrupt-parent = <&gpio6>;
                interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
                reg = <5 0 0xff>;
@@ -74,8 +91,6 @@
 };
 &i2c1 {
-        clock-frequency = <400000>;
        twl: twl@48 {
                reg = <0x48>;
                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
@@ -86,10 +101,31 @@
 #include "twl4030.dtsi"
 #include "twl4030_omap3.dtsi"
-&i2c3 {
+&mmc1 {
-        clock-frequency = <400000>;
+        vmmc-supply = <&vmmc1>;
 };
 &twl_gpio {
        ti,use-leds;
+        /* pullups: BIT(0) */
+        ti,pullups = <0x000001>;
+};
+&hsusb1_phy {
+        reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>;
+};
+&hsusb2_phy {
+        reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>;
+};
+&usb_otg_hs {
+        pinctrl-names = "default";
+        pinctrl-0 = <&hsusb0_pins>;
+        interface-type = <0>;
+        usb-phy = <&usb2_phy>;
+        phys = <&usb2_phy>;
+        phy-names = "usb2-phy";
+        mode = <3>;
+        power = <50>;
 };
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 4665421bb7bc..bf5a515a3247 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -101,20 +101,8 @@
        status = "disabled";
 };
-&mcbsp1 {
+&mcbsp2 {
-        status = "disabled";
+        status = "okay";
-};
-&mcbsp3 {
-        status = "disabled";
-};
-&mcbsp4 {
-        status = "disabled";
-};
-&mcbsp5 {
-        status = "disabled";
 };
 &gpmc {
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts
index d3b253bbc885..f8ad125fa46f 100644
--- a/arch/arm/boot/dts/omap3-gta04.dts
+++ b/arch/arm/boot/dts/omap3-gta04.dts
@@ -36,6 +36,14 @@
                        gpio-key,wakeup;
                };
        };
+        sound {
+                compatible = "ti,omap-twl4030";
+                ti,model = "gta04";
+                ti,mcbsp = <&mcbsp2>;
+                ti,codec = <&twl_audio>;
+        };
 };
 &omap3_pmx_core {
@@ -80,6 +88,12 @@
                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
                interrupt-parent = <&intc>;
        };
+        twl_audio: audio {
+                compatible = "ti,twl4030-audio";
+                codec {
+                };
+        };
 };
 #include "twl4030.dtsi"
@@ -96,6 +110,14 @@
                interrupts = <17 IRQ_TYPE_EDGE_RISING>;
        };
+        /* accelerometer */
+        bma180@41 {
+                compatible = "bosch,bma180";
+                reg = <0x41>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+        };
        /* leds */
        tca6507@45 {
                compatible = "ti,tca6507";
@@ -124,6 +146,22 @@
                        reg = <0x4>;
                };
        };
+        /* compass aka magnetometer */
+        hmc5843@1e {
+                compatible = "honeywell,hmc5843";
+                reg = <0x1e>;
+        };
+        /* touchscreen */
+        tsc2007@48 {
+                compatible = "ti,tsc2007";
+                reg = <0x48>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+                gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;
+                ti,x-plate-ohms = <600>;
+        };
 };
 &i2c3 {
@@ -148,7 +186,9 @@
 };
 &mmc2 {
-        status = "disabled";
+        vmmc-supply = <&vaux4>;
+        bus-width = <4>;
+        ti,non-removable;
 };
 &mmc3 {
@@ -170,3 +210,12 @@
        pinctrl-0 = <&uart3_pins>;
 };
+&charger {
+        bb_uvolt = <3200000>;
+        bb_uamp = <150>;
+};
+&vaux4 {
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <3150000>;
+};
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index c17009323520..b97736d98a64 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -170,6 +170,7 @@
 &mcbsp2 {
        pinctrl-names = "default";
        pinctrl-0 = <&mcbsp2_pins>;
+        status = "okay";
 };
 &mmc1 {
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index f2779ac75872..7abd64f6ae21 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -61,22 +61,63 @@
                reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
                vcc-supply = <&hsusb1_power>;
        };
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+                powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+        dvi0: connector@0 {
+                compatible = "dvi-connector";
+                label = "dvi";
+                digital;
+                ddc-i2c-bus = <&i2c3>;
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
 };
 &omap3_pmx_core {
        pinctrl-names = "default";
        pinctrl-0 = <
                &tfp410_pins
-                &dss_pins
+                &dss_dpi_pins
        >;
-        tfp410_pins: tfp410_dvi_pins {
+        tfp410_pins: pinmux_tfp410_pins {
                pinctrl-single,pins = <
                        0x196 (PIN_OUTPUT | MUX_MODE4)   /* hdq_sio.gpio_170 */
                >;
        };
-        dss_pins: pinmux_dss_dvi_pins {
+        dss_dpi_pins: pinmux_dss_dpi_pins {
                pinctrl-single,pins = <
                        0x0a4 (PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
                        0x0a6 (PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
@@ -226,3 +267,14 @@
        /* Needed for DSS */
        regulator-name = "vdds_dsi";
 };
+&dss {
+        status = "ok";
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index ddce0d807f70..0abe986a4ecc 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -174,8 +174,20 @@
 };
 &mmc1 {
+        /* See 35xx errata 2.1.1.128 in SPRZ278F */
+        compatible = "ti,omap3-pre-es3-hsmmc";
        vmmc-supply = <&vmmc1>;
        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+};
+&mmc2 {
+        status="disabled";
+};
+&mmc3 {
+        status="disabled";
 };
 &omap3_pmx_core {
@@ -209,6 +221,17 @@
                        0x174 (PIN_OUTPUT | MUX_MODE0)  /* hsusb0_stp.hsusb0_stp */
                >;
        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
+                >;
+        };
 };
 &usb_otg_hs {
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
new file mode 100644
index 000000000000..6369d9f43ca2
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -0,0 +1,459 @@
+/*
+ * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include "omap36xx.dtsi"
+/ {
+        model = "INCOstartec LILLY-A83X module (DM3730)";
+        compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+        chosen {
+                        bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x8000000>;   /* 128 MB */
+        };
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        label = "lilly-a83x::led1";
+                        gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+        sound {
+                compatible = "ti,omap-twl4030";
+                ti,model = "lilly-a83x";
+                ti,mcbsp = <&mcbsp2>;
+                ti,codec = <&twl_audio>;
+        };
+        reg_vcc3: vcc3 {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+                vcc-supply = <&reg_vcc3>;
+        };
+};
+&omap3_pmx_wkup {
+        pinctrl-names = "default";
+        lan9221_pins: pinmux_lan9221_pins {
+                pinctrl-single,pins = <
+                        OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4)   /* reserved.gpio_129 */
+                >;
+        };
+        tsc2048_pins: pinmux_tsc2048_pins {
+                pinctrl-single,pins = <
+                        OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4)   /* sys_boot6.gpio_8 */
+                >;
+        };
+        mmc1cd_pins: pinmux_mmc1cd_pins {
+                pinctrl-single,pins = <
+                        OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4)   /* reserved.gpio_126 */
+                >;
+        };
+};
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        uart1_pins: pinmux_uart1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0)   /* uart1_tx.uart1_tx */
+                        OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0)   /* uart1_rts.uart1_rts */
+                        OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0)    /* uart1_cts.uart1_cts */
+                        OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)    /* uart1_rx.uart1_rx */
+                >;
+        };
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)   /* mcbsp3_clkx.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)    /* mcbsp3_fsx.uart2_rx */
+                >;
+        };
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)    /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)   /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl.i2c1_scl */
+                        OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda.i2c1_sda */
+                >;
+        };
+        i2c2_pins: pinmux_i2c2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)   /* i2c2_scl.i2c2_scl */
+                        OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)   /* i2c2_sda.i2c2_sda */
+                >;
+        };
+        i2c3_pins: pinmux_i2c3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)   /* i2c3_scl.i2c3_scl */
+                        OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)   /* i2c3_sda.i2c3_sda */
+                >;
+        };
+        hsusb1_pins: pinmux_hsusb1_pins {
+                pinctrl-single,pins = <
+                        /* GPIO 182 controls USB-Hub reset. But USB-Phy its
+                         * reset can't be controlled. So we clamp this GPIO to
+                         * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub.
+                         */
+                        OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4)   /* mcspi2_cs1.gpio_182 */
+                >;
+        };
+        hsusb_otg_pins: pinmux_hsusb_otg_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)   /* hsusb0_clk.hsusb0_clk */
+                        OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)  /* hsusb0_stp.hsusb0_stp */
+                        OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)   /* hsusb0_dir.hsusb0_dir */
+                        OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)   /* hsusb0_nxt.hsusb0_nxt */
+                        OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)   /* hsusb0_data0.hsusb0_data0 */
+                        OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)   /* hsusb0_data1.hsusb0_data1 */
+                        OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)   /* hsusb0_data2.hsusb0_data2 */
+                        OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)   /* hsusb0_data3.hsusb0_data3 */
+                        OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)   /* hsusb0_data4.hsusb0_data4 */
+                        OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)   /* hsusb0_data5.hsusb0_data5 */
+                        OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)   /* hsusb0_data6.hsusb0_data6 */
+                        OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)   /* hsusb0_data7.hsusb0_data7 */
+                >;
+        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc1_dat3.sdmmc1_dat3 */
+                >;
+        };
+        spi2_pins: pinmux_spi2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_clk.mcspi2_clk */
+                        OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_simo.mcspi2_simo */
+                        OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi2_somi.mcspi2_somi */
+                        OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0)   /* mcspi2_cs0.mcspi2_cs0 */
+                >;
+        };
+};
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusb1_2_pins
+        >;
+        hsusb1_2_pins: pinmux_hsusb1_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)  /* etk_clk.hsusb1_stp */
+                        OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3)   /* etk_ctl.hsusb1_clk */
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3)   /* etk_d0.hsusb1_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3)   /* etk_d1.hsusb1_data1 */
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3)   /* etk_d2.hsusb1_data2 */
+                        OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3)   /* etk_d3.hsusb1_data7 */
+                        OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3)   /* etk_d4.hsusb1_data4 */
+                        OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3)   /* etk_d5.hsusb1_data5 */
+                        OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3)   /* etk_d6.hsusb1_data6 */
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3)   /* etk_d7.hsusb1_data3 */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3)   /* etk_d8.hsusb1_dir */
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3)   /* etk_d9.hsusb1_nxt */
+                >;
+        };
+        gpio1_pins: pinmux_gpio1_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4)   /* etk_d15.gpio_29 */
+                >;
+        };
+};
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio1_pins>;
+};
+&gpio6 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&hsusb1_pins>;
+};
+&i2c1 {
+        clock-frequency = <2600000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>;   /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+                        codec {
+                        };
+                };
+        };
+};
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+&twl {
+        vmmc1: regulator-vmmc1 {
+                regulator-always-on;
+        };
+        vdd1: regulator-vdd1 {
+                regulator-always-on;
+        };
+        vdd2: regulator-vdd2 {
+                regulator-always-on;
+        };
+};
+&i2c2 {
+        clock-frequency = <2600000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+};
+&i2c3 {
+        clock-frequency = <2600000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+                gpiom1: gpio@20 {
+                        compatible = "mcp,mcp23017";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        reg = <0x20>;
+                };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>;
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+&uart4 {
+        status = "disabled";
+};
+&mmc1 {
+        cd-gpios = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
+        cd-inverted;
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins &mmc1cd_pins>;
+        cap-sdio-irq;
+        cap-sd-highspeed;
+        cap-mmc-highspeed;
+};
+&mmc2 {
+        status = "disabled";
+};
+&mmc3 {
+        status = "disabled";
+};
+&mcspi2 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi2_pins>;
+        tsc2046@0 {
+                reg = <0>;   /* CS0 */
+                compatible = "ti,tsc2046";
+                interrupt-parent = <&gpio1>;
+                interrupts = <8 0>;   /* boot6 / gpio_8 */
+                spi-max-frequency = <1000000>;
+                pendown-gpio = <&gpio1 8 0>;
+                vcc-supply = <&reg_vcc3>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&tsc2048_pins>;
+                ti,x-min = <300>;
+                ti,x-max = <3000>;
+                ti,y-min = <600>;
+                ti,y-max = <3600>;
+                ti,x-plate-ohms = <80>;
+                ti,pressure-max = <255>;
+                ti,swap-xy;
+                linux,wakeup;
+        };
+};
+&usbhsehci {
+        phys = <&hsusb1_phy>;
+};
+&usbhshost {
+        pinctrl-names = "default";
+        pinctrl-0 = <&hsusb1_2_pins>;
+        num-ports = <2>;
+        port1-mode = "ehci-phy";
+};
+&usb_otg_hs {
+        pinctrl-names = "default";
+        pinctrl-0 = <&hsusb_otg_pins>;
+        interface-type = <0>;
+        usb-phy = <&usb2_phy>;
+        phys = <&usb2_phy>;
+        phy-names = "usb2-phy";
+        mode = <3>;
+        power = <50>;
+};
+&gpmc {
+        ranges = <0 0 0x30000000 0x1000000>,
+                <7 0 0x15000000 0x01000000>;
+        nand@0,0 {
+                reg = <0 0 0x1000000>;
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "bch8";
+                /* no elm on omap3 */
+                gpmc,mux-add-data = <0>;
+                gpmc,device-nand;
+                gpmc,device-width = <2>;
+                gpmc,wait-pin = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,burst-length= <4>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <100>;
+                gpmc,cs-wr-off-ns = <100>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <100>;
+                gpmc,adv-wr-off-ns = <100>;
+                gpmc,oe-on-ns = <5>;
+                gpmc,oe-off-ns = <75>;
+                gpmc,we-on-ns = <5>;
+                gpmc,we-off-ns = <75>;
+                gpmc,rd-cycle-ns = <100>;
+                gpmc,wr-cycle-ns = <100>;
+                gpmc,access-ns = <60>;
+                gpmc,page-burst-access-ns = <5>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-delay-ns = <50>;
+                gpmc,wr-data-mux-bus-ns = <75>;
+                gpmc,wr-access-ns = <155>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "MLO";
+                        reg = <0 0x80000>;
+                };
+                partition@0x80000 {
+                        label = "u-boot";
+                        reg = <0x80000 0x1e0000>;
+                };
+                partition@0x260000 {
+                        label = "u-boot-environment";
+                        reg = <0x260000 0x20000>;
+                };
+                partition@0x280000 {
+                        label = "kernel";
+                        reg = <0x280000 0x500000>;
+                };
+                partition@0x780000 {
+                        label = "filesystem";
+                        reg = <0x780000 0xf880000>;
+                };
+        };
+        ethernet@7,0 {
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                bank-width = <2>;
+                gpmc,mux-add-data = <2>;
+                gpmc,cs-on-ns = <10>;
+                gpmc,cs-rd-off-ns = <60>;
+                gpmc,cs-wr-off-ns = <60>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <10>;
+                gpmc,adv-wr-off-ns = <10>;
+                gpmc,oe-on-ns = <10>;
+                gpmc,oe-off-ns = <60>;
+                gpmc,we-on-ns = <10>;
+                gpmc,we-off-ns = <60>;
+                gpmc,rd-cycle-ns = <100>;
+                gpmc,wr-cycle-ns = <100>;
+                gpmc,access-ns = <50>;
+                gpmc,page-burst-access-ns = <5>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <75>;
+                gpmc,wr-data-mux-bus-ns = <15>;
+                gpmc,wr-access-ns = <75>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+                vddvario-supply = <&reg_vcc3>;
+                vdd33a-supply = <&reg_vcc3>;
+                reg-io-width = <4>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <1 0x2>;
+                reg = <7 0 0xff>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&lan9221_pins>;
+                phy-mode = "mii";
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
new file mode 100644
index 000000000000..834f7c65f62d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+/dts-v1/;
+#include "omap3-lilly-a83x.dtsi"
+/ {
+        model = "INCOstartec LILLY-DBB056 (DM3730)";
+        compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+};
+&twl {
+        vaux2: regulator-vaux2 {
+                compatible = "ti,twl4030-vaux2";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                regulator-always-on;
+        };
+};
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <&lcd_pins>;
+        lan9117_pins: pinmux_lan9117_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4)   /* cam_fld.gpio_98 */
+                >;
+        };
+        gpio4_pins: pinmux_gpio4_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4)   /* cam_xclkb.gpio_111 -> sja1000 IRQ */
+                >;
+        };
+        gpio5_pins: pinmux_gpio5_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4)   /* mcbsp1_clk.gpio_156 -> enable DSS */
+                >;
+        };
+        lcd_pins: pinmux_lcd_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+                        OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+                        OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+                        OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+                        OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
+                        OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
+                        OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
+                        OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
+                        OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
+                        OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
+                        OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+                        OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+                        OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+                        OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+                        OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+                        OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+                        OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+                        OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+                        OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+                        OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+                        OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+                        OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+                >;
+        };
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_clk.sdmmc2_clk */
+                        OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_cmd.sdmmc2_cmd */
+                        OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_dat0.sdmmc2_dat0 */
+                        OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_dat1.sdmmc2_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_dat2.sdmmc2_dat2 */
+                        OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)   /* sdmmc2_dat3.sdmmc2_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1)   /* sdmmc2_dat4.sdmmc2_dir_dat0 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1)   /* sdmmc2_dat5.sdmmc2_dir_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1)   /* sdmmc2_dat6.sdmmc2_dir_cmd */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1)    /* sdmmc2_dat7.sdmmc2_clkin */
+                        OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4)   /* uart3_cts_rctx.gpio_163 -> wp */
+                        OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4)   /* uart3_rts_sd.gpio_164 -> cd */
+                >;
+        };
+        spi1_pins: pinmux_spi1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)   /* mcspi1_clk.mcspi1_clk */
+                        OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0)   /* mcspi1_simo.mcspi1_simo */
+                        OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0)   /* mcspi1_somi.mcspi1_somi */
+                        OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0)   /* mcspi1_cs0.mcspi1_cs0 */
+                >;
+        };
+};
+&gpio4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio4_pins>;
+};
+&gpio5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio5_pins>;
+};
+&mmc2 {
+        status = "okay";
+        bus-width = <4>;
+        vmmc-supply = <&vmmc1>;
+        cd-gpios = <&gpio6 4 0>;   /* gpio_164 */
+        wp-gpios = <&gpio6 3 0>;   /* gpio_163 */
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        ti,dual-volt;
+};
+&mcspi1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi1_pins>;
+};
+&gpmc {
+        ranges = <0 0 0x30000000 0x1000000>,   /* nand assigned by COM a83x */
+                <4 0 0x20000000 0x01000000>,
+                <7 0 0x15000000 0x01000000>;   /* eth assigend by COM a83x */
+        ethernet@4,0 {
+                compatible = "smsc,lan9117", "smsc,lan9115";
+                bank-width = <2>;
+                gpmc,mux-add-data = <2>;
+                gpmc,cs-on-ns = <10>;
+                gpmc,cs-rd-off-ns = <65>;
+                gpmc,cs-wr-off-ns = <65>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <10>;
+                gpmc,adv-wr-off-ns = <10>;
+                gpmc,oe-on-ns = <10>;
+                gpmc,oe-off-ns = <65>;
+                gpmc,we-on-ns = <10>;
+                gpmc,we-off-ns = <65>;
+                gpmc,rd-cycle-ns = <100>;
+                gpmc,wr-cycle-ns = <100>;
+                gpmc,access-ns = <60>;
+                gpmc,page-burst-access-ns = <5>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <75>;
+                gpmc,wr-data-mux-bus-ns = <15>;
+                gpmc,wr-access-ns = <75>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+                vddvario-supply = <&reg_vcc3>;
+                vdd33a-supply = <&reg_vcc3>;
+                reg-io-width = <4>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <2 0x2>;
+                reg = <4 0 0xff>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&lan9117_pins>;
+                phy-mode = "mii";
+                smsc,force-internal-phy;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 0bf40c90faba..1a57b61f5e24 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -74,6 +74,22 @@
                };
        };
+        isp1704: isp1704 {
+                compatible = "nxp,isp1704";
+                nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+                usb-phy = <&usb2_phy>;
+        };
+        tv: connector {
+                compatible = "composite-connector";
+                label = "tv";
+                port {
+                        tv_connector_in: endpoint {
+                                remote-endpoint = <&venc_out>;
+                        };
+                };
+        };
 };
 &omap3_pmx_core {
@@ -140,11 +156,23 @@
                >;
        };
-        display_pins: pinmux_display_pins {
+        acx565akm_pins: pinmux_acx565akm_pins {
                pinctrl-single,pins = <
                        0x0d4 (PIN_OUTPUT | MUX_MODE4)          /* RX51_LCD_RESET_GPIO */
                >;
        };
+        dss_sdi_pins: pinmux_dss_sdi_pins {
+                pinctrl-single,pins = <
+                        0x0c0 (PIN_OUTPUT | MUX_MODE1)   /* dss_data10.sdi_dat1n */
+                        0x0c2 (PIN_OUTPUT | MUX_MODE1)   /* dss_data11.sdi_dat1p */
+                        0x0c4 (PIN_OUTPUT | MUX_MODE1)   /* dss_data12.sdi_dat2n */
+                        0x0c6 (PIN_OUTPUT | MUX_MODE1)   /* dss_data13.sdi_dat2p */
+                        0x0d8 (PIN_OUTPUT | MUX_MODE1)   /* dss_data22.sdi_clkp */
+                        0x0da (PIN_OUTPUT | MUX_MODE1)   /* dss_data23.sdi_clkn */
+                >;
+        };
 };
 &i2c1 {
@@ -254,6 +282,61 @@
        };
 };
+&twl_keypad {
+        linux,keymap = < 0x00000010 /* KEY_Q */
+                         0x00010018 /* KEY_O */
+                         0x00020019 /* KEY_P */
+                         0x00030033 /* KEY_COMMA */
+                         0x0004000e /* KEY_BACKSPACE */
+                         0x0006001e /* KEY_A */
+                         0x0007001f /* KEY_S */
+                         0x01000011 /* KEY_W */
+                         0x01010020 /* KEY_D */
+                         0x01020021 /* KEY_F */
+                         0x01030022 /* KEY_G */
+                         0x01040023 /* KEY_H */
+                         0x01050024 /* KEY_J */
+                         0x01060025 /* KEY_K */
+                         0x01070026 /* KEY_L */
+                         0x02000012 /* KEY_E */
+                         0x02010034 /* KEY_DOT */
+                         0x02020067 /* KEY_UP */
+                         0x0203001c /* KEY_ENTER */
+                         0x0205002c /* KEY_Z */
+                         0x0206002d /* KEY_X */
+                         0x0207002e /* KEY_C */
+                         0x02080043 /* KEY_F9 */
+                         0x03000013 /* KEY_R */
+                         0x0301002f /* KEY_V */
+                         0x03020030 /* KEY_B */
+                         0x03030031 /* KEY_N */
+                         0x03040032 /* KEY_M */
+                         0x03050039 /* KEY_SPACE */
+                         0x03060039 /* KEY_SPACE */
+                         0x03070069 /* KEY_LEFT */
+                         0x04000014 /* KEY_T */
+                         0x0401006c /* KEY_DOWN */
+                         0x0402006a /* KEY_RIGHT */
+                         0x0404001d /* KEY_LEFTCTRL */
+                         0x04050064 /* KEY_RIGHTALT */
+                         0x0406002a /* KEY_LEFTSHIFT */
+                         0x04080044 /* KEY_F10 */
+                         0x05000015 /* KEY_Y */
+                         0x05080057 /* KEY_F11 */
+                         0x06000016 /* KEY_U */
+                         0x07000017 /* KEY_I */
+                         0x07010041 /* KEY_F7 */
+                         0x07020042 /* KEY_F8 */
+                         >;
+};
 &twl_gpio {
        ti,pullups      = <0x0>;
        ti,pulldowns    = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
@@ -291,6 +374,13 @@
                DVDD-supply = <&vio>;
        };
+        tsl2563: tsl2563@29 {
+                compatible = "amstaos,tsl2563";
+                reg = <0x29>;
+                amstaos,cover-comp-gain = <16>;
+        };
        lp5523: lp5523@32 {
                compatible = "national,lp5523";
                reg = <0x32>;
@@ -356,6 +446,29 @@
                compatible = "ti,bq27200";
                reg = <0x55>;
        };
+        tpa6130a2: tpa6130a2@60 {
+                compatible = "ti,tpa6130a2";
+                reg = <0x60>;
+                Vdd-supply = <&vmmc2>;
+                power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
+        };
+        bq24150a: bq24150a@6b {
+                compatible = "ti,bq24150a";
+                reg = <0x6b>;
+                ti,current-limit = <100>;
+                ti,weak-battery-voltage = <3400>;
+                ti,battery-regulation-voltage = <4200>;
+                ti,charge-current = <650>;
+                ti,termination-current = <100>;
+                ti,resistor-sense = <68>;
+                ti,usb-charger-detection = <&isp1704>;
+        };
 };
 &i2c3 {
@@ -471,13 +584,23 @@
                spi-max-frequency = <6000000>;
                reg = <0>;
        };
-        mipid@2 {
-                compatible = "acx565akm";
+        acx565akm@2 {
+                compatible = "sony,acx565akm";
                spi-max-frequency = <6000000>;
                reg = <2>;
                pinctrl-names = "default";
-                pinctrl-0 = <&display_pins>;
+                pinctrl-0 = <&acx565akm_pins>;
+                label = "lcd";
+                reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
+                port {
+                        lcd_in: endpoint {
+                                remote-endpoint = <&sdi_out>;
+                        };
+                };
        };
 };
@@ -503,3 +626,39 @@
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_pins>;
 };
+&dss {
+        status = "ok";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_sdi_pins>;
+        vdds_sdi-supply = <&vaux1>;
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@1 {
+                        reg = <1>;
+                        sdi_out: endpoint {
+                                remote-endpoint = <&lcd_in>;
+                                datapairs = <2>;
+                        };
+                };
+        };
+};
+&venc {
+        status = "ok";
+        vdda-supply = <&vdac>;
+        port {
+                venc_out: endpoint {
+                        remote-endpoint = <&tv_connector_in>;
+                        ti,channels = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi
new file mode 100644
index 000000000000..19d64864a109
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Alto35 expansion board is manufactured by Gumstix Inc.
+ */
+#include "omap3-overo-common-peripherals.dtsi"
+#include <dt-bindings/input/input.h>
+/ {
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+                gpio148 {
+                        label = "overo:red:gpio148";
+                        gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;           /* gpio 148 */
+                };
+                gpio150 {
+                        label = "overo:yellow:gpio150";
+                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;           /* gpio 150 */
+                };
+                gpio151 {
+                        label = "overo:blue:gpio151";
+                        gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;           /* gpio 151 */
+                };
+                gpio170 {
+                        label = "overo:green:gpio170";
+                        gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;           /* gpio 170 */
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&button_pins>;
+                button0@10 {
+                        label = "button0";
+                        linux,code = <BTN_0>;
+                        gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;            /* gpio_10 */
+                        gpio-key,wakeup;
+                };
+        };
+};
+&omap3_pmx_core {
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4)       /* uart1_tx.gpio_148 */
+                        OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4)       /* uart1_cts.gpio_150 */
+                        OMAP3_CORE1_IOPAD(0x2182, PIN_OUTPUT | MUX_MODE4)       /* uart1_rx.gpio_151 */
+                        OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4)       /* hdq_sio.gpio_170 */
+                >;
+        };
+};
+&omap3_pmx_wkup {
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4)         /* sys_clkout1.gpio_10 */
+                >;
+        };
+};
+&usbhshost {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3-overo-alto35.dts b/arch/arm/boot/dts/omap3-overo-alto35.dts
new file mode 100644
index 000000000000..a3249eb7501d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-alto35.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Alto35 expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo.dtsi"
+#include "omap3-overo-alto35-common.dtsi"
+/ {
+        model = "OMAP35xx Gumstix Overo on Alto35";
+        compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
+};
diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi
new file mode 100644
index 000000000000..d36bf0250a05
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-base.dtsi
@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * The Gumstix Overo must be combined with an expansion board.
+ */
+/ {
+        pwmleds {
+                compatible = "pwm-leds";
+                overo {
+                        label = "overo:blue:COM";
+                        pwms = <&twl_pwmled 1 7812500>;
+                        max-brightness = <127>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+        sound {
+                compatible = "ti,omap-twl4030";
+                ti,model = "overo";
+                ti,mcbsp = <&mcbsp2>;
+                ti,codec = <&twl_audio>;
+        };
+        /* HS USB Port 2 Power */
+        hsusb2_power: hsusb2_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio6 8 0>;                            /* gpio_168: vbus enable */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>;      /* gpio_183 */
+                vcc-supply = <&hsusb2_power>;
+        };
+        /* Regulator to trigger the nPoweron signal of the Wifi module */
+        w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-w3cbw003c-npoweron";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>;            /* gpio_54: nPoweron */
+                enable-active-high;
+        };
+        /* Regulator to trigger the nReset signal of the Wifi module */
+        w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset {
+                pinctrl-names = "default";
+                pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>;
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-w3cbw003c-wifi-nreset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;            /* gpio_16: WiFi nReset */
+                startup-delay-us = <10000>;
+        };
+        /* Regulator to trigger the nReset signal of the Bluetooth module */
+        w3cbw003c_bt_nreset: regulator-w3cbw003c-bt-nreset {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-w3cbw003c-bt-nreset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;             /* gpio_164: BT nReset */
+                startup-delay-us = <10000>;
+        };
+};
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusb2_pins
+        >;
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)        /* mcbsp3_dx.uart2_cts */
+                        OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1)       /* mcbsp3_dr.uart2_rts */
+                        OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)       /* mcbsp3_clk.uart2_tx */
+                        OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)        /* mcbsp3_fsx.uart2_rx */
+                >;
+        };
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)                /* i2c1_scl.i2c1_scl */
+                        OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)                /* i2c1_sda.i2c1_sda */
+                >;
+        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc1_dat3.sdmmc1_dat3 */
+                >;
+        };
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_clk.sdmmc2_clk */
+                        OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_cmd.sdmmc2_cmd */
+                        OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat0.sdmmc2_dat0 */
+                        OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat1.sdmmc2_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat2.sdmmc2_dat2 */
+                        OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)         /* sdmmc2_dat3.sdmmc2_dat3 */
+                >;
+        };
+        /* WiFi/BT combo */
+        w3cbw003c_pins: pinmux_w3cbw003c_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4)               /* gpmc_ncs3.gpio_54 */
+                        OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)               /* uart3_rts_sd.gpio_164 */
+                >;
+        };
+        hsusb2_pins: pinmux_hsusb2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
+                        OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
+                        OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
+                        OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
+                        OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
+                        OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
+                        OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4)               /* i2c2_scl.gpio_168 */
+                        OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4)               /* i2c2_sda.gpio_183 */
+                >;
+        };
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        clock-frequency = <2600000>;
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+                        codec {
+                        };
+                };
+        };
+};
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+/* i2c2 pins are used for gpio */
+&i2c2 {
+        status = "disabled";
+};
+/* on board microSD slot */
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+};
+/* optional on board WiFi */
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&w3cbw003c_npoweron>;
+        vqmmc-supply = <&w3cbw003c_bt_nreset>;
+        vmmc_aux-supply = <&w3cbw003c_wifi_nreset>;
+        bus-width = <4>;
+        cap-sdio-irq;
+        non-removable;
+};
+&twl_gpio {
+        ti,use-leds;
+};
+&usb_otg_hs {
+        interface-type = <0>;
+        usb-phy = <&usb2_phy>;
+        phys = <&usb2_phy>;
+        phy-names = "usb2-phy";
+        mode = <3>;
+        power = <50>;
+};
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+&usbhsehci {
+        phys = <0 &hsusb2_phy>;
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi
new file mode 100644
index 000000000000..19de6ff79686
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Chestnut43 expansion board is manufactured by Gumstix Inc.
+ */
+#include "omap3-overo-common-peripherals.dtsi"
+#include <dt-bindings/input/input.h>
+/ {
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+                heartbeat {
+                        label = "overo:red:gpio21";
+                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;            /* gpio_21 */
+                        linux,default-trigger = "heartbeat";
+                };
+                gpio22 {
+                        label = "overo:blue:gpio22";
+                        gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;            /* gpio_22 */
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&button_pins>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button0@23 {
+                        label = "button0";
+                        linux,code = <BTN_0>;
+                        gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;            /* gpio_23 */
+                        gpio-key,wakeup;
+                };
+                button1@14 {
+                        label = "button1";
+                        linux,code = <BTN_1>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;            /* gpio_14 */
+                        gpio-key,wakeup;
+                };
+        };
+};
+#include "omap-gpmc-smsc9221.dtsi"
+&gpmc {
+        ranges = <5 0 0x2c000000 0x1000000>;    /* CS5 */
+        ethernet@gpmc {
+                reg = <5 0 0xff>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;   /* GPIO 176 */
+        };
+};
+&lis33de {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-chestnut43.dts
new file mode 100644
index 000000000000..fe0824aca3c0
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-chestnut43.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Chestnut43 expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo.dtsi"
+#include "omap3-overo-chestnut43-common.dtsi"
+/ {
+        model = "OMAP35xx Gumstix Overo on Chestnut43";
+        compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
+};
+&omap3_pmx_core2 {
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)    /* etk_d7.gpio_21 */
+                        OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)    /* etk_d8.gpio_22 */
+                >;
+        };
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4)     /* etk_d9.gpio_23 */
+                        OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4)     /* etk_d0.gpio_14 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
new file mode 100644
index 000000000000..5831bcc52966
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...)
+ */
+/ {
+        lis33_3v3: lis33-3v3-reg {
+                compatible = "regulator-fixed";
+                regulator-name = "lis33-3v3-reg";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        lis33_1v8: lis33-1v8-reg {
+                compatible = "regulator-fixed";
+                regulator-name = "lis33-1v8-reg";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+};
+&omap3_pmx_core {
+        i2c3_pins: pinmux_i2c3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)        /* i2c3_scl.i2c3_scl */
+                        OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)        /* i2c3_sda.i2c3_sda */
+                >;
+        };
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)               /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+        clock-frequency = <100000>;
+        /* optional 1K EEPROM with revision information */
+        eeprom@51 {
+                compatible = "atmel,24c01";
+                reg = <0x51>;
+                pagesize = <8>;
+        };
+        lis33de: lis33de@1d {
+                compatible = "st,lis33de", "st,lis3lv02d";
+                reg = <0x1d>;
+                Vdd-supply = <&lis33_1v8>;
+                Vdd_IO-supply = <&lis33_3v3>;
+                st,click-single-x;
+                st,click-single-y;
+                st,click-single-z;
+                st,click-thresh-x = <10>;
+                st,click-thresh-y = <10>;
+                st,click-thresh-z = <10>;
+                st,irq1-click;
+                st,irq2-click;
+                st,wakeup-x-lo;
+                st,wakeup-x-hi;
+                st,wakeup-y-lo;
+                st,wakeup-y-hi;
+                st,wakeup-z-lo;
+                st,wakeup-z-hi;
+                st,min-limit-x = <120>;
+                st,min-limit-y = <120>;
+                st,min-limit-z = <140>;
+                st,max-limit-x = <550>;
+                st,max-limit-y = <550>;
+                st,max-limit-z = <750>;
+        };
+};
+&mmc3 {
+        status = "disabled";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi
new file mode 100644
index 000000000000..5e848c26986b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Gallop43 expansion board is manufactured by Gumstix Inc.
+ */
+#include "omap3-overo-common-peripherals.dtsi"
+#include <dt-bindings/input/input.h>
+/ {
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+                heartbeat {
+                        label = "overo:red:gpio21";
+                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;            /* gpio_21 */
+                        linux,default-trigger = "heartbeat";
+                };
+                gpio22 {
+                        label = "overo:blue:gpio22";
+                        gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;            /* gpio_22 */
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&button_pins>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button0@23 {
+                        label = "button0";
+                        linux,code = <BTN_0>;
+                        gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;            /* gpio_23 */
+                        gpio-key,wakeup;
+                };
+                button1@14 {
+                        label = "button1";
+                        linux,code = <BTN_1>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;            /* gpio_14 */
+                        gpio-key,wakeup;
+                };
+        };
+};
+&usbhshost {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3-overo-gallop43.dts b/arch/arm/boot/dts/omap3-overo-gallop43.dts
new file mode 100644
index 000000000000..241f5c1914e0
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-gallop43.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Gallop43 expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo.dtsi"
+#include "omap3-overo-gallop43-common.dtsi"
+/ {
+        model = "OMAP35xx Gumstix Overo on Gallop43";
+        compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
+};
+&omap3_pmx_core2 {
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)    /* etk_d7.gpio_21 */
+                        OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)    /* etk_d8.gpio_22 */
+                >;
+        };
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4)     /* etk_d9.gpio_23 */
+                        OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4)     /* etk_d0.gpio_14 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi
new file mode 100644
index 000000000000..abea232825b9
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Palo43 expansion board is manufactured by Gumstix Inc.
+ */
+#include "omap3-overo-common-peripherals.dtsi"
+#include <dt-bindings/input/input.h>
+/ {
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+                heartbeat {
+                        label = "overo:red:gpio21";
+                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;            /* gpio_21 */
+                        linux,default-trigger = "heartbeat";
+                };
+                gpio22 {
+                        label = "overo:blue:gpio22";
+                        gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;            /* gpio_22 */
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&button_pins>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button0@23 {
+                        label = "button0";
+                        linux,code = <BTN_0>;
+                        gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;            /* gpio_23 */
+                        gpio-key,wakeup;
+                };
+                button1@14 {
+                        label = "button1";
+                        linux,code = <BTN_1>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;            /* gpio_14 */
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-palo43.dts b/arch/arm/boot/dts/omap3-overo-palo43.dts
new file mode 100644
index 000000000000..cedb103b4b66
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-palo43.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Palo43 expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo.dtsi"
+#include "omap3-overo-palo43-common.dtsi"
+/ {
+        model = "OMAP35xx Gumstix Overo on Palo43";
+        compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
+};
+&omap3_pmx_core2 {
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)    /* etk_d7.gpio_21 */
+                        OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)    /* etk_d8.gpio_22 */
+                >;
+        };
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4)     /* etk_d9.gpio_23 */
+                        OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4)     /* etk_d0.gpio_14 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
new file mode 100644
index 000000000000..e9cae52afc25
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Alto35 expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo-storm.dtsi"
+#include "omap3-overo-alto35-common.dtsi"
+/ {
+        model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35";
+        compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
new file mode 100644
index 000000000000..7d82fdfd9909
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Chestnut43 expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo-storm.dtsi"
+#include "omap3-overo-chestnut43-common.dtsi"
+/ {
+        model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43";
+        compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+};
+&omap3_pmx_core2 {
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)    /* etk_d7.gpio_21 */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)    /* etk_d8.gpio_22 */
+                >;
+        };
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4)     /* etk_d9.gpio_23 */
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4)     /* etk_d0.gpio_14 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
new file mode 100644
index 000000000000..a1b57e0cf37f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Gallop43 expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo-storm.dtsi"
+#include "omap3-overo-gallop43-common.dtsi"
+/ {
+        model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43";
+        compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+};
+&omap3_pmx_core2 {
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)    /* etk_d7.gpio_21 */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)    /* etk_d8.gpio_22 */
+                >;
+        };
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4)     /* etk_d9.gpio_23 */
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4)     /* etk_d0.gpio_14 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
new file mode 100644
index 000000000000..b585d8fbc347
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Palo43 expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo-storm.dtsi"
+#include "omap3-overo-palo43-common.dtsi"
+/ {
+        model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43";
+        compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+};
+&omap3_pmx_core2 {
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)    /* etk_d7.gpio_21 */
+                        OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)    /* etk_d8.gpio_22 */
+                >;
+        };
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4)     /* etk_d9.gpio_23 */
+                        OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4)     /* etk_d0.gpio_14 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
new file mode 100644
index 000000000000..a0d7fd8369d7
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Summit expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo-storm.dtsi"
+#include "omap3-overo-summit-common.dtsi"
+/ {
+        model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit";
+        compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+};
+&omap3_pmx_core2 {
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)    /* etk_d7.gpio_21 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
index 966b5c9cd96a..879383acad87 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
@@ -12,7 +12,7 @@
 /dts-v1/;
-#include "omap36xx.dtsi"
+#include "omap3-overo-storm.dtsi"
 #include "omap3-overo-tobi-common.dtsi"
 / {
diff --git a/arch/arm/boot/dts/omap3-overo-storm.dtsi b/arch/arm/boot/dts/omap3-overo-storm.dtsi
new file mode 100644
index 000000000000..6cb418b4124a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "omap36xx.dtsi"
+#include "omap3-overo-base.dtsi"
+&omap3_pmx_core2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusb2_2_pins
+        >;
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                        OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                        OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
+        };
+        w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
+                pinctrl-single,pins = <
+                        OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)            /* etk_d2.gpio_16 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi b/arch/arm/boot/dts/omap3-overo-summit-common.dtsi
new file mode 100644
index 000000000000..999d1cd4a09f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-summit-common.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Summit expansion board is manufactured by Gumstix Inc.
+ */
+#include "omap3-overo-common-peripherals.dtsi"
+/ {
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+                heartbeat {
+                        label = "overo:red:gpio21";
+                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;            /* gpio_21 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+&lis33de {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3-overo-summit.dts b/arch/arm/boot/dts/omap3-overo-summit.dts
new file mode 100644
index 000000000000..69765609455a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-summit.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Summit expansion board is manufactured by Gumstix Inc.
+ */
+/dts-v1/;
+#include "omap3-overo.dtsi"
+#include "omap3-overo-summit-common.dtsi"
+/ {
+        model = "OMAP35xx Gumstix Overo on Summit";
+        compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
+};
+&omap3_pmx_core2 {
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)    /* etk_d7.gpio_21 */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
index 4edc013a91c1..13df50b39442 100644
--- a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
@@ -10,7 +10,7 @@
 * Tobi expansion board is manufactured by Gumstix Inc.
 */
-#include "omap3-overo.dtsi"
+#include "omap3-overo-common-peripherals.dtsi"
 / {
        leds {
@@ -21,60 +21,21 @@
                        linux,default-trigger = "heartbeat";
                };
        };
-        vddvario: regulator-vddvario {
-                  compatible = "regulator-fixed";
-                  regulator-name = "vddvario";
-                  regulator-always-on;
-        };
-        vdd33a: regulator-vdd33a {
-                compatible = "regulator-fixed";
-                regulator-name = "vdd33a";
-                regulator-always-on;
-        };
 };
+#include "omap-gpmc-smsc9221.dtsi"
 &gpmc {
        ranges = <5 0 0x2c000000 0x1000000>;    /* CS5 */
-        ethernet@5,0 {
+        ethernet@gpmc {
-                compatible = "smsc,lan9221", "smsc,lan9115";
                reg = <5 0 0xff>;
-                bank-width = <2>;
-                gpmc,mux-add-data;
-                gpmc,cs-on-ns = <0>;
-                gpmc,cs-rd-off-ns = <42>;
-                gpmc,cs-wr-off-ns = <36>;
-                gpmc,adv-on-ns = <6>;
-                gpmc,adv-rd-off-ns = <12>;
-                gpmc,adv-wr-off-ns = <12>;
-                gpmc,oe-on-ns = <0>;
-                gpmc,oe-off-ns = <42>;
-                gpmc,we-on-ns = <0>;
-                gpmc,we-off-ns = <36>;
-                gpmc,rd-cycle-ns = <60>;
-                gpmc,wr-cycle-ns = <54>;
-                gpmc,access-ns = <36>;
-                gpmc,page-burst-access-ns = <0>;
-                gpmc,bus-turnaround-ns = <0>;
-                gpmc,cycle2cycle-delay-ns = <0>;
-                gpmc,wr-data-mux-bus-ns = <18>;
-                gpmc,wr-access-ns = <42>;
-                gpmc,cycle2cycle-samecsen;
-                gpmc,cycle2cycle-diffcsen;
                interrupt-parent = <&gpio6>;
                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;   /* GPIO 176 */
-                reg-io-width = <4>;
        };
 };
-&i2c3 {
+&lis33de {
-        clock-frequency = <100000>;
-};
-&mmc3 {
        status = "disabled";
 };
diff --git a/arch/arm/boot/dts/omap3-overo-tobi.dts b/arch/arm/boot/dts/omap3-overo-tobi.dts
index de5653e1b5ca..fd6400efcdee 100644
--- a/arch/arm/boot/dts/omap3-overo-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-tobi.dts
@@ -12,7 +12,7 @@
 /dts-v1/;
-#include "omap34xx.dtsi"
+#include "omap3-overo.dtsi"
 #include "omap3-overo-tobi-common.dtsi"
 / {
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index 597099907f8e..69ca7c45bca2 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -1,94 +1,38 @@
 /*
- * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-/*
+#include "omap34xx.dtsi"
- * The Gumstix Overo must be combined with an expansion board.
+#include "omap3-overo-base.dtsi"
- */
-/ {
+&omap3_pmx_core2 {
-        pwmleds {
+        pinctrl-names = "default";
-                compatible = "pwm-leds";
+        pinctrl-0 = <
+                        &hsusb2_2_pins
-                overo {
+        >;
-                        label = "overo:blue:COM";
-                        pwms = <&twl_pwmled 1 7812500>;
-                        max-brightness = <127>;
-                        linux,default-trigger = "mmc0";
-                };
-        };
-        sound {
-                compatible = "ti,omap-twl4030";
-                ti,model = "overo";
-                ti,mcbsp = <&mcbsp2>;
-                ti,codec = <&twl_audio>;
-        };
-};
-&i2c1 {
-        clock-frequency = <2600000>;
-        twl: twl@48 {
-                reg = <0x48>;
-                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
-                interrupt-parent = <&intc>;
-                twl_audio: audio {
+        hsusb2_2_pins: pinmux_hsusb2_2_pins {
-                        compatible = "ti,twl4030-audio";
+                pinctrl-single,pins = <
-                        codec {
+                        OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
-                        };
+                        OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
-                };
+                        OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                        OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                        OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                        OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+                >;
        };
-};
-#include "twl4030.dtsi"
-#include "twl4030_omap3.dtsi"
-/* i2c2 pins are used for gpio */
-&i2c2 {
-        status = "disabled";
-};
-/* on board microSD slot */
+        w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
-&mmc1 {
-        vmmc-supply = <&vmmc1>;
-        bus-width = <4>;
-};
-/* optional on board WiFi */
-&mmc2 {
-        bus-width = <4>;
-};
-&twl_gpio {
-        ti,use-leds;
-};
-&usb_otg_hs {
-        interface-type = <0>;
-        usb-phy = <&usb2_phy>;
-        phys = <&usb2_phy>;
-        phy-names = "usb2-phy";
-        mode = <3>;
-        power = <50>;
-};
-&omap3_pmx_core {
-        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)            /* etk_d2.gpio_16 */
-                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
                >;
        };
 };
-&uart3 {
+&mcbsp2 {
-        pinctrl-names = "default";
+        status = "okay";
-        pinctrl-0 = <&uart3_pins>;
 };
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index b9a2fedce7ee..7909c51b05a5 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -2,11 +2,36 @@
 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
 */
+/ {
+        vddvario_sb_t35: regulator-vddvario-sb-t35 {
+                compatible = "regulator-fixed";
+                regulator-name = "vddvario";
+                regulator-always-on;
+        };
+        vdd33a_sb_t35: regulator-vdd33a-sb-t35 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
+};
+&omap3_pmx_core {
+        smsc2_pins: pinmux_smsc2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0)       /* gpmc_ncs4.gpmc_ncs4 */
+                        OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */
+                >;
+        };
+};
 &gpmc {
        ranges = <4 0 0x2d000000 0x01000000>;
        smsc2: ethernet@4,0 {
                compatible = "smsc,lan9221", "smsc,lan9115";
+                pinctrl-names = "default";
+                pinctrl-0 = <&smsc2_pins>;
                interrupt-parent = <&gpio3>;
                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
                reg = <4 0 0xff>;
@@ -32,8 +57,8 @@
                gpmc,wr-access-ns = <186>;
                gpmc,cycle2cycle-samecsen;
                gpmc,cycle2cycle-diffcsen;
-                vddvario-supply = <&vddvario>;
+                vddvario-supply = <&vddvario_sb_t35>;
-                vdd33a-supply = <&vdd33a>;
+                vdd33a-supply = <&vdd33a_sb_t35>;
                reg-io-width = <4>;
                smsc,save-mac-address;
        };
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
new file mode 100644
index 000000000000..024c9c6c682d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -0,0 +1,43 @@
+/*
+ * Suppport for CompuLab SBC-T3517 with CM-T3517
+ */
+#include "omap3-cm-t3517.dts"
+#include "omap3-sb-t35.dtsi"
+/ {
+        model = "CompuLab SBC-T3517 with CM-T3517";
+        compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
+};
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &sb_t35_usb_hub_pins
+                        &usb_hub_pins
+                    >;
+        mmc1_aux_pins: pinmux_mmc1_aux_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59   */
+                        OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */
+                >;
+        };
+        sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */
+                >;
+        };
+};
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &mmc1_pins
+                &mmc1_aux_pins
+        >;
+        wp-gpios =  <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59  */
+        cd-gpios =  <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */
+};
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
new file mode 100644
index 000000000000..bbbeea6b1988
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -0,0 +1,36 @@
+/*
+ * Suppport for CompuLab SBC-T3530 with CM-T3530
+ */
+#include "omap3-cm-t3530.dts"
+#include "omap3-sb-t35.dtsi"
+/ {
+        model = "CompuLab SBC-T3530 with CM-T3530";
+        compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+};
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sb_t35_usb_hub_pins>;
+        sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */
+                >;
+        };
+};
+/*
+ * The following ranges correspond to SMSC9x eth chips on CM-T3530 CoM and
+ * SB-T35 baseboard respectively.
+ * This setting includes both chips in SBC-T3530 board device tree.
+ */
+&gpmc {
+        ranges = <5 0 0x2c000000 0x01000000>,
+                 <4 0 0x2d000000 0x01000000>;
+};
+&mmc1 {
+        cd-gpios =  <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index c119bd545053..08e4a7086f22 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -10,21 +10,18 @@
        compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
 };
-&gpmc {
+&omap3_pmx_core {
-        ranges = <5 0 0x2c000000 0x01000000>,
-                 <4 0 0x2d000000 0x01000000>;
-};
-&smsc2 {
        pinctrl-names = "default";
-        pinctrl-0 = <&smsc2_pins>;
+        pinctrl-0 = <&sb_t35_usb_hub_pins>;
-};
-&omap3_pmx_core {
+        sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins {
-        smsc2_pins: pinmux_smsc2_pins {
                pinctrl-single,pins = <
-                        0x86 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_ncs4.gpmc_ncs4 */
+                        OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */
-                        0xa2 (PIN_INPUT_PULLUP | MUX_MODE4)     /* gpmc_wait3.gpio_65 */
                >;
        };
-};
-\ No newline at end of file
+};
+&gpmc {
+        ranges = <5 0 0x2c000000 0x01000000>,
+                 <4 0 0x2d000000 0x01000000>;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index a5fc83b9c835..5e5790f631eb 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -35,6 +35,11 @@
                        compatible = "arm,cortex-a8";
                        device_type = "cpu";
                        reg = <0x0>;
+                        clocks = <&dpll1_ck>;
+                        clock-names = "cpu";
+                        clock-latency = <300000>; /* From omap-cpufreq driver */
                };
        };
@@ -176,6 +181,22 @@
                        pinctrl-single,function-mask = <0xff1f>;
                };
+                omap3_scm_general: tisyscon@48002270 {
+                        compatible = "syscon";
+                        reg = <0x48002270 0x2f0>;
+                };
+                pbias_regulator: pbias_regulator {
+                        compatible = "ti,pbias-omap";
+                        reg = <0x2b0 0x4>;
+                        syscon = <&omap3_scm_general>;
+                        pbias_mmc_reg: pbias_mmc_omap2430 {
+                                regulator-name = "pbias_mmc_omap2430";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                };
                gpio1: gpio@48310000 {
                        compatible = "ti,omap3-gpio";
                        reg = <0x48310000 0x200>;
@@ -390,6 +411,7 @@
                        ti,dual-volt;
                        dmas = <&sdma 61>, <&sdma 62>;
                        dma-names = "tx", "rx";
+                        pbias-supply = <&pbias_mmc_reg>;
                };
                mmc2: mmc@480b4000 {
@@ -411,10 +433,19 @@
                };
                mmu_isp: mmu@480bd400 {
-                        compatible = "ti,omap3-mmu-isp";
+                        compatible = "ti,omap2-iommu";
-                        ti,hwmods = "mmu_isp";
                        reg = <0x480bd400 0x80>;
-                        interrupts = <8>;
+                        interrupts = <24>;
+                        ti,hwmods = "mmu_isp";
+                        ti,#tlb-entries = <8>;
+                };
+                mmu_iva: mmu@5d000000 {
+                        compatible = "ti,omap2-iommu";
+                        reg = <0x5d000000 0x80>;
+                        interrupts = <28>;
+                        ti,hwmods = "mmu_iva";
+                        status = "disabled";
                };
                wdt2: wdt@48314000 {
@@ -436,6 +467,7 @@
                        dmas = <&sdma 31>,
                               <&sdma 32>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp2: mcbsp@49022000 {
@@ -453,6 +485,7 @@
                        dmas = <&sdma 33>,
                               <&sdma 34>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp3: mcbsp@49024000 {
@@ -470,6 +503,7 @@
                        dmas = <&sdma 17>,
                               <&sdma 18>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp4: mcbsp@49026000 {
@@ -485,6 +519,7 @@
                        dmas = <&sdma 19>,
                               <&sdma 20>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp5: mcbsp@48096000 {
@@ -500,6 +535,7 @@
                        dmas = <&sdma 21>,
                               <&sdma 22>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                sham: sham@480c3000 {
@@ -634,14 +670,14 @@
                        ranges;
                        usbhsohci: ohci@48064400 {
-                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                compatible = "ti,ohci-omap3";
                                reg = <0x48064400 0x400>;
                                interrupt-parent = <&intc>;
                                interrupts = <76>;
                        };
                        usbhsehci: ehci@48064800 {
-                                compatible = "ti,ehci-omap", "usb-ehci";
+                                compatible = "ti,ehci-omap";
                                reg = <0x48064800 0x400>;
                                interrupt-parent = <&intc>;
                                interrupts = <77>;
@@ -669,6 +705,58 @@
                        num-eps = <16>;
                        ram-bits = <12>;
                };
+                dss: dss@48050000 {
+                        compatible = "ti,omap3-dss";
+                        reg = <0x48050000 0x200>;
+                        status = "disabled";
+                        ti,hwmods = "dss_core";
+                        clocks = <&dss1_alwon_fck>;
+                        clock-names = "fck";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        dispc@48050400 {
+                                compatible = "ti,omap3-dispc";
+                                reg = <0x48050400 0x400>;
+                                interrupts = <25>;
+                                ti,hwmods = "dss_dispc";
+                                clocks = <&dss1_alwon_fck>;
+                                clock-names = "fck";
+                        };
+                        dsi: encoder@4804fc00 {
+                                compatible = "ti,omap3-dsi";
+                                reg = <0x4804fc00 0x200>,
+                                      <0x4804fe00 0x40>,
+                                      <0x4804ff00 0x20>;
+                                reg-names = "proto", "phy", "pll";
+                                interrupts = <25>;
+                                status = "disabled";
+                                ti,hwmods = "dss_dsi1";
+                                clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
+                                clock-names = "fck", "sys_clk";
+                        };
+                        rfbi: encoder@48050800 {
+                                compatible = "ti,omap3-rfbi";
+                                reg = <0x48050800 0x100>;
+                                status = "disabled";
+                                ti,hwmods = "dss_rfbi";
+                                clocks = <&dss1_alwon_fck>, <&dss_ick>;
+                                clock-names = "fck", "ick";
+                        };
+                        venc: encoder@48050c00 {
+                                compatible = "ti,omap3-venc";
+                                reg = <0x48050c00 0x100>;
+                                status = "disabled";
+                                ti,hwmods = "dss_venc";
+                                clocks = <&dss_tv_fck>;
+                                clock-names = "fck";
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 281914ed0151..02f69f4a8fd3 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -34,6 +34,10 @@
 &mmc1 {
        vmmc-supply = <&vmmc1>;
        vmmc_aux-supply = <&vsim>;
+        /*
+         * S6-3 must be in ON position for 8 bit mode to function
+         * Else, use 4 bit mode
+         */
        bus-width = <8>;
 };
@@ -103,9 +107,8 @@
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <1 0 0x08000000>;
+                ti,nand-ecc-opt = "ham1";
                nand-bus-width = <8>;
-                ti,nand-ecc-opt = "sw";
                gpmc,cs-on-ns = <0>;
                gpmc,cs-rd-off-ns = <36>;
                gpmc,cs-wr-off-ns = <36>;
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
index 02f6c7fabbec..4c22f3a7f813 100644
--- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -82,16 +82,16 @@
                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
        };
-        ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
+        ssi_ssr_fck: ssi_ssr_fck_3430es1 {
                #clock-cells = <0>;
                compatible = "ti,composite-clock";
                clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
        };
-        ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+        ssi_sst_fck: ssi_sst_fck_3430es1 {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
-                clocks = <&ssi_ssr_fck_3430es1>;
+                clocks = <&ssi_ssr_fck>;
                clock-mult = <1>;
                clock-div = <2>;
        };
@@ -120,7 +120,7 @@
                clock-div = <1>;
        };
-        ssi_ick_3430es1: ssi_ick_3430es1 {
+        ssi_ick: ssi_ick_3430es1 {
                #clock-cells = <0>;
                compatible = "ti,omap3-no-wait-interface-clock";
                clocks = <&ssi_l4_ick>;
@@ -152,7 +152,7 @@
                clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
        };
-        dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
+        dss1_alwon_fck: dss1_alwon_fck_3430es1 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
                clocks = <&dpll4_m4x2_ck>;
@@ -161,7 +161,7 @@
                ti,set-rate-parent;
        };
-        dss_ick_3430es1: dss_ick_3430es1 {
+        dss_ick: dss_ick_3430es1 {
                #clock-cells = <0>;
                compatible = "ti,omap3-no-wait-interface-clock";
                clocks = <&l4_ick>;
@@ -184,7 +184,7 @@
        dss_clkdm: dss_clkdm {
                compatible = "ti,clockdomain";
                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
-                         <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
+                         <&dss1_alwon_fck>, <&dss_ick>;
        };
        d2d_clkdm: d2d_clkdm {
@@ -203,6 +203,6 @@
                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
-                         <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
+                         <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
        };
 };
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
index af9ae5346bf2..080fb3f4e429 100644
--- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -160,7 +160,7 @@
                ti,bit-shift = <30>;
        };
-        dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
+        dss1_alwon_fck: dss1_alwon_fck_3430es2 {
                #clock-cells = <0>;
                compatible = "ti,dss-gate-clock";
                clocks = <&dpll4_m4x2_ck>;
@@ -169,7 +169,7 @@
                ti,set-rate-parent;
        };
-        dss_ick_3430es2: dss_ick_3430es2 {
+        dss_ick: dss_ick_3430es2 {
                #clock-cells = <0>;
                compatible = "ti,omap3-dss-interface-clock";
                clocks = <&l4_ick>;
@@ -216,7 +216,7 @@
        dss_clkdm: dss_clkdm {
                compatible = "ti,clockdomain";
                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
-                         <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+                         <&dss1_alwon_fck>, <&dss_ick>;
        };
        core_l4_clkdm: core_l4_clkdm {
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
index 2fcf253b677c..6b5280d04a0e 100644
--- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -70,6 +70,26 @@
        };
 };
+&dpll4_m2x2_mul_ck {
+        clock-mult = <1>;
+};
+&dpll4_m3x2_mul_ck {
+        clock-mult = <1>;
+};
+&dpll4_m4x2_mul_ck {
+        ti,clock-mult = <1>;
+};
+&dpll4_m5x2_mul_ck {
+        clock-mult = <1>;
+};
+&dpll4_m6x2_mul_ck {
+        clock-mult = <1>;
+};
 &cm_clockdomains {
        dpll4_clkdm: dpll4_clkdm {
                compatible = "ti,clockdomain";
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
index 8ed475dd63c9..877318c28364 100644
--- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -25,16 +25,16 @@
                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
        };
-        ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
+        ssi_ssr_fck: ssi_ssr_fck_3430es2 {
                #clock-cells = <0>;
                compatible = "ti,composite-clock";
                clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
        };
-        ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+        ssi_sst_fck: ssi_sst_fck_3430es2 {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
-                clocks = <&ssi_ssr_fck_3430es2>;
+                clocks = <&ssi_ssr_fck>;
                clock-mult = <1>;
                clock-div = <2>;
        };
@@ -55,7 +55,7 @@
                clock-div = <1>;
        };
-        ssi_ick_3430es2: ssi_ick_3430es2 {
+        ssi_ick: ssi_ick_3430es2 {
                #clock-cells = <0>;
                compatible = "ti,omap3-ssi-interface-clock";
                clocks = <&ssi_l4_ick>;
@@ -193,6 +193,6 @@
                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
-                         <&ssi_ick_3430es2>;
+                         <&ssi_ick>;
        };
 };
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 7e8dee9175d6..22cf4647087e 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -39,6 +39,26 @@
                        clock-frequency = <48000000>;
                };
+                abb_mpu_iva: regulator-abb-mpu {
+                        compatible = "ti,abb-v1";
+                        regulator-name = "abb_mpu_iva";
+                        #address-cell = <0>;
+                        #size-cells = <0>;
+                        reg = <0x483072f0 0x8>, <0x48306818 0x4>;
+                        reg-names = "base-address", "int-address";
+                        ti,tranxdone-status-mask = <0x4000000>;
+                        clocks = <&sys_ck>;
+                        ti,settling-time = <30>;
+                        ti,clock-cycles = <8>;
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m   fbb_m   vset_m*/
+                        1012500         0       0       0       0       0
+                        1200000         0       0       0       0       0
+                        1325000         0       0       0       0       0
+                        1375000         1       0       0       0       0
+                        >;
+                };
                omap3_pmx_core2: pinmux@480025a0 {
                        compatible = "ti,omap3-padconf", "pinctrl-single";
                        reg = <0x480025a0 0x5c>;
@@ -52,7 +72,13 @@
        };
 };
-/include/ "omap36xx-clocks.dtsi"
+/* OMAP3630 needs dss_96m_fck for VENC */
+&venc {
+        clocks = <&dss_tv_fck>, <&dss_96m_fck>;
+        clock-names = "fck", "tv_dac_clk";
+};
 /include/ "omap34xx-omap36xx-clocks.dtsi"
 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index cb04d4b37e7f..12be2b35dae9 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -425,10 +425,11 @@
        dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
                #clock-cells = <0>;
-                compatible = "fixed-factor-clock";
+                compatible = "ti,fixed-factor-clock";
                clocks = <&dpll4_m4_ck>;
-                clock-mult = <2>;
+                ti,clock-mult = <2>;
-                clock-div = <1>;
+                ti,clock-div = <1>;
+                ti,set-rate-parent;
        };
        dpll4_m4x2_ck: dpll4_m4x2_ck {
@@ -438,6 +439,7 @@
                ti,bit-shift = <0x1d>;
                reg = <0x0d00>;
                ti,set-bit-to-disable;
+                ti,set-rate-parent;
        };
        dpll4_m5_ck: dpll4_m5_ck {
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts
new file mode 100644
index 000000000000..96f51d870812
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "omap4-duovero.dtsi"
+#include <dt-bindings/input/input.h>
+/ {
+        model = "OMAP4430 Gumstix Duovero on Parlor";
+        compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
+        leds {
+                compatible = "gpio-leds";
+                led0 {
+                        label = "duovero:blue:led0";
+                        gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;   /* gpio_122 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button0@121 {
+                        label = "button0";
+                        linux,code = <BTN_0>;
+                        gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;    /* gpio_121 */
+                        gpio-key,wakeup;
+                };
+        };
+};
+&omap4_pmx_core {
+        pinctrl-0 = <
+                        &led_pins
+                        &button_pins
+                        &smsc_pins
+        >;
+        led_pins: pinmux_led_pins {
+                pinctrl-single,pins = <
+                        0xd6 (PIN_OUTPUT | MUX_MODE3)           /* abe_dmic_din3.gpio_122 */
+                >;
+        };
+        button_pins: pinmux_button_pins {
+                pinctrl-single,pins = <
+                        0xd4 (PIN_INPUT_PULLUP | MUX_MODE3)     /* abe_dmic_din2.gpio_121 */
+                >;
+        };
+        i2c2_pins: pinmux_i2c2_pins {
+                pinctrl-single,pins = <
+                        0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_scl */
+                        0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_sda */
+                >;
+        };
+        i2c3_pins: pinmux_i2c3_pins {
+                pinctrl-single,pins = <
+                        0xea (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_scl */
+                        0xec (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_sda */
+                >;
+        };
+        smsc_pins: pinmux_smsc_pins {
+                pinctrl-single,pins = <
+                        0x28 (PIN_INPUT | MUX_MODE3)            /* gpmc_a20.gpio_44: IRQ */
+                        0x2a (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a21.gpio_45: nReset */
+                        0x30 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a24.gpio_48: amdix enabled */
+                >;
+        };
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+        clock-frequency = <400000>;
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+        clock-frequency = <100000>;
+        /* optional 1K EEPROM with revision information */
+        eeprom@51 {
+                compatible = "atmel,24c01";
+                reg = <0x51>;
+                pagesize = <8>;
+        };
+};
+&mmc3 {
+        status = "disabled";
+};
+#include "omap-gpmc-smsc911x.dtsi"
+&gpmc {
+        ranges = <5 0 0x2c000000 0x1000000>;                    /* CS5 */
+        ethernet@gpmc {
+                reg = <5 0 0xff>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <12 IRQ_TYPE_LEVEL_LOW>;           /* gpio_44 */
+                phy-mode = "mii";
+                gpmc,cs-on-ns = <10>;
+                gpmc,cs-rd-off-ns = <50>;
+                gpmc,cs-wr-off-ns = <50>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <10>;
+                gpmc,adv-wr-off-ns = <10>;
+                gpmc,oe-on-ns = <15>;
+                gpmc,oe-off-ns = <50>;
+                gpmc,we-on-ns = <15>;
+                gpmc,we-off-ns = <50>;
+                gpmc,rd-cycle-ns = <50>;
+                gpmc,wr-cycle-ns = <50>;
+                gpmc,access-ns = <50>;
+                gpmc,page-burst-access-ns = <0>;
+                gpmc,bus-turnaround-ns = <35>;
+                gpmc,cycle2cycle-delay-ns = <35>;
+                gpmc,wr-data-mux-bus-ns = <35>;
+                gpmc,wr-access-ns = <50>;
+                gpmc,mux-add-data = <2>;
+                gpmc,sync-read;
+                gpmc,sync-write;
+                gpmc,clk-activation-ns = <5>;
+                gpmc,sync-clk-ps = <20000>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi
new file mode 100644
index 000000000000..a514791154eb
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-duovero.dtsi
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "omap443x.dtsi"
+/ {
+        model = "Gumstix Duovero";
+        compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+        sound {
+                compatible = "ti,abe-twl6040";
+                ti,model = "DuoVero";
+                ti,mclk-freq = <38400000>;
+                ti,mcpdm = <&mcpdm>;
+                ti,twl6040 = <&twl6040>;
+                /* Audio routing */
+                ti,audio-routing =
+                        "Headset Stereophone", "HSOL",
+                        "Headset Stereophone", "HSOR",
+                        "HSMIC", "Headset Mic",
+                        "Headset Mic", "Headset Mic Bias";
+        };
+        /* HS USB Host PHY on PORT 1 */
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+                reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;      /* gpio_62 */
+                pinctrl-names = "default";
+                pinctrl-0 = <&hsusb1phy_pins>;
+                clocks = <&auxclk3_ck>;
+                clock-names = "main_clk";
+                clock-frequency = <19200000>;
+        };
+        /* regulator for w2cbw0015 on sdio5 */
+        w2cbw0015_vmmc: w2cbw0015_vmmc {
+                pinctrl-names = "default";
+                pinctrl-0 = <&w2cbw0015_pins>;
+                compatible = "regulator-fixed";
+                regulator-name = "w2cbw0015";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+                gpio = <&gpio2 11 GPIO_ACTIVE_LOW>;             /* gpio_43 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+};
+&omap4_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6040_pins
+                        &mcpdm_pins
+                        &mcbsp1_pins
+                        &hsusbb1_pins
+        >;
+        twl6040_pins: pinmux_twl6040_pins {
+                pinctrl-single,pins = <
+                        0x126 (PIN_OUTPUT | MUX_MODE3)          /* usbb2_ulpitll_nxt.gpio_160 */
+                        0x160 (PIN_INPUT | MUX_MODE0)           /* sys_nirq2.sys_nirq2 */
+                >;
+        };
+        mcpdm_pins: pinmux_mcpdm_pins {
+                pinctrl-single,pins = <
+                        0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_ul_data.abe_pdm_ul_data */
+                        0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_dl_data.abe_pdm_dl_data */
+                        0xca (PIN_INPUT_PULLUP   | MUX_MODE0)   /* abe_pdm_frame.abe_pdm_frame */
+                        0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_lb_clk.abe_pdm_lb_clk */
+                        0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_clks.abe_clks */
+                >;
+        };
+        mcbsp1_pins: pinmux_mcbsp1_pins {
+                pinctrl-single,pins = <
+                        0xbe (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+                        0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+                        0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+                        0xc4 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
+                >;
+        };
+        hsusbb1_pins: pinmux_hsusbb1_pins {
+                pinctrl-single,pins = <
+                        0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
+                        0x84 (PIN_OUTPUT | MUX_MODE4)           /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
+                        0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
+                        0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
+                        0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
+                        0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
+                        0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
+                        0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
+                        0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
+                        0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
+                        0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
+                        0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
+                >;
+        };
+        hsusb1phy_pins: pinmux_hsusb1phy_pins {
+                pinctrl-single,pins = <
+                        0x4c (PIN_OUTPUT | MUX_MODE3)           /* gpmc_wait1.gpio_62 */
+                >;
+        };
+        w2cbw0015_pins: pinmux_w2cbw0015_pins {
+                pinctrl-single,pins = <
+                        0x26 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_a19.gpio_43 */
+                        0x3a (PIN_INPUT | MUX_MODE3)            /* gpmc_ncs3.gpio_53 */
+                >;
+        };
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_scl */
+                        0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_sda */
+                >;
+        };
+        i2c4_pins: pinmux_i2c4_pins {
+                pinctrl-single,pins = <
+                        0xee (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_scl */
+                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_sda */
+                >;
+        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        0xa2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmmc1_clk */
+                        0xa4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmcc1_cmd */
+                        0xa6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmcc1_dat0 */
+                        0xa8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmmc1_dat1 */
+                        0xaa (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmmc1_dat2 */
+                        0xac (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmmc1_dat3 */
+                >;
+        };
+        mmc5_pins: pinmux_mmc5_pins {
+                pinctrl-single,pins = <
+                        0x108 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc5_clk */
+                        0x10a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmcc5_cmd */
+                        0x10c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmcc5_dat0 */
+                        0x10e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc5_dat1 */
+                        0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc5_dat2 */
+                        0x112 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc5_dat3 */
+                >;
+        };
+};
+/* PMIC */
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        clock-frequency = <400000>;
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;           /* IRQ_SYS_1N cascaded to gic */
+                interrupt-parent = <&gic>;
+        };
+        twl6040: twl@4b {
+                compatible = "ti,twl6040";
+                reg = <0x4b>;
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;         /* IRQ_SYS_2N cascaded to gic */
+                interrupt-parent = <&gic>;
+                ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>;         /* gpio_160 */
+                vio-supply = <&v1v8>;
+                v2v1-supply = <&v2v1>;
+                enable-active-high;
+        };
+};
+#include "twl6030.dtsi"
+#include "twl6030_omap4.dtsi"
+/* on-board bluetooth / WiFi module */
+&i2c4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c4_pins>;
+        clock-frequency = <400000>;
+};
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&vmmc>;
+        ti,bus-width = <4>;
+        ti,non-removable;               /* FIXME: use PMIC_MMC detect */
+};
+&mmc2 {
+        status = "disabled";
+};
+/* mmc3 is available to the expansion board */
+&mmc4 {
+        status = "disabled";
+};
+/* on-board WiFi module */
+&mmc5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc5_pins>;
+        vmmc-supply = <&w2cbw0015_vmmc>;
+        ti,bus-width = <4>;
+        ti,non-removable;
+        cap-power-off-card;
+};
+&twl_usb_comparator {
+        usb-supply = <&vusb>;
+};
+&usb_otg_hs {
+        interface-type = <1>;
+        mode = <3>;
+        power = <50>;
+};
+&usbhshost {
+        port1-mode = "ehci-phy";
+};
+&usbhsehci {
+        phys = <&hsusb1_phy>;
+};
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 88c6a05cab41..d2c45bfaaa2c 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,6 +16,11 @@
                reg = <0x80000000 0x40000000>; /* 1 GB */
        };
+        aliases {
+                display0 = &dvi0;
+                display1 = &hdmi0;
+        };
        leds: leds {
                compatible = "gpio-leds";
                pinctrl-names = "default";
@@ -83,12 +88,8 @@
                compatible = "usb-nop-xceiv";
                reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;   /* gpio_62 */
                vcc-supply = <&hsusb1_power>;
-        /**
+                clocks = <&auxclk3_ck>;
-         * FIXME:
+                clock-names = "main_clk";
-         * put the right clock phandle here when available
-         *      clocks = <&auxclk3>;
-         *      clock-names = "main_clk";
-         */
                clock-frequency = <19200000>;
        };
@@ -104,14 +105,94 @@
                startup-delay-us = <70000>;
                enable-active-high;
        };
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+                powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;   /* gpio_0 */
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+        dvi0: connector@0 {
+                compatible = "dvi-connector";
+                label = "dvi";
+                digital;
+                ddc-i2c-bus = <&i2c3>;
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
+        tpd12s015: encoder@1 {
+                compatible = "ti,tpd12s015";
+                gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,   /* 60, CT CP HPD */
+                        <&gpio2 9 GPIO_ACTIVE_HIGH>,    /* 41, LS OE */
+                        <&gpio2 31 GPIO_ACTIVE_HIGH>;   /* 63, HPD */
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tpd12s015_in: endpoint@0 {
+                                        remote-endpoint = <&hdmi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tpd12s015_out: endpoint@0 {
+                                        remote-endpoint = <&hdmi_connector_in>;
+                                };
+                        };
+                };
+        };
+        hdmi0: connector@1 {
+                compatible = "hdmi-connector";
+                label = "hdmi";
+                type = "a";
+                port {
+                        hdmi_connector_in: endpoint {
+                                remote-endpoint = <&tpd12s015_out>;
+                        };
+                };
+        };
 };
 &omap4_pmx_core {
        pinctrl-names = "default";
        pinctrl-0 = <
-                        &twl6040_pins
-                        &mcpdm_pins
-                        &mcbsp1_pins
                        &dss_dpi_pins
                        &tfp410_pins
                        &dss_hdmi_pins
@@ -300,6 +381,10 @@
        twl6040: twl@4b {
                compatible = "ti,twl6040";
                reg = <0x4b>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&twl6040_pins>;
                /* IRQ# = 119 */
                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
                interrupt-parent = <&gic>;
@@ -380,16 +465,16 @@
        device-handle = <&elpida_ECB240ABACN>;
 };
-&mcbsp2 {
+&mcbsp1 {
-        status = "disabled";
+        pinctrl-names = "default";
-};
+        pinctrl-0 = <&mcbsp1_pins>;
+        status = "okay";
-&mcbsp3 {
-        status = "disabled";
 };
-&dmic {
+&mcpdm {
-        status = "disabled";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcpdm_pins>;
+        status = "okay";
 };
 &twl_usb_comparator {
@@ -409,3 +494,30 @@
 &usbhsehci {
        phys = <&hsusb1_phy>;
 };
+&dss {
+        status = "ok";
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+&dsi2 {
+        status = "ok";
+        vdd-supply = <&vcxio>;
+};
+&hdmi {
+        status = "ok";
+        vdda-supply = <&vdac>;
+        port {
+                hdmi_out: endpoint {
+                        remote-endpoint = <&tpd12s015_in>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index dbc81fb6ef03..48983c8d56c2 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -19,6 +19,12 @@
                reg = <0x80000000 0x40000000>; /* 1 GB */
        };
+        aliases {
+                display0 = &lcd0;
+                display1 = &lcd1;
+                display2 = &hdmi0;
+        };
        vdd_eth: fixedregulator-vdd-eth {
                compatible = "regulator-fixed";
                regulator-name = "VDD_ETH";
@@ -153,16 +159,53 @@
                startup-delay-us = <70000>;
                enable-active-high;
        };
+        tpd12s015: encoder@0 {
+                compatible = "ti,tpd12s015";
+                gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,   /* 60, CT CP HPD */
+                        <&gpio2 9 GPIO_ACTIVE_HIGH>,    /* 41, LS OE */
+                        <&gpio2 31 GPIO_ACTIVE_HIGH>;   /* 63, HPD */
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tpd12s015_in: endpoint@0 {
+                                        remote-endpoint = <&hdmi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tpd12s015_out: endpoint@0 {
+                                        remote-endpoint = <&hdmi_connector_in>;
+                                };
+                        };
+                };
+        };
+        hdmi0: connector@0 {
+                compatible = "hdmi-connector";
+                label = "hdmi";
+                type = "c";
+                port {
+                        hdmi_connector_in: endpoint {
+                                remote-endpoint = <&tpd12s015_out>;
+                        };
+                };
+        };
 };
 &omap4_pmx_core {
        pinctrl-names = "default";
        pinctrl-0 = <
-                        &twl6040_pins
-                        &mcpdm_pins
-                        &dmic_pins
-                        &mcbsp1_pins
-                        &mcbsp2_pins
                        &dss_hdmi_pins
                        &tpd12s015_pins
        >;
@@ -326,6 +369,10 @@
        twl6040: twl@4b {
                compatible = "ti,twl6040";
                reg = <0x4b>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&twl6040_pins>;
                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
                interrupt-parent = <&gic>;
@@ -537,8 +584,28 @@
        pinctrl-0 = <&uart4_pins>;
 };
-&mcbsp3 {
+&mcbsp1 {
-        status = "disabled";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp1_pins>;
+        status = "okay";
+};
+&mcbsp2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp2_pins>;
+        status = "okay";
+};
+&dmic {
+        pinctrl-names = "default";
+        pinctrl-0 = <&dmic_pins>;
+        status = "okay";
+};
+&mcpdm {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcpdm_pins>;
+        status = "okay";
 };
 &twl_usb_comparator {
@@ -550,3 +617,68 @@
        mode = <3>;
        power = <50>;
 };
+&dss {
+        status = "ok";
+};
+&dsi1 {
+        status = "ok";
+        vdd-supply = <&vcxio>;
+        port {
+                dsi1_out_ep: endpoint {
+                        remote-endpoint = <&lcd0_in>;
+                        lanes = <0 1 2 3 4 5>;
+                };
+        };
+        lcd0: display {
+                compatible = "tpo,taal", "panel-dsi-cm";
+                label = "lcd0";
+                reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;      /* 102 */
+                port {
+                        lcd0_in: endpoint {
+                                remote-endpoint = <&dsi1_out_ep>;
+                        };
+                };
+        };
+};
+&dsi2 {
+        status = "ok";
+        vdd-supply = <&vcxio>;
+        port {
+                dsi2_out_ep: endpoint {
+                        remote-endpoint = <&lcd1_in>;
+                        lanes = <0 1 2 3 4 5>;
+                };
+        };
+        lcd1: display {
+                compatible = "tpo,taal", "panel-dsi-cm";
+                label = "lcd1";
+                reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;      /* 104 */
+                port {
+                        lcd1_in: endpoint {
+                                remote-endpoint = <&dsi2_out_ep>;
+                        };
+                };
+        };
+};
+&hdmi {
+        status = "ok";
+        vdda-supply = <&vdac>;
+        port {
+                hdmi_out: endpoint {
+                        remote-endpoint = <&tpd12s015_in>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index d3f8a6e8ca20..27fcac874742 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -36,6 +36,11 @@
                        device_type = "cpu";
                        next-level-cache = <&L2>;
                        reg = <0x0>;
+                        clocks = <&dpll_mpu_ck>;
+                        clock-names = "cpu";
+                        clock-latency = <300000>; /* From omap-cpufreq driver */
                };
                cpu@1 {
                        compatible = "arm,cortex-a9";
@@ -186,6 +191,22 @@
                        pinctrl-single,function-mask = <0x7fff>;
                };
+                omap4_padconf_global: tisyscon@4a1005a0 {
+                        compatible = "syscon";
+                        reg = <0x4a1005a0 0x170>;
+                };
+                pbias_regulator: pbias_regulator {
+                        compatible = "ti,pbias-omap";
+                        reg = <0x60 0x4>;
+                        syscon = <&omap4_padconf_global>;
+                        pbias_mmc_reg: pbias_mmc_omap4 {
+                                regulator-name = "pbias_mmc_omap4";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                };
                sdma: dma-controller@4a056000 {
                        compatible = "ti,omap4430-sdma";
                        reg = <0x4a056000 0x1000>;
@@ -275,6 +296,8 @@
                        gpmc,num-waitpins = <4>;
                        ti,hwmods = "gpmc";
                        ti,no-idle-on-init;
+                        clocks = <&l3_div_ck>;
+                        clock-names = "fck";
                };
                uart1: serial@4806a000 {
@@ -313,6 +336,7 @@
                        compatible = "ti,omap4-hwspinlock";
                        reg = <0x4a0f6000 0x1000>;
                        ti,hwmods = "spinlock";
+                        #hwlock-cells = <1>;
                };
                i2c1: i2c@48070000 {
@@ -419,6 +443,7 @@
                        ti,needs-special-reset;
                        dmas = <&sdma 61>, <&sdma 62>;
                        dma-names = "tx", "rx";
+                        pbias-supply = <&pbias_mmc_reg>;
                };
                mmc2: mmc@480b4000 {
@@ -461,6 +486,21 @@
                        dma-names = "tx", "rx";
                };
+                mmu_dsp: mmu@4a066000 {
+                        compatible = "ti,omap4-iommu";
+                        reg = <0x4a066000 0x100>;
+                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "mmu_dsp";
+                };
+                mmu_ipu: mmu@55082000 {
+                        compatible = "ti,omap4-iommu";
+                        reg = <0x55082000 0x100>;
+                        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "mmu_ipu";
+                        ti,iommu-bus-err-back;
+                };
                wdt2: wdt@4a314000 {
                        compatible = "ti,omap4-wdt", "ti,omap3-wdt";
                        reg = <0x4a314000 0x80>;
@@ -478,6 +518,7 @@
                        dmas = <&sdma 65>,
                               <&sdma 66>;
                        dma-names = "up_link", "dn_link";
+                        status = "disabled";
                };
                dmic: dmic@4012e000 {
@@ -489,6 +530,7 @@
                        ti,hwmods = "dmic";
                        dmas = <&sdma 67>;
                        dma-names = "up_link";
+                        status = "disabled";
                };
                mcbsp1: mcbsp@40122000 {
@@ -503,6 +545,7 @@
                        dmas = <&sdma 33>,
                               <&sdma 34>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp2: mcbsp@40124000 {
@@ -517,6 +560,7 @@
                        dmas = <&sdma 17>,
                               <&sdma 18>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp3: mcbsp@40126000 {
@@ -531,6 +575,7 @@
                        dmas = <&sdma 19>,
                               <&sdma 20>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp4: mcbsp@48096000 {
@@ -544,6 +589,7 @@
                        dmas = <&sdma 31>,
                               <&sdma 32>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                keypad: keypad@4a31c000 {
@@ -554,6 +600,13 @@
                        ti,hwmods = "kbd";
                };
+                dmm@4e000000 {
+                        compatible = "ti,omap4-dmm";
+                        reg = <0x4e000000 0x800>;
+                        interrupts = <0 113 0x4>;
+                        ti,hwmods = "dmm";
+                };
                emif1: emif@4c000000 {
                        compatible = "ti,emif-4d";
                        reg = <0x4c000000 0x100>;
@@ -697,16 +750,22 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
+                        clocks = <&init_60m_fclk>,
+                                 <&xclk60mhsp1_ck>,
+                                 <&xclk60mhsp2_ck>;
+                        clock-names = "refclk_60m_int",
+                                      "refclk_60m_ext_p1",
+                                      "refclk_60m_ext_p2";
                        usbhsohci: ohci@4a064800 {
-                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                compatible = "ti,ohci-omap3";
                                reg = <0x4a064800 0x400>;
                                interrupt-parent = <&gic>;
                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        usbhsehci: ehci@4a064c00 {
-                                compatible = "ti,ehci-omap", "usb-ehci";
+                                compatible = "ti,ehci-omap";
                                reg = <0x4a064c00 0x400>;
                                interrupt-parent = <&gic>;
                                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@@ -757,6 +816,111 @@
                        dmas = <&sdma 117>, <&sdma 116>;
                        dma-names = "tx", "rx";
                };
+                abb_mpu: regulator-abb-mpu {
+                        compatible = "ti,abb-v2";
+                        regulator-name = "abb_mpu";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        ti,tranxdone-status-mask = <0x80>;
+                        clocks = <&sys_clkin_ck>;
+                        ti,settling-time = <50>;
+                        ti,clock-cycles = <16>;
+                        status = "disabled";
+                };
+                abb_iva: regulator-abb-iva {
+                        compatible = "ti,abb-v2";
+                        regulator-name = "abb_iva";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        ti,tranxdone-status-mask = <0x80000000>;
+                        clocks = <&sys_clkin_ck>;
+                        ti,settling-time = <50>;
+                        ti,clock-cycles = <16>;
+                        status = "disabled";
+                };
+                dss: dss@58000000 {
+                        compatible = "ti,omap4-dss";
+                        reg = <0x58000000 0x80>;
+                        status = "disabled";
+                        ti,hwmods = "dss_core";
+                        clocks = <&dss_dss_clk>;
+                        clock-names = "fck";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        dispc@58001000 {
+                                compatible = "ti,omap4-dispc";
+                                reg = <0x58001000 0x1000>;
+                                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                                ti,hwmods = "dss_dispc";
+                                clocks = <&dss_dss_clk>;
+                                clock-names = "fck";
+                        };
+                        rfbi: encoder@58002000  {
+                                compatible = "ti,omap4-rfbi";
+                                reg = <0x58002000 0x1000>;
+                                status = "disabled";
+                                ti,hwmods = "dss_rfbi";
+                                clocks = <&dss_dss_clk>, <&dss_fck>;
+                                clock-names = "fck", "ick";
+                        };
+                        venc: encoder@58003000 {
+                                compatible = "ti,omap4-venc";
+                                reg = <0x58003000 0x1000>;
+                                status = "disabled";
+                                ti,hwmods = "dss_venc";
+                                clocks = <&dss_tv_clk>;
+                                clock-names = "fck";
+                        };
+                        dsi1: encoder@58004000 {
+                                compatible = "ti,omap4-dsi";
+                                reg = <0x58004000 0x200>,
+                                      <0x58004200 0x40>,
+                                      <0x58004300 0x20>;
+                                reg-names = "proto", "phy", "pll";
+                                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                                status = "disabled";
+                                ti,hwmods = "dss_dsi1";
+                                clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+                                clock-names = "fck", "sys_clk";
+                        };
+                        dsi2: encoder@58005000 {
+                                compatible = "ti,omap4-dsi";
+                                reg = <0x58005000 0x200>,
+                                      <0x58005200 0x40>,
+                                      <0x58005300 0x20>;
+                                reg-names = "proto", "phy", "pll";
+                                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                                status = "disabled";
+                                ti,hwmods = "dss_dsi2";
+                                clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+                                clock-names = "fck", "sys_clk";
+                        };
+                        hdmi: encoder@58006000 {
+                                compatible = "ti,omap4-hdmi";
+                                reg = <0x58006000 0x200>,
+                                      <0x58006200 0x100>,
+                                      <0x58006300 0x100>,
+                                      <0x58006400 0x1000>;
+                                reg-names = "wp", "pll", "phy", "core";
+                                interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                                status = "disabled";
+                                ti,hwmods = "dss_hdmi";
+                                clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
+                                clock-names = "fck", "sys_clk";
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index 8c1cfad30d60..0adfa1d1ef20 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -43,6 +43,32 @@
                        #thermal-sensor-cells = <0>;
                };
        };
+        ocp {
+                abb_mpu: regulator-abb-mpu {
+                        status = "okay";
+                        reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>;
+                        reg-names = "base-address", "int-address";
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m   fbb_m   vset_m*/
+                        1025000         0       0       0       0       0
+                        1200000         0       0       0       0       0
+                        1313000         0       0       0       0       0
+                        1375000         1       0       0       0       0
+                        1389000         1       0       0       0       0
+                        >;
+                };
+                /* Default unused, just provide register info for record */
+                abb_iva: regulator-abb-iva {
+                        reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>;
+                        reg-names = "base-address", "int-address";
+                };
+        };
 };
 /include/ "omap443x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 6b32f520741a..194f9ef0a009 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -50,7 +50,44 @@
                        #thermal-sensor-cells = <0>;
                };
+                abb_mpu: regulator-abb-mpu {
+                        status = "okay";
+                        reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
+                              <0x4A002268 0x4>;
+                        reg-names = "base-address", "int-address",
+                                    "efuse-address";
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m   fbb_m   vset_m*/
+                        1025000         0       0       0       0       0
+                        1200000         0       0       0       0       0
+                        1313000         0       0       0x100000 0x40000 0
+                        1375000         1       0       0       0       0
+                        1389000         1       0       0       0       0
+                        >;
+                };
+                abb_iva: regulator-abb-iva {
+                        status = "okay";
+                        reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
+                              <0x4A002268 0x4>;
+                        reg-names = "base-address", "int-address",
+                                    "efuse-address";
+                        ti,abb_info = <
+                        /*uV            ABB     efuse   rbb_m   fbb_m   vset_m*/
+                        950000          0       0       0       0       0
+                        1140000         0       0       0       0       0
+                        1291000         0       0       0x200000 0      0
+                        1375000         1       0       0       0       0
+                        1376000         1       0       0       0       0
+                        >;
+                };
        };
 };
 /include/ "omap446x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 002fa70180a5..3b99ec25b748 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -31,12 +31,8 @@
        hsusb2_phy: hsusb2_phy {
                compatible = "usb-nop-xceiv";
                reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
-        /**
+                clocks = <&auxclk1_ck>;
-          * FIXME
+                clock-names = "main_clk";
-          * Put the right clock phandle here when available
-          *     clocks = <&auxclk1>;
-          *     clock-names = "main_clk";
-          */
                clock-frequency = <19200000>;
        };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index a72813a9663e..6f3de22fb266 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -49,6 +49,12 @@
                                1000000 1060000
                                1500000 1250000
                        >;
+                        clocks = <&dpll_mpu_ck>;
+                        clock-names = "cpu";
+                        clock-latency = <300000>; /* From omap-cpufreq driver */
                        /* cooling options */
                        cooling-min-level = <0>;
                        cooling-max-level = <2>;
@@ -192,6 +198,22 @@
                        pinctrl-single,function-mask = <0x7fff>;
                };
+                omap5_padconf_global: tisyscon@4a002da0 {
+                        compatible = "syscon";
+                        reg = <0x4A002da0 0xec>;
+                };
+                pbias_regulator: pbias_regulator {
+                        compatible = "ti,pbias-omap";
+                        reg = <0x60 0x4>;
+                        syscon = <&omap5_padconf_global>;
+                        pbias_mmc_reg: pbias_mmc_omap5 {
+                                regulator-name = "pbias_mmc_omap5";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                };
                sdma: dma-controller@4a056000 {
                        compatible = "ti,omap4430-sdma";
                        reg = <0x4a056000 0x1000>;
@@ -302,6 +324,8 @@
                        gpmc,num-cs = <8>;
                        gpmc,num-waitpins = <4>;
                        ti,hwmods = "gpmc";
+                        clocks = <&l3_iclk_div>;
+                        clock-names = "fck";
                };
                i2c1: i2c@48070000 {
@@ -353,6 +377,7 @@
                        compatible = "ti,omap4-hwspinlock";
                        reg = <0x4a0f6000 0x1000>;
                        ti,hwmods = "spinlock";
+                        #hwlock-cells = <1>;
                };
                mcspi1: spi@48098000 {
@@ -471,6 +496,7 @@
                        ti,needs-special-reset;
                        dmas = <&sdma 61>, <&sdma 62>;
                        dma-names = "tx", "rx";
+                        pbias-supply = <&pbias_mmc_reg>;
                };
                mmc2: mmc@480b4000 {
@@ -513,6 +539,21 @@
                        dma-names = "tx", "rx";
                };
+                mmu_dsp: mmu@4a066000 {
+                        compatible = "ti,omap4-iommu";
+                        reg = <0x4a066000 0x100>;
+                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "mmu_dsp";
+                };
+                mmu_ipu: mmu@55082000 {
+                        compatible = "ti,omap4-iommu";
+                        reg = <0x55082000 0x100>;
+                        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "mmu_ipu";
+                        ti,iommu-bus-err-back;
+                };
                keypad: keypad@4ae1c000 {
                        compatible = "ti,omap4-keypad";
                        reg = <0x4ae1c000 0x400>;
@@ -529,6 +570,7 @@
                        dmas = <&sdma 65>,
                               <&sdma 66>;
                        dma-names = "up_link", "dn_link";
+                        status = "disabled";
                };
                dmic: dmic@4012e000 {
@@ -540,6 +582,7 @@
                        ti,hwmods = "dmic";
                        dmas = <&sdma 67>;
                        dma-names = "up_link";
+                        status = "disabled";
                };
                mcbsp1: mcbsp@40122000 {
@@ -554,6 +597,7 @@
                        dmas = <&sdma 33>,
                               <&sdma 34>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp2: mcbsp@40124000 {
@@ -568,6 +612,7 @@
                        dmas = <&sdma 17>,
                               <&sdma 18>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                mcbsp3: mcbsp@40126000 {
@@ -582,6 +627,7 @@
                        dmas = <&sdma 19>,
                               <&sdma 20>;
                        dma-names = "tx", "rx";
+                        status = "disabled";
                };
                timer1: timer@4ae18000 {
@@ -683,6 +729,13 @@
                        ti,hwmods = "wd_timer2";
                };
+                dmm@4e000000 {
+                        compatible = "ti,omap5-dmm";
+                        reg = <0x4e000000 0x800>;
+                        interrupts = <0 113 0x4>;
+                        ti,hwmods = "dmm";
+                };
                emif1: emif@4c000000 {
                        compatible      = "ti,emif-4d5";
                        ti,hwmods       = "emif1";
@@ -732,7 +785,8 @@
                                compatible = "snps,dwc3";
                                reg = <0x4a030000 0x10000>;
                                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-                                usb-phy = <&usb2_phy>, <&usb3_phy>;
+                                phys = <&usb2_phy>, <&usb3_phy>;
+                                phy-names = "usb2-phy", "usb3-phy";
                                dr_mode = "peripheral";
                                tx-fifo-resize;
                        };
@@ -749,6 +803,7 @@
                                compatible = "ti,omap-usb2";
                                reg = <0x4a084000 0x7c>;
                                ctrl-module = <&omap_control_usb2phy>;
+                                #phy-cells = <0>;
                        };
                        usb3_phy: usb3phy@4a084400 {
@@ -758,6 +813,7 @@
                                      <0x4a084c00 0x40>;
                                reg-names = "phy_rx", "phy_tx", "pll_ctrl";
                                ctrl-module = <&omap_control_usb3phy>;
+                                #phy-cells = <0>;
                        };
                };
@@ -775,16 +831,22 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
+                        clocks = <&l3init_60m_fclk>,
+                                 <&xclk60mhsp1_ck>,
+                                 <&xclk60mhsp2_ck>;
+                        clock-names = "refclk_60m_int",
+                                      "refclk_60m_ext_p1",
+                                      "refclk_60m_ext_p2";
                        usbhsohci: ohci@4a064800 {
-                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                compatible = "ti,ohci-omap3";
                                reg = <0x4a064800 0x400>;
                                interrupt-parent = <&gic>;
                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
                        };
                        usbhsehci: ehci@4a064c00 {
-                                compatible = "ti,ehci-omap", "usb-ehci";
+                                compatible = "ti,ehci-omap";
                                reg = <0x4a064c00 0x400>;
                                interrupt-parent = <&gic>;
                                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 0e219932d7cc..1e82571d6823 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -76,9 +76,10 @@
                                #clock-cells = <1>;
                        };
-                        reset-controller@88010000 {
+                        rstc: reset-controller@88010000 {
                                compatible = "sirf,prima2-rstc";
                                reg = <0x88010000 0x1000>;
+                                #reset-cells = <1>;
                        };
                        rsc-controller@88020000 {
@@ -223,8 +224,8 @@
                                interrupts = <17>;
                                fifosize = <128>;
                                clocks = <&clks 13>;
-                                sirf,uart-dma-rx-channel = <21>;
+                                dmas = <&dmac1 5>, <&dmac0 2>;
-                                sirf,uart-dma-tx-channel = <2>;
+                                dma-names = "rx", "tx";
                        };
                        uart1: uart@b0060000 {
@@ -243,8 +244,8 @@
                                interrupts = <19>;
                                fifosize = <128>;
                                clocks = <&clks 15>;
-                                sirf,uart-dma-rx-channel = <6>;
+                                dmas = <&dmac0 6>, <&dmac0 7>;
-                                sirf,uart-dma-tx-channel = <7>;
+                                dma-names = "rx", "tx";
                        };
                        usp0: usp@b0080000 {
@@ -254,8 +255,8 @@
                                interrupts = <20>;
                                fifosize = <128>;
                                clocks = <&clks 28>;
-                                sirf,usp-dma-rx-channel = <17>;
+                                dmas = <&dmac1 1>, <&dmac1 2>;
-                                sirf,usp-dma-tx-channel = <18>;
+                                dma-names = "rx", "tx";
                        };
                        usp1: usp@b0090000 {
@@ -265,8 +266,8 @@
                                interrupts = <21>;
                                fifosize = <128>;
                                clocks = <&clks 29>;
-                                sirf,usp-dma-rx-channel = <14>;
+                                dmas = <&dmac0 14>, <&dmac0 15>;
-                                sirf,usp-dma-tx-channel = <15>;
+                                dma-names = "rx", "tx";
                        };
                        usp2: usp@b00a0000 {
@@ -276,8 +277,8 @@
                                interrupts = <22>;
                                fifosize = <128>;
                                clocks = <&clks 30>;
-                                sirf,usp-dma-rx-channel = <10>;
+                                dmas = <&dmac0 10>, <&dmac0 11>;
-                                sirf,usp-dma-tx-channel = <11>;
+                                dma-names = "rx", "tx";
                        };
                        dmac0: dma-controller@b00b0000 {
@@ -286,6 +287,7 @@
                                reg = <0xb00b0000 0x10000>;
                                interrupts = <12>;
                                clocks = <&clks 24>;
+                                #dma-cells = <1>;
                        };
                        dmac1: dma-controller@b0160000 {
@@ -294,6 +296,7 @@
                                reg = <0xb0160000 0x10000>;
                                interrupts = <13>;
                                clocks = <&clks 25>;
+                                #dma-cells = <1>;
                        };
                        vip@b00C0000 {
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 68a72f5507b9..169bad90dac9 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -1,63 +1,6 @@
-/dts-v1/;
+#include "qcom-msm8660.dtsi"
-/include/ "skeleton.dtsi"
-#include <dt-bindings/clock/qcom,gcc-msm8660.h>
 / {
        model = "Qualcomm MSM8660 SURF";
        compatible = "qcom,msm8660-surf", "qcom,msm8660";
-        interrupt-parent = <&intc>;
-        intc: interrupt-controller@2080000 {
-                compatible = "qcom,msm-8660-qgic";
-                interrupt-controller;
-                #interrupt-cells = <3>;
-                reg = < 0x02080000 0x1000 >,
-                      < 0x02081000 0x1000 >;
-        };
-        timer@2000000 {
-                compatible = "qcom,scss-timer", "qcom,msm-timer";
-                interrupts = <1 0 0x301>,
-                             <1 1 0x301>,
-                             <1 2 0x301>;
-                reg = <0x02000000 0x100>;
-                clock-frequency = <27000000>,
-                                  <32768>;
-                cpu-offset = <0x40000>;
-        };
-        msmgpio: gpio@800000 {
-                compatible = "qcom,msm-gpio";
-                reg = <0x00800000 0x4000>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                ngpio = <173>;
-                interrupts = <0 16 0x4>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-        };
-        gcc: clock-controller@900000 {
-                compatible = "qcom,gcc-msm8660";
-                #clock-cells = <1>;
-                #reset-cells = <1>;
-                reg = <0x900000 0x4000>;
-        };
-        serial@19c40000 {
-                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-                reg = <0x19c40000 0x1000>,
-                      <0x19c00000 0x1000>;
-                interrupts = <0 195 0x0>;
-                clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
-                clock-names = "core", "iface";
-        };
-        qcom,ssbi@500000 {
-                compatible = "qcom,ssbi";
-                reg = <0x500000 0x1000>;
-                qcom,controller-type = "pmic-arbiter";
-        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
new file mode 100644
index 000000000000..c52a9e964a44
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -0,0 +1,87 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/qcom,gcc-msm8660.h>
+/ {
+        model = "Qualcomm MSM8660";
+        compatible = "qcom,msm8660";
+        interrupt-parent = <&intc>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "qcom,scorpion";
+                enable-method = "qcom,gcc-msm8660";
+                cpu@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+                L2: l2-cache {
+                        compatible = "cache";
+                        cache-level = <2>;
+                };
+        };
+        intc: interrupt-controller@2080000 {
+                compatible = "qcom,msm-8660-qgic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x02080000 0x1000 >,
+                      < 0x02081000 0x1000 >;
+        };
+        timer@2000000 {
+                compatible = "qcom,scss-timer", "qcom,msm-timer";
+                interrupts = <1 0 0x301>,
+                             <1 1 0x301>,
+                             <1 2 0x301>;
+                reg = <0x02000000 0x100>;
+                clock-frequency = <27000000>,
+                                  <32768>;
+                cpu-offset = <0x40000>;
+        };
+        msmgpio: gpio@800000 {
+                compatible = "qcom,msm-gpio";
+                reg = <0x00800000 0x4000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpio = <173>;
+                interrupts = <0 16 0x4>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gcc: clock-controller@900000 {
+                compatible = "qcom,gcc-msm8660";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+                reg = <0x900000 0x4000>;
+        };
+        serial@19c40000 {
+                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                reg = <0x19c40000 0x1000>,
+                      <0x19c00000 0x1000>;
+                interrupts = <0 195 0x0>;
+                clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
+                clock-names = "core", "iface";
+        };
+        qcom,ssbi@500000 {
+                compatible = "qcom,ssbi";
+                reg = <0x500000 0x1000>;
+                qcom,controller-type = "pmic-arbiter";
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 7c30de4fa302..a58fb88315f6 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -1,70 +1,6 @@
-/dts-v1/;
+#include "qcom-msm8960.dtsi"
-/include/ "skeleton.dtsi"
-#include <dt-bindings/clock/qcom,gcc-msm8960.h>
 / {
        model = "Qualcomm MSM8960 CDP";
        compatible = "qcom,msm8960-cdp", "qcom,msm8960";
-        interrupt-parent = <&intc>;
-        intc: interrupt-controller@2000000 {
-                compatible = "qcom,msm-qgic2";
-                interrupt-controller;
-                #interrupt-cells = <3>;
-                reg = < 0x02000000 0x1000 >,
-                      < 0x02002000 0x1000 >;
-        };
-        timer@200a000 {
-                compatible = "qcom,kpss-timer", "qcom,msm-timer";
-                interrupts = <1 1 0x301>,
-                             <1 2 0x301>,
-                             <1 3 0x301>;
-                reg = <0x0200a000 0x100>;
-                clock-frequency = <27000000>,
-                                  <32768>;
-                cpu-offset = <0x80000>;
-        };
-        msmgpio: gpio@800000 {
-                compatible = "qcom,msm-gpio";
-                gpio-controller;
-                #gpio-cells = <2>;
-                ngpio = <150>;
-                interrupts = <0 16 0x4>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-                reg = <0x800000 0x4000>;
-        };
-        gcc: clock-controller@900000 {
-                compatible = "qcom,gcc-msm8960";
-                #clock-cells = <1>;
-                #reset-cells = <1>;
-                reg = <0x900000 0x4000>;
-        };
-        clock-controller@4000000 {
-                compatible = "qcom,mmcc-msm8960";
-                reg = <0x4000000 0x1000>;
-                #clock-cells = <1>;
-                #reset-cells = <1>;
-        };
-        serial@16440000 {
-                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-                reg = <0x16440000 0x1000>,
-                      <0x16400000 0x1000>;
-                interrupts = <0 154 0x0>;
-                clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
-                clock-names = "core", "iface";
-        };
-        qcom,ssbi@500000 {
-                compatible = "qcom,ssbi";
-                reg = <0x500000 0x1000>;
-                qcom,controller-type = "pmic-arbiter";
-        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
new file mode 100644
index 000000000000..997b7b94e117
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -0,0 +1,135 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/qcom,gcc-msm8960.h>
+/ {
+        model = "Qualcomm MSM8960";
+        compatible = "qcom,msm8960";
+        interrupt-parent = <&intc>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupts = <1 14 0x304>;
+                compatible = "qcom,krait";
+                enable-method = "qcom,kpss-acc-v1";
+                cpu@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc0>;
+                        qcom,saw = <&saw0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc1>;
+                        qcom,saw = <&saw1>;
+                };
+                L2: l2-cache {
+                        compatible = "cache";
+                        cache-level = <2>;
+                        interrupts = <0 2 0x4>;
+                };
+        };
+        cpu-pmu {
+                compatible = "qcom,krait-pmu";
+                interrupts = <1 10 0x304>;
+                qcom,no-pc-write;
+        };
+        intc: interrupt-controller@2000000 {
+                compatible = "qcom,msm-qgic2";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x02000000 0x1000 >,
+                      < 0x02002000 0x1000 >;
+        };
+        timer@200a000 {
+                compatible = "qcom,kpss-timer", "qcom,msm-timer";
+                interrupts = <1 1 0x301>,
+                             <1 2 0x301>,
+                             <1 3 0x301>;
+                reg = <0x0200a000 0x100>;
+                clock-frequency = <27000000>,
+                                  <32768>;
+                cpu-offset = <0x80000>;
+        };
+        msmgpio: gpio@800000 {
+                compatible = "qcom,msm-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpio = <150>;
+                interrupts = <0 16 0x4>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                reg = <0x800000 0x4000>;
+        };
+        gcc: clock-controller@900000 {
+                compatible = "qcom,gcc-msm8960";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+                reg = <0x900000 0x4000>;
+        };
+        clock-controller@4000000 {
+                compatible = "qcom,mmcc-msm8960";
+                reg = <0x4000000 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+        acc0: clock-controller@2088000 {
+                compatible = "qcom,kpss-acc-v1";
+                reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+        };
+        acc1: clock-controller@2098000 {
+                compatible = "qcom,kpss-acc-v1";
+                reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+        };
+        saw0: regulator@2089000 {
+                compatible = "qcom,saw2";
+                reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+                regulator;
+        };
+        saw1: regulator@2099000 {
+                compatible = "qcom,saw2";
+                reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+                regulator;
+        };
+        serial@16440000 {
+                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                reg = <0x16440000 0x1000>,
+                      <0x16400000 0x1000>;
+                interrupts = <0 154 0x0>;
+                clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
+                clock-names = "core", "iface";
+        };
+        qcom,ssbi@500000 {
+                compatible = "qcom,ssbi";
+                reg = <0x500000 0x1000>;
+                qcom,controller-type = "pmic-arbiter";
+        };
+        rng@1a500000 {
+                compatible = "qcom,prng";
+                reg = <0x1a500000 0x200>;
+                clocks = <&gcc PRNG_CLK>;
+                clock-names = "core";
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 9e5dadb101eb..f68723918b3f 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -9,6 +9,54 @@
        compatible = "qcom,msm8974";
        interrupt-parent = <&intc>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupts = <1 9 0xf04>;
+                compatible = "qcom,krait";
+                enable-method = "qcom,kpss-acc-v2";
+                cpu@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc3>;
+                };
+                L2: l2-cache {
+                        compatible = "cache";
+                        cache-level = <2>;
+                        interrupts = <0 2 0x4>;
+                        qcom,saw = <&saw_l2>;
+                };
+        };
+        cpu-pmu {
+                compatible = "qcom,krait-pmu";
+                interrupts = <1 7 0xf04>;
+        };
        soc: soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -91,6 +139,32 @@
                        };
                };
+                saw_l2: regulator@f9012000 {
+                        compatible = "qcom,saw2";
+                        reg = <0xf9012000 0x1000>;
+                        regulator;
+                };
+                acc0: clock-controller@f9088000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
+                };
+                acc1: clock-controller@f9098000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
+                };
+                acc2: clock-controller@f90a8000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
+                };
+                acc3: clock-controller@f90b8000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
+                };
                restart@fc4ab000 {
                        compatible = "qcom,pshold";
                        reg = <0xfc4ab000 0x4>;
@@ -117,5 +191,12 @@
                        clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                };
+                rng@f9bff000 {
+                        compatible = "qcom,prng";
+                        reg = <0xf9bff000 0x200>;
+                        clocks = <&gcc GCC_PRNG_AHB_CLK>;
+                        clock-names = "core";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/r7s72100-genmai-reference.dts b/arch/arm/boot/dts/r7s72100-genmai-reference.dts
index da19c70ed82b..e664611a47c8 100644
--- a/arch/arm/boot/dts/r7s72100-genmai-reference.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai-reference.dts
@@ -9,7 +9,7 @@
 */
 /dts-v1/;
-/include/ "r7s72100.dtsi"
+#include "r7s72100.dtsi"
 / {
        model = "Genmai";
@@ -29,3 +29,14 @@
                #size-cells = <1>;
        };
 };
+&i2c2 {
+        status = "okay";
+        clock-frequency = <400000>;
+        eeprom@50 {
+                compatible = "renesas,24c128";
+                reg = <0x50>;
+                pagesize = <64>;
+        };
+};
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 46b82aa7dc4e..ee700717a34b 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -8,12 +8,26 @@
 * kind, whether express or implied.
 */
+#include <dt-bindings/interrupt-controller/irq.h>
 / {
        compatible = "renesas,r7s72100";
        interrupt-parent = <&gic>;
        #address-cells = <1>;
        #size-cells = <1>;
+        aliases {
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                i2c3 = &i2c3;
+                spi0 = &spi0;
+                spi1 = &spi1;
+                spi2 = &spi2;
+                spi3 = &spi3;
+                spi4 = &spi4;
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -33,4 +47,137 @@
                reg = <0xe8201000 0x1000>,
                        <0xe8202000 0x1000>;
        };
+        i2c0: i2c@fcfee000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+                reg = <0xfcfee000 0x44>;
+                interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 158 IRQ_TYPE_EDGE_RISING>,
+                             <0 159 IRQ_TYPE_EDGE_RISING>,
+                             <0 160 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 161 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 162 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 163 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 164 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <100000>;
+                status = "disabled";
+        };
+        i2c1: i2c@fcfee400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+                reg = <0xfcfee400 0x44>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 166 IRQ_TYPE_EDGE_RISING>,
+                             <0 167 IRQ_TYPE_EDGE_RISING>,
+                             <0 168 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 169 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 170 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 171 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 172 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <100000>;
+                status = "disabled";
+        };
+        i2c2: i2c@fcfee800 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+                reg = <0xfcfee800 0x44>;
+                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 174 IRQ_TYPE_EDGE_RISING>,
+                             <0 175 IRQ_TYPE_EDGE_RISING>,
+                             <0 176 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 177 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 178 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 179 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 180 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <100000>;
+                status = "disabled";
+        };
+        i2c3: i2c@fcfeec00 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+                reg = <0xfcfeec00 0x44>;
+                interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 182 IRQ_TYPE_EDGE_RISING>,
+                             <0 183 IRQ_TYPE_EDGE_RISING>,
+                             <0 184 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 185 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 186 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 187 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 188 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <100000>;
+                status = "disabled";
+        };
+        spi0: spi@e800c800 {
+                compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+                reg = <0xe800c800 0x24>;
+                interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 239 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 240 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error", "rx", "tx";
+                num-cs = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi1: spi@e800d000 {
+                compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+                reg = <0xe800d000 0x24>;
+                interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 242 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 243 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error", "rx", "tx";
+                num-cs = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi2: spi@e800d800 {
+                compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+                reg = <0xe800d800 0x24>;
+                interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 245 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 246 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error", "rx", "tx";
+                num-cs = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi3: spi@e800e000 {
+                compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+                reg = <0xe800e000 0x24>;
+                interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 248 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 249 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error", "rx", "tx";
+                num-cs = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        spi4: spi@e800e800 {
+                compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+                reg = <0xe800e800 0x24>;
+                interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 251 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 252 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error", "rx", "tx";
+                num-cs = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index bb62c7a906f4..06cda19dac6a 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -17,6 +17,7 @@
 /dts-v1/;
 #include "r8a7778.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        model = "bockw";
@@ -84,7 +85,7 @@
        sdhi0_pins: sd0 {
                renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
-                                  "sdhi0_cd", "sdhi0_wp";
+                                  "sdhi0_cd";
                renesas,function = "sdhi0";
        };
@@ -101,6 +102,7 @@
        vmmc-supply = <&fixedregulator3v3>;
        bus-width = <4>;
        status = "okay";
+        wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
 };
 &hspi0 {
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ddb3bd7a8838..85c5b3b99f5e 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -203,46 +203,6 @@
                status = "disabled";
        };
-        i2c0: i2c@ffc70000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7778";
-                reg = <0xffc70000 0x1000>;
-                interrupt-parent = <&gic>;
-                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
-                status = "disabled";
-        };
-        i2c1: i2c@ffc71000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7778";
-                reg = <0xffc71000 0x1000>;
-                interrupt-parent = <&gic>;
-                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
-                status = "disabled";
-        };
-        i2c2: i2c@ffc72000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7778";
-                reg = <0xffc72000 0x1000>;
-                interrupt-parent = <&gic>;
-                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
-                status = "disabled";
-        };
-        i2c3: i2c@ffc73000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7778";
-                reg = <0xffc73000 0x1000>;
-                interrupt-parent = <&gic>;
-                interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
-                status = "disabled";
-        };
        hspi0: spi@fffc7000 {
                compatible = "renesas,hspi";
                reg = <0xfffc7000 0x18>;
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 57569cba1528..6e99eb2df076 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -1,7 +1,8 @@
 /*
 * Device Tree Source for the Lager board
 *
- * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded, Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
@@ -56,6 +57,54 @@
                regulator-boot-on;
                regulator-always-on;
        };
+        vcc_sdhi0: regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "SDHI0 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+        vccq_sdhi0: regulator@2 {
+                compatible = "regulator-gpio";
+                regulator-name = "SDHI0 VccQ";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+                gpios-states = <1>;
+                states = <3300000 1
+                          1800000 0>;
+        };
+        vcc_sdhi2: regulator@3 {
+                compatible = "regulator-fixed";
+                regulator-name = "SDHI2 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+        vccq_sdhi2: regulator@4 {
+                compatible = "regulator-gpio";
+                regulator-name = "SDHI2 VccQ";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
+                gpios-states = <1>;
+                states = <3300000 1
+                          1800000 0>;
+        };
 };
 &extal_clk {
@@ -63,23 +112,68 @@
 };
 &pfc {
-        pinctrl-0 = <&scif0_pins &scif1_pins>;
+        pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>;
        pinctrl-names = "default";
+        du_pins: du {
+                renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
+                renesas,function = "du";
+        };
        scif0_pins: serial0 {
                renesas,groups = "scif0_data";
                renesas,function = "scif0";
        };
+        ether_pins: ether {
+                renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
+                renesas,function = "eth";
+        };
+        phy1_pins: phy1 {
+                renesas,groups = "intc_irq0";
+                renesas,function = "intc";
+        };
        scif1_pins: serial1 {
                renesas,groups = "scif1_data";
                renesas,function = "scif1";
        };
+        sdhi0_pins: sd0 {
+                renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
+                renesas,function = "sdhi0";
+        };
+        sdhi2_pins: sd2 {
+                renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
+                renesas,function = "sdhi2";
+        };
        mmc1_pins: mmc1 {
                renesas,groups = "mmc1_data8", "mmc1_ctrl";
                renesas,function = "mmc1";
        };
+        qspi_pins: spi {
+                renesas,groups = "qspi_ctrl", "qspi_data4";
+                renesas,function = "qspi";
+        };
+};
+&ether {
+        pinctrl-0 = <&ether_pins &phy1_pins>;
+        pinctrl-names = "default";
+        phy-handle = <&phy1>;
+        renesas,ether-link-active-low;
+        status = "ok";
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+        };
 };
 &mmcif1 {
@@ -91,3 +185,58 @@
        non-removable;
        status = "okay";
 };
+&sata1 {
+        status = "okay";
+};
+&spi {
+        pinctrl-0 = <&qspi_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        flash: flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl512s";
+                reg = <0>;
+                spi-max-frequency = <30000000>;
+                m25p,fast-read;
+                partition@0 {
+                        label = "loader";
+                        reg = <0x00000000 0x00040000>;
+                        read-only;
+                };
+                partition@40000 {
+                        label = "user";
+                        reg = <0x00040000 0x00400000>;
+                        read-only;
+                };
+                partition@440000 {
+                        label = "flash";
+                        reg = <0x00440000 0x03bc0000>;
+                };
+        };
+};
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&vcc_sdhi0>;
+        vqmmc-supply = <&vccq_sdhi0>;
+        cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+&sdhi2 {
+        pinctrl-0 = <&sdhi2_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&vcc_sdhi2>;
+        vqmmc-supply = <&vccq_sdhi2>;
+        cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 71b1251f79c7..618e5b537eaf 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1,7 +1,8 @@
 /*
 * Device Tree Source for the r8a7790 SoC
 *
- * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
@@ -18,6 +19,13 @@
        #address-cells = <2>;
        #size-cells = <2>;
+        aliases {
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                i2c3 = &i2c3;
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -94,7 +102,6 @@
        gpio0: gpio@e6050000 {
                compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                reg = <0 0xe6050000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -106,7 +113,6 @@
        gpio1: gpio@e6051000 {
                compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                reg = <0 0xe6051000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -118,7 +124,6 @@
        gpio2: gpio@e6052000 {
                compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                reg = <0 0xe6052000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -130,7 +135,6 @@
        gpio3: gpio@e6053000 {
                compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                reg = <0 0xe6053000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -142,7 +146,6 @@
        gpio4: gpio@e6054000 {
                compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                reg = <0 0xe6054000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -154,7 +157,6 @@
        gpio5: gpio@e6055000 {
                compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                reg = <0 0xe6055000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -166,8 +168,8 @@
        thermal@e61f0000 {
                compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
-                interrupt-parent = <&gic>;
                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
        };
        timer {
@@ -183,7 +185,6 @@
                #interrupt-cells = <2>;
                interrupt-controller;
                reg = <0 0xe61c0000 0 0x200>;
-                interrupt-parent = <&gic>;
                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
@@ -195,7 +196,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7790";
                reg = <0 0xe6508000 0 0x40>;
-                interrupt-parent = <&gic>;
                interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
                status = "disabled";
@@ -206,7 +206,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7790";
                reg = <0 0xe6518000 0 0x40>;
-                interrupt-parent = <&gic>;
                interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
                status = "disabled";
@@ -217,7 +216,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7790";
                reg = <0 0xe6530000 0 0x40>;
-                interrupt-parent = <&gic>;
                interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
                status = "disabled";
@@ -228,7 +226,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7790";
                reg = <0 0xe6540000 0 0x40>;
-                interrupt-parent = <&gic>;
                interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
                status = "disabled";
@@ -237,7 +234,6 @@
        mmcif0: mmcif@ee200000 {
                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                reg = <0 0xee200000 0 0x80>;
-                interrupt-parent = <&gic>;
                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
                reg-io-width = <4>;
@@ -247,7 +243,6 @@
        mmcif1: mmc@ee220000 {
                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                reg = <0 0xee220000 0 0x80>;
-                interrupt-parent = <&gic>;
                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
                reg-io-width = <4>;
@@ -262,7 +257,6 @@
        sdhi0: sd@ee100000 {
                compatible = "renesas,sdhi-r8a7790";
                reg = <0 0xee100000 0 0x200>;
-                interrupt-parent = <&gic>;
                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
                cap-sd-highspeed;
@@ -272,7 +266,6 @@
        sdhi1: sd@ee120000 {
                compatible = "renesas,sdhi-r8a7790";
                reg = <0 0xee120000 0 0x200>;
-                interrupt-parent = <&gic>;
                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
                cap-sd-highspeed;
@@ -282,7 +275,6 @@
        sdhi2: sd@ee140000 {
                compatible = "renesas,sdhi-r8a7790";
                reg = <0 0xee140000 0 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
                cap-sd-highspeed;
@@ -292,13 +284,129 @@
        sdhi3: sd@ee160000 {
                compatible = "renesas,sdhi-r8a7790";
                reg = <0 0xee160000 0 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
                cap-sd-highspeed;
                status = "disabled";
        };
+        scifa0: serial@e6c40000 {
+                compatible = "renesas,scifa-r8a7790", "renesas,scifa";
+                reg = <0 0xe6c40000 0 64>;
+                interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifa1: serial@e6c50000 {
+                compatible = "renesas,scifa-r8a7790", "renesas,scifa";
+                reg = <0 0xe6c50000 0 64>;
+                interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifa2: serial@e6c60000 {
+                compatible = "renesas,scifa-r8a7790", "renesas,scifa";
+                reg = <0 0xe6c60000 0 64>;
+                interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifb0: serial@e6c20000 {
+                compatible = "renesas,scifb-r8a7790", "renesas,scifb";
+                reg = <0 0xe6c20000 0 64>;
+                interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifb1: serial@e6c30000 {
+                compatible = "renesas,scifb-r8a7790", "renesas,scifb";
+                reg = <0 0xe6c30000 0 64>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifb2: serial@e6ce0000 {
+                compatible = "renesas,scifb-r8a7790", "renesas,scifb";
+                reg = <0 0xe6ce0000 0 64>;
+                interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif0: serial@e6e60000 {
+                compatible = "renesas,scif-r8a7790", "renesas,scif";
+                reg = <0 0xe6e60000 0 64>;
+                interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif1: serial@e6e68000 {
+                compatible = "renesas,scif-r8a7790", "renesas,scif";
+                reg = <0 0xe6e68000 0 64>;
+                interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        hscif0: serial@e62c0000 {
+                compatible = "renesas,hscif-r8a7790", "renesas,hscif";
+                reg = <0 0xe62c0000 0 96>;
+                interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        hscif1: serial@e62c8000 {
+                compatible = "renesas,hscif-r8a7790", "renesas,hscif";
+                reg = <0 0xe62c8000 0 96>;
+                interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        ether: ethernet@ee700000 {
+                compatible = "renesas,ether-r8a7790";
+                reg = <0 0xee700000 0 0x400>;
+                interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
+                phy-mode = "rmii";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        sata0: sata@ee300000 {
+                compatible = "renesas,sata-r8a7790";
+                reg = <0 0xee300000 0 0x2000>;
+                interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
+                status = "disabled";
+        };
+        sata1: sata@ee500000 {
+                compatible = "renesas,sata-r8a7790";
+                reg = <0 0xee500000 0 0x2000>;
+                interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
+                status = "disabled";
+        };
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -313,6 +421,29 @@
                        clock-output-names = "extal";
                };
+                /*
+                 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
+                 * default. Boards that provide audio clocks should override them.
+                 */
+                audio_clk_a: audio_clk_a {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "audio_clk_a";
+                };
+                audio_clk_b: audio_clk_b {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "audio_clk_b";
+                };
+                audio_clk_c: audio_clk_c {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <0>;
+                        clock-output-names = "audio_clk_c";
+                };
                /* Special CPG clocks */
                cpg_clocks: cpg_clocks@e6150000 {
                        compatible = "renesas,r8a7790-cpg-clocks",
@@ -607,10 +738,16 @@
                mstp8_clks: mstp8_clks@e6150990 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
-                        clocks = <&p_clk>;
+                        clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
+                                 <&zs_clk>, <&zs_clk>;
                        #clock-cells = <1>;
-                        renesas,clock-indices = <R8A7790_CLK_ETHER>;
+                        renesas,clock-indices = <
-                        clock-output-names = "ether";
+                                R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
+                                R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
+                                R8A7790_CLK_SATA0
+                        >;
+                        clock-output-names =
+                                "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
                };
                mstp9_clks: mstp9_clks@e6150994 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -627,4 +764,15 @@
                                "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
                };
        };
+        spi: spi@e6b10000 {
+                compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+                reg = <0 0xe6b10000 0 0x2c>;
+                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
+                num-cs = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
deleted file mode 100644
index 588ca17ea1f0..000000000000
--- a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Device Tree Source for the Koelsch board
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-/dts-v1/;
-#include "r8a7791.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-/ {
-        model = "Koelsch";
-        compatible = "renesas,koelsch-reference", "renesas,r8a7791";
-        chosen {
-                bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
-        };
-        memory@40000000 {
-                device_type = "memory";
-                reg = <0 0x40000000 0 0x80000000>;
-        };
-        lbsc {
-                #address-cells = <1>;
-                #size-cells = <1>;
-        };
-        gpio-keys {
-                compatible = "gpio-keys";
-                key-a {
-                        gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
-                        linux,code = <30>;
-                        label = "SW30";
-                        gpio-key,wakeup;
-                        debounce-interval = <20>;
-                };
-                key-b {
-                        gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
-                        linux,code = <48>;
-                        label = "SW31";
-                        gpio-key,wakeup;
-                        debounce-interval = <20>;
-                };
-                key-c {
-                        gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
-                        linux,code = <46>;
-                        label = "SW32";
-                        gpio-key,wakeup;
-                        debounce-interval = <20>;
-                };
-                key-d {
-                        gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
-                        linux,code = <32>;
-                        label = "SW33";
-                        gpio-key,wakeup;
-                        debounce-interval = <20>;
-                };
-                key-e {
-                        gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
-                        linux,code = <18>;
-                        label = "SW34";
-                        gpio-key,wakeup;
-                        debounce-interval = <20>;
-                };
-                key-f {
-                        gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
-                        linux,code = <33>;
-                        label = "SW35";
-                        gpio-key,wakeup;
-                        debounce-interval = <20>;
-                };
-                key-g {
-                        gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
-                        linux,code = <34>;
-                        label = "SW36";
-                        gpio-key,wakeup;
-                        debounce-interval = <20>;
-                };
-        };
-        leds {
-                compatible = "gpio-leds";
-                led6 {
-                        gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-                };
-                led7 {
-                        gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
-                };
-                led8 {
-                        gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
-                };
-        };
-};
-&pfc {
-        pinctrl-0 = <&scif0_pins &scif1_pins>;
-        pinctrl-names = "default";
-        scif0_pins: serial0 {
-                renesas,groups = "scif0_data_d";
-                renesas,function = "scif0";
-        };
-        scif1_pins: serial1 {
-                renesas,groups = "scif1_data_d";
-                renesas,function = "scif1";
-        };
-};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index fd556c3483e3..bdd73e6657b2 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -2,7 +2,8 @@
 * Device Tree Source for the Koelsch board
 *
 * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded, Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
@@ -23,7 +24,12 @@
        memory@40000000 {
                device_type = "memory";
-                reg = <0 0x40000000 0 0x80000000>;
+                reg = <0 0x40000000 0 0x40000000>;
+        };
+        memory@200000000 {
+                device_type = "memory";
+                reg = <2 0x00000000 0 0x40000000>;
        };
        lbsc {
@@ -31,6 +37,60 @@
                #size-cells = <1>;
        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                key-a {
+                        gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+                        linux,code = <30>;
+                        label = "SW30";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-b {
+                        gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+                        linux,code = <48>;
+                        label = "SW31";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-c {
+                        gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <46>;
+                        label = "SW32";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-d {
+                        gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <32>;
+                        label = "SW33";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-e {
+                        gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+                        linux,code = <18>;
+                        label = "SW34";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-f {
+                        gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+                        linux,code = <33>;
+                        label = "SW35";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-g {
+                        gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+                        linux,code = <34>;
+                        label = "SW36";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+        };
        leds {
                compatible = "gpio-leds";
                led6 {
@@ -43,16 +103,112 @@
                        gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
                };
        };
+        vcc_sdhi0: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "SDHI0 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+        vccq_sdhi0: regulator@1 {
+                compatible = "regulator-gpio";
+                regulator-name = "SDHI0 VccQ";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+                gpios-states = <1>;
+                states = <3300000 1
+                          1800000 0>;
+        };
+        vcc_sdhi1: regulator@2 {
+                compatible = "regulator-fixed";
+                regulator-name = "SDHI1 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+        vccq_sdhi1: regulator@3 {
+                compatible = "regulator-gpio";
+                regulator-name = "SDHI1 VccQ";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+                gpios-states = <1>;
+                states = <3300000 1
+                          1800000 0>;
+        };
+        vcc_sdhi2: regulator@4 {
+                compatible = "regulator-fixed";
+                regulator-name = "SDHI2 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+        vccq_sdhi2: regulator@5 {
+                compatible = "regulator-gpio";
+                regulator-name = "SDHI2 VccQ";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+                gpios-states = <1>;
+                states = <3300000 1
+                          1800000 0>;
+        };
 };
 &extal_clk {
        clock-frequency = <20000000>;
 };
+&i2c2 {
+        pinctrl-0 = <&i2c2_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        clock-frequency = <400000>;
+        eeprom@50 {
+                compatible = "renesas,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+};
 &pfc {
-        pinctrl-0 = <&scif0_pins &scif1_pins>;
+        pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>;
        pinctrl-names = "default";
+        i2c2_pins: i2c {
+                renesas,groups = "i2c2";
+                renesas,function = "i2c2";
+        };
+        du_pins: du {
+                renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0";
+                renesas,function = "du";
+        };
        scif0_pins: serial0 {
                renesas,groups = "scif0_data_d";
                renesas,function = "scif0";
@@ -62,4 +218,116 @@
                renesas,groups = "scif1_data_d";
                renesas,function = "scif1";
        };
+        ether_pins: ether {
+                renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
+                renesas,function = "eth";
+        };
+        phy1_pins: phy1 {
+                renesas,groups = "intc_irq0";
+                renesas,function = "intc";
+        };
+        sdhi0_pins: sd0 {
+                renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
+                renesas,function = "sdhi0";
+        };
+        sdhi1_pins: sd1 {
+                renesas,gpios = "sdhi1_data4", "sdhi1_ctrl";
+                renesas,function = "sdhi1";
+        };
+        sdhi2_pins: sd2 {
+                renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
+                renesas,function = "sdhi2";
+        };
+        qspi_pins: spi {
+                renesas,groups = "qspi_ctrl", "qspi_data4";
+                renesas,function = "qspi";
+        };
+};
+&ether {
+        pinctrl-0 = <&ether_pins &phy1_pins>;
+        pinctrl-names = "default";
+        phy-handle = <&phy1>;
+        renesas,ether-link-active-low;
+        status = "ok";
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+&sata0 {
+        status = "okay";
+};
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&vcc_sdhi0>;
+        vqmmc-supply = <&vccq_sdhi0>;
+        cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&sdhi1 {
+        pinctrl-0 = <&sdhi1_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&vcc_sdhi1>;
+        vqmmc-supply = <&vccq_sdhi1>;
+        cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&sdhi2 {
+        pinctrl-0 = <&sdhi2_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&vcc_sdhi2>;
+        vqmmc-supply = <&vccq_sdhi2>;
+        cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+&spi {
+        pinctrl-0 = <&qspi_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        flash: flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl512s";
+                reg = <0>;
+                spi-max-frequency = <30000000>;
+                m25p,fast-read;
+                partition@0 {
+                        label = "loader";
+                        reg = <0x00000000 0x00080000>;
+                        read-only;
+                };
+                partition@80000 {
+                        label = "bootenv";
+                        reg = <0x00080000 0x00080000>;
+                        read-only;
+                };
+                partition@100000 {
+                        label = "data";
+                        reg = <0x00100000 0x03f00000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 19c65509a22d..46181708e59c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -2,7 +2,8 @@
 * Device Tree Source for the r8a7791 SoC
 *
 * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
@@ -19,6 +20,15 @@
        #address-cells = <2>;
        #size-cells = <2>;
+        aliases {
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                i2c3 = &i2c3;
+                i2c4 = &i2c4;
+                i2c5 = &i2c5;
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -53,7 +63,6 @@
        gpio0: gpio@e6050000 {
                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
                reg = <0 0xe6050000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -65,7 +74,6 @@
        gpio1: gpio@e6051000 {
                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
                reg = <0 0xe6051000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -77,7 +85,6 @@
        gpio2: gpio@e6052000 {
                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
                reg = <0 0xe6052000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -89,7 +96,6 @@
        gpio3: gpio@e6053000 {
                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
                reg = <0 0xe6053000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -101,7 +107,6 @@
        gpio4: gpio@e6054000 {
                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
                reg = <0 0xe6054000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -113,7 +118,6 @@
        gpio5: gpio@e6055000 {
                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
                reg = <0 0xe6055000 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -125,7 +129,6 @@
        gpio6: gpio@e6055400 {
                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
                reg = <0 0xe6055400 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -137,7 +140,6 @@
        gpio7: gpio@e6055800 {
                compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
                reg = <0 0xe6055800 0 0x50>;
-                interrupt-parent = <&gic>;
                interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -149,8 +151,8 @@
        thermal@e61f0000 {
                compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
-                interrupt-parent = <&gic>;
                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
        };
        timer {
@@ -166,7 +168,6 @@
                #interrupt-cells = <2>;
                interrupt-controller;
                reg = <0 0xe61c0000 0 0x200>;
-                interrupt-parent = <&gic>;
                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
@@ -179,12 +180,288 @@
                             <0 17 IRQ_TYPE_LEVEL_HIGH>;
        };
+        i2c0: i2c@e6508000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7791";
+                reg = <0 0xe6508000 0 0x40>;
+                interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
+                status = "disabled";
+        };
+        i2c1: i2c@e6518000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7791";
+                reg = <0 0xe6518000 0 0x40>;
+                interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
+                status = "disabled";
+        };
+        i2c2: i2c@e6530000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7791";
+                reg = <0 0xe6530000 0 0x40>;
+                interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
+                status = "disabled";
+        };
+        i2c3: i2c@e6540000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7791";
+                reg = <0 0xe6540000 0 0x40>;
+                interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
+                status = "disabled";
+        };
+        i2c4: i2c@e6520000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7791";
+                reg = <0 0xe6520000 0 0x40>;
+                interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
+                status = "disabled";
+        };
+        i2c5: i2c@e6528000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,i2c-r8a7791";
+                reg = <0 0xe6528000 0 0x40>;
+                interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
+                status = "disabled";
+        };
        pfc: pfc@e6060000 {
                compatible = "renesas,pfc-r8a7791";
                reg = <0 0xe6060000 0 0x250>;
                #gpio-range-cells = <3>;
        };
+        sdhi0: sd@ee100000 {
+                compatible = "renesas,sdhi-r8a7791";
+                reg = <0 0xee100000 0 0x200>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
+                status = "disabled";
+        };
+        sdhi1: sd@ee140000 {
+                compatible = "renesas,sdhi-r8a7791";
+                reg = <0 0xee140000 0 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
+                status = "disabled";
+        };
+        sdhi2: sd@ee160000 {
+                compatible = "renesas,sdhi-r8a7791";
+                reg = <0 0xee160000 0 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
+                status = "disabled";
+        };
+        scifa0: serial@e6c40000 {
+                compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+                reg = <0 0xe6c40000 0 64>;
+                interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifa1: serial@e6c50000 {
+                compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+                reg = <0 0xe6c50000 0 64>;
+                interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifa2: serial@e6c60000 {
+                compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+                reg = <0 0xe6c60000 0 64>;
+                interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifa3: serial@e6c70000 {
+                compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+                reg = <0 0xe6c70000 0 64>;
+                interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifa4: serial@e6c78000 {
+                compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+                reg = <0 0xe6c78000 0 64>;
+                interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifa5: serial@e6c80000 {
+                compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+                reg = <0 0xe6c80000 0 64>;
+                interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifb0: serial@e6c20000 {
+                compatible = "renesas,scifb-r8a7791", "renesas,scifb";
+                reg = <0 0xe6c20000 0 64>;
+                interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifb1: serial@e6c30000 {
+                compatible = "renesas,scifb-r8a7791", "renesas,scifb";
+                reg = <0 0xe6c30000 0 64>;
+                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scifb2: serial@e6ce0000 {
+                compatible = "renesas,scifb-r8a7791", "renesas,scifb";
+                reg = <0 0xe6ce0000 0 64>;
+                interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif0: serial@e6e60000 {
+                compatible = "renesas,scif-r8a7791", "renesas,scif";
+                reg = <0 0xe6e60000 0 64>;
+                interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif1: serial@e6e68000 {
+                compatible = "renesas,scif-r8a7791", "renesas,scif";
+                reg = <0 0xe6e68000 0 64>;
+                interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif2: serial@e6e58000 {
+                compatible = "renesas,scif-r8a7791", "renesas,scif";
+                reg = <0 0xe6e58000 0 64>;
+                interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif3: serial@e6ea8000 {
+                compatible = "renesas,scif-r8a7791", "renesas,scif";
+                reg = <0 0xe6ea8000 0 64>;
+                interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif4: serial@e6ee0000 {
+                compatible = "renesas,scif-r8a7791", "renesas,scif";
+                reg = <0 0xe6ee0000 0 64>;
+                interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif5: serial@e6ee8000 {
+                compatible = "renesas,scif-r8a7791", "renesas,scif";
+                reg = <0 0xe6ee8000 0 64>;
+                interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        hscif0: serial@e62c0000 {
+                compatible = "renesas,hscif-r8a7791", "renesas,hscif";
+                reg = <0 0xe62c0000 0 96>;
+                interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        hscif1: serial@e62c8000 {
+                compatible = "renesas,hscif-r8a7791", "renesas,hscif";
+                reg = <0 0xe62c8000 0 96>;
+                interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        hscif2: serial@e62d0000 {
+                compatible = "renesas,hscif-r8a7791", "renesas,hscif";
+                reg = <0 0xe62d0000 0 96>;
+                interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        ether: ethernet@ee700000 {
+                compatible = "renesas,ether-r8a7791";
+                reg = <0 0xee700000 0 0x400>;
+                interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
+                phy-mode = "rmii";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        sata0: sata@ee300000 {
+                compatible = "renesas,sata-r8a7791";
+                reg = <0 0xee300000 0 0x2000>;
+                interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
+                status = "disabled";
+        };
+        sata1: sata@ee500000 {
+                compatible = "renesas,sata-r8a7791";
+                reg = <0 0xee500000 0 0x2000>;
+                interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
+                status = "disabled";
+        };
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -429,7 +706,7 @@
                                R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
                        >;
                        clock-output-names =
-                                "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
+                                "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
                                "scifb1", "msiof1", "scifb2";
                };
                mstp3_clks: mstp3_clks@e615013c {
@@ -474,10 +751,15 @@
                mstp8_clks: mstp8_clks@e6150990 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
-                        clocks = <&p_clk>;
+                        clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
+                                 <&zs_clk>;
                        #clock-cells = <1>;
-                        renesas,clock-indices = <R8A7791_CLK_ETHER>;
+                        renesas,clock-indices = <
-                        clock-output-names = "ether";
+                                R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
+                                R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
+                        >;
+                        clock-output-names =
+                                "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
                };
                mstp9_clks: mstp9_clks@e6150994 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -488,7 +770,7 @@
                        #clock-cells = <1>;
                        renesas,clock-indices = <
                                R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
-                                R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
+                                R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
                                R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
                        >;
                        clock-output-names =
@@ -506,4 +788,15 @@
                        clock-output-names = "scifa3", "scifa4", "scifa5";
                };
        };
+        spi: spi@e6b10000 {
+                compatible = "renesas,qspi-r8a7791", "renesas,qspi";
+                reg = <0 0xe6b10000 0 0x2c>;
+                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
+                num-cs = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index be5d2b09a363..4d4dfbb59f4b 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -64,6 +64,19 @@
                        clock-names = "timer", "pclk";
                };
+                sram: sram@10080000 {
+                        compatible = "mmio-sram";
+                        reg = <0x10080000 0x10000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x10080000 0x10000>;
+                        smp-sram@0 {
+                                compatible = "rockchip,rk3066-smp-sram";
+                                reg = <0x0 0x50>;
+                        };
+                };
                pinctrl@20008000 {
                        compatible = "rockchip,rk3066a-pinctrl";
                        reg = <0x20008000 0x150>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 1a26b03b3649..bb36596ea205 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -60,6 +60,19 @@
                        interrupts = <GIC_PPI 13 0xf04>;
                };
+                sram: sram@10080000 {
+                        compatible = "mmio-sram";
+                        reg = <0x10080000 0x8000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x10080000 0x8000>;
+                        smp-sram@0 {
+                                compatible = "rockchip,rk3066-smp-sram";
+                                reg = <0x0 0x50>;
+                        };
+                };
                pinctrl@20008000 {
                        compatible = "rockchip,rk3188-pinctrl";
                        reg = <0x20008000 0xa0>,
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 0fcbcfd67de2..26e5a968d49d 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -26,6 +26,16 @@
                compatible = "simple-bus";
                ranges;
+                scu@1013c000 {
+                        compatible = "arm,cortex-a9-scu";
+                        reg = <0x1013c000 0x100>;
+                };
+                pmu@20004000 {
+                        compatible = "rockchip,rk3066-pmu";
+                        reg = <0x20004000 0x100>;
+                };
                gic: interrupt-controller@1013d000 {
                        compatible = "arm,cortex-a9-gic";
                        interrupt-controller;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 3d5faf85f51b..eabcfdbb403a 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -239,7 +239,9 @@
                        };
                        adc0: adc@f8018000 {
-                                compatible = "atmel,at91sam9260-adc";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9x5-adc";
                                reg = <0xf8018000 0x100>;
                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
@@ -261,52 +263,39 @@
                                clocks = <&adc_clk>,
                                         <&adc_op_clk>;
                                clock-names = "adc_clk", "adc_op_clk";
-                                atmel,adc-channel-base = <0x50>;
                                atmel,adc-channels-used = <0xfff>;
-                                atmel,adc-drdy-mask = <0x1000000>;
-                                atmel,adc-num-channels = <12>;
                                atmel,adc-startup-time = <40>;
-                                atmel,adc-status-register = <0x30>;
+                                atmel,adc-use-external-triggers;
-                                atmel,adc-trigger-register = <0xc0>;
-                                atmel,adc-use-external;
                                atmel,adc-vref = <3000>;
                                atmel,adc-res = <10 12>;
                                atmel,adc-res-names = "lowres", "highres";
                                status = "disabled";
                                trigger@0 {
+                                        reg = <0>;
                                        trigger-name = "external-rising";
                                        trigger-value = <0x1>;
                                        trigger-external;
                                };
                                trigger@1 {
+                                        reg = <1>;
                                        trigger-name = "external-falling";
                                        trigger-value = <0x2>;
                                        trigger-external;
                                };
                                trigger@2 {
+                                        reg = <2>;
                                        trigger-name = "external-any";
                                        trigger-value = <0x3>;
                                        trigger-external;
                                };
                                trigger@3 {
+                                        reg = <3>;
                                        trigger-name = "continuous";
                                        trigger-value = <0x6>;
                                };
                        };
-                        tsadcc: tsadcc@f8018000 {
-                                compatible = "atmel,at91sam9x5-tsadcc";
-                                reg = <0xf8018000 0x4000>;
-                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
-                                atmel,tsadcc_clock = <300000>;
-                                atmel,filtering_average = <0x03>;
-                                atmel,pendet_debounce = <0x08>;
-                                atmel,pendet_sensitivity = <0x02>;
-                                atmel,ts_sample_hold_time = <0x0a>;
-                                status = "disabled";
-                        };
                        i2c2: i2c@f801c000 {
                                compatible = "atmel,at91sam9x5-i2c";
                                reg = <0xf801c000 0x4000>;
@@ -1256,6 +1245,7 @@
                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
                        atmel,nand-addr-offset = <21>;
                        atmel,nand-cmd-offset = <22>;
+                        atmel,nand-has-dma;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand0_ale_cle>;
                        atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
index f9bdde542ced..035ab72b3990 100644
--- a/arch/arm/boot/dts/sama5d3xdm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -23,10 +23,8 @@
                        };
                        adc0: adc@f8018000 {
-                                status = "disabled";
+                                atmel,adc-ts-wires = <4>;
-                        };
+                                atmel,adc-ts-pressure-threshold = <10000>;
-                        tsadcc: tsadcc@f8018000 {
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 537f1a5c07f5..56fc214e6d2c 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -92,7 +92,12 @@
                                        #address-cells = <1>;
                                        #size-cells = <0>;
-                                        osc: osc1 {
+                                        osc1: osc1 {
+                                                #clock-cells = <0>;
+                                                compatible = "fixed-clock";
+                                        };
+                                        osc2: osc2 {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
                                        };
@@ -100,7 +105,11 @@
                                        f2s_periph_ref_clk: f2s_periph_ref_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
-                                                clock-frequency = <10000000>;
+                                        };
+                                        f2s_sdram_ref_clk: f2s_sdram_ref_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "fixed-clock";
                                        };
                                        main_pll: main_pll {
@@ -108,7 +117,7 @@
                                                #size-cells = <0>;
                                                #clock-cells = <0>;
                                                compatible = "altr,socfpga-pll-clock";
-                                                clocks = <&osc>;
+                                                clocks = <&osc1>;
                                                reg = <0x40>;
                                                mpuclk: mpuclk {
@@ -162,7 +171,7 @@
                                                #size-cells = <0>;
                                                #clock-cells = <0>;
                                                compatible = "altr,socfpga-pll-clock";
-                                                clocks = <&osc>;
+                                                clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
                                                reg = <0x80>;
                                                emac0_clk: emac0_clk {
@@ -213,7 +222,7 @@
                                                #size-cells = <0>;
                                                #clock-cells = <0>;
                                                compatible = "altr,socfpga-pll-clock";
-                                                clocks = <&osc>;
+                                                clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
                                                reg = <0xC0>;
                                                ddr_dqs_clk: ddr_dqs_clk {
@@ -415,6 +424,7 @@
                                                compatible = "altr,socfpga-gate-clk";
                                                clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
                                                clk-gate = <0xa0 8>;
+                                                clk-phase = <0 135>;
                                        };
                                        nand_x_clk: nand_x_clk {
@@ -443,6 +453,7 @@
                gmac0: ethernet@ff700000 {
                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                        altr,sysmgr-syscon = <&sysmgr 0x60 0>;
                        reg = <0xff700000 0x2000>;
                        interrupts = <0 115 4>;
                        interrupt-names = "macirq";
@@ -454,6 +465,7 @@
                gmac1: ethernet@ff702000 {
                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                        altr,sysmgr-syscon = <&sysmgr 0x60 2>;
                        reg = <0xff702000 0x2000>;
                        interrupts = <0 120 4>;
                        interrupt-names = "macirq";
@@ -473,6 +485,17 @@
                        arm,data-latency = <2 1 1>;
                };
+                mmc: dwmmc0@ff704000 {
+                        compatible = "altr,socfpga-dw-mshc";
+                        reg = <0xff704000 0x1000>;
+                        interrupts = <0 139 4>;
+                        fifo-depth = <0x400>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+                        clock-names = "biu", "ciu";
+                };
                /* Local timer */
                timer@fffec600 {
                        compatible = "arm,cortex-a9-twd-timer";
@@ -526,9 +549,9 @@
                        reg = <0xffd05000 0x1000>;
                };
-                sysmgr@ffd08000 {
+                sysmgr: sysmgr@ffd08000 {
-                                compatible = "altr,sys-mgr";
+                        compatible = "altr,sys-mgr", "syscon";
-                                reg = <0xffd08000 0x4000>;
+                        reg = <0xffd08000 0x4000>;
-                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index a85b4043f888..6c87b7070ca7 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -27,6 +27,17 @@
                        };
                };
+                dwmmc0@ff704000 {
+                        num-slots = <1>;
+                        supports-highspeed;
+                        broken-cd;
+                        slot@0 {
+                                reg = <0>;
+                                bus-width = <4>;
+                        };
+                };
                serial0@ffc02000 {
                        clock-frequency = <100000000>;
                };
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 5beffb2265f4..a87ee1c07661 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,4 +37,25 @@
                */
                ethernet0 = &gmac1;
        };
+        aliases {
+                /* this allow the ethaddr uboot environmnet variable contents
+                 * to be added to the gmac1 device tree blob.
+                 */
+                ethernet0 = &gmac1;
+        };
+};
+&gmac1 {
+        status = "okay";
+        phy-mode = "rgmii";
+        rxd0-skew-ps = <0>;
+        rxd1-skew-ps = <0>;
+        rxd2-skew-ps = <0>;
+        rxd3-skew-ps = <0>;
+        txen-skew-ps = <0>;
+        txc-skew-ps = <2600>;
+        rxdv-skew-ps = <0>;
+        rxc-skew-ps = <2000>;
 };
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index a8716f6dbe2e..ca41b0ebf461 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -28,6 +28,17 @@
                        };
                };
+                dwmmc0@ff704000 {
+                        num-slots = <1>;
+                        supports-highspeed;
+                        broken-cd;
+                        slot@0 {
+                                reg = <0>;
+                                bus-width = <4>;
+                        };
+                };
                ethernet@ff702000 {
                        phy-mode = "rgmii";
                        phy-addr = <0xffffffff>; /* probe for phy addr */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 2ee52ab8cabb..ae16d975196d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -38,3 +38,17 @@
                ethernet0 = &gmac1;
        };
 };
+&gmac1 {
+        status = "okay";
+        phy-mode = "rgmii";
+        rxd0-skew-ps = <0>;
+        rxd1-skew-ps = <0>;
+        rxd2-skew-ps = <0>;
+        rxd3-skew-ps = <0>;
+        txen-skew-ps = <0>;
+        txc-skew-ps = <2600>;
+        rxdv-skew-ps = <0>;
+        rxc-skew-ps = <2000>;
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index 50b99a2c12ae..b79e2a2bf175 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -30,8 +30,25 @@
                device_type = "memory";
                reg = <0x0 0x40000000>; /* 1GB */
        };
+        aliases {
+                /* this allow the ethaddr uboot environmnet variable contents
+                 * to be added to the gmac1 device tree blob.
+                 */
+                ethernet0 = &gmac1;
+        };
 };
 &gmac1 {
        status = "okay";
+        phy-mode = "rgmii";
+        rxd0-skew-ps = <0>;
+        rxd1-skew-ps = <0>;
+        rxd2-skew-ps = <0>;
+        rxd3-skew-ps = <0>;
+        txen-skew-ps = <0>;
+        txc-skew-ps = <2600>;
+        rxdv-skew-ps = <0>;
+        rxc-skew-ps = <2000>;
 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index d1ec0cab2dee..87d6f759a9c1 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,17 @@
                        };
                };
+                dwmmc0@ff704000 {
+                        num-slots = <1>;
+                        supports-highspeed;
+                        broken-cd;
+                        slot@0 {
+                                reg = <0>;
+                                bus-width = <4>;
+                        };
+                };
                ethernet@ff700000 {
                        phy-mode = "gmii";
                        status = "okay";
@@ -75,3 +86,8 @@
                };
        };
 };
+&gmac0 {
+        status = "okay";
+        phy-mode = "gmii";
+};
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index e0853ea02df2..e41eedca3ce3 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -705,7 +705,7 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                        clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
-                        clock-names = "ssp0clk", "apb_pclk";
+                        clock-names = "SSPCLK", "apb_pclk";
                        dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
                               <&dma 8 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
@@ -718,7 +718,7 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                        clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
-                        clock-names = "ssp1clk", "apb_pclk";
+                        clock-names = "SSPCLK", "apb_pclk";
                        dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
                               <&dma 9 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
@@ -732,7 +732,7 @@
                        #size-cells = <0>;
                        /* Same clock wired to kernel and pclk */
                        clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
-                        clock-names = "spi0clk", "apb_pclk";
+                        clock-names = "SSPCLK", "apb_pclk";
                        dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
                               <&dma 0 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
@@ -746,7 +746,7 @@
                        #size-cells = <0>;
                        /* Same clock wired to kernel and pclk */
                        clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
-                        clock-names = "spi1clk", "apb_pclk";
+                        clock-names = "SSPCLK", "apb_pclk";
                        dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
                               <&dma 35 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
@@ -760,7 +760,7 @@
                        #size-cells = <0>;
                        /* Same clock wired to kernel and pclk */
                        clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
-                        clock-names = "spi2clk", "apb_pclk";
+                        clock-names = "SSPCLK", "apb_pclk";
                        dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
                               <&dma 33 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
@@ -774,7 +774,7 @@
                        #size-cells = <0>;
                        /* Same clock wired to kernel and pclk */
                        clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
-                        clock-names = "spi3clk", "apb_pclk";
+                        clock-names = "SSPCLK", "apb_pclk";
                        dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
                               <&dma 40 0 0x0>; /* Logical - MemToDev */
                        dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
new file mode 100644
index 000000000000..30f8601da323
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -0,0 +1,428 @@
+/*
+ * Copyright 2014 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/ {
+        soc {
+                prcmu@80157000 {
+                        ab8500 {
+                                ab8500-gpio {
+                                        /* Hog a few default settings */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&gpio2_default_mode>,
+                                                    <&gpio4_default_mode>,
+                                                    <&gpio10_default_mode>,
+                                                    <&gpio11_default_mode>,
+                                                    <&gpio12_default_mode>,
+                                                    <&gpio13_default_mode>,
+                                                    <&gpio16_default_mode>,
+                                                    <&gpio24_default_mode>,
+                                                    <&gpio25_default_mode>,
+                                                    <&gpio36_default_mode>,
+                                                    <&gpio37_default_mode>,
+                                                    <&gpio38_default_mode>,
+                                                    <&gpio39_default_mode>,
+                                                    <&gpio42_default_mode>,
+                                                    <&gpio26_default_mode>,
+                                                    <&gpio35_default_mode>,
+                                                    <&ycbcr_default_mode>,
+                                                    <&pwm_default_mode>,
+                                                    <&adi1_default_mode>,
+                                                    <&usbuicc_default_mode>,
+                                                    <&dmic_default_mode>,
+                                                    <&extcpena_default_mode>,
+                                                    <&modsclsda_default_mode>;
+                                        /*
+                                         * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
+                                         * are muxed in as GPIO, and configured as INPUT PULL DOWN
+                                         */
+                                        gpio2 {
+                                                gpio2_default_mode: gpio2_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio2_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO2_T9";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio4 {
+                                                gpio4_default_mode: gpio4_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio4_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO4_W2";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio10 {
+                                                gpio10_default_mode: gpio10_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio10_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO10_U17";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio11 {
+                                                gpio11_default_mode: gpio11_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio11_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO11_AA18";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio12 {
+                                                gpio12_default_mode: gpio12_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio12_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO12_U16";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio13 {
+                                                gpio13_default_mode: gpio13_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio13_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO13_W17";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio16 {
+                                                gpio16_default_mode: gpio16_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio16_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO16_F15";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio24 {
+                                                gpio24_default_mode: gpio24_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio24_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO24_T14";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio25 {
+                                                gpio25_default_mode: gpio25_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio25_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO25_R16";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio36 {
+                                                gpio36_default_mode: gpio36_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio36_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO36_A17";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio37 {
+                                                gpio37_default_mode: gpio37_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio37_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO37_E15";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio38 {
+                                                gpio38_default_mode: gpio38_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio38_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO38_C17";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio39 {
+                                                gpio39_default_mode: gpio39_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio39_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO39_E16";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio42 {
+                                                gpio42_default_mode: gpio42_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio42_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO42_U2";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        /*
+                                         * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW
+                                         */
+                                        gpio26 {
+                                                gpio26_default_mode: gpio26_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio26_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO26_M16";
+                                                                output-low;
+                                                        };
+                                                };
+                                        };
+                                        gpio35 {
+                                                gpio35_default_mode: gpio35_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio35_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO35_W15";
+                                                                output-low;
+                                                        };
+                                                };
+                                        };
+                                        /*
+                                         * This sets up the YCBCR connector pins, i.e. analog video out.
+                                         * Set as input with no bias.
+                                         */
+                                        ycbcr {
+                                                ycbcr_default_mode: ycbcr_default {
+                                                        default_mux {
+                                                                ste,function = "ycbcr";
+                                                                ste,pins = "ycbcr0123_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO6_Y18",
+                                                                         "GPIO7_AA20",
+                                                                         "GPIO8_W18",
+                                                                         "GPIO9_AA19";
+                                                                input-enable;
+                                                                bias-disable;
+                                                        };
+                                                };
+                                        };
+                                        /* This sets up the PWM pins 14 and 15 */
+                                        pwm {
+                                                pwm_default_mode: pwm_default {
+                                                        default_mux {
+                                                                ste,function = "pwmout";
+                                                                ste,pins = "pwmout1_d_1", "pwmout2_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO14_F14",
+                                                                         "GPIO15_B17";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        /* This sets up audio interface 1 */
+                                        adi1 {
+                                                adi1_default_mode: adi1_default {
+                                                        default_mux {
+                                                                ste,function = "adi1";
+                                                                ste,pins = "adi1_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO17_P5",
+                                                                         "GPIO18_R5",
+                                                                         "GPIO19_U5",
+                                                                         "GPIO20_T5";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        /* This sets up the USB UICC pins */
+                                        usbuicc {
+                                                usbuicc_default_mode: usbuicc_default {
+                                                        default_mux {
+                                                                ste,function = "usbuicc";
+                                                                ste,pins = "usbuicc_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO21_H19",
+                                                                         "GPIO22_G20",
+                                                                         "GPIO23_G19";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        /* This sets up the microphone pins */
+                                        dmic {
+                                                dmic_default_mode: dmic_default {
+                                                        default_mux {
+                                                                ste,function = "dmic";
+                                                                ste,pins = "dmic12_d_1",
+                                                                         "dmic34_d_1",
+                                                                         "dmic56_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO27_J6",
+                                                                         "GPIO28_K6",
+                                                                         "GPIO29_G6",
+                                                                         "GPIO30_H6",
+                                                                         "GPIO31_F5",
+                                                                         "GPIO32_G5";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        extcpena {
+                                                extcpena_default_mode: extcpena_default {
+                                                        default_mux {
+                                                                ste,function = "extcpena";
+                                                                ste,pins = "extcpena_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO34_R17";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        /* Modem I2C setup (SCL and SDA pins) */
+                                        modsclsda {
+                                                modsclsda_default_mode: modsclsda_default {
+                                                        default_mux {
+                                                                ste,function = "modsclsda";
+                                                                ste,pins = "modsclsda_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO40_T19",
+                                                                        "GPIO41_U19";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        /*
+                                         * Clock output pins associated with regulators.
+                                         */
+                                        sysclkreq2 {
+                                                sysclkreq2_default_mode: sysclkreq2_default {
+                                                        default_mux {
+                                                                ste,function = "sysclkreq";
+                                                                ste,pins = "sysclkreq2_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO1_T10";
+                                                                input-enable;
+                                                                bias-disable;
+                                                        };
+                                                };
+                                                sysclkreq2_sleep_mode: sysclkreq2_sleep {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio1_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO1_T10";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        sysclkreq4 {
+                                                sysclkreq4_default_mode: sysclkreq4_default {
+                                                        default_mux {
+                                                                ste,function = "sysclkreq";
+                                                                ste,pins = "sysclkreq4_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO3_U9";
+                                                                input-enable;
+                                                                bias-disable;
+                                                        };
+                                                };
+                                                sysclkreq4_sleep_mode: sysclkreq4_sleep {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio3_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO3_U9";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ste-href-ab8505.dtsi b/arch/arm/boot/dts/ste-href-ab8505.dtsi
new file mode 100644
index 000000000000..6006d62086a2
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-ab8505.dtsi
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2014 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/ {
+        soc {
+                prcmu@80157000 {
+                        ab8505 {
+                                ab8505-gpio {
+                                        /* Hog a few default settings */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&gpio2_default_mode>,
+                                                    <&gpio10_default_mode>,
+                                                    <&gpio11_default_mode>,
+                                                    <&gpio13_default_mode>,
+                                                    <&gpio34_default_mode>,
+                                                    <&gpio50_default_mode>,
+                                                    <&pwm_default_mode>,
+                                                    <&adi2_default_mode>,
+                                                    <&modsclsda_default_mode>,
+                                                    <&resethw_default_mode>,
+                                                    <&service_default_mode>;
+                                        /*
+                                         * Pins 2, 10, 11, 13, 34 and 50
+                                         * are muxed in as GPIO, and configured as INPUT PULL DOWN
+                                         */
+                                        gpio2 {
+                                                gpio2_default_mode: gpio2_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio2_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO2_R5";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio10 {
+                                                gpio10_default_mode: gpio10_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio10_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO10_B16";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio11 {
+                                                gpio11_default_mode: gpio11_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio11_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO11_B17";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio13 {
+                                                gpio13_default_mode: gpio13_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio13_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO13_D17";
+                                                                input-enable;
+                                                                bias-disable;
+                                                        };
+                                                };
+                                        };
+                                        gpio34 {
+                                                gpio34_default_mode: gpio34_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio34_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO34_H14";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        gpio50 {
+                                                gpio50_default_mode: gpio50_default {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio50_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO50_L4";
+                                                                input-enable;
+                                                                bias-disable;
+                                                        };
+                                                };
+                                        };
+                                        /* This sets up the PWM pin 14 */
+                                        pwm {
+                                                pwm_default_mode: pwm_default {
+                                                        default_mux {
+                                                                ste,function = "pwmout";
+                                                                ste,pins = "pwmout1_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO14_C16";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        /* This sets up audio interface 2 */
+                                        adi2 {
+                                                adi2_default_mode: adi2_default {
+                                                        default_mux {
+                                                                ste,function = "adi2";
+                                                                ste,pins = "adi2_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO17_P2",
+                                                                         "GPIO18_N3",
+                                                                         "GPIO19_T1",
+                                                                         "GPIO20_P3";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        /* Modem I2C setup (SCL and SDA pins) */
+                                        modsclsda {
+                                                modsclsda_default_mode: modsclsda_default {
+                                                        default_mux {
+                                                                ste,function = "modsclsda";
+                                                                ste,pins = "modsclsda_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO40_J15",
+                                                                        "GPIO41_J14";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        resethw {
+                                                resethw_default_mode: resethw_default {
+                                                        default_mux {
+                                                                ste,function = "resethw";
+                                                                ste,pins = "resethw_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO52_D16";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        service {
+                                                service_default_mode: service_default {
+                                                        default_mux {
+                                                                ste,function = "service";
+                                                                ste,pins = "service_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO53_D15";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        /*
+                                         * Clock output pins associated with regulators.
+                                         */
+                                        sysclkreq2 {
+                                                sysclkreq2_default_mode: sysclkreq2_default {
+                                                        default_mux {
+                                                                ste,function = "sysclkreq";
+                                                                ste,pins = "sysclkreq2_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO1_N4";
+                                                                input-enable;
+                                                                bias-disable;
+                                                        };
+                                                };
+                                                sysclkreq2_sleep_mode: sysclkreq2_sleep {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio1_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO1_N4";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                        sysclkreq4 {
+                                                sysclkreq4_default_mode: sysclkreq4_default {
+                                                        default_mux {
+                                                                ste,function = "sysclkreq";
+                                                                ste,pins = "sysclkreq4_d_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO3_P5";
+                                                                input-enable;
+                                                                bias-disable;
+                                                        };
+                                                };
+                                                sysclkreq4_sleep_mode: sysclkreq4_sleep {
+                                                        default_mux {
+                                                                ste,function = "gpio";
+                                                                ste,pins = "gpio3_a_1";
+                                                        };
+                                                        default_cfg {
+                                                                ste,pins = "GPIO3_P5";
+                                                                input-enable;
+                                                                bias-pull-down;
+                                                        };
+                                                };
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index 40f0ecdf9303..abc762e24fcb 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -12,6 +12,7 @@
 */
 #include "ste-dbx5x0.dtsi"
+#include "ste-href-ab8500.dtsi"
 #include "ste-href.dtsi"
 / {
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 3b6d1181939b..c2341061b943 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -10,6 +10,7 @@
 */
 #include "ste-dbx5x0.dtsi"
+#include "ste-href-ab8500.dtsi"
 #include "ste-href.dtsi"
 / {
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 97d5d21b7db7..a2f632d0be2a 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -11,6 +11,7 @@
 /dts-v1/;
 #include "ste-dbx5x0.dtsi"
+#include "ste-href-ab8500.dtsi"
 #include "ste-href-family-pinctrl.dtsi"
 / {
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index a9da4800daf0..6fe688e9e4da 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -457,7 +457,7 @@
                        interrupt-parent = <&vica>;
                        interrupts = <23>;
                        clocks = <&spi_clk>, <&spi_clk>;
-                        clock-names = "apb_pclk", "spi_clk";
+                        clock-names = "SSPCLK", "apb_pclk";
                        dmas = <&dmac 27 &dmac 28>;
                        dma-names = "tx", "rx";
                        num-cs = <3>;
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 174c799df741..d047dbc28d61 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -34,5 +34,19 @@
                        compatible = "fixed-clock";
                        clock-frequency = <100000000>;
                };
+                CLKS_GMAC0_PHY: clockgenA1@7 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <25000000>;
+                        clock-output-names = "CLKS_GMAC0_PHY";
+                };
+                CLKS_ETH1_PHY: clockgenA0@7 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <25000000>;
+                        clock-output-names = "CLKS_ETH1_PHY";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index e56449d41481..f09fb10a3791 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -7,6 +7,7 @@
 * publishhed by the Free Software Foundation.
 */
 #include "st-pincfg.h"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
        aliases {
@@ -45,35 +46,49 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih415-sbc-pinctrl";
                        st,syscfg       = <&syscfg_sbc>;
+                        reg             = <0xfe61f080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges          = <0 0xfe610000 0x5000>;
                        PIO0: gpio@fe610000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO0";
                        };
                        PIO1: gpio@fe611000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO1";
                        };
                        PIO2: gpio@fe612000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO2";
                        };
                        PIO3: gpio@fe613000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO3";
                        };
                        PIO4: gpio@fe614000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO4";
                        };
@@ -104,6 +119,64 @@
                                        };
                                };
                        };
+                        rc{
+                                pinctrl_ir: ir0 {
+                                        st,pins {
+                                                ir = <&PIO4 0 ALT2 IN>;
+                                        };
+                                };
+                        };
+                        gmac1 {
+                                pinctrl_mii1: mii1 {
+                                                st,pins {
+                                                 txd0   = <&PIO0 0 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd1   = <&PIO0 1 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd2   = <&PIO0 2 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txd3   = <&PIO0 3 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txer   = <&PIO0 4 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txen   = <&PIO0 5 ALT1 OUT  SE_NICLK_IO        0       CLK_A>;
+                                                 txclk  = <&PIO0 6 ALT1 IN   NICLK      0       CLK_A>;
+                                                 col    = <&PIO0 7 ALT1 IN   BYPASS     1000>;
+                                                 mdio   = <&PIO1 0 ALT1 OUT  BYPASS     0>;
+                                                 mdc    = <&PIO1 1 ALT1 OUT  NICLK      0       CLK_A>;
+                                                 crs    = <&PIO1 2 ALT1 IN   BYPASS     1000>;
+                                                 mdint  = <&PIO1 3 ALT1 IN   BYPASS     0>;
+                                                 rxd0   = <&PIO1 4 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd1   = <&PIO1 5 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd2   = <&PIO1 6 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxd3   = <&PIO1 7 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxdv   = <&PIO2 0 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rx_er  = <&PIO2 1 ALT1 IN   SE_NICLK_IO        0       CLK_A>;
+                                                 rxclk  = <&PIO2 2 ALT1 IN   NICLK      0       CLK_A>;
+                                                 phyclk = <&PIO2 3 ALT1 IN   NICLK      1000    CLK_A>;
+                                        };
+                                };
+                                pinctrl_rgmii1: rgmii1-0 {
+                                        st,pins {
+                                                 txd0 =  <&PIO0 0 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd1 =  <&PIO0 1 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd2 =  <&PIO0 2 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txd3 =  <&PIO0 3 ALT1 OUT DE_IO        1000    CLK_A>;
+                                                 txen =  <&PIO0 5 ALT1 OUT DE_IO        0       CLK_A>;
+                                                 txclk = <&PIO0 6 ALT1 IN       NICLK   0       CLK_A>;
+                                                 mdio =  <&PIO1 0 ALT1 OUT      BYPASS  0>;
+                                                 mdc =   <&PIO1 1 ALT1 OUT      NICLK   0       CLK_A>;
+                                                 rxd0 =  <&PIO1 4 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd1 =  <&PIO1 5 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd2 =  <&PIO1 6 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxd3 =  <&PIO1 7 ALT1 IN DE_IO 0       CLK_A>;
+                                                 rxdv =   <&PIO2 0 ALT1 IN DE_IO        500     CLK_A>;
+                                                 rxclk =  <&PIO2 2 ALT1 IN      NICLK   0       CLK_A>;
+                                                 phyclk = <&PIO2 3 ALT4 OUT     NICLK   0       CLK_B>;
+                                                 clk125= <&PIO3 7 ALT4 IN       NICLK   0       CLK_A>;
+                                        };
+                                };
+                        };
                };
                pin-controller-front {
@@ -111,53 +184,73 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih415-front-pinctrl";
                        st,syscfg       = <&syscfg_front>;
+                        reg             = <0xfee0f080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges          = <0 0xfee00000 0x8000>;
                        PIO5: gpio@fee00000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO5";
                        };
                        PIO6: gpio@fee01000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO6";
                        };
                        PIO7: gpio@fee02000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO7";
                        };
                        PIO8: gpio@fee03000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO8";
                        };
                        PIO9: gpio@fee04000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO9";
                        };
                        PIO10: gpio@fee05000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x5000 0x100>;
                                st,bank-name    = "PIO10";
                        };
                        PIO11: gpio@fee06000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x6000 0x100>;
                                st,bank-name    = "PIO11";
                        };
                        PIO12: gpio@fee07000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x7000 0x100>;
                                st,bank-name    = "PIO12";
                        };
@@ -186,41 +279,57 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih415-rear-pinctrl";
                        st,syscfg       = <&syscfg_rear>;
+                        reg             = <0xfe82f080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges          = <0 0xfe820000 0x8000>;
                        PIO13: gpio@fe820000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO13";
                        };
                        PIO14: gpio@fe821000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO14";
                        };
                        PIO15: gpio@fe822000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO15";
                        };
                        PIO16: gpio@fe823000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO16";
                        };
                        PIO17: gpio@fe824000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO17";
                        };
                        PIO18: gpio@fe825000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x5000 0x100>;
                                st,bank-name    = "PIO18";
                        };
@@ -233,6 +342,77 @@
                                        };
                                };
                        };
+                        gmac0{
+                                pinctrl_mii0: mii0 {
+                                        st,pins {
+                                         mdint =        <&PIO13 6 ALT2  IN      BYPASS          0>;
+                                         txen =         <&PIO13 7 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         txd0 =         <&PIO14 0 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         txd1 =         <&PIO14 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         txd2 =         <&PIO14 2 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
+                                         txd3 =         <&PIO14 3 ALT2  OUT     SE_NICLK_IO     0       CLK_B>;
+                                         txclk =        <&PIO15 0 ALT2  IN      NICLK           0       CLK_A>;
+                                         txer =         <&PIO15 1 ALT2  OUT     SE_NICLK_IO     0       CLK_A>;
+                                         crs =          <&PIO15 2 ALT2  IN      BYPASS          1000>;
+                                         col =          <&PIO15 3 ALT2  IN      BYPASS          1000>;
+                                         mdio  =        <&PIO15 4 ALT2  OUT     BYPASS  3000>;
+                                         mdc   =        <&PIO15 5 ALT2  OUT     NICLK   0       CLK_B>;
+                                         rxd0 =         <&PIO16 0 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd1 =         <&PIO16 1 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd2 =         <&PIO16 2 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxd3 =         <&PIO16 3 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxdv =         <&PIO15 6 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rx_er =        <&PIO15 7 ALT2  IN      SE_NICLK_IO     0       CLK_A>;
+                                         rxclk =        <&PIO17 0 ALT2  IN      NICLK           0       CLK_A>;
+                                         phyclk =       <&PIO13 5 ALT2  OUT     NICLK   1000    CLK_A>;
+                                        };
+                                };
+                        pinctrl_gmii0: gmii0 {
+                                st,pins {
+                                         mdint =        <&PIO13 6       ALT2 IN         BYPASS  0>;
+                                         mdio  =        <&PIO15 4       ALT2 OUT        BYPASS  3000>;
+                                         mdc   =        <&PIO15 5       ALT2 OUT        NICLK   0       CLK_B>;
+                                         txen =         <&PIO13 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         txd0 =         <&PIO14 0       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         txd1 =         <&PIO14 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         txd2 =         <&PIO14 2       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd3 =         <&PIO14 3       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd4 =         <&PIO14 4       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd5 =         <&PIO14 5       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd6 =         <&PIO14 6       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txd7 =         <&PIO14 7       ALT2 OUT        SE_NICLK_IO     3000    CLK_B>;
+                                         txclk =        <&PIO15 0       ALT2 IN         NICLK   0       CLK_A>;
+                                         txer =         <&PIO15 1       ALT2 OUT        SE_NICLK_IO     3000    CLK_A>;
+                                         crs =          <&PIO15 2       ALT2 IN         BYPASS  1000>;
+                                         col =          <&PIO15 3       ALT2 IN         BYPASS  1000>;
+                                         rxdv =         <&PIO15 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rx_er =        <&PIO15 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd0 =         <&PIO16 0       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd1 =         <&PIO16 1       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd2 =         <&PIO16 2       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd3 =         <&PIO16 3       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd4 =         <&PIO16 4       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd5 =         <&PIO16 5       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd6 =         <&PIO16 6       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxd7 =         <&PIO16 7       ALT2 IN         SE_NICLK_IO     1500    CLK_A>;
+                                         rxclk =        <&PIO17 0       ALT2 IN NICLK   0       CLK_A>;
+                                         clk125 =       <&PIO17 6       ALT1 IN NICLK   0       CLK_A>;
+                                         phyclk =       <&PIO13 5       ALT4 OUT NICLK   0       CLK_B>;
+                                        };
+                                };
+                        };
                };
                pin-controller-left {
@@ -240,23 +420,33 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih415-left-pinctrl";
                        st,syscfg       = <&syscfg_left>;
+                        reg             = <0xfd6bf080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges          = <0 0xfd6b0000 0x3000>;
                        PIO100: gpio@fd6b0000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO100";
                        };
                        PIO101: gpio@fd6b1000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO101";
                        };
                        PIO102: gpio@fd6b2000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO102";
                        };
@@ -267,35 +457,49 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih415-right-pinctrl";
                        st,syscfg       = <&syscfg_right>;
+                        reg             = <0xfd33f080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges          = <0 0xfd330000 0x5000>;
                        PIO103: gpio@fd330000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO103";
                        };
                        PIO104: gpio@fd331000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO104";
                        };
                        PIO105: gpio@fd332000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO105";
                        };
                        PIO106: gpio@fd333000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO106";
                        };
                        PIO107: gpio@fd334000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO107";
                        };
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d9c7dd1d95a4..d89064c20c8a 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -10,6 +10,7 @@
 #include "stih415-clock.dtsi"
 #include "stih415-pinctrl.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset-controller/stih415-resets.h>
 / {
        L2: cache-controller {
@@ -28,6 +29,16 @@
                ranges;
                compatible      = "simple-bus";
+                powerdown: powerdown-controller {
+                        #reset-cells = <1>;
+                        compatible = "st,stih415-powerdown";
+                };
+                softreset: softreset-controller {
+                        #reset-cells = <1>;
+                        compatible = "st,stih415-softreset";
+                };
                syscfg_sbc: sbc-syscfg@fe600000{
                        compatible      = "st,stih415-sbc-syscfg", "syscon";
                        reg             = <0xfe600000 0xb4>;
@@ -136,5 +147,64 @@
                        status          = "disabled";
                };
+                ethernet0: dwmac@fe810000 {
+                        device_type     = "network";
+                        compatible      = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
+                        status          = "disabled";
+                        reg             = <0xfe810000 0x8000>, <0x148 0x4>;
+                        reg-names       = "stmmaceth", "sti-ethconf";
+                        interrupts      = <0 147 0>, <0 148 0>, <0 149 0>;
+                        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+                        resets                  = <&softreset STIH415_ETH0_SOFTRESET>;
+                        reset-names             = "stmmaceth";
+                        snps,pbl        = <32>;
+                        snps,mixed-burst;
+                        snps,force_sf_dma_mode;
+                        st,syscon       = <&syscfg_rear>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mii0>;
+                        clock-names     = "stmmaceth";
+                        clocks          = <&CLKS_GMAC0_PHY>;
+                };
+                ethernet1: dwmac@fef08000 {
+                        device_type = "network";
+                        compatible      = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
+                        status          = "disabled";
+                        reg             = <0xfef08000 0x8000>, <0x74 0x4>;
+                        reg-names       = "stmmaceth", "sti-ethconf";
+                        interrupts      = <0 150 0>, <0 151 0>, <0 152 0>;
+                        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+                        snps,pbl        = <32>;
+                        snps,mixed-burst;
+                        snps,force_sf_dma_mode;
+                        st,syscon               = <&syscfg_sbc>;
+                        resets                  = <&softreset STIH415_ETH1_SOFTRESET>;
+                        reset-names             = "stmmaceth";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mii1>;
+                        clock-names     = "stmmaceth";
+                        clocks          = <&CLKS_ETH1_PHY>;
+                };
+                rc: rc@fe518000 {
+                        compatible      = "st,comms-irb";
+                        reg             = <0xfe518000 0x234>;
+                        interrupts      =  <0 203 0>;
+                        clocks          = <&CLK_SYSIN>;
+                        rx-mode         = "infrared";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_ir>;
+                        resets          = <&softreset STIH415_IRB_SOFTRESET>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1158d8..a6942c75cbbb 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
                        clock-frequency = <100000000>;
                        clock-output-names = "CLK_S_ICN_REG_0";
                };
+                CLK_S_GMAC0_PHY: clockgenA1@7 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <25000000>;
+                        clock-output-names = "CLK_S_GMAC0_PHY";
+                };
+                CLK_S_ETH1_PHY: clockgenA0@7 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <25000000>;
+                        clock-output-names = "CLK_S_ETH1_PHY";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index b29ff4ba542c..aeea304086eb 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -8,6 +8,7 @@
 * publishhed by the Free Software Foundation.
 */
 #include "st-pincfg.h"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
        aliases {
@@ -49,46 +50,69 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih416-sbc-pinctrl";
                        st,syscfg       = <&syscfg_sbc>;
+                        reg             = <0xfe61f080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges          = <0 0xfe610000 0x6000>;
                        PIO0: gpio@fe610000 {
                                gpio-controller;
                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO0";
                        };
                        PIO1: gpio@fe611000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO1";
                        };
                        PIO2: gpio@fe612000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO2";
                        };
                        PIO3: gpio@fe613000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO3";
                        };
                        PIO4: gpio@fe614000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO4";
                        };
                        PIO40: gpio@fe615000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x5000 0x100>;
                                st,bank-name    = "PIO40";
                                st,retime-pin-mask = <0x7f>;
                        };
+                        rc{
+                                pinctrl_ir: ir0 {
+                                        st,pins {
+                                                ir = <&PIO4 0 ALT2 IN>;
+                                        };
+                                };
+                        };
                        sbc_serial1 {
                                pinctrl_sbc_serial1: sbc_serial1 {
                                        st,pins {
@@ -115,6 +139,58 @@
                                        };
                                };
                        };
+                        gmac1 {
+                                pinctrl_mii1: mii1 {
+                                        st,pins {
+                                                txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
+                                                col =   <&PIO0 7 ALT1 IN BYPASS 1000>;
+                                                mdio =  <&PIO1 0 ALT1 OUT BYPASS 1500>;
+                                                mdc =   <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
+                                                crs =   <&PIO1 2 ALT1 IN BYPASS 1000>;
+                                                mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
+                                                rxd0 =  <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd1 =  <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd2 =  <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd3 =  <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxdv =  <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
+                                                phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
+                                        };
+                                };
+                                pinctrl_rgmii1: rgmii1-0 {
+                                        st,pins {
+                                                txd0 =  <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd1 =  <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd2 =  <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txd3 =  <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
+                                                txen =  <&PIO0 5 ALT1 OUT DE_IO 0   CLK_A>;
+                                                txclk = <&PIO0 6 ALT1 IN  NICLK 0   CLK_A>;
+                                                mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
+                                                mdc  = <&PIO1 1 ALT1 OUT NICLK  0 CLK_A>;
+                                                rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
+                                                rxdv   = <&PIO2 0 ALT1 IN  DE_IO 500 CLK_A>;
+                                                rxclk  = <&PIO2 2 ALT1 IN  NICLK 0   CLK_A>;
+                                                phyclk = <&PIO2 3 ALT4 OUT NICLK 0   CLK_B>;
+                                                clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
+                                        };
+                                };
+                        };
                };
                pin-controller-front {
@@ -122,65 +198,89 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih416-front-pinctrl";
                        st,syscfg       = <&syscfg_front>;
+                        reg             = <0xfee0f080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges          = <0 0xfee00000 0x10000>;
                        PIO5: gpio@fee00000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO5";
                        };
                        PIO6: gpio@fee01000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO6";
                        };
                        PIO7: gpio@fee02000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO7";
                        };
                        PIO8: gpio@fee03000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO8";
                        };
                        PIO9: gpio@fee04000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO9";
                        };
                        PIO10: gpio@fee05000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x5000 0x100>;
                                st,bank-name    = "PIO10";
                        };
                        PIO11: gpio@fee06000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x6000 0x100>;
                                st,bank-name    = "PIO11";
                        };
                        PIO12: gpio@fee07000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x7000 0x100>;
                                st,bank-name    = "PIO12";
                        };
                        PIO30: gpio@fee08000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x8000 0x100>;
                                st,bank-name    = "PIO30";
                        };
                        PIO31: gpio@fee09000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x9000 0x100>;
                                st,bank-name    = "PIO31";
                        };
@@ -210,6 +310,19 @@
                                        };
                                };
                        };
+                        fsm {
+                                pinctrl_fsm: fsm {
+                                        st,pins {
+                                                spi-fsm-clk  = <&PIO12 2 ALT1 OUT>;
+                                                spi-fsm-cs   = <&PIO12 3 ALT1 OUT>;
+                                                spi-fsm-mosi = <&PIO12 4 ALT1 OUT>;
+                                                spi-fsm-miso = <&PIO12 5 ALT1 IN>;
+                                                spi-fsm-hol  = <&PIO12 6 ALT1 OUT>;
+                                                spi-fsm-wp   = <&PIO12 7 ALT1 OUT>;
+                                        };
+                                };
+                        };
                };
                pin-controller-rear {
@@ -217,41 +330,57 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih416-rear-pinctrl";
                        st,syscfg       = <&syscfg_rear>;
+                        reg             = <0xfe82f080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges          = <0 0xfe820000 0x6000>;
                        PIO13: gpio@fe820000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO13";
                        };
                        PIO14: gpio@fe821000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO14";
                        };
                        PIO15: gpio@fe822000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO15";
                        };
                        PIO16: gpio@fe823000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO16";
                        };
                        PIO17: gpio@fe824000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO17";
                        };
                        PIO18: gpio@fe825000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x5000 0x100>;
                                st,bank-name    = "PIO18";
                                st,retime-pin-mask = <0xf>;
@@ -265,6 +394,63 @@
                                        };
                                };
                        };
+                        gmac0 {
+                                pinctrl_mii0: mii0 {
+                                        st,pins {
+                                                mdint = <&PIO13 6 ALT2 IN  BYPASS      0>;
+                                                txen =  <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd0 =  <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd1 =  <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd2 =  <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+                                                txd3 =  <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
+                                                txclk = <&PIO15 0 ALT2 IN  NICLK       0 CLK_A>;
+                                                txer =  <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+                                                crs = <&PIO15 2 ALT2 IN  BYPASS 1000>;
+                                                col = <&PIO15 3 ALT2 IN  BYPASS 1000>;
+                                                mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
+                                                mdc = <&PIO15 5 ALT2 OUT NICLK  0    CLK_B>;
+                                                rxd0 =  <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd1 =  <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd2 =  <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd3 =  <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxdv =  <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+                                                phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
+                                        };
+                                };
+                                pinctrl_gmii0: gmii0 {
+                                        st,pins {
+                                                };
+                                };
+                                pinctrl_rgmii0: rgmii0 {
+                                        st,pins {
+                                                 phyclk = <&PIO13  5 ALT4 OUT NICLK 0 CLK_B>;
+                                                 txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
+                                                 txd0  = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
+                                                 txd1  = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
+                                                 txd2  = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
+                                                 txd3  = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
+                                                 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
+                                                 mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
+                                                 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
+                                                 rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
+                                                 rxd0 =<&PIO16 0 ALT2 IN DE_IO  500 CLK_A>;
+                                                 rxd1 =<&PIO16 1 ALT2 IN DE_IO  500 CLK_A>;
+                                                 rxd2 =<&PIO16 2 ALT2 IN DE_IO  500 CLK_A>;
+                                                 rxd3  =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
+                                                 rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
+                                                 clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
+                                        };
+                                };
+                        };
                };
                pin-controller-fvdp-fe {
@@ -272,23 +458,33 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih416-fvdp-fe-pinctrl";
                        st,syscfg       = <&syscfg_fvdp_fe>;
+                        reg             = <0xfd6bf080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges          = <0 0xfd6b0000 0x3000>;
                        PIO100: gpio@fd6b0000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO100";
                        };
                        PIO101: gpio@fd6b1000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO101";
                        };
                        PIO102: gpio@fd6b2000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO102";
                        };
@@ -299,29 +495,41 @@
                        #size-cells     = <1>;
                        compatible      = "st,stih416-fvdp-lite-pinctrl";
                        st,syscfg               = <&syscfg_fvdp_lite>;
+                        reg             = <0xfd33f080 0x4>;
+                        reg-names       = "irqmux";
+                        interrupts      = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-names = "irqmux";
                        ranges                  = <0 0xfd330000 0x5000>;
                        PIO103: gpio@fd330000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0 0x100>;
                                st,bank-name    = "PIO103";
                        };
                        PIO104: gpio@fd331000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x1000 0x100>;
                                st,bank-name    = "PIO104";
                        };
                        PIO105: gpio@fd332000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x2000 0x100>;
                                st,bank-name    = "PIO105";
                        };
                        PIO106: gpio@fd333000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x3000 0x100>;
                                st,bank-name    = "PIO106";
                        };
@@ -329,6 +537,8 @@
                        PIO107: gpio@fd334000 {
                                gpio-controller;
                                #gpio-cells     = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                                reg             = <0x4000 0x100>;
                                st,bank-name    = "PIO107";
                                st,retime-pin-mask = <0xf>;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index b7ab47b95816..78746d20382e 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -10,6 +10,7 @@
 #include "stih416-clock.dtsi"
 #include "stih416-pinctrl.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset-controller/stih416-resets.h>
 / {
        L2: cache-controller {
                compatible = "arm,pl310-cache";
@@ -27,6 +28,16 @@
                ranges;
                compatible      = "simple-bus";
+                powerdown: powerdown-controller {
+                        #reset-cells = <1>;
+                        compatible = "st,stih416-powerdown";
+                };
+                softreset: softreset-controller {
+                        #reset-cells = <1>;
+                        compatible = "st,stih416-softreset";
+                };
                syscfg_sbc:sbc-syscfg@fe600000{
                        compatible      = "st,stih416-sbc-syscfg", "syscon";
                        reg             = <0xfe600000 0x1000>;
@@ -145,5 +156,73 @@
                        status          = "disabled";
                };
+                ethernet0: dwmac@fe810000 {
+                        device_type     = "network";
+                        compatible      = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+                        status          = "disabled";
+                        reg             = <0xfe810000 0x8000>, <0x8bc 0x4>;
+                        reg-names       = "stmmaceth", "sti-ethconf";
+                        interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
+                        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+                        snps,pbl        = <32>;
+                        snps,mixed-burst;
+                        st,syscon               = <&syscfg_rear>;
+                        resets                  = <&softreset STIH416_ETH0_SOFTRESET>;
+                        reset-names             = "stmmaceth";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mii0>;
+                        clock-names     = "stmmaceth";
+                        clocks          = <&CLK_S_GMAC0_PHY>;
+                };
+                ethernet1: dwmac@fef08000 {
+                        device_type = "network";
+                        compatible              = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+                        status          = "disabled";
+                        reg             = <0xfef08000 0x8000>, <0x7f0 0x4>;
+                        reg-names       = "stmmaceth", "sti-ethconf";
+                        interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
+                        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+                        snps,pbl        = <32>;
+                        snps,mixed-burst;
+                        st,syscon       = <&syscfg_sbc>;
+                        resets          = <&softreset STIH416_ETH1_SOFTRESET>;
+                        reset-names     = "stmmaceth";
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_mii1>;
+                        clock-names     = "stmmaceth";
+                        clocks          = <&CLK_S_ETH1_PHY>;
+                };
+                rc: rc@fe518000 {
+                        compatible      = "st,comms-irb";
+                        reg             = <0xfe518000 0x234>;
+                        interrupts      =  <0 203 0>;
+                        rx-mode         = "infrared";
+                        clocks          = <&CLK_SYSIN>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_ir>;
+                        resets          = <&softreset STIH416_IRB_SOFTRESET>;
+                };
+                /* FSM */
+                spifsm: spifsm@fe902000 {
+                        compatible         = "st,spi-fsm";
+                        reg                = <0xfe902000 0x1000>;
+                        pinctrl-0          = <&pinctrl_fsm>;
+                        st,syscfg          = <&syscfg_rear>;
+                        st,boot-device-reg = <0x958>;
+                        st,boot-device-spi = <0x1a>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 1e6aa92772f5..bf65c49095af 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -20,6 +20,8 @@
        aliases {
                ttyAS0 = &serial2;
+                ethernet0 = &ethernet0;
+                ethernet1 = &ethernet1;
        };
        soc {
@@ -46,5 +48,25 @@
                        status = "okay";
                };
+                ethernet0: dwmac@fe810000 {
+                        status                  = "okay";
+                        phy-mode                = "mii";
+                        pinctrl-0               = <&pinctrl_mii0>;
+                        snps,reset-gpio         = <&PIO106 2>;
+                        snps,reset-active-low;
+                        snps,reset-delays-us    = <0 10000 10000>;
+                };
+                ethernet1: dwmac@fef08000 {
+                        status                  = "disabled";
+                        phy-mode                = "mii";
+                        st,tx-retime-src        = "txclk";
+                        snps,reset-gpio         = <&PIO4 7>;
+                        snps,reset-active-low;
+                        snps,reset-delays-us    = <0 10000 10000>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 0ef0a69df8ea..838513f9ddc0 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -6,6 +6,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
+#include "stih41x-b2020x.dtsi"
 / {
        memory{
                device_type = "memory";
@@ -19,6 +20,7 @@
        aliases {
                ttyAS0 = &sbc_serial1;
+                ethernet1 = &ethernet1;
        };
        soc {
                sbc_serial1: serial@fe531000 {
@@ -60,5 +62,17 @@
                i2c@fe541000 {
                        status = "okay";
                };
+                ethernet1: dwmac@fef08000 {
+                        status                  = "okay";
+                        phy-mode                = "rgmii-id";
+                        max-speed               = <1000>;
+                        st,tx-retime-src        = "clk_125";
+                        snps,reset-gpio         = <&PIO3 0>;
+                        snps,reset-active-low;
+                        snps,reset-delays-us    = <0 10000 10000>;
+                        pinctrl-0       = <&pinctrl_rgmii1>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi
new file mode 100644
index 000000000000..df01c1211b32
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2020x.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Lee Jones <lee.jones@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/ {
+        soc {
+                spifsm: spifsm@fe902000 {
+                        #address-cells = <1>;
+                        #size-cells    = <1>;
+                        status = "okay";
+                        partition@0 {
+                                label = "SerialFlash1";
+                                reg   = <0x00000000 0x00500000>;
+                        };
+                        partition@500000 {
+                                label = "SerialFlash2";
+                                reg   = <0x00500000 0x00b00000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index d4b081d6a167..fa746aea5e66 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -13,6 +13,7 @@
 /dts-v1/;
 /include/ "sun4i-a10.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "Mele A1000";
@@ -35,6 +36,32 @@
                        };
                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ahci: sata@01c18000 {
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
                pinctrl@01c20800 {
                        emac_power_pin_a1000: emac_power_pin@0 {
                                allwinner,pins = "PH15";
@@ -80,18 +107,22 @@
                };
        };
-        regulators {
+        reg_emac_3v3: emac-3v3 {
-                compatible = "simple-bus";
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&emac_power_pin_a1000>;
+                regulator-name = "emac-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                gpio = <&pio 7 15 0>;
+        };
-                reg_emac_3v3: emac-3v3 {
+        reg_usb1_vbus: usb1-vbus {
-                        compatible = "regulator-fixed";
+                status = "okay";
-                        pinctrl-names = "default";
+        };
-                        pinctrl-0 = <&emac_power_pin_a1000>;
-                        regulator-name = "emac-3v3";
+        reg_usb2_vbus: usb2-vbus {
-                        regulator-min-microvolt = <3300000>;
+                status = "okay";
-                        regulator-max-microvolt = <3300000>;
-                        enable-active-high;
-                        gpio = <&pio 7 15 0>;
-                };
        };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b139ee6bcf99..4684cbe6843b 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -12,6 +12,7 @@
 /dts-v1/;
 /include/ "sun4i-a10.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "Cubietech Cubieboard";
@@ -33,6 +34,33 @@
                        };
                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ahci: sata@01c18000 {
+                        target-supply = <&reg_ahci_5v>;
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
                pinctrl@01c20800 {
                        led_pins_cubieboard: led_pins@0 {
                                allwinner,pins = "PH20", "PH21";
@@ -77,4 +105,16 @@
                        linux,default-trigger = "heartbeat";
                };
        };
+        reg_ahci_5v: ahci-5v {
+                status = "okay";
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 3a1595f67823..d7c17e46ce23 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -13,6 +13,7 @@
 /dts-v1/;
 /include/ "sun4i-a10.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "Miniand Hackberry";
@@ -35,6 +36,28 @@
                        };
                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
                pio: pinctrl@01c20800 {
                        pinctrl-names = "default";
                        pinctrl-0 = <&hackberry_hogs>;
@@ -45,6 +68,13 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        usb2_vbus_pin_hackberry: usb2_vbus_pin@0 {
+                                        allwinner,pins = "PH12";
+                                        allwinner,function = "gpio_out";
+                                        allwinner,drive = <0>;
+                                        allwinner,pull = <0>;
+                        };
                };
                uart0: serial@01c28000 {
@@ -54,16 +84,22 @@
                };
        };
-        regulators {
+        reg_emac_3v3: emac-3v3 {
-                compatible = "simple-bus";
+                compatible = "regulator-fixed";
+                regulator-name = "emac-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                gpio = <&pio 7 19 0>;
+        };
-                reg_emac_3v3: emac-3v3 {
+        reg_usb1_vbus: usb1-vbus {
-                        compatible = "regulator-fixed";
+                status = "okay";
-                        regulator-name = "emac-3v3";
+        };
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
+        reg_usb2_vbus: usb2-vbus {
-                        enable-active-high;
+                pinctrl-0 = <&usb2_vbus_pin_hackberry>;
-                        gpio = <&pio 7 19 0>;
+                gpio = <&pio 7 12 0>;
-                };
+                status = "okay";
        };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
new file mode 100644
index 000000000000..fe9272ee55c3
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2014 Open Source Support GmbH
+ *
+ * David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun4i-a10.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "INet-97F Rev 02";
+        compatible = "primux,inet97fv2", "allwinner,sun4i-a10";
+        aliases {
+                serial0 = &uart0;
+        };
+        soc@01c00000 {
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 70b3323caf1a..dd84a9e313b3 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -13,16 +13,47 @@
 /dts-v1/;
 /include/ "sun4i-a10.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "PineRiver Mini X-Plus";
        compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
        soc@01c00000 {
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
                uart0: serial@01c28000 {
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart0_pins_a>;
                        status = "okay";
                };
        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
new file mode 100644
index 000000000000..66cf0c7cf5b7
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun4i-a10.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "Olimex A10-OLinuXino-LIME";
+        compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
+        soc@01c00000 {
+                emac: ethernet@01c0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&emac_pins_a>;
+                        phy = <&phy1>;
+                        status = "okay";
+                };
+                mdio@01c0b080 {
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ahci: sata@01c18000 {
+                        target-supply = <&reg_ahci_5v>;
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+                pinctrl@01c20800 {
+                        ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
+                                allwinner,pins = "PC3";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        led_pins_olinuxinolime: led_pins@0 {
+                                allwinner,pins = "PH2";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxinolime>;
+                green {
+                        label = "a10-olinuxino-lime:green:usr";
+                        gpios = <&pio 7 2 0>;
+                        default-state = "on";
+                };
+        };
+        reg_ahci_5v: ahci-5v {
+                pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
+                gpio = <&pio 2 3 0>;
+                status = "okay";
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
new file mode 100644
index 000000000000..255b47e7019c
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2014 Zoltan HERPAI
+ * Zoltan HERPAI <wigyori@uid0.hu>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun4i-a10.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "LinkSprite pcDuino";
+        compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10";
+        soc@01c00000 {
+                emac: ethernet@01c0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&emac_pins_a>;
+                        phy = <&phy1>;
+                        status = "okay";
+                };
+                mdio@01c0b080 {
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 249b6e0ba737..9174724571e2 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -19,6 +19,12 @@
                ethernet0 = &emac;
                serial0 = &uart0;
                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                serial6 = &uart6;
+                serial7 = &uart7;
        };
        cpus {
@@ -52,44 +58,48 @@
                        clock-frequency = <0>;
                };
-                osc24M: osc24M@01c20050 {
+                osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-osc-clk";
+                        compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
+                        clock-output-names = "osc24M";
                };
-                osc32k: osc32k {
+                osc32k: clk@0 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
                };
-                pll1: pll1@01c20000 {
+                pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-pll1-clk";
+                        compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
+                        clock-output-names = "pll1";
                };
-                pll4: pll4@01c20018 {
+                pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-pll1-clk";
+                        compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
+                        clock-output-names = "pll4";
                };
-                pll5: pll5@01c20020 {
+                pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-pll5-clk";
+                        compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
                };
-                pll6: pll6@01c20028 {
+                pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-pll6-clk";
+                        compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -98,21 +108,23 @@
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-cpu-clk";
+                        compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                        clock-output-names = "cpu";
                };
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-axi-clk";
+                        compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
+                        clock-output-names = "axi";
                };
-                axi_gates: axi_gates@01c2005c {
+                axi_gates: clk@01c2005c {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        compatible = "allwinner,sun4i-a10-axi-gates-clk";
                        reg = <0x01c2005c 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "axi_dram";
@@ -120,14 +132,15 @@
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-ahb-clk";
+                        compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
+                        clock-output-names = "ahb";
                };
-                ahb_gates: ahb_gates@01c20060 {
+                ahb_gates: clk@01c20060 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        compatible = "allwinner,sun4i-a10-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
                        clocks = <&ahb>;
                        clock-output-names = "ahb_usb0", "ahb_ehci0",
@@ -145,14 +158,15 @@
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb0-clk";
+                        compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
+                        clock-output-names = "apb0";
                };
-                apb0_gates: apb0_gates@01c20068 {
+                apb0_gates: clk@01c20068 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        compatible = "allwinner,sun4i-a10-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
                        clocks = <&apb0>;
                        clock-output-names = "apb0_codec", "apb0_spdif",
@@ -162,21 +176,23 @@
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                        clock-output-names = "apb1_mux";
                };
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb1-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
+                        clock-output-names = "apb1";
                };
-                apb1_gates: apb1_gates@01c2006c {
+                apb1_gates: clk@01c2006c {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
                        clocks = <&apb1>;
                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
@@ -189,7 +205,7 @@
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
@@ -197,7 +213,7 @@
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
@@ -205,7 +221,7 @@
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
@@ -213,7 +229,7 @@
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
@@ -221,7 +237,7 @@
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
@@ -229,7 +245,7 @@
                mmc3_clk: clk@01c20094 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20094 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc3";
@@ -237,7 +253,7 @@
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
@@ -245,7 +261,7 @@
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
@@ -253,7 +269,7 @@
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
@@ -261,7 +277,7 @@
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
@@ -269,7 +285,7 @@
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
@@ -277,7 +293,7 @@
                pata_clk: clk@01c200ac {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200ac 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "pata";
@@ -285,7 +301,7 @@
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
@@ -293,15 +309,24 @@
                ir1_clk: clk@01c200b4 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir1";
                };
+                usb_clk: clk@01c200cc {
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-usb-clk";
+                        reg = <0x01c200cc 0x4>;
+                        clocks = <&pll6 1>;
+                        clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+                };
                spi3_clk: clk@01c200d4 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200d4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi3";
@@ -314,6 +339,28 @@
                #size-cells = <1>;
                ranges;
+                spi0: spi@01c05000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c05000 0x1000>;
+                        interrupts = <10>;
+                        clocks = <&ahb_gates 20>, <&spi0_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                spi1: spi@01c06000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c06000 0x1000>;
+                        interrupts = <11>;
+                        clocks = <&ahb_gates 21>, <&spi1_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
                emac: ethernet@01c0b000 {
                        compatible = "allwinner,sun4i-a10-emac";
                        reg = <0x01c0b000 0x1000>;
@@ -330,6 +377,88 @@
                        #size-cells = <0>;
                };
+                usbphy: phy@01c13400 {
+                        #phy-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-usb-phy";
+                        reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+                        reg-names = "phy_ctrl", "pmu1", "pmu2";
+                        clocks = <&usb_clk 8>;
+                        clock-names = "usb_phy";
+                        resets = <&usb_clk 1>, <&usb_clk 2>;
+                        reset-names = "usb1_reset", "usb2_reset";
+                        status = "disabled";
+                };
+                ehci0: usb@01c14000 {
+                        compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
+                        reg = <0x01c14000 0x100>;
+                        interrupts = <39>;
+                        clocks = <&ahb_gates 1>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ohci0: usb@01c14400 {
+                        compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
+                        reg = <0x01c14400 0x100>;
+                        interrupts = <64>;
+                        clocks = <&usb_clk 6>, <&ahb_gates 2>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                spi2: spi@01c17000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c17000 0x1000>;
+                        interrupts = <12>;
+                        clocks = <&ahb_gates 22>, <&spi2_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                ahci: sata@01c18000 {
+                        compatible = "allwinner,sun4i-a10-ahci";
+                        reg = <0x01c18000 0x1000>;
+                        interrupts = <56>;
+                        clocks = <&pll6 0>, <&ahb_gates 25>;
+                        status = "disabled";
+                };
+                ehci1: usb@01c1c000 {
+                        compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
+                        reg = <0x01c1c000 0x100>;
+                        interrupts = <40>;
+                        clocks = <&ahb_gates 3>;
+                        phys = <&usbphy 2>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ohci1: usb@01c1c400 {
+                        compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
+                        reg = <0x01c1c400 0x100>;
+                        interrupts = <65>;
+                        clocks = <&usb_clk 7>, <&ahb_gates 4>;
+                        phys = <&usbphy 2>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                spi3: spi@01c1f000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c1f000 0x1000>;
+                        interrupts = <50>;
+                        clocks = <&ahb_gates 23>, <&spi3_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
                intc: interrupt-controller@01c20400 {
                        compatible = "allwinner,sun4i-a10-ic";
                        reg = <0x01c20400 0x400>;
@@ -410,18 +539,18 @@
                };
                wdt: watchdog@01c20c90 {
-                        compatible = "allwinner,sun4i-wdt";
+                        compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                };
                rtc: rtc@01c20d00 {
-                        compatible = "allwinner,sun4i-rtc";
+                        compatible = "allwinner,sun4i-a10-rtc";
                        reg = <0x01c20d00 0x20>;
                        interrupts = <24>;
                };
                sid: eeprom@01c23800 {
-                        compatible = "allwinner,sun4i-sid";
+                        compatible = "allwinner,sun4i-a10-sid";
                        reg = <0x01c23800 0x10>;
                };
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 3c9f8b3cd3e3..23611b71d3aa 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -13,6 +13,7 @@
 /dts-v1/;
 /include/ "sun5i-a10s.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "Olimex A10s-Olinuxino Micro";
@@ -34,6 +35,19 @@
                        };
                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
                pinctrl@01c20800 {
                        led_pins_olinuxino: led_pins@0 {
                                allwinner,pins = "PE3";
@@ -41,6 +55,13 @@
                                allwinner,drive = <1>;
                                allwinner,pull = <0>;
                        };
+                        usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 {
+                                allwinner,pins = "PB10";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                };
                uart0: serial@01c28000 {
@@ -98,4 +119,10 @@
                        default-state = "on";
                };
        };
+        reg_usb1_vbus: usb1-vbus {
+                pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>;
+                gpio = <&pio 1 10 0>;
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ddb25452d78e..79989ed5658d 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -18,6 +18,10 @@
        aliases {
                ethernet0 = &emac;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
        };
        cpus {
@@ -47,44 +51,48 @@
                        clock-frequency = <0>;
                };
-                osc24M: osc24M@01c20050 {
+                osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-osc-clk";
+                        compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
+                        clock-output-names = "osc24M";
                };
-                osc32k: osc32k {
+                osc32k: clk@0 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
                };
-                pll1: pll1@01c20000 {
+                pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-pll1-clk";
+                        compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
+                        clock-output-names = "pll1";
                };
-                pll4: pll4@01c20018 {
+                pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-pll1-clk";
+                        compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
+                        clock-output-names = "pll4";
                };
-                pll5: pll5@01c20020 {
+                pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-pll5-clk";
+                        compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
                };
-                pll6: pll6@01c20028 {
+                pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-pll6-clk";
+                        compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +101,23 @@
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-cpu-clk";
+                        compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                        clock-output-names = "cpu";
                };
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-axi-clk";
+                        compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
+                        clock-output-names = "axi";
                };
-                axi_gates: axi_gates@01c2005c {
+                axi_gates: clk@01c2005c {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        compatible = "allwinner,sun4i-a10-axi-gates-clk";
                        reg = <0x01c2005c 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "axi_dram";
@@ -115,12 +125,13 @@
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-ahb-clk";
+                        compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
+                        clock-output-names = "ahb";
                };
-                ahb_gates: ahb_gates@01c20060 {
+                ahb_gates: clk@01c20060 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
@@ -136,12 +147,13 @@
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb0-clk";
+                        compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
+                        clock-output-names = "apb0";
                };
-                apb0_gates: apb0_gates@01c20068 {
+                apb0_gates: clk@01c20068 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
@@ -152,19 +164,21 @@
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                        clock-output-names = "apb1_mux";
                };
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb1-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
+                        clock-output-names = "apb1";
                };
-                apb1_gates: apb1_gates@01c2006c {
+                apb1_gates: clk@01c2006c {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
@@ -176,7 +190,7 @@
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
@@ -184,7 +198,7 @@
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
@@ -192,7 +206,7 @@
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
@@ -200,7 +214,7 @@
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
@@ -208,7 +222,7 @@
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
@@ -216,7 +230,7 @@
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
@@ -224,7 +238,7 @@
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
@@ -232,7 +246,7 @@
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
@@ -240,7 +254,7 @@
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
@@ -248,7 +262,7 @@
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
@@ -256,15 +270,24 @@
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
                };
+                usb_clk: clk@01c200cc {
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun5i-a13-usb-clk";
+                        reg = <0x01c200cc 0x4>;
+                        clocks = <&pll6 1>;
+                        clock-output-names = "usb_ohci0", "usb_phy";
+                };
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2015c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mbus";
@@ -277,6 +300,28 @@
                #size-cells = <1>;
                ranges;
+                spi0: spi@01c05000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c05000 0x1000>;
+                        interrupts = <10>;
+                        clocks = <&ahb_gates 20>, <&spi0_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                spi1: spi@01c06000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c06000 0x1000>;
+                        interrupts = <11>;
+                        clocks = <&ahb_gates 21>, <&spi1_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
                emac: ethernet@01c0b000 {
                        compatible = "allwinner,sun4i-a10-emac";
                        reg = <0x01c0b000 0x1000>;
@@ -293,6 +338,49 @@
                        #size-cells = <0>;
                };
+                usbphy: phy@01c13400 {
+                        #phy-cells = <1>;
+                        compatible = "allwinner,sun5i-a13-usb-phy";
+                        reg = <0x01c13400 0x10 0x01c14800 0x4>;
+                        reg-names = "phy_ctrl", "pmu1";
+                        clocks = <&usb_clk 8>;
+                        clock-names = "usb_phy";
+                        resets = <&usb_clk 1>;
+                        reset-names = "usb1_reset";
+                        status = "disabled";
+                };
+                ehci0: usb@01c14000 {
+                        compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
+                        reg = <0x01c14000 0x100>;
+                        interrupts = <39>;
+                        clocks = <&ahb_gates 1>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ohci0: usb@01c14400 {
+                        compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
+                        reg = <0x01c14400 0x100>;
+                        interrupts = <40>;
+                        clocks = <&usb_clk 6>, <&ahb_gates 2>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                spi2: spi@01c17000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c17000 0x1000>;
+                        interrupts = <12>;
+                        clocks = <&ahb_gates 22>, <&spi2_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
                intc: interrupt-controller@01c20400 {
                        compatible = "allwinner,sun4i-a10-ic";
                        reg = <0x01c20400 0x400>;
@@ -373,12 +461,12 @@
                };
                wdt: watchdog@01c20c90 {
-                        compatible = "allwinner,sun4i-wdt";
+                        compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                };
                sid: eeprom@01c23800 {
-                        compatible = "allwinner,sun4i-sid";
+                        compatible = "allwinner,sun4i-a10-sid";
                        reg = <0x01c23800 0x10>;
                };
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index fe2ce0acdb06..11169d5b5b86 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -14,12 +14,26 @@
 /dts-v1/;
 /include/ "sun5i-a13.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "Olimex A13-Olinuxino Micro";
        compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
        soc@01c00000 {
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
                pinctrl@01c20800 {
                        led_pins_olinuxinom: led_pins@0 {
                                allwinner,pins = "PG9";
@@ -27,6 +41,13 @@
                                allwinner,drive = <1>;
                                allwinner,pull = <0>;
                        };
+                        usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 {
+                                allwinner,pins = "PG11";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                };
                uart1: serial@01c28400 {
@@ -65,4 +86,10 @@
                        default-state = "on";
                };
        };
+        reg_usb1_vbus: usb1-vbus {
+                pinctrl-0 = <&usb1_vbus_pin_olinuxinom>;
+                gpio = <&pio 6 11 0>;
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index a4ba5ff010cf..7a9187bbeb28 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -13,12 +13,26 @@
 /dts-v1/;
 /include/ "sun5i-a13.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "Olimex A13-Olinuxino";
        compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
        soc@01c00000 {
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
                pinctrl@01c20800 {
                        led_pins_olinuxino: led_pins@0 {
                                allwinner,pins = "PG9";
@@ -26,6 +40,13 @@
                                allwinner,drive = <1>;
                                allwinner,pull = <0>;
                        };
+                        usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
+                                allwinner,pins = "PG11";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                };
                uart1: serial@01c28400 {
@@ -63,4 +84,10 @@
                        default-state = "on";
                };
        };
+        reg_usb1_vbus: usb1-vbus {
+                pinctrl-0 = <&usb1_vbus_pin_olinuxino>;
+                gpio = <&pio 6 11 0>;
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index b373c74a9b3d..f01c315bdc4b 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -16,6 +16,11 @@
 / {
        interrupt-parent = <&intc>;
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart3;
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -47,44 +52,48 @@
                        clock-frequency = <0>;
                };
-                osc24M: osc24M@01c20050 {
+                osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-osc-clk";
+                        compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
+                        clock-output-names = "osc24M";
                };
-                osc32k: osc32k {
+                osc32k: clk@0 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
                };
-                pll1: pll1@01c20000 {
+                pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-pll1-clk";
+                        compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
+                        clock-output-names = "pll1";
                };
-                pll4: pll4@01c20018 {
+                pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-pll1-clk";
+                        compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
+                        clock-output-names = "pll4";
                };
-                pll5: pll5@01c20020 {
+                pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-pll5-clk";
+                        compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
                };
-                pll6: pll6@01c20028 {
+                pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-pll6-clk";
+                        compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +102,23 @@
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-cpu-clk";
+                        compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                        clock-output-names = "cpu";
                };
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-axi-clk";
+                        compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
+                        clock-output-names = "axi";
                };
-                axi_gates: axi_gates@01c2005c {
+                axi_gates: clk@01c2005c {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        compatible = "allwinner,sun4i-a10-axi-gates-clk";
                        reg = <0x01c2005c 0x4>;
                        clocks = <&axi>;
                        clock-output-names = "axi_dram";
@@ -115,12 +126,13 @@
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-ahb-clk";
+                        compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
+                        clock-output-names = "ahb";
                };
-                ahb_gates: ahb_gates@01c20060 {
+                ahb_gates: clk@01c20060 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a13-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
@@ -135,12 +147,13 @@
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb0-clk";
+                        compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
+                        clock-output-names = "apb0";
                };
-                apb0_gates: apb0_gates@01c20068 {
+                apb0_gates: clk@01c20068 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a13-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
@@ -150,19 +163,21 @@
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                        clock-output-names = "apb1_mux";
                };
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb1-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
+                        clock-output-names = "apb1";
                };
-                apb1_gates: apb1_gates@01c2006c {
+                apb1_gates: clk@01c2006c {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun5i-a13-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
@@ -173,7 +188,7 @@
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
@@ -181,7 +196,7 @@
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
@@ -189,7 +204,7 @@
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
@@ -197,7 +212,7 @@
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
@@ -205,7 +220,7 @@
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
@@ -213,7 +228,7 @@
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
@@ -221,7 +236,7 @@
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
@@ -229,7 +244,7 @@
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
@@ -237,7 +252,7 @@
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
@@ -245,7 +260,7 @@
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
@@ -253,15 +268,24 @@
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
                };
+                usb_clk: clk@01c200cc {
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun5i-a13-usb-clk";
+                        reg = <0x01c200cc 0x4>;
+                        clocks = <&pll6 1>;
+                        clock-output-names = "usb_ohci0", "usb_phy";
+                };
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2015c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mbus";
@@ -274,6 +298,71 @@
                #size-cells = <1>;
                ranges;
+                spi0: spi@01c05000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c05000 0x1000>;
+                        interrupts = <10>;
+                        clocks = <&ahb_gates 20>, <&spi0_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                spi1: spi@01c06000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c06000 0x1000>;
+                        interrupts = <11>;
+                        clocks = <&ahb_gates 21>, <&spi1_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                usbphy: phy@01c13400 {
+                        #phy-cells = <1>;
+                        compatible = "allwinner,sun5i-a13-usb-phy";
+                        reg = <0x01c13400 0x10 0x01c14800 0x4>;
+                        reg-names = "phy_ctrl", "pmu1";
+                        clocks = <&usb_clk 8>;
+                        clock-names = "usb_phy";
+                        resets = <&usb_clk 1>;
+                        reset-names = "usb1_reset";
+                        status = "disabled";
+                };
+                ehci0: usb@01c14000 {
+                        compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
+                        reg = <0x01c14000 0x100>;
+                        interrupts = <39>;
+                        clocks = <&ahb_gates 1>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ohci0: usb@01c14400 {
+                        compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
+                        reg = <0x01c14400 0x100>;
+                        interrupts = <40>;
+                        clocks = <&usb_clk 6>, <&ahb_gates 2>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                spi2: spi@01c17000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c17000 0x1000>;
+                        interrupts = <12>;
+                        clocks = <&ahb_gates 22>, <&spi2_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
                intc: interrupt-controller@01c20400 {
                        compatible = "allwinner,sun4i-a10-ic";
                        reg = <0x01c20400 0x400>;
@@ -336,12 +425,12 @@
                };
                wdt: watchdog@01c20c90 {
-                        compatible = "allwinner,sun4i-wdt";
+                        compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                };
                sid: eeprom@01c23800 {
-                        compatible = "allwinner,sun4i-sid";
+                        compatible = "allwinner,sun4i-a10-sid";
                        reg = <0x01c23800 0x10>;
                };
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index e5adae30899b..3898a7bce831 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -28,5 +28,23 @@
                        pinctrl-0 = <&uart0_pins_a>;
                        status = "okay";
                };
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "fail";
+                };
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 38d43febda4c..d45efa74827c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -16,6 +16,16 @@
 / {
        interrupt-parent = <&gic>;
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -60,34 +70,32 @@
                        clock-frequency = <24000000>;
                };
-                osc32k: osc32k {
+                osc32k: clk@0 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <32768>;
+                        clock-output-names = "osc32k";
                };
-                pll1: pll1@01c20000 {
+                pll1: clk@01c20000 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun6i-a31-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
+                        clock-output-names = "pll1";
                };
-                /*
+                pll6: clk@01c20028 {
-                 * This is a dummy clock, to be used as placeholder on
-                 * other mux clocks when a specific parent clock is not
-                 * yet implemented. It should be dropped when the driver
-                 * is complete.
-                 */
-                pll6: pll6 {
                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
+                        compatible = "allwinner,sun6i-a31-pll6-clk";
-                        clock-frequency = <0>;
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6";
                };
                cpu: cpu@01c20050 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-cpu-clk";
+                        compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20050 0x4>;
                        /*
@@ -97,13 +105,15 @@
                         * Allwinner.
                         */
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+                        clock-output-names = "cpu";
                };
                axi: axi@01c20050 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-axi-clk";
+                        compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20050 0x4>;
                        clocks = <&cpu>;
+                        clock-output-names = "axi";
                };
                ahb1_mux: ahb1_mux@01c20054 {
@@ -111,16 +121,18 @@
                        compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+                        clock-output-names = "ahb1_mux";
                };
                ahb1: ahb1@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-ahb-clk";
+                        compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb1_mux>;
+                        clock-output-names = "ahb1";
                };
-                ahb1_gates: ahb1_gates@01c20060 {
+                ahb1_gates: clk@01c20060 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
                        reg = <0x01c20060 0x8>;
@@ -143,12 +155,13 @@
                apb1: apb1@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb0-clk";
+                        compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb1>;
+                        clock-output-names = "apb1";
                };
-                apb1_gates: apb1_gates@01c20060 {
+                apb1_gates: clk@01c20068 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun6i-a31-apb1-gates-clk";
                        reg = <0x01c20068 0x4>;
@@ -160,9 +173,10 @@
                apb2_mux: apb2_mux@01c20058 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                        clock-output-names = "apb2_mux";
                };
                apb2: apb2@01c20058 {
@@ -170,9 +184,10 @@
                        compatible = "allwinner,sun6i-a31-apb2-div-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb2_mux>;
+                        clock-output-names = "apb2";
                };
-                apb2_gates: apb2_gates@01c2006c {
+                apb2_gates: clk@01c2006c {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun6i-a31-apb2-gates-clk";
                        reg = <0x01c2006c 0x4>;
@@ -182,6 +197,38 @@
                                        "apb2_uart1", "apb2_uart2", "apb2_uart3",
                                        "apb2_uart4", "apb2_uart5";
                };
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "spi0";
+                };
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "spi1";
+                };
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "spi2";
+                };
+                spi3_clk: clk@01c200ac {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c200ac 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "spi3";
+                };
        };
        soc@01c00000 {
@@ -218,6 +265,27 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PH14", "PH15";
+                                allwinner,function = "i2c0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PH16", "PH17";
+                                allwinner,function = "i2c1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PH18", "PH19";
+                                allwinner,function = "i2c2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                };
                ahb1_rst: reset@01c202c0 {
@@ -250,7 +318,7 @@
                };
                wdt1: watchdog@01c20ca0 {
-                        compatible = "allwinner,sun6i-wdt";
+                        compatible = "allwinner,sun6i-a31-wdt";
                        reg = <0x01c20ca0 0x20>;
                };
@@ -320,6 +388,86 @@
                        status = "disabled";
                };
+                i2c0: i2c@01c2ac00 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <0 6 4>;
+                        clocks = <&apb2_gates 0>;
+                        clock-frequency = <100000>;
+                        resets = <&apb2_rst 0>;
+                        status = "disabled";
+                };
+                i2c1: i2c@01c2b000 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <0 7 4>;
+                        clocks = <&apb2_gates 1>;
+                        clock-frequency = <100000>;
+                        resets = <&apb2_rst 1>;
+                        status = "disabled";
+                };
+                i2c2: i2c@01c2b400 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2b400 0x400>;
+                        interrupts = <0 8 4>;
+                        clocks = <&apb2_gates 2>;
+                        clock-frequency = <100000>;
+                        resets = <&apb2_rst 2>;
+                        status = "disabled";
+                };
+                i2c3: i2c@01c2b800 {
+                        compatible = "allwinner,sun6i-a31-i2c";
+                        reg = <0x01c2b800 0x400>;
+                        interrupts = <0 9 4>;
+                        clocks = <&apb2_gates 3>;
+                        clock-frequency = <100000>;
+                        resets = <&apb2_rst 3>;
+                        status = "disabled";
+                };
+                spi0: spi@01c68000 {
+                        compatible = "allwinner,sun6i-a31-spi";
+                        reg = <0x01c68000 0x1000>;
+                        interrupts = <0 65 4>;
+                        clocks = <&ahb1_gates 20>, <&spi0_clk>;
+                        clock-names = "ahb", "mod";
+                        resets = <&ahb1_rst 20>;
+                        status = "disabled";
+                };
+                spi1: spi@01c69000 {
+                        compatible = "allwinner,sun6i-a31-spi";
+                        reg = <0x01c69000 0x1000>;
+                        interrupts = <0 66 4>;
+                        clocks = <&ahb1_gates 21>, <&spi1_clk>;
+                        clock-names = "ahb", "mod";
+                        resets = <&ahb1_rst 21>;
+                        status = "disabled";
+                };
+                spi2: spi@01c6a000 {
+                        compatible = "allwinner,sun6i-a31-spi";
+                        reg = <0x01c6a000 0x1000>;
+                        interrupts = <0 67 4>;
+                        clocks = <&ahb1_gates 22>, <&spi2_clk>;
+                        clock-names = "ahb", "mod";
+                        resets = <&ahb1_rst 22>;
+                        status = "disabled";
+                };
+                spi3: spi@01c6b000 {
+                        compatible = "allwinner,sun6i-a31-spi";
+                        reg = <0x01c6b000 0x1000>;
+                        interrupts = <0 68 4>;
+                        clocks = <&ahb1_gates 23>, <&spi3_clk>;
+                        clock-names = "ahb", "mod";
+                        resets = <&ahb1_rst 23>;
+                        status = "disabled";
+                };
                gic: interrupt-controller@01c81000 {
                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
                        reg = <0x01c81000 0x1000>,
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 5c51cb8a98b0..68de89ffbdfa 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -13,25 +13,38 @@
 /dts-v1/;
 /include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "Cubietech Cubieboard2";
        compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
        soc@01c00000 {
-                emac: ethernet@01c0b000 {
+                usbphy: phy@01c13400 {
-                        pinctrl-names = "default";
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
-                        pinctrl-0 = <&emac_pins_a>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
-                        phy = <&phy1>;
                        status = "okay";
                };
-                mdio@01c0b080 {
+                ehci0: usb@01c14000 {
                        status = "okay";
+                };
-                        phy1: ethernet-phy@1 {
+                ohci0: usb@01c14400 {
-                                reg = <1>;
+                        status = "okay";
-                        };
+                };
+                ahci: sata@01c18000 {
+                        target-supply = <&reg_ahci_5v>;
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
                };
                pinctrl@01c20800 {
@@ -60,6 +73,18 @@
                        pinctrl-0 = <&i2c1_pins_a>;
                        status = "okay";
                };
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_mii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "mii";
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
        };
        leds {
@@ -77,4 +102,16 @@
                        gpios = <&pio 7 20 0>;
                };
        };
+        reg_ahci_5v: ahci-5v {
+                status = "okay";
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f9dcb61a5305..cb25d3c8da58 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -13,13 +13,48 @@
 /dts-v1/;
 /include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "Cubietech Cubietruck";
        compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
        soc@01c00000 {
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ahci: sata@01c18000 {
+                        target-supply = <&reg_ahci_5v>;
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
                pinctrl@01c20800 {
+                        ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
+                                allwinner,pins = "PH12";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                        led_pins_cubietruck: led_pins@0 {
                                allwinner,pins = "PH7", "PH11", "PH20", "PH21";
                                allwinner,function = "gpio_out";
@@ -51,6 +86,18 @@
                        pinctrl-0 = <&i2c2_pins_a>;
                        status = "okay";
                };
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_rgmii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "rgmii";
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
        };
        leds {
@@ -78,4 +125,18 @@
                        gpios = <&pio 7 7 0>;
                };
        };
+        reg_ahci_5v: ahci-5v {
+                pinctrl-0 = <&ahci_pwr_pin_cubietruck>;
+                gpio = <&pio 7 12 0>;
+                status = "okay";
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index ead3013f9aca..eeadf76362fa 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -13,25 +13,55 @@
 /dts-v1/;
 /include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "Olimex A20-Olinuxino Micro";
        compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
+        aliases {
+                spi0 = &spi1;
+                spi1 = &spi2;
+        };
        soc@01c00000 {
-                emac: ethernet@01c0b000 {
+                spi1: spi@01c06000 {
                        pinctrl-names = "default";
-                        pinctrl-0 = <&emac_pins_a>;
+                        pinctrl-0 = <&spi1_pins_a>;
-                        phy = <&phy1>;
                        status = "okay";
                };
-                mdio@01c0b080 {
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
                        status = "okay";
+                };
-                        phy1: ethernet-phy@1 {
+                ehci0: usb@01c14000 {
-                                reg = <1>;
+                        status = "okay";
-                        };
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                spi2: spi@01c17000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi2_pins_a>;
+                        status = "okay";
+                };
+                ahci: sata@01c18000 {
+                        target-supply = <&reg_ahci_5v>;
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
                };
                pinctrl@01c20800 {
@@ -78,6 +108,18 @@
                        pinctrl-0 = <&i2c2_pins_a>;
                        status = "okay";
                };
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_mii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "mii";
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
        };
        leds {
@@ -91,4 +133,16 @@
                        default-state = "on";
                };
        };
+        reg_ahci_5v: ahci-5v {
+                status = "okay";
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index cadcf2f9881d..32efc105df83 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -17,7 +17,15 @@
        interrupt-parent = <&gic>;
        aliases {
-                ethernet0 = &emac;
+                ethernet0 = &gmac;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                serial6 = &uart6;
+                serial7 = &uart7;
        };
        cpus {
@@ -41,16 +49,25 @@
                reg = <0x40000000 0x80000000>;
        };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
-                osc24M: osc24M@01c20050 {
+                osc24M: clk@01c20050 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-osc-clk";
+                        compatible = "allwinner,sun4i-a10-osc-clk";
                        reg = <0x01c20050 0x4>;
                        clock-frequency = <24000000>;
+                        clock-output-names = "osc24M";
                };
                osc32k: clk@0 {
@@ -60,31 +77,33 @@
                        clock-output-names = "osc32k";
                };
-                pll1: pll1@01c20000 {
+                pll1: clk@01c20000 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-pll1-clk";
+                        compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20000 0x4>;
                        clocks = <&osc24M>;
+                        clock-output-names = "pll1";
                };
-                pll4: pll4@01c20018 {
+                pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-pll1-clk";
+                        compatible = "allwinner,sun4i-a10-pll1-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
+                        clock-output-names = "pll4";
                };
-                pll5: pll5@01c20020 {
+                pll5: clk@01c20020 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-pll5-clk";
+                        compatible = "allwinner,sun4i-a10-pll5-clk";
                        reg = <0x01c20020 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll5_ddr", "pll5_other";
                };
-                pll6: pll6@01c20028 {
+                pll6: clk@01c20028 {
                        #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-pll6-clk";
+                        compatible = "allwinner,sun4i-a10-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -92,26 +111,29 @@
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-cpu-clk";
+                        compatible = "allwinner,sun4i-a10-cpu-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
+                        clock-output-names = "cpu";
                };
                axi: axi@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-axi-clk";
+                        compatible = "allwinner,sun4i-a10-axi-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&cpu>;
+                        clock-output-names = "axi";
                };
                ahb: ahb@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-ahb-clk";
+                        compatible = "allwinner,sun4i-a10-ahb-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&axi>;
+                        clock-output-names = "ahb";
                };
-                ahb_gates: ahb_gates@01c20060 {
+                ahb_gates: clk@01c20060 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun7i-a20-ahb-gates-clk";
                        reg = <0x01c20060 0x8>;
@@ -133,12 +155,13 @@
                apb0: apb0@01c20054 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb0-clk";
+                        compatible = "allwinner,sun4i-a10-apb0-clk";
                        reg = <0x01c20054 0x4>;
                        clocks = <&ahb>;
+                        clock-output-names = "apb0";
                };
-                apb0_gates: apb0_gates@01c20068 {
+                apb0_gates: clk@01c20068 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun7i-a20-apb0-gates-clk";
                        reg = <0x01c20068 0x4>;
@@ -151,19 +174,21 @@
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+                        clock-output-names = "apb1_mux";
                };
                apb1: apb1@01c20058 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-apb1-clk";
+                        compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
                        clocks = <&apb1_mux>;
+                        clock-output-names = "apb1";
                };
-                apb1_gates: apb1_gates@01c2006c {
+                apb1_gates: clk@01c2006c {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun7i-a20-apb1-gates-clk";
                        reg = <0x01c2006c 0x4>;
@@ -178,7 +203,7 @@
                nand_clk: clk@01c20080 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20080 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "nand";
@@ -186,7 +211,7 @@
                ms_clk: clk@01c20084 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20084 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ms";
@@ -194,7 +219,7 @@
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
@@ -202,7 +227,7 @@
                mmc1_clk: clk@01c2008c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
@@ -210,7 +235,7 @@
                mmc2_clk: clk@01c20090 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
@@ -218,7 +243,7 @@
                mmc3_clk: clk@01c20094 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20094 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc3";
@@ -226,7 +251,7 @@
                ts_clk: clk@01c20098 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20098 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ts";
@@ -234,7 +259,7 @@
                ss_clk: clk@01c2009c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2009c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ss";
@@ -242,7 +267,7 @@
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi0";
@@ -250,7 +275,7 @@
                spi1_clk: clk@01c200a4 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi1";
@@ -258,7 +283,7 @@
                spi2_clk: clk@01c200a8 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi2";
@@ -266,7 +291,7 @@
                pata_clk: clk@01c200ac {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200ac 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "pata";
@@ -274,7 +299,7 @@
                ir0_clk: clk@01c200b0 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b0 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir0";
@@ -282,15 +307,24 @@
                ir1_clk: clk@01c200b4 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200b4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "ir1";
                };
+                usb_clk: clk@01c200cc {
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-usb-clk";
+                        reg = <0x01c200cc 0x4>;
+                        clocks = <&pll6 1>;
+                        clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+                };
                spi3_clk: clk@01c200d4 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200d4 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "spi3";
@@ -298,13 +332,41 @@
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-mod0-clk";
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2015c 0x4>;
                        clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
                        clock-output-names = "mbus";
                };
                /*
+                 * The following two are dummy clocks, placeholders used in the gmac_tx
+                 * clock. The gmac driver will choose one parent depending on the PHY
+                 * interface mode, using clk_set_rate auto-reparenting.
+                 * The actual TX clock rate is not controlled by the gmac_tx clock.
+                 */
+                mii_phy_tx_clk: clk@2 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <25000000>;
+                        clock-output-names = "mii_phy_tx";
+                };
+                gmac_int_tx_clk: clk@3 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <125000000>;
+                        clock-output-names = "gmac_int_tx";
+                };
+                gmac_tx_clk: clk@01c20164 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun7i-a20-gmac-clk";
+                        reg = <0x01c20164 0x4>;
+                        clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+                        clock-output-names = "gmac_tx";
+                };
+                /*
                 * Dummy clock used by output clocks
                 */
                osc24M_32k: clk@1 {
@@ -347,6 +409,28 @@
                        interrupts = <0 0 4>;
                };
+                spi0: spi@01c05000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c05000 0x1000>;
+                        interrupts = <0 10 4>;
+                        clocks = <&ahb_gates 20>, <&spi0_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                spi1: spi@01c06000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c06000 0x1000>;
+                        interrupts = <0 11 4>;
+                        clocks = <&ahb_gates 21>, <&spi1_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
                emac: ethernet@01c0b000 {
                        compatible = "allwinner,sun4i-a10-emac";
                        reg = <0x01c0b000 0x1000>;
@@ -363,6 +447,88 @@
                        #size-cells = <0>;
                };
+                usbphy: phy@01c13400 {
+                        #phy-cells = <1>;
+                        compatible = "allwinner,sun7i-a20-usb-phy";
+                        reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+                        reg-names = "phy_ctrl", "pmu1", "pmu2";
+                        clocks = <&usb_clk 8>;
+                        clock-names = "usb_phy";
+                        resets = <&usb_clk 1>, <&usb_clk 2>;
+                        reset-names = "usb1_reset", "usb2_reset";
+                        status = "disabled";
+                };
+                ehci0: usb@01c14000 {
+                        compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+                        reg = <0x01c14000 0x100>;
+                        interrupts = <0 39 4>;
+                        clocks = <&ahb_gates 1>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ohci0: usb@01c14400 {
+                        compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+                        reg = <0x01c14400 0x100>;
+                        interrupts = <0 64 4>;
+                        clocks = <&usb_clk 6>, <&ahb_gates 2>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                spi2: spi@01c17000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c17000 0x1000>;
+                        interrupts = <0 12 4>;
+                        clocks = <&ahb_gates 22>, <&spi2_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+                ahci: sata@01c18000 {
+                        compatible = "allwinner,sun4i-a10-ahci";
+                        reg = <0x01c18000 0x1000>;
+                        interrupts = <0 56 4>;
+                        clocks = <&pll6 0>, <&ahb_gates 25>;
+                        status = "disabled";
+                };
+                ehci1: usb@01c1c000 {
+                        compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+                        reg = <0x01c1c000 0x100>;
+                        interrupts = <0 40 4>;
+                        clocks = <&ahb_gates 3>;
+                        phys = <&usbphy 2>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ohci1: usb@01c1c400 {
+                        compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+                        reg = <0x01c1c400 0x100>;
+                        interrupts = <0 65 4>;
+                        clocks = <&usb_clk 7>, <&ahb_gates 4>;
+                        phys = <&usbphy 2>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                spi3: spi@01c1f000 {
+                        compatible = "allwinner,sun4i-a10-spi";
+                        reg = <0x01c1f000 0x1000>;
+                        interrupts = <0 50 4>;
+                        clocks = <&ahb_gates 23>, <&spi3_clk>;
+                        clock-names = "ahb", "mod";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
                pio: pinctrl@01c20800 {
                        compatible = "allwinner,sun7i-a20-pinctrl";
                        reg = <0x01c20800 0x400>;
@@ -381,6 +547,13 @@
                                allwinner,pull = <0>;
                        };
+                        uart2_pins_a: uart2@0 {
+                                allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+                                allwinner,function = "uart2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                        uart6_pins_a: uart6@0 {
                                allwinner,pins = "PI12", "PI13";
                                allwinner,function = "uart6";
@@ -440,6 +613,46 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        gmac_pins_mii_a: gmac_mii@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA9", "PA10",
+                                                "PA11", "PA12", "PA13", "PA14",
+                                                "PA15", "PA16";
+                                allwinner,function = "gmac";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        gmac_pins_rgmii_a: gmac_rgmii@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA10",
+                                                "PA11", "PA12", "PA13",
+                                                "PA15", "PA16";
+                                allwinner,function = "gmac";
+                                /*
+                                 * data lines in RGMII mode use DDR mode
+                                 * and need a higher signal drive strength
+                                 */
+                                allwinner,drive = <3>;
+                                allwinner,pull = <0>;
+                        };
+                        spi1_pins_a: spi1@0 {
+                                allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+                                allwinner,function = "spi1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        spi2_pins_a: spi2@0 {
+                                allwinner,pins = "PC19", "PC20", "PC21", "PC22";
+                                allwinner,function = "spi2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                };
                timer@01c20c00 {
@@ -455,7 +668,7 @@
                };
                wdt: watchdog@01c20c90 {
-                        compatible = "allwinner,sun4i-wdt";
+                        compatible = "allwinner,sun4i-a10-wdt";
                        reg = <0x01c20c90 0x10>;
                };
@@ -601,6 +814,21 @@
                        status = "disabled";
                };
+                gmac: ethernet@01c50000 {
+                        compatible = "allwinner,sun7i-a20-gmac";
+                        reg = <0x01c50000 0x10000>;
+                        interrupts = <0 85 4>;
+                        interrupt-names = "macirq";
+                        clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
+                        clock-names = "stmmaceth", "allwinner_gmac_tx";
+                        snps,pbl = <2>;
+                        snps,fixed-burst;
+                        snps,force_sf_dma_mode;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
                hstimer@01c60000 {
                        compatible = "allwinner,sun7i-a20-hstimer";
                        reg = <0x01c60000 0x1000>;
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
new file mode 100644
index 000000000000..18eeac0670b9
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -0,0 +1,75 @@
+/*
+ * sunxi boards common regulator (ahci target power supply, usb-vbus) code
+ *
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/ {
+        soc@01c00000 {
+                pio: pinctrl@01c20800 {
+                        ahci_pwr_pin_a: ahci_pwr_pin@0 {
+                                allwinner,pins = "PB8";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        usb1_vbus_pin_a: usb1_vbus_pin@0 {
+                                allwinner,pins = "PH6";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        usb2_vbus_pin_a: usb2_vbus_pin@0 {
+                                allwinner,pins = "PH3";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+        };
+        reg_ahci_5v: ahci-5v {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&ahci_pwr_pin_a>;
+                regulator-name = "ahci-5v";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&pio 1 8 0>;
+                status = "disabled";
+        };
+        reg_usb1_vbus: usb1-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb1_vbus_pin_a>;
+                regulator-name = "usb1-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&pio 7 6 0>;
+                status = "disabled";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb2_vbus_pin_a>;
+                regulator-name = "usb2-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&pio 7 3 0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 73aecfb57ccb..a288a12823ed 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,3 +1,8 @@
+/*
+ * This dts file supports Dalmore A04.
+ * Other board revisions are not supported
+ */
 /dts-v1/;
 #include <dt-bindings/input/input.h>
@@ -715,7 +720,6 @@
                                nvidia,pins = "drive_sdio1";
                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                nvidia,pull-down-strength = <36>;
                                nvidia,pull-up-strength = <20>;
                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
@@ -725,7 +729,6 @@
                                nvidia,pins = "drive_sdio3";
                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                nvidia,pull-down-strength = <22>;
                                nvidia,pull-up-strength = <36>;
                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
@@ -735,12 +738,10 @@
                                nvidia,pins = "drive_gma";
                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                nvidia,pull-down-strength = <2>;
                                nvidia,pull-up-strength = <1>;
                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
-                                nvidia,drive-type = <1>;
                        };
                };
        };
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 44ec401ec366..fdc559ab2db3 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -604,7 +604,7 @@
                clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
                resets = <&tegra_car 14>;
                reset-names = "sdhci";
-                status = "disable";
+                status = "disabled";
        };
        sdhci@78000200 {
@@ -614,7 +614,7 @@
                clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
                resets = <&tegra_car 9>;
                reset-names = "sdhci";
-                status = "disable";
+                status = "disabled";
        };
        sdhci@78000400 {
@@ -624,7 +624,7 @@
                clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
                resets = <&tegra_car 69>;
                reset-names = "sdhci";
-                status = "disable";
+                status = "disabled";
        };
        sdhci@78000600 {
@@ -634,7 +634,7 @@
                clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
                resets = <&tegra_car 15>;
                reset-names = "sdhci";
-                status = "disable";
+                status = "disabled";
        };
        usb@7d000000 {
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index c6dcef513e5d..c17283c04598 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -8,15 +8,29 @@
        compatible = "nvidia,venice2", "nvidia,tegra124";
        aliases {
-                rtc0 = "/i2c@7000d000/as3722@40";
+                rtc0 = "/i2c@0,7000d000/pmic@40";
-                rtc1 = "/rtc@7000e000";
+                rtc1 = "/rtc@0,7000e000";
        };
        memory {
-                reg = <0x80000000 0x80000000>;
+                reg = <0x0 0x80000000 0x0 0x80000000>;
        };
-        pinmux: pinmux@70000868 {
+        host1x@0,50000000 {
+                sor@0,54540000 {
+                        status = "okay";
+                        nvidia,dpaux = <&dpaux>;
+                        nvidia,panel = <&panel>;
+                };
+                dpaux: dpaux@0,545c0000 {
+                        vdd-supply = <&vdd_3v3_panel>;
+                        status = "okay";
+                };
+        };
+        pinmux: pinmux@0,70000868 {
                pinctrl-names = "default";
                pinctrl-0 = <&pinmux_default>;
@@ -138,14 +152,9 @@
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        sdmmc1_clk_pz0 {
-                                nvidia,pins = "sdmmc1_clk_pz0",
+                                nvidia,pins = "sdmmc1_clk_pz0";
-                                              "sdmmc1_cmd_pz1",
-                                              "sdmmc1_dat0_py7",
-                                              "sdmmc1_dat1_py6",
-                                              "sdmmc1_dat2_py5",
-                                              "sdmmc1_dat3_py4";
                                nvidia,function = "sdmmc1";
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                        };
@@ -402,19 +411,11 @@
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };
                        usb_vbus_en0_pn4 {
-                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,pins = "usb_vbus_en0_pn4",
+                                              "usb_vbus_en1_pn5";
                                nvidia,function = "usb";
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
-                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-                        };
-                        usb_vbus_en1_pn5 {
-                                nvidia,pins = "usb_vbus_en1_pn5";
-                                nvidia,function = "usb";
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,lock = <TEGRA_PIN_DISABLE>;
                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
@@ -423,7 +424,6 @@
                                nvidia,pins = "drive_sdio1";
                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                nvidia,pull-down-strength = <32>;
                                nvidia,pull-up-strength = <42>;
                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
@@ -433,7 +433,6 @@
                                nvidia,pins = "drive_sdio3";
                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
-                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                nvidia,pull-down-strength = <20>;
                                nvidia,pull-up-strength = <36>;
                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
@@ -572,15 +571,15 @@
                };
        };
-        serial@70006000 {
+        serial@0,70006000 {
                status = "okay";
        };
-        pwm: pwm@7000a000 {
+        pwm: pwm@0,7000a000 {
                status = "okay";
        };
-        i2c@7000c000 {
+        i2c@0,7000c000 {
                status = "okay";
                clock-frequency = <100000>;
@@ -592,30 +591,32 @@
                };
        };
-        i2c@7000c400 {
+        i2c@0,7000c400 {
                status = "okay";
                clock-frequency = <100000>;
        };
-        i2c@7000c500 {
+        i2c@0,7000c500 {
                status = "okay";
                clock-frequency = <100000>;
        };
-        i2c@7000c700 {
+        i2c@0,7000c700 {
                status = "okay";
                clock-frequency = <100000>;
        };
-        i2c@7000d000 {
+        i2c@0,7000d000 {
                status = "okay";
                clock-frequency = <400000>;
-                as3722: as3722@40 {
+                pmic: pmic@40 {
                        compatible = "ams,as3722";
                        reg = <0x40>;
                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+                        ams,system-power-controller;
                        #interrupt-cells = <2>;
                        interrupt-controller;
@@ -650,19 +651,19 @@
                        };
                        regulators {
-                                vsup-sd2-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd2-supply = <&vdd_5v0_sys>;
-                                vsup-sd3-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd3-supply = <&vdd_5v0_sys>;
-                                vsup-sd4-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd4-supply = <&vdd_5v0_sys>;
-                                vsup-sd5-supply = <&vdd_ac_bat_reg>;
+                                vsup-sd5-supply = <&vdd_5v0_sys>;
-                                vin-ldo0-supply = <&as3722_sd2>;
+                                vin-ldo0-supply = <&vdd_1v35_lp0>;
-                                vin-ldo1-6-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo1-6-supply = <&vdd_3v3_run>;
-                                vin-ldo2-5-7-supply = <&as3722_sd5>;
+                                vin-ldo2-5-7-supply = <&vddio_1v8>;
-                                vin-ldo3-4-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo3-4-supply = <&vdd_3v3_sys>;
-                                vin-ldo9-10-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo9-10-supply = <&vdd_5v0_sys>;
-                                vin-ldo11-supply = <&vdd_ac_bat_reg>;
+                                vin-ldo11-supply = <&vdd_3v3_run>;
                                sd0 {
-                                        regulator-name = "vdd-cpu";
+                                        regulator-name = "+VDD_CPU_AP";
                                        regulator-min-microvolt = <700000>;
                                        regulator-max-microvolt = <1400000>;
                                        regulator-min-microamp = <3500000>;
@@ -673,7 +674,7 @@
                                };
                                sd1 {
-                                        regulator-name = "vdd-core";
+                                        regulator-name = "+VDD_CORE";
                                        regulator-min-microvolt = <700000>;
                                        regulator-max-microvolt = <1350000>;
                                        regulator-min-microamp = <2500000>;
@@ -683,8 +684,8 @@
                                        ams,external-control = <1>;
                                };
-                                as3722_sd2: sd2 {
+                                vdd_1v35_lp0: sd2 {
-                                        regulator-name = "vddio-ddr";
+                                        regulator-name = "+1.35V_LP0(sd2)";
                                        regulator-min-microvolt = <1350000>;
                                        regulator-max-microvolt = <1350000>;
                                        regulator-always-on;
@@ -692,7 +693,7 @@
                                };
                                sd3 {
-                                        regulator-name = "vddio-ddr-2phase";
+                                        regulator-name = "+1.35V_LP0(sd3)";
                                        regulator-min-microvolt = <1350000>;
                                        regulator-max-microvolt = <1350000>;
                                        regulator-always-on;
@@ -700,15 +701,13 @@
                                };
                                sd4 {
-                                        regulator-name = "avdd-pex-sata";
+                                        regulator-name = "+1.05V_RUN";
                                        regulator-min-microvolt = <1050000>;
                                        regulator-max-microvolt = <1050000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
                                };
-                                as3722_sd5: sd5 {
+                                vddio_1v8: sd5 {
-                                        regulator-name = "vddio-sys";
+                                        regulator-name = "+1.8V_VDDIO";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                        regulator-boot-on;
@@ -716,7 +715,7 @@
                                };
                                sd6 {
-                                        regulator-name = "vdd-gpu";
+                                        regulator-name = "+VDD_GPU_AP";
                                        regulator-min-microvolt = <650000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-min-microamp = <3500000>;
@@ -726,7 +725,7 @@
                                };
                                ldo0 {
-                                        regulator-name = "avdd_pll";
+                                        regulator-name = "+1.05V_RUN_AVDD";
                                        regulator-min-microvolt = <1050000>;
                                        regulator-max-microvolt = <1050000>;
                                        regulator-boot-on;
@@ -735,13 +734,13 @@
                                };
                                ldo1 {
-                                        regulator-name = "run-cam-1.8";
+                                        regulator-name = "+1.8V_RUN_CAM";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
                                ldo2 {
-                                        regulator-name = "gen-avdd,vddio-hsic";
+                                        regulator-name = "+1.2V_GEN_AVDD";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                        regulator-boot-on;
@@ -749,7 +748,7 @@
                                };
                                ldo3 {
-                                        regulator-name = "vdd-rtc";
+                                        regulator-name = "+1.00V_LP0_VDD_RTC";
                                        regulator-min-microvolt = <1000000>;
                                        regulator-max-microvolt = <1000000>;
                                        regulator-boot-on;
@@ -757,48 +756,44 @@
                                        ams,enable-tracking;
                                };
-                                ldo4 {
+                                vdd_run_cam: ldo4 {
-                                        regulator-name = "vdd-cam";
+                                        regulator-name = "+3.3V_RUN_CAM";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
                                };
                                ldo5 {
-                                        regulator-name = "vdd-cam-front";
+                                        regulator-name = "+1.2V_RUN_CAM_FRONT";
                                        regulator-min-microvolt = <1200000>;
                                        regulator-max-microvolt = <1200000>;
                                };
-                                ldo6 {
+                                vddio_sdmmc3: ldo6 {
-                                        regulator-name = "vddio-sdmmc3";
+                                        regulator-name = "+VDDIO_SDMMC3";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <3300000>;
-                                        regulator-boot-on;
-                                        regulator-always-on;
                                };
                                ldo7 {
-                                        regulator-name = "vdd-cam-rear";
+                                        regulator-name = "+1.05V_RUN_CAM_REAR";
                                        regulator-min-microvolt = <1050000>;
                                        regulator-max-microvolt = <1050000>;
                                };
                                ldo9 {
-                                        regulator-name = "vdd-touch";
+                                        regulator-name = "+2.8V_RUN_TOUCH";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
                                };
                                ldo10 {
-                                        regulator-name = "vdd-cam-af";
+                                        regulator-name = "+2.8V_RUN_CAM_AF";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <2800000>;
                                };
                                ldo11 {
-                                        regulator-name = "vpp-fuse";
+                                        regulator-name = "+1.8V_RUN_VPP_FUSE";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
                                };
@@ -806,7 +801,7 @@
                };
        };
-        spi@7000d400 {
+        spi@0,7000d400 {
                status = "okay";
                cros-ec@0 {
@@ -912,7 +907,17 @@
                };
        };
-        pmc@7000e400 {
+        spi@0,7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+                spi-flash@0 {
+                        compatible = "winbond,w25q32dw";
+                        reg = <0>;
+                        spi-max-frequency = <20000000>;
+                };
+        };
+        pmc@0,7000e400 {
                nvidia,invert-interrupt;
                nvidia,suspend-mode = <1>;
                nvidia,cpu-pwr-good-time = <500>;
@@ -923,24 +928,63 @@
                nvidia,sys-clock-req-active-high;
        };
-        sdhci@700b0400 {
+        sdhci@0,700b0400 {
                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
                status = "okay";
                bus-width = <4>;
+                vmmc-supply = <&vddio_sdmmc3>;
        };
-        sdhci@700b0600 {
+        sdhci@0,700b0600 {
                status = "okay";
                bus-width = <8>;
        };
-        ahub@70300000 {
+        ahub@0,70300000 {
-                i2s@70301100 {
+                i2s@0,70301100 {
                        status = "okay";
                };
        };
+        usb@0,7d000000 {
+                status = "okay";
+        };
+        usb-phy@0,7d000000 {
+                status = "okay";
+                vbus-supply = <&vdd_usb1_vbus>;
+        };
+        usb@0,7d004000 {
+                status = "okay";
+        };
+        usb-phy@0,7d004000 {
+                status = "okay";
+                vbus-supply = <&vdd_run_cam>;
+        };
+        usb@0,7d008000 {
+                status = "okay";
+        };
+        usb-phy@0,7d008000 {
+                status = "okay";
+                vbus-supply = <&vdd_usb3_vbus>;
+        };
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_led>;
+                pwms = <&pwm 1 1000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
        clocks {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -948,7 +992,7 @@
                clk32k_in: clock@0 {
                        compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                        #clock-cells = <0>;
                        clock-frequency = <32768>;
                };
@@ -966,104 +1010,140 @@
                };
        };
+        panel: panel {
+                compatible = "lg,lp129qe", "simple-panel";
+                backlight = <&backlight>;
+                ddc-i2c-bus = <&dpaux>;
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <0>;
-                vdd_ac_bat_reg: regulator@0 {
+                vdd_mux: regulator@0 {
                        compatible = "regulator-fixed";
                        reg = <0>;
-                        regulator-name = "vdd_ac_bat";
+                        regulator-name = "+VDD_MUX";
-                        regulator-min-microvolt = <5000000>;
+                        regulator-min-microvolt = <12000000>;
-                        regulator-max-microvolt = <5000000>;
+                        regulator-max-microvolt = <12000000>;
                        regulator-always-on;
+                        regulator-boot-on;
                };
-                vdd_3v3_reg: regulator@1 {
+                vdd_5v0_sys: regulator@1 {
                        compatible = "regulator-fixed";
                        reg = <1>;
-                        regulator-name = "vdd_3v3";
+                        regulator-name = "+5V_SYS";
-                        regulator-min-microvolt = <3300000>;
+                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <3300000>;
+                        regulator-max-microvolt = <5000000>;
                        regulator-always-on;
                        regulator-boot-on;
-                        enable-active-high;
+                        vin-supply = <&vdd_mux>;
-                        gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
                };
-                vdd_3v3_modem_reg: regulator@2 {
+                vdd_3v3_sys: regulator@2 {
                        compatible = "regulator-fixed";
                        reg = <2>;
-                        regulator-name = "vdd-modem-3v3";
+                        regulator-name = "+3.3V_SYS";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
-                        enable-active-high;
+                        regulator-always-on;
-                        gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
+                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
                };
-                vdd_hdmi_5v0_reg: regulator@3 {
+                vdd_3v3_run: regulator@3 {
                        compatible = "regulator-fixed";
                        reg = <3>;
-                        regulator-name = "vdd-hdmi-5v0";
+                        regulator-name = "+3.3V_RUN";
-                        regulator-min-microvolt = <5000000>;
+                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <5000000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                        enable-active-high;
-                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+                        vin-supply = <&vdd_3v3_sys>;
                };
-                vdd_bl_reg: regulator@4 {
+                vdd_3v3_hdmi: regulator@4 {
                        compatible = "regulator-fixed";
                        reg = <4>;
-                        regulator-name = "vdd-bl";
+                        regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
-                        gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>;
+                        vin-supply = <&vdd_3v3_run>;
                };
-                vdd_ts_sw_5v0: regulator@5 {
+                vdd_led: regulator@5 {
                        compatible = "regulator-fixed";
                        reg = <5>;
-                        regulator-name = "vdd_ts_sw";
+                        regulator-name = "+VDD_LED";
-                        regulator-min-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
-                        regulator-max-microvolt = <5000000>;
                        enable-active-high;
-                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
-                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>;
                };
-                usb1_vbus_reg: regulator@6 {
+                vdd_5v0_ts: regulator@6 {
                        compatible = "regulator-fixed";
                        reg = <6>;
-                        regulator-name = "usb1_vbus";
+                        regulator-name = "+5V_VDD_TS_SW";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        regulator-boot-on;
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
                        enable-active-high;
-                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+                        vin-supply = <&vdd_5v0_sys>;
-                        gpio-open-drain;
                };
-                usb3_vbus_reg: regulator@7 {
+                vdd_usb1_vbus: regulator@7 {
                        compatible = "regulator-fixed";
                        reg = <7>;
-                        regulator-name = "usb3_vbus";
+                        regulator-name = "+5V_USB_HS";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
-                        regulator-boot-on;
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
                        enable-active-high;
-                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
                };
-                panel_3v3_reg: regulator@8 {
+                vdd_usb3_vbus: regulator@8 {
                        compatible = "regulator-fixed";
                        reg = <8>;
-                        regulator-name = "panel_3v3";
+                        regulator-name = "+5V_USB_SS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+                vdd_3v3_panel: regulator@9 {
+                        compatible = "regulator-fixed";
+                        reg = <9>;
+                        regulator-name = "+3.3V_PANEL";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_run>;
+                };
+                vdd_3v3_lp0: regulator@10 {
+                        compatible = "regulator-fixed";
+                        reg = <10>;
+                        regulator-name = "+3.3V_LP0";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
+                        /*
+                         * TODO: find a way to wire this up with the USB EHCI
+                         * controllers so that it can be enabled on demand.
+                         */
+                        regulator-always-on;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
                        enable-active-high;
-                        gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
+                        vin-supply = <&vdd_3v3_sys>;
                };
        };
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index ec0698a8354a..cf45a1a39483 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -8,22 +8,91 @@
 / {
        compatible = "nvidia,tegra124";
        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        host1x@0,50000000 {
+                compatible = "nvidia,tegra124-host1x", "simple-bus";
+                reg = <0x0 0x50000000 0x0 0x00034000>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+                clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
+                resets = <&tegra_car 28>;
+                reset-names = "host1x";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
+                dc@0,54200000 {
+                        compatible = "nvidia,tegra124-dc";
+                        reg = <0x0 0x54200000 0x0 0x00040000>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA124_CLK_DISP1>,
+                                 <&tegra_car TEGRA124_CLK_PLL_P>;
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 27>;
+                        reset-names = "dc";
+                        nvidia,head = <0>;
+                };
+                dc@0,54240000 {
+                        compatible = "nvidia,tegra124-dc";
+                        reg = <0x0 0x54240000 0x0 0x00040000>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA124_CLK_DISP2>,
+                                 <&tegra_car TEGRA124_CLK_PLL_P>;
+                        clock-names = "dc", "parent";
+                        resets = <&tegra_car 26>;
+                        reset-names = "dc";
+                        nvidia,head = <1>;
+                };
-        gic: interrupt-controller@50041000 {
+                sor@0,54540000 {
+                        compatible = "nvidia,tegra124-sor";
+                        reg = <0x0 0x54540000 0x0 0x00040000>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA124_CLK_SOR0>,
+                                 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
+                                 <&tegra_car TEGRA124_CLK_PLL_DP>,
+                                 <&tegra_car TEGRA124_CLK_CLK_M>;
+                        clock-names = "sor", "parent", "dp", "safe";
+                        resets = <&tegra_car 182>;
+                        reset-names = "sor";
+                        status = "disabled";
+                };
+                dpaux@0,545c0000 {
+                        compatible = "nvidia,tegra124-dpaux";
+                        reg = <0x0 0x545c0000 0x0 0x00040000>;
+                        interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
+                                 <&tegra_car TEGRA124_CLK_PLL_DP>;
+                        clock-names = "dpaux", "parent";
+                        resets = <&tegra_car 181>;
+                        reset-names = "dpaux";
+                        status = "disabled";
+                };
+        };
+        gic: interrupt-controller@0,50041000 {
                compatible = "arm,cortex-a15-gic";
                #interrupt-cells = <3>;
                interrupt-controller;
-                reg = <0x50041000 0x1000>,
+                reg = <0x0 0x50041000 0x0 0x1000>,
-                      <0x50042000 0x1000>,
+                      <0x0 0x50042000 0x0 0x1000>,
-                      <0x50044000 0x2000>,
+                      <0x0 0x50044000 0x0 0x2000>,
-                      <0x50046000 0x2000>;
+                      <0x0 0x50046000 0x0 0x2000>;
                interrupts = <GIC_PPI 9
                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
        };
-        timer@60005000 {
+        timer@0,60005000 {
                compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
-                reg = <0x60005000 0x400>;
+                reg = <0x0 0x60005000 0x0 0x400>;
                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -33,16 +102,16 @@
                clocks = <&tegra_car TEGRA124_CLK_TIMER>;
        };
-        tegra_car: clock@60006000 {
+        tegra_car: clock@0,60006000 {
                compatible = "nvidia,tegra124-car";
-                reg = <0x60006000 0x1000>;
+                reg = <0x0 0x60006000 0x0 0x1000>;
                #clock-cells = <1>;
                #reset-cells = <1>;
        };
-        gpio: gpio@6000d000 {
+        gpio: gpio@0,6000d000 {
                compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
-                reg = <0x6000d000 0x1000>;
+                reg = <0x0 0x6000d000 0x0 0x1000>;
                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
@@ -57,9 +126,9 @@
                interrupt-controller;
        };
-        apbdma: dma@60020000 {
+        apbdma: dma@0,60020000 {
                compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
-                reg = <0x60020000 0x1400>;
+                reg = <0x0 0x60020000 0x0 0x1400>;
                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
@@ -98,10 +167,10 @@
                #dma-cells = <1>;
        };
-        pinmux: pinmux@70000868 {
+        pinmux: pinmux@0,70000868 {
                compatible = "nvidia,tegra124-pinmux";
-                reg = <0x70000868 0x164>,       /* Pad control registers */
+                reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
-                      <0x70003000 0x434>;       /* Mux registers */
+                      <0x0 0x70003000 0x0 0x434>; /* Mux registers */
        };
        /*
@@ -112,9 +181,9 @@
         * the APB DMA based serial driver, the comptible is
         * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
         */
-        serial@70006000 {
+        serial@0,70006000 {
                compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
-                reg = <0x70006000 0x40>;
+                reg = <0x0 0x70006000 0x0 0x40>;
                reg-shift = <2>;
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_UARTA>;
@@ -125,9 +194,9 @@
                status = "disabled";
        };
-        serial@70006040 {
+        serial@0,70006040 {
                compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
-                reg = <0x70006040 0x40>;
+                reg = <0x0 0x70006040 0x0 0x40>;
                reg-shift = <2>;
                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_UARTB>;
@@ -138,9 +207,9 @@
                status = "disabled";
        };
-        serial@70006200 {
+        serial@0,70006200 {
                compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
-                reg = <0x70006200 0x40>;
+                reg = <0x0 0x70006200 0x0 0x40>;
                reg-shift = <2>;
                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_UARTC>;
@@ -151,9 +220,9 @@
                status = "disabled";
        };
-        serial@70006300 {
+        serial@0,70006300 {
                compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
-                reg = <0x70006300 0x40>;
+                reg = <0x0 0x70006300 0x0 0x40>;
                reg-shift = <2>;
                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_UARTD>;
@@ -164,9 +233,9 @@
                status = "disabled";
        };
-        serial@70006400 {
+        serial@0,70006400 {
                compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
-                reg = <0x70006400 0x40>;
+                reg = <0x0 0x70006400 0x0 0x40>;
                reg-shift = <2>;
                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_UARTE>;
@@ -177,9 +246,9 @@
                status = "disabled";
        };
-        pwm@7000a000 {
+        pwm@0,7000a000 {
                compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
-                reg = <0x7000a000 0x100>;
+                reg = <0x0 0x7000a000 0x0 0x100>;
                #pwm-cells = <2>;
                clocks = <&tegra_car TEGRA124_CLK_PWM>;
                resets = <&tegra_car 17>;
@@ -187,9 +256,9 @@
                status = "disabled";
        };
-        i2c@7000c000 {
+        i2c@0,7000c000 {
                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
-                reg = <0x7000c000 0x100>;
+                reg = <0x0 0x7000c000 0x0 0x100>;
                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -202,9 +271,9 @@
                status = "disabled";
        };
-        i2c@7000c400 {
+        i2c@0,7000c400 {
                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
-                reg = <0x7000c400 0x100>;
+                reg = <0x0 0x7000c400 0x0 0x100>;
                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -217,9 +286,9 @@
                status = "disabled";
        };
-        i2c@7000c500 {
+        i2c@0,7000c500 {
                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
-                reg = <0x7000c500 0x100>;
+                reg = <0x0 0x7000c500 0x0 0x100>;
                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -232,9 +301,9 @@
                status = "disabled";
        };
-        i2c@7000c700 {
+        i2c@0,7000c700 {
                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
-                reg = <0x7000c700 0x100>;
+                reg = <0x0 0x7000c700 0x0 0x100>;
                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -247,9 +316,9 @@
                status = "disabled";
        };
-        i2c@7000d000 {
+        i2c@0,7000d000 {
                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
-                reg = <0x7000d000 0x100>;
+                reg = <0x0 0x7000d000 0x0 0x100>;
                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -262,9 +331,9 @@
                status = "disabled";
        };
-        i2c@7000d100 {
+        i2c@0,7000d100 {
                compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
-                reg = <0x7000d100 0x100>;
+                reg = <0x0 0x7000d100 0x0 0x100>;
                interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -277,9 +346,9 @@
                status = "disabled";
        };
-        spi@7000d400 {
+        spi@0,7000d400 {
                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
-                reg = <0x7000d400 0x200>;
+                reg = <0x0 0x7000d400 0x0 0x200>;
                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -292,9 +361,9 @@
                status = "disabled";
        };
-        spi@7000d600 {
+        spi@0,7000d600 {
                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
-                reg = <0x7000d600 0x200>;
+                reg = <0x0 0x7000d600 0x0 0x200>;
                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -307,9 +376,9 @@
                status = "disabled";
        };
-        spi@7000d800 {
+        spi@0,7000d800 {
                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
-                reg = <0x7000d800 0x200>;
+                reg = <0x0 0x7000d800 0x0 0x200>;
                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -322,9 +391,9 @@
                status = "disabled";
        };
-        spi@7000da00 {
+        spi@0,7000da00 {
                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
-                reg = <0x7000da00 0x200>;
+                reg = <0x0 0x7000da00 0x0 0x200>;
                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -337,9 +406,9 @@
                status = "disabled";
        };
-        spi@7000dc00 {
+        spi@0,7000dc00 {
                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
-                reg = <0x7000dc00 0x200>;
+                reg = <0x0 0x7000dc00 0x0 0x200>;
                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -352,9 +421,9 @@
                status = "disabled";
        };
-        spi@7000de00 {
+        spi@0,7000de00 {
                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
-                reg = <0x7000de00 0x200>;
+                reg = <0x0 0x7000de00 0x0 0x200>;
                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -367,65 +436,65 @@
                status = "disabled";
        };
-        rtc@7000e000 {
+        rtc@0,7000e000 {
                compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
-                reg = <0x7000e000 0x100>;
+                reg = <0x0 0x7000e000 0x0 0x100>;
                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_RTC>;
        };
-        pmc@7000e400 {
+        pmc@0,7000e400 {
                compatible = "nvidia,tegra124-pmc";
-                reg = <0x7000e400 0x400>;
+                reg = <0x0 0x7000e400 0x0 0x400>;
                clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
                clock-names = "pclk", "clk32k_in";
        };
-        sdhci@700b0000 {
+        sdhci@0,700b0000 {
                compatible = "nvidia,tegra124-sdhci";
-                reg = <0x700b0000 0x200>;
+                reg = <0x0 0x700b0000 0x0 0x200>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
                resets = <&tegra_car 14>;
                reset-names = "sdhci";
-                status = "disable";
+                status = "disabled";
        };
-        sdhci@700b0200 {
+        sdhci@0,700b0200 {
                compatible = "nvidia,tegra124-sdhci";
-                reg = <0x700b0200 0x200>;
+                reg = <0x0 0x700b0200 0x0 0x200>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
                resets = <&tegra_car 9>;
                reset-names = "sdhci";
-                status = "disable";
+                status = "disabled";
        };
-        sdhci@700b0400 {
+        sdhci@0,700b0400 {
                compatible = "nvidia,tegra124-sdhci";
-                reg = <0x700b0400 0x200>;
+                reg = <0x0 0x700b0400 0x0 0x200>;
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
                resets = <&tegra_car 69>;
                reset-names = "sdhci";
-                status = "disable";
+                status = "disabled";
        };
-        sdhci@700b0600 {
+        sdhci@0,700b0600 {
                compatible = "nvidia,tegra124-sdhci";
-                reg = <0x700b0600 0x200>;
+                reg = <0x0 0x700b0600 0x0 0x200>;
                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
                resets = <&tegra_car 15>;
                reset-names = "sdhci";
-                status = "disable";
+                status = "disabled";
        };
-        ahub@70300000 {
+        ahub@0,70300000 {
                compatible = "nvidia,tegra124-ahub";
-                reg = <0x70300000 0x200>,
+                reg = <0x0 0x70300000 0x0 0x200>,
-                      <0x70300800 0x800>,
+                      <0x0 0x70300800 0x0 0x800>,
-                      <0x70300200 0x600>;
+                      <0x0 0x70300200 0x0 0x600>;
                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
                         <&tegra_car TEGRA124_CLK_APBIF>;
@@ -470,12 +539,12 @@
                            "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
                            "rx9", "tx9";
                ranges;
-                #address-cells = <1>;
+                #address-cells = <2>;
-                #size-cells = <1>;
+                #size-cells = <2>;
-                tegra_i2s0: i2s@70301000 {
+                tegra_i2s0: i2s@0,70301000 {
                        compatible = "nvidia,tegra124-i2s";
-                        reg = <0x70301000 0x100>;
+                        reg = <0x0 0x70301000 0x0 0x100>;
                        nvidia,ahub-cif-ids = <4 4>;
                        clocks = <&tegra_car TEGRA124_CLK_I2S0>;
                        resets = <&tegra_car 30>;
@@ -483,9 +552,9 @@
                        status = "disabled";
                };
-                tegra_i2s1: i2s@70301100 {
+                tegra_i2s1: i2s@0,70301100 {
                        compatible = "nvidia,tegra124-i2s";
-                        reg = <0x70301100 0x100>;
+                        reg = <0x0 0x70301100 0x0 0x100>;
                        nvidia,ahub-cif-ids = <5 5>;
                        clocks = <&tegra_car TEGRA124_CLK_I2S1>;
                        resets = <&tegra_car 11>;
@@ -493,9 +562,9 @@
                        status = "disabled";
                };
-                tegra_i2s2: i2s@70301200 {
+                tegra_i2s2: i2s@0,70301200 {
                        compatible = "nvidia,tegra124-i2s";
-                        reg = <0x70301200 0x100>;
+                        reg = <0x0 0x70301200 0x0 0x100>;
                        nvidia,ahub-cif-ids = <6 6>;
                        clocks = <&tegra_car TEGRA124_CLK_I2S2>;
                        resets = <&tegra_car 18>;
@@ -503,9 +572,9 @@
                        status = "disabled";
                };
-                tegra_i2s3: i2s@70301300 {
+                tegra_i2s3: i2s@0,70301300 {
                        compatible = "nvidia,tegra124-i2s";
-                        reg = <0x70301300 0x100>;
+                        reg = <0x0 0x70301300 0x0 0x100>;
                        nvidia,ahub-cif-ids = <7 7>;
                        clocks = <&tegra_car TEGRA124_CLK_I2S3>;
                        resets = <&tegra_car 101>;
@@ -513,9 +582,9 @@
                        status = "disabled";
                };
-                tegra_i2s4: i2s@70301400 {
+                tegra_i2s4: i2s@0,70301400 {
                        compatible = "nvidia,tegra124-i2s";
-                        reg = <0x70301400 0x100>;
+                        reg = <0x0 0x70301400 0x0 0x100>;
                        nvidia,ahub-cif-ids = <8 8>;
                        clocks = <&tegra_car TEGRA124_CLK_I2S4>;
                        resets = <&tegra_car 102>;
@@ -524,6 +593,108 @@
                };
        };
+        usb@0,7d000000 {
+                compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+                reg = <0x0 0x7d000000 0x0 0x4000>;
+                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                phy_type = "utmi";
+                clocks = <&tegra_car TEGRA124_CLK_USBD>;
+                resets = <&tegra_car 22>;
+                reset-names = "usb";
+                nvidia,phy = <&phy1>;
+                status = "disabled";
+        };
+        phy1: usb-phy@0,7d000000 {
+                compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
+                reg = <0x0 0x7d000000 0x0 0x4000>,
+                      <0x0 0x7d000000 0x0 0x4000>;
+                phy_type = "utmi";
+                clocks = <&tegra_car TEGRA124_CLK_USBD>,
+                         <&tegra_car TEGRA124_CLK_PLL_U>,
+                         <&tegra_car TEGRA124_CLK_USBD>;
+                clock-names = "reg", "pll_u", "utmi-pads";
+                nvidia,hssync-start-delay = <0>;
+                nvidia,idle-wait-delay = <17>;
+                nvidia,elastic-limit = <16>;
+                nvidia,term-range-adj = <6>;
+                nvidia,xcvr-setup = <9>;
+                nvidia,xcvr-lsfslew = <0>;
+                nvidia,xcvr-lsrslew = <3>;
+                nvidia,hssquelch-level = <2>;
+                nvidia,hsdiscon-level = <5>;
+                nvidia,xcvr-hsslew = <12>;
+                status = "disabled";
+        };
+        usb@0,7d004000 {
+                compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+                reg = <0x0 0x7d004000 0x0 0x4000>;
+                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                phy_type = "utmi";
+                clocks = <&tegra_car TEGRA124_CLK_USB2>;
+                resets = <&tegra_car 58>;
+                reset-names = "usb";
+                nvidia,phy = <&phy2>;
+                status = "disabled";
+        };
+        phy2: usb-phy@0,7d004000 {
+                compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
+                reg = <0x0 0x7d004000 0x0 0x4000>,
+                      <0x0 0x7d000000 0x0 0x4000>;
+                phy_type = "utmi";
+                clocks = <&tegra_car TEGRA124_CLK_USB2>,
+                         <&tegra_car TEGRA124_CLK_PLL_U>,
+                         <&tegra_car TEGRA124_CLK_USBD>;
+                clock-names = "reg", "pll_u", "utmi-pads";
+                nvidia,hssync-start-delay = <0>;
+                nvidia,idle-wait-delay = <17>;
+                nvidia,elastic-limit = <16>;
+                nvidia,term-range-adj = <6>;
+                nvidia,xcvr-setup = <9>;
+                nvidia,xcvr-lsfslew = <0>;
+                nvidia,xcvr-lsrslew = <3>;
+                nvidia,hssquelch-level = <2>;
+                nvidia,hsdiscon-level = <5>;
+                nvidia,xcvr-hsslew = <12>;
+                status = "disabled";
+        };
+        usb@0,7d008000 {
+                compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+                reg = <0x0 0x7d008000 0x0 0x4000>;
+                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                phy_type = "utmi";
+                clocks = <&tegra_car TEGRA124_CLK_USB3>;
+                resets = <&tegra_car 59>;
+                reset-names = "usb";
+                nvidia,phy = <&phy3>;
+                status = "disabled";
+        };
+        phy3: usb-phy@0,7d008000 {
+                compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
+                reg = <0x0 0x7d008000 0x0 0x4000>,
+                      <0x0 0x7d000000 0x0 0x4000>;
+                phy_type = "utmi";
+                clocks = <&tegra_car TEGRA124_CLK_USB3>,
+                         <&tegra_car TEGRA124_CLK_PLL_U>,
+                         <&tegra_car TEGRA124_CLK_USBD>;
+                clock-names = "reg", "pll_u", "utmi-pads";
+                nvidia,hssync-start-delay = <0>;
+                nvidia,idle-wait-delay = <17>;
+                nvidia,elastic-limit = <16>;
+                nvidia,term-range-adj = <6>;
+                nvidia,xcvr-setup = <9>;
+                nvidia,xcvr-lsfslew = <0>;
+                nvidia,xcvr-lsrslew = <3>;
+                nvidia,hssquelch-level = <2>;
+                nvidia,hsdiscon-level = <5>;
+                nvidia,xcvr-hsslew = <12>;
+                status = "disabled";
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index c7cd8e6802d7..9a39a8001f78 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -17,6 +17,14 @@
        };
        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+                                nvidia,panel = <&panel>;
+                        };
+                };
                hdmi@54280000 {
                        status = "okay";
@@ -257,7 +265,11 @@
                status = "okay";
        };
-        i2c@7000c000 {
+        pwm: pwm@7000a000 {
+                status = "okay";
+        };
+        lvds_ddc: i2c@7000c000 {
                status = "okay";
                clock-frequency = <400000>;
@@ -475,6 +487,18 @@
                non-removable;
        };
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+                pwms = <&pwm 0 5000000>;
+                brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
+                default-brightness-level = <10>;
+                backlight-boot-off;
+        };
        clocks {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -509,6 +533,16 @@
                };
        };
+        panel: panel {
+                compatible = "samsung,ltn101nt05", "simple-panel";
+                ddc-i2c-bus = <&lvds_ddc>;
+                power-supply = <&vdd_pnl_reg>;
+                enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
+                backlight = <&backlight>;
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -522,6 +556,16 @@
                        regulator-max-microvolt = <5000000>;
                        regulator-always-on;
                };
+                vdd_pnl_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "+3VS,vdd_pnl";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
        };
        sound {
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index a11b6e7b4759..a1d4bf9895d7 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -17,6 +17,14 @@
        };
        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+                                nvidia,panel = <&panel>;
+                        };
+                };
                hdmi@54280000 {
                        status = "okay";
@@ -312,6 +320,10 @@
                status = "okay";
        };
+        pwm: pwm@7000a000 {
+                status = "okay";
+        };
        i2c@7000c000 {
                status = "okay";
                clock-frequency = <400000>;
@@ -369,7 +381,7 @@
                        #size-cells = <0>;
                };
-                i2c@1 {
+                lvds_ddc: i2c@1 {
                        reg = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -762,6 +774,17 @@
                non-removable;
        };
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_bl_reg>;
+                pwms = <&pwm 2 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
        clocks {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -795,6 +818,16 @@
                };
        };
+        panel: panel {
+                compatible = "chunghwa,claa101wa01a", "simple-panel";
+                power-supply = <&vdd_pnl_reg>;
+                enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+                backlight = <&backlight>;
+                ddc-i2c-bus = <&lvds_ddc>;
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -839,6 +872,26 @@
                        regulator-always-on;
                        regulator-boot-on;
                };
+                vdd_pnl_reg: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "vdd_pnl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                vdd_bl_reg: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
        };
        sound {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 571d12e6ac2d..ca8484cccddc 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -17,6 +17,14 @@
        };
        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+                                nvidia,panel = <&panel>;
+                        };
+                };
                hdmi@54280000 {
                        status = "okay";
@@ -309,6 +317,10 @@
                status = "okay";
        };
+        pwm: pwm@7000a000 {
+                status = "okay";
+        };
        i2c@7000c000 {
                status = "okay";
                clock-frequency = <400000>;
@@ -359,7 +371,7 @@
                        #size-cells = <0>;
                };
-                i2c@1 {
+                lvds_ddc: i2c@1 {
                        reg = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -557,6 +569,17 @@
                non-removable;
        };
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+                power-supply = <&vdd_bl_reg>;
+                pwms = <&pwm 2 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
        clocks {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -581,6 +604,16 @@
                };
        };
+        panel: panel {
+                compatible = "chunghwa,claa101wa01a", "simple-panel";
+                power-supply = <&vdd_pnl_reg>;
+                enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+                backlight = <&backlight>;
+                ddc-i2c-bus = <&lvds_ddc>;
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -614,7 +647,7 @@
                        enable-active-high;
                };
-                regulator@3 {
+                vdd_pnl_reg: regulator@3 {
                        compatible = "regulator-fixed";
                        reg = <3>;
                        regulator-name = "vdd_pnl";
@@ -624,7 +657,7 @@
                        enable-active-high;
                };
-                regulator@4 {
+                vdd_bl_reg: regulator@4 {
                        compatible = "regulator-fixed";
                        reg = <4>;
                        regulator-name = "vdd_bl";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 48d2a7f4d0c0..a7ddf70df50b 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -556,6 +556,10 @@
                              GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
                interrupt-names = "intr", "msi";
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                bus-range = <0x00 0xff>;
                #address-cells = <3>;
                #size-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 1e156d9d0506..0cf0848a82d8 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -187,6 +187,13 @@
                        interrupt-parent = <&gpio>;
                        interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
                };
+                i2cmux@70 {
+                        compatible = "nxp,pca9546";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x70>;
+                };
        };
        i2c@7000c700 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 19a84e933f4e..dec4fc823901 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -28,6 +28,10 @@
                              GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
                interrupt-names = "intr", "msi";
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                bus-range = <0x00 0xff>;
                #address-cells = <3>;
                #size-cells = <2>;
@@ -144,9 +148,9 @@
                        compatible = "nvidia,tegra30-gr2d";
                        reg = <0x54140000 0x00040000>;
                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_GR2D>;
                        resets = <&tegra_car 21>;
                        reset-names = "2d";
-                        clocks = <&tegra_car TEGRA30_CLK_GR2D>;
                };
                gr3d@54180000 {
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
index 92693a89160e..b0ac6657a170 100644
--- a/arch/arm/boot/dts/tps65910.dtsi
+++ b/arch/arm/boot/dts/tps65910.dtsi
@@ -82,5 +82,10 @@
                        reg = <12>;
                        regulator-compatible = "vmmc";
                };
+                vbb_reg: regulator@13 {
+                        reg = <13>;
+                        regulator-compatible = "vbb";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 4217096ee677..86cfc7d15ca7 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -145,4 +145,11 @@
                compatible = "ti,twl4030-pwrbutton";
                interrupts = <8>;
        };
+        twl_keypad: keypad {
+                compatible = "ti,twl4030-keypad";
+                interrupts = <1>;
+                keypad,num-rows = <8>;
+                keypad,num-columns = <8>;
+        };
 };
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index c42e4f938dcd..3fd1b74e1216 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -36,12 +36,37 @@
 &fec1 {
        phy-mode = "rmii";
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec1_1>;
+        pinctrl-0 = <&pinctrl_fec1>;
        status = "okay";
 };
+&iomuxc {
+        vf610-cosmic {
+                pinctrl_fec1: fec1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
+                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB4__UART1_TX                0x21a2
+                                VF610_PAD_PTB5__UART1_RX                0x21a1
+                        >;
+                };
+        };
+};
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index c8047ca16501..7dd1d6ede525 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -34,12 +34,70 @@
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_3p3v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+                reg_vcc_3v3_mcu: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vcc_3v3_mcu";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                };
+        };
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,widgets =
+                        "Microphone", "Microphone Jack",
+                        "Headphone", "Headphone Jack",
+                        "Speaker", "Speaker Ext",
+                        "Line", "Line In Jack";
+                simple-audio-card,routing =
+                        "MIC_IN", "Microphone Jack",
+                        "Microphone Jack", "Mic Bias",
+                        "LINE_IN", "Line In Jack",
+                        "Headphone Jack", "HP_OUT",
+                        "Speaker Ext", "LINE_OUT";
+                simple-audio-card,cpu {
+                        sound-dai = <&sai2>;
+                        master-clkdir-out;
+                        frame-master;
+                        bitclock-master;
+                };
+                simple-audio-card,codec {
+                        sound-dai = <&codec>;
+                        frame-master;
+                        bitclock-master;
+                };
+        };
+};
+&adc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_adc0_ad5>;
+        vref-supply = <&reg_vcc_3v3_mcu>;
+        status = "okay";
 };
 &dspi0 {
        bus-num = <0>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_dspi0_1>;
+        pinctrl-0 = <&pinctrl_dspi0>;
        status = "okay";
        sflash: at26df081a@0 {
@@ -56,26 +114,116 @@
 &fec0 {
        phy-mode = "rmii";
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec0_1>;
+        pinctrl-0 = <&pinctrl_fec0>;
        status = "okay";
 };
 &fec1 {
        phy-mode = "rmii";
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec1_1>;
+        pinctrl-0 = <&pinctrl_fec1>;
        status = "okay";
 };
 &i2c0 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c0_1>;
+        pinctrl-0 = <&pinctrl_i2c0>;
+        status = "okay";
+        codec: sgtl5000@0a {
+               #sound-dai-cells = <0>;
+               compatible = "fsl,sgtl5000";
+               reg = <0x0a>;
+               VDDA-supply = <&reg_3p3v>;
+               VDDIO-supply = <&reg_3p3v>;
+               clocks = <&clks VF610_CLK_SAI2>;
+       };
+};
+&iomuxc {
+        vf610-twr {
+                pinctrl_adc0_ad5: adc0ad5grp {
+                        fsl,pins = <
+                                VF610_PAD_PTC30__ADC0_SE5               0xa1
+                        >;
+                };
+                pinctrl_dspi0: dspi0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB19__DSPI0_CS0              0x1182
+                                VF610_PAD_PTB20__DSPI0_SIN              0x1181
+                                VF610_PAD_PTB21__DSPI0_SOUT             0x1182
+                                VF610_PAD_PTB22__DSPI0_SCK              0x1182
+                        >;
+                };
+                pinctrl_fec0: fec0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTA6__RMII_CLKIN              0x30d1
+                                VF610_PAD_PTC0__ENET_RMII0_MDC          0x30d3
+                                VF610_PAD_PTC1__ENET_RMII0_MDIO         0x30d1
+                                VF610_PAD_PTC2__ENET_RMII0_CRS          0x30d1
+                                VF610_PAD_PTC3__ENET_RMII0_RXD1         0x30d1
+                                VF610_PAD_PTC4__ENET_RMII0_RXD0         0x30d1
+                                VF610_PAD_PTC5__ENET_RMII0_RXER         0x30d1
+                                VF610_PAD_PTC6__ENET_RMII0_TXD1         0x30d2
+                                VF610_PAD_PTC7__ENET_RMII0_TXD0         0x30d2
+                                VF610_PAD_PTC8__ENET_RMII0_TXEN         0x30d2
+                        >;
+                };
+                pinctrl_fec1: fec1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
+                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+                        >;
+                };
+                pinctrl_i2c0: i2c0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB14__I2C0_SCL               0x30d3
+                                VF610_PAD_PTB15__I2C0_SDA               0x30d3
+                        >;
+                };
+                pinctrl_sai2: sai2grp {
+                        fsl,pins = <
+                                VF610_PAD_PTA16__SAI2_TX_BCLK           0x02ed
+                                VF610_PAD_PTA18__SAI2_TX_DATA           0x02ee
+                                VF610_PAD_PTA19__SAI2_TX_SYNC           0x02ed
+                                VF610_PAD_PTA21__SAI2_RX_BCLK           0x02ed
+                                VF610_PAD_PTA22__SAI2_RX_DATA           0x02ed
+                                VF610_PAD_PTA23__SAI2_RX_SYNC           0x02ed
+                                VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x02ed
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB4__UART1_TX                0x21a2
+                                VF610_PAD_PTB5__UART1_RX                0x21a1
+                        >;
+                };
+        };
+};
+&sai2 {
+        #sound-dai-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sai2>;
        status = "okay";
 };
 &uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index d31ce1b4a7b0..804873367669 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -10,6 +10,7 @@
 #include "skeleton.dtsi"
 #include "vf610-pinfunc.h"
 #include <dt-bindings/clock/vf610-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 / {
        aliases {
@@ -87,39 +88,66 @@
                                arm,tag-latency = <2 2 2>;
                        };
+                        edma0: dma-controller@40018000 {
+                                #dma-cells = <2>;
+                                compatible = "fsl,vf610-edma";
+                                reg = <0x40018000 0x2000>,
+                                        <0x40024000 0x1000>,
+                                        <0x40025000 0x1000>;
+                                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
+                                                <0 9 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "edma-tx", "edma-err";
+                                dma-channels = <32>;
+                                clock-names = "dmamux0", "dmamux1";
+                                clocks = <&clks VF610_CLK_DMAMUX0>,
+                                        <&clks VF610_CLK_DMAMUX1>;
+                        };
                        uart0: serial@40027000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x40027000 0x1000>;
-                                interrupts = <0 61 0x00>;
+                                interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART0>;
                                clock-names = "ipg";
+                                dmas = <&edma0 0 2>,
+                                        <&edma0 0 3>;
+                                dma-names = "rx","tx";
                                status = "disabled";
                        };
                        uart1: serial@40028000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x40028000 0x1000>;
-                                interrupts = <0 62 0x04>;
+                                interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART1>;
                                clock-names = "ipg";
+                                dmas = <&edma0 0 4>,
+                                        <&edma0 0 5>;
+                                dma-names = "rx","tx";
                                status = "disabled";
                        };
                        uart2: serial@40029000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x40029000 0x1000>;
-                                interrupts = <0 63 0x04>;
+                                interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART2>;
                                clock-names = "ipg";
+                                dmas = <&edma0 0 6>,
+                                        <&edma0 0 7>;
+                                dma-names = "rx","tx";
                                status = "disabled";
                        };
                        uart3: serial@4002a000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x4002a000 0x1000>;
-                                interrupts = <0 64 0x04>;
+                                interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART3>;
                                clock-names = "ipg";
+                                dmas = <&edma0 0 8>,
+                                        <&edma0 0 9>;
+                                dma-names = "rx","tx";
                                status = "disabled";
                        };
@@ -128,7 +156,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,vf610-dspi";
                                reg = <0x4002c000 0x1000>;
-                                interrupts = <0 67 0x04>;
+                                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_DSPI0>;
                                clock-names = "dspi";
                                spi-num-chipselects = <5>;
@@ -138,20 +166,32 @@
                        sai2: sai@40031000 {
                                compatible = "fsl,vf610-sai";
                                reg = <0x40031000 0x1000>;
-                                interrupts = <0 86 0x04>;
+                                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_SAI2>;
                                clock-names = "sai";
+                                dma-names = "tx", "rx";
+                                dmas = <&edma0 0 21>,
+                                        <&edma0 0 20>;
                                status = "disabled";
                        };
                        pit: pit@40037000 {
                                compatible = "fsl,vf610-pit";
                                reg = <0x40037000 0x1000>;
-                                interrupts = <0 39 0x04>;
+                                interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_PIT>;
                                clock-names = "pit";
                        };
+                        adc0: adc@4003b000 {
+                                compatible = "fsl,vf610-adc";
+                                reg = <0x4003b000 0x1000>;
+                                interrupts = <0 53 0x04>;
+                                clocks = <&clks VF610_CLK_ADC0>;
+                                clock-names = "adc";
+                                status = "disabled";
+                        };
                        wdog@4003e000 {
                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
                                reg = <0x4003e000 0x1000>;
@@ -164,7 +204,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,vf610-qspi";
                                reg = <0x40044000 0x1000>;
-                                interrupts = <0 24 0x04>;
+                                interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_QSPI0_EN>,
                                        <&clks VF610_CLK_QSPI0>;
                                clock-names = "qspi_en", "qspi";
@@ -175,182 +215,12 @@
                                compatible = "fsl,vf610-iomuxc";
                                reg = <0x40048000 0x1000>;
                                #gpio-range-cells = <3>;
-                                /* functions and groups pins */
-                                dcu0 {
-                                        pinctrl_dcu0_1: dcu0grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTB8__GPIO_30         0x42
-                                                VF610_PAD_PTE0__DCU0_HSYNC      0x42
-                                                VF610_PAD_PTE1__DCU0_VSYNC      0x42
-                                                VF610_PAD_PTE2__DCU0_PCLK       0x42
-                                                VF610_PAD_PTE4__DCU0_DE         0x42
-                                                VF610_PAD_PTE5__DCU0_R0         0x42
-                                                VF610_PAD_PTE6__DCU0_R1         0x42
-                                                VF610_PAD_PTE7__DCU0_R2         0x42
-                                                VF610_PAD_PTE8__DCU0_R3         0x42
-                                                VF610_PAD_PTE9__DCU0_R4         0x42
-                                                VF610_PAD_PTE10__DCU0_R5        0x42
-                                                VF610_PAD_PTE11__DCU0_R6        0x42
-                                                VF610_PAD_PTE12__DCU0_R7        0x42
-                                                VF610_PAD_PTE13__DCU0_G0        0x42
-                                                VF610_PAD_PTE14__DCU0_G1        0x42
-                                                VF610_PAD_PTE15__DCU0_G2        0x42
-                                                VF610_PAD_PTE16__DCU0_G3        0x42
-                                                VF610_PAD_PTE17__DCU0_G4        0x42
-                                                VF610_PAD_PTE18__DCU0_G5        0x42
-                                                VF610_PAD_PTE19__DCU0_G6        0x42
-                                                VF610_PAD_PTE20__DCU0_G7        0x42
-                                                VF610_PAD_PTE21__DCU0_B0        0x42
-                                                VF610_PAD_PTE22__DCU0_B1        0x42
-                                                VF610_PAD_PTE23__DCU0_B2        0x42
-                                                VF610_PAD_PTE24__DCU0_B3        0x42
-                                                VF610_PAD_PTE25__DCU0_B4        0x42
-                                                VF610_PAD_PTE26__DCU0_B5        0x42
-                                                VF610_PAD_PTE27__DCU0_B6        0x42
-                                                VF610_PAD_PTE28__DCU0_B7        0x42
-                                                >;
-                                        };
-                                };
-                                dspi0 {
-                                        pinctrl_dspi0_1: dspi0grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTB19__DSPI0_CS0      0x1182
-                                                VF610_PAD_PTB20__DSPI0_SIN      0x1181
-                                                VF610_PAD_PTB21__DSPI0_SOUT     0x1182
-                                                VF610_PAD_PTB22__DSPI0_SCK      0x1182
-                                                >;
-                                        };
-                                };
-                                esdhc1 {
-                                        pinctrl_esdhc1_1: esdhc1grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
-                                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
-                                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
-                                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
-                                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
-                                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
-                                                VF610_PAD_PTA7__GPIO_134        0x219d
-                                                >;
-                                        };
-                                };
-                                fec0 {
-                                        pinctrl_fec0_1: fec0grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTA6__RMII_CLKIN      0x30d1
-                                                VF610_PAD_PTC0__ENET_RMII0_MDC  0x30d3
-                                                VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
-                                                VF610_PAD_PTC2__ENET_RMII0_CRS  0x30d1
-                                                VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
-                                                VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
-                                                VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
-                                                VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
-                                                VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
-                                                VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
-                                                >;
-                                        };
-                                };
-                                fec1 {
-                                        pinctrl_fec1_1: fec1grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
-                                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
-                                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
-                                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
-                                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
-                                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
-                                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
-                                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
-                                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
-                                                >;
-                                        };
-                                };
-                                i2c0 {
-                                        pinctrl_i2c0_1: i2c0grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTB14__I2C0_SCL       0x30d3
-                                                VF610_PAD_PTB15__I2C0_SDA       0x30d3
-                                                >;
-                                        };
-                                };
-                                pwm0 {
-                                        pinctrl_pwm0_1: pwm0grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTB0__FTM0_CH0        0x1582
-                                                VF610_PAD_PTB1__FTM0_CH1        0x1582
-                                                VF610_PAD_PTB2__FTM0_CH2        0x1582
-                                                VF610_PAD_PTB3__FTM0_CH3        0x1582
-                                                VF610_PAD_PTB6__FTM0_CH6        0x1582
-                                                VF610_PAD_PTB7__FTM0_CH7        0x1582
-                                                >;
-                                        };
-                                };
-                                qspi0 {
-                                        pinctrl_qspi0_1: qspi0grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTD0__QSPI0_A_QSCK    0x307b
-                                                VF610_PAD_PTD1__QSPI0_A_CS0     0x307f
-                                                VF610_PAD_PTD2__QSPI0_A_DATA3   0x3073
-                                                VF610_PAD_PTD3__QSPI0_A_DATA2   0x3073
-                                                VF610_PAD_PTD4__QSPI0_A_DATA1   0x3073
-                                                VF610_PAD_PTD5__QSPI0_A_DATA0   0x307b
-                                                VF610_PAD_PTD7__QSPI0_B_QSCK    0x307b
-                                                VF610_PAD_PTD8__QSPI0_B_CS0     0x307f
-                                                VF610_PAD_PTD9__QSPI0_B_DATA3   0x3073
-                                                VF610_PAD_PTD10__QSPI0_B_DATA2  0x3073
-                                                VF610_PAD_PTD11__QSPI0_B_DATA1  0x3073
-                                                VF610_PAD_PTD12__QSPI0_B_DATA0  0x307b
-                                                >;
-                                        };
-                                };
-                                sai2 {
-                                        pinctrl_sai2_1: sai2grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTA16__SAI2_TX_BCLK   0x02ed
-                                                VF610_PAD_PTA18__SAI2_TX_DATA   0x02ee
-                                                VF610_PAD_PTA19__SAI2_TX_SYNC   0x02ed
-                                                VF610_PAD_PTA21__SAI2_RX_BCLK   0x02ed
-                                                VF610_PAD_PTA22__SAI2_RX_DATA   0x02ed
-                                                VF610_PAD_PTA23__SAI2_RX_SYNC   0x02ed
-                                                VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
-                                                >;
-                                        };
-                                };
-                                uart1 {
-                                        pinctrl_uart1_1: uart1grp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTB4__UART1_TX        0x21a2
-                                                VF610_PAD_PTB5__UART1_RX        0x21a1
-                                                >;
-                                        };
-                                };
-                                usbvbus {
-                                        pinctrl_usbvbus_1: usbvbusgrp_1 {
-                                                fsl,pins = <
-                                                VF610_PAD_PTA24__USB1_VBUS_EN   0x219c
-                                                VF610_PAD_PTA16__USB0_VBUS_EN   0x219c
-                                                >;
-                                        };
-                                };
                        };
                        gpio1: gpio@40049000 {
                                compatible = "fsl,vf610-gpio";
                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
-                                interrupts = <0 107 0x04>;
+                                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -361,7 +231,7 @@
                        gpio2: gpio@4004a000 {
                                compatible = "fsl,vf610-gpio";
                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
-                                interrupts = <0 108 0x04>;
+                                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -372,7 +242,7 @@
                        gpio3: gpio@4004b000 {
                                compatible = "fsl,vf610-gpio";
                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
-                                interrupts = <0 109 0x04>;
+                                interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -383,7 +253,7 @@
                        gpio4: gpio@4004c000 {
                                compatible = "fsl,vf610-gpio";
                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
-                                interrupts = <0 110 0x04>;
+                                interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -394,7 +264,7 @@
                        gpio5: gpio@4004d000 {
                                compatible = "fsl,vf610-gpio";
                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
-                                interrupts = <0 111 0x04>;
+                                interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
                                gpio-controller;
                                #gpio-cells = <2>;
                                interrupt-controller;
@@ -412,9 +282,12 @@
                                #size-cells = <0>;
                                compatible = "fsl,vf610-i2c";
                                reg = <0x40066000 0x1000>;
-                                interrupts =<0 71 0x04>;
+                                interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_I2C0>;
                                clock-names = "ipg";
+                                dmas = <&edma0 0 50>,
+                                        <&edma0 0 51>;
+                                dma-names = "rx","tx";
                                status = "disabled";
                        };
@@ -432,10 +305,25 @@
                        reg = <0x40080000 0x80000>;
                        ranges;
+                        edma1: dma-controller@40098000 {
+                                #dma-cells = <2>;
+                                compatible = "fsl,vf610-edma";
+                                reg = <0x40098000 0x2000>,
+                                        <0x400a1000 0x1000>,
+                                        <0x400a2000 0x1000>;
+                                interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
+                                                <0 11 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "edma-tx", "edma-err";
+                                dma-channels = <32>;
+                                clock-names = "dmamux0", "dmamux1";
+                                clocks = <&clks VF610_CLK_DMAMUX2>,
+                                        <&clks VF610_CLK_DMAMUX3>;
+                        };
                        uart4: serial@400a9000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x400a9000 0x1000>;
-                                interrupts = <0 65 0x04>;
+                                interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART4>;
                                clock-names = "ipg";
                                status = "disabled";
@@ -444,16 +332,25 @@
                        uart5: serial@400aa000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x400aa000 0x1000>;
-                                interrupts = <0 66 0x04>;
+                                interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART5>;
                                clock-names = "ipg";
                                status = "disabled";
                        };
+                        adc1: adc@400bb000 {
+                                compatible = "fsl,vf610-adc";
+                                reg = <0x400bb000 0x1000>;
+                                interrupts = <0 54 0x04>;
+                                clocks = <&clks VF610_CLK_ADC1>;
+                                clock-names = "adc";
+                                status = "disabled";
+                        };
                        fec0: ethernet@400d0000 {
                                compatible = "fsl,mvf600-fec";
                                reg = <0x400d0000 0x1000>;
-                                interrupts = <0 78 0x04>;
+                                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ENET0>,
                                        <&clks VF610_CLK_ENET0>,
                                        <&clks VF610_CLK_ENET>;
@@ -464,7 +361,7 @@
                        fec1: ethernet@400d1000 {
                                compatible = "fsl,mvf600-fec";
                                reg = <0x400d1000 0x1000>;
-                                interrupts = <0 79 0x04>;
+                                interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ENET1>,
                                        <&clks VF610_CLK_ENET1>,
                                        <&clks VF610_CLK_ENET>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 789d0bacc110..511180769af5 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -129,29 +129,28 @@
                } ;
                slcr: slcr@f8000000 {
-                        compatible = "xlnx,zynq-slcr";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "xlnx,zynq-slcr", "syscon";
                        reg = <0xF8000000 0x1000>;
+                        ranges;
-                        clocks {
+                        clkc: clkc@100 {
-                                #address-cells = <1>;
+                                #clock-cells = <1>;
-                                #size-cells = <0>;
+                                compatible = "xlnx,ps7-clkc";
+                                ps-clk-frequency = <33333333>;
-                                clkc: clkc {
+                                fclk-enable = <0>;
-                                        #clock-cells = <1>;
+                                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
-                                        compatible = "xlnx,ps7-clkc";
+                                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
-                                        ps-clk-frequency = <33333333>;
+                                                "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
-                                        clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                                                "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
-                                                        "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                                                "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
-                                                        "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                                "dma", "usb0_aper", "usb1_aper", "gem0_aper",
-                                                        "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                                "gem1_aper", "sdio0_aper", "sdio1_aper",
-                                                        "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                                "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
-                                                        "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                                "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
-                                                        "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                                "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
-                                                        "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                                "dbg_trc", "dbg_apb";
-                                                        "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                reg = <0x100 0x100>;
-                                                        "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
-                                                        "dbg_trc", "dbg_apb";
-                                };
                        };
                };
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 4bdc41622c36..70b1eff477b3 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_ARM_TIMER_SP804)   += timer-sp.o
 obj-$(CONFIG_MCPM)              += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
+CFLAGS_REMOVE_mcpm_entry.o      = -pg
 AFLAGS_mcpm_head.o              := -march=armv7-a
 AFLAGS_vlock.o                  := -march=armv7-a
 obj-$(CONFIG_TI_PRIV_EDMA)      += edma.o
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index a5c3dc38aa18..6ef146edd0cd 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -232,8 +232,6 @@ static int scoop_probe(struct platform_device *pdev)
        return 0;
-        if (devptr->gpio.base != -1)
-                temp = gpiochip_remove(&devptr->gpio);
 err_gpio:
        platform_set_drvdata(pdev, NULL);
 err_ioremap:
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index 53c6a26b633d..fd6bff0c5b96 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -271,10 +271,14 @@ static void __init integrator_cp_of_init(struct device_node *np)
        void __iomem *base;
        int irq;
        const char *name = of_get_property(np, "compatible", NULL);
+        struct clk *clk;
        base = of_iomap(np, 0);
        if (WARN_ON(!base))
                return;
+        clk = of_clk_get(np, 0);
+        if (WARN_ON(IS_ERR(clk)))
+                return;
        /* Ensure timer is disabled */
        writel(0, base + TIMER_CTRL);
@@ -283,13 +287,13 @@ static void __init integrator_cp_of_init(struct device_node *np)
                goto err;
        if (!init_count)
-                sp804_clocksource_init(base, name);
+                __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
        else {
                irq = irq_of_parse_and_map(np, 0);
                if (irq <= 0)
                        goto err;
-                sp804_clockevents_init(base, irq, name);
+                __sp804_clockevents_init(base, irq, clk, name);
        }
        init_count++;
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index cb26c62dc722..bb396c0e5fda 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -48,6 +48,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6_SIT is not set
 CONFIG_NETFILTER=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CADENCE is not set
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 9287a62de830..065adddeee3e 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -58,6 +58,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_MD=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 0b4e9b5210d8..300ded9acbe9 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -16,10 +16,12 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_SOC_AT91RM9200=y
 CONFIG_SOC_AT91SAM9260=y
+CONFIG_SOC_AT91SAM9261=y
 CONFIG_SOC_AT91SAM9263=y
 CONFIG_SOC_AT91SAM9G45=y
 CONFIG_SOC_AT91SAM9X5=y
 CONFIG_SOC_AT91SAM9N12=y
+CONFIG_SOC_AT91SAM9RL=y
 CONFIG_MACH_AT91RM9200_DT=y
 CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_TIMER_HZ=128
@@ -119,6 +121,7 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
 # CONFIG_SERIO is not set
 CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_ATMEL=y
diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
index 2cd832918e9c..c4c160fc8791 100644
--- a/arch/arm/configs/at91sam9260_9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
@@ -30,15 +31,12 @@ CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_SLOW_CLOCK=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 CONFIG_AUTO_ZRELADDR=y
-CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -57,15 +55,14 @@ CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
@@ -112,8 +109,6 @@ CONFIG_SND_PCM_OSS=y
 CONFIG_SND_SEQUENCER_OSS=y
 # CONFIG_SND_VERBOSE_PROCFS is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
index 7b6f131cecd6..85f846ae9ff2 100644
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ b/arch/arm/configs/at91sam9rl_defconfig
@@ -1,8 +1,8 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EMBEDDED=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
@@ -14,20 +14,23 @@ CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9RL=y
 CONFIG_MACH_AT91SAM9RLEK=y
 # CONFIG_ARM_THUMB is not set
+CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,17105363 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_NET=y
 CONFIG_UNIX=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
@@ -66,6 +69,7 @@ CONFIG_EXT2_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_UBIFS_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index f43392dc2dcf..0302d293fba0 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -31,6 +31,7 @@ CONFIG_OPROFILE=y
 CONFIG_JUMP_LABEL=y
 CONFIG_ARCH_MULTI_V6=y
 # CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM2835=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 2519d6de0640..01004640ee4d 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -79,6 +79,13 @@ CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 # CONFIG_HWMON is not set
+CONFIG_MFD_BCM590XX=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
+CONFIG_REGULATOR_BCM590XX=y
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index 80cff50beb34..e816140d81c5 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -44,6 +44,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index 9e8c8316d6b0..0facf9da047c 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_CDB89712=y
 CONFIG_ARCH_CLEP7312=y
 CONFIG_ARCH_EDB7211=y
 CONFIG_ARCH_P720T=y
-CONFIG_ARCH_FORTUNET=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -27,7 +26,6 @@ CONFIG_INET=y
 # CONFIG_IPV6 is not set
 CONFIG_IRDA=y
 CONFIG_IRTTY_SIR=y
-CONFIG_EP7211_DONGLE=y
 # CONFIG_WIRELESS is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
@@ -58,6 +56,7 @@ CONFIG_CS89x0_PLATFORM=y
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
+CONFIG_SERIAL_CLPS711X=y
 CONFIG_SERIAL_CLPS711X_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
deleted file mode 100644
index 1571bea48bed..000000000000
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ /dev/null
@@ -1,139 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CGROUPS=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_DAVINCI=y
-CONFIG_ARCH_DAVINCI_DA830=y
-CONFIG_ARCH_DAVINCI_DA850=y
-CONFIG_MACH_DA8XX_DT=y
-CONFIG_MACH_MITYOMAPL138=y
-CONFIG_MACH_OMAPL138_HAWKBOARD=y
-CONFIG_DAVINCI_RESET_CLOCKS=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_USE_OF=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_IDLE=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_LRO is not set
-CONFIG_NETFILTER=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=32768
-CONFIG_EEPROM_AT24=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_NETDEVICES=y
-CONFIG_TUN=m
-CONFIG_LXT_PHY=y
-CONFIG_LSI_ET1011C_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_TI_DAVINCI_EMAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_NETCONSOLE=y
-CONFIG_NETPOLL_TRAP=y
-CONFIG_INPUT_MOUSEDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_ATKBD=m
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_XTKBD=m
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_VT_CONSOLE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_DAVINCI=y
-CONFIG_PINCTRL_SINGLE=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DUMMY=y
-CONFIG_REGULATOR_TPS6507X=y
-CONFIG_FB=y
-CONFIG_FB_DA8XX=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SOC=m
-CONFIG_SND_DAVINCI_SOC=m
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_DMADEVICES=y
-CONFIG_TI_EDMA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_XFS_FS=m
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_TIMER_STATS=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_T10DIF=m
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index ab2f7378352c..2a282c051cfd 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -20,9 +20,14 @@ CONFIG_ARCH_DAVINCI_DM644x=y
 CONFIG_ARCH_DAVINCI_DM355=y
 CONFIG_ARCH_DAVINCI_DM646x=y
 CONFIG_ARCH_DAVINCI_DM365=y
+CONFIG_ARCH_DAVINCI_DA830=y
+CONFIG_ARCH_DAVINCI_DA850=y
+CONFIG_MACH_DA8XX_DT=y
 CONFIG_MACH_SFFSDR=y
 CONFIG_MACH_NEUROS_OSD2=y
 CONFIG_MACH_DM355_LEOPARD=y
+CONFIG_MACH_MITYOMAPL138=y
+CONFIG_MACH_OMAPL138_HAWKBOARD=y
 CONFIG_DAVINCI_MUX_DEBUG=y
 CONFIG_DAVINCI_MUX_WARNINGS=y
 CONFIG_DAVINCI_RESET_CLOCKS=y
@@ -32,8 +37,18 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_LEDS=y
+CONFIG_USE_OF=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_IDLE=y
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -57,6 +72,7 @@ CONFIG_MTD_CFI_AMDSTD=m
 CONFIG_MTD_PHYSMAP=m
 CONFIG_MTD_NAND=m
 CONFIG_MTD_NAND_DAVINCI=m
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
@@ -71,6 +87,7 @@ CONFIG_TUN=m
 CONFIG_LXT_PHY=y
 CONFIG_LSI_ET1011C_PHY=y
 CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
 CONFIG_TI_DAVINCI_EMAC=y
 CONFIG_DM9000=y
 # CONFIG_NETDEV_1000 is not set
@@ -97,15 +114,21 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=3
 # CONFIG_HW_RANDOM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_DAVINCI=y
+CONFIG_PINCTRL_SINGLE=y
 CONFIG_GPIO_PCF857X=y
 CONFIG_WATCHDOG=y
 CONFIG_DAVINCI_WATCHDOG=m
 CONFIG_MFD_DM355EVM_MSP=y
+CONFIG_TPS6507X=y
 CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_TPS6507X=y
 CONFIG_FB=y
+CONFIG_FB_DA8XX=y
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -198,3 +221,5 @@ CONFIG_DEBUG_ERRORS=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
 CONFIG_CRC_T10DIF=m
+CONFIG_GPIO_PCA953X=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 110105476848..f15955144175 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -48,7 +48,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_STAA=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_M25P80=y
-CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
@@ -80,6 +79,8 @@ CONFIG_SPI_ORION=y
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
 CONFIG_DOVE_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index dbe1f1c47bb0..4ce7b70ea901 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -94,7 +94,7 @@ CONFIG_FONT_7x14=y
 CONFIG_LOGO=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_S5P=y
+CONFIG_USB_EHCI_EXYNOS=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_PHY=y
diff --git a/arch/arm/configs/genmai_defconfig b/arch/arm/configs/genmai_defconfig
index aa0b704f48af..d238fafb6762 100644
--- a/arch/arm/configs/genmai_defconfig
+++ b/arch/arm/configs/genmai_defconfig
@@ -50,6 +50,9 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_EEPROM_AT24=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CORE is not set
 # CONFIG_NET_VENDOR_ARC is not set
@@ -78,7 +81,10 @@ CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=10
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_I2C_SH_MOBILE=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_RIIC=y
+CONFIG_SPI=y
+CONFIG_SPI_RSPI=y
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 6309ee52ccfc..f1aeb7d72712 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -154,6 +154,7 @@ CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 53e82c2523eb..09e974392fa1 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -39,6 +39,8 @@ CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
 CONFIG_SOC_VF610=y
+CONFIG_PCI=y
+CONFIG_PCI_IMX6=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
@@ -165,6 +167,7 @@ CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_ANATOP=y
 CONFIG_REGULATOR_DA9052=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_REGULATOR_PFUZE100=y
@@ -186,6 +189,7 @@ CONFIG_LCD_L4F00242T03=y
 CONFIG_LCD_PLATFORM=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
+CONFIG_BACKLIGHT_GPIO=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
@@ -211,6 +215,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
@@ -225,6 +230,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_MC13XXX=y
 CONFIG_RTC_DRV_MXC=y
 CONFIG_RTC_DRV_SNVS=y
@@ -277,6 +283,7 @@ CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=y
+CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_PROVE_LOCKING=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 4582e160feab..ec9a41d50680 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -111,6 +111,7 @@ CONFIG_MTD_BLOCK=y
 CONFIG_MTD_PLATRAM=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_DAVINCI=y
 CONFIG_MTD_UBI=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
@@ -131,6 +132,8 @@ CONFIG_SPI_DAVINCI=y
 CONFIG_SPI_SPIDEV=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_DAVINCI_WATCHDOG=y
 CONFIG_USB=y
 CONFIG_USB_DEBUG=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
@@ -145,6 +148,7 @@ CONFIG_DMADEVICES=y
 CONFIG_TI_EDMA=y
 CONFIG_COMMON_CLK_DEBUG=y
 CONFIG_MEMORY=y
+CONFIG_TI_AEMIF=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_MSDOS_FS=y
@@ -177,3 +181,14 @@ CONFIG_CRYPTO_DES=y
 CONFIG_CRYPTO_ANSI_CPRNG=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DAVINCI=y
+CONFIG_LEDS_CLASS=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig
index e248f49d5549..86faab565a96 100644
--- a/arch/arm/configs/koelsch_defconfig
+++ b/arch/arm/configs/koelsch_defconfig
@@ -8,7 +8,6 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
-# CONFIG_BLOCK is not set
 CONFIG_ARCH_SHMOBILE_LEGACY=y
 CONFIG_ARCH_R8A7791=y
 CONFIG_MACH_KOELSCH=y
@@ -35,7 +34,14 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_SATA_RCAR=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_ARC is not set
 # CONFIG_NET_CADENCE is not set
@@ -53,18 +59,31 @@ CONFIG_SH_ETH=y
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=20
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_RSPI=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_RCAR=y
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
 # CONFIG_HID is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_DNOTIFY is not set
 CONFIG_TMPFS=y
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
deleted file mode 100644
index e42ce3756af3..000000000000
--- a/arch/arm/configs/kzm9d_defconfig
+++ /dev/null
@@ -1,89 +0,0 @@
-# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_EMBEDDED=y
-CONFIG_PERF_EVENTS=y
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE_LEGACY=y
-CONFIG_ARCH_EMEV2=y
-CONFIG_MACH_KZM9D=y
-CONFIG_MEMORY_START=0x40000000
-CONFIG_MEMORY_SIZE=0x10000000
-# CONFIG_SH_TIMER_TMU is not set
-# CONFIG_SWP_EMULATE is not set
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-CONFIG_HOTPLUG_CPU=y
-# CONFIG_LOCAL_TIMERS is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_CROSS_MEMORY_ATTACH is not set
-CONFIG_FORCE_MAX_ZONEORDER=13
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_VFP=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_BLK_DEV is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EM=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_EM=y
-# CONFIG_HWMON is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_IOMMU_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 9934dbc23d64..12bd1f63c399 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -60,6 +60,8 @@ CONFIG_IRDA=y
 CONFIG_SH_IRDA=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 883443f8f4f3..58702440472a 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -49,6 +49,13 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_SATA_RCAR=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CORE is not set
 # CONFIG_NET_VENDOR_ARC is not set
@@ -81,6 +88,8 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_RSPI=y
 CONFIG_GPIO_SH_PFC=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_RCAR=y
@@ -90,8 +99,20 @@ CONFIG_RCAR_THERMAL=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_PLATFORM=y
+CONFIG_VIDEO_RCAR_VIN=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+CONFIG_VIDEO_ADV7180=y
 CONFIG_DRM=y
 CONFIG_DRM_RCAR_DU=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_RCAR=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index a61e1653fc5e..57ececba2ae6 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -42,6 +42,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index f21bd405cc2a..92994f7f6fd8 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -43,6 +43,8 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_IPV6 is not set
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
new file mode 100644
index 000000000000..aa3dfb084fed
--- /dev/null
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -0,0 +1,190 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_MVEBU=y
+CONFIG_MACH_KIRKWOOD=y
+CONFIG_MACH_T5325=y
+CONFIG_ARCH_MXC=y
+CONFIG_MACH_IMX25_DT=y
+CONFIG_MACH_IMX27_DT=y
+CONFIG_ARCH_U300=y
+CONFIG_PCI_MVEBU=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_KIRKWOOD_CPUIDLE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IPV6 is not set
+CONFIG_NET_PKTGEN=m
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ORION=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_EEPROM_AT24=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=m
+CONFIG_CHR_DEV_SG=m
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_MV=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
+CONFIG_MV643XX_ETH=y
+CONFIG_R8169=y
+CONFIG_MARVELL_PHY=y
+CONFIG_LIBERTAS=y
+CONFIG_LIBERTAS_SDIO=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_NOMADIK=y
+CONFIG_SPI=y
+CONFIG_SPI_ORION=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_QNAP=y
+CONFIG_SENSORS_ADT7475=y
+CONFIG_SENSORS_LM63=y
+CONFIG_SENSORS_LM75=y
+CONFIG_SENSORS_LM85=y
+CONFIG_THERMAL=y
+CONFIG_KIRKWOOD_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_KIRKWOOD_SOC=y
+CONFIG_SND_KIRKWOOD_SOC_T5325=y
+# CONFIG_ABX500_CORE is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_HID_DRAGONRISE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_PRINTER=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_MMC=y
+CONFIG_SDIO_UART=y
+CONFIG_MMC_MVSDIO=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RS5C372=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_DRV_S35390A=y
+CONFIG_RTC_DRV_MV=y
+CONFIG_DMADEVICES=y
+CONFIG_MV_XOR=y
+CONFIG_STAGING=y
+CONFIG_FB_XGI=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_UTF8=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_MV_CESA=y
+CONFIG_CRC_CCITT=y
+CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index ee6982976d66..d4e8a47a2f7c 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -9,8 +10,12 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
+CONFIG_MACH_ARMADA_375=y
+CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
+CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_MACH_BERLIN_BG2=y
@@ -31,6 +36,10 @@ CONFIG_SOC_OMAP5=y
 CONFIG_SOC_AM33XX=y
 CONFIG_SOC_DRA7XX=y
 CONFIG_SOC_AM43XX=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_MSM8X60=y
+CONFIG_ARCH_MSM8960=y
+CONFIG_ARCH_MSM8974=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_PLAT_SPEAR=y
@@ -55,6 +64,7 @@ CONFIG_ARCH_VEXPRESS_CA9X4=y
 CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_WM8850=y
 CONFIG_ARCH_ZYNQ=y
+CONFIG_NEON=y
 CONFIG_TRUSTED_FOUNDATIONS=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
@@ -94,6 +104,7 @@ CONFIG_RFKILL_GPIO=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=64
 CONFIG_OMAP_OCP2SCP=y
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
@@ -111,6 +122,7 @@ CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
 CONFIG_SUN4I_EMAC=y
 CONFIG_NET_CALXEDA_XGMAC=y
+CONFIG_MV643XX_ETH=y
 CONFIG_MVNETA=y
 CONFIG_KS8851=y
 CONFIG_R8169=y
@@ -146,6 +158,8 @@ CONFIG_SERIAL_SIRFSOC_CONSOLE=y
 CONFIG_SERIAL_TEGRA=y
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SERIAL_VT8500=y
 CONFIG_SERIAL_VT8500_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
@@ -159,6 +173,7 @@ CONFIG_SERIAL_ST_ASC=y
 CONFIG_SERIAL_ST_ASC_CONSOLE=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_I2C_MV64XXX=y
@@ -187,7 +202,10 @@ CONFIG_POWER_RESET_AS3722=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_LM90=y
 CONFIG_THERMAL=y
+CONFIG_DOVE_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
 CONFIG_MFD_AS3722=y
 CONFIG_MFD_CROS_EC=y
 CONFIG_MFD_CROS_EC_SPI=y
@@ -212,6 +230,8 @@ CONFIG_REGULATOR_VEXPRESS=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_GSPCA=y
 CONFIG_DRM=y
 CONFIG_DRM_TEGRA=y
 CONFIG_DRM_PANEL_SIMPLE=y
@@ -254,6 +274,7 @@ CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMC_SDHCI_DOVE=y
 CONFIG_MMC_SDHCI_SPEAR=y
 CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_MMC_OMAP=y
@@ -294,6 +315,10 @@ CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
 CONFIG_NVEC_POWER=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_MSM_GCC_8660=y
+CONFIG_MSM_MMCC_8960=y
+CONFIG_MSM_MMCC_8974=y
 CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig
new file mode 100644
index 000000000000..36484a37a1ca
--- /dev/null
+++ b/arch/arm/configs/mvebu_v5_defconfig
@@ -0,0 +1,181 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_MVEBU=y
+CONFIG_MACH_KIRKWOOD=y
+CONFIG_MACH_T5325=y
+# CONFIG_CPU_FEROCEON_OLD_ID is not set
+CONFIG_PCI_MVEBU=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IPV6 is not set
+CONFIG_NET_PKTGEN=m
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ORION=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_EEPROM_AT24=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=m
+CONFIG_CHR_DEV_SG=m
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_MV=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
+CONFIG_MV643XX_ETH=y
+CONFIG_R8169=y
+CONFIG_MARVELL_PHY=y
+CONFIG_LIBERTAS=y
+CONFIG_LIBERTAS_SDIO=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_SPI=y
+CONFIG_SPI_ORION=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_QNAP=y
+CONFIG_SENSORS_ADT7475=y
+CONFIG_SENSORS_LM63=y
+CONFIG_SENSORS_LM75=y
+CONFIG_SENSORS_LM85=y
+CONFIG_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_KIRKWOOD_SOC=y
+CONFIG_SND_KIRKWOOD_SOC_T5325=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_HID_DRAGONRISE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_PRINTER=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_MMC=y
+CONFIG_SDIO_UART=y
+CONFIG_MMC_MVSDIO=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RS5C372=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_DRV_S35390A=y
+CONFIG_RTC_DRV_MV=y
+CONFIG_DMADEVICES=y
+CONFIG_MV_XOR=y
+CONFIG_STAGING=y
+CONFIG_FB_XGI=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_UTF8=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_MV_CESA=y
+CONFIG_CRC_CCITT=y
+CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index 0f4511d2849f..a34713d8db9f 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -10,7 +10,10 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
+CONFIG_MACH_ARMADA_375=y
+CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
+CONFIG_NEON=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
 CONFIG_PCI=y
@@ -62,6 +65,13 @@ CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_KIRKWOOD_SOC=y
+CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB=y
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
 CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 3a0b53d225e7..a9667957b757 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -28,6 +28,7 @@ CONFIG_ARCH_OMAP3=y
 CONFIG_ARCH_OMAP4=y
 CONFIG_SOC_OMAP5=y
 CONFIG_SOC_AM33XX=y
+CONFIG_SOC_AM43XX=y
 CONFIG_SOC_DRA7XX=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_ERRATA_411920=y
@@ -169,6 +170,7 @@ CONFIG_DRA752_THERMAL=y
 CONFIG_WATCHDOG=y
 CONFIG_OMAP_WATCHDOG=y
 CONFIG_TWL4030_WATCHDOG=y
+CONFIG_MFD_SYSCON=y
 CONFIG_MFD_PALMAS=y
 CONFIG_MFD_TPS65217=y
 CONFIG_MFD_TPS65910=y
@@ -180,6 +182,7 @@ CONFIG_REGULATOR_TPS6507X=y
 CONFIG_REGULATOR_TPS65217=y
 CONFIG_REGULATOR_TPS65910=y
 CONFIG_REGULATOR_TWL4030=y
+CONFIG_REGULATOR_PBIAS=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_MODE_HELPERS=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
new file mode 100644
index 000000000000..83b07258a385
--- /dev/null
+++ b/arch/arm/configs/shmobile_defconfig
@@ -0,0 +1,129 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_ARCH_SHMOBILE_MULTI=y
+CONFIG_ARCH_EMEV2=y
+CONFIG_ARCH_R8A7790=y
+CONFIG_ARCH_R8A7791=y
+CONFIG_MACH_KOELSCH=y
+CONFIG_MACH_LAGER=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_CPU_BPREDICT_DISABLE=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_NR_CPUS=8
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_KEXEC=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_SATA_RCAR=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_SH_ETH=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_EM=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=20
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_RSPI=y
+CONFIG_GPIO_EM=y
+CONFIG_GPIO_RCAR=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_RCAR_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_PLATFORM=y
+CONFIG_VIDEO_RCAR_VIN=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+CONFIG_VIDEO_ADV7180=y
+CONFIG_DRM=y
+CONFIG_DRM_RCAR_DU=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_RCAR=y
+CONFIG_USB_RCAR_GEN2_PHY=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_SH_DMAE=y
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 4e1ce211d43f..e3a05e8801d8 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -52,6 +52,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_STMMAC_ETH=y
+CONFIG_MICREL_PHY=y
 # CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_SERPORT is not set
@@ -66,6 +67,9 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT3_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
 CONFIG_VFAT_FS=y
@@ -82,3 +86,5 @@ CONFIG_DEBUG_INFO=y
 CONFIG_ENABLE_DEFAULT_TRACERS=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
+CONFIG_MMC=y
+CONFIG_MMC_DW=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 3e2259b60236..b5df4a511b0a 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -24,6 +24,7 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_EEPROM_SUNXI_SID=y
 CONFIG_NETDEVICES=y
 CONFIG_SUN4I_EMAC=y
 # CONFIG_NET_CADENCE is not set
@@ -48,6 +49,8 @@ CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MV64XXX=y
+CONFIG_SPI=y
+CONFIG_SPI_SUN6I=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 27d69b558c5d..2926281368ab 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
@@ -86,6 +87,7 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=64
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
 CONFIG_PROC_DEVICETREE=y
@@ -125,6 +127,7 @@ CONFIG_SERIAL_TEGRA=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
@@ -141,6 +144,7 @@ CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
 CONFIG_CHARGER_TPS65090=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AS3722=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_AS3722=y
@@ -166,7 +170,8 @@ CONFIG_REGULATOR_TPS65910=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_MEDIA_USB_SUPPORT=y
-CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_GSPCA=y
 CONFIG_DRM=y
 CONFIG_DRM_TEGRA=y
 CONFIG_DRM_PANEL_SIMPLE=y
diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig
index bb00ccf00d66..ad396af68e47 100644
--- a/arch/arm/firmware/Kconfig
+++ b/arch/arm/firmware/Kconfig
@@ -11,6 +11,7 @@ menu "Firmware options"
 config TRUSTED_FOUNDATIONS
        bool "Trusted Foundations secure monitor support"
        depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
+        default y
        help
          Some devices (including most Tegra-based consumer devices on the
          market) are booted with the Trusted Foundations secure monitor
@@ -20,7 +21,7 @@ config TRUSTED_FOUNDATIONS
          This option allows the kernel to invoke the secure monitor whenever
          required on devices using Trusted Foundations. See
          arch/arm/include/asm/trusted_foundations.h or the
-          tl,trusted-foundations device tree binding documentation for details
+          tlm,trusted-foundations device tree binding documentation for details
          on how to use it.
          Say n if you don't know what this is about.
diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c
index ef1e3d8f4af0..3fb1b5a1dce9 100644
--- a/arch/arm/firmware/trusted_foundations.c
+++ b/arch/arm/firmware/trusted_foundations.c
@@ -22,6 +22,15 @@
 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
+#define TF_CPU_PM               0xfffffffc
+#define TF_CPU_PM_S3            0xffffffe3
+#define TF_CPU_PM_S2            0xffffffe6
+#define TF_CPU_PM_S2_NO_MC_CLK  0xffffffe5
+#define TF_CPU_PM_S1            0xffffffe4
+#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
+static unsigned long cpu_boot_addr;
 static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
 {
        asm volatile(
@@ -41,13 +50,22 @@ static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
 static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
-        tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0);
+        cpu_boot_addr = boot_addr;
+        tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
+        return 0;
+}
+static int tf_prepare_idle(void)
+{
+        tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr);
        return 0;
 }
 static const struct firmware_ops trusted_foundations_ops = {
        .set_cpu_boot_addr = tf_set_cpu_boot_addr,
+        .prepare_idle = tf_prepare_idle,
 };
 void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 5c2285160575..b974184f9941 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -23,6 +23,7 @@
 #include <asm/ptrace.h>
 #include <asm/domain.h>
 #include <asm/opcodes-virt.h>
+#include <asm/asm-offsets.h>
 #define IOMEM(x)        (x)
@@ -30,8 +31,8 @@
 * Endian independent macros for shifting bytes within registers.
 */
 #ifndef __ARMEB__
-#define pull            lsr
+#define lspull          lsr
-#define push            lsl
+#define lspush          lsl
 #define get_byte_0      lsl #0
 #define get_byte_1      lsr #8
 #define get_byte_2      lsr #16
@@ -41,8 +42,8 @@
 #define put_byte_2      lsl #16
 #define put_byte_3      lsl #24
 #else
-#define pull            lsl
+#define lspull          lsl
-#define push            lsr
+#define lspush          lsr
 #define get_byte_0      lsr #24
 #define get_byte_1      lsr #16
 #define get_byte_2      lsr #8
@@ -174,6 +175,47 @@
        restore_irqs_notrace \oldcpsr
        .endm
+/*
+ * Get current thread_info.
+ */
+        .macro  get_thread_info, rd
+ ARM(   mov     \rd, sp, lsr #13        )
+ THUMB( mov     \rd, sp                 )
+ THUMB( lsr     \rd, \rd, #13           )
+        mov     \rd, \rd, lsl #13
+        .endm
+/*
+ * Increment/decrement the preempt count.
+ */
+#ifdef CONFIG_PREEMPT_COUNT
+        .macro  inc_preempt_count, ti, tmp
+        ldr     \tmp, [\ti, #TI_PREEMPT]        @ get preempt count
+        add     \tmp, \tmp, #1                  @ increment it
+        str     \tmp, [\ti, #TI_PREEMPT]
+        .endm
+        .macro  dec_preempt_count, ti, tmp
+        ldr     \tmp, [\ti, #TI_PREEMPT]        @ get preempt count
+        sub     \tmp, \tmp, #1                  @ decrement it
+        str     \tmp, [\ti, #TI_PREEMPT]
+        .endm
+        .macro  dec_preempt_count_ti, ti, tmp
+        get_thread_info \ti
+        dec_preempt_count \ti, \tmp
+        .endm
+#else
+        .macro  inc_preempt_count, ti, tmp
+        .endm
+        .macro  dec_preempt_count, ti, tmp
+        .endm
+        .macro  dec_preempt_count_ti, ti, tmp
+        .endm
+#endif
 #define USER(x...)                              \
 9999:   x;                                      \
        .pushsection __ex_table,"a";            \
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 62d2cb53b069..9a92fd7864a8 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -60,6 +60,7 @@ static inline int atomic_add_return(int i, atomic_t *v)
        int result;
        smp_mb();
+        prefetchw(&v->counter);
        __asm__ __volatile__("@ atomic_add_return\n"
 "1:     ldrex   %0, [%3]\n"
@@ -99,6 +100,7 @@ static inline int atomic_sub_return(int i, atomic_t *v)
        int result;
        smp_mb();
+        prefetchw(&v->counter);
        __asm__ __volatile__("@ atomic_sub_return\n"
 "1:     ldrex   %0, [%3]\n"
@@ -121,6 +123,7 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
        unsigned long res;
        smp_mb();
+        prefetchw(&ptr->counter);
        do {
                __asm__ __volatile__("@ atomic_cmpxchg\n"
@@ -138,6 +141,33 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
        return oldval;
 }
+static inline int __atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int oldval, newval;
+        unsigned long tmp;
+        smp_mb();
+        prefetchw(&v->counter);
+        __asm__ __volatile__ ("@ atomic_add_unless\n"
+"1:     ldrex   %0, [%4]\n"
+"       teq     %0, %5\n"
+"       beq     2f\n"
+"       add     %1, %0, %6\n"
+"       strex   %2, %1, [%4]\n"
+"       teq     %2, #0\n"
+"       bne     1b\n"
+"2:"
+        : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
+        : "r" (&v->counter), "r" (u), "r" (a)
+        : "cc");
+        if (oldval != u)
+                smp_mb();
+        return oldval;
+}
 #else /* ARM_ARCH_6 */
 #ifdef CONFIG_SMP
@@ -186,10 +216,6 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
        return ret;
 }
-#endif /* __LINUX_ARM_ARCH__ */
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
 {
        int c, old;
@@ -200,6 +226,10 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
        return c;
 }
+#endif /* __LINUX_ARM_ARCH__ */
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 #define atomic_inc(v)           atomic_add(1, v)
 #define atomic_dec(v)           atomic_sub(1, v)
@@ -299,6 +329,7 @@ static inline long long atomic64_add_return(long long i, atomic64_t *v)
        unsigned long tmp;
        smp_mb();
+        prefetchw(&v->counter);
        __asm__ __volatile__("@ atomic64_add_return\n"
 "1:     ldrexd  %0, %H0, [%3]\n"
@@ -340,6 +371,7 @@ static inline long long atomic64_sub_return(long long i, atomic64_t *v)
        unsigned long tmp;
        smp_mb();
+        prefetchw(&v->counter);
        __asm__ __volatile__("@ atomic64_sub_return\n"
 "1:     ldrexd  %0, %H0, [%3]\n"
@@ -364,6 +396,7 @@ static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old,
        unsigned long res;
        smp_mb();
+        prefetchw(&ptr->counter);
        do {
                __asm__ __volatile__("@ atomic64_cmpxchg\n"
@@ -388,6 +421,7 @@ static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
        unsigned long tmp;
        smp_mb();
+        prefetchw(&ptr->counter);
        __asm__ __volatile__("@ atomic64_xchg\n"
 "1:     ldrexd  %0, %H0, [%3]\n"
@@ -409,6 +443,7 @@ static inline long long atomic64_dec_if_positive(atomic64_t *v)
        unsigned long tmp;
        smp_mb();
+        prefetchw(&v->counter);
        __asm__ __volatile__("@ atomic64_dec_if_positive\n"
 "1:     ldrexd  %0, %H0, [%3]\n"
@@ -436,6 +471,7 @@ static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
        int ret = 1;
        smp_mb();
+        prefetchw(&v->counter);
        __asm__ __volatile__("@ atomic64_add_unless\n"
 "1:     ldrexd  %0, %H0, [%4]\n"
diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index df2fbba7efc8..abb2c3769b01 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -2,6 +2,7 @@
 #define __ASM_ARM_CMPXCHG_H
 #include <linux/irqflags.h>
+#include <linux/prefetch.h>
 #include <asm/barrier.h>
 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
@@ -35,6 +36,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
 #endif
        smp_mb();
+        prefetchw((const void *)ptr);
        switch (size) {
 #if __LINUX_ARM_ARCH__ >= 6
@@ -138,6 +140,8 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
 {
        unsigned long oldval, res;
+        prefetchw((const void *)ptr);
        switch (size) {
 #ifndef CONFIG_CPU_V6   /* min ARCH >= ARMv6K */
        case 1:
@@ -230,6 +234,8 @@ static inline unsigned long long __cmpxchg64(unsigned long long *ptr,
        unsigned long long oldval;
        unsigned long res;
+        prefetchw(ptr);
        __asm__ __volatile__(
 "1:     ldrexd          %1, %H1, [%3]\n"
 "       teq             %1, %4\n"
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index acdde76b39bb..c651e3b26ec7 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -71,6 +71,7 @@
 #define ARM_CPU_PART_CORTEX_A5          0xC050
 #define ARM_CPU_PART_CORTEX_A15         0xC0F0
 #define ARM_CPU_PART_CORTEX_A7          0xC070
+#define ARM_CPU_PART_CORTEX_A12         0xC0D0
 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
@@ -220,4 +221,23 @@ static inline int cpu_is_xsc3(void)
 #define cpu_is_xscale() 1
 #endif
+/*
+ * Marvell's PJ4 core is based on V7 version. It has some modification
+ * for coprocessor setting. For this reason, we need a way to distinguish
+ * it.
+ */
+#ifndef CONFIG_CPU_PJ4
+#define cpu_is_pj4()    0
+#else
+static inline int cpu_is_pj4(void)
+{
+        unsigned int id;
+        id = read_cpuid_id();
+        if ((id & 0xfffffff0) == 0x562f5840)
+                return 1;
+        return 0;
+}
+#endif
 #endif
diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h
index a8c56acc8c98..eec0a12c5c1d 100644
--- a/arch/arm/include/asm/dma-iommu.h
+++ b/arch/arm/include/asm/dma-iommu.h
@@ -13,9 +13,12 @@ struct dma_iommu_mapping {
        /* iommu specific data */
        struct iommu_domain     *domain;
-        void                    *bitmap;
+        unsigned long           **bitmaps;      /* array of bitmaps */
-        size_t                  bits;
+        unsigned int            nr_bitmaps;     /* nr of elements in array */
-        unsigned int            order;
+        unsigned int            extensions;
+        size_t                  bitmap_size;    /* size of a single bitmap */
+        size_t                  bits;           /* per bitmap */
+        unsigned int            size;           /* per bitmap */
        dma_addr_t              base;
        spinlock_t              lock;
@@ -23,8 +26,7 @@ struct dma_iommu_mapping {
 };
 struct dma_iommu_mapping *
-arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
+arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size);
-                         int order);
 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping);
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
index 15631300c238..2c9f10df7568 100644
--- a/arch/arm/include/asm/firmware.h
+++ b/arch/arm/include/asm/firmware.h
@@ -22,6 +22,10 @@
 */
 struct firmware_ops {
        /*
+         * Inform the firmware we intend to enter CPU idle mode
+         */
+        int (*prepare_idle)(void);
+        /*
         * Enters CPU idle mode
         */
        int (*do_idle)(void);
diff --git a/arch/arm/include/asm/floppy.h b/arch/arm/include/asm/floppy.h
index c9f03eccc9d8..f4882553fbb0 100644
--- a/arch/arm/include/asm/floppy.h
+++ b/arch/arm/include/asm/floppy.h
@@ -25,7 +25,7 @@
 #define fd_inb(port)            inb((port))
 #define fd_request_irq()        request_irq(IRQ_FLOPPYDISK,floppy_interrupt,\
-                                            IRQF_DISABLED,"floppy",NULL)
+                                            0,"floppy",NULL)
 #define fd_free_irq()           free_irq(IRQ_FLOPPYDISK,NULL)
 #define fd_disable_irq()        disable_irq(IRQ_FLOPPYDISK)
 #define fd_enable_irq()         enable_irq(IRQ_FLOPPYDISK)
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index e42cf597f6e6..53e69dae796f 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -3,11 +3,6 @@
 #ifdef __KERNEL__
-#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP)
-/* ARM doesn't provide unprivileged exclusive memory accessors */
-#include <asm-generic/futex.h>
-#else
 #include <linux/futex.h>
 #include <linux/uaccess.h>
 #include <asm/errno.h>
@@ -28,6 +23,7 @@
 #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
        smp_mb();                                               \
+        prefetchw(uaddr);                                       \
        __asm__ __volatile__(                                   \
        "1:     ldrex   %1, [%3]\n"                             \
        "       " insn "\n"                                     \
@@ -51,6 +47,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                return -EFAULT;
        smp_mb();
+        /* Prefetching cannot fault */
+        prefetchw(uaddr);
        __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
        "1:     ldrex   %1, [%4]\n"
        "       teq     %1, %2\n"
@@ -164,6 +162,5 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
        return ret;
 }
-#endif /* !(CPU_USE_DOMAINS && SMP) */
 #endif /* __KERNEL__ */
 #endif /* _ASM_ARM_FUTEX_H */
diff --git a/arch/arm/plat-orion/include/plat/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
index 06f982d55697..12e1588dc4f1 100644
--- a/arch/arm/plat-orion/include/plat/cache-feroceon-l2.h
+++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-orion/include/plat/cache-feroceon-l2.h
+ * arch/arm/include/asm/hardware/cache-feroceon-l2.h
 *
 * Copyright (C) 2008 Marvell Semiconductor
 *
@@ -9,3 +9,5 @@
 */
 extern void __init feroceon_l2_init(int l2_wt_override);
+extern int __init feroceon_of_init(void);
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index eef55ea9ef00..8e427c7b4425 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -51,6 +51,7 @@ static inline void decode_ctrl_reg(u32 reg,
 #define ARM_DEBUG_ARCH_V7_ECP14 3
 #define ARM_DEBUG_ARCH_V7_MM    4
 #define ARM_DEBUG_ARCH_V7_1     5
+#define ARM_DEBUG_ARCH_V8       6
 /* Breakpoint */
 #define ARM_BREAKPOINT_EXECUTE  0
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index 6ff56eca3f1f..6e183fd269fb 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -9,6 +9,7 @@
 * instruction set this cpu supports.
 */
 #define ELF_HWCAP       (elf_hwcap)
-extern unsigned int elf_hwcap;
+#define ELF_HWCAP2      (elf_hwcap2)
+extern unsigned int elf_hwcap, elf_hwcap2;
 #endif
 #endif
diff --git a/arch/arm/include/asm/jump_label.h b/arch/arm/include/asm/jump_label.h
index 863c892b4aaa..70f9b9bfb1f9 100644
--- a/arch/arm/include/asm/jump_label.h
+++ b/arch/arm/include/asm/jump_label.h
@@ -4,7 +4,6 @@
 #ifdef __KERNEL__
 #include <linux/types.h>
-#include <asm/system.h>
 #define JUMP_LABEL_NOP_SIZE 4
diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h
index f82ec22eeb11..49fa0dfaad33 100644
--- a/arch/arm/include/asm/kprobes.h
+++ b/arch/arm/include/asm/kprobes.h
@@ -18,7 +18,7 @@
 #include <linux/types.h>
 #include <linux/ptrace.h>
-#include <linux/percpu.h>
+#include <linux/notifier.h>
 #define __ARCH_WANT_KPROBES_INSN_SLOT
 #define MAX_INSN_SIZE                   2
@@ -28,21 +28,10 @@
 #define kretprobe_blacklist_size        0
 typedef u32 kprobe_opcode_t;
 struct kprobe;
-typedef void (kprobe_insn_handler_t)(struct kprobe *, struct pt_regs *);
+#include <asm/probes.h>
-typedef unsigned long (kprobe_check_cc)(unsigned long);
-typedef void (kprobe_insn_singlestep_t)(struct kprobe *, struct pt_regs *);
-typedef void (kprobe_insn_fn_t)(void);
-/* Architecture specific copy of original instruction. */
+#define arch_specific_insn      arch_probes_insn
-struct arch_specific_insn {
-        kprobe_opcode_t                 *insn;
-        kprobe_insn_handler_t           *insn_handler;
-        kprobe_check_cc                 *insn_check_cc;
-        kprobe_insn_singlestep_t        *insn_singlestep;
-        kprobe_insn_fn_t                *insn_fn;
-};
 struct prev_kprobe {
        struct kprobe *kp;
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 1d3153c7eb41..816db0bf2dd8 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -55,6 +55,7 @@
 * The bits we set in HCR:
 * TAC:         Trap ACTLR
 * TSC:         Trap SMC
+ * TVM:         Trap VM ops (until MMU and caches are on)
 * TSW:         Trap cache operations by set/way
 * TWI:         Trap WFI
 * TWE:         Trap WFE
@@ -68,8 +69,7 @@
 */
 #define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
                        HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
-                        HCR_TWE | HCR_SWIO | HCR_TIDCP)
+                        HCR_TVM | HCR_TWE | HCR_SWIO | HCR_TIDCP)
-#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
 /* System Control Register (SCTLR) bits */
 #define SCTLR_TE        (1 << 30)
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 661da11f76f4..53b3c4a50d5c 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -48,7 +48,9 @@
 #define c13_TID_URO     26      /* Thread ID, User R/O */
 #define c13_TID_PRIV    27      /* Thread ID, Privileged */
 #define c14_CNTKCTL     28      /* Timer Control Register (PL1) */
-#define NR_CP15_REGS    29      /* Number of regs (incl. invalid) */
+#define c10_AMAIR0      29      /* Auxilary Memory Attribute Indirection Reg0 */
+#define c10_AMAIR1      30      /* Auxilary Memory Attribute Indirection Reg1 */
+#define NR_CP15_REGS    31      /* Number of regs (incl. invalid) */
 #define ARM_EXCEPTION_RESET       0
 #define ARM_EXCEPTION_UNDEFINED   1
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 098f7dd6d564..09af14999c9b 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -101,6 +101,12 @@ struct kvm_vcpu_arch {
        /* The CPU type we expose to the VM */
        u32 midr;
+        /* HYP trapping configuration */
+        u32 hcr;
+        /* Interrupt related fields */
+        u32 irq_lines;          /* IRQ and FIQ levels */
        /* Exception Information */
        struct kvm_vcpu_fault_info fault;
@@ -128,9 +134,6 @@ struct kvm_vcpu_arch {
        /* IO related fields */
        struct kvm_decode mmio_decode;
-        /* Interrupt related fields */
-        u32 irq_lines;          /* IRQ and FIQ levels */
        /* Cache some mmu pages needed inside spinlock regions */
        struct kvm_mmu_memory_cache mmu_page_cache;
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 2d122adcdb22..5c7aa3c1519f 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -114,11 +114,34 @@ static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
        pmd_val(*pmd) |= L_PMD_S2_RDWR;
 }
+/* Open coded p*d_addr_end that can deal with 64bit addresses */
+#define kvm_pgd_addr_end(addr, end)                                     \
+({      u64 __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK;            \
+        (__boundary - 1 < (end) - 1)? __boundary: (end);                \
+})
+#define kvm_pud_addr_end(addr,end)              (end)
+#define kvm_pmd_addr_end(addr, end)                                     \
+({      u64 __boundary = ((addr) + PMD_SIZE) & PMD_MASK;                \
+        (__boundary - 1 < (end) - 1)? __boundary: (end);                \
+})
 struct kvm;
-static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva,
+#define kvm_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))
-                                              unsigned long size)
+static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
 {
+        return (vcpu->arch.cp15[c1_SCTLR] & 0b101) == 0b101;
+}
+static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
+                                             unsigned long size)
+{
+        if (!vcpu_has_cache_enabled(vcpu))
+                kvm_flush_dcache_to_poc((void *)hva, size);
+        
        /*
         * If we are going to insert an instruction page and the icache is
         * either VIPT or PIPT, there is a potential problem where the host
@@ -139,9 +162,10 @@ static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva,
        }
 }
-#define kvm_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))
 #define kvm_virt_to_phys(x)             virt_to_idmap((unsigned long)(x))
+void stage2_flush_vm(struct kvm *kvm);
 #endif  /* !__ASSEMBLY__ */
 #endif /* __ARM_KVM_MMU_H__ */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 4afb376d9c7c..02fa2558f662 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -166,9 +166,17 @@
 * Physical vs virtual RAM address space conversion.  These are
 * private definitions which should NOT be used outside memory.h
 * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
+ *
+ * PFNs are used to describe any physical page; this means
+ * PFN 0 == physical address 0.
 */
-#ifndef __virt_to_phys
+#if defined(__virt_to_phys)
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
+#define PHYS_OFFSET     PLAT_PHYS_OFFSET
+#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
+#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
+#elif defined(CONFIG_ARM_PATCH_PHYS_VIRT)
 /*
 * Constants used to force the right instruction encodings and shifts
@@ -177,12 +185,17 @@
 #define __PV_BITS_31_24 0x81000000
 #define __PV_BITS_7_0   0x81
-extern u64 __pv_phys_offset;
+extern unsigned long __pv_phys_pfn_offset;
 extern u64 __pv_offset;
 extern void fixup_pv_table(const void *, unsigned long);
 extern const void *__pv_table_begin, *__pv_table_end;
-#define PHYS_OFFSET __pv_phys_offset
+#define PHYS_OFFSET     ((phys_addr_t)__pv_phys_pfn_offset << PAGE_SHIFT)
+#define PHYS_PFN_OFFSET (__pv_phys_pfn_offset)
+#define virt_to_pfn(kaddr) \
+        ((((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT) + \
+         PHYS_PFN_OFFSET)
 #define __pv_stub(from,to,instr,type)                   \
        __asm__("@ __pv_stub\n"                         \
@@ -243,6 +256,7 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
 #else
 #define PHYS_OFFSET     PLAT_PHYS_OFFSET
+#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
 static inline phys_addr_t __virt_to_phys(unsigned long x)
 {
@@ -254,18 +268,11 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
        return x - PHYS_OFFSET + PAGE_OFFSET;
 }
-#endif
+#define virt_to_pfn(kaddr) \
-#endif
+        ((((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT) + \
+         PHYS_PFN_OFFSET)
-/*
+#endif
- * PFNs are used to describe any physical page; this means
- * PFN 0 == physical address 0.
- *
- * This is the PFN of the first RAM page in the kernel
- * direct-mapped view.  We assume this is the first page
- * of RAM in the mem_map as well.
- */
-#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
 /*
 * These are *only* valid on the kernel direct mapped RAM memory.
@@ -343,9 +350,9 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 */
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
-#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define virt_to_page(kaddr)     pfn_to_page(virt_to_pfn(kaddr))
 #define virt_addr_valid(kaddr)  (((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) \
-                                        && pfn_valid(__pa(kaddr) >> PAGE_SHIFT) )
+                                        && pfn_valid(virt_to_pfn(kaddr)))
 #endif
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index dfff709fda3c..219ac88a9542 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -140,6 +140,7 @@
 #define L_PTE_MT_DEV_NONSHARED  (_AT(pteval_t, 0x0c) << 2)      /* 1100 */
 #define L_PTE_MT_DEV_WC         (_AT(pteval_t, 0x09) << 2)      /* 1001 */
 #define L_PTE_MT_DEV_CACHED     (_AT(pteval_t, 0x0b) << 2)      /* 1011 */
+#define L_PTE_MT_VECTORS        (_AT(pteval_t, 0x0f) << 2)      /* 1111 */
 #define L_PTE_MT_MASK           (_AT(pteval_t, 0x0f) << 2)
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 7d59b524f2af..5478e5d6ad89 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -216,13 +216,16 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 #define pte_none(pte)           (!pte_val(pte))
 #define pte_present(pte)        (pte_val(pte) & L_PTE_PRESENT)
+#define pte_valid(pte)          (pte_val(pte) & L_PTE_VALID)
+#define pte_accessible(mm, pte) (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
 #define pte_write(pte)          (!(pte_val(pte) & L_PTE_RDONLY))
 #define pte_dirty(pte)          (pte_val(pte) & L_PTE_DIRTY)
 #define pte_young(pte)          (pte_val(pte) & L_PTE_YOUNG)
 #define pte_exec(pte)           (!(pte_val(pte) & L_PTE_XN))
 #define pte_special(pte)        (0)
-#define pte_present_user(pte)  (pte_present(pte) && (pte_val(pte) & L_PTE_USER))
+#define pte_valid_user(pte)     \
+        (pte_valid(pte) && (pte_val(pte) & L_PTE_USER) && pte_young(pte))
 #if __LINUX_ARM_ARCH__ < 6
 static inline void __sync_icache_dcache(pte_t pteval)
@@ -237,7 +240,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 {
        unsigned long ext = 0;
-        if (addr < TASK_SIZE && pte_present_user(pteval)) {
+        if (addr < TASK_SIZE && pte_valid_user(pteval)) {
                __sync_icache_dcache(pteval);
                ext |= PTE_EXT_NG;
        }
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index f24edad26c70..ae1919be8f98 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -71,6 +71,8 @@ struct arm_pmu {
        void            (*disable)(struct perf_event *event);
        int             (*get_event_idx)(struct pmu_hw_events *hw_events,
                                         struct perf_event *event);
+        void            (*clear_event_idx)(struct pmu_hw_events *hw_events,
+                                         struct perf_event *event);
        int             (*set_event_filter)(struct hw_perf_event *evt,
                                            struct perf_event_attr *attr);
        u32             (*read_counter)(struct perf_event *event);
diff --git a/arch/arm/include/asm/probes.h b/arch/arm/include/asm/probes.h
new file mode 100644
index 000000000000..806cfe622a9e
--- /dev/null
+++ b/arch/arm/include/asm/probes.h
@@ -0,0 +1,43 @@
+/*
+ * arch/arm/include/asm/probes.h
+ *
+ * Original contents copied from arch/arm/include/asm/kprobes.h
+ * which contains the following notice...
+ *
+ * Copyright (C) 2006, 2007 Motorola Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+#ifndef _ASM_PROBES_H
+#define _ASM_PROBES_H
+typedef u32 probes_opcode_t;
+struct arch_probes_insn;
+typedef void (probes_insn_handler_t)(probes_opcode_t,
+                                     struct arch_probes_insn *,
+                                     struct pt_regs *);
+typedef unsigned long (probes_check_cc)(unsigned long);
+typedef void (probes_insn_singlestep_t)(probes_opcode_t,
+                                        struct arch_probes_insn *,
+                                        struct pt_regs *);
+typedef void (probes_insn_fn_t)(void);
+/* Architecture specific copy of original instruction. */
+struct arch_probes_insn {
+        probes_opcode_t                 *insn;
+        probes_insn_handler_t           *insn_handler;
+        probes_check_cc                 *insn_check_cc;
+        probes_insn_singlestep_t        *insn_singlestep;
+        probes_insn_fn_t                *insn_fn;
+};
+#endif
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 04c99f36ff7f..c877654fe3bf 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -27,9 +27,13 @@ struct pt_regs {
 #define thumb_mode(regs) (0)
 #endif
+#ifndef CONFIG_CPU_V7M
 #define isa_mode(regs) \
-        ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
+        ((((regs)->ARM_cpsr & PSR_J_BIT) >> (__ffs(PSR_J_BIT) - 1)) | \
-         (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
+         (((regs)->ARM_cpsr & PSR_T_BIT) >> (__ffs(PSR_T_BIT))))
+#else
+#define isa_mode(regs) 1 /* Thumb */
+#endif
 #define processor_mode(regs) \
        ((regs)->ARM_cpsr & MODE_MASK)
@@ -80,6 +84,12 @@ static inline long regs_return_value(struct pt_regs *regs)
 #define instruction_pointer(regs)       (regs)->ARM_pc
+static inline void instruction_pointer_set(struct pt_regs *regs,
+                                           unsigned long val)
+{
+        instruction_pointer(regs) = val;
+}
 #ifdef CONFIG_SMP
 extern unsigned long profile_pc(struct pt_regs *regs);
 #else
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 22a3b9b5d4a1..2ec765c39ab4 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -74,6 +74,7 @@ struct secondary_data {
 };
 extern struct secondary_data secondary_data;
 extern volatile int pen_release;
+extern void secondary_startup(void);
 extern int __cpu_disable(void);
@@ -114,6 +115,15 @@ struct smp_operations {
 #endif
 };
+struct of_cpu_method {
+        const char *method;
+        struct smp_operations *ops;
+};
+#define CPU_METHOD_OF_DECLARE(name, _method, _ops)                      \
+        static const struct of_cpu_method __cpu_method_of_table_##name  \
+                __used __section(__cpu_method_of_table)                 \
+                = { .method = _method, .ops = _ops }
 /*
 * set platform specific SMP operations
 */
diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h
index 63479eecbf76..9732b8e11e63 100644
--- a/arch/arm/include/asm/sync_bitops.h
+++ b/arch/arm/include/asm/sync_bitops.h
@@ -2,7 +2,6 @@
 #define __ASM_SYNC_BITOPS_H__
 #include <asm/bitops.h>
-#include <asm/system.h>
 /* sync_bitops functions are equivalent to the SMP implementation of the
 * original functions, independently from CONFIG_SMP being defined.
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index 73ddd7239b33..4651f6999b7d 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -7,7 +7,7 @@
 #ifndef _ASM_ARM_SYSCALL_H
 #define _ASM_ARM_SYSCALL_H
-#include <linux/audit.h> /* for AUDIT_ARCH_* */
+#include <uapi/linux/audit.h> /* for AUDIT_ARCH_* */
 #include <linux/elf.h> /* for ELF_EM */
 #include <linux/err.h>
 #include <linux/sched.h>
@@ -103,8 +103,7 @@ static inline void syscall_set_arguments(struct task_struct *task,
        memcpy(&regs->ARM_r0 + i, args, n * sizeof(args[0]));
 }
-static inline int syscall_get_arch(struct task_struct *task,
+static inline int syscall_get_arch(void)
-                                   struct pt_regs *regs)
 {
        /* ARM tasks don't change audit architectures on the fly. */
        return AUDIT_ARCH_ARM;
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
deleted file mode 100644
index 368165e33c1c..000000000000
--- a/arch/arm/include/asm/system.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
-#include <asm/barrier.h>
-#include <asm/compiler.h>
-#include <asm/cmpxchg.h>
-#include <asm/switch_to.h>
-#include <asm/system_info.h>
-#include <asm/system_misc.h>
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 71a06b293489..f989d7c22dc5 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -153,6 +153,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_SIGPENDING          0
 #define TIF_NEED_RESCHED        1
 #define TIF_NOTIFY_RESUME       2       /* callback before returning to user */
+#define TIF_UPROBE              7
 #define TIF_SYSCALL_TRACE       8
 #define TIF_SYSCALL_AUDIT       9
 #define TIF_SYSCALL_TRACEPOINT  10
@@ -165,6 +166,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
 #define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
+#define _TIF_UPROBE             (1 << TIF_UPROBE)
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
 #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
@@ -178,7 +180,8 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 /*
 * Change these and you break ASM code in entry-common.S
 */
-#define _TIF_WORK_MASK          (_TIF_NEED_RESCHED | _TIF_SIGPENDING | _TIF_NOTIFY_RESUME)
+#define _TIF_WORK_MASK          (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
+                                 _TIF_NOTIFY_RESUME | _TIF_UPROBE)
 #endif /* __KERNEL__ */
 #endif /* __ASM_ARM_THREAD_INFO_H */
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index 83f2aa83899c..f6fcc67ef06e 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,12 +12,6 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
-#ifdef CONFIG_ARCH_MULTIPLATFORM
-#define CLOCK_TICK_RATE 1000000
-#else
-#include <mach/timex.h>
-#endif
 typedef unsigned long cycles_t;
 #define get_cycles()    ({ cycles_t c; read_current_timer(&c) ? 0 : c; })
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h
index 3bd36e2c5f2e..b5f7705abcb0 100644
--- a/arch/arm/include/asm/trusted_foundations.h
+++ b/arch/arm/include/asm/trusted_foundations.h
@@ -30,6 +30,8 @@
 #include <linux/printk.h>
 #include <linux/bug.h>
 #include <linux/of.h>
+#include <linux/cpu.h>
+#include <linux/smp.h>
 struct trusted_foundations_platform_data {
        unsigned int version_major;
@@ -47,10 +49,13 @@ static inline void register_trusted_foundations(
                                   struct trusted_foundations_platform_data *pd)
 {
        /*
-         * If we try to register TF, this means the system needs it to continue.
+         * If the system requires TF and we cannot provide it, continue booting
-         * Its absence if thus a fatal error.
+         * but disable features that cannot be provided.
         */
-        panic("No support for Trusted Foundations, stopping...\n");
+        pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
+        pr_err("Secondary processors as well as CPU PM will be disabled.\n");
+        setup_max_cpus = 0;
+        cpu_idle_poll_ctrl(true);
 }
 static inline void of_register_trusted_foundations(void)
@@ -59,7 +64,7 @@ static inline void of_register_trusted_foundations(void)
         * If we find the target should enable TF but does not support it,
         * fail as the system won't be able to do much anyway
         */
-        if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations"))
+        if (of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations"))
                register_trusted_foundations(NULL);
 }
 #endif /* CONFIG_TRUSTED_FOUNDATIONS */
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 72abdc541f38..12c3a5decc60 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -19,7 +19,7 @@
 #include <asm/unified.h>
 #include <asm/compiler.h>
-#if __LINUX_ARM_ARCH__ < 6
+#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 #include <asm-generic/uaccess-unaligned.h>
 #else
 #define __get_user_unaligned __get_user
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index acabef1a75df..43876245fc57 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -48,6 +48,5 @@
 */
 #define __IGNORE_fadvise64_64
 #define __IGNORE_migrate_pages
-#define __IGNORE_kcmp
 #endif /* __ASM_ARM_UNISTD_H */
diff --git a/arch/arm/include/asm/uprobes.h b/arch/arm/include/asm/uprobes.h
new file mode 100644
index 000000000000..9472c20b7d49
--- /dev/null
+++ b/arch/arm/include/asm/uprobes.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2012 Rabin Vincent <rabin at rab.in>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASM_UPROBES_H
+#define _ASM_UPROBES_H
+#include <asm/probes.h>
+#include <asm/opcodes.h>
+typedef u32 uprobe_opcode_t;
+#define MAX_UINSN_BYTES         4
+#define UPROBE_XOL_SLOT_BYTES   64
+#define UPROBE_SWBP_ARM_INSN    0xe7f001f9
+#define UPROBE_SS_ARM_INSN      0xe7f001fa
+#define UPROBE_SWBP_INSN        __opcode_to_mem_arm(UPROBE_SWBP_ARM_INSN)
+#define UPROBE_SWBP_INSN_SIZE   4
+struct arch_uprobe_task {
+        u32 backup;
+        unsigned long   saved_trap_no;
+};
+struct arch_uprobe {
+        u8 insn[MAX_UINSN_BYTES];
+        unsigned long ixol[2];
+        uprobe_opcode_t bpinsn;
+        bool simulate;
+        u32 pcreg;
+        void (*prehandler)(struct arch_uprobe *auprobe,
+                           struct arch_uprobe_task *autask,
+                           struct pt_regs *regs);
+        void (*posthandler)(struct arch_uprobe *auprobe,
+                            struct arch_uprobe_task *autask,
+                            struct pt_regs *regs);
+        struct arch_probes_insn asi;
+};
+#endif
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index e0965abacb7d..cf4f3e867395 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -97,16 +97,13 @@ static inline pte_t *lookup_address(unsigned long address, unsigned int *level)
        return NULL;
 }
-static inline int m2p_add_override(unsigned long mfn, struct page *page,
+extern int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops,
-                struct gnttab_map_grant_ref *kmap_op)
+                                   struct gnttab_map_grant_ref *kmap_ops,
-{
+                                   struct page **pages, unsigned int count);
-        return 0;
-}
-static inline int m2p_remove_override(struct page *page, bool clear_pte)
+extern int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops,
-{
+                                     struct gnttab_map_grant_ref *kmap_ops,
-        return 0;
+                                     struct page **pages, unsigned int count);
-}
 bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn);
 bool __set_phys_to_machine_multi(unsigned long pfn, unsigned long mfn,
diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S
index f3a9cff6d5d4..8d8d922e5e44 100644
--- a/arch/arm/include/debug/samsung.S
+++ b/arch/arm/include/debug/samsung.S
@@ -9,7 +9,7 @@
 * published by the Free Software Foundation.
 */
-#include <plat/regs-serial.h>
+#include <linux/serial_s3c.h>
 /* The S5PV210/S5PC110 implementations are as belows. */
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
index f98763f0bc17..3bc80599c022 100644
--- a/arch/arm/include/debug/tegra.S
+++ b/arch/arm/include/debug/tegra.S
@@ -53,8 +53,7 @@
 #define checkuart(rp, rv, lhu, bit, uart) \
                /* Load address of CLK_RST register */ \
-                movw    rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
+                ldr     rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \
-                movt    rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
                /* Load value from CLK_RST register */ \
                ldr     rp, [rp, #0] ; \
                /* Test UART's reset bit */ \
@@ -62,8 +61,7 @@
                /* If set, can't use UART; jump to save no UART */ \
                bne     90f ; \
                /* Load address of CLK_OUT_ENB register */ \
-                movw    rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
+                ldr     rp, =TEGRA_CLK_OUT_ENB_##lhu ; \
-                movt    rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
                /* Load value from CLK_OUT_ENB register */ \
                ldr     rp, [rp, #0] ; \
                /* Test UART's clock enable bit */ \
@@ -71,8 +69,7 @@
                /* If clear, can't use UART; jump to save no UART */ \
                beq     90f ; \
                /* Passed all tests, load address of UART registers */ \
-                movw    rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
+                ldr     rp, =TEGRA_UART##uart##_BASE ; \
-                movt    rp, #TEGRA_UART##uart##_BASE >> 16 ; \
                /* Jump to save UART address */ \
                b 91f
@@ -90,15 +87,16 @@
 #ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
                /* Check ODMDATA */
-10:             movw    \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
+10:             ldr     \rp, =TEGRA_PMC_SCRATCH20
-                movt    \rp, #TEGRA_PMC_SCRATCH20 >> 16
                ldr     \rp, [\rp, #0]          @ Load PMC_SCRATCH20
-                ubfx    \rv, \rp, #18, #2       @ 19:18 are console type
+                lsr     \rv, \rp, #18           @ 19:18 are console type
+                and     \rv, \rv, #3
                cmp     \rv, #2                 @ 2 and 3 mean DCC, UART
                beq     11f                     @ some boards swap the meaning
                cmp     \rv, #3                 @ so accept either
                bne     90f
-11:             ubfx    \rv, \rp, #15, #3       @ 17:15 are UART ID
+11:             lsr     \rv, \rp, #15           @ 17:15 are UART ID
+                and     \rv, #7 
                cmp     \rv, #0                 @ UART 0?
                beq     20f
                cmp     \rv, #1                 @ UART 1?
diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S
index f9aa9740a73f..0b762fafa758 100644
--- a/arch/arm/include/debug/zynq.S
+++ b/arch/arm/include/debug/zynq.S
@@ -42,6 +42,9 @@
                .endm
                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #UART_SR_OFFSET]
+                tst     \rd, #UART_SR_TXEMPTY
+                beq     1001b
                .endm
                .macro  busyuart,rd,rx
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 7dcc10d67253..20d12f230a2f 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -28,4 +28,13 @@
 #define HWCAP_LPAE      (1 << 20)
 #define HWCAP_EVTSTRM   (1 << 21)
+/*
+ * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
+ */
+#define HWCAP2_AES      (1 << 0)
+#define HWCAP2_PMULL    (1 << 1)
+#define HWCAP2_SHA1     (1 << 2)
+#define HWCAP2_SHA2     (1 << 3)
+#define HWCAP2_CRC32    (1 << 4)
 #endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index a30fc9be9e9e..a766bcbaf8ad 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -50,11 +50,12 @@ obj-$(CONFIG_DYNAMIC_FTRACE)	+= ftrace.o insn.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)     += ftrace.o insn.o
 obj-$(CONFIG_JUMP_LABEL)        += jump_label.o insn.o patch.o
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
-obj-$(CONFIG_KPROBES)           += kprobes.o kprobes-common.o patch.o
+obj-$(CONFIG_UPROBES)           += probes.o probes-arm.o uprobes.o uprobes-arm.o
+obj-$(CONFIG_KPROBES)           += probes.o kprobes.o kprobes-common.o patch.o
 ifdef CONFIG_THUMB2_KERNEL
-obj-$(CONFIG_KPROBES)           += kprobes-thumb.o
+obj-$(CONFIG_KPROBES)           += kprobes-thumb.o probes-thumb.o
 else
-obj-$(CONFIG_KPROBES)           += kprobes-arm.o
+obj-$(CONFIG_KPROBES)           += kprobes-arm.o probes-arm.o
 endif
 obj-$(CONFIG_ARM_KPROBES_TEST)  += test-kprobes.o
 test-kprobes-objs               := kprobes-test.o
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 85e664b6a5f1..f7b450f97e68 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -158,6 +158,6 @@ EXPORT_SYMBOL(__gnu_mcount_nc);
 #endif
 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
-EXPORT_SYMBOL(__pv_phys_offset);
+EXPORT_SYMBOL(__pv_phys_pfn_offset);
 EXPORT_SYMBOL(__pv_offset);
 #endif
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index ded041711beb..85598b5d1efd 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -174,6 +174,7 @@ int main(void)
  DEFINE(VCPU_FIQ_REGS,         offsetof(struct kvm_vcpu, arch.regs.fiq_regs));
  DEFINE(VCPU_PC,               offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
  DEFINE(VCPU_CPSR,             offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
+  DEFINE(VCPU_HCR,              offsetof(struct kvm_vcpu, arch.hcr));
  DEFINE(VCPU_IRQ_LINES,        offsetof(struct kvm_vcpu, arch.irq_lines));
  DEFINE(VCPU_HSR,              offsetof(struct kvm_vcpu, arch.fault.hsr));
  DEFINE(VCPU_HxFAR,            offsetof(struct kvm_vcpu, arch.fault.hxfar));
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 317da88ae65b..16d43cd45619 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -19,7 +19,7 @@
 static int debug_pci;
 /*
- * We can't use pci_find_device() here since we are
+ * We can't use pci_get_device() here since we are
 * called from interrupt context.
 */
 static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
@@ -57,13 +57,10 @@ static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, in
 void pcibios_report_status(u_int status_mask, int warn)
 {
-        struct list_head *l;
+        struct pci_bus *bus;
-        list_for_each(l, &pci_root_buses) {
-                struct pci_bus *bus = pci_bus_b(l);
+        list_for_each_entry(bus, &pci_root_buses, node)
                pcibios_bus_report_status(bus, status_mask, warn);
-        }
 }
 /*
@@ -608,41 +605,10 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 */
 int pcibios_enable_device(struct pci_dev *dev, int mask)
 {
-        u16 cmd, old_cmd;
+        if (pci_has_flag(PCI_PROBE_ONLY))
-        int idx;
+                return 0;
-        struct resource *r;
-        pci_read_config_word(dev, PCI_COMMAND, &cmd);
-        old_cmd = cmd;
-        for (idx = 0; idx < 6; idx++) {
-                /* Only set up the requested stuff */
-                if (!(mask & (1 << idx)))
-                        continue;
-                r = dev->resource + idx;
-                if (!r->start && r->end) {
-                        printk(KERN_ERR "PCI: Device %s not available because"
-                               " of resource collisions\n", pci_name(dev));
-                        return -EINVAL;
-                }
-                if (r->flags & IORESOURCE_IO)
-                        cmd |= PCI_COMMAND_IO;
-                if (r->flags & IORESOURCE_MEM)
-                        cmd |= PCI_COMMAND_MEMORY;
-        }
-        /*
-         * Bridges (eg, cardbus bridges) need to be fully enabled
-         */
-        if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
-                cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-        if (cmd != old_cmd) {
+        return pci_enable_resources(dev, mask);
-                printk("PCI: enabling device %s (%04x -> %04x)\n",
-                       pci_name(dev), old_cmd, cmd);
-                pci_write_config_word(dev, PCI_COMMAND, cmd);
-        }
-        return 0;
 }
 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c
index 90c50d4b43f7..5d1286d51154 100644
--- a/arch/arm/kernel/crash_dump.c
+++ b/arch/arm/kernel/crash_dump.c
@@ -39,7 +39,7 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
        if (!csize)
                return 0;
-        vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
+        vaddr = ioremap(__pfn_to_phys(pfn), PAGE_SIZE);
        if (!vaddr)
                return -ENOMEM;
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index f751714d52c1..c7419a585ddc 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -18,6 +18,7 @@
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/smp.h>
 #include <asm/cputype.h>
 #include <asm/setup.h>
@@ -63,6 +64,34 @@ void __init arm_dt_memblock_reserve(void)
        }
 }
+#ifdef CONFIG_SMP
+extern struct of_cpu_method __cpu_method_of_table_begin[];
+extern struct of_cpu_method __cpu_method_of_table_end[];
+static int __init set_smp_ops_by_method(struct device_node *node)
+{
+        const char *method;
+        struct of_cpu_method *m = __cpu_method_of_table_begin;
+        if (of_property_read_string(node, "enable-method", &method))
+                return 0;
+        for (; m < __cpu_method_of_table_end; m++)
+                if (!strcmp(m->method, method)) {
+                        smp_set_ops(m->ops);
+                        return 1;
+                }
+        return 0;
+}
+#else
+static inline int set_smp_ops_by_method(struct device_node *node)
+{
+        return 1;
+}
+#endif
 /*
 * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
 * and builds the cpu logical map array containing MPIDR values related to
@@ -79,6 +108,7 @@ void __init arm_dt_init_cpu_maps(void)
         * read as 0.
         */
        struct device_node *cpu, *cpus;
+        int found_method = 0;
        u32 i, j, cpuidx = 1;
        u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
@@ -150,8 +180,18 @@ void __init arm_dt_init_cpu_maps(void)
                }
                tmp_map[i] = hwid;
+                if (!found_method)
+                        found_method = set_smp_ops_by_method(cpu);
        }
+        /*
+         * Fallback to an enable-method in the cpus node if nothing found in
+         * a cpu node.
+         */
+        if (!found_method)
+                set_smp_ops_by_method(cpus);
        if (!bootcpu_valid) {
                pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
                return;
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 39f89fbd5111..1420725142ca 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -236,11 +236,6 @@
        movs    pc, lr                          @ return & move spsr_svc into cpsr
        .endm
-        .macro  get_thread_info, rd
-        mov     \rd, sp, lsr #13
-        mov     \rd, \rd, lsl #13
-        .endm
        @
        @ 32-bit wide "mov pc, reg"
        @
@@ -306,12 +301,6 @@
        .endm
 #endif  /* ifdef CONFIG_CPU_V7M / else */
-        .macro  get_thread_info, rd
-        mov     \rd, sp
-        lsr     \rd, \rd, #13
-        mov     \rd, \rd, lsl #13
-        .endm
        @
        @ 32-bit wide "mov pc, reg"
        @
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index 34e56647dcee..c108ddcb9ba4 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -156,10 +156,8 @@ int ftrace_make_nop(struct module *mod,
        return ret;
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        *(unsigned long *)data = 0;
        return 0;
 }
 #endif /* CONFIG_DYNAMIC_FTRACE */
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index f5f381d91556..f8c08839edf3 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -584,9 +584,10 @@ __fixup_pv_table:
        subs    r3, r0, r3      @ PHYS_OFFSET - PAGE_OFFSET
        add     r4, r4, r3      @ adjust table start address
        add     r5, r5, r3      @ adjust table end address
-        add     r6, r6, r3      @ adjust __pv_phys_offset address
+        add     r6, r6, r3      @ adjust __pv_phys_pfn_offset address
        add     r7, r7, r3      @ adjust __pv_offset address
-        str     r8, [r6, #LOW_OFFSET]   @ save computed PHYS_OFFSET to __pv_phys_offset
+        mov     r0, r8, lsr #12 @ convert to PFN
+        str     r0, [r6, #LOW_OFFSET]   @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
        strcc   ip, [r7, #HIGH_OFFSET]  @ save to __pv_offset high bits
        mov     r6, r3, lsr #24 @ constant for add/sub instructions
        teq     r3, r6, lsl #24 @ must be 16MiB aligned
@@ -600,7 +601,7 @@ ENDPROC(__fixup_pv_table)
 1:      .long   .
        .long   __pv_table_begin
        .long   __pv_table_end
-2:      .long   __pv_phys_offset
+2:      .long   __pv_phys_pfn_offset
        .long   __pv_offset
        .text
@@ -688,11 +689,11 @@ ENTRY(fixup_pv_table)
 ENDPROC(fixup_pv_table)
        .data
-        .globl  __pv_phys_offset
+        .globl  __pv_phys_pfn_offset
-        .type   __pv_phys_offset, %object
+        .type   __pv_phys_pfn_offset, %object
-__pv_phys_offset:
+__pv_phys_pfn_offset:
-        .quad   0
+        .word   0
-        .size   __pv_phys_offset, . -__pv_phys_offset
+        .size   __pv_phys_pfn_offset, . -__pv_phys_pfn_offset
        .globl  __pv_offset
        .type   __pv_offset, %object
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 3d446605cbf8..4d963fb66e3f 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -167,7 +167,7 @@ static int debug_arch_supported(void)
 /* Can we determine the watchpoint access type from the fsr? */
 static int debug_exception_updates_fsr(void)
 {
-        return 0;
+        return get_debug_arch() >= ARM_DEBUG_ARCH_V8;
 }
 /* Determine number of WRP registers available. */
@@ -257,6 +257,7 @@ static int enable_monitor_mode(void)
                break;
        case ARM_DEBUG_ARCH_V7_ECP14:
        case ARM_DEBUG_ARCH_V7_1:
+        case ARM_DEBUG_ARCH_V8:
                ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
                isb();
                break;
@@ -1072,6 +1073,8 @@ static int __init arch_hw_breakpoint_init(void)
        core_num_brps = get_num_brps();
        core_num_wrps = get_num_wrps();
+        cpu_notifier_register_begin();
        /*
         * We need to tread carefully here because DBGSWENABLE may be
         * driven low on this core and there isn't an architected way to
@@ -1088,6 +1091,7 @@ static int __init arch_hw_breakpoint_init(void)
        if (!cpumask_empty(&debug_err_mask)) {
                core_num_brps = 0;
                core_num_wrps = 0;
+                cpu_notifier_register_done();
                return 0;
        }
@@ -1107,7 +1111,10 @@ static int __init arch_hw_breakpoint_init(void)
                        TRAP_HWBKPT, "breakpoint debug exception");
        /* Register hotplug and PM notifiers. */
-        register_cpu_notifier(&dbg_reset_nb);
+        __register_cpu_notifier(&dbg_reset_nb);
+        cpu_notifier_register_done();
        pm_init();
        return 0;
 }
diff --git a/arch/arm/kernel/kprobes-arm.c b/arch/arm/kernel/kprobes-arm.c
index 8a30c89da70e..ac300c60d656 100644
--- a/arch/arm/kernel/kprobes-arm.c
+++ b/arch/arm/kernel/kprobes-arm.c
@@ -60,13 +60,10 @@
 #include <linux/kernel.h>
 #include <linux/kprobes.h>
-#include <linux/module.h>
+#include <linux/ptrace.h>
 #include "kprobes.h"
+#include "probes-arm.h"
-#define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
-#define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
 #if  __LINUX_ARM_ARCH__ >= 6
 #define BLX(reg)        "blx    "reg"           \n\t"
@@ -75,92 +72,11 @@
                        "mov    pc, "reg"       \n\t"
 #endif
-/*
- * To avoid the complications of mimicing single-stepping on a
- * processor without a Next-PC or a single-step mode, and to
- * avoid having to deal with the side-effects of boosting, we
- * simulate or emulate (almost) all ARM instructions.
- *
- * "Simulation" is where the instruction's behavior is duplicated in
- * C code.  "Emulation" is where the original instruction is rewritten
- * and executed, often by altering its registers.
- *
- * By having all behavior of the kprobe'd instruction completed before
- * returning from the kprobe_handler(), all locks (scheduler and
- * interrupt) can safely be released.  There is no need for secondary
- * breakpoints, no race with MP or preemptable kernels, nor having to
- * clean up resources counts at a later time impacting overall system
- * performance.  By rewriting the instruction, only the minimum registers
- * need to be loaded and saved back optimizing performance.
- *
- * Calling the insnslot_*_rwflags version of a function doesn't hurt
- * anything even when the CPSR flags aren't updated by the
- * instruction.  It's just a little slower in return for saving
- * a little space by not having a duplicate function that doesn't
- * update the flags.  (The same optimization can be said for
- * instructions that do or don't perform register writeback)
- * Also, instructions can either read the flags, only write the
- * flags, or read and write the flags.  To save combinations
- * rather than for sheer performance, flag functions just assume
- * read and write of flags.
- */
-static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs)
-{
-        kprobe_opcode_t insn = p->opcode;
-        long iaddr = (long)p->addr;
-        int disp  = branch_displacement(insn);
-        if (insn & (1 << 24))
-                regs->ARM_lr = iaddr + 4;
-        regs->ARM_pc = iaddr + 8 + disp;
-}
-static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs)
-{
-        kprobe_opcode_t insn = p->opcode;
-        long iaddr = (long)p->addr;
-        int disp = branch_displacement(insn);
-        regs->ARM_lr = iaddr + 4;
-        regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
-        regs->ARM_cpsr |= PSR_T_BIT;
-}
-static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs)
-{
-        kprobe_opcode_t insn = p->opcode;
-        int rm = insn & 0xf;
-        long rmv = regs->uregs[rm];
-        if (insn & (1 << 5))
-                regs->ARM_lr = (long)p->addr + 4;
-        regs->ARM_pc = rmv & ~0x1;
-        regs->ARM_cpsr &= ~PSR_T_BIT;
-        if (rmv & 0x1)
-                regs->ARM_cpsr |= PSR_T_BIT;
-}
-static void __kprobes simulate_mrs(struct kprobe *p, struct pt_regs *regs)
-{
-        kprobe_opcode_t insn = p->opcode;
-        int rd = (insn >> 12) & 0xf;
-        unsigned long mask = 0xf8ff03df; /* Mask out execution state */
-        regs->uregs[rd] = regs->ARM_cpsr & mask;
-}
-static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs)
-{
-        regs->uregs[12] = regs->uregs[13];
-}
 static void __kprobes
-emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
+emulate_ldrdstrd(probes_opcode_t insn,
+        struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc + 4;
-        unsigned long pc = (unsigned long)p->addr + 8;
        int rt = (insn >> 12) & 0xf;
        int rn = (insn >> 16) & 0xf;
        int rm = insn & 0xf;
@@ -175,7 +91,7 @@ emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
                BLX("%[fn]")
                : "=r" (rtv), "=r" (rt2v), "=r" (rnv)
                : "0" (rtv), "1" (rt2v), "2" (rnv), "r" (rmv),
-                  [fn] "r" (p->ainsn.insn_fn)
+                  [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -186,10 +102,10 @@ emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-emulate_ldr(struct kprobe *p, struct pt_regs *regs)
+emulate_ldr(probes_opcode_t insn,
+        struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc + 4;
-        unsigned long pc = (unsigned long)p->addr + 8;
        int rt = (insn >> 12) & 0xf;
        int rn = (insn >> 16) & 0xf;
        int rm = insn & 0xf;
@@ -202,7 +118,7 @@ emulate_ldr(struct kprobe *p, struct pt_regs *regs)
        __asm__ __volatile__ (
                BLX("%[fn]")
                : "=r" (rtv), "=r" (rnv)
-                : "1" (rnv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn)
+                : "1" (rnv), "r" (rmv), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -216,11 +132,11 @@ emulate_ldr(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-emulate_str(struct kprobe *p, struct pt_regs *regs)
+emulate_str(probes_opcode_t insn,
+        struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long rtpc = regs->ARM_pc - 4 + str_pc_offset;
-        unsigned long rtpc = (unsigned long)p->addr + str_pc_offset;
+        unsigned long rnpc = regs->ARM_pc + 4;
-        unsigned long rnpc = (unsigned long)p->addr + 8;
        int rt = (insn >> 12) & 0xf;
        int rn = (insn >> 16) & 0xf;
        int rm = insn & 0xf;
@@ -234,7 +150,7 @@ emulate_str(struct kprobe *p, struct pt_regs *regs)
        __asm__ __volatile__ (
                BLX("%[fn]")
                : "=r" (rnv)
-                : "r" (rtv), "0" (rnv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn)
+                : "r" (rtv), "0" (rnv), "r" (rmv), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -243,10 +159,10 @@ emulate_str(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-emulate_rd12rn16rm0rs8_rwflags(struct kprobe *p, struct pt_regs *regs)
+emulate_rd12rn16rm0rs8_rwflags(probes_opcode_t insn,
+        struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc + 4;
-        unsigned long pc = (unsigned long)p->addr + 8;
        int rd = (insn >> 12) & 0xf;
        int rn = (insn >> 16) & 0xf;
        int rm = insn & 0xf;
@@ -266,7 +182,7 @@ emulate_rd12rn16rm0rs8_rwflags(struct kprobe *p, struct pt_regs *regs)
                "mrs    %[cpsr], cpsr           \n\t"
                : "=r" (rdv), [cpsr] "=r" (cpsr)
                : "0" (rdv), "r" (rnv), "r" (rmv), "r" (rsv),
-                  "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
+                  "1" (cpsr), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -278,9 +194,9 @@ emulate_rd12rn16rm0rs8_rwflags(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-emulate_rd12rn16rm0_rwflags_nopc(struct kprobe *p, struct pt_regs *regs)
+emulate_rd12rn16rm0_rwflags_nopc(probes_opcode_t insn,
+        struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rd = (insn >> 12) & 0xf;
        int rn = (insn >> 16) & 0xf;
        int rm = insn & 0xf;
@@ -296,7 +212,7 @@ emulate_rd12rn16rm0_rwflags_nopc(struct kprobe *p, struct pt_regs *regs)
                "mrs    %[cpsr], cpsr           \n\t"
                : "=r" (rdv), [cpsr] "=r" (cpsr)
                : "0" (rdv), "r" (rnv), "r" (rmv),
-                  "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
+                  "1" (cpsr), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -305,9 +221,10 @@ emulate_rd12rn16rm0_rwflags_nopc(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-emulate_rd16rn12rm0rs8_rwflags_nopc(struct kprobe *p, struct pt_regs *regs)
+emulate_rd16rn12rm0rs8_rwflags_nopc(probes_opcode_t insn,
+        struct arch_probes_insn *asi,
+        struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rd = (insn >> 16) & 0xf;
        int rn = (insn >> 12) & 0xf;
        int rm = insn & 0xf;
@@ -325,7 +242,7 @@ emulate_rd16rn12rm0rs8_rwflags_nopc(struct kprobe *p, struct pt_regs *regs)
                "mrs    %[cpsr], cpsr           \n\t"
                : "=r" (rdv), [cpsr] "=r" (cpsr)
                : "0" (rdv), "r" (rnv), "r" (rmv), "r" (rsv),
-                  "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
+                  "1" (cpsr), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -334,9 +251,9 @@ emulate_rd16rn12rm0rs8_rwflags_nopc(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-emulate_rd12rm0_noflags_nopc(struct kprobe *p, struct pt_regs *regs)
+emulate_rd12rm0_noflags_nopc(probes_opcode_t insn,
+        struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rd = (insn >> 12) & 0xf;
        int rm = insn & 0xf;
@@ -346,7 +263,7 @@ emulate_rd12rm0_noflags_nopc(struct kprobe *p, struct pt_regs *regs)
        __asm__ __volatile__ (
                BLX("%[fn]")
                : "=r" (rdv)
-                : "0" (rdv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn)
+                : "0" (rdv), "r" (rmv), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -354,9 +271,10 @@ emulate_rd12rm0_noflags_nopc(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-emulate_rdlo12rdhi16rn0rm8_rwflags_nopc(struct kprobe *p, struct pt_regs *regs)
+emulate_rdlo12rdhi16rn0rm8_rwflags_nopc(probes_opcode_t insn,
+        struct arch_probes_insn *asi,
+        struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rdlo = (insn >> 12) & 0xf;
        int rdhi = (insn >> 16) & 0xf;
        int rn = insn & 0xf;
@@ -374,7 +292,7 @@ emulate_rdlo12rdhi16rn0rm8_rwflags_nopc(struct kprobe *p, struct pt_regs *regs)
                "mrs    %[cpsr], cpsr           \n\t"
                : "=r" (rdlov), "=r" (rdhiv), [cpsr] "=r" (cpsr)
                : "0" (rdlov), "1" (rdhiv), "r" (rnv), "r" (rmv),
-                  "2" (cpsr), [fn] "r" (p->ainsn.insn_fn)
+                  "2" (cpsr), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -383,623 +301,43 @@ emulate_rdlo12rdhi16rn0rm8_rwflags_nopc(struct kprobe *p, struct pt_regs *regs)
        regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
 }
-/*
+const union decode_action kprobes_arm_actions[NUM_PROBES_ARM_ACTIONS] = {
- * For the instruction masking and comparisons in all the "space_*"
+        [PROBES_EMULATE_NONE] = {.handler = probes_emulate_none},
- * functions below, Do _not_ rearrange the order of tests unless
+        [PROBES_SIMULATE_NOP] = {.handler = probes_simulate_nop},
- * you're very, very sure of what you are doing.  For the sake of
+        [PROBES_PRELOAD_IMM] = {.handler = probes_simulate_nop},
- * efficiency, the masks for some tests sometimes assume other test
+        [PROBES_PRELOAD_REG] = {.handler = probes_simulate_nop},
- * have been done prior to them so the number of patterns to test
+        [PROBES_BRANCH_IMM] = {.handler = simulate_blx1},
- * for an instruction set can be as broad as possible to reduce the
+        [PROBES_MRS] = {.handler = simulate_mrs},
- * number of tests needed.
+        [PROBES_BRANCH_REG] = {.handler = simulate_blx2bx},
- */
+        [PROBES_CLZ] = {.handler = emulate_rd12rm0_noflags_nopc},
+        [PROBES_SATURATING_ARITHMETIC] = {
-static const union decode_item arm_1111_table[] = {
+                .handler = emulate_rd12rn16rm0_rwflags_nopc},
-        /* Unconditional instructions                                   */
+        [PROBES_MUL1] = {.handler = emulate_rdlo12rdhi16rn0rm8_rwflags_nopc},
+        [PROBES_MUL2] = {.handler = emulate_rd16rn12rm0rs8_rwflags_nopc},
-        /* memory hint          1111 0100 x001 xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_SWP] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
-        /* PLDI (immediate)     1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_LDRSTRD] = {.handler = emulate_ldrdstrd},
-        /* PLDW (immediate)     1111 0101 x001 xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_LOAD_EXTRA] = {.handler = emulate_ldr},
-        /* PLD (immediate)      1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_LOAD] = {.handler = emulate_ldr},
-        DECODE_SIMULATE (0xfe300000, 0xf4100000, kprobe_simulate_nop),
+        [PROBES_STORE_EXTRA] = {.handler = emulate_str},
+        [PROBES_STORE] = {.handler = emulate_str},
-        /* memory hint          1111 0110 x001 xxxx xxxx xxxx xxx0 xxxx */
+        [PROBES_MOV_IP_SP] = {.handler = simulate_mov_ipsp},
-        /* PLDI (register)      1111 0110 x101 xxxx xxxx xxxx xxx0 xxxx */
+        [PROBES_DATA_PROCESSING_REG] = {
-        /* PLDW (register)      1111 0111 x001 xxxx xxxx xxxx xxx0 xxxx */
+                .handler = emulate_rd12rn16rm0rs8_rwflags},
-        /* PLD (register)       1111 0111 x101 xxxx xxxx xxxx xxx0 xxxx */
+        [PROBES_DATA_PROCESSING_IMM] = {
-        DECODE_SIMULATE (0xfe300010, 0xf6100000, kprobe_simulate_nop),
+                .handler = emulate_rd12rn16rm0rs8_rwflags},
+        [PROBES_MOV_HALFWORD] = {.handler = emulate_rd12rm0_noflags_nopc},
-        /* BLX (immediate)      1111 101x xxxx xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_SEV] = {.handler = probes_emulate_none},
-        DECODE_SIMULATE (0xfe000000, 0xfa000000, simulate_blx1),
+        [PROBES_WFE] = {.handler = probes_simulate_nop},
+        [PROBES_SATURATE] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
-        /* CPS                  1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */
+        [PROBES_REV] = {.handler = emulate_rd12rm0_noflags_nopc},
-        /* SETEND               1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
+        [PROBES_MMI] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
-        /* SRS                  1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_PACK] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
-        /* RFE                  1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_EXTEND] = {.handler = emulate_rd12rm0_noflags_nopc},
+        [PROBES_EXTEND_ADD] = {.handler = emulate_rd12rn16rm0_rwflags_nopc},
-        /* Coprocessor instructions... */
+        [PROBES_MUL_ADD_LONG] = {
-        /* MCRR2                1111 1100 0100 xxxx xxxx xxxx xxxx xxxx */
+                .handler = emulate_rdlo12rdhi16rn0rm8_rwflags_nopc},
-        /* MRRC2                1111 1100 0101 xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_MUL_ADD] = {.handler = emulate_rd16rn12rm0rs8_rwflags_nopc},
-        /* LDC2                 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_BITFIELD] = {.handler = emulate_rd12rm0_noflags_nopc},
-        /* STC2                 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
+        [PROBES_BRANCH] = {.handler = simulate_bbl},
-        /* CDP2                 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
+        [PROBES_LDMSTM] = {.decoder = kprobe_decode_ldmstm}
-        /* MCR2                 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
-        /* MRC2                 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
-        /* Other unallocated instructions...                            */
-        DECODE_END
-};
-static const union decode_item arm_cccc_0001_0xx0____0xxx_table[] = {
-        /* Miscellaneous instructions                                   */
-        /* MRS cpsr             cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
-        DECODE_SIMULATEX(0x0ff000f0, 0x01000000, simulate_mrs,
-                                                 REGS(0, NOPC, 0, 0, 0)),
-        /* BX                   cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
-        DECODE_SIMULATE (0x0ff000f0, 0x01200010, simulate_blx2bx),
-        /* BLX (register)       cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
-        DECODE_SIMULATEX(0x0ff000f0, 0x01200030, simulate_blx2bx,
-                                                 REGS(0, 0, 0, 0, NOPC)),
-        /* CLZ                  cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
-        DECODE_EMULATEX (0x0ff000f0, 0x01600010, emulate_rd12rm0_noflags_nopc,
-                                                 REGS(0, NOPC, 0, 0, NOPC)),
-        /* QADD                 cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx */
-        /* QSUB                 cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx */
-        /* QDADD                cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx */
-        /* QDSUB                cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx */
-        DECODE_EMULATEX (0x0f9000f0, 0x01000050, emulate_rd12rn16rm0_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
-        /* BXJ                  cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
-        /* MSR                  cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
-        /* MRS spsr             cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */
-        /* BKPT                 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
-        /* SMC                  cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */
-        /* And unallocated instructions...                              */
-        DECODE_END
-};
-static const union decode_item arm_cccc_0001_0xx0____1xx0_table[] = {
-        /* Halfword multiply and multiply-accumulate                    */
-        /* SMLALxy              cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
-        DECODE_EMULATEX (0x0ff00090, 0x01400080, emulate_rdlo12rdhi16rn0rm8_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
-        /* SMULWy               cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
-        DECODE_OR       (0x0ff000b0, 0x012000a0),
-        /* SMULxy               cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
-        DECODE_EMULATEX (0x0ff00090, 0x01600080, emulate_rd16rn12rm0rs8_rwflags_nopc,
-                                                 REGS(NOPC, 0, NOPC, 0, NOPC)),
-        /* SMLAxy               cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx */
-        DECODE_OR       (0x0ff00090, 0x01000080),
-        /* SMLAWy               cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx */
-        DECODE_EMULATEX (0x0ff000b0, 0x01200080, emulate_rd16rn12rm0rs8_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
-        DECODE_END
 };
-static const union decode_item arm_cccc_0000_____1001_table[] = {
-        /* Multiply and multiply-accumulate                             */
-        /* MUL                  cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx */
-        /* MULS                 cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx */
-        DECODE_EMULATEX (0x0fe000f0, 0x00000090, emulate_rd16rn12rm0rs8_rwflags_nopc,
-                                                 REGS(NOPC, 0, NOPC, 0, NOPC)),
-        /* MLA                  cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx */
-        /* MLAS                 cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx */
-        DECODE_OR       (0x0fe000f0, 0x00200090),
-        /* MLS                  cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx */
-        DECODE_EMULATEX (0x0ff000f0, 0x00600090, emulate_rd16rn12rm0rs8_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
-        /* UMAAL                cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx */
-        DECODE_OR       (0x0ff000f0, 0x00400090),
-        /* UMULL                cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx */
-        /* UMULLS               cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx */
-        /* UMLAL                cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx */
-        /* UMLALS               cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx */
-        /* SMULL                cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx */
-        /* SMULLS               cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx */
-        /* SMLAL                cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx */
-        /* SMLALS               cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx */
-        DECODE_EMULATEX (0x0f8000f0, 0x00800090, emulate_rdlo12rdhi16rn0rm8_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
-        DECODE_END
-};
-static const union decode_item arm_cccc_0001_____1001_table[] = {
-        /* Synchronization primitives                                   */
-#if __LINUX_ARM_ARCH__ < 6
-        /* Deprecated on ARMv6 and may be UNDEFINED on v7               */
-        /* SMP/SWPB             cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */
-        DECODE_EMULATEX (0x0fb000f0, 0x01000090, emulate_rd12rn16rm0_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
-#endif
-        /* LDREX/STREX{,D,B,H}  cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */
-        /* And unallocated instructions...                              */
-        DECODE_END
-};
-static const union decode_item arm_cccc_000x_____1xx1_table[] = {
-        /* Extra load/store instructions                                */
-        /* STRHT                cccc 0000 xx10 xxxx xxxx xxxx 1011 xxxx */
-        /* ???                  cccc 0000 xx10 xxxx xxxx xxxx 11x1 xxxx */
-        /* LDRHT                cccc 0000 xx11 xxxx xxxx xxxx 1011 xxxx */
-        /* LDRSBT               cccc 0000 xx11 xxxx xxxx xxxx 1101 xxxx */
-        /* LDRSHT               cccc 0000 xx11 xxxx xxxx xxxx 1111 xxxx */
-        DECODE_REJECT   (0x0f200090, 0x00200090),
-        /* LDRD/STRD lr,pc,{... cccc 000x x0x0 xxxx 111x xxxx 1101 xxxx */
-        DECODE_REJECT   (0x0e10e0d0, 0x0000e0d0),
-        /* LDRD (register)      cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx */
-        /* STRD (register)      cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx */
-        DECODE_EMULATEX (0x0e5000d0, 0x000000d0, emulate_ldrdstrd,
-                                                 REGS(NOPCWB, NOPCX, 0, 0, NOPC)),
-        /* LDRD (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx */
-        /* STRD (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx */
-        DECODE_EMULATEX (0x0e5000d0, 0x004000d0, emulate_ldrdstrd,
-                                                 REGS(NOPCWB, NOPCX, 0, 0, 0)),
-        /* STRH (register)      cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx */
-        DECODE_EMULATEX (0x0e5000f0, 0x000000b0, emulate_str,
-                                                 REGS(NOPCWB, NOPC, 0, 0, NOPC)),
-        /* LDRH (register)      cccc 000x x0x1 xxxx xxxx xxxx 1011 xxxx */
-        /* LDRSB (register)     cccc 000x x0x1 xxxx xxxx xxxx 1101 xxxx */
-        /* LDRSH (register)     cccc 000x x0x1 xxxx xxxx xxxx 1111 xxxx */
-        DECODE_EMULATEX (0x0e500090, 0x00100090, emulate_ldr,
-                                                 REGS(NOPCWB, NOPC, 0, 0, NOPC)),
-        /* STRH (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1011 xxxx */
-        DECODE_EMULATEX (0x0e5000f0, 0x004000b0, emulate_str,
-                                                 REGS(NOPCWB, NOPC, 0, 0, 0)),
-        /* LDRH (immediate)     cccc 000x x1x1 xxxx xxxx xxxx 1011 xxxx */
-        /* LDRSB (immediate)    cccc 000x x1x1 xxxx xxxx xxxx 1101 xxxx */
-        /* LDRSH (immediate)    cccc 000x x1x1 xxxx xxxx xxxx 1111 xxxx */
-        DECODE_EMULATEX (0x0e500090, 0x00500090, emulate_ldr,
-                                                 REGS(NOPCWB, NOPC, 0, 0, 0)),
-        DECODE_END
-};
-static const union decode_item arm_cccc_000x_table[] = {
-        /* Data-processing (register)                                   */
-        /* <op>S PC, ...        cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */
-        DECODE_REJECT   (0x0e10f000, 0x0010f000),
-        /* MOV IP, SP           1110 0001 1010 0000 1100 0000 0000 1101 */
-        DECODE_SIMULATE (0xffffffff, 0xe1a0c00d, simulate_mov_ipsp),
-        /* TST (register)       cccc 0001 0001 xxxx xxxx xxxx xxx0 xxxx */
-        /* TEQ (register)       cccc 0001 0011 xxxx xxxx xxxx xxx0 xxxx */
-        /* CMP (register)       cccc 0001 0101 xxxx xxxx xxxx xxx0 xxxx */
-        /* CMN (register)       cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */
-        DECODE_EMULATEX (0x0f900010, 0x01100000, emulate_rd12rn16rm0rs8_rwflags,
-                                                 REGS(ANY, 0, 0, 0, ANY)),
-        /* MOV (register)       cccc 0001 101x xxxx xxxx xxxx xxx0 xxxx */
-        /* MVN (register)       cccc 0001 111x xxxx xxxx xxxx xxx0 xxxx */
-        DECODE_EMULATEX (0x0fa00010, 0x01a00000, emulate_rd12rn16rm0rs8_rwflags,
-                                                 REGS(0, ANY, 0, 0, ANY)),
-        /* AND (register)       cccc 0000 000x xxxx xxxx xxxx xxx0 xxxx */
-        /* EOR (register)       cccc 0000 001x xxxx xxxx xxxx xxx0 xxxx */
-        /* SUB (register)       cccc 0000 010x xxxx xxxx xxxx xxx0 xxxx */
-        /* RSB (register)       cccc 0000 011x xxxx xxxx xxxx xxx0 xxxx */
-        /* ADD (register)       cccc 0000 100x xxxx xxxx xxxx xxx0 xxxx */
-        /* ADC (register)       cccc 0000 101x xxxx xxxx xxxx xxx0 xxxx */
-        /* SBC (register)       cccc 0000 110x xxxx xxxx xxxx xxx0 xxxx */
-        /* RSC (register)       cccc 0000 111x xxxx xxxx xxxx xxx0 xxxx */
-        /* ORR (register)       cccc 0001 100x xxxx xxxx xxxx xxx0 xxxx */
-        /* BIC (register)       cccc 0001 110x xxxx xxxx xxxx xxx0 xxxx */
-        DECODE_EMULATEX (0x0e000010, 0x00000000, emulate_rd12rn16rm0rs8_rwflags,
-                                                 REGS(ANY, ANY, 0, 0, ANY)),
-        /* TST (reg-shift reg)  cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */
-        /* TEQ (reg-shift reg)  cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */
-        /* CMP (reg-shift reg)  cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */
-        /* CMN (reg-shift reg)  cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
-        DECODE_EMULATEX (0x0f900090, 0x01100010, emulate_rd12rn16rm0rs8_rwflags,
-                                                 REGS(ANY, 0, NOPC, 0, ANY)),
-        /* MOV (reg-shift reg)  cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */
-        /* MVN (reg-shift reg)  cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */
-        DECODE_EMULATEX (0x0fa00090, 0x01a00010, emulate_rd12rn16rm0rs8_rwflags,
-                                                 REGS(0, ANY, NOPC, 0, ANY)),
-        /* AND (reg-shift reg)  cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */
-        /* EOR (reg-shift reg)  cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */
-        /* SUB (reg-shift reg)  cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */
-        /* RSB (reg-shift reg)  cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */
-        /* ADD (reg-shift reg)  cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */
-        /* ADC (reg-shift reg)  cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */
-        /* SBC (reg-shift reg)  cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */
-        /* RSC (reg-shift reg)  cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */
-        /* ORR (reg-shift reg)  cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */
-        /* BIC (reg-shift reg)  cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */
-        DECODE_EMULATEX (0x0e000090, 0x00000010, emulate_rd12rn16rm0rs8_rwflags,
-                                                 REGS(ANY, ANY, NOPC, 0, ANY)),
-        DECODE_END
-};
-static const union decode_item arm_cccc_001x_table[] = {
-        /* Data-processing (immediate)                                  */
-        /* MOVW                 cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */
-        /* MOVT                 cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0x0fb00000, 0x03000000, emulate_rd12rm0_noflags_nopc,
-                                                 REGS(0, NOPC, 0, 0, 0)),
-        /* YIELD                cccc 0011 0010 0000 xxxx xxxx 0000 0001 */
-        DECODE_OR       (0x0fff00ff, 0x03200001),
-        /* SEV                  cccc 0011 0010 0000 xxxx xxxx 0000 0100 */
-        DECODE_EMULATE  (0x0fff00ff, 0x03200004, kprobe_emulate_none),
-        /* NOP                  cccc 0011 0010 0000 xxxx xxxx 0000 0000 */
-        /* WFE                  cccc 0011 0010 0000 xxxx xxxx 0000 0010 */
-        /* WFI                  cccc 0011 0010 0000 xxxx xxxx 0000 0011 */
-        DECODE_SIMULATE (0x0fff00fc, 0x03200000, kprobe_simulate_nop),
-        /* DBG                  cccc 0011 0010 0000 xxxx xxxx ffff xxxx */
-        /* unallocated hints    cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */
-        /* MSR (immediate)      cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0x0fb00000, 0x03200000),
-        /* <op>S PC, ...        cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */
-        DECODE_REJECT   (0x0e10f000, 0x0210f000),
-        /* TST (immediate)      cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx */
-        /* TEQ (immediate)      cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx */
-        /* CMP (immediate)      cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx */
-        /* CMN (immediate)      cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0x0f900000, 0x03100000, emulate_rd12rn16rm0rs8_rwflags,
-                                                 REGS(ANY, 0, 0, 0, 0)),
-        /* MOV (immediate)      cccc 0011 101x xxxx xxxx xxxx xxxx xxxx */
-        /* MVN (immediate)      cccc 0011 111x xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0x0fa00000, 0x03a00000, emulate_rd12rn16rm0rs8_rwflags,
-                                                 REGS(0, ANY, 0, 0, 0)),
-        /* AND (immediate)      cccc 0010 000x xxxx xxxx xxxx xxxx xxxx */
-        /* EOR (immediate)      cccc 0010 001x xxxx xxxx xxxx xxxx xxxx */
-        /* SUB (immediate)      cccc 0010 010x xxxx xxxx xxxx xxxx xxxx */
-        /* RSB (immediate)      cccc 0010 011x xxxx xxxx xxxx xxxx xxxx */
-        /* ADD (immediate)      cccc 0010 100x xxxx xxxx xxxx xxxx xxxx */
-        /* ADC (immediate)      cccc 0010 101x xxxx xxxx xxxx xxxx xxxx */
-        /* SBC (immediate)      cccc 0010 110x xxxx xxxx xxxx xxxx xxxx */
-        /* RSC (immediate)      cccc 0010 111x xxxx xxxx xxxx xxxx xxxx */
-        /* ORR (immediate)      cccc 0011 100x xxxx xxxx xxxx xxxx xxxx */
-        /* BIC (immediate)      cccc 0011 110x xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0x0e000000, 0x02000000, emulate_rd12rn16rm0rs8_rwflags,
-                                                 REGS(ANY, ANY, 0, 0, 0)),
-        DECODE_END
-};
-static const union decode_item arm_cccc_0110_____xxx1_table[] = {
-        /* Media instructions                                           */
-        /* SEL                  cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx */
-        DECODE_EMULATEX (0x0ff000f0, 0x068000b0, emulate_rd12rn16rm0_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
-        /* SSAT                 cccc 0110 101x xxxx xxxx xxxx xx01 xxxx */
-        /* USAT                 cccc 0110 111x xxxx xxxx xxxx xx01 xxxx */
-        DECODE_OR(0x0fa00030, 0x06a00010),
-        /* SSAT16               cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx */
-        /* USAT16               cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx */
-        DECODE_EMULATEX (0x0fb000f0, 0x06a00030, emulate_rd12rn16rm0_rwflags_nopc,
-                                                 REGS(0, NOPC, 0, 0, NOPC)),
-        /* REV                  cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
-        /* REV16                cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
-        /* RBIT                 cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */
-        /* REVSH                cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
-        DECODE_EMULATEX (0x0fb00070, 0x06b00030, emulate_rd12rm0_noflags_nopc,
-                                                 REGS(0, NOPC, 0, 0, NOPC)),
-        /* ???                  cccc 0110 0x00 xxxx xxxx xxxx xxx1 xxxx */
-        DECODE_REJECT   (0x0fb00010, 0x06000010),
-        /* ???                  cccc 0110 0xxx xxxx xxxx xxxx 1011 xxxx */
-        DECODE_REJECT   (0x0f8000f0, 0x060000b0),
-        /* ???                  cccc 0110 0xxx xxxx xxxx xxxx 1101 xxxx */
-        DECODE_REJECT   (0x0f8000f0, 0x060000d0),
-        /* SADD16               cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx */
-        /* SADDSUBX             cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx */
-        /* SSUBADDX             cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx */
-        /* SSUB16               cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx */
-        /* SADD8                cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx */
-        /* SSUB8                cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx */
-        /* QADD16               cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx */
-        /* QADDSUBX             cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx */
-        /* QSUBADDX             cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx */
-        /* QSUB16               cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx */
-        /* QADD8                cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx */
-        /* QSUB8                cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx */
-        /* SHADD16              cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx */
-        /* SHADDSUBX            cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx */
-        /* SHSUBADDX            cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx */
-        /* SHSUB16              cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx */
-        /* SHADD8               cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx */
-        /* SHSUB8               cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx */
-        /* UADD16               cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx */
-        /* UADDSUBX             cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx */
-        /* USUBADDX             cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx */
-        /* USUB16               cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx */
-        /* UADD8                cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx */
-        /* USUB8                cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx */
-        /* UQADD16              cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx */
-        /* UQADDSUBX            cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx */
-        /* UQSUBADDX            cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx */
-        /* UQSUB16              cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx */
-        /* UQADD8               cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx */
-        /* UQSUB8               cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx */
-        /* UHADD16              cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx */
-        /* UHADDSUBX            cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx */
-        /* UHSUBADDX            cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx */
-        /* UHSUB16              cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx */
-        /* UHADD8               cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx */
-        /* UHSUB8               cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx */
-        DECODE_EMULATEX (0x0f800010, 0x06000010, emulate_rd12rn16rm0_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
-        /* PKHBT                cccc 0110 1000 xxxx xxxx xxxx x001 xxxx */
-        /* PKHTB                cccc 0110 1000 xxxx xxxx xxxx x101 xxxx */
-        DECODE_EMULATEX (0x0ff00030, 0x06800010, emulate_rd12rn16rm0_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
-        /* ???                  cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx */
-        /* ???                  cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx */
-        DECODE_REJECT   (0x0fb000f0, 0x06900070),
-        /* SXTB16               cccc 0110 1000 1111 xxxx xxxx 0111 xxxx */
-        /* SXTB                 cccc 0110 1010 1111 xxxx xxxx 0111 xxxx */
-        /* SXTH                 cccc 0110 1011 1111 xxxx xxxx 0111 xxxx */
-        /* UXTB16               cccc 0110 1100 1111 xxxx xxxx 0111 xxxx */
-        /* UXTB                 cccc 0110 1110 1111 xxxx xxxx 0111 xxxx */
-        /* UXTH                 cccc 0110 1111 1111 xxxx xxxx 0111 xxxx */
-        DECODE_EMULATEX (0x0f8f00f0, 0x068f0070, emulate_rd12rm0_noflags_nopc,
-                                                 REGS(0, NOPC, 0, 0, NOPC)),
-        /* SXTAB16              cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx */
-        /* SXTAB                cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx */
-        /* SXTAH                cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx */
-        /* UXTAB16              cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx */
-        /* UXTAB                cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx */
-        /* UXTAH                cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx */
-        DECODE_EMULATEX (0x0f8000f0, 0x06800070, emulate_rd12rn16rm0_rwflags_nopc,
-                                                 REGS(NOPCX, NOPC, 0, 0, NOPC)),
-        DECODE_END
-};
-static const union decode_item arm_cccc_0111_____xxx1_table[] = {
-        /* Media instructions                                           */
-        /* UNDEFINED            cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
-        DECODE_REJECT   (0x0ff000f0, 0x07f000f0),
-        /* SMLALD               cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
-        /* SMLSLD               cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
-        DECODE_EMULATEX (0x0ff00090, 0x07400010, emulate_rdlo12rdhi16rn0rm8_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
-        /* SMUAD                cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx */
-        /* SMUSD                cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx */
-        DECODE_OR       (0x0ff0f090, 0x0700f010),
-        /* SMMUL                cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx */
-        DECODE_OR       (0x0ff0f0d0, 0x0750f010),
-        /* USAD8                cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
-        DECODE_EMULATEX (0x0ff0f0f0, 0x0780f010, emulate_rd16rn12rm0rs8_rwflags_nopc,
-                                                 REGS(NOPC, 0, NOPC, 0, NOPC)),
-        /* SMLAD                cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx */
-        /* SMLSD                cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx */
-        DECODE_OR       (0x0ff00090, 0x07000010),
-        /* SMMLA                cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx */
-        DECODE_OR       (0x0ff000d0, 0x07500010),
-        /* USADA8               cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
-        DECODE_EMULATEX (0x0ff000f0, 0x07800010, emulate_rd16rn12rm0rs8_rwflags_nopc,
-                                                 REGS(NOPC, NOPCX, NOPC, 0, NOPC)),
-        /* SMMLS                cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx */
-        DECODE_EMULATEX (0x0ff000d0, 0x075000d0, emulate_rd16rn12rm0rs8_rwflags_nopc,
-                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
-        /* SBFX                 cccc 0111 101x xxxx xxxx xxxx x101 xxxx */
-        /* UBFX                 cccc 0111 111x xxxx xxxx xxxx x101 xxxx */
-        DECODE_EMULATEX (0x0fa00070, 0x07a00050, emulate_rd12rm0_noflags_nopc,
-                                                 REGS(0, NOPC, 0, 0, NOPC)),
-        /* BFC                  cccc 0111 110x xxxx xxxx xxxx x001 1111 */
-        DECODE_EMULATEX (0x0fe0007f, 0x07c0001f, emulate_rd12rm0_noflags_nopc,
-                                                 REGS(0, NOPC, 0, 0, 0)),
-        /* BFI                  cccc 0111 110x xxxx xxxx xxxx x001 xxxx */
-        DECODE_EMULATEX (0x0fe00070, 0x07c00010, emulate_rd12rm0_noflags_nopc,
-                                                 REGS(0, NOPC, 0, 0, NOPCX)),
-        DECODE_END
-};
-static const union decode_item arm_cccc_01xx_table[] = {
-        /* Load/store word and unsigned byte                            */
-        /* LDRB/STRB pc,[...]   cccc 01xx x0xx xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0x0c40f000, 0x0440f000),
-        /* STRT                 cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRT                 cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
-        /* STRBT                cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRBT                cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0x0d200000, 0x04200000),
-        /* STR (immediate)      cccc 010x x0x0 xxxx xxxx xxxx xxxx xxxx */
-        /* STRB (immediate)     cccc 010x x1x0 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0x0e100000, 0x04000000, emulate_str,
-                                                 REGS(NOPCWB, ANY, 0, 0, 0)),
-        /* LDR (immediate)      cccc 010x x0x1 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRB (immediate)     cccc 010x x1x1 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0x0e100000, 0x04100000, emulate_ldr,
-                                                 REGS(NOPCWB, ANY, 0, 0, 0)),
-        /* STR (register)       cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx */
-        /* STRB (register)      cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0x0e100000, 0x06000000, emulate_str,
-                                                 REGS(NOPCWB, ANY, 0, 0, NOPC)),
-        /* LDR (register)       cccc 011x x0x1 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRB (register)      cccc 011x x1x1 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0x0e100000, 0x06100000, emulate_ldr,
-                                                 REGS(NOPCWB, ANY, 0, 0, NOPC)),
-        DECODE_END
-};
-static const union decode_item arm_cccc_100x_table[] = {
-        /* Block data transfer instructions                             */
-        /* LDM                  cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
-        /* STM                  cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_CUSTOM   (0x0e400000, 0x08000000, kprobe_decode_ldmstm),
-        /* STM (user registers) cccc 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
-        /* LDM (user registers) cccc 100x x1x1 xxxx 0xxx xxxx xxxx xxxx */
-        /* LDM (exception ret)  cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
-        DECODE_END
-};
-const union decode_item kprobe_decode_arm_table[] = {
-        /*
-         * Unconditional instructions
-         *                      1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xf0000000, 0xf0000000, arm_1111_table),
-        /*
-         * Miscellaneous instructions
-         *                      cccc 0001 0xx0 xxxx xxxx xxxx 0xxx xxxx
-         */
-        DECODE_TABLE    (0x0f900080, 0x01000000, arm_cccc_0001_0xx0____0xxx_table),
-        /*
-         * Halfword multiply and multiply-accumulate
-         *                      cccc 0001 0xx0 xxxx xxxx xxxx 1xx0 xxxx
-         */
-        DECODE_TABLE    (0x0f900090, 0x01000080, arm_cccc_0001_0xx0____1xx0_table),
-        /*
-         * Multiply and multiply-accumulate
-         *                      cccc 0000 xxxx xxxx xxxx xxxx 1001 xxxx
-         */
-        DECODE_TABLE    (0x0f0000f0, 0x00000090, arm_cccc_0000_____1001_table),
-        /*
-         * Synchronization primitives
-         *                      cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx
-         */
-        DECODE_TABLE    (0x0f0000f0, 0x01000090, arm_cccc_0001_____1001_table),
-        /*
-         * Extra load/store instructions
-         *                      cccc 000x xxxx xxxx xxxx xxxx 1xx1 xxxx
-         */
-        DECODE_TABLE    (0x0e000090, 0x00000090, arm_cccc_000x_____1xx1_table),
-        /*
-         * Data-processing (register)
-         *                      cccc 000x xxxx xxxx xxxx xxxx xxx0 xxxx
-         * Data-processing (register-shifted register)
-         *                      cccc 000x xxxx xxxx xxxx xxxx 0xx1 xxxx
-         */
-        DECODE_TABLE    (0x0e000000, 0x00000000, arm_cccc_000x_table),
-        /*
-         * Data-processing (immediate)
-         *                      cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0x0e000000, 0x02000000, arm_cccc_001x_table),
-        /*
-         * Media instructions
-         *                      cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx
-         */
-        DECODE_TABLE    (0x0f000010, 0x06000010, arm_cccc_0110_____xxx1_table),
-        DECODE_TABLE    (0x0f000010, 0x07000010, arm_cccc_0111_____xxx1_table),
-        /*
-         * Load/store word and unsigned byte
-         *                      cccc 01xx xxxx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0x0c000000, 0x04000000, arm_cccc_01xx_table),
-        /*
-         * Block data transfer instructions
-         *                      cccc 100x xxxx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0x0e000000, 0x08000000, arm_cccc_100x_table),
-        /* B                    cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
-        /* BL                   cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
-        DECODE_SIMULATE (0x0e000000, 0x0a000000, simulate_bbl),
-        /*
-         * Supervisor Call, and coprocessor instructions
-         */
-        /* MCRR                 cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx */
-        /* MRRC                 cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx */
-        /* LDC                  cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
-        /* STC                  cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
-        /* CDP                  cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
-        /* MCR                  cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
-        /* MRC                  cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
-        /* SVC                  cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0x0c000000, 0x0c000000),
-        DECODE_END
-};
-#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
-EXPORT_SYMBOL_GPL(kprobe_decode_arm_table);
-#endif
-static void __kprobes arm_singlestep(struct kprobe *p, struct pt_regs *regs)
-{
-        regs->ARM_pc += 4;
-        p->ainsn.insn_handler(p, regs);
-}
-/* Return:
- *   INSN_REJECTED     If instruction is one not allowed to kprobe,
- *   INSN_GOOD         If instruction is supported and uses instruction slot,
- *   INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
- *
- * For instructions we don't want to kprobe (INSN_REJECTED return result):
- *   These are generally ones that modify the processor state making
- *   them "hard" to simulate such as switches processor modes or
- *   make accesses in alternate modes.  Any of these could be simulated
- *   if the work was put into it, but low return considering they
- *   should also be very rare.
- */
-enum kprobe_insn __kprobes
-arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
-{
-        asi->insn_singlestep = arm_singlestep;
-        asi->insn_check_cc = kprobe_condition_checks[insn>>28];
-        return kprobe_decode_insn(insn, asi, kprobe_decode_arm_table, false);
-}
diff --git a/arch/arm/kernel/kprobes-common.c b/arch/arm/kernel/kprobes-common.c
index 18a76282970e..0bf5d64eba1d 100644
--- a/arch/arm/kernel/kprobes-common.c
+++ b/arch/arm/kernel/kprobes-common.c
@@ -13,178 +13,15 @@
 #include <linux/kernel.h>
 #include <linux/kprobes.h>
-#include <asm/system_info.h>
+#include <asm/opcodes.h>
 #include "kprobes.h"
-#ifndef find_str_pc_offset
+static void __kprobes simulate_ldm1stm1(probes_opcode_t insn,
+                struct arch_probes_insn *asi,
-/*
+                struct pt_regs *regs)
- * For STR and STM instructions, an ARM core may choose to use either
- * a +8 or a +12 displacement from the current instruction's address.
- * Whichever value is chosen for a given core, it must be the same for
- * both instructions and may not change.  This function measures it.
- */
-int str_pc_offset;
-void __init find_str_pc_offset(void)
-{
-        int addr, scratch, ret;
-        __asm__ (
-                "sub    %[ret], pc, #4          \n\t"
-                "str    pc, %[addr]             \n\t"
-                "ldr    %[scr], %[addr]         \n\t"
-                "sub    %[ret], %[scr], %[ret]  \n\t"
-                : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
-        str_pc_offset = ret;
-}
-#endif /* !find_str_pc_offset */
-#ifndef test_load_write_pc_interworking
-bool load_write_pc_interworks;
-void __init test_load_write_pc_interworking(void)
-{
-        int arch = cpu_architecture();
-        BUG_ON(arch == CPU_ARCH_UNKNOWN);
-        load_write_pc_interworks = arch >= CPU_ARCH_ARMv5T;
-}
-#endif /* !test_load_write_pc_interworking */
-#ifndef test_alu_write_pc_interworking
-bool alu_write_pc_interworks;
-void __init test_alu_write_pc_interworking(void)
-{
-        int arch = cpu_architecture();
-        BUG_ON(arch == CPU_ARCH_UNKNOWN);
-        alu_write_pc_interworks = arch >= CPU_ARCH_ARMv7;
-}
-#endif /* !test_alu_write_pc_interworking */
-void __init arm_kprobe_decode_init(void)
-{
-        find_str_pc_offset();
-        test_load_write_pc_interworking();
-        test_alu_write_pc_interworking();
-}
-static unsigned long __kprobes __check_eq(unsigned long cpsr)
-{
-        return cpsr & PSR_Z_BIT;
-}
-static unsigned long __kprobes __check_ne(unsigned long cpsr)
-{
-        return (~cpsr) & PSR_Z_BIT;
-}
-static unsigned long __kprobes __check_cs(unsigned long cpsr)
-{
-        return cpsr & PSR_C_BIT;
-}
-static unsigned long __kprobes __check_cc(unsigned long cpsr)
-{
-        return (~cpsr) & PSR_C_BIT;
-}
-static unsigned long __kprobes __check_mi(unsigned long cpsr)
-{
-        return cpsr & PSR_N_BIT;
-}
-static unsigned long __kprobes __check_pl(unsigned long cpsr)
-{
-        return (~cpsr) & PSR_N_BIT;
-}
-static unsigned long __kprobes __check_vs(unsigned long cpsr)
-{
-        return cpsr & PSR_V_BIT;
-}
-static unsigned long __kprobes __check_vc(unsigned long cpsr)
-{
-        return (~cpsr) & PSR_V_BIT;
-}
-static unsigned long __kprobes __check_hi(unsigned long cpsr)
-{
-        cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
-        return cpsr & PSR_C_BIT;
-}
-static unsigned long __kprobes __check_ls(unsigned long cpsr)
-{
-        cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
-        return (~cpsr) & PSR_C_BIT;
-}
-static unsigned long __kprobes __check_ge(unsigned long cpsr)
-{
-        cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
-        return (~cpsr) & PSR_N_BIT;
-}
-static unsigned long __kprobes __check_lt(unsigned long cpsr)
-{
-        cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
-        return cpsr & PSR_N_BIT;
-}
-static unsigned long __kprobes __check_gt(unsigned long cpsr)
-{
-        unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
-        temp |= (cpsr << 1);                     /* PSR_N_BIT |= PSR_Z_BIT */
-        return (~temp) & PSR_N_BIT;
-}
-static unsigned long __kprobes __check_le(unsigned long cpsr)
-{
-        unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
-        temp |= (cpsr << 1);                     /* PSR_N_BIT |= PSR_Z_BIT */
-        return temp & PSR_N_BIT;
-}
-static unsigned long __kprobes __check_al(unsigned long cpsr)
-{
-        return true;
-}
-kprobe_check_cc * const kprobe_condition_checks[16] = {
-        &__check_eq, &__check_ne, &__check_cs, &__check_cc,
-        &__check_mi, &__check_pl, &__check_vs, &__check_vc,
-        &__check_hi, &__check_ls, &__check_ge, &__check_lt,
-        &__check_gt, &__check_le, &__check_al, &__check_al
-};
-void __kprobes kprobe_simulate_nop(struct kprobe *p, struct pt_regs *regs)
-{
-}
-void __kprobes kprobe_emulate_none(struct kprobe *p, struct pt_regs *regs)
-{
-        p->ainsn.insn_fn();
-}
-static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rn = (insn >> 16) & 0xf;
        int lbit = insn & (1 << 20);
        int wbit = insn & (1 << 21);
@@ -223,24 +60,31 @@ static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
        }
 }
-static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs)
+static void __kprobes simulate_stm1_pc(probes_opcode_t insn,
+        struct arch_probes_insn *asi,
+        struct pt_regs *regs)
 {
-        regs->ARM_pc = (long)p->addr + str_pc_offset;
+        unsigned long addr = regs->ARM_pc - 4;
-        simulate_ldm1stm1(p, regs);
-        regs->ARM_pc = (long)p->addr + 4;
+        regs->ARM_pc = (long)addr + str_pc_offset;
+        simulate_ldm1stm1(insn, asi, regs);
+        regs->ARM_pc = (long)addr + 4;
 }
-static void __kprobes simulate_ldm1_pc(struct kprobe *p, struct pt_regs *regs)
+static void __kprobes simulate_ldm1_pc(probes_opcode_t insn,
+        struct arch_probes_insn *asi,
+        struct pt_regs *regs)
 {
-        simulate_ldm1stm1(p, regs);
+        simulate_ldm1stm1(insn, asi, regs);
        load_write_pc(regs->ARM_pc, regs);
 }
 static void __kprobes
-emulate_generic_r0_12_noflags(struct kprobe *p, struct pt_regs *regs)
+emulate_generic_r0_12_noflags(probes_opcode_t insn,
+        struct arch_probes_insn *asi, struct pt_regs *regs)
 {
        register void *rregs asm("r1") = regs;
-        register void *rfn asm("lr") = p->ainsn.insn_fn;
+        register void *rfn asm("lr") = asi->insn_fn;
        __asm__ __volatile__ (
                "stmdb  sp!, {%[regs], r11}     \n\t"
@@ -264,22 +108,27 @@ emulate_generic_r0_12_noflags(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-emulate_generic_r2_14_noflags(struct kprobe *p, struct pt_regs *regs)
+emulate_generic_r2_14_noflags(probes_opcode_t insn,
+        struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        emulate_generic_r0_12_noflags(p, (struct pt_regs *)(regs->uregs+2));
+        emulate_generic_r0_12_noflags(insn, asi,
+                (struct pt_regs *)(regs->uregs+2));
 }
 static void __kprobes
-emulate_ldm_r3_15(struct kprobe *p, struct pt_regs *regs)
+emulate_ldm_r3_15(probes_opcode_t insn,
+        struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        emulate_generic_r0_12_noflags(p, (struct pt_regs *)(regs->uregs+3));
+        emulate_generic_r0_12_noflags(insn, asi,
+                (struct pt_regs *)(regs->uregs+3));
        load_write_pc(regs->ARM_pc, regs);
 }
-enum kprobe_insn __kprobes
+enum probes_insn __kprobes
-kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+kprobe_decode_ldmstm(probes_opcode_t insn, struct arch_probes_insn *asi,
+                const struct decode_header *h)
 {
-        kprobe_insn_handler_t *handler = 0;
+        probes_insn_handler_t *handler = 0;
        unsigned reglist = insn & 0xffff;
        int is_ldm = insn & 0x100000;
        int rn = (insn >> 16) & 0xf;
@@ -305,7 +154,8 @@ kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
        if (handler) {
                /* We can emulate the instruction in (possibly) modified form */
-                asi->insn[0] = (insn & 0xfff00000) | (rn << 16) | reglist;
+                asi->insn[0] = __opcode_to_mem_arm((insn & 0xfff00000) |
+                                                   (rn << 16) | reglist);
                asi->insn_handler = handler;
                return INSN_GOOD;
        }
@@ -319,260 +169,3 @@ kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
        return INSN_GOOD_NO_SLOT;
 }
-/*
- * Prepare an instruction slot to receive an instruction for emulating.
- * This is done by placing a subroutine return after the location where the
- * instruction will be placed. We also modify ARM instructions to be
- * unconditional as the condition code will already be checked before any
- * emulation handler is called.
- */
-static kprobe_opcode_t __kprobes
-prepare_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
-                                                                bool thumb)
-{
-#ifdef CONFIG_THUMB2_KERNEL
-        if (thumb) {
-                u16 *thumb_insn = (u16 *)asi->insn;
-                thumb_insn[1] = 0x4770; /* Thumb bx lr */
-                thumb_insn[2] = 0x4770; /* Thumb bx lr */
-                return insn;
-        }
-        asi->insn[1] = 0xe12fff1e; /* ARM bx lr */
-#else
-        asi->insn[1] = 0xe1a0f00e; /* mov pc, lr */
-#endif
-        /* Make an ARM instruction unconditional */
-        if (insn < 0xe0000000)
-                insn = (insn | 0xe0000000) & ~0x10000000;
-        return insn;
-}
-/*
- * Write a (probably modified) instruction into the slot previously prepared by
- * prepare_emulated_insn
- */
-static void  __kprobes
-set_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
-                                                                bool thumb)
-{
-#ifdef CONFIG_THUMB2_KERNEL
-        if (thumb) {
-                u16 *ip = (u16 *)asi->insn;
-                if (is_wide_instruction(insn))
-                        *ip++ = insn >> 16;
-                *ip++ = insn;
-                return;
-        }
-#endif
-        asi->insn[0] = insn;
-}
-/*
- * When we modify the register numbers encoded in an instruction to be emulated,
- * the new values come from this define. For ARM and 32-bit Thumb instructions
- * this gives...
- *
- *      bit position      16  12   8   4   0
- *      ---------------+---+---+---+---+---+
- *      register         r2  r0  r1  --  r3
- */
-#define INSN_NEW_BITS           0x00020103
-/* Each nibble has same value as that at INSN_NEW_BITS bit 16 */
-#define INSN_SAMEAS16_BITS      0x22222222
-/*
- * Validate and modify each of the registers encoded in an instruction.
- *
- * Each nibble in regs contains a value from enum decode_reg_type. For each
- * non-zero value, the corresponding nibble in pinsn is validated and modified
- * according to the type.
- */
-static bool __kprobes decode_regs(kprobe_opcode_t* pinsn, u32 regs)
-{
-        kprobe_opcode_t insn = *pinsn;
-        kprobe_opcode_t mask = 0xf; /* Start at least significant nibble */
-        for (; regs != 0; regs >>= 4, mask <<= 4) {
-                kprobe_opcode_t new_bits = INSN_NEW_BITS;
-                switch (regs & 0xf) {
-                case REG_TYPE_NONE:
-                        /* Nibble not a register, skip to next */
-                        continue;
-                case REG_TYPE_ANY:
-                        /* Any register is allowed */
-                        break;
-                case REG_TYPE_SAMEAS16:
-                        /* Replace register with same as at bit position 16 */
-                        new_bits = INSN_SAMEAS16_BITS;
-                        break;
-                case REG_TYPE_SP:
-                        /* Only allow SP (R13) */
-                        if ((insn ^ 0xdddddddd) & mask)
-                                goto reject;
-                        break;
-                case REG_TYPE_PC:
-                        /* Only allow PC (R15) */
-                        if ((insn ^ 0xffffffff) & mask)
-                                goto reject;
-                        break;
-                case REG_TYPE_NOSP:
-                        /* Reject SP (R13) */
-                        if (((insn ^ 0xdddddddd) & mask) == 0)
-                                goto reject;
-                        break;
-                case REG_TYPE_NOSPPC:
-                case REG_TYPE_NOSPPCX:
-                        /* Reject SP and PC (R13 and R15) */
-                        if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0)
-                                goto reject;
-                        break;
-                case REG_TYPE_NOPCWB:
-                        if (!is_writeback(insn))
-                                break; /* No writeback, so any register is OK */
-                        /* fall through... */
-                case REG_TYPE_NOPC:
-                case REG_TYPE_NOPCX:
-                        /* Reject PC (R15) */
-                        if (((insn ^ 0xffffffff) & mask) == 0)
-                                goto reject;
-                        break;
-                }
-                /* Replace value of nibble with new register number... */
-                insn &= ~mask;
-                insn |= new_bits & mask;
-        }
-        *pinsn = insn;
-        return true;
-reject:
-        return false;
-}
-static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
-        [DECODE_TYPE_TABLE]     = sizeof(struct decode_table),
-        [DECODE_TYPE_CUSTOM]    = sizeof(struct decode_custom),
-        [DECODE_TYPE_SIMULATE]  = sizeof(struct decode_simulate),
-        [DECODE_TYPE_EMULATE]   = sizeof(struct decode_emulate),
-        [DECODE_TYPE_OR]        = sizeof(struct decode_or),
-        [DECODE_TYPE_REJECT]    = sizeof(struct decode_reject)
-};
-/*
- * kprobe_decode_insn operates on data tables in order to decode an ARM
- * architecture instruction onto which a kprobe has been placed.
- *
- * These instruction decoding tables are a concatenation of entries each
- * of which consist of one of the following structs:
- *
- *      decode_table
- *      decode_custom
- *      decode_simulate
- *      decode_emulate
- *      decode_or
- *      decode_reject
- *
- * Each of these starts with a struct decode_header which has the following
- * fields:
- *
- *      type_regs
- *      mask
- *      value
- *
- * The least significant DECODE_TYPE_BITS of type_regs contains a value
- * from enum decode_type, this indicates which of the decode_* structs
- * the entry contains. The value DECODE_TYPE_END indicates the end of the
- * table.
- *
- * When the table is parsed, each entry is checked in turn to see if it
- * matches the instruction to be decoded using the test:
- *
- *      (insn & mask) == value
- *
- * If no match is found before the end of the table is reached then decoding
- * fails with INSN_REJECTED.
- *
- * When a match is found, decode_regs() is called to validate and modify each
- * of the registers encoded in the instruction; the data it uses to do this
- * is (type_regs >> DECODE_TYPE_BITS). A validation failure will cause decoding
- * to fail with INSN_REJECTED.
- *
- * Once the instruction has passed the above tests, further processing
- * depends on the type of the table entry's decode struct.
- *
- */
-int __kprobes
-kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
-                                const union decode_item *table, bool thumb)
-{
-        const struct decode_header *h = (struct decode_header *)table;
-        const struct decode_header *next;
-        bool matched = false;
-        insn = prepare_emulated_insn(insn, asi, thumb);
-        for (;; h = next) {
-                enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
-                u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
-                if (type == DECODE_TYPE_END)
-                        return INSN_REJECTED;
-                next = (struct decode_header *)
-                                ((uintptr_t)h + decode_struct_sizes[type]);
-                if (!matched && (insn & h->mask.bits) != h->value.bits)
-                        continue;
-                if (!decode_regs(&insn, regs))
-                        return INSN_REJECTED;
-                switch (type) {
-                case DECODE_TYPE_TABLE: {
-                        struct decode_table *d = (struct decode_table *)h;
-                        next = (struct decode_header *)d->table.table;
-                        break;
-                }
-                case DECODE_TYPE_CUSTOM: {
-                        struct decode_custom *d = (struct decode_custom *)h;
-                        return (*d->decoder.decoder)(insn, asi);
-                }
-                case DECODE_TYPE_SIMULATE: {
-                        struct decode_simulate *d = (struct decode_simulate *)h;
-                        asi->insn_handler = d->handler.handler;
-                        return INSN_GOOD_NO_SLOT;
-                }
-                case DECODE_TYPE_EMULATE: {
-                        struct decode_emulate *d = (struct decode_emulate *)h;
-                        asi->insn_handler = d->handler.handler;
-                        set_emulated_insn(insn, asi, thumb);
-                        return INSN_GOOD;
-                }
-                case DECODE_TYPE_OR:
-                        matched = true;
-                        break;
-                case DECODE_TYPE_REJECT:
-                default:
-                        return INSN_REJECTED;
-                }
-                }
-        }
diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
index 839312905067..9db4b659d03e 100644
--- a/arch/arm/kernel/kprobes-test-arm.c
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -10,6 +10,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <asm/system_info.h>
+#include <asm/opcodes.h>
 #include "kprobes-test.h"
@@ -158,9 +160,9 @@ void kprobe_arm_test_cases(void)
        TEST_SUPPORTED("cmp     sp, #0x1000");
        /* Data-processing with PC as shift*/
-        TEST_UNSUPPORTED(".word 0xe15c0f1e      @ cmp   r12, r14, asl pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe15c0f1e) "       @ cmp   r12, r14, asl pc")
-        TEST_UNSUPPORTED(".word 0xe1a0cf1e      @ mov   r12, r14, asl pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe1a0cf1e) "       @ mov   r12, r14, asl pc")
-        TEST_UNSUPPORTED(".word 0xe08caf1e      @ add   r10, r12, r14, asl pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe08caf1e) "       @ add   r10, r12, r14, asl pc")
        /* Data-processing with PC as shift*/
        TEST_UNSUPPORTED("movs  pc, r1")
@@ -202,7 +204,7 @@ void kprobe_arm_test_cases(void)
        TEST("mrs       r0, cpsr")
        TEST("mrspl     r7, cpsr")
        TEST("mrs       r14, cpsr")
-        TEST_UNSUPPORTED(".word 0xe10ff000      @ mrs r15, cpsr")
+        TEST_UNSUPPORTED(__inst_arm(0xe10ff000) "       @ mrs r15, cpsr")
        TEST_UNSUPPORTED("mrs   r0, spsr")
        TEST_UNSUPPORTED("mrs   lr, spsr")
@@ -218,8 +220,8 @@ void kprobe_arm_test_cases(void)
        TEST_R("clzeq   r7, r",14,0x1,"")
        TEST_R("clz     lr, r",7, 0xffffffff,"")
        TEST(  "clz     r4, sp")
-        TEST_UNSUPPORTED(".word 0x016fff10      @ clz pc, r0")
+        TEST_UNSUPPORTED(__inst_arm(0x016fff10) "       @ clz pc, r0")
-        TEST_UNSUPPORTED(".word 0x016f0f1f      @ clz r0, pc")
+        TEST_UNSUPPORTED(__inst_arm(0x016f0f1f) "       @ clz r0, pc")
 #if __LINUX_ARM_ARCH__ >= 6
        TEST_UNSUPPORTED("bxj   r0")
@@ -228,7 +230,7 @@ void kprobe_arm_test_cases(void)
        TEST_BF_R("blx  r",0,2f,"")
        TEST_BB_R("blx  r",7,2f,"")
        TEST_BF_R("blxeq        r",14,2f,"")
-        TEST_UNSUPPORTED(".word 0x0120003f      @ blx pc")
+        TEST_UNSUPPORTED(__inst_arm(0x0120003f) "       @ blx pc")
        TEST_RR(   "qadd        r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(   "qaddvs      lr, r",9, VAL2,", r",8, VAL1,"")
@@ -242,190 +244,190 @@ void kprobe_arm_test_cases(void)
        TEST_RR(   "qdsub       r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(   "qdsubvs     lr, r",9, VAL2,", r",8, VAL1,"")
        TEST_R(    "qdsub       lr, r",9, VAL2,", r13")
-        TEST_UNSUPPORTED(".word 0xe101f050      @ qadd pc, r0, r1")
+        TEST_UNSUPPORTED(__inst_arm(0xe101f050) "       @ qadd pc, r0, r1")
-        TEST_UNSUPPORTED(".word 0xe121f050      @ qsub pc, r0, r1")
+        TEST_UNSUPPORTED(__inst_arm(0xe121f050) "       @ qsub pc, r0, r1")
-        TEST_UNSUPPORTED(".word 0xe141f050      @ qdadd pc, r0, r1")
+        TEST_UNSUPPORTED(__inst_arm(0xe141f050) "       @ qdadd pc, r0, r1")
-        TEST_UNSUPPORTED(".word 0xe161f050      @ qdsub pc, r0, r1")
+        TEST_UNSUPPORTED(__inst_arm(0xe161f050) "       @ qdsub pc, r0, r1")
-        TEST_UNSUPPORTED(".word 0xe16f2050      @ qdsub r2, r0, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe16f2050) "       @ qdsub r2, r0, pc")
-        TEST_UNSUPPORTED(".word 0xe161205f      @ qdsub r2, pc, r1")
+        TEST_UNSUPPORTED(__inst_arm(0xe161205f) "       @ qdsub r2, pc, r1")
        TEST_UNSUPPORTED("bkpt  0xffff")
        TEST_UNSUPPORTED("bkpt  0x0000")
-        TEST_UNSUPPORTED(".word 0xe1600070 @ smc #0")
+        TEST_UNSUPPORTED(__inst_arm(0xe1600070) " @ smc #0")
        TEST_GROUP("Halfword multiply and multiply-accumulate")
        TEST_RRR(    "smlabb    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(    "smlabbge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
        TEST_RR(     "smlabb    lr, r",1, VAL2,", r",2, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe10f3281 @ smlabb pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe10f3281) " @ smlabb pc, r1, r2, r3")
        TEST_RRR(    "smlatb    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(    "smlatbge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
        TEST_RR(     "smlatb    lr, r",1, VAL2,", r",2, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe10f32a1 @ smlatb pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe10f32a1) " @ smlatb pc, r1, r2, r3")
        TEST_RRR(    "smlabt    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(    "smlabtge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
        TEST_RR(     "smlabt    lr, r",1, VAL2,", r",2, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe10f32c1 @ smlabt pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe10f32c1) " @ smlabt pc, r1, r2, r3")
        TEST_RRR(    "smlatt    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(    "smlattge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
        TEST_RR(     "smlatt    lr, r",1, VAL2,", r",2, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe10f32e1 @ smlatt pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe10f32e1) " @ smlatt pc, r1, r2, r3")
        TEST_RRR(    "smlawb    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(    "smlawbge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
        TEST_RR(     "smlawb    lr, r",1, VAL2,", r",2, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe12f3281 @ smlawb pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe12f3281) " @ smlawb pc, r1, r2, r3")
        TEST_RRR(    "smlawt    r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(    "smlawtge  r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
        TEST_RR(     "smlawt    lr, r",1, VAL2,", r",2, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe12f32c1 @ smlawt pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe12f32c1) " @ smlawt pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe12032cf @ smlawt r0, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe12032cf) " @ smlawt r0, pc, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe1203fc1 @ smlawt r0, r1, pc, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe1203fc1) " @ smlawt r0, r1, pc, r3")
-        TEST_UNSUPPORTED(".word 0xe120f2c1 @ smlawt r0, r1, r2, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe120f2c1) " @ smlawt r0, r1, r2, pc")
        TEST_RR(    "smulwb     r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(    "smulwbge   r7, r",8, VAL3,", r",9, VAL1,"")
        TEST_R(     "smulwb     lr, r",1, VAL2,", r13")
-        TEST_UNSUPPORTED(".word 0xe12f02a1 @ smulwb pc, r1, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe12f02a1) " @ smulwb pc, r1, r2")
        TEST_RR(    "smulwt     r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(    "smulwtge   r7, r",8, VAL3,", r",9, VAL1,"")
        TEST_R(     "smulwt     lr, r",1, VAL2,", r13")
-        TEST_UNSUPPORTED(".word 0xe12f02e1 @ smulwt pc, r1, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe12f02e1) " @ smulwt pc, r1, r2")
        TEST_RRRR(  "smlalbb    r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
        TEST_RRRR(  "smlalbble  r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
        TEST_RRR(   "smlalbb    r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
-        TEST_UNSUPPORTED(".word 0xe14f1382 @ smlalbb pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe14f1382) " @ smlalbb pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe141f382 @ smlalbb r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe141f382) " @ smlalbb r1, pc, r2, r3")
        TEST_RRRR(  "smlaltb    r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
        TEST_RRRR(  "smlaltble  r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
        TEST_RRR(   "smlaltb    r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
-        TEST_UNSUPPORTED(".word 0xe14f13a2 @ smlaltb pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe14f13a2) " @ smlaltb pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe141f3a2 @ smlaltb r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe141f3a2) " @ smlaltb r1, pc, r2, r3")
        TEST_RRRR(  "smlalbt    r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
        TEST_RRRR(  "smlalbtle  r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
        TEST_RRR(   "smlalbt    r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
-        TEST_UNSUPPORTED(".word 0xe14f13c2 @ smlalbt pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe14f13c2) " @ smlalbt pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe141f3c2 @ smlalbt r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe141f3c2) " @ smlalbt r1, pc, r2, r3")
        TEST_RRRR(  "smlaltt    r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
        TEST_RRRR(  "smlalttle  r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
        TEST_RRR(   "smlaltt    r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
-        TEST_UNSUPPORTED(".word 0xe14f13e2 @ smlalbb pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe14f13e2) " @ smlalbb pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe140f3e2 @ smlalbb r0, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe140f3e2) " @ smlalbb r0, pc, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe14013ef @ smlalbb r0, r1, pc, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe14013ef) " @ smlalbb r0, r1, pc, r3")
-        TEST_UNSUPPORTED(".word 0xe1401fe2 @ smlalbb r0, r1, r2, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe1401fe2) " @ smlalbb r0, r1, r2, pc")
        TEST_RR(    "smulbb     r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(    "smulbbge   r7, r",8, VAL3,", r",9, VAL1,"")
        TEST_R(     "smulbb     lr, r",1, VAL2,", r13")
-        TEST_UNSUPPORTED(".word 0xe16f0281 @ smulbb pc, r1, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe16f0281) " @ smulbb pc, r1, r2")
        TEST_RR(    "smultb     r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(    "smultbge   r7, r",8, VAL3,", r",9, VAL1,"")
        TEST_R(     "smultb     lr, r",1, VAL2,", r13")
-        TEST_UNSUPPORTED(".word 0xe16f02a1 @ smultb pc, r1, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe16f02a1) " @ smultb pc, r1, r2")
        TEST_RR(    "smulbt     r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(    "smulbtge   r7, r",8, VAL3,", r",9, VAL1,"")
        TEST_R(     "smulbt     lr, r",1, VAL2,", r13")
-        TEST_UNSUPPORTED(".word 0xe16f02c1 @ smultb pc, r1, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe16f02c1) " @ smultb pc, r1, r2")
        TEST_RR(    "smultt     r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(    "smulttge   r7, r",8, VAL3,", r",9, VAL1,"")
        TEST_R(     "smultt     lr, r",1, VAL2,", r13")
-        TEST_UNSUPPORTED(".word 0xe16f02e1 @ smultt pc, r1, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe16f02e1) " @ smultt pc, r1, r2")
-        TEST_UNSUPPORTED(".word 0xe16002ef @ smultt r0, pc, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe16002ef) " @ smultt r0, pc, r2")
-        TEST_UNSUPPORTED(".word 0xe1600fe1 @ smultt r0, r1, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe1600fe1) " @ smultt r0, r1, pc")
        TEST_GROUP("Multiply and multiply-accumulate")
        TEST_RR(    "mul        r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(    "mulls      r7, r",8, VAL2,", r",9, VAL2,"")
        TEST_R(     "mul        lr, r",4, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe00f0291 @ mul pc, r1, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe00f0291) " @ mul pc, r1, r2")
-        TEST_UNSUPPORTED(".word 0xe000029f @ mul r0, pc, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe000029f) " @ mul r0, pc, r2")
-        TEST_UNSUPPORTED(".word 0xe0000f91 @ mul r0, r1, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe0000f91) " @ mul r0, r1, pc")
        TEST_RR(    "muls       r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(    "mullss     r7, r",8, VAL2,", r",9, VAL2,"")
        TEST_R(     "muls       lr, r",4, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe01f0291 @ muls pc, r1, r2")
+        TEST_UNSUPPORTED(__inst_arm(0xe01f0291) " @ muls pc, r1, r2")
        TEST_RRR(    "mla       r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(    "mlahi     r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
        TEST_RR(     "mla       lr, r",1, VAL2,", r",2, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe02f3291 @ mla pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe02f3291) " @ mla pc, r1, r2, r3")
        TEST_RRR(    "mlas      r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(    "mlahis    r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
        TEST_RR(     "mlas      lr, r",1, VAL2,", r",2, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe03f3291 @ mlas pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe03f3291) " @ mlas pc, r1, r2, r3")
 #if __LINUX_ARM_ARCH__ >= 6
        TEST_RR(  "umaal        r0, r1, r",2, VAL1,", r",3, VAL2,"")
        TEST_RR(  "umaalls      r7, r8, r",9, VAL2,", r",10, VAL1,"")
        TEST_R(   "umaal        lr, r12, r",11,VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe041f392 @ umaal pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe041f392) " @ umaal pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe04f0392 @ umaal r0, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe04f0392) " @ umaal r0, pc, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
+        TEST_UNSUPPORTED(__inst_arm(0xe0500090) " @ undef")
-        TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
+        TEST_UNSUPPORTED(__inst_arm(0xe05fff9f) " @ undef")
 #endif
 #if __LINUX_ARM_ARCH__ >= 7
        TEST_RRR(  "mls         r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(  "mlshi       r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
        TEST_RR(   "mls         lr, r",1, VAL2,", r",2, VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe06f3291) " @ mls pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe060329f) " @ mls r0, pc, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0603f91) " @ mls r0, r1, pc, r3")
-        TEST_UNSUPPORTED(".word 0xe060f291 @ mls r0, r1, r2, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe060f291) " @ mls r0, r1, r2, pc")
 #endif
-        TEST_UNSUPPORTED(".word 0xe0700090 @ undef")
+        TEST_UNSUPPORTED(__inst_arm(0xe0700090) " @ undef")
-        TEST_UNSUPPORTED(".word 0xe07fff9f @ undef")
+        TEST_UNSUPPORTED(__inst_arm(0xe07fff9f) " @ undef")
        TEST_RR(  "umull        r0, r1, r",2, VAL1,", r",3, VAL2,"")
        TEST_RR(  "umullls      r7, r8, r",9, VAL2,", r",10, VAL1,"")
        TEST_R(   "umull        lr, r12, r",11,VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe081f392 @ umull pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe081f392) " @ umull pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe08f1392 @ umull r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe08f1392) " @ umull r1, pc, r2, r3")
        TEST_RR(  "umulls       r0, r1, r",2, VAL1,", r",3, VAL2,"")
        TEST_RR(  "umulllss     r7, r8, r",9, VAL2,", r",10, VAL1,"")
        TEST_R(   "umulls       lr, r12, r",11,VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe091f392 @ umulls pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe091f392) " @ umulls pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe09f1392 @ umulls r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe09f1392) " @ umulls r1, pc, r2, r3")
        TEST_RRRR(  "umlal      r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
        TEST_RRRR(  "umlalle    r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
        TEST_RRR(   "umlal      r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
-        TEST_UNSUPPORTED(".word 0xe0af1392 @ umlal pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0af1392) " @ umlal pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe0a1f392 @ umlal r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0a1f392) " @ umlal r1, pc, r2, r3")
        TEST_RRRR(  "umlals     r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
        TEST_RRRR(  "umlalles   r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
        TEST_RRR(   "umlals     r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
-        TEST_UNSUPPORTED(".word 0xe0bf1392 @ umlals pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0bf1392) " @ umlals pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe0b1f392 @ umlals r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0b1f392) " @ umlals r1, pc, r2, r3")
        TEST_RR(  "smull        r0, r1, r",2, VAL1,", r",3, VAL2,"")
        TEST_RR(  "smullls      r7, r8, r",9, VAL2,", r",10, VAL1,"")
        TEST_R(   "smull        lr, r12, r",11,VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe0c1f392 @ smull pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0c1f392) " @ smull pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe0cf1392 @ smull r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0cf1392) " @ smull r1, pc, r2, r3")
        TEST_RR(  "smulls       r0, r1, r",2, VAL1,", r",3, VAL2,"")
        TEST_RR(  "smulllss     r7, r8, r",9, VAL2,", r",10, VAL1,"")
        TEST_R(   "smulls       lr, r12, r",11,VAL3,", r13")
-        TEST_UNSUPPORTED(".word 0xe0d1f392 @ smulls pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0d1f392) " @ smulls pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe0df1392 @ smulls r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0df1392) " @ smulls r1, pc, r2, r3")
        TEST_RRRR(  "smlal      r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
        TEST_RRRR(  "smlalle    r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
        TEST_RRR(   "smlal      r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
-        TEST_UNSUPPORTED(".word 0xe0ef1392 @ smlal pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0ef1392) " @ smlal pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe0e1f392 @ smlal r1, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0e1f392) " @ smlal r1, pc, r2, r3")
        TEST_RRRR(  "smlals     r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
        TEST_RRRR(  "smlalles   r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
        TEST_RRR(   "smlals     r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
-        TEST_UNSUPPORTED(".word 0xe0ff1392 @ smlals pc, r1, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0ff1392) " @ smlals pc, r1, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe0f0f392 @ smlals r0, pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0f0f392) " @ smlals r0, pc, r2, r3")
-        TEST_UNSUPPORTED(".word 0xe0f0139f @ smlals r0, r1, pc, r3")
+        TEST_UNSUPPORTED(__inst_arm(0xe0f0139f) " @ smlals r0, r1, pc, r3")
-        TEST_UNSUPPORTED(".word 0xe0f01f92 @ smlals r0, r1, r2, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe0f01f92) " @ smlals r0, r1, r2, pc")
        TEST_GROUP("Synchronization primitives")
@@ -434,28 +436,28 @@ void kprobe_arm_test_cases(void)
        TEST_R( "swpvs  r0, r",1,VAL1,", [sp]")
        TEST_RP("swp    sp, r",14,VAL2,", [r",12,13*4,"]")
 #else
-        TEST_UNSUPPORTED(".word 0xe108e097 @ swp        lr, r7, [r8]")
+        TEST_UNSUPPORTED(__inst_arm(0xe108e097) " @ swp lr, r7, [r8]")
-        TEST_UNSUPPORTED(".word 0x610d0091 @ swpvs      r0, r1, [sp]")
+        TEST_UNSUPPORTED(__inst_arm(0x610d0091) " @ swpvs       r0, r1, [sp]")
-        TEST_UNSUPPORTED(".word 0xe10cd09e @ swp        sp, r14 [r12]")
+        TEST_UNSUPPORTED(__inst_arm(0xe10cd09e) " @ swp sp, r14 [r12]")
 #endif
-        TEST_UNSUPPORTED(".word 0xe102f091 @ swp pc, r1, [r2]")
+        TEST_UNSUPPORTED(__inst_arm(0xe102f091) " @ swp pc, r1, [r2]")
-        TEST_UNSUPPORTED(".word 0xe102009f @ swp r0, pc, [r2]")
+        TEST_UNSUPPORTED(__inst_arm(0xe102009f) " @ swp r0, pc, [r2]")
-        TEST_UNSUPPORTED(".word 0xe10f0091 @ swp r0, r1, [pc]")
+        TEST_UNSUPPORTED(__inst_arm(0xe10f0091) " @ swp r0, r1, [pc]")
 #if __LINUX_ARM_ARCH__ < 6
        TEST_RP("swpb   lr, r",7,VAL2,", [r",8,0,"]")
        TEST_R( "swpvsb r0, r",1,VAL1,", [sp]")
 #else
-        TEST_UNSUPPORTED(".word 0xe148e097 @ swpb       lr, r7, [r8]")
+        TEST_UNSUPPORTED(__inst_arm(0xe148e097) " @ swpb        lr, r7, [r8]")
-        TEST_UNSUPPORTED(".word 0x614d0091 @ swpvsb     r0, r1, [sp]")
+        TEST_UNSUPPORTED(__inst_arm(0x614d0091) " @ swpvsb      r0, r1, [sp]")
 #endif
-        TEST_UNSUPPORTED(".word 0xe142f091 @ swpb pc, r1, [r2]")
+        TEST_UNSUPPORTED(__inst_arm(0xe142f091) " @ swpb pc, r1, [r2]")
-        TEST_UNSUPPORTED(".word 0xe1100090") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe1100090)) /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe1200090") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe1200090)) /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe1300090") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe1300090)) /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe1500090") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe1500090)) /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe1600090") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe1600090)) /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe1700090") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe1700090)) /* Unallocated space */
 #if __LINUX_ARM_ARCH__ >= 6
        TEST_UNSUPPORTED("ldrex r2, [sp]")
 #endif
@@ -475,9 +477,9 @@ void kprobe_arm_test_cases(void)
        TEST_RPR(  "strneh      r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
        TEST_RPR(  "strh        r",2, VAL1,", [r",3, 24,"], r",4, 48,"")
        TEST_RPR(  "strh        r",10,VAL2,", [r",9, 48,"], -r",11,24,"")
-        TEST_UNSUPPORTED(".word 0xe1afc0ba      @ strh r12, [pc, r10]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1afc0ba) "       @ strh r12, [pc, r10]!")
-        TEST_UNSUPPORTED(".word 0xe089f0bb      @ strh pc, [r9], r11")
+        TEST_UNSUPPORTED(__inst_arm(0xe089f0bb) "       @ strh pc, [r9], r11")
-        TEST_UNSUPPORTED(".word 0xe089a0bf      @ strh r10, [r9], pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe089a0bf) "       @ strh r10, [r9], pc")
        TEST_PR(   "ldrh        r0, [r",0,  48,", -r",2, 24,"]")
        TEST_PR(   "ldrcsh      r14, [r",13,0, ", r",12, 48,"]")
@@ -485,9 +487,9 @@ void kprobe_arm_test_cases(void)
        TEST_PR(   "ldrcch      r12, [r",11,48,", -r",10,24,"]!")
        TEST_PR(   "ldrh        r2, [r",3,  24,"], r",4, 48,"")
        TEST_PR(   "ldrh        r10, [r",9, 48,"], -r",11,24,"")
-        TEST_UNSUPPORTED(".word 0xe1bfc0ba      @ ldrh r12, [pc, r10]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1bfc0ba) "       @ ldrh r12, [pc, r10]!")
-        TEST_UNSUPPORTED(".word 0xe099f0bb      @ ldrh pc, [r9], r11")
+        TEST_UNSUPPORTED(__inst_arm(0xe099f0bb) "       @ ldrh pc, [r9], r11")
-        TEST_UNSUPPORTED(".word 0xe099a0bf      @ ldrh r10, [r9], pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe099a0bf) "       @ ldrh r10, [r9], pc")
        TEST_RP(   "strh        r",0, VAL1,", [r",1, 24,", #-2]")
        TEST_RP(   "strmih      r",14,VAL2,", [r",13,0, ", #2]")
@@ -495,8 +497,8 @@ void kprobe_arm_test_cases(void)
        TEST_RP(   "strplh      r",12,VAL2,", [r",11,24,", #-4]!")
        TEST_RP(   "strh        r",2, VAL1,", [r",3, 24,"], #48")
        TEST_RP(   "strh        r",10,VAL2,", [r",9, 64,"], #-48")
-        TEST_UNSUPPORTED(".word 0xe1efc3b0      @ strh r12, [pc, #48]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1efc3b0) "       @ strh r12, [pc, #48]!")
-        TEST_UNSUPPORTED(".word 0xe0c9f3b0      @ strh pc, [r9], #48")
+        TEST_UNSUPPORTED(__inst_arm(0xe0c9f3b0) "       @ strh pc, [r9], #48")
        TEST_P(    "ldrh        r0, [r",0,  24,", #-2]")
        TEST_P(    "ldrvsh      r14, [r",13,0, ", #2]")
@@ -505,8 +507,8 @@ void kprobe_arm_test_cases(void)
        TEST_P(    "ldrh        r2, [r",3,  24,"], #48")
        TEST_P(    "ldrh        r10, [r",9, 64,"], #-48")
        TEST(      "ldrh        r0, [pc, #0]")
-        TEST_UNSUPPORTED(".word 0xe1ffc3b0      @ ldrh r12, [pc, #48]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1ffc3b0) "       @ ldrh r12, [pc, #48]!")
-        TEST_UNSUPPORTED(".word 0xe0d9f3b0      @ ldrh pc, [r9], #48")
+        TEST_UNSUPPORTED(__inst_arm(0xe0d9f3b0) "       @ ldrh pc, [r9], #48")
        TEST_PR(   "ldrsb       r0, [r",0,  48,", -r",2, 24,"]")
        TEST_PR(   "ldrhisb     r14, [r",13,0,", r",12,  48,"]")
@@ -514,8 +516,8 @@ void kprobe_arm_test_cases(void)
        TEST_PR(   "ldrlssb     r12, [r",11,48,", -r",10,24,"]!")
        TEST_PR(   "ldrsb       r2, [r",3,  24,"], r",4, 48,"")
        TEST_PR(   "ldrsb       r10, [r",9, 48,"], -r",11,24,"")
-        TEST_UNSUPPORTED(".word 0xe1bfc0da      @ ldrsb r12, [pc, r10]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1bfc0da) "       @ ldrsb r12, [pc, r10]!")
-        TEST_UNSUPPORTED(".word 0xe099f0db      @ ldrsb pc, [r9], r11")
+        TEST_UNSUPPORTED(__inst_arm(0xe099f0db) "       @ ldrsb pc, [r9], r11")
        TEST_P(    "ldrsb       r0, [r",0,  24,", #-1]")
        TEST_P(    "ldrgesb     r14, [r",13,0, ", #1]")
@@ -524,8 +526,8 @@ void kprobe_arm_test_cases(void)
        TEST_P(    "ldrsb       r2, [r",3,  24,"], #48")
        TEST_P(    "ldrsb       r10, [r",9, 64,"], #-48")
        TEST(      "ldrsb       r0, [pc, #0]")
-        TEST_UNSUPPORTED(".word 0xe1ffc3d0      @ ldrsb r12, [pc, #48]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1ffc3d0) "       @ ldrsb r12, [pc, #48]!")
-        TEST_UNSUPPORTED(".word 0xe0d9f3d0      @ ldrsb pc, [r9], #48")
+        TEST_UNSUPPORTED(__inst_arm(0xe0d9f3d0) "       @ ldrsb pc, [r9], #48")
        TEST_PR(   "ldrsh       r0, [r",0,  48,", -r",2, 24,"]")
        TEST_PR(   "ldrgtsh     r14, [r",13,0, ", r",12, 48,"]")
@@ -533,8 +535,8 @@ void kprobe_arm_test_cases(void)
        TEST_PR(   "ldrlesh     r12, [r",11,48,", -r",10,24,"]!")
        TEST_PR(   "ldrsh       r2, [r",3,  24,"], r",4, 48,"")
        TEST_PR(   "ldrsh       r10, [r",9, 48,"], -r",11,24,"")
-        TEST_UNSUPPORTED(".word 0xe1bfc0fa      @ ldrsh r12, [pc, r10]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1bfc0fa) "       @ ldrsh r12, [pc, r10]!")
-        TEST_UNSUPPORTED(".word 0xe099f0fb      @ ldrsh pc, [r9], r11")
+        TEST_UNSUPPORTED(__inst_arm(0xe099f0fb) "       @ ldrsh pc, [r9], r11")
        TEST_P(    "ldrsh       r0, [r",0,  24,", #-1]")
        TEST_P(    "ldreqsh     r14, [r",13,0 ,", #1]")
@@ -543,8 +545,8 @@ void kprobe_arm_test_cases(void)
        TEST_P(    "ldrsh       r2, [r",3,  24,"], #48")
        TEST_P(    "ldrsh       r10, [r",9, 64,"], #-48")
        TEST(      "ldrsh       r0, [pc, #0]")
-        TEST_UNSUPPORTED(".word 0xe1ffc3f0      @ ldrsh r12, [pc, #48]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1ffc3f0) "       @ ldrsh r12, [pc, #48]!")
-        TEST_UNSUPPORTED(".word 0xe0d9f3f0      @ ldrsh pc, [r9], #48")
+        TEST_UNSUPPORTED(__inst_arm(0xe0d9f3f0) "       @ ldrsh pc, [r9], #48")
 #if __LINUX_ARM_ARCH__ >= 7
        TEST_UNSUPPORTED("strht r1, [r2], r3")
@@ -563,7 +565,7 @@ void kprobe_arm_test_cases(void)
        TEST_RPR(  "strcsd      r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
        TEST_RPR(  "strd        r",2, VAL1,", [r",5, 24,"], r",4,48,"")
        TEST_RPR(  "strd        r",10,VAL2,", [r",9, 48,"], -r",7,24,"")
-        TEST_UNSUPPORTED(".word 0xe1afc0fa      @ strd r12, [pc, r10]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1afc0fa) "       @ strd r12, [pc, r10]!")
        TEST_PR(   "ldrd        r0, [r",0, 48,", -r",2,24,"]")
        TEST_PR(   "ldrmid      r8, [r",13,0, ", r",12,48,"]")
@@ -571,10 +573,10 @@ void kprobe_arm_test_cases(void)
        TEST_PR(   "ldrpld      r6, [r",11,48,", -r",10,24,"]!")
        TEST_PR(   "ldrd        r2, [r",5, 24,"], r",4,48,"")
        TEST_PR(   "ldrd        r10, [r",9,48,"], -r",7,24,"")
-        TEST_UNSUPPORTED(".word 0xe1afc0da      @ ldrd r12, [pc, r10]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1afc0da) "       @ ldrd r12, [pc, r10]!")
-        TEST_UNSUPPORTED(".word 0xe089f0db      @ ldrd pc, [r9], r11")
+        TEST_UNSUPPORTED(__inst_arm(0xe089f0db) "       @ ldrd pc, [r9], r11")
-        TEST_UNSUPPORTED(".word 0xe089e0db      @ ldrd lr, [r9], r11")
+        TEST_UNSUPPORTED(__inst_arm(0xe089e0db) "       @ ldrd lr, [r9], r11")
-        TEST_UNSUPPORTED(".word 0xe089c0df      @ ldrd r12, [r9], pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe089c0df) "       @ ldrd r12, [r9], pc")
        TEST_RP(   "strd        r",0, VAL1,", [r",1, 24,", #-8]")
        TEST_RP(   "strvsd      r",8, VAL2,", [r",13,0, ", #8]")
@@ -582,7 +584,7 @@ void kprobe_arm_test_cases(void)
        TEST_RP(   "strvcd      r",12,VAL2,", [r",11,24,", #-16]!")
        TEST_RP(   "strd        r",2, VAL1,", [r",4, 24,"], #48")
        TEST_RP(   "strd        r",10,VAL2,", [r",9, 64,"], #-48")
-        TEST_UNSUPPORTED(".word 0xe1efc3f0      @ strd r12, [pc, #48]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1efc3f0) "       @ strd r12, [pc, #48]!")
        TEST_P(    "ldrd        r0, [r",0, 24,", #-8]")
        TEST_P(    "ldrhid      r8, [r",13,0, ", #8]")
@@ -590,9 +592,9 @@ void kprobe_arm_test_cases(void)
        TEST_P(    "ldrlsd      r6, [r",11,24,", #-16]!")
        TEST_P(    "ldrd        r2, [r",5, 24,"], #48")
        TEST_P(    "ldrd        r10, [r",9,6,"], #-48")
-        TEST_UNSUPPORTED(".word 0xe1efc3d0      @ ldrd r12, [pc, #48]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe1efc3d0) "       @ ldrd r12, [pc, #48]!")
-        TEST_UNSUPPORTED(".word 0xe0c9f3d0      @ ldrd pc, [r9], #48")
+        TEST_UNSUPPORTED(__inst_arm(0xe0c9f3d0) "       @ ldrd pc, [r9], #48")
-        TEST_UNSUPPORTED(".word 0xe0c9e3d0      @ ldrd lr, [r9], #48")
+        TEST_UNSUPPORTED(__inst_arm(0xe0c9e3d0) "       @ ldrd lr, [r9], #48")
        TEST_GROUP("Miscellaneous")
@@ -600,11 +602,11 @@ void kprobe_arm_test_cases(void)
        TEST("movw      r0, #0")
        TEST("movw      r0, #0xffff")
        TEST("movw      lr, #0xffff")
-        TEST_UNSUPPORTED(".word 0xe300f000      @ movw pc, #0")
+        TEST_UNSUPPORTED(__inst_arm(0xe300f000) "       @ movw pc, #0")
        TEST_R("movt    r",0, VAL1,", #0")
        TEST_R("movt    r",0, VAL2,", #0xffff")
        TEST_R("movt    r",14,VAL1,", #0xffff")
-        TEST_UNSUPPORTED(".word 0xe340f000      @ movt pc, #0")
+        TEST_UNSUPPORTED(__inst_arm(0xe340f000) "       @ movt pc, #0")
 #endif
        TEST_UNSUPPORTED("msr   cpsr, 0x13")
@@ -672,20 +674,20 @@ void kprobe_arm_test_cases(void)
 #ifdef CONFIG_THUMB2_KERNEL
        TEST_ARM_TO_THUMB_INTERWORK_P("ldr      pc, [r",0,0,", #15*4]")
 #endif
-        TEST_UNSUPPORTED(".word 0xe5af6008      @ str r6, [pc, #8]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe5af6008) "       @ str r6, [pc, #8]!")
-        TEST_UNSUPPORTED(".word 0xe7af6008      @ str r6, [pc, r8]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe7af6008) "       @ str r6, [pc, r8]!")
-        TEST_UNSUPPORTED(".word 0xe5bf6008      @ ldr r6, [pc, #8]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe5bf6008) "       @ ldr r6, [pc, #8]!")
-        TEST_UNSUPPORTED(".word 0xe7bf6008      @ ldr r6, [pc, r8]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe7bf6008) "       @ ldr r6, [pc, r8]!")
-        TEST_UNSUPPORTED(".word 0xe788600f      @ str r6, [r8, pc]")
+        TEST_UNSUPPORTED(__inst_arm(0xe788600f) "       @ str r6, [r8, pc]")
-        TEST_UNSUPPORTED(".word 0xe798600f      @ ldr r6, [r8, pc]")
+        TEST_UNSUPPORTED(__inst_arm(0xe798600f) "       @ ldr r6, [r8, pc]")
        LOAD_STORE("b")
-        TEST_UNSUPPORTED(".word 0xe5f7f008      @ ldrb pc, [r7, #8]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe5f7f008) "       @ ldrb pc, [r7, #8]!")
-        TEST_UNSUPPORTED(".word 0xe7f7f008      @ ldrb pc, [r7, r8]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe7f7f008) "       @ ldrb pc, [r7, r8]!")
-        TEST_UNSUPPORTED(".word 0xe5ef6008      @ strb r6, [pc, #8]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe5ef6008) "       @ strb r6, [pc, #8]!")
-        TEST_UNSUPPORTED(".word 0xe7ef6008      @ strb r6, [pc, r3]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe7ef6008) "       @ strb r6, [pc, r3]!")
-        TEST_UNSUPPORTED(".word 0xe5ff6008      @ ldrb r6, [pc, #8]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe5ff6008) "       @ ldrb r6, [pc, #8]!")
-        TEST_UNSUPPORTED(".word 0xe7ff6008      @ ldrb r6, [pc, r3]!")
+        TEST_UNSUPPORTED(__inst_arm(0xe7ff6008) "       @ ldrb r6, [pc, r3]!")
        TEST_UNSUPPORTED("ldrt  r0, [r1], #4")
        TEST_UNSUPPORTED("ldrt  r1, [r2], r3")
@@ -699,153 +701,153 @@ void kprobe_arm_test_cases(void)
 #if __LINUX_ARM_ARCH__ >= 7
        TEST_GROUP("Parallel addition and subtraction, signed")
-        TEST_UNSUPPORTED(".word 0xe6000010") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe6000010) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe60fffff") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe60fffff) "") /* Unallocated space */
        TEST_RR(    "sadd16     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "sadd16     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe61cff1a      @ sadd16        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe61cff1a) "       @ sadd16        pc, r12, r10")
        TEST_RR(    "sasx       r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "sasx       r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe61cff3a      @ sasx  pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe61cff3a) "       @ sasx  pc, r12, r10")
        TEST_RR(    "ssax       r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "ssax       r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe61cff5a      @ ssax  pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe61cff5a) "       @ ssax  pc, r12, r10")
        TEST_RR(    "ssub16     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "ssub16     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe61cff7a      @ ssub16        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe61cff7a) "       @ ssub16        pc, r12, r10")
        TEST_RR(    "sadd8      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "sadd8      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe61cff9a      @ sadd8 pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe61cff9a) "       @ sadd8 pc, r12, r10")
-        TEST_UNSUPPORTED(".word 0xe61000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe61000b0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe61fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe61fffbf) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe61000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe61000d0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe61fffdf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe61fffdf) "") /* Unallocated space */
        TEST_RR(    "ssub8      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "ssub8      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe61cfffa      @ ssub8 pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe61cfffa) "       @ ssub8 pc, r12, r10")
        TEST_RR(    "qadd16     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "qadd16     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe62cff1a      @ qadd16        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe62cff1a) "       @ qadd16        pc, r12, r10")
        TEST_RR(    "qasx       r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "qasx       r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe62cff3a      @ qasx  pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe62cff3a) "       @ qasx  pc, r12, r10")
        TEST_RR(    "qsax       r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "qsax       r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe62cff5a      @ qsax  pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe62cff5a) "       @ qsax  pc, r12, r10")
        TEST_RR(    "qsub16     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "qsub16     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe62cff7a      @ qsub16        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe62cff7a) "       @ qsub16        pc, r12, r10")
        TEST_RR(    "qadd8      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "qadd8      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe62cff9a      @ qadd8 pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe62cff9a) "       @ qadd8 pc, r12, r10")
-        TEST_UNSUPPORTED(".word 0xe62000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe62000b0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe62fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe62fffbf) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe62000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe62000d0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe62fffdf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe62fffdf) "") /* Unallocated space */
        TEST_RR(    "qsub8      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "qsub8      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe62cfffa      @ qsub8 pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe62cfffa) "       @ qsub8 pc, r12, r10")
        TEST_RR(    "shadd16    r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "shadd16    r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe63cff1a      @ shadd16       pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe63cff1a) "       @ shadd16       pc, r12, r10")
        TEST_RR(    "shasx      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "shasx      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe63cff3a      @ shasx pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe63cff3a) "       @ shasx pc, r12, r10")
        TEST_RR(    "shsax      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "shsax      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe63cff5a      @ shsax pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe63cff5a) "       @ shsax pc, r12, r10")
        TEST_RR(    "shsub16    r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "shsub16    r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe63cff7a      @ shsub16       pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe63cff7a) "       @ shsub16       pc, r12, r10")
        TEST_RR(    "shadd8     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "shadd8     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe63cff9a      @ shadd8        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe63cff9a) "       @ shadd8        pc, r12, r10")
-        TEST_UNSUPPORTED(".word 0xe63000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe63000b0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe63fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe63fffbf) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe63000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe63000d0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe63fffdf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe63fffdf) "") /* Unallocated space */
        TEST_RR(    "shsub8     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "shsub8     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe63cfffa      @ shsub8        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe63cfffa) "       @ shsub8        pc, r12, r10")
        TEST_GROUP("Parallel addition and subtraction, unsigned")
-        TEST_UNSUPPORTED(".word 0xe6400010") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe6400010) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe64fffff") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe64fffff) "") /* Unallocated space */
        TEST_RR(    "uadd16     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uadd16     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe65cff1a      @ uadd16        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe65cff1a) "       @ uadd16        pc, r12, r10")
        TEST_RR(    "uasx       r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uasx       r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe65cff3a      @ uasx  pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe65cff3a) "       @ uasx  pc, r12, r10")
        TEST_RR(    "usax       r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "usax       r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe65cff5a      @ usax  pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe65cff5a) "       @ usax  pc, r12, r10")
        TEST_RR(    "usub16     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "usub16     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe65cff7a      @ usub16        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe65cff7a) "       @ usub16        pc, r12, r10")
        TEST_RR(    "uadd8      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uadd8      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe65cff9a      @ uadd8 pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe65cff9a) "       @ uadd8 pc, r12, r10")
-        TEST_UNSUPPORTED(".word 0xe65000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe65000b0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe65fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe65fffbf) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe65000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe65000d0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe65fffdf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe65fffdf) "") /* Unallocated space */
        TEST_RR(    "usub8      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "usub8      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe65cfffa      @ usub8 pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe65cfffa) "       @ usub8 pc, r12, r10")
        TEST_RR(    "uqadd16    r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uqadd16    r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe66cff1a      @ uqadd16       pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe66cff1a) "       @ uqadd16       pc, r12, r10")
        TEST_RR(    "uqasx      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uqasx      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe66cff3a      @ uqasx pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe66cff3a) "       @ uqasx pc, r12, r10")
        TEST_RR(    "uqsax      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uqsax      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe66cff5a      @ uqsax pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe66cff5a) "       @ uqsax pc, r12, r10")
        TEST_RR(    "uqsub16    r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uqsub16    r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe66cff7a      @ uqsub16       pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe66cff7a) "       @ uqsub16       pc, r12, r10")
        TEST_RR(    "uqadd8     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uqadd8     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe66cff9a      @ uqadd8        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe66cff9a) "       @ uqadd8        pc, r12, r10")
-        TEST_UNSUPPORTED(".word 0xe66000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe66000b0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe66fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe66fffbf) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe66000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe66000d0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe66fffdf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe66fffdf) "") /* Unallocated space */
        TEST_RR(    "uqsub8     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uqsub8     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe66cfffa      @ uqsub8        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe66cfffa) "       @ uqsub8        pc, r12, r10")
        TEST_RR(    "uhadd16    r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uhadd16    r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe67cff1a      @ uhadd16       pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe67cff1a) "       @ uhadd16       pc, r12, r10")
        TEST_RR(    "uhasx      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uhasx      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe67cff3a      @ uhasx pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe67cff3a) "       @ uhasx pc, r12, r10")
        TEST_RR(    "uhsax      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uhsax      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe67cff5a      @ uhsax pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe67cff5a) "       @ uhsax pc, r12, r10")
        TEST_RR(    "uhsub16    r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uhsub16    r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe67cff7a      @ uhsub16       pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe67cff7a) "       @ uhsub16       pc, r12, r10")
        TEST_RR(    "uhadd8     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uhadd8     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe67cff9a      @ uhadd8        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe67cff9a) "       @ uhadd8        pc, r12, r10")
-        TEST_UNSUPPORTED(".word 0xe67000b0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe67000b0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe67fffbf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe67fffbf) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe67000d0") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe67000d0) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe67fffdf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe67fffdf) "") /* Unallocated space */
        TEST_RR(    "uhsub8     r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uhsub8     r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe67cfffa      @ uhsub8        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe67cfffa) "       @ uhsub8        pc, r12, r10")
-        TEST_UNSUPPORTED(".word 0xe67feffa      @ uhsub8        r14, pc, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe67feffa) "       @ uhsub8        r14, pc, r10")
-        TEST_UNSUPPORTED(".word 0xe67cefff      @ uhsub8        r14, r12, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe67cefff) "       @ uhsub8        r14, r12, pc")
 #endif /* __LINUX_ARM_ARCH__ >= 7 */
 #if __LINUX_ARM_ARCH__ >= 6
@@ -853,99 +855,99 @@ void kprobe_arm_test_cases(void)
        TEST_RR(    "pkhbt      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "pkhbt      r14,r",12, HH1,", r",10,HH2,", lsl #2")
-        TEST_UNSUPPORTED(".word 0xe68cf11a      @ pkhbt pc, r12, r10, lsl #2")
+        TEST_UNSUPPORTED(__inst_arm(0xe68cf11a) "       @ pkhbt pc, r12, r10, lsl #2")
        TEST_RR(    "pkhtb      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "pkhtb      r14,r",12, HH1,", r",10,HH2,", asr #2")
-        TEST_UNSUPPORTED(".word 0xe68cf15a      @ pkhtb pc, r12, r10, asr #2")
+        TEST_UNSUPPORTED(__inst_arm(0xe68cf15a) "       @ pkhtb pc, r12, r10, asr #2")
-        TEST_UNSUPPORTED(".word 0xe68fe15a      @ pkhtb r14, pc, r10, asr #2")
+        TEST_UNSUPPORTED(__inst_arm(0xe68fe15a) "       @ pkhtb r14, pc, r10, asr #2")
-        TEST_UNSUPPORTED(".word 0xe68ce15f      @ pkhtb r14, r12, pc, asr #2")
+        TEST_UNSUPPORTED(__inst_arm(0xe68ce15f) "       @ pkhtb r14, r12, pc, asr #2")
-        TEST_UNSUPPORTED(".word 0xe6900010") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe6900010) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe69fffdf") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe69fffdf) "") /* Unallocated space */
        TEST_R(     "ssat       r0, #24, r",0,   VAL1,"")
        TEST_R(     "ssat       r14, #24, r",12, VAL2,"")
        TEST_R(     "ssat       r0, #24, r",0,   VAL1,", lsl #8")
        TEST_R(     "ssat       r14, #24, r",12, VAL2,", asr #8")
-        TEST_UNSUPPORTED(".word 0xe6b7f01c      @ ssat  pc, #24, r12")
+        TEST_UNSUPPORTED(__inst_arm(0xe6b7f01c) "       @ ssat  pc, #24, r12")
        TEST_R(     "usat       r0, #24, r",0,   VAL1,"")
        TEST_R(     "usat       r14, #24, r",12, VAL2,"")
        TEST_R(     "usat       r0, #24, r",0,   VAL1,", lsl #8")
        TEST_R(     "usat       r14, #24, r",12, VAL2,", asr #8")
-        TEST_UNSUPPORTED(".word 0xe6f7f01c      @ usat  pc, #24, r12")
+        TEST_UNSUPPORTED(__inst_arm(0xe6f7f01c) "       @ usat  pc, #24, r12")
        TEST_RR(    "sxtab16    r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "sxtab16    r14,r",12, HH2,", r",10,HH1,", ror #8")
        TEST_R(     "sxtb16     r8, r",7,  HH1,"")
-        TEST_UNSUPPORTED(".word 0xe68cf47a      @ sxtab16       pc,r12, r10, ror #8")
+        TEST_UNSUPPORTED(__inst_arm(0xe68cf47a) "       @ sxtab16       pc,r12, r10, ror #8")
        TEST_RR(    "sel        r0, r",0,  VAL1,", r",1, VAL2,"")
        TEST_RR(    "sel        r14, r",12,VAL1,", r",10, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe68cffba      @ sel   pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe68cffba) "       @ sel   pc, r12, r10")
-        TEST_UNSUPPORTED(".word 0xe68fefba      @ sel   r14, pc, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe68fefba) "       @ sel   r14, pc, r10")
-        TEST_UNSUPPORTED(".word 0xe68cefbf      @ sel   r14, r12, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe68cefbf) "       @ sel   r14, r12, pc")
        TEST_R(     "ssat16     r0, #12, r",0,   HH1,"")
        TEST_R(     "ssat16     r14, #12, r",12, HH2,"")
-        TEST_UNSUPPORTED(".word 0xe6abff3c      @ ssat16        pc, #12, r12")
+        TEST_UNSUPPORTED(__inst_arm(0xe6abff3c) "       @ ssat16        pc, #12, r12")
        TEST_RR(    "sxtab      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "sxtab      r14,r",12, HH2,", r",10,HH1,", ror #8")
        TEST_R(     "sxtb       r8, r",7,  HH1,"")
-        TEST_UNSUPPORTED(".word 0xe6acf47a      @ sxtab pc,r12, r10, ror #8")
+        TEST_UNSUPPORTED(__inst_arm(0xe6acf47a) "       @ sxtab pc,r12, r10, ror #8")
        TEST_R(     "rev        r0, r",0,   VAL1,"")
        TEST_R(     "rev        r14, r",12, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe6bfff3c      @ rev   pc, r12")
+        TEST_UNSUPPORTED(__inst_arm(0xe6bfff3c) "       @ rev   pc, r12")
        TEST_RR(    "sxtah      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "sxtah      r14,r",12, HH2,", r",10,HH1,", ror #8")
        TEST_R(     "sxth       r8, r",7,  HH1,"")
-        TEST_UNSUPPORTED(".word 0xe6bcf47a      @ sxtah pc,r12, r10, ror #8")
+        TEST_UNSUPPORTED(__inst_arm(0xe6bcf47a) "       @ sxtah pc,r12, r10, ror #8")
        TEST_R(     "rev16      r0, r",0,   VAL1,"")
        TEST_R(     "rev16      r14, r",12, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe6bfffbc      @ rev16 pc, r12")
+        TEST_UNSUPPORTED(__inst_arm(0xe6bfffbc) "       @ rev16 pc, r12")
        TEST_RR(    "uxtab16    r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uxtab16    r14,r",12, HH2,", r",10,HH1,", ror #8")
        TEST_R(     "uxtb16     r8, r",7,  HH1,"")
-        TEST_UNSUPPORTED(".word 0xe6ccf47a      @ uxtab16       pc,r12, r10, ror #8")
+        TEST_UNSUPPORTED(__inst_arm(0xe6ccf47a) "       @ uxtab16       pc,r12, r10, ror #8")
        TEST_R(     "usat16     r0, #12, r",0,   HH1,"")
        TEST_R(     "usat16     r14, #12, r",12, HH2,"")
-        TEST_UNSUPPORTED(".word 0xe6ecff3c      @ usat16        pc, #12, r12")
+        TEST_UNSUPPORTED(__inst_arm(0xe6ecff3c) "       @ usat16        pc, #12, r12")
-        TEST_UNSUPPORTED(".word 0xe6ecef3f      @ usat16        r14, #12, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe6ecef3f) "       @ usat16        r14, #12, pc")
        TEST_RR(    "uxtab      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uxtab      r14,r",12, HH2,", r",10,HH1,", ror #8")
        TEST_R(     "uxtb       r8, r",7,  HH1,"")
-        TEST_UNSUPPORTED(".word 0xe6ecf47a      @ uxtab pc,r12, r10, ror #8")
+        TEST_UNSUPPORTED(__inst_arm(0xe6ecf47a) "       @ uxtab pc,r12, r10, ror #8")
 #if __LINUX_ARM_ARCH__ >= 7
        TEST_R(     "rbit       r0, r",0,   VAL1,"")
        TEST_R(     "rbit       r14, r",12, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe6ffff3c      @ rbit  pc, r12")
+        TEST_UNSUPPORTED(__inst_arm(0xe6ffff3c) "       @ rbit  pc, r12")
 #endif
        TEST_RR(    "uxtah      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uxtah      r14,r",12, HH2,", r",10,HH1,", ror #8")
        TEST_R(     "uxth       r8, r",7,  HH1,"")
-        TEST_UNSUPPORTED(".word 0xe6fff077      @ uxth  pc, r7")
+        TEST_UNSUPPORTED(__inst_arm(0xe6fff077) "       @ uxth  pc, r7")
-        TEST_UNSUPPORTED(".word 0xe6ff807f      @ uxth  r8, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe6ff807f) "       @ uxth  r8, pc")
-        TEST_UNSUPPORTED(".word 0xe6fcf47a      @ uxtah pc, r12, r10, ror #8")
+        TEST_UNSUPPORTED(__inst_arm(0xe6fcf47a) "       @ uxtah pc, r12, r10, ror #8")
-        TEST_UNSUPPORTED(".word 0xe6fce47f      @ uxtah r14, r12, pc, ror #8")
+        TEST_UNSUPPORTED(__inst_arm(0xe6fce47f) "       @ uxtah r14, r12, pc, ror #8")
        TEST_R(     "revsh      r0, r",0,   VAL1,"")
        TEST_R(     "revsh      r14, r",12, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe6ffff3c      @ revsh pc, r12")
+        TEST_UNSUPPORTED(__inst_arm(0xe6ffff3c) "       @ revsh pc, r12")
-        TEST_UNSUPPORTED(".word 0xe6ffef3f      @ revsh r14, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe6ffef3f) "       @ revsh r14, pc")
-        TEST_UNSUPPORTED(".word 0xe6900070") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe6900070) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe69fff7f") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe69fff7f) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe6d00070") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe6d00070) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".word 0xe6dfff7f") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_arm(0xe6dfff7f) "") /* Unallocated space */
 #endif /* __LINUX_ARM_ARCH__ >= 6 */
 #if __LINUX_ARM_ARCH__ >= 6
@@ -953,79 +955,79 @@ void kprobe_arm_test_cases(void)
        TEST_RRR(   "smlad      r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
        TEST_RRR(   "smlad      r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe70f8a1c      @ smlad pc, r12, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe70f8a1c) "       @ smlad pc, r12, r10, r8")
        TEST_RRR(   "smladx     r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
        TEST_RRR(   "smladx     r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe70f8a3c      @ smladx        pc, r12, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe70f8a3c) "       @ smladx        pc, r12, r10, r8")
        TEST_RR(   "smuad       r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(   "smuad       r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe70ffa1c      @ smuad pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe70ffa1c) "       @ smuad pc, r12, r10")
        TEST_RR(   "smuadx      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(   "smuadx      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe70ffa3c      @ smuadx        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe70ffa3c) "       @ smuadx        pc, r12, r10")
        TEST_RRR(   "smlsd      r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
        TEST_RRR(   "smlsd      r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe70f8a5c      @ smlsd pc, r12, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe70f8a5c) "       @ smlsd pc, r12, r10, r8")
        TEST_RRR(   "smlsdx     r0, r",0,  HH1,", r",1, HH2,", r",2, VAL1,"")
        TEST_RRR(   "smlsdx     r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe70f8a7c      @ smlsdx        pc, r12, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe70f8a7c) "       @ smlsdx        pc, r12, r10, r8")
        TEST_RR(   "smusd       r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(   "smusd       r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe70ffa5c      @ smusd pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe70ffa5c) "       @ smusd pc, r12, r10")
        TEST_RR(   "smusdx      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(   "smusdx      r14, r",12,HH2,", r",10,HH1,"")
-        TEST_UNSUPPORTED(".word 0xe70ffa7c      @ smusdx        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe70ffa7c) "       @ smusdx        pc, r12, r10")
        TEST_RRRR( "smlald      r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
        TEST_RRRR( "smlald      r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
-        TEST_UNSUPPORTED(".word 0xe74af819      @ smlald        pc, r10, r9, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe74af819) "       @ smlald        pc, r10, r9, r8")
-        TEST_UNSUPPORTED(".word 0xe74fb819      @ smlald        r11, pc, r9, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe74fb819) "       @ smlald        r11, pc, r9, r8")
-        TEST_UNSUPPORTED(".word 0xe74ab81f      @ smlald        r11, r10, pc, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe74ab81f) "       @ smlald        r11, r10, pc, r8")
-        TEST_UNSUPPORTED(".word 0xe74abf19      @ smlald        r11, r10, r9, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe74abf19) "       @ smlald        r11, r10, r9, pc")
        TEST_RRRR( "smlaldx     r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
        TEST_RRRR( "smlaldx     r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
-        TEST_UNSUPPORTED(".word 0xe74af839      @ smlaldx       pc, r10, r9, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe74af839) "       @ smlaldx       pc, r10, r9, r8")
-        TEST_UNSUPPORTED(".word 0xe74fb839      @ smlaldx       r11, pc, r9, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe74fb839) "       @ smlaldx       r11, pc, r9, r8")
        TEST_RRR(  "smmla       r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
        TEST_RRR(  "smmla       r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe75f8a1c      @ smmla pc, r12, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe75f8a1c) "       @ smmla pc, r12, r10, r8")
        TEST_RRR(  "smmlar      r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
        TEST_RRR(  "smmlar      r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe75f8a3c      @ smmlar        pc, r12, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe75f8a3c) "       @ smmlar        pc, r12, r10, r8")
        TEST_RR(   "smmul       r0, r",0,  VAL1,", r",1, VAL2,"")
        TEST_RR(   "smmul       r14, r",12,VAL2,", r",10,VAL1,"")
-        TEST_UNSUPPORTED(".word 0xe75ffa1c      @ smmul pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe75ffa1c) "       @ smmul pc, r12, r10")
        TEST_RR(   "smmulr      r0, r",0,  VAL1,", r",1, VAL2,"")
        TEST_RR(   "smmulr      r14, r",12,VAL2,", r",10,VAL1,"")
-        TEST_UNSUPPORTED(".word 0xe75ffa3c      @ smmulr        pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe75ffa3c) "       @ smmulr        pc, r12, r10")
        TEST_RRR(  "smmls       r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
        TEST_RRR(  "smmls       r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe75f8adc      @ smmls pc, r12, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe75f8adc) "       @ smmls pc, r12, r10, r8")
        TEST_RRR(  "smmlsr      r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL1,"")
        TEST_RRR(  "smmlsr      r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
-        TEST_UNSUPPORTED(".word 0xe75f8afc      @ smmlsr        pc, r12, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe75f8afc) "       @ smmlsr        pc, r12, r10, r8")
-        TEST_UNSUPPORTED(".word 0xe75e8aff      @ smmlsr        r14, pc, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe75e8aff) "       @ smmlsr        r14, pc, r10, r8")
-        TEST_UNSUPPORTED(".word 0xe75e8ffc      @ smmlsr        r14, r12, pc, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe75e8ffc) "       @ smmlsr        r14, r12, pc, r8")
-        TEST_UNSUPPORTED(".word 0xe75efafc      @ smmlsr        r14, r12, r10, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe75efafc) "       @ smmlsr        r14, r12, r10, pc")
        TEST_RR(   "usad8       r0, r",0,  VAL1,", r",1, VAL2,"")
        TEST_RR(   "usad8       r14, r",12,VAL2,", r",10,VAL1,"")
-        TEST_UNSUPPORTED(".word 0xe75ffa1c      @ usad8 pc, r12, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe75ffa1c) "       @ usad8 pc, r12, r10")
-        TEST_UNSUPPORTED(".word 0xe75efa1f      @ usad8 r14, pc, r10")
+        TEST_UNSUPPORTED(__inst_arm(0xe75efa1f) "       @ usad8 r14, pc, r10")
-        TEST_UNSUPPORTED(".word 0xe75eff1c      @ usad8 r14, r12, pc")
+        TEST_UNSUPPORTED(__inst_arm(0xe75eff1c) "       @ usad8 r14, r12, pc")
        TEST_RRR(  "usada8      r0, r",0,  VAL1,", r",1, VAL2,", r",2, VAL3,"")
        TEST_RRR(  "usada8      r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL3,"")
-        TEST_UNSUPPORTED(".word 0xe78f8a1c      @ usada8        pc, r12, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe78f8a1c) "       @ usada8        pc, r12, r10, r8")
-        TEST_UNSUPPORTED(".word 0xe78e8a1f      @ usada8        r14, pc, r10, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe78e8a1f) "       @ usada8        r14, pc, r10, r8")
-        TEST_UNSUPPORTED(".word 0xe78e8f1c      @ usada8        r14, r12, pc, r8")
+        TEST_UNSUPPORTED(__inst_arm(0xe78e8f1c) "       @ usada8        r14, r12, pc, r8")
 #endif /* __LINUX_ARM_ARCH__ >= 6 */
 #if __LINUX_ARM_ARCH__ >= 7
@@ -1034,26 +1036,26 @@ void kprobe_arm_test_cases(void)
        TEST_R(     "sbfx       r0, r",0  , VAL1,", #0, #31")
        TEST_R(     "sbfxeq     r14, r",12, VAL2,", #8, #16")
        TEST_R(     "sbfx       r4, r",10,  VAL1,", #16, #15")
-        TEST_UNSUPPORTED(".word 0xe7aff45c      @ sbfx  pc, r12, #8, #16")
+        TEST_UNSUPPORTED(__inst_arm(0xe7aff45c) "       @ sbfx  pc, r12, #8, #16")
        TEST_R(     "ubfx       r0, r",0  , VAL1,", #0, #31")
        TEST_R(     "ubfxcs     r14, r",12, VAL2,", #8, #16")
        TEST_R(     "ubfx       r4, r",10,  VAL1,", #16, #15")
-        TEST_UNSUPPORTED(".word 0xe7eff45c      @ ubfx  pc, r12, #8, #16")
+        TEST_UNSUPPORTED(__inst_arm(0xe7eff45c) "       @ ubfx  pc, r12, #8, #16")
-        TEST_UNSUPPORTED(".word 0xe7efc45f      @ ubfx  r12, pc, #8, #16")
+        TEST_UNSUPPORTED(__inst_arm(0xe7efc45f) "       @ ubfx  r12, pc, #8, #16")
        TEST_R(     "bfc        r",0, VAL1,", #4, #20")
        TEST_R(     "bfcvs      r",14,VAL2,", #4, #20")
        TEST_R(     "bfc        r",7, VAL1,", #0, #31")
        TEST_R(     "bfc        r",8, VAL2,", #0, #31")
-        TEST_UNSUPPORTED(".word 0xe7def01f      @ bfc   pc, #0, #31");
+        TEST_UNSUPPORTED(__inst_arm(0xe7def01f) "       @ bfc   pc, #0, #31");
        TEST_RR(    "bfi        r",0, VAL1,", r",0  , VAL2,", #0, #31")
        TEST_RR(    "bfipl      r",12,VAL1,", r",14 , VAL2,", #4, #20")
-        TEST_UNSUPPORTED(".word 0xe7d7f21e      @ bfi   pc, r14, #4, #20")
+        TEST_UNSUPPORTED(__inst_arm(0xe7d7f21e) "       @ bfi   pc, r14, #4, #20")
-        TEST_UNSUPPORTED(".word 0x07f000f0")  /* Permanently UNDEFINED */
+        TEST_UNSUPPORTED(__inst_arm(0x07f000f0) "")  /* Permanently UNDEFINED */
-        TEST_UNSUPPORTED(".word 0x07ffffff")  /* Permanently UNDEFINED */
+        TEST_UNSUPPORTED(__inst_arm(0x07ffffff) "")  /* Permanently UNDEFINED */
 #endif /* __LINUX_ARM_ARCH__ >= 6 */
        TEST_GROUP("Branch, branch with link, and block data transfer")
@@ -1180,43 +1182,43 @@ void kprobe_arm_test_cases(void)
                                                                                \
        TEST_COPROCESSOR( "stc"two"     0, cr0, [r15, #4]")                     \
        TEST_COPROCESSOR( "stc"two"     0, cr0, [r15, #-4]")                    \
-        TEST_UNSUPPORTED(".word 0x"cc"daf0001   @ stc"two"      0, cr0, [r15, #4]!")    \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##daf0001) "  @ stc"two"      0, cr0, [r15, #4]!")    \
-        TEST_UNSUPPORTED(".word 0x"cc"d2f0001   @ stc"two"      0, cr0, [r15, #-4]!")   \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##d2f0001) "  @ stc"two"      0, cr0, [r15, #-4]!")   \
-        TEST_UNSUPPORTED(".word 0x"cc"caf0001   @ stc"two"      0, cr0, [r15], #4")     \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##caf0001) "  @ stc"two"      0, cr0, [r15], #4")     \
-        TEST_UNSUPPORTED(".word 0x"cc"c2f0001   @ stc"two"      0, cr0, [r15], #-4")    \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##c2f0001) "  @ stc"two"      0, cr0, [r15], #-4")    \
        TEST_COPROCESSOR( "stc"two"     0, cr0, [r15], {1}")                    \
        TEST_COPROCESSOR( "stc"two"l    0, cr0, [r15, #4]")                     \
        TEST_COPROCESSOR( "stc"two"l    0, cr0, [r15, #-4]")                    \
-        TEST_UNSUPPORTED(".word 0x"cc"def0001   @ stc"two"l     0, cr0, [r15, #4]!")    \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##def0001) "  @ stc"two"l     0, cr0, [r15, #4]!")    \
-        TEST_UNSUPPORTED(".word 0x"cc"d6f0001   @ stc"two"l     0, cr0, [r15, #-4]!")   \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##d6f0001) "  @ stc"two"l     0, cr0, [r15, #-4]!")   \
-        TEST_UNSUPPORTED(".word 0x"cc"cef0001   @ stc"two"l     0, cr0, [r15], #4")     \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##cef0001) "  @ stc"two"l     0, cr0, [r15], #4")     \
-        TEST_UNSUPPORTED(".word 0x"cc"c6f0001   @ stc"two"l     0, cr0, [r15], #-4")    \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##c6f0001) "  @ stc"two"l     0, cr0, [r15], #-4")    \
        TEST_COPROCESSOR( "stc"two"l    0, cr0, [r15], {1}")                    \
        TEST_COPROCESSOR( "ldc"two"     0, cr0, [r15, #4]")                     \
        TEST_COPROCESSOR( "ldc"two"     0, cr0, [r15, #-4]")                    \
-        TEST_UNSUPPORTED(".word 0x"cc"dbf0001   @ ldc"two"      0, cr0, [r15, #4]!")    \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##dbf0001) "  @ ldc"two"      0, cr0, [r15, #4]!")    \
-        TEST_UNSUPPORTED(".word 0x"cc"d3f0001   @ ldc"two"      0, cr0, [r15, #-4]!")   \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##d3f0001) "  @ ldc"two"      0, cr0, [r15, #-4]!")   \
-        TEST_UNSUPPORTED(".word 0x"cc"cbf0001   @ ldc"two"      0, cr0, [r15], #4")     \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##cbf0001) "  @ ldc"two"      0, cr0, [r15], #4")     \
-        TEST_UNSUPPORTED(".word 0x"cc"c3f0001   @ ldc"two"      0, cr0, [r15], #-4")    \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##c3f0001) "  @ ldc"two"      0, cr0, [r15], #-4")    \
        TEST_COPROCESSOR( "ldc"two"     0, cr0, [r15], {1}")                    \
        TEST_COPROCESSOR( "ldc"two"l    0, cr0, [r15, #4]")                     \
        TEST_COPROCESSOR( "ldc"two"l    0, cr0, [r15, #-4]")                    \
-        TEST_UNSUPPORTED(".word 0x"cc"dff0001   @ ldc"two"l     0, cr0, [r15, #4]!")    \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##dff0001) "  @ ldc"two"l     0, cr0, [r15, #4]!")    \
-        TEST_UNSUPPORTED(".word 0x"cc"d7f0001   @ ldc"two"l     0, cr0, [r15, #-4]!")   \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##d7f0001) "  @ ldc"two"l     0, cr0, [r15, #-4]!")   \
-        TEST_UNSUPPORTED(".word 0x"cc"cff0001   @ ldc"two"l     0, cr0, [r15], #4")     \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##cff0001) "  @ ldc"two"l     0, cr0, [r15], #4")     \
-        TEST_UNSUPPORTED(".word 0x"cc"c7f0001   @ ldc"two"l     0, cr0, [r15], #-4")    \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##c7f0001) "  @ ldc"two"l     0, cr0, [r15], #-4")    \
        TEST_COPROCESSOR( "ldc"two"l    0, cr0, [r15], {1}")
 #define COPROCESSOR_INSTRUCTIONS_MC_MR(two,cc)                                  \
                                                                                \
        TEST_COPROCESSOR( "mcrr"two"    0, 15, r0, r14, cr0")                   \
        TEST_COPROCESSOR( "mcrr"two"    15, 0, r14, r0, cr15")                  \
-        TEST_UNSUPPORTED(".word 0x"cc"c4f00f0   @ mcrr"two"     0, 15, r0, r15, cr0")   \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##c4f00f0) "  @ mcrr"two"     0, 15, r0, r15, cr0")   \
-        TEST_UNSUPPORTED(".word 0x"cc"c40ff0f   @ mcrr"two"     15, 0, r15, r0, cr15")  \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##c40ff0f) "  @ mcrr"two"     15, 0, r15, r0, cr15")  \
        TEST_COPROCESSOR( "mrrc"two"    0, 15, r0, r14, cr0")                   \
        TEST_COPROCESSOR( "mrrc"two"    15, 0, r14, r0, cr15")                  \
-        TEST_UNSUPPORTED(".word 0x"cc"c5f00f0   @ mrrc"two"     0, 15, r0, r15, cr0")   \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##c5f00f0) "  @ mrrc"two"     0, 15, r0, r15, cr0")   \
-        TEST_UNSUPPORTED(".word 0x"cc"c50ff0f   @ mrrc"two"     15, 0, r15, r0, cr15")  \
+        TEST_UNSUPPORTED(__inst_arm(0x##cc##c50ff0f) "  @ mrrc"two"     15, 0, r15, r0, cr15")  \
        TEST_COPROCESSOR( "cdp"two"     15, 15, cr15, cr15, cr15, 7")           \
        TEST_COPROCESSOR( "cdp"two"     0, 0, cr0, cr0, cr0, 0")                \
        TEST_COPROCESSOR( "mcr"two"     15, 7, r15, cr15, cr15, 7")             \
@@ -1224,8 +1226,8 @@ void kprobe_arm_test_cases(void)
        TEST_COPROCESSOR( "mrc"two"     15, 7, r15, cr15, cr15, 7")             \
        TEST_COPROCESSOR( "mrc"two"     0, 0, r0, cr0, cr0, 0")
-        COPROCESSOR_INSTRUCTIONS_ST_LD("","e")
+        COPROCESSOR_INSTRUCTIONS_ST_LD("",e)
-        COPROCESSOR_INSTRUCTIONS_MC_MR("","e")
+        COPROCESSOR_INSTRUCTIONS_MC_MR("",e)
        TEST_UNSUPPORTED("svc   0")
        TEST_UNSUPPORTED("svc   0xffffff")
@@ -1251,14 +1253,14 @@ void kprobe_arm_test_cases(void)
        TEST_UNSUPPORTED("rfedb sp!")
        TEST_UNSUPPORTED("rfeia sp!")
        TEST_UNSUPPORTED("rfeib sp!")
-        TEST_UNSUPPORTED(".word 0xf81d0a00      @ rfeda pc")
+        TEST_UNSUPPORTED(__inst_arm(0xf81d0a00) "       @ rfeda pc")
-        TEST_UNSUPPORTED(".word 0xf91d0a00      @ rfedb pc")
+        TEST_UNSUPPORTED(__inst_arm(0xf91d0a00) "       @ rfedb pc")
-        TEST_UNSUPPORTED(".word 0xf89d0a00      @ rfeia pc")
+        TEST_UNSUPPORTED(__inst_arm(0xf89d0a00) "       @ rfeia pc")
-        TEST_UNSUPPORTED(".word 0xf99d0a00      @ rfeib pc")
+        TEST_UNSUPPORTED(__inst_arm(0xf99d0a00) "       @ rfeib pc")
-        TEST_UNSUPPORTED(".word 0xf83d0a00      @ rfeda pc!")
+        TEST_UNSUPPORTED(__inst_arm(0xf83d0a00) "       @ rfeda pc!")
-        TEST_UNSUPPORTED(".word 0xf93d0a00      @ rfedb pc!")
+        TEST_UNSUPPORTED(__inst_arm(0xf93d0a00) "       @ rfedb pc!")
-        TEST_UNSUPPORTED(".word 0xf8bd0a00      @ rfeia pc!")
+        TEST_UNSUPPORTED(__inst_arm(0xf8bd0a00) "       @ rfeia pc!")
-        TEST_UNSUPPORTED(".word 0xf9bd0a00      @ rfeib pc!")
+        TEST_UNSUPPORTED(__inst_arm(0xf9bd0a00) "       @ rfeib pc!")
 #endif /* __LINUX_ARM_ARCH__ >= 6 */
 #if __LINUX_ARM_ARCH__ >= 6
@@ -1285,9 +1287,9 @@ void kprobe_arm_test_cases(void)
        TEST(   "blx    __dummy_thumb_subroutine_odd")
 #endif /* __LINUX_ARM_ARCH__ >= 6 */
-        COPROCESSOR_INSTRUCTIONS_ST_LD("2","f")
+        COPROCESSOR_INSTRUCTIONS_ST_LD("2",f)
 #if __LINUX_ARM_ARCH__ >= 6
-        COPROCESSOR_INSTRUCTIONS_MC_MR("2","f")
+        COPROCESSOR_INSTRUCTIONS_MC_MR("2",f)
 #endif
        TEST_GROUP("Miscellaneous instructions, memory hints, and Advanced SIMD instructions")
@@ -1317,9 +1319,9 @@ void kprobe_arm_test_cases(void)
 #endif
 #if __LINUX_ARM_ARCH__ >= 7
-        TEST_SUPPORTED(  ".word 0xf590f000      @ pldw [r0, #0]")
+        TEST_SUPPORTED(  __inst_arm(0xf590f000) "       @ pldw [r0, #0]")
-        TEST_SUPPORTED(  ".word 0xf797f000      @ pldw  [r7, r0]")
+        TEST_SUPPORTED(  __inst_arm(0xf797f000) "       @ pldw  [r7, r0]")
-        TEST_SUPPORTED(  ".word 0xf798f18c      @ pldw  [r8, r12, lsl #3]");
+        TEST_SUPPORTED(  __inst_arm(0xf798f18c) "       @ pldw  [r8, r12, lsl #3]");
 #endif
 #if __LINUX_ARM_ARCH__ >= 7
diff --git a/arch/arm/kernel/kprobes-test-thumb.c b/arch/arm/kernel/kprobes-test-thumb.c
index 5d8b85792222..844dd10d8593 100644
--- a/arch/arm/kernel/kprobes-test-thumb.c
+++ b/arch/arm/kernel/kprobes-test-thumb.c
@@ -10,6 +10,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <asm/opcodes.h>
 #include "kprobes-test.h"
@@ -119,7 +120,7 @@ void kprobe_thumb16_test_cases(void)
        TEST_R(   "add  sp"        ", r",8,-8,  "")
        TEST_R(   "add  r",14,VAL1,", pc")
        TEST_BF_R("add  pc"        ", r",0,2f-1f-8,"")
-        TEST_UNSUPPORTED(".short 0x44ff @ add pc, pc")
+        TEST_UNSUPPORTED(__inst_thumb16(0x44ff) "       @ add pc, pc")
        TEST_RR(  "cmp  r",3,VAL1,", r",8,VAL2,"")
        TEST_RR(  "cmp  r",8,VAL2,", r",0,VAL1,"")
@@ -150,7 +151,7 @@ void kprobe_thumb16_test_cases(void)
        TEST_BF_R("blx  r",0, 2f+1,"")
        TEST_BB_R("blx  r",14,2f+1,"")
-        TEST_UNSUPPORTED(".short 0x47f8 @ blx pc")
+        TEST_UNSUPPORTED(__inst_thumb16(0x47f8) "       @ blx pc")
        TEST_GROUP("Load from Literal Pool")
@@ -237,8 +238,8 @@ DONT_TEST_IN_ITBLOCK(
        TEST_R("rev     r7, r",0, VAL2,"")
        TEST_R("rev16   r0, r",7, VAL1,"")
        TEST_R("rev16   r7, r",0, VAL2,"")
-        TEST_UNSUPPORTED(".short 0xba80")
+        TEST_UNSUPPORTED(__inst_thumb16(0xba80) "")
-        TEST_UNSUPPORTED(".short 0xbabf")
+        TEST_UNSUPPORTED(__inst_thumb16(0xbabf) "")
        TEST_R("revsh   r0, r",7, VAL1,"")
        TEST_R("revsh   r7, r",0, VAL2,"")
@@ -272,8 +273,8 @@ DONT_TEST_IN_ITBLOCK(
        TEST("nop")
        TEST("wfi")
        TEST_SUPPORTED("wfe")
-        TEST_UNSUPPORTED(".short 0xbf50") /* Unassigned hints */
+        TEST_UNSUPPORTED(__inst_thumb16(0xbf50) "") /* Unassigned hints */
-        TEST_UNSUPPORTED(".short 0xbff0") /* Unassigned hints */
+        TEST_UNSUPPORTED(__inst_thumb16(0xbff0) "") /* Unassigned hints */
 #define TEST_IT(code, code2)                    \
        TESTCASE_START(code)                    \
@@ -310,8 +311,8 @@ CONDITION_INSTRUCTIONS(8,
        TEST_BF("bgt    2f")
        TEST_BB("blt    2b")
 )
-        TEST_UNSUPPORTED(".short 0xde00")
+        TEST_UNSUPPORTED(__inst_thumb16(0xde00) "")
-        TEST_UNSUPPORTED(".short 0xdeff")
+        TEST_UNSUPPORTED(__inst_thumb16(0xdeff) "")
        TEST_UNSUPPORTED("svc   #0x00")
        TEST_UNSUPPORTED("svc   #0xff")
@@ -380,13 +381,13 @@ void kprobe_thumb32_test_cases(void)
        TEST_THUMB_TO_ARM_INTERWORK_P("ldmia    r",0,14*4,", {r12,pc}")
        TEST_THUMB_TO_ARM_INTERWORK_P("ldmia    r",13,2*4,", {r0-r12,pc}")
-        TEST_UNSUPPORTED(".short 0xe88f,0x0101  @ stmia pc, {r0,r8}")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe88f0101) "   @ stmia pc, {r0,r8}")
-        TEST_UNSUPPORTED(".short 0xe92f,0x5f00  @ stmdb pc!, {r8-r12,r14}")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe92f5f00) "   @ stmdb pc!, {r8-r12,r14}")
-        TEST_UNSUPPORTED(".short 0xe8bd,0xc000  @ ldmia r13!, {r14,pc}")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe8bdc000) "   @ ldmia r13!, {r14,pc}")
-        TEST_UNSUPPORTED(".short 0xe93e,0xc000  @ ldmdb r14!, {r14,pc}")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe93ec000) "   @ ldmdb r14!, {r14,pc}")
-        TEST_UNSUPPORTED(".short 0xe8a7,0x3f00  @ stmia r7!, {r8-r12,sp}")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe8a73f00) "   @ stmia r7!, {r8-r12,sp}")
-        TEST_UNSUPPORTED(".short 0xe8a7,0x9f00  @ stmia r7!, {r8-r12,pc}")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe8a79f00) "   @ stmia r7!, {r8-r12,pc}")
-        TEST_UNSUPPORTED(".short 0xe93e,0x2010  @ ldmdb r14!, {r4,sp}")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe93e2010) "   @ ldmdb r14!, {r4,sp}")
        TEST_GROUP("Load/store double or exclusive, table branch")
@@ -402,12 +403,12 @@ void kprobe_thumb32_test_cases(void)
                "3:     .word   "__stringify(VAL1)"     \n\t"
                "       .word   "__stringify(VAL2))
-        TEST_UNSUPPORTED(".short 0xe9ff,0xec04  @ ldrd  r14, r12, [pc, #16]!")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe9ffec04) "   @ ldrd  r14, r12, [pc, #16]!")
-        TEST_UNSUPPORTED(".short 0xe8ff,0xec04  @ ldrd  r14, r12, [pc], #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe8ffec04) "   @ ldrd  r14, r12, [pc], #16")
-        TEST_UNSUPPORTED(".short 0xe9d4,0xd800  @ ldrd  sp, r8, [r4]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe9d4d800) "   @ ldrd  sp, r8, [r4]")
-        TEST_UNSUPPORTED(".short 0xe9d4,0xf800  @ ldrd  pc, r8, [r4]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe9d4f800) "   @ ldrd  pc, r8, [r4]")
-        TEST_UNSUPPORTED(".short 0xe9d4,0x7d00  @ ldrd  r7, sp, [r4]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe9d47d00) "   @ ldrd  r7, sp, [r4]")
-        TEST_UNSUPPORTED(".short 0xe9d4,0x7f00  @ ldrd  r7, pc, [r4]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe9d47f00) "   @ ldrd  r7, pc, [r4]")
        TEST_RRP("strd  r",0, VAL1,", r",1, VAL2,", [r",1, 24,", #-16]")
        TEST_RR( "strd  r",12,VAL2,", r",14,VAL1,", [sp, #16]")
@@ -415,8 +416,8 @@ void kprobe_thumb32_test_cases(void)
        TEST_RR( "strd  r",14,VAL2,", r",12,VAL1,", [sp, #16]!")
        TEST_RRP("strd  r",1, VAL1,", r",0, VAL2,", [r",7, 24,"], #16")
        TEST_RR( "strd  r",7, VAL2,", r",8, VAL1,", [sp], #-16")
-        TEST_UNSUPPORTED(".short 0xe9ef,0xec04  @ strd  r14, r12, [pc, #16]!")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe9efec04) "   @ strd  r14, r12, [pc, #16]!")
-        TEST_UNSUPPORTED(".short 0xe8ef,0xec04  @ strd  r14, r12, [pc], #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe8efec04) "   @ strd  r14, r12, [pc], #16")
        TEST_RX("tbb    [pc, r",0, (9f-(1f+4)),"]",
                "9:                     \n\t"
@@ -460,9 +461,9 @@ void kprobe_thumb32_test_cases(void)
                "3:     mvn     r0, r0  \n\t"
                "2:     nop             \n\t")
-        TEST_UNSUPPORTED(".short 0xe8d1,0xf01f  @ tbh [r1, pc]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe8d1f01f) "   @ tbh [r1, pc]")
-        TEST_UNSUPPORTED(".short 0xe8d1,0xf01d  @ tbh [r1, sp]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe8d1f01d) "   @ tbh [r1, sp]")
-        TEST_UNSUPPORTED(".short 0xe8dd,0xf012  @ tbh [sp, r2]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xe8ddf012) "   @ tbh [sp, r2]")
        TEST_UNSUPPORTED("strexb        r0, r1, [r2]")
        TEST_UNSUPPORTED("strexh        r0, r1, [r2]")
@@ -540,40 +541,40 @@ void kprobe_thumb32_test_cases(void)
        TEST_RR("pkhtb  r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR("pkhtb  r14,r",12, HH1,", r",10,HH2,", asr #2")
-        TEST_UNSUPPORTED(".short 0xea17,0x0f0d  @ tst.w r7, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea170f0d) "   @ tst.w r7, sp")
-        TEST_UNSUPPORTED(".short 0xea17,0x0f0f  @ tst.w r7, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea170f0f) "   @ tst.w r7, pc")
-        TEST_UNSUPPORTED(".short 0xea1d,0x0f07  @ tst.w sp, r7")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea1d0f07) "   @ tst.w sp, r7")
-        TEST_UNSUPPORTED(".short 0xea1f,0x0f07  @ tst.w pc, r7")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea1f0f07) "   @ tst.w pc, r7")
-        TEST_UNSUPPORTED(".short 0xf01d,0x1f08  @ tst sp, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf01d1f08) "   @ tst sp, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf01f,0x1f08  @ tst pc, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf01f1f08) "   @ tst pc, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xea97,0x0f0d  @ teq.w r7, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea970f0d) "   @ teq.w r7, sp")
-        TEST_UNSUPPORTED(".short 0xea97,0x0f0f  @ teq.w r7, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea970f0f) "   @ teq.w r7, pc")
-        TEST_UNSUPPORTED(".short 0xea9d,0x0f07  @ teq.w sp, r7")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea9d0f07) "   @ teq.w sp, r7")
-        TEST_UNSUPPORTED(".short 0xea9f,0x0f07  @ teq.w pc, r7")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea9f0f07) "   @ teq.w pc, r7")
-        TEST_UNSUPPORTED(".short 0xf09d,0x1f08  @ tst sp, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf09d1f08) "   @ tst sp, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf09f,0x1f08  @ tst pc, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf09f1f08) "   @ tst pc, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xeb17,0x0f0d  @ cmn.w r7, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb170f0d) "   @ cmn.w r7, sp")
-        TEST_UNSUPPORTED(".short 0xeb17,0x0f0f  @ cmn.w r7, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb170f0f) "   @ cmn.w r7, pc")
        TEST_P("cmn.w   sp, r",7,0,"")
-        TEST_UNSUPPORTED(".short 0xeb1f,0x0f07  @ cmn.w pc, r7")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb1f0f07) "   @ cmn.w pc, r7")
        TEST(  "cmn     sp, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf11f,0x1f08  @ cmn pc, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf11f1f08) "   @ cmn pc, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xebb7,0x0f0d  @ cmp.w r7, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xebb70f0d) "   @ cmp.w r7, sp")
-        TEST_UNSUPPORTED(".short 0xebb7,0x0f0f  @ cmp.w r7, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xebb70f0f) "   @ cmp.w r7, pc")
        TEST_P("cmp.w   sp, r",7,0,"")
-        TEST_UNSUPPORTED(".short 0xebbf,0x0f07  @ cmp.w pc, r7")
+        TEST_UNSUPPORTED(__inst_thumb32(0xebbf0f07) "   @ cmp.w pc, r7")
        TEST(  "cmp     sp, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf1bf,0x1f08  @ cmp pc, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf1bf1f08) "   @ cmp pc, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xea5f,0x070d  @ movs.w r7, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea5f070d) "   @ movs.w r7, sp")
-        TEST_UNSUPPORTED(".short 0xea5f,0x070f  @ movs.w r7, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea5f070f) "   @ movs.w r7, pc")
-        TEST_UNSUPPORTED(".short 0xea5f,0x0d07  @ movs.w sp, r7")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea5f0d07) "   @ movs.w sp, r7")
-        TEST_UNSUPPORTED(".short 0xea4f,0x0f07  @ mov.w  pc, r7")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea4f0f07) "   @ mov.w  pc, r7")
-        TEST_UNSUPPORTED(".short 0xf04f,0x1d08  @ mov sp, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf04f1d08) "   @ mov sp, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf04f,0x1f08  @ mov pc, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf04f1f08) "   @ mov pc, #0x00080008")
        TEST_R("add.w   r0, sp, r",1, 4,"")
        TEST_R("adds    r0, sp, r",1, 4,", asl #3")
@@ -581,15 +582,15 @@ void kprobe_thumb32_test_cases(void)
        TEST_R("add     r0, sp, r",1, 16,", ror #1")
        TEST_R("add.w   sp, sp, r",1, 4,"")
        TEST_R("add     sp, sp, r",1, 4,", asl #3")
-        TEST_UNSUPPORTED(".short 0xeb0d,0x1d01  @ add sp, sp, r1, asl #4")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb0d1d01) "   @ add sp, sp, r1, asl #4")
-        TEST_UNSUPPORTED(".short 0xeb0d,0x0d71  @ add sp, sp, r1, ror #1")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb0d0d71) "   @ add sp, sp, r1, ror #1")
        TEST(  "add.w   r0, sp, #24")
        TEST(  "add.w   sp, sp, #24")
-        TEST_UNSUPPORTED(".short 0xeb0d,0x0f01  @ add pc, sp, r1")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb0d0f01) "   @ add pc, sp, r1")
-        TEST_UNSUPPORTED(".short 0xeb0d,0x000f  @ add r0, sp, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb0d000f) "   @ add r0, sp, pc")
-        TEST_UNSUPPORTED(".short 0xeb0d,0x000d  @ add r0, sp, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb0d000d) "   @ add r0, sp, sp")
-        TEST_UNSUPPORTED(".short 0xeb0d,0x0d0f  @ add sp, sp, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb0d0d0f) "   @ add sp, sp, pc")
-        TEST_UNSUPPORTED(".short 0xeb0d,0x0d0d  @ add sp, sp, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb0d0d0d) "   @ add sp, sp, sp")
        TEST_R("sub.w   r0, sp, r",1, 4,"")
        TEST_R("subs    r0, sp, r",1, 4,", asl #3")
@@ -597,54 +598,54 @@ void kprobe_thumb32_test_cases(void)
        TEST_R("sub     r0, sp, r",1, 16,", ror #1")
        TEST_R("sub.w   sp, sp, r",1, 4,"")
        TEST_R("sub     sp, sp, r",1, 4,", asl #3")
-        TEST_UNSUPPORTED(".short 0xebad,0x1d01  @ sub sp, sp, r1, asl #4")
+        TEST_UNSUPPORTED(__inst_thumb32(0xebad1d01) "   @ sub sp, sp, r1, asl #4")
-        TEST_UNSUPPORTED(".short 0xebad,0x0d71  @ sub sp, sp, r1, ror #1")
+        TEST_UNSUPPORTED(__inst_thumb32(0xebad0d71) "   @ sub sp, sp, r1, ror #1")
-        TEST_UNSUPPORTED(".short 0xebad,0x0f01  @ sub pc, sp, r1")
+        TEST_UNSUPPORTED(__inst_thumb32(0xebad0f01) "   @ sub pc, sp, r1")
        TEST(  "sub.w   r0, sp, #24")
        TEST(  "sub.w   sp, sp, #24")
-        TEST_UNSUPPORTED(".short 0xea02,0x010f  @ and r1, r2, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea02010f) "   @ and r1, r2, pc")
-        TEST_UNSUPPORTED(".short 0xea0f,0x0103  @ and r1, pc, r3")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea0f0103) "   @ and r1, pc, r3")
-        TEST_UNSUPPORTED(".short 0xea02,0x0f03  @ and pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea020f03) "   @ and pc, r2, r3")
-        TEST_UNSUPPORTED(".short 0xea02,0x010d  @ and r1, r2, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea02010d) "   @ and r1, r2, sp")
-        TEST_UNSUPPORTED(".short 0xea0d,0x0103  @ and r1, sp, r3")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea0d0103) "   @ and r1, sp, r3")
-        TEST_UNSUPPORTED(".short 0xea02,0x0d03  @ and sp, r2, r3")
+        TEST_UNSUPPORTED(__inst_thumb32(0xea020d03) "   @ and sp, r2, r3")
-        TEST_UNSUPPORTED(".short 0xf00d,0x1108  @ and r1, sp, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf00d1108) "   @ and r1, sp, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf00f,0x1108  @ and r1, pc, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf00f1108) "   @ and r1, pc, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf002,0x1d08  @ and sp, r8, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf0021d08) "   @ and sp, r8, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf002,0x1f08  @ and pc, r8, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf0021f08) "   @ and pc, r8, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xeb02,0x010f  @ add r1, r2, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb02010f) "   @ add r1, r2, pc")
-        TEST_UNSUPPORTED(".short 0xeb0f,0x0103  @ add r1, pc, r3")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb0f0103) "   @ add r1, pc, r3")
-        TEST_UNSUPPORTED(".short 0xeb02,0x0f03  @ add pc, r2, r3")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb020f03) "   @ add pc, r2, r3")
-        TEST_UNSUPPORTED(".short 0xeb02,0x010d  @ add r1, r2, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb02010d) "   @ add r1, r2, sp")
-        TEST_SUPPORTED(  ".short 0xeb0d,0x0103  @ add r1, sp, r3")
+        TEST_SUPPORTED(  __inst_thumb32(0xeb0d0103) "   @ add r1, sp, r3")
-        TEST_UNSUPPORTED(".short 0xeb02,0x0d03  @ add sp, r2, r3")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb020d03) "   @ add sp, r2, r3")
-        TEST_SUPPORTED(  ".short 0xf10d,0x1108  @ add r1, sp, #0x00080008")
+        TEST_SUPPORTED(  __inst_thumb32(0xf10d1108) "   @ add r1, sp, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf10d,0x1f08  @ add pc, sp, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf10d1f08) "   @ add pc, sp, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf10f,0x1108  @ add r1, pc, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf10f1108) "   @ add r1, pc, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf102,0x1d08  @ add sp, r8, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf1021d08) "   @ add sp, r8, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xf102,0x1f08  @ add pc, r8, #0x00080008")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf1021f08) "   @ add pc, r8, #0x00080008")
-        TEST_UNSUPPORTED(".short 0xeaa0,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeaa00000) "")
-        TEST_UNSUPPORTED(".short 0xeaf0,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeaf00000) "")
-        TEST_UNSUPPORTED(".short 0xeb20,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb200000) "")
-        TEST_UNSUPPORTED(".short 0xeb80,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeb800000) "")
-        TEST_UNSUPPORTED(".short 0xebe0,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xebe00000) "")
-        TEST_UNSUPPORTED(".short 0xf0a0,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf0a00000) "")
-        TEST_UNSUPPORTED(".short 0xf0c0,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf0c00000) "")
-        TEST_UNSUPPORTED(".short 0xf0f0,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf0f00000) "")
-        TEST_UNSUPPORTED(".short 0xf120,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf1200000) "")
-        TEST_UNSUPPORTED(".short 0xf180,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf1800000) "")
-        TEST_UNSUPPORTED(".short 0xf1e0,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf1e00000) "")
        TEST_GROUP("Coprocessor instructions")
-        TEST_UNSUPPORTED(".short 0xec00,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xec000000) "")
-        TEST_UNSUPPORTED(".short 0xeff0,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xeff00000) "")
-        TEST_UNSUPPORTED(".short 0xfc00,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfc000000) "")
-        TEST_UNSUPPORTED(".short 0xfff0,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfff00000) "")
        TEST_GROUP("Data-processing (plain binary immediate)")
@@ -652,92 +653,92 @@ void kprobe_thumb32_test_cases(void)
        TEST(  "addw    r14, sp, #0xf5a")
        TEST(  "addw    sp, sp, #0x20")
        TEST(  "addw    r7,  pc, #0x888")
-        TEST_UNSUPPORTED(".short 0xf20f,0x1f20  @ addw pc, pc, #0x120")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf20f1f20) "   @ addw pc, pc, #0x120")
-        TEST_UNSUPPORTED(".short 0xf20d,0x1f20  @ addw pc, sp, #0x120")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf20d1f20) "   @ addw pc, sp, #0x120")
-        TEST_UNSUPPORTED(".short 0xf20f,0x1d20  @ addw sp, pc, #0x120")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf20f1d20) "   @ addw sp, pc, #0x120")
-        TEST_UNSUPPORTED(".short 0xf200,0x1d20  @ addw sp, r0, #0x120")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf2001d20) "   @ addw sp, r0, #0x120")
        TEST_R("subw    r0,  r",1, VAL1,", #0x123")
        TEST(  "subw    r14, sp, #0xf5a")
        TEST(  "subw    sp, sp, #0x20")
        TEST(  "subw    r7,  pc, #0x888")
-        TEST_UNSUPPORTED(".short 0xf2af,0x1f20  @ subw pc, pc, #0x120")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf2af1f20) "   @ subw pc, pc, #0x120")
-        TEST_UNSUPPORTED(".short 0xf2ad,0x1f20  @ subw pc, sp, #0x120")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf2ad1f20) "   @ subw pc, sp, #0x120")
-        TEST_UNSUPPORTED(".short 0xf2af,0x1d20  @ subw sp, pc, #0x120")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf2af1d20) "   @ subw sp, pc, #0x120")
-        TEST_UNSUPPORTED(".short 0xf2a0,0x1d20  @ subw sp, r0, #0x120")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf2a01d20) "   @ subw sp, r0, #0x120")
        TEST("movw      r0, #0")
        TEST("movw      r0, #0xffff")
        TEST("movw      lr, #0xffff")
-        TEST_UNSUPPORTED(".short 0xf240,0x0d00  @ movw sp, #0")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf2400d00) "   @ movw sp, #0")
-        TEST_UNSUPPORTED(".short 0xf240,0x0f00  @ movw pc, #0")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf2400f00) "   @ movw pc, #0")
        TEST_R("movt    r",0, VAL1,", #0")
        TEST_R("movt    r",0, VAL2,", #0xffff")
        TEST_R("movt    r",14,VAL1,", #0xffff")
-        TEST_UNSUPPORTED(".short 0xf2c0,0x0d00  @ movt sp, #0")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf2c00d00) "   @ movt sp, #0")
-        TEST_UNSUPPORTED(".short 0xf2c0,0x0f00  @ movt pc, #0")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf2c00f00) "   @ movt pc, #0")
        TEST_R(     "ssat       r0, #24, r",0,   VAL1,"")
        TEST_R(     "ssat       r14, #24, r",12, VAL2,"")
        TEST_R(     "ssat       r0, #24, r",0,   VAL1,", lsl #8")
        TEST_R(     "ssat       r14, #24, r",12, VAL2,", asr #8")
-        TEST_UNSUPPORTED(".short 0xf30c,0x0d17  @ ssat  sp, #24, r12")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf30c0d17) "   @ ssat  sp, #24, r12")
-        TEST_UNSUPPORTED(".short 0xf30c,0x0f17  @ ssat  pc, #24, r12")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf30c0f17) "   @ ssat  pc, #24, r12")
-        TEST_UNSUPPORTED(".short 0xf30d,0x0c17  @ ssat  r12, #24, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf30d0c17) "   @ ssat  r12, #24, sp")
-        TEST_UNSUPPORTED(".short 0xf30f,0x0c17  @ ssat  r12, #24, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf30f0c17) "   @ ssat  r12, #24, pc")
        TEST_R(     "usat       r0, #24, r",0,   VAL1,"")
        TEST_R(     "usat       r14, #24, r",12, VAL2,"")
        TEST_R(     "usat       r0, #24, r",0,   VAL1,", lsl #8")
        TEST_R(     "usat       r14, #24, r",12, VAL2,", asr #8")
-        TEST_UNSUPPORTED(".short 0xf38c,0x0d17  @ usat  sp, #24, r12")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf38c0d17) "   @ usat  sp, #24, r12")
-        TEST_UNSUPPORTED(".short 0xf38c,0x0f17  @ usat  pc, #24, r12")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf38c0f17) "   @ usat  pc, #24, r12")
-        TEST_UNSUPPORTED(".short 0xf38d,0x0c17  @ usat  r12, #24, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf38d0c17) "   @ usat  r12, #24, sp")
-        TEST_UNSUPPORTED(".short 0xf38f,0x0c17  @ usat  r12, #24, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf38f0c17) "   @ usat  r12, #24, pc")
        TEST_R(     "ssat16     r0, #12, r",0,   HH1,"")
        TEST_R(     "ssat16     r14, #12, r",12, HH2,"")
-        TEST_UNSUPPORTED(".short 0xf32c,0x0d0b  @ ssat16        sp, #12, r12")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf32c0d0b) "   @ ssat16        sp, #12, r12")
-        TEST_UNSUPPORTED(".short 0xf32c,0x0f0b  @ ssat16        pc, #12, r12")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf32c0f0b) "   @ ssat16        pc, #12, r12")
-        TEST_UNSUPPORTED(".short 0xf32d,0x0c0b  @ ssat16        r12, #12, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf32d0c0b) "   @ ssat16        r12, #12, sp")
-        TEST_UNSUPPORTED(".short 0xf32f,0x0c0b  @ ssat16        r12, #12, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf32f0c0b) "   @ ssat16        r12, #12, pc")
        TEST_R(     "usat16     r0, #12, r",0,   HH1,"")
        TEST_R(     "usat16     r14, #12, r",12, HH2,"")
-        TEST_UNSUPPORTED(".short 0xf3ac,0x0d0b  @ usat16        sp, #12, r12")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3ac0d0b) "   @ usat16        sp, #12, r12")
-        TEST_UNSUPPORTED(".short 0xf3ac,0x0f0b  @ usat16        pc, #12, r12")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3ac0f0b) "   @ usat16        pc, #12, r12")
-        TEST_UNSUPPORTED(".short 0xf3ad,0x0c0b  @ usat16        r12, #12, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3ad0c0b) "   @ usat16        r12, #12, sp")
-        TEST_UNSUPPORTED(".short 0xf3af,0x0c0b  @ usat16        r12, #12, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3af0c0b) "   @ usat16        r12, #12, pc")
        TEST_R(     "sbfx       r0, r",0  , VAL1,", #0, #31")
        TEST_R(     "sbfx       r14, r",12, VAL2,", #8, #16")
        TEST_R(     "sbfx       r4, r",10,  VAL1,", #16, #15")
-        TEST_UNSUPPORTED(".short 0xf34c,0x2d0f  @ sbfx  sp, r12, #8, #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf34c2d0f) "   @ sbfx  sp, r12, #8, #16")
-        TEST_UNSUPPORTED(".short 0xf34c,0x2f0f  @ sbfx  pc, r12, #8, #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf34c2f0f) "   @ sbfx  pc, r12, #8, #16")
-        TEST_UNSUPPORTED(".short 0xf34d,0x2c0f  @ sbfx  r12, sp, #8, #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf34d2c0f) "   @ sbfx  r12, sp, #8, #16")
-        TEST_UNSUPPORTED(".short 0xf34f,0x2c0f  @ sbfx  r12, pc, #8, #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf34f2c0f) "   @ sbfx  r12, pc, #8, #16")
        TEST_R(     "ubfx       r0, r",0  , VAL1,", #0, #31")
        TEST_R(     "ubfx       r14, r",12, VAL2,", #8, #16")
        TEST_R(     "ubfx       r4, r",10,  VAL1,", #16, #15")
-        TEST_UNSUPPORTED(".short 0xf3cc,0x2d0f  @ ubfx  sp, r12, #8, #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3cc2d0f) "   @ ubfx  sp, r12, #8, #16")
-        TEST_UNSUPPORTED(".short 0xf3cc,0x2f0f  @ ubfx  pc, r12, #8, #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3cc2f0f) "   @ ubfx  pc, r12, #8, #16")
-        TEST_UNSUPPORTED(".short 0xf3cd,0x2c0f  @ ubfx  r12, sp, #8, #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3cd2c0f) "   @ ubfx  r12, sp, #8, #16")
-        TEST_UNSUPPORTED(".short 0xf3cf,0x2c0f  @ ubfx  r12, pc, #8, #16")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3cf2c0f) "   @ ubfx  r12, pc, #8, #16")
        TEST_R(     "bfc        r",0, VAL1,", #4, #20")
        TEST_R(     "bfc        r",14,VAL2,", #4, #20")
        TEST_R(     "bfc        r",7, VAL1,", #0, #31")
        TEST_R(     "bfc        r",8, VAL2,", #0, #31")
-        TEST_UNSUPPORTED(".short 0xf36f,0x0d1e  @ bfc   sp, #0, #31")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf36f0d1e) "   @ bfc   sp, #0, #31")
-        TEST_UNSUPPORTED(".short 0xf36f,0x0f1e  @ bfc   pc, #0, #31")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf36f0f1e) "   @ bfc   pc, #0, #31")
        TEST_RR(    "bfi        r",0, VAL1,", r",0  , VAL2,", #0, #31")
        TEST_RR(    "bfi        r",12,VAL1,", r",14 , VAL2,", #4, #20")
-        TEST_UNSUPPORTED(".short 0xf36e,0x1d17  @ bfi   sp, r14, #4, #20")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf36e1d17) "   @ bfi   sp, r14, #4, #20")
-        TEST_UNSUPPORTED(".short 0xf36e,0x1f17  @ bfi   pc, r14, #4, #20")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf36e1f17) "   @ bfi   pc, r14, #4, #20")
-        TEST_UNSUPPORTED(".short 0xf36d,0x1e17  @ bfi   r14, sp, #4, #20")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf36d1e17) "   @ bfi   r14, sp, #4, #20")
        TEST_GROUP("Branches and miscellaneous control")
@@ -775,14 +776,14 @@ CONDITION_INSTRUCTIONS(22,
        TEST("mrs       r0, cpsr")
        TEST("mrs       r14, cpsr")
-        TEST_UNSUPPORTED(".short 0xf3ef,0x8d00  @ mrs   sp, spsr")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3ef8d00) "   @ mrs   sp, spsr")
-        TEST_UNSUPPORTED(".short 0xf3ef,0x8f00  @ mrs   pc, spsr")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf3ef8f00) "   @ mrs   pc, spsr")
        TEST_UNSUPPORTED("mrs   r0, spsr")
        TEST_UNSUPPORTED("mrs   lr, spsr")
-        TEST_UNSUPPORTED(".short 0xf7f0,0x8000 @ smc #0")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf7f08000) " @ smc #0")
-        TEST_UNSUPPORTED(".short 0xf7f0,0xa000 @ undefeined")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf7f0a000) " @ undefeined")
        TEST_BF(  "b.w  2f")
        TEST_BB(  "b.w  2b")
@@ -829,15 +830,15 @@ CONDITION_INSTRUCTIONS(22,
        SINGLE_STORE("")
        TEST("str       sp, [sp]")
-        TEST_UNSUPPORTED(".short 0xf8cf,0xe000  @ str   r14, [pc]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf8cfe000) "   @ str   r14, [pc]")
-        TEST_UNSUPPORTED(".short 0xf8ce,0xf000  @ str   pc, [r14]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf8cef000) "   @ str   pc, [r14]")
        TEST_GROUP("Advanced SIMD element or structure load/store instructions")
-        TEST_UNSUPPORTED(".short 0xf900,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf9000000) "")
-        TEST_UNSUPPORTED(".short 0xf92f,0xffff")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf92fffff) "")
-        TEST_UNSUPPORTED(".short 0xf980,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf9800000) "")
-        TEST_UNSUPPORTED(".short 0xf9ef,0xffff")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf9efffff) "")
        TEST_GROUP("Load single data item and memory hints")
@@ -881,20 +882,20 @@ CONDITION_INSTRUCTIONS(22,
        TEST_SUPPORTED("ldr     sp, 99f")
        TEST_SUPPORTED("ldr     pc, 99f")
-        TEST_UNSUPPORTED(".short 0xf854,0x700d  @ ldr   r7, [r4, sp]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf854700d) "   @ ldr   r7, [r4, sp]")
-        TEST_UNSUPPORTED(".short 0xf854,0x700f  @ ldr   r7, [r4, pc]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf854700f) "   @ ldr   r7, [r4, pc]")
-        TEST_UNSUPPORTED(".short 0xf814,0x700d  @ ldrb  r7, [r4, sp]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf814700d) "   @ ldrb  r7, [r4, sp]")
-        TEST_UNSUPPORTED(".short 0xf814,0x700f  @ ldrb  r7, [r4, pc]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf814700f) "   @ ldrb  r7, [r4, pc]")
-        TEST_UNSUPPORTED(".short 0xf89f,0xd004  @ ldrb  sp, 99f")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf89fd004) "   @ ldrb  sp, 99f")
-        TEST_UNSUPPORTED(".short 0xf814,0xd008  @ ldrb  sp, [r4, r8]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf814d008) "   @ ldrb  sp, [r4, r8]")
-        TEST_UNSUPPORTED(".short 0xf894,0xd000  @ ldrb  sp, [r4]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf894d000) "   @ ldrb  sp, [r4]")
-        TEST_UNSUPPORTED(".short 0xf860,0x0000") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xf8600000) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xf9ff,0xffff") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xf9ffffff) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xf950,0x0000") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xf9500000) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xf95f,0xffff") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xf95fffff) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xf800,0x0800") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xf8000800) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xf97f,0xfaff") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xf97ffaff) "") /* Unallocated space */
        TEST(   "pli    [pc, #4]")
        TEST(   "pli    [pc, #-4]")
@@ -902,22 +903,22 @@ CONDITION_INSTRUCTIONS(22,
        TEST(   "pld    [pc, #-4]")
        TEST_P( "pld    [r",0,-1024,", #1024]")
-        TEST(   ".short 0xf8b0,0xf400   @ pldw  [r0, #1024]")
+        TEST(   __inst_thumb32(0xf8b0f400) "    @ pldw  [r0, #1024]")
        TEST_P( "pli    [r",4, 0b,", #1024]")
        TEST_P( "pld    [r",7, 120,", #-120]")
-        TEST(   ".short 0xf837,0xfc78   @ pldw  [r7, #-120]")
+        TEST(   __inst_thumb32(0xf837fc78) "    @ pldw  [r7, #-120]")
        TEST_P( "pli    [r",11,120,", #-120]")
        TEST(   "pld    [sp, #0]")
        TEST_PR("pld    [r",7, 24, ", r",0, 16,"]")
        TEST_PR("pld    [r",8, 24, ", r",12,16,", lsl #3]")
-        TEST_SUPPORTED(".short 0xf837,0xf000    @ pldw  [r7, r0]")
+        TEST_SUPPORTED(__inst_thumb32(0xf837f000) "     @ pldw  [r7, r0]")
-        TEST_SUPPORTED(".short 0xf838,0xf03c    @ pldw  [r8, r12, lsl #3]");
+        TEST_SUPPORTED(__inst_thumb32(0xf838f03c) "     @ pldw  [r8, r12, lsl #3]");
        TEST_RR("pli    [r",12,0b,", r",0, 16,"]")
        TEST_RR("pli    [r",0, 0b,", r",12,16,", lsl #3]")
        TEST_R( "pld    [sp, r",1, 16,"]")
-        TEST_UNSUPPORTED(".short 0xf817,0xf00d  @pld    [r7, sp]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf817f00d) "  @pld     [r7, sp]")
-        TEST_UNSUPPORTED(".short 0xf817,0xf00f  @pld    [r7, pc]")
+        TEST_UNSUPPORTED(__inst_thumb32(0xf817f00f) "  @pld     [r7, pc]")
        TEST_GROUP("Data-processing (register)")
@@ -934,21 +935,21 @@ CONDITION_INSTRUCTIONS(22,
        SHIFTS32("ror")
        SHIFTS32("rors")
-        TEST_UNSUPPORTED(".short 0xfa01,0xff02  @ lsl   pc, r1, r2")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa01ff02) "   @ lsl   pc, r1, r2")
-        TEST_UNSUPPORTED(".short 0xfa01,0xfd02  @ lsl   sp, r1, r2")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa01fd02) "   @ lsl   sp, r1, r2")
-        TEST_UNSUPPORTED(".short 0xfa0f,0xf002  @ lsl   r0, pc, r2")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa0ff002) "   @ lsl   r0, pc, r2")
-        TEST_UNSUPPORTED(".short 0xfa0d,0xf002  @ lsl   r0, sp, r2")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa0df002) "   @ lsl   r0, sp, r2")
-        TEST_UNSUPPORTED(".short 0xfa01,0xf00f  @ lsl   r0, r1, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa01f00f) "   @ lsl   r0, r1, pc")
-        TEST_UNSUPPORTED(".short 0xfa01,0xf00d  @ lsl   r0, r1, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa01f00d) "   @ lsl   r0, r1, sp")
        TEST_RR(    "sxtah      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "sxtah      r14,r",12, HH2,", r",10,HH1,", ror #8")
        TEST_R(     "sxth       r8, r",7,  HH1,"")
-        TEST_UNSUPPORTED(".short 0xfa0f,0xff87  @ sxth  pc, r7");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa0fff87) "   @ sxth  pc, r7");
-        TEST_UNSUPPORTED(".short 0xfa0f,0xfd87  @ sxth  sp, r7");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa0ffd87) "   @ sxth  sp, r7");
-        TEST_UNSUPPORTED(".short 0xfa0f,0xf88f  @ sxth  r8, pc");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa0ff88f) "   @ sxth  r8, pc");
-        TEST_UNSUPPORTED(".short 0xfa0f,0xf88d  @ sxth  r8, sp");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa0ff88d) "   @ sxth  r8, sp");
        TEST_RR(    "uxtah      r0, r",0,  HH1,", r",1, HH2,"")
        TEST_RR(    "uxtah      r14,r",12, HH2,", r",10,HH1,", ror #8")
@@ -970,8 +971,8 @@ CONDITION_INSTRUCTIONS(22,
        TEST_RR(    "uxtab      r14,r",12, HH2,", r",10,HH1,", ror #8")
        TEST_R(     "uxtb       r8, r",7,  HH1,"")
-        TEST_UNSUPPORTED(".short 0xfa60,0x00f0")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa6000f0) "")
-        TEST_UNSUPPORTED(".short 0xfa7f,0xffff")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa7fffff) "")
 #define PARALLEL_ADD_SUB(op)                                    \
        TEST_RR(  op"add16      r0, r",0,  HH1,", r",1, HH2,"") \
@@ -1019,10 +1020,10 @@ CONDITION_INSTRUCTIONS(22,
        TEST_R("revsh.w r0, r",0,   VAL1,"")
        TEST_R("revsh   r14, r",12, VAL2,"")
-        TEST_UNSUPPORTED(".short 0xfa9c,0xff8c  @ rev   pc, r12");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa9cff8c) "   @ rev   pc, r12");
-        TEST_UNSUPPORTED(".short 0xfa9c,0xfd8c  @ rev   sp, r12");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa9cfd8c) "   @ rev   sp, r12");
-        TEST_UNSUPPORTED(".short 0xfa9f,0xfe8f  @ rev   r14, pc");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa9ffe8f) "   @ rev   r14, pc");
-        TEST_UNSUPPORTED(".short 0xfa9d,0xfe8d  @ rev   r14, sp");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa9dfe8d) "   @ rev   r14, sp");
        TEST_RR("sel    r0, r",0,  VAL1,", r",1, VAL2,"")
        TEST_RR("sel    r14, r",12,VAL1,", r",10, VAL2,"")
@@ -1031,31 +1032,31 @@ CONDITION_INSTRUCTIONS(22,
        TEST_R("clz     r7, r",14,0x1,"")
        TEST_R("clz     lr, r",7, 0xffffffff,"")
-        TEST_UNSUPPORTED(".short 0xfa80,0xf030") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfa80f030) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xfaff,0xff7f") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfaffff7f) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xfab0,0xf000") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfab0f000) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xfaff,0xff7f") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfaffff7f) "") /* Unallocated space */
        TEST_GROUP("Multiply, multiply accumulate, and absolute difference operations")
        TEST_RR(    "mul        r0, r",1, VAL1,", r",2, VAL2,"")
        TEST_RR(    "mul        r7, r",8, VAL2,", r",9, VAL2,"")
-        TEST_UNSUPPORTED(".short 0xfb08,0xff09  @ mul   pc, r8, r9")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb08ff09) "   @ mul   pc, r8, r9")
-        TEST_UNSUPPORTED(".short 0xfb08,0xfd09  @ mul   sp, r8, r9")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb08fd09) "   @ mul   sp, r8, r9")
-        TEST_UNSUPPORTED(".short 0xfb0f,0xf709  @ mul   r7, pc, r9")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb0ff709) "   @ mul   r7, pc, r9")
-        TEST_UNSUPPORTED(".short 0xfb0d,0xf709  @ mul   r7, sp, r9")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb0df709) "   @ mul   r7, sp, r9")
-        TEST_UNSUPPORTED(".short 0xfb08,0xf70f  @ mul   r7, r8, pc")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb08f70f) "   @ mul   r7, r8, pc")
-        TEST_UNSUPPORTED(".short 0xfb08,0xf70d  @ mul   r7, r8, sp")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb08f70d) "   @ mul   r7, r8, sp")
        TEST_RRR(   "mla        r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(   "mla        r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
-        TEST_UNSUPPORTED(".short 0xfb08,0xaf09  @ mla   pc, r8, r9, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb08af09) "   @ mla   pc, r8, r9, r10");
-        TEST_UNSUPPORTED(".short 0xfb08,0xad09  @ mla   sp, r8, r9, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb08ad09) "   @ mla   sp, r8, r9, r10");
-        TEST_UNSUPPORTED(".short 0xfb0f,0xa709  @ mla   r7, pc, r9, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb0fa709) "   @ mla   r7, pc, r9, r10");
-        TEST_UNSUPPORTED(".short 0xfb0d,0xa709  @ mla   r7, sp, r9, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb0da709) "   @ mla   r7, sp, r9, r10");
-        TEST_UNSUPPORTED(".short 0xfb08,0xa70f  @ mla   r7, r8, pc, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb08a70f) "   @ mla   r7, r8, pc, r10");
-        TEST_UNSUPPORTED(".short 0xfb08,0xa70d  @ mla   r7, r8, sp, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb08a70d) "   @ mla   r7, r8, sp, r10");
-        TEST_UNSUPPORTED(".short 0xfb08,0xd709  @ mla   r7, r8, r9, sp");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb08d709) "   @ mla   r7, r8, r9, sp");
        TEST_RRR(   "mls        r0, r",1, VAL1,", r",2, VAL2,", r",3,  VAL3,"")
        TEST_RRR(   "mls        r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
@@ -1123,25 +1124,25 @@ CONDITION_INSTRUCTIONS(22,
        TEST_RR(    "usad8      r0, r",0,  VAL1,", r",1, VAL2,"")
        TEST_RR(    "usad8      r14, r",12,VAL2,", r",10,VAL1,"")
-        TEST_UNSUPPORTED(".short 0xfb00,0xf010") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb00f010) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xfb0f,0xff1f") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb0fff1f) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xfb70,0xf010") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb70f010) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xfb7f,0xff1f") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb7fff1f) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xfb70,0x0010") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb700010) "") /* Unallocated space */
-        TEST_UNSUPPORTED(".short 0xfb7f,0xff1f") /* Unallocated space */
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb7fff1f) "") /* Unallocated space */
        TEST_GROUP("Long multiply, long multiply accumulate, and divide")
        TEST_RR(   "smull       r0, r1, r",2, VAL1,", r",3, VAL2,"")
        TEST_RR(   "smull       r7, r8, r",9, VAL2,", r",10, VAL1,"")
-        TEST_UNSUPPORTED(".short 0xfb89,0xf80a  @ smull pc, r8, r9, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb89f80a) "   @ smull pc, r8, r9, r10");
-        TEST_UNSUPPORTED(".short 0xfb89,0xd80a  @ smull sp, r8, r9, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb89d80a) "   @ smull sp, r8, r9, r10");
-        TEST_UNSUPPORTED(".short 0xfb89,0x7f0a  @ smull r7, pc, r9, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb897f0a) "   @ smull r7, pc, r9, r10");
-        TEST_UNSUPPORTED(".short 0xfb89,0x7d0a  @ smull r7, sp, r9, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb897d0a) "   @ smull r7, sp, r9, r10");
-        TEST_UNSUPPORTED(".short 0xfb8f,0x780a  @ smull r7, r8, pc, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb8f780a) "   @ smull r7, r8, pc, r10");
-        TEST_UNSUPPORTED(".short 0xfb8d,0x780a  @ smull r7, r8, sp, r10");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb8d780a) "   @ smull r7, r8, sp, r10");
-        TEST_UNSUPPORTED(".short 0xfb89,0x780f  @ smull r7, r8, r9, pc");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb89780f) "   @ smull r7, r8, r9, pc");
-        TEST_UNSUPPORTED(".short 0xfb89,0x780d  @ smull r7, r8, r9, sp");
+        TEST_UNSUPPORTED(__inst_thumb32(0xfb89780d) "   @ smull r7, r8, r9, sp");
        TEST_RR(   "umull       r0, r1, r",2, VAL1,", r",3, VAL2,"")
        TEST_RR(   "umull       r7, r8, r",9, VAL2,", r",10, VAL1,"")
@@ -1175,8 +1176,8 @@ CONDITION_INSTRUCTIONS(22,
        TEST_GROUP("Coprocessor instructions")
-        TEST_UNSUPPORTED(".short 0xfc00,0x0000")
+        TEST_UNSUPPORTED(__inst_thumb32(0xfc000000) "")
-        TEST_UNSUPPORTED(".short 0xffff,0xffff")
+        TEST_UNSUPPORTED(__inst_thumb32(0xffffffff) "")
        TEST_GROUP("Testing instructions in IT blocks")
diff --git a/arch/arm/kernel/kprobes-test.c b/arch/arm/kernel/kprobes-test.c
index 0cd63d080c7b..379639998d5a 100644
--- a/arch/arm/kernel/kprobes-test.c
+++ b/arch/arm/kernel/kprobes-test.c
@@ -113,7 +113,7 @@
 *      @ start of inline data...
 *      .ascii "mov r0, r7"     @ text title for test case
 *      .byte   0
- *      .align  2
+ *      .align  2, 0
 *
 *      @ TEST_ARG_REG
 *      .byte   ARG_TYPE_REG
@@ -201,10 +201,14 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/kprobes.h>
+#include <linux/errno.h>
+#include <linux/stddef.h>
+#include <linux/bug.h>
 #include <asm/opcodes.h>
 #include "kprobes.h"
+#include "probes-arm.h"
+#include "probes-thumb.h"
 #include "kprobes-test.h"
@@ -1329,7 +1333,8 @@ static void test_case_failed(const char *message)
 static unsigned long next_instruction(unsigned long pc)
 {
 #ifdef CONFIG_THUMB2_KERNEL
-        if ((pc & 1) && !is_wide_instruction(*(u16 *)(pc - 1)))
+        if ((pc & 1) &&
+            !is_wide_instruction(__mem_to_opcode_thumb16(*(u16 *)(pc - 1))))
                return pc + 2;
        else
 #endif
@@ -1374,13 +1379,13 @@ static uintptr_t __used kprobes_test_case_start(const char *title, void *stack)
        if (test_case_is_thumb) {
                u16 *p = (u16 *)(test_code & ~1);
-                current_instruction = p[0];
+                current_instruction = __mem_to_opcode_thumb16(p[0]);
                if (is_wide_instruction(current_instruction)) {
-                        current_instruction <<= 16;
+                        u16 instr2 = __mem_to_opcode_thumb16(p[1]);
-                        current_instruction |= p[1];
+                        current_instruction = __opcode_thumb32_compose(current_instruction, instr2);
                }
        } else {
-                current_instruction = *(u32 *)test_code;
+                current_instruction = __mem_to_opcode_arm(*(u32 *)test_code);
        }
        if (current_title[0] == '.')
@@ -1608,7 +1613,7 @@ static int __init run_all_tests(void)
                goto out;
        pr_info("ARM instruction simulation\n");
-        ret = run_test_cases(kprobe_arm_test_cases, kprobe_decode_arm_table);
+        ret = run_test_cases(kprobe_arm_test_cases, probes_decode_arm_table);
        if (ret)
                goto out;
@@ -1631,13 +1636,13 @@ static int __init run_all_tests(void)
        pr_info("16-bit Thumb instruction simulation\n");
        ret = run_test_cases(kprobe_thumb16_test_cases,
-                                kprobe_decode_thumb16_table);
+                                probes_decode_thumb16_table);
        if (ret)
                goto out;
        pr_info("32-bit Thumb instruction simulation\n");
        ret = run_test_cases(kprobe_thumb32_test_cases,
-                                kprobe_decode_thumb32_table);
+                                probes_decode_thumb32_table);
        if (ret)
                goto out;
 #endif
diff --git a/arch/arm/kernel/kprobes-test.h b/arch/arm/kernel/kprobes-test.h
index e28a869b1ae4..eecc90a0fd91 100644
--- a/arch/arm/kernel/kprobes-test.h
+++ b/arch/arm/kernel/kprobes-test.h
@@ -115,7 +115,7 @@ struct test_arg_end {
        /* multiple strings to be concatenated.  */             \
        ".ascii "#title"                                \n\t"   \
        ".byte  0                                       \n\t"   \
-        ".align 2                                       \n\t"
+        ".align 2, 0                                    \n\t"
 #define TEST_ARG_REG(reg, val)                                  \
        ".byte  "__stringify(ARG_TYPE_REG)"             \n\t"   \
diff --git a/arch/arm/kernel/kprobes-thumb.c b/arch/arm/kernel/kprobes-thumb.c
index 6123daf397a7..9495d7f3516f 100644
--- a/arch/arm/kernel/kprobes-thumb.c
+++ b/arch/arm/kernel/kprobes-thumb.c
@@ -8,41 +8,25 @@
 * published by the Free Software Foundation.
 */
+#include <linux/types.h>
 #include <linux/kernel.h>
+#include <linux/ptrace.h>
 #include <linux/kprobes.h>
-#include <linux/module.h>
 #include "kprobes.h"
+#include "probes-thumb.h"
+/* These emulation encodings are functionally equivalent... */
+#define t32_emulate_rd8rn16rm0ra12_noflags \
+                t32_emulate_rdlo12rdhi8rn16rm0_noflags
-/*
+/* t32 thumb actions */
- * True if current instruction is in an IT block.
- */
-#define in_it_block(cpsr)       ((cpsr & 0x06000c00) != 0x00000000)
-/*
- * Return the condition code to check for the currently executing instruction.
- * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
- * in_it_block returns true.
- */
-#define current_cond(cpsr)      ((cpsr >> 12) & 0xf)
-/*
- * Return the PC value for a probe in thumb code.
- * This is the address of the probed instruction plus 4.
- * We subtract one because the address will have bit zero set to indicate
- * a pointer to thumb code.
- */
-static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
-{
-        return (unsigned long)p->addr - 1 + 4;
-}
 static void __kprobes
-t32_simulate_table_branch(struct kprobe *p, struct pt_regs *regs)
+t32_simulate_table_branch(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc;
-        unsigned long pc = thumb_probe_pc(p);
        int rn = (insn >> 16) & 0xf;
        int rm = insn & 0xf;
@@ -59,19 +43,19 @@ t32_simulate_table_branch(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t32_simulate_mrs(struct kprobe *p, struct pt_regs *regs)
+t32_simulate_mrs(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rd = (insn >> 8) & 0xf;
        unsigned long mask = 0xf8ff03df; /* Mask out execution state */
        regs->uregs[rd] = regs->ARM_cpsr & mask;
 }
 static void __kprobes
-t32_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
+t32_simulate_cond_branch(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc;
-        unsigned long pc = thumb_probe_pc(p);
        long offset = insn & 0x7ff;             /* imm11 */
        offset += (insn & 0x003f0000) >> 5;     /* imm6 */
@@ -82,20 +66,21 @@ t32_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
        regs->ARM_pc = pc + (offset * 2);
 }
-static enum kprobe_insn __kprobes
+static enum probes_insn __kprobes
-t32_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+t32_decode_cond_branch(probes_opcode_t insn, struct arch_probes_insn *asi,
+                const struct decode_header *d)
 {
        int cc = (insn >> 22) & 0xf;
-        asi->insn_check_cc = kprobe_condition_checks[cc];
+        asi->insn_check_cc = probes_condition_checks[cc];
        asi->insn_handler = t32_simulate_cond_branch;
        return INSN_GOOD_NO_SLOT;
 }
 static void __kprobes
-t32_simulate_branch(struct kprobe *p, struct pt_regs *regs)
+t32_simulate_branch(probes_opcode_t insn,
+                    struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc;
-        unsigned long pc = thumb_probe_pc(p);
        long offset = insn & 0x7ff;             /* imm11 */
        offset += (insn & 0x03ff0000) >> 5;     /* imm10 */
@@ -108,7 +93,7 @@ t32_simulate_branch(struct kprobe *p, struct pt_regs *regs)
        if (insn & (1 << 14)) {
                /* BL or BLX */
-                regs->ARM_lr = (unsigned long)p->addr + 4;
+                regs->ARM_lr = regs->ARM_pc | 1;
                if (!(insn & (1 << 12))) {
                        /* BLX so switch to ARM mode */
                        regs->ARM_cpsr &= ~PSR_T_BIT;
@@ -120,10 +105,10 @@ t32_simulate_branch(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t32_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
+t32_simulate_ldr_literal(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long addr = regs->ARM_pc & ~3;
-        unsigned long addr = thumb_probe_pc(p) & ~3;
        int rt = (insn >> 12) & 0xf;
        unsigned long rtv;
@@ -157,24 +142,25 @@ t32_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
        regs->uregs[rt] = rtv;
 }
-static enum kprobe_insn __kprobes
+static enum probes_insn __kprobes
-t32_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+t32_decode_ldmstm(probes_opcode_t insn, struct arch_probes_insn *asi,
+                const struct decode_header *d)
 {
-        enum kprobe_insn ret = kprobe_decode_ldmstm(insn, asi);
+        enum probes_insn ret = kprobe_decode_ldmstm(insn, asi, d);
        /* Fixup modified instruction to have halfwords in correct order...*/
-        insn = asi->insn[0];
+        insn = __mem_to_opcode_arm(asi->insn[0]);
-        ((u16 *)asi->insn)[0] = insn >> 16;
+        ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn >> 16);
-        ((u16 *)asi->insn)[1] = insn & 0xffff;
+        ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0xffff);
        return ret;
 }
 static void __kprobes
-t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
+t32_emulate_ldrdstrd(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc & ~3;
-        unsigned long pc = thumb_probe_pc(p) & ~3;
        int rt1 = (insn >> 12) & 0xf;
        int rt2 = (insn >> 8) & 0xf;
        int rn = (insn >> 16) & 0xf;
@@ -187,7 +173,7 @@ t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
        __asm__ __volatile__ (
                "blx    %[fn]"
                : "=r" (rt1v), "=r" (rt2v), "=r" (rnv)
-                : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (p->ainsn.insn_fn)
+                : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -198,9 +184,9 @@ t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t32_emulate_ldrstr(struct kprobe *p, struct pt_regs *regs)
+t32_emulate_ldrstr(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rt = (insn >> 12) & 0xf;
        int rn = (insn >> 16) & 0xf;
        int rm = insn & 0xf;
@@ -212,7 +198,7 @@ t32_emulate_ldrstr(struct kprobe *p, struct pt_regs *regs)
        __asm__ __volatile__ (
                "blx    %[fn]"
                : "=r" (rtv), "=r" (rnv)
-                : "0" (rtv), "1" (rnv), "r" (rmv), [fn] "r" (p->ainsn.insn_fn)
+                : "0" (rtv), "1" (rnv), "r" (rmv), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -224,9 +210,9 @@ t32_emulate_ldrstr(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t32_emulate_rd8rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
+t32_emulate_rd8rn16rm0_rwflags(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rd = (insn >> 8) & 0xf;
        int rn = (insn >> 16) & 0xf;
        int rm = insn & 0xf;
@@ -242,7 +228,7 @@ t32_emulate_rd8rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
                "mrs    %[cpsr], cpsr           \n\t"
                : "=r" (rdv), [cpsr] "=r" (cpsr)
                : "0" (rdv), "r" (rnv), "r" (rmv),
-                  "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
+                  "1" (cpsr), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -251,10 +237,10 @@ t32_emulate_rd8rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t32_emulate_rd8pc16_noflags(struct kprobe *p, struct pt_regs *regs)
+t32_emulate_rd8pc16_noflags(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc;
-        unsigned long pc = thumb_probe_pc(p);
        int rd = (insn >> 8) & 0xf;
        register unsigned long rdv asm("r1") = regs->uregs[rd];
@@ -263,7 +249,7 @@ t32_emulate_rd8pc16_noflags(struct kprobe *p, struct pt_regs *regs)
        __asm__ __volatile__ (
                "blx    %[fn]"
                : "=r" (rdv)
-                : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
+                : "0" (rdv), "r" (rnv), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -271,9 +257,9 @@ t32_emulate_rd8pc16_noflags(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t32_emulate_rd8rn16_noflags(struct kprobe *p, struct pt_regs *regs)
+t32_emulate_rd8rn16_noflags(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rd = (insn >> 8) & 0xf;
        int rn = (insn >> 16) & 0xf;
@@ -283,7 +269,7 @@ t32_emulate_rd8rn16_noflags(struct kprobe *p, struct pt_regs *regs)
        __asm__ __volatile__ (
                "blx    %[fn]"
                : "=r" (rdv)
-                : "0" (rdv), "r" (rnv), [fn] "r" (p->ainsn.insn_fn)
+                : "0" (rdv), "r" (rnv), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -291,9 +277,10 @@ t32_emulate_rd8rn16_noflags(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t32_emulate_rdlo12rdhi8rn16rm0_noflags(struct kprobe *p, struct pt_regs *regs)
+t32_emulate_rdlo12rdhi8rn16rm0_noflags(probes_opcode_t insn,
+                struct arch_probes_insn *asi,
+                struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rdlo = (insn >> 12) & 0xf;
        int rdhi = (insn >> 8) & 0xf;
        int rn = (insn >> 16) & 0xf;
@@ -308,674 +295,43 @@ t32_emulate_rdlo12rdhi8rn16rm0_noflags(struct kprobe *p, struct pt_regs *regs)
                "blx    %[fn]"
                : "=r" (rdlov), "=r" (rdhiv)
                : "0" (rdlov), "1" (rdhiv), "r" (rnv), "r" (rmv),
-                  [fn] "r" (p->ainsn.insn_fn)
+                  [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
        regs->uregs[rdlo] = rdlov;
        regs->uregs[rdhi] = rdhiv;
 }
+/* t16 thumb actions */
-/* These emulation encodings are functionally equivalent... */
-#define t32_emulate_rd8rn16rm0ra12_noflags \
-                t32_emulate_rdlo12rdhi8rn16rm0_noflags
-static const union decode_item t32_table_1110_100x_x0xx[] = {
-        /* Load/store multiple instructions */
-        /* Rn is PC             1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfe4f0000, 0xe80f0000),
-        /* SRS                  1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */
-        /* RFE                  1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xffc00000, 0xe8000000),
-        /* SRS                  1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */
-        /* RFE                  1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xffc00000, 0xe9800000),
-        /* STM Rn, {...pc}      1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfe508000, 0xe8008000),
-        /* LDM Rn, {...lr,pc}   1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfe50c000, 0xe810c000),
-        /* LDM/STM Rn, {...sp}  1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfe402000, 0xe8002000),
-        /* STMIA                1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */
-        /* LDMIA                1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */
-        /* STMDB                1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */
-        /* LDMDB                1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_CUSTOM   (0xfe400000, 0xe8000000, t32_decode_ldmstm),
-        DECODE_END
-};
-static const union decode_item t32_table_1110_100x_x1xx[] = {
-        /* Load/store dual, load/store exclusive, table branch */
-        /* STRD (immediate)     1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRD (immediate)     1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_OR       (0xff600000, 0xe8600000),
-        /* STRD (immediate)     1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRD (immediate)     1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xff400000, 0xe9400000, t32_emulate_ldrdstrd,
-                                                 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
-        /* TBB                  1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */
-        /* TBH                  1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */
-        DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, t32_simulate_table_branch,
-                                                 REGS(NOSP, 0, 0, 0, NOSPPC)),
-        /* STREX                1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */
-        /* LDREX                1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */
-        /* STREXB               1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */
-        /* STREXH               1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */
-        /* STREXD               1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */
-        /* LDREXB               1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */
-        /* LDREXH               1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */
-        /* LDREXD               1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */
-        /* And unallocated instructions...                              */
-        DECODE_END
-};
-static const union decode_item t32_table_1110_101x[] = {
-        /* Data-processing (shifted register)                           */
-        /* TST                  1110 1010 0001 xxxx xxxx 1111 xxxx xxxx */
-        /* TEQ                  1110 1010 1001 xxxx xxxx 1111 xxxx xxxx */
-        DECODE_EMULATEX (0xff700f00, 0xea100f00, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(NOSPPC, 0, 0, 0, NOSPPC)),
-        /* CMN                  1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */
-        DECODE_OR       (0xfff00f00, 0xeb100f00),
-        /* CMP                  1110 1011 1011 xxxx xxxx 1111 xxxx xxxx */
-        DECODE_EMULATEX (0xfff00f00, 0xebb00f00, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(NOPC, 0, 0, 0, NOSPPC)),
-        /* MOV                  1110 1010 010x 1111 xxxx xxxx xxxx xxxx */
-        /* MVN                  1110 1010 011x 1111 xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xffcf0000, 0xea4f0000, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(0, 0, NOSPPC, 0, NOSPPC)),
-        /* ???                  1110 1010 101x xxxx xxxx xxxx xxxx xxxx */
-        /* ???                  1110 1010 111x xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xffa00000, 0xeaa00000),
-        /* ???                  1110 1011 001x xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xffe00000, 0xeb200000),
-        /* ???                  1110 1011 100x xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xffe00000, 0xeb800000),
-        /* ???                  1110 1011 111x xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xffe00000, 0xebe00000),
-        /* ADD/SUB SP, SP, Rm, LSL #0..3                                */
-        /*                      1110 1011 x0xx 1101 x000 1101 xx00 xxxx */
-        DECODE_EMULATEX (0xff4f7f30, 0xeb0d0d00, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(SP, 0, SP, 0, NOSPPC)),
-        /* ADD/SUB SP, SP, Rm, shift                                    */
-        /*                      1110 1011 x0xx 1101 xxxx 1101 xxxx xxxx */
-        DECODE_REJECT   (0xff4f0f00, 0xeb0d0d00),
-        /* ADD/SUB Rd, SP, Rm, shift                                    */
-        /*                      1110 1011 x0xx 1101 xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xff4f0000, 0xeb0d0000, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(SP, 0, NOPC, 0, NOSPPC)),
-        /* AND                  1110 1010 000x xxxx xxxx xxxx xxxx xxxx */
-        /* BIC                  1110 1010 001x xxxx xxxx xxxx xxxx xxxx */
-        /* ORR                  1110 1010 010x xxxx xxxx xxxx xxxx xxxx */
-        /* ORN                  1110 1010 011x xxxx xxxx xxxx xxxx xxxx */
-        /* EOR                  1110 1010 100x xxxx xxxx xxxx xxxx xxxx */
-        /* PKH                  1110 1010 110x xxxx xxxx xxxx xxxx xxxx */
-        /* ADD                  1110 1011 000x xxxx xxxx xxxx xxxx xxxx */
-        /* ADC                  1110 1011 010x xxxx xxxx xxxx xxxx xxxx */
-        /* SBC                  1110 1011 011x xxxx xxxx xxxx xxxx xxxx */
-        /* SUB                  1110 1011 101x xxxx xxxx xxxx xxxx xxxx */
-        /* RSB                  1110 1011 110x xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfe000000, 0xea000000, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
-        DECODE_END
-};
-static const union decode_item t32_table_1111_0x0x___0[] = {
-        /* Data-processing (modified immediate)                         */
-        /* TST                  1111 0x00 0001 xxxx 0xxx 1111 xxxx xxxx */
-        /* TEQ                  1111 0x00 1001 xxxx 0xxx 1111 xxxx xxxx */
-        DECODE_EMULATEX (0xfb708f00, 0xf0100f00, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(NOSPPC, 0, 0, 0, 0)),
-        /* CMN                  1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */
-        DECODE_OR       (0xfbf08f00, 0xf1100f00),
-        /* CMP                  1111 0x01 1011 xxxx 0xxx 1111 xxxx xxxx */
-        DECODE_EMULATEX (0xfbf08f00, 0xf1b00f00, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(NOPC, 0, 0, 0, 0)),
-        /* MOV                  1111 0x00 010x 1111 0xxx xxxx xxxx xxxx */
-        /* MVN                  1111 0x00 011x 1111 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfbcf8000, 0xf04f0000, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(0, 0, NOSPPC, 0, 0)),
-        /* ???                  1111 0x00 101x xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfbe08000, 0xf0a00000),
-        /* ???                  1111 0x00 110x xxxx 0xxx xxxx xxxx xxxx */
-        /* ???                  1111 0x00 111x xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfbc08000, 0xf0c00000),
-        /* ???                  1111 0x01 001x xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfbe08000, 0xf1200000),
-        /* ???                  1111 0x01 100x xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfbe08000, 0xf1800000),
-        /* ???                  1111 0x01 111x xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfbe08000, 0xf1e00000),
-        /* ADD Rd, SP, #imm     1111 0x01 000x 1101 0xxx xxxx xxxx xxxx */
-        /* SUB Rd, SP, #imm     1111 0x01 101x 1101 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfb4f8000, 0xf10d0000, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(SP, 0, NOPC, 0, 0)),
-        /* AND                  1111 0x00 000x xxxx 0xxx xxxx xxxx xxxx */
-        /* BIC                  1111 0x00 001x xxxx 0xxx xxxx xxxx xxxx */
-        /* ORR                  1111 0x00 010x xxxx 0xxx xxxx xxxx xxxx */
-        /* ORN                  1111 0x00 011x xxxx 0xxx xxxx xxxx xxxx */
-        /* EOR                  1111 0x00 100x xxxx 0xxx xxxx xxxx xxxx */
-        /* ADD                  1111 0x01 000x xxxx 0xxx xxxx xxxx xxxx */
-        /* ADC                  1111 0x01 010x xxxx 0xxx xxxx xxxx xxxx */
-        /* SBC                  1111 0x01 011x xxxx 0xxx xxxx xxxx xxxx */
-        /* SUB                  1111 0x01 101x xxxx 0xxx xxxx xxxx xxxx */
-        /* RSB                  1111 0x01 110x xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfa008000, 0xf0000000, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
-        DECODE_END
-};
-static const union decode_item t32_table_1111_0x1x___0[] = {
-        /* Data-processing (plain binary immediate)                     */
-        /* ADDW Rd, PC, #imm    1111 0x10 0000 1111 0xxx xxxx xxxx xxxx */
-        DECODE_OR       (0xfbff8000, 0xf20f0000),
-        /* SUBW Rd, PC, #imm    1111 0x10 1010 1111 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfbff8000, 0xf2af0000, t32_emulate_rd8pc16_noflags,
-                                                 REGS(PC, 0, NOSPPC, 0, 0)),
-        /* ADDW SP, SP, #imm    1111 0x10 0000 1101 0xxx 1101 xxxx xxxx */
-        DECODE_OR       (0xfbff8f00, 0xf20d0d00),
-        /* SUBW SP, SP, #imm    1111 0x10 1010 1101 0xxx 1101 xxxx xxxx */
-        DECODE_EMULATEX (0xfbff8f00, 0xf2ad0d00, t32_emulate_rd8rn16_noflags,
-                                                 REGS(SP, 0, SP, 0, 0)),
-        /* ADDW                 1111 0x10 0000 xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_OR       (0xfbf08000, 0xf2000000),
-        /* SUBW                 1111 0x10 1010 xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfbf08000, 0xf2a00000, t32_emulate_rd8rn16_noflags,
-                                                 REGS(NOPCX, 0, NOSPPC, 0, 0)),
-        /* MOVW                 1111 0x10 0100 xxxx 0xxx xxxx xxxx xxxx */
-        /* MOVT                 1111 0x10 1100 xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfb708000, 0xf2400000, t32_emulate_rd8rn16_noflags,
-                                                 REGS(0, 0, NOSPPC, 0, 0)),
-        /* SSAT16               1111 0x11 0010 xxxx 0000 xxxx 00xx xxxx */
-        /* SSAT                 1111 0x11 00x0 xxxx 0xxx xxxx xxxx xxxx */
-        /* USAT16               1111 0x11 1010 xxxx 0000 xxxx 00xx xxxx */
-        /* USAT                 1111 0x11 10x0 xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfb508000, 0xf3000000, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
-        /* SFBX                 1111 0x11 0100 xxxx 0xxx xxxx xxxx xxxx */
-        /* UFBX                 1111 0x11 1100 xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfb708000, 0xf3400000, t32_emulate_rd8rn16_noflags,
-                                                 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
-        /* BFC                  1111 0x11 0110 1111 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfbff8000, 0xf36f0000, t32_emulate_rd8rn16_noflags,
-                                                 REGS(0, 0, NOSPPC, 0, 0)),
-        /* BFI                  1111 0x11 0110 xxxx 0xxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfbf08000, 0xf3600000, t32_emulate_rd8rn16_noflags,
-                                                 REGS(NOSPPCX, 0, NOSPPC, 0, 0)),
-        DECODE_END
-};
-static const union decode_item t32_table_1111_0xxx___1[] = {
-        /* Branches and miscellaneous control                           */
-        /* YIELD                1111 0011 1010 xxxx 10x0 x000 0000 0001 */
-        DECODE_OR       (0xfff0d7ff, 0xf3a08001),
-        /* SEV                  1111 0011 1010 xxxx 10x0 x000 0000 0100 */
-        DECODE_EMULATE  (0xfff0d7ff, 0xf3a08004, kprobe_emulate_none),
-        /* NOP                  1111 0011 1010 xxxx 10x0 x000 0000 0000 */
-        /* WFE                  1111 0011 1010 xxxx 10x0 x000 0000 0010 */
-        /* WFI                  1111 0011 1010 xxxx 10x0 x000 0000 0011 */
-        DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, kprobe_simulate_nop),
-        /* MRS Rd, CPSR         1111 0011 1110 xxxx 10x0 xxxx xxxx xxxx */
-        DECODE_SIMULATEX(0xfff0d000, 0xf3e08000, t32_simulate_mrs,
-                                                 REGS(0, 0, NOSPPC, 0, 0)),
-        /*
-         * Unsupported instructions
-         *                      1111 0x11 1xxx xxxx 10x0 xxxx xxxx xxxx
-         *
-         * MSR                  1111 0011 100x xxxx 10x0 xxxx xxxx xxxx
-         * DBG hint             1111 0011 1010 xxxx 10x0 x000 1111 xxxx
-         * Unallocated hints    1111 0011 1010 xxxx 10x0 x000 xxxx xxxx
-         * CPS                  1111 0011 1010 xxxx 10x0 xxxx xxxx xxxx
-         * CLREX/DSB/DMB/ISB    1111 0011 1011 xxxx 10x0 xxxx xxxx xxxx
-         * BXJ                  1111 0011 1100 xxxx 10x0 xxxx xxxx xxxx
-         * SUBS PC,LR,#<imm8>   1111 0011 1101 xxxx 10x0 xxxx xxxx xxxx
-         * MRS Rd, SPSR         1111 0011 1111 xxxx 10x0 xxxx xxxx xxxx
-         * SMC                  1111 0111 1111 xxxx 1000 xxxx xxxx xxxx
-         * UNDEFINED            1111 0111 1111 xxxx 1010 xxxx xxxx xxxx
-         * ???                  1111 0111 1xxx xxxx 1010 xxxx xxxx xxxx
-         */
-        DECODE_REJECT   (0xfb80d000, 0xf3808000),
-        /* Bcc                  1111 0xxx xxxx xxxx 10x0 xxxx xxxx xxxx */
-        DECODE_CUSTOM   (0xf800d000, 0xf0008000, t32_decode_cond_branch),
-        /* BLX                  1111 0xxx xxxx xxxx 11x0 xxxx xxxx xxx0 */
-        DECODE_OR       (0xf800d001, 0xf000c000),
-        /* B                    1111 0xxx xxxx xxxx 10x1 xxxx xxxx xxxx */
-        /* BL                   1111 0xxx xxxx xxxx 11x1 xxxx xxxx xxxx */
-        DECODE_SIMULATE (0xf8009000, 0xf0009000, t32_simulate_branch),
-        DECODE_END
-};
-static const union decode_item t32_table_1111_100x_x0x1__1111[] = {
-        /* Memory hints                                                 */
-        /* PLD (literal)        1111 1000 x001 1111 1111 xxxx xxxx xxxx */
-        /* PLI (literal)        1111 1001 x001 1111 1111 xxxx xxxx xxxx */
-        DECODE_SIMULATE (0xfe7ff000, 0xf81ff000, kprobe_simulate_nop),
-        /* PLD{W} (immediate)   1111 1000 10x1 xxxx 1111 xxxx xxxx xxxx */
-        DECODE_OR       (0xffd0f000, 0xf890f000),
-        /* PLD{W} (immediate)   1111 1000 00x1 xxxx 1111 1100 xxxx xxxx */
-        DECODE_OR       (0xffd0ff00, 0xf810fc00),
-        /* PLI (immediate)      1111 1001 1001 xxxx 1111 xxxx xxxx xxxx */
-        DECODE_OR       (0xfff0f000, 0xf990f000),
-        /* PLI (immediate)      1111 1001 0001 xxxx 1111 1100 xxxx xxxx */
-        DECODE_SIMULATEX(0xfff0ff00, 0xf910fc00, kprobe_simulate_nop,
-                                                 REGS(NOPCX, 0, 0, 0, 0)),
-        /* PLD{W} (register)    1111 1000 00x1 xxxx 1111 0000 00xx xxxx */
-        DECODE_OR       (0xffd0ffc0, 0xf810f000),
-        /* PLI (register)       1111 1001 0001 xxxx 1111 0000 00xx xxxx */
-        DECODE_SIMULATEX(0xfff0ffc0, 0xf910f000, kprobe_simulate_nop,
-                                                 REGS(NOPCX, 0, 0, 0, NOSPPC)),
-        /* Other unallocated instructions...                            */
-        DECODE_END
-};
-static const union decode_item t32_table_1111_100x[] = {
-        /* Store/Load single data item                                  */
-        /* ???                  1111 100x x11x xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfe600000, 0xf8600000),
-        /* ???                  1111 1001 0101 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xfff00000, 0xf9500000),
-        /* ???                  1111 100x 0xxx xxxx xxxx 10x0 xxxx xxxx */
-        DECODE_REJECT   (0xfe800d00, 0xf8000800),
-        /* STRBT                1111 1000 0000 xxxx xxxx 1110 xxxx xxxx */
-        /* STRHT                1111 1000 0010 xxxx xxxx 1110 xxxx xxxx */
-        /* STRT                 1111 1000 0100 xxxx xxxx 1110 xxxx xxxx */
-        /* LDRBT                1111 1000 0001 xxxx xxxx 1110 xxxx xxxx */
-        /* LDRSBT               1111 1001 0001 xxxx xxxx 1110 xxxx xxxx */
-        /* LDRHT                1111 1000 0011 xxxx xxxx 1110 xxxx xxxx */
-        /* LDRSHT               1111 1001 0011 xxxx xxxx 1110 xxxx xxxx */
-        /* LDRT                 1111 1000 0101 xxxx xxxx 1110 xxxx xxxx */
-        DECODE_REJECT   (0xfe800f00, 0xf8000e00),
-        /* STR{,B,H} Rn,[PC...] 1111 1000 xxx0 1111 xxxx xxxx xxxx xxxx */
-        DECODE_REJECT   (0xff1f0000, 0xf80f0000),
-        /* STR{,B,H} PC,[Rn...] 1111 1000 xxx0 xxxx 1111 xxxx xxxx xxxx */
-        DECODE_REJECT   (0xff10f000, 0xf800f000),
-        /* LDR (literal)        1111 1000 x101 1111 xxxx xxxx xxxx xxxx */
-        DECODE_SIMULATEX(0xff7f0000, 0xf85f0000, t32_simulate_ldr_literal,
-                                                 REGS(PC, ANY, 0, 0, 0)),
-        /* STR (immediate)      1111 1000 0100 xxxx xxxx 1xxx xxxx xxxx */
-        /* LDR (immediate)      1111 1000 0101 xxxx xxxx 1xxx xxxx xxxx */
-        DECODE_OR       (0xffe00800, 0xf8400800),
-        /* STR (immediate)      1111 1000 1100 xxxx xxxx xxxx xxxx xxxx */
-        /* LDR (immediate)      1111 1000 1101 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xffe00000, 0xf8c00000, t32_emulate_ldrstr,
-                                                 REGS(NOPCX, ANY, 0, 0, 0)),
-        /* STR (register)       1111 1000 0100 xxxx xxxx 0000 00xx xxxx */
-        /* LDR (register)       1111 1000 0101 xxxx xxxx 0000 00xx xxxx */
-        DECODE_EMULATEX (0xffe00fc0, 0xf8400000, t32_emulate_ldrstr,
-                                                 REGS(NOPCX, ANY, 0, 0, NOSPPC)),
-        /* LDRB (literal)       1111 1000 x001 1111 xxxx xxxx xxxx xxxx */
-        /* LDRSB (literal)      1111 1001 x001 1111 xxxx xxxx xxxx xxxx */
-        /* LDRH (literal)       1111 1000 x011 1111 xxxx xxxx xxxx xxxx */
-        /* LDRSH (literal)      1111 1001 x011 1111 xxxx xxxx xxxx xxxx */
-        DECODE_SIMULATEX(0xfe5f0000, 0xf81f0000, t32_simulate_ldr_literal,
-                                                 REGS(PC, NOSPPCX, 0, 0, 0)),
-        /* STRB (immediate)     1111 1000 0000 xxxx xxxx 1xxx xxxx xxxx */
-        /* STRH (immediate)     1111 1000 0010 xxxx xxxx 1xxx xxxx xxxx */
-        /* LDRB (immediate)     1111 1000 0001 xxxx xxxx 1xxx xxxx xxxx */
-        /* LDRSB (immediate)    1111 1001 0001 xxxx xxxx 1xxx xxxx xxxx */
-        /* LDRH (immediate)     1111 1000 0011 xxxx xxxx 1xxx xxxx xxxx */
-        /* LDRSH (immediate)    1111 1001 0011 xxxx xxxx 1xxx xxxx xxxx */
-        DECODE_OR       (0xfec00800, 0xf8000800),
-        /* STRB (immediate)     1111 1000 1000 xxxx xxxx xxxx xxxx xxxx */
-        /* STRH (immediate)     1111 1000 1010 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRB (immediate)     1111 1000 1001 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRSB (immediate)    1111 1001 1001 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRH (immediate)     1111 1000 1011 xxxx xxxx xxxx xxxx xxxx */
-        /* LDRSH (immediate)    1111 1001 1011 xxxx xxxx xxxx xxxx xxxx */
-        DECODE_EMULATEX (0xfec00000, 0xf8800000, t32_emulate_ldrstr,
-                                                 REGS(NOPCX, NOSPPCX, 0, 0, 0)),
-        /* STRB (register)      1111 1000 0000 xxxx xxxx 0000 00xx xxxx */
-        /* STRH (register)      1111 1000 0010 xxxx xxxx 0000 00xx xxxx */
-        /* LDRB (register)      1111 1000 0001 xxxx xxxx 0000 00xx xxxx */
-        /* LDRSB (register)     1111 1001 0001 xxxx xxxx 0000 00xx xxxx */
-        /* LDRH (register)      1111 1000 0011 xxxx xxxx 0000 00xx xxxx */
-        /* LDRSH (register)     1111 1001 0011 xxxx xxxx 0000 00xx xxxx */
-        DECODE_EMULATEX (0xfe800fc0, 0xf8000000, t32_emulate_ldrstr,
-                                                 REGS(NOPCX, NOSPPCX, 0, 0, NOSPPC)),
-        /* Other unallocated instructions...                            */
-        DECODE_END
-};
-static const union decode_item t32_table_1111_1010___1111[] = {
-        /* Data-processing (register)                                   */
-        /* ???                  1111 1010 011x xxxx 1111 xxxx 1xxx xxxx */
-        DECODE_REJECT   (0xffe0f080, 0xfa60f080),
-        /* SXTH                 1111 1010 0000 1111 1111 xxxx 1xxx xxxx */
-        /* UXTH                 1111 1010 0001 1111 1111 xxxx 1xxx xxxx */
-        /* SXTB16               1111 1010 0010 1111 1111 xxxx 1xxx xxxx */
-        /* UXTB16               1111 1010 0011 1111 1111 xxxx 1xxx xxxx */
-        /* SXTB                 1111 1010 0100 1111 1111 xxxx 1xxx xxxx */
-        /* UXTB                 1111 1010 0101 1111 1111 xxxx 1xxx xxxx */
-        DECODE_EMULATEX (0xff8ff080, 0xfa0ff080, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(0, 0, NOSPPC, 0, NOSPPC)),
-        /* ???                  1111 1010 1xxx xxxx 1111 xxxx 0x11 xxxx */
-        DECODE_REJECT   (0xff80f0b0, 0xfa80f030),
-        /* ???                  1111 1010 1x11 xxxx 1111 xxxx 0xxx xxxx */
-        DECODE_REJECT   (0xffb0f080, 0xfab0f000),
-        /* SADD16               1111 1010 1001 xxxx 1111 xxxx 0000 xxxx */
-        /* SASX                 1111 1010 1010 xxxx 1111 xxxx 0000 xxxx */
-        /* SSAX                 1111 1010 1110 xxxx 1111 xxxx 0000 xxxx */
-        /* SSUB16               1111 1010 1101 xxxx 1111 xxxx 0000 xxxx */
-        /* SADD8                1111 1010 1000 xxxx 1111 xxxx 0000 xxxx */
-        /* SSUB8                1111 1010 1100 xxxx 1111 xxxx 0000 xxxx */
-        /* QADD16               1111 1010 1001 xxxx 1111 xxxx 0001 xxxx */
-        /* QASX                 1111 1010 1010 xxxx 1111 xxxx 0001 xxxx */
-        /* QSAX                 1111 1010 1110 xxxx 1111 xxxx 0001 xxxx */
-        /* QSUB16               1111 1010 1101 xxxx 1111 xxxx 0001 xxxx */
-        /* QADD8                1111 1010 1000 xxxx 1111 xxxx 0001 xxxx */
-        /* QSUB8                1111 1010 1100 xxxx 1111 xxxx 0001 xxxx */
-        /* SHADD16              1111 1010 1001 xxxx 1111 xxxx 0010 xxxx */
-        /* SHASX                1111 1010 1010 xxxx 1111 xxxx 0010 xxxx */
-        /* SHSAX                1111 1010 1110 xxxx 1111 xxxx 0010 xxxx */
-        /* SHSUB16              1111 1010 1101 xxxx 1111 xxxx 0010 xxxx */
-        /* SHADD8               1111 1010 1000 xxxx 1111 xxxx 0010 xxxx */
-        /* SHSUB8               1111 1010 1100 xxxx 1111 xxxx 0010 xxxx */
-        /* UADD16               1111 1010 1001 xxxx 1111 xxxx 0100 xxxx */
-        /* UASX                 1111 1010 1010 xxxx 1111 xxxx 0100 xxxx */
-        /* USAX                 1111 1010 1110 xxxx 1111 xxxx 0100 xxxx */
-        /* USUB16               1111 1010 1101 xxxx 1111 xxxx 0100 xxxx */
-        /* UADD8                1111 1010 1000 xxxx 1111 xxxx 0100 xxxx */
-        /* USUB8                1111 1010 1100 xxxx 1111 xxxx 0100 xxxx */
-        /* UQADD16              1111 1010 1001 xxxx 1111 xxxx 0101 xxxx */
-        /* UQASX                1111 1010 1010 xxxx 1111 xxxx 0101 xxxx */
-        /* UQSAX                1111 1010 1110 xxxx 1111 xxxx 0101 xxxx */
-        /* UQSUB16              1111 1010 1101 xxxx 1111 xxxx 0101 xxxx */
-        /* UQADD8               1111 1010 1000 xxxx 1111 xxxx 0101 xxxx */
-        /* UQSUB8               1111 1010 1100 xxxx 1111 xxxx 0101 xxxx */
-        /* UHADD16              1111 1010 1001 xxxx 1111 xxxx 0110 xxxx */
-        /* UHASX                1111 1010 1010 xxxx 1111 xxxx 0110 xxxx */
-        /* UHSAX                1111 1010 1110 xxxx 1111 xxxx 0110 xxxx */
-        /* UHSUB16              1111 1010 1101 xxxx 1111 xxxx 0110 xxxx */
-        /* UHADD8               1111 1010 1000 xxxx 1111 xxxx 0110 xxxx */
-        /* UHSUB8               1111 1010 1100 xxxx 1111 xxxx 0110 xxxx */
-        DECODE_OR       (0xff80f080, 0xfa80f000),
-        /* SXTAH                1111 1010 0000 xxxx 1111 xxxx 1xxx xxxx */
-        /* UXTAH                1111 1010 0001 xxxx 1111 xxxx 1xxx xxxx */
-        /* SXTAB16              1111 1010 0010 xxxx 1111 xxxx 1xxx xxxx */
-        /* UXTAB16              1111 1010 0011 xxxx 1111 xxxx 1xxx xxxx */
-        /* SXTAB                1111 1010 0100 xxxx 1111 xxxx 1xxx xxxx */
-        /* UXTAB                1111 1010 0101 xxxx 1111 xxxx 1xxx xxxx */
-        DECODE_OR       (0xff80f080, 0xfa00f080),
-        /* QADD                 1111 1010 1000 xxxx 1111 xxxx 1000 xxxx */
-        /* QDADD                1111 1010 1000 xxxx 1111 xxxx 1001 xxxx */
-        /* QSUB                 1111 1010 1000 xxxx 1111 xxxx 1010 xxxx */
-        /* QDSUB                1111 1010 1000 xxxx 1111 xxxx 1011 xxxx */
-        DECODE_OR       (0xfff0f0c0, 0xfa80f080),
-        /* SEL                  1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
-        DECODE_OR       (0xfff0f0f0, 0xfaa0f080),
-        /* LSL                  1111 1010 000x xxxx 1111 xxxx 0000 xxxx */
-        /* LSR                  1111 1010 001x xxxx 1111 xxxx 0000 xxxx */
-        /* ASR                  1111 1010 010x xxxx 1111 xxxx 0000 xxxx */
-        /* ROR                  1111 1010 011x xxxx 1111 xxxx 0000 xxxx */
-        DECODE_EMULATEX (0xff80f0f0, 0xfa00f000, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
-        /* CLZ                  1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
-        DECODE_OR       (0xfff0f0f0, 0xfab0f080),
-        /* REV                  1111 1010 1001 xxxx 1111 xxxx 1000 xxxx */
-        /* REV16                1111 1010 1001 xxxx 1111 xxxx 1001 xxxx */
-        /* RBIT                 1111 1010 1001 xxxx 1111 xxxx 1010 xxxx */
-        /* REVSH                1111 1010 1001 xxxx 1111 xxxx 1011 xxxx */
-        DECODE_EMULATEX (0xfff0f0c0, 0xfa90f080, t32_emulate_rd8rn16_noflags,
-                                                 REGS(NOSPPC, 0, NOSPPC, 0, SAMEAS16)),
-        /* Other unallocated instructions...                            */
-        DECODE_END
-};
-static const union decode_item t32_table_1111_1011_0[] = {
-        /* Multiply, multiply accumulate, and absolute difference       */
-        /* ???                  1111 1011 0000 xxxx 1111 xxxx 0001 xxxx */
-        DECODE_REJECT   (0xfff0f0f0, 0xfb00f010),
-        /* ???                  1111 1011 0111 xxxx 1111 xxxx 0001 xxxx */
-        DECODE_REJECT   (0xfff0f0f0, 0xfb70f010),
-        /* SMULxy               1111 1011 0001 xxxx 1111 xxxx 00xx xxxx */
-        DECODE_OR       (0xfff0f0c0, 0xfb10f000),
-        /* MUL                  1111 1011 0000 xxxx 1111 xxxx 0000 xxxx */
-        /* SMUAD{X}             1111 1011 0010 xxxx 1111 xxxx 000x xxxx */
-        /* SMULWy               1111 1011 0011 xxxx 1111 xxxx 000x xxxx */
-        /* SMUSD{X}             1111 1011 0100 xxxx 1111 xxxx 000x xxxx */
-        /* SMMUL{R}             1111 1011 0101 xxxx 1111 xxxx 000x xxxx */
-        /* USAD8                1111 1011 0111 xxxx 1111 xxxx 0000 xxxx */
-        DECODE_EMULATEX (0xff80f0e0, 0xfb00f000, t32_emulate_rd8rn16rm0_rwflags,
-                                                 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
-        /* ???                  1111 1011 0111 xxxx xxxx xxxx 0001 xxxx */
-        DECODE_REJECT   (0xfff000f0, 0xfb700010),
-        /* SMLAxy               1111 1011 0001 xxxx xxxx xxxx 00xx xxxx */
-        DECODE_OR       (0xfff000c0, 0xfb100000),
-        /* MLA                  1111 1011 0000 xxxx xxxx xxxx 0000 xxxx */
-        /* MLS                  1111 1011 0000 xxxx xxxx xxxx 0001 xxxx */
-        /* SMLAD{X}             1111 1011 0010 xxxx xxxx xxxx 000x xxxx */
-        /* SMLAWy               1111 1011 0011 xxxx xxxx xxxx 000x xxxx */
-        /* SMLSD{X}             1111 1011 0100 xxxx xxxx xxxx 000x xxxx */
-        /* SMMLA{R}             1111 1011 0101 xxxx xxxx xxxx 000x xxxx */
-        /* SMMLS{R}             1111 1011 0110 xxxx xxxx xxxx 000x xxxx */
-        /* USADA8               1111 1011 0111 xxxx xxxx xxxx 0000 xxxx */
-        DECODE_EMULATEX (0xff8000c0, 0xfb000000, t32_emulate_rd8rn16rm0ra12_noflags,
-                                                 REGS(NOSPPC, NOSPPCX, NOSPPC, 0, NOSPPC)),
-        /* Other unallocated instructions...                            */
-        DECODE_END
-};
-static const union decode_item t32_table_1111_1011_1[] = {
-        /* Long multiply, long multiply accumulate, and divide          */
-        /* UMAAL                1111 1011 1110 xxxx xxxx xxxx 0110 xxxx */
-        DECODE_OR       (0xfff000f0, 0xfbe00060),
-        /* SMLALxy              1111 1011 1100 xxxx xxxx xxxx 10xx xxxx */
-        DECODE_OR       (0xfff000c0, 0xfbc00080),
-        /* SMLALD{X}            1111 1011 1100 xxxx xxxx xxxx 110x xxxx */
-        /* SMLSLD{X}            1111 1011 1101 xxxx xxxx xxxx 110x xxxx */
-        DECODE_OR       (0xffe000e0, 0xfbc000c0),
-        /* SMULL                1111 1011 1000 xxxx xxxx xxxx 0000 xxxx */
-        /* UMULL                1111 1011 1010 xxxx xxxx xxxx 0000 xxxx */
-        /* SMLAL                1111 1011 1100 xxxx xxxx xxxx 0000 xxxx */
-        /* UMLAL                1111 1011 1110 xxxx xxxx xxxx 0000 xxxx */
-        DECODE_EMULATEX (0xff9000f0, 0xfb800000, t32_emulate_rdlo12rdhi8rn16rm0_noflags,
-                                                 REGS(NOSPPC, NOSPPC, NOSPPC, 0, NOSPPC)),
-        /* SDIV                 1111 1011 1001 xxxx xxxx xxxx 1111 xxxx */
-        /* UDIV                 1111 1011 1011 xxxx xxxx xxxx 1111 xxxx */
-        /* Other unallocated instructions...                            */
-        DECODE_END
-};
-const union decode_item kprobe_decode_thumb32_table[] = {
-        /*
-         * Load/store multiple instructions
-         *                      1110 100x x0xx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx),
-        /*
-         * Load/store dual, load/store exclusive, table branch
-         *                      1110 100x x1xx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx),
-        /*
-         * Data-processing (shifted register)
-         *                      1110 101x xxxx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xfe000000, 0xea000000, t32_table_1110_101x),
-        /*
-         * Coprocessor instructions
-         *                      1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_REJECT   (0xfc000000, 0xec000000),
-        /*
-         * Data-processing (modified immediate)
-         *                      1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xfa008000, 0xf0000000, t32_table_1111_0x0x___0),
-        /*
-         * Data-processing (plain binary immediate)
-         *                      1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xfa008000, 0xf2000000, t32_table_1111_0x1x___0),
-        /*
-         * Branches and miscellaneous control
-         *                      1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1),
-        /*
-         * Advanced SIMD element or structure load/store instructions
-         *                      1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_REJECT   (0xff100000, 0xf9000000),
-        /*
-         * Memory hints
-         *                      1111 100x x0x1 xxxx 1111 xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xfe50f000, 0xf810f000, t32_table_1111_100x_x0x1__1111),
-        /*
-         * Store single data item
-         *                      1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx
-         * Load single data items
-         *                      1111 100x xxx1 xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xfe000000, 0xf8000000, t32_table_1111_100x),
-        /*
-         * Data-processing (register)
-         *                      1111 1010 xxxx xxxx 1111 xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xff00f000, 0xfa00f000, t32_table_1111_1010___1111),
-        /*
-         * Multiply, multiply accumulate, and absolute difference
-         *                      1111 1011 0xxx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xff800000, 0xfb000000, t32_table_1111_1011_0),
-        /*
-         * Long multiply, long multiply accumulate, and divide
-         *                      1111 1011 1xxx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xff800000, 0xfb800000, t32_table_1111_1011_1),
-        /*
-         * Coprocessor instructions
-         *                      1111 11xx xxxx xxxx xxxx xxxx xxxx xxxx
-         */
-        DECODE_END
-};
-#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
-EXPORT_SYMBOL_GPL(kprobe_decode_thumb32_table);
-#endif
 static void __kprobes
-t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
+t16_simulate_bxblx(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc + 2;
-        unsigned long pc = thumb_probe_pc(p);
        int rm = (insn >> 3) & 0xf;
        unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
        if (insn & (1 << 7)) /* BLX ? */
-                regs->ARM_lr = (unsigned long)p->addr + 2;
+                regs->ARM_lr = regs->ARM_pc | 1;
        bx_write_pc(rmv, regs);
 }
 static void __kprobes
-t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
+t16_simulate_ldr_literal(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long *base = (unsigned long *)((regs->ARM_pc + 2) & ~3);
-        unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
        long index = insn & 0xff;
        int rt = (insn >> 8) & 0x7;
        regs->uregs[rt] = base[index];
 }
 static void __kprobes
-t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
+t16_simulate_ldrstr_sp_relative(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        unsigned long* base = (unsigned long *)regs->ARM_sp;
        long index = insn & 0xff;
        int rt = (insn >> 8) & 0x7;
@@ -986,20 +342,20 @@ t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs)
+t16_simulate_reladr(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        unsigned long base = (insn & 0x800) ? regs->ARM_sp
-                                            : (thumb_probe_pc(p) & ~3);
+                                            : ((regs->ARM_pc + 2) & ~3);
        long offset = insn & 0xff;
        int rt = (insn >> 8) & 0x7;
        regs->uregs[rt] = base + offset * 4;
 }
 static void __kprobes
-t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
+t16_simulate_add_sp_imm(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        long imm = insn & 0x7f;
        if (insn & 0x80) /* SUB */
                regs->ARM_sp -= imm * 4;
@@ -1008,21 +364,22 @@ t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs)
+t16_simulate_cbz(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
        int rn = insn & 0x7;
-        kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
+        probes_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
        if (nonzero & 0x800) {
                long i = insn & 0x200;
                long imm5 = insn & 0xf8;
-                unsigned long pc = thumb_probe_pc(p);
+                unsigned long pc = regs->ARM_pc + 2;
                regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
        }
 }
 static void __kprobes
-t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
+t16_simulate_it(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
        /*
         * The 8 IT state bits are split into two parts in CPSR:
@@ -1030,7 +387,6 @@ t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
         *      ITSTATE<7:2> are in CPSR<15:10>
         * The new IT state is in the lower byte of insn.
         */
-        kprobe_opcode_t insn = p->opcode;
        unsigned long cpsr = regs->ARM_cpsr;
        cpsr &= ~PSR_IT_MASK;
        cpsr |= (insn & 0xfc) << 8;
@@ -1039,50 +395,54 @@ t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t16_singlestep_it(struct kprobe *p, struct pt_regs *regs)
+t16_singlestep_it(probes_opcode_t insn,
+                  struct arch_probes_insn *asi, struct pt_regs *regs)
 {
        regs->ARM_pc += 2;
-        t16_simulate_it(p, regs);
+        t16_simulate_it(insn, asi, regs);
 }
-static enum kprobe_insn __kprobes
+static enum probes_insn __kprobes
-t16_decode_it(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+t16_decode_it(probes_opcode_t insn, struct arch_probes_insn *asi,
+                const struct decode_header *d)
 {
        asi->insn_singlestep = t16_singlestep_it;
        return INSN_GOOD_NO_SLOT;
 }
 static void __kprobes
-t16_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
+t16_simulate_cond_branch(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc + 2;
-        unsigned long pc = thumb_probe_pc(p);
        long offset = insn & 0x7f;
        offset -= insn & 0x80; /* Apply sign bit */
        regs->ARM_pc = pc + (offset * 2);
 }
-static enum kprobe_insn __kprobes
+static enum probes_insn __kprobes
-t16_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+t16_decode_cond_branch(probes_opcode_t insn, struct arch_probes_insn *asi,
+                const struct decode_header *d)
 {
        int cc = (insn >> 8) & 0xf;
-        asi->insn_check_cc = kprobe_condition_checks[cc];
+        asi->insn_check_cc = probes_condition_checks[cc];
        asi->insn_handler = t16_simulate_cond_branch;
        return INSN_GOOD_NO_SLOT;
 }
 static void __kprobes
-t16_simulate_branch(struct kprobe *p, struct pt_regs *regs)
+t16_simulate_branch(probes_opcode_t insn,
+                   struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc + 2;
-        unsigned long pc = thumb_probe_pc(p);
        long offset = insn & 0x3ff;
        offset -= insn & 0x400; /* Apply sign bit */
        regs->ARM_pc = pc + (offset * 2);
 }
 static unsigned long __kprobes
-t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
+t16_emulate_loregs(probes_opcode_t insn,
+                   struct arch_probes_insn *asi, struct pt_regs *regs)
 {
        unsigned long oldcpsr = regs->ARM_cpsr;
        unsigned long newcpsr;
@@ -1095,7 +455,7 @@ t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
                "mrs    %[newcpsr], cpsr        \n\t"
                : [newcpsr] "=r" (newcpsr)
                : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
-                  [fn] "r" (p->ainsn.insn_fn)
+                  [fn] "r" (asi->insn_fn)
                : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
                  "lr", "memory", "cc"
                );
@@ -1104,24 +464,26 @@ t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
 }
 static void __kprobes
-t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs)
+t16_emulate_loregs_rwflags(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        regs->ARM_cpsr = t16_emulate_loregs(p, regs);
+        regs->ARM_cpsr = t16_emulate_loregs(insn, asi, regs);
 }
 static void __kprobes
-t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs)
+t16_emulate_loregs_noitrwflags(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        unsigned long cpsr = t16_emulate_loregs(p, regs);
+        unsigned long cpsr = t16_emulate_loregs(insn, asi, regs);
        if (!in_it_block(cpsr))
                regs->ARM_cpsr = cpsr;
 }
 static void __kprobes
-t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
+t16_emulate_hiregs(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
-        kprobe_opcode_t insn = p->opcode;
+        unsigned long pc = regs->ARM_pc + 2;
-        unsigned long pc = thumb_probe_pc(p);
        int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
        int rm = (insn >> 3) & 0xf;
@@ -1137,7 +499,7 @@ t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
                "blx    %[fn]                   \n\t"
                "mrs    %[cpsr], cpsr           \n\t"
                : "=r" (rdnv), [cpsr] "=r" (cpsr)
-                : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
+                : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (asi->insn_fn)
                : "lr", "memory", "cc"
        );
@@ -1148,18 +510,20 @@ t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
        regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
 }
-static enum kprobe_insn __kprobes
+static enum probes_insn __kprobes
-t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+t16_decode_hiregs(probes_opcode_t insn, struct arch_probes_insn *asi,
+                const struct decode_header *d)
 {
        insn &= ~0x00ff;
        insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
-        ((u16 *)asi->insn)[0] = insn;
+        ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn);
        asi->insn_handler = t16_emulate_hiregs;
        return INSN_GOOD;
 }
 static void __kprobes
-t16_emulate_push(struct kprobe *p, struct pt_regs *regs)
+t16_emulate_push(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
        __asm__ __volatile__ (
                "ldr    r9, [%[regs], #13*4]    \n\t"
@@ -1168,28 +532,32 @@ t16_emulate_push(struct kprobe *p, struct pt_regs *regs)
                "blx    %[fn]                   \n\t"
                "str    r9, [%[regs], #13*4]    \n\t"
                :
-                : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
+                : [regs] "r" (regs), [fn] "r" (asi->insn_fn)
                : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
                  "lr", "memory", "cc"
                );
 }
-static enum kprobe_insn __kprobes
+static enum probes_insn __kprobes
-t16_decode_push(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+t16_decode_push(probes_opcode_t insn, struct arch_probes_insn *asi,
+                const struct decode_header *d)
 {
        /*
         * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}"
         * and call it with R9=SP and LR in the register list represented
         * by R8.
         */
-        ((u16 *)asi->insn)[0] = 0xe929;         /* 1st half STMDB R9!,{} */
+        /* 1st half STMDB R9!,{} */
-        ((u16 *)asi->insn)[1] = insn & 0x1ff;   /* 2nd half (register list) */
+        ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe929);
+        /* 2nd half (register list) */
+        ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff);
        asi->insn_handler = t16_emulate_push;
        return INSN_GOOD;
 }
 static void __kprobes
-t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs)
+t16_emulate_pop_nopc(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
        __asm__ __volatile__ (
                "ldr    r9, [%[regs], #13*4]    \n\t"
@@ -1198,14 +566,15 @@ t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs)
                "stmia  %[regs], {r0-r7}        \n\t"
                "str    r9, [%[regs], #13*4]    \n\t"
                :
-                : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
+                : [regs] "r" (regs), [fn] "r" (asi->insn_fn)
                : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
                  "lr", "memory", "cc"
                );
 }
 static void __kprobes
-t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
+t16_emulate_pop_pc(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
 {
        register unsigned long pc asm("r8");
@@ -1216,7 +585,7 @@ t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
                "stmia  %[regs], {r0-r7}        \n\t"
                "str    r9, [%[regs], #13*4]    \n\t"
                : "=r" (pc)
-                : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
+                : [regs] "r" (regs), [fn] "r" (asi->insn_fn)
                : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
                  "lr", "memory", "cc"
                );
@@ -1224,246 +593,74 @@ t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
        bx_write_pc(pc, regs);
 }
-static enum kprobe_insn __kprobes
+static enum probes_insn __kprobes
-t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi)
+t16_decode_pop(probes_opcode_t insn, struct arch_probes_insn *asi,
+                const struct decode_header *d)
 {
        /*
         * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}"
         * and call it with R9=SP and PC in the register list represented
         * by R8.
         */
-        ((u16 *)asi->insn)[0] = 0xe8b9;         /* 1st half LDMIA R9!,{} */
+        /* 1st half LDMIA R9!,{} */
-        ((u16 *)asi->insn)[1] = insn & 0x1ff;   /* 2nd half (register list) */
+        ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe8b9);
+        /* 2nd half (register list) */
+        ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff);
        asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc
                                         : t16_emulate_pop_nopc;
        return INSN_GOOD;
 }
-static const union decode_item t16_table_1011[] = {
+const union decode_action kprobes_t16_actions[NUM_PROBES_T16_ACTIONS] = {
-        /* Miscellaneous 16-bit instructions                */
+        [PROBES_T16_ADD_SP] = {.handler = t16_simulate_add_sp_imm},
+        [PROBES_T16_CBZ] = {.handler = t16_simulate_cbz},
-        /* ADD (SP plus immediate)      1011 0000 0xxx xxxx */
+        [PROBES_T16_SIGN_EXTEND] = {.handler = t16_emulate_loregs_rwflags},
-        /* SUB (SP minus immediate)     1011 0000 1xxx xxxx */
+        [PROBES_T16_PUSH] = {.decoder = t16_decode_push},
-        DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm),
+        [PROBES_T16_POP] = {.decoder = t16_decode_pop},
+        [PROBES_T16_SEV] = {.handler = probes_emulate_none},
-        /* CBZ                          1011 00x1 xxxx xxxx */
+        [PROBES_T16_WFE] = {.handler = probes_simulate_nop},
-        /* CBNZ                         1011 10x1 xxxx xxxx */
+        [PROBES_T16_IT] = {.decoder = t16_decode_it},
-        DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz),
+        [PROBES_T16_CMP] = {.handler = t16_emulate_loregs_rwflags},
+        [PROBES_T16_ADDSUB] = {.handler = t16_emulate_loregs_noitrwflags},
-        /* SXTH                         1011 0010 00xx xxxx */
+        [PROBES_T16_LOGICAL] = {.handler = t16_emulate_loregs_noitrwflags},
-        /* SXTB                         1011 0010 01xx xxxx */
+        [PROBES_T16_LDR_LIT] = {.handler = t16_simulate_ldr_literal},
-        /* UXTH                         1011 0010 10xx xxxx */
+        [PROBES_T16_BLX] = {.handler = t16_simulate_bxblx},
-        /* UXTB                         1011 0010 11xx xxxx */
+        [PROBES_T16_HIREGOPS] = {.decoder = t16_decode_hiregs},
-        /* REV                          1011 1010 00xx xxxx */
+        [PROBES_T16_LDRHSTRH] = {.handler = t16_emulate_loregs_rwflags},
-        /* REV16                        1011 1010 01xx xxxx */
+        [PROBES_T16_LDRSTR] = {.handler = t16_simulate_ldrstr_sp_relative},
-        /* ???                          1011 1010 10xx xxxx */
+        [PROBES_T16_ADR] = {.handler = t16_simulate_reladr},
-        /* REVSH                        1011 1010 11xx xxxx */
+        [PROBES_T16_LDMSTM] = {.handler = t16_emulate_loregs_rwflags},
-        DECODE_REJECT   (0xffc0, 0xba80),
+        [PROBES_T16_BRANCH_COND] = {.decoder = t16_decode_cond_branch},
-        DECODE_EMULATE  (0xf500, 0xb000, t16_emulate_loregs_rwflags),
+        [PROBES_T16_BRANCH] = {.handler = t16_simulate_branch},
-        /* PUSH                         1011 010x xxxx xxxx */
-        DECODE_CUSTOM   (0xfe00, 0xb400, t16_decode_push),
-        /* POP                          1011 110x xxxx xxxx */
-        DECODE_CUSTOM   (0xfe00, 0xbc00, t16_decode_pop),
-        /*
-         * If-Then, and hints
-         *                              1011 1111 xxxx xxxx
-         */
-        /* YIELD                        1011 1111 0001 0000 */
-        DECODE_OR       (0xffff, 0xbf10),
-        /* SEV                          1011 1111 0100 0000 */
-        DECODE_EMULATE  (0xffff, 0xbf40, kprobe_emulate_none),
-        /* NOP                          1011 1111 0000 0000 */
-        /* WFE                          1011 1111 0010 0000 */
-        /* WFI                          1011 1111 0011 0000 */
-        DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop),
-        /* Unassigned hints             1011 1111 xxxx 0000 */
-        DECODE_REJECT   (0xff0f, 0xbf00),
-        /* IT                           1011 1111 xxxx xxxx */
-        DECODE_CUSTOM   (0xff00, 0xbf00, t16_decode_it),
-        /* SETEND                       1011 0110 010x xxxx */
-        /* CPS                          1011 0110 011x xxxx */
-        /* BKPT                         1011 1110 xxxx xxxx */
-        /* And unallocated instructions...                  */
-        DECODE_END
 };
-const union decode_item kprobe_decode_thumb16_table[] = {
+const union decode_action kprobes_t32_actions[NUM_PROBES_T32_ACTIONS] = {
+        [PROBES_T32_LDMSTM] = {.decoder = t32_decode_ldmstm},
-        /*
+        [PROBES_T32_LDRDSTRD] = {.handler = t32_emulate_ldrdstrd},
-         * Shift (immediate), add, subtract, move, and compare
+        [PROBES_T32_TABLE_BRANCH] = {.handler = t32_simulate_table_branch},
-         *                              00xx xxxx xxxx xxxx
+        [PROBES_T32_TST] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
-         */
+        [PROBES_T32_MOV] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
+        [PROBES_T32_ADDSUB] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
-        /* CMP (immediate)              0010 1xxx xxxx xxxx */
+        [PROBES_T32_LOGICAL] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
-        DECODE_EMULATE  (0xf800, 0x2800, t16_emulate_loregs_rwflags),
+        [PROBES_T32_CMP] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
+        [PROBES_T32_ADDWSUBW_PC] = {.handler = t32_emulate_rd8pc16_noflags,},
-        /* ADD (register)               0001 100x xxxx xxxx */
+        [PROBES_T32_ADDWSUBW] = {.handler = t32_emulate_rd8rn16_noflags},
-        /* SUB (register)               0001 101x xxxx xxxx */
+        [PROBES_T32_MOVW] = {.handler = t32_emulate_rd8rn16_noflags},
-        /* LSL (immediate)              0000 0xxx xxxx xxxx */
+        [PROBES_T32_SAT] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
-        /* LSR (immediate)              0000 1xxx xxxx xxxx */
+        [PROBES_T32_BITFIELD] = {.handler = t32_emulate_rd8rn16_noflags},
-        /* ASR (immediate)              0001 0xxx xxxx xxxx */
+        [PROBES_T32_SEV] = {.handler = probes_emulate_none},
-        /* ADD (immediate, Thumb)       0001 110x xxxx xxxx */
+        [PROBES_T32_WFE] = {.handler = probes_simulate_nop},
-        /* SUB (immediate, Thumb)       0001 111x xxxx xxxx */
+        [PROBES_T32_MRS] = {.handler = t32_simulate_mrs},
-        /* MOV (immediate)              0010 0xxx xxxx xxxx */
+        [PROBES_T32_BRANCH_COND] = {.decoder = t32_decode_cond_branch},
-        /* ADD (immediate, Thumb)       0011 0xxx xxxx xxxx */
+        [PROBES_T32_BRANCH] = {.handler = t32_simulate_branch},
-        /* SUB (immediate, Thumb)       0011 1xxx xxxx xxxx */
+        [PROBES_T32_PLDI] = {.handler = probes_simulate_nop},
-        DECODE_EMULATE  (0xc000, 0x0000, t16_emulate_loregs_noitrwflags),
+        [PROBES_T32_LDR_LIT] = {.handler = t32_simulate_ldr_literal},
+        [PROBES_T32_LDRSTR] = {.handler = t32_emulate_ldrstr},
-        /*
+        [PROBES_T32_SIGN_EXTEND] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
-         * 16-bit Thumb data-processing instructions
+        [PROBES_T32_MEDIA] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
-         *                              0100 00xx xxxx xxxx
+        [PROBES_T32_REVERSE] = {.handler = t32_emulate_rd8rn16_noflags},
-         */
+        [PROBES_T32_MUL_ADD] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
+        [PROBES_T32_MUL_ADD2] = {.handler = t32_emulate_rd8rn16rm0ra12_noflags},
-        /* TST (register)               0100 0010 00xx xxxx */
+        [PROBES_T32_MUL_ADD_LONG] = {
-        DECODE_EMULATE  (0xffc0, 0x4200, t16_emulate_loregs_rwflags),
+                .handler = t32_emulate_rdlo12rdhi8rn16rm0_noflags},
-        /* CMP (register)               0100 0010 10xx xxxx */
-        /* CMN (register)               0100 0010 11xx xxxx */
-        DECODE_EMULATE  (0xff80, 0x4280, t16_emulate_loregs_rwflags),
-        /* AND (register)               0100 0000 00xx xxxx */
-        /* EOR (register)               0100 0000 01xx xxxx */
-        /* LSL (register)               0100 0000 10xx xxxx */
-        /* LSR (register)               0100 0000 11xx xxxx */
-        /* ASR (register)               0100 0001 00xx xxxx */
-        /* ADC (register)               0100 0001 01xx xxxx */
-        /* SBC (register)               0100 0001 10xx xxxx */
-        /* ROR (register)               0100 0001 11xx xxxx */
-        /* RSB (immediate)              0100 0010 01xx xxxx */
-        /* ORR (register)               0100 0011 00xx xxxx */
-        /* MUL                          0100 0011 00xx xxxx */
-        /* BIC (register)               0100 0011 10xx xxxx */
-        /* MVN (register)               0100 0011 10xx xxxx */
-        DECODE_EMULATE  (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),
-        /*
-         * Special data instructions and branch and exchange
-         *                              0100 01xx xxxx xxxx
-         */
-        /* BLX pc                       0100 0111 1111 1xxx */
-        DECODE_REJECT   (0xfff8, 0x47f8),
-        /* BX (register)                0100 0111 0xxx xxxx */
-        /* BLX (register)               0100 0111 1xxx xxxx */
-        DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),
-        /* ADD pc, pc                   0100 0100 1111 1111 */
-        DECODE_REJECT   (0xffff, 0x44ff),
-        /* ADD (register)               0100 0100 xxxx xxxx */
-        /* CMP (register)               0100 0101 xxxx xxxx */
-        /* MOV (register)               0100 0110 xxxx xxxx */
-        DECODE_CUSTOM   (0xfc00, 0x4400, t16_decode_hiregs),
-        /*
-         * Load from Literal Pool
-         * LDR (literal)                0100 1xxx xxxx xxxx
-         */
-        DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal),
-        /*
-         * 16-bit Thumb Load/store instructions
-         *                              0101 xxxx xxxx xxxx
-         *                              011x xxxx xxxx xxxx
-         *                              100x xxxx xxxx xxxx
-         */
-        /* STR (register)               0101 000x xxxx xxxx */
-        /* STRH (register)              0101 001x xxxx xxxx */
-        /* STRB (register)              0101 010x xxxx xxxx */
-        /* LDRSB (register)             0101 011x xxxx xxxx */
-        /* LDR (register)               0101 100x xxxx xxxx */
-        /* LDRH (register)              0101 101x xxxx xxxx */
-        /* LDRB (register)              0101 110x xxxx xxxx */
-        /* LDRSH (register)             0101 111x xxxx xxxx */
-        /* STR (immediate, Thumb)       0110 0xxx xxxx xxxx */
-        /* LDR (immediate, Thumb)       0110 1xxx xxxx xxxx */
-        /* STRB (immediate, Thumb)      0111 0xxx xxxx xxxx */
-        /* LDRB (immediate, Thumb)      0111 1xxx xxxx xxxx */
-        DECODE_EMULATE  (0xc000, 0x4000, t16_emulate_loregs_rwflags),
-        /* STRH (immediate, Thumb)      1000 0xxx xxxx xxxx */
-        /* LDRH (immediate, Thumb)      1000 1xxx xxxx xxxx */
-        DECODE_EMULATE  (0xf000, 0x8000, t16_emulate_loregs_rwflags),
-        /* STR (immediate, Thumb)       1001 0xxx xxxx xxxx */
-        /* LDR (immediate, Thumb)       1001 1xxx xxxx xxxx */
-        DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),
-        /*
-         * Generate PC-/SP-relative address
-         * ADR (literal)                1010 0xxx xxxx xxxx
-         * ADD (SP plus immediate)      1010 1xxx xxxx xxxx
-         */
-        DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr),
-        /*
-         * Miscellaneous 16-bit instructions
-         *                              1011 xxxx xxxx xxxx
-         */
-        DECODE_TABLE    (0xf000, 0xb000, t16_table_1011),
-        /* STM                          1100 0xxx xxxx xxxx */
-        /* LDM                          1100 1xxx xxxx xxxx */
-        DECODE_EMULATE  (0xf000, 0xc000, t16_emulate_loregs_rwflags),
-        /*
-         * Conditional branch, and Supervisor Call
-         */
-        /* Permanently UNDEFINED        1101 1110 xxxx xxxx */
-        /* SVC                          1101 1111 xxxx xxxx */
-        DECODE_REJECT   (0xfe00, 0xde00),
-        /* Conditional branch           1101 xxxx xxxx xxxx */
-        DECODE_CUSTOM   (0xf000, 0xd000, t16_decode_cond_branch),
-        /*
-         * Unconditional branch
-         * B                            1110 0xxx xxxx xxxx
-         */
-        DECODE_SIMULATE (0xf800, 0xe000, t16_simulate_branch),
-        DECODE_END
 };
-#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
-EXPORT_SYMBOL_GPL(kprobe_decode_thumb16_table);
-#endif
-static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
-{
-        if (unlikely(in_it_block(cpsr)))
-                return kprobe_condition_checks[current_cond(cpsr)](cpsr);
-        return true;
-}
-static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs)
-{
-        regs->ARM_pc += 2;
-        p->ainsn.insn_handler(p, regs);
-        regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
-}
-static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs)
-{
-        regs->ARM_pc += 4;
-        p->ainsn.insn_handler(p, regs);
-        regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
-}
-enum kprobe_insn __kprobes
-thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
-{
-        asi->insn_singlestep = thumb16_singlestep;
-        asi->insn_check_cc = thumb_check_cc;
-        return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
-}
-enum kprobe_insn __kprobes
-thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
-{
-        asi->insn_singlestep = thumb32_singlestep;
-        asi->insn_check_cc = thumb_check_cc;
-        return kprobe_decode_insn(insn, asi, kprobe_decode_thumb32_table, true);
-}
diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
index a7b621ece23d..6d644202c8dc 100644
--- a/arch/arm/kernel/kprobes.c
+++ b/arch/arm/kernel/kprobes.c
@@ -26,9 +26,14 @@
 #include <linux/stop_machine.h>
 #include <linux/stringify.h>
 #include <asm/traps.h>
+#include <asm/opcodes.h>
 #include <asm/cacheflush.h>
+#include <linux/percpu.h>
+#include <linux/bug.h>
 #include "kprobes.h"
+#include "probes-arm.h"
+#include "probes-thumb.h"
 #include "patch.h"
 #define MIN_STACK_SIZE(addr)                            \
@@ -54,6 +59,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
        unsigned long addr = (unsigned long)p->addr;
        bool thumb;
        kprobe_decode_insn_t *decode_insn;
+        const union decode_action *actions;
        int is;
        if (in_exception_text(addr))
@@ -62,25 +68,29 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
 #ifdef CONFIG_THUMB2_KERNEL
        thumb = true;
        addr &= ~1; /* Bit 0 would normally be set to indicate Thumb code */
-        insn = ((u16 *)addr)[0];
+        insn = __mem_to_opcode_thumb16(((u16 *)addr)[0]);
        if (is_wide_instruction(insn)) {
-                insn <<= 16;
+                u16 inst2 = __mem_to_opcode_thumb16(((u16 *)addr)[1]);
-                insn |= ((u16 *)addr)[1];
+                insn = __opcode_thumb32_compose(insn, inst2);
-                decode_insn = thumb32_kprobe_decode_insn;
+                decode_insn = thumb32_probes_decode_insn;
-        } else
+                actions = kprobes_t32_actions;
-                decode_insn = thumb16_kprobe_decode_insn;
+        } else {
+                decode_insn = thumb16_probes_decode_insn;
+                actions = kprobes_t16_actions;
+        }
 #else /* !CONFIG_THUMB2_KERNEL */
        thumb = false;
        if (addr & 0x3)
                return -EINVAL;
-        insn = *p->addr;
+        insn = __mem_to_opcode_arm(*p->addr);
-        decode_insn = arm_kprobe_decode_insn;
+        decode_insn = arm_probes_decode_insn;
+        actions = kprobes_arm_actions;
 #endif
        p->opcode = insn;
        p->ainsn.insn = tmp_insn;
-        switch ((*decode_insn)(insn, &p->ainsn)) {
+        switch ((*decode_insn)(insn, &p->ainsn, true, actions)) {
        case INSN_REJECTED:     /* not supported */
                return -EINVAL;
@@ -92,7 +102,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
                        p->ainsn.insn[is] = tmp_insn[is];
                flush_insns(p->ainsn.insn,
                                sizeof(p->ainsn.insn[0]) * MAX_INSN_SIZE);
-                p->ainsn.insn_fn = (kprobe_insn_fn_t *)
+                p->ainsn.insn_fn = (probes_insn_fn_t *)
                                        ((uintptr_t)p->ainsn.insn | thumb);
                break;
@@ -197,7 +207,7 @@ singlestep_skip(struct kprobe *p, struct pt_regs *regs)
 static inline void __kprobes
 singlestep(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb)
 {
-        p->ainsn.insn_singlestep(p, regs);
+        p->ainsn.insn_singlestep(p->opcode, &p->ainsn, regs);
 }
 /*
@@ -607,7 +617,7 @@ static struct undef_hook kprobes_arm_break_hook = {
 int __init arch_init_kprobes()
 {
-        arm_kprobe_decode_init();
+        arm_probes_decode_init();
 #ifdef CONFIG_THUMB2_KERNEL
        register_undef_hook(&kprobes_thumb16_break_hook);
        register_undef_hook(&kprobes_thumb32_break_hook);
diff --git a/arch/arm/kernel/kprobes.h b/arch/arm/kernel/kprobes.h
index 38945f78f9f1..9a2712ecefc3 100644
--- a/arch/arm/kernel/kprobes.h
+++ b/arch/arm/kernel/kprobes.h
@@ -19,6 +19,8 @@
 #ifndef _ARM_KERNEL_KPROBES_H
 #define _ARM_KERNEL_KPROBES_H
+#include "probes.h"
 /*
 * These undefined instructions must be unique and
 * reserved solely for kprobes' use.
@@ -27,402 +29,24 @@
 #define KPROBE_THUMB16_BREAKPOINT_INSTRUCTION   0xde18
 #define KPROBE_THUMB32_BREAKPOINT_INSTRUCTION   0xf7f0a018
+enum probes_insn __kprobes
+kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_probes_insn *asi,
+                const struct decode_header *h);
-enum kprobe_insn {
+typedef enum probes_insn (kprobe_decode_insn_t)(probes_opcode_t,
-        INSN_REJECTED,
+                                                struct arch_probes_insn *,
-        INSN_GOOD,
+                                                bool,
-        INSN_GOOD_NO_SLOT
+                                                const union decode_action *);
-};
-typedef enum kprobe_insn (kprobe_decode_insn_t)(kprobe_opcode_t,
-                                                struct arch_specific_insn *);
 #ifdef CONFIG_THUMB2_KERNEL
-enum kprobe_insn thumb16_kprobe_decode_insn(kprobe_opcode_t,
+extern const union decode_action kprobes_t32_actions[];
-                                                struct arch_specific_insn *);
+extern const union decode_action kprobes_t16_actions[];
-enum kprobe_insn thumb32_kprobe_decode_insn(kprobe_opcode_t,
-                                                struct arch_specific_insn *);
 #else /* !CONFIG_THUMB2_KERNEL */
-enum kprobe_insn arm_kprobe_decode_insn(kprobe_opcode_t,
+extern const union decode_action kprobes_arm_actions[];
-                                        struct arch_specific_insn *);
-#endif
-void __init arm_kprobe_decode_init(void);
-extern kprobe_check_cc * const kprobe_condition_checks[16];
-#if __LINUX_ARM_ARCH__ >= 7
-/* str_pc_offset is architecturally defined from ARMv7 onwards */
-#define str_pc_offset 8
-#define find_str_pc_offset()
-#else /* __LINUX_ARM_ARCH__ < 7 */
-/* We need a run-time check to determine str_pc_offset */
-extern int str_pc_offset;
-void __init find_str_pc_offset(void);
 #endif
-/*
- * Update ITSTATE after normal execution of an IT block instruction.
- *
- * The 8 IT state bits are split into two parts in CPSR:
- *      ITSTATE<1:0> are in CPSR<26:25>
- *      ITSTATE<7:2> are in CPSR<15:10>
- */
-static inline unsigned long it_advance(unsigned long cpsr)
-        {
-        if ((cpsr & 0x06000400) == 0) {
-                /* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */
-                cpsr &= ~PSR_IT_MASK;
-        } else {
-                /* We need to shift left ITSTATE<4:0> */
-                const unsigned long mask = 0x06001c00;  /* Mask ITSTATE<4:0> */
-                unsigned long it = cpsr & mask;
-                it <<= 1;
-                it |= it >> (27 - 10);  /* Carry ITSTATE<2> to correct place */
-                it &= mask;
-                cpsr &= ~mask;
-                cpsr |= it;
-        }
-        return cpsr;
-}
-static inline void __kprobes bx_write_pc(long pcv, struct pt_regs *regs)
-{
-        long cpsr = regs->ARM_cpsr;
-        if (pcv & 0x1) {
-                cpsr |= PSR_T_BIT;
-                pcv &= ~0x1;
-        } else {
-                cpsr &= ~PSR_T_BIT;
-                pcv &= ~0x2;    /* Avoid UNPREDICTABLE address allignment */
-        }
-        regs->ARM_cpsr = cpsr;
-        regs->ARM_pc = pcv;
-}
-#if __LINUX_ARM_ARCH__ >= 6
-/* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */
-#define load_write_pc_interworks true
-#define test_load_write_pc_interworking()
-#else /* __LINUX_ARM_ARCH__ < 6 */
-/* We need run-time testing to determine if load_write_pc() should interwork. */
-extern bool load_write_pc_interworks;
-void __init test_load_write_pc_interworking(void);
-#endif
-static inline void __kprobes load_write_pc(long pcv, struct pt_regs *regs)
-{
-        if (load_write_pc_interworks)
-                bx_write_pc(pcv, regs);
-        else
-                regs->ARM_pc = pcv;
-}
-#if __LINUX_ARM_ARCH__ >= 7
-#define alu_write_pc_interworks true
-#define test_alu_write_pc_interworking()
-#elif __LINUX_ARM_ARCH__ <= 5
-/* Kernels built for <= ARMv5 should never run on >= ARMv6 hardware, so... */
-#define alu_write_pc_interworks false
-#define test_alu_write_pc_interworking()
-#else /* __LINUX_ARM_ARCH__ == 6 */
-/* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */
-extern bool alu_write_pc_interworks;
-void __init test_alu_write_pc_interworking(void);
-#endif /* __LINUX_ARM_ARCH__ == 6 */
-static inline void __kprobes alu_write_pc(long pcv, struct pt_regs *regs)
-{
-        if (alu_write_pc_interworks)
-                bx_write_pc(pcv, regs);
-        else
-                regs->ARM_pc = pcv;
-}
-void __kprobes kprobe_simulate_nop(struct kprobe *p, struct pt_regs *regs);
-void __kprobes kprobe_emulate_none(struct kprobe *p, struct pt_regs *regs);
-enum kprobe_insn __kprobes
-kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi);
-/*
- * Test if load/store instructions writeback the address register.
- * if P (bit 24) == 0 or W (bit 21) == 1
- */
-#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
-/*
- * The following definitions and macros are used to build instruction
- * decoding tables for use by kprobe_decode_insn.
- *
- * These tables are a concatenation of entries each of which consist of one of
- * the decode_* structs. All of the fields in every type of decode structure
- * are of the union type decode_item, therefore the entire decode table can be
- * viewed as an array of these and declared like:
- *
- *      static const union decode_item table_name[] = {};
- *
- * In order to construct each entry in the table, macros are used to
- * initialise a number of sequential decode_item values in a layout which
- * matches the relevant struct. E.g. DECODE_SIMULATE initialise a struct
- * decode_simulate by initialising four decode_item objects like this...
- *
- *      {.bits = _type},
- *      {.bits = _mask},
- *      {.bits = _value},
- *      {.handler = _handler},
- *
- * Initialising a specified member of the union means that the compiler
- * will produce a warning if the argument is of an incorrect type.
- *
- * Below is a list of each of the macros used to initialise entries and a
- * description of the action performed when that entry is matched to an
- * instruction. A match is found when (instruction & mask) == value.
- *
- * DECODE_TABLE(mask, value, table)
- *      Instruction decoding jumps to parsing the new sub-table 'table'.
- *
- * DECODE_CUSTOM(mask, value, decoder)
- *      The custom function 'decoder' is called to the complete decoding
- *      of an instruction.
- *
- * DECODE_SIMULATE(mask, value, handler)
- *      Set the probes instruction handler to 'handler', this will be used
- *      to simulate the instruction when the probe is hit. Decoding returns
- *      with INSN_GOOD_NO_SLOT.
- *
- * DECODE_EMULATE(mask, value, handler)
- *      Set the probes instruction handler to 'handler', this will be used
- *      to emulate the instruction when the probe is hit. The modified
- *      instruction (see below) is placed in the probes instruction slot so it
- *      may be called by the emulation code. Decoding returns with INSN_GOOD.
- *
- * DECODE_REJECT(mask, value)
- *      Instruction decoding fails with INSN_REJECTED
- *
- * DECODE_OR(mask, value)
- *      This allows the mask/value test of multiple table entries to be
- *      logically ORed. Once an 'or' entry is matched the decoding action to
- *      be performed is that of the next entry which isn't an 'or'. E.g.
- *
- *              DECODE_OR       (mask1, value1)
- *              DECODE_OR       (mask2, value2)
- *              DECODE_SIMULATE (mask3, value3, simulation_handler)
- *
- *      This means that if any of the three mask/value pairs match the
- *      instruction being decoded, then 'simulation_handler' will be used
- *      for it.
- *
- * Both the SIMULATE and EMULATE macros have a second form which take an
- * additional 'regs' argument.
- *
- *      DECODE_SIMULATEX(mask, value, handler, regs)
- *      DECODE_EMULATEX (mask, value, handler, regs)
- *
- * These are used to specify what kind of CPU register is encoded in each of the
- * least significant 5 nibbles of the instruction being decoded. The regs value
- * is specified using the REGS macro, this takes any of the REG_TYPE_* values
- * from enum decode_reg_type as arguments; only the '*' part of the name is
- * given. E.g.
- *
- *      REGS(0, ANY, NOPC, 0, ANY)
- *
- * This indicates an instruction is encoded like:
- *
- *      bits 19..16     ignore
- *      bits 15..12     any register allowed here
- *      bits 11.. 8     any register except PC allowed here
- *      bits  7.. 4     ignore
- *      bits  3.. 0     any register allowed here
- *
- * This register specification is checked after a decode table entry is found to
- * match an instruction (through the mask/value test). Any invalid register then
- * found in the instruction will cause decoding to fail with INSN_REJECTED. In
- * the above example this would happen if bits 11..8 of the instruction were
- * 1111, indicating R15 or PC.
- *
- * As well as checking for legal combinations of registers, this data is also
- * used to modify the registers encoded in the instructions so that an
- * emulation routines can use it. (See decode_regs() and INSN_NEW_BITS.)
- *
- * Here is a real example which matches ARM instructions of the form
- * "AND <Rd>,<Rn>,<Rm>,<shift> <Rs>"
- *
- *      DECODE_EMULATEX (0x0e000090, 0x00000010, emulate_rd12rn16rm0rs8_rwflags,
- *                                               REGS(ANY, ANY, NOPC, 0, ANY)),
- *                                                    ^    ^    ^        ^
- *                                                    Rn   Rd   Rs       Rm
- *
- * Decoding the instruction "AND R4, R5, R6, ASL R15" will be rejected because
- * Rs == R15
- *
- * Decoding the instruction "AND R4, R5, R6, ASL R7" will be accepted and the
- * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into
- * the kprobes instruction slot. This can then be called later by the handler
- * function emulate_rd12rn16rm0rs8_rwflags in order to simulate the instruction.
- */
-enum decode_type {
-        DECODE_TYPE_END,
-        DECODE_TYPE_TABLE,
-        DECODE_TYPE_CUSTOM,
-        DECODE_TYPE_SIMULATE,
-        DECODE_TYPE_EMULATE,
-        DECODE_TYPE_OR,
-        DECODE_TYPE_REJECT,
-        NUM_DECODE_TYPES /* Must be last enum */
-};
-#define DECODE_TYPE_BITS        4
-#define DECODE_TYPE_MASK        ((1 << DECODE_TYPE_BITS) - 1)
-enum decode_reg_type {
-        REG_TYPE_NONE = 0, /* Not a register, ignore */
-        REG_TYPE_ANY,      /* Any register allowed */
-        REG_TYPE_SAMEAS16, /* Register should be same as that at bits 19..16 */
-        REG_TYPE_SP,       /* Register must be SP */
-        REG_TYPE_PC,       /* Register must be PC */
-        REG_TYPE_NOSP,     /* Register must not be SP */
-        REG_TYPE_NOSPPC,   /* Register must not be SP or PC */
-        REG_TYPE_NOPC,     /* Register must not be PC */
-        REG_TYPE_NOPCWB,   /* No PC if load/store write-back flag also set */
-        /* The following types are used when the encoding for PC indicates
-         * another instruction form. This distiction only matters for test
-         * case coverage checks.
-         */
-        REG_TYPE_NOPCX,    /* Register must not be PC */
-        REG_TYPE_NOSPPCX,  /* Register must not be SP or PC */
-        /* Alias to allow '0' arg to be used in REGS macro. */
-        REG_TYPE_0 = REG_TYPE_NONE
-};
-#define REGS(r16, r12, r8, r4, r0)      \
-        ((REG_TYPE_##r16) << 16) +      \
-        ((REG_TYPE_##r12) << 12) +      \
-        ((REG_TYPE_##r8) << 8) +        \
-        ((REG_TYPE_##r4) << 4) +        \
-        (REG_TYPE_##r0)
-union decode_item {
-        u32                     bits;
-        const union decode_item *table;
-        kprobe_insn_handler_t   *handler;
-        kprobe_decode_insn_t    *decoder;
-};
-#define DECODE_END                      \
-        {.bits = DECODE_TYPE_END}
-struct decode_header {
-        union decode_item       type_regs;
-        union decode_item       mask;
-        union decode_item       value;
-};
-#define DECODE_HEADER(_type, _mask, _value, _regs)              \
-        {.bits = (_type) | ((_regs) << DECODE_TYPE_BITS)},      \
-        {.bits = (_mask)},                                      \
-        {.bits = (_value)}
-struct decode_table {
-        struct decode_header    header;
-        union decode_item       table;
-};
-#define DECODE_TABLE(_mask, _value, _table)                     \
-        DECODE_HEADER(DECODE_TYPE_TABLE, _mask, _value, 0),     \
-        {.table = (_table)}
-struct decode_custom {
-        struct decode_header    header;
-        union decode_item       decoder;
-};
-#define DECODE_CUSTOM(_mask, _value, _decoder)                  \
-        DECODE_HEADER(DECODE_TYPE_CUSTOM, _mask, _value, 0),    \
-        {.decoder = (_decoder)}
-struct decode_simulate {
-        struct decode_header    header;
-        union decode_item       handler;
-};
-#define DECODE_SIMULATEX(_mask, _value, _handler, _regs)                \
-        DECODE_HEADER(DECODE_TYPE_SIMULATE, _mask, _value, _regs),      \
-        {.handler = (_handler)}
-#define DECODE_SIMULATE(_mask, _value, _handler)        \
-        DECODE_SIMULATEX(_mask, _value, _handler, 0)
-struct decode_emulate {
-        struct decode_header    header;
-        union decode_item       handler;
-};
-#define DECODE_EMULATEX(_mask, _value, _handler, _regs)                 \
-        DECODE_HEADER(DECODE_TYPE_EMULATE, _mask, _value, _regs),       \
-        {.handler = (_handler)}
-#define DECODE_EMULATE(_mask, _value, _handler)         \
-        DECODE_EMULATEX(_mask, _value, _handler, 0)
-struct decode_or {
-        struct decode_header    header;
-};
-#define DECODE_OR(_mask, _value)                                \
-        DECODE_HEADER(DECODE_TYPE_OR, _mask, _value, 0)
-struct decode_reject {
-        struct decode_header    header;
-};
-#define DECODE_REJECT(_mask, _value)                            \
-        DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0)
-#ifdef CONFIG_THUMB2_KERNEL
-extern const union decode_item kprobe_decode_thumb16_table[];
-extern const union decode_item kprobe_decode_thumb32_table[];
-#else
-extern const union decode_item kprobe_decode_arm_table[];
-#endif
-int kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
-                        const union decode_item *table, bool thumb16);
 #endif /* _ARM_KERNEL_KPROBES_H */
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 789d846a9184..a6bc431cde70 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -16,6 +16,8 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/uaccess.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
 #include <asm/irq_regs.h>
 #include <asm/pmu.h>
@@ -205,6 +207,8 @@ armpmu_del(struct perf_event *event, int flags)
        armpmu_stop(event, PERF_EF_UPDATE);
        hw_events->events[idx] = NULL;
        clear_bit(idx, hw_events->used_mask);
+        if (armpmu->clear_event_idx)
+                armpmu->clear_event_idx(hw_events, event);
        perf_event_update_userpage(event);
 }
@@ -295,14 +299,27 @@ validate_group(struct perf_event *event)
 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 {
-        struct arm_pmu *armpmu = (struct arm_pmu *) dev;
+        struct arm_pmu *armpmu;
-        struct platform_device *plat_device = armpmu->plat_device;
+        struct platform_device *plat_device;
-        struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
+        struct arm_pmu_platdata *plat;
+        int ret;
+        u64 start_clock, finish_clock;
+        if (irq_is_percpu(irq))
+                dev = *(void **)dev;
+        armpmu = dev;
+        plat_device = armpmu->plat_device;
+        plat = dev_get_platdata(&plat_device->dev);
+        start_clock = sched_clock();
        if (plat && plat->handle_irq)
-                return plat->handle_irq(irq, dev, armpmu->handle_irq);
+                ret = plat->handle_irq(irq, dev, armpmu->handle_irq);
        else
-                return armpmu->handle_irq(irq, dev);
+                ret = armpmu->handle_irq(irq, dev);
+        finish_clock = sched_clock();
+        perf_sample_event_took(finish_clock - start_clock);
+        return ret;
 }
 static void
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 20d553c9f5e2..51798d7854ac 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -25,6 +25,8 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
 #include <asm/cputype.h>
 #include <asm/irq_regs.h>
@@ -33,6 +35,7 @@
 /* Set at runtime when we know what CPU type we are. */
 static struct arm_pmu *cpu_pmu;
+static DEFINE_PER_CPU(struct arm_pmu *, percpu_pmu);
 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
@@ -71,6 +74,26 @@ static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
        return this_cpu_ptr(&cpu_hw_events);
 }
+static void cpu_pmu_enable_percpu_irq(void *data)
+{
+        struct arm_pmu *cpu_pmu = data;
+        struct platform_device *pmu_device = cpu_pmu->plat_device;
+        int irq = platform_get_irq(pmu_device, 0);
+        enable_percpu_irq(irq, IRQ_TYPE_NONE);
+        cpumask_set_cpu(smp_processor_id(), &cpu_pmu->active_irqs);
+}
+static void cpu_pmu_disable_percpu_irq(void *data)
+{
+        struct arm_pmu *cpu_pmu = data;
+        struct platform_device *pmu_device = cpu_pmu->plat_device;
+        int irq = platform_get_irq(pmu_device, 0);
+        cpumask_clear_cpu(smp_processor_id(), &cpu_pmu->active_irqs);
+        disable_percpu_irq(irq);
+}
 static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
 {
        int i, irq, irqs;
@@ -78,12 +101,18 @@ static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
        irqs = min(pmu_device->num_resources, num_possible_cpus());
-        for (i = 0; i < irqs; ++i) {
+        irq = platform_get_irq(pmu_device, 0);
-                if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
+        if (irq >= 0 && irq_is_percpu(irq)) {
-                        continue;
+                on_each_cpu(cpu_pmu_disable_percpu_irq, cpu_pmu, 1);
-                irq = platform_get_irq(pmu_device, i);
+                free_percpu_irq(irq, &percpu_pmu);
-                if (irq >= 0)
+        } else {
-                        free_irq(irq, cpu_pmu);
+                for (i = 0; i < irqs; ++i) {
+                        if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
+                                continue;
+                        irq = platform_get_irq(pmu_device, i);
+                        if (irq >= 0)
+                                free_irq(irq, cpu_pmu);
+                }
        }
 }
@@ -101,33 +130,44 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
                return -ENODEV;
        }
-        for (i = 0; i < irqs; ++i) {
+        irq = platform_get_irq(pmu_device, 0);
-                err = 0;
+        if (irq >= 0 && irq_is_percpu(irq)) {
-                irq = platform_get_irq(pmu_device, i);
+                err = request_percpu_irq(irq, handler, "arm-pmu", &percpu_pmu);
-                if (irq < 0)
-                        continue;
-                /*
-                 * If we have a single PMU interrupt that we can't shift,
-                 * assume that we're running on a uniprocessor machine and
-                 * continue. Otherwise, continue without this interrupt.
-                 */
-                if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
-                        pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
-                                    irq, i);
-                        continue;
-                }
-                err = request_irq(irq, handler,
-                                  IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
-                                  cpu_pmu);
                if (err) {
                        pr_err("unable to request IRQ%d for ARM PMU counters\n",
                                irq);
                        return err;
                }
+                on_each_cpu(cpu_pmu_enable_percpu_irq, cpu_pmu, 1);
-                cpumask_set_cpu(i, &cpu_pmu->active_irqs);
+        } else {
+                for (i = 0; i < irqs; ++i) {
+                        err = 0;
+                        irq = platform_get_irq(pmu_device, i);
+                        if (irq < 0)
+                                continue;
+                        /*
+                         * If we have a single PMU interrupt that we can't shift,
+                         * assume that we're running on a uniprocessor machine and
+                         * continue. Otherwise, continue without this interrupt.
+                         */
+                        if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+                                pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+                                            irq, i);
+                                continue;
+                        }
+                        err = request_irq(irq, handler,
+                                          IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
+                                          cpu_pmu);
+                        if (err) {
+                                pr_err("unable to request IRQ%d for ARM PMU counters\n",
+                                        irq);
+                                return err;
+                        }
+                        cpumask_set_cpu(i, &cpu_pmu->active_irqs);
+                }
        }
        return 0;
@@ -141,6 +181,7 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
                events->events = per_cpu(hw_events, cpu);
                events->used_mask = per_cpu(used_mask, cpu);
                raw_spin_lock_init(&events->pmu_lock);
+                per_cpu(percpu_pmu, cpu) = cpu_pmu;
        }
        cpu_pmu->get_hw_events  = cpu_pmu_get_cpu_events;
@@ -181,6 +222,7 @@ static struct notifier_block cpu_pmu_hotplug_notifier = {
 */
 static struct of_device_id cpu_pmu_of_device_ids[] = {
        {.compatible = "arm,cortex-a15-pmu",    .data = armv7_a15_pmu_init},
+        {.compatible = "arm,cortex-a12-pmu",    .data = armv7_a12_pmu_init},
        {.compatible = "arm,cortex-a9-pmu",     .data = armv7_a9_pmu_init},
        {.compatible = "arm,cortex-a8-pmu",     .data = armv7_a8_pmu_init},
        {.compatible = "arm,cortex-a7-pmu",     .data = armv7_a7_pmu_init},
@@ -188,6 +230,7 @@ static struct of_device_id cpu_pmu_of_device_ids[] = {
        {.compatible = "arm,arm11mpcore-pmu",   .data = armv6mpcore_pmu_init},
        {.compatible = "arm,arm1176-pmu",       .data = armv6pmu_init},
        {.compatible = "arm,arm1136-pmu",       .data = armv6pmu_init},
+        {.compatible = "qcom,krait-pmu",        .data = krait_pmu_init},
        {},
 };
@@ -225,15 +268,6 @@ static int probe_current_pmu(struct arm_pmu *pmu)
                case ARM_CPU_PART_CORTEX_A9:
                        ret = armv7_a9_pmu_init(pmu);
                        break;
-                case ARM_CPU_PART_CORTEX_A5:
-                        ret = armv7_a5_pmu_init(pmu);
-                        break;
-                case ARM_CPU_PART_CORTEX_A15:
-                        ret = armv7_a15_pmu_init(pmu);
-                        break;
-                case ARM_CPU_PART_CORTEX_A7:
-                        ret = armv7_a7_pmu_init(pmu);
-                        break;
                }
        /* Intel CPUs [xscale]. */
        } else if (implementor == ARM_CPU_IMP_INTEL) {
@@ -270,6 +304,9 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
                return -ENOMEM;
        }
+        cpu_pmu = pmu;
+        cpu_pmu->plat_device = pdev;
        if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
                init_fn = of_id->data;
                ret = init_fn(pmu);
@@ -282,8 +319,6 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
                goto out_free;
        }
-        cpu_pmu = pmu;
-        cpu_pmu->plat_device = pdev;
        cpu_pmu_init(cpu_pmu);
        ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 039cffb053a7..f4ef3981ed02 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -18,6 +18,10 @@
 #ifdef CONFIG_CPU_V7
+#include <asm/cp15.h>
+#include <asm/vfp.h>
+#include "../vfp/vfpinstr.h"
 /*
 * Common ARMv7 event types
 *
@@ -109,6 +113,33 @@ enum armv7_a15_perf_types {
        ARMV7_A15_PERFCTR_PC_WRITE_SPEC                 = 0x76,
 };
+/* ARMv7 Cortex-A12 specific event types */
+enum armv7_a12_perf_types {
+        ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ         = 0x40,
+        ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE        = 0x41,
+        ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ          = 0x50,
+        ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE         = 0x51,
+        ARMV7_A12_PERFCTR_PC_WRITE_SPEC                 = 0x76,
+        ARMV7_A12_PERFCTR_PF_TLB_REFILL                 = 0xe7,
+};
+/* ARMv7 Krait specific event types */
+enum krait_perf_types {
+        KRAIT_PMRESR0_GROUP0                            = 0xcc,
+        KRAIT_PMRESR1_GROUP0                            = 0xd0,
+        KRAIT_PMRESR2_GROUP0                            = 0xd4,
+        KRAIT_VPMRESR0_GROUP0                           = 0xd8,
+        KRAIT_PERFCTR_L1_ICACHE_ACCESS                  = 0x10011,
+        KRAIT_PERFCTR_L1_ICACHE_MISS                    = 0x10010,
+        KRAIT_PERFCTR_L1_ITLB_ACCESS                    = 0x12222,
+        KRAIT_PERFCTR_L1_DTLB_ACCESS                    = 0x12210,
+};
 /*
 * Cortex-A8 HW events mapping
 *
@@ -732,6 +763,262 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 };
 /*
+ * Cortex-A12 HW events mapping
+ */
+static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_A12_PERFCTR_PC_WRITE_SPEC,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = ARMV7_PERFCTR_BUS_CYCLES,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
+};
+static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                /*
+                 * Not all performance counters differentiate between read
+                 * and write accesses/misses so we're not always strictly
+                 * correct, but it's the best we can do. Writes and reads get
+                 * combined in these cases.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_A12_PERFCTR_PF_TLB_REFILL,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(NODE)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+/*
+ * Krait HW events mapping
+ */
+static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = KRAIT_PERFCTR_L1_ICACHE_ACCESS,
+                        [C(RESULT_MISS)]        = KRAIT_PERFCTR_L1_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = KRAIT_PERFCTR_L1_DTLB_ACCESS,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = KRAIT_PERFCTR_L1_DTLB_ACCESS,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = KRAIT_PERFCTR_L1_ITLB_ACCESS,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = KRAIT_PERFCTR_L1_ITLB_ACCESS,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(NODE)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+/*
 * Perf Events' indices
 */
 #define ARMV7_IDX_CYCLE_COUNTER 0
@@ -1212,6 +1499,24 @@ static int armv7_a7_map_event(struct perf_event *event)
                                &armv7_a7_perf_cache_map, 0xFF);
 }
+static int armv7_a12_map_event(struct perf_event *event)
+{
+        return armpmu_map_event(event, &armv7_a12_perf_map,
+                                &armv7_a12_perf_cache_map, 0xFF);
+}
+static int krait_map_event(struct perf_event *event)
+{
+        return armpmu_map_event(event, &krait_perf_map,
+                                &krait_perf_cache_map, 0xFFFFF);
+}
+static int krait_map_event_no_branch(struct perf_event *event)
+{
+        return armpmu_map_event(event, &krait_perf_map_no_branch,
+                                &krait_perf_cache_map, 0xFFFFF);
+}
 static void armv7pmu_init(struct arm_pmu *cpu_pmu)
 {
        cpu_pmu->handle_irq     = armv7pmu_handle_irq;
@@ -1283,6 +1588,408 @@ static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
        cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
        return 0;
 }
+static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
+{
+        armv7pmu_init(cpu_pmu);
+        cpu_pmu->name           = "ARMv7 Cortex-A12";
+        cpu_pmu->map_event      = armv7_a12_map_event;
+        cpu_pmu->num_events     = armv7_read_num_pmnc_events();
+        cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
+        return 0;
+}
+/*
+ * Krait Performance Monitor Region Event Selection Register (PMRESRn)
+ *
+ *            31   30     24     16     8      0
+ *            +--------------------------------+
+ *  PMRESR0   | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 0
+ *            +--------------------------------+
+ *  PMRESR1   | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 1
+ *            +--------------------------------+
+ *  PMRESR2   | EN |  CC  |  CC  |  CC  |  CC  |   N = 1, R = 2
+ *            +--------------------------------+
+ *  VPMRESR0  | EN |  CC  |  CC  |  CC  |  CC  |   N = 2, R = ?
+ *            +--------------------------------+
+ *              EN | G=3  | G=2  | G=1  | G=0
+ *
+ *  Event Encoding:
+ *
+ *      hwc->config_base = 0xNRCCG
+ *
+ *      N  = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR)
+ *      R  = region register
+ *      CC = class of events the group G is choosing from
+ *      G  = group or particular event
+ *
+ *  Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2
+ *
+ *  A region (R) corresponds to a piece of the CPU (execution unit, instruction
+ *  unit, etc.) while the event code (CC) corresponds to a particular class of
+ *  events (interrupts for example). An event code is broken down into
+ *  groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for
+ *  example).
+ */
+#define KRAIT_EVENT             (1 << 16)
+#define VENUM_EVENT             (2 << 16)
+#define KRAIT_EVENT_MASK        (KRAIT_EVENT | VENUM_EVENT)
+#define PMRESRn_EN              BIT(31)
+static u32 krait_read_pmresrn(int n)
+{
+        u32 val;
+        switch (n) {
+        case 0:
+                asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val));
+                break;
+        case 1:
+                asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val));
+                break;
+        case 2:
+                asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val));
+                break;
+        default:
+                BUG(); /* Should be validated in krait_pmu_get_event_idx() */
+        }
+        return val;
+}
+static void krait_write_pmresrn(int n, u32 val)
+{
+        switch (n) {
+        case 0:
+                asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val));
+                break;
+        case 1:
+                asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val));
+                break;
+        case 2:
+                asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val));
+                break;
+        default:
+                BUG(); /* Should be validated in krait_pmu_get_event_idx() */
+        }
+}
+static u32 krait_read_vpmresr0(void)
+{
+        u32 val;
+        asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val));
+        return val;
+}
+static void krait_write_vpmresr0(u32 val)
+{
+        asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val));
+}
+static void krait_pre_vpmresr0(u32 *venum_orig_val, u32 *fp_orig_val)
+{
+        u32 venum_new_val;
+        u32 fp_new_val;
+        BUG_ON(preemptible());
+        /* CPACR Enable CP10 and CP11 access */
+        *venum_orig_val = get_copro_access();
+        venum_new_val = *venum_orig_val | CPACC_SVC(10) | CPACC_SVC(11);
+        set_copro_access(venum_new_val);
+        /* Enable FPEXC */
+        *fp_orig_val = fmrx(FPEXC);
+        fp_new_val = *fp_orig_val | FPEXC_EN;
+        fmxr(FPEXC, fp_new_val);
+}
+static void krait_post_vpmresr0(u32 venum_orig_val, u32 fp_orig_val)
+{
+        BUG_ON(preemptible());
+        /* Restore FPEXC */
+        fmxr(FPEXC, fp_orig_val);
+        isb();
+        /* Restore CPACR */
+        set_copro_access(venum_orig_val);
+}
+static u32 krait_get_pmresrn_event(unsigned int region)
+{
+        static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0,
+                                             KRAIT_PMRESR1_GROUP0,
+                                             KRAIT_PMRESR2_GROUP0 };
+        return pmresrn_table[region];
+}
+static void krait_evt_setup(int idx, u32 config_base)
+{
+        u32 val;
+        u32 mask;
+        u32 vval, fval;
+        unsigned int region;
+        unsigned int group;
+        unsigned int code;
+        unsigned int group_shift;
+        bool venum_event;
+        venum_event = !!(config_base & VENUM_EVENT);
+        region = (config_base >> 12) & 0xf;
+        code   = (config_base >> 4) & 0xff;
+        group  = (config_base >> 0)  & 0xf;
+        group_shift = group * 8;
+        mask = 0xff << group_shift;
+        /* Configure evtsel for the region and group */
+        if (venum_event)
+                val = KRAIT_VPMRESR0_GROUP0;
+        else
+                val = krait_get_pmresrn_event(region);
+        val += group;
+        /* Mix in mode-exclusion bits */
+        val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1);
+        armv7_pmnc_write_evtsel(idx, val);
+        asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
+        if (venum_event) {
+                krait_pre_vpmresr0(&vval, &fval);
+                val = krait_read_vpmresr0();
+                val &= ~mask;
+                val |= code << group_shift;
+                val |= PMRESRn_EN;
+                krait_write_vpmresr0(val);
+                krait_post_vpmresr0(vval, fval);
+        } else {
+                val = krait_read_pmresrn(region);
+                val &= ~mask;
+                val |= code << group_shift;
+                val |= PMRESRn_EN;
+                krait_write_pmresrn(region, val);
+        }
+}
+static u32 krait_clear_pmresrn_group(u32 val, int group)
+{
+        u32 mask;
+        int group_shift;
+        group_shift = group * 8;
+        mask = 0xff << group_shift;
+        val &= ~mask;
+        /* Don't clear enable bit if entire region isn't disabled */
+        if (val & ~PMRESRn_EN)
+                return val |= PMRESRn_EN;
+        return 0;
+}
+static void krait_clearpmu(u32 config_base)
+{
+        u32 val;
+        u32 vval, fval;
+        unsigned int region;
+        unsigned int group;
+        bool venum_event;
+        venum_event = !!(config_base & VENUM_EVENT);
+        region = (config_base >> 12) & 0xf;
+        group  = (config_base >> 0)  & 0xf;
+        if (venum_event) {
+                krait_pre_vpmresr0(&vval, &fval);
+                val = krait_read_vpmresr0();
+                val = krait_clear_pmresrn_group(val, group);
+                krait_write_vpmresr0(val);
+                krait_post_vpmresr0(vval, fval);
+        } else {
+                val = krait_read_pmresrn(region);
+                val = krait_clear_pmresrn_group(val, group);
+                krait_write_pmresrn(region, val);
+        }
+}
+static void krait_pmu_disable_event(struct perf_event *event)
+{
+        unsigned long flags;
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        /* Disable counter and interrupt */
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
+        /* Disable counter */
+        armv7_pmnc_disable_counter(idx);
+        /*
+         * Clear pmresr code (if destined for PMNx counters)
+         */
+        if (hwc->config_base & KRAIT_EVENT_MASK)
+                krait_clearpmu(hwc->config_base);
+        /* Disable interrupt for this counter */
+        armv7_pmnc_disable_intens(idx);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+}
+static void krait_pmu_enable_event(struct perf_event *event)
+{
+        unsigned long flags;
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+        struct pmu_hw_events *events = cpu_pmu->get_hw_events();
+        /*
+         * Enable counter and interrupt, and set the counter to count
+         * the event that we're interested in.
+         */
+        raw_spin_lock_irqsave(&events->pmu_lock, flags);
+        /* Disable counter */
+        armv7_pmnc_disable_counter(idx);
+        /*
+         * Set event (if destined for PMNx counters)
+         * We set the event for the cycle counter because we
+         * have the ability to perform event filtering.
+         */
+        if (hwc->config_base & KRAIT_EVENT_MASK)
+                krait_evt_setup(idx, hwc->config_base);
+        else
+                armv7_pmnc_write_evtsel(idx, hwc->config_base);
+        /* Enable interrupt for this counter */
+        armv7_pmnc_enable_intens(idx);
+        /* Enable counter */
+        armv7_pmnc_enable_counter(idx);
+        raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+}
+static void krait_pmu_reset(void *info)
+{
+        u32 vval, fval;
+        armv7pmu_reset(info);
+        /* Clear all pmresrs */
+        krait_write_pmresrn(0, 0);
+        krait_write_pmresrn(1, 0);
+        krait_write_pmresrn(2, 0);
+        krait_pre_vpmresr0(&vval, &fval);
+        krait_write_vpmresr0(0);
+        krait_post_vpmresr0(vval, fval);
+}
+static int krait_event_to_bit(struct perf_event *event, unsigned int region,
+                              unsigned int group)
+{
+        int bit;
+        struct hw_perf_event *hwc = &event->hw;
+        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
+        if (hwc->config_base & VENUM_EVENT)
+                bit = KRAIT_VPMRESR0_GROUP0;
+        else
+                bit = krait_get_pmresrn_event(region);
+        bit -= krait_get_pmresrn_event(0);
+        bit += group;
+        /*
+         * Lower bits are reserved for use by the counters (see
+         * armv7pmu_get_event_idx() for more info)
+         */
+        bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1;
+        return bit;
+}
+/*
+ * We check for column exclusion constraints here.
+ * Two events cant use the same group within a pmresr register.
+ */
+static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+                                   struct perf_event *event)
+{
+        int idx;
+        int bit;
+        unsigned int prefix;
+        unsigned int region;
+        unsigned int code;
+        unsigned int group;
+        bool krait_event;
+        struct hw_perf_event *hwc = &event->hw;
+        region = (hwc->config_base >> 12) & 0xf;
+        code   = (hwc->config_base >> 4) & 0xff;
+        group  = (hwc->config_base >> 0) & 0xf;
+        krait_event = !!(hwc->config_base & KRAIT_EVENT_MASK);
+        if (krait_event) {
+                /* Ignore invalid events */
+                if (group > 3 || region > 2)
+                        return -EINVAL;
+                prefix = hwc->config_base & KRAIT_EVENT_MASK;
+                if (prefix != KRAIT_EVENT && prefix != VENUM_EVENT)
+                        return -EINVAL;
+                if (prefix == VENUM_EVENT && (code & 0xe0))
+                        return -EINVAL;
+                bit = krait_event_to_bit(event, region, group);
+                if (test_and_set_bit(bit, cpuc->used_mask))
+                        return -EAGAIN;
+        }
+        idx = armv7pmu_get_event_idx(cpuc, event);
+        if (idx < 0 && krait_event)
+                clear_bit(bit, cpuc->used_mask);
+        return idx;
+}
+static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc,
+                                      struct perf_event *event)
+{
+        int bit;
+        struct hw_perf_event *hwc = &event->hw;
+        unsigned int region;
+        unsigned int group;
+        bool krait_event;
+        region = (hwc->config_base >> 12) & 0xf;
+        group  = (hwc->config_base >> 0) & 0xf;
+        krait_event = !!(hwc->config_base & KRAIT_EVENT_MASK);
+        if (krait_event) {
+                bit = krait_event_to_bit(event, region, group);
+                clear_bit(bit, cpuc->used_mask);
+        }
+}
+static int krait_pmu_init(struct arm_pmu *cpu_pmu)
+{
+        armv7pmu_init(cpu_pmu);
+        cpu_pmu->name           = "ARMv7 Krait";
+        /* Some early versions of Krait don't support PC write events */
+        if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node,
+                                  "qcom,no-pc-write"))
+                cpu_pmu->map_event = krait_map_event_no_branch;
+        else
+                cpu_pmu->map_event = krait_map_event;
+        cpu_pmu->num_events     = armv7_read_num_pmnc_events();
+        cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
+        cpu_pmu->reset          = krait_pmu_reset;
+        cpu_pmu->enable         = krait_pmu_enable_event;
+        cpu_pmu->disable        = krait_pmu_disable_event;
+        cpu_pmu->get_event_idx  = krait_pmu_get_event_idx;
+        cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx;
+        return 0;
+}
 #else
 static inline int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
 {
@@ -1308,4 +2015,14 @@ static inline int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
 {
        return -ENODEV;
 }
+static inline int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
+{
+        return -ENODEV;
+}
+static inline int krait_pmu_init(struct arm_pmu *cpu_pmu)
+{
+        return -ENODEV;
+}
 #endif  /* CONFIG_CPU_V7 */
diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
index 679cf4d18c08..fc7208636284 100644
--- a/arch/arm/kernel/pj4-cp0.c
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <asm/thread_notify.h>
+#include <asm/cputype.h>
 static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
 {
@@ -80,6 +81,9 @@ static int __init pj4_cp0_init(void)
 {
        u32 cp_access;
+        if (!cpu_is_pj4())
+                return 0;
        cp_access = pj4_cp_access_read() & ~0xf;
        pj4_cp_access_write(cp_access);
diff --git a/arch/arm/kernel/probes-arm.c b/arch/arm/kernel/probes-arm.c
new file mode 100644
index 000000000000..51a13a027989
--- /dev/null
+++ b/arch/arm/kernel/probes-arm.c
@@ -0,0 +1,734 @@
+/*
+ * arch/arm/kernel/probes-arm.c
+ *
+ * Some code moved here from arch/arm/kernel/kprobes-arm.c
+ *
+ * Copyright (C) 2006, 2007 Motorola Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/stddef.h>
+#include <linux/ptrace.h>
+#include "probes.h"
+#include "probes-arm.h"
+#define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
+#define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
+/*
+ * To avoid the complications of mimicing single-stepping on a
+ * processor without a Next-PC or a single-step mode, and to
+ * avoid having to deal with the side-effects of boosting, we
+ * simulate or emulate (almost) all ARM instructions.
+ *
+ * "Simulation" is where the instruction's behavior is duplicated in
+ * C code.  "Emulation" is where the original instruction is rewritten
+ * and executed, often by altering its registers.
+ *
+ * By having all behavior of the kprobe'd instruction completed before
+ * returning from the kprobe_handler(), all locks (scheduler and
+ * interrupt) can safely be released.  There is no need for secondary
+ * breakpoints, no race with MP or preemptable kernels, nor having to
+ * clean up resources counts at a later time impacting overall system
+ * performance.  By rewriting the instruction, only the minimum registers
+ * need to be loaded and saved back optimizing performance.
+ *
+ * Calling the insnslot_*_rwflags version of a function doesn't hurt
+ * anything even when the CPSR flags aren't updated by the
+ * instruction.  It's just a little slower in return for saving
+ * a little space by not having a duplicate function that doesn't
+ * update the flags.  (The same optimization can be said for
+ * instructions that do or don't perform register writeback)
+ * Also, instructions can either read the flags, only write the
+ * flags, or read and write the flags.  To save combinations
+ * rather than for sheer performance, flag functions just assume
+ * read and write of flags.
+ */
+void __kprobes simulate_bbl(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
+{
+        long iaddr = (long) regs->ARM_pc - 4;
+        int disp  = branch_displacement(insn);
+        if (insn & (1 << 24))
+                regs->ARM_lr = iaddr + 4;
+        regs->ARM_pc = iaddr + 8 + disp;
+}
+void __kprobes simulate_blx1(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
+{
+        long iaddr = (long) regs->ARM_pc - 4;
+        int disp = branch_displacement(insn);
+        regs->ARM_lr = iaddr + 4;
+        regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
+        regs->ARM_cpsr |= PSR_T_BIT;
+}
+void __kprobes simulate_blx2bx(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
+{
+        int rm = insn & 0xf;
+        long rmv = regs->uregs[rm];
+        if (insn & (1 << 5))
+                regs->ARM_lr = (long) regs->ARM_pc;
+        regs->ARM_pc = rmv & ~0x1;
+        regs->ARM_cpsr &= ~PSR_T_BIT;
+        if (rmv & 0x1)
+                regs->ARM_cpsr |= PSR_T_BIT;
+}
+void __kprobes simulate_mrs(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
+{
+        int rd = (insn >> 12) & 0xf;
+        unsigned long mask = 0xf8ff03df; /* Mask out execution state */
+        regs->uregs[rd] = regs->ARM_cpsr & mask;
+}
+void __kprobes simulate_mov_ipsp(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
+{
+        regs->uregs[12] = regs->uregs[13];
+}
+/*
+ * For the instruction masking and comparisons in all the "space_*"
+ * functions below, Do _not_ rearrange the order of tests unless
+ * you're very, very sure of what you are doing.  For the sake of
+ * efficiency, the masks for some tests sometimes assume other test
+ * have been done prior to them so the number of patterns to test
+ * for an instruction set can be as broad as possible to reduce the
+ * number of tests needed.
+ */
+static const union decode_item arm_1111_table[] = {
+        /* Unconditional instructions                                   */
+        /* memory hint          1111 0100 x001 xxxx xxxx xxxx xxxx xxxx */
+        /* PLDI (immediate)     1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */
+        /* PLDW (immediate)     1111 0101 x001 xxxx xxxx xxxx xxxx xxxx */
+        /* PLD (immediate)      1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_SIMULATE (0xfe300000, 0xf4100000, PROBES_PRELOAD_IMM),
+        /* memory hint          1111 0110 x001 xxxx xxxx xxxx xxx0 xxxx */
+        /* PLDI (register)      1111 0110 x101 xxxx xxxx xxxx xxx0 xxxx */
+        /* PLDW (register)      1111 0111 x001 xxxx xxxx xxxx xxx0 xxxx */
+        /* PLD (register)       1111 0111 x101 xxxx xxxx xxxx xxx0 xxxx */
+        DECODE_SIMULATE (0xfe300010, 0xf6100000, PROBES_PRELOAD_REG),
+        /* BLX (immediate)      1111 101x xxxx xxxx xxxx xxxx xxxx xxxx */
+        DECODE_SIMULATE (0xfe000000, 0xfa000000, PROBES_BRANCH_IMM),
+        /* CPS                  1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */
+        /* SETEND               1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
+        /* SRS                  1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
+        /* RFE                  1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
+        /* Coprocessor instructions... */
+        /* MCRR2                1111 1100 0100 xxxx xxxx xxxx xxxx xxxx */
+        /* MRRC2                1111 1100 0101 xxxx xxxx xxxx xxxx xxxx */
+        /* LDC2                 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
+        /* STC2                 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
+        /* CDP2                 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
+        /* MCR2                 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
+        /* MRC2                 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
+        /* Other unallocated instructions...                            */
+        DECODE_END
+};
+static const union decode_item arm_cccc_0001_0xx0____0xxx_table[] = {
+        /* Miscellaneous instructions                                   */
+        /* MRS cpsr             cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
+        DECODE_SIMULATEX(0x0ff000f0, 0x01000000, PROBES_MRS,
+                                                 REGS(0, NOPC, 0, 0, 0)),
+        /* BX                   cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
+        DECODE_SIMULATE (0x0ff000f0, 0x01200010, PROBES_BRANCH_REG),
+        /* BLX (register)       cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
+        DECODE_SIMULATEX(0x0ff000f0, 0x01200030, PROBES_BRANCH_REG,
+                                                 REGS(0, 0, 0, 0, NOPC)),
+        /* CLZ                  cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
+        DECODE_EMULATEX (0x0ff000f0, 0x01600010, PROBES_CLZ,
+                                                 REGS(0, NOPC, 0, 0, NOPC)),
+        /* QADD                 cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx */
+        /* QSUB                 cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx */
+        /* QDADD                cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx */
+        /* QDSUB                cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx */
+        DECODE_EMULATEX (0x0f9000f0, 0x01000050, PROBES_SATURATING_ARITHMETIC,
+                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
+        /* BXJ                  cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
+        /* MSR                  cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
+        /* MRS spsr             cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */
+        /* BKPT                 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
+        /* SMC                  cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */
+        /* And unallocated instructions...                              */
+        DECODE_END
+};
+static const union decode_item arm_cccc_0001_0xx0____1xx0_table[] = {
+        /* Halfword multiply and multiply-accumulate                    */
+        /* SMLALxy              cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
+        DECODE_EMULATEX (0x0ff00090, 0x01400080, PROBES_MUL1,
+                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
+        /* SMULWy               cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
+        DECODE_OR       (0x0ff000b0, 0x012000a0),
+        /* SMULxy               cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
+        DECODE_EMULATEX (0x0ff00090, 0x01600080, PROBES_MUL2,
+                                                 REGS(NOPC, 0, NOPC, 0, NOPC)),
+        /* SMLAxy               cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx */
+        DECODE_OR       (0x0ff00090, 0x01000080),
+        /* SMLAWy               cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx */
+        DECODE_EMULATEX (0x0ff000b0, 0x01200080, PROBES_MUL2,
+                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
+        DECODE_END
+};
+static const union decode_item arm_cccc_0000_____1001_table[] = {
+        /* Multiply and multiply-accumulate                             */
+        /* MUL                  cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx */
+        /* MULS                 cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx */
+        DECODE_EMULATEX (0x0fe000f0, 0x00000090, PROBES_MUL2,
+                                                 REGS(NOPC, 0, NOPC, 0, NOPC)),
+        /* MLA                  cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx */
+        /* MLAS                 cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx */
+        DECODE_OR       (0x0fe000f0, 0x00200090),
+        /* MLS                  cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx */
+        DECODE_EMULATEX (0x0ff000f0, 0x00600090, PROBES_MUL2,
+                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
+        /* UMAAL                cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx */
+        DECODE_OR       (0x0ff000f0, 0x00400090),
+        /* UMULL                cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx */
+        /* UMULLS               cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx */
+        /* UMLAL                cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx */
+        /* UMLALS               cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx */
+        /* SMULL                cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx */
+        /* SMULLS               cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx */
+        /* SMLAL                cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx */
+        /* SMLALS               cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx */
+        DECODE_EMULATEX (0x0f8000f0, 0x00800090, PROBES_MUL1,
+                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
+        DECODE_END
+};
+static const union decode_item arm_cccc_0001_____1001_table[] = {
+        /* Synchronization primitives                                   */
+#if __LINUX_ARM_ARCH__ < 6
+        /* Deprecated on ARMv6 and may be UNDEFINED on v7               */
+        /* SMP/SWPB             cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */
+        DECODE_EMULATEX (0x0fb000f0, 0x01000090, PROBES_SWP,
+                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
+#endif
+        /* LDREX/STREX{,D,B,H}  cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */
+        /* And unallocated instructions...                              */
+        DECODE_END
+};
+static const union decode_item arm_cccc_000x_____1xx1_table[] = {
+        /* Extra load/store instructions                                */
+        /* STRHT                cccc 0000 xx10 xxxx xxxx xxxx 1011 xxxx */
+        /* ???                  cccc 0000 xx10 xxxx xxxx xxxx 11x1 xxxx */
+        /* LDRHT                cccc 0000 xx11 xxxx xxxx xxxx 1011 xxxx */
+        /* LDRSBT               cccc 0000 xx11 xxxx xxxx xxxx 1101 xxxx */
+        /* LDRSHT               cccc 0000 xx11 xxxx xxxx xxxx 1111 xxxx */
+        DECODE_REJECT   (0x0f200090, 0x00200090),
+        /* LDRD/STRD lr,pc,{... cccc 000x x0x0 xxxx 111x xxxx 1101 xxxx */
+        DECODE_REJECT   (0x0e10e0d0, 0x0000e0d0),
+        /* LDRD (register)      cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx */
+        /* STRD (register)      cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx */
+        DECODE_EMULATEX (0x0e5000d0, 0x000000d0, PROBES_LDRSTRD,
+                                                 REGS(NOPCWB, NOPCX, 0, 0, NOPC)),
+        /* LDRD (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx */
+        /* STRD (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx */
+        DECODE_EMULATEX (0x0e5000d0, 0x004000d0, PROBES_LDRSTRD,
+                                                 REGS(NOPCWB, NOPCX, 0, 0, 0)),
+        /* STRH (register)      cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx */
+        DECODE_EMULATEX (0x0e5000f0, 0x000000b0, PROBES_STORE_EXTRA,
+                                                 REGS(NOPCWB, NOPC, 0, 0, NOPC)),
+        /* LDRH (register)      cccc 000x x0x1 xxxx xxxx xxxx 1011 xxxx */
+        /* LDRSB (register)     cccc 000x x0x1 xxxx xxxx xxxx 1101 xxxx */
+        /* LDRSH (register)     cccc 000x x0x1 xxxx xxxx xxxx 1111 xxxx */
+        DECODE_EMULATEX (0x0e500090, 0x00100090, PROBES_LOAD_EXTRA,
+                                                 REGS(NOPCWB, NOPC, 0, 0, NOPC)),
+        /* STRH (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1011 xxxx */
+        DECODE_EMULATEX (0x0e5000f0, 0x004000b0, PROBES_STORE_EXTRA,
+                                                 REGS(NOPCWB, NOPC, 0, 0, 0)),
+        /* LDRH (immediate)     cccc 000x x1x1 xxxx xxxx xxxx 1011 xxxx */
+        /* LDRSB (immediate)    cccc 000x x1x1 xxxx xxxx xxxx 1101 xxxx */
+        /* LDRSH (immediate)    cccc 000x x1x1 xxxx xxxx xxxx 1111 xxxx */
+        DECODE_EMULATEX (0x0e500090, 0x00500090, PROBES_LOAD_EXTRA,
+                                                 REGS(NOPCWB, NOPC, 0, 0, 0)),
+        DECODE_END
+};
+static const union decode_item arm_cccc_000x_table[] = {
+        /* Data-processing (register)                                   */
+        /* <op>S PC, ...        cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */
+        DECODE_REJECT   (0x0e10f000, 0x0010f000),
+        /* MOV IP, SP           1110 0001 1010 0000 1100 0000 0000 1101 */
+        DECODE_SIMULATE (0xffffffff, 0xe1a0c00d, PROBES_MOV_IP_SP),
+        /* TST (register)       cccc 0001 0001 xxxx xxxx xxxx xxx0 xxxx */
+        /* TEQ (register)       cccc 0001 0011 xxxx xxxx xxxx xxx0 xxxx */
+        /* CMP (register)       cccc 0001 0101 xxxx xxxx xxxx xxx0 xxxx */
+        /* CMN (register)       cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */
+        DECODE_EMULATEX (0x0f900010, 0x01100000, PROBES_DATA_PROCESSING_REG,
+                                                 REGS(ANY, 0, 0, 0, ANY)),
+        /* MOV (register)       cccc 0001 101x xxxx xxxx xxxx xxx0 xxxx */
+        /* MVN (register)       cccc 0001 111x xxxx xxxx xxxx xxx0 xxxx */
+        DECODE_EMULATEX (0x0fa00010, 0x01a00000, PROBES_DATA_PROCESSING_REG,
+                                                 REGS(0, ANY, 0, 0, ANY)),
+        /* AND (register)       cccc 0000 000x xxxx xxxx xxxx xxx0 xxxx */
+        /* EOR (register)       cccc 0000 001x xxxx xxxx xxxx xxx0 xxxx */
+        /* SUB (register)       cccc 0000 010x xxxx xxxx xxxx xxx0 xxxx */
+        /* RSB (register)       cccc 0000 011x xxxx xxxx xxxx xxx0 xxxx */
+        /* ADD (register)       cccc 0000 100x xxxx xxxx xxxx xxx0 xxxx */
+        /* ADC (register)       cccc 0000 101x xxxx xxxx xxxx xxx0 xxxx */
+        /* SBC (register)       cccc 0000 110x xxxx xxxx xxxx xxx0 xxxx */
+        /* RSC (register)       cccc 0000 111x xxxx xxxx xxxx xxx0 xxxx */
+        /* ORR (register)       cccc 0001 100x xxxx xxxx xxxx xxx0 xxxx */
+        /* BIC (register)       cccc 0001 110x xxxx xxxx xxxx xxx0 xxxx */
+        DECODE_EMULATEX (0x0e000010, 0x00000000, PROBES_DATA_PROCESSING_REG,
+                                                 REGS(ANY, ANY, 0, 0, ANY)),
+        /* TST (reg-shift reg)  cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */
+        /* TEQ (reg-shift reg)  cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */
+        /* CMP (reg-shift reg)  cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */
+        /* CMN (reg-shift reg)  cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
+        DECODE_EMULATEX (0x0f900090, 0x01100010, PROBES_DATA_PROCESSING_REG,
+                                                 REGS(ANY, 0, NOPC, 0, ANY)),
+        /* MOV (reg-shift reg)  cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */
+        /* MVN (reg-shift reg)  cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */
+        DECODE_EMULATEX (0x0fa00090, 0x01a00010, PROBES_DATA_PROCESSING_REG,
+                                                 REGS(0, ANY, NOPC, 0, ANY)),
+        /* AND (reg-shift reg)  cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */
+        /* EOR (reg-shift reg)  cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */
+        /* SUB (reg-shift reg)  cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */
+        /* RSB (reg-shift reg)  cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */
+        /* ADD (reg-shift reg)  cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */
+        /* ADC (reg-shift reg)  cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */
+        /* SBC (reg-shift reg)  cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */
+        /* RSC (reg-shift reg)  cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */
+        /* ORR (reg-shift reg)  cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */
+        /* BIC (reg-shift reg)  cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */
+        DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
+                                                 REGS(ANY, ANY, NOPC, 0, ANY)),
+        DECODE_END
+};
+static const union decode_item arm_cccc_001x_table[] = {
+        /* Data-processing (immediate)                                  */
+        /* MOVW                 cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */
+        /* MOVT                 cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0x0fb00000, 0x03000000, PROBES_DATA_PROCESSING_IMM,
+                                                 REGS(0, NOPC, 0, 0, 0)),
+        /* YIELD                cccc 0011 0010 0000 xxxx xxxx 0000 0001 */
+        DECODE_OR       (0x0fff00ff, 0x03200001),
+        /* SEV                  cccc 0011 0010 0000 xxxx xxxx 0000 0100 */
+        DECODE_EMULATE  (0x0fff00ff, 0x03200004, PROBES_EMULATE_NONE),
+        /* NOP                  cccc 0011 0010 0000 xxxx xxxx 0000 0000 */
+        /* WFE                  cccc 0011 0010 0000 xxxx xxxx 0000 0010 */
+        /* WFI                  cccc 0011 0010 0000 xxxx xxxx 0000 0011 */
+        DECODE_SIMULATE (0x0fff00fc, 0x03200000, PROBES_SIMULATE_NOP),
+        /* DBG                  cccc 0011 0010 0000 xxxx xxxx ffff xxxx */
+        /* unallocated hints    cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */
+        /* MSR (immediate)      cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0x0fb00000, 0x03200000),
+        /* <op>S PC, ...        cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */
+        DECODE_REJECT   (0x0e10f000, 0x0210f000),
+        /* TST (immediate)      cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx */
+        /* TEQ (immediate)      cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx */
+        /* CMP (immediate)      cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx */
+        /* CMN (immediate)      cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0x0f900000, 0x03100000, PROBES_DATA_PROCESSING_IMM,
+                                                 REGS(ANY, 0, 0, 0, 0)),
+        /* MOV (immediate)      cccc 0011 101x xxxx xxxx xxxx xxxx xxxx */
+        /* MVN (immediate)      cccc 0011 111x xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0x0fa00000, 0x03a00000, PROBES_DATA_PROCESSING_IMM,
+                                                 REGS(0, ANY, 0, 0, 0)),
+        /* AND (immediate)      cccc 0010 000x xxxx xxxx xxxx xxxx xxxx */
+        /* EOR (immediate)      cccc 0010 001x xxxx xxxx xxxx xxxx xxxx */
+        /* SUB (immediate)      cccc 0010 010x xxxx xxxx xxxx xxxx xxxx */
+        /* RSB (immediate)      cccc 0010 011x xxxx xxxx xxxx xxxx xxxx */
+        /* ADD (immediate)      cccc 0010 100x xxxx xxxx xxxx xxxx xxxx */
+        /* ADC (immediate)      cccc 0010 101x xxxx xxxx xxxx xxxx xxxx */
+        /* SBC (immediate)      cccc 0010 110x xxxx xxxx xxxx xxxx xxxx */
+        /* RSC (immediate)      cccc 0010 111x xxxx xxxx xxxx xxxx xxxx */
+        /* ORR (immediate)      cccc 0011 100x xxxx xxxx xxxx xxxx xxxx */
+        /* BIC (immediate)      cccc 0011 110x xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0x0e000000, 0x02000000, PROBES_DATA_PROCESSING_IMM,
+                                                 REGS(ANY, ANY, 0, 0, 0)),
+        DECODE_END
+};
+static const union decode_item arm_cccc_0110_____xxx1_table[] = {
+        /* Media instructions                                           */
+        /* SEL                  cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx */
+        DECODE_EMULATEX (0x0ff000f0, 0x068000b0, PROBES_SATURATE,
+                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
+        /* SSAT                 cccc 0110 101x xxxx xxxx xxxx xx01 xxxx */
+        /* USAT                 cccc 0110 111x xxxx xxxx xxxx xx01 xxxx */
+        DECODE_OR(0x0fa00030, 0x06a00010),
+        /* SSAT16               cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx */
+        /* USAT16               cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx */
+        DECODE_EMULATEX (0x0fb000f0, 0x06a00030, PROBES_SATURATE,
+                                                 REGS(0, NOPC, 0, 0, NOPC)),
+        /* REV                  cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
+        /* REV16                cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
+        /* RBIT                 cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */
+        /* REVSH                cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
+        DECODE_EMULATEX (0x0fb00070, 0x06b00030, PROBES_REV,
+                                                 REGS(0, NOPC, 0, 0, NOPC)),
+        /* ???                  cccc 0110 0x00 xxxx xxxx xxxx xxx1 xxxx */
+        DECODE_REJECT   (0x0fb00010, 0x06000010),
+        /* ???                  cccc 0110 0xxx xxxx xxxx xxxx 1011 xxxx */
+        DECODE_REJECT   (0x0f8000f0, 0x060000b0),
+        /* ???                  cccc 0110 0xxx xxxx xxxx xxxx 1101 xxxx */
+        DECODE_REJECT   (0x0f8000f0, 0x060000d0),
+        /* SADD16               cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx */
+        /* SADDSUBX             cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx */
+        /* SSUBADDX             cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx */
+        /* SSUB16               cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx */
+        /* SADD8                cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx */
+        /* SSUB8                cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx */
+        /* QADD16               cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx */
+        /* QADDSUBX             cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx */
+        /* QSUBADDX             cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx */
+        /* QSUB16               cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx */
+        /* QADD8                cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx */
+        /* QSUB8                cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx */
+        /* SHADD16              cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx */
+        /* SHADDSUBX            cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx */
+        /* SHSUBADDX            cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx */
+        /* SHSUB16              cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx */
+        /* SHADD8               cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx */
+        /* SHSUB8               cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx */
+        /* UADD16               cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx */
+        /* UADDSUBX             cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx */
+        /* USUBADDX             cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx */
+        /* USUB16               cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx */
+        /* UADD8                cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx */
+        /* USUB8                cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx */
+        /* UQADD16              cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx */
+        /* UQADDSUBX            cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx */
+        /* UQSUBADDX            cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx */
+        /* UQSUB16              cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx */
+        /* UQADD8               cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx */
+        /* UQSUB8               cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx */
+        /* UHADD16              cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx */
+        /* UHADDSUBX            cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx */
+        /* UHSUBADDX            cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx */
+        /* UHSUB16              cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx */
+        /* UHADD8               cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx */
+        /* UHSUB8               cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx */
+        DECODE_EMULATEX (0x0f800010, 0x06000010, PROBES_MMI,
+                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
+        /* PKHBT                cccc 0110 1000 xxxx xxxx xxxx x001 xxxx */
+        /* PKHTB                cccc 0110 1000 xxxx xxxx xxxx x101 xxxx */
+        DECODE_EMULATEX (0x0ff00030, 0x06800010, PROBES_PACK,
+                                                 REGS(NOPC, NOPC, 0, 0, NOPC)),
+        /* ???                  cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx */
+        /* ???                  cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx */
+        DECODE_REJECT   (0x0fb000f0, 0x06900070),
+        /* SXTB16               cccc 0110 1000 1111 xxxx xxxx 0111 xxxx */
+        /* SXTB                 cccc 0110 1010 1111 xxxx xxxx 0111 xxxx */
+        /* SXTH                 cccc 0110 1011 1111 xxxx xxxx 0111 xxxx */
+        /* UXTB16               cccc 0110 1100 1111 xxxx xxxx 0111 xxxx */
+        /* UXTB                 cccc 0110 1110 1111 xxxx xxxx 0111 xxxx */
+        /* UXTH                 cccc 0110 1111 1111 xxxx xxxx 0111 xxxx */
+        DECODE_EMULATEX (0x0f8f00f0, 0x068f0070, PROBES_EXTEND,
+                                                 REGS(0, NOPC, 0, 0, NOPC)),
+        /* SXTAB16              cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx */
+        /* SXTAB                cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx */
+        /* SXTAH                cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx */
+        /* UXTAB16              cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx */
+        /* UXTAB                cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx */
+        /* UXTAH                cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx */
+        DECODE_EMULATEX (0x0f8000f0, 0x06800070, PROBES_EXTEND_ADD,
+                                                 REGS(NOPCX, NOPC, 0, 0, NOPC)),
+        DECODE_END
+};
+static const union decode_item arm_cccc_0111_____xxx1_table[] = {
+        /* Media instructions                                           */
+        /* UNDEFINED            cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
+        DECODE_REJECT   (0x0ff000f0, 0x07f000f0),
+        /* SMLALD               cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
+        /* SMLSLD               cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
+        DECODE_EMULATEX (0x0ff00090, 0x07400010, PROBES_MUL_ADD_LONG,
+                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
+        /* SMUAD                cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx */
+        /* SMUSD                cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx */
+        DECODE_OR       (0x0ff0f090, 0x0700f010),
+        /* SMMUL                cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx */
+        DECODE_OR       (0x0ff0f0d0, 0x0750f010),
+        /* USAD8                cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
+        DECODE_EMULATEX (0x0ff0f0f0, 0x0780f010, PROBES_MUL_ADD,
+                                                 REGS(NOPC, 0, NOPC, 0, NOPC)),
+        /* SMLAD                cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx */
+        /* SMLSD                cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx */
+        DECODE_OR       (0x0ff00090, 0x07000010),
+        /* SMMLA                cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx */
+        DECODE_OR       (0x0ff000d0, 0x07500010),
+        /* USADA8               cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
+        DECODE_EMULATEX (0x0ff000f0, 0x07800010, PROBES_MUL_ADD,
+                                                 REGS(NOPC, NOPCX, NOPC, 0, NOPC)),
+        /* SMMLS                cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx */
+        DECODE_EMULATEX (0x0ff000d0, 0x075000d0, PROBES_MUL_ADD,
+                                                 REGS(NOPC, NOPC, NOPC, 0, NOPC)),
+        /* SBFX                 cccc 0111 101x xxxx xxxx xxxx x101 xxxx */
+        /* UBFX                 cccc 0111 111x xxxx xxxx xxxx x101 xxxx */
+        DECODE_EMULATEX (0x0fa00070, 0x07a00050, PROBES_BITFIELD,
+                                                 REGS(0, NOPC, 0, 0, NOPC)),
+        /* BFC                  cccc 0111 110x xxxx xxxx xxxx x001 1111 */
+        DECODE_EMULATEX (0x0fe0007f, 0x07c0001f, PROBES_BITFIELD,
+                                                 REGS(0, NOPC, 0, 0, 0)),
+        /* BFI                  cccc 0111 110x xxxx xxxx xxxx x001 xxxx */
+        DECODE_EMULATEX (0x0fe00070, 0x07c00010, PROBES_BITFIELD,
+                                                 REGS(0, NOPC, 0, 0, NOPCX)),
+        DECODE_END
+};
+static const union decode_item arm_cccc_01xx_table[] = {
+        /* Load/store word and unsigned byte                            */
+        /* LDRB/STRB pc,[...]   cccc 01xx x0xx xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0x0c40f000, 0x0440f000),
+        /* STRT                 cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRT                 cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
+        /* STRBT                cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRBT                cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0x0d200000, 0x04200000),
+        /* STR (immediate)      cccc 010x x0x0 xxxx xxxx xxxx xxxx xxxx */
+        /* STRB (immediate)     cccc 010x x1x0 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0x0e100000, 0x04000000, PROBES_STORE,
+                                                 REGS(NOPCWB, ANY, 0, 0, 0)),
+        /* LDR (immediate)      cccc 010x x0x1 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRB (immediate)     cccc 010x x1x1 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0x0e100000, 0x04100000, PROBES_LOAD,
+                                                 REGS(NOPCWB, ANY, 0, 0, 0)),
+        /* STR (register)       cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx */
+        /* STRB (register)      cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0x0e100000, 0x06000000, PROBES_STORE,
+                                                 REGS(NOPCWB, ANY, 0, 0, NOPC)),
+        /* LDR (register)       cccc 011x x0x1 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRB (register)      cccc 011x x1x1 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0x0e100000, 0x06100000, PROBES_LOAD,
+                                                 REGS(NOPCWB, ANY, 0, 0, NOPC)),
+        DECODE_END
+};
+static const union decode_item arm_cccc_100x_table[] = {
+        /* Block data transfer instructions                             */
+        /* LDM                  cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
+        /* STM                  cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_CUSTOM   (0x0e400000, 0x08000000, PROBES_LDMSTM),
+        /* STM (user registers) cccc 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
+        /* LDM (user registers) cccc 100x x1x1 xxxx 0xxx xxxx xxxx xxxx */
+        /* LDM (exception ret)  cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
+        DECODE_END
+};
+const union decode_item probes_decode_arm_table[] = {
+        /*
+         * Unconditional instructions
+         *                      1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xf0000000, 0xf0000000, arm_1111_table),
+        /*
+         * Miscellaneous instructions
+         *                      cccc 0001 0xx0 xxxx xxxx xxxx 0xxx xxxx
+         */
+        DECODE_TABLE    (0x0f900080, 0x01000000, arm_cccc_0001_0xx0____0xxx_table),
+        /*
+         * Halfword multiply and multiply-accumulate
+         *                      cccc 0001 0xx0 xxxx xxxx xxxx 1xx0 xxxx
+         */
+        DECODE_TABLE    (0x0f900090, 0x01000080, arm_cccc_0001_0xx0____1xx0_table),
+        /*
+         * Multiply and multiply-accumulate
+         *                      cccc 0000 xxxx xxxx xxxx xxxx 1001 xxxx
+         */
+        DECODE_TABLE    (0x0f0000f0, 0x00000090, arm_cccc_0000_____1001_table),
+        /*
+         * Synchronization primitives
+         *                      cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx
+         */
+        DECODE_TABLE    (0x0f0000f0, 0x01000090, arm_cccc_0001_____1001_table),
+        /*
+         * Extra load/store instructions
+         *                      cccc 000x xxxx xxxx xxxx xxxx 1xx1 xxxx
+         */
+        DECODE_TABLE    (0x0e000090, 0x00000090, arm_cccc_000x_____1xx1_table),
+        /*
+         * Data-processing (register)
+         *                      cccc 000x xxxx xxxx xxxx xxxx xxx0 xxxx
+         * Data-processing (register-shifted register)
+         *                      cccc 000x xxxx xxxx xxxx xxxx 0xx1 xxxx
+         */
+        DECODE_TABLE    (0x0e000000, 0x00000000, arm_cccc_000x_table),
+        /*
+         * Data-processing (immediate)
+         *                      cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0x0e000000, 0x02000000, arm_cccc_001x_table),
+        /*
+         * Media instructions
+         *                      cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx
+         */
+        DECODE_TABLE    (0x0f000010, 0x06000010, arm_cccc_0110_____xxx1_table),
+        DECODE_TABLE    (0x0f000010, 0x07000010, arm_cccc_0111_____xxx1_table),
+        /*
+         * Load/store word and unsigned byte
+         *                      cccc 01xx xxxx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0x0c000000, 0x04000000, arm_cccc_01xx_table),
+        /*
+         * Block data transfer instructions
+         *                      cccc 100x xxxx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0x0e000000, 0x08000000, arm_cccc_100x_table),
+        /* B                    cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
+        /* BL                   cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
+        DECODE_SIMULATE (0x0e000000, 0x0a000000, PROBES_BRANCH),
+        /*
+         * Supervisor Call, and coprocessor instructions
+         */
+        /* MCRR                 cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx */
+        /* MRRC                 cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx */
+        /* LDC                  cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
+        /* STC                  cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
+        /* CDP                  cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
+        /* MCR                  cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
+        /* MRC                  cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
+        /* SVC                  cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0x0c000000, 0x0c000000),
+        DECODE_END
+};
+#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
+EXPORT_SYMBOL_GPL(probes_decode_arm_table);
+#endif
+static void __kprobes arm_singlestep(probes_opcode_t insn,
+                struct arch_probes_insn *asi, struct pt_regs *regs)
+{
+        regs->ARM_pc += 4;
+        asi->insn_handler(insn, asi, regs);
+}
+/* Return:
+ *   INSN_REJECTED     If instruction is one not allowed to kprobe,
+ *   INSN_GOOD         If instruction is supported and uses instruction slot,
+ *   INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
+ *
+ * For instructions we don't want to kprobe (INSN_REJECTED return result):
+ *   These are generally ones that modify the processor state making
+ *   them "hard" to simulate such as switches processor modes or
+ *   make accesses in alternate modes.  Any of these could be simulated
+ *   if the work was put into it, but low return considering they
+ *   should also be very rare.
+ */
+enum probes_insn __kprobes
+arm_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
+                       bool emulate, const union decode_action *actions)
+{
+        asi->insn_singlestep = arm_singlestep;
+        asi->insn_check_cc = probes_condition_checks[insn>>28];
+        return probes_decode_insn(insn, asi, probes_decode_arm_table, false,
+                                  emulate, actions);
+}
diff --git a/arch/arm/kernel/probes-arm.h b/arch/arm/kernel/probes-arm.h
new file mode 100644
index 000000000000..ace6572f6e26
--- /dev/null
+++ b/arch/arm/kernel/probes-arm.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/kernel/probes-arm.h
+ *
+ * Copyright 2013 Linaro Ltd.
+ * Written by: David A. Long
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef _ARM_KERNEL_PROBES_ARM_H
+#define  _ARM_KERNEL_PROBES_ARM_H
+enum probes_arm_action {
+        PROBES_EMULATE_NONE,
+        PROBES_SIMULATE_NOP,
+        PROBES_PRELOAD_IMM,
+        PROBES_PRELOAD_REG,
+        PROBES_BRANCH_IMM,
+        PROBES_BRANCH_REG,
+        PROBES_MRS,
+        PROBES_CLZ,
+        PROBES_SATURATING_ARITHMETIC,
+        PROBES_MUL1,
+        PROBES_MUL2,
+        PROBES_SWP,
+        PROBES_LDRSTRD,
+        PROBES_LOAD,
+        PROBES_STORE,
+        PROBES_LOAD_EXTRA,
+        PROBES_STORE_EXTRA,
+        PROBES_MOV_IP_SP,
+        PROBES_DATA_PROCESSING_REG,
+        PROBES_DATA_PROCESSING_IMM,
+        PROBES_MOV_HALFWORD,
+        PROBES_SEV,
+        PROBES_WFE,
+        PROBES_SATURATE,
+        PROBES_REV,
+        PROBES_MMI,
+        PROBES_PACK,
+        PROBES_EXTEND,
+        PROBES_EXTEND_ADD,
+        PROBES_MUL_ADD_LONG,
+        PROBES_MUL_ADD,
+        PROBES_BITFIELD,
+        PROBES_BRANCH,
+        PROBES_LDMSTM,
+        NUM_PROBES_ARM_ACTIONS
+};
+void __kprobes simulate_bbl(probes_opcode_t opcode,
+        struct arch_probes_insn *asi, struct pt_regs *regs);
+void __kprobes simulate_blx1(probes_opcode_t opcode,
+        struct arch_probes_insn *asi, struct pt_regs *regs);
+void __kprobes simulate_blx2bx(probes_opcode_t opcode,
+        struct arch_probes_insn *asi, struct pt_regs *regs);
+void __kprobes simulate_mrs(probes_opcode_t opcode,
+        struct arch_probes_insn *asi, struct pt_regs *regs);
+void __kprobes simulate_mov_ipsp(probes_opcode_t opcode,
+        struct arch_probes_insn *asi, struct pt_regs *regs);
+extern const union decode_item probes_decode_arm_table[];
+enum probes_insn arm_probes_decode_insn(probes_opcode_t,
+                struct arch_probes_insn *, bool emulate,
+                const union decode_action *actions);
+#endif
diff --git a/arch/arm/kernel/probes-thumb.c b/arch/arm/kernel/probes-thumb.c
new file mode 100644
index 000000000000..4131351e812f
--- /dev/null
+++ b/arch/arm/kernel/probes-thumb.c
@@ -0,0 +1,882 @@
+/*
+ * arch/arm/kernel/probes-thumb.c
+ *
+ * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include "probes.h"
+#include "probes-thumb.h"
+static const union decode_item t32_table_1110_100x_x0xx[] = {
+        /* Load/store multiple instructions */
+        /* Rn is PC             1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfe4f0000, 0xe80f0000),
+        /* SRS                  1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */
+        /* RFE                  1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xffc00000, 0xe8000000),
+        /* SRS                  1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */
+        /* RFE                  1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xffc00000, 0xe9800000),
+        /* STM Rn, {...pc}      1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfe508000, 0xe8008000),
+        /* LDM Rn, {...lr,pc}   1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfe50c000, 0xe810c000),
+        /* LDM/STM Rn, {...sp}  1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfe402000, 0xe8002000),
+        /* STMIA                1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */
+        /* LDMIA                1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */
+        /* STMDB                1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */
+        /* LDMDB                1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_CUSTOM   (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
+        DECODE_END
+};
+static const union decode_item t32_table_1110_100x_x1xx[] = {
+        /* Load/store dual, load/store exclusive, table branch */
+        /* STRD (immediate)     1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRD (immediate)     1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_OR       (0xff600000, 0xe8600000),
+        /* STRD (immediate)     1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRD (immediate)     1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
+                                                 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
+        /* TBB                  1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */
+        /* TBH                  1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */
+        DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, PROBES_T32_TABLE_BRANCH,
+                                                 REGS(NOSP, 0, 0, 0, NOSPPC)),
+        /* STREX                1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */
+        /* LDREX                1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */
+        /* STREXB               1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */
+        /* STREXH               1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */
+        /* STREXD               1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */
+        /* LDREXB               1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */
+        /* LDREXH               1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */
+        /* LDREXD               1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */
+        /* And unallocated instructions...                              */
+        DECODE_END
+};
+static const union decode_item t32_table_1110_101x[] = {
+        /* Data-processing (shifted register)                           */
+        /* TST                  1110 1010 0001 xxxx xxxx 1111 xxxx xxxx */
+        /* TEQ                  1110 1010 1001 xxxx xxxx 1111 xxxx xxxx */
+        DECODE_EMULATEX (0xff700f00, 0xea100f00, PROBES_T32_TST,
+                                                 REGS(NOSPPC, 0, 0, 0, NOSPPC)),
+        /* CMN                  1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */
+        DECODE_OR       (0xfff00f00, 0xeb100f00),
+        /* CMP                  1110 1011 1011 xxxx xxxx 1111 xxxx xxxx */
+        DECODE_EMULATEX (0xfff00f00, 0xebb00f00, PROBES_T32_TST,
+                                                 REGS(NOPC, 0, 0, 0, NOSPPC)),
+        /* MOV                  1110 1010 010x 1111 xxxx xxxx xxxx xxxx */
+        /* MVN                  1110 1010 011x 1111 xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xffcf0000, 0xea4f0000, PROBES_T32_MOV,
+                                                 REGS(0, 0, NOSPPC, 0, NOSPPC)),
+        /* ???                  1110 1010 101x xxxx xxxx xxxx xxxx xxxx */
+        /* ???                  1110 1010 111x xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xffa00000, 0xeaa00000),
+        /* ???                  1110 1011 001x xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xffe00000, 0xeb200000),
+        /* ???                  1110 1011 100x xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xffe00000, 0xeb800000),
+        /* ???                  1110 1011 111x xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xffe00000, 0xebe00000),
+        /* ADD/SUB SP, SP, Rm, LSL #0..3                                */
+        /*                      1110 1011 x0xx 1101 x000 1101 xx00 xxxx */
+        DECODE_EMULATEX (0xff4f7f30, 0xeb0d0d00, PROBES_T32_ADDSUB,
+                                                 REGS(SP, 0, SP, 0, NOSPPC)),
+        /* ADD/SUB SP, SP, Rm, shift                                    */
+        /*                      1110 1011 x0xx 1101 xxxx 1101 xxxx xxxx */
+        DECODE_REJECT   (0xff4f0f00, 0xeb0d0d00),
+        /* ADD/SUB Rd, SP, Rm, shift                                    */
+        /*                      1110 1011 x0xx 1101 xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xff4f0000, 0xeb0d0000, PROBES_T32_ADDSUB,
+                                                 REGS(SP, 0, NOPC, 0, NOSPPC)),
+        /* AND                  1110 1010 000x xxxx xxxx xxxx xxxx xxxx */
+        /* BIC                  1110 1010 001x xxxx xxxx xxxx xxxx xxxx */
+        /* ORR                  1110 1010 010x xxxx xxxx xxxx xxxx xxxx */
+        /* ORN                  1110 1010 011x xxxx xxxx xxxx xxxx xxxx */
+        /* EOR                  1110 1010 100x xxxx xxxx xxxx xxxx xxxx */
+        /* PKH                  1110 1010 110x xxxx xxxx xxxx xxxx xxxx */
+        /* ADD                  1110 1011 000x xxxx xxxx xxxx xxxx xxxx */
+        /* ADC                  1110 1011 010x xxxx xxxx xxxx xxxx xxxx */
+        /* SBC                  1110 1011 011x xxxx xxxx xxxx xxxx xxxx */
+        /* SUB                  1110 1011 101x xxxx xxxx xxxx xxxx xxxx */
+        /* RSB                  1110 1011 110x xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfe000000, 0xea000000, PROBES_T32_LOGICAL,
+                                                 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
+        DECODE_END
+};
+static const union decode_item t32_table_1111_0x0x___0[] = {
+        /* Data-processing (modified immediate)                         */
+        /* TST                  1111 0x00 0001 xxxx 0xxx 1111 xxxx xxxx */
+        /* TEQ                  1111 0x00 1001 xxxx 0xxx 1111 xxxx xxxx */
+        DECODE_EMULATEX (0xfb708f00, 0xf0100f00, PROBES_T32_TST,
+                                                 REGS(NOSPPC, 0, 0, 0, 0)),
+        /* CMN                  1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */
+        DECODE_OR       (0xfbf08f00, 0xf1100f00),
+        /* CMP                  1111 0x01 1011 xxxx 0xxx 1111 xxxx xxxx */
+        DECODE_EMULATEX (0xfbf08f00, 0xf1b00f00, PROBES_T32_CMP,
+                                                 REGS(NOPC, 0, 0, 0, 0)),
+        /* MOV                  1111 0x00 010x 1111 0xxx xxxx xxxx xxxx */
+        /* MVN                  1111 0x00 011x 1111 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfbcf8000, 0xf04f0000, PROBES_T32_MOV,
+                                                 REGS(0, 0, NOSPPC, 0, 0)),
+        /* ???                  1111 0x00 101x xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfbe08000, 0xf0a00000),
+        /* ???                  1111 0x00 110x xxxx 0xxx xxxx xxxx xxxx */
+        /* ???                  1111 0x00 111x xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfbc08000, 0xf0c00000),
+        /* ???                  1111 0x01 001x xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfbe08000, 0xf1200000),
+        /* ???                  1111 0x01 100x xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfbe08000, 0xf1800000),
+        /* ???                  1111 0x01 111x xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfbe08000, 0xf1e00000),
+        /* ADD Rd, SP, #imm     1111 0x01 000x 1101 0xxx xxxx xxxx xxxx */
+        /* SUB Rd, SP, #imm     1111 0x01 101x 1101 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfb4f8000, 0xf10d0000, PROBES_T32_ADDSUB,
+                                                 REGS(SP, 0, NOPC, 0, 0)),
+        /* AND                  1111 0x00 000x xxxx 0xxx xxxx xxxx xxxx */
+        /* BIC                  1111 0x00 001x xxxx 0xxx xxxx xxxx xxxx */
+        /* ORR                  1111 0x00 010x xxxx 0xxx xxxx xxxx xxxx */
+        /* ORN                  1111 0x00 011x xxxx 0xxx xxxx xxxx xxxx */
+        /* EOR                  1111 0x00 100x xxxx 0xxx xxxx xxxx xxxx */
+        /* ADD                  1111 0x01 000x xxxx 0xxx xxxx xxxx xxxx */
+        /* ADC                  1111 0x01 010x xxxx 0xxx xxxx xxxx xxxx */
+        /* SBC                  1111 0x01 011x xxxx 0xxx xxxx xxxx xxxx */
+        /* SUB                  1111 0x01 101x xxxx 0xxx xxxx xxxx xxxx */
+        /* RSB                  1111 0x01 110x xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfa008000, 0xf0000000, PROBES_T32_LOGICAL,
+                                                 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
+        DECODE_END
+};
+static const union decode_item t32_table_1111_0x1x___0[] = {
+        /* Data-processing (plain binary immediate)                     */
+        /* ADDW Rd, PC, #imm    1111 0x10 0000 1111 0xxx xxxx xxxx xxxx */
+        DECODE_OR       (0xfbff8000, 0xf20f0000),
+        /* SUBW Rd, PC, #imm    1111 0x10 1010 1111 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfbff8000, 0xf2af0000, PROBES_T32_ADDWSUBW_PC,
+                                                 REGS(PC, 0, NOSPPC, 0, 0)),
+        /* ADDW SP, SP, #imm    1111 0x10 0000 1101 0xxx 1101 xxxx xxxx */
+        DECODE_OR       (0xfbff8f00, 0xf20d0d00),
+        /* SUBW SP, SP, #imm    1111 0x10 1010 1101 0xxx 1101 xxxx xxxx */
+        DECODE_EMULATEX (0xfbff8f00, 0xf2ad0d00, PROBES_T32_ADDWSUBW,
+                                                 REGS(SP, 0, SP, 0, 0)),
+        /* ADDW                 1111 0x10 0000 xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_OR       (0xfbf08000, 0xf2000000),
+        /* SUBW                 1111 0x10 1010 xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfbf08000, 0xf2a00000, PROBES_T32_ADDWSUBW,
+                                                 REGS(NOPCX, 0, NOSPPC, 0, 0)),
+        /* MOVW                 1111 0x10 0100 xxxx 0xxx xxxx xxxx xxxx */
+        /* MOVT                 1111 0x10 1100 xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfb708000, 0xf2400000, PROBES_T32_MOVW,
+                                                 REGS(0, 0, NOSPPC, 0, 0)),
+        /* SSAT16               1111 0x11 0010 xxxx 0000 xxxx 00xx xxxx */
+        /* SSAT                 1111 0x11 00x0 xxxx 0xxx xxxx xxxx xxxx */
+        /* USAT16               1111 0x11 1010 xxxx 0000 xxxx 00xx xxxx */
+        /* USAT                 1111 0x11 10x0 xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfb508000, 0xf3000000, PROBES_T32_SAT,
+                                                 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
+        /* SFBX                 1111 0x11 0100 xxxx 0xxx xxxx xxxx xxxx */
+        /* UFBX                 1111 0x11 1100 xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfb708000, 0xf3400000, PROBES_T32_BITFIELD,
+                                                 REGS(NOSPPC, 0, NOSPPC, 0, 0)),
+        /* BFC                  1111 0x11 0110 1111 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfbff8000, 0xf36f0000, PROBES_T32_BITFIELD,
+                                                 REGS(0, 0, NOSPPC, 0, 0)),
+        /* BFI                  1111 0x11 0110 xxxx 0xxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfbf08000, 0xf3600000, PROBES_T32_BITFIELD,
+                                                 REGS(NOSPPCX, 0, NOSPPC, 0, 0)),
+        DECODE_END
+};
+static const union decode_item t32_table_1111_0xxx___1[] = {
+        /* Branches and miscellaneous control                           */
+        /* YIELD                1111 0011 1010 xxxx 10x0 x000 0000 0001 */
+        DECODE_OR       (0xfff0d7ff, 0xf3a08001),
+        /* SEV                  1111 0011 1010 xxxx 10x0 x000 0000 0100 */
+        DECODE_EMULATE  (0xfff0d7ff, 0xf3a08004, PROBES_T32_SEV),
+        /* NOP                  1111 0011 1010 xxxx 10x0 x000 0000 0000 */
+        /* WFE                  1111 0011 1010 xxxx 10x0 x000 0000 0010 */
+        /* WFI                  1111 0011 1010 xxxx 10x0 x000 0000 0011 */
+        DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, PROBES_T32_WFE),
+        /* MRS Rd, CPSR         1111 0011 1110 xxxx 10x0 xxxx xxxx xxxx */
+        DECODE_SIMULATEX(0xfff0d000, 0xf3e08000, PROBES_T32_MRS,
+                                                 REGS(0, 0, NOSPPC, 0, 0)),
+        /*
+         * Unsupported instructions
+         *                      1111 0x11 1xxx xxxx 10x0 xxxx xxxx xxxx
+         *
+         * MSR                  1111 0011 100x xxxx 10x0 xxxx xxxx xxxx
+         * DBG hint             1111 0011 1010 xxxx 10x0 x000 1111 xxxx
+         * Unallocated hints    1111 0011 1010 xxxx 10x0 x000 xxxx xxxx
+         * CPS                  1111 0011 1010 xxxx 10x0 xxxx xxxx xxxx
+         * CLREX/DSB/DMB/ISB    1111 0011 1011 xxxx 10x0 xxxx xxxx xxxx
+         * BXJ                  1111 0011 1100 xxxx 10x0 xxxx xxxx xxxx
+         * SUBS PC,LR,#<imm8>   1111 0011 1101 xxxx 10x0 xxxx xxxx xxxx
+         * MRS Rd, SPSR         1111 0011 1111 xxxx 10x0 xxxx xxxx xxxx
+         * SMC                  1111 0111 1111 xxxx 1000 xxxx xxxx xxxx
+         * UNDEFINED            1111 0111 1111 xxxx 1010 xxxx xxxx xxxx
+         * ???                  1111 0111 1xxx xxxx 1010 xxxx xxxx xxxx
+         */
+        DECODE_REJECT   (0xfb80d000, 0xf3808000),
+        /* Bcc                  1111 0xxx xxxx xxxx 10x0 xxxx xxxx xxxx */
+        DECODE_CUSTOM   (0xf800d000, 0xf0008000, PROBES_T32_BRANCH_COND),
+        /* BLX                  1111 0xxx xxxx xxxx 11x0 xxxx xxxx xxx0 */
+        DECODE_OR       (0xf800d001, 0xf000c000),
+        /* B                    1111 0xxx xxxx xxxx 10x1 xxxx xxxx xxxx */
+        /* BL                   1111 0xxx xxxx xxxx 11x1 xxxx xxxx xxxx */
+        DECODE_SIMULATE (0xf8009000, 0xf0009000, PROBES_T32_BRANCH),
+        DECODE_END
+};
+static const union decode_item t32_table_1111_100x_x0x1__1111[] = {
+        /* Memory hints                                                 */
+        /* PLD (literal)        1111 1000 x001 1111 1111 xxxx xxxx xxxx */
+        /* PLI (literal)        1111 1001 x001 1111 1111 xxxx xxxx xxxx */
+        DECODE_SIMULATE (0xfe7ff000, 0xf81ff000, PROBES_T32_PLDI),
+        /* PLD{W} (immediate)   1111 1000 10x1 xxxx 1111 xxxx xxxx xxxx */
+        DECODE_OR       (0xffd0f000, 0xf890f000),
+        /* PLD{W} (immediate)   1111 1000 00x1 xxxx 1111 1100 xxxx xxxx */
+        DECODE_OR       (0xffd0ff00, 0xf810fc00),
+        /* PLI (immediate)      1111 1001 1001 xxxx 1111 xxxx xxxx xxxx */
+        DECODE_OR       (0xfff0f000, 0xf990f000),
+        /* PLI (immediate)      1111 1001 0001 xxxx 1111 1100 xxxx xxxx */
+        DECODE_SIMULATEX(0xfff0ff00, 0xf910fc00, PROBES_T32_PLDI,
+                                                 REGS(NOPCX, 0, 0, 0, 0)),
+        /* PLD{W} (register)    1111 1000 00x1 xxxx 1111 0000 00xx xxxx */
+        DECODE_OR       (0xffd0ffc0, 0xf810f000),
+        /* PLI (register)       1111 1001 0001 xxxx 1111 0000 00xx xxxx */
+        DECODE_SIMULATEX(0xfff0ffc0, 0xf910f000, PROBES_T32_PLDI,
+                                                 REGS(NOPCX, 0, 0, 0, NOSPPC)),
+        /* Other unallocated instructions...                            */
+        DECODE_END
+};
+static const union decode_item t32_table_1111_100x[] = {
+        /* Store/Load single data item                                  */
+        /* ???                  1111 100x x11x xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfe600000, 0xf8600000),
+        /* ???                  1111 1001 0101 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xfff00000, 0xf9500000),
+        /* ???                  1111 100x 0xxx xxxx xxxx 10x0 xxxx xxxx */
+        DECODE_REJECT   (0xfe800d00, 0xf8000800),
+        /* STRBT                1111 1000 0000 xxxx xxxx 1110 xxxx xxxx */
+        /* STRHT                1111 1000 0010 xxxx xxxx 1110 xxxx xxxx */
+        /* STRT                 1111 1000 0100 xxxx xxxx 1110 xxxx xxxx */
+        /* LDRBT                1111 1000 0001 xxxx xxxx 1110 xxxx xxxx */
+        /* LDRSBT               1111 1001 0001 xxxx xxxx 1110 xxxx xxxx */
+        /* LDRHT                1111 1000 0011 xxxx xxxx 1110 xxxx xxxx */
+        /* LDRSHT               1111 1001 0011 xxxx xxxx 1110 xxxx xxxx */
+        /* LDRT                 1111 1000 0101 xxxx xxxx 1110 xxxx xxxx */
+        DECODE_REJECT   (0xfe800f00, 0xf8000e00),
+        /* STR{,B,H} Rn,[PC...] 1111 1000 xxx0 1111 xxxx xxxx xxxx xxxx */
+        DECODE_REJECT   (0xff1f0000, 0xf80f0000),
+        /* STR{,B,H} PC,[Rn...] 1111 1000 xxx0 xxxx 1111 xxxx xxxx xxxx */
+        DECODE_REJECT   (0xff10f000, 0xf800f000),
+        /* LDR (literal)        1111 1000 x101 1111 xxxx xxxx xxxx xxxx */
+        DECODE_SIMULATEX(0xff7f0000, 0xf85f0000, PROBES_T32_LDR_LIT,
+                                                 REGS(PC, ANY, 0, 0, 0)),
+        /* STR (immediate)      1111 1000 0100 xxxx xxxx 1xxx xxxx xxxx */
+        /* LDR (immediate)      1111 1000 0101 xxxx xxxx 1xxx xxxx xxxx */
+        DECODE_OR       (0xffe00800, 0xf8400800),
+        /* STR (immediate)      1111 1000 1100 xxxx xxxx xxxx xxxx xxxx */
+        /* LDR (immediate)      1111 1000 1101 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xffe00000, 0xf8c00000, PROBES_T32_LDRSTR,
+                                                 REGS(NOPCX, ANY, 0, 0, 0)),
+        /* STR (register)       1111 1000 0100 xxxx xxxx 0000 00xx xxxx */
+        /* LDR (register)       1111 1000 0101 xxxx xxxx 0000 00xx xxxx */
+        DECODE_EMULATEX (0xffe00fc0, 0xf8400000, PROBES_T32_LDRSTR,
+                                                 REGS(NOPCX, ANY, 0, 0, NOSPPC)),
+        /* LDRB (literal)       1111 1000 x001 1111 xxxx xxxx xxxx xxxx */
+        /* LDRSB (literal)      1111 1001 x001 1111 xxxx xxxx xxxx xxxx */
+        /* LDRH (literal)       1111 1000 x011 1111 xxxx xxxx xxxx xxxx */
+        /* LDRSH (literal)      1111 1001 x011 1111 xxxx xxxx xxxx xxxx */
+        DECODE_SIMULATEX(0xfe5f0000, 0xf81f0000, PROBES_T32_LDR_LIT,
+                                                 REGS(PC, NOSPPCX, 0, 0, 0)),
+        /* STRB (immediate)     1111 1000 0000 xxxx xxxx 1xxx xxxx xxxx */
+        /* STRH (immediate)     1111 1000 0010 xxxx xxxx 1xxx xxxx xxxx */
+        /* LDRB (immediate)     1111 1000 0001 xxxx xxxx 1xxx xxxx xxxx */
+        /* LDRSB (immediate)    1111 1001 0001 xxxx xxxx 1xxx xxxx xxxx */
+        /* LDRH (immediate)     1111 1000 0011 xxxx xxxx 1xxx xxxx xxxx */
+        /* LDRSH (immediate)    1111 1001 0011 xxxx xxxx 1xxx xxxx xxxx */
+        DECODE_OR       (0xfec00800, 0xf8000800),
+        /* STRB (immediate)     1111 1000 1000 xxxx xxxx xxxx xxxx xxxx */
+        /* STRH (immediate)     1111 1000 1010 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRB (immediate)     1111 1000 1001 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRSB (immediate)    1111 1001 1001 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRH (immediate)     1111 1000 1011 xxxx xxxx xxxx xxxx xxxx */
+        /* LDRSH (immediate)    1111 1001 1011 xxxx xxxx xxxx xxxx xxxx */
+        DECODE_EMULATEX (0xfec00000, 0xf8800000, PROBES_T32_LDRSTR,
+                                                 REGS(NOPCX, NOSPPCX, 0, 0, 0)),
+        /* STRB (register)      1111 1000 0000 xxxx xxxx 0000 00xx xxxx */
+        /* STRH (register)      1111 1000 0010 xxxx xxxx 0000 00xx xxxx */
+        /* LDRB (register)      1111 1000 0001 xxxx xxxx 0000 00xx xxxx */
+        /* LDRSB (register)     1111 1001 0001 xxxx xxxx 0000 00xx xxxx */
+        /* LDRH (register)      1111 1000 0011 xxxx xxxx 0000 00xx xxxx */
+        /* LDRSH (register)     1111 1001 0011 xxxx xxxx 0000 00xx xxxx */
+        DECODE_EMULATEX (0xfe800fc0, 0xf8000000, PROBES_T32_LDRSTR,
+                                                 REGS(NOPCX, NOSPPCX, 0, 0, NOSPPC)),
+        /* Other unallocated instructions...                            */
+        DECODE_END
+};
+static const union decode_item t32_table_1111_1010___1111[] = {
+        /* Data-processing (register)                                   */
+        /* ???                  1111 1010 011x xxxx 1111 xxxx 1xxx xxxx */
+        DECODE_REJECT   (0xffe0f080, 0xfa60f080),
+        /* SXTH                 1111 1010 0000 1111 1111 xxxx 1xxx xxxx */
+        /* UXTH                 1111 1010 0001 1111 1111 xxxx 1xxx xxxx */
+        /* SXTB16               1111 1010 0010 1111 1111 xxxx 1xxx xxxx */
+        /* UXTB16               1111 1010 0011 1111 1111 xxxx 1xxx xxxx */
+        /* SXTB                 1111 1010 0100 1111 1111 xxxx 1xxx xxxx */
+        /* UXTB                 1111 1010 0101 1111 1111 xxxx 1xxx xxxx */
+        DECODE_EMULATEX (0xff8ff080, 0xfa0ff080, PROBES_T32_SIGN_EXTEND,
+                                                 REGS(0, 0, NOSPPC, 0, NOSPPC)),
+        /* ???                  1111 1010 1xxx xxxx 1111 xxxx 0x11 xxxx */
+        DECODE_REJECT   (0xff80f0b0, 0xfa80f030),
+        /* ???                  1111 1010 1x11 xxxx 1111 xxxx 0xxx xxxx */
+        DECODE_REJECT   (0xffb0f080, 0xfab0f000),
+        /* SADD16               1111 1010 1001 xxxx 1111 xxxx 0000 xxxx */
+        /* SASX                 1111 1010 1010 xxxx 1111 xxxx 0000 xxxx */
+        /* SSAX                 1111 1010 1110 xxxx 1111 xxxx 0000 xxxx */
+        /* SSUB16               1111 1010 1101 xxxx 1111 xxxx 0000 xxxx */
+        /* SADD8                1111 1010 1000 xxxx 1111 xxxx 0000 xxxx */
+        /* SSUB8                1111 1010 1100 xxxx 1111 xxxx 0000 xxxx */
+        /* QADD16               1111 1010 1001 xxxx 1111 xxxx 0001 xxxx */
+        /* QASX                 1111 1010 1010 xxxx 1111 xxxx 0001 xxxx */
+        /* QSAX                 1111 1010 1110 xxxx 1111 xxxx 0001 xxxx */
+        /* QSUB16               1111 1010 1101 xxxx 1111 xxxx 0001 xxxx */
+        /* QADD8                1111 1010 1000 xxxx 1111 xxxx 0001 xxxx */
+        /* QSUB8                1111 1010 1100 xxxx 1111 xxxx 0001 xxxx */
+        /* SHADD16              1111 1010 1001 xxxx 1111 xxxx 0010 xxxx */
+        /* SHASX                1111 1010 1010 xxxx 1111 xxxx 0010 xxxx */
+        /* SHSAX                1111 1010 1110 xxxx 1111 xxxx 0010 xxxx */
+        /* SHSUB16              1111 1010 1101 xxxx 1111 xxxx 0010 xxxx */
+        /* SHADD8               1111 1010 1000 xxxx 1111 xxxx 0010 xxxx */
+        /* SHSUB8               1111 1010 1100 xxxx 1111 xxxx 0010 xxxx */
+        /* UADD16               1111 1010 1001 xxxx 1111 xxxx 0100 xxxx */
+        /* UASX                 1111 1010 1010 xxxx 1111 xxxx 0100 xxxx */
+        /* USAX                 1111 1010 1110 xxxx 1111 xxxx 0100 xxxx */
+        /* USUB16               1111 1010 1101 xxxx 1111 xxxx 0100 xxxx */
+        /* UADD8                1111 1010 1000 xxxx 1111 xxxx 0100 xxxx */
+        /* USUB8                1111 1010 1100 xxxx 1111 xxxx 0100 xxxx */
+        /* UQADD16              1111 1010 1001 xxxx 1111 xxxx 0101 xxxx */
+        /* UQASX                1111 1010 1010 xxxx 1111 xxxx 0101 xxxx */
+        /* UQSAX                1111 1010 1110 xxxx 1111 xxxx 0101 xxxx */
+        /* UQSUB16              1111 1010 1101 xxxx 1111 xxxx 0101 xxxx */
+        /* UQADD8               1111 1010 1000 xxxx 1111 xxxx 0101 xxxx */
+        /* UQSUB8               1111 1010 1100 xxxx 1111 xxxx 0101 xxxx */
+        /* UHADD16              1111 1010 1001 xxxx 1111 xxxx 0110 xxxx */
+        /* UHASX                1111 1010 1010 xxxx 1111 xxxx 0110 xxxx */
+        /* UHSAX                1111 1010 1110 xxxx 1111 xxxx 0110 xxxx */
+        /* UHSUB16              1111 1010 1101 xxxx 1111 xxxx 0110 xxxx */
+        /* UHADD8               1111 1010 1000 xxxx 1111 xxxx 0110 xxxx */
+        /* UHSUB8               1111 1010 1100 xxxx 1111 xxxx 0110 xxxx */
+        DECODE_OR       (0xff80f080, 0xfa80f000),
+        /* SXTAH                1111 1010 0000 xxxx 1111 xxxx 1xxx xxxx */
+        /* UXTAH                1111 1010 0001 xxxx 1111 xxxx 1xxx xxxx */
+        /* SXTAB16              1111 1010 0010 xxxx 1111 xxxx 1xxx xxxx */
+        /* UXTAB16              1111 1010 0011 xxxx 1111 xxxx 1xxx xxxx */
+        /* SXTAB                1111 1010 0100 xxxx 1111 xxxx 1xxx xxxx */
+        /* UXTAB                1111 1010 0101 xxxx 1111 xxxx 1xxx xxxx */
+        DECODE_OR       (0xff80f080, 0xfa00f080),
+        /* QADD                 1111 1010 1000 xxxx 1111 xxxx 1000 xxxx */
+        /* QDADD                1111 1010 1000 xxxx 1111 xxxx 1001 xxxx */
+        /* QSUB                 1111 1010 1000 xxxx 1111 xxxx 1010 xxxx */
+        /* QDSUB                1111 1010 1000 xxxx 1111 xxxx 1011 xxxx */
+        DECODE_OR       (0xfff0f0c0, 0xfa80f080),
+        /* SEL                  1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
+        DECODE_OR       (0xfff0f0f0, 0xfaa0f080),
+        /* LSL                  1111 1010 000x xxxx 1111 xxxx 0000 xxxx */
+        /* LSR                  1111 1010 001x xxxx 1111 xxxx 0000 xxxx */
+        /* ASR                  1111 1010 010x xxxx 1111 xxxx 0000 xxxx */
+        /* ROR                  1111 1010 011x xxxx 1111 xxxx 0000 xxxx */
+        DECODE_EMULATEX (0xff80f0f0, 0xfa00f000, PROBES_T32_MEDIA,
+                                                 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
+        /* CLZ                  1111 1010 1010 xxxx 1111 xxxx 1000 xxxx */
+        DECODE_OR       (0xfff0f0f0, 0xfab0f080),
+        /* REV                  1111 1010 1001 xxxx 1111 xxxx 1000 xxxx */
+        /* REV16                1111 1010 1001 xxxx 1111 xxxx 1001 xxxx */
+        /* RBIT                 1111 1010 1001 xxxx 1111 xxxx 1010 xxxx */
+        /* REVSH                1111 1010 1001 xxxx 1111 xxxx 1011 xxxx */
+        DECODE_EMULATEX (0xfff0f0c0, 0xfa90f080, PROBES_T32_REVERSE,
+                                                 REGS(NOSPPC, 0, NOSPPC, 0, SAMEAS16)),
+        /* Other unallocated instructions...                            */
+        DECODE_END
+};
+static const union decode_item t32_table_1111_1011_0[] = {
+        /* Multiply, multiply accumulate, and absolute difference       */
+        /* ???                  1111 1011 0000 xxxx 1111 xxxx 0001 xxxx */
+        DECODE_REJECT   (0xfff0f0f0, 0xfb00f010),
+        /* ???                  1111 1011 0111 xxxx 1111 xxxx 0001 xxxx */
+        DECODE_REJECT   (0xfff0f0f0, 0xfb70f010),
+        /* SMULxy               1111 1011 0001 xxxx 1111 xxxx 00xx xxxx */
+        DECODE_OR       (0xfff0f0c0, 0xfb10f000),
+        /* MUL                  1111 1011 0000 xxxx 1111 xxxx 0000 xxxx */
+        /* SMUAD{X}             1111 1011 0010 xxxx 1111 xxxx 000x xxxx */
+        /* SMULWy               1111 1011 0011 xxxx 1111 xxxx 000x xxxx */
+        /* SMUSD{X}             1111 1011 0100 xxxx 1111 xxxx 000x xxxx */
+        /* SMMUL{R}             1111 1011 0101 xxxx 1111 xxxx 000x xxxx */
+        /* USAD8                1111 1011 0111 xxxx 1111 xxxx 0000 xxxx */
+        DECODE_EMULATEX (0xff80f0e0, 0xfb00f000, PROBES_T32_MUL_ADD,
+                                                 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)),
+        /* ???                  1111 1011 0111 xxxx xxxx xxxx 0001 xxxx */
+        DECODE_REJECT   (0xfff000f0, 0xfb700010),
+        /* SMLAxy               1111 1011 0001 xxxx xxxx xxxx 00xx xxxx */
+        DECODE_OR       (0xfff000c0, 0xfb100000),
+        /* MLA                  1111 1011 0000 xxxx xxxx xxxx 0000 xxxx */
+        /* MLS                  1111 1011 0000 xxxx xxxx xxxx 0001 xxxx */
+        /* SMLAD{X}             1111 1011 0010 xxxx xxxx xxxx 000x xxxx */
+        /* SMLAWy               1111 1011 0011 xxxx xxxx xxxx 000x xxxx */
+        /* SMLSD{X}             1111 1011 0100 xxxx xxxx xxxx 000x xxxx */
+        /* SMMLA{R}             1111 1011 0101 xxxx xxxx xxxx 000x xxxx */
+        /* SMMLS{R}             1111 1011 0110 xxxx xxxx xxxx 000x xxxx */
+        /* USADA8               1111 1011 0111 xxxx xxxx xxxx 0000 xxxx */
+        DECODE_EMULATEX (0xff8000c0, 0xfb000000,  PROBES_T32_MUL_ADD2,
+                                                 REGS(NOSPPC, NOSPPCX, NOSPPC, 0, NOSPPC)),
+        /* Other unallocated instructions...                            */
+        DECODE_END
+};
+static const union decode_item t32_table_1111_1011_1[] = {
+        /* Long multiply, long multiply accumulate, and divide          */
+        /* UMAAL                1111 1011 1110 xxxx xxxx xxxx 0110 xxxx */
+        DECODE_OR       (0xfff000f0, 0xfbe00060),
+        /* SMLALxy              1111 1011 1100 xxxx xxxx xxxx 10xx xxxx */
+        DECODE_OR       (0xfff000c0, 0xfbc00080),
+        /* SMLALD{X}            1111 1011 1100 xxxx xxxx xxxx 110x xxxx */
+        /* SMLSLD{X}            1111 1011 1101 xxxx xxxx xxxx 110x xxxx */
+        DECODE_OR       (0xffe000e0, 0xfbc000c0),
+        /* SMULL                1111 1011 1000 xxxx xxxx xxxx 0000 xxxx */
+        /* UMULL                1111 1011 1010 xxxx xxxx xxxx 0000 xxxx */
+        /* SMLAL                1111 1011 1100 xxxx xxxx xxxx 0000 xxxx */
+        /* UMLAL                1111 1011 1110 xxxx xxxx xxxx 0000 xxxx */
+        DECODE_EMULATEX (0xff9000f0, 0xfb800000, PROBES_T32_MUL_ADD_LONG,
+                                                 REGS(NOSPPC, NOSPPC, NOSPPC, 0, NOSPPC)),
+        /* SDIV                 1111 1011 1001 xxxx xxxx xxxx 1111 xxxx */
+        /* UDIV                 1111 1011 1011 xxxx xxxx xxxx 1111 xxxx */
+        /* Other unallocated instructions...                            */
+        DECODE_END
+};
+const union decode_item probes_decode_thumb32_table[] = {
+        /*
+         * Load/store multiple instructions
+         *                      1110 100x x0xx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx),
+        /*
+         * Load/store dual, load/store exclusive, table branch
+         *                      1110 100x x1xx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx),
+        /*
+         * Data-processing (shifted register)
+         *                      1110 101x xxxx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xfe000000, 0xea000000, t32_table_1110_101x),
+        /*
+         * Coprocessor instructions
+         *                      1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_REJECT   (0xfc000000, 0xec000000),
+        /*
+         * Data-processing (modified immediate)
+         *                      1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xfa008000, 0xf0000000, t32_table_1111_0x0x___0),
+        /*
+         * Data-processing (plain binary immediate)
+         *                      1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xfa008000, 0xf2000000, t32_table_1111_0x1x___0),
+        /*
+         * Branches and miscellaneous control
+         *                      1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1),
+        /*
+         * Advanced SIMD element or structure load/store instructions
+         *                      1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_REJECT   (0xff100000, 0xf9000000),
+        /*
+         * Memory hints
+         *                      1111 100x x0x1 xxxx 1111 xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xfe50f000, 0xf810f000, t32_table_1111_100x_x0x1__1111),
+        /*
+         * Store single data item
+         *                      1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx
+         * Load single data items
+         *                      1111 100x xxx1 xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xfe000000, 0xf8000000, t32_table_1111_100x),
+        /*
+         * Data-processing (register)
+         *                      1111 1010 xxxx xxxx 1111 xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xff00f000, 0xfa00f000, t32_table_1111_1010___1111),
+        /*
+         * Multiply, multiply accumulate, and absolute difference
+         *                      1111 1011 0xxx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xff800000, 0xfb000000, t32_table_1111_1011_0),
+        /*
+         * Long multiply, long multiply accumulate, and divide
+         *                      1111 1011 1xxx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xff800000, 0xfb800000, t32_table_1111_1011_1),
+        /*
+         * Coprocessor instructions
+         *                      1111 11xx xxxx xxxx xxxx xxxx xxxx xxxx
+         */
+        DECODE_END
+};
+#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
+EXPORT_SYMBOL_GPL(probes_decode_thumb32_table);
+#endif
+static const union decode_item t16_table_1011[] = {
+        /* Miscellaneous 16-bit instructions                */
+        /* ADD (SP plus immediate)      1011 0000 0xxx xxxx */
+        /* SUB (SP minus immediate)     1011 0000 1xxx xxxx */
+        DECODE_SIMULATE (0xff00, 0xb000, PROBES_T16_ADD_SP),
+        /* CBZ                          1011 00x1 xxxx xxxx */
+        /* CBNZ                         1011 10x1 xxxx xxxx */
+        DECODE_SIMULATE (0xf500, 0xb100, PROBES_T16_CBZ),
+        /* SXTH                         1011 0010 00xx xxxx */
+        /* SXTB                         1011 0010 01xx xxxx */
+        /* UXTH                         1011 0010 10xx xxxx */
+        /* UXTB                         1011 0010 11xx xxxx */
+        /* REV                          1011 1010 00xx xxxx */
+        /* REV16                        1011 1010 01xx xxxx */
+        /* ???                          1011 1010 10xx xxxx */
+        /* REVSH                        1011 1010 11xx xxxx */
+        DECODE_REJECT   (0xffc0, 0xba80),
+        DECODE_EMULATE  (0xf500, 0xb000, PROBES_T16_SIGN_EXTEND),
+        /* PUSH                         1011 010x xxxx xxxx */
+        DECODE_CUSTOM   (0xfe00, 0xb400, PROBES_T16_PUSH),
+        /* POP                          1011 110x xxxx xxxx */
+        DECODE_CUSTOM   (0xfe00, 0xbc00, PROBES_T16_POP),
+        /*
+         * If-Then, and hints
+         *                              1011 1111 xxxx xxxx
+         */
+        /* YIELD                        1011 1111 0001 0000 */
+        DECODE_OR       (0xffff, 0xbf10),
+        /* SEV                          1011 1111 0100 0000 */
+        DECODE_EMULATE  (0xffff, 0xbf40, PROBES_T16_SEV),
+        /* NOP                          1011 1111 0000 0000 */
+        /* WFE                          1011 1111 0010 0000 */
+        /* WFI                          1011 1111 0011 0000 */
+        DECODE_SIMULATE (0xffcf, 0xbf00, PROBES_T16_WFE),
+        /* Unassigned hints             1011 1111 xxxx 0000 */
+        DECODE_REJECT   (0xff0f, 0xbf00),
+        /* IT                           1011 1111 xxxx xxxx */
+        DECODE_CUSTOM   (0xff00, 0xbf00, PROBES_T16_IT),
+        /* SETEND                       1011 0110 010x xxxx */
+        /* CPS                          1011 0110 011x xxxx */
+        /* BKPT                         1011 1110 xxxx xxxx */
+        /* And unallocated instructions...                  */
+        DECODE_END
+};
+const union decode_item probes_decode_thumb16_table[] = {
+        /*
+         * Shift (immediate), add, subtract, move, and compare
+         *                              00xx xxxx xxxx xxxx
+         */
+        /* CMP (immediate)              0010 1xxx xxxx xxxx */
+        DECODE_EMULATE  (0xf800, 0x2800, PROBES_T16_CMP),
+        /* ADD (register)               0001 100x xxxx xxxx */
+        /* SUB (register)               0001 101x xxxx xxxx */
+        /* LSL (immediate)              0000 0xxx xxxx xxxx */
+        /* LSR (immediate)              0000 1xxx xxxx xxxx */
+        /* ASR (immediate)              0001 0xxx xxxx xxxx */
+        /* ADD (immediate, Thumb)       0001 110x xxxx xxxx */
+        /* SUB (immediate, Thumb)       0001 111x xxxx xxxx */
+        /* MOV (immediate)              0010 0xxx xxxx xxxx */
+        /* ADD (immediate, Thumb)       0011 0xxx xxxx xxxx */
+        /* SUB (immediate, Thumb)       0011 1xxx xxxx xxxx */
+        DECODE_EMULATE  (0xc000, 0x0000, PROBES_T16_ADDSUB),
+        /*
+         * 16-bit Thumb data-processing instructions
+         *                              0100 00xx xxxx xxxx
+         */
+        /* TST (register)               0100 0010 00xx xxxx */
+        DECODE_EMULATE  (0xffc0, 0x4200, PROBES_T16_CMP),
+        /* CMP (register)               0100 0010 10xx xxxx */
+        /* CMN (register)               0100 0010 11xx xxxx */
+        DECODE_EMULATE  (0xff80, 0x4280, PROBES_T16_CMP),
+        /* AND (register)               0100 0000 00xx xxxx */
+        /* EOR (register)               0100 0000 01xx xxxx */
+        /* LSL (register)               0100 0000 10xx xxxx */
+        /* LSR (register)               0100 0000 11xx xxxx */
+        /* ASR (register)               0100 0001 00xx xxxx */
+        /* ADC (register)               0100 0001 01xx xxxx */
+        /* SBC (register)               0100 0001 10xx xxxx */
+        /* ROR (register)               0100 0001 11xx xxxx */
+        /* RSB (immediate)              0100 0010 01xx xxxx */
+        /* ORR (register)               0100 0011 00xx xxxx */
+        /* MUL                          0100 0011 00xx xxxx */
+        /* BIC (register)               0100 0011 10xx xxxx */
+        /* MVN (register)               0100 0011 10xx xxxx */
+        DECODE_EMULATE  (0xfc00, 0x4000, PROBES_T16_LOGICAL),
+        /*
+         * Special data instructions and branch and exchange
+         *                              0100 01xx xxxx xxxx
+         */
+        /* BLX pc                       0100 0111 1111 1xxx */
+        DECODE_REJECT   (0xfff8, 0x47f8),
+        /* BX (register)                0100 0111 0xxx xxxx */
+        /* BLX (register)               0100 0111 1xxx xxxx */
+        DECODE_SIMULATE (0xff00, 0x4700, PROBES_T16_BLX),
+        /* ADD pc, pc                   0100 0100 1111 1111 */
+        DECODE_REJECT   (0xffff, 0x44ff),
+        /* ADD (register)               0100 0100 xxxx xxxx */
+        /* CMP (register)               0100 0101 xxxx xxxx */
+        /* MOV (register)               0100 0110 xxxx xxxx */
+        DECODE_CUSTOM   (0xfc00, 0x4400, PROBES_T16_HIREGOPS),
+        /*
+         * Load from Literal Pool
+         * LDR (literal)                0100 1xxx xxxx xxxx
+         */
+        DECODE_SIMULATE (0xf800, 0x4800, PROBES_T16_LDR_LIT),
+        /*
+         * 16-bit Thumb Load/store instructions
+         *                              0101 xxxx xxxx xxxx
+         *                              011x xxxx xxxx xxxx
+         *                              100x xxxx xxxx xxxx
+         */
+        /* STR (register)               0101 000x xxxx xxxx */
+        /* STRH (register)              0101 001x xxxx xxxx */
+        /* STRB (register)              0101 010x xxxx xxxx */
+        /* LDRSB (register)             0101 011x xxxx xxxx */
+        /* LDR (register)               0101 100x xxxx xxxx */
+        /* LDRH (register)              0101 101x xxxx xxxx */
+        /* LDRB (register)              0101 110x xxxx xxxx */
+        /* LDRSH (register)             0101 111x xxxx xxxx */
+        /* STR (immediate, Thumb)       0110 0xxx xxxx xxxx */
+        /* LDR (immediate, Thumb)       0110 1xxx xxxx xxxx */
+        /* STRB (immediate, Thumb)      0111 0xxx xxxx xxxx */
+        /* LDRB (immediate, Thumb)      0111 1xxx xxxx xxxx */
+        DECODE_EMULATE  (0xc000, 0x4000, PROBES_T16_LDRHSTRH),
+        /* STRH (immediate, Thumb)      1000 0xxx xxxx xxxx */
+        /* LDRH (immediate, Thumb)      1000 1xxx xxxx xxxx */
+        DECODE_EMULATE  (0xf000, 0x8000, PROBES_T16_LDRHSTRH),
+        /* STR (immediate, Thumb)       1001 0xxx xxxx xxxx */
+        /* LDR (immediate, Thumb)       1001 1xxx xxxx xxxx */
+        DECODE_SIMULATE (0xf000, 0x9000, PROBES_T16_LDRSTR),
+        /*
+         * Generate PC-/SP-relative address
+         * ADR (literal)                1010 0xxx xxxx xxxx
+         * ADD (SP plus immediate)      1010 1xxx xxxx xxxx
+         */
+        DECODE_SIMULATE (0xf000, 0xa000, PROBES_T16_ADR),
+        /*
+         * Miscellaneous 16-bit instructions
+         *                              1011 xxxx xxxx xxxx
+         */
+        DECODE_TABLE    (0xf000, 0xb000, t16_table_1011),
+        /* STM                          1100 0xxx xxxx xxxx */
+        /* LDM                          1100 1xxx xxxx xxxx */
+        DECODE_EMULATE  (0xf000, 0xc000, PROBES_T16_LDMSTM),
+        /*
+         * Conditional branch, and Supervisor Call
+         */
+        /* Permanently UNDEFINED        1101 1110 xxxx xxxx */
+        /* SVC                          1101 1111 xxxx xxxx */
+        DECODE_REJECT   (0xfe00, 0xde00),
+        /* Conditional branch           1101 xxxx xxxx xxxx */
+        DECODE_CUSTOM   (0xf000, 0xd000, PROBES_T16_BRANCH_COND),
+        /*
+         * Unconditional branch
+         * B                            1110 0xxx xxxx xxxx
+         */
+        DECODE_SIMULATE (0xf800, 0xe000, PROBES_T16_BRANCH),
+        DECODE_END
+};
+#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
+EXPORT_SYMBOL_GPL(probes_decode_thumb16_table);
+#endif
+static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
+{
+        if (unlikely(in_it_block(cpsr)))
+                return probes_condition_checks[current_cond(cpsr)](cpsr);
+        return true;
+}
+static void __kprobes thumb16_singlestep(probes_opcode_t opcode,
+                struct arch_probes_insn *asi,
+                struct pt_regs *regs)
+{
+        regs->ARM_pc += 2;
+        asi->insn_handler(opcode, asi, regs);
+        regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
+}
+static void __kprobes thumb32_singlestep(probes_opcode_t opcode,
+                struct arch_probes_insn *asi,
+                struct pt_regs *regs)
+{
+        regs->ARM_pc += 4;
+        asi->insn_handler(opcode, asi, regs);
+        regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
+}
+enum probes_insn __kprobes
+thumb16_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
+                           bool emulate, const union decode_action *actions)
+{
+        asi->insn_singlestep = thumb16_singlestep;
+        asi->insn_check_cc = thumb_check_cc;
+        return probes_decode_insn(insn, asi, probes_decode_thumb16_table, true,
+                                  emulate, actions);
+}
+enum probes_insn __kprobes
+thumb32_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
+                           bool emulate, const union decode_action *actions)
+{
+        asi->insn_singlestep = thumb32_singlestep;
+        asi->insn_check_cc = thumb_check_cc;
+        return probes_decode_insn(insn, asi, probes_decode_thumb32_table, true,
+                                  emulate, actions);
+}
diff --git a/arch/arm/kernel/probes-thumb.h b/arch/arm/kernel/probes-thumb.h
new file mode 100644
index 000000000000..7c6f6ebe514f
--- /dev/null
+++ b/arch/arm/kernel/probes-thumb.h
@@ -0,0 +1,97 @@
+/*
+ * arch/arm/kernel/probes-thumb.h
+ *
+ * Copyright 2013 Linaro Ltd.
+ * Written by: David A. Long
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef _ARM_KERNEL_PROBES_THUMB_H
+#define  _ARM_KERNEL_PROBES_THUMB_H
+/*
+ * True if current instruction is in an IT block.
+ */
+#define in_it_block(cpsr)       ((cpsr & 0x06000c00) != 0x00000000)
+/*
+ * Return the condition code to check for the currently executing instruction.
+ * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
+ * in_it_block returns true.
+ */
+#define current_cond(cpsr)      ((cpsr >> 12) & 0xf)
+enum probes_t32_action {
+        PROBES_T32_EMULATE_NONE,
+        PROBES_T32_SIMULATE_NOP,
+        PROBES_T32_LDMSTM,
+        PROBES_T32_LDRDSTRD,
+        PROBES_T32_TABLE_BRANCH,
+        PROBES_T32_TST,
+        PROBES_T32_CMP,
+        PROBES_T32_MOV,
+        PROBES_T32_ADDSUB,
+        PROBES_T32_LOGICAL,
+        PROBES_T32_ADDWSUBW_PC,
+        PROBES_T32_ADDWSUBW,
+        PROBES_T32_MOVW,
+        PROBES_T32_SAT,
+        PROBES_T32_BITFIELD,
+        PROBES_T32_SEV,
+        PROBES_T32_WFE,
+        PROBES_T32_MRS,
+        PROBES_T32_BRANCH_COND,
+        PROBES_T32_BRANCH,
+        PROBES_T32_PLDI,
+        PROBES_T32_LDR_LIT,
+        PROBES_T32_LDRSTR,
+        PROBES_T32_SIGN_EXTEND,
+        PROBES_T32_MEDIA,
+        PROBES_T32_REVERSE,
+        PROBES_T32_MUL_ADD,
+        PROBES_T32_MUL_ADD2,
+        PROBES_T32_MUL_ADD_LONG,
+        NUM_PROBES_T32_ACTIONS
+};
+enum probes_t16_action {
+        PROBES_T16_ADD_SP,
+        PROBES_T16_CBZ,
+        PROBES_T16_SIGN_EXTEND,
+        PROBES_T16_PUSH,
+        PROBES_T16_POP,
+        PROBES_T16_SEV,
+        PROBES_T16_WFE,
+        PROBES_T16_IT,
+        PROBES_T16_CMP,
+        PROBES_T16_ADDSUB,
+        PROBES_T16_LOGICAL,
+        PROBES_T16_BLX,
+        PROBES_T16_HIREGOPS,
+        PROBES_T16_LDR_LIT,
+        PROBES_T16_LDRHSTRH,
+        PROBES_T16_LDRSTR,
+        PROBES_T16_ADR,
+        PROBES_T16_LDMSTM,
+        PROBES_T16_BRANCH_COND,
+        PROBES_T16_BRANCH,
+        NUM_PROBES_T16_ACTIONS
+};
+extern const union decode_item probes_decode_thumb32_table[];
+extern const union decode_item probes_decode_thumb16_table[];
+enum probes_insn __kprobes
+thumb16_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
+                bool emulate, const union decode_action *actions);
+enum probes_insn __kprobes
+thumb32_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
+                bool emulate, const union decode_action *actions);
+#endif
diff --git a/arch/arm/kernel/probes.c b/arch/arm/kernel/probes.c
new file mode 100644
index 000000000000..a8ab540d7e73
--- /dev/null
+++ b/arch/arm/kernel/probes.c
@@ -0,0 +1,456 @@
+/*
+ * arch/arm/kernel/probes.c
+ *
+ * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
+ *
+ * Some contents moved here from arch/arm/include/asm/kprobes-arm.c which is
+ * Copyright (C) 2006, 2007 Motorola Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <asm/system_info.h>
+#include <asm/ptrace.h>
+#include <linux/bug.h>
+#include "probes.h"
+#ifndef find_str_pc_offset
+/*
+ * For STR and STM instructions, an ARM core may choose to use either
+ * a +8 or a +12 displacement from the current instruction's address.
+ * Whichever value is chosen for a given core, it must be the same for
+ * both instructions and may not change.  This function measures it.
+ */
+int str_pc_offset;
+void __init find_str_pc_offset(void)
+{
+        int addr, scratch, ret;
+        __asm__ (
+                "sub    %[ret], pc, #4          \n\t"
+                "str    pc, %[addr]             \n\t"
+                "ldr    %[scr], %[addr]         \n\t"
+                "sub    %[ret], %[scr], %[ret]  \n\t"
+                : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
+        str_pc_offset = ret;
+}
+#endif /* !find_str_pc_offset */
+#ifndef test_load_write_pc_interworking
+bool load_write_pc_interworks;
+void __init test_load_write_pc_interworking(void)
+{
+        int arch = cpu_architecture();
+        BUG_ON(arch == CPU_ARCH_UNKNOWN);
+        load_write_pc_interworks = arch >= CPU_ARCH_ARMv5T;
+}
+#endif /* !test_load_write_pc_interworking */
+#ifndef test_alu_write_pc_interworking
+bool alu_write_pc_interworks;
+void __init test_alu_write_pc_interworking(void)
+{
+        int arch = cpu_architecture();
+        BUG_ON(arch == CPU_ARCH_UNKNOWN);
+        alu_write_pc_interworks = arch >= CPU_ARCH_ARMv7;
+}
+#endif /* !test_alu_write_pc_interworking */
+void __init arm_probes_decode_init(void)
+{
+        find_str_pc_offset();
+        test_load_write_pc_interworking();
+        test_alu_write_pc_interworking();
+}
+static unsigned long __kprobes __check_eq(unsigned long cpsr)
+{
+        return cpsr & PSR_Z_BIT;
+}
+static unsigned long __kprobes __check_ne(unsigned long cpsr)
+{
+        return (~cpsr) & PSR_Z_BIT;
+}
+static unsigned long __kprobes __check_cs(unsigned long cpsr)
+{
+        return cpsr & PSR_C_BIT;
+}
+static unsigned long __kprobes __check_cc(unsigned long cpsr)
+{
+        return (~cpsr) & PSR_C_BIT;
+}
+static unsigned long __kprobes __check_mi(unsigned long cpsr)
+{
+        return cpsr & PSR_N_BIT;
+}
+static unsigned long __kprobes __check_pl(unsigned long cpsr)
+{
+        return (~cpsr) & PSR_N_BIT;
+}
+static unsigned long __kprobes __check_vs(unsigned long cpsr)
+{
+        return cpsr & PSR_V_BIT;
+}
+static unsigned long __kprobes __check_vc(unsigned long cpsr)
+{
+        return (~cpsr) & PSR_V_BIT;
+}
+static unsigned long __kprobes __check_hi(unsigned long cpsr)
+{
+        cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
+        return cpsr & PSR_C_BIT;
+}
+static unsigned long __kprobes __check_ls(unsigned long cpsr)
+{
+        cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
+        return (~cpsr) & PSR_C_BIT;
+}
+static unsigned long __kprobes __check_ge(unsigned long cpsr)
+{
+        cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+        return (~cpsr) & PSR_N_BIT;
+}
+static unsigned long __kprobes __check_lt(unsigned long cpsr)
+{
+        cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+        return cpsr & PSR_N_BIT;
+}
+static unsigned long __kprobes __check_gt(unsigned long cpsr)
+{
+        unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+        temp |= (cpsr << 1);                     /* PSR_N_BIT |= PSR_Z_BIT */
+        return (~temp) & PSR_N_BIT;
+}
+static unsigned long __kprobes __check_le(unsigned long cpsr)
+{
+        unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
+        temp |= (cpsr << 1);                     /* PSR_N_BIT |= PSR_Z_BIT */
+        return temp & PSR_N_BIT;
+}
+static unsigned long __kprobes __check_al(unsigned long cpsr)
+{
+        return true;
+}
+probes_check_cc * const probes_condition_checks[16] = {
+        &__check_eq, &__check_ne, &__check_cs, &__check_cc,
+        &__check_mi, &__check_pl, &__check_vs, &__check_vc,
+        &__check_hi, &__check_ls, &__check_ge, &__check_lt,
+        &__check_gt, &__check_le, &__check_al, &__check_al
+};
+void __kprobes probes_simulate_nop(probes_opcode_t opcode,
+        struct arch_probes_insn *asi,
+        struct pt_regs *regs)
+{
+}
+void __kprobes probes_emulate_none(probes_opcode_t opcode,
+        struct arch_probes_insn *asi,
+        struct pt_regs *regs)
+{
+        asi->insn_fn();
+}
+/*
+ * Prepare an instruction slot to receive an instruction for emulating.
+ * This is done by placing a subroutine return after the location where the
+ * instruction will be placed. We also modify ARM instructions to be
+ * unconditional as the condition code will already be checked before any
+ * emulation handler is called.
+ */
+static probes_opcode_t __kprobes
+prepare_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
+                      bool thumb)
+{
+#ifdef CONFIG_THUMB2_KERNEL
+        if (thumb) {
+                u16 *thumb_insn = (u16 *)asi->insn;
+                /* Thumb bx lr */
+                thumb_insn[1] = __opcode_to_mem_thumb16(0x4770);
+                thumb_insn[2] = __opcode_to_mem_thumb16(0x4770);
+                return insn;
+        }
+        asi->insn[1] = __opcode_to_mem_arm(0xe12fff1e); /* ARM bx lr */
+#else
+        asi->insn[1] = __opcode_to_mem_arm(0xe1a0f00e); /* mov pc, lr */
+#endif
+        /* Make an ARM instruction unconditional */
+        if (insn < 0xe0000000)
+                insn = (insn | 0xe0000000) & ~0x10000000;
+        return insn;
+}
+/*
+ * Write a (probably modified) instruction into the slot previously prepared by
+ * prepare_emulated_insn
+ */
+static void  __kprobes
+set_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
+                  bool thumb)
+{
+#ifdef CONFIG_THUMB2_KERNEL
+        if (thumb) {
+                u16 *ip = (u16 *)asi->insn;
+                if (is_wide_instruction(insn))
+                        *ip++ = __opcode_to_mem_thumb16(insn >> 16);
+                *ip++ = __opcode_to_mem_thumb16(insn);
+                return;
+        }
+#endif
+        asi->insn[0] = __opcode_to_mem_arm(insn);
+}
+/*
+ * When we modify the register numbers encoded in an instruction to be emulated,
+ * the new values come from this define. For ARM and 32-bit Thumb instructions
+ * this gives...
+ *
+ *      bit position      16  12   8   4   0
+ *      ---------------+---+---+---+---+---+
+ *      register         r2  r0  r1  --  r3
+ */
+#define INSN_NEW_BITS           0x00020103
+/* Each nibble has same value as that at INSN_NEW_BITS bit 16 */
+#define INSN_SAMEAS16_BITS      0x22222222
+/*
+ * Validate and modify each of the registers encoded in an instruction.
+ *
+ * Each nibble in regs contains a value from enum decode_reg_type. For each
+ * non-zero value, the corresponding nibble in pinsn is validated and modified
+ * according to the type.
+ */
+static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs, bool modify)
+{
+        probes_opcode_t insn = *pinsn;
+        probes_opcode_t mask = 0xf; /* Start at least significant nibble */
+        for (; regs != 0; regs >>= 4, mask <<= 4) {
+                probes_opcode_t new_bits = INSN_NEW_BITS;
+                switch (regs & 0xf) {
+                case REG_TYPE_NONE:
+                        /* Nibble not a register, skip to next */
+                        continue;
+                case REG_TYPE_ANY:
+                        /* Any register is allowed */
+                        break;
+                case REG_TYPE_SAMEAS16:
+                        /* Replace register with same as at bit position 16 */
+                        new_bits = INSN_SAMEAS16_BITS;
+                        break;
+                case REG_TYPE_SP:
+                        /* Only allow SP (R13) */
+                        if ((insn ^ 0xdddddddd) & mask)
+                                goto reject;
+                        break;
+                case REG_TYPE_PC:
+                        /* Only allow PC (R15) */
+                        if ((insn ^ 0xffffffff) & mask)
+                                goto reject;
+                        break;
+                case REG_TYPE_NOSP:
+                        /* Reject SP (R13) */
+                        if (((insn ^ 0xdddddddd) & mask) == 0)
+                                goto reject;
+                        break;
+                case REG_TYPE_NOSPPC:
+                case REG_TYPE_NOSPPCX:
+                        /* Reject SP and PC (R13 and R15) */
+                        if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0)
+                                goto reject;
+                        break;
+                case REG_TYPE_NOPCWB:
+                        if (!is_writeback(insn))
+                                break; /* No writeback, so any register is OK */
+                        /* fall through... */
+                case REG_TYPE_NOPC:
+                case REG_TYPE_NOPCX:
+                        /* Reject PC (R15) */
+                        if (((insn ^ 0xffffffff) & mask) == 0)
+                                goto reject;
+                        break;
+                }
+                /* Replace value of nibble with new register number... */
+                insn &= ~mask;
+                insn |= new_bits & mask;
+        }
+        if (modify)
+                *pinsn = insn;
+        return true;
+reject:
+        return false;
+}
+static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
+        [DECODE_TYPE_TABLE]     = sizeof(struct decode_table),
+        [DECODE_TYPE_CUSTOM]    = sizeof(struct decode_custom),
+        [DECODE_TYPE_SIMULATE]  = sizeof(struct decode_simulate),
+        [DECODE_TYPE_EMULATE]   = sizeof(struct decode_emulate),
+        [DECODE_TYPE_OR]        = sizeof(struct decode_or),
+        [DECODE_TYPE_REJECT]    = sizeof(struct decode_reject)
+};
+/*
+ * probes_decode_insn operates on data tables in order to decode an ARM
+ * architecture instruction onto which a kprobe has been placed.
+ *
+ * These instruction decoding tables are a concatenation of entries each
+ * of which consist of one of the following structs:
+ *
+ *      decode_table
+ *      decode_custom
+ *      decode_simulate
+ *      decode_emulate
+ *      decode_or
+ *      decode_reject
+ *
+ * Each of these starts with a struct decode_header which has the following
+ * fields:
+ *
+ *      type_regs
+ *      mask
+ *      value
+ *
+ * The least significant DECODE_TYPE_BITS of type_regs contains a value
+ * from enum decode_type, this indicates which of the decode_* structs
+ * the entry contains. The value DECODE_TYPE_END indicates the end of the
+ * table.
+ *
+ * When the table is parsed, each entry is checked in turn to see if it
+ * matches the instruction to be decoded using the test:
+ *
+ *      (insn & mask) == value
+ *
+ * If no match is found before the end of the table is reached then decoding
+ * fails with INSN_REJECTED.
+ *
+ * When a match is found, decode_regs() is called to validate and modify each
+ * of the registers encoded in the instruction; the data it uses to do this
+ * is (type_regs >> DECODE_TYPE_BITS). A validation failure will cause decoding
+ * to fail with INSN_REJECTED.
+ *
+ * Once the instruction has passed the above tests, further processing
+ * depends on the type of the table entry's decode struct.
+ *
+ */
+int __kprobes
+probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
+                   const union decode_item *table, bool thumb,
+                   bool emulate, const union decode_action *actions)
+{
+        const struct decode_header *h = (struct decode_header *)table;
+        const struct decode_header *next;
+        bool matched = false;
+        if (emulate)
+                insn = prepare_emulated_insn(insn, asi, thumb);
+        for (;; h = next) {
+                enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
+                u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
+                if (type == DECODE_TYPE_END)
+                        return INSN_REJECTED;
+                next = (struct decode_header *)
+                                ((uintptr_t)h + decode_struct_sizes[type]);
+                if (!matched && (insn & h->mask.bits) != h->value.bits)
+                        continue;
+                if (!decode_regs(&insn, regs, emulate))
+                        return INSN_REJECTED;
+                switch (type) {
+                case DECODE_TYPE_TABLE: {
+                        struct decode_table *d = (struct decode_table *)h;
+                        next = (struct decode_header *)d->table.table;
+                        break;
+                }
+                case DECODE_TYPE_CUSTOM: {
+                        struct decode_custom *d = (struct decode_custom *)h;
+                        return actions[d->decoder.action].decoder(insn, asi, h);
+                }
+                case DECODE_TYPE_SIMULATE: {
+                        struct decode_simulate *d = (struct decode_simulate *)h;
+                        asi->insn_handler = actions[d->handler.action].handler;
+                        return INSN_GOOD_NO_SLOT;
+                }
+                case DECODE_TYPE_EMULATE: {
+                        struct decode_emulate *d = (struct decode_emulate *)h;
+                        if (!emulate)
+                                return actions[d->handler.action].decoder(insn,
+                                        asi, h);
+                        asi->insn_handler = actions[d->handler.action].handler;
+                        set_emulated_insn(insn, asi, thumb);
+                        return INSN_GOOD;
+                }
+                case DECODE_TYPE_OR:
+                        matched = true;
+                        break;
+                case DECODE_TYPE_REJECT:
+                default:
+                        return INSN_REJECTED;
+                }
+        }
+}
diff --git a/arch/arm/kernel/probes.h b/arch/arm/kernel/probes.h
new file mode 100644
index 000000000000..dba9f2466a93
--- /dev/null
+++ b/arch/arm/kernel/probes.h
@@ -0,0 +1,407 @@
+/*
+ * arch/arm/kernel/probes.h
+ *
+ * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
+ *
+ * Some contents moved here from arch/arm/include/asm/kprobes.h which is
+ * Copyright (C) 2006, 2007 Motorola Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+#ifndef _ARM_KERNEL_PROBES_H
+#define  _ARM_KERNEL_PROBES_H
+#include <linux/types.h>
+#include <linux/stddef.h>
+#include <asm/probes.h>
+void __init arm_probes_decode_init(void);
+extern probes_check_cc * const probes_condition_checks[16];
+#if __LINUX_ARM_ARCH__ >= 7
+/* str_pc_offset is architecturally defined from ARMv7 onwards */
+#define str_pc_offset 8
+#define find_str_pc_offset()
+#else /* __LINUX_ARM_ARCH__ < 7 */
+/* We need a run-time check to determine str_pc_offset */
+extern int str_pc_offset;
+void __init find_str_pc_offset(void);
+#endif
+/*
+ * Update ITSTATE after normal execution of an IT block instruction.
+ *
+ * The 8 IT state bits are split into two parts in CPSR:
+ *      ITSTATE<1:0> are in CPSR<26:25>
+ *      ITSTATE<7:2> are in CPSR<15:10>
+ */
+static inline unsigned long it_advance(unsigned long cpsr)
+        {
+        if ((cpsr & 0x06000400) == 0) {
+                /* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */
+                cpsr &= ~PSR_IT_MASK;
+        } else {
+                /* We need to shift left ITSTATE<4:0> */
+                const unsigned long mask = 0x06001c00;  /* Mask ITSTATE<4:0> */
+                unsigned long it = cpsr & mask;
+                it <<= 1;
+                it |= it >> (27 - 10);  /* Carry ITSTATE<2> to correct place */
+                it &= mask;
+                cpsr &= ~mask;
+                cpsr |= it;
+        }
+        return cpsr;
+}
+static inline void __kprobes bx_write_pc(long pcv, struct pt_regs *regs)
+{
+        long cpsr = regs->ARM_cpsr;
+        if (pcv & 0x1) {
+                cpsr |= PSR_T_BIT;
+                pcv &= ~0x1;
+        } else {
+                cpsr &= ~PSR_T_BIT;
+                pcv &= ~0x2;    /* Avoid UNPREDICTABLE address allignment */
+        }
+        regs->ARM_cpsr = cpsr;
+        regs->ARM_pc = pcv;
+}
+#if __LINUX_ARM_ARCH__ >= 6
+/* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */
+#define load_write_pc_interworks true
+#define test_load_write_pc_interworking()
+#else /* __LINUX_ARM_ARCH__ < 6 */
+/* We need run-time testing to determine if load_write_pc() should interwork. */
+extern bool load_write_pc_interworks;
+void __init test_load_write_pc_interworking(void);
+#endif
+static inline void __kprobes load_write_pc(long pcv, struct pt_regs *regs)
+{
+        if (load_write_pc_interworks)
+                bx_write_pc(pcv, regs);
+        else
+                regs->ARM_pc = pcv;
+}
+#if __LINUX_ARM_ARCH__ >= 7
+#define alu_write_pc_interworks true
+#define test_alu_write_pc_interworking()
+#elif __LINUX_ARM_ARCH__ <= 5
+/* Kernels built for <= ARMv5 should never run on >= ARMv6 hardware, so... */
+#define alu_write_pc_interworks false
+#define test_alu_write_pc_interworking()
+#else /* __LINUX_ARM_ARCH__ == 6 */
+/* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */
+extern bool alu_write_pc_interworks;
+void __init test_alu_write_pc_interworking(void);
+#endif /* __LINUX_ARM_ARCH__ == 6 */
+static inline void __kprobes alu_write_pc(long pcv, struct pt_regs *regs)
+{
+        if (alu_write_pc_interworks)
+                bx_write_pc(pcv, regs);
+        else
+                regs->ARM_pc = pcv;
+}
+/*
+ * Test if load/store instructions writeback the address register.
+ * if P (bit 24) == 0 or W (bit 21) == 1
+ */
+#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
+/*
+ * The following definitions and macros are used to build instruction
+ * decoding tables for use by probes_decode_insn.
+ *
+ * These tables are a concatenation of entries each of which consist of one of
+ * the decode_* structs. All of the fields in every type of decode structure
+ * are of the union type decode_item, therefore the entire decode table can be
+ * viewed as an array of these and declared like:
+ *
+ *      static const union decode_item table_name[] = {};
+ *
+ * In order to construct each entry in the table, macros are used to
+ * initialise a number of sequential decode_item values in a layout which
+ * matches the relevant struct. E.g. DECODE_SIMULATE initialise a struct
+ * decode_simulate by initialising four decode_item objects like this...
+ *
+ *      {.bits = _type},
+ *      {.bits = _mask},
+ *      {.bits = _value},
+ *      {.action = _handler},
+ *
+ * Initialising a specified member of the union means that the compiler
+ * will produce a warning if the argument is of an incorrect type.
+ *
+ * Below is a list of each of the macros used to initialise entries and a
+ * description of the action performed when that entry is matched to an
+ * instruction. A match is found when (instruction & mask) == value.
+ *
+ * DECODE_TABLE(mask, value, table)
+ *      Instruction decoding jumps to parsing the new sub-table 'table'.
+ *
+ * DECODE_CUSTOM(mask, value, decoder)
+ *      The value of 'decoder' is used as an index into the array of
+ *      action functions, and the retrieved decoder function is invoked
+ *      to complete decoding of the instruction.
+ *
+ * DECODE_SIMULATE(mask, value, handler)
+ *      The probes instruction handler is set to the value found by
+ *      indexing into the action array using the value of 'handler'. This
+ *      will be used to simulate the instruction when the probe is hit.
+ *      Decoding returns with INSN_GOOD_NO_SLOT.
+ *
+ * DECODE_EMULATE(mask, value, handler)
+ *      The probes instruction handler is set to the value found by
+ *      indexing into the action array using the value of 'handler'. This
+ *      will be used to emulate the instruction when the probe is hit. The
+ *      modified instruction (see below) is placed in the probes instruction
+ *      slot so it may be called by the emulation code. Decoding returns
+ *      with INSN_GOOD.
+ *
+ * DECODE_REJECT(mask, value)
+ *      Instruction decoding fails with INSN_REJECTED
+ *
+ * DECODE_OR(mask, value)
+ *      This allows the mask/value test of multiple table entries to be
+ *      logically ORed. Once an 'or' entry is matched the decoding action to
+ *      be performed is that of the next entry which isn't an 'or'. E.g.
+ *
+ *              DECODE_OR       (mask1, value1)
+ *              DECODE_OR       (mask2, value2)
+ *              DECODE_SIMULATE (mask3, value3, simulation_handler)
+ *
+ *      This means that if any of the three mask/value pairs match the
+ *      instruction being decoded, then 'simulation_handler' will be used
+ *      for it.
+ *
+ * Both the SIMULATE and EMULATE macros have a second form which take an
+ * additional 'regs' argument.
+ *
+ *      DECODE_SIMULATEX(mask, value, handler, regs)
+ *      DECODE_EMULATEX (mask, value, handler, regs)
+ *
+ * These are used to specify what kind of CPU register is encoded in each of the
+ * least significant 5 nibbles of the instruction being decoded. The regs value
+ * is specified using the REGS macro, this takes any of the REG_TYPE_* values
+ * from enum decode_reg_type as arguments; only the '*' part of the name is
+ * given. E.g.
+ *
+ *      REGS(0, ANY, NOPC, 0, ANY)
+ *
+ * This indicates an instruction is encoded like:
+ *
+ *      bits 19..16     ignore
+ *      bits 15..12     any register allowed here
+ *      bits 11.. 8     any register except PC allowed here
+ *      bits  7.. 4     ignore
+ *      bits  3.. 0     any register allowed here
+ *
+ * This register specification is checked after a decode table entry is found to
+ * match an instruction (through the mask/value test). Any invalid register then
+ * found in the instruction will cause decoding to fail with INSN_REJECTED. In
+ * the above example this would happen if bits 11..8 of the instruction were
+ * 1111, indicating R15 or PC.
+ *
+ * As well as checking for legal combinations of registers, this data is also
+ * used to modify the registers encoded in the instructions so that an
+ * emulation routines can use it. (See decode_regs() and INSN_NEW_BITS.)
+ *
+ * Here is a real example which matches ARM instructions of the form
+ * "AND <Rd>,<Rn>,<Rm>,<shift> <Rs>"
+ *
+ *      DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
+ *                                               REGS(ANY, ANY, NOPC, 0, ANY)),
+ *                                                    ^    ^    ^        ^
+ *                                                    Rn   Rd   Rs       Rm
+ *
+ * Decoding the instruction "AND R4, R5, R6, ASL R15" will be rejected because
+ * Rs == R15
+ *
+ * Decoding the instruction "AND R4, R5, R6, ASL R7" will be accepted and the
+ * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into
+ * the kprobes instruction slot. This can then be called later by the handler
+ * function emulate_rd12rn16rm0rs8_rwflags (a pointer to which is retrieved from
+ * the indicated slot in the action array), in order to simulate the instruction.
+ */
+enum decode_type {
+        DECODE_TYPE_END,
+        DECODE_TYPE_TABLE,
+        DECODE_TYPE_CUSTOM,
+        DECODE_TYPE_SIMULATE,
+        DECODE_TYPE_EMULATE,
+        DECODE_TYPE_OR,
+        DECODE_TYPE_REJECT,
+        NUM_DECODE_TYPES /* Must be last enum */
+};
+#define DECODE_TYPE_BITS        4
+#define DECODE_TYPE_MASK        ((1 << DECODE_TYPE_BITS) - 1)
+enum decode_reg_type {
+        REG_TYPE_NONE = 0, /* Not a register, ignore */
+        REG_TYPE_ANY,      /* Any register allowed */
+        REG_TYPE_SAMEAS16, /* Register should be same as that at bits 19..16 */
+        REG_TYPE_SP,       /* Register must be SP */
+        REG_TYPE_PC,       /* Register must be PC */
+        REG_TYPE_NOSP,     /* Register must not be SP */
+        REG_TYPE_NOSPPC,   /* Register must not be SP or PC */
+        REG_TYPE_NOPC,     /* Register must not be PC */
+        REG_TYPE_NOPCWB,   /* No PC if load/store write-back flag also set */
+        /* The following types are used when the encoding for PC indicates
+         * another instruction form. This distiction only matters for test
+         * case coverage checks.
+         */
+        REG_TYPE_NOPCX,    /* Register must not be PC */
+        REG_TYPE_NOSPPCX,  /* Register must not be SP or PC */
+        /* Alias to allow '0' arg to be used in REGS macro. */
+        REG_TYPE_0 = REG_TYPE_NONE
+};
+#define REGS(r16, r12, r8, r4, r0)      \
+        (((REG_TYPE_##r16) << 16) +     \
+        ((REG_TYPE_##r12) << 12) +      \
+        ((REG_TYPE_##r8) << 8) +        \
+        ((REG_TYPE_##r4) << 4) +        \
+        (REG_TYPE_##r0))
+union decode_item {
+        u32                     bits;
+        const union decode_item *table;
+        int                     action;
+};
+struct decode_header;
+typedef enum probes_insn (probes_custom_decode_t)(probes_opcode_t,
+                                                  struct arch_probes_insn *,
+                                                  const struct decode_header *);
+union decode_action {
+        probes_insn_handler_t   *handler;
+        probes_custom_decode_t  *decoder;
+};
+#define DECODE_END                      \
+        {.bits = DECODE_TYPE_END}
+struct decode_header {
+        union decode_item       type_regs;
+        union decode_item       mask;
+        union decode_item       value;
+};
+#define DECODE_HEADER(_type, _mask, _value, _regs)              \
+        {.bits = (_type) | ((_regs) << DECODE_TYPE_BITS)},      \
+        {.bits = (_mask)},                                      \
+        {.bits = (_value)}
+struct decode_table {
+        struct decode_header    header;
+        union decode_item       table;
+};
+#define DECODE_TABLE(_mask, _value, _table)                     \
+        DECODE_HEADER(DECODE_TYPE_TABLE, _mask, _value, 0),     \
+        {.table = (_table)}
+struct decode_custom {
+        struct decode_header    header;
+        union decode_item       decoder;
+};
+#define DECODE_CUSTOM(_mask, _value, _decoder)                  \
+        DECODE_HEADER(DECODE_TYPE_CUSTOM, _mask, _value, 0),    \
+        {.action = (_decoder)}
+struct decode_simulate {
+        struct decode_header    header;
+        union decode_item       handler;
+};
+#define DECODE_SIMULATEX(_mask, _value, _handler, _regs)                \
+        DECODE_HEADER(DECODE_TYPE_SIMULATE, _mask, _value, _regs),      \
+        {.action = (_handler)}
+#define DECODE_SIMULATE(_mask, _value, _handler)        \
+        DECODE_SIMULATEX(_mask, _value, _handler, 0)
+struct decode_emulate {
+        struct decode_header    header;
+        union decode_item       handler;
+};
+#define DECODE_EMULATEX(_mask, _value, _handler, _regs)                 \
+        DECODE_HEADER(DECODE_TYPE_EMULATE, _mask, _value, _regs),       \
+        {.action = (_handler)}
+#define DECODE_EMULATE(_mask, _value, _handler)         \
+        DECODE_EMULATEX(_mask, _value, _handler, 0)
+struct decode_or {
+        struct decode_header    header;
+};
+#define DECODE_OR(_mask, _value)                                \
+        DECODE_HEADER(DECODE_TYPE_OR, _mask, _value, 0)
+enum probes_insn {
+        INSN_REJECTED,
+        INSN_GOOD,
+        INSN_GOOD_NO_SLOT
+};
+struct decode_reject {
+        struct decode_header    header;
+};
+#define DECODE_REJECT(_mask, _value)                            \
+        DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0)
+probes_insn_handler_t probes_simulate_nop;
+probes_insn_handler_t probes_emulate_none;
+int __kprobes
+probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
+                const union decode_item *table, bool thumb, bool emulate,
+                const union decode_action *actions);
+#endif
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index adabeababeb0..81ef686a91ca 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -38,6 +38,7 @@
 #include <asm/processor.h>
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
+#include <asm/system_misc.h>
 #include <asm/mach/time.h>
 #include <asm/tls.h>
@@ -47,14 +48,14 @@ unsigned long __stack_chk_guard __read_mostly;
 EXPORT_SYMBOL(__stack_chk_guard);
 #endif
-static const char *processor_modes[] = {
+static const char *processor_modes[] __maybe_unused = {
  "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
  "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
  "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" ,
  "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
 };
-static const char *isa_modes[] = {
+static const char *isa_modes[] __maybe_unused = {
  "ARM" , "Thumb" , "Jazelle", "ThumbEE"
 };
@@ -99,7 +100,7 @@ void soft_restart(unsigned long addr)
        u64 *stack = soft_restart_stack + ARRAY_SIZE(soft_restart_stack);
        /* Disable interrupts first */
-        local_irq_disable();
+        raw_local_irq_disable();
        local_fiq_disable();
        /* Disable the L2 if we're the last man standing. */
@@ -270,12 +271,17 @@ void __show_regs(struct pt_regs *regs)
        buf[3] = flags & PSR_V_BIT ? 'V' : 'v';
        buf[4] = '\0';
+#ifndef CONFIG_CPU_V7M
        printk("Flags: %s  IRQs o%s  FIQs o%s  Mode %s  ISA %s  Segment %s\n",
                buf, interrupts_enabled(regs) ? "n" : "ff",
                fast_interrupts_enabled(regs) ? "n" : "ff",
                processor_modes[processor_mode(regs)],
                isa_modes[isa_mode(regs)],
                get_fs() == get_ds() ? "kernel" : "user");
+#else
+        printk("xPSR: %08lx\n", regs->ARM_cpsr);
+#endif
 #ifdef CONFIG_CPU_CP15
        {
                unsigned int ctrl;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1e8b030dbefd..50e198c1e9c8 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -100,6 +100,9 @@ EXPORT_SYMBOL(system_serial_high);
 unsigned int elf_hwcap __read_mostly;
 EXPORT_SYMBOL(elf_hwcap);
+unsigned int elf_hwcap2 __read_mostly;
+EXPORT_SYMBOL(elf_hwcap2);
 #ifdef MULTI_CPU
 struct processor processor __read_mostly;
@@ -1005,6 +1008,15 @@ static const char *hwcap_str[] = {
        NULL
 };
+static const char *hwcap2_str[] = {
+        "aes",
+        "pmull",
+        "sha1",
+        "sha2",
+        "crc32",
+        NULL
+};
 static int c_show(struct seq_file *m, void *v)
 {
        int i, j;
@@ -1028,6 +1040,10 @@ static int c_show(struct seq_file *m, void *v)
                        if (elf_hwcap & (1 << j))
                                seq_printf(m, "%s ", hwcap_str[j]);
+                for (j = 0; hwcap2_str[j]; j++)
+                        if (elf_hwcap2 & (1 << j))
+                                seq_printf(m, "%s ", hwcap2_str[j]);
                seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
                seq_printf(m, "CPU architecture: %s\n",
                           proc_arch[cpu_architecture()]);
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 04d63880037f..bd1983437205 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -13,6 +13,7 @@
 #include <linux/personality.h>
 #include <linux/uaccess.h>
 #include <linux/tracehook.h>
+#include <linux/uprobes.h>
 #include <asm/elf.h>
 #include <asm/cacheflush.h>
@@ -590,6 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall)
                                        return restart;
                                }
                                syscall = 0;
+                        } else if (thread_flags & _TIF_UPROBE) {
+                                clear_thread_flag(TIF_UPROBE);
+                                uprobe_notify_resume(regs);
                        } else {
                                clear_thread_flag(TIF_NOTIFY_RESUME);
                                tracehook_notify_resume(regs);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index b7b4c86e338b..7c4fada440f0 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -674,8 +674,7 @@ static int cpufreq_callback(struct notifier_block *nb,
        }
        if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
-            (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
+            (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
-            (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) {
                loops_per_jiffy = cpufreq_scale(global_l_p_j_ref,
                                                global_l_p_j_ref_freq,
                                                freq->new);
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 6591e26fc13f..dfc32130bc44 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -166,7 +166,7 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
         * frequency.  The timer is local to a cpu, so cross-call to the
         * changing cpu.
         */
-        if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
+        if (state == CPUFREQ_POSTCHANGE)
                smp_call_function_single(freqs->cpu, twd_update_frequency,
                        NULL, 1);
diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c
index 3e94811690ce..702bd329d9d0 100644
--- a/arch/arm/kernel/sys_oabi-compat.c
+++ b/arch/arm/kernel/sys_oabi-compat.c
@@ -203,6 +203,9 @@ asmlinkage long sys_oabi_fcntl64(unsigned int fd, unsigned int cmd,
        int ret;
        switch (cmd) {
+        case F_GETLKP:
+        case F_SETLKP:
+        case F_SETLKPW:
        case F_GETLK64:
        case F_SETLK64:
        case F_SETLKW64:
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 172ee18ff124..abd2fc067736 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -445,6 +445,7 @@ die_sig:
        if (user_debug & UDBG_UNDEFINED) {
                printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n",
                        current->comm, task_pid_nr(current), pc);
+                __show_regs(regs);
                dump_instr(KERN_INFO, regs);
        }
 #endif
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 00df012c4678..3c217694ebec 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -68,6 +68,12 @@ EXPORT_SYMBOL(__aeabi_unwind_cpp_pr2);
 struct unwind_ctrl_block {
        unsigned long vrs[16];          /* virtual register set */
        const unsigned long *insn;      /* pointer to the current instructions word */
+        unsigned long sp_high;          /* highest value of sp allowed */
+        /*
+         * 1 : check for stack overflow for each register pop.
+         * 0 : save overhead if there is plenty of stack remaining.
+         */
+        int check_each_pop;
        int entries;                    /* number of entries left to interpret */
        int byte;                       /* current byte number in the instructions word */
 };
@@ -235,12 +241,85 @@ static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl)
        return ret;
 }
+/* Before poping a register check whether it is feasible or not */
+static int unwind_pop_register(struct unwind_ctrl_block *ctrl,
+                                unsigned long **vsp, unsigned int reg)
+{
+        if (unlikely(ctrl->check_each_pop))
+                if (*vsp >= (unsigned long *)ctrl->sp_high)
+                        return -URC_FAILURE;
+        ctrl->vrs[reg] = *(*vsp)++;
+        return URC_OK;
+}
+/* Helper functions to execute the instructions */
+static int unwind_exec_pop_subset_r4_to_r13(struct unwind_ctrl_block *ctrl,
+                                                unsigned long mask)
+{
+        unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
+        int load_sp, reg = 4;
+        load_sp = mask & (1 << (13 - 4));
+        while (mask) {
+                if (mask & 1)
+                        if (unwind_pop_register(ctrl, &vsp, reg))
+                                return -URC_FAILURE;
+                mask >>= 1;
+                reg++;
+        }
+        if (!load_sp)
+                ctrl->vrs[SP] = (unsigned long)vsp;
+        return URC_OK;
+}
+static int unwind_exec_pop_r4_to_rN(struct unwind_ctrl_block *ctrl,
+                                        unsigned long insn)
+{
+        unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
+        int reg;
+        /* pop R4-R[4+bbb] */
+        for (reg = 4; reg <= 4 + (insn & 7); reg++)
+                if (unwind_pop_register(ctrl, &vsp, reg))
+                                return -URC_FAILURE;
+        if (insn & 0x80)
+                if (unwind_pop_register(ctrl, &vsp, 14))
+                                return -URC_FAILURE;
+        ctrl->vrs[SP] = (unsigned long)vsp;
+        return URC_OK;
+}
+static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl,
+                                                unsigned long mask)
+{
+        unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
+        int reg = 0;
+        /* pop R0-R3 according to mask */
+        while (mask) {
+                if (mask & 1)
+                        if (unwind_pop_register(ctrl, &vsp, reg))
+                                return -URC_FAILURE;
+                mask >>= 1;
+                reg++;
+        }
+        ctrl->vrs[SP] = (unsigned long)vsp;
+        return URC_OK;
+}
 /*
 * Execute the current unwind instruction.
 */
 static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 {
        unsigned long insn = unwind_get_byte(ctrl);
+        int ret = URC_OK;
        pr_debug("%s: insn = %08lx\n", __func__, insn);
@@ -250,8 +329,6 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
                ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4;
        else if ((insn & 0xf0) == 0x80) {
                unsigned long mask;
-                unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
-                int load_sp, reg = 4;
                insn = (insn << 8) | unwind_get_byte(ctrl);
                mask = insn & 0x0fff;
@@ -261,29 +338,16 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
                        return -URC_FAILURE;
                }
-                /* pop R4-R15 according to mask */
+                ret = unwind_exec_pop_subset_r4_to_r13(ctrl, mask);
-                load_sp = mask & (1 << (13 - 4));
+                if (ret)
-                while (mask) {
+                        goto error;
-                        if (mask & 1)
-                                ctrl->vrs[reg] = *vsp++;
-                        mask >>= 1;
-                        reg++;
-                }
-                if (!load_sp)
-                        ctrl->vrs[SP] = (unsigned long)vsp;
        } else if ((insn & 0xf0) == 0x90 &&
                   (insn & 0x0d) != 0x0d)
                ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f];
        else if ((insn & 0xf0) == 0xa0) {
-                unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
+                ret = unwind_exec_pop_r4_to_rN(ctrl, insn);
-                int reg;
+                if (ret)
+                        goto error;
-                /* pop R4-R[4+bbb] */
-                for (reg = 4; reg <= 4 + (insn & 7); reg++)
-                        ctrl->vrs[reg] = *vsp++;
-                if (insn & 0x80)
-                        ctrl->vrs[14] = *vsp++;
-                ctrl->vrs[SP] = (unsigned long)vsp;
        } else if (insn == 0xb0) {
                if (ctrl->vrs[PC] == 0)
                        ctrl->vrs[PC] = ctrl->vrs[LR];
@@ -291,8 +355,6 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
                ctrl->entries = 0;
        } else if (insn == 0xb1) {
                unsigned long mask = unwind_get_byte(ctrl);
-                unsigned long *vsp = (unsigned long *)ctrl->vrs[SP];
-                int reg = 0;
                if (mask == 0 || mask & 0xf0) {
                        pr_warning("unwind: Spare encoding %04lx\n",
@@ -300,14 +362,9 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
                        return -URC_FAILURE;
                }
-                /* pop R0-R3 according to mask */
+                ret = unwind_exec_pop_subset_r0_to_r3(ctrl, mask);
-                while (mask) {
+                if (ret)
-                        if (mask & 1)
+                        goto error;
-                                ctrl->vrs[reg] = *vsp++;
-                        mask >>= 1;
-                        reg++;
-                }
-                ctrl->vrs[SP] = (unsigned long)vsp;
        } else if (insn == 0xb2) {
                unsigned long uleb128 = unwind_get_byte(ctrl);
@@ -320,7 +377,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
        pr_debug("%s: fp = %08lx sp = %08lx lr = %08lx pc = %08lx\n", __func__,
                 ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]);
-        return URC_OK;
+error:
+        return ret;
 }
 /*
@@ -329,13 +387,13 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl)
 */
 int unwind_frame(struct stackframe *frame)
 {
-        unsigned long high, low;
+        unsigned long low;
        const struct unwind_idx *idx;
        struct unwind_ctrl_block ctrl;
-        /* only go to a higher address on the stack */
+        /* store the highest address on the stack to avoid crossing it*/
        low = frame->sp;
-        high = ALIGN(low, THREAD_SIZE);
+        ctrl.sp_high = ALIGN(low, THREAD_SIZE);
        pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__,
                 frame->pc, frame->lr, frame->sp);
@@ -382,11 +440,16 @@ int unwind_frame(struct stackframe *frame)
                return -URC_FAILURE;
        }
+        ctrl.check_each_pop = 0;
        while (ctrl.entries > 0) {
-                int urc = unwind_exec_insn(&ctrl);
+                int urc;
+                if ((ctrl.sp_high - ctrl.vrs[SP]) < sizeof(ctrl.vrs))
+                        ctrl.check_each_pop = 1;
+                urc = unwind_exec_insn(&ctrl);
                if (urc < 0)
                        return urc;
-                if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high)
+                if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= ctrl.sp_high)
                        return -URC_FAILURE;
        }
diff --git a/arch/arm/kernel/uprobes-arm.c b/arch/arm/kernel/uprobes-arm.c
new file mode 100644
index 000000000000..d3b655ff17da
--- /dev/null
+++ b/arch/arm/kernel/uprobes-arm.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2012 Rabin Vincent <rabin at rab.in>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/stddef.h>
+#include <linux/wait.h>
+#include <linux/uprobes.h>
+#include <linux/module.h>
+#include "probes.h"
+#include "probes-arm.h"
+#include "uprobes.h"
+static int uprobes_substitute_pc(unsigned long *pinsn, u32 oregs)
+{
+        probes_opcode_t insn = __mem_to_opcode_arm(*pinsn);
+        probes_opcode_t temp;
+        probes_opcode_t mask;
+        int freereg;
+        u32 free = 0xffff;
+        u32 regs;
+        for (regs = oregs; regs; regs >>= 4, insn >>= 4) {
+                if ((regs & 0xf) == REG_TYPE_NONE)
+                        continue;
+                free &= ~(1 << (insn & 0xf));
+        }
+        /* No PC, no problem */
+        if (free & (1 << 15))
+                return 15;
+        if (!free)
+                return -1;
+        /*
+         * fls instead of ffs ensures that for "ldrd r0, r1, [pc]" we would
+         * pick LR instead of R1.
+         */
+        freereg = free = fls(free) - 1;
+        temp = __mem_to_opcode_arm(*pinsn);
+        insn = temp;
+        regs = oregs;
+        mask = 0xf;
+        for (; regs; regs >>= 4, mask <<= 4, free <<= 4, temp >>= 4) {
+                if ((regs & 0xf) == REG_TYPE_NONE)
+                        continue;
+                if ((temp & 0xf) != 15)
+                        continue;
+                insn &= ~mask;
+                insn |= free & mask;
+        }
+        *pinsn = __opcode_to_mem_arm(insn);
+        return freereg;
+}
+static void uprobe_set_pc(struct arch_uprobe *auprobe,
+                          struct arch_uprobe_task *autask,
+                          struct pt_regs *regs)
+{
+        u32 pcreg = auprobe->pcreg;
+        autask->backup = regs->uregs[pcreg];
+        regs->uregs[pcreg] = regs->ARM_pc + 8;
+}
+static void uprobe_unset_pc(struct arch_uprobe *auprobe,
+                            struct arch_uprobe_task *autask,
+                            struct pt_regs *regs)
+{
+        /* PC will be taken care of by common code */
+        regs->uregs[auprobe->pcreg] = autask->backup;
+}
+static void uprobe_aluwrite_pc(struct arch_uprobe *auprobe,
+                               struct arch_uprobe_task *autask,
+                               struct pt_regs *regs)
+{
+        u32 pcreg = auprobe->pcreg;
+        alu_write_pc(regs->uregs[pcreg], regs);
+        regs->uregs[pcreg] = autask->backup;
+}
+static void uprobe_write_pc(struct arch_uprobe *auprobe,
+                            struct arch_uprobe_task *autask,
+                            struct pt_regs *regs)
+{
+        u32 pcreg = auprobe->pcreg;
+        load_write_pc(regs->uregs[pcreg], regs);
+        regs->uregs[pcreg] = autask->backup;
+}
+enum probes_insn
+decode_pc_ro(probes_opcode_t insn, struct arch_probes_insn *asi,
+             const struct decode_header *d)
+{
+        struct arch_uprobe *auprobe = container_of(asi, struct arch_uprobe,
+                                                   asi);
+        struct decode_emulate *decode = (struct decode_emulate *) d;
+        u32 regs = decode->header.type_regs.bits >> DECODE_TYPE_BITS;
+        int reg;
+        reg = uprobes_substitute_pc(&auprobe->ixol[0], regs);
+        if (reg == 15)
+                return INSN_GOOD;
+        if (reg == -1)
+                return INSN_REJECTED;
+        auprobe->pcreg = reg;
+        auprobe->prehandler = uprobe_set_pc;
+        auprobe->posthandler = uprobe_unset_pc;
+        return INSN_GOOD;
+}
+enum probes_insn
+decode_wb_pc(probes_opcode_t insn, struct arch_probes_insn *asi,
+             const struct decode_header *d, bool alu)
+{
+        struct arch_uprobe *auprobe = container_of(asi, struct arch_uprobe,
+                                                   asi);
+        enum probes_insn ret = decode_pc_ro(insn, asi, d);
+        if (((insn >> 12) & 0xf) == 15)
+                auprobe->posthandler = alu ? uprobe_aluwrite_pc
+                                           : uprobe_write_pc;
+        return ret;
+}
+enum probes_insn
+decode_rd12rn16rm0rs8_rwflags(probes_opcode_t insn,
+                              struct arch_probes_insn *asi,
+                              const struct decode_header *d)
+{
+        return decode_wb_pc(insn, asi, d, true);
+}
+enum probes_insn
+decode_ldr(probes_opcode_t insn, struct arch_probes_insn *asi,
+           const struct decode_header *d)
+{
+        return decode_wb_pc(insn, asi, d, false);
+}
+enum probes_insn
+uprobe_decode_ldmstm(probes_opcode_t insn,
+                     struct arch_probes_insn *asi,
+                     const struct decode_header *d)
+{
+        struct arch_uprobe *auprobe = container_of(asi, struct arch_uprobe,
+                                                   asi);
+        unsigned reglist = insn & 0xffff;
+        int rn = (insn >> 16) & 0xf;
+        int lbit = insn & (1 << 20);
+        unsigned used = reglist | (1 << rn);
+        if (rn == 15)
+                return INSN_REJECTED;
+        if (!(used & (1 << 15)))
+                return INSN_GOOD;
+        if (used & (1 << 14))
+                return INSN_REJECTED;
+        /* Use LR instead of PC */
+        insn ^= 0xc000;
+        auprobe->pcreg = 14;
+        auprobe->ixol[0] = __opcode_to_mem_arm(insn);
+        auprobe->prehandler = uprobe_set_pc;
+        if (lbit)
+                auprobe->posthandler = uprobe_write_pc;
+        else
+                auprobe->posthandler = uprobe_unset_pc;
+        return INSN_GOOD;
+}
+const union decode_action uprobes_probes_actions[] = {
+        [PROBES_EMULATE_NONE] = {.handler = probes_simulate_nop},
+        [PROBES_SIMULATE_NOP] = {.handler = probes_simulate_nop},
+        [PROBES_PRELOAD_IMM] = {.handler = probes_simulate_nop},
+        [PROBES_PRELOAD_REG] = {.handler = probes_simulate_nop},
+        [PROBES_BRANCH_IMM] = {.handler = simulate_blx1},
+        [PROBES_MRS] = {.handler = simulate_mrs},
+        [PROBES_BRANCH_REG] = {.handler = simulate_blx2bx},
+        [PROBES_CLZ] = {.handler = probes_simulate_nop},
+        [PROBES_SATURATING_ARITHMETIC] = {.handler = probes_simulate_nop},
+        [PROBES_MUL1] = {.handler = probes_simulate_nop},
+        [PROBES_MUL2] = {.handler = probes_simulate_nop},
+        [PROBES_SWP] = {.handler = probes_simulate_nop},
+        [PROBES_LDRSTRD] = {.decoder = decode_pc_ro},
+        [PROBES_LOAD_EXTRA] = {.decoder = decode_pc_ro},
+        [PROBES_LOAD] = {.decoder = decode_ldr},
+        [PROBES_STORE_EXTRA] = {.decoder = decode_pc_ro},
+        [PROBES_STORE] = {.decoder = decode_pc_ro},
+        [PROBES_MOV_IP_SP] = {.handler = simulate_mov_ipsp},
+        [PROBES_DATA_PROCESSING_REG] = {
+                .decoder = decode_rd12rn16rm0rs8_rwflags},
+        [PROBES_DATA_PROCESSING_IMM] = {
+                .decoder = decode_rd12rn16rm0rs8_rwflags},
+        [PROBES_MOV_HALFWORD] = {.handler = probes_simulate_nop},
+        [PROBES_SEV] = {.handler = probes_simulate_nop},
+        [PROBES_WFE] = {.handler = probes_simulate_nop},
+        [PROBES_SATURATE] = {.handler = probes_simulate_nop},
+        [PROBES_REV] = {.handler = probes_simulate_nop},
+        [PROBES_MMI] = {.handler = probes_simulate_nop},
+        [PROBES_PACK] = {.handler = probes_simulate_nop},
+        [PROBES_EXTEND] = {.handler = probes_simulate_nop},
+        [PROBES_EXTEND_ADD] = {.handler = probes_simulate_nop},
+        [PROBES_MUL_ADD_LONG] = {.handler = probes_simulate_nop},
+        [PROBES_MUL_ADD] = {.handler = probes_simulate_nop},
+        [PROBES_BITFIELD] = {.handler = probes_simulate_nop},
+        [PROBES_BRANCH] = {.handler = simulate_bbl},
+        [PROBES_LDMSTM] = {.decoder = uprobe_decode_ldmstm}
+};
diff --git a/arch/arm/kernel/uprobes.c b/arch/arm/kernel/uprobes.c
new file mode 100644
index 000000000000..f9bacee973bf
--- /dev/null
+++ b/arch/arm/kernel/uprobes.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2012 Rabin Vincent <rabin at rab.in>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/errno.h>
+#include <linux/highmem.h>
+#include <linux/sched.h>
+#include <linux/uprobes.h>
+#include <linux/notifier.h>
+#include <asm/opcodes.h>
+#include <asm/traps.h>
+#include "probes.h"
+#include "probes-arm.h"
+#include "uprobes.h"
+#define UPROBE_TRAP_NR  UINT_MAX
+bool is_swbp_insn(uprobe_opcode_t *insn)
+{
+        return (__mem_to_opcode_arm(*insn) & 0x0fffffff) ==
+                (UPROBE_SWBP_ARM_INSN & 0x0fffffff);
+}
+int set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm,
+             unsigned long vaddr)
+{
+        return uprobe_write_opcode(mm, vaddr,
+                   __opcode_to_mem_arm(auprobe->bpinsn));
+}
+bool arch_uprobe_ignore(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+        if (!auprobe->asi.insn_check_cc(regs->ARM_cpsr)) {
+                regs->ARM_pc += 4;
+                return true;
+        }
+        return false;
+}
+bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+        probes_opcode_t opcode;
+        if (!auprobe->simulate)
+                return false;
+        opcode = __mem_to_opcode_arm(*(unsigned int *) auprobe->insn);
+        auprobe->asi.insn_singlestep(opcode, &auprobe->asi, regs);
+        return true;
+}
+unsigned long
+arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr,
+                                  struct pt_regs *regs)
+{
+        unsigned long orig_ret_vaddr;
+        orig_ret_vaddr = regs->ARM_lr;
+        /* Replace the return addr with trampoline addr */
+        regs->ARM_lr = trampoline_vaddr;
+        return orig_ret_vaddr;
+}
+int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
+                             unsigned long addr)
+{
+        unsigned int insn;
+        unsigned int bpinsn;
+        enum probes_insn ret;
+        /* Thumb not yet support */
+        if (addr & 0x3)
+                return -EINVAL;
+        insn = __mem_to_opcode_arm(*(unsigned int *)auprobe->insn);
+        auprobe->ixol[0] = __opcode_to_mem_arm(insn);
+        auprobe->ixol[1] = __opcode_to_mem_arm(UPROBE_SS_ARM_INSN);
+        ret = arm_probes_decode_insn(insn, &auprobe->asi, false,
+                                     uprobes_probes_actions);
+        switch (ret) {
+        case INSN_REJECTED:
+                return -EINVAL;
+        case INSN_GOOD_NO_SLOT:
+                auprobe->simulate = true;
+                break;
+        case INSN_GOOD:
+        default:
+                break;
+        }
+        bpinsn = UPROBE_SWBP_ARM_INSN & 0x0fffffff;
+        if (insn >= 0xe0000000)
+                bpinsn |= 0xe0000000;  /* Unconditional instruction */
+        else
+                bpinsn |= insn & 0xf0000000;  /* Copy condition from insn */
+        auprobe->bpinsn = bpinsn;
+        return 0;
+}
+int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+        struct uprobe_task *utask = current->utask;
+        if (auprobe->prehandler)
+                auprobe->prehandler(auprobe, &utask->autask, regs);
+        utask->autask.saved_trap_no = current->thread.trap_no;
+        current->thread.trap_no = UPROBE_TRAP_NR;
+        regs->ARM_pc = utask->xol_vaddr;
+        return 0;
+}
+int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+        struct uprobe_task *utask = current->utask;
+        WARN_ON_ONCE(current->thread.trap_no != UPROBE_TRAP_NR);
+        current->thread.trap_no = utask->autask.saved_trap_no;
+        regs->ARM_pc = utask->vaddr + 4;
+        if (auprobe->posthandler)
+                auprobe->posthandler(auprobe, &utask->autask, regs);
+        return 0;
+}
+bool arch_uprobe_xol_was_trapped(struct task_struct *t)
+{
+        if (t->thread.trap_no != UPROBE_TRAP_NR)
+                return true;
+        return false;
+}
+void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
+{
+        struct uprobe_task *utask = current->utask;
+        current->thread.trap_no = utask->autask.saved_trap_no;
+        instruction_pointer_set(regs, utask->vaddr);
+}
+int arch_uprobe_exception_notify(struct notifier_block *self,
+                                 unsigned long val, void *data)
+{
+        return NOTIFY_DONE;
+}
+static int uprobe_trap_handler(struct pt_regs *regs, unsigned int instr)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        instr &= 0x0fffffff;
+        if (instr == (UPROBE_SWBP_ARM_INSN & 0x0fffffff))
+                uprobe_pre_sstep_notifier(regs);
+        else if (instr == (UPROBE_SS_ARM_INSN & 0x0fffffff))
+                uprobe_post_sstep_notifier(regs);
+        local_irq_restore(flags);
+        return 0;
+}
+unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
+{
+        return instruction_pointer(regs);
+}
+static struct undef_hook uprobes_arm_break_hook = {
+        .instr_mask     = 0x0fffffff,
+        .instr_val      = (UPROBE_SWBP_ARM_INSN & 0x0fffffff),
+        .cpsr_mask      = MODE_MASK,
+        .cpsr_val       = USR_MODE,
+        .fn             = uprobe_trap_handler,
+};
+static struct undef_hook uprobes_arm_ss_hook = {
+        .instr_mask     = 0x0fffffff,
+        .instr_val      = (UPROBE_SS_ARM_INSN & 0x0fffffff),
+        .cpsr_mask      = MODE_MASK,
+        .cpsr_val       = USR_MODE,
+        .fn             = uprobe_trap_handler,
+};
+static int arch_uprobes_init(void)
+{
+        register_undef_hook(&uprobes_arm_break_hook);
+        register_undef_hook(&uprobes_arm_ss_hook);
+        return 0;
+}
+device_initcall(arch_uprobes_init);
diff --git a/arch/arm/kernel/uprobes.h b/arch/arm/kernel/uprobes.h
new file mode 100644
index 000000000000..1d0c12dfbd03
--- /dev/null
+++ b/arch/arm/kernel/uprobes.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012 Rabin Vincent <rabin at rab.in>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARM_KERNEL_UPROBES_H
+#define __ARM_KERNEL_UPROBES_H
+enum probes_insn uprobe_decode_ldmstm(probes_opcode_t insn,
+                                      struct arch_probes_insn *asi,
+                                      const struct decode_header *d);
+enum probes_insn decode_ldr(probes_opcode_t insn,
+                            struct arch_probes_insn *asi,
+                            const struct decode_header *d);
+enum probes_insn
+decode_rd12rn16rm0rs8_rwflags(probes_opcode_t insn,
+                              struct arch_probes_insn *asi,
+                              const struct decode_header *d);
+enum probes_insn
+decode_wb_pc(probes_opcode_t insn, struct arch_probes_insn *asi,
+             const struct decode_header *d, bool alu);
+enum probes_insn
+decode_pc_ro(probes_opcode_t insn, struct arch_probes_insn *asi,
+             const struct decode_header *d);
+extern const union decode_action uprobes_probes_actions[];
+#endif
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index bd18bb8b2770..f0e50a0f3a65 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -1051,21 +1051,26 @@ int kvm_arch_init(void *opaque)
                }
        }
+        cpu_notifier_register_begin();
        err = init_hyp_mode();
        if (err)
                goto out_err;
-        err = register_cpu_notifier(&hyp_init_cpu_nb);
+        err = __register_cpu_notifier(&hyp_init_cpu_nb);
        if (err) {
                kvm_err("Cannot register HYP init CPU notifier (%d)\n", err);
                goto out_err;
        }
+        cpu_notifier_register_done();
        hyp_cpu_pm_init();
        kvm_coproc_table_init();
        return 0;
 out_err:
+        cpu_notifier_register_done();
        return err;
 }
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 78c0885d6501..c58a35116f63 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -23,6 +23,7 @@
 #include <asm/kvm_host.h>
 #include <asm/kvm_emulate.h>
 #include <asm/kvm_coproc.h>
+#include <asm/kvm_mmu.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
 #include <trace/events/kvm.h>
@@ -205,6 +206,44 @@ done:
 }
 /*
+ * Generic accessor for VM registers. Only called as long as HCR_TVM
+ * is set.
+ */
+static bool access_vm_reg(struct kvm_vcpu *vcpu,
+                          const struct coproc_params *p,
+                          const struct coproc_reg *r)
+{
+        BUG_ON(!p->is_write);
+        vcpu->arch.cp15[r->reg] = *vcpu_reg(vcpu, p->Rt1);
+        if (p->is_64bit)
+                vcpu->arch.cp15[r->reg + 1] = *vcpu_reg(vcpu, p->Rt2);
+        return true;
+}
+/*
+ * SCTLR accessor. Only called as long as HCR_TVM is set.  If the
+ * guest enables the MMU, we stop trapping the VM sys_regs and leave
+ * it in complete control of the caches.
+ *
+ * Used by the cpu-specific code.
+ */
+bool access_sctlr(struct kvm_vcpu *vcpu,
+                  const struct coproc_params *p,
+                  const struct coproc_reg *r)
+{
+        access_vm_reg(vcpu, p, r);
+        if (vcpu_has_cache_enabled(vcpu)) {     /* MMU+Caches enabled? */
+                vcpu->arch.hcr &= ~HCR_TVM;
+                stage2_flush_vm(vcpu->kvm);
+        }
+        return true;
+}
+/*
 * We could trap ID_DFR0 and tell the guest we don't support performance
 * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 * NAKed, so it will read the PMCR anyway.
@@ -261,33 +300,36 @@ static const struct coproc_reg cp15_regs[] = {
        { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
                        NULL, reset_val, c1_CPACR, 0x00000000 },
-        /* TTBR0/TTBR1: swapped by interrupt.S. */
+        /* TTBR0/TTBR1/TTBCR: swapped by interrupt.S. */
-        { CRm64( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
+        { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 },
-        { CRm64( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
+        { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
+                        access_vm_reg, reset_unknown, c2_TTBR0 },
-        /* TTBCR: swapped by interrupt.S. */
+        { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
+                        access_vm_reg, reset_unknown, c2_TTBR1 },
        { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
-                        NULL, reset_val, c2_TTBCR, 0x00000000 },
+                        access_vm_reg, reset_val, c2_TTBCR, 0x00000000 },
+        { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 },
        /* DACR: swapped by interrupt.S. */
        { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
-                        NULL, reset_unknown, c3_DACR },
+                        access_vm_reg, reset_unknown, c3_DACR },
        /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
        { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
-                        NULL, reset_unknown, c5_DFSR },
+                        access_vm_reg, reset_unknown, c5_DFSR },
        { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
-                        NULL, reset_unknown, c5_IFSR },
+                        access_vm_reg, reset_unknown, c5_IFSR },
        { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
-                        NULL, reset_unknown, c5_ADFSR },
+                        access_vm_reg, reset_unknown, c5_ADFSR },
        { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
-                        NULL, reset_unknown, c5_AIFSR },
+                        access_vm_reg, reset_unknown, c5_AIFSR },
        /* DFAR/IFAR: swapped by interrupt.S. */
        { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
-                        NULL, reset_unknown, c6_DFAR },
+                        access_vm_reg, reset_unknown, c6_DFAR },
        { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
-                        NULL, reset_unknown, c6_IFAR },
+                        access_vm_reg, reset_unknown, c6_IFAR },
        /* PAR swapped by interrupt.S */
        { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
@@ -324,9 +366,15 @@ static const struct coproc_reg cp15_regs[] = {
        /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
        { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
-                        NULL, reset_unknown, c10_PRRR},
+                        access_vm_reg, reset_unknown, c10_PRRR},
        { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
-                        NULL, reset_unknown, c10_NMRR},
+                        access_vm_reg, reset_unknown, c10_NMRR},
+        /* AMAIR0/AMAIR1: swapped by interrupt.S. */
+        { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32,
+                        access_vm_reg, reset_unknown, c10_AMAIR0},
+        { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32,
+                        access_vm_reg, reset_unknown, c10_AMAIR1},
        /* VBAR: swapped by interrupt.S. */
        { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
@@ -334,7 +382,7 @@ static const struct coproc_reg cp15_regs[] = {
        /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
        { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
-                        NULL, reset_val, c13_CID, 0x00000000 },
+                        access_vm_reg, reset_val, c13_CID, 0x00000000 },
        { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
                        NULL, reset_unknown, c13_TID_URW },
        { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
@@ -443,7 +491,7 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
        struct coproc_params params;
-        params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
+        params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
        params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
        params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
        params.is_64bit = true;
@@ -451,7 +499,7 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
        params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
        params.Op2 = 0;
        params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
-        params.CRn = 0;
+        params.CRm = 0;
        return emulate_cp15(vcpu, &params);
 }
diff --git a/arch/arm/kvm/coproc.h b/arch/arm/kvm/coproc.h
index 0461d5c8d3de..1a44bbe39643 100644
--- a/arch/arm/kvm/coproc.h
+++ b/arch/arm/kvm/coproc.h
@@ -58,8 +58,8 @@ static inline void print_cp_instr(const struct coproc_params *p)
 {
        /* Look, we even formatted it for you to paste into the table! */
        if (p->is_64bit) {
-                kvm_pr_unimpl(" { CRm(%2lu), Op1(%2lu), is64, func_%s },\n",
+                kvm_pr_unimpl(" { CRm64(%2lu), Op1(%2lu), is64, func_%s },\n",
-                              p->CRm, p->Op1, p->is_write ? "write" : "read");
+                              p->CRn, p->Op1, p->is_write ? "write" : "read");
        } else {
                kvm_pr_unimpl(" { CRn(%2lu), CRm(%2lu), Op1(%2lu), Op2(%2lu), is32,"
                              " func_%s },\n",
@@ -135,13 +135,13 @@ static inline int cmp_reg(const struct coproc_reg *i1,
                return -1;
        if (i1->CRn != i2->CRn)
                return i1->CRn - i2->CRn;
-        if (i1->is_64 != i2->is_64)
-                return i2->is_64 - i1->is_64;
        if (i1->CRm != i2->CRm)
                return i1->CRm - i2->CRm;
        if (i1->Op1 != i2->Op1)
                return i1->Op1 - i2->Op1;
-        return i1->Op2 - i2->Op2;
+        if (i1->Op2 != i2->Op2)
+                return i1->Op2 - i2->Op2;
+        return i2->is_64 - i1->is_64;
 }
@@ -153,4 +153,8 @@ static inline int cmp_reg(const struct coproc_reg *i1,
 #define is64            .is_64 = true
 #define is32            .is_64 = false
+bool access_sctlr(struct kvm_vcpu *vcpu,
+                  const struct coproc_params *p,
+                  const struct coproc_reg *r);
 #endif /* __ARM_KVM_COPROC_LOCAL_H__ */
diff --git a/arch/arm/kvm/coproc_a15.c b/arch/arm/kvm/coproc_a15.c
index bb0cac1410cc..e6f4ae48bda9 100644
--- a/arch/arm/kvm/coproc_a15.c
+++ b/arch/arm/kvm/coproc_a15.c
@@ -34,7 +34,7 @@
 static const struct coproc_reg a15_regs[] = {
        /* SCTLR: swapped by interrupt.S. */
        { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
-                        NULL, reset_val, c1_SCTLR, 0x00C50078 },
+                        access_sctlr, reset_val, c1_SCTLR, 0x00C50078 },
 };
 static struct kvm_coproc_target_table a15_target_table = {
diff --git a/arch/arm/kvm/coproc_a7.c b/arch/arm/kvm/coproc_a7.c
index 1df767331588..17fc7cd479d3 100644
--- a/arch/arm/kvm/coproc_a7.c
+++ b/arch/arm/kvm/coproc_a7.c
@@ -37,7 +37,7 @@
 static const struct coproc_reg a7_regs[] = {
        /* SCTLR: swapped by interrupt.S. */
        { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
-                        NULL, reset_val, c1_SCTLR, 0x00C50878 },
+                        access_sctlr, reset_val, c1_SCTLR, 0x00C50878 },
 };
 static struct kvm_coproc_target_table a7_target_table = {
diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
index 2786eae10c0d..b23a59c1c522 100644
--- a/arch/arm/kvm/guest.c
+++ b/arch/arm/kvm/guest.c
@@ -38,6 +38,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
 {
+        vcpu->arch.hcr = HCR_GUEST_MASK;
        return 0;
 }
diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 6f18695a09cb..76af93025574 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -303,13 +303,17 @@ vcpu	.req	r0		@ vcpu pointer always in r0
        mrc     p15, 0, r2, c14, c1, 0  @ CNTKCTL
        mrrc    p15, 0, r4, r5, c7      @ PAR
+        mrc     p15, 0, r6, c10, c3, 0  @ AMAIR0
+        mrc     p15, 0, r7, c10, c3, 1  @ AMAIR1
        .if \store_to_vcpu == 0
-        push    {r2,r4-r5}
+        push    {r2,r4-r7}
        .else
        str     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
        add     r12, vcpu, #CP15_OFFSET(c7_PAR)
        strd    r4, r5, [r12]
+        str     r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
+        str     r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
        .endif
 .endm
@@ -322,15 +326,19 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 */
 .macro write_cp15_state read_from_vcpu
        .if \read_from_vcpu == 0
-        pop     {r2,r4-r5}
+        pop     {r2,r4-r7}
        .else
        ldr     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
        add     r12, vcpu, #CP15_OFFSET(c7_PAR)
        ldrd    r4, r5, [r12]
+        ldr     r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
+        ldr     r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
        .endif
        mcr     p15, 0, r2, c14, c1, 0  @ CNTKCTL
        mcrr    p15, 0, r4, r5, c7      @ PAR
+        mcr     p15, 0, r6, c10, c3, 0  @ AMAIR0
+        mcr     p15, 0, r7, c10, c3, 1  @ AMAIR1
        .if \read_from_vcpu == 0
        pop     {r2-r12}
@@ -597,17 +605,14 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 /* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */
 .macro configure_hyp_role operation
-        mrc     p15, 4, r2, c1, c1, 0   @ HCR
-        bic     r2, r2, #HCR_VIRT_EXCP_MASK
-        ldr     r3, =HCR_GUEST_MASK
        .if \operation == vmentry
-        orr     r2, r2, r3
+        ldr     r2, [vcpu, #VCPU_HCR]
        ldr     r3, [vcpu, #VCPU_IRQ_LINES]
        orr     r2, r2, r3
        .else
-        bic     r2, r2, r3
+        mov     r2, #0
        .endif
-        mcr     p15, 4, r2, c1, c1, 0
+        mcr     p15, 4, r2, c1, c1, 0   @ HCR
 .endm
 .macro load_vcpu
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 7789857d1470..80bb1e6c2c29 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -144,8 +144,9 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
        while (addr < end) {
                pgd = pgdp + pgd_index(addr);
                pud = pud_offset(pgd, addr);
+                pte = NULL;
                if (pud_none(*pud)) {
-                        addr = pud_addr_end(addr, end);
+                        addr = kvm_pud_addr_end(addr, end);
                        continue;
                }
@@ -155,13 +156,13 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
                         * move on.
                         */
                        clear_pud_entry(kvm, pud, addr);
-                        addr = pud_addr_end(addr, end);
+                        addr = kvm_pud_addr_end(addr, end);
                        continue;
                }
                pmd = pmd_offset(pud, addr);
                if (pmd_none(*pmd)) {
-                        addr = pmd_addr_end(addr, end);
+                        addr = kvm_pmd_addr_end(addr, end);
                        continue;
                }
@@ -174,12 +175,12 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
                /*
                 * If the pmd entry is to be cleared, walk back up the ladder
                 */
-                if (kvm_pmd_huge(*pmd) || page_empty(pte)) {
+                if (kvm_pmd_huge(*pmd) || (pte && page_empty(pte))) {
                        clear_pmd_entry(kvm, pmd, addr);
-                        next = pmd_addr_end(addr, end);
+                        next = kvm_pmd_addr_end(addr, end);
                        if (page_empty(pmd) && !page_empty(pud)) {
                                clear_pud_entry(kvm, pud, addr);
-                                next = pud_addr_end(addr, end);
+                                next = kvm_pud_addr_end(addr, end);
                        }
                }
@@ -187,6 +188,99 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
        }
 }
+static void stage2_flush_ptes(struct kvm *kvm, pmd_t *pmd,
+                              phys_addr_t addr, phys_addr_t end)
+{
+        pte_t *pte;
+        pte = pte_offset_kernel(pmd, addr);
+        do {
+                if (!pte_none(*pte)) {
+                        hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);
+                        kvm_flush_dcache_to_poc((void*)hva, PAGE_SIZE);
+                }
+        } while (pte++, addr += PAGE_SIZE, addr != end);
+}
+static void stage2_flush_pmds(struct kvm *kvm, pud_t *pud,
+                              phys_addr_t addr, phys_addr_t end)
+{
+        pmd_t *pmd;
+        phys_addr_t next;
+        pmd = pmd_offset(pud, addr);
+        do {
+                next = kvm_pmd_addr_end(addr, end);
+                if (!pmd_none(*pmd)) {
+                        if (kvm_pmd_huge(*pmd)) {
+                                hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);
+                                kvm_flush_dcache_to_poc((void*)hva, PMD_SIZE);
+                        } else {
+                                stage2_flush_ptes(kvm, pmd, addr, next);
+                        }
+                }
+        } while (pmd++, addr = next, addr != end);
+}
+static void stage2_flush_puds(struct kvm *kvm, pgd_t *pgd,
+                              phys_addr_t addr, phys_addr_t end)
+{
+        pud_t *pud;
+        phys_addr_t next;
+        pud = pud_offset(pgd, addr);
+        do {
+                next = kvm_pud_addr_end(addr, end);
+                if (!pud_none(*pud)) {
+                        if (pud_huge(*pud)) {
+                                hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);
+                                kvm_flush_dcache_to_poc((void*)hva, PUD_SIZE);
+                        } else {
+                                stage2_flush_pmds(kvm, pud, addr, next);
+                        }
+                }
+        } while (pud++, addr = next, addr != end);
+}
+static void stage2_flush_memslot(struct kvm *kvm,
+                                 struct kvm_memory_slot *memslot)
+{
+        phys_addr_t addr = memslot->base_gfn << PAGE_SHIFT;
+        phys_addr_t end = addr + PAGE_SIZE * memslot->npages;
+        phys_addr_t next;
+        pgd_t *pgd;
+        pgd = kvm->arch.pgd + pgd_index(addr);
+        do {
+                next = kvm_pgd_addr_end(addr, end);
+                stage2_flush_puds(kvm, pgd, addr, next);
+        } while (pgd++, addr = next, addr != end);
+}
+/**
+ * stage2_flush_vm - Invalidate cache for pages mapped in stage 2
+ * @kvm: The struct kvm pointer
+ *
+ * Go through the stage 2 page tables and invalidate any cache lines
+ * backing memory already mapped to the VM.
+ */
+void stage2_flush_vm(struct kvm *kvm)
+{
+        struct kvm_memslots *slots;
+        struct kvm_memory_slot *memslot;
+        int idx;
+        idx = srcu_read_lock(&kvm->srcu);
+        spin_lock(&kvm->mmu_lock);
+        slots = kvm_memslots(kvm);
+        kvm_for_each_memslot(memslot, slots)
+                stage2_flush_memslot(kvm, memslot);
+        spin_unlock(&kvm->mmu_lock);
+        srcu_read_unlock(&kvm->srcu, idx);
+}
 /**
 * free_boot_hyp_pgd - free HYP boot page tables
 *
@@ -715,7 +809,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
                        kvm_set_s2pmd_writable(&new_pmd);
                        kvm_set_pfn_dirty(pfn);
                }
-                coherent_icache_guest_page(kvm, hva & PMD_MASK, PMD_SIZE);
+                coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE);
                ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd);
        } else {
                pte_t new_pte = pfn_pte(pfn, PAGE_S2);
@@ -723,7 +817,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
                        kvm_set_s2pte_writable(&new_pte);
                        kvm_set_pfn_dirty(pfn);
                }
-                coherent_icache_guest_page(kvm, hva, PAGE_SIZE);
+                coherent_cache_guest_page(vcpu, hva, PAGE_SIZE);
                ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte, false);
        }
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 52886b89706c..9f12ed1eea86 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -37,6 +37,11 @@ UNWIND(	.fnstart	)
        add     r1, r1, r0, lsl #2      @ Get word offset
        mov     r3, r2, lsl r3          @ create mask
        smp_dmb
+#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
+        .arch_extension mp
+        ALT_SMP(W(pldw) [r1])
+        ALT_UP(W(nop))
+#endif
 1:      ldrex   r2, [r1]
        ands    r0, r2, r3              @ save old value of bit
        \instr  r2, r2, r3              @ toggle bit
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 805e3f8fb007..3bc8eb811a73 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -197,24 +197,24 @@
 12:     PLD(    pld     [r1, #124]              )
 13:             ldr4w   r1, r4, r5, r6, r7, abort=19f
-                mov     r3, lr, pull #\pull
+                mov     r3, lr, lspull #\pull
                subs    r2, r2, #32
                ldr4w   r1, r8, r9, ip, lr, abort=19f
-                orr     r3, r3, r4, push #\push
+                orr     r3, r3, r4, lspush #\push
-                mov     r4, r4, pull #\pull
+                mov     r4, r4, lspull #\pull
-                orr     r4, r4, r5, push #\push
+                orr     r4, r4, r5, lspush #\push
-                mov     r5, r5, pull #\pull
+                mov     r5, r5, lspull #\pull
-                orr     r5, r5, r6, push #\push
+                orr     r5, r5, r6, lspush #\push
-                mov     r6, r6, pull #\pull
+                mov     r6, r6, lspull #\pull
-                orr     r6, r6, r7, push #\push
+                orr     r6, r6, r7, lspush #\push
-                mov     r7, r7, pull #\pull
+                mov     r7, r7, lspull #\pull
-                orr     r7, r7, r8, push #\push
+                orr     r7, r7, r8, lspush #\push
-                mov     r8, r8, pull #\pull
+                mov     r8, r8, lspull #\pull
-                orr     r8, r8, r9, push #\push
+                orr     r8, r8, r9, lspush #\push
-                mov     r9, r9, pull #\pull
+                mov     r9, r9, lspull #\pull
-                orr     r9, r9, ip, push #\push
+                orr     r9, r9, ip, lspush #\push
-                mov     ip, ip, pull #\pull
+                mov     ip, ip, lspull #\pull
-                orr     ip, ip, lr, push #\push
+                orr     ip, ip, lr, lspush #\push
                str8w   r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
                bge     12b
        PLD(    cmn     r2, #96                 )
@@ -225,10 +225,10 @@
 14:             ands    ip, r2, #28
                beq     16f
-15:             mov     r3, lr, pull #\pull
+15:             mov     r3, lr, lspull #\pull
                ldr1w   r1, lr, abort=21f
                subs    ip, ip, #4
-                orr     r3, r3, lr, push #\push
+                orr     r3, r3, lr, lspush #\push
                str1w   r0, r3, abort=21f
                bgt     15b
        CALGN(  cmp     r2, #0                  )
diff --git a/arch/arm/lib/csumpartialcopygeneric.S b/arch/arm/lib/csumpartialcopygeneric.S
index d620a5f22a09..d6e742d24007 100644
--- a/arch/arm/lib/csumpartialcopygeneric.S
+++ b/arch/arm/lib/csumpartialcopygeneric.S
@@ -141,7 +141,7 @@ FN_ENTRY
                tst     len, #2
                mov     r5, r4, get_byte_0
                beq     .Lexit
-                adcs    sum, sum, r4, push #16
+                adcs    sum, sum, r4, lspush #16
                strb    r5, [dst], #1
                mov     r5, r4, get_byte_1
                strb    r5, [dst], #1
@@ -171,23 +171,23 @@ FN_ENTRY
                cmp     ip, #2
                beq     .Lsrc2_aligned
                bhi     .Lsrc3_aligned
-                mov     r4, r5, pull #8         @ C = 0
+                mov     r4, r5, lspull #8               @ C = 0
                bics    ip, len, #15
                beq     2f
 1:              load4l  r5, r6, r7, r8
-                orr     r4, r4, r5, push #24
+                orr     r4, r4, r5, lspush #24
-                mov     r5, r5, pull #8
+                mov     r5, r5, lspull #8
-                orr     r5, r5, r6, push #24
+                orr     r5, r5, r6, lspush #24
-                mov     r6, r6, pull #8
+                mov     r6, r6, lspull #8
-                orr     r6, r6, r7, push #24
+                orr     r6, r6, r7, lspush #24
-                mov     r7, r7, pull #8
+                mov     r7, r7, lspull #8
-                orr     r7, r7, r8, push #24
+                orr     r7, r7, r8, lspush #24
                stmia   dst!, {r4, r5, r6, r7}
                adcs    sum, sum, r4
                adcs    sum, sum, r5
                adcs    sum, sum, r6
                adcs    sum, sum, r7
-                mov     r4, r8, pull #8
+                mov     r4, r8, lspull #8
                sub     ip, ip, #16
                teq     ip, #0
                bne     1b
@@ -196,50 +196,50 @@ FN_ENTRY
                tst     ip, #8
                beq     3f
                load2l  r5, r6
-                orr     r4, r4, r5, push #24
+                orr     r4, r4, r5, lspush #24
-                mov     r5, r5, pull #8
+                mov     r5, r5, lspull #8
-                orr     r5, r5, r6, push #24
+                orr     r5, r5, r6, lspush #24
                stmia   dst!, {r4, r5}
                adcs    sum, sum, r4
                adcs    sum, sum, r5
-                mov     r4, r6, pull #8
+                mov     r4, r6, lspull #8
                tst     ip, #4
                beq     4f
 3:              load1l  r5
-                orr     r4, r4, r5, push #24
+                orr     r4, r4, r5, lspush #24
                str     r4, [dst], #4
                adcs    sum, sum, r4
-                mov     r4, r5, pull #8
+                mov     r4, r5, lspull #8
 4:              ands    len, len, #3
                beq     .Ldone
                mov     r5, r4, get_byte_0
                tst     len, #2
                beq     .Lexit
-                adcs    sum, sum, r4, push #16
+                adcs    sum, sum, r4, lspush #16
                strb    r5, [dst], #1
                mov     r5, r4, get_byte_1
                strb    r5, [dst], #1
                mov     r5, r4, get_byte_2
                b       .Lexit
-.Lsrc2_aligned: mov     r4, r5, pull #16
+.Lsrc2_aligned: mov     r4, r5, lspull #16
                adds    sum, sum, #0
                bics    ip, len, #15
                beq     2f
 1:              load4l  r5, r6, r7, r8
-                orr     r4, r4, r5, push #16
+                orr     r4, r4, r5, lspush #16
-                mov     r5, r5, pull #16
+                mov     r5, r5, lspull #16
-                orr     r5, r5, r6, push #16
+                orr     r5, r5, r6, lspush #16
-                mov     r6, r6, pull #16
+                mov     r6, r6, lspull #16
-                orr     r6, r6, r7, push #16
+                orr     r6, r6, r7, lspush #16
-                mov     r7, r7, pull #16
+                mov     r7, r7, lspull #16
-                orr     r7, r7, r8, push #16
+                orr     r7, r7, r8, lspush #16
                stmia   dst!, {r4, r5, r6, r7}
                adcs    sum, sum, r4
                adcs    sum, sum, r5
                adcs    sum, sum, r6
                adcs    sum, sum, r7
-                mov     r4, r8, pull #16
+                mov     r4, r8, lspull #16
                sub     ip, ip, #16
                teq     ip, #0
                bne     1b
@@ -248,20 +248,20 @@ FN_ENTRY
                tst     ip, #8
                beq     3f
                load2l  r5, r6
-                orr     r4, r4, r5, push #16
+                orr     r4, r4, r5, lspush #16
-                mov     r5, r5, pull #16
+                mov     r5, r5, lspull #16
-                orr     r5, r5, r6, push #16
+                orr     r5, r5, r6, lspush #16
                stmia   dst!, {r4, r5}
                adcs    sum, sum, r4
                adcs    sum, sum, r5
-                mov     r4, r6, pull #16
+                mov     r4, r6, lspull #16
                tst     ip, #4
                beq     4f
 3:              load1l  r5
-                orr     r4, r4, r5, push #16
+                orr     r4, r4, r5, lspush #16
                str     r4, [dst], #4
                adcs    sum, sum, r4
-                mov     r4, r5, pull #16
+                mov     r4, r5, lspull #16
 4:              ands    len, len, #3
                beq     .Ldone
                mov     r5, r4, get_byte_0
@@ -276,24 +276,24 @@ FN_ENTRY
                load1b  r5
                b       .Lexit
-.Lsrc3_aligned: mov     r4, r5, pull #24
+.Lsrc3_aligned: mov     r4, r5, lspull #24
                adds    sum, sum, #0
                bics    ip, len, #15
                beq     2f
 1:              load4l  r5, r6, r7, r8
-                orr     r4, r4, r5, push #8
+                orr     r4, r4, r5, lspush #8
-                mov     r5, r5, pull #24
+                mov     r5, r5, lspull #24
-                orr     r5, r5, r6, push #8
+                orr     r5, r5, r6, lspush #8
-                mov     r6, r6, pull #24
+                mov     r6, r6, lspull #24
-                orr     r6, r6, r7, push #8
+                orr     r6, r6, r7, lspush #8
-                mov     r7, r7, pull #24
+                mov     r7, r7, lspull #24
-                orr     r7, r7, r8, push #8
+                orr     r7, r7, r8, lspush #8
                stmia   dst!, {r4, r5, r6, r7}
                adcs    sum, sum, r4
                adcs    sum, sum, r5
                adcs    sum, sum, r6
                adcs    sum, sum, r7
-                mov     r4, r8, pull #24
+                mov     r4, r8, lspull #24
                sub     ip, ip, #16
                teq     ip, #0
                bne     1b
@@ -302,20 +302,20 @@ FN_ENTRY
                tst     ip, #8
                beq     3f
                load2l  r5, r6
-                orr     r4, r4, r5, push #8
+                orr     r4, r4, r5, lspush #8
-                mov     r5, r5, pull #24
+                mov     r5, r5, lspull #24
-                orr     r5, r5, r6, push #8
+                orr     r5, r5, r6, lspush #8
                stmia   dst!, {r4, r5}
                adcs    sum, sum, r4
                adcs    sum, sum, r5
-                mov     r4, r6, pull #24
+                mov     r4, r6, lspull #24
                tst     ip, #4
                beq     4f
 3:              load1l  r5
-                orr     r4, r4, r5, push #8
+                orr     r4, r4, r5, lspush #8
                str     r4, [dst], #4
                adcs    sum, sum, r4
-                mov     r4, r5, pull #24
+                mov     r4, r5, lspull #24
 4:              ands    len, len, #3
                beq     .Ldone
                mov     r5, r4, get_byte_0
@@ -326,7 +326,7 @@ FN_ENTRY
                load1l  r4
                mov     r5, r4, get_byte_0
                strb    r5, [dst], #1
-                adcs    sum, sum, r4, push #24
+                adcs    sum, sum, r4, lspush #24
                mov     r5, r4, get_byte_1
                b       .Lexit
 FN_EXIT
diff --git a/arch/arm/lib/io-readsl.S b/arch/arm/lib/io-readsl.S
index 5fb97e7f9f4b..7a7430950c79 100644
--- a/arch/arm/lib/io-readsl.S
+++ b/arch/arm/lib/io-readsl.S
@@ -47,25 +47,25 @@ ENTRY(__raw_readsl)
                strb    ip, [r1], #1
 4:              subs    r2, r2, #1
-                mov     ip, r3, pull #24
+                mov     ip, r3, lspull #24
                ldrne   r3, [r0]
-                orrne   ip, ip, r3, push #8
+                orrne   ip, ip, r3, lspush #8
                strne   ip, [r1], #4
                bne     4b
                b       8f
 5:              subs    r2, r2, #1
-                mov     ip, r3, pull #16
+                mov     ip, r3, lspull #16
                ldrne   r3, [r0]
-                orrne   ip, ip, r3, push #16
+                orrne   ip, ip, r3, lspush #16
                strne   ip, [r1], #4
                bne     5b
                b       7f
 6:              subs    r2, r2, #1
-                mov     ip, r3, pull #8
+                mov     ip, r3, lspull #8
                ldrne   r3, [r0]
-                orrne   ip, ip, r3, push #24
+                orrne   ip, ip, r3, lspush #24
                strne   ip, [r1], #4
                bne     6b
diff --git a/arch/arm/lib/io-writesl.S b/arch/arm/lib/io-writesl.S
index 8d3b7813725c..d0d104a0dd11 100644
--- a/arch/arm/lib/io-writesl.S
+++ b/arch/arm/lib/io-writesl.S
@@ -41,26 +41,26 @@ ENTRY(__raw_writesl)
                blt     5f
                bgt     6f
-4:              mov     ip, r3, pull #16
+4:              mov     ip, r3, lspull #16
                ldr     r3, [r1], #4
                subs    r2, r2, #1
-                orr     ip, ip, r3, push #16
+                orr     ip, ip, r3, lspush #16
                str     ip, [r0]
                bne     4b
                mov     pc, lr
-5:              mov     ip, r3, pull #8
+5:              mov     ip, r3, lspull #8
                ldr     r3, [r1], #4
                subs    r2, r2, #1
-                orr     ip, ip, r3, push #24
+                orr     ip, ip, r3, lspush #24
                str     ip, [r0]
                bne     5b
                mov     pc, lr
-6:              mov     ip, r3, pull #24
+6:              mov     ip, r3, lspull #24
                ldr     r3, [r1], #4
                subs    r2, r2, #1
-                orr     ip, ip, r3, push #8
+                orr     ip, ip, r3, lspush #8
                str     ip, [r0]
                bne     6b
                mov     pc, lr
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index 938fc14f962d..d1fc0c0c342c 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -147,24 +147,24 @@ ENTRY(memmove)
 12:     PLD(    pld     [r1, #-128]             )
 13:             ldmdb   r1!, {r7, r8, r9, ip}
-                mov     lr, r3, push #\push
+                mov     lr, r3, lspush #\push
                subs    r2, r2, #32
                ldmdb   r1!, {r3, r4, r5, r6}
-                orr     lr, lr, ip, pull #\pull
+                orr     lr, lr, ip, lspull #\pull
-                mov     ip, ip, push #\push
+                mov     ip, ip, lspush #\push
-                orr     ip, ip, r9, pull #\pull
+                orr     ip, ip, r9, lspull #\pull
-                mov     r9, r9, push #\push
+                mov     r9, r9, lspush #\push
-                orr     r9, r9, r8, pull #\pull
+                orr     r9, r9, r8, lspull #\pull
-                mov     r8, r8, push #\push
+                mov     r8, r8, lspush #\push
-                orr     r8, r8, r7, pull #\pull
+                orr     r8, r8, r7, lspull #\pull
-                mov     r7, r7, push #\push
+                mov     r7, r7, lspush #\push
-                orr     r7, r7, r6, pull #\pull
+                orr     r7, r7, r6, lspull #\pull
-                mov     r6, r6, push #\push
+                mov     r6, r6, lspush #\push
-                orr     r6, r6, r5, pull #\pull
+                orr     r6, r6, r5, lspull #\pull
-                mov     r5, r5, push #\push
+                mov     r5, r5, lspush #\push
-                orr     r5, r5, r4, pull #\pull
+                orr     r5, r5, r4, lspull #\pull
-                mov     r4, r4, push #\push
+                mov     r4, r4, lspush #\push
-                orr     r4, r4, r3, pull #\pull
+                orr     r4, r4, r3, lspull #\pull
                stmdb   r0!, {r4 - r9, ip, lr}
                bge     12b
        PLD(    cmn     r2, #96                 )
@@ -175,10 +175,10 @@ ENTRY(memmove)
 14:             ands    ip, r2, #28
                beq     16f
-15:             mov     lr, r3, push #\push
+15:             mov     lr, r3, lspush #\push
                ldr     r3, [r1, #-4]!
                subs    ip, ip, #4
-                orr     lr, lr, r3, pull #\pull
+                orr     lr, lr, r3, lspull #\pull
                str     lr, [r0, #-4]!
                bgt     15b
        CALGN(  cmp     r2, #0                  )
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index 5c908b1cb8ed..e50520904b76 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -117,9 +117,9 @@ USER(	TUSER(	strgtb) r3, [r0], #1)			@ May fault
 .Lc2u_1fupi:    subs    r2, r2, #4
                addmi   ip, r2, #4
                bmi     .Lc2u_1nowords
-                mov     r3, r7, pull #8
+                mov     r3, r7, lspull #8
                ldr     r7, [r1], #4
-                orr     r3, r3, r7, push #24
+                orr     r3, r3, r7, lspush #24
 USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
                mov     ip, r0, lsl #32 - PAGE_SHIFT
                rsb     ip, ip, #0
@@ -131,30 +131,30 @@ USER(	TUSER(	str)	r3, [r0], #4)			@ May fault
                subs    ip, ip, #16
                blt     .Lc2u_1rem8lp
-.Lc2u_1cpy8lp:  mov     r3, r7, pull #8
+.Lc2u_1cpy8lp:  mov     r3, r7, lspull #8
                ldmia   r1!, {r4 - r7}
                subs    ip, ip, #16
-                orr     r3, r3, r4, push #24
+                orr     r3, r3, r4, lspush #24
-                mov     r4, r4, pull #8
+                mov     r4, r4, lspull #8
-                orr     r4, r4, r5, push #24
+                orr     r4, r4, r5, lspush #24
-                mov     r5, r5, pull #8
+                mov     r5, r5, lspull #8
-                orr     r5, r5, r6, push #24
+                orr     r5, r5, r6, lspush #24
-                mov     r6, r6, pull #8
+                mov     r6, r6, lspull #8
-                orr     r6, r6, r7, push #24
+                orr     r6, r6, r7, lspush #24
                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
                bpl     .Lc2u_1cpy8lp
 .Lc2u_1rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #8
+                movne   r3, r7, lspull #8
                ldmneia r1!, {r4, r7}
-                orrne   r3, r3, r4, push #24
+                orrne   r3, r3, r4, lspush #24
-                movne   r4, r4, pull #8
+                movne   r4, r4, lspull #8
-                orrne   r4, r4, r7, push #24
+                orrne   r4, r4, r7, lspush #24
                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
                tst     ip, #4
-                movne   r3, r7, pull #8
+                movne   r3, r7, lspull #8
                ldrne   r7, [r1], #4
-                orrne   r3, r3, r7, push #24
+                orrne   r3, r3, r7, lspush #24
        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
                ands    ip, ip, #3
                beq     .Lc2u_1fupi
@@ -172,9 +172,9 @@ USER(	TUSER(	strgtb) r3, [r0], #1)			@ May fault
 .Lc2u_2fupi:    subs    r2, r2, #4
                addmi   ip, r2, #4
                bmi     .Lc2u_2nowords
-                mov     r3, r7, pull #16
+                mov     r3, r7, lspull #16
                ldr     r7, [r1], #4
-                orr     r3, r3, r7, push #16
+                orr     r3, r3, r7, lspush #16
 USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
                mov     ip, r0, lsl #32 - PAGE_SHIFT
                rsb     ip, ip, #0
@@ -186,30 +186,30 @@ USER(	TUSER(	str)	r3, [r0], #4)			@ May fault
                subs    ip, ip, #16
                blt     .Lc2u_2rem8lp
-.Lc2u_2cpy8lp:  mov     r3, r7, pull #16
+.Lc2u_2cpy8lp:  mov     r3, r7, lspull #16
                ldmia   r1!, {r4 - r7}
                subs    ip, ip, #16
-                orr     r3, r3, r4, push #16
+                orr     r3, r3, r4, lspush #16
-                mov     r4, r4, pull #16
+                mov     r4, r4, lspull #16
-                orr     r4, r4, r5, push #16
+                orr     r4, r4, r5, lspush #16
-                mov     r5, r5, pull #16
+                mov     r5, r5, lspull #16
-                orr     r5, r5, r6, push #16
+                orr     r5, r5, r6, lspush #16
-                mov     r6, r6, pull #16
+                mov     r6, r6, lspull #16
-                orr     r6, r6, r7, push #16
+                orr     r6, r6, r7, lspush #16
                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
                bpl     .Lc2u_2cpy8lp
 .Lc2u_2rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #16
+                movne   r3, r7, lspull #16
                ldmneia r1!, {r4, r7}
-                orrne   r3, r3, r4, push #16
+                orrne   r3, r3, r4, lspush #16
-                movne   r4, r4, pull #16
+                movne   r4, r4, lspull #16
-                orrne   r4, r4, r7, push #16
+                orrne   r4, r4, r7, lspush #16
                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
                tst     ip, #4
-                movne   r3, r7, pull #16
+                movne   r3, r7, lspull #16
                ldrne   r7, [r1], #4
-                orrne   r3, r3, r7, push #16
+                orrne   r3, r3, r7, lspush #16
        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
                ands    ip, ip, #3
                beq     .Lc2u_2fupi
@@ -227,9 +227,9 @@ USER(	TUSER(	strgtb) r3, [r0], #1)			@ May fault
 .Lc2u_3fupi:    subs    r2, r2, #4
                addmi   ip, r2, #4
                bmi     .Lc2u_3nowords
-                mov     r3, r7, pull #24
+                mov     r3, r7, lspull #24
                ldr     r7, [r1], #4
-                orr     r3, r3, r7, push #8
+                orr     r3, r3, r7, lspush #8
 USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
                mov     ip, r0, lsl #32 - PAGE_SHIFT
                rsb     ip, ip, #0
@@ -241,30 +241,30 @@ USER(	TUSER(	str)	r3, [r0], #4)			@ May fault
                subs    ip, ip, #16
                blt     .Lc2u_3rem8lp
-.Lc2u_3cpy8lp:  mov     r3, r7, pull #24
+.Lc2u_3cpy8lp:  mov     r3, r7, lspull #24
                ldmia   r1!, {r4 - r7}
                subs    ip, ip, #16
-                orr     r3, r3, r4, push #8
+                orr     r3, r3, r4, lspush #8
-                mov     r4, r4, pull #24
+                mov     r4, r4, lspull #24
-                orr     r4, r4, r5, push #8
+                orr     r4, r4, r5, lspush #8
-                mov     r5, r5, pull #24
+                mov     r5, r5, lspull #24
-                orr     r5, r5, r6, push #8
+                orr     r5, r5, r6, lspush #8
-                mov     r6, r6, pull #24
+                mov     r6, r6, lspull #24
-                orr     r6, r6, r7, push #8
+                orr     r6, r6, r7, lspush #8
                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
                bpl     .Lc2u_3cpy8lp
 .Lc2u_3rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #24
+                movne   r3, r7, lspull #24
                ldmneia r1!, {r4, r7}
-                orrne   r3, r3, r4, push #8
+                orrne   r3, r3, r4, lspush #8
-                movne   r4, r4, pull #24
+                movne   r4, r4, lspull #24
-                orrne   r4, r4, r7, push #8
+                orrne   r4, r4, r7, lspush #8
                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
                tst     ip, #4
-                movne   r3, r7, pull #24
+                movne   r3, r7, lspull #24
                ldrne   r7, [r1], #4
-                orrne   r3, r3, r7, push #8
+                orrne   r3, r3, r7, lspush #8
        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
                ands    ip, ip, #3
                beq     .Lc2u_3fupi
@@ -382,9 +382,9 @@ USER(	TUSER(	ldr)	r7, [r1], #4)			@ May fault
 .Lcfu_1fupi:    subs    r2, r2, #4
                addmi   ip, r2, #4
                bmi     .Lcfu_1nowords
-                mov     r3, r7, pull #8
+                mov     r3, r7, lspull #8
 USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
-                orr     r3, r3, r7, push #24
+                orr     r3, r3, r7, lspush #24
                str     r3, [r0], #4
                mov     ip, r1, lsl #32 - PAGE_SHIFT
                rsb     ip, ip, #0
@@ -396,30 +396,30 @@ USER(	TUSER(	ldr)	r7, [r1], #4)			@ May fault
                subs    ip, ip, #16
                blt     .Lcfu_1rem8lp
-.Lcfu_1cpy8lp:  mov     r3, r7, pull #8
+.Lcfu_1cpy8lp:  mov     r3, r7, lspull #8
                ldmia   r1!, {r4 - r7}                  @ Shouldnt fault
                subs    ip, ip, #16
-                orr     r3, r3, r4, push #24
+                orr     r3, r3, r4, lspush #24
-                mov     r4, r4, pull #8
+                mov     r4, r4, lspull #8
-                orr     r4, r4, r5, push #24
+                orr     r4, r4, r5, lspush #24
-                mov     r5, r5, pull #8
+                mov     r5, r5, lspull #8
-                orr     r5, r5, r6, push #24
+                orr     r5, r5, r6, lspush #24
-                mov     r6, r6, pull #8
+                mov     r6, r6, lspull #8
-                orr     r6, r6, r7, push #24
+                orr     r6, r6, r7, lspush #24
                stmia   r0!, {r3 - r6}
                bpl     .Lcfu_1cpy8lp
 .Lcfu_1rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #8
+                movne   r3, r7, lspull #8
                ldmneia r1!, {r4, r7}                   @ Shouldnt fault
-                orrne   r3, r3, r4, push #24
+                orrne   r3, r3, r4, lspush #24
-                movne   r4, r4, pull #8
+                movne   r4, r4, lspull #8
-                orrne   r4, r4, r7, push #24
+                orrne   r4, r4, r7, lspush #24
                stmneia r0!, {r3 - r4}
                tst     ip, #4
-                movne   r3, r7, pull #8
+                movne   r3, r7, lspull #8
 USER(   TUSER(  ldrne) r7, [r1], #4)                    @ May fault
-                orrne   r3, r3, r7, push #24
+                orrne   r3, r3, r7, lspush #24
                strne   r3, [r0], #4
                ands    ip, ip, #3
                beq     .Lcfu_1fupi
@@ -437,9 +437,9 @@ USER(	TUSER(	ldrne) r7, [r1], #4)			@ May fault
 .Lcfu_2fupi:    subs    r2, r2, #4
                addmi   ip, r2, #4
                bmi     .Lcfu_2nowords
-                mov     r3, r7, pull #16
+                mov     r3, r7, lspull #16
 USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
-                orr     r3, r3, r7, push #16
+                orr     r3, r3, r7, lspush #16
                str     r3, [r0], #4
                mov     ip, r1, lsl #32 - PAGE_SHIFT
                rsb     ip, ip, #0
@@ -452,30 +452,30 @@ USER(	TUSER(	ldr)	r7, [r1], #4)			@ May fault
                blt     .Lcfu_2rem8lp
-.Lcfu_2cpy8lp:  mov     r3, r7, pull #16
+.Lcfu_2cpy8lp:  mov     r3, r7, lspull #16
                ldmia   r1!, {r4 - r7}                  @ Shouldnt fault
                subs    ip, ip, #16
-                orr     r3, r3, r4, push #16
+                orr     r3, r3, r4, lspush #16
-                mov     r4, r4, pull #16
+                mov     r4, r4, lspull #16
-                orr     r4, r4, r5, push #16
+                orr     r4, r4, r5, lspush #16
-                mov     r5, r5, pull #16
+                mov     r5, r5, lspull #16
-                orr     r5, r5, r6, push #16
+                orr     r5, r5, r6, lspush #16
-                mov     r6, r6, pull #16
+                mov     r6, r6, lspull #16
-                orr     r6, r6, r7, push #16
+                orr     r6, r6, r7, lspush #16
                stmia   r0!, {r3 - r6}
                bpl     .Lcfu_2cpy8lp
 .Lcfu_2rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #16
+                movne   r3, r7, lspull #16
                ldmneia r1!, {r4, r7}                   @ Shouldnt fault
-                orrne   r3, r3, r4, push #16
+                orrne   r3, r3, r4, lspush #16
-                movne   r4, r4, pull #16
+                movne   r4, r4, lspull #16
-                orrne   r4, r4, r7, push #16
+                orrne   r4, r4, r7, lspush #16
                stmneia r0!, {r3 - r4}
                tst     ip, #4
-                movne   r3, r7, pull #16
+                movne   r3, r7, lspull #16
 USER(   TUSER(  ldrne) r7, [r1], #4)                    @ May fault
-                orrne   r3, r3, r7, push #16
+                orrne   r3, r3, r7, lspush #16
                strne   r3, [r0], #4
                ands    ip, ip, #3
                beq     .Lcfu_2fupi
@@ -493,9 +493,9 @@ USER(	TUSER(	ldrgtb) r3, [r1], #0)			@ May fault
 .Lcfu_3fupi:    subs    r2, r2, #4
                addmi   ip, r2, #4
                bmi     .Lcfu_3nowords
-                mov     r3, r7, pull #24
+                mov     r3, r7, lspull #24
 USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
-                orr     r3, r3, r7, push #8
+                orr     r3, r3, r7, lspush #8
                str     r3, [r0], #4
                mov     ip, r1, lsl #32 - PAGE_SHIFT
                rsb     ip, ip, #0
@@ -507,30 +507,30 @@ USER(	TUSER(	ldr)	r7, [r1], #4)			@ May fault
                subs    ip, ip, #16
                blt     .Lcfu_3rem8lp
-.Lcfu_3cpy8lp:  mov     r3, r7, pull #24
+.Lcfu_3cpy8lp:  mov     r3, r7, lspull #24
                ldmia   r1!, {r4 - r7}                  @ Shouldnt fault
-                orr     r3, r3, r4, push #8
+                orr     r3, r3, r4, lspush #8
-                mov     r4, r4, pull #24
+                mov     r4, r4, lspull #24
-                orr     r4, r4, r5, push #8
+                orr     r4, r4, r5, lspush #8
-                mov     r5, r5, pull #24
+                mov     r5, r5, lspull #24
-                orr     r5, r5, r6, push #8
+                orr     r5, r5, r6, lspush #8
-                mov     r6, r6, pull #24
+                mov     r6, r6, lspull #24
-                orr     r6, r6, r7, push #8
+                orr     r6, r6, r7, lspush #8
                stmia   r0!, {r3 - r6}
                subs    ip, ip, #16
                bpl     .Lcfu_3cpy8lp
 .Lcfu_3rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #24
+                movne   r3, r7, lspull #24
                ldmneia r1!, {r4, r7}                   @ Shouldnt fault
-                orrne   r3, r3, r4, push #8
+                orrne   r3, r3, r4, lspush #8
-                movne   r4, r4, pull #24
+                movne   r4, r4, lspull #24
-                orrne   r4, r4, r7, push #8
+                orrne   r4, r4, r7, lspush #8
                stmneia r0!, {r3 - r4}
                tst     ip, #4
-                movne   r3, r7, pull #24
+                movne   r3, r7, lspull #24
 USER(   TUSER(  ldrne) r7, [r1], #4)                    @ May fault
-                orrne   r3, r3, r7, push #8
+                orrne   r3, r3, r7, lspush #8
                strne   r3, [r0], #4
                ands    ip, ip, #3
                beq     .Lcfu_3fupi
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 4f0e800e7e71..b2d2cf4dc052 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -57,6 +57,7 @@ config SOC_SAMA5
        select GENERIC_CLOCKEVENTS
        select MULTI_IRQ_HANDLER
        select SPARSE_IRQ
+        select USE_OF
 menu "Atmel AT91 System-on-Chip"
@@ -64,11 +65,22 @@ choice
        prompt "Core type"
+config ARCH_AT91X40
+        bool "ARM7 AT91X40"
+        depends on !MMU
+        select CPU_ARM7TDMI
+        select ARCH_USES_GETTIMEOFFSET
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+        help
+          Select this if you are using one of Atmel's AT91X40 SoC.
 config SOC_SAM_V4_V5
-        bool "ARM7/ARM9"
+        bool "ARM9 AT91SAM9/AT91RM9200"
        help
-          Select this if you are using one of Atmel's AT91SAM9, AT91RM9200
+          Select this if you are using one of Atmel's AT91SAM9 or
-          or AT91X40 SoC.
+          AT91RM9200 SoC.
 config SOC_SAM_V7
        bool "Cortex A5"
@@ -119,7 +131,6 @@ config SOC_AT91SAM9261
        select HAVE_AT91_DBGU0
        select HAVE_FB_ATMEL
        select SOC_AT91SAM9
-        select AT91_USE_OLD_CLK
        select HAVE_AT91_USB_CLK
        help
          Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
@@ -137,7 +148,6 @@ config SOC_AT91SAM9RL
        select HAVE_AT91_DBGU0
        select HAVE_FB_ATMEL
        select SOC_AT91SAM9
-        select AT91_USE_OLD_CLK
        select HAVE_AT91_UTMI
 config SOC_AT91SAM9G45
@@ -179,9 +189,12 @@ config SOC_AT91SAM9N12
          Select this if you are using Atmel's AT91SAM9N12 SoC.
 # ----------------------------------------------------------
+endif # SOC_SAM_V4_V5
+if SOC_SAM_V4_V5 || ARCH_AT91X40
 source arch/arm/mach-at91/Kconfig.non_dt
-endif # SOC_SAM_V4_V5
+endif
 comment "Generic Board Type"
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 1f73e9b527da..44ace320d2e1 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -5,6 +5,7 @@ config HAVE_AT91_DATAFLASH_CARD
 choice
        prompt "Atmel AT91 Processor Devices for non DT boards"
+        depends on !ARCH_AT91X40
 config ARCH_AT91_NONE
        bool "None"
@@ -39,13 +40,6 @@ config ARCH_AT91SAM9G45
        select SOC_AT91SAM9G45
        select AT91_USE_OLD_CLK
-config ARCH_AT91X40
-        bool "AT91x40"
-        depends on !MMU
-        select ARCH_USES_GETTIMEOFFSET
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
 endchoice
 config ARCH_AT91SAM9G20
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index e47f5fd232f5..787bb50a4dff 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -21,6 +21,7 @@
 #include <mach/at91rm9200.h>
 #include <mach/at91_st.h>
 #include <mach/cpu.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "soc.h"
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 3ebc9792560c..f3f19f21352a 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -21,6 +21,7 @@
 #include <mach/at91rm9200.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
+#include <mach/hardware.h>
 #include "board.h"
 #include "generic.h"
@@ -922,6 +923,7 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -960,6 +962,7 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -987,9 +990,10 @@ static inline void configure_usart0_pins(unsigned pins)
        if (pins & ATMEL_UART_RTS) {
                /*
                 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
-                 *  We need to drive the pin manually.  Default is off (RTS is active low).
+                 * We need to drive the pin manually. The serial driver will driver
+                 * this to high when initializing.
                 */
-                at91_set_gpio_output(AT91_PIN_PA21, 1);
+                uart0_data.rts_gpio = AT91_PIN_PA21;
        }
 }
@@ -1009,6 +1013,7 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1060,6 +1065,7 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
@@ -1103,6 +1109,7 @@ static struct resource uart3_resources[] = {
 static struct atmel_uart_data uart3_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart3_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index bc7b363a3083..7fd13aef9827 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -31,6 +31,7 @@
 #include <asm/mach/time.h>
 #include <mach/at91_st.h>
+#include <mach/hardware.h>
 static unsigned long last_crtr;
 static u32 irqmask;
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 6c821e562159..c3d22be73b7c 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -21,6 +21,7 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index eda8d1679d40..8b1b0a870025 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -25,6 +25,7 @@
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_adc.h>
+#include <mach/hardware.h>
 #include "board.h"
 #include "generic.h"
@@ -819,6 +820,7 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -857,6 +859,7 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -908,6 +911,7 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -951,6 +955,7 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
@@ -994,6 +999,7 @@ static struct resource uart3_resources[] = {
 static struct atmel_uart_data uart3_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart3_dmamask = DMA_BIT_MASK(32);
@@ -1037,6 +1043,7 @@ static struct resource uart4_resources[] = {
 static struct atmel_uart_data uart4_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart4_dmamask = DMA_BIT_MASK(32);
@@ -1075,6 +1082,7 @@ static struct resource uart5_resources[] = {
 static struct atmel_uart_data uart5_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart5_dmamask = DMA_BIT_MASK(32);
@@ -1255,12 +1263,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        at91_set_A_periph(AT91_PIN_PC10, 0);    /* CFRNW */
        at91_set_A_periph(AT91_PIN_PC15, 1);    /* NWAIT */
-        if (data->flags & AT91_CF_TRUE_IDE)
+        if (IS_ENABLED(CONFIG_PATA_AT91) && (data->flags & AT91_CF_TRUE_IDE))
-#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
                pdev->name = "pata_at91";
-#else
-#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91"
-#endif
        else
                pdev->name = "at91_cf";
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 6276b4c1acfe..fb164a5d04a9 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -20,15 +20,18 @@
 #include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
-#include "clock.h"
 #include "sam9_smc.h"
 #include "pm.h"
+#if defined(CONFIG_OLD_CLK_AT91)
+#include "clock.h"
 /* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */
@@ -189,6 +192,23 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_ID("pioA", &pioA_clk),
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
+        /* more lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
+        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &hck0),
+        CLKDEV_CON_DEV_ID("hclk", "600000.fb", &hck1),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -247,7 +267,9 @@ static void __init at91sam9261_register_clocks(void)
        clk_register(&hck0);
        clk_register(&hck1);
 }
+#else
+#define at91sam9261_register_clocks NULL
+#endif
 /* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index b2a34740146a..80e35895d28f 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -25,6 +25,7 @@
 #include <mach/at91sam9261_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/hardware.h>
 #include "board.h"
 #include "generic.h"
@@ -880,6 +881,7 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -918,6 +920,7 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -961,6 +964,7 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1004,6 +1008,7 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 37b90f4b990c..f30290572293 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -19,6 +19,7 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "at91_rstc.h"
@@ -223,6 +224,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 4aeadddbc181..43d53d6156dd 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -24,6 +24,7 @@
 #include <mach/at91sam9263_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/hardware.h>
 #include "board.h"
 #include "generic.h"
@@ -1324,6 +1325,7 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -1362,6 +1364,7 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -1405,6 +1408,7 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1448,6 +1452,7 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 0f04ffe9c5a8..0a9e2fc8f796 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -19,6 +19,7 @@
 #include <linux/of_irq.h>
 #include <asm/mach/time.h>
+#include <mach/hardware.h>
 #define AT91_PIT_MR             0x00                    /* Mode Register */
 #define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 2f455ce35268..5e6f498db0a8 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -20,6 +20,7 @@
 #include <asm/system_misc.h>
 #include <mach/at91sam9g45.h>
 #include <mach/cpu.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "soc.h"
@@ -284,6 +285,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_ID("pioE", &pioDE_clk),
        /* Fake adc clock */
        CLKDEV_CON_ID("adc_clk", &tsc_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index cb36fa872d30..77b04c2edd78 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -32,6 +32,7 @@
 #include <mach/at91sam9_smc.h>
 #include <linux/platform_data/dma-atmel.h>
 #include <mach/atmel-mci.h>
+#include <mach/hardware.h>
 #include <media/atmel-isi.h>
@@ -1587,6 +1588,7 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,
+        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -1625,6 +1627,7 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -1668,6 +1671,7 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1711,6 +1715,7 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
@@ -1754,6 +1759,7 @@ static struct resource uart3_resources[] = {
 static struct atmel_uart_data uart3_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart3_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 4ef088c62eab..f2ea7b0a02da 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -182,6 +182,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        /* additional fake clock for macb_hclk */
        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
        CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
 };
 /*
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 3651517abedf..57f12d86c0e6 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -20,18 +20,20 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "at91_rstc.h"
 #include "soc.h"
 #include "generic.h"
-#include "clock.h"
 #include "sam9_smc.h"
 #include "pm.h"
 /* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */
+#if defined(CONFIG_OLD_CLK_AT91)
+#include "clock.h"
 /*
 * The peripheral clocks.
@@ -196,6 +198,24 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_ID("pioB", &pioB_clk),
        CLKDEV_CON_ID("pioC", &pioC_clk),
        CLKDEV_CON_ID("pioD", &pioD_clk),
+        /* more lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
+        CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -238,6 +258,7 @@ static void __init at91sam9rl_register_clocks(void)
        clk_register(&pck0);
        clk_register(&pck1);
 }
+#endif
 /* --------------------------------------------------------------------
 *  GPIO
@@ -350,6 +371,8 @@ AT91_SOC_START(at91sam9rl)
        .default_irq_priority = at91sam9rl_default_irq_priority,
        .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
        .ioremap_registers = at91sam9rl_ioremap_registers,
+#if defined(CONFIG_OLD_CLK_AT91)
        .register_clocks = at91sam9rl_register_clocks,
+#endif
        .init = at91sam9rl_initialize,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index a698bdab2cce..428fc412aaf1 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -21,6 +21,7 @@
 #include <mach/at91sam9rl_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/hardware.h>
 #include <linux/platform_data/dma-atmel.h>
 #include "board.h"
@@ -956,6 +957,7 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -994,6 +996,7 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -1045,6 +1048,7 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1088,6 +1092,7 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
@@ -1131,6 +1136,7 @@ static struct resource uart3_resources[] = {
 static struct atmel_uart_data uart3_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
+        .rts_gpio       = -EINVAL,
 };
 static u64 uart3_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 3e8ec26e39dc..9ad781d5ee7c 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -253,6 +253,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
        CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
        CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
 };
 /*
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index bad94b84a46f..7523f1cdfe1d 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -19,7 +19,7 @@
 #include <asm/mach/arch.h>
 #include <mach/at91x40.h>
 #include <mach/at91_st.h>
-#include <mach/timex.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index c0e637adf65d..07d0bf2ac2da 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -25,6 +25,7 @@
 #include <linux/time.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <mach/at91x40.h>
 #include <asm/mach/time.h>
 #include "at91_tc.h"
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 3dab868b02fa..575b0be66ca8 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -13,6 +13,7 @@
 #include <linux/gpio.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/clk-provider.h>
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -25,6 +26,14 @@
 #include "generic.h"
+static void __init sam9_dt_timer_init(void)
+{
+#if defined(CONFIG_COMMON_CLK)
+        of_clk_init(NULL);
+#endif
+        at91sam926x_pit_init();
+}
 static const struct of_device_id irq_of_match[] __initconst = {
        { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
@@ -43,7 +52,7 @@ static const char *at91_dt_board_compat[] __initdata = {
 DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
        /* Maintainer: Atmel */
-        .init_time      = at91sam926x_pit_init,
+        .init_time      = sam9_dt_timer_init,
        .map_io         = at91_map_io,
        .handle_irq     = at91_aic_handle_irq,
        .init_early     = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index c1d61d247790..416bae8435ee 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -31,6 +31,7 @@
 #include <asm/mach/arch.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "board.h"
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 65c0d6b5ecba..5f25fa54eb93 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -30,6 +30,7 @@
 #include <asm/mach/arch.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "board.h"
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 869cbecf00b7..e4a5ac17cdbc 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -26,6 +26,7 @@
 #include <asm/mach/arch.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "board.h"
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index 90680217064e..38dca2bb027f 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -55,4 +55,6 @@
 #define AT91_PS_CR      (AT91_PS + 0)   /* PS Control register */
 #define AT91_PS_CR_CPU  (1 << 0)        /* CPU clock disable bit */
+#define AT91X40_MASTER_CLOCK    40000000
 #endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
deleted file mode 100644
index 5e917a66edd7..000000000000
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/timex.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-#include <mach/hardware.h>
-#ifdef CONFIG_ARCH_AT91X40
-#define AT91X40_MASTER_CLOCK    40000000
-#define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
-#else
-#define CLOCK_TICK_RATE         12345678
-#endif
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 590b52dea9f7..8bda1cefdf96 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -27,6 +27,7 @@
 #include <asm/mach/irq.h>
 #include <mach/cpu.h>
+#include <mach/hardware.h>
 #include "at91_aic.h"
 #include "generic.h"
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index b26156bf15db..826315af6d11 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -36,6 +36,7 @@ void sam9_smc_write_mode(int id, int cs,
 {
        sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
 }
+EXPORT_SYMBOL_GPL(sam9_smc_write_mode);
 static void sam9_smc_cs_configure(void __iomem *base,
                                        struct sam9_smc_config *config)
@@ -69,6 +70,7 @@ void sam9_smc_configure(int id, int cs,
 {
        sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
 }
+EXPORT_SYMBOL_GPL(sam9_smc_configure);
 static void sam9_smc_cs_read_mode(void __iomem *base,
                                        struct sam9_smc_config *config)
@@ -84,6 +86,7 @@ void sam9_smc_read_mode(int id, int cs,
 {
        sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
 }
+EXPORT_SYMBOL_GPL(sam9_smc_read_mode);
 static void sam9_smc_cs_read(void __iomem *base,
                                        struct sam9_smc_config *config)
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index f7ca97b7291e..f7a07a58ebb6 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -351,7 +351,7 @@ void __init at91_ioremap_matrix(u32 base_addr)
                panic("Impossible to ioremap at91_matrix_base\n");
 }
-#if defined(CONFIG_OF)
+#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
 static struct of_device_id rstc_ids[] = {
        { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
        { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index b1aa6a9b3bd1..49c914cd9c7a 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -16,12 +16,7 @@ config ARCH_BCM_MOBILE
        select ARM_ERRATA_754322
        select ARM_ERRATA_764369 if SMP
        select ARM_GIC
-        select CPU_V7
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_TIME
        select GPIO_BCM_KONA
-        select SPARSE_IRQ
        select TICK_ONESHOT
        select CACHE_L2X0
        select HAVE_ARM_ARCH_TIMER
@@ -32,6 +27,48 @@ config ARCH_BCM_MOBILE
          BCM11130, BCM11140, BCM11351, BCM28145 and
          BCM28155 variants.
+config ARCH_BCM2835
+        bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select ARM_ERRATA_411920
+        select ARM_TIMER_SP804
+        select CLKDEV_LOOKUP
+        select CLKSRC_OF
+        select CPU_V6
+        select GENERIC_CLOCKEVENTS
+        select PINCTRL
+        select PINCTRL_BCM2835
+        help
+          This enables support for the Broadcom BCM2835 SoC. This SoC is
+          used in the Raspberry Pi and Roku 2 devices.
+config ARCH_BCM_5301X
+        bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+        depends on MMU
+        select ARM_GIC
+        select CACHE_L2X0
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if SMP
+        select HAVE_SMP
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select ARM_GLOBAL_TIMER
+        select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+        select MIGHT_HAVE_PCI
+        help
+          Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+          This is a network SoC line mostly used in home routers and
+          wifi access points, it's internal name is Northstar.
+          This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+          BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+          BCM4708 and BCM4709.
+          Do not confuse this with the BCM4760 which is a totally
+          different SoC or with the older BCM47XX and BCM53XX based
+          network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 endmenu
 endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index c2ccd5a0f772..a326b28c4406 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2012-2013 Broadcom Corporation
+# Copyright (C) 2012-2014 Broadcom Corporation
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
@@ -10,6 +10,10 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-obj-$(CONFIG_ARCH_BCM_MOBILE)   := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
+obj-$(CONFIG_ARCH_BCM_MOBILE)   := board_bcm281xx.o board_bcm21664.o \
+                                bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
+obj-$(CONFIG_ARCH_BCM2835)      += board_bcm2835.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_bcm_kona_smc_asm.o       :=-Wa,-march=armv7-a$(plus_sec)
+obj-$(CONFIG_ARCH_BCM_5301X)    += bcm_5301x.o
diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c
new file mode 100644
index 000000000000..edff69761e04
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_5301x.c
@@ -0,0 +1,61 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ *
+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/siginfo.h>
+#include <asm/signal.h>
+static bool first_fault = true;
+static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
+                                 struct pt_regs *regs)
+{
+        if (fsr == 0x1c06 && first_fault) {
+                first_fault = false;
+                /*
+                 * These faults with code 0x1c06 happens for no good reason,
+                 * possibly left over from the CFE boot loader.
+                 */
+                pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
+                addr, fsr);
+                /* Returning non-zero causes fault display and panic */
+                return 0;
+        }
+        /* Others should cause a fault */
+        return 1;
+}
+static void __init bcm5301x_init_early(void)
+{
+        /* Install our hook */
+        hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
+                        "imprecise external abort");
+}
+static void __init bcm5301x_dt_init(void)
+{
+        l2x0_of_init(0, ~0UL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+static const char __initconst *bcm5301x_dt_compat[] = {
+        "brcm,bcm4708",
+        NULL,
+};
+DT_MACHINE_START(BCM5301X, "BCM5301X")
+        .init_early     = bcm5301x_init_early,
+        .init_machine   = bcm5301x_dt_init,
+        .dt_compat      = bcm5301x_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c
new file mode 100644
index 000000000000..acc1573fd005
--- /dev/null
+++ b/arch/arm/mach-bcm/board_bcm21664.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clocksource.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include "bcm_kona_smc.h"
+#include "kona.h"
+#define RSTMGR_DT_STRING                "brcm,bcm21664-resetmgr"
+#define RSTMGR_REG_WR_ACCESS_OFFSET     0
+#define RSTMGR_REG_CHIP_SOFT_RST_OFFSET 4
+#define RSTMGR_WR_PASSWORD              0xa5a5
+#define RSTMGR_WR_PASSWORD_SHIFT        8
+#define RSTMGR_WR_ACCESS_ENABLE         1
+static void bcm21664_restart(enum reboot_mode mode, const char *cmd)
+{
+        void __iomem *base;
+        struct device_node *resetmgr;
+        resetmgr = of_find_compatible_node(NULL, NULL, RSTMGR_DT_STRING);
+        if (!resetmgr) {
+                pr_emerg("Couldn't find " RSTMGR_DT_STRING "\n");
+                return;
+        }
+        base = of_iomap(resetmgr, 0);
+        if (!base) {
+                pr_emerg("Couldn't map " RSTMGR_DT_STRING "\n");
+                return;
+        }
+        /*
+         * A soft reset is triggered by writing a 0 to bit 0 of the soft reset
+         * register. To write to that register we must first write the password
+         * and the enable bit in the write access enable register.
+         */
+        writel((RSTMGR_WR_PASSWORD << RSTMGR_WR_PASSWORD_SHIFT) |
+                RSTMGR_WR_ACCESS_ENABLE,
+                base + RSTMGR_REG_WR_ACCESS_OFFSET);
+        writel(0, base + RSTMGR_REG_CHIP_SOFT_RST_OFFSET);
+        /* Wait for reset */
+        while (1);
+}
+static void __init bcm21664_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL,
+                &platform_bus);
+        kona_l2_cache_init();
+}
+static const char * const bcm21664_dt_compat[] = {
+        "brcm,bcm21664",
+        NULL,
+};
+DT_MACHINE_START(BCM21664_DT, "BCM21664 Broadcom Application Processor")
+        .init_machine = bcm21664_init,
+        .restart = bcm21664_restart,
+        .dt_compat = bcm21664_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c
index cb3dc364405c..6be54c10f8cb 100644
--- a/arch/arm/mach-bcm/board_bcm281xx.c
+++ b/arch/arm/mach-bcm/board_bcm281xx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012-2013 Broadcom Corporation
+ * Copyright (C) 2012-2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
@@ -11,64 +11,65 @@
 * GNU General Public License for more details.
 */
-#include <linux/of_platform.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
 #include <linux/clocksource.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/cache-l2x0.h>
-#include "bcm_kona_smc.h"
 #include "kona.h"
-static int __init kona_l2_cache_init(void)
+#define SECWDOG_OFFSET                  0x00000000
+#define SECWDOG_RESERVED_MASK           0xe2000000
+#define SECWDOG_WD_LOAD_FLAG_MASK       0x10000000
+#define SECWDOG_EN_MASK                 0x08000000
+#define SECWDOG_SRSTEN_MASK             0x04000000
+#define SECWDOG_CLKS_SHIFT              20
+#define SECWDOG_COUNT_SHIFT             0
+static void bcm281xx_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (!IS_ENABLED(CONFIG_CACHE_L2X0))
+        uint32_t val;
-                return 0;
+        void __iomem *base;
+        struct device_node *np_wdog;
-        if (bcm_kona_smc_init() < 0) {
+        np_wdog = of_find_compatible_node(NULL, NULL, "brcm,kona-wdt");
-                pr_info("Kona secure API not available. Skipping L2 init\n");
+        if (!np_wdog) {
-                return 0;
+                pr_emerg("Couldn't find brcm,kona-wdt\n");
+                return;
+        }
+        base = of_iomap(np_wdog, 0);
+        if (!base) {
+                pr_emerg("Couldn't map brcm,kona-wdt\n");
+                return;
        }
-        bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
+        /* Enable watchdog with short timeout (244us). */
+        val = readl(base + SECWDOG_OFFSET);
-        /*
+        val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK;
-         * The aux_val and aux_mask have no effect since L2 cache is already
+        val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK |
-         * enabled.  Pass 0s for aux_val and 1s for aux_mask for default value.
+                (0x15 << SECWDOG_CLKS_SHIFT) |
-         */
+                (0x8 << SECWDOG_COUNT_SHIFT);
-        return l2x0_of_init(0, ~0);
+        writel(val, base + SECWDOG_OFFSET);
-}
-static void bcm_board_setup_restart(void)
-{
-        struct device_node *np;
-        np = of_find_compatible_node(NULL, NULL, "brcm,bcm11351");
+        /* Wait for reset */
-        if (np) {
+        while (1);
-                if (of_device_is_available(np))
-                        bcm_kona_setup_restart();
-                of_node_put(np);
-        }
-        /* Restart setup for other boards goes here */
 }
-static void __init board_init(void)
+static void __init bcm281xx_init(void)
 {
        of_platform_populate(NULL, of_default_bus_match_table, NULL,
                &platform_bus);
-        bcm_board_setup_restart();
        kona_l2_cache_init();
 }
-static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, };
+static const char * const bcm281xx_dt_compat[] = {
+        "brcm,bcm11351",        /* Have to use the first number upstreamed */
+        NULL,
+};
-DT_MACHINE_START(BCM11351_DT, "BCM281xx Broadcom Application Processor")
+DT_MACHINE_START(BCM281XX_DT, "BCM281xx Broadcom Application Processor")
-        .init_machine = board_init,
+        .init_machine = bcm281xx_init,
-        .restart = bcm_kona_restart,
+        .restart = bcm281xx_restart,
-        .dt_compat = bcm11351_dt_compat,
+        .dt_compat = bcm281xx_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c
index 70f2f3925f0e..70f2f3925f0e 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm/board_bcm2835.c
diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona.c
index 6939d9017f63..768bc2837bf5 100644
--- a/arch/arm/mach-bcm/kona.c
+++ b/arch/arm/mach-bcm/kona.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Broadcom Corporation
+ * Copyright (C) 2012-2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
@@ -11,55 +11,33 @@
 * GNU General Public License for more details.
 */
-#include <linux/of_address.h>
+#include <linux/of_platform.h>
-#include <asm/io.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "bcm_kona_smc.h"
 #include "kona.h"
-static void __iomem *watchdog_base;
+void __init kona_l2_cache_init(void)
-void bcm_kona_setup_restart(void)
 {
-        struct device_node *np_wdog;
+        int ret;
-        /*
+        if (!IS_ENABLED(CONFIG_CACHE_L2X0))
-         * The assumption is that whoever calls bcm_kona_setup_restart()
-         * also needs a Kona Watchdog Timer entry in Device Tree, i.e. we
-         * report an error if the DT entry is missing.
-         */
-        np_wdog = of_find_compatible_node(NULL, NULL, "brcm,kona-wdt");
-        if (!np_wdog) {
-                pr_err("brcm,kona-wdt not found in DT, reboot disabled\n");
                return;
-        }
-        watchdog_base = of_iomap(np_wdog, 0);
-        WARN(!watchdog_base, "failed to map watchdog base");
-        of_node_put(np_wdog);
-}
-#define SECWDOG_OFFSET                  0x00000000
-#define SECWDOG_RESERVED_MASK           0xE2000000
-#define SECWDOG_WD_LOAD_FLAG_MASK       0x10000000
-#define SECWDOG_EN_MASK                 0x08000000
-#define SECWDOG_SRSTEN_MASK             0x04000000
-#define SECWDOG_CLKS_SHIFT              20
-#define SECWDOG_LOCK_SHIFT              0
-void bcm_kona_restart(enum reboot_mode mode, const char *cmd)
+        ret = bcm_kona_smc_init();
-{
+        if (ret) {
-        uint32_t val;
+                pr_info("Secure API not available (%d). Skipping L2 init.\n",
+                        ret);
-        if (!watchdog_base)
+                return;
-                panic("Watchdog not mapped. Reboot failed.\n");
+        }
-        /* Enable watchdog2 with very short timeout. */
+        bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
-        val = readl(watchdog_base + SECWDOG_OFFSET);
-        val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK;
-        val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK |
-                (0x8 << SECWDOG_CLKS_SHIFT) |
-                (0x8 << SECWDOG_LOCK_SHIFT);
-        writel(val, watchdog_base + SECWDOG_OFFSET);
-        while (1)
+        /*
-                ;
+         * The aux_val and aux_mask have no effect since L2 cache is already
+         * enabled.  Pass 0s for aux_val and 1s for aux_mask for default value.
+         */
+        ret = l2x0_of_init(0, ~0);
+        if (ret)
+                pr_err("Couldn't enable L2 cache: %d\n", ret);
 }
diff --git a/arch/arm/mach-bcm/kona.h b/arch/arm/mach-bcm/kona.h
index 291eca3e06ff..3a7a017c29cd 100644
--- a/arch/arm/mach-bcm/kona.h
+++ b/arch/arm/mach-bcm/kona.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Broadcom Corporation
+ * Copyright (C) 2012-2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
@@ -11,7 +11,4 @@
 * GNU General Public License for more details.
 */
-#include <linux/reboot.h>
+void __init kona_l2_cache_init(void);
-void bcm_kona_setup_restart(void);
-void bcm_kona_restart(enum reboot_mode mode, const char *cmd);
diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig
deleted file mode 100644
index d1f9612f8c15..000000000000
--- a/arch/arm/mach-bcm2835/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-config ARCH_BCM2835
-        bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select ARM_ERRATA_411920
-        select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
-        select CLKSRC_OF
-        select CPU_V6
-        select GENERIC_CLOCKEVENTS
-        select PINCTRL
-        select PINCTRL_BCM2835
-        help
-          This enables support for the Broadcom BCM2835 SoC. This SoC is
-          used in the Raspberry Pi and Roku 2 devices.
diff --git a/arch/arm/mach-bcm2835/Makefile b/arch/arm/mach-bcm2835/Makefile
deleted file mode 100644
index 4c3892fe02c3..000000000000
--- a/arch/arm/mach-bcm2835/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += bcm2835.o
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index 7a02d222c378..b0cb0722acd2 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -1,9 +1,7 @@
 config ARCH_BERLIN
        bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
        select ARM_GIC
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select COMMON_CLK
        select DW_APB_ICTL
        select DW_APB_TIMER_OF
@@ -16,12 +14,10 @@ config MACH_BERLIN_BG2
        select CACHE_L2X0
        select CPU_PJ4B
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
 config MACH_BERLIN_BG2CD
        bool "Marvell Armada 1500-mini (BG2CD)"
        select CACHE_L2X0
-        select CPU_V7
        select HAVE_ARM_TWD if SMP
 endmenu
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index bea6295c8c59..f711498c180c 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -33,20 +33,6 @@ config ARCH_P720T
          Say Y here if you intend to run this kernel on the ARM Prospector
          720T.
-config EP72XX_ROM_BOOT
-        bool "EP721x/EP731x ROM boot"
-        help
-          If you say Y here, your CLPS711x-based kernel will use the bootstrap
-          mode memory map instead of the normal memory map.
-          Processors derived from the Cirrus CLPS711X core support two boot
-          modes.  Normal mode boots from the external memory device at CS0.
-          Bootstrap mode rearranges parts of the memory map, placing an
-          internal 128 byte bootstrap ROM at CS0.  This option performs the
-          address map changes required to support booting in this mode.
-          You almost surely want to say N here.
 endmenu
 endif
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index f8d71a89644a..d62ca16d5394 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -73,7 +73,7 @@
 #define AUTCPU12_SMC_NCE        (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
 #define AUTCPU12_SMC_RDY        CLPS711X_GPIO(1, 2)
 #define AUTCPU12_SMC_ALE        CLPS711X_GPIO(1, 3)
-#define AUTCPU12_SMC_CLE        CLPS711X_GPIO(1, 3)
+#define AUTCPU12_SMC_CLE        CLPS711X_GPIO(1, 4)
 /* LCD contrast digital potentiometer */
 #define AUTCPU12_DPOT_CS        CLPS711X_GPIO(4, 0)
@@ -265,14 +265,12 @@ static void __init autcpu12_init_late(void)
 MACHINE_START(AUTCPU12, "autronix autcpu12")
        /* Maintainer: Thomas Gleixner */
        .atag_offset    = 0x20000,
-        .nr_irqs        = CLPS711X_NR_IRQS,
        .map_io         = clps711x_map_io,
        .init_early     = clps711x_init_early,
        .init_irq       = clps711x_init_irq,
        .init_time      = clps711x_timer_init,
        .init_machine   = autcpu12_init,
        .init_late      = autcpu12_init_late,
-        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index a9e38c6bcfb4..e261a47f2aff 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -139,12 +139,10 @@ static void __init cdb89712_init(void)
 MACHINE_START(CDB89712, "Cirrus-CDB89712")
        /* Maintainer: Ray Lehtiniemi */
        .atag_offset    = 0x100,
-        .nr_irqs        = CLPS711X_NR_IRQS,
        .map_io         = clps711x_map_io,
        .init_early     = clps711x_init_early,
        .init_irq       = clps711x_init_irq,
        .init_time      = clps711x_timer_init,
        .init_machine   = cdb89712_init,
-        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index b4764246d0f8..221b9de32dd6 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -36,12 +36,10 @@ fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
        /* Maintainer: Nobody */
        .atag_offset    = 0x0100,
-        .nr_irqs        = CLPS711X_NR_IRQS,
        .fixup          = fixup_clep7312,
        .map_io         = clps711x_map_io,
        .init_early     = clps711x_init_early,
        .init_irq       = clps711x_init_irq,
        .init_time      = clps711x_timer_init,
-        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index fe6184ead896..077609841f14 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -177,7 +177,6 @@ static void __init edb7211_init_late(void)
 MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
        /* Maintainer: Jon McClintock */
        .atag_offset    = VIDEORAM_SIZE + 0x100,
-        .nr_irqs        = CLPS711X_NR_IRQS,
        .fixup          = fixup_edb7211,
        .reserve        = edb7211_reserve,
        .map_io         = clps711x_map_io,
@@ -186,6 +185,5 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
        .init_time      = clps711x_timer_init,
        .init_machine   = edb7211_init,
        .init_late      = edb7211_init_late,
-        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index dd81b06f68fe..67b733744ed7 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -363,7 +363,6 @@ static void __init p720t_init_late(void)
 MACHINE_START(P720T, "ARM-Prospector720T")
        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
        .atag_offset    = 0x100,
-        .nr_irqs        = CLPS711X_NR_IRQS,
        .fixup          = fixup_p720t,
        .map_io         = clps711x_map_io,
        .init_early     = clps711x_init_early,
@@ -371,6 +370,5 @@ MACHINE_START(P720T, "ARM-Prospector720T")
        .init_time      = clps711x_timer_init,
        .init_machine   = p720t_init,
        .init_late      = p720t_init_late,
-        .handle_irq     = clps711x_handle_irq,
        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index a1935911e4f1..aee81fa46ccf 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -31,14 +31,14 @@
 #include <linux/clk-provider.h>
 #include <linux/sched_clock.h>
-#include <asm/exception.h>
-#include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
 #include <mach/hardware.h>
+#include "common.h"
 static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
                  *clk_tint, *clk_spi;
@@ -59,204 +59,9 @@ void __init clps711x_map_io(void)
        iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
 }
-static void int1_mask(struct irq_data *d)
-{
-        u32 intmr1;
-        intmr1 = clps_readl(INTMR1);
-        intmr1 &= ~(1 << d->irq);
-        clps_writel(intmr1, INTMR1);
-}
-static void int1_eoi(struct irq_data *d)
-{
-        switch (d->irq) {
-        case IRQ_CSINT:  clps_writel(0, COEOI);  break;
-        case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
-        case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
-        case IRQ_RTCMI:  clps_writel(0, RTCEOI); break;
-        case IRQ_TINT:   clps_writel(0, TEOI);   break;
-        case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
-        }
-}
-static void int1_unmask(struct irq_data *d)
-{
-        u32 intmr1;
-        intmr1 = clps_readl(INTMR1);
-        intmr1 |= 1 << d->irq;
-        clps_writel(intmr1, INTMR1);
-}
-static struct irq_chip int1_chip = {
-        .name           = "Interrupt Vector 1",
-        .irq_eoi        = int1_eoi,
-        .irq_mask       = int1_mask,
-        .irq_unmask     = int1_unmask,
-};
-static void int2_mask(struct irq_data *d)
-{
-        u32 intmr2;
-        intmr2 = clps_readl(INTMR2);
-        intmr2 &= ~(1 << (d->irq - 16));
-        clps_writel(intmr2, INTMR2);
-}
-static void int2_eoi(struct irq_data *d)
-{
-        switch (d->irq) {
-        case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
-        }
-}
-static void int2_unmask(struct irq_data *d)
-{
-        u32 intmr2;
-        intmr2 = clps_readl(INTMR2);
-        intmr2 |= 1 << (d->irq - 16);
-        clps_writel(intmr2, INTMR2);
-}
-static struct irq_chip int2_chip = {
-        .name           = "Interrupt Vector 2",
-        .irq_eoi        = int2_eoi,
-        .irq_mask       = int2_mask,
-        .irq_unmask     = int2_unmask,
-};
-static void int3_mask(struct irq_data *d)
-{
-        u32 intmr3;
-        intmr3 = clps_readl(INTMR3);
-        intmr3 &= ~(1 << (d->irq - 32));
-        clps_writel(intmr3, INTMR3);
-}
-static void int3_unmask(struct irq_data *d)
-{
-        u32 intmr3;
-        intmr3 = clps_readl(INTMR3);
-        intmr3 |= 1 << (d->irq - 32);
-        clps_writel(intmr3, INTMR3);
-}
-static struct irq_chip int3_chip = {
-        .name           = "Interrupt Vector 3",
-        .irq_mask       = int3_mask,
-        .irq_unmask     = int3_unmask,
-};
-static struct {
-        int                     nr;
-        struct irq_chip         *chip;
-        irq_flow_handler_t      handle;
-} clps711x_irqdescs[] __initdata = {
-        { IRQ_CSINT,    &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_EINT1,    &int1_chip,     handle_level_irq,       },
-        { IRQ_EINT2,    &int1_chip,     handle_level_irq,       },
-        { IRQ_EINT3,    &int1_chip,     handle_level_irq,       },
-        { IRQ_TC1OI,    &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_TC2OI,    &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_RTCMI,    &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_TINT,     &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_UTXINT1,  &int1_chip,     handle_level_irq,       },
-        { IRQ_URXINT1,  &int1_chip,     handle_level_irq,       },
-        { IRQ_UMSINT,   &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_SSEOTI,   &int1_chip,     handle_level_irq,       },
-        { IRQ_KBDINT,   &int2_chip,     handle_fasteoi_irq,     },
-        { IRQ_SS2RX,    &int2_chip,     handle_level_irq,       },
-        { IRQ_SS2TX,    &int2_chip,     handle_level_irq,       },
-        { IRQ_UTXINT2,  &int2_chip,     handle_level_irq,       },
-        { IRQ_URXINT2,  &int2_chip,     handle_level_irq,       },
-};
 void __init clps711x_init_irq(void)
 {
-        unsigned int i;
+        clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);
-        /* Disable interrupts */
-        clps_writel(0, INTMR1);
-        clps_writel(0, INTMR2);
-        clps_writel(0, INTMR3);
-        /* Clear down any pending interrupts */
-        clps_writel(0, BLEOI);
-        clps_writel(0, MCEOI);
-        clps_writel(0, COEOI);
-        clps_writel(0, TC1EOI);
-        clps_writel(0, TC2EOI);
-        clps_writel(0, RTCEOI);
-        clps_writel(0, TEOI);
-        clps_writel(0, UMSEOI);
-        clps_writel(0, KBDEOI);
-        clps_writel(0, SRXEOF);
-        clps_writel(0xffffffff, DAISR);
-        for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
-                irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
-                                         clps711x_irqdescs[i].chip,
-                                         clps711x_irqdescs[i].handle);
-                set_irq_flags(clps711x_irqdescs[i].nr,
-                              IRQF_VALID | IRQF_PROBE);
-        }
-        if (IS_ENABLED(CONFIG_FIQ)) {
-                init_FIQ(0);
-                irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip,
-                                         handle_bad_irq);
-                set_irq_flags(IRQ_DAIINT,
-                              IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
-        }
-}
-static inline u32 fls16(u32 x)
-{
-        u32 r = 15;
-        if (!(x & 0xff00)) {
-                x <<= 8;
-                r -= 8;
-        }
-        if (!(x & 0xf000)) {
-                x <<= 4;
-                r -= 4;
-        }
-        if (!(x & 0xc000)) {
-                x <<= 2;
-                r -= 2;
-        }
-        if (!(x & 0x8000))
-                r--;
-        return r;
-}
-asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
-{
-        do {
-                u32 irqstat;
-                void __iomem *base = CLPS711X_VIRT_BASE;
-                irqstat = readw_relaxed(base + INTSR1) &
-                          readw_relaxed(base + INTMR1);
-                if (irqstat)
-                        handle_IRQ(fls16(irqstat), regs);
-                irqstat = readw_relaxed(base + INTSR2) &
-                          readw_relaxed(base + INTMR2);
-                if (irqstat) {
-                        handle_IRQ(fls16(irqstat) + 16, regs);
-                        continue;
-                }
-                break;
-        } while (1);
 }
 static u64 notrace clps711x_sched_clock_read(void)
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index 9a6767bfdc47..7489139d5d63 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -6,13 +6,14 @@
 #include <linux/reboot.h>
-#define CLPS711X_NR_IRQS        (33)
 #define CLPS711X_NR_GPIO        (4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
 extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
-extern void clps711x_handle_irq(struct pt_regs *regs);
 extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
 extern void clps711x_init_early(void);
+/* drivers/irqchip/irq-clps711x.c */
+void clps711x_intc_init(phys_addr_t, resource_size_t);
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 0286f4bf9945..eb052a11aa9d 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -40,8 +40,6 @@
 #define MEMCFG1         (0x0180)
 #define MEMCFG2         (0x01c0)
 #define DRFPR           (0x0200)
-#define INTSR1          (0x0240)
-#define INTMR1          (0x0280)
 #define LCDCON          (0x02c0)
 #define TC1D            (0x0300)
 #define TC2D            (0x0340)
@@ -55,28 +53,16 @@
 #define PALLSW          (0x0540)
 #define PALMSW          (0x0580)
 #define STFCLR          (0x05c0)
-#define BLEOI           (0x0600)
-#define MCEOI           (0x0640)
-#define TEOI            (0x0680)
-#define TC1EOI          (0x06c0)
-#define TC2EOI          (0x0700)
-#define RTCEOI          (0x0740)
-#define UMSEOI          (0x0780)
-#define COEOI           (0x07c0)
 #define HALT            (0x0800)
 #define STDBY           (0x0840)
 #define FBADDR          (0x1000)
 #define SYSCON2         (0x1100)
 #define SYSFLG2         (0x1140)
-#define INTSR2          (0x1240)
-#define INTMR2          (0x1280)
 #define UARTDR2         (0x1480)
 #define UBRLCR2         (0x14c0)
 #define SS2DR           (0x1500)
-#define SRXEOF          (0x1600)
 #define SS2POP          (0x16c0)
-#define KBDEOI          (0x1700)
 #define DAIR            (0x2000)
 #define DAIDR0          (0x2040)
@@ -84,8 +70,6 @@
 #define DAIDR2          (0x20c0)
 #define DAISR           (0x2100)
 #define SYSCON3         (0x2200)
-#define INTSR3          (0x2240)
-#define INTMR3          (0x2280)
 #define LEDFLSH         (0x22c0)
 #define SDCONF          (0x2300)
 #define SDRFPR          (0x2340)
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index c5a8ea6839ef..5d6afda1c0e8 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -38,13 +38,6 @@
 #define clps_writel(val,off)    writel(val, CLPS711X_VIRT_BASE + (off))
 #endif
-/*
- * The physical addresses that the external chip select signals map to is
- * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
- * processors.  CONFIG_EP72XX_BOOT_ROM is only available if these
- * processors are in use.
- */
-#ifndef CONFIG_EP72XX_ROM_BOOT
 #define CS0_PHYS_BASE           (0x00000000)
 #define CS1_PHYS_BASE           (0x10000000)
 #define CS2_PHYS_BASE           (0x20000000)
@@ -53,16 +46,6 @@
 #define CS5_PHYS_BASE           (0x50000000)
 #define CS6_PHYS_BASE           (0x60000000)
 #define CS7_PHYS_BASE           (0x70000000)
-#else
-#define CS0_PHYS_BASE           (0x70000000)
-#define CS1_PHYS_BASE           (0x60000000)
-#define CS2_PHYS_BASE           (0x50000000)
-#define CS3_PHYS_BASE           (0x40000000)
-#define CS4_PHYS_BASE           (0x30000000)
-#define CS5_PHYS_BASE           (0x20000000)
-#define CS6_PHYS_BASE           (0x10000000)
-#define CS7_PHYS_BASE           (0x00000000)
-#endif
 #define CLPS711X_SRAM_BASE      CS6_PHYS_BASE
 #define CLPS711X_SRAM_SIZE      (48 * 1024)
diff --git a/arch/arm/mach-clps711x/include/mach/timex.h b/arch/arm/mach-clps711x/include/mach/timex.h
deleted file mode 100644
index de6fd192d1c3..000000000000
--- a/arch/arm/mach-clps711x/include/mach/timex.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* Bogus value */
-#define CLOCK_TICK_RATE 512000
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index dbf0df8bb0ac..dce8decd5d46 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -1,9 +1,6 @@
 config ARCH_CNS3XXX
        bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
        select ARM_GIC
-        select CPU_V6K
-        select GENERIC_CLOCKEVENTS
-        select MIGHT_HAVE_CACHE_L2X0
        select MIGHT_HAVE_PCI
        select PCI_DOMAINS if PCI
        help
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index ce096d678aa4..d863d8729edc 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -246,7 +246,6 @@ static void __init cns3420_map_io(void)
 MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
        .atag_offset    = 0x100,
-        .nr_irqs        = NR_IRQS_CNS3XXX,
        .map_io         = cns3420_map_io,
        .init_irq       = cns3xxx_init_irq,
        .init_time      = cns3xxx_timer_init,
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index e38b279f402c..2ae28a69e3e5 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -47,6 +47,38 @@ static struct map_desc cns3xxx_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(CNS3XXX_PM_BASE),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
+#ifdef CONFIG_PCI
+        }, {
+                .virtual        = CNS3XXX_PCIE0_HOST_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
+                .length         = SZ_64K, /* really 4 KiB at offset 32 KiB */
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_PCIE1_HOST_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
+                .length         = SZ_64K, /* really 4 KiB at offset 32 KiB */
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE,
+#endif
        },
 };
@@ -155,7 +187,7 @@ static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
 static struct irqaction cns3xxx_timer_irq = {
        .name           = "timer",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = cns3xxx_timer_interrupt,
 };
@@ -368,7 +400,6 @@ static const char *cns3xxx_dt_compat[] __initdata = {
 DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
        .dt_compat      = cns3xxx_dt_compat,
-        .nr_irqs        = NR_IRQS_CNS3XXX,
        .map_io         = cns3xxx_map_io,
        .init_irq       = cns3xxx_init_irq,
        .init_time      = cns3xxx_timer_init,
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index c7b204bff386..413134c54452 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -23,15 +23,10 @@
 #include "cns3xxx.h"
 #include "core.h"
-enum cns3xxx_access_type {
-        CNS3XXX_HOST_TYPE = 0,
-        CNS3XXX_CFG0_TYPE,
-        CNS3XXX_CFG1_TYPE,
-        CNS3XXX_NUM_ACCESS_TYPES,
-};
 struct cns3xxx_pcie {
-        struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
+        void __iomem *host_regs; /* PCI config registers for host bridge */
+        void __iomem *cfg0_regs; /* PCI Type 0 config registers */
+        void __iomem *cfg1_regs; /* PCI Type 1 config registers */
        unsigned int irqs[2];
        struct resource res_io;
        struct resource res_mem;
@@ -66,7 +61,6 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
        int busno = bus->number;
        int slot = PCI_SLOT(devfn);
        int offset;
-        enum cns3xxx_access_type type;
        void __iomem *base;
        /* If there is no link, just show the CNS PCI bridge. */
@@ -78,17 +72,21 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
         * we still want to access it. For this to work, we must place
         * the first device on the same bus as the CNS PCI bridge.
         */
-        if (busno == 0) {
+        if (busno == 0) { /* directly connected PCIe bus */
-                if (slot > 1)
+                switch (slot) {
-                        return NULL;
+                case 0: /* host bridge device, function 0 only */
-                type = slot;
+                        base = cnspci->host_regs;
-        } else {
+                        break;
-                type = CNS3XXX_CFG1_TYPE;
+                case 1: /* directly connected device */
-        }
+                        base = cnspci->cfg0_regs;
+                        break;
+                default:
+                        return NULL; /* no such device */
+                }
+        } else /* remote PCI bus */
+                base = cnspci->cfg1_regs;
-        base = (void __iomem *)cnspci->cfg_bases[type].virtual;
        offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
        return base + offset;
 }
@@ -180,36 +178,19 @@ static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 static struct cns3xxx_pcie cns3xxx_pcie[] = {
        [0] = {
-                .cfg_bases = {
+                .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
-                        [CNS3XXX_HOST_TYPE] = {
+                .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
-                                .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
+                .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
-                                .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
-                                .length = SZ_16M,
-                                .type = MT_DEVICE,
-                        },
-                        [CNS3XXX_CFG0_TYPE] = {
-                                .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
-                                .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
-                                .length = SZ_16M,
-                                .type = MT_DEVICE,
-                        },
-                        [CNS3XXX_CFG1_TYPE] = {
-                                .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
-                                .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
-                                .length = SZ_16M,
-                                .type = MT_DEVICE,
-                        },
-                },
                .res_io = {
                        .name = "PCIe0 I/O space",
                        .start = CNS3XXX_PCIE0_IO_BASE,
-                        .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
+                        .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
                        .flags = IORESOURCE_IO,
                },
                .res_mem = {
                        .name = "PCIe0 non-prefetchable",
                        .start = CNS3XXX_PCIE0_MEM_BASE,
-                        .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
+                        .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
                        .flags = IORESOURCE_MEM,
                },
                .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
@@ -222,36 +203,19 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = {
                },
        },
        [1] = {
-                .cfg_bases = {
+                .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
-                        [CNS3XXX_HOST_TYPE] = {
+                .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
-                                .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
+                .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
-                                .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
-                                .length = SZ_16M,
-                                .type = MT_DEVICE,
-                        },
-                        [CNS3XXX_CFG0_TYPE] = {
-                                .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
-                                .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
-                                .length = SZ_16M,
-                                .type = MT_DEVICE,
-                        },
-                        [CNS3XXX_CFG1_TYPE] = {
-                                .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
-                                .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
-                                .length = SZ_16M,
-                                .type = MT_DEVICE,
-                        },
-                },
                .res_io = {
                        .name = "PCIe1 I/O space",
                        .start = CNS3XXX_PCIE1_IO_BASE,
-                        .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
+                        .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
                        .flags = IORESOURCE_IO,
                },
                .res_mem = {
                        .name = "PCIe1 non-prefetchable",
                        .start = CNS3XXX_PCIE1_MEM_BASE,
-                        .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
+                        .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
                        .flags = IORESOURCE_MEM,
                },
                .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
@@ -307,18 +271,15 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
                .ops = &cns3xxx_pcie_ops,
                .sysdata = &sd,
        };
-        u32 io_base = cnspci->res_io.start >> 16;
+        u16 mem_base  = cnspci->res_mem.start >> 16;
-        u32 mem_base = cnspci->res_mem.start >> 16;
+        u16 mem_limit = cnspci->res_mem.end   >> 16;
-        u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
+        u16 io_base   = cnspci->res_io.start  >> 16;
-        u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
+        u16 io_limit  = cnspci->res_io.end    >> 16;
        u32 devfn = 0;
        u8 tmp8;
        u16 pos;
        u16 dc;
-        host_base = (__pfn_to_phys(host_base) - 1) >> 16;
-        cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
        pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
        pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
        pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
@@ -328,9 +289,9 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
        pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
        pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
-        pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
+        pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, mem_limit);
        pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
-        pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
+        pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, io_limit);
        if (!cnspci->linked)
                return;
@@ -368,8 +329,6 @@ static int __init cns3xxx_pcie_init(void)
                        "imprecise external abort");
        for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
-                iotable_init(cns3xxx_pcie[i].cfg_bases,
-                             ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
                cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
                cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
                cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a075b3e0c5c7..db18ef866593 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -51,11 +51,6 @@ config ARCH_DAVINCI_DM365
        select AINTC
        select ARCH_DAVINCI_DMx
-config ARCH_DAVINCI_TNETV107X
-        bool "TNETV107X based system"
-        select CPU_V6
-        select CP_INTC
 comment "DaVinci Board Type"
 config MACH_DA8XX_DT
@@ -214,18 +209,6 @@ config DA850_WL12XX
          Say Y if you want to use a wl1271 expansion card connected to the
          AM18x EVM.
-config GPIO_PCA953X
-        default MACH_DAVINCI_DA850_EVM
-config KEYBOARD_GPIO_POLLED
-        default MACH_DAVINCI_DA850_EVM
-config MACH_TNETV107X
-        bool "TI TNETV107X Reference Platform"
-        default ARCH_DAVINCI_TNETV107X
-        depends on ARCH_DAVINCI_TNETV107X
-        help
-          Say Y here to select the TI TNETV107X Evaluation Module.
 config MACH_MITYOMAPL138
        bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 63997a1128e6..2204239ed243 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DM365)        += dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
-obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
 obj-$(CONFIG_AINTC)                     += irq.o
 obj-$(CONFIG_CP_INTC)                   += cp_intc.o
@@ -32,7 +31,6 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)	+= board-dm646x-evm.o cdce949.o
 obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)    += board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)    += board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)    += board-da850-evm.o
-obj-$(CONFIG_MACH_TNETV107X)            += board-tnetv107x-evm.o
 obj-$(CONFIG_MACH_MITYOMAPL138)         += board-mityomapl138.o
 obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)   += board-omapl138-hawk.o
diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot
index 04a6c4e67b14..4b81601754a2 100644
--- a/arch/arm/mach-davinci/Makefile.boot
+++ b/arch/arm/mach-davinci/Makefile.boot
@@ -1,13 +1,7 @@
-ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y)
+zreladdr-$(CONFIG_ARCH_DAVINCI_DA8XX)           += 0xc0008000
-ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
+params_phys-$(CONFIG_ARCH_DAVINCI_DA8XX)        := 0xc0000100
-$(error Cannot enable DaVinci and DA8XX platforms concurrently)
+initrd_phys-$(CONFIG_ARCH_DAVINCI_DA8XX)        := 0xc0800000
-else
-   zreladdr-y   += 0xc0008000
+zreladdr-$(CONFIG_ARCH_DAVINCI_DMx)             += 0x80008000
-params_phys-y   := 0xc0000100
+params_phys-$(CONFIG_ARCH_DAVINCI_DMx)          := 0x80000100
-initrd_phys-y   := 0xc0800000
+initrd_phys-$(CONFIG_ARCH_DAVINCI_DMx)          := 0x80800000
-endif
-else
-   zreladdr-y   += 0x80008000
-params_phys-y   := 0x80000100
-initrd_phys-y   := 0x80800000
-endif
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index f091a9010c2f..ff8b7e76b6e9 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -16,6 +16,7 @@
 #include <linux/time.h>
 #include <linux/platform_data/mtd-davinci-aemif.h>
+#include <linux/platform_data/mtd-davinci.h>
 /* Timing value configuration */
@@ -43,6 +44,17 @@
                                WSTROBE(WSTROBE_MAX) | \
                                WSETUP(WSETUP_MAX))
+static inline unsigned int davinci_aemif_readl(void __iomem *base, int offset)
+{
+        return readl_relaxed(base + offset);
+}
+static inline void davinci_aemif_writel(void __iomem *base,
+                                        int offset, unsigned long value)
+{
+        writel_relaxed(value, base + offset);
+}
 /*
 * aemif_calc_rate - calculate timing data.
 * @wanted: The cycle time needed in nanoseconds.
@@ -76,6 +88,7 @@ static int aemif_calc_rate(int wanted, unsigned long clk, int max)
 * @t: timing values to be progammed
 * @base: The virtual base address of the AEMIF interface
 * @cs: chip-select to program the timing values for
+ * @clkrate: the AEMIF clkrate
 *
 * This function programs the given timing values (in real clock) into the
 * AEMIF registers taking the AEMIF clock into account.
@@ -86,24 +99,17 @@ static int aemif_calc_rate(int wanted, unsigned long clk, int max)
 *
 * Returns 0 on success, else negative errno.
 */
-int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
+static int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
-                                        void __iomem *base, unsigned cs)
+                                        void __iomem *base, unsigned cs,
+                                        unsigned long clkrate)
 {
        unsigned set, val;
        int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
        unsigned offset = A1CR_OFFSET + cs * 4;
-        struct clk *aemif_clk;
-        unsigned long clkrate;
        if (!t)
                return 0;       /* Nothing to do */
-        aemif_clk = clk_get(NULL, "aemif");
-        if (IS_ERR(aemif_clk))
-                return PTR_ERR(aemif_clk);
-        clkrate = clk_get_rate(aemif_clk);
        clkrate /= 1000;        /* turn clock into kHz for ease of use */
        ta      = aemif_calc_rate(t->ta, clkrate, TA_MAX);
@@ -130,4 +136,83 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
        return 0;
 }
-EXPORT_SYMBOL(davinci_aemif_setup_timing);
+/**
+ * davinci_aemif_setup - setup AEMIF interface by davinci_nand_pdata
+ * @pdev - link to platform device to setup settings for
+ *
+ * This function does not use any locking while programming the AEMIF
+ * because it is expected that there is only one user of a given
+ * chip-select.
+ *
+ * Returns 0 on success, else negative errno.
+ */
+int davinci_aemif_setup(struct platform_device *pdev)
+{
+        struct davinci_nand_pdata *pdata = dev_get_platdata(&pdev->dev);
+        uint32_t val;
+        unsigned long clkrate;
+        struct resource *res;
+        void __iomem *base;
+        struct clk *clk;
+        int ret = 0;
+        clk = clk_get(&pdev->dev, "aemif");
+        if (IS_ERR(clk)) {
+                ret = PTR_ERR(clk);
+                dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
+                return ret;
+        }
+        ret = clk_prepare_enable(clk);
+        if (ret < 0) {
+                dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
+                        ret);
+                goto err_put;
+        }
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (!res) {
+                dev_err(&pdev->dev, "cannot get IORESOURCE_MEM\n");
+                ret = -ENOMEM;
+                goto err;
+        }
+        base = ioremap(res->start, resource_size(res));
+        if (!base) {
+                dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res);
+                ret = -ENOMEM;
+                goto err;
+        }
+        /*
+         * Setup Async configuration register in case we did not boot
+         * from NAND and so bootloader did not bother to set it up.
+         */
+        val = davinci_aemif_readl(base, A1CR_OFFSET + pdev->id * 4);
+        /*
+         * Extended Wait is not valid and Select Strobe mode is not
+         * used
+         */
+        val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
+        if (pdata->options & NAND_BUSWIDTH_16)
+                val |= 0x1;
+        davinci_aemif_writel(base, A1CR_OFFSET + pdev->id * 4, val);
+        clkrate = clk_get_rate(clk);
+        if (pdata->timing)
+                ret = davinci_aemif_setup_timing(pdata->timing, base, pdev->id,
+                                                 clkrate);
+        if (ret < 0)
+                dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
+        iounmap(base);
+err:
+        clk_disable_unprepare(clk);
+err_put:
+        clk_put(clk);
+        return ret;
+}
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index d1f45af7a530..5623131c4f0b 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -419,6 +419,9 @@ static inline void da830_evm_init_nand(int mux_mode)
        if (ret)
                pr_warning("da830_evm_init: NAND device not registered.\n");
+        if (davinci_aemif_setup(&da830_evm_nand_device))
+                pr_warn("%s: Cannot configure AEMIF.\n", __func__);
        gpio_direction_output(mux_mode, 1);
 }
 #else
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index e0af0eccde8f..234c5bb091f5 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -358,6 +358,9 @@ static inline void da850_evm_setup_nor_nand(void)
                platform_add_devices(da850_evm_devices,
                                        ARRAY_SIZE(da850_evm_devices));
+                if (davinci_aemif_setup(&da850_evm_nandflash_device))
+                        pr_warn("%s: Cannot configure AEMIF.\n", __func__);
        }
 }
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 987605b78556..e583e58b5e1e 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -778,6 +778,11 @@ static __init void davinci_evm_init(void)
                /* only one device will be jumpered and detected */
                if (HAS_NAND) {
                        platform_device_register(&davinci_evm_nandflash_device);
+                        if (davinci_aemif_setup(&davinci_evm_nandflash_device))
+                                pr_warn("%s: Cannot configure AEMIF.\n",
+                                        __func__);
                        evm_leds[7].default_trigger = "nand-disk";
                        if (HAS_NOR)
                                pr_warning("WARNING: both NAND and NOR flash "
@@ -799,11 +804,12 @@ static __init void davinci_evm_init(void)
        /* irlml6401 switches over 1A, in under 8 msec */
        davinci_setup_usb(1000, 8);
-        soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
+        if (IS_BUILTIN(CONFIG_PHYLIB)) {
-        /* Register the fixup for PHY on DaVinci */
+                soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
-        phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
+                /* Register the fixup for PHY on DaVinci */
-                                        davinci_phy_fixup);
+                phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
+                                                davinci_phy_fixup);
+        }
 }
 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 13d0801fd6b1..ae129bc49273 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -805,6 +805,9 @@ static __init void evm_init(void)
        platform_device_register(&davinci_nand_device);
+        if (davinci_aemif_setup(&davinci_nand_device))
+                pr_warn("%s: Cannot configure AEMIF.\n", __func__);
        dm646x_init_edma(dm646x_edma_rsv);
        if (HAS_ATA)
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 7aa105b1fd0f..96fc00a167f5 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -27,6 +27,7 @@
 #include <mach/cp_intc.h>
 #include <mach/da8xx.h>
 #include <linux/platform_data/mtd-davinci.h>
+#include <linux/platform_data/mtd-davinci-aemif.h>
 #include <mach/mux.h>
 #include <linux/platform_data/spi-davinci.h>
@@ -432,6 +433,9 @@ static void __init mityomapl138_setup_nand(void)
 {
        platform_add_devices(mityomapl138_devices,
                                 ARRAY_SIZE(mityomapl138_devices));
+        if (davinci_aemif_setup(&mityomapl138_nandflash_device))
+                pr_warn("%s: Cannot configure AEMIF.\n", __func__);
 }
 static const short mityomap_mii_pins[] = {
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
deleted file mode 100644
index 78ea395d2aca..000000000000
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Texas Instruments TNETV107X EVM Board Support
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/ratelimit.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/input.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/platform_data/edma.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/irqs.h>
-#include <mach/mux.h>
-#include <mach/cp_intc.h>
-#include <mach/tnetv107x.h>
-#define EVM_MMC_WP_GPIO         21
-#define EVM_MMC_CD_GPIO         24
-#define EVM_SPI_CS_GPIO         54
-static int initialize_gpio(int gpio, char *desc)
-{
-        int ret;
-        ret = gpio_request(gpio, desc);
-        if (ret < 0) {
-                pr_err_ratelimited("cannot open %s gpio\n", desc);
-                return -ENOSYS;
-        }
-        gpio_direction_input(gpio);
-        return gpio;
-}
-static int mmc_get_cd(int index)
-{
-        static int gpio;
-        if (!gpio)
-                gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
-        if (gpio < 0)
-                return gpio;
-        return gpio_get_value(gpio) ? 0 : 1;
-}
-static int mmc_get_ro(int index)
-{
-        static int gpio;
-        if (!gpio)
-                gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
-        if (gpio < 0)
-                return gpio;
-        return gpio_get_value(gpio) ? 1 : 0;
-}
-static struct davinci_mmc_config mmc_config = {
-        .get_cd         = mmc_get_cd,
-        .get_ro         = mmc_get_ro,
-        .wires          = 4,
-        .max_freq       = 50000000,
-        .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-static const short sdio1_pins[] __initconst = {
-        TNETV107X_SDIO1_CLK_1,          TNETV107X_SDIO1_CMD_1,
-        TNETV107X_SDIO1_DATA0_1,        TNETV107X_SDIO1_DATA1_1,
-        TNETV107X_SDIO1_DATA2_1,        TNETV107X_SDIO1_DATA3_1,
-        TNETV107X_GPIO21,               TNETV107X_GPIO24,
-        -1
-};
-static const short uart1_pins[] __initconst = {
-        TNETV107X_UART1_RD,             TNETV107X_UART1_TD,
-        -1
-};
-static const short ssp_pins[] __initconst = {
-        TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
-        TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
-        TNETV107X_SSP1_3, -1
-};
-static struct mtd_partition nand_partitions[] = {
-        /* bootloader (U-Boot, etc) in first 12 sectors */
-        {
-                .name           = "bootloader",
-                .offset         = 0,
-                .size           = (12*SZ_128K),
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        /* bootloader params in the next sector */
-        {
-                .name           = "params",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = SZ_128K,
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        /* kernel */
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = SZ_4M,
-                .mask_flags     = 0,
-        },
-        /* file system */
-        {
-                .name           = "filesystem",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = MTDPART_SIZ_FULL,
-                .mask_flags     = 0,
-        }
-};
-static struct davinci_nand_pdata nand_config = {
-        .mask_cle       = 0x4000,
-        .mask_ale       = 0x2000,
-        .parts          = nand_partitions,
-        .nr_parts       = ARRAY_SIZE(nand_partitions),
-        .ecc_mode       = NAND_ECC_HW,
-        .bbt_options    = NAND_BBT_USE_FLASH,
-        .ecc_bits       = 1,
-};
-static struct davinci_uart_config serial_config __initconst = {
-        .enabled_uarts  = BIT(1),
-};
-static const uint32_t keymap[] = {
-        KEY(0, 0, KEY_NUMERIC_1),
-        KEY(0, 1, KEY_NUMERIC_2),
-        KEY(0, 2, KEY_NUMERIC_3),
-        KEY(0, 3, KEY_FN_F1),
-        KEY(0, 4, KEY_MENU),
-        KEY(1, 0, KEY_NUMERIC_4),
-        KEY(1, 1, KEY_NUMERIC_5),
-        KEY(1, 2, KEY_NUMERIC_6),
-        KEY(1, 3, KEY_UP),
-        KEY(1, 4, KEY_FN_F2),
-        KEY(2, 0, KEY_NUMERIC_7),
-        KEY(2, 1, KEY_NUMERIC_8),
-        KEY(2, 2, KEY_NUMERIC_9),
-        KEY(2, 3, KEY_LEFT),
-        KEY(2, 4, KEY_ENTER),
-        KEY(3, 0, KEY_NUMERIC_STAR),
-        KEY(3, 1, KEY_NUMERIC_0),
-        KEY(3, 2, KEY_NUMERIC_POUND),
-        KEY(3, 3, KEY_DOWN),
-        KEY(3, 4, KEY_RIGHT),
-        KEY(4, 0, KEY_FN_F3),
-        KEY(4, 1, KEY_FN_F4),
-        KEY(4, 2, KEY_MUTE),
-        KEY(4, 3, KEY_HOME),
-        KEY(4, 4, KEY_BACK),
-        KEY(5, 0, KEY_VOLUMEDOWN),
-        KEY(5, 1, KEY_VOLUMEUP),
-        KEY(5, 2, KEY_F1),
-        KEY(5, 3, KEY_F2),
-        KEY(5, 4, KEY_F3),
-};
-static const struct matrix_keymap_data keymap_data = {
-        .keymap         = keymap,
-        .keymap_size    = ARRAY_SIZE(keymap),
-};
-static struct matrix_keypad_platform_data keypad_config = {
-        .keymap_data    = &keymap_data,
-        .num_row_gpios  = 6,
-        .num_col_gpios  = 5,
-        .debounce_ms    = 0, /* minimum */
-        .active_low     = 0, /* pull up realization */
-        .no_autorepeat  = 0,
-};
-static void spi_select_device(int cs)
-{
-        static int gpio;
-        if (!gpio) {
-                int ret;
-                ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
-                if (ret < 0) {
-                        pr_err("cannot open spi chipsel gpio\n");
-                        gpio = -ENOSYS;
-                        return;
-                } else {
-                        gpio = EVM_SPI_CS_GPIO;
-                        gpio_direction_output(gpio, 0);
-                }
-        }
-        if (gpio < 0)
-                return;
-        return gpio_set_value(gpio, cs ? 1 : 0);
-}
-static struct ti_ssp_spi_data spi_master_data = {
-        .num_cs = 2,
-        .select = spi_select_device,
-        .iosel  = SSP_PIN_SEL(0, SSP_CLOCK)     | SSP_PIN_SEL(1, SSP_DATA) |
-                  SSP_PIN_SEL(2, SSP_CHIPSEL)   | SSP_PIN_SEL(3, SSP_IN)   |
-                  SSP_INPUT_SEL(3),
-};
-static struct ti_ssp_data ssp_config = {
-        .out_clock      = 250 * 1000,
-        .dev_data       = {
-                [1] = {
-                        .dev_name = "ti-ssp-spi",
-                        .pdata = &spi_master_data,
-                        .pdata_size = sizeof(spi_master_data),
-                },
-        },
-};
-static struct tnetv107x_device_info evm_device_info __initconst = {
-        .serial_config          = &serial_config,
-        .mmc_config[1]          = &mmc_config,  /* controller 1 */
-        .nand_config[0]         = &nand_config, /* chip select 0 */
-        .keypad_config          = &keypad_config,
-        .ssp_config             = &ssp_config,
-};
-static struct spi_board_info spi_info[] __initconst = {
-};
-static __init void tnetv107x_evm_board_init(void)
-{
-        davinci_cfg_reg_list(sdio1_pins);
-        davinci_cfg_reg_list(uart1_pins);
-        davinci_cfg_reg_list(ssp_pins);
-        tnetv107x_devices_init(&evm_device_info);
-        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
-}
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init tnetv107x_evm_console_init(void)
-{
-        return add_preferred_console("ttyS", 0, "115200");
-}
-console_initcall(tnetv107x_evm_console_init);
-#endif
-MACHINE_START(TNETV107X, "TNETV107X EVM")
-        .atag_offset    = 0x100,
-        .map_io         = tnetv107x_init,
-        .init_irq       = cp_intc_init,
-        .init_time      = davinci_timer_init,
-        .init_machine   = tnetv107x_evm_board_init,
-        .init_late      = davinci_init_late,
-        .dma_zone_size  = SZ_128M,
-        .restart        = tnetv107x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 2eebc4338802..4ffc37accce0 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -79,6 +79,8 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata);
 #define DM646X_ASYNC_EMIF_CONTROL_BASE  0x20008000
 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
+int davinci_init_wdt(void);
 /* DM355 function declarations */
 void dm355_init(void);
 void dm355_init_spi0(unsigned chipselect_mask,
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
deleted file mode 100644
index 01d8686e553c..000000000000
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/*
- * Texas Instruments TNETV107X SoC devices
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/slab.h>
-#include <linux/platform_data/edma.h>
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/tnetv107x.h>
-#include "clock.h"
-/* Base addresses for on-chip devices */
-#define TNETV107X_TPCC_BASE                     0x01c00000
-#define TNETV107X_TPTC0_BASE                    0x01c10000
-#define TNETV107X_TPTC1_BASE                    0x01c10400
-#define TNETV107X_WDOG_BASE                     0x08086700
-#define TNETV107X_TSC_BASE                      0x08088500
-#define TNETV107X_SDIO0_BASE                    0x08088700
-#define TNETV107X_SDIO1_BASE                    0x08088800
-#define TNETV107X_KEYPAD_BASE                   0x08088a00
-#define TNETV107X_SSP_BASE                      0x08088c00
-#define TNETV107X_ASYNC_EMIF_CNTRL_BASE         0x08200000
-#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE      0x30000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE      0x40000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE      0x44000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE      0x48000000
-/* TNETV107X specific EDMA3 information */
-#define EDMA_TNETV107X_NUM_DMACH        64
-#define EDMA_TNETV107X_NUM_TCC          64
-#define EDMA_TNETV107X_NUM_PARAMENTRY   128
-#define EDMA_TNETV107X_NUM_EVQUE        2
-#define EDMA_TNETV107X_NUM_TC           2
-#define EDMA_TNETV107X_CHMAP_EXIST      0
-#define EDMA_TNETV107X_NUM_REGIONS      4
-#define TNETV107X_DMACH2EVENT_MAP0      0x3C0CE000u
-#define TNETV107X_DMACH2EVENT_MAP1      0x000FFFFFu
-#define TNETV107X_DMACH_SDIO0_RX                26
-#define TNETV107X_DMACH_SDIO0_TX                27
-#define TNETV107X_DMACH_SDIO1_RX                28
-#define TNETV107X_DMACH_SDIO1_TX                29
-static s8 edma_tc_mapping[][2] = {
-        /* event queue no       TC no   */
-        {        0,              0      },
-        {        1,              1      },
-        {       -1,             -1      }
-};
-static s8 edma_priority_mapping[][2] = {
-        /* event queue no       Prio    */
-        {        0,              3      },
-        {        1,              7      },
-        {       -1,             -1      }
-};
-static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = EDMA_TNETV107X_NUM_DMACH,
-        .n_region               = EDMA_TNETV107X_NUM_REGIONS,
-        .n_slot                 = EDMA_TNETV107X_NUM_PARAMENTRY,
-        .n_tc                   = EDMA_TNETV107X_NUM_TC,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = edma_tc_mapping,
-        .queue_priority_mapping = edma_priority_mapping,
-        .default_queue          = EVENTQ_1,
-};
-static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
-        &edma_cc0_info,
-};
-static struct resource edma_resources[] = {
-        {
-                .name   = "edma_cc0",
-                .start  = TNETV107X_TPCC_BASE,
-                .end    = TNETV107X_TPCC_BASE + SZ_32K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "edma_tc0",
-                .start  = TNETV107X_TPTC0_BASE,
-                .end    = TNETV107X_TPTC0_BASE + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "edma_tc1",
-                .start  = TNETV107X_TPTC1_BASE,
-                .end    = TNETV107X_TPTC1_BASE + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "edma0",
-                .start  = IRQ_TNETV107X_TPCC,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .name   = "edma0_err",
-                .start  = IRQ_TNETV107X_TPCC_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device edma_device = {
-        .name           = "edma",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(edma_resources),
-        .resource       = edma_resources,
-        .dev.platform_data = tnetv107x_edma_info,
-};
-static struct plat_serial8250_port serial0_platform_data[] = {
-        {
-                .mapbase        = TNETV107X_UART0_BASE,
-                .irq            = IRQ_TNETV107X_UART0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
-                                        UPF_FIXED_TYPE | UPF_IOREMAP,
-                .type           = PORT_AR7,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-        },
-        {
-                .flags  = 0,
-        }
-};
-static struct plat_serial8250_port serial1_platform_data[] = {
-        {
-                .mapbase        = TNETV107X_UART1_BASE,
-                .irq            = IRQ_TNETV107X_UART1,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
-                                        UPF_FIXED_TYPE | UPF_IOREMAP,
-                .type           = PORT_AR7,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-        },
-        {
-                .flags  = 0,
-        }
-};
-static struct plat_serial8250_port serial2_platform_data[] = {
-        {
-                .mapbase        = TNETV107X_UART2_BASE,
-                .irq            = IRQ_TNETV107X_UART2,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
-                                        UPF_FIXED_TYPE | UPF_IOREMAP,
-                .type           = PORT_AR7,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-        },
-        {
-                .flags  = 0,
-        }
-};
-struct platform_device tnetv107x_serial_device[] = {
-        {
-                .name                   = "serial8250",
-                .id                     = PLAT8250_DEV_PLATFORM,
-                .dev.platform_data      = serial0_platform_data,
-        },
-        {
-                .name                   = "serial8250",
-                .id                     = PLAT8250_DEV_PLATFORM1,
-                .dev.platform_data      = serial1_platform_data,
-        },
-        {
-                .name                   = "serial8250",
-                .id                     = PLAT8250_DEV_PLATFORM2,
-                .dev.platform_data      = serial2_platform_data,
-        },
-        {
-        }
-};
-static struct resource mmc0_resources[] = {
-        { /* Memory mapped registers */
-                .start  = TNETV107X_SDIO0_BASE,
-                .end    = TNETV107X_SDIO0_BASE + 0x0ff,
-                .flags  = IORESOURCE_MEM
-        },
-        { /* MMC interrupt */
-                .start  = IRQ_TNETV107X_MMC0,
-                .flags  = IORESOURCE_IRQ
-        },
-        { /* SDIO interrupt */
-                .start  = IRQ_TNETV107X_SDIO0,
-                .flags  = IORESOURCE_IRQ
-        },
-        { /* DMA RX */
-                .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
-                .flags  = IORESOURCE_DMA
-        },
-        { /* DMA TX */
-                .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
-                .flags  = IORESOURCE_DMA
-        },
-};
-static struct resource mmc1_resources[] = {
-        { /* Memory mapped registers */
-                .start  = TNETV107X_SDIO1_BASE,
-                .end    = TNETV107X_SDIO1_BASE + 0x0ff,
-                .flags  = IORESOURCE_MEM
-        },
-        { /* MMC interrupt */
-                .start  = IRQ_TNETV107X_MMC1,
-                .flags  = IORESOURCE_IRQ
-        },
-        { /* SDIO interrupt */
-                .start  = IRQ_TNETV107X_SDIO1,
-                .flags  = IORESOURCE_IRQ
-        },
-        { /* DMA RX */
-                .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
-                .flags  = IORESOURCE_DMA
-        },
-        { /* DMA TX */
-                .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
-                .flags  = IORESOURCE_DMA
-        },
-};
-static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
-static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
-static struct platform_device mmc_devices[2] = {
-        {
-                .name           = "dm6441-mmc",
-                .id             = 0,
-                .dev            = {
-                        .dma_mask               = &mmc0_dma_mask,
-                        .coherent_dma_mask      = DMA_BIT_MASK(32),
-                },
-                .num_resources  = ARRAY_SIZE(mmc0_resources),
-                .resource       = mmc0_resources
-        },
-        {
-                .name           = "dm6441-mmc",
-                .id             = 1,
-                .dev            = {
-                        .dma_mask               = &mmc1_dma_mask,
-                        .coherent_dma_mask      = DMA_BIT_MASK(32),
-                },
-                .num_resources  = ARRAY_SIZE(mmc1_resources),
-                .resource       = mmc1_resources
-        },
-};
-static const u32 emif_windows[] = {
-        TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
-        TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
-};
-static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
-static struct resource wdt_resources[] = {
-        {
-                .start  = TNETV107X_WDOG_BASE,
-                .end    = TNETV107X_WDOG_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-struct platform_device tnetv107x_wdt_device = {
-        .name           = "tnetv107x_wdt",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-        .resource       = wdt_resources,
-};
-static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
-{
-        struct resource res[2];
-        struct platform_device *pdev;
-        u32     range;
-        int     ret;
-        /* Figure out the resource range from the ale/cle masks */
-        range = max(data->mask_cle, data->mask_ale);
-        range = PAGE_ALIGN(range + 4) - 1;
-        if (range >= emif_window_sizes[chipsel])
-                return -EINVAL;
-        pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
-        if (!pdev)
-                return -ENOMEM;
-        pdev->name              = "davinci_nand";
-        pdev->id                = chipsel;
-        pdev->dev.platform_data = data;
-        memset(res, 0, sizeof(res));
-        res[0].start    = emif_windows[chipsel];
-        res[0].end      = res[0].start + range;
-        res[0].flags    = IORESOURCE_MEM;
-        res[1].start    = TNETV107X_ASYNC_EMIF_CNTRL_BASE;
-        res[1].end      = res[1].start + SZ_4K - 1;
-        res[1].flags    = IORESOURCE_MEM;
-        ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
-        if (ret < 0) {
-                kfree(pdev);
-                return ret;
-        }
-        return platform_device_register(pdev);
-}
-static struct resource keypad_resources[] = {
-        {
-                .start  = TNETV107X_KEYPAD_BASE,
-                .end    = TNETV107X_KEYPAD_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_TNETV107X_KEYPAD,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "press",
-        },
-        {
-                .start  = IRQ_TNETV107X_KEYPAD_FREE,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "release",
-        },
-};
-static struct platform_device keypad_device = {
-        .name           = "tnetv107x-keypad",
-        .num_resources  = ARRAY_SIZE(keypad_resources),
-        .resource       = keypad_resources,
-};
-static struct resource tsc_resources[] = {
-        {
-                .start  = TNETV107X_TSC_BASE,
-                .end    = TNETV107X_TSC_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_TNETV107X_TSC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device tsc_device = {
-        .name           = "tnetv107x-ts",
-        .num_resources  = ARRAY_SIZE(tsc_resources),
-        .resource       = tsc_resources,
-};
-static struct resource ssp_resources[] = {
-        {
-                .start  = TNETV107X_SSP_BASE,
-                .end    = TNETV107X_SSP_BASE + 0x1ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_TNETV107X_SSP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device ssp_device = {
-        .name           = "ti-ssp",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(ssp_resources),
-        .resource       = ssp_resources,
-};
-void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
-{
-        int i, error;
-        struct clk *tsc_clk;
-        /*
-         * The reset defaults for tnetv107x tsc clock divider is set too high.
-         * This forces the clock down to a range that allows the ADC to
-         * complete sample conversion in time.
-         */
-        tsc_clk = clk_get(NULL, "sys_tsc_clk");
-        if (!IS_ERR(tsc_clk)) {
-                error = clk_set_rate(tsc_clk, 5000000);
-                WARN_ON(error < 0);
-                clk_put(tsc_clk);
-        }
-        platform_device_register(&edma_device);
-        platform_device_register(&tnetv107x_wdt_device);
-        platform_device_register(&tsc_device);
-        if (info->serial_config)
-                davinci_serial_init(tnetv107x_serial_device);
-        for (i = 0; i < 2; i++)
-                if (info->mmc_config[i]) {
-                        mmc_devices[i].dev.platform_data = info->mmc_config[i];
-                        platform_device_register(&mmc_devices[i]);
-                }
-        for (i = 0; i < 4; i++)
-                if (info->nand_config[i])
-                        nand_init(i, info->nand_config[i]);
-        if (info->keypad_config) {
-                keypad_device.dev.platform_data = info->keypad_config;
-                platform_device_register(&keypad_device);
-        }
-        if (info->ssp_config) {
-                ssp_device.dev.platform_data = info->ssp_config;
-                platform_device_register(&ssp_device);
-        }
-}
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 5cf9a027dcc6..6257aa452568 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -313,9 +313,9 @@ void davinci_restart(enum reboot_mode mode, const char *cmd)
        davinci_watchdog_reset(&davinci_wdt_device);
 }
-static void davinci_init_wdt(void)
+int davinci_init_wdt(void)
 {
-        platform_device_register(&davinci_wdt_device);
+        return platform_device_register(&davinci_wdt_device);
 }
 static struct platform_device davinci_gpio_device = {
@@ -348,16 +348,3 @@ struct davinci_timer_instance davinci_timer_instance[2] = {
        },
 };
-/*-------------------------------------------------------------------------*/
-static int __init davinci_init_devices(void)
-{
-        /* please keep these calls, and their implementations above,
-         * in alphabetical order so they're easier to sort through.
-         */
-        davinci_init_wdt();
-        return 0;
-}
-arch_initcall(davinci_init_devices);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 4668c0e19767..07381d8cea62 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -1076,12 +1076,18 @@ int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
 static int __init dm355_init_devices(void)
 {
+        int ret = 0;
        if (!cpu_is_davinci_dm355())
                return 0;
        davinci_cfg_reg(DM355_INT_EDMA_CC);
        platform_device_register(&dm355_edma_device);
-        return 0;
+        ret = davinci_init_wdt();
+        if (ret)
+                pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
+        return ret;
 }
 postcore_initcall(dm355_init_devices);
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index b44b49e2801a..08a61b938333 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1436,6 +1436,8 @@ int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
 static int __init dm365_init_devices(void)
 {
+        int ret = 0;
        if (!cpu_is_davinci_dm365())
                return 0;
@@ -1445,6 +1447,10 @@ static int __init dm365_init_devices(void)
        platform_device_register(&dm365_mdio_device);
        platform_device_register(&dm365_emac_device);
-        return 0;
+        ret = davinci_init_wdt();
+        if (ret)
+                pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
+        return ret;
 }
 postcore_initcall(dm365_init_devices);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 5c3e0be95ef3..5debffba4b24 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -964,6 +964,8 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
 static int __init dm644x_init_devices(void)
 {
+        int ret = 0;
        if (!cpu_is_davinci_dm644x())
                return 0;
@@ -972,6 +974,10 @@ static int __init dm644x_init_devices(void)
        platform_device_register(&dm644x_mdio_device);
        platform_device_register(&dm644x_emac_device);
-        return 0;
+        ret = davinci_init_wdt();
+        if (ret)
+                pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
+        return ret;
 }
 postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 81768dd47096..332d00d24dc2 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -955,12 +955,18 @@ void __init dm646x_init(void)
 static int __init dm646x_init_devices(void)
 {
+        int ret = 0;
        if (!cpu_is_davinci_dm646x())
                return 0;
        platform_device_register(&dm646x_mdio_device);
        platform_device_register(&dm646x_emac_device);
-        return 0;
+        ret = davinci_init_wdt();
+        if (ret)
+                pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
+        return ret;
 }
 postcore_initcall(dm646x_init_devices);
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 957fb87e832e..1fc84e21664d 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -33,7 +33,6 @@ struct davinci_id {
 #define DAVINCI_CPU_ID_DM365            0x03650000
 #define DAVINCI_CPU_ID_DA830            0x08300000
 #define DAVINCI_CPU_ID_DA850            0x08500000
-#define DAVINCI_CPU_ID_TNETV107X        0x0b8a0000
 #define IS_DAVINCI_CPU(type, id)                                        \
 static inline int is_davinci_ ##type(void)                              \
@@ -47,7 +46,6 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
 IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
 IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
 IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
-IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
 #ifdef CONFIG_ARCH_DAVINCI_DM644x
 #define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -85,10 +83,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
 #define cpu_is_davinci_da850() 0
 #endif
-#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
-#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
-#else
-#define cpu_is_davinci_tnetv107x() 0
-#endif
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index ec76c7775c2e..354af71798dc 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -401,103 +401,6 @@
 #define DA850_N_CP_INTC_IRQ             101
-/* TNETV107X specific interrupts */
-#define IRQ_TNETV107X_TDM1_TXDMA                0
-#define IRQ_TNETV107X_EXT_INT_0                 1
-#define IRQ_TNETV107X_EXT_INT_1                 2
-#define IRQ_TNETV107X_GPIO_INT12                3
-#define IRQ_TNETV107X_GPIO_INT13                4
-#define IRQ_TNETV107X_TIMER_0_TINT12            5
-#define IRQ_TNETV107X_TIMER_1_TINT12            6
-#define IRQ_TNETV107X_UART0                     7
-#define IRQ_TNETV107X_TDM1_RXDMA                8
-#define IRQ_TNETV107X_MCDMA_INT0                9
-#define IRQ_TNETV107X_MCDMA_INT1                10
-#define IRQ_TNETV107X_TPCC                      11
-#define IRQ_TNETV107X_TPCC_INT0                 12
-#define IRQ_TNETV107X_TPCC_INT1                 13
-#define IRQ_TNETV107X_TPCC_INT2                 14
-#define IRQ_TNETV107X_TPCC_INT3                 15
-#define IRQ_TNETV107X_TPTC0                     16
-#define IRQ_TNETV107X_TPTC1                     17
-#define IRQ_TNETV107X_TIMER_0_TINT34            18
-#define IRQ_TNETV107X_ETHSS                     19
-#define IRQ_TNETV107X_TIMER_1_TINT34            20
-#define IRQ_TNETV107X_DSP2ARM_INT0              21
-#define IRQ_TNETV107X_DSP2ARM_INT1              22
-#define IRQ_TNETV107X_ARM_NPMUIRQ               23
-#define IRQ_TNETV107X_USB1                      24
-#define IRQ_TNETV107X_VLYNQ                     25
-#define IRQ_TNETV107X_UART0_DMATX               26
-#define IRQ_TNETV107X_UART0_DMARX               27
-#define IRQ_TNETV107X_TDM1_TXMCSP               28
-#define IRQ_TNETV107X_SSP                       29
-#define IRQ_TNETV107X_MCDMA_INT2                30
-#define IRQ_TNETV107X_MCDMA_INT3                31
-#define IRQ_TNETV107X_TDM_CODECIF_EOT           32
-#define IRQ_TNETV107X_IMCOP_SQR_ARM             33
-#define IRQ_TNETV107X_USB0                      34
-#define IRQ_TNETV107X_USB_CDMA                  35
-#define IRQ_TNETV107X_LCD                       36
-#define IRQ_TNETV107X_KEYPAD                    37
-#define IRQ_TNETV107X_KEYPAD_FREE               38
-#define IRQ_TNETV107X_RNG                       39
-#define IRQ_TNETV107X_PKA                       40
-#define IRQ_TNETV107X_TDM0_TXDMA                41
-#define IRQ_TNETV107X_TDM0_RXDMA                42
-#define IRQ_TNETV107X_TDM0_TXMCSP               43
-#define IRQ_TNETV107X_TDM0_RXMCSP               44
-#define IRQ_TNETV107X_TDM1_RXMCSP               45
-#define IRQ_TNETV107X_SDIO1                     46
-#define IRQ_TNETV107X_SDIO0                     47
-#define IRQ_TNETV107X_TSC                       48
-#define IRQ_TNETV107X_TS                        49
-#define IRQ_TNETV107X_UART1                     50
-#define IRQ_TNETV107X_MBX_LITE                  51
-#define IRQ_TNETV107X_GPIO_INT00                52
-#define IRQ_TNETV107X_GPIO_INT01                53
-#define IRQ_TNETV107X_GPIO_INT02                54
-#define IRQ_TNETV107X_GPIO_INT03                55
-#define IRQ_TNETV107X_UART2                     56
-#define IRQ_TNETV107X_UART2_DMATX               57
-#define IRQ_TNETV107X_UART2_DMARX               58
-#define IRQ_TNETV107X_IMCOP_IMX                 59
-#define IRQ_TNETV107X_IMCOP_VLCD                60
-#define IRQ_TNETV107X_AES                       61
-#define IRQ_TNETV107X_DES                       62
-#define IRQ_TNETV107X_SHAMD5                    63
-#define IRQ_TNETV107X_TPCC_ERR                  68
-#define IRQ_TNETV107X_TPCC_PROT                 69
-#define IRQ_TNETV107X_TPTC0_ERR                 70
-#define IRQ_TNETV107X_TPTC1_ERR                 71
-#define IRQ_TNETV107X_UART0_ERR                 72
-#define IRQ_TNETV107X_UART1_ERR                 73
-#define IRQ_TNETV107X_AEMIF_ERR                 74
-#define IRQ_TNETV107X_DDR_ERR                   75
-#define IRQ_TNETV107X_WDTARM_INT0               76
-#define IRQ_TNETV107X_MCDMA_ERR                 77
-#define IRQ_TNETV107X_GPIO_ERR                  78
-#define IRQ_TNETV107X_MPU_ADDR                  79
-#define IRQ_TNETV107X_MPU_PROT                  80
-#define IRQ_TNETV107X_IOPU_ADDR                 81
-#define IRQ_TNETV107X_IOPU_PROT                 82
-#define IRQ_TNETV107X_KEYPAD_ADDR_ERR           83
-#define IRQ_TNETV107X_WDT0_ADDR_ERR             84
-#define IRQ_TNETV107X_WDT1_ADDR_ERR             85
-#define IRQ_TNETV107X_CLKCTL_ADDR_ERR           86
-#define IRQ_TNETV107X_PLL_UNLOCK                87
-#define IRQ_TNETV107X_WDTDSP_INT0               88
-#define IRQ_TNETV107X_SEC_CTRL_VIOLATION        89
-#define IRQ_TNETV107X_KEY_MNG_VIOLATION         90
-#define IRQ_TNETV107X_PBIST_CPU                 91
-#define IRQ_TNETV107X_WDTARM                    92
-#define IRQ_TNETV107X_PSC                       93
-#define IRQ_TNETV107X_MMC0                      94
-#define IRQ_TNETV107X_MMC1                      95
-#define TNETV107X_N_CP_INTC_IRQ                 96
 /* da850 currently has the most gpio pins (144) */
 #define DAVINCI_N_GPIO                  144
 /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 9e95b8a1edb6..631655e68ae0 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -972,275 +972,6 @@ enum davinci_da850_index {
        DA850_VPIF_CLKO3,
 };
-enum davinci_tnetv107x_index {
-        TNETV107X_ASR_A00,
-        TNETV107X_GPIO32,
-        TNETV107X_ASR_A01,
-        TNETV107X_GPIO33,
-        TNETV107X_ASR_A02,
-        TNETV107X_GPIO34,
-        TNETV107X_ASR_A03,
-        TNETV107X_GPIO35,
-        TNETV107X_ASR_A04,
-        TNETV107X_GPIO36,
-        TNETV107X_ASR_A05,
-        TNETV107X_GPIO37,
-        TNETV107X_ASR_A06,
-        TNETV107X_GPIO38,
-        TNETV107X_ASR_A07,
-        TNETV107X_GPIO39,
-        TNETV107X_ASR_A08,
-        TNETV107X_GPIO40,
-        TNETV107X_ASR_A09,
-        TNETV107X_GPIO41,
-        TNETV107X_ASR_A10,
-        TNETV107X_GPIO42,
-        TNETV107X_ASR_A11,
-        TNETV107X_BOOT_STRP_0,
-        TNETV107X_ASR_A12,
-        TNETV107X_BOOT_STRP_1,
-        TNETV107X_ASR_A13,
-        TNETV107X_GPIO43,
-        TNETV107X_ASR_A14,
-        TNETV107X_GPIO44,
-        TNETV107X_ASR_A15,
-        TNETV107X_GPIO45,
-        TNETV107X_ASR_A16,
-        TNETV107X_GPIO46,
-        TNETV107X_ASR_A17,
-        TNETV107X_GPIO47,
-        TNETV107X_ASR_A18,
-        TNETV107X_GPIO48,
-        TNETV107X_SDIO1_DATA3_0,
-        TNETV107X_ASR_A19,
-        TNETV107X_GPIO49,
-        TNETV107X_SDIO1_DATA2_0,
-        TNETV107X_ASR_A20,
-        TNETV107X_GPIO50,
-        TNETV107X_SDIO1_DATA1_0,
-        TNETV107X_ASR_A21,
-        TNETV107X_GPIO51,
-        TNETV107X_SDIO1_DATA0_0,
-        TNETV107X_ASR_A22,
-        TNETV107X_GPIO52,
-        TNETV107X_SDIO1_CMD_0,
-        TNETV107X_ASR_A23,
-        TNETV107X_GPIO53,
-        TNETV107X_SDIO1_CLK_0,
-        TNETV107X_ASR_BA_1,
-        TNETV107X_GPIO54,
-        TNETV107X_SYS_PLL_CLK,
-        TNETV107X_ASR_CS0,
-        TNETV107X_ASR_CS1,
-        TNETV107X_ASR_CS2,
-        TNETV107X_TDM_PLL_CLK,
-        TNETV107X_ASR_CS3,
-        TNETV107X_ETH_PHY_CLK,
-        TNETV107X_ASR_D00,
-        TNETV107X_GPIO55,
-        TNETV107X_ASR_D01,
-        TNETV107X_GPIO56,
-        TNETV107X_ASR_D02,
-        TNETV107X_GPIO57,
-        TNETV107X_ASR_D03,
-        TNETV107X_GPIO58,
-        TNETV107X_ASR_D04,
-        TNETV107X_GPIO59_0,
-        TNETV107X_ASR_D05,
-        TNETV107X_GPIO60_0,
-        TNETV107X_ASR_D06,
-        TNETV107X_GPIO61_0,
-        TNETV107X_ASR_D07,
-        TNETV107X_GPIO62_0,
-        TNETV107X_ASR_D08,
-        TNETV107X_GPIO63_0,
-        TNETV107X_ASR_D09,
-        TNETV107X_GPIO64_0,
-        TNETV107X_ASR_D10,
-        TNETV107X_SDIO1_DATA3_1,
-        TNETV107X_ASR_D11,
-        TNETV107X_SDIO1_DATA2_1,
-        TNETV107X_ASR_D12,
-        TNETV107X_SDIO1_DATA1_1,
-        TNETV107X_ASR_D13,
-        TNETV107X_SDIO1_DATA0_1,
-        TNETV107X_ASR_D14,
-        TNETV107X_SDIO1_CMD_1,
-        TNETV107X_ASR_D15,
-        TNETV107X_SDIO1_CLK_1,
-        TNETV107X_ASR_OE,
-        TNETV107X_BOOT_STRP_2,
-        TNETV107X_ASR_RNW,
-        TNETV107X_GPIO29_0,
-        TNETV107X_ASR_WAIT,
-        TNETV107X_GPIO30_0,
-        TNETV107X_ASR_WE,
-        TNETV107X_BOOT_STRP_3,
-        TNETV107X_ASR_WE_DQM0,
-        TNETV107X_GPIO31,
-        TNETV107X_LCD_PD17_0,
-        TNETV107X_ASR_WE_DQM1,
-        TNETV107X_ASR_BA0_0,
-        TNETV107X_VLYNQ_CLK,
-        TNETV107X_GPIO14,
-        TNETV107X_LCD_PD19_0,
-        TNETV107X_VLYNQ_RXD0,
-        TNETV107X_GPIO15,
-        TNETV107X_LCD_PD20_0,
-        TNETV107X_VLYNQ_RXD1,
-        TNETV107X_GPIO16,
-        TNETV107X_LCD_PD21_0,
-        TNETV107X_VLYNQ_TXD0,
-        TNETV107X_GPIO17,
-        TNETV107X_LCD_PD22_0,
-        TNETV107X_VLYNQ_TXD1,
-        TNETV107X_GPIO18,
-        TNETV107X_LCD_PD23_0,
-        TNETV107X_SDIO0_CLK,
-        TNETV107X_GPIO19,
-        TNETV107X_SDIO0_CMD,
-        TNETV107X_GPIO20,
-        TNETV107X_SDIO0_DATA0,
-        TNETV107X_GPIO21,
-        TNETV107X_SDIO0_DATA1,
-        TNETV107X_GPIO22,
-        TNETV107X_SDIO0_DATA2,
-        TNETV107X_GPIO23,
-        TNETV107X_SDIO0_DATA3,
-        TNETV107X_GPIO24,
-        TNETV107X_EMU0,
-        TNETV107X_EMU1,
-        TNETV107X_RTCK,
-        TNETV107X_TRST_N,
-        TNETV107X_TCK,
-        TNETV107X_TDI,
-        TNETV107X_TDO,
-        TNETV107X_TMS,
-        TNETV107X_TDM1_CLK,
-        TNETV107X_TDM1_RX,
-        TNETV107X_TDM1_TX,
-        TNETV107X_TDM1_FS,
-        TNETV107X_KEYPAD_R0,
-        TNETV107X_KEYPAD_R1,
-        TNETV107X_KEYPAD_R2,
-        TNETV107X_KEYPAD_R3,
-        TNETV107X_KEYPAD_R4,
-        TNETV107X_KEYPAD_R5,
-        TNETV107X_KEYPAD_R6,
-        TNETV107X_GPIO12,
-        TNETV107X_KEYPAD_R7,
-        TNETV107X_GPIO10,
-        TNETV107X_KEYPAD_C0,
-        TNETV107X_KEYPAD_C1,
-        TNETV107X_KEYPAD_C2,
-        TNETV107X_KEYPAD_C3,
-        TNETV107X_KEYPAD_C4,
-        TNETV107X_KEYPAD_C5,
-        TNETV107X_KEYPAD_C6,
-        TNETV107X_GPIO13,
-        TNETV107X_TEST_CLK_IN,
-        TNETV107X_KEYPAD_C7,
-        TNETV107X_GPIO11,
-        TNETV107X_SSP0_0,
-        TNETV107X_SCC_DCLK,
-        TNETV107X_LCD_PD20_1,
-        TNETV107X_SSP0_1,
-        TNETV107X_SCC_CS_N,
-        TNETV107X_LCD_PD21_1,
-        TNETV107X_SSP0_2,
-        TNETV107X_SCC_D,
-        TNETV107X_LCD_PD22_1,
-        TNETV107X_SSP0_3,
-        TNETV107X_SCC_RESETN,
-        TNETV107X_LCD_PD23_1,
-        TNETV107X_SSP1_0,
-        TNETV107X_GPIO25,
-        TNETV107X_UART2_CTS,
-        TNETV107X_SSP1_1,
-        TNETV107X_GPIO26,
-        TNETV107X_UART2_RD,
-        TNETV107X_SSP1_2,
-        TNETV107X_GPIO27,
-        TNETV107X_UART2_RTS,
-        TNETV107X_SSP1_3,
-        TNETV107X_GPIO28,
-        TNETV107X_UART2_TD,
-        TNETV107X_UART0_CTS,
-        TNETV107X_UART0_RD,
-        TNETV107X_UART0_RTS,
-        TNETV107X_UART0_TD,
-        TNETV107X_UART1_RD,
-        TNETV107X_UART1_TD,
-        TNETV107X_LCD_AC_NCS,
-        TNETV107X_LCD_HSYNC_RNW,
-        TNETV107X_LCD_VSYNC_A0,
-        TNETV107X_LCD_MCLK,
-        TNETV107X_LCD_PD16_0,
-        TNETV107X_LCD_PCLK_E,
-        TNETV107X_LCD_PD00,
-        TNETV107X_LCD_PD01,
-        TNETV107X_LCD_PD02,
-        TNETV107X_LCD_PD03,
-        TNETV107X_LCD_PD04,
-        TNETV107X_LCD_PD05,
-        TNETV107X_LCD_PD06,
-        TNETV107X_LCD_PD07,
-        TNETV107X_LCD_PD08,
-        TNETV107X_GPIO59_1,
-        TNETV107X_LCD_PD09,
-        TNETV107X_GPIO60_1,
-        TNETV107X_LCD_PD10,
-        TNETV107X_ASR_BA0_1,
-        TNETV107X_GPIO61_1,
-        TNETV107X_LCD_PD11,
-        TNETV107X_GPIO62_1,
-        TNETV107X_LCD_PD12,
-        TNETV107X_GPIO63_1,
-        TNETV107X_LCD_PD13,
-        TNETV107X_GPIO64_1,
-        TNETV107X_LCD_PD14,
-        TNETV107X_GPIO29_1,
-        TNETV107X_LCD_PD15,
-        TNETV107X_GPIO30_1,
-        TNETV107X_EINT0,
-        TNETV107X_GPIO08,
-        TNETV107X_EINT1,
-        TNETV107X_GPIO09,
-        TNETV107X_GPIO00,
-        TNETV107X_LCD_PD20_2,
-        TNETV107X_TDM_CLK_IN_2,
-        TNETV107X_GPIO01,
-        TNETV107X_LCD_PD21_2,
-        TNETV107X_24M_CLK_OUT_1,
-        TNETV107X_GPIO02,
-        TNETV107X_LCD_PD22_2,
-        TNETV107X_GPIO03,
-        TNETV107X_LCD_PD23_2,
-        TNETV107X_GPIO04,
-        TNETV107X_LCD_PD16_1,
-        TNETV107X_USB0_RXERR,
-        TNETV107X_GPIO05,
-        TNETV107X_LCD_PD17_1,
-        TNETV107X_TDM_CLK_IN_1,
-        TNETV107X_GPIO06,
-        TNETV107X_LCD_PD18,
-        TNETV107X_24M_CLK_OUT_2,
-        TNETV107X_GPIO07,
-        TNETV107X_LCD_PD19_1,
-        TNETV107X_USB1_RXERR,
-        TNETV107X_ETH_PLL_CLK,
-        TNETV107X_MDIO,
-        TNETV107X_MDC,
-        TNETV107X_AIC_MUTE_STAT_N,
-        TNETV107X_TDM0_CLK,
-        TNETV107X_AIC_HNS_EN_N,
-        TNETV107X_TDM0_FS,
-        TNETV107X_AIC_HDS_EN_STAT_N,
-        TNETV107X_TDM0_TX,
-        TNETV107X_AIC_HNF_EN_STAT_N,
-        TNETV107X_TDM0_RX,
-};
 #define PINMUX(x)               (4 * (x))
 #ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 0a22710493fd..99d47cfa301f 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -182,53 +182,6 @@
 #define DA8XX_LPSC1_CR_P3_SS            26
 #define DA8XX_LPSC1_L3_CBA_RAM          31
-/* TNETV107X LPSC Assignments */
-#define TNETV107X_LPSC_ARM                      0
-#define TNETV107X_LPSC_GEM                      1
-#define TNETV107X_LPSC_DDR2_PHY                 2
-#define TNETV107X_LPSC_TPCC                     3
-#define TNETV107X_LPSC_TPTC0                    4
-#define TNETV107X_LPSC_TPTC1                    5
-#define TNETV107X_LPSC_RAM                      6
-#define TNETV107X_LPSC_MBX_LITE                 7
-#define TNETV107X_LPSC_LCD                      8
-#define TNETV107X_LPSC_ETHSS                    9
-#define TNETV107X_LPSC_AEMIF                    10
-#define TNETV107X_LPSC_CHIP_CFG                 11
-#define TNETV107X_LPSC_TSC                      12
-#define TNETV107X_LPSC_ROM                      13
-#define TNETV107X_LPSC_UART2                    14
-#define TNETV107X_LPSC_PKTSEC                   15
-#define TNETV107X_LPSC_SECCTL                   16
-#define TNETV107X_LPSC_KEYMGR                   17
-#define TNETV107X_LPSC_KEYPAD                   18
-#define TNETV107X_LPSC_GPIO                     19
-#define TNETV107X_LPSC_MDIO                     20
-#define TNETV107X_LPSC_SDIO0                    21
-#define TNETV107X_LPSC_UART0                    22
-#define TNETV107X_LPSC_UART1                    23
-#define TNETV107X_LPSC_TIMER0                   24
-#define TNETV107X_LPSC_TIMER1                   25
-#define TNETV107X_LPSC_WDT_ARM                  26
-#define TNETV107X_LPSC_WDT_DSP                  27
-#define TNETV107X_LPSC_SSP                      28
-#define TNETV107X_LPSC_TDM0                     29
-#define TNETV107X_LPSC_VLYNQ                    30
-#define TNETV107X_LPSC_MCDMA                    31
-#define TNETV107X_LPSC_USB0                     32
-#define TNETV107X_LPSC_TDM1                     33
-#define TNETV107X_LPSC_DEBUGSS                  34
-#define TNETV107X_LPSC_ETHSS_RGMII              35
-#define TNETV107X_LPSC_SYSTEM                   36
-#define TNETV107X_LPSC_IMCOP                    37
-#define TNETV107X_LPSC_SPARE                    38
-#define TNETV107X_LPSC_SDIO1                    39
-#define TNETV107X_LPSC_USB1                     40
-#define TNETV107X_LPSC_USBSS                    41
-#define TNETV107X_LPSC_DDR2_EMIF1_VRST          42
-#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST      43
-#define TNETV107X_LPSC_MAX                      44
 /* PSC register offsets */
 #define EPCPR           0x070
 #define PTCMD           0x120
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index ce402cd21fa0..d4b4aa87964f 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -23,14 +23,6 @@
 #define DA8XX_UART1_BASE        (IO_PHYS + 0x10c000)
 #define DA8XX_UART2_BASE        (IO_PHYS + 0x10d000)
-#define TNETV107X_UART0_BASE    0x08108100
-#define TNETV107X_UART1_BASE    0x08088400
-#define TNETV107X_UART2_BASE    0x08108300
-#define TNETV107X_UART0_VIRT    IOMEM(0xfee08100)
-#define TNETV107X_UART1_VIRT    IOMEM(0xfed88400)
-#define TNETV107X_UART2_VIRT    IOMEM(0xfee08300)
 /* DaVinci UART register offsets */
 #define UART_DAVINCI_PWREMU             0x0c
 #define UART_DM646X_SCR                 0x10
diff --git a/arch/arm/mach-davinci/include/mach/timex.h b/arch/arm/mach-davinci/include/mach/timex.h
deleted file mode 100644
index 9b885298f106..000000000000
--- a/arch/arm/mach-davinci/include/mach/timex.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * DaVinci timer defines
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-/*
- * Alert: Not all timers of the DaVinci family run at a frequency of 27MHz,
- * but we should be fine as long as CLOCK_TICK_RATE or LATCH (see include/
- * linux/jiffies.h) are not used directly in code. Currently none of the
- * code relevant to DaVinci platform depends on these values directly.
- */
-#define CLOCK_TICK_RATE 27000000
-#endif /* __ASM_ARCH_TIMEX_H__ */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
deleted file mode 100644
index 494fcf5ccfe1..000000000000
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Texas Instruments TNETV107X SoC Specific Defines
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
-#define __ASM_ARCH_DAVINCI_TNETV107X_H
-#include <asm/sizes.h>
-#define TNETV107X_DDR_BASE      0x80000000
-/*
- * Fixed mapping for early init starts here. If low-level debug is enabled,
- * this area also gets mapped via io_pg_offset and io_phys by the boot code.
- * To fit in with the io_pg_offset calculation, the io base address selected
- * here _must_ be a multiple of 2^20.
- */
-#define TNETV107X_IO_BASE       0x08000000
-#define TNETV107X_IO_VIRT       (IO_VIRT + SZ_1M)
-#define TNETV107X_N_GPIO        65
-#ifndef __ASSEMBLY__
-#include <linux/serial_8250.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/mfd/ti_ssp.h>
-#include <linux/reboot.h>
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <mach/serial.h>
-struct tnetv107x_device_info {
-        struct davinci_mmc_config       *mmc_config[2];  /* 2 controllers */
-        struct davinci_nand_pdata       *nand_config[4]; /* 4 chipsels */
-        struct matrix_keypad_platform_data *keypad_config;
-        struct ti_ssp_data              *ssp_config;
-};
-extern struct platform_device tnetv107x_wdt_device;
-extern struct platform_device tnetv107x_serial_device[];
-extern void tnetv107x_init(void);
-extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
-extern void tnetv107x_irq_init(void);
-void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
-#endif
-#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index f49c2916aa3a..8fb97b93b6bb 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -68,9 +68,6 @@ static inline void set_uart_info(u32 phys)
 #define DEBUG_LL_DA8XX(machine, port)                           \
        _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
-#define DEBUG_LL_TNETV107X(machine, port)                       \
-        _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE)
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
        /*
@@ -94,9 +91,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                DEBUG_LL_DA8XX(davinci_da850_evm,       2);
                DEBUG_LL_DA8XX(mityomapl138,            1);
                DEBUG_LL_DA8XX(omapl138_hawkboard,      2);
-                /* TNETV107x boards */
-                DEBUG_LL_TNETV107X(tnetv107x,           1);
        } while (0);
 }
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
deleted file mode 100644
index f4d7fbb24b3b..000000000000
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ /dev/null
@@ -1,766 +0,0 @@
-/*
- * Texas Instruments TNETV107X SoC Support
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/reboot.h>
-#include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/time.h>
-#include <mach/cputype.h>
-#include <mach/psc.h>
-#include <mach/cp_intc.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/tnetv107x.h>
-#include <mach/gpio-davinci.h>
-#include "clock.h"
-#include "mux.h"
-/* Base addresses for on-chip devices */
-#define TNETV107X_INTC_BASE                     0x03000000
-#define TNETV107X_TIMER0_BASE                   0x08086500
-#define TNETV107X_TIMER1_BASE                   0x08086600
-#define TNETV107X_CHIP_CFG_BASE                 0x08087000
-#define TNETV107X_GPIO_BASE                     0x08088000
-#define TNETV107X_CLOCK_CONTROL_BASE            0x0808a000
-#define TNETV107X_PSC_BASE                      0x0808b000
-/* Reference clock frequencies */
-#define OSC_FREQ_ONCHIP         (24000 * 1000)
-#define OSC_FREQ_OFFCHIP_SYS    (25000 * 1000)
-#define OSC_FREQ_OFFCHIP_ETH    (25000 * 1000)
-#define OSC_FREQ_OFFCHIP_TDM    (19200 * 1000)
-#define N_PLLS  3
-/* Clock Control Registers */
-struct clk_ctrl_regs {
-        u32     pll_bypass;
-        u32     _reserved0;
-        u32     gem_lrst;
-        u32     _reserved1;
-        u32     pll_unlock_stat;
-        u32     sys_unlock;
-        u32     eth_unlock;
-        u32     tdm_unlock;
-};
-/* SSPLL Registers */
-struct sspll_regs {
-        u32     modes;
-        u32     post_div;
-        u32     pre_div;
-        u32     mult_factor;
-        u32     divider_range;
-        u32     bw_divider;
-        u32     spr_amount;
-        u32     spr_rate_div;
-        u32     diag;
-};
-/* Watchdog Timer Registers */
-struct wdt_regs {
-        u32     kick_lock;
-        u32     kick;
-        u32     change_lock;
-        u32     change ;
-        u32     disable_lock;
-        u32     disable;
-        u32     prescale_lock;
-        u32     prescale;
-};
-static struct clk_ctrl_regs __iomem *clk_ctrl_regs;
-static struct sspll_regs __iomem *sspll_regs[N_PLLS];
-static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 };
-/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */
-static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) };
-/* offchip (external) reference clock frequencies */
-static u32 pll_ext_freq[] = {
-        OSC_FREQ_OFFCHIP_SYS,
-        OSC_FREQ_OFFCHIP_TDM,
-        OSC_FREQ_OFFCHIP_ETH
-};
-/* PSC control registers */
-static u32 psc_regs[] = { TNETV107X_PSC_BASE };
-/* Host map for interrupt controller */
-static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
-static unsigned long clk_sspll_recalc(struct clk *clk);
-/* Level 1 - the PLLs */
-#define define_pll_clk(cname, pll, divmask, base)       \
-        static struct pll_data pll_##cname##_data = {   \
-                .num            = pll,                  \
-                .div_ratio_mask = divmask,              \
-                .phys_base      = base +                \
-                        TNETV107X_CLOCK_CONTROL_BASE,   \
-        };                                              \
-        static struct clk pll_##cname##_clk = {         \
-                .name           = "pll_" #cname "_clk", \
-                .pll_data       = &pll_##cname##_data,  \
-                .flags          = CLK_PLL,              \
-                .recalc         = clk_sspll_recalc,     \
-        }
-define_pll_clk(sys, 0, 0x1ff, 0x600);
-define_pll_clk(tdm, 1, 0x0ff, 0x200);
-define_pll_clk(eth, 2, 0x0ff, 0x400);
-/* Level 2 - divided outputs from the PLLs */
-#define define_pll_div_clk(pll, cname, div)                     \
-        static struct clk pll##_##cname##_clk = {               \
-                .name           = #pll "_" #cname "_clk",       \
-                .parent         = &pll_##pll##_clk,             \
-                .flags          = CLK_PLL,                      \
-                .div_reg        = PLLDIV##div,                  \
-                .set_rate       = davinci_set_sysclk_rate,      \
-        }
-define_pll_div_clk(sys, arm1176,        1);
-define_pll_div_clk(sys, dsp,            2);
-define_pll_div_clk(sys, ddr,            3);
-define_pll_div_clk(sys, full,           4);
-define_pll_div_clk(sys, lcd,            5);
-define_pll_div_clk(sys, vlynq_ref,      6);
-define_pll_div_clk(sys, tsc,            7);
-define_pll_div_clk(sys, half,           8);
-define_pll_div_clk(eth, 5mhz,           1);
-define_pll_div_clk(eth, 50mhz,          2);
-define_pll_div_clk(eth, 125mhz,         3);
-define_pll_div_clk(eth, 250mhz,         4);
-define_pll_div_clk(eth, 25mhz,          5);
-define_pll_div_clk(tdm, 0,              1);
-define_pll_div_clk(tdm, extra,          2);
-define_pll_div_clk(tdm, 1,              3);
-/* Level 3 - LPSC gated clocks */
-#define __lpsc_clk(cname, _parent, mod, flg)            \
-        static struct clk clk_##cname = {               \
-                .name           = #cname,               \
-                .parent         = &_parent,             \
-                .lpsc           = TNETV107X_LPSC_##mod,\
-                .flags          = flg,                  \
-        }
-#define lpsc_clk_enabled(cname, parent, mod)            \
-        __lpsc_clk(cname, parent, mod, ALWAYS_ENABLED)
-#define lpsc_clk(cname, parent, mod)                    \
-        __lpsc_clk(cname, parent, mod, 0)
-lpsc_clk_enabled(arm,           sys_arm1176_clk, ARM);
-lpsc_clk_enabled(gem,           sys_dsp_clk,    GEM);
-lpsc_clk_enabled(ddr2_phy,      sys_ddr_clk,    DDR2_PHY);
-lpsc_clk_enabled(tpcc,          sys_full_clk,   TPCC);
-lpsc_clk_enabled(tptc0,         sys_full_clk,   TPTC0);
-lpsc_clk_enabled(tptc1,         sys_full_clk,   TPTC1);
-lpsc_clk_enabled(ram,           sys_full_clk,   RAM);
-lpsc_clk_enabled(aemif,         sys_full_clk,   AEMIF);
-lpsc_clk_enabled(chipcfg,       sys_half_clk,   CHIP_CFG);
-lpsc_clk_enabled(rom,           sys_half_clk,   ROM);
-lpsc_clk_enabled(secctl,        sys_half_clk,   SECCTL);
-lpsc_clk_enabled(keymgr,        sys_half_clk,   KEYMGR);
-lpsc_clk_enabled(gpio,          sys_half_clk,   GPIO);
-lpsc_clk_enabled(debugss,       sys_half_clk,   DEBUGSS);
-lpsc_clk_enabled(system,        sys_half_clk,   SYSTEM);
-lpsc_clk_enabled(ddr2_vrst,     sys_ddr_clk,    DDR2_EMIF1_VRST);
-lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk,    DDR2_EMIF2_VCTL_RST);
-lpsc_clk_enabled(wdt_arm,       sys_half_clk,   WDT_ARM);
-lpsc_clk_enabled(timer1,        sys_half_clk,   TIMER1);
-lpsc_clk(mbx_lite,      sys_arm1176_clk,        MBX_LITE);
-lpsc_clk(ethss,         eth_125mhz_clk,         ETHSS);
-lpsc_clk(tsc,           sys_tsc_clk,            TSC);
-lpsc_clk(uart0,         sys_half_clk,           UART0);
-lpsc_clk(uart1,         sys_half_clk,           UART1);
-lpsc_clk(uart2,         sys_half_clk,           UART2);
-lpsc_clk(pktsec,        sys_half_clk,           PKTSEC);
-lpsc_clk(keypad,        sys_half_clk,           KEYPAD);
-lpsc_clk(mdio,          sys_half_clk,           MDIO);
-lpsc_clk(sdio0,         sys_half_clk,           SDIO0);
-lpsc_clk(sdio1,         sys_half_clk,           SDIO1);
-lpsc_clk(timer0,        sys_half_clk,           TIMER0);
-lpsc_clk(wdt_dsp,       sys_half_clk,           WDT_DSP);
-lpsc_clk(ssp,           sys_half_clk,           SSP);
-lpsc_clk(tdm0,          tdm_0_clk,              TDM0);
-lpsc_clk(tdm1,          tdm_1_clk,              TDM1);
-lpsc_clk(vlynq,         sys_vlynq_ref_clk,      VLYNQ);
-lpsc_clk(mcdma,         sys_half_clk,           MCDMA);
-lpsc_clk(usbss,         sys_half_clk,           USBSS);
-lpsc_clk(usb0,          clk_usbss,              USB0);
-lpsc_clk(usb1,          clk_usbss,              USB1);
-lpsc_clk(ethss_rgmii,   eth_250mhz_clk,         ETHSS_RGMII);
-lpsc_clk(imcop,         sys_dsp_clk,            IMCOP);
-lpsc_clk(spare,         sys_half_clk,           SPARE);
-/* LCD needs a full power down to clear controller state */
-__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE);
-/* Level 4 - leaf clocks for LPSC modules shared across drivers */
-static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec };
-static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec };
-static struct clk_lookup clks[] = {
-        CLK(NULL,               "pll_sys_clk",          &pll_sys_clk),
-        CLK(NULL,               "pll_eth_clk",          &pll_eth_clk),
-        CLK(NULL,               "pll_tdm_clk",          &pll_tdm_clk),
-        CLK(NULL,               "sys_arm1176_clk",      &sys_arm1176_clk),
-        CLK(NULL,               "sys_dsp_clk",          &sys_dsp_clk),
-        CLK(NULL,               "sys_ddr_clk",          &sys_ddr_clk),
-        CLK(NULL,               "sys_full_clk",         &sys_full_clk),
-        CLK(NULL,               "sys_lcd_clk",          &sys_lcd_clk),
-        CLK(NULL,               "sys_vlynq_ref_clk",    &sys_vlynq_ref_clk),
-        CLK(NULL,               "sys_tsc_clk",          &sys_tsc_clk),
-        CLK(NULL,               "sys_half_clk",         &sys_half_clk),
-        CLK(NULL,               "eth_5mhz_clk",         &eth_5mhz_clk),
-        CLK(NULL,               "eth_50mhz_clk",        &eth_50mhz_clk),
-        CLK(NULL,               "eth_125mhz_clk",       &eth_125mhz_clk),
-        CLK(NULL,               "eth_250mhz_clk",       &eth_250mhz_clk),
-        CLK(NULL,               "eth_25mhz_clk",        &eth_25mhz_clk),
-        CLK(NULL,               "tdm_0_clk",            &tdm_0_clk),
-        CLK(NULL,               "tdm_extra_clk",        &tdm_extra_clk),
-        CLK(NULL,               "tdm_1_clk",            &tdm_1_clk),
-        CLK(NULL,               "clk_arm",              &clk_arm),
-        CLK(NULL,               "clk_gem",              &clk_gem),
-        CLK(NULL,               "clk_ddr2_phy",         &clk_ddr2_phy),
-        CLK(NULL,               "clk_tpcc",             &clk_tpcc),
-        CLK(NULL,               "clk_tptc0",            &clk_tptc0),
-        CLK(NULL,               "clk_tptc1",            &clk_tptc1),
-        CLK(NULL,               "clk_ram",              &clk_ram),
-        CLK(NULL,               "clk_mbx_lite",         &clk_mbx_lite),
-        CLK("tnetv107x-fb.0",   NULL,                   &clk_lcd),
-        CLK(NULL,               "clk_ethss",            &clk_ethss),
-        CLK(NULL,               "aemif",                &clk_aemif),
-        CLK(NULL,               "clk_chipcfg",          &clk_chipcfg),
-        CLK("tnetv107x-ts.0",   NULL,                   &clk_tsc),
-        CLK(NULL,               "clk_rom",              &clk_rom),
-        CLK("serial8250.2",     NULL,                   &clk_uart2),
-        CLK(NULL,               "clk_pktsec",           &clk_pktsec),
-        CLK("tnetv107x-rng.0",  NULL,                   &clk_rng),
-        CLK("tnetv107x-pka.0",  NULL,                   &clk_pka),
-        CLK(NULL,               "clk_secctl",           &clk_secctl),
-        CLK(NULL,               "clk_keymgr",           &clk_keymgr),
-        CLK("tnetv107x-keypad.0", NULL,                 &clk_keypad),
-        CLK(NULL,               "clk_gpio",             &clk_gpio),
-        CLK(NULL,               "clk_mdio",             &clk_mdio),
-        CLK("dm6441-mmc.0",     NULL,                   &clk_sdio0),
-        CLK("serial8250.0",     NULL,                   &clk_uart0),
-        CLK("serial8250.1",     NULL,                   &clk_uart1),
-        CLK(NULL,               "timer0",               &clk_timer0),
-        CLK(NULL,               "timer1",               &clk_timer1),
-        CLK("tnetv107x_wdt.0",  NULL,                   &clk_wdt_arm),
-        CLK(NULL,               "clk_wdt_dsp",          &clk_wdt_dsp),
-        CLK("ti-ssp",           NULL,                   &clk_ssp),
-        CLK(NULL,               "clk_tdm0",             &clk_tdm0),
-        CLK(NULL,               "clk_vlynq",            &clk_vlynq),
-        CLK(NULL,               "clk_mcdma",            &clk_mcdma),
-        CLK(NULL,               "clk_usbss",            &clk_usbss),
-        CLK(NULL,               "clk_usb0",             &clk_usb0),
-        CLK(NULL,               "clk_usb1",             &clk_usb1),
-        CLK(NULL,               "clk_tdm1",             &clk_tdm1),
-        CLK(NULL,               "clk_debugss",          &clk_debugss),
-        CLK(NULL,               "clk_ethss_rgmii",      &clk_ethss_rgmii),
-        CLK(NULL,               "clk_system",           &clk_system),
-        CLK(NULL,               "clk_imcop",            &clk_imcop),
-        CLK(NULL,               "clk_spare",            &clk_spare),
-        CLK("dm6441-mmc.1",     NULL,                   &clk_sdio1),
-        CLK(NULL,               "clk_ddr2_vrst",        &clk_ddr2_vrst),
-        CLK(NULL,               "clk_ddr2_vctl_rst",    &clk_ddr2_vctl_rst),
-        CLK(NULL,               NULL,                   NULL),
-};
-static const struct mux_config pins[] = {
-#ifdef CONFIG_DAVINCI_MUX
-        MUX_CFG(TNETV107X, ASR_A00,             0, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO32,              0, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A01,             0, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO33,              0, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A02,             0, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO34,              0, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A03,             0, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO35,              0, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A04,             0, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO36,              0, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A05,             0, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO37,              0, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A06,             1, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO38,              1, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A07,             1, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO39,              1, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A08,             1, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO40,              1, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A09,             1, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO41,              1, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A10,             1, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO42,              1, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A11,             1, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, BOOT_STRP_0,         1, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A12,             2, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, BOOT_STRP_1,         2, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A13,             2, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO43,              2, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A14,             2, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO44,              2, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A15,             2, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO45,              2, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A16,             2, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO46,              2, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A17,             2, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO47,              2, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A18,             3, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO48,              3, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA3_0,       3, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A19,             3, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO49,              3, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA2_0,       3, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A20,             3, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO50,              3, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA1_0,       3, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A21,             3, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO51,              3, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA0_0,       3, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A22,             3, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO52,              3, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_CMD_0,         3, 20, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A23,             3, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO53,              3, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_CLK_0,         3, 25, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_BA_1,            4, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO54,              4, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SYS_PLL_CLK,         4, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_CS0,             4, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ASR_CS1,             4, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ASR_CS2,             4, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM_PLL_CLK,         4, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_CS3,             4, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ETH_PHY_CLK,         4, 20, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, ASR_D00,             4, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO55,              4, 25, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D01,             5, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO56,              5, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D02,             5, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO57,              5, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D03,             5, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO58,              5, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D04,             5, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO59_0,            5, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D05,             5, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO60_0,            5, 20, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D06,             5, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO61_0,            5, 25, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D07,             6, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO62_0,            6, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D08,             6, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO63_0,            6, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D09,             6, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO64_0,            6, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D10,             6, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA3_1,       6, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D11,             6, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA2_1,       6, 20, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D12,             6, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA1_1,       6, 25, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D13,             7, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA0_1,       7, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D14,             7, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_CMD_1,         7, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D15,             7, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_CLK_1,         7, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_OE,              7, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, BOOT_STRP_2,         7, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_RNW,             7, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO29_0,            7, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_WAIT,            7, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO30_0,            7, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_WE,              8, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, BOOT_STRP_3,         8, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_WE_DQM0,         8, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO31,              8, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD17_0,          8, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_WE_DQM1,         8, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ASR_BA0_0,           8, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, VLYNQ_CLK,           9, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO14,              9, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD19_0,          9, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, VLYNQ_RXD0,          9, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO15,              9, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD20_0,          9, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, VLYNQ_RXD1,          9, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO16,              9, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD21_0,          9, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, VLYNQ_TXD0,          9, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO17,              9, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD22_0,          9, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, VLYNQ_TXD1,          9, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO18,              9, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD23_0,          9, 20, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, SDIO0_CLK,           10, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO19,              10, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_CMD,           10, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO20,              10, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_DATA0,         10, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO21,              10, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_DATA1,         10, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO22,              10, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_DATA2,         10, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO23,              10, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_DATA3,         10, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO24,              10, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, EMU0,                11, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, EMU1,                11, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, RTCK,                12, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TRST_N,              12, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TCK,                 12, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDI,                 12, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDO,                 12, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TMS,                 12, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM1_CLK,            13, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM1_RX,             13, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM1_TX,             13, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM1_FS,             13, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R0,           14, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R1,           14, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R2,           14, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R3,           14, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R4,           14, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R5,           14, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R6,           15, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO12,              15, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, KEYPAD_R7,           15, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO10,              15, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, KEYPAD_C0,           15, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C1,           15, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C2,           15, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C3,           15, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C4,           16, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C5,           16, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C6,           16, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO13,              16, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, TEST_CLK_IN,         16, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, KEYPAD_C7,           16, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO11,              16, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SSP0_0,              17, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SCC_DCLK,            17, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD20_1,          17, 0, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP0_1,              17, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SCC_CS_N,            17, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD21_1,          17, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP0_2,              17, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SCC_D,               17, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD22_1,          17, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP0_3,              17, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SCC_RESETN,          17, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD23_1,          17, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP1_0,              18, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO25,              18, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, UART2_CTS,           18, 0, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP1_1,              18, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO26,              18, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, UART2_RD,            18, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP1_2,              18, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO27,              18, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, UART2_RTS,           18, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP1_3,              18, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO28,              18, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, UART2_TD,            18, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, UART0_CTS,           19, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART0_RD,            19, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART0_RTS,           19, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART0_TD,            19, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART1_RD,            19, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART1_TD,            19, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_AC_NCS,          20, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_HSYNC_RNW,       20, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_VSYNC_A0,        20, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_MCLK,            20, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD16_0,          20, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PCLK_E,          20, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD00,            20, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD01,            21, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD02,            21, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD03,            21, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD04,            21, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD05,            21, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD06,            21, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD07,            22, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD08,            22, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO59_1,            22, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD09,            22, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO60_1,            22, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD10,            22, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ASR_BA0_1,           22, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, GPIO61_1,            22, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD11,            22, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO62_1,            22, 20, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD12,            22, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO63_1,            22, 25, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD13,            23, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO64_1,            23, 0, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD14,            23, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO29_1,            23, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD15,            23, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO30_1,            23, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, EINT0,               24, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO08,              24, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, EINT1,               24, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO09,              24, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, GPIO00,              24, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD20_2,          24, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, TDM_CLK_IN_2,        24, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO01,              24, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD21_2,          24, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, 24M_CLK_OUT_1,       24, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO02,              24, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD22_2,          24, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, GPIO03,              24, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD23_2,          24, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, GPIO04,              25, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD16_1,          25, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, USB0_RXERR,          25, 0, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO05,              25, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD17_1,          25, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, TDM_CLK_IN_1,        25, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO06,              25, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD18,            25, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, 24M_CLK_OUT_2,       25, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO07,              25, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD19_1,          25, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, USB1_RXERR,          25, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, ETH_PLL_CLK,         25, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, MDIO,                26, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, MDC,                 26, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, AIC_MUTE_STAT_N,     26, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM0_CLK,            26, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, AIC_HNS_EN_N,        26, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM0_FS,             26, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N,   26, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM0_TX,             26, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N,   26, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM0_RX,             26, 25, 0x1f, 0x04, false)
-#endif
-};
-/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
-static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = {
-        /* fill in default priority 7 */
-        [0 ... (TNETV107X_N_CP_INTC_IRQ - 1)]   = 7,
-        /* now override as needed, e.g. [xxx] = 5 */
-};
-/* Contents of JTAG ID register used to identify exact cpu type */
-static struct davinci_id ids[] = {
-        {
-                .variant        = 0x0,
-                .part_no        = 0xb8a1,
-                .manufacturer   = 0x017,
-                .cpu_id         = DAVINCI_CPU_ID_TNETV107X,
-                .name           = "tnetv107x rev 1.0",
-        },
-        {
-                .variant        = 0x1,
-                .part_no        = 0xb8a1,
-                .manufacturer   = 0x017,
-                .cpu_id         = DAVINCI_CPU_ID_TNETV107X,
-                .name           = "tnetv107x rev 1.1/1.2",
-        },
-};
-static struct davinci_timer_instance timer_instance[2] = {
-        {
-                .base           = TNETV107X_TIMER0_BASE,
-                .bottom_irq     = IRQ_TNETV107X_TIMER_0_TINT12,
-                .top_irq        = IRQ_TNETV107X_TIMER_0_TINT34,
-        },
-        {
-                .base           = TNETV107X_TIMER1_BASE,
-                .bottom_irq     = IRQ_TNETV107X_TIMER_1_TINT12,
-                .top_irq        = IRQ_TNETV107X_TIMER_1_TINT34,
-        },
-};
-static struct davinci_timer_info timer_info = {
-        .timers         = timer_instance,
-        .clockevent_id  = T0_BOT,
-        .clocksource_id = T0_TOP,
-};
-/*
- * TNETV107X platforms do not use the static mappings from Davinci
- * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses,
- * and changing IO_PHYS would break away from existing Davinci SOCs.
- *
- * The primary impact of the current model is that IO_ADDRESS() is not to be
- * used to map registers on TNETV107X.
- *
- * 1.   The first chunk is for INTC:  This needs to be mapped in via iotable
- *      because ioremap() does not seem to be operational at the time when
- *      irqs are initialized.  Without this, consistent dma init bombs.
- *
- * 2.   The second chunk maps in register areas that need to be populated into
- *      davinci_soc_info.  Note that alignment restrictions come into play if
- *      low-level debug is enabled (see note in <mach/tnetv107x.h>).
- */
-static struct map_desc io_desc[] = {
-        {       /* INTC */
-                .virtual        = IO_VIRT,
-                .pfn            = __phys_to_pfn(TNETV107X_INTC_BASE),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE
-        },
-        {       /* Most of the rest */
-                .virtual        = TNETV107X_IO_VIRT,
-                .pfn            = __phys_to_pfn(TNETV107X_IO_BASE),
-                .length         = IO_SIZE - SZ_1M,
-                .type           = MT_DEVICE
-        },
-};
-static unsigned long clk_sspll_recalc(struct clk *clk)
-{
-        int             pll;
-        unsigned long   mult = 0, prediv = 1, postdiv = 1;
-        unsigned long   ref = OSC_FREQ_ONCHIP, ret;
-        u32             tmp;
-        if (WARN_ON(!clk->pll_data))
-                return clk->rate;
-        if (!clk_ctrl_regs) {
-                void __iomem *tmp;
-                tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K);
-                if (WARN(!tmp, "failed ioremap for clock control regs\n"))
-                        return clk->parent ? clk->parent->rate : 0;
-                for (pll = 0; pll < N_PLLS; pll++)
-                        sspll_regs[pll] = tmp + sspll_regs_base[pll];
-                clk_ctrl_regs = tmp;
-        }
-        pll = clk->pll_data->num;
-        tmp = __raw_readl(&clk_ctrl_regs->pll_bypass);
-        if (!(tmp & bypass_mask[pll])) {
-                mult    = __raw_readl(&sspll_regs[pll]->mult_factor);
-                prediv  = __raw_readl(&sspll_regs[pll]->pre_div) + 1;
-                postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1;
-        }
-        tmp = __raw_readl(clk->pll_data->base + PLLCTL);
-        if (tmp & PLLCTL_CLKMODE)
-                ref = pll_ext_freq[pll];
-        clk->pll_data->input_rate = ref;
-        tmp = __raw_readl(clk->pll_data->base + PLLCTL);
-        if (!(tmp & PLLCTL_PLLEN))
-                return ref;
-        ret = ref;
-        if (mult)
-                ret += ((unsigned long long)ref * mult) / 256;
-        ret /= (prediv * postdiv);
-        return ret;
-}
-static void tnetv107x_watchdog_reset(struct platform_device *pdev)
-{
-        struct wdt_regs __iomem *regs;
-        regs = ioremap(pdev->resource[0].start, SZ_4K);
-        /* disable watchdog */
-        __raw_writel(0x7777, &regs->disable_lock);
-        __raw_writel(0xcccc, &regs->disable_lock);
-        __raw_writel(0xdddd, &regs->disable_lock);
-        __raw_writel(0, &regs->disable);
-        /* program prescale */
-        __raw_writel(0x5a5a, &regs->prescale_lock);
-        __raw_writel(0xa5a5, &regs->prescale_lock);
-        __raw_writel(0, &regs->prescale);
-        /* program countdown */
-        __raw_writel(0x6666, &regs->change_lock);
-        __raw_writel(0xbbbb, &regs->change_lock);
-        __raw_writel(1, &regs->change);
-        /* enable watchdog */
-        __raw_writel(0x7777, &regs->disable_lock);
-        __raw_writel(0xcccc, &regs->disable_lock);
-        __raw_writel(0xdddd, &regs->disable_lock);
-        __raw_writel(1, &regs->disable);
-        /* kick */
-        __raw_writel(0x5555, &regs->kick_lock);
-        __raw_writel(0xaaaa, &regs->kick_lock);
-        __raw_writel(1, &regs->kick);
-}
-void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
-{
-        tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
-}
-static struct davinci_soc_info tnetv107x_soc_info = {
-        .io_desc                = io_desc,
-        .io_desc_num            = ARRAY_SIZE(io_desc),
-        .ids                    = ids,
-        .ids_num                = ARRAY_SIZE(ids),
-        .jtag_id_reg            = TNETV107X_CHIP_CFG_BASE + 0x018,
-        .cpu_clks               = clks,
-        .psc_bases              = psc_regs,
-        .psc_bases_num          = ARRAY_SIZE(psc_regs),
-        .pinmux_base            = TNETV107X_CHIP_CFG_BASE + 0x150,
-        .pinmux_pins            = pins,
-        .pinmux_pins_num        = ARRAY_SIZE(pins),
-        .intc_type              = DAVINCI_INTC_TYPE_CP_INTC,
-        .intc_base              = TNETV107X_INTC_BASE,
-        .intc_irq_prios         = irq_prios,
-        .intc_irq_num           = TNETV107X_N_CP_INTC_IRQ,
-        .intc_host_map          = intc_host_map,
-        .gpio_base              = TNETV107X_GPIO_BASE,
-        .gpio_type              = GPIO_TYPE_TNETV107X,
-        .gpio_num               = TNETV107X_N_GPIO,
-        .timer_info             = &timer_info,
-        .serial_dev             = tnetv107x_serial_device,
-};
-void __init tnetv107x_init(void)
-{
-        davinci_common_init(&tnetv107x_soc_info);
-}
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 0bc7cdf8cf46..d8c439c89ea9 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -20,18 +20,6 @@ config MACH_CM_A510
          Say 'Y' here if you want your kernel to support the
          CompuLab CM-A510 Board.
-config MACH_DOVE_DT
-        bool "Marvell Dove Flattened Device Tree"
-        select DOVE_CLK
-        select ORION_IRQCHIP
-        select ORION_TIMER
-        select REGULATOR
-        select REGULATOR_FIXED_VOLTAGE
-        select USE_OF
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell Dove using flattened device tree.
 endmenu
 endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index cbc5c0618788..b608a21919fb 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -2,5 +2,4 @@ obj-y				+= common.o
 obj-$(CONFIG_DOVE_LEGACY)       += irq.o mpp.o
 obj-$(CONFIG_PCI)               += pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
-obj-$(CONFIG_MACH_DOVE_DT)      += board-dt.o
 obj-$(CONFIG_MACH_CM_A510)      += cm-a510.o
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index 5362df3df89f..f4a5b34489b7 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -21,6 +21,7 @@
 #define  CPU_CTRL_PCIE1_LINK    0x00000008
 #define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
+#define RSTOUTn_MASK_PHYS       (BRIDGE_PHYS_BASE + 0x0108)
 #define  SOFT_RESET_OUT_EN      0x00000004
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
diff --git a/arch/arm/mach-dove/include/mach/timex.h b/arch/arm/mach-dove/include/mach/timex.h
deleted file mode 100644
index 251d538541db..000000000000
--- a/arch/arm/mach-dove/include/mach/timex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/timex.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 68ac934d4565..8254e716b095 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -206,7 +206,7 @@ ebsa110_timer_interrupt(int irq, void *dev_id)
 static struct irqaction ebsa110_timer_irq = {
        .name           = "EBSA110 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = ebsa110_timer_interrupt,
 };
diff --git a/arch/arm/mach-ebsa110/include/mach/timex.h b/arch/arm/mach-ebsa110/include/mach/timex.h
deleted file mode 100644
index 4fb43b22a102..000000000000
--- a/arch/arm/mach-ebsa110/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  arch/arm/mach-ebsa110/include/mach/timex.h
- *
- *  Copyright (C) 1997, 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  EBSA110 architecture timex specifications
- */
-/*
- * On the EBSA, the clock ticks at weird rates.
- * This is therefore not used to calculate the
- * divisor.
- */
-#define CLOCK_TICK_RATE         47894000
diff --git a/arch/arm/mach-efm32/include/mach/entry-macro.S b/arch/arm/mach-efm32/include/mach/entry-macro.S
deleted file mode 100644
index 322159d5ed91..000000000000
--- a/arch/arm/mach-efm32/include/mach/entry-macro.S
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * Empty file waiting for deletion once <mach/entry-macro.S> isn't needed any
- * more. Patch "ARM: v7-M: drop using mach/entry-macro.S" sitting in next.
- */
diff --git a/arch/arm/mach-efm32/include/mach/timex.h b/arch/arm/mach-efm32/include/mach/timex.h
deleted file mode 100644
index 7a8b26da6599..000000000000
--- a/arch/arm/mach-efm32/include/mach/timex.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * Empty file waiting for deletion once <mach/timex.h> isn't needed any more.
- */
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 157ba88433c9..0e571f1749d6 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -117,7 +117,7 @@ void __init ep93xx_map_io(void)
 #define EP93XX_TIMER4_CLOCK             983040
 #define TIMER1_RELOAD                   ((EP93XX_TIMER123_CLOCK / HZ) - 1)
-#define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
+#define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(EP93XX_TIMER4_CLOCK, HZ)
 static unsigned int last_jiffy_time;
@@ -242,6 +242,7 @@ unsigned int ep93xx_chip_revision(void)
        v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
        return v;
 }
+EXPORT_SYMBOL_GPL(ep93xx_chip_revision);
 /*************************************************************************
 * EP93xx GPIO
diff --git a/arch/arm/mach-ep93xx/include/mach/timex.h b/arch/arm/mach-ep93xx/include/mach/timex.h
deleted file mode 100644
index 6b3503b01fa6..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/timex.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/timex.h
- */
-#define CLOCK_TICK_RATE         983040
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c414af75ef0..fc8bf18e222d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -24,7 +24,7 @@ config ARCH_EXYNOS4
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
-        select PM_GENERIC_DOMAINS if PM
+        select PM_GENERIC_DOMAINS if PM_RUNTIME
        select S5P_DEV_MFC
        help
          Samsung EXYNOS4 SoCs based systems
@@ -36,7 +36,6 @@ config ARCH_EXYNOS5
        select HAVE_ARM_SCU if SMP
        select HAVE_SMP
        select PINCTRL
-        select USB_ARCH_HAS_XHCI
        help
          Samsung EXYNOS5 (Cortex-A15) SoC based systems
@@ -47,10 +46,8 @@ config CPU_EXYNOS4210
        default y
        depends on ARCH_EXYNOS4
        select ARCH_HAS_BANDGAP
-        select ARM_CPU_SUSPEND if PM
+        select ARM_CPU_SUSPEND if PM_SLEEP
        select PINCTRL_EXYNOS
-        select S5P_PM if PM
-        select S5P_SLEEP if PM
        select SAMSUNG_DMADEV
        help
          Enable EXYNOS4210 CPU support
@@ -61,8 +58,6 @@ config SOC_EXYNOS4212
        depends on ARCH_EXYNOS4
        select ARCH_HAS_BANDGAP
        select PINCTRL_EXYNOS
-        select S5P_PM if PM
-        select S5P_SLEEP if PM
        select SAMSUNG_DMADEV
        help
          Enable EXYNOS4212 SoC support
@@ -83,9 +78,7 @@ config SOC_EXYNOS5250
        depends on ARCH_EXYNOS5
        select ARCH_HAS_BANDGAP
        select PINCTRL_EXYNOS
-        select PM_GENERIC_DOMAINS if PM
+        select PM_GENERIC_DOMAINS if PM_RUNTIME
-        select S5P_PM if PM
-        select S5P_SLEEP if PM
        select S5P_DEV_MFC
        select SAMSUNG_DMADEV
        help
@@ -95,9 +88,7 @@ config SOC_EXYNOS5420
        bool "SAMSUNG EXYNOS5420"
        default y
        depends on ARCH_EXYNOS5
-        select PM_GENERIC_DOMAINS if PM
+        select PM_GENERIC_DOMAINS if PM_RUNTIME
-        select S5P_PM if PM
-        select S5P_SLEEP if PM
        help
          Enable EXYNOS5420 SoC support
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8930b66b4abd..a656dbe3b78c 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,9 +12,9 @@ obj-				:=
 # Core
-obj-$(CONFIG_ARCH_EXYNOS)       += common.o
+obj-$(CONFIG_ARCH_EXYNOS)       += exynos.o
-obj-$(CONFIG_S5P_PM)            += pm.o
+obj-$(CONFIG_PM_SLEEP)          += pm.o sleep.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
@@ -29,8 +29,3 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= firmware.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o             :=-Wa,-march=armv7-a$(plus_sec)
-# machine support
-obj-$(CONFIG_ARCH_EXYNOS4)      += mach-exynos4-dt.o
-obj-$(CONFIG_ARCH_EXYNOS5)      += mach-exynos5-dt.o
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index f76967b1c551..9ef3f83efaff 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -19,14 +19,27 @@ void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
 struct map_desc;
 void exynos_init_io(void);
-void exynos4_restart(enum reboot_mode mode, const char *cmd);
+void exynos_restart(enum reboot_mode mode, const char *cmd);
-void exynos5_restart(enum reboot_mode mode, const char *cmd);
 void exynos_cpuidle_init(void);
 void exynos_cpufreq_init(void);
 void exynos_init_late(void);
 void exynos_firmware_init(void);
+#ifdef CONFIG_PINCTRL_EXYNOS
+extern u32 exynos_get_eint_wake_mask(void);
+#else
+static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
+#endif
+#ifdef CONFIG_PM_SLEEP
+extern void __init exynos_pm_init(void);
+#else
+static inline void exynos_pm_init(void) {}
+#endif
+extern void exynos_cpu_resume(void);
 extern struct smp_operations exynos_smp_ops;
 extern void exynos_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index f57cb91f02aa..c57cae0e8779 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -14,6 +14,7 @@
 #include <linux/cpu_pm.h>
 #include <linux/io.h>
 #include <linux/export.h>
+#include <linux/module.h>
 #include <linux/time.h>
 #include <linux/platform_device.h>
@@ -26,7 +27,6 @@
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <mach/pm-core.h>
 #include <mach/map.h>
 #include "common.h"
@@ -127,7 +127,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
        /* Set value of power down register for aftr mode */
        exynos_sys_powerdown_conf(SYS_AFTR);
-        __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+        __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
        __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
        save_cpu_arch_register();
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/exynos.c
index f18be40e5b21..b32a907d021d 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -1,105 +1,40 @@
 /*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * SAMSUNG EXYNOS Flattened Device Tree enabled machine
- *              http://www.samsung.com
 *
- * Common Codes for EXYNOS
+ * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <linux/kernel.h>
+#include <linux/init.h>
-#include <linux/bitops.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqchip.h>
 #include <linux/io.h>
-#include <linux/device.h>
+#include <linux/kernel.h>
-#include <linux/gpio.h>
+#include <linux/serial_s3c.h>
-#include <clocksource/samsung_pwm.h>
-#include <linux/sched.h>
-#include <linux/serial_core.h>
 #include <linux/of.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/pm_domain.h>
-#include <linux/export.h>
-#include <linux/irqdomain.h>
 #include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
+#include <linux/of_fdt.h>
-#include <linux/irqchip/chained_irq.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/pm_domain.h>
-#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
-#include <asm/exception.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <asm/memory.h>
-#include <asm/cacheflush.h>
 #include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/regs-serial.h>
 #include "common.h"
+#include "mfc.h"
 #include "regs-pmu.h"
 #define L2_AUX_VAL 0x7C470001
 #define L2_AUX_MASK 0xC200ffff
-static const char name_exynos4210[] = "EXYNOS4210";
-static const char name_exynos4212[] = "EXYNOS4212";
-static const char name_exynos4412[] = "EXYNOS4412";
-static const char name_exynos5250[] = "EXYNOS5250";
-static const char name_exynos5420[] = "EXYNOS5420";
-static const char name_exynos5440[] = "EXYNOS5440";
-static void exynos4_map_io(void);
-static void exynos5_map_io(void);
-static int exynos_init(void);
-static struct cpu_table cpu_ids[] __initdata = {
-        {
-                .idcode         = EXYNOS4210_CPU_ID,
-                .idmask         = EXYNOS4_CPU_MASK,
-                .map_io         = exynos4_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos4210,
-        }, {
-                .idcode         = EXYNOS4212_CPU_ID,
-                .idmask         = EXYNOS4_CPU_MASK,
-                .map_io         = exynos4_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos4212,
-        }, {
-                .idcode         = EXYNOS4412_CPU_ID,
-                .idmask         = EXYNOS4_CPU_MASK,
-                .map_io         = exynos4_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos4412,
-        }, {
-                .idcode         = EXYNOS5250_SOC_ID,
-                .idmask         = EXYNOS5_SOC_MASK,
-                .map_io         = exynos5_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos5250,
-        }, {
-                .idcode         = EXYNOS5420_SOC_ID,
-                .idmask         = EXYNOS5_SOC_MASK,
-                .map_io         = exynos5_map_io,
-                .init           = exynos_init,
-                .name           = name_exynos5420,
-        }, {
-                .idcode         = EXYNOS5440_SOC_ID,
-                .idmask         = EXYNOS5_SOC_MASK,
-                .init           = exynos_init,
-                .name           = name_exynos5440,
-        },
-};
-/* Initial IO mappings */
 static struct map_desc exynos4_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S3C_VA_SYS,
@@ -263,19 +198,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
        },
 };
-void exynos4_restart(enum reboot_mode mode, const char *cmd)
+void exynos_restart(enum reboot_mode mode, const char *cmd)
-{
-        __raw_writel(0x1, S5P_SWRESET);
-}
-void exynos5_restart(enum reboot_mode mode, const char *cmd)
 {
        struct device_node *np;
-        u32 val;
+        u32 val = 0x1;
-        void __iomem *addr;
+        void __iomem *addr = EXYNOS_SWRESET;
-        val = 0x1;
-        addr = EXYNOS_SWRESET;
        if (of_machine_is_compatible("samsung,exynos5440")) {
                u32 status;
@@ -315,6 +242,7 @@ void __init exynos_init_late(void)
                return;
        pm_genpd_poweroff_unused();
+        exynos_pm_init();
 }
 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
@@ -345,6 +273,28 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 *
 * register the standard cpu IO areas
 */
+static void __init exynos_map_io(void)
+{
+        if (soc_is_exynos4())
+                iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
+        if (soc_is_exynos5())
+                iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+        if (soc_is_exynos4210()) {
+                if (samsung_rev() == EXYNOS4210_REV_0)
+                        iotable_init(exynos4_iodesc0,
+                                                ARRAY_SIZE(exynos4_iodesc0));
+                else
+                        iotable_init(exynos4_iodesc1,
+                                                ARRAY_SIZE(exynos4_iodesc1));
+                iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
+        }
+        if (soc_is_exynos4212() || soc_is_exynos4412())
+                iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
+        if (soc_is_exynos5250())
+                iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+}
 void __init exynos_init_io(void)
 {
@@ -355,30 +305,7 @@ void __init exynos_init_io(void)
        /* detect cpu id and rev. */
        s5p_init_cpu(S5P_VA_CHIPID);
-        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+        exynos_map_io();
-}
-static void __init exynos4_map_io(void)
-{
-        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
-        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
-                iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
-        else
-                iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
-        if (soc_is_exynos4210())
-                iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
-        if (soc_is_exynos4212() || soc_is_exynos4412())
-                iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
-}
-static void __init exynos5_map_io(void)
-{
-        iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
-        if (soc_is_exynos5250())
-                iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 }
 struct bus_type exynos_subsys = {
@@ -386,10 +313,6 @@ struct bus_type exynos_subsys = {
        .dev_name       = "exynos-core",
 };
-static struct device exynos4_dev = {
-        .bus    = &exynos_subsys,
-};
 static int __init exynos_core_init(void)
 {
        return subsys_system_register(&exynos_subsys, NULL);
@@ -404,15 +327,85 @@ static int __init exynos4_l2x0_cache_init(void)
        if (ret)
                return ret;
-        l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+        if (IS_ENABLED(CONFIG_S5P_SLEEP)) {
-        clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+        }
        return 0;
 }
 early_initcall(exynos4_l2x0_cache_init);
-static int __init exynos_init(void)
+static void __init exynos_dt_machine_init(void)
 {
-        printk(KERN_INFO "EXYNOS: Initializing architecture\n");
+        struct device_node *i2c_np;
+        const char *i2c_compat = "samsung,s3c2440-i2c";
+        unsigned int tmp;
+        int id;
+        /*
+         * Exynos5's legacy i2c controller and new high speed i2c
+         * controller have muxed interrupt sources. By default the
+         * interrupts for 4-channel HS-I2C controller are enabled.
+         * If node for first four channels of legacy i2c controller
+         * are available then re-configure the interrupts via the
+         * system register.
+         */
+        if (soc_is_exynos5()) {
+                for_each_compatible_node(i2c_np, NULL, i2c_compat) {
+                        if (of_device_is_available(i2c_np)) {
+                                id = of_alias_get_id(i2c_np, "i2c");
+                                if (id < 4) {
+                                        tmp = readl(EXYNOS5_SYS_I2C_CFG);
+                                        writel(tmp & ~(0x1 << id),
+                                                        EXYNOS5_SYS_I2C_CFG);
+                                }
+                        }
+                }
+        }
-        return device_register(&exynos4_dev);
+        exynos_cpuidle_init();
+        exynos_cpufreq_init();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
+static char const *exynos_dt_compat[] __initconst = {
+        "samsung,exynos4",
+        "samsung,exynos4210",
+        "samsung,exynos4212",
+        "samsung,exynos4412",
+        "samsung,exynos5",
+        "samsung,exynos5250",
+        "samsung,exynos5420",
+        "samsung,exynos5440",
+        NULL
+};
+static void __init exynos_reserve(void)
+{
+#ifdef CONFIG_S5P_DEV_MFC
+        int i;
+        char *mfc_mem[] = {
+                "samsung,mfc-v5",
+                "samsung,mfc-v6",
+                "samsung,mfc-v7",
+        };
+        for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
+                if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
+                        break;
+#endif
+}
+DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
+        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .smp            = smp_ops(exynos_smp_ops),
+        .map_io         = exynos_init_io,
+        .init_early     = exynos_firmware_init,
+        .init_machine   = exynos_dt_machine_init,
+        .init_late      = exynos_init_late,
+        .dt_compat      = exynos_dt_compat,
+        .restart        = exynos_restart,
+        .reserve        = exynos_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/include/mach/hardware.h b/arch/arm/mach-exynos/include/mach/hardware.h
deleted file mode 100644
index 5109eb232f23..000000000000
--- a/arch/arm/mach-exynos/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Hardware support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H __FILE__
-/* currently nothing here, placeholder */
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
deleted file mode 100644
index dc0697c2fa92..000000000000
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_PM_CORE_H
-#define __ASM_ARCH_PM_CORE_H __FILE__
-#include <linux/of.h>
-#include <mach/map.h>
-#define S5P_EINT_WAKEUP_MASK                    (S5P_VA_PMU + 0x0604)
-#define S5P_WAKEUP_MASK                         (S5P_VA_PMU + 0x0608)
-#ifdef CONFIG_PINCTRL_EXYNOS
-extern u32 exynos_get_eint_wake_mask(void);
-#else
-static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
-#endif
-static inline void s3c_pm_debug_init_uart(void)
-{
-        /* nothing here yet */
-}
-static inline void s3c_pm_arch_prepare_irqs(void)
-{
-        __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
-        __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
-}
-static inline void s3c_pm_arch_stop_clocks(void)
-{
-        /* nothing here yet */
-}
-static inline void s3c_pm_arch_show_resume_irqs(void)
-{
-        /* nothing here yet */
-}
-static inline void s3c_pm_arch_update_uart(void __iomem *regs,
-                                           struct pm_uart_save *save)
-{
-        /* nothing here yet */
-}
-static inline void s3c_pm_restored_gpios(void)
-{
-        /* nothing here yet */
-}
-static inline void samsung_pm_saved_gpios(void)
-{
-        /* nothing here yet */
-}
-/* Compatibility definitions to make plat-samsung/pm.c compile */
-#define IRQ_EINT_BIT(x)         1
-#define s3c_irqwake_intallow    0
-#define s3c_irqwake_eintallow   0
-#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/include/mach/timex.h b/arch/arm/mach-exynos/include/mach/timex.h
deleted file mode 100644
index 6d138750a708..000000000000
--- a/arch/arm/mach-exynos/include/mach/timex.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/timex.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (c) 2003-2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Based on arch/arm/mach-s5p6442/include/mach/timex.h
- *
- * EXYNOS4 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H __FILE__
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-#define CLOCK_TICK_RATE 12000000
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
deleted file mode 100644
index 5d7ce36be46f..000000000000
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H __FILE__
-#include <asm/mach-types.h>
-#include <mach/map.h>
-#include <plat/uncompress.h>
-static unsigned int __raw_readl(unsigned int ptr)
-{
-        return *((volatile unsigned int *)ptr);
-}
-static void arch_detect_cpu(void)
-{
-        u32 chip_id = __raw_readl(EXYNOS_PA_CHIPID);
-        /*
-         * product_id is bits 31:12
-         * bits 23:20 describe the exynosX family
-         * bits 27:24 describe the exynosX family in exynos5420
-         */
-        chip_id >>= 20;
-        if ((chip_id & 0x0f) == 0x5 || (chip_id & 0xf0) == 0x50)
-                uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
-        else
-                uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
-        /*
-         * For preventing FIFO overrun or infinite loop of UART console,
-         * fifo_max should be the minimum fifo size of all of the UART channels
-         */
-        fifo_mask = S5PV210_UFSTAT_TXMASK;
-        fifo_max = 15 << S5PV210_UFSTAT_TXSHIFT;
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
deleted file mode 100644
index d3e54b7644d7..000000000000
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Samsung's EXYNOS4 flattened device tree enabled machine
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- * Copyright (c) 2010-2011 Linaro Ltd.
- *              www.linaro.org
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/of_platform.h>
-#include <linux/of_fdt.h>
-#include <asm/mach/arch.h>
-#include <plat/mfc.h>
-#include "common.h"
-static void __init exynos4_dt_machine_init(void)
-{
-        exynos_cpuidle_init();
-        exynos_cpufreq_init();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static char const *exynos4_dt_compat[] __initdata = {
-        "samsung,exynos4210",
-        "samsung,exynos4212",
-        "samsung,exynos4412",
-        NULL
-};
-static void __init exynos4_reserve(void)
-{
-#ifdef CONFIG_S5P_DEV_MFC
-        struct s5p_mfc_dt_meminfo mfc_mem;
-        /* Reserve memory for MFC only if it's available */
-        mfc_mem.compatible = "samsung,mfc-v5";
-        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
-                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
-                                mfc_mem.lsize);
-#endif
-}
-DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
-        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
-        .smp            = smp_ops(exynos_smp_ops),
-        .map_io         = exynos_init_io,
-        .init_early     = exynos_firmware_init,
-        .init_machine   = exynos4_dt_machine_init,
-        .init_late      = exynos_init_late,
-        .dt_compat      = exynos4_dt_compat,
-        .restart        = exynos4_restart,
-        .reserve        = exynos4_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
deleted file mode 100644
index 37ea261f0f6c..000000000000
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/of_platform.h>
-#include <linux/of_fdt.h>
-#include <linux/io.h>
-#include <asm/mach/arch.h>
-#include <plat/mfc.h>
-#include "common.h"
-#include "regs-pmu.h"
-static void __init exynos5_dt_machine_init(void)
-{
-        struct device_node *i2c_np;
-        const char *i2c_compat = "samsung,s3c2440-i2c";
-        unsigned int tmp;
-        /*
-         * Exynos5's legacy i2c controller and new high speed i2c
-         * controller have muxed interrupt sources. By default the
-         * interrupts for 4-channel HS-I2C controller are enabled.
-         * If node for first four channels of legacy i2c controller
-         * are available then re-configure the interrupts via the
-         * system register.
-         */
-        for_each_compatible_node(i2c_np, NULL, i2c_compat) {
-                if (of_device_is_available(i2c_np)) {
-                        if (of_alias_get_id(i2c_np, "i2c") < 4) {
-                                tmp = readl(EXYNOS5_SYS_I2C_CFG);
-                                writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")),
-                                                EXYNOS5_SYS_I2C_CFG);
-                        }
-                }
-        }
-        exynos_cpuidle_init();
-        exynos_cpufreq_init();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static char const *exynos5_dt_compat[] __initdata = {
-        "samsung,exynos5250",
-        "samsung,exynos5420",
-        "samsung,exynos5440",
-        NULL
-};
-static void __init exynos5_reserve(void)
-{
-#ifdef CONFIG_S5P_DEV_MFC
-        struct s5p_mfc_dt_meminfo mfc_mem;
-        /* Reserve memory for MFC only if it's available */
-        mfc_mem.compatible = "samsung,mfc-v6";
-        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
-                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
-                                mfc_mem.lsize);
-#endif
-}
-DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .smp            = smp_ops(exynos_smp_ops),
-        .map_io         = exynos_init_io,
-        .init_machine   = exynos5_dt_machine_init,
-        .init_late      = exynos_init_late,
-        .dt_compat      = exynos5_dt_compat,
-        .restart        = exynos5_restart,
-        .reserve        = exynos5_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mfc.h b/arch/arm/mach-exynos/mfc.h
new file mode 100644
index 000000000000..dec93cd5b3c6
--- /dev/null
+++ b/arch/arm/mach-exynos/mfc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __MACH_EXYNOS_MFC_H
+#define __MACH_EXYNOS_MFC_H __FILE__
+int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
+                                int depth, void *data);
+#endif /* __MACH_EXYNOS_MFC_H */
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f63fed9..03e5e9f94705 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -26,8 +26,6 @@
 #include <asm/smp_scu.h>
 #include <asm/firmware.h>
-#include <mach/hardware.h>
 #include <plat/cpu.h>
 #include "common.h"
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e00025bbbe89..15af0ceb0a66 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -17,72 +17,33 @@
 #include <linux/suspend.h>
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/smp_scu.h>
+#include <asm/suspend.h>
 #include <plat/cpu.h>
-#include <plat/pm.h>
+#include <plat/pm-common.h>
 #include <plat/pll.h>
 #include <plat/regs-srom.h>
 #include <mach/map.h>
-#include <mach/pm-core.h>
 #include "common.h"
 #include "regs-pmu.h"
-#define EXYNOS4_EPLL_LOCK                       (S5P_VA_CMU + 0x0C010)
+/**
-#define EXYNOS4_VPLL_LOCK                       (S5P_VA_CMU + 0x0C020)
+ * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
+ * @hwirq: Hardware IRQ signal of the GIC
-#define EXYNOS4_EPLL_CON0                       (S5P_VA_CMU + 0x0C110)
+ * @mask: Mask in PMU wake-up mask register
-#define EXYNOS4_EPLL_CON1                       (S5P_VA_CMU + 0x0C114)
+ */
-#define EXYNOS4_VPLL_CON0                       (S5P_VA_CMU + 0x0C120)
+struct exynos_wkup_irq {
-#define EXYNOS4_VPLL_CON1                       (S5P_VA_CMU + 0x0C124)
+        unsigned int hwirq;
+        u32 mask;
-#define EXYNOS4_CLKSRC_MASK_TOP                 (S5P_VA_CMU + 0x0C310)
-#define EXYNOS4_CLKSRC_MASK_CAM                 (S5P_VA_CMU + 0x0C320)
-#define EXYNOS4_CLKSRC_MASK_TV                  (S5P_VA_CMU + 0x0C324)
-#define EXYNOS4_CLKSRC_MASK_LCD0                (S5P_VA_CMU + 0x0C334)
-#define EXYNOS4_CLKSRC_MASK_MAUDIO              (S5P_VA_CMU + 0x0C33C)
-#define EXYNOS4_CLKSRC_MASK_FSYS                (S5P_VA_CMU + 0x0C340)
-#define EXYNOS4_CLKSRC_MASK_PERIL0              (S5P_VA_CMU + 0x0C350)
-#define EXYNOS4_CLKSRC_MASK_PERIL1              (S5P_VA_CMU + 0x0C354)
-#define EXYNOS4_CLKSRC_MASK_DMC                 (S5P_VA_CMU + 0x10300)
-#define EXYNOS4_EPLLCON0_LOCKED_SHIFT           (29)
-#define EXYNOS4_VPLLCON0_LOCKED_SHIFT           (29)
-#define EXYNOS4210_CLKSRC_MASK_LCD1             (S5P_VA_CMU + 0x0C338)
-static const struct sleep_save exynos4_set_clksrc[] = {
-        { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
-        { .reg = EXYNOS4_CLKSRC_MASK_CAM                , .val = 0x11111111, },
-        { .reg = EXYNOS4_CLKSRC_MASK_TV                 , .val = 0x00000111, },
-        { .reg = EXYNOS4_CLKSRC_MASK_LCD0               , .val = 0x00001111, },
-        { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO             , .val = 0x00000001, },
-        { .reg = EXYNOS4_CLKSRC_MASK_FSYS               , .val = 0x01011111, },
-        { .reg = EXYNOS4_CLKSRC_MASK_PERIL0             , .val = 0x01111111, },
-        { .reg = EXYNOS4_CLKSRC_MASK_PERIL1             , .val = 0x01110111, },
-        { .reg = EXYNOS4_CLKSRC_MASK_DMC                , .val = 0x00010000, },
-};
-static const struct sleep_save exynos4210_set_clksrc[] = {
-        { .reg = EXYNOS4210_CLKSRC_MASK_LCD1            , .val = 0x00001111, },
-};
-static struct sleep_save exynos4_epll_save[] = {
-        SAVE_ITEM(EXYNOS4_EPLL_CON0),
-        SAVE_ITEM(EXYNOS4_EPLL_CON1),
-};
-static struct sleep_save exynos4_vpll_save[] = {
-        SAVE_ITEM(EXYNOS4_VPLL_CON0),
-        SAVE_ITEM(EXYNOS4_VPLL_CON1),
 };
 static struct sleep_save exynos5_sys_save[] = {
@@ -98,6 +59,46 @@ static struct sleep_save exynos_core_save[] = {
        SAVE_ITEM(S5P_SROM_BC3),
 };
+/*
+ * GIC wake-up support
+ */
+static u32 exynos_irqwake_intmask = 0xffffffff;
+static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
+        { 76, BIT(1) }, /* RTC alarm */
+        { 77, BIT(2) }, /* RTC tick */
+        { /* sentinel */ },
+};
+static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
+        { 75, BIT(1) }, /* RTC alarm */
+        { 76, BIT(2) }, /* RTC tick */
+        { /* sentinel */ },
+};
+static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
+{
+        const struct exynos_wkup_irq *wkup_irq;
+        if (soc_is_exynos5250())
+                wkup_irq = exynos5250_wkup_irq;
+        else
+                wkup_irq = exynos4_wkup_irq;
+        while (wkup_irq->mask) {
+                if (wkup_irq->hwirq == data->hwirq) {
+                        if (!state)
+                                exynos_irqwake_intmask |= wkup_irq->mask;
+                        else
+                                exynos_irqwake_intmask &= ~wkup_irq->mask;
+                        return 0;
+                }
+                ++wkup_irq;
+        }
+        return -ENOENT;
+}
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
@@ -122,12 +123,13 @@ static void exynos_pm_prepare(void)
 {
        unsigned int tmp;
+        /* Set wake-up mask registers */
+        __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+        __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
        s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-        if (!soc_is_exynos5250()) {
+        if (soc_is_exynos5250()) {
-                s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
-                s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
-        } else {
                s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
                /* Disable USE_RETENTION of JPEG_MEM_OPTION */
                tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
@@ -142,127 +144,8 @@ static void exynos_pm_prepare(void)
        /* ensure at least INFORM0 has the resume address */
-        __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
+        __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
-        /* Before enter central sequence mode, clock src register have to set */
-        if (!soc_is_exynos5250())
-                s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
-        if (soc_is_exynos4210())
-                s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
-}
-static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
-{
-        pm_cpu_prep = exynos_pm_prepare;
-        pm_cpu_sleep = exynos_cpu_suspend;
-        return 0;
-}
-static unsigned long pll_base_rate;
-static void exynos4_restore_pll(void)
-{
-        unsigned long pll_con, locktime, lockcnt;
-        unsigned long pll_in_rate;
-        unsigned int p_div, epll_wait = 0, vpll_wait = 0;
-        if (pll_base_rate == 0)
-                return;
-        pll_in_rate = pll_base_rate;
-        /* EPLL */
-        pll_con = exynos4_epll_save[0].val;
-        if (pll_con & (1 << 31)) {
-                pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
-                p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
-                pll_in_rate /= 1000000;
-                locktime = (3000 / pll_in_rate) * p_div;
-                lockcnt = locktime * 10000 / (10000 / pll_in_rate);
-                __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
-                s3c_pm_do_restore_core(exynos4_epll_save,
-                                        ARRAY_SIZE(exynos4_epll_save));
-                epll_wait = 1;
-        }
-        pll_in_rate = pll_base_rate;
-        /* VPLL */
-        pll_con = exynos4_vpll_save[0].val;
-        if (pll_con & (1 << 31)) {
-                pll_in_rate /= 1000000;
-                /* 750us */
-                locktime = 750;
-                lockcnt = locktime * 10000 / (10000 / pll_in_rate);
-                __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
-                s3c_pm_do_restore_core(exynos4_vpll_save,
-                                        ARRAY_SIZE(exynos4_vpll_save));
-                vpll_wait = 1;
-        }
-        /* Wait PLL locking */
-        do {
-                if (epll_wait) {
-                        pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
-                        if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
-                                epll_wait = 0;
-                }
-                if (vpll_wait) {
-                        pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
-                        if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
-                                vpll_wait = 0;
-                }
-        } while (epll_wait || vpll_wait);
-}
-static struct subsys_interface exynos_pm_interface = {
-        .name           = "exynos_pm",
-        .subsys         = &exynos_subsys,
-        .add_dev        = exynos_pm_add,
-};
-static __init int exynos_pm_drvinit(void)
-{
-        struct clk *pll_base;
-        unsigned int tmp;
-        if (soc_is_exynos5440())
-                return 0;
-        s3c_pm_init();
-        /* All wakeup disable */
-        tmp = __raw_readl(S5P_WAKEUP_MASK);
-        tmp |= ((0xFF << 8) | (0x1F << 1));
-        __raw_writel(tmp, S5P_WAKEUP_MASK);
-        if (!soc_is_exynos5250()) {
-                pll_base = clk_get(NULL, "xtal");
-                if (!IS_ERR(pll_base)) {
-                        pll_base_rate = clk_get_rate(pll_base);
-                        clk_put(pll_base);
-                }
-        }
-        return subsys_interface_register(&exynos_pm_interface);
 }
-arch_initcall(exynos_pm_drvinit);
 static int exynos_pm_suspend(void)
 {
@@ -343,13 +226,8 @@ static void exynos_pm_resume(void)
        s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-        if (!soc_is_exynos5250()) {
+        if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
-                exynos4_restore_pll();
-#ifdef CONFIG_SMP
                scu_enable(S5P_VA_SCU);
-#endif
-        }
 early_wakeup:
@@ -364,12 +242,80 @@ static struct syscore_ops exynos_pm_syscore_ops = {
        .resume         = exynos_pm_resume,
 };
-static __init int exynos_pm_syscore_init(void)
+/*
+ * Suspend Ops
+ */
+static int exynos_suspend_enter(suspend_state_t state)
 {
-        if (soc_is_exynos5440())
+        int ret;
-                return 0;
+        s3c_pm_debug_init();
+        S3C_PMDBG("%s: suspending the system...\n", __func__);
+        S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
+                        exynos_irqwake_intmask, exynos_get_eint_wake_mask());
+        if (exynos_irqwake_intmask == -1U
+            && exynos_get_eint_wake_mask() == -1U) {
+                pr_err("%s: No wake-up sources!\n", __func__);
+                pr_err("%s: Aborting sleep\n", __func__);
+                return -EINVAL;
+        }
+        s3c_pm_save_uarts();
+        exynos_pm_prepare();
+        flush_cache_all();
+        s3c_pm_check_store();
+        ret = cpu_suspend(0, exynos_cpu_suspend);
+        if (ret)
+                return ret;
+        s3c_pm_restore_uarts();
+        S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
+                        __raw_readl(S5P_WAKEUP_STAT));
+        s3c_pm_check_restore();
+        S3C_PMDBG("%s: resuming the system...\n", __func__);
-        register_syscore_ops(&exynos_pm_syscore_ops);
        return 0;
 }
-arch_initcall(exynos_pm_syscore_init);
+static int exynos_suspend_prepare(void)
+{
+        s3c_pm_check_prepare();
+        return 0;
+}
+static void exynos_suspend_finish(void)
+{
+        s3c_pm_check_cleanup();
+}
+static const struct platform_suspend_ops exynos_suspend_ops = {
+        .enter          = exynos_suspend_enter,
+        .prepare        = exynos_suspend_prepare,
+        .finish         = exynos_suspend_finish,
+        .valid          = suspend_valid_only_mem,
+};
+void __init exynos_pm_init(void)
+{
+        u32 tmp;
+        /* Platform-specific GIC callback */
+        gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
+        /* All wakeup disable */
+        tmp = __raw_readl(S5P_WAKEUP_MASK);
+        tmp |= ((0xFF << 8) | (0x1F << 1));
+        __raw_writel(tmp, S5P_WAKEUP_MASK);
+        register_syscore_ops(&exynos_pm_syscore_ops);
+        suspend_set_ops(&exynos_suspend_ops);
+}
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 8fd24882f0b1..fe6570ebbdde 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -22,8 +22,6 @@
 #include <linux/of_platform.h>
 #include <linux/sched.h>
-#include <plat/devs.h>
 #include "regs-pmu.h"
 /*
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 7c029ce27711..4f6a2560d022 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -26,11 +26,12 @@
 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
-#define S5P_SWRESET                             S5P_PMUREG(0x0400)
 #define EXYNOS_SWRESET                          S5P_PMUREG(0x0400)
 #define EXYNOS5440_SWRESET                      S5P_PMUREG(0x00C4)
 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
+#define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
+#define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
 #define S5P_INFORM0                             S5P_PMUREG(0x0800)
 #define S5P_INFORM1                             S5P_PMUREG(0x0804)
diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
new file mode 100644
index 000000000000..a2613e944e10
--- /dev/null
+++ b/arch/arm/mach-exynos/sleep.S
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Exynos low-level resume code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+#define CPU_MASK        0xff0ffff0
+#define CPU_CORTEX_A9   0x410fc090
+        /*
+         * The following code is located into the .data section. This is to
+         * allow l2x0_regs_phys to be accessed with a relative load while we
+         * can't rely on any MMU translation. We could have put l2x0_regs_phys
+         * in the .text section as well, but some setups might insist on it to
+         * be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
+         */
+        .data
+        .align
+        /*
+         * sleep magic, to allow the bootloader to check for an valid
+         * image to resume to. Must be the first word before the
+         * exynos_cpu_resume entry.
+         */
+        .word   0x2bedf00d
+        /*
+         * exynos_cpu_resume
+         *
+         * resume code entry for bootloader to call
+         */
+ENTRY(exynos_cpu_resume)
+#ifdef CONFIG_CACHE_L2X0
+        mrc     p15, 0, r0, c0, c0, 0
+        ldr     r1, =CPU_MASK
+        and     r0, r0, r1
+        ldr     r1, =CPU_CORTEX_A9
+        cmp     r0, r1
+        bne     skip_l2_resume
+        adr     r0, l2x0_regs_phys
+        ldr     r0, [r0]
+        cmp     r0, #0
+        beq     skip_l2_resume
+        ldr     r1, [r0, #L2X0_R_PHY_BASE]
+        ldr     r2, [r1, #L2X0_CTRL]
+        tst     r2, #0x1
+        bne     skip_l2_resume
+        ldr     r2, [r0, #L2X0_R_AUX_CTRL]
+        str     r2, [r1, #L2X0_AUX_CTRL]
+        ldr     r2, [r0, #L2X0_R_TAG_LATENCY]
+        str     r2, [r1, #L2X0_TAG_LATENCY_CTRL]
+        ldr     r2, [r0, #L2X0_R_DATA_LATENCY]
+        str     r2, [r1, #L2X0_DATA_LATENCY_CTRL]
+        ldr     r2, [r0, #L2X0_R_PREFETCH_CTRL]
+        str     r2, [r1, #L2X0_PREFETCH_CTRL]
+        ldr     r2, [r0, #L2X0_R_PWR_CTRL]
+        str     r2, [r1, #L2X0_POWER_CTRL]
+        mov     r2, #1
+        str     r2, [r1, #L2X0_CTRL]
+skip_l2_resume:
+#endif
+        b       cpu_resume
+ENDPROC(exynos_cpu_resume)
+#ifdef CONFIG_CACHE_L2X0
+        .globl l2x0_regs_phys
+l2x0_regs_phys:
+        .long   0
+#endif
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
index fba55fb9f47d..07152d00fc50 100644
--- a/arch/arm/mach-footbridge/Kconfig
+++ b/arch/arm/mach-footbridge/Kconfig
@@ -52,6 +52,7 @@ config ARCH_EBSA285_HOST
        select FOOTBRIDGE_HOST
        select ISA
        select ISA_DMA
+        select ARCH_MAY_HAVE_PC_FDC
        select PCI
        help
          Say Y here if you intend to run this kernel on the EBSA285 card
@@ -94,6 +95,5 @@ config FOOTBRIDGE_ADDIN
 # EBSA285 board in either host or addin mode
 config ARCH_EBSA285
        bool
-        select ARCH_MAY_HAVE_PC_FDC
 endif
diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
index 0b64dd430d61..c3faa3bc84dd 100644
--- a/arch/arm/mach-footbridge/Makefile
+++ b/arch/arm/mach-footbridge/Makefile
@@ -4,11 +4,12 @@
 # Object file lists.
-obj-y                   := common.o dc21285.o dma.o isa-irq.o
+obj-y                   := common.o dma.o isa-irq.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
+pci-y                   += dc21285.o
 pci-$(CONFIG_ARCH_CATS) += cats-pci.o
 pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
 pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 9669cc0b6318..da0415094856 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -78,9 +78,11 @@ __initcall(cats_hw_init);
 static void __init
 fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 {
+#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
        screen_info.orig_video_lines  = 25;
        screen_info.orig_video_points = 16;
        screen_info.orig_y = 24;
+#endif
 }
 MACHINE_START(CATS, "Chalice-CATS")
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 3971104d32d4..bf7aa7d298e7 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -105,7 +105,7 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id)
 static struct irqaction footbridge_timer_irq = {
        .name           = "dc21285_timer1",
        .handler        = timer1_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .dev_id         = &ckevt_dc21285,
 };
@@ -125,7 +125,7 @@ void __init footbridge_timer_init(void)
        clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
 }
-static u32 notrace footbridge_read_sched_clock(void)
+static u64 notrace footbridge_read_sched_clock(void)
 {
        return ~*CSR_TIMER3_VALUE;
 }
@@ -138,5 +138,5 @@ void __init footbridge_sched_clock(void)
        *CSR_TIMER3_CLR = 0;
        *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
-        setup_sched_clock(footbridge_read_sched_clock, 24, rate);
+        sched_clock_register(footbridge_read_sched_clock, 24, rate);
 }
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 7c2fdae9a38b..96a3d73ef4bf 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -334,15 +334,15 @@ void __init dc21285_preinit(void)
        /*
         * We don't care if these fail.
         */
-        dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, IRQF_DISABLED,
+        dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, 0,
                            "PCI system error", &serr_timer);
-        dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, IRQF_DISABLED,
+        dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, 0,
                            "PCI parity error", &perr_timer);
-        dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, IRQF_DISABLED,
+        dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, 0,
                            "PCI abort", NULL);
-        dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, IRQF_DISABLED,
+        dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, 0,
                            "Discard timer", NULL);
-        dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, IRQF_DISABLED,
+        dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0,
                            "PCI data parity", NULL);
        if (cfn_mode) {
diff --git a/arch/arm/mach-footbridge/include/mach/timex.h b/arch/arm/mach-footbridge/include/mach/timex.h
deleted file mode 100644
index d0fea9d6d4ab..000000000000
--- a/arch/arm/mach-footbridge/include/mach/timex.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  arch/arm/mach-footbridge/include/mach/timex.h
- *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  EBSA285 architecture timex specifications
- */
-/*
- * We assume a constant here; this satisfies the maths in linux/timex.h
- * and linux/time.h.  CLOCK_TICK_RATE is actually system dependent, but
- * this must be a constant.
- */
-#define CLOCK_TICK_RATE         (50000000/16)
diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c
index d9301dd56354..b73f52e196b9 100644
--- a/arch/arm/mach-footbridge/isa-timer.c
+++ b/arch/arm/mach-footbridge/isa-timer.c
@@ -27,7 +27,7 @@ static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
 static struct irqaction pit_timer_irq = {
        .name           = "pit",
        .handler        = pit_timer_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .dev_id         = &i8253_clockevent,
 };
diff --git a/arch/arm/mach-gemini/idle.c b/arch/arm/mach-gemini/idle.c
index 87dff4f5059e..ddf8ec9d203b 100644
--- a/arch/arm/mach-gemini/idle.c
+++ b/arch/arm/mach-gemini/idle.c
@@ -3,7 +3,7 @@
 */
 #include <linux/init.h>
-#include <asm/system.h>
+#include <asm/system_misc.h>
 #include <asm/proc-fns.h>
 static void gemini_idle(void)
diff --git a/arch/arm/mach-gemini/include/mach/timex.h b/arch/arm/mach-gemini/include/mach/timex.h
deleted file mode 100644
index dc5690ba975c..000000000000
--- a/arch/arm/mach-gemini/include/mach/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Gemini timex specifications
- *
- * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-/* When AHB bus frequency is 150MHz */
-#define CLOCK_TICK_RATE 38000000
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 0aded64a9ebc..830b76e70250 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -5,7 +5,6 @@ config ARCH_HIGHBANK
        select ARCH_HAS_HOLES_MEMORYMODEL
        select ARCH_HAS_OPP
        select ARCH_SUPPORTS_BIG_ENDIAN
-        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_AMBA
        select ARM_ERRATA_764369 if SMP
        select ARM_ERRATA_775420
@@ -14,14 +13,8 @@ config ARCH_HIGHBANK
        select ARM_PSCI
        select ARM_TIMER_SP804
        select CACHE_L2X0
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select MAILBOX
        select PL320_MBOX
-        select SPARSE_IRQ
-        select USE_OF
        select ZONE_DMA if ARM_LPAE
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 1abae5f6a418..feee4dbb0760 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -3,13 +3,9 @@ config ARCH_HI3xxx
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
-        select ARCH_WANT_OPTIONAL_GPIOLIB
        select CACHE_L2X0
-        select CLKSRC_OF
+        select HAVE_ARM_SCU if SMP
-        select GENERIC_CLOCKEVENTS
-        select HAVE_ARM_SCU
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select PINCTRL
        select PINCTRL_SINGLE
        help
diff --git a/arch/arm/mach-hisi/Makefile b/arch/arm/mach-hisi/Makefile
index 6870058d0a48..2ae1b59267c2 100644
--- a/arch/arm/mach-hisi/Makefile
+++ b/arch/arm/mach-hisi/Makefile
@@ -3,5 +3,4 @@
 #
 obj-y   += hisilicon.o
-obj-$(CONFIG_SMP)               += platsmp.o
+obj-$(CONFIG_SMP)               += platsmp.o hotplug.o
-obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c
index b909854eee7f..abd441b0c604 100644
--- a/arch/arm/mach-hisi/hotplug.c
+++ b/arch/arm/mach-hisi/hotplug.c
@@ -178,6 +178,7 @@ static inline void cpu_enter_lowpower(void)
          : "cc");
 }
+#ifdef CONFIG_HOTPLUG_CPU
 void hi3xxx_cpu_die(unsigned int cpu)
 {
        cpu_enter_lowpower();
@@ -198,3 +199,4 @@ int hi3xxx_cpu_kill(unsigned int cpu)
        hi3xxx_set_cpu(cpu, false);
        return 1;
 }
+#endif
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 33567aa5880f..5740296dc429 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,19 +1,15 @@
 config ARCH_MXC
        bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
        select ARCH_REQUIRE_GPIOLIB
        select ARM_CPU_SUSPEND if PM
-        select ARM_PATCH_PHYS_VIRT
        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_ALLOCATOR
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
-        select MULTI_IRQ_HANDLER
        select PINCTRL
+        select PM_OPP if PM
        select SOC_BUS
-        select SPARSE_IRQ
+        select SRAM
-        select USE_OF
        help
          Support for Freescale MXC/iMX-based family of processors
@@ -121,18 +117,16 @@ config SOC_IMX31
 config SOC_IMX35
        bool
        select ARCH_MXC_IOMUX_V3
-        select CPU_V6K
        select HAVE_EPIT
        select MXC_AVIC
+        select PINCTRL_IMX35
        select SMP_ON_UP if SMP
-        select PINCTRL
 config SOC_IMX5
        bool
        select ARCH_HAS_CPUFREQ
        select ARCH_HAS_OPP
        select ARCH_MXC_IOMUX_V3
-        select CPU_V7
        select MXC_TZIC
 config  SOC_IMX51
@@ -777,65 +771,50 @@ config	SOC_IMX50
 config  SOC_IMX53
        bool "i.MX53 support"
        select HAVE_IMX_SRC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
        select PINCTRL_IMX53
        select SOC_IMX5
        help
          This enables support for Freescale i.MX53 processor.
-config SOC_IMX6Q
+config SOC_IMX6
-        bool "i.MX6 Quad/DualLite support"
+        bool
-        select ARCH_HAS_CPUFREQ
-        select ARCH_HAS_OPP
        select ARM_ERRATA_754322
-        select ARM_ERRATA_764369 if SMP
        select ARM_ERRATA_775420
        select ARM_GIC
-        select CPU_V7
-        select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if SMP
        select HAVE_IMX_ANATOP
        select HAVE_IMX_GPC
        select HAVE_IMX_MMDC
        select HAVE_IMX_SRC
-        select HAVE_SMP
        select MFD_SYSCON
-        select MIGHT_HAVE_PCI
-        select PCI_DOMAINS if PCI
-        select PINCTRL_IMX6Q
        select PL310_ERRATA_588369 if CACHE_PL310
        select PL310_ERRATA_727915 if CACHE_PL310
        select PL310_ERRATA_769419 if CACHE_PL310
-        select PM_OPP if PM
+config SOC_IMX6Q
+        bool "i.MX6 Quad/DualLite support"
+        select ARM_ERRATA_764369 if SMP
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if SMP
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
+        select PINCTRL_IMX6Q
+        select SOC_IMX6
        help
          This enables support for Freescale i.MX6 Quad processor.
 config SOC_IMX6SL
        bool "i.MX6 SoloLite support"
-        select ARM_ERRATA_754322
-        select ARM_ERRATA_775420
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_IMX_ANATOP
-        select HAVE_IMX_GPC
-        select HAVE_IMX_MMDC
-        select HAVE_IMX_SRC
-        select MFD_SYSCON
        select PINCTRL_IMX6SL
-        select PL310_ERRATA_588369 if CACHE_PL310
+        select SOC_IMX6
-        select PL310_ERRATA_727915 if CACHE_PL310
-        select PL310_ERRATA_769419 if CACHE_PL310
        help
          This enables support for Freescale i.MX6 SoloLite processor.
 config SOC_VF610
        bool "Vybrid Family VF610 support"
-        select CPU_V7
        select ARM_GIC
-        select CLKSRC_OF
        select PINCTRL_VF610
        select VF_PIT_TIMER
        select PL310_ERRATA_588369 if CACHE_PL310
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ec419649320f..f4ed83032dd0 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
 obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
+obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
 endif
 ifdef CONFIG_SND_IMX_SOC
@@ -101,9 +102,11 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
 obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
+ifeq ($(CONFIG_SUSPEND),y)
-# i.MX6SL reuses i.MX6Q code
+AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
+obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
+endif
+obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
 # i.MX5 based machines
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index d7ed66091a2a..bdc2e4630a08 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -149,7 +149,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
        clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
        clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
        clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
-        clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
        clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
        clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
        clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 69858c78f40d..dc36e6c2f1da 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -265,14 +265,6 @@ int __init mx25_clocks_init(void)
        clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
        clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
        clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
        clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
        clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
        clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index c6b40f386786..d2da8908b268 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -231,7 +231,6 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
        clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
-        clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
        clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 19fca1fdc6fe..568ef0a4de84 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -266,8 +266,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
        clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
        clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0");
-        clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1");
        clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
        clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
        clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4d677f442539..b0e7f9d2c245 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -437,12 +437,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
+        clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
-        clk_register_clkdev(clk[ahb], "ahb", NULL);
-        clk_register_clkdev(clk[cko1], "cko1", NULL);
-        clk_register_clkdev(clk[arm], NULL, "cpu0");
-        clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
-        clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
        if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
            cpu_is_imx6dl()) {
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 4c86f3035205..f7073c0782fb 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -18,27 +18,43 @@
 #include "clk.h"
 #include "common.h"
-static const char const *step_sels[]            = { "osc", "pll2_pfd2", };
+#define CCSR                    0xc
-static const char const *pll1_sw_sels[]         = { "pll1_sys", "step", };
+#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
-static const char const *ocram_alt_sels[]       = { "pll2_pfd2", "pll3_pfd1", };
+#define CACRR                   0x10
-static const char const *ocram_sels[]           = { "periph", "ocram_alt_sels", };
+#define CDHIPR                  0x48
-static const char const *pre_periph_sels[]      = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16)
-static const char const *periph_clk2_sels[]     = { "pll3_usb_otg", "osc", "osc", "dummy", };
+#define ARM_WAIT_DIV_396M       2
-static const char const *periph2_clk2_sels[]    = { "pll3_usb_otg", "pll2_bus", };
+#define ARM_WAIT_DIV_792M       4
-static const char const *periph_sels[]          = { "pre_periph_sel", "periph_clk2_podf", };
+#define ARM_WAIT_DIV_996M       6
-static const char const *periph2_sels[]         = { "pre_periph2_sel", "periph2_clk2_podf", };
-static const char const *csi_lcdif_sels[]       = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+#define PLL_ARM                 0x0
-static const char const *usdhc_sels[]           = { "pll2_pfd2", "pll2_pfd0", };
+#define BM_PLL_ARM_DIV_SELECT   (0x7f << 0)
-static const char const *ssi_sels[]             = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
+#define BM_PLL_ARM_POWERDOWN    (1 << 12)
-static const char const *perclk_sels[]          = { "ipg", "osc", };
+#define BM_PLL_ARM_ENABLE       (1 << 13)
-static const char const *epdc_pxp_sels[]        = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+#define BM_PLL_ARM_LOCK         (1 << 31)
-static const char const *gpu2d_ovg_sels[]       = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+#define PLL_ARM_DIV_792M        66
-static const char const *gpu2d_sels[]           = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
-static const char const *lcdif_pix_sels[]       = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+static const char *step_sels[]          = { "osc", "pll2_pfd2", };
-static const char const *epdc_pix_sels[]        = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+static const char *pll1_sw_sels[]       = { "pll1_sys", "step", };
-static const char const *audio_sels[]           = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char *ocram_alt_sels[]     = { "pll2_pfd2", "pll3_pfd1", };
-static const char const *ecspi_sels[]           = { "pll3_60m", "osc", };
+static const char *ocram_sels[]         = { "periph", "ocram_alt_sels", };
-static const char const *uart_sels[]            = { "pll3_80m", "osc", };
+static const char *pre_periph_sels[]    = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+static const char *periph_clk2_sels[]   = { "pll3_usb_otg", "osc", "osc", "dummy", };
+static const char *periph2_clk2_sels[]  = { "pll3_usb_otg", "pll2_bus", };
+static const char *periph_sels[]        = { "pre_periph_sel", "periph_clk2_podf", };
+static const char *periph2_sels[]       = { "pre_periph2_sel", "periph2_clk2_podf", };
+static const char *csi_lcdif_sels[]     = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+static const char *usdhc_sels[]         = { "pll2_pfd2", "pll2_pfd0", };
+static const char *ssi_sels[]           = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
+static const char *perclk_sels[]        = { "ipg", "osc", };
+static const char *epdc_pxp_sels[]      = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char *gpu2d_ovg_sels[]     = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+static const char *gpu2d_sels[]         = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
+static const char *lcdif_pix_sels[]     = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+static const char *epdc_pix_sels[]      = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+static const char *audio_sels[]         = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char *ecspi_sels[]         = { "pll3_60m", "osc", };
+static const char *uart_sels[]          = { "pll3_80m", "osc", };
 static struct clk_div_table clk_enet_ref_table[] = {
        { .val = 0, .div = 20, },
@@ -65,6 +81,89 @@ static struct clk_div_table video_div_table[] = {
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
+static void __iomem *ccm_base;
+static void __iomem *anatop_base;
+static const u32 clks_init_on[] __initconst = {
+        IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
+};
+/*
+ * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
+ *           during WAIT mode entry process could cause cache memory
+ *           corruption.
+ *
+ * Software workaround:
+ *     To prevent this issue from occurring, software should ensure that the
+ * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
+ * entering WAIT mode.
+ *
+ * This function will set the ARM clk to max value within the 12:5 limit.
+ * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
+ * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
+ * the clk APIs can NOT be called in idle thread(may cause kernel schedule
+ * as there is sleep function in PLL wait function), so here we just slow
+ * down ARM to below freq according to previous freq:
+ *
+ * run mode      wait mode
+ * 396MHz   ->   132MHz;
+ * 792MHz   ->   158.4MHz;
+ * 996MHz   ->   142.3MHz;
+ */
+static int imx6sl_get_arm_divider_for_wait(void)
+{
+        if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
+                return ARM_WAIT_DIV_396M;
+        } else {
+                if ((readl_relaxed(anatop_base + PLL_ARM) &
+                        BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
+                        return ARM_WAIT_DIV_792M;
+                else
+                        return ARM_WAIT_DIV_996M;
+        }
+}
+static void imx6sl_enable_pll_arm(bool enable)
+{
+        static u32 saved_pll_arm;
+        u32 val;
+        if (enable) {
+                saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
+                val |= BM_PLL_ARM_ENABLE;
+                val &= ~BM_PLL_ARM_POWERDOWN;
+                writel_relaxed(val, anatop_base + PLL_ARM);
+                while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
+                        ;
+        } else {
+                 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
+        }
+}
+void imx6sl_set_wait_clk(bool enter)
+{
+        static unsigned long saved_arm_div;
+        int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
+        /*
+         * According to hardware design, arm podf change need
+         * PLL1 clock enabled.
+         */
+        if (arm_div_for_wait == ARM_WAIT_DIV_396M)
+                imx6sl_enable_pll_arm(true);
+        if (enter) {
+                saved_arm_div = readl_relaxed(ccm_base + CACRR);
+                writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
+        } else {
+                writel_relaxed(saved_arm_div, ccm_base + CACRR);
+        }
+        while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
+                ;
+        if (arm_div_for_wait == ARM_WAIT_DIV_396M)
+                imx6sl_enable_pll_arm(false);
+}
 static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 {
@@ -72,6 +171,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        void __iomem *base;
        int irq;
        int i;
+        int ret;
        clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
        clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
@@ -80,6 +180,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
        base = of_iomap(np, 0);
        WARN_ON(!base);
+        anatop_base = base;
        /*                                             type               name            parent  base         div_mask */
        clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f);
@@ -127,6 +228,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        np = ccm_node;
        base = of_iomap(np, 0);
        WARN_ON(!base);
+        ccm_base = base;
        /* Reuse imx6q pm code */
        imx6q_pm_set_ccm_base(base);
@@ -258,6 +360,19 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
        clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
+        /* Ensure the AHB clk is at 132MHz. */
+        ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
+        if (ret)
+                pr_warn("%s: failed to set AHB clock rate %d!\n",
+                        __func__, ret);
+        /*
+         * Make sure those always on clocks are enabled to maintain the correct
+         * usecount and enabling/disabling of parent PLLs.
+         */
+        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+                clk_prepare_enable(clks[clks_init_on[i]]);
        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index ecd66d8e20b6..22dc3ee21fd4 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -63,25 +63,25 @@ static void __iomem *anatop_base;
 static void __iomem *ccm_base;
 /* sources for multiplexer clocks, this is used multiple times */
-static const char const *fast_sels[]    = { "firc", "fxosc", };
+static const char *fast_sels[]  = { "firc", "fxosc", };
-static const char const *slow_sels[]    = { "sirc_32k", "sxosc", };
+static const char *slow_sels[]  = { "sirc_32k", "sxosc", };
-static const char const *pll1_sels[]    = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
+static const char *pll1_sels[]  = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
-static const char const *pll2_sels[]    = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
+static const char *pll2_sels[]  = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
-static const char const *sys_sels[]     = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
+static const char *sys_sels[]   = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
-static const char const *ddr_sels[]     = { "pll2_pfd2", "sys_sel", };
+static const char *ddr_sels[]   = { "pll2_pfd2", "sys_sel", };
-static const char const *rmii_sels[]    = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
+static const char *rmii_sels[]  = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
-static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
+static const char *enet_ts_sels[]       = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
-static const char const *esai_sels[]    = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char *esai_sels[]  = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
-static const char const *sai_sels[]     = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char *sai_sels[]   = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
-static const char const *nfc_sels[]     = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
+static const char *nfc_sels[]   = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
-static const char const *qspi_sels[]    = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
+static const char *qspi_sels[]  = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
-static const char const *esdhc_sels[]   = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
+static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
-static const char const *dcu_sels[]     = { "pll1_pfd2", "pll3_main", };
+static const char *dcu_sels[]   = { "pll1_pfd2", "pll3_main", };
-static const char const *gpu_sels[]     = { "pll2_pfd2", "pll3_pfd2", };
+static const char *gpu_sels[]   = { "pll2_pfd2", "pll3_pfd2", };
-static const char const *vadc_sels[]    = { "pll6_main_div", "pll3_main_div", "pll3_main", };
+static const char *vadc_sels[]  = { "pll6_main_div", "pll3_main_div", "pll3_main", };
 /* FTM counter clock source, not module clock */
-static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
+static const char *ftm_ext_sels[]       = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
-static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
+static const char *ftm_fix_sels[]       = { "sxosc", "ipg_bus", };
 static struct clk_div_table pll4_main_div_table[] = {
        { .val = 0, .div = 1 },
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index baf439dc22d8..b5241ea76706 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
 */
 /*
@@ -116,7 +116,6 @@ void imx_enable_cpu(int cpu, bool enable);
 void imx_set_cpu_jump(int cpu, void *jump_addr);
 u32 imx_get_cpu_arg(int cpu);
 void imx_set_cpu_arg(int cpu, u32 arg);
-void v7_cpu_resume(void);
 #ifdef CONFIG_SMP
 void v7_secondary_startup(void);
 void imx_scu_map_io(void);
@@ -139,13 +138,25 @@ void imx_anatop_init(void);
 void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-void imx6q_set_chicken_bit(void);
+void imx6q_set_int_mem_clk_lpm(void);
+void imx6sl_set_wait_clk(bool enter);
 void imx_cpu_die(unsigned int cpu);
 int imx_cpu_kill(unsigned int cpu);
+#ifdef CONFIG_SUSPEND
+void v7_cpu_resume(void);
+void imx6_suspend(void __iomem *ocram_vbase);
+#else
+static inline void v7_cpu_resume(void) {}
+static inline void imx6_suspend(void __iomem *ocram_vbase) {}
+#endif
 void imx6q_pm_init(void);
+void imx6dl_pm_init(void);
+void imx6sl_pm_init(void);
 void imx6q_pm_set_ccm_base(void __iomem *base);
 #ifdef CONFIG_PM
 void imx5_pm_init(void);
 #else
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 23ddfb693b2d..6bcae0479049 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -68,8 +68,8 @@ int __init imx6q_cpuidle_init(void)
        /* Need to enable SCU standby for entering WAIT modes */
        imx_scu_standby_enable();
-        /* Set chicken bit to get a reliable WAIT mode support */
+        /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
-        imx6q_set_chicken_bit();
+        imx6q_set_int_mem_clk_lpm();
        return cpuidle_register(&imx6q_cpuidle_driver, NULL);
 }
diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c
new file mode 100644
index 000000000000..d4b6b8171fa9
--- /dev/null
+++ b/arch/arm/mach-imx/cpuidle-imx6sl.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include "common.h"
+#include "cpuidle.h"
+static int imx6sl_enter_wait(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv, int index)
+{
+        imx6q_set_lpm(WAIT_UNCLOCKED);
+        /*
+         * Software workaround for ERR005311, see function
+         * description for details.
+         */
+        imx6sl_set_wait_clk(true);
+        cpu_do_idle();
+        imx6sl_set_wait_clk(false);
+        imx6q_set_lpm(WAIT_CLOCKED);
+        return index;
+}
+static struct cpuidle_driver imx6sl_cpuidle_driver = {
+        .name = "imx6sl_cpuidle",
+        .owner = THIS_MODULE,
+        .states = {
+                /* WFI */
+                ARM_CPUIDLE_WFI_STATE,
+                /* WAIT */
+                {
+                        .exit_latency = 50,
+                        .target_residency = 75,
+                        .flags = CPUIDLE_FLAG_TIME_VALID |
+                                CPUIDLE_FLAG_TIMER_STOP,
+                        .enter = imx6sl_enter_wait,
+                        .name = "WAIT",
+                        .desc = "Clock off",
+                },
+        },
+        .state_count = 2,
+        .safe_state_index = 0,
+};
+int __init imx6sl_cpuidle_init(void)
+{
+        return cpuidle_register(&imx6sl_cpuidle_driver, NULL);
+}
diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
index 786f98ecc145..24e33670417c 100644
--- a/arch/arm/mach-imx/cpuidle.h
+++ b/arch/arm/mach-imx/cpuidle.h
@@ -13,6 +13,7 @@
 #ifdef CONFIG_CPU_IDLE
 extern int imx5_cpuidle_init(void);
 extern int imx6q_cpuidle_init(void);
+extern int imx6sl_cpuidle_init(void);
 #else
 static inline int imx5_cpuidle_init(void)
 {
@@ -22,4 +23,8 @@ static inline int imx6q_cpuidle_init(void)
 {
        return 0;
 }
+static inline int imx6sl_cpuidle_init(void)
+{
+        return 0;
+}
 #endif
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index 769563fdeaa0..61a114cddc39 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -83,7 +83,3 @@ extern const struct imx_spi_imx_data imx25_cspi_data[];
 #define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
 #define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
 #define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
-extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
-#define imx25_add_mxc_pwm(id)   \
-        imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
index deee5baee88c..26389f35a2b2 100644
--- a/arch/arm/mach-imx/devices-imx51.h
+++ b/arch/arm/mach-imx/devices-imx51.h
@@ -57,10 +57,6 @@ extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
 #define imx51_add_imx2_wdt(id)  \
        imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
-extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
-#define imx51_add_mxc_pwm(id)   \
-        imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
 extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
 #define imx51_add_imx_keypad(pdata)     \
        imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 68c74fb0373c..2d260a5a307c 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -67,9 +67,6 @@ config IMX_HAVE_PLATFORM_MXC_MMC
 config IMX_HAVE_PLATFORM_MXC_NAND
        bool
-config IMX_HAVE_PLATFORM_MXC_PWM
-        bool
 config IMX_HAVE_PLATFORM_MXC_RNGA
        bool
        select ARCH_HAS_RNGA
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 67416fb1dc69..1cbc14cd80d1 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index c13b76b9f6b3..61352a80bb59 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -290,15 +290,6 @@ struct imx_pata_imx_data {
 struct platform_device *__init imx_add_pata_imx(
                const struct imx_pata_imx_data *data);
-struct imx_mxc_pwm_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_pwm(
-                const struct imx_mxc_pwm_data *data);
 /* mxc_rtc */
 struct imx_mxc_rtc_data {
        const char *devid;
diff --git a/arch/arm/mach-imx/devices/platform-mxc_pwm.c b/arch/arm/mach-imx/devices/platform-mxc_pwm.c
deleted file mode 100644
index dcd289777687..000000000000
--- a/arch/arm/mach-imx/devices/platform-mxc_pwm.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)           \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_PWM ## _hwid,                        \
-        }
-#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size)                  \
-        [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
-        imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
-#define imx25_mxc_pwm_data_entry(_id, _hwid)                            \
-        imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
-        imx25_mxc_pwm_data_entry(0, 1),
-        imx25_mxc_pwm_data_entry(1, 2),
-        imx25_mxc_pwm_data_entry(2, 3),
-        imx25_mxc_pwm_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
-        imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = {
-#define imx51_mxc_pwm_data_entry(_id, _hwid)                            \
-        imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_mxc_pwm_data_entry(0, 1),
-        imx51_mxc_pwm_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-struct platform_device *__init imx_add_mxc_pwm(
-                const struct imx_mxc_pwm_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-        return imx_add_platform_device("mxc_pwm", data->id,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index a3b0b04b45c9..abf43bb47eca 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
@@ -20,7 +20,9 @@
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #define __ASM_ARCH_MXC_HARDWARE_H__
+#ifndef __ASSEMBLY__
 #include <asm/io.h>
+#endif
 #include <asm/sizes.h>
 #define addr_in_module(addr, mod) \
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 627f16f0e9d1..de5047c8a6c8 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -12,12 +12,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
-        .section ".text.head", "ax"
-#ifdef CONFIG_SMP
 diag_reg_offset:
        .word   g_diag_reg - .
@@ -34,38 +29,3 @@ ENTRY(v7_secondary_startup)
        set_diag_reg
        b       secondary_startup
 ENDPROC(v7_secondary_startup)
-#endif
-#ifdef CONFIG_ARM_CPU_SUSPEND
-/*
- * The following code must assume it is running from physical address
- * where absolute virtual addresses to the data section have to be
- * turned into relative ones.
- */
-#ifdef CONFIG_CACHE_L2X0
-        .macro  pl310_resume
-        adr     r0, l2x0_saved_regs_offset
-        ldr     r2, [r0]
-        add     r2, r2, r0
-        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
-        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
-        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
-        mov     r1, #0x1
-        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
-        .endm
-l2x0_saved_regs_offset:
-        .word   l2x0_saved_regs - .
-#else
-        .macro  pl310_resume
-        .endm
-#endif
-ENTRY(v7_cpu_resume)
-        bl      v7_invalidate_l1
-        pl310_resume
-        b       cpu_resume
-ENDPROC(v7_cpu_resume)
-#endif
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 76e5db4fce35..e60456d85c9d 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -182,16 +182,83 @@ static void __init imx6q_enet_phy_init(void)
 static void __init imx6q_1588_init(void)
 {
+        struct device_node *np;
+        struct clk *ptp_clk;
+        struct clk *enet_ref;
        struct regmap *gpr;
+        u32 clksel;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
+        if (!np) {
+                pr_warn("%s: failed to find fec node\n", __func__);
+                return;
+        }
+        ptp_clk = of_clk_get(np, 2);
+        if (IS_ERR(ptp_clk)) {
+                pr_warn("%s: failed to get ptp clock\n", __func__);
+                goto put_node;
+        }
+        enet_ref = clk_get_sys(NULL, "enet_ref");
+        if (IS_ERR(enet_ref)) {
+                pr_warn("%s: failed to get enet clock\n", __func__);
+                goto put_ptp_clk;
+        }
+        /*
+         * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
+         * set bit IOMUXC_GPR1[21].  Or the PTP clock must be from pad
+         * (external OSC), and we need to clear the bit.
+         */
+        clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
+                                       IMX6Q_GPR1_ENET_CLK_SEL_PAD;
        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
        if (!IS_ERR(gpr))
                regmap_update_bits(gpr, IOMUXC_GPR1,
                                IMX6Q_GPR1_ENET_CLK_SEL_MASK,
-                                IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
+                                clksel);
        else
                pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
+        clk_put(enet_ref);
+put_ptp_clk:
+        clk_put(ptp_clk);
+put_node:
+        of_node_put(np);
+}
+static void __init imx6q_axi_init(void)
+{
+        struct regmap *gpr;
+        unsigned int mask;
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+        if (!IS_ERR(gpr)) {
+                /*
+                 * Enable the cacheable attribute of VPU and IPU
+                 * AXI transactions.
+                 */
+                mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL |
+                        IMX6Q_GPR4_VPU_RD_CACHE_SEL |
+                        IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
+                        IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
+                        IMX6Q_GPR4_IPU_WR_CACHE_CTL |
+                        IMX6Q_GPR4_IPU_RD_CACHE_CTL;
+                regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);
+                /* Increase IPU read QoS priority */
+                regmap_update_bits(gpr, IOMUXC_GPR6,
+                                IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
+                                IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
+                                (0xf << 16) | (0x7 << 20));
+                regmap_update_bits(gpr, IOMUXC_GPR7,
+                                IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
+                                IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
+                                (0xf << 16) | (0x7 << 20));
+        } else {
+                pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
+        }
 }
 static void __init imx6q_init_machine(void)
@@ -212,15 +279,18 @@ static void __init imx6q_init_machine(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
        imx_anatop_init();
-        imx6q_pm_init();
+        cpu_is_imx6q() ?  imx6q_pm_init() : imx6dl_pm_init();
        imx6q_1588_init();
+        imx6q_axi_init();
 }
 #define OCOTP_CFG3                      0x440
 #define OCOTP_CFG3_SPEED_SHIFT          16
 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
+#define OCOTP_CFG3_SPEED_996MHZ         0x2
+#define OCOTP_CFG3_SPEED_852MHZ         0x1
-static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
+static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
 {
        struct device_node *np;
        void __iomem *base;
@@ -238,11 +308,29 @@ static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
                goto put_node;
        }
+        /*
+         * SPEED_GRADING[1:0] defines the max speed of ARM:
+         * 2b'11: 1200000000Hz;
+         * 2b'10: 996000000Hz;
+         * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
+         * 2b'00: 792000000Hz;
+         * We need to set the max speed of ARM according to fuse map.
+         */
        val = readl_relaxed(base + OCOTP_CFG3);
        val >>= OCOTP_CFG3_SPEED_SHIFT;
-        if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
+        val &= 0x3;
+        if (val != OCOTP_CFG3_SPEED_1P2GHZ)
                if (dev_pm_opp_disable(cpu_dev, 1200000000))
                        pr_warn("failed to disable 1.2 GHz OPP\n");
+        if (val < OCOTP_CFG3_SPEED_996MHZ)
+                if (dev_pm_opp_disable(cpu_dev, 996000000))
+                        pr_warn("failed to disable 996 MHz OPP\n");
+        if (cpu_is_imx6q()) {
+                if (val != OCOTP_CFG3_SPEED_852MHZ)
+                        if (dev_pm_opp_disable(cpu_dev, 852000000))
+                                pr_warn("failed to disable 852 MHz OPP\n");
+        }
 put_node:
        of_node_put(np);
@@ -268,7 +356,7 @@ static void __init imx6q_opp_init(void)
                goto put_node;
        }
-        imx6q_opp_check_1p2ghz(cpu_dev);
+        imx6q_opp_check_speed_grading(cpu_dev);
 put_node:
        of_node_put(np);
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 0f4fd4c0ab8e..ad323385115c 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -17,6 +17,7 @@
 #include <asm/mach/map.h>
 #include "common.h"
+#include "cpuidle.h"
 static void __init imx6sl_fec_init(void)
 {
@@ -39,6 +40,8 @@ static void __init imx6sl_init_late(void)
        /* imx6sl reuses imx6q cpufreq driver */
        if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
                platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
+        imx6sl_cpuidle_init();
 }
 static void __init imx6sl_init_machine(void)
@@ -55,8 +58,7 @@ static void __init imx6sl_init_machine(void)
        imx6sl_fec_init();
        imx_anatop_init();
-        /* Reuse imx6q pm code */
+        imx6sl_pm_init();
-        imx6q_pm_init();
 }
 static void __init imx6sl_init_irq(void)
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 9821b824dcaf..a7a4a9c67615 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -21,6 +21,10 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/irq.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -195,14 +199,58 @@ static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
 static struct i2c_board_info mx27ads_i2c_devices[] = {
 };
-void lcd_power(int on)
+static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-        if (on)
+        if (value)
                __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
        else
                __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 }
+static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
+{
+        return 0;
+}
+#define MX27ADS_LCD_GPIO        (6 * 32)
+static struct regulator_consumer_supply mx27ads_lcd_regulator_consumer =
+        REGULATOR_SUPPLY("lcd", "imx-fb.0");
+static struct regulator_init_data mx27ads_lcd_regulator_init_data = {
+        .constraints    = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+},
+        .consumer_supplies      = &mx27ads_lcd_regulator_consumer,
+        .num_consumer_supplies  = 1,
+};
+static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = {
+        .supply_name    = "LCD",
+        .microvolts     = 3300000,
+        .gpio           = MX27ADS_LCD_GPIO,
+        .init_data      = &mx27ads_lcd_regulator_init_data,
+};
+static void __init mx27ads_regulator_init(void)
+{
+        struct gpio_chip *vchip;
+        vchip = kzalloc(sizeof(*vchip), GFP_KERNEL);
+        vchip->owner            = THIS_MODULE;
+        vchip->label            = "LCD";
+        vchip->base             = MX27ADS_LCD_GPIO;
+        vchip->ngpio            = 1;
+        vchip->direction_output = vgpio_dir_out;
+        vchip->set              = vgpio_set;
+        gpiochip_add(vchip);
+        platform_device_register_data(&platform_bus, "reg-fixed-voltage",
+                                      PLATFORM_DEVID_AUTO,
+                                      &mx27ads_lcd_regulator_pdata,
+                                      sizeof(mx27ads_lcd_regulator_pdata));
+}
 static struct imx_fb_videomode mx27ads_modes[] = {
        {
                .mode = {
@@ -239,8 +287,6 @@ static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
        .pwmr           = 0x00A903FF,
        .lscr1          = 0x00120300,
        .dmacr          = 0x00020010,
-        .lcd_power      = lcd_power,
 };
 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
@@ -304,6 +350,7 @@ static void __init mx27ads_board_init(void)
        i2c_register_board_info(1, mx27ads_i2c_devices,
                                ARRAY_SIZE(mx27ads_i2c_devices));
        imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
+        mx27ads_regulator_init();
        imx27_add_imx_fb(&mx27ads_fb_data);
        imx27_add_mxc_mmc(0, &sdhc1_pdata);
        imx27_add_mxc_mmc(1, &sdhc2_pdata);
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index b3738e616f19..8f45afe785f8 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -128,27 +128,15 @@ static struct platform_device mx31moboard_flash = {
        .num_resources = 1,
 };
-static int moboard_uart0_init(struct platform_device *pdev)
+static void __init moboard_uart0_init(void)
 {
-        int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
+        if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack")) {
-        if (ret)
+                gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
-                return ret;
-        ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
-        if (ret)
                gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
+        }
-        return ret;
-}
-static void moboard_uart0_exit(struct platform_device *pdev)
-{
-        gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
 }
 static const struct imxuart_platform_data uart0_pdata __initconst = {
-        .init = moboard_uart0_init,
-        .exit = moboard_uart0_exit,
 };
 static const struct imxuart_platform_data uart4_pdata __initconst = {
@@ -543,6 +531,7 @@ static void __init mx31moboard_init(void)
        imx31_add_imx2_wdt();
+        moboard_uart0_init();
        imx31_add_imx_uart0(&uart0_pdata);
        imx31_add_imx_uart4(&uart4_pdata);
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
new file mode 100644
index 000000000000..9392a8f4ef24
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -0,0 +1,551 @@
+/*
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/genalloc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <linux/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/fncpy.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/tlb.h>
+#include "common.h"
+#include "hardware.h"
+#define CCR                             0x0
+#define BM_CCR_WB_COUNT                 (0x7 << 16)
+#define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
+#define BM_CCR_RBC_EN                   (0x1 << 27)
+#define CLPCR                           0x54
+#define BP_CLPCR_LPM                    0
+#define BM_CLPCR_LPM                    (0x3 << 0)
+#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
+#define BM_CLPCR_SBYOS                  (0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
+#define BM_CLPCR_VSTBY                  (0x1 << 8)
+#define BP_CLPCR_STBY_COUNT             9
+#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
+#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
+#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
+#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
+#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
+#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
+#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
+#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
+#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
+#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
+#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
+#define CGPR                            0x64
+#define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
+#define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
+#define MX6_MAX_MMDC_IO_NUM             33
+static void __iomem *ccm_base;
+static void __iomem *suspend_ocram_base;
+static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
+/*
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ *                              .
+ *                              .
+ *                              .
+ *                              ^
+ *                              ^
+ *                              ^
+ *                      imx6_suspend code
+ *              PM_INFO structure(imx6_cpu_pm_info)
+ * ======================== low address =======================
+ */
+struct imx6_pm_base {
+        phys_addr_t pbase;
+        void __iomem *vbase;
+};
+struct imx6_pm_socdata {
+        u32 cpu_type;
+        const char *mmdc_compat;
+        const char *src_compat;
+        const char *iomuxc_compat;
+        const char *gpc_compat;
+        const u32 mmdc_io_num;
+        const u32 *mmdc_io_offset;
+};
+static const u32 imx6q_mmdc_io_offset[] __initconst = {
+        0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
+        0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
+        0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+        0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
+        0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
+        0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
+        0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+        0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x74c,                      /* GPR_ADDS */
+};
+static const u32 imx6dl_mmdc_io_offset[] __initconst = {
+        0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
+        0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
+        0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+        0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
+        0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
+        0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
+        0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+        0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x74c,                      /* GPR_ADDS */
+};
+static const u32 imx6sl_mmdc_io_offset[] __initconst = {
+        0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
+        0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
+        0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
+        0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
+};
+static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6Q,
+        .mmdc_compat = "fsl,imx6q-mmdc",
+        .src_compat = "fsl,imx6q-src",
+        .iomuxc_compat = "fsl,imx6q-iomuxc",
+        .gpc_compat = "fsl,imx6q-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
+        .mmdc_io_offset = imx6q_mmdc_io_offset,
+};
+static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6DL,
+        .mmdc_compat = "fsl,imx6q-mmdc",
+        .src_compat = "fsl,imx6q-src",
+        .iomuxc_compat = "fsl,imx6dl-iomuxc",
+        .gpc_compat = "fsl,imx6q-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
+        .mmdc_io_offset = imx6dl_mmdc_io_offset,
+};
+static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6SL,
+        .mmdc_compat = "fsl,imx6sl-mmdc",
+        .src_compat = "fsl,imx6sl-src",
+        .iomuxc_compat = "fsl,imx6sl-iomuxc",
+        .gpc_compat = "fsl,imx6sl-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
+        .mmdc_io_offset = imx6sl_mmdc_io_offset,
+};
+/*
+ * This structure is for passing necessary data for low level ocram
+ * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
+ * definition is changed, the offset definition in
+ * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
+ * otherwise, the suspend to ocram function will be broken!
+ */
+struct imx6_cpu_pm_info {
+        phys_addr_t pbase; /* The physical address of pm_info. */
+        phys_addr_t resume_addr; /* The physical resume address for asm code */
+        u32 cpu_type;
+        u32 pm_info_size; /* Size of pm_info. */
+        struct imx6_pm_base mmdc_base;
+        struct imx6_pm_base src_base;
+        struct imx6_pm_base iomuxc_base;
+        struct imx6_pm_base ccm_base;
+        struct imx6_pm_base gpc_base;
+        struct imx6_pm_base l2_base;
+        u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
+        u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
+} __aligned(8);
+void imx6q_set_int_mem_clk_lpm(void)
+{
+        u32 val = readl_relaxed(ccm_base + CGPR);
+        val |= BM_CGPR_INT_MEM_CLK_LPM;
+        writel_relaxed(val, ccm_base + CGPR);
+}
+static void imx6q_enable_rbc(bool enable)
+{
+        u32 val;
+        /*
+         * need to mask all interrupts in GPC before
+         * operating RBC configurations
+         */
+        imx_gpc_mask_all();
+        /* configure RBC enable bit */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_RBC_EN;
+        val |= enable ? BM_CCR_RBC_EN : 0;
+        writel_relaxed(val, ccm_base + CCR);
+        /* configure RBC count */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_RBC_BYPASS_COUNT;
+        val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
+        writel(val, ccm_base + CCR);
+        /*
+         * need to delay at least 2 cycles of CKIL(32K)
+         * due to hardware design requirement, which is
+         * ~61us, here we use 65us for safe
+         */
+        udelay(65);
+        /* restore GPC interrupt mask settings */
+        imx_gpc_restore_all();
+}
+static void imx6q_enable_wb(bool enable)
+{
+        u32 val;
+        /* configure well bias enable bit */
+        val = readl_relaxed(ccm_base + CLPCR);
+        val &= ~BM_CLPCR_WB_PER_AT_LPM;
+        val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
+        writel_relaxed(val, ccm_base + CLPCR);
+        /* configure well bias count */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_WB_COUNT;
+        val |= enable ? BM_CCR_WB_COUNT : 0;
+        writel_relaxed(val, ccm_base + CCR);
+}
+int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+{
+        struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
+        u32 val = readl_relaxed(ccm_base + CLPCR);
+        val &= ~BM_CLPCR_LPM;
+        switch (mode) {
+        case WAIT_CLOCKED:
+                break;
+        case WAIT_UNCLOCKED:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
+                break;
+        case STOP_POWER_ON:
+                val |= 0x2 << BP_CLPCR_LPM;
+                break;
+        case WAIT_UNCLOCKED_POWER_OFF:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val &= ~BM_CLPCR_VSTBY;
+                val &= ~BM_CLPCR_SBYOS;
+                break;
+        case STOP_POWER_OFF:
+                val |= 0x2 << BP_CLPCR_LPM;
+                val |= 0x3 << BP_CLPCR_STBY_COUNT;
+                val |= BM_CLPCR_VSTBY;
+                val |= BM_CLPCR_SBYOS;
+                if (cpu_is_imx6sl()) {
+                        val |= BM_CLPCR_BYPASS_PMIC_READY;
+                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
+                } else {
+                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+        /*
+         * ERR007265: CCM: When improper low-power sequence is used,
+         * the SoC enters low power mode before the ARM core executes WFI.
+         *
+         * Software workaround:
+         * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
+         *    by setting IOMUX_GPR1_GINT.
+         * 2) Software should then unmask IRQ #32 in GPC before setting CCM
+         *    Low-Power mode.
+         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
+         *    is set (set bits 0-1 of CCM_CLPCR).
+         */
+        imx_gpc_irq_unmask(iomuxc_irq_data);
+        writel_relaxed(val, ccm_base + CLPCR);
+        imx_gpc_irq_mask(iomuxc_irq_data);
+        return 0;
+}
+static int imx6q_suspend_finish(unsigned long val)
+{
+        if (!imx6_suspend_in_ocram_fn) {
+                cpu_do_idle();
+        } else {
+                /*
+                 * call low level suspend function in ocram,
+                 * as we need to float DDR IO.
+                 */
+                local_flush_tlb_all();
+                imx6_suspend_in_ocram_fn(suspend_ocram_base);
+        }
+        return 0;
+}
+static int imx6q_pm_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                imx6q_set_lpm(STOP_POWER_OFF);
+                imx6q_enable_wb(true);
+                /*
+                 * For suspend into ocram, asm code already take care of
+                 * RBC setting, so we do NOT need to do that here.
+                 */
+                if (!imx6_suspend_in_ocram_fn)
+                        imx6q_enable_rbc(true);
+                imx_gpc_pre_suspend();
+                imx_anatop_pre_suspend();
+                imx_set_cpu_jump(0, v7_cpu_resume);
+                /* Zzz ... */
+                cpu_suspend(0, imx6q_suspend_finish);
+                if (cpu_is_imx6q() || cpu_is_imx6dl())
+                        imx_smp_prepare();
+                imx_anatop_post_resume();
+                imx_gpc_post_resume();
+                imx6q_enable_rbc(false);
+                imx6q_enable_wb(false);
+                imx6q_set_lpm(WAIT_CLOCKED);
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+static const struct platform_suspend_ops imx6q_pm_ops = {
+        .enter = imx6q_pm_enter,
+        .valid = suspend_valid_only_mem,
+};
+void __init imx6q_pm_set_ccm_base(void __iomem *base)
+{
+        ccm_base = base;
+}
+static int __init imx6_pm_get_base(struct imx6_pm_base *base,
+                                const char *compat)
+{
+        struct device_node *node;
+        struct resource res;
+        int ret = 0;
+        node = of_find_compatible_node(NULL, NULL, compat);
+        if (!node) {
+                ret = -ENODEV;
+                goto out;
+        }
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret)
+                goto put_node;
+        base->pbase = res.start;
+        base->vbase = ioremap(res.start, resource_size(&res));
+        if (!base->vbase)
+                ret = -ENOMEM;
+put_node:
+        of_node_put(node);
+out:
+        return ret;
+}
+static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
+{
+        phys_addr_t ocram_pbase;
+        struct device_node *node;
+        struct platform_device *pdev;
+        struct imx6_cpu_pm_info *pm_info;
+        struct gen_pool *ocram_pool;
+        unsigned long ocram_base;
+        int i, ret = 0;
+        const u32 *mmdc_offset_array;
+        suspend_set_ops(&imx6q_pm_ops);
+        if (!socdata) {
+                pr_warn("%s: invalid argument!\n", __func__);
+                return -EINVAL;
+        }
+        node = of_find_compatible_node(NULL, NULL, "mmio-sram");
+        if (!node) {
+                pr_warn("%s: failed to find ocram node!\n", __func__);
+                return -ENODEV;
+        }
+        pdev = of_find_device_by_node(node);
+        if (!pdev) {
+                pr_warn("%s: failed to find ocram device!\n", __func__);
+                ret = -ENODEV;
+                goto put_node;
+        }
+        ocram_pool = dev_get_gen_pool(&pdev->dev);
+        if (!ocram_pool) {
+                pr_warn("%s: ocram pool unavailable!\n", __func__);
+                ret = -ENODEV;
+                goto put_node;
+        }
+        ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
+        if (!ocram_base) {
+                pr_warn("%s: unable to alloc ocram!\n", __func__);
+                ret = -ENOMEM;
+                goto put_node;
+        }
+        ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
+        suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
+                MX6Q_SUSPEND_OCRAM_SIZE, false);
+        pm_info = suspend_ocram_base;
+        pm_info->pbase = ocram_pbase;
+        pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
+        pm_info->pm_info_size = sizeof(*pm_info);
+        /*
+         * ccm physical address is not used by asm code currently,
+         * so get ccm virtual address directly, as we already have
+         * it from ccm driver.
+         */
+        pm_info->ccm_base.vbase = ccm_base;
+        ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
+        if (ret) {
+                pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
+                goto put_node;
+        }
+        ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
+        if (ret) {
+                pr_warn("%s: failed to get src base %d!\n", __func__, ret);
+                goto src_map_failed;
+        }
+        ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
+        if (ret) {
+                pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
+                goto iomuxc_map_failed;
+        }
+        ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
+        if (ret) {
+                pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
+                goto gpc_map_failed;
+        }
+        ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
+        if (ret) {
+                pr_warn("%s: failed to get pl310-cache base %d!\n",
+                        __func__, ret);
+                goto pl310_cache_map_failed;
+        }
+        pm_info->cpu_type = socdata->cpu_type;
+        pm_info->mmdc_io_num = socdata->mmdc_io_num;
+        mmdc_offset_array = socdata->mmdc_io_offset;
+        for (i = 0; i < pm_info->mmdc_io_num; i++) {
+                pm_info->mmdc_io_val[i][0] =
+                        mmdc_offset_array[i];
+                pm_info->mmdc_io_val[i][1] =
+                        readl_relaxed(pm_info->iomuxc_base.vbase +
+                        mmdc_offset_array[i]);
+        }
+        imx6_suspend_in_ocram_fn = fncpy(
+                suspend_ocram_base + sizeof(*pm_info),
+                &imx6_suspend,
+                MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
+        goto put_node;
+pl310_cache_map_failed:
+        iounmap(&pm_info->gpc_base.vbase);
+gpc_map_failed:
+        iounmap(&pm_info->iomuxc_base.vbase);
+iomuxc_map_failed:
+        iounmap(&pm_info->src_base.vbase);
+src_map_failed:
+        iounmap(&pm_info->mmdc_base.vbase);
+put_node:
+        of_node_put(node);
+        return ret;
+}
+static void __init imx6_pm_common_init(const struct imx6_pm_socdata
+                                        *socdata)
+{
+        struct regmap *gpr;
+        int ret;
+        WARN_ON(!ccm_base);
+        if (IS_ENABLED(CONFIG_SUSPEND)) {
+                ret = imx6q_suspend_init(socdata);
+                if (ret)
+                        pr_warn("%s: No DDR LPM support with suspend %d!\n",
+                                __func__, ret);
+        }
+        /*
+         * This is for SW workaround step #1 of ERR007265, see comments
+         * in imx6q_set_lpm for details of this errata.
+         * Force IOMUXC irq pending, so that the interrupt to GPC can be
+         * used to deassert dsm_request signal when the signal gets
+         * asserted unexpectedly.
+         */
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+        if (!IS_ERR(gpr))
+                regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
+                                   IMX6Q_GPR1_GINT);
+}
+void __init imx6q_pm_init(void)
+{
+        imx6_pm_common_init(&imx6q_pm_data);
+}
+void __init imx6dl_pm_init(void)
+{
+        imx6_pm_common_init(&imx6dl_pm_data);
+}
+void __init imx6sl_pm_init(void)
+{
+        imx6_pm_common_init(&imx6sl_pm_data);
+}
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
deleted file mode 100644
index 29e3fe6a6669..000000000000
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/mfd/syscon.h>
-#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/regmap.h>
-#include <linux/suspend.h>
-#include <asm/cacheflush.h>
-#include <asm/proc-fns.h>
-#include <asm/suspend.h>
-#include <asm/hardware/cache-l2x0.h>
-#include "common.h"
-#include "hardware.h"
-#define CCR                             0x0
-#define BM_CCR_WB_COUNT                 (0x7 << 16)
-#define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
-#define BM_CCR_RBC_EN                   (0x1 << 27)
-#define CLPCR                           0x54
-#define BP_CLPCR_LPM                    0
-#define BM_CLPCR_LPM                    (0x3 << 0)
-#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
-#define BM_CLPCR_SBYOS                  (0x1 << 6)
-#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
-#define BM_CLPCR_VSTBY                  (0x1 << 8)
-#define BP_CLPCR_STBY_COUNT             9
-#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
-#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
-#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
-#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
-#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
-#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
-#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
-#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
-#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
-#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
-#define CGPR                            0x64
-#define BM_CGPR_CHICKEN_BIT             (0x1 << 17)
-static void __iomem *ccm_base;
-void imx6q_set_chicken_bit(void)
-{
-        u32 val = readl_relaxed(ccm_base + CGPR);
-        val |= BM_CGPR_CHICKEN_BIT;
-        writel_relaxed(val, ccm_base + CGPR);
-}
-static void imx6q_enable_rbc(bool enable)
-{
-        u32 val;
-        /*
-         * need to mask all interrupts in GPC before
-         * operating RBC configurations
-         */
-        imx_gpc_mask_all();
-        /* configure RBC enable bit */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_RBC_EN;
-        val |= enable ? BM_CCR_RBC_EN : 0;
-        writel_relaxed(val, ccm_base + CCR);
-        /* configure RBC count */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_RBC_BYPASS_COUNT;
-        val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
-        writel(val, ccm_base + CCR);
-        /*
-         * need to delay at least 2 cycles of CKIL(32K)
-         * due to hardware design requirement, which is
-         * ~61us, here we use 65us for safe
-         */
-        udelay(65);
-        /* restore GPC interrupt mask settings */
-        imx_gpc_restore_all();
-}
-static void imx6q_enable_wb(bool enable)
-{
-        u32 val;
-        /* configure well bias enable bit */
-        val = readl_relaxed(ccm_base + CLPCR);
-        val &= ~BM_CLPCR_WB_PER_AT_LPM;
-        val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
-        writel_relaxed(val, ccm_base + CLPCR);
-        /* configure well bias count */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_WB_COUNT;
-        val |= enable ? BM_CCR_WB_COUNT : 0;
-        writel_relaxed(val, ccm_base + CCR);
-}
-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
-{
-        struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
-        u32 val = readl_relaxed(ccm_base + CLPCR);
-        val &= ~BM_CLPCR_LPM;
-        switch (mode) {
-        case WAIT_CLOCKED:
-                break;
-        case WAIT_UNCLOCKED:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
-                break;
-        case STOP_POWER_ON:
-                val |= 0x2 << BP_CLPCR_LPM;
-                break;
-        case WAIT_UNCLOCKED_POWER_OFF:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val &= ~BM_CLPCR_VSTBY;
-                val &= ~BM_CLPCR_SBYOS;
-                break;
-        case STOP_POWER_OFF:
-                val |= 0x2 << BP_CLPCR_LPM;
-                val |= 0x3 << BP_CLPCR_STBY_COUNT;
-                val |= BM_CLPCR_VSTBY;
-                val |= BM_CLPCR_SBYOS;
-                if (cpu_is_imx6sl()) {
-                        val |= BM_CLPCR_BYPASS_PMIC_READY;
-                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
-                } else {
-                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
-                }
-                break;
-        default:
-                return -EINVAL;
-        }
-        /*
-         * ERR007265: CCM: When improper low-power sequence is used,
-         * the SoC enters low power mode before the ARM core executes WFI.
-         *
-         * Software workaround:
-         * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
-         *    by setting IOMUX_GPR1_GINT.
-         * 2) Software should then unmask IRQ #32 in GPC before setting CCM
-         *    Low-Power mode.
-         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
-         *    is set (set bits 0-1 of CCM_CLPCR).
-         */
-        imx_gpc_irq_unmask(iomuxc_irq_data);
-        writel_relaxed(val, ccm_base + CLPCR);
-        imx_gpc_irq_mask(iomuxc_irq_data);
-        return 0;
-}
-static int imx6q_suspend_finish(unsigned long val)
-{
-        cpu_do_idle();
-        return 0;
-}
-static int imx6q_pm_enter(suspend_state_t state)
-{
-        switch (state) {
-        case PM_SUSPEND_MEM:
-                imx6q_set_lpm(STOP_POWER_OFF);
-                imx6q_enable_wb(true);
-                imx6q_enable_rbc(true);
-                imx_gpc_pre_suspend();
-                imx_anatop_pre_suspend();
-                imx_set_cpu_jump(0, v7_cpu_resume);
-                /* Zzz ... */
-                cpu_suspend(0, imx6q_suspend_finish);
-                if (cpu_is_imx6q() || cpu_is_imx6dl())
-                        imx_smp_prepare();
-                imx_anatop_post_resume();
-                imx_gpc_post_resume();
-                imx6q_enable_rbc(false);
-                imx6q_enable_wb(false);
-                imx6q_set_lpm(WAIT_CLOCKED);
-                break;
-        default:
-                return -EINVAL;
-        }
-        return 0;
-}
-static const struct platform_suspend_ops imx6q_pm_ops = {
-        .enter = imx6q_pm_enter,
-        .valid = suspend_valid_only_mem,
-};
-void __init imx6q_pm_set_ccm_base(void __iomem *base)
-{
-        ccm_base = base;
-}
-void __init imx6q_pm_init(void)
-{
-        struct regmap *gpr;
-        WARN_ON(!ccm_base);
-        /*
-         * This is for SW workaround step #1 of ERR007265, see comments
-         * in imx6q_set_lpm for details of this errata.
-         * Force IOMUXC irq pending, so that the interrupt to GPC can be
-         * used to deassert dsm_request signal when the signal gets
-         * asserted unexpectedly.
-         */
-        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-        if (!IS_ERR(gpr))
-                regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
-                                   IMX6Q_GPR1_GINT);
-        suspend_set_ops(&imx6q_pm_ops);
-}
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
new file mode 100644
index 000000000000..20048ff05739
--- /dev/null
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -0,0 +1,361 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "hardware.h"
+/*
+ * ==================== low level suspend ====================
+ *
+ * Better to follow below rules to use ARM registers:
+ * r0: pm_info structure address;
+ * r1 ~ r4: for saving pm_info members;
+ * r5 ~ r10: free registers;
+ * r11: io base address.
+ *
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ *                              .
+ *                              .
+ *                              .
+ *                              ^
+ *                              ^
+ *                              ^
+ *                      imx6_suspend code
+ *              PM_INFO structure(imx6_cpu_pm_info)
+ * ======================== low address =======================
+ */
+/*
+ * Below offsets are based on struct imx6_cpu_pm_info
+ * which defined in arch/arm/mach-imx/pm-imx6q.c, this
+ * structure contains necessary pm info for low level
+ * suspend related code.
+ */
+#define PM_INFO_PBASE_OFFSET                    0x0
+#define PM_INFO_RESUME_ADDR_OFFSET              0x4
+#define PM_INFO_CPU_TYPE_OFFSET                 0x8
+#define PM_INFO_PM_INFO_SIZE_OFFSET             0xC
+#define PM_INFO_MX6Q_MMDC_P_OFFSET              0x10
+#define PM_INFO_MX6Q_MMDC_V_OFFSET              0x14
+#define PM_INFO_MX6Q_SRC_P_OFFSET               0x18
+#define PM_INFO_MX6Q_SRC_V_OFFSET               0x1C
+#define PM_INFO_MX6Q_IOMUXC_P_OFFSET            0x20
+#define PM_INFO_MX6Q_IOMUXC_V_OFFSET            0x24
+#define PM_INFO_MX6Q_CCM_P_OFFSET               0x28
+#define PM_INFO_MX6Q_CCM_V_OFFSET               0x2C
+#define PM_INFO_MX6Q_GPC_P_OFFSET               0x30
+#define PM_INFO_MX6Q_GPC_V_OFFSET               0x34
+#define PM_INFO_MX6Q_L2_P_OFFSET                0x38
+#define PM_INFO_MX6Q_L2_V_OFFSET                0x3C
+#define PM_INFO_MMDC_IO_NUM_OFFSET              0x40
+#define PM_INFO_MMDC_IO_VAL_OFFSET              0x44
+#define MX6Q_SRC_GPR1   0x20
+#define MX6Q_SRC_GPR2   0x24
+#define MX6Q_MMDC_MAPSR 0x404
+#define MX6Q_MMDC_MPDGCTRL0     0x83c
+#define MX6Q_GPC_IMR1   0x08
+#define MX6Q_GPC_IMR2   0x0c
+#define MX6Q_GPC_IMR3   0x10
+#define MX6Q_GPC_IMR4   0x14
+#define MX6Q_CCM_CCR    0x0
+        .align 3
+        .macro  sync_l2_cache
+        /* sync L2 cache to drain L2's buffers to DRAM. */
+#ifdef CONFIG_CACHE_L2X0
+        ldr     r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
+        mov     r6, #0x0
+        str     r6, [r11, #L2X0_CACHE_SYNC]
+1:
+        ldr     r6, [r11, #L2X0_CACHE_SYNC]
+        ands    r6, r6, #0x1
+        bne     1b
+#endif
+        .endm
+        .macro  resume_mmdc
+        /* restore MMDC IO */
+        cmp     r5, #0x0
+        ldreq   r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+        ldrne   r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
+        ldr     r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
+        ldr     r7, =PM_INFO_MMDC_IO_VAL_OFFSET
+        add     r7, r7, r0
+1:
+        ldr     r8, [r7], #0x4
+        ldr     r9, [r7], #0x4
+        str     r9, [r11, r8]
+        subs    r6, r6, #0x1
+        bne     1b
+        cmp     r5, #0x0
+        ldreq   r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
+        ldrne   r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
+        cmp     r3, #MXC_CPU_IMX6SL
+        bne     4f
+        /* reset read FIFO, RST_RD_FIFO */
+        ldr     r7, =MX6Q_MMDC_MPDGCTRL0
+        ldr     r6, [r11, r7]
+        orr     r6, r6, #(1 << 31)
+        str     r6, [r11, r7]
+2:
+        ldr     r6, [r11, r7]
+        ands    r6, r6, #(1 << 31)
+        bne     2b
+        /* reset FIFO a second time */
+        ldr     r6, [r11, r7]
+        orr     r6, r6, #(1 << 31)
+        str     r6, [r11, r7]
+3:
+        ldr     r6, [r11, r7]
+        ands    r6, r6, #(1 << 31)
+        bne     3b
+4:
+        /* let DDR out of self-refresh */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        bic     r7, r7, #(1 << 21)
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+5:
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        ands    r7, r7, #(1 << 25)
+        bne     5b
+        /* enable DDR auto power saving */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        bic     r7, r7, #0x1
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+        .endm
+ENTRY(imx6_suspend)
+        ldr     r1, [r0, #PM_INFO_PBASE_OFFSET]
+        ldr     r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        ldr     r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
+        /*
+         * counting the resume address in iram
+         * to set it in SRC register.
+         */
+        ldr     r6, =imx6_suspend
+        ldr     r7, =resume
+        sub     r7, r7, r6
+        add     r8, r1, r4
+        add     r9, r8, r7
+        /*
+         * make sure TLB contain the addr we want,
+         * as we will access them after MMDC IO floated.
+         */
+        ldr     r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
+        ldr     r6, [r11, #0x0]
+        ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+        ldr     r6, [r11, #0x0]
+        /* use r11 to store the IO address */
+        ldr     r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
+        /* store physical resume addr and pm_info address. */
+        str     r9, [r11, #MX6Q_SRC_GPR1]
+        str     r1, [r11, #MX6Q_SRC_GPR2]
+        /* need to sync L2 cache before DSM. */
+        sync_l2_cache
+        ldr     r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
+        /*
+         * put DDR explicitly into self-refresh and
+         * disable automatic power savings.
+         */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        orr     r7, r7, #0x1
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+        /* make the DDR explicitly enter self-refresh. */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        orr     r7, r7, #(1 << 21)
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+poll_dvfs_set:
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        ands    r7, r7, #(1 << 25)
+        beq     poll_dvfs_set
+        ldr     r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+        ldr     r6, =0x0
+        ldr     r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
+        ldr     r8, =PM_INFO_MMDC_IO_VAL_OFFSET
+        add     r8, r8, r0
+        /* i.MX6SL's last 3 IOs need special setting */
+        cmp     r3, #MXC_CPU_IMX6SL
+        subeq   r7, r7, #0x3
+set_mmdc_io_lpm:
+        ldr     r9, [r8], #0x8
+        str     r6, [r11, r9]
+        subs    r7, r7, #0x1
+        bne     set_mmdc_io_lpm
+        cmp     r3, #MXC_CPU_IMX6SL
+        bne     set_mmdc_io_lpm_done
+        ldr     r6, =0x1000
+        ldr     r9, [r8], #0x8
+        str     r6, [r11, r9]
+        ldr     r9, [r8], #0x8
+        str     r6, [r11, r9]
+        ldr     r6, =0x80000
+        ldr     r9, [r8]
+        str     r6, [r11, r9]
+set_mmdc_io_lpm_done:
+        /*
+         * mask all GPC interrupts before
+         * enabling the RBC counters to
+         * avoid the counter starting too
+         * early if an interupt is already
+         * pending.
+         */
+        ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+        ldr     r6, [r11, #MX6Q_GPC_IMR1]
+        ldr     r7, [r11, #MX6Q_GPC_IMR2]
+        ldr     r8, [r11, #MX6Q_GPC_IMR3]
+        ldr     r9, [r11, #MX6Q_GPC_IMR4]
+        ldr     r10, =0xffffffff
+        str     r10, [r11, #MX6Q_GPC_IMR1]
+        str     r10, [r11, #MX6Q_GPC_IMR2]
+        str     r10, [r11, #MX6Q_GPC_IMR3]
+        str     r10, [r11, #MX6Q_GPC_IMR4]
+        /*
+         * enable the RBC bypass counter here
+         * to hold off the interrupts. RBC counter
+         * = 32 (1ms), Minimum RBC delay should be
+         * 400us for the analog LDOs to power down.
+         */
+        ldr     r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
+        ldr     r10, [r11, #MX6Q_CCM_CCR]
+        bic     r10, r10, #(0x3f << 21)
+        orr     r10, r10, #(0x20 << 21)
+        str     r10, [r11, #MX6Q_CCM_CCR]
+        /* enable the counter. */
+        ldr     r10, [r11, #MX6Q_CCM_CCR]
+        orr     r10, r10, #(0x1 << 27)
+        str     r10, [r11, #MX6Q_CCM_CCR]
+        /* unmask all the GPC interrupts. */
+        ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+        str     r6, [r11, #MX6Q_GPC_IMR1]
+        str     r7, [r11, #MX6Q_GPC_IMR2]
+        str     r8, [r11, #MX6Q_GPC_IMR3]
+        str     r9, [r11, #MX6Q_GPC_IMR4]
+        /*
+         * now delay for a short while (3usec)
+         * ARM is at 1GHz at this point
+         * so a short loop should be enough.
+         * this delay is required to ensure that
+         * the RBC counter can start counting in
+         * case an interrupt is already pending
+         * or in case an interrupt arrives just
+         * as ARM is about to assert DSM_request.
+         */
+        ldr     r6, =2000
+rbc_loop:
+        subs    r6, r6, #0x1
+        bne     rbc_loop
+        /* Zzz, enter stop mode */
+        wfi
+        nop
+        nop
+        nop
+        nop
+        /*
+         * run to here means there is pending
+         * wakeup source, system should auto
+         * resume, we need to restore MMDC IO first
+         */
+        mov     r5, #0x0
+        resume_mmdc
+        /* return to suspend finish */
+        mov     pc, lr
+resume:
+        /* invalidate L1 I-cache first */
+        mov     r6, #0x0
+        mcr     p15, 0, r6, c7, c5, 0
+        mcr     p15, 0, r6, c7, c5, 6
+        /* enable the Icache and branch prediction */
+        mov     r6, #0x1800
+        mcr     p15, 0, r6, c1, c0, 0
+        isb
+        /* get physical resume address from pm_info. */
+        ldr     lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+        /* clear core0's entry and parameter */
+        ldr     r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
+        mov     r7, #0x0
+        str     r7, [r11, #MX6Q_SRC_GPR1]
+        str     r7, [r11, #MX6Q_SRC_GPR2]
+        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        mov     r5, #0x1
+        resume_mmdc
+        mov     pc, lr
+ENDPROC(imx6_suspend)
+/*
+ * The following code must assume it is running from physical address
+ * where absolute virtual addresses to the data section have to be
+ * turned into relative ones.
+ */
+#ifdef CONFIG_CACHE_L2X0
+        .macro  pl310_resume
+        adr     r0, l2x0_saved_regs_offset
+        ldr     r2, [r0]
+        add     r2, r2, r0
+        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
+        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
+        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
+        mov     r1, #0x1
+        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
+        .endm
+l2x0_saved_regs_offset:
+        .word   l2x0_saved_regs - .
+#else
+        .macro  pl310_resume
+        .endm
+#endif
+ENTRY(v7_cpu_resume)
+        bl      v7_invalidate_l1
+        pl310_resume
+        b       cpu_resume
+ENDPROC(v7_cpu_resume)
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 1a3a5f615770..65222ea0df6d 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -25,6 +25,7 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/sched_clock.h>
@@ -116,11 +117,22 @@ static u64 notrace mxc_read_sched_clock(void)
        return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
 }
+static struct delay_timer imx_delay_timer;
+static unsigned long imx_read_current_timer(void)
+{
+        return __raw_readl(sched_clock_reg);
+}
 static int __init mxc_clocksource_init(struct clk *timer_clk)
 {
        unsigned int c = clk_get_rate(timer_clk);
        void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
+        imx_delay_timer.read_current_timer = &imx_read_current_timer;
+        imx_delay_timer.freq = c;
+        register_current_timer_delay(&imx_delay_timer);
        sched_clock_reg = reg;
        sched_clock_register(mxc_read_sched_clock, 32, c);
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index abeff25532ab..ba43321001d8 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -6,8 +6,8 @@ config ARCH_INTEGRATOR_AP
        bool "Support Integrator/AP and Integrator/PP2 platforms"
        select CLKSRC_MMIO
        select MIGHT_HAVE_PCI
-        select SERIAL_AMBA_PL010
+        select SERIAL_AMBA_PL010 if TTY
-        select SERIAL_AMBA_PL010_CONSOLE
+        select SERIAL_AMBA_PL010_CONSOLE if TTY
        select SOC_BUS
        help
          Include support for the ARM(R) Integrator/AP and
@@ -18,8 +18,8 @@ config ARCH_INTEGRATOR_CP
        select ARCH_CINTEGRATOR
        select ARM_TIMER_SP804
        select PLAT_VERSATILE_CLCD
-        select SERIAL_AMBA_PL011
+        select SERIAL_AMBA_PL011 if TTY
-        select SERIAL_AMBA_PL011_CONSOLE
+        select SERIAL_AMBA_PL011_CONSOLE if TTY
        select SOC_BUS
        help
          Include support for the ARM(R) Integrator CP platform.
@@ -30,6 +30,9 @@ config ARCH_CINTEGRATOR
 config INTEGRATOR_IMPD1
        tristate "Include support for Integrator/IM-PD1"
        depends on ARCH_INTEGRATOR_AP
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_VIC
+        select GPIO_PL061 if GPIOLIB
        help
          The IM-PD1 is an add-on logic module for the Integrator which
          allows ARM(R) Ltd PrimeCells to be developed and evaluated.
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 00ddf20ed91b..e3f3aca43efb 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -25,13 +25,11 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
+#include "hardware.h"
 #include "cm.h"
 #include "common.h"
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/hardware.h
index 306d025d9730..857ca5f8b9a6 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/hardware.h
@@ -1,4 +1,8 @@
 /*
+ *  This file contains the hardware definitions of the Integrator.
+ *
+ *  Copyright (C) 1998-1999 ARM Limited.
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
@@ -13,26 +17,28 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-/**************************************************************************
+#ifndef INTEGRATOR_HARDWARE_H
- * * Copyright © ARM Limited 1998.  All rights reserved.
+#define INTEGRATOR_HARDWARE_H
- * ***********************************************************************/
-/* ************************************************************************
- *
- *   Integrator address map
- *
- * ***********************************************************************/
-#ifndef __address_h
+/*
-#define __address_h                     1
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define IO_BASE                 0xF0000000                 // VA of IO
+#define IO_SIZE                 0x0B000000                 // How much?
+#define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
+/* macro to get at IO space when running virtually */
+#ifdef CONFIG_MMU
+#define IO_ADDRESS(x)   (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
+#else
+#define IO_ADDRESS(x)   (x)
+#endif
-/* ========================================================================
+#define __io_address(n)         ((void __iomem *)IO_ADDRESS(n))
- *  Integrator definitions
- * ========================================================================
+/*
- * ------------------------------------------------------------------------
- *  Memory definitions
- * ------------------------------------------------------------------------
 *  Integrator memory map
- *
 */
 #define INTEGRATOR_BOOT_ROM_LO          0x00000000
 #define INTEGRATOR_BOOT_ROM_HI          0x20000000
@@ -40,13 +46,13 @@
 #define INTEGRATOR_BOOT_ROM_SIZE        SZ_512K
 /*
- *  New Core Modules have different amounts of SSRAM, the amount of SSRAM
+ * New Core Modules have different amounts of SSRAM, the amount of SSRAM
- *  fitted can be found in HDR_STAT.
+ * fitted can be found in HDR_STAT.
 *
- *  The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
+ * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
- *  the minimum amount of SSRAM fitted on any core module.
+ * the minimum amount of SSRAM fitted on any core module.
 *
- *  New Core Modules also alias the SSRAM.
+ * New Core Modules also alias the SSRAM.
 *
 */
 #define INTEGRATOR_SSRAM_BASE           0x00000000
@@ -61,7 +67,6 @@
 /*
 *  SDRAM is a SIMM therefore the size is not known.
- *
 */
 #define INTEGRATOR_SDRAM_BASE           0x00040000
@@ -81,10 +86,8 @@
 #define INTEGRATOR_LOGIC_MODULE2_BASE   0xE0000000
 #define INTEGRATOR_LOGIC_MODULE3_BASE   0xF0000000
-/* ------------------------------------------------------------------------
+/*
- *  Integrator header card registers
+ * Integrator header card registers
- * ------------------------------------------------------------------------
- *
 */
 #define INTEGRATOR_HDR_ID_OFFSET        0x00
 #define INTEGRATOR_HDR_PROC_OFFSET      0x04
@@ -173,16 +176,12 @@
 #define INTEGRATOR_HDR_SDRAM_SPD_OK     (1 << 5)
+/*
-/* ------------------------------------------------------------------------
+ * Integrator system registers
- *  Integrator system registers
- * ------------------------------------------------------------------------
- *
 */
 /*
 *  System Controller
- *
 */
 #define INTEGRATOR_SC_ID_OFFSET         0x00
 #define INTEGRATOR_SC_OSC_OFFSET        0x04
@@ -223,7 +222,6 @@
 /*
 *  External Bus Interface
- *
 */
 #define INTEGRATOR_EBI_BASE             0x12000000
@@ -272,7 +270,6 @@
 /*
 *  LED's & Switches
- *
 */
 #define INTEGRATOR_DBG_ALPHA_OFFSET     0x00
 #define INTEGRATOR_DBG_LEDS_OFFSET      0x04
@@ -292,32 +289,25 @@
 #define INTEGRATOR_CP_SIC_BASE          0xCA000000      /* SIC */
 #define INTEGRATOR_CP_CTL_BASE          0xCB000000      /* CP system control */
-/* ------------------------------------------------------------------------
- *  KMI keyboard/mouse definitions
- * ------------------------------------------------------------------------
- */
 /* PS2 Keyboard interface */
 #define KMI0_BASE                       INTEGRATOR_KBD_BASE
 /* PS2 Mouse interface */
 #define KMI1_BASE                       INTEGRATOR_MOUSE_BASE
-/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
+/*
+ * Integrator Interrupt Controllers
-/* ------------------------------------------------------------------------
- *  Integrator Interrupt Controllers
- * ------------------------------------------------------------------------
 *
- *  Offsets from interrupt controller base
 *
- *  System Controller interrupt controller base is
+ * Offsets from interrupt controller base
+ *
+ * System Controller interrupt controller base is
 *
 *      INTEGRATOR_IC_BASE + (header_number << 6)
 *
- *  Core Module interrupt controller base is
+ * Core Module interrupt controller base is
 *
 *      INTEGRATOR_HDR_IC
- *
 */
 #define IRQ_STATUS                      0
 #define IRQ_RAW_STATUS                  0x04
@@ -335,25 +325,8 @@
 #define FIQ_ENABLE_CLEAR                0x2C
-/* ------------------------------------------------------------------------
+/*
- *  Interrupts
+ * LED's
- * ------------------------------------------------------------------------
- *
- *
- *  Each Core Module has two interrupts controllers, one on the core module
- *  itself and one in the system controller on the motherboard.  The
- *  READ_INT macro in target.s reads both interrupt controllers and returns
- *  a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
- *  and bits 24 to 31 are from the core module.
- *
- *  The following definitions relate to the bitmask returned by READ_INT.
- *
- */
-/* ------------------------------------------------------------------------
- *  LED's
- * ------------------------------------------------------------------------
- *
 */
 #define GREEN_LED                       0x01
 #define YELLOW_LED                      0x02
@@ -371,7 +344,6 @@
 *
 *  Timer 0 runs at bus frequency
 */
 #define INTEGRATOR_TIMER0_BASE          INTEGRATOR_CT_BASE
 #define INTEGRATOR_TIMER1_BASE          (INTEGRATOR_CT_BASE + 0x100)
 #define INTEGRATOR_TIMER2_BASE          (INTEGRATOR_CT_BASE + 0x200)
@@ -379,4 +351,4 @@
 #define INTEGRATOR_CSR_BASE             0x10000000
 #define INTEGRATOR_CSR_SIZE             0x10000000
-#endif
+#endif /* INTEGRATOR_HARDWARE_H */
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 9f82f9dcbb98..0e870ea818c4 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -23,10 +23,11 @@
 #include <linux/io.h>
 #include <linux/platform_data/clk-integrator.h>
 #include <linux/slab.h>
+#include <linux/irqchip/arm-vic.h>
-#include <mach/lm.h>
-#include <mach/impd1.h>
 #include <asm/sizes.h>
+#include "lm.h"
+#include "impd1.h"
 static int module_id;
@@ -35,6 +36,7 @@ MODULE_PARM_DESC(lmid, "logic module stack position");
 struct impd1_module {
        void __iomem    *base;
+        void __iomem    *vic_base;
 };
 void impd1_tweak_control(struct device *dev, u32 mask, u32 val)
@@ -262,9 +264,6 @@ struct impd1_device {
 static struct impd1_device impd1_devs[] = {
        {
-                .offset = 0x03000000,
-                .id     = 0x00041190,
-        }, {
                .offset = 0x00100000,
                .irq    = { 1 },
                .id     = 0x00141011,
@@ -304,46 +303,72 @@ static struct impd1_device impd1_devs[] = {
        }
 };
-static int impd1_probe(struct lm_device *dev)
+/*
+ * Valid IRQs: 0 thru 9 and 11, 10 unused.
+ */
+#define IMPD1_VALID_IRQS 0x00000bffU
+static int __init impd1_probe(struct lm_device *dev)
 {
        struct impd1_module *impd1;
-        int i, ret;
+        int irq_base;
+        int i;
        if (dev->id != module_id)
                return -EINVAL;
-        if (!request_mem_region(dev->resource.start, SZ_4K, "LM registers"))
+        if (!devm_request_mem_region(&dev->dev, dev->resource.start,
+                                     SZ_4K, "LM registers"))
                return -EBUSY;
-        impd1 = kzalloc(sizeof(struct impd1_module), GFP_KERNEL);
+        impd1 = devm_kzalloc(&dev->dev, sizeof(struct impd1_module),
-        if (!impd1) {
+                             GFP_KERNEL);
-                ret = -ENOMEM;
+        if (!impd1)
-                goto release_lm;
+                return -ENOMEM;
-        }
-        impd1->base = ioremap(dev->resource.start, SZ_4K);
+        impd1->base = devm_ioremap(&dev->dev, dev->resource.start, SZ_4K);
-        if (!impd1->base) {
+        if (!impd1->base)
-                ret = -ENOMEM;
+                return -ENOMEM;
-                goto free_impd1;
-        }
-        lm_set_drvdata(dev, impd1);
+        integrator_impd1_clk_init(impd1->base, dev->id);
-        printk("IM-PD1 found at 0x%08lx\n",
+        if (!devm_request_mem_region(&dev->dev,
-                (unsigned long)dev->resource.start);
+                                     dev->resource.start + 0x03000000,
+                                     SZ_4K, "VIC"))
+                return -EBUSY;
-        integrator_impd1_clk_init(impd1->base, dev->id);
+        impd1->vic_base = devm_ioremap(&dev->dev,
+                                       dev->resource.start + 0x03000000,
+                                       SZ_4K);
+        if (!impd1->vic_base)
+                return -ENOMEM;
+        irq_base = vic_init_cascaded(impd1->vic_base, dev->irq,
+                                     IMPD1_VALID_IRQS, 0);
+        lm_set_drvdata(dev, impd1);
+        dev_info(&dev->dev, "IM-PD1 found at 0x%08lx\n",
+                 (unsigned long)dev->resource.start);
        for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) {
                struct impd1_device *idev = impd1_devs + i;
                struct amba_device *d;
                unsigned long pc_base;
                char devname[32];
+                int irq1 = idev->irq[0];
+                int irq2 = idev->irq[1];
+                /* Translate IRQs to IM-PD1 local numberspace */
+                if (irq1)
+                        irq1 += irq_base;
+                if (irq2)
+                        irq2 += irq_base;
                pc_base = dev->resource.start + idev->offset;
                snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
                d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K,
-                                            dev->irq, dev->irq,
+                                            irq1, irq2,
                                            idev->platform_data, idev->id,
                                            &dev->resource);
                if (IS_ERR(d)) {
@@ -353,14 +378,6 @@ static int impd1_probe(struct lm_device *dev)
        }
        return 0;
- free_impd1:
-        if (impd1 && impd1->base)
-                iounmap(impd1->base);
-        kfree(impd1);
- release_lm:
-        release_mem_region(dev->resource.start, SZ_4K);
-        return ret;
 }
 static int impd1_remove_one(struct device *dev, void *data)
@@ -371,16 +388,10 @@ static int impd1_remove_one(struct device *dev, void *data)
 static void impd1_remove(struct lm_device *dev)
 {
-        struct impd1_module *impd1 = lm_get_drvdata(dev);
        device_for_each_child(&dev->dev, NULL, impd1_remove_one);
        integrator_impd1_clk_exit(dev->id);
        lm_set_drvdata(dev, NULL);
-        iounmap(impd1->base);
-        kfree(impd1);
-        release_mem_region(dev->resource.start, SZ_4K);
 }
 static struct lm_driver impd1_driver = {
diff --git a/arch/arm/mach-integrator/include/mach/impd1.h b/arch/arm/mach-integrator/impd1.h
index d75de4b14237..76de4dc9bee4 100644
--- a/arch/arm/mach-integrator/include/mach/impd1.h
+++ b/arch/arm/mach-integrator/impd1.h
@@ -1,6 +1,3 @@
-#define IMPD1_OSC1      0x00
-#define IMPD1_OSC2      0x04
-#define IMPD1_LOCK      0x08
 #define IMPD1_LEDS      0x0c
 #define IMPD1_INT       0x10
 #define IMPD1_SW        0x14
@@ -15,4 +12,3 @@
 struct device;
 void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
deleted file mode 100644
index 65fed7c0eb84..000000000000
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/hardware.h
- *
- *  This file contains the hardware definitions of the Integrator.
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-#include <asm/sizes.h>
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define IO_BASE                 0xF0000000                 // VA of IO 
-#define IO_SIZE                 0x0B000000                 // How much?
-#define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
-/* macro to get at IO space when running virtually */
-#ifdef CONFIG_MMU
-#define IO_ADDRESS(x)   (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
-#else
-#define IO_ADDRESS(x)   (x)
-#endif
-#define __io_address(n)         ((void __iomem *)IO_ADDRESS(n))
-#endif
diff --git a/arch/arm/mach-integrator/include/mach/timex.h b/arch/arm/mach-integrator/include/mach/timex.h
deleted file mode 100644
index 1dcb42028c82..000000000000
--- a/arch/arm/mach-integrator/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/timex.h
- *
- *  Integrator architecture timex specifications
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * ??
- */
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 17c0fe627435..dd0cc677d596 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -42,24 +42,23 @@
 #include <linux/sys_soc.h>
 #include <linux/termios.h>
 #include <linux/sched_clock.h>
+#include <linux/clk-provider.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/setup.h>
 #include <asm/param.h>          /* HZ */
 #include <asm/mach-types.h>
-#include <mach/lm.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include "hardware.h"
 #include "cm.h"
 #include "common.h"
 #include "pci_v3.h"
+#include "lm.h"
 /* Base address to the AP system controller */
 void __iomem *ap_syscon_base;
@@ -358,7 +357,7 @@ static struct clock_event_device integrator_clockevent = {
 static struct irqaction integrator_timer_irq = {
        .name           = "timer",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = integrator_timer_interrupt,
        .dev_id         = &integrator_clockevent,
 };
@@ -402,10 +401,7 @@ static void __init ap_of_timer_init(void)
        struct clk *clk;
        unsigned long rate;
-        clk = clk_get_sys("ap_timer", NULL);
+        of_clk_init(NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        rate = clk_get_rate(clk);
        err = of_property_read_string(of_aliases,
                                "arm,timer-primary", &path);
@@ -415,6 +411,12 @@ static void __init ap_of_timer_init(void)
        base = of_iomap(node, 0);
        if (WARN_ON(!base))
                return;
+        clk = of_clk_get(node, 0);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        rate = clk_get_rate(clk);
        writel(0, base + TIMER_CTRL);
        integrator_clocksource_init(rate, base);
@@ -427,6 +429,12 @@ static void __init ap_of_timer_init(void)
        if (WARN_ON(!base))
                return;
        irq = irq_of_parse_and_map(node, 0);
+        clk = of_clk_get(node, 0);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        rate = clk_get_rate(clk);
        writel(0, base + TIMER_CTRL);
        integrator_clockevent_init(rate, base, irq);
 }
@@ -440,7 +448,6 @@ static void __init ap_init_irq_of(void)
 {
        cm_init();
        of_irq_init(fpga_irq_of_match);
-        integrator_clk_init(false);
 }
 /* For the Device Tree, add in the UART callbacks as AUXDATA */
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index a3ef961e4a93..a938242b0c95 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -23,31 +23,22 @@
 #include <linux/irqchip/versatile-fpga.h>
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
-#include <linux/platform_data/clk-integrator.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/sys_soc.h>
+#include <linux/sched_clock.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/icst.h>
-#include <mach/lm.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/hardware/timer-sp.h>
 #include <plat/clcd.h>
-#include <plat/sched_clock.h>
+#include "hardware.h"
 #include "cm.h"
 #include "common.h"
@@ -234,11 +225,14 @@ static struct clcd_board clcd_data = {
 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
+static u64 notrace intcp_read_sched_clock(void)
+{
+        return readl(REFCOUNTER);
+}
 static void __init intcp_init_early(void)
 {
-#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
+        sched_clock_register(intcp_read_sched_clock, 32, 24000000);
-        versatile_sched_clock_init(REFCOUNTER, 24000000);
-#endif
 }
 static const struct of_device_id fpga_irq_of_match[] __initconst = {
@@ -250,7 +244,6 @@ static void __init intcp_init_irq_of(void)
 {
        cm_init();
        of_irq_init(fpga_irq_of_match);
-        integrator_clk_init(true);
 }
 /*
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index cb6ac58f5e07..f1dcb57a59e2 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -11,9 +11,7 @@
 #include <linux/slab.h>
 #include <linux/leds.h>
-#include <mach/hardware.h>
+#include "hardware.h"
-#include <mach/platform.h>
 #include "cm.h"
 #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
diff --git a/arch/arm/mach-integrator/lm.c b/arch/arm/mach-integrator/lm.c
index f52c7af31eaa..3f9e9f043168 100644
--- a/arch/arm/mach-integrator/lm.c
+++ b/arch/arm/mach-integrator/lm.c
@@ -12,7 +12,7 @@
 #include <linux/device.h>
 #include <linux/slab.h>
-#include <mach/lm.h>
+#include "lm.h"
 #define to_lm_device(d) container_of(d, struct lm_device, dev)
 #define to_lm_driver(d) container_of(d, struct lm_driver, drv)
diff --git a/arch/arm/mach-integrator/include/mach/lm.h b/arch/arm/mach-integrator/lm.h
index 28186b6f2c09..28186b6f2c09 100644
--- a/arch/arm/mach-integrator/include/mach/lm.h
+++ b/arch/arm/mach-integrator/lm.h
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index c5e01b24d9fb..05e1f73a1e8d 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -34,15 +34,13 @@
 #include <linux/of_pci.h>
 #include <video/vga.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
 #include <asm/mach/map.h>
 #include <asm/signal.h>
 #include <asm/mach/pci.h>
 #include <asm/irq_regs.h>
 #include "pci_v3.h"
+#include "hardware.h"
 /*
 * Where in the memory map does PCI live?
diff --git a/arch/arm/mach-iop13xx/include/mach/timex.h b/arch/arm/mach-iop13xx/include/mach/timex.h
deleted file mode 100644
index 45fb2745bb54..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/timex.h
+++ /dev/null
@@ -1 +0,0 @@
-#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-iop32x/include/mach/timex.h b/arch/arm/mach-iop32x/include/mach/timex.h
deleted file mode 100644
index 7262ab81419d..000000000000
--- a/arch/arm/mach-iop32x/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/timex.h
- *
- * IOP32x architecture timex specifications
- */
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-iop33x/include/mach/timex.h b/arch/arm/mach-iop33x/include/mach/timex.h
deleted file mode 100644
index 54c589091d6e..000000000000
--- a/arch/arm/mach-iop33x/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/timex.h
- *
- * IOP3xx architecture timex specifications
- */
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 200970d56f6d..4977296f0c78 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -315,33 +315,6 @@ static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *r
        return 0;
 }
-static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
-{
-        return (dma_addr + size) >= SZ_64M;
-}
-/*
- * Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
- */
-static int ixp4xx_pci_platform_notify(struct device *dev)
-{
-        if (dev_is_pci(dev)) {
-                *dev->dma_mask =  SZ_64M - 1;
-                dev->coherent_dma_mask = SZ_64M - 1;
-                dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
-        }
-        return 0;
-}
-static int ixp4xx_pci_platform_notify_remove(struct device *dev)
-{
-        if (dev_is_pci(dev))
-                dmabounce_unregister_dev(dev);
-        return 0;
-}
 void __init ixp4xx_pci_preinit(void)
 {
        unsigned long cpuid = read_cpuid_id();
@@ -475,20 +448,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
-        platform_notify = ixp4xx_pci_platform_notify;
-        platform_notify_remove = ixp4xx_pci_platform_notify_remove;
        return 1;
 }
-int dma_set_coherent_mask(struct device *dev, u64 mask)
-{
-        if (mask >= SZ_64M - 1)
-                return 0;
-        return -EIO;
-}
 EXPORT_SYMBOL(ixp4xx_pci_read);
 EXPORT_SYMBOL(ixp4xx_pci_write);
-EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6d68aed6548a..fc4b7b24265e 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -23,15 +23,14 @@
 #include <linux/interrupt.h>
 #include <linux/bitops.h>
 #include <linux/time.h>
-#include <linux/timex.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/io.h>
 #include <linux/export.h>
 #include <linux/gpio.h>
 #include <linux/cpu.h>
+#include <linux/pci.h>
 #include <linux/sched_clock.h>
 #include <mach/udc.h>
 #include <mach/hardware.h>
 #include <mach/io.h>
@@ -40,11 +39,21 @@
 #include <asm/page.h>
 #include <asm/irq.h>
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
+#define IXP4XX_TIMER_FREQ 66666000
+/*
+ * The timer register doesn't allow to specify the two least significant bits of
+ * the timeout value and assumes them being zero. So make sure IXP4XX_LATCH is
+ * the best value with the two least significant bits unset.
+ */
+#define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, \
+                                       (IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \
+                        (IXP4XX_OST_RELOAD_MASK + 1)
 static void __init ixp4xx_clocksource_init(void);
 static void __init ixp4xx_clockevent_init(void);
 static struct clock_event_device clockevent_ixp4xx;
@@ -312,7 +321,7 @@ static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 static struct irqaction ixp4xx_timer_irq = {
        .name           = "timer1",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = ixp4xx_timer_interrupt,
        .dev_id         = &clockevent_ixp4xx,
 };
@@ -520,7 +529,7 @@ static void ixp4xx_set_mode(enum clock_event_mode mode,
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
-                osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
+                osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
                opts = IXP4XX_OST_ENABLE;
                break;
        case CLOCK_EVT_MODE_ONESHOT:
@@ -578,6 +587,54 @@ void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
        }
 }
+#ifdef CONFIG_PCI
+static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
+{
+        return (dma_addr + size) > SZ_64M;
+}
+static int ixp4xx_platform_notify_remove(struct device *dev)
+{
+        if (dev_is_pci(dev))
+                dmabounce_unregister_dev(dev);
+        return 0;
+}
+#endif
+/*
+ * Setup DMA mask to 64MB on PCI devices and 4 GB on all other things.
+ */
+static int ixp4xx_platform_notify(struct device *dev)
+{
+        dev->dma_mask = &dev->coherent_dma_mask;
+#ifdef CONFIG_PCI
+        if (dev_is_pci(dev)) {
+                dev->coherent_dma_mask = DMA_BIT_MASK(28); /* 64 MB */
+                dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
+                return 0;
+        }
+#endif
+        dev->coherent_dma_mask = DMA_BIT_MASK(32);
+        return 0;
+}
+int dma_set_coherent_mask(struct device *dev, u64 mask)
+{
+        if (dev_is_pci(dev))
+                mask &= DMA_BIT_MASK(28); /* 64 MB */
+        if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) {
+                dev->coherent_dma_mask = mask;
+                return 0;
+        }
+        return -EIO;            /* device wanted sub-64MB mask */
+}
+EXPORT_SYMBOL(dma_set_coherent_mask);
 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
 /*
 * In the case of using indirect PCI, we simply return the actual PCI
@@ -600,12 +657,16 @@ static void ixp4xx_iounmap(void __iomem *addr)
        if (!is_pci_memory((__force u32)addr))
                __iounmap(addr);
 }
+#endif
 void __init ixp4xx_init_early(void)
 {
+        platform_notify = ixp4xx_platform_notify;
+#ifdef CONFIG_PCI
+        platform_notify_remove = ixp4xx_platform_notify_remove;
+#endif
+#ifdef CONFIG_IXP4XX_INDIRECT_PCI
        arch_ioremap_caller = ixp4xx_ioremap_caller;
        arch_iounmap = ixp4xx_iounmap;
-}
-#else
-void __init ixp4xx_init_early(void) {}
 #endif
+}
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 736dc692d540..43ee06d3abe5 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -233,8 +233,7 @@ static int __init dsmg600_gpio_init(void)
        gpio_request(DSMG600_RB_GPIO, "reset button");
        if (request_irq(gpio_to_irq(DSMG600_RB_GPIO), &dsmg600_reset_handler,
-                IRQF_DISABLED | IRQF_TRIGGER_LOW,
+                IRQF_TRIGGER_LOW, "DSM-G600 reset button", NULL) < 0) {
-                "DSM-G600 reset button", NULL) < 0) {
                printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
                        gpio_to_irq(DSMG600_RB_GPIO));
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 429966b756ed..5c4b0c4a1b37 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -208,16 +208,14 @@ static void __init fsg_init(void)
        platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
        if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler,
-                        IRQF_DISABLED | IRQF_TRIGGER_LOW,
+                        IRQF_TRIGGER_LOW, "FSG reset button", NULL) < 0) {
-                        "FSG reset button", NULL) < 0) {
                printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
                        gpio_to_irq(FSG_RB_GPIO));
        }
        if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler,
-                        IRQF_DISABLED | IRQF_TRIGGER_LOW,
+                        IRQF_TRIGGER_LOW, "FSG power button", NULL) < 0) {
-                        "FSG power button", NULL) < 0) {
                printk(KERN_DEBUG "Power Button IRQ %d not available\n",
                        gpio_to_irq(FSG_SB_GPIO));
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index e54ff491c105..80bd9d6d04de 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -4,6 +4,7 @@
 */
 #include <linux/delay.h>
+#include <linux/gpio.h>
 #include <linux/hdlc.h>
 #include <linux/i2c-gpio.h>
 #include <linux/io.h>
@@ -79,19 +80,19 @@ static u8 control_value;
 static void set_scl(u8 value)
 {
-        gpio_line_set(GPIO_SCL, !!value);
+        gpio_set_value(GPIO_SCL, !!value);
        udelay(3);
 }
 static void set_sda(u8 value)
 {
-        gpio_line_set(GPIO_SDA, !!value);
+        gpio_set_value(GPIO_SDA, !!value);
        udelay(3);
 }
 static void set_str(u8 value)
 {
-        gpio_line_set(GPIO_STR, !!value);
+        gpio_set_value(GPIO_STR, !!value);
        udelay(3);
 }
@@ -108,8 +109,8 @@ static void output_control(void)
 {
        int i;
-        gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
+        gpio_direction_output(GPIO_SCL, 1);
-        gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
+        gpio_direction_output(GPIO_SDA, 1);
        for (i = 0; i < 8; i++) {
                set_scl(0);
@@ -151,8 +152,8 @@ static int hss_set_clock(int port, unsigned int clock_type)
 static irqreturn_t hss_dcd_irq(int irq, void *pdev)
 {
-        int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
+        int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
-        gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
+        int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
        set_carrier_cb_tab[port](pdev, !i);
        return IRQ_HANDLED;
 }
@@ -168,7 +169,7 @@ static int hss_open(int port, void *pdev,
        else
                irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
-        gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
+        i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
        set_carrier_cb(pdev, !i);
        set_carrier_cb_tab[!!port] = set_carrier_cb;
@@ -181,7 +182,7 @@ static int hss_open(int port, void *pdev,
        set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
        output_control();
-        gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
+        gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
        return 0;
 }
@@ -193,7 +194,7 @@ static void hss_close(int port, void *pdev)
        set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
        output_control();
-        gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
+        gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
 }
@@ -413,13 +414,21 @@ static void __init gmlr_init(void)
        if (hw_bits & CFG_HW_HAS_EEPROM)
                device_tab[devices++] = &device_i2c; /* max index 6 */
-        gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
+        gpio_request(GPIO_SCL, "SCL/clock");
-        gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
+        gpio_request(GPIO_SDA, "SDA/data");
-        gpio_line_config(GPIO_STR, IXP4XX_GPIO_OUT);
+        gpio_request(GPIO_STR, "strobe");
-        gpio_line_config(GPIO_HSS0_RTS_N, IXP4XX_GPIO_OUT);
+        gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS");
-        gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
+        gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS");
-        gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
+        gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD");
-        gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
+        gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD");
+        gpio_direction_output(GPIO_SCL, 1);
+        gpio_direction_output(GPIO_SDA, 1);
+        gpio_direction_output(GPIO_STR, 0);
+        gpio_direction_output(GPIO_HSS0_RTS_N, 1);
+        gpio_direction_output(GPIO_HSS1_RTS_N, 1);
+        gpio_direction_input(GPIO_HSS0_DCD_N);
+        gpio_direction_input(GPIO_HSS1_DCD_N);
        irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
        irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 5cf30d1b78d2..559c69a47731 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -48,9 +48,10 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
 * fallback to the default.
 */
+extern unsigned long pcibios_min_mem;
 static inline int is_pci_memory(u32 addr)
 {
-        return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
+        return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF);
 }
 #define writeb(v, p)                    __indirect_writeb(v, p)
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
deleted file mode 100644
index 0396d89f947c..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/timex.h
- * 
- */
-#include <mach/ixp4xx-regs.h>
-/*
- * We use IXP425 General purpose timer for our timer needs, it runs at 
- * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
- * timer register ignores the bottom 2 bits of the LATCH value.
- */
-#define IXP4XX_TIMER_FREQ 66666000
-#define CLOCK_TICK_RATE \
-        (((IXP4XX_TIMER_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 507cb5233537..4e0f762bc651 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -295,8 +295,7 @@ static void __init nas100d_init(void)
        pm_power_off = nas100d_power_off;
        if (request_irq(gpio_to_irq(NAS100D_RB_GPIO), &nas100d_reset_handler,
-                IRQF_DISABLED | IRQF_TRIGGER_LOW,
+                IRQF_TRIGGER_LOW, "NAS100D reset button", NULL) < 0) {
-                "NAS100D reset button", NULL) < 0) {
                printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
                        gpio_to_irq(NAS100D_RB_GPIO));
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index ba5f1cda2a9d..88c025f52d8d 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -265,16 +265,14 @@ static void __init nslu2_init(void)
        pm_power_off = nslu2_power_off;
        if (request_irq(gpio_to_irq(NSLU2_RB_GPIO), &nslu2_reset_handler,
-                IRQF_DISABLED | IRQF_TRIGGER_LOW,
+                IRQF_TRIGGER_LOW, "NSLU2 reset button", NULL) < 0) {
-                "NSLU2 reset button", NULL) < 0) {
                printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
                        gpio_to_irq(NSLU2_RB_GPIO));
        }
        if (request_irq(gpio_to_irq(NSLU2_PB_GPIO), &nslu2_power_handler,
-                IRQF_DISABLED | IRQF_TRIGGER_HIGH,
+                IRQF_TRIGGER_HIGH, "NSLU2 power button", NULL) < 0) {
-                "NSLU2 power button", NULL) < 0) {
                printk(KERN_DEBUG "Power Button IRQ %d not available\n",
                        gpio_to_irq(NSLU2_PB_GPIO));
diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c
index 75ef03dc9964..2d494b454376 100644
--- a/arch/arm/mach-ixp4xx/omixp-setup.c
+++ b/arch/arm/mach-ixp4xx/omixp-setup.c
@@ -17,9 +17,7 @@
 #include <linux/serial_8250.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
-#ifdef CONFIG_LEDS_CLASS
 #include <linux/leds.h>
-#endif
 #include <asm/setup.h>
 #include <asm/memory.h>
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 90a708fef541..f50bc936cb84 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -1,13 +1,9 @@
 config ARCH_KEYSTONE
        bool "Texas Instruments Keystone Devices"
        depends on ARCH_MULTI_V7
-        select CPU_V7
        select ARM_GIC
        select HAVE_ARM_ARCH_TIMER
-        select HAVE_SMP
        select CLKSRC_MMIO
-        select GENERIC_CLOCKEVENTS
-        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_ERRATA_798181 if SMP
        select COMMON_CLK_KEYSTONE
        select ARCH_SUPPORTS_BIG_ENDIAN
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index 6e6bb7d5ea30..e0b9e1b9cf30 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -46,7 +46,7 @@ static void __init keystone_init(void)
 }
 static const char *keystone_match[] __initconst = {
-        "ti,keystone-evm",
+        "ti,keystone",
        NULL,
 };
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index fe8319ad3158..df4b26340ae4 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -106,13 +106,6 @@ config ARCH_KIRKWOOD_DT
          Say 'Y' here if you want your kernel to support the
          Marvell Kirkwood using flattened device tree.
-config MACH_MV88F6281GTW_GE_DT
-        bool "Marvell 88F6281 GTW GE Board (Flattened Device Tree)"
-        depends on ARCH_KIRKWOOD_DT
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell 88F6281 GTW GE Board (Flattened Device Tree).
 endmenu
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 144b51102939..3a72c5c6e747 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,5 +1,4 @@
-obj-y                           += common.o pcie.o
+obj-$(CONFIG_KIRKWOOD_LEGACY)   += irq.o mpp.o common.o pcie.o
-obj-$(CONFIG_KIRKWOOD_LEGACY)   += irq.o mpp.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
@@ -13,4 +12,3 @@ obj-$(CONFIG_MACH_TS219)		+= ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
-obj-$(CONFIG_MACH_MV88F6281GTW_GE_DT)   += board-mv88f6281gtw_ge.o
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 78188159484d..2801da49e2a3 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -19,11 +19,84 @@
 #include <linux/of_platform.h>
 #include <linux/dma-mapping.h>
 #include <linux/irqchip.h>
-#include <linux/kexec.h>
+#include <asm/hardware/cache-feroceon-l2.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <mach/bridge-regs.h>
 #include <plat/common.h>
-#include "common.h"
+#include <plat/pcie.h>
+#include "pm.h"
+static struct map_desc kirkwood_io_desc[] __initdata = {
+        {
+                .virtual        = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
+                .length         = KIRKWOOD_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+static void __init kirkwood_map_io(void)
+{
+        iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
+}
+static struct resource kirkwood_cpufreq_resources[] = {
+        [0] = {
+                .start  = CPU_CONTROL_PHYS,
+                .end    = CPU_CONTROL_PHYS + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device kirkwood_cpufreq_device = {
+        .name           = "kirkwood-cpufreq",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(kirkwood_cpufreq_resources),
+        .resource       = kirkwood_cpufreq_resources,
+};
+static void __init kirkwood_cpufreq_init(void)
+{
+        platform_device_register(&kirkwood_cpufreq_device);
+}
+static struct resource kirkwood_cpuidle_resource[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+                .start  = DDR_OPERATION_BASE,
+                .end    = DDR_OPERATION_BASE + 3,
+        },
+};
+static struct platform_device kirkwood_cpuidle = {
+        .name           = "kirkwood_cpuidle",
+        .id             = -1,
+        .resource       = kirkwood_cpuidle_resource,
+        .num_resources  = 1,
+};
+static void __init kirkwood_cpuidle_init(void)
+{
+        platform_device_register(&kirkwood_cpuidle);
+}
+/* Temporary here since mach-mvebu has a function we can use */
+static void kirkwood_restart(enum reboot_mode mode, const char *cmd)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+        while (1)
+                ;
+}
 #define MV643XX_ETH_MAC_ADDR_LOW        0x0414
 #define MV643XX_ETH_MAC_ADDR_HIGH       0x0418
@@ -104,35 +177,35 @@ eth_fixup_skip:
        }
 }
-static void __init kirkwood_dt_init(void)
+/*
+ * Disable propagation of mbus errors to the CPU local bus, as this
+ * causes mbus errors (which can occur for example for PCI aborts) to
+ * throw CPU aborts, which we're not set up to deal with.
+ */
+static void __init kirkwood_disable_mbus_error_propagation(void)
 {
-        pr_info("Kirkwood: %s.\n", kirkwood_id());
+        void __iomem *cpu_config;
-        /*
+        cpu_config = ioremap(CPU_CONFIG_PHYS, 4);
-         * Disable propagation of mbus errors to the CPU local bus,
+        writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config);
-         * as this causes mbus errors (which can occur for example
+        iounmap(cpu_config);
-         * for PCI aborts) to throw CPU aborts, which we're not set
+}
-         * up to deal with.
-         */
-        writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
-        BUG_ON(mvebu_mbus_dt_init());
+static void __init kirkwood_dt_init(void)
+{
+        kirkwood_disable_mbus_error_propagation();
-        kirkwood_l2_init();
+        BUG_ON(mvebu_mbus_dt_init());
+#ifdef CONFIG_CACHE_FEROCEON_L2
+        feroceon_of_init();
+#endif
        kirkwood_cpufreq_init();
        kirkwood_cpuidle_init();
        kirkwood_pm_init();
        kirkwood_dt_eth_fixup();
-#ifdef CONFIG_KEXEC
-        kexec_reinit = kirkwood_enable_pcie;
-#endif
-        if (of_machine_is_compatible("marvell,mv88f6281gtw-ge"))
-                mv88f6281gtw_ge_init();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c b/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c
deleted file mode 100644
index ee5eea678c11..000000000000
--- a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c
- *
- * Marvell 88F6281 GTW GE Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/timer.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <linux/gpio.h>
-#include <net/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <mach/kirkwood.h>
-#include "common.h"
-static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_NONE,
-        .speed          = SPEED_1000,
-        .duplex         = DUPLEX_FULL,
-};
-static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = {
-        .port_names[0]  = "lan1",
-        .port_names[1]  = "lan2",
-        .port_names[2]  = "lan3",
-        .port_names[3]  = "lan4",
-        .port_names[4]  = "wan",
-        .port_names[5]  = "cpu",
-};
-static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = {
-        .nr_chips       = 1,
-        .chip           = &mv88f6281gtw_ge_switch_chip_data,
-};
-void __init mv88f6281gtw_ge_init(void)
-{
-        kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data);
-        kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ);
-}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index f3407a5db216..255f33a3903c 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -25,10 +25,10 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-feroceon-l2.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
 #include <linux/platform_data/asoc-kirkwood.h>
-#include <plat/cache-feroceon-l2.h>
 #include <linux/platform_data/mmc-mvsdio.h>
 #include <linux/platform_data/mtd-orion_nand.h>
 #include <linux/platform_data/usb-ehci-orion.h>
@@ -36,6 +36,7 @@
 #include <plat/time.h>
 #include <linux/platform_data/dma-mv_xor.h>
 #include "common.h"
+#include "pm.h"
 /* These can go away once Kirkwood uses the mvebu-mbus DT binding */
 #define KIRKWOOD_MBUS_NAND_TARGET 0x01
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05fd648df543..832a4e2ab8d7 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -58,19 +58,6 @@ void kirkwood_cpufreq_init(void);
 void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
-#ifdef CONFIG_PM
-void kirkwood_pm_init(void);
-#else
-static inline void kirkwood_pm_init(void) {};
-#endif
-/* board init functions for boards not fully converted to fdt */
-#ifdef CONFIG_MACH_MV88F6281GTW_GE_DT
-void mv88f6281gtw_ge_init(void);
-#else
-static inline void mv88f6281gtw_ge_init(void) {};
-#endif
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 8b9d1c9ff199..1c37082c8b39 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -14,6 +14,7 @@
 #include <mach/kirkwood.h>
 #define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0100)
+#define CPU_CONFIG_PHYS         (BRIDGE_PHYS_BASE + 0x0100)
 #define CPU_CONFIG_ERROR_PROP   0x00000004
 #define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
@@ -21,6 +22,7 @@
 #define CPU_RESET               0x00000002
 #define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
+#define RSTOUTn_MASK_PHYS       (BRIDGE_PHYS_BASE + 0x0108)
 #define SOFT_RESET_OUT_EN       0x00000004
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
@@ -79,5 +81,6 @@
 #define CGC_RESERVED            (0x6 << 21)
 #define MEMORY_PM_CTRL          (BRIDGE_VIRT_BASE + 0x118)
+#define MEMORY_PM_CTRL_PHYS     (BRIDGE_PHYS_BASE + 0x118)
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/timex.h b/arch/arm/mach-kirkwood/include/mach/timex.h
deleted file mode 100644
index c923cd169b9c..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/timex.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/timex.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c
index c6ab8d9303a5..8e5e0329d04c 100644
--- a/arch/arm/mach-kirkwood/pm.c
+++ b/arch/arm/mach-kirkwood/pm.c
@@ -21,15 +21,16 @@
 #include "common.h"
 static void __iomem *ddr_operation_base;
+static void __iomem *memory_pm_ctrl;
 static void kirkwood_low_power(void)
 {
        u32 mem_pm_ctrl;
-        mem_pm_ctrl = readl(MEMORY_PM_CTRL);
+        mem_pm_ctrl = readl(memory_pm_ctrl);
        /* Set peripherals to low-power mode */
-        writel_relaxed(~0, MEMORY_PM_CTRL);
+        writel_relaxed(~0, memory_pm_ctrl);
        /* Set DDR in self-refresh */
        writel_relaxed(0x7, ddr_operation_base);
@@ -41,7 +42,7 @@ static void kirkwood_low_power(void)
         */
        cpu_do_idle();
-        writel_relaxed(mem_pm_ctrl, MEMORY_PM_CTRL);
+        writel_relaxed(mem_pm_ctrl, memory_pm_ctrl);
 }
 static int kirkwood_suspend_enter(suspend_state_t state)
@@ -69,5 +70,7 @@ static const struct platform_suspend_ops kirkwood_suspend_ops = {
 void __init kirkwood_pm_init(void)
 {
        ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
+        memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4);
        suspend_set_ops(&kirkwood_suspend_ops);
 }
diff --git a/arch/arm/mach-kirkwood/pm.h b/arch/arm/mach-kirkwood/pm.h
new file mode 100644
index 000000000000..21e7530f368b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/pm.h
@@ -0,0 +1,26 @@
+/*
+ * Power Management driver for Marvell Kirkwood SoCs
+ *
+ * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com>
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License,
+ * version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ARCH_KIRKWOOD_PM_H
+#define __ARCH_KIRKWOOD_PM_H
+#ifdef CONFIG_PM
+void kirkwood_pm_init(void);
+#else
+static inline void kirkwood_pm_init(void) {};
+#endif
+#endif
diff --git a/arch/arm/mach-ks8695/board-og.c b/arch/arm/mach-ks8695/board-og.c
index 002bc619bb68..f2658168eeff 100644
--- a/arch/arm/mach-ks8695/board-og.c
+++ b/arch/arm/mach-ks8695/board-og.c
@@ -44,7 +44,8 @@ static void __init og_register_pci(void)
        if (machine_is_im4004())
                ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_LOW);
-        ks8695_init_pci(&og_pci);
+        if (IS_ENABLED(CONFIG_PCI))
+                ks8695_init_pci(&og_pci);
 }
 /*
diff --git a/arch/arm/mach-ks8695/include/mach/timex.h b/arch/arm/mach-ks8695/include/mach/timex.h
deleted file mode 100644
index 10f716371bd3..000000000000
--- a/arch/arm/mach-ks8695/include/mach/timex.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/timex.h
- *
- * Copyright (C) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * KS8695 - Time Parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-#include <mach/hardware.h>
-#define CLOCK_TICK_RATE         KS8695_CLOCK_RATE
-#endif
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 426c97662f5b..a197874bf382 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -122,7 +122,7 @@ static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
 static struct irqaction ks8695_timer_irq = {
        .name           = "ks8695_tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .flags          = IRQF_TIMER,
        .handler        = ks8695_timer_interrupt,
 };
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index d7aa54c25c59..de03620d7fa7 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -99,6 +99,7 @@ u32 lpc32xx_return_iram_size(void)
        return iram_size;
 }
+EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size);
 /*
 * Computes PLL rate from PLL register and input clock
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index 20eab63d10ba..4e5837299c04 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -90,7 +90,7 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
 static struct irqaction lpc32xx_timer_irq = {
        .name           = "LPC32XX Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = lpc32xx_timer_interrupt,
 };
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 0c002099c3a3..7e0248582efd 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -231,7 +231,7 @@ static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
        .debounce_interval      = 30,
 };
-#if defined(CONFIG_USB_EHCI_MV)
+#if IS_ENABLED(CONFIG_USB_EHCI_MV)
 static struct mv_usb_platform_data pxa168_sph_pdata = {
        .mode           = MV_USB_MODE_HOST,
        .phy_init       = pxa_usb_phy_init,
@@ -258,7 +258,7 @@ static void __init common_init(void)
        /* off-chip devices */
        platform_device_register(&smc91x_device);
-#if defined(CONFIG_USB_EHCI_MV)
+#if IS_ENABLED(CONFIG_USB_EHCI_MV)
        pxa168_add_usb_host(&pxa168_sph_pdata);
 #endif
 }
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
index dd2d8b103cc8..2bcb766af05d 100644
--- a/arch/arm/mach-mmp/devices.c
+++ b/arch/arm/mach-mmp/devices.c
@@ -72,7 +72,7 @@ int __init pxa_register_device(struct pxa_device_desc *desc,
        return platform_device_add(pdev);
 }
-#if defined(CONFIG_USB) || defined(CONFIG_USB_GADGET)
+#if IS_ENABLED(CONFIG_USB) || IS_ENABLED(CONFIG_USB_GADGET)
 /*****************************************************************************
 * The registers read/write routines
@@ -112,9 +112,9 @@ static void u2o_write(void __iomem *base, unsigned int offset,
        readl_relaxed(base + offset);
 }
-#if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV)
+#if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV)
-#if defined(CONFIG_CPU_PXA910) || defined(CONFIG_CPU_PXA168)
+#if IS_ENABLED(CONFIG_CPU_PXA910) || IS_ENABLED(CONFIG_CPU_PXA168)
 static DEFINE_MUTEX(phy_lock);
 static int phy_init_cnt;
@@ -238,10 +238,10 @@ void pxa_usb_phy_deinit(void __iomem *phy_reg)
 #endif
 #endif
-#ifdef CONFIG_USB_SUPPORT
+#if IS_ENABLED(CONFIG_USB_SUPPORT)
 static u64 usb_dma_mask = ~(u32)0;
-#ifdef CONFIG_USB_MV_UDC
+#if IS_ENABLED(CONFIG_USB_MV_UDC)
 struct resource pxa168_u2o_resources[] = {
        /* regbase */
        [0] = {
@@ -276,7 +276,7 @@ struct platform_device pxa168_device_u2o = {
 };
 #endif /* CONFIG_USB_MV_UDC */
-#ifdef CONFIG_USB_EHCI_MV_U2O
+#if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
 struct resource pxa168_u2oehci_resources[] = {
        /* regbase */
        [0] = {
@@ -312,7 +312,7 @@ struct platform_device pxa168_device_u2oehci = {
 };
 #endif
-#if defined(CONFIG_USB_MV_OTG)
+#if IS_ENABLED(CONFIG_USB_MV_OTG)
 struct resource pxa168_u2ootg_resources[] = {
        /* regbase */
        [0] = {
diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h
deleted file mode 100644
index 70c9f1d88c02..000000000000
--- a/arch/arm/mach-mmp/include/mach/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/timex.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifdef CONFIG_CPU_MMP2
-#define CLOCK_TICK_RATE         6500000
-#else
-#define CLOCK_TICK_RATE         3250000
-#endif
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 024022d91fe3..2756351dbb35 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -39,6 +39,12 @@
 #include "clock.h"
+#ifdef CONFIG_CPU_MMP2
+#define MMP_CLOCK_FREQ          6500000
+#else
+#define MMP_CLOCK_FREQ          3250000
+#endif
 #define TIMERS_VIRT_BASE        TIMERS1_VIRT_BASE
 #define MAX_DELTA               (0xfffffffe)
@@ -186,7 +192,7 @@ static void __init timer_config(void)
 static struct irqaction timer_irq = {
        .name           = "timer",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = timer_interrupt,
        .dev_id         = &ckevt,
 };
@@ -195,14 +201,14 @@ void __init timer_init(int irq)
 {
        timer_config();
-        sched_clock_register(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
+        sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ);
        ckevt.cpumask = cpumask_of(0);
        setup_irq(irq, &timer_irq);
-        clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
+        clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ);
-        clockevents_config_and_register(&ckevt, CLOCK_TICK_RATE,
+        clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ,
                                        MIN_DELTA, MAX_DELTA);
 }
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index cfadd974f5ce..ac4af81de3ea 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -164,8 +164,8 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = {
        },
 };
-#ifdef CONFIG_USB_SUPPORT
+#if IS_ENABLED(CONFIG_USB_SUPPORT)
-#if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV_U2O)
+#if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
 static struct mv_usb_platform_data ttc_usb_pdata = {
        .vbus           = NULL,
@@ -178,14 +178,14 @@ static struct mv_usb_platform_data ttc_usb_pdata = {
 #endif
 #endif
-#ifdef CONFIG_MTD_NAND_PXA3xx
+#if IS_ENABLED(CONFIG_MTD_NAND_PXA3xx)
 static struct pxa3xx_nand_platform_data dkb_nand_info = {
        .enable_arbiter = 1,
        .num_cs = 1,
 };
 #endif
-#ifdef CONFIG_MMP_DISP
+#if IS_ENABLED(CONFIG_MMP_DISP)
 /* path config */
 #define CFG_IOPADMODE(iopad)   (iopad)  /* 0x0 ~ 0xd */
 #define SCLK_SOURCE_SELECT(x)  (x << 30) /* 0x0 ~ 0x3 */
@@ -275,7 +275,7 @@ static void __init ttc_dkb_init(void)
        /* on-chip devices */
        pxa910_add_uart(1);
-#ifdef CONFIG_MTD_NAND_PXA3xx
+#if IS_ENABLED(CONFIG_MTD_NAND_PXA3xx)
        pxa910_add_nand(&dkb_nand_info);
 #endif
@@ -285,22 +285,22 @@ static void __init ttc_dkb_init(void)
                                 sizeof(struct pxa_gpio_platform_data));
        platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
-#ifdef CONFIG_USB_MV_UDC
+#if IS_ENABLED(CONFIG_USB_MV_UDC)
        pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata;
        platform_device_register(&pxa168_device_u2o);
 #endif
-#ifdef CONFIG_USB_EHCI_MV_U2O
+#if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
        pxa168_device_u2oehci.dev.platform_data = &ttc_usb_pdata;
        platform_device_register(&pxa168_device_u2oehci);
 #endif
-#ifdef CONFIG_USB_MV_OTG
+#if IS_ENABLED(CONFIG_USB_MV_OTG)
        pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
        platform_device_register(&pxa168_device_u2ootg);
 #endif
-#ifdef CONFIG_MMP_DISP
+#if IS_ENABLED(CONFIG_MMP_DISP)
        add_disp();
 #endif
 }
diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig
index 3795ae28a613..82a4ba8578a2 100644
--- a/arch/arm/mach-moxart/Kconfig
+++ b/arch/arm/mach-moxart/Kconfig
@@ -1,15 +1,10 @@
 config ARCH_MOXART
-        bool "MOXA ART SoC" if ARCH_MULTI_V4T
+        bool "MOXA ART SoC" if ARCH_MULTI_V4
        select CPU_FA526
        select ARM_DMA_MEM_BUFFERABLE
-        select USE_OF
-        select CLKSRC_OF
        select CLKSRC_MMIO
-        select HAVE_CLK
-        select COMMON_CLK
        select GENERIC_IRQ_CHIP
        select ARCH_REQUIRE_GPIOLIB
-        select GENERIC_CLOCKEVENTS
        select PHYLIB if NETDEVICES
        help
          Say Y here if you want to run your kernel on hardware with a
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 9625cf378931..a7f959e58c3d 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,50 +1,9 @@
-config ARCH_MSM
-        bool
-config ARCH_MSM_DT
-        bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7
-        select ARCH_MSM
-        select ARCH_REQUIRE_GPIOLIB
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
-        help
-          Support for Qualcomm's devicetree based MSM systems.
 if ARCH_MSM
-menu "Qualcomm MSM SoC Selection"
-        depends on ARCH_MSM_DT
-config ARCH_MSM8X60
-        bool "Enable support for MSM8X60"
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
-        select MSM_SCM if SMP
-        select MSM_TIMER
-config ARCH_MSM8960
-        bool "Enable support for MSM8960"
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
-        select MSM_SCM if SMP
-        select MSM_TIMER
-config ARCH_MSM8974
-        bool "Enable support for MSM8974"
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_ARM_ARCH_TIMER
-        select HAVE_SMP
-        select MSM_SCM if SMP
-endmenu
 choice
        prompt "Qualcomm MSM SoC Type"
        default ARCH_MSM7X00A
-        depends on ARCH_MSM_NODT
+        depends on ARCH_MSM
 config ARCH_MSM7X00A
        bool "MSM7x00A / MSM7x01A"
@@ -54,7 +13,7 @@ config ARCH_MSM7X00A
        select MACH_TROUT if !MACH_HALIBUT
        select MSM_PROC_COMM
        select MSM_SMD
-        select MSM_TIMER
+        select CLKSRC_QCOM
        select MSM_SMD_PKG3
 config ARCH_MSM7X30
@@ -66,7 +25,7 @@ config ARCH_MSM7X30
        select MSM_GPIOMUX
        select MSM_PROC_COMM
        select MSM_SMD
-        select MSM_TIMER
+        select CLKSRC_QCOM
        select MSM_VIC
 config ARCH_QSD8X50
@@ -78,7 +37,7 @@ config ARCH_QSD8X50
        select MSM_GPIOMUX
        select MSM_PROC_COMM
        select MSM_SMD
-        select MSM_TIMER
+        select CLKSRC_QCOM
        select MSM_VIC
 endchoice
@@ -99,7 +58,7 @@ config  MSM_VIC
        bool
 menu "Qualcomm MSM Board Type"
-        depends on ARCH_MSM_NODT
+        depends on ARCH_MSM
 config MACH_HALIBUT
        depends on ARCH_MSM
@@ -153,7 +112,4 @@ config MSM_GPIOMUX
 config MSM_SCM
        bool
-config MSM_TIMER
-        bool
 endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 8e307a10d3c3..27c078a568df 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,4 +1,3 @@
-obj-$(CONFIG_MSM_TIMER) += timer.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
@@ -14,18 +13,11 @@ obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
-obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
-CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
 obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
-obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o
 obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index 33c7725adae2..572479a3c7be 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -23,9 +23,6 @@ extern void msm_map_qsd8x50_io(void);
 extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                          unsigned int mtype, void *caller);
-extern struct smp_operations msm_smp_ops;
-extern void msm_cpu_die(unsigned int cpu);
 struct msm_mmc_platform_data;
 extern void msm_add_devices(void);
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index f8f6adfa07c6..fb9762464718 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 #include <linux/interrupt.h>
 #include <linux/completion.h>
+#include <linux/module.h>
 #include <mach/dma.h>
 #include <mach/msm_iomap.h>
@@ -77,6 +78,7 @@ void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful)
 {
        writel((graceful << 31), DMOV_FLUSH0(id));
 }
+EXPORT_SYMBOL_GPL(msm_dmov_stop_cmd);
 void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd)
 {
@@ -115,6 +117,7 @@ void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd)
        }
        spin_unlock_irqrestore(&msm_dmov_lock, irq_flags);
 }
+EXPORT_SYMBOL_GPL(msm_dmov_enqueue_cmd);
 struct msm_dmov_exec_cmdptr_cmd {
        struct msm_dmov_cmd dmov_cmd;
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
deleted file mode 100644
index 6c62c3f82fe6..000000000000
--- a/arch/arm/mach-msm/headsmp.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-/*
- * MSM specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(msm_secondary_startup)
-        mrc     p15, 0, r0, c0, c0, 5
-        and     r0, r0, #15
-        adr     r4, 1f
-        ldmia   r4, {r5, r6}
-        sub     r4, r4, r5
-        add     r6, r6, r4
-pen:    ldr     r7, [r6]
-        cmp     r7, r0
-        bne     pen
-        /*
-         * we've been released from the holding pen: secondary_stack
-         * should now contain the SVC stack for this core
-         */
-        b       secondary_startup
-ENDPROC(msm_secondary_startup)
-        .align
-1:      .long   .
-        .long   pen_release
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
deleted file mode 100644
index 326a87261f9a..000000000000
--- a/arch/arm/mach-msm/hotplug.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <asm/smp_plat.h>
-#include "common.h"
-static inline void cpu_enter_lowpower(void)
-{
-}
-static inline void cpu_leave_lowpower(void)
-{
-}
-static inline void platform_do_lowpower(unsigned int cpu)
-{
-        /* Just enter wfi for now. TODO: Properly shut off the cpu. */
-        for (;;) {
-                /*
-                 * here's the WFI
-                 */
-                asm("wfi"
-                    :
-                    :
-                    : "memory", "cc");
-                if (pen_release == cpu_logical_map(cpu)) {
-                        /*
-                         * OK, proper wakeup, we're done
-                         */
-                        break;
-                }
-                /*
-                 * getting here, means that we have come out of WFI without
-                 * having been woken up - this shouldn't happen
-                 *
-                 * The trouble is, letting people know about this is not really
-                 * possible, since we are currently running incoherently, and
-                 * therefore cannot safely call printk() or anything else
-                 */
-                pr_debug("CPU%u: spurious wakeup call\n", cpu);
-        }
-}
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void __ref msm_cpu_die(unsigned int cpu)
-{
-        /*
-         * we're ready for shutdown now, so do it
-         */
-        cpu_enter_lowpower();
-        platform_do_lowpower(cpu);
-        /*
-         * bring this CPU back into the world of cache
-         * coherency, and then restore interrupts
-         */
-        cpu_leave_lowpower();
-}
diff --git a/arch/arm/mach-msm/include/mach/timex.h b/arch/arm/mach-msm/include/mach/timex.h
deleted file mode 100644
index a62e6b215aec..000000000000
--- a/arch/arm/mach-msm/include/mach/timex.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-msm/include/mach/timex.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_MSM_TIMEX_H
-#define __ASM_ARCH_MSM_TIMEX_H
-#define CLOCK_TICK_RATE         1000000
-#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index adc8971c7266..34e09474636d 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -78,8 +78,10 @@ void __init msm_map_common_io(void)
        asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
                defined(CONFIG_DEBUG_MSM_UART3)
+#ifdef CONFIG_MMU
        debug_ll_addr(&msm_io_desc[size - 1].pfn,
                      &msm_io_desc[size - 1].virtual);
+#endif
        msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
 #endif
        iotable_init(msm_io_desc, size);
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
deleted file mode 100644
index f10a1f58fde9..000000000000
--- a/arch/arm/mach-msm/platsmp.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-#include <asm/cacheflush.h>
-#include <asm/cputype.h>
-#include <asm/mach-types.h>
-#include <asm/smp_plat.h>
-#include "scm-boot.h"
-#include "common.h"
-#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
-#define SCSS_CPU1CORE_RESET 0xD80
-#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
-extern void msm_secondary_startup(void);
-static DEFINE_SPINLOCK(boot_lock);
-static inline int get_core_count(void)
-{
-        /* 1 + the PART[1:0] field of MIDR */
-        return ((read_cpuid_id() >> 4) & 3) + 1;
-}
-static void msm_secondary_init(unsigned int cpu)
-{
-        /*
-         * let the primary processor know we're out of the
-         * pen, then head off into the C entry point
-         */
-        pen_release = -1;
-        smp_wmb();
-        /*
-         * Synchronise with the boot thread.
-         */
-        spin_lock(&boot_lock);
-        spin_unlock(&boot_lock);
-}
-static void prepare_cold_cpu(unsigned int cpu)
-{
-        int ret;
-        ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
-                                SCM_FLAG_COLDBOOT_CPU1);
-        if (ret == 0) {
-                void __iomem *sc1_base_ptr;
-                sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
-                if (sc1_base_ptr) {
-                        writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
-                        writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
-                        writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
-                        iounmap(sc1_base_ptr);
-                }
-        } else
-                printk(KERN_DEBUG "Failed to set secondary core boot "
-                                  "address\n");
-}
-static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        unsigned long timeout;
-        static int cold_boot_done;
-        /* Only need to bring cpu out of reset this way once */
-        if (cold_boot_done == false) {
-                prepare_cold_cpu(cpu);
-                cold_boot_done = true;
-        }
-        /*
-         * set synchronisation state between this boot processor
-         * and the secondary one
-         */
-        spin_lock(&boot_lock);
-        /*
-         * The secondary processor is waiting to be released from
-         * the holding pen - release it, then wait for it to flag
-         * that it has been released by resetting pen_release.
-         *
-         * Note that "pen_release" is the hardware CPU ID, whereas
-         * "cpu" is Linux's internal ID.
-         */
-        pen_release = cpu_logical_map(cpu);
-        sync_cache_w(&pen_release);
-        /*
-         * Send the secondary CPU a soft interrupt, thereby causing
-         * the boot monitor to read the system wide flags register,
-         * and branch to the address found there.
-         */
-        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout)) {
-                smp_rmb();
-                if (pen_release == -1)
-                        break;
-                udelay(10);
-        }
-        /*
-         * now the secondary core is starting up let it run its
-         * calibrations, then wait for it to finish
-         */
-        spin_unlock(&boot_lock);
-        return pen_release != -1 ? -ENOSYS : 0;
-}
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system. The msm8x60
- * does not support the ARM SCU, so just set the possible cpu mask to
- * NR_CPUS.
- */
-static void __init msm_smp_init_cpus(void)
-{
-        unsigned int i, ncores = get_core_count();
-        if (ncores > nr_cpu_ids) {
-                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-                        ncores, nr_cpu_ids);
-                ncores = nr_cpu_ids;
-        }
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
-{
-}
-struct smp_operations msm_smp_ops __initdata = {
-        .smp_init_cpus          = msm_smp_init_cpus,
-        .smp_prepare_cpus       = msm_smp_prepare_cpus,
-        .smp_secondary_init     = msm_secondary_init,
-        .smp_boot_secondary     = msm_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_die                = msm_cpu_die,
-#endif
-};
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
deleted file mode 100644
index fd1644987534..000000000000
--- a/arch/arm/mach-msm/timer.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/cpu.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/sched_clock.h>
-#include <asm/mach/time.h>
-#include "common.h"
-#define TIMER_MATCH_VAL                 0x0000
-#define TIMER_COUNT_VAL                 0x0004
-#define TIMER_ENABLE                    0x0008
-#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
-#define TIMER_ENABLE_EN                 BIT(0)
-#define TIMER_CLEAR                     0x000C
-#define DGT_CLK_CTL                     0x10
-#define DGT_CLK_CTL_DIV_4               0x3
-#define TIMER_STS_GPT0_CLR_PEND         BIT(10)
-#define GPT_HZ 32768
-#define MSM_DGT_SHIFT 5
-static void __iomem *event_base;
-static void __iomem *sts_base;
-static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-        /* Stop the timer tick */
-        if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
-                u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
-                ctrl &= ~TIMER_ENABLE_EN;
-                writel_relaxed(ctrl, event_base + TIMER_ENABLE);
-        }
-        evt->event_handler(evt);
-        return IRQ_HANDLED;
-}
-static int msm_timer_set_next_event(unsigned long cycles,
-                                    struct clock_event_device *evt)
-{
-        u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
-        ctrl &= ~TIMER_ENABLE_EN;
-        writel_relaxed(ctrl, event_base + TIMER_ENABLE);
-        writel_relaxed(ctrl, event_base + TIMER_CLEAR);
-        writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
-        if (sts_base)
-                while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
-                        cpu_relax();
-        writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
-        return 0;
-}
-static void msm_timer_set_mode(enum clock_event_mode mode,
-                              struct clock_event_device *evt)
-{
-        u32 ctrl;
-        ctrl = readl_relaxed(event_base + TIMER_ENABLE);
-        ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
-        switch (mode) {
-        case CLOCK_EVT_MODE_RESUME:
-        case CLOCK_EVT_MODE_PERIODIC:
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                /* Timer is enabled in set_next_event */
-                break;
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                break;
-        }
-        writel_relaxed(ctrl, event_base + TIMER_ENABLE);
-}
-static struct clock_event_device __percpu *msm_evt;
-static void __iomem *source_base;
-static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
-{
-        return readl_relaxed(source_base + TIMER_COUNT_VAL);
-}
-static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
-{
-        /*
-         * Shift timer count down by a constant due to unreliable lower bits
-         * on some targets.
-         */
-        return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
-}
-static struct clocksource msm_clocksource = {
-        .name   = "dg_timer",
-        .rating = 300,
-        .read   = msm_read_timer_count,
-        .mask   = CLOCKSOURCE_MASK(32),
-        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-static int msm_timer_irq;
-static int msm_timer_has_ppi;
-static int msm_local_timer_setup(struct clock_event_device *evt)
-{
-        int cpu = smp_processor_id();
-        int err;
-        evt->irq = msm_timer_irq;
-        evt->name = "msm_timer";
-        evt->features = CLOCK_EVT_FEAT_ONESHOT;
-        evt->rating = 200;
-        evt->set_mode = msm_timer_set_mode;
-        evt->set_next_event = msm_timer_set_next_event;
-        evt->cpumask = cpumask_of(cpu);
-        clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
-        if (msm_timer_has_ppi) {
-                enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
-        } else {
-                err = request_irq(evt->irq, msm_timer_interrupt,
-                                IRQF_TIMER | IRQF_NOBALANCING |
-                                IRQF_TRIGGER_RISING, "gp_timer", evt);
-                if (err)
-                        pr_err("request_irq failed\n");
-        }
-        return 0;
-}
-static void msm_local_timer_stop(struct clock_event_device *evt)
-{
-        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
-        disable_percpu_irq(evt->irq);
-}
-static int msm_timer_cpu_notify(struct notifier_block *self,
-                                           unsigned long action, void *hcpu)
-{
-        /*
-         * Grab cpu pointer in each case to avoid spurious
-         * preemptible warnings
-         */
-        switch (action & ~CPU_TASKS_FROZEN) {
-        case CPU_STARTING:
-                msm_local_timer_setup(this_cpu_ptr(msm_evt));
-                break;
-        case CPU_DYING:
-                msm_local_timer_stop(this_cpu_ptr(msm_evt));
-                break;
-        }
-        return NOTIFY_OK;
-}
-static struct notifier_block msm_timer_cpu_nb = {
-        .notifier_call = msm_timer_cpu_notify,
-};
-static u64 notrace msm_sched_clock_read(void)
-{
-        return msm_clocksource.read(&msm_clocksource);
-}
-static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
-                                  bool percpu)
-{
-        struct clocksource *cs = &msm_clocksource;
-        int res = 0;
-        msm_timer_irq = irq;
-        msm_timer_has_ppi = percpu;
-        msm_evt = alloc_percpu(struct clock_event_device);
-        if (!msm_evt) {
-                pr_err("memory allocation failed for clockevents\n");
-                goto err;
-        }
-        if (percpu)
-                res = request_percpu_irq(irq, msm_timer_interrupt,
-                                         "gp_timer", msm_evt);
-        if (res) {
-                pr_err("request_percpu_irq failed\n");
-        } else {
-                res = register_cpu_notifier(&msm_timer_cpu_nb);
-                if (res) {
-                        free_percpu_irq(irq, msm_evt);
-                        goto err;
-                }
-                /* Immediately configure the timer on the boot CPU */
-                msm_local_timer_setup(__this_cpu_ptr(msm_evt));
-        }
-err:
-        writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
-        res = clocksource_register_hz(cs, dgt_hz);
-        if (res)
-                pr_err("clocksource_register failed\n");
-        sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
-}
-#ifdef CONFIG_OF
-static void __init msm_dt_timer_init(struct device_node *np)
-{
-        u32 freq;
-        int irq;
-        struct resource res;
-        u32 percpu_offset;
-        void __iomem *base;
-        void __iomem *cpu0_base;
-        base = of_iomap(np, 0);
-        if (!base) {
-                pr_err("Failed to map event base\n");
-                return;
-        }
-        /* We use GPT0 for the clockevent */
-        irq = irq_of_parse_and_map(np, 1);
-        if (irq <= 0) {
-                pr_err("Can't get irq\n");
-                return;
-        }
-        /* We use CPU0's DGT for the clocksource */
-        if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
-                percpu_offset = 0;
-        if (of_address_to_resource(np, 0, &res)) {
-                pr_err("Failed to parse DGT resource\n");
-                return;
-        }
-        cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
-        if (!cpu0_base) {
-                pr_err("Failed to map source base\n");
-                return;
-        }
-        if (of_property_read_u32(np, "clock-frequency", &freq)) {
-                pr_err("Unknown frequency\n");
-                return;
-        }
-        event_base = base + 0x4;
-        sts_base = base + 0x88;
-        source_base = cpu0_base + 0x24;
-        freq /= 4;
-        writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
-        msm_timer_init(freq, 32, irq, !!percpu_offset);
-}
-CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
-CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
-#endif
-static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
-                                u32 sts)
-{
-        void __iomem *base;
-        base = ioremap(addr, SZ_256);
-        if (!base) {
-                pr_err("Failed to map timer base\n");
-                return -ENOMEM;
-        }
-        event_base = base + event;
-        source_base = base + source;
-        if (sts)
-                sts_base = base + sts;
-        return 0;
-}
-void __init msm7x01_timer_init(void)
-{
-        struct clocksource *cs = &msm_clocksource;
-        if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
-                return;
-        cs->read = msm_read_timer_count_shift;
-        cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
-        /* 600 KHz */
-        msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
-                        false);
-}
-void __init msm7x30_timer_init(void)
-{
-        if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
-                return;
-        msm_timer_init(24576000 / 4, 32, 1, false);
-}
-void __init qsd8x50_timer_init(void)
-{
-        if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
-                return;
-        msm_timer_init(19200000 / 4, 32, 7, false);
-}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 75062eff2494..e6ac679bece9 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -15,11 +15,11 @@
 #include <linux/ata_platform.h>
 #include <linux/clk-provider.h>
 #include <linux/ethtool.h>
+#include <asm/hardware/cache-feroceon-l2.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/mv78xx0.h>
 #include <mach/bridge-regs.h>
-#include <plat/cache-feroceon-l2.h>
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <linux/platform_data/mtd-orion_nand.h>
 #include <plat/time.h>
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index 5f03484584d4..e20d6da234a6 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -15,6 +15,7 @@
 #define L2_WRITETHROUGH         0x00020000
 #define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
+#define RSTOUTn_MASK_PHYS       (BRIDGE_PHYS_BASE + 0x0108)
 #define SOFT_RESET_OUT_EN       0x00000004
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
diff --git a/arch/arm/mach-mv78xx0/include/mach/timex.h b/arch/arm/mach-mv78xx0/include/mach/timex.h
deleted file mode 100644
index 0e8c443c723a..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/timex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/timex.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 5e269d7263ce..3f73eecbcfb0 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,51 +1,109 @@
 config ARCH_MVEBU
-        bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+        bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V5)
        select ARCH_SUPPORTS_BIG_ENDIAN
        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
        select IRQ_DOMAIN
-        select MULTI_IRQ_HANDLER
        select PINCTRL
        select PLAT_ORION
-        select SPARSE_IRQ
-        select CLKDEV_LOOKUP
        select MVEBU_MBUS
        select ZONE_DMA if ARM_LPAE
        select ARCH_REQUIRE_GPIOLIB
        select MIGHT_HAVE_PCI
        select PCI_QUIRKS if PCI
+        select OF_ADDRESS_PCI
 if ARCH_MVEBU
-menu "Marvell SOC with device tree"
+menu "Marvell EBU SoC variants"
-config MACH_ARMADA_370_XP
+config MACH_MVEBU_V7
        bool
        select ARMADA_370_XP_TIMER
-        select HAVE_SMP
        select CACHE_L2X0
-        select CPU_PJ4B
 config MACH_ARMADA_370
-        bool "Marvell Armada 370 boards"
+        bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
        select ARMADA_370_CLK
-        select MACH_ARMADA_370_XP
+        select CPU_PJ4B
+        select MACH_MVEBU_V7
        select PINCTRL_ARMADA_370
        help
          Say 'Y' here if you want your kernel to support boards based
          on the Marvell Armada 370 SoC with device tree.
+config MACH_ARMADA_375
+        bool "Marvell Armada 375 boards" if ARCH_MULTI_V7
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_753970
+        select ARM_GIC
+        select ARMADA_375_CLK
+        select CPU_V7
+        select MACH_MVEBU_V7
+        select PINCTRL_ARMADA_375
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada 375 SoC with device tree.
+config MACH_ARMADA_38X
+        bool "Marvell Armada 380/385 boards" if ARCH_MULTI_V7
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_753970
+        select ARM_GIC
+        select ARMADA_38X_CLK
+        select CPU_V7
+        select MACH_MVEBU_V7
+        select PINCTRL_ARMADA_38X
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada 380/385 SoC with device tree.
 config MACH_ARMADA_XP
-        bool "Marvell Armada XP boards"
+        bool "Marvell Armada XP boards" if ARCH_MULTI_V7
        select ARMADA_XP_CLK
-        select MACH_ARMADA_370_XP
+        select CPU_PJ4B
+        select MACH_MVEBU_V7
        select PINCTRL_ARMADA_XP
        help
          Say 'Y' here if you want your kernel to support boards based
          on the Marvell Armada XP SoC with device tree.
+config MACH_DOVE
+        bool "Marvell Dove boards" if ARCH_MULTI_V7
+        select CACHE_L2X0
+        select CPU_PJ4
+        select DOVE_CLK
+        select ORION_IRQCHIP
+        select ORION_TIMER
+        select PINCTRL_DOVE
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Dove using flattened device tree.
+config MACH_KIRKWOOD
+        bool "Marvell Kirkwood boards" if ARCH_MULTI_V5
+        select ARCH_HAS_CPUFREQ
+        select ARCH_REQUIRE_GPIOLIB
+        select CPU_FEROCEON
+        select KIRKWOOD_CLK
+        select OF_IRQ
+        select ORION_IRQCHIP
+        select ORION_TIMER
+        select PCI
+        select PCI_QUIRKS
+        select PINCTRL_KIRKWOOD
+        select USE_OF
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Kirkwood device tree.
+config MACH_T5325
+        bool "HP T5325 thin client"
+        depends on MACH_KIRKWOOD
+        help
+          Say 'Y' here if you want your kernel to support the
+          HP T5325 Thin client
 endmenu
 endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 878aebe98dcc..a63e43b6b451 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -4,7 +4,10 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 AFLAGS_coherency_ll.o           := -Wa,-march=armv7-a
 obj-y                            += system-controller.o mvebu-soc-id.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
+obj-$(CONFIG_MACH_MVEBU_V7)      += board-v7.o
+obj-$(CONFIG_MACH_DOVE)          += dove.o
 obj-$(CONFIG_ARCH_MVEBU)         += coherency.o coherency_ll.o pmsu.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
+obj-$(CONFIG_MACH_KIRKWOOD)      += kirkwood.o kirkwood-pm.o
+obj-$(CONFIG_MACH_T5325)         += board-t5325.o
diff --git a/arch/arm/mach-mvebu/board-t5325.c b/arch/arm/mach-mvebu/board-t5325.c
new file mode 100644
index 000000000000..65ace6db9f28
--- /dev/null
+++ b/arch/arm/mach-mvebu/board-t5325.c
@@ -0,0 +1,41 @@
+/*
+ * HP T5325 Board Setup
+ *
+ * Copyright (C) 2014
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <sound/alc5623.h>
+#include "board.h"
+static struct platform_device hp_t5325_audio_device = {
+        .name           = "t5325-audio",
+        .id             = -1,
+};
+static struct alc5623_platform_data alc5621_data = {
+        .add_ctrl = 0x3700,
+        .jack_det_ctrl = 0x4810,
+};
+static struct i2c_board_info i2c_board_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("alc5621", 0x1a),
+                .platform_data = &alc5621_data,
+        },
+};
+void __init t5325_init(void)
+{
+        i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
+        platform_device_register(&hp_t5325_audio_device);
+}
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/board-v7.c
index f6c9d1d85c14..333fca8fdc41 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -21,6 +21,7 @@
 #include <linux/clocksource.h>
 #include <linux/dma-mapping.h>
 #include <linux/mbus.h>
+#include <linux/signal.h>
 #include <linux/slab.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -31,12 +32,28 @@
 #include "coherency.h"
 #include "mvebu-soc-id.h"
-static void __init armada_370_xp_map_io(void)
+/*
+ * Early versions of Armada 375 SoC have a bug where the BootROM
+ * leaves an external data abort pending. The kernel is hit by this
+ * data abort as soon as it enters userspace, because it unmasks the
+ * data aborts at this moment. We register a custom abort handler
+ * below to ignore the first data abort to work around this
+ * problem.
+ */
+static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
+                                        struct pt_regs *regs)
 {
-        debug_ll_io_init();
+        static int ignore_first;
+        if (!ignore_first && fsr == 0x1406) {
+                ignore_first = 1;
+                return 0;
+        }
+        return 1;
 }
-static void __init armada_370_xp_timer_and_clk_init(void)
+static void __init mvebu_timer_and_clk_init(void)
 {
        of_clk_init(NULL);
        clocksource_of_init();
@@ -45,6 +62,10 @@ static void __init armada_370_xp_timer_and_clk_init(void)
 #ifdef CONFIG_CACHE_L2X0
        l2x0_of_init(0, ~0UL);
 #endif
+        if (of_machine_is_compatible("marvell,armada375"))
+                hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
+                                "imprecise external abort");
 }
 static void __init i2c_quirk(void)
@@ -75,7 +96,7 @@ static void __init i2c_quirk(void)
        return;
 }
-static void __init armada_370_xp_dt_init(void)
+static void __init mvebu_dt_init(void)
 {
        if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
                i2c_quirk();
@@ -87,11 +108,33 @@ static const char * const armada_370_xp_dt_compat[] = {
        NULL,
 };
-DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
+DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
        .smp            = smp_ops(armada_xp_smp_ops),
-        .init_machine   = armada_370_xp_dt_init,
+        .init_machine   = mvebu_dt_init,
-        .map_io         = armada_370_xp_map_io,
+        .init_time      = mvebu_timer_and_clk_init,
-        .init_time      = armada_370_xp_timer_and_clk_init,
        .restart        = mvebu_restart,
        .dt_compat      = armada_370_xp_dt_compat,
 MACHINE_END
+static const char * const armada_375_dt_compat[] = {
+        "marvell,armada375",
+        NULL,
+};
+DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
+        .init_time      = mvebu_timer_and_clk_init,
+        .restart        = mvebu_restart,
+        .dt_compat      = armada_375_dt_compat,
+MACHINE_END
+static const char * const armada_38x_dt_compat[] = {
+        "marvell,armada380",
+        "marvell,armada385",
+        NULL,
+};
+DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
+        .init_time      = mvebu_timer_and_clk_init,
+        .restart        = mvebu_restart,
+        .dt_compat      = armada_38x_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/board.h b/arch/arm/mach-mvebu/board.h
new file mode 100644
index 000000000000..de7f0a191394
--- /dev/null
+++ b/arch/arm/mach-mvebu/board.h
@@ -0,0 +1,22 @@
+/*
+ * Board functions for Marvell System On Chip
+ *
+ * Copyright (C) 2014
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ARCH_MVEBU_BOARD_H
+#define __ARCH_MVEBU_BOARD_H
+#ifdef CONFIG_MACH_T5325
+void t5325_init(void);
+#else
+static inline void t5325_init(void) {};
+#endif
+#endif
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-mvebu/dove.c
index 49fa9abd09da..5e5a43624237 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-dove/board-dt.c
+ * arch/arm/mach-mvebu/dove.c
 *
 * Marvell Dove 88AP510 System On Chip FDT Board
 *
@@ -9,17 +9,14 @@
 */
 #include <linux/init.h>
-#include <linux/clk-provider.h>
+#include <linux/mbus.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <asm/hardware/cache-tauros2.h>
 #include <asm/mach/arch.h>
-#include <mach/dove.h>
-#include <mach/pm.h>
-#include <plat/common.h>
 #include "common.h"
-static void __init dove_dt_init(void)
+static void __init dove_init(void)
 {
        pr_info("Dove 88AP510 SoC\n");
@@ -30,14 +27,13 @@ static void __init dove_dt_init(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-static const char * const dove_dt_board_compat[] = {
+static const char * const dove_dt_compat[] = {
        "marvell,dove",
        NULL
 };
-DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+DT_MACHINE_START(DOVE_DT, "Marvell Dove")
-        .map_io         = dove_map_io,
+        .init_machine   = dove_init,
-        .init_machine   = dove_dt_init,
+        .restart        = mvebu_restart,
-        .restart        = dove_restart,
+        .dt_compat      = dove_dt_compat,
-        .dt_compat      = dove_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mvebu/kirkwood-pm.c b/arch/arm/mach-mvebu/kirkwood-pm.c
new file mode 100644
index 000000000000..cbb816f2120c
--- /dev/null
+++ b/arch/arm/mach-mvebu/kirkwood-pm.c
@@ -0,0 +1,76 @@
+/*
+ * Power Management driver for Marvell Kirkwood SoCs
+ *
+ * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com>
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License,
+ * version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include "kirkwood.h"
+static void __iomem *ddr_operation_base;
+static void __iomem *memory_pm_ctrl;
+static void kirkwood_low_power(void)
+{
+        u32 mem_pm_ctrl;
+        mem_pm_ctrl = readl(memory_pm_ctrl);
+        /* Set peripherals to low-power mode */
+        writel_relaxed(~0, memory_pm_ctrl);
+        /* Set DDR in self-refresh */
+        writel_relaxed(0x7, ddr_operation_base);
+        /*
+         * Set CPU in wait-for-interrupt state.
+         * This disables the CPU core clocks,
+         * the array clocks, and also the L2 controller.
+         */
+        cpu_do_idle();
+        writel_relaxed(mem_pm_ctrl, memory_pm_ctrl);
+}
+static int kirkwood_suspend_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+                kirkwood_low_power();
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+static int kirkwood_pm_valid_standby(suspend_state_t state)
+{
+        return state == PM_SUSPEND_STANDBY;
+}
+static const struct platform_suspend_ops kirkwood_suspend_ops = {
+        .enter = kirkwood_suspend_enter,
+        .valid = kirkwood_pm_valid_standby,
+};
+int __init kirkwood_pm_init(void)
+{
+        ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
+        memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4);
+        suspend_set_ops(&kirkwood_suspend_ops);
+        return 0;
+}
diff --git a/arch/arm/mach-mvebu/kirkwood-pm.h b/arch/arm/mach-mvebu/kirkwood-pm.h
new file mode 100644
index 000000000000..21e7530f368b
--- /dev/null
+++ b/arch/arm/mach-mvebu/kirkwood-pm.h
@@ -0,0 +1,26 @@
+/*
+ * Power Management driver for Marvell Kirkwood SoCs
+ *
+ * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com>
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License,
+ * version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ARCH_KIRKWOOD_PM_H
+#define __ARCH_KIRKWOOD_PM_H
+#ifdef CONFIG_PM
+void kirkwood_pm_init(void);
+#else
+static inline void kirkwood_pm_init(void) {};
+#endif
+#endif
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
new file mode 100644
index 000000000000..120207fc36f1
--- /dev/null
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
+ *
+ * arch/arm/mach-mvebu/kirkwood.c
+ *
+ * Flattened Device Tree board initialization
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <asm/hardware/cache-feroceon-l2.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include "kirkwood.h"
+#include "kirkwood-pm.h"
+#include "common.h"
+#include "board.h"
+static struct resource kirkwood_cpufreq_resources[] = {
+        [0] = {
+                .start  = CPU_CONTROL_PHYS,
+                .end    = CPU_CONTROL_PHYS + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device kirkwood_cpufreq_device = {
+        .name           = "kirkwood-cpufreq",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(kirkwood_cpufreq_resources),
+        .resource       = kirkwood_cpufreq_resources,
+};
+static void __init kirkwood_cpufreq_init(void)
+{
+        platform_device_register(&kirkwood_cpufreq_device);
+}
+static struct resource kirkwood_cpuidle_resource[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+                .start  = DDR_OPERATION_BASE,
+                .end    = DDR_OPERATION_BASE + 3,
+        },
+};
+static struct platform_device kirkwood_cpuidle = {
+        .name           = "kirkwood_cpuidle",
+        .id             = -1,
+        .resource       = kirkwood_cpuidle_resource,
+        .num_resources  = 1,
+};
+static void __init kirkwood_cpuidle_init(void)
+{
+        platform_device_register(&kirkwood_cpuidle);
+}
+#define MV643XX_ETH_MAC_ADDR_LOW        0x0414
+#define MV643XX_ETH_MAC_ADDR_HIGH       0x0418
+static void __init kirkwood_dt_eth_fixup(void)
+{
+        struct device_node *np;
+        /*
+         * The ethernet interfaces forget the MAC address assigned by u-boot
+         * if the clocks are turned off. Usually, u-boot on kirkwood boards
+         * has no DT support to properly set local-mac-address property.
+         * As a workaround, we get the MAC address from mv643xx_eth registers
+         * and update the port device node if no valid MAC address is set.
+         */
+        for_each_compatible_node(np, NULL, "marvell,kirkwood-eth-port") {
+                struct device_node *pnp = of_get_parent(np);
+                struct clk *clk;
+                struct property *pmac;
+                void __iomem *io;
+                u8 *macaddr;
+                u32 reg;
+                if (!pnp)
+                        continue;
+                /* skip disabled nodes or nodes with valid MAC address*/
+                if (!of_device_is_available(pnp) || of_get_mac_address(np))
+                        goto eth_fixup_skip;
+                clk = of_clk_get(pnp, 0);
+                if (IS_ERR(clk))
+                        goto eth_fixup_skip;
+                io = of_iomap(pnp, 0);
+                if (!io)
+                        goto eth_fixup_no_map;
+                /* ensure port clock is not gated to not hang CPU */
+                clk_prepare_enable(clk);
+                /* store MAC address register contents in local-mac-address */
+                pr_err(FW_INFO "%s: local-mac-address is not set\n",
+                       np->full_name);
+                pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL);
+                if (!pmac)
+                        goto eth_fixup_no_mem;
+                pmac->value = pmac + 1;
+                pmac->length = 6;
+                pmac->name = kstrdup("local-mac-address", GFP_KERNEL);
+                if (!pmac->name) {
+                        kfree(pmac);
+                        goto eth_fixup_no_mem;
+                }
+                macaddr = pmac->value;
+                reg = readl(io + MV643XX_ETH_MAC_ADDR_HIGH);
+                macaddr[0] = (reg >> 24) & 0xff;
+                macaddr[1] = (reg >> 16) & 0xff;
+                macaddr[2] = (reg >> 8) & 0xff;
+                macaddr[3] = reg & 0xff;
+                reg = readl(io + MV643XX_ETH_MAC_ADDR_LOW);
+                macaddr[4] = (reg >> 8) & 0xff;
+                macaddr[5] = reg & 0xff;
+                of_update_property(np, pmac);
+eth_fixup_no_mem:
+                iounmap(io);
+                clk_disable_unprepare(clk);
+eth_fixup_no_map:
+                clk_put(clk);
+eth_fixup_skip:
+                of_node_put(pnp);
+        }
+}
+/*
+ * Disable propagation of mbus errors to the CPU local bus, as this
+ * causes mbus errors (which can occur for example for PCI aborts) to
+ * throw CPU aborts, which we're not set up to deal with.
+ */
+void kirkwood_disable_mbus_error_propagation(void)
+{
+        void __iomem *cpu_config;
+        cpu_config = ioremap(CPU_CONFIG_PHYS, 4);
+        writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config);
+}
+static struct of_dev_auxdata auxdata[] __initdata = {
+        OF_DEV_AUXDATA("marvell,kirkwood-audio", 0xf10a0000,
+                       "mvebu-audio", NULL),
+        { /* sentinel */ }
+};
+static void __init kirkwood_dt_init(void)
+{
+        kirkwood_disable_mbus_error_propagation();
+        BUG_ON(mvebu_mbus_dt_init());
+#ifdef CONFIG_CACHE_FEROCEON_L2
+        feroceon_of_init();
+#endif
+        kirkwood_cpufreq_init();
+        kirkwood_cpuidle_init();
+        kirkwood_pm_init();
+        kirkwood_dt_eth_fixup();
+        if (of_machine_is_compatible("hp,t5325"))
+                t5325_init();
+        of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
+}
+static const char * const kirkwood_dt_board_compat[] = {
+        "marvell,kirkwood",
+        NULL
+};
+DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
+        /* Maintainer: Jason Cooper <jason@lakedaemon.net> */
+        .init_machine   = kirkwood_dt_init,
+        .restart        = mvebu_restart,
+        .dt_compat      = kirkwood_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/kirkwood.h b/arch/arm/mach-mvebu/kirkwood.h
new file mode 100644
index 000000000000..89f3d1f51643
--- /dev/null
+++ b/arch/arm/mach-mvebu/kirkwood.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-mvebu/kirkwood.h
+ *
+ * Generic definitions for Marvell Kirkwood SoC flavors:
+ * 88F6180, 88F6192 and 88F6281.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
+#define DDR_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
+#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
+#define DDR_OPERATION_BASE      (DDR_PHYS_BASE + 0x1418)
+#define CPU_CONFIG_PHYS         (BRIDGE_PHYS_BASE + 0x0100)
+#define CPU_CONFIG_ERROR_PROP   0x00000004
+#define CPU_CONTROL_PHYS        (BRIDGE_PHYS_BASE + 0x0104)
+#define MEMORY_PM_CTRL_PHYS     (BRIDGE_PHYS_BASE + 0x0118)
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
index f3b325f6cbd4..f3d4cf53f746 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.c
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -38,6 +38,7 @@ static bool is_id_valid;
 static const struct of_device_id mvebu_pcie_of_match_table[] = {
        { .compatible = "marvell,armada-xp-pcie", },
        { .compatible = "marvell,armada-370-pcie", },
+        { .compatible = "marvell,kirkwood-pcie" },
        {},
 };
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index a7fb89a5b5d9..614ba6832ff3 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -1,5 +1,5 @@
 /*
- * System controller support for Armada 370 and XP platforms.
+ * System controller support for Armada 370, 375 and XP platforms.
 *
 * Copyright (C) 2012 Marvell
 *
@@ -11,7 +11,7 @@
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
- * The Armada 370 and Armada XP SoCs both have a range of
+ * The Armada 370, 375 and Armada XP SoCs have a range of
 * miscellaneous registers, that do not belong to a particular device,
 * but rather provide system-level features. This basic
 * system-controller driver provides a device tree binding for those
@@ -47,6 +47,13 @@ static const struct mvebu_system_controller armada_370_xp_system_controller = {
        .system_soft_reset = 0x1,
 };
+static const struct mvebu_system_controller armada_375_system_controller = {
+        .rstoutn_mask_offset = 0x54,
+        .system_soft_reset_offset = 0x58,
+        .rstoutn_mask_reset_out_en = 0x1,
+        .system_soft_reset = 0x1,
+};
 static const struct mvebu_system_controller orion_system_controller = {
        .rstoutn_mask_offset = 0x108,
        .system_soft_reset_offset = 0x10c,
@@ -54,13 +61,16 @@ static const struct mvebu_system_controller orion_system_controller = {
        .system_soft_reset = 0x1,
 };
-static struct of_device_id of_system_controller_table[] = {
+static const struct of_device_id of_system_controller_table[] = {
        {
                .compatible = "marvell,orion-system-controller",
                .data = (void *) &orion_system_controller,
        }, {
                .compatible = "marvell,armada-370-xp-system-controller",
                .data = (void *) &armada_370_xp_system_controller,
+        }, {
+                .compatible = "marvell,armada-375-system-controller",
+                .data = (void *) &armada_375_system_controller,
        },
        { /* end of list */ },
 };
@@ -90,13 +100,12 @@ void mvebu_restart(enum reboot_mode mode, const char *cmd)
 static int __init mvebu_system_controller_init(void)
 {
+        const struct of_device_id *match;
        struct device_node *np;
-        np = of_find_matching_node(NULL, of_system_controller_table);
+        np = of_find_matching_node_and_match(NULL, of_system_controller_table,
+                                             &match);
        if (np) {
-                const struct of_device_id *match =
-                    of_match_node(of_system_controller_table, np);
-                BUG_ON(!match);
                system_controller_base = of_iomap(np, 0);
                mvebu_sc = (struct mvebu_system_controller *)match->data;
                of_node_put(np);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 8cde9e05b5d6..84794137b175 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -16,11 +16,7 @@ config ARCH_MXS
        bool "Freescale MXS (i.MX23, i.MX28) support"
        depends on ARCH_MULTI_V5
        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK_PREPARE
        select PINCTRL
        select SOC_BUS
        select SOC_IMX23
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 1dc5acd4fc99..2e7cec86e50e 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -157,6 +157,8 @@ enum mac_oui {
        OUI_FSL,
        OUI_DENX,
        OUI_CRYSTALFONTZ,
+        OUI_I2SE,
+        OUI_ARMADEUS,
 };
 static void __init update_fec_mac_prop(enum mac_oui oui)
@@ -211,6 +213,16 @@ static void __init update_fec_mac_prop(enum mac_oui oui)
                        macaddr[1] = 0xb9;
                        macaddr[2] = 0xe1;
                        break;
+                case OUI_I2SE:
+                        macaddr[0] = 0x00;
+                        macaddr[1] = 0x01;
+                        macaddr[2] = 0x87;
+                        break;
+                case OUI_ARMADEUS:
+                        macaddr[0] = 0x00;
+                        macaddr[1] = 0x1e;
+                        macaddr[2] = 0xac;
+                        break;
                }
                val = ocotp[i];
                macaddr[3] = (val >> 16) & 0xff;
@@ -236,6 +248,11 @@ static void __init imx28_evk_init(void)
        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
 }
+static void __init imx28_apf28_init(void)
+{
+        update_fec_mac_prop(OUI_ARMADEUS);
+}
 static int apx4devkit_phy_fixup(struct phy_device *phy)
 {
        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
@@ -330,6 +347,11 @@ static void __init crystalfontz_init(void)
        update_fec_mac_prop(OUI_CRYSTALFONTZ);
 }
+static void __init duckbill_init(void)
+{
+        update_fec_mac_prop(OUI_I2SE);
+}
 static void __init m28cu3_init(void)
 {
        update_fec_mac_prop(OUI_DENX);
@@ -426,6 +448,11 @@ static int __init mxs_restart_init(void)
        return 0;
 }
+static void __init eukrea_mbmx283lc_init(void)
+{
+        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
+}
 static void __init mxs_machine_init(void)
 {
        struct device_node *root;
@@ -458,10 +485,16 @@ static void __init mxs_machine_init(void)
        if (of_machine_is_compatible("fsl,imx28-evk"))
                imx28_evk_init();
+        if (of_machine_is_compatible("armadeus,imx28-apf28"))
+                imx28_apf28_init();
        else if (of_machine_is_compatible("bluegiga,apx4devkit"))
                apx4devkit_init();
        else if (of_machine_is_compatible("crystalfontz,cfa10036"))
                crystalfontz_init();
+        else if (of_machine_is_compatible("eukrea,mbmx283lc"))
+                eukrea_mbmx283lc_init();
+        else if (of_machine_is_compatible("i2se,duckbill"))
+                duckbill_init();
        else if (of_machine_is_compatible("msr,m28cu3"))
                m28cu3_init();
diff --git a/arch/arm/mach-netx/include/mach/timex.h b/arch/arm/mach-netx/include/mach/timex.h
deleted file mode 100644
index 1120dd0ba393..000000000000
--- a/arch/arm/mach-netx/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-netx/include/mach/timex.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define CLOCK_TICK_RATE 100000000
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index 6df42e643031..5fb2a590ec17 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -28,6 +28,9 @@
 #include <asm/mach/time.h>
 #include <mach/netx-regs.h>
+#define NETX_CLOCK_FREQ 100000000
+#define NETX_LATCH DIV_ROUND_CLOSEST(NETX_CLOCK_FREQ, HZ)
 #define TIMER_CLOCKEVENT 0
 #define TIMER_CLOCKSOURCE 1
@@ -41,7 +44,7 @@ static void netx_set_mode(enum clock_event_mode mode,
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
-                writel(LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
+                writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
                tmode = NETX_GPIO_COUNTER_CTRL_RST_EN |
                        NETX_GPIO_COUNTER_CTRL_IRQ_EN |
                        NETX_GPIO_COUNTER_CTRL_RUN;
@@ -99,7 +102,7 @@ netx_timer_interrupt(int irq, void *dev_id)
 static struct irqaction netx_timer_irq = {
        .name           = "NetX Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = netx_timer_interrupt,
 };
@@ -114,7 +117,7 @@ void __init netx_timer_init(void)
        /* Reset the timer value to zero */
        writel(0, NETX_GPIO_COUNTER_CURRENT(0));
-        writel(LATCH, NETX_GPIO_COUNTER_MAX(0));
+        writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0));
        /* acknowledge interrupt */
        writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
@@ -137,11 +140,11 @@ void __init netx_timer_init(void)
                        NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
        clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
-                "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);
+                "netx_timer", NETX_CLOCK_FREQ, 200, 32, clocksource_mmio_readl_up);
        /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
         * Adding some safety ... */
        netx_clockevent.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&netx_clockevent, CLOCK_TICK_RATE,
+        clockevents_config_and_register(&netx_clockevent, NETX_CLOCK_FREQ,
                                        0xa00, 0xfffffffe);
 }
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 4d42da49753c..486d301f43fd 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -6,16 +6,11 @@ config ARCH_NOMADIK
        select ARM_VIC
        select CLKSRC_NOMADIK_MTU
        select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
-        select CLKSRC_OF
-        select COMMON_CLK
        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
        select PINCTRL_NOMADIK
        select PINCTRL_STN8815
-        select SPARSE_IRQ
-        select USE_OF
        help
          Support for the Nomadik platform by ST-Ericsson
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
index 59d8f0a70919..bc41f26c1a12 100644
--- a/arch/arm/mach-nspire/Kconfig
+++ b/arch/arm/mach-nspire/Kconfig
@@ -3,14 +3,9 @@ config ARCH_NSPIRE
        depends on ARCH_MULTI_V4_V5
        depends on MMU
        select CPU_ARM926T
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select SPARSE_IRQ
        select ARM_AMBA
        select ARM_VIC
        select ARM_TIMER_SP804
-        select USE_OF
-        select CLKSRC_OF
        help
          This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
index 4b2ed2e8352f..3d24ebf12095 100644
--- a/arch/arm/mach-nspire/nspire.c
+++ b/arch/arm/mach-nspire/nspire.c
@@ -63,7 +63,7 @@ static void __init nspire_init(void)
                        nspire_auxdata, NULL);
 }
-static void nspire_restart(char mode, const char *cmd)
+static void nspire_restart(enum reboot_mode mode, const char *cmd)
 {
        void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
        if (!base)
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index fd90cafc2e36..65d2acb31498 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -318,6 +318,9 @@ static void __init h2_init_smc91x(void)
 static int tps_setup(struct i2c_client *client, void *context)
 {
+        if (!IS_BUILTIN(CONFIG_TPS65010))
+                return -ENOSYS;
+        
        tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V |
                                TPS_LDO1_ENABLE | TPS_VLDO1_3_0V);
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index d68909b095f1..3a0262156e93 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -191,6 +191,9 @@ static struct platform_device osk5912_tps_leds = {
 static int osk_tps_setup(struct i2c_client *client, void *context)
 {
+        if (!IS_BUILTIN(CONFIG_TPS65010))
+                return -ENOSYS;
        /* Set GPIO 1 HIGH to disable VBUS power supply;
         * OHCI driver powers it up/down as needed.
         */
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 5bb8ce86d54b..4be601b638d7 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -32,55 +32,51 @@
 #define OMAP1_DMA_BASE                  (0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT      17
-#define OMAP1_DMA_STRIDE                0x40
-static u32 errata;
 static u32 enable_1510_mode;
-static u8 dma_stride;
-static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+static const struct omap_dma_reg reg_map[] = {
+        [GCR]           = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
-static u16 reg_map[] = {
+        [GSCR]          = { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
-        [GCR]           = 0x400,
+        [GRST1]         = { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
-        [GSCR]          = 0x404,
+        [HW_ID]         = { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
-        [GRST1]         = 0x408,
+        [PCH2_ID]       = { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
-        [HW_ID]         = 0x442,
+        [PCH0_ID]       = { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
-        [PCH2_ID]       = 0x444,
+        [PCH1_ID]       = { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
-        [PCH0_ID]       = 0x446,
+        [PCHG_ID]       = { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
-        [PCH1_ID]       = 0x448,
+        [PCHD_ID]       = { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
-        [PCHG_ID]       = 0x44a,
+        [CAPS_0]        = { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
-        [PCHD_ID]       = 0x44c,
+        [CAPS_1]        = { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
-        [CAPS_0]        = 0x44e,
+        [CAPS_2]        = { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
-        [CAPS_1]        = 0x452,
+        [CAPS_3]        = { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
-        [CAPS_2]        = 0x456,
+        [CAPS_4]        = { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
-        [CAPS_3]        = 0x458,
+        [PCH2_SR]       = { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
-        [CAPS_4]        = 0x45a,
+        [PCH0_SR]       = { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
-        [PCH2_SR]       = 0x460,
+        [PCH1_SR]       = { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
-        [PCH0_SR]       = 0x480,
+        [PCHD_SR]       = { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
-        [PCH1_SR]       = 0x482,
-        [PCHD_SR]       = 0x4c0,
        /* Common Registers */
-        [CSDP]          = 0x00,
+        [CSDP]          = { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
-        [CCR]           = 0x02,
+        [CCR]           = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
-        [CICR]          = 0x04,
+        [CICR]          = { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
-        [CSR]           = 0x06,
+        [CSR]           = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
-        [CEN]           = 0x10,
+        [CEN]           = { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
-        [CFN]           = 0x12,
+        [CFN]           = { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
-        [CSFI]          = 0x14,
+        [CSFI]          = { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
-        [CSEI]          = 0x16,
+        [CSEI]          = { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
-        [CPC]           = 0x18, /* 15xx only */
+        [CPC]           = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, /* 15xx only */
-        [CSAC]          = 0x18,
+        [CSAC]          = { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
-        [CDAC]          = 0x1a,
+        [CDAC]          = { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
-        [CDEI]          = 0x1c,
+        [CDEI]          = { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
-        [CDFI]          = 0x1e,
+        [CDFI]          = { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
-        [CLNK_CTRL]     = 0x28,
+        [CLNK_CTRL]     = { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
        /* Channel specific register offsets */
-        [CSSA]          = 0x08,
+        [CSSA]          = { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
-        [CDSA]          = 0x0c,
+        [CDSA]          = { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
-        [COLOR]         = 0x20,
+        [COLOR]         = { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
-        [CCR2]          = 0x24,
+        [CCR2]          = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
-        [LCH_CTRL]      = 0x2a,
+        [LCH_CTRL]      = { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
 };
 static struct resource res[] __initdata = {
@@ -181,44 +177,36 @@ static struct resource res[] __initdata = {
 static void __iomem *dma_base;
 static inline void dma_write(u32 val, int reg, int lch)
 {
-        u8  stride;
+        void __iomem *addr = dma_base;
-        u32 offset;
-        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        addr += reg_map[reg].offset;
-        offset = reg_map[reg] + (stride * lch);
+        addr += reg_map[reg].stride * lch;
-        __raw_writew(val, dma_base + offset);
+        __raw_writew(val, addr);
-        if ((reg > CLNK_CTRL && reg < CCEN) ||
+        if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
-                        (reg > PCHD_ID && reg < CAPS_2)) {
+                __raw_writew(val >> 16, addr + 2);
-                u32 offset2 = reg_map[reg] + 2 + (stride * lch);
-                __raw_writew(val >> 16, dma_base + offset2);
-        }
 }
 static inline u32 dma_read(int reg, int lch)
 {
-        u8 stride;
+        void __iomem *addr = dma_base;
-        u32 offset, val;
+        uint32_t val;
-        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        addr += reg_map[reg].offset;
-        offset = reg_map[reg] + (stride * lch);
+        addr += reg_map[reg].stride * lch;
-        val = __raw_readw(dma_base + offset);
+        val = __raw_readw(addr);
-        if ((reg > CLNK_CTRL && reg < CCEN) ||
+        if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
-                        (reg > PCHD_ID && reg < CAPS_2)) {
+                val |= __raw_readw(addr + 2) << 16;
-                u16 upper;
-                u32 offset2 = reg_map[reg] + 2 + (stride * lch);
-                upper = __raw_readw(dma_base + offset2);
-                val |= (upper << 16);
-        }
        return val;
 }
 static void omap1_clear_lch_regs(int lch)
 {
-        int i = dma_common_ch_start;
+        int i;
-        for (; i <= dma_common_ch_end; i += 1)
+        for (i = CPC; i <= COLOR; i += 1)
                dma_write(0, i, lch);
 }
@@ -255,8 +243,9 @@ static void omap1_show_dma_caps(void)
        return;
 }
-static u32 configure_dma_errata(void)
+static unsigned configure_dma_errata(void)
 {
+        unsigned errata = 0;
        /*
         * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
@@ -272,11 +261,23 @@ static const struct platform_device_info omap_dma_dev_info = {
        .name = "omap-dma-engine",
        .id = -1,
        .dma_mask = DMA_BIT_MASK(32),
+        .res = res,
+        .num_res = 1,
+};
+static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+        .reg_map        = reg_map,
+        .channel_stride = 0x40,
+        .show_dma_caps  = omap1_show_dma_caps,
+        .clear_lch_regs = omap1_clear_lch_regs,
+        .clear_dma      = omap1_clear_dma,
+        .dma_write      = dma_write,
+        .dma_read       = dma_read,
 };
 static int __init omap1_system_dma_init(void)
 {
-        struct omap_system_dma_plat_info        *p;
+        struct omap_system_dma_plat_info        p;
        struct omap_dma_dev_attr                *d;
        struct platform_device                  *pdev, *dma_pdev;
        int ret;
@@ -302,20 +303,12 @@ static int __init omap1_system_dma_init(void)
                goto exit_iounmap;
        }
-        p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
-        if (!p) {
-                dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
-                        __func__, pdev->name);
-                ret = -ENOMEM;
-                goto exit_iounmap;
-        }
        d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
        if (!d) {
                dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
                        __func__, pdev->name);
                ret = -ENOMEM;
-                goto exit_release_p;
+                goto exit_iounmap;
        }
        d->lch_count            = OMAP1_LOGICAL_DMA_CH_COUNT;
@@ -336,17 +329,6 @@ static int __init omap1_system_dma_init(void)
        d->dev_caps             |= CLEAR_CSR_ON_READ;
        d->dev_caps             |= IS_WORD_16;
-        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
-                                        (d->lch_count), GFP_KERNEL);
-        if (!d->chan) {
-                dev_err(&pdev->dev,
-                        "%s: Memory allocation failed for d->chan!\n",
-                        __func__);
-                ret = -ENOMEM;
-                goto exit_release_d;
-        }
        if (cpu_is_omap15xx())
                d->chan_count = 9;
        else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
@@ -356,35 +338,24 @@ static int __init omap1_system_dma_init(void)
                        d->chan_count = 9;
        }
-        p->dma_attr = d;
+        p = dma_plat_info;
+        p.dma_attr = d;
-        p->show_dma_caps        = omap1_show_dma_caps;
+        p.errata = configure_dma_errata();
-        p->clear_lch_regs       = omap1_clear_lch_regs;
-        p->clear_dma            = omap1_clear_dma;
-        p->dma_write            = dma_write;
-        p->dma_read             = dma_read;
-        p->disable_irq_lch      = NULL;
-        p->errata = configure_dma_errata();
-        ret = platform_device_add_data(pdev, p, sizeof(*p));
+        ret = platform_device_add_data(pdev, &p, sizeof(p));
        if (ret) {
                dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
                        __func__, pdev->name, pdev->id);
-                goto exit_release_chan;
+                goto exit_release_d;
        }
        ret = platform_device_add(pdev);
        if (ret) {
                dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
                        __func__, pdev->name, pdev->id);
-                goto exit_release_chan;
+                goto exit_release_d;
        }
-        dma_stride              = OMAP1_DMA_STRIDE;
-        dma_common_ch_start     = CPC;
-        dma_common_ch_end       = COLOR;
        dma_pdev = platform_device_register_full(&omap_dma_dev_info);
        if (IS_ERR(dma_pdev)) {
                ret = PTR_ERR(dma_pdev);
@@ -395,12 +366,8 @@ static int __init omap1_system_dma_init(void)
 exit_release_pdev:
        platform_device_del(pdev);
-exit_release_chan:
-        kfree(d->chan);
 exit_release_d:
        kfree(d);
-exit_release_p:
-        kfree(p);
 exit_iounmap:
        iounmap(dma_base);
 exit_device_put:
diff --git a/arch/arm/mach-omap1/include/mach/timex.h b/arch/arm/mach-omap1/include/mach/timex.h
deleted file mode 100644
index 4793790d53cc..000000000000
--- a/arch/arm/mach-omap1/include/mach/timex.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/timex.h
- */
-#include <plat/timex.h>
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 40a1ae319610..dbee729e3b6d 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -71,7 +71,11 @@ static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
-#ifdef CONFIG_OMAP_32K_TIMER
+#ifndef CONFIG_OMAP_32K_TIMER
+static unsigned short enable_dyn_sleep = 0;
+#else
 static unsigned short enable_dyn_sleep = 1;
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 0af7ca02314d..cb31d4390d52 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -6,7 +6,6 @@ config ARCH_OMAP2
        depends on ARCH_MULTI_V6
        select ARCH_OMAP2PLUS
        select CPU_V6
-        select MULTI_IRQ_HANDLER
        select SOC_HAS_OMAP2_SDRC
 config ARCH_OMAP3
@@ -15,13 +14,10 @@ config ARCH_OMAP3
        select ARCH_OMAP2PLUS
        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
-        select CPU_V7
-        select MULTI_IRQ_HANDLER
        select OMAP_INTERCONNECT
        select PM_OPP if PM
        select PM_RUNTIME if CPU_IDLE
        select SOC_HAS_OMAP2_SDRC
-        select USB_ARCH_HAS_EHCI if USB_SUPPORT
 config ARCH_OMAP4
        bool "TI OMAP4"
@@ -33,16 +29,13 @@ config ARCH_OMAP4
        select ARM_ERRATA_720789
        select ARM_GIC
        select CACHE_L2X0
-        select CPU_V7
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select OMAP_INTERCONNECT
        select PL310_ERRATA_588369
        select PL310_ERRATA_727915
        select PM_OPP if PM
        select PM_RUNTIME if CPU_IDLE
-        select USB_ARCH_HAS_EHCI if USB_SUPPORT
        select ARM_ERRATA_754322
        select ARM_ERRATA_775420
@@ -53,10 +46,8 @@ config SOC_OMAP5
        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
        select ARM_GIC
-        select CPU_V7
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select HAVE_ARM_ARCH_TIMER
        select ARM_ERRATA_798181 if SMP
@@ -66,16 +57,12 @@ config SOC_AM33XX
        select ARCH_OMAP2PLUS
        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
-        select CPU_V7
-        select MULTI_IRQ_HANDLER
 config SOC_AM43XX
        bool "TI AM43x"
        depends on ARCH_MULTI_V7
-        select CPU_V7
        select ARCH_OMAP2PLUS
        select ARCH_HAS_OPP
-        select MULTI_IRQ_HANDLER
        select ARM_GIC
        select MACH_OMAP_GENERIC
@@ -86,9 +73,8 @@ config SOC_DRA7XX
        select ARCH_HAS_OPP
        select ARM_CPU_SUSPEND if PM
        select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
        select HAVE_ARM_ARCH_TIMER
+        select IRQ_CROSSBAR
 config ARCH_OMAP2PLUS
        bool
@@ -98,17 +84,12 @@ config ARCH_OMAP2PLUS
        select ARCH_OMAP
        select ARCH_REQUIRE_GPIOLIB
        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
        select MACH_OMAP_GENERIC
        select OMAP_DM_TIMER
        select PINCTRL
-        select PROC_DEVICETREE if PROC_FS
        select SOC_BUS
-        select SPARSE_IRQ
        select TI_PRIV_EDMA
-        select USE_OF
        help
          Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
@@ -169,12 +150,6 @@ config SOC_TI81XX
        depends on ARCH_OMAP3
        default y
-config OMAP_PACKAGE_ZAF
-       bool
-config OMAP_PACKAGE_ZAC
-       bool
 config OMAP_PACKAGE_CBC
       bool
@@ -284,7 +259,6 @@ config MACH_NOKIA_N8X0
        default y
        select MACH_NOKIA_N810
        select MACH_NOKIA_N810_WIMAX
-        select OMAP_PACKAGE_ZAC
 config MACH_NOKIA_RX51
        bool "Nokia N900 (RX-51) phone"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e6eec6f72fd3..8421f38cf445 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -60,6 +60,7 @@ AFLAGS_sram34xx.o			:=-Wa,-march=armv7-a
 obj-$(CONFIG_SOC_OMAP2420)              += omap2-restart.o
 obj-$(CONFIG_SOC_OMAP2430)              += omap2-restart.o
 obj-$(CONFIG_SOC_AM33XX)                += am33xx-restart.o
+obj-$(CONFIG_SOC_AM43XX)                += omap4-restart.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap3-restart.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap4-restart.o
 obj-$(CONFIG_SOC_OMAP5)                 += omap4-restart.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 25b79a297365..6a6935caac1e 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -17,7 +17,6 @@
 #include <linux/err.h>
 #include <linux/davinci_emac.h>
-#include <asm/system.h>
 #include "omap_device.h"
 #include "am35xx.h"
 #include "control.h"
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 8dd0ec858cf1..018353d88b96 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -16,6 +16,8 @@
 *
 */
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
@@ -542,8 +544,22 @@ static struct isp_platform_data cm_t35_isp_pdata = {
        .subdevs = cm_t35_isp_subdevs,
 };
+static struct regulator_consumer_supply cm_t35_camera_supplies[] = {
+        REGULATOR_SUPPLY("vaa", "3-005d"),
+        REGULATOR_SUPPLY("vdd", "3-005d"),
+};
 static void __init cm_t35_init_camera(void)
 {
+        struct clk *clk;
+        clk = clk_register_fixed_rate(NULL, "mt9t001-clkin", NULL, CLK_IS_ROOT,
+                                      48000000);
+        clk_register_clkdev(clk, NULL, "3-005d");
+        regulator_register_fixed(2, cm_t35_camera_supplies,
+                                 ARRAY_SIZE(cm_t35_camera_supplies));
        if (omap3_init_camera(&cm_t35_isp_pdata) < 0)
                pr_warn("CM-T3x: Failed registering camera device!\n");
 }
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 8e3daa11602b..b8920b6bc104 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -35,7 +35,11 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
 static void __init omap_generic_init(void)
 {
+        omapdss_early_init_of();
        pdata_quirks_init(omap_dt_match_table);
+        omapdss_init_of();
 }
 #ifdef CONFIG_SOC_OMAP2420
@@ -229,8 +233,9 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
        .init_late      = am43xx_init_late,
        .init_irq       = omap_gic_of_init,
        .init_machine   = omap_generic_init,
-        .init_time      = omap3_sync32k_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
        .dt_compat      = am43_boards_compat,
+        .restart        = omap44xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index de1bc6bbe585..cf18340eb3bb 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -536,11 +536,13 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
 static void __init pandora_wl1251_init(void)
 {
-        struct wl12xx_platform_data pandora_wl1251_pdata;
+        struct wl1251_platform_data pandora_wl1251_pdata;
        int ret;
        memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata));
+        pandora_wl1251_pdata.power_gpio = -1;
        ret = gpio_request_one(PANDORA_WIFI_IRQ_GPIO, GPIOF_IN, "wl1251 irq");
        if (ret < 0)
                goto fail;
@@ -550,7 +552,7 @@ static void __init pandora_wl1251_init(void)
                goto fail_irq;
        pandora_wl1251_pdata.use_eeprom = true;
-        ret = wl12xx_set_platform_data(&pandora_wl1251_pdata);
+        ret = wl1251_set_platform_data(&pandora_wl1251_pdata);
        if (ret < 0)
                goto fail_irq;
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 8760bbe3baab..ddfc8df83c6a 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -84,7 +84,7 @@ enum {
        RX51_SPI_MIPID,         /* LCD panel */
 };
-static struct wl12xx_platform_data wl1251_pdata;
+static struct wl1251_platform_data wl1251_pdata;
 static struct tsc2005_platform_data tsc2005_pdata;
 #if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
@@ -1173,13 +1173,7 @@ static inline void board_smc91x_init(void)
 #endif
-static void rx51_wl1251_set_power(bool enable)
-{
-        gpio_set_value(RX51_WL1251_POWER_GPIO, enable);
-}
 static struct gpio rx51_wl1251_gpios[] __initdata = {
-        { RX51_WL1251_POWER_GPIO, GPIOF_OUT_INIT_LOW,   "wl1251 power"  },
        { RX51_WL1251_IRQ_GPIO,   GPIOF_IN,             "wl1251 irq"    },
 };
@@ -1196,17 +1190,16 @@ static void __init rx51_init_wl1251(void)
        if (irq < 0)
                goto err_irq;
-        wl1251_pdata.set_power = rx51_wl1251_set_power;
+        wl1251_pdata.power_gpio = RX51_WL1251_POWER_GPIO;
        rx51_peripherals_spi_board_info[RX51_SPI_WL1251].irq = irq;
        return;
 err_irq:
        gpio_free(RX51_WL1251_IRQ_GPIO);
-        gpio_free(RX51_WL1251_POWER_GPIO);
 error:
        printk(KERN_ERR "wl1251 board initialisation failed\n");
-        wl1251_pdata.set_power = NULL;
+        wl1251_pdata.power_gpio = -1;
        /*
         * Now rx51_peripherals_spi_board_info[1].irq is zero and
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 11ed9152e665..8f5121b89688 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3497,10 +3497,6 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck),
        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck),
        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck),
-        CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck),
-        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck),
-        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck),
-        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck),
        CLK(NULL,       "init_60m_fclk",        &dummy_ck),
        CLK(NULL,       "gpt1_fck",     &gpt1_fck),
        CLK(NULL,       "aes2_ick",     &aes2_ick),
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 47f9562ca7aa..2649ce445845 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -306,7 +306,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
        ref_rate = __clk_get_rate(dd->clk_ref);
        clk_name = __clk_get_name(hw->clk);
-        pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
+        pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
                 clk_name, target_rate);
        scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
@@ -342,7 +342,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
                if (r == DPLL_MULT_UNDERFLOW)
                        continue;
-                pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
+                pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
                         clk_name, m, n, new_rate);
                if (target_rate == new_rate) {
@@ -354,7 +354,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
        }
        if (target_rate != new_rate) {
-                pr_debug("clock: %s: cannot round to rate %ld\n",
+                pr_debug("clock: %s: cannot round to rate %lu\n",
                         clk_name, target_rate);
                return ~0;
        }
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index e6b91e552d3d..f03dc97921ad 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -247,7 +247,7 @@ static struct clockdomain neon_clkdm = {
 static struct clockdomain iva2_clkdm = {
        .name           = "iva2_clkdm",
        .pwrdm          = { .name = "iva2_pwrdm" },
-        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .flags          = CLKDM_CAN_SWSUP,
        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
        .wkdep_srcs     = iva2_wkdeps,
        .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 731ca134348c..f5c4731b6f06 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -254,6 +254,11 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
 *
 */
+void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
+}
 /**
 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
@@ -404,8 +409,17 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
 static int omap4_clkdm_sleep(struct clockdomain *clkdm)
 {
-        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+        if (clkdm->flags & CLKDM_CAN_HWSUP)
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
+                omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+                                                clkdm->cm_inst,
+                                                clkdm->clkdm_offs);
+        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+                                               clkdm->cm_inst,
+                                               clkdm->clkdm_offs);
+        else
+                return -EINVAL;
        return 0;
 }
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index a6aae300542c..d88aff7baff8 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -315,5 +315,8 @@ extern int omap_dss_reset(struct omap_hwmod *);
 /* SoC specific clock initializer */
 int omap_clk_init(void);
+int __init omapdss_init_of(void);
+void __init omapdss_early_init_of(void);
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 0dd6398bade4..e58609b312c7 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -229,6 +229,9 @@ static struct omap_iommu_arch_data omap3_isp_iommu = {
 int omap3_init_camera(struct isp_platform_data *pdata)
 {
+        if (of_have_populated_dt())
+                omap3_isp_iommu.name = "480bd400.mmu";
        omap3isp_device.dev.platform_data = pdata;
        omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu;
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 4cf165502b35..16d33d831287 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -23,6 +23,9 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
 #include <video/omapdss.h>
 #include "omap_hwmod.h"
@@ -301,7 +304,6 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
        board_data->version = ver;
        board_data->dsi_enable_pads = omap_dsi_enable_pads;
        board_data->dsi_disable_pads = omap_dsi_disable_pads;
-        board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
        board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
        omap_display_device.dev.platform_data = board_data;
@@ -552,3 +554,166 @@ int omap_dss_reset(struct omap_hwmod *oh)
        return r;
 }
+/* list of 'compatible' nodes to convert to omapdss specific */
+static const char * const dss_compat_conv_list[] __initconst = {
+        "composite-connector",
+        "dvi-connector",
+        "hdmi-connector",
+        "panel-dpi",
+        "panel-dsi-cm",
+        "sony,acx565akm",
+        "svideo-connector",
+        "ti,tfp410",
+        "ti,tpd12s015",
+};
+/* prepend compatible string with "omapdss," */
+static __init void omapdss_omapify_node(struct device_node *node,
+        const char *compat)
+{
+        char *new_compat;
+        struct property *prop;
+        new_compat = kasprintf(GFP_KERNEL, "omapdss,%s", compat);
+        prop = kzalloc(sizeof(*prop), GFP_KERNEL);
+        if (!prop) {
+                pr_err("omapdss_omapify_node: kzalloc failed\n");
+                return;
+        }
+        prop->name = "compatible";
+        prop->value = new_compat;
+        prop->length = strlen(new_compat) + 1;
+        of_update_property(node, prop);
+}
+/*
+ * As omapdss panel drivers are omapdss specific, but we want to define the
+ * DT-data in generic manner, we convert the compatible strings of the panel
+ * nodes from "panel-foo" to "omapdss,panel-foo". This way we can have both
+ * correct DT data and omapdss specific drivers.
+ *
+ * When we get generic panel drivers to the kernel, this will be removed.
+ */
+void __init omapdss_early_init_of(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(dss_compat_conv_list); ++i) {
+                const char *compat = dss_compat_conv_list[i];
+                struct device_node *node = NULL;
+                while ((node = of_find_compatible_node(node, NULL, compat))) {
+                        if (!of_device_is_available(node))
+                                continue;
+                        omapdss_omapify_node(node, compat);
+                }
+        }
+}
+struct device_node * __init omapdss_find_dss_of_node(void)
+{
+        struct device_node *node;
+        node = of_find_compatible_node(NULL, NULL, "ti,omap2-dss");
+        if (node)
+                return node;
+        node = of_find_compatible_node(NULL, NULL, "ti,omap3-dss");
+        if (node)
+                return node;
+        node = of_find_compatible_node(NULL, NULL, "ti,omap4-dss");
+        if (node)
+                return node;
+        return NULL;
+}
+int __init omapdss_init_of(void)
+{
+        int r;
+        enum omapdss_version ver;
+        struct device_node *node;
+        struct platform_device *pdev;
+        static struct omap_dss_board_info board_data = {
+                .dsi_enable_pads = omap_dsi_enable_pads,
+                .dsi_disable_pads = omap_dsi_disable_pads,
+                .set_min_bus_tput = omap_dss_set_min_bus_tput,
+        };
+        /* only create dss helper devices if dss is enabled in the .dts */
+        node = omapdss_find_dss_of_node();
+        if (!node)
+                return 0;
+        if (!of_device_is_available(node))
+                return 0;
+        ver = omap_display_get_version();
+        if (ver == OMAPDSS_VER_UNKNOWN) {
+                pr_err("DSS not supported on this SoC\n");
+                return -ENODEV;
+        }
+        pdev = of_find_device_by_node(node);
+        if (!pdev) {
+                pr_err("Unable to find DSS platform device\n");
+                return -ENODEV;
+        }
+        r = of_platform_populate(node, NULL, NULL, &pdev->dev);
+        if (r) {
+                pr_err("Unable to populate DSS submodule devices\n");
+                return r;
+        }
+        board_data.version = ver;
+        omap_display_device.dev.platform_data = &board_data;
+        r = platform_device_register(&omap_display_device);
+        if (r < 0) {
+                pr_err("Unable to register omapdss device\n");
+                return r;
+        }
+        /* create DRM device */
+        r = omap_init_drm();
+        if (r < 0) {
+                pr_err("Unable to register omapdrm device\n");
+                return r;
+        }
+        /* create vrfb device */
+        r = omap_init_vrfb();
+        if (r < 0) {
+                pr_err("Unable to register omapvrfb device\n");
+                return r;
+        }
+        /* create FB device */
+        r = omap_init_fb();
+        if (r < 0) {
+                pr_err("Unable to register omapfb device\n");
+                return r;
+        }
+        /* create V4L2 display device */
+        r = omap_init_vout();
+        if (r < 0) {
+                pr_err("Unable to register omap_vout device\n");
+                return r;
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/display.h b/arch/arm/mach-omap2/display.h
index f3d2ce4bc262..7375854b16c7 100644
--- a/arch/arm/mach-omap2/display.h
+++ b/arch/arm/mach-omap2/display.h
@@ -30,4 +30,7 @@ int omap_init_drm(void);
 int omap_init_vrfb(void);
 int omap_init_fb(void);
 int omap_init_vout(void);
+struct device_node * __init omapdss_find_dss_of_node(void);
 #endif
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 49fd0d501c9b..5689c88d986d 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -35,97 +35,80 @@
 #include "omap_hwmod.h"
 #include "omap_device.h"
-#define OMAP2_DMA_STRIDE        0x60
+static enum omap_reg_offsets dma_common_ch_end;
-static u32 errata;
+static const struct omap_dma_reg reg_map[] = {
-static u8 dma_stride;
+        [REVISION]      = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
+        [GCR]           = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
-static struct omap_dma_dev_attr *d;
+        [IRQSTATUS_L0]  = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
+        [IRQSTATUS_L1]  = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
-static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+        [IRQSTATUS_L2]  = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
+        [IRQSTATUS_L3]  = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
-static u16 reg_map[] = {
+        [IRQENABLE_L0]  = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
-        [REVISION]              = 0x00,
+        [IRQENABLE_L1]  = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
-        [GCR]                   = 0x78,
+        [IRQENABLE_L2]  = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
-        [IRQSTATUS_L0]          = 0x08,
+        [IRQENABLE_L3]  = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
-        [IRQSTATUS_L1]          = 0x0c,
+        [SYSSTATUS]     = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
-        [IRQSTATUS_L2]          = 0x10,
+        [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
-        [IRQSTATUS_L3]          = 0x14,
+        [CAPS_0]        = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
-        [IRQENABLE_L0]          = 0x18,
+        [CAPS_2]        = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
-        [IRQENABLE_L1]          = 0x1c,
+        [CAPS_3]        = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
-        [IRQENABLE_L2]          = 0x20,
+        [CAPS_4]        = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
-        [IRQENABLE_L3]          = 0x24,
-        [SYSSTATUS]             = 0x28,
-        [OCP_SYSCONFIG]         = 0x2c,
-        [CAPS_0]                = 0x64,
-        [CAPS_2]                = 0x6c,
-        [CAPS_3]                = 0x70,
-        [CAPS_4]                = 0x74,
        /* Common register offsets */
-        [CCR]                   = 0x80,
+        [CCR]           = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
-        [CLNK_CTRL]             = 0x84,
+        [CLNK_CTRL]     = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
-        [CICR]                  = 0x88,
+        [CICR]          = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
-        [CSR]                   = 0x8c,
+        [CSR]           = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
-        [CSDP]                  = 0x90,
+        [CSDP]          = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
-        [CEN]                   = 0x94,
+        [CEN]           = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
-        [CFN]                   = 0x98,
+        [CFN]           = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
-        [CSEI]                  = 0xa4,
+        [CSEI]          = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
-        [CSFI]                  = 0xa8,
+        [CSFI]          = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
-        [CDEI]                  = 0xac,
+        [CDEI]          = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
-        [CDFI]                  = 0xb0,
+        [CDFI]          = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
-        [CSAC]                  = 0xb4,
+        [CSAC]          = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
-        [CDAC]                  = 0xb8,
+        [CDAC]          = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
        /* Channel specific register offsets */
-        [CSSA]                  = 0x9c,
+        [CSSA]          = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
-        [CDSA]                  = 0xa0,
+        [CDSA]          = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
-        [CCEN]                  = 0xbc,
+        [CCEN]          = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
-        [CCFN]                  = 0xc0,
+        [CCFN]          = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
-        [COLOR]                 = 0xc4,
+        [COLOR]         = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
        /* OMAP4 specific registers */
-        [CDP]                   = 0xd0,
+        [CDP]           = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
-        [CNDP]                  = 0xd4,
+        [CNDP]          = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
-        [CCDN]                  = 0xd8,
+        [CCDN]          = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
 };
 static void __iomem *dma_base;
 static inline void dma_write(u32 val, int reg, int lch)
 {
-        u8  stride;
+        void __iomem *addr = dma_base;
-        u32 offset;
-        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        addr += reg_map[reg].offset;
-        offset = reg_map[reg] + (stride * lch);
+        addr += reg_map[reg].stride * lch;
-        __raw_writel(val, dma_base + offset);
+        __raw_writel(val, addr);
 }
 static inline u32 dma_read(int reg, int lch)
 {
-        u8 stride;
+        void __iomem *addr = dma_base;
-        u32 offset, val;
-        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
-        offset = reg_map[reg] + (stride * lch);
-        val = __raw_readl(dma_base + offset);
-        return val;
-}
-static inline void omap2_disable_irq_lch(int lch)
+        addr += reg_map[reg].offset;
-{
+        addr += reg_map[reg].stride * lch;
-        u32 val;
-        val = dma_read(IRQENABLE_L0, lch);
+        return __raw_readl(addr);
-        val &= ~(1 << lch);
-        dma_write(val, IRQENABLE_L0, lch);
 }
 static void omap2_clear_dma(int lch)
 {
-        int i = dma_common_ch_start;
+        int i;
-        for (; i <= dma_common_ch_end; i += 1)
+        for (i = CSDP; i <= dma_common_ch_end; i += 1)
                dma_write(0, i, lch);
 }
@@ -137,8 +120,9 @@ static void omap2_show_dma_caps(void)
        return;
 }
-static u32 configure_dma_errata(void)
+static unsigned configure_dma_errata(void)
 {
+        unsigned errata = 0;
        /*
         * Errata applicable for OMAP2430ES1.0 and all omap2420
@@ -220,48 +204,50 @@ static u32 configure_dma_errata(void)
        return errata;
 }
+static struct omap_system_dma_plat_info dma_plat_info __initdata = {
+        .reg_map        = reg_map,
+        .channel_stride = 0x60,
+        .show_dma_caps  = omap2_show_dma_caps,
+        .clear_dma      = omap2_clear_dma,
+        .dma_write      = dma_write,
+        .dma_read       = dma_read,
+};
+static struct platform_device_info omap_dma_dev_info = {
+        .name = "omap-dma-engine",
+        .id = -1,
+        .dma_mask = DMA_BIT_MASK(32),
+};
 /* One time initializations */
 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 {
        struct platform_device                  *pdev;
-        struct omap_system_dma_plat_info        *p;
+        struct omap_system_dma_plat_info        p;
+        struct omap_dma_dev_attr                *d;
        struct resource                         *mem;
        char                                    *name = "omap_dma_system";
-        dma_stride              = OMAP2_DMA_STRIDE;
+        p = dma_plat_info;
-        dma_common_ch_start     = CSDP;
+        p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
+        p.errata = configure_dma_errata();
-        p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
-        if (!p) {
-                pr_err("%s: Unable to allocate pdata for %s:%s\n",
-                        __func__, name, oh->name);
-                return -ENOMEM;
-        }
-        p->dma_attr             = (struct omap_dma_dev_attr *)oh->dev_attr;
-        p->disable_irq_lch      = omap2_disable_irq_lch;
-        p->show_dma_caps        = omap2_show_dma_caps;
-        p->clear_dma            = omap2_clear_dma;
-        p->dma_write            = dma_write;
-        p->dma_read             = dma_read;
-        p->clear_lch_regs       = NULL;
-        p->errata               = configure_dma_errata();
-        pdev = omap_device_build(name, 0, oh, p, sizeof(*p));
+        pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
-        kfree(p);
        if (IS_ERR(pdev)) {
                pr_err("%s: Can't build omap_device for %s:%s.\n",
                        __func__, name, oh->name);
                return PTR_ERR(pdev);
        }
+        omap_dma_dev_info.res = pdev->resource;
+        omap_dma_dev_info.num_res = pdev->num_resources;
        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!mem) {
                dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
                return -EINVAL;
        }
        dma_base = ioremap(mem->start, resource_size(mem));
        if (!dma_base) {
                dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
@@ -269,13 +255,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
        }
        d = oh->dev_attr;
-        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
-                                        (d->lch_count), GFP_KERNEL);
-        if (!d->chan) {
-                dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
-                return -ENOMEM;
-        }
        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
                d->dev_caps |= HS_CHANNELS_RESERVED;
@@ -289,12 +268,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
        return 0;
 }
-static const struct platform_device_info omap_dma_dev_info = {
-        .name = "omap-dma-engine",
-        .id = -1,
-        .dma_mask = DMA_BIT_MASK(32),
-};
 static int __init omap2_system_dma_init(void)
 {
        struct platform_device *pdev;
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3c418ea54bbe..fcd8036af910 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -525,7 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
        * stuff is inherited for free
        */
-        if (!ret)
+        if (!ret && clk_get_parent(hw->clk) != new_parent)
                __clk_reparent(hw->clk, new_parent);
        return 0;
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index dadccc91488c..ea2be0f5953b 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -33,227 +33,5 @@
 #include "soc.h"
 #include "dss-common.h"
 #include "mux.h"
+#include "display.h"
-#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
-#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
-#define HDMI_GPIO_HPD  63 /* Hotplug detect */
-#define PANDA_DVI_TFP410_POWER_DOWN_GPIO        0
-/* DVI Connector */
-static struct connector_dvi_platform_data omap4_panda_dvi_connector_pdata = {
-        .name                   = "dvi",
-        .source                 = "tfp410.0",
-        .i2c_bus_num            = 2,
-};
-static struct platform_device omap4_panda_dvi_connector_device = {
-        .name                   = "connector-dvi",
-        .id                     = 0,
-        .dev.platform_data      = &omap4_panda_dvi_connector_pdata,
-};
-/* TFP410 DPI-to-DVI chip */
-static struct encoder_tfp410_platform_data omap4_panda_tfp410_pdata = {
-        .name                   = "tfp410.0",
-        .source                 = "dpi.0",
-        .data_lines             = 24,
-        .power_down_gpio        = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
-};
-static struct platform_device omap4_panda_tfp410_device = {
-        .name                   = "tfp410",
-        .id                     = 0,
-        .dev.platform_data      = &omap4_panda_tfp410_pdata,
-};
-/* HDMI Connector */
-static struct connector_hdmi_platform_data omap4_panda_hdmi_connector_pdata = {
-        .name                   = "hdmi",
-        .source                 = "tpd12s015.0",
-};
-static struct platform_device omap4_panda_hdmi_connector_device = {
-        .name                   = "connector-hdmi",
-        .id                     = 0,
-        .dev.platform_data      = &omap4_panda_hdmi_connector_pdata,
-};
-/* TPD12S015 HDMI ESD protection & level shifter chip */
-static struct encoder_tpd12s015_platform_data omap4_panda_tpd_pdata = {
-        .name                   = "tpd12s015.0",
-        .source                 = "hdmi.0",
-        .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
-        .ls_oe_gpio = HDMI_GPIO_LS_OE,
-        .hpd_gpio = HDMI_GPIO_HPD,
-};
-static struct platform_device omap4_panda_tpd_device = {
-        .name                   = "tpd12s015",
-        .id                     = 0,
-        .dev.platform_data      = &omap4_panda_tpd_pdata,
-};
-static struct omap_dss_board_info omap4_panda_dss_data = {
-        .default_display_name = "dvi",
-};
-void __init omap4_panda_display_init_of(void)
-{
-        omap_display_init(&omap4_panda_dss_data);
-        platform_device_register(&omap4_panda_tfp410_device);
-        platform_device_register(&omap4_panda_dvi_connector_device);
-        platform_device_register(&omap4_panda_tpd_device);
-        platform_device_register(&omap4_panda_hdmi_connector_device);
-}
-/* OMAP4 Blaze display data */
-#define DISPLAY_SEL_GPIO        59      /* LCD2/PicoDLP switch */
-#define DLP_POWER_ON_GPIO       40
-static struct panel_dsicm_platform_data dsi1_panel = {
-        .name           = "lcd",
-        .source         = "dsi.0",
-        .reset_gpio     = 102,
-        .use_ext_te     = false,
-        .ext_te_gpio    = 101,
-        .pin_config = {
-                .num_pins       = 6,
-                .pins           = { 0, 1, 2, 3, 4, 5 },
-        },
-};
-static struct platform_device sdp4430_lcd_device = {
-        .name                   = "panel-dsi-cm",
-        .id                     = 0,
-        .dev.platform_data      = &dsi1_panel,
-};
-static struct panel_dsicm_platform_data dsi2_panel = {
-        .name           = "lcd2",
-        .source         = "dsi.1",
-        .reset_gpio     = 104,
-        .use_ext_te     = false,
-        .ext_te_gpio    = 103,
-        .pin_config = {
-                .num_pins       = 6,
-                .pins           = { 0, 1, 2, 3, 4, 5 },
-        },
-};
-static struct platform_device sdp4430_lcd2_device = {
-        .name                   = "panel-dsi-cm",
-        .id                     = 1,
-        .dev.platform_data      = &dsi2_panel,
-};
-/* HDMI Connector */
-static struct connector_hdmi_platform_data sdp4430_hdmi_connector_pdata = {
-        .name                   = "hdmi",
-        .source                 = "tpd12s015.0",
-};
-static struct platform_device sdp4430_hdmi_connector_device = {
-        .name                   = "connector-hdmi",
-        .id                     = 0,
-        .dev.platform_data      = &sdp4430_hdmi_connector_pdata,
-};
-/* TPD12S015 HDMI ESD protection & level shifter chip */
-static struct encoder_tpd12s015_platform_data sdp4430_tpd_pdata = {
-        .name                   = "tpd12s015.0",
-        .source                 = "hdmi.0",
-        .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD,
-        .ls_oe_gpio = HDMI_GPIO_LS_OE,
-        .hpd_gpio = HDMI_GPIO_HPD,
-};
-static struct platform_device sdp4430_tpd_device = {
-        .name                   = "tpd12s015",
-        .id                     = 0,
-        .dev.platform_data      = &sdp4430_tpd_pdata,
-};
-static struct omap_dss_board_info sdp4430_dss_data = {
-        .default_display_name = "lcd",
-};
-/*
- * we select LCD2 by default (instead of Pico DLP) by setting DISPLAY_SEL_GPIO.
- * Setting DLP_POWER_ON gpio enables the VDLP_2V5 VDLP_1V8 and VDLP_1V0 rails
- * used by picodlp on the 4430sdp platform. Keep this gpio disabled as LCD2 is
- * selected by default
- */
-void __init omap_4430sdp_display_init_of(void)
-{
-        int r;
-        r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH,
-                        "display_sel");
-        if (r)
-                pr_err("%s: Could not get display_sel GPIO\n", __func__);
-        r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW,
-                "DLP POWER ON");
-        if (r)
-                pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__);
-        omap_display_init(&sdp4430_dss_data);
-        platform_device_register(&sdp4430_lcd_device);
-        platform_device_register(&sdp4430_lcd2_device);
-        platform_device_register(&sdp4430_tpd_device);
-        platform_device_register(&sdp4430_hdmi_connector_device);
-}
-/* OMAP3 IGEPv2 data */
-#define IGEP2_DVI_TFP410_POWER_DOWN_GPIO        170
-/* DVI Connector */
-static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = {
-        .name                   = "dvi",
-        .source                 = "tfp410.0",
-        .i2c_bus_num            = 2,
-};
-static struct platform_device omap3_igep2_dvi_connector_device = {
-        .name                   = "connector-dvi",
-        .id                     = 0,
-        .dev.platform_data      = &omap3_igep2_dvi_connector_pdata,
-};
-/* TFP410 DPI-to-DVI chip */
-static struct encoder_tfp410_platform_data omap3_igep2_tfp410_pdata = {
-        .name                   = "tfp410.0",
-        .source                 = "dpi.0",
-        .data_lines             = 24,
-        .power_down_gpio        = IGEP2_DVI_TFP410_POWER_DOWN_GPIO,
-};
-static struct platform_device omap3_igep2_tfp410_device = {
-        .name                   = "tfp410",
-        .id                     = 0,
-        .dev.platform_data      = &omap3_igep2_tfp410_pdata,
-};
-static struct omap_dss_board_info igep2_dss_data = {
-        .default_display_name = "dvi",
-};
-void __init omap3_igep2_display_init_of(void)
-{
-        omap_display_init(&igep2_dss_data);
-        platform_device_register(&omap3_igep2_tfp410_device);
-        platform_device_register(&omap3_igep2_dvi_connector_device);
-}
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 174caecc3186..4349e82debfe 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -45,24 +45,31 @@ static struct platform_device gpmc_nand_device = {
 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 {
-        /* support only OMAP3 class */
+        /* platforms which support all ECC schemes */
-        if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
+        if (soc_is_am33xx() || cpu_is_omap44xx() ||
-                pr_err("BCH ecc is not supported on this CPU\n");
+                 soc_is_omap54xx() || soc_is_dra7xx())
+                return 1;
+        /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
+         * which require H/W based ECC error detection */
+        if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&
+            ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
+                 (ecc_opt == OMAP_ECC_BCH8_CODE_HW)))
                return 0;
-        }
        /*
         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
         * and AM33xx derivates. Other chips may be added if confirmed to work.
         */
-        if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
+        if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) &&
-            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
+            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)))
-            (!soc_is_am33xx())) {
-                pr_err("BCH 4-bit mode is not supported on this CPU\n");
                return 0;
-        }
-        return 1;
+        /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
+        if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
+                return 1;
+        else
+                return 0;
 }
 /* This function will go away once the device-tree convertion is complete */
@@ -133,8 +140,10 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
        gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
-        if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
+        if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
+                dev_err(dev, "Unsupported NAND ECC scheme selected\n");
                return -EINVAL;
+        }
        err = platform_device_register(&gpmc_nand_device);
        if (err < 0) {
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9428c5f9d4f2..157412e4273a 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -465,8 +465,18 @@ void __init omap3xxx_check_revision(void)
                }
                break;
        case 0xb98c:
-                omap_revision = AM437X_REV_ES1_0;
+                switch (rev) {
-                cpu_rev = "1.0";
+                case 0:
+                        omap_revision = AM437X_REV_ES1_0;
+                        cpu_rev = "1.0";
+                        break;
+                case 1:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = AM437X_REV_ES1_1;
+                        cpu_rev = "1.1";
+                        break;
+                }
                break;
        case 0xb8f2:
                switch (rev) {
@@ -657,6 +667,8 @@ static const char * __init omap_get_family(void)
                return kasprintf(GFP_KERNEL, "OMAP4");
        else if (soc_is_omap54xx())
                return kasprintf(GFP_KERNEL, "OMAP5");
+        else if (soc_is_am43xx())
+                return kasprintf(GFP_KERNEL, "AM43xx");
        else
                return kasprintf(GFP_KERNEL, "Unknown");
 }
diff --git a/arch/arm/mach-omap2/include/mach/timex.h b/arch/arm/mach-omap2/include/mach/timex.h
deleted file mode 100644
index de9f8fc40e7c..000000000000
--- a/arch/arm/mach-omap2/include/mach/timex.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/timex.h
- */
-#include <plat/timex.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index af432b191255..f14f9ac2dca1 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -604,6 +604,7 @@ void __init am43xx_init_early(void)
        omap_prm_base_init();
        omap_cm_base_init();
        omap3xxx_check_revision();
+        am33xx_check_features();
        am43xx_powerdomains_init();
        am43xx_clockdomains_init();
        am43xx_hwmod_init();
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index e022a869bff2..6037a9a01ed5 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -222,6 +222,7 @@ void __init ti81xx_init_irq(void)
 static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
 {
        u32 irqnr;
+        int handled_irq = 0;
        do {
                irqnr = readl_relaxed(base_addr + 0x98);
@@ -249,8 +250,15 @@ out:
                if (irqnr) {
                        irqnr = irq_find_mapping(domain, irqnr);
                        handle_IRQ(irqnr, regs);
+                        handled_irq = 1;
                }
        } while (irqnr);
+        /* If an irq is masked or deasserted while active, we will
+         * keep ending up here with no irq handled. So remove it from
+         * the INTC with an ack.*/
+        if (!handled_irq)
+                omap_ack_irq(NULL);
 }
 asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index a722330d4d53..d121fb6df4e6 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -63,9 +63,6 @@
 #define OMAP_PACKAGE_CUS                5               /* 423-pin 0.65 */
 #define OMAP_PACKAGE_CBB                4               /* 515-pin 0.40 0.50 */
 #define OMAP_PACKAGE_CBC                3               /* 515-pin 0.50 0.65 */
-#define OMAP_PACKAGE_ZAC                2               /* 24xx 447-pin POP */
-#define OMAP_PACKAGE_ZAF                1               /* 2420 447-pin SIP */
 #define OMAP_MUX_NR_MODES               8               /* Available modes */
 #define OMAP_MUX_NR_SIDES               2               /* Bottom & top */
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index f6daae821ebb..f1fab5684a24 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -10,6 +10,7 @@
 * published by the Free Software Foundation.
 */
+#include <linux/of.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/err.h>
@@ -58,6 +59,10 @@ static int __init omap_iommu_dev_init(struct omap_hwmod *oh, void *unused)
 static int __init omap_iommu_init(void)
 {
+        /* If dtb is there, the devices will be created dynamically */
+        if (of_have_populated_dt())
+                return -ENODEV;
        return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL);
 }
 /* must be ready before omap3isp is probed */
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 3664562f9148..693fe486e917 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -138,7 +138,7 @@ static void wakeupgen_mask(struct irq_data *d)
        unsigned long flags;
        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
-        _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
+        _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
@@ -150,7 +150,7 @@ static void wakeupgen_unmask(struct irq_data *d)
        unsigned long flags;
        raw_spin_lock_irqsave(&wakeupgen_lock, flags);
-        _wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
+        _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
        raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 6cd3f3772ecf..95e171a055f3 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,6 +22,7 @@
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/irq-crossbar.h>
 #include <linux/of_address.h>
 #include <linux/reboot.h>
@@ -288,5 +289,8 @@ void __init omap_gic_of_init(void)
 skip_errata_init:
        omap_wakeupgen_init();
+#ifdef CONFIG_IRQ_CROSSBAR
+        irqcrossbar_init();
+#endif
        irqchip_init();
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 4c3b1e6df508..a123ff0070bd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1955,10 +1955,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
        .sysc = &omap3xxx_usb_host_hs_sysc,
 };
-static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
-          { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
-};
 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
        { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
        { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
@@ -1981,8 +1977,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
                        .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
                },
        },
-        .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
        /*
         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3029,8 +3023,6 @@ static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
        .flags          = HWMOD_NO_IDLEST,
 };
-#ifdef CONFIG_OMAP_IOMMU_IVA2
 /* mmu iva */
 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
@@ -3070,20 +3062,22 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
        .name           = "mmu_iva",
        .class          = &omap3xxx_mmu_hwmod_class,
        .mpu_irqs       = omap3xxx_mmu_iva_irqs,
+        .clkdm_name     = "iva2_clkdm",
        .rst_lines      = omap3xxx_mmu_iva_resets,
        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
        .main_clk       = "iva2_ck",
        .prcm = {
                .omap2 = {
                        .module_offs = OMAP3430_IVA2_MOD,
+                        .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
                },
        },
        .dev_attr       = &mmu_iva_dev_attr,
        .flags          = HWMOD_NO_IDLEST,
 };
-#endif
 /* l4_per -> gpio4 */
 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
        {
@@ -3855,9 +3849,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
        &omap3xxx_l4_core__hdq1w,
        &omap3xxx_sad2d__l3,
        &omap3xxx_l4_core__mmu_isp,
-#ifdef CONFIG_OMAP_IOMMU_IVA2
        &omap3xxx_l3_main__mmu_iva,
-#endif
        &omap34xx_l4_core__ssi,
        NULL
 };
@@ -3881,9 +3873,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
        &omap3xxx_l4_core__hdq1w,
        &omap3xxx_sad2d__l3,
        &omap3xxx_l4_core__mmu_isp,
-#ifdef CONFIG_OMAP_IOMMU_IVA2
        &omap3xxx_l3_main__mmu_iva,
-#endif
        NULL
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 9002fca76699..5c2cc8083fdd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -719,6 +719,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
        &am33xx_l4_ls__uart4,
        &am33xx_l4_ls__uart5,
        &am33xx_l4_ls__uart6,
+        &am33xx_l4_ls__spinlock,
        &am33xx_l4_ls__elm,
        &am33xx_l4_ls__epwmss0,
        &am33xx_epwmss0__ecap0,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3318cae96e7d..1219280bb976 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2541,8 +2541,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-                           SIDLE_SMART_WKUP),
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index e297d6231c3a..892317294fdc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -1122,6 +1122,71 @@ static struct omap_hwmod omap54xx_mmc5_hwmod = {
 };
 /*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
+        .name = "mmu",
+        .sysc = &omap54xx_mmu_sysc,
+};
+static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 1 },
+};
+static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
+        .name           = "mmu_dsp",
+        .class          = &omap54xx_mmu_hwmod_class,
+        .clkdm_name     = "dsp_clkdm",
+        .rst_lines      = omap54xx_mmu_dsp_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
+        .main_clk       = "dpll_iva_h11x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/* mmu ipu */
+static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 2 },
+};
+static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
+        .name           = "mmu_ipu",
+        .class          = &omap54xx_mmu_hwmod_class,
+        .clkdm_name     = "ipu_clkdm",
+        .rst_lines      = omap54xx_mmu_ipu_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
+        .main_clk       = "dpll_core_h22x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/*
 * 'mpu' class
 * mpu sub-system
 */
@@ -1763,6 +1828,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+/* l4_cfg -> mmu_dsp */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_mmu_dsp_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 /* mpu -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
        .master         = &omap54xx_mpu_hwmod,
@@ -1787,6 +1860,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+/* l3_main_2 -> mmu_ipu */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_mmu_ipu_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 /* l3_main_1 -> l3_main_3 */
 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
        .master         = &omap54xx_l3_main_1_hwmod,
@@ -2345,6 +2426,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
        &omap54xx_l4_wkup__counter_32k,
        &omap54xx_l4_cfg__dma_system,
        &omap54xx_l4_abe__dmic,
+        &omap54xx_l4_cfg__mmu_dsp,
        &omap54xx_mpu__emif1,
        &omap54xx_mpu__emif2,
        &omap54xx_l4_wkup__gpio1,
@@ -2360,6 +2442,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
        &omap54xx_l4_per__i2c3,
        &omap54xx_l4_per__i2c4,
        &omap54xx_l4_per__i2c5,
+        &omap54xx_l3_main_2__mmu_ipu,
        &omap54xx_l4_wkup__kbd,
        &omap54xx_l4_cfg__mailbox,
        &omap54xx_l4_abe__mcbsp1,
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index c33e07e2f0d4..c3b73351cb7a 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -16,12 +16,14 @@
 #include <linux/wl12xx.h>
 #include <linux/platform_data/pinctrl-single.h>
+#include <linux/platform_data/iommu-omap.h>
 #include "am35xx.h"
 #include "common.h"
 #include "common-board-devices.h"
 #include "dss-common.h"
 #include "control.h"
+#include "omap_device.h"
 #include "omap-secure.h"
 #include "soc.h"
@@ -33,20 +35,6 @@ struct pdata_init {
 struct of_dev_auxdata omap_auxdata_lookup[];
 static struct twl4030_gpio_platform_data twl_gpio_auxdata;
-/*
- * Create alias for USB host PHY clock.
- * Remove this when clock phandle can be provided via DT
- */
-static void __init __used legacy_init_ehci_clk(char *clkname)
-{
-        int ret;
-        ret = clk_add_alias("main_clk", NULL, clkname, NULL);
-        if (ret)
-                pr_err("%s:Failed to add main_clk alias to %s :%d\n",
-                       __func__, clkname, ret);
-}
 #if IS_ENABLED(CONFIG_WL12XX)
 static struct wl12xx_platform_data wl12xx __initdata;
@@ -94,6 +82,12 @@ static void __init hsmmc2_internal_input_clk(void)
        omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
 }
+static struct iommu_platform_data omap3_iommu_pdata = {
+        .reset_name = "mmu",
+        .assert_reset = omap_device_assert_hardreset,
+        .deassert_reset = omap_device_deassert_hardreset,
+};
 static int omap3_sbc_t3730_twl_callback(struct device *dev,
                                           unsigned gpio,
                                           unsigned ngpio)
@@ -101,7 +95,7 @@ static int omap3_sbc_t3730_twl_callback(struct device *dev,
        int res;
        res = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH,
-                               "wlan rst");
+                               "wlan pwr");
        if (res)
                return res;
@@ -110,6 +104,23 @@ static int omap3_sbc_t3730_twl_callback(struct device *dev,
        return 0;
 }
+static void __init omap3_sbc_t3x_usb_hub_init(int gpio, char *hub_name)
+{
+        int err = gpio_request_one(gpio, GPIOF_OUT_INIT_LOW, hub_name);
+        if (err) {
+                pr_err("SBC-T3x: %s reset gpio request failed: %d\n",
+                        hub_name, err);
+                return;
+        }
+        gpio_export(gpio, 0);
+        udelay(10);
+        gpio_set_value(gpio, 1);
+        msleep(1);
+}
 static void __init omap3_sbc_t3730_twl_init(void)
 {
        twl_gpio_auxdata.setup = omap3_sbc_t3730_twl_callback;
@@ -117,13 +128,19 @@ static void __init omap3_sbc_t3730_twl_init(void)
 static void __init omap3_sbc_t3730_legacy_init(void)
 {
+        omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136);
        omap_ads7846_init(1, 57, 0, NULL);
 }
+static void __init omap3_sbc_t3530_legacy_init(void)
+{
+        omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
+        omap_ads7846_init(1, 57, 0, NULL);
+}
 static void __init omap3_igep0020_legacy_init(void)
 {
-        omap3_igep2_display_init_of();
 }
 static void __init omap3_evm_legacy_init(void)
@@ -162,7 +179,7 @@ static struct emac_platform_data am35xx_emac_pdata = {
        .interrupt_disable      = am35xx_disable_emac_int,
 };
-static void __init am3517_evm_legacy_init(void)
+static void __init am35xx_emac_reset(void)
 {
        u32 v;
@@ -172,6 +189,43 @@ static void __init am3517_evm_legacy_init(void)
        omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
 }
+static struct gpio cm_t3517_wlan_gpios[] __initdata = {
+        { 56,   GPIOF_OUT_INIT_HIGH,    "wlan pwr" },
+        { 4,    GPIOF_OUT_INIT_HIGH,    "xcvr noe" },
+};
+static void __init omap3_sbc_t3517_wifi_init(void)
+{
+        int err = gpio_request_array(cm_t3517_wlan_gpios,
+                                ARRAY_SIZE(cm_t3517_wlan_gpios));
+        if (err) {
+                pr_err("SBC-T3517: wl12xx gpios request failed: %d\n", err);
+                return;
+        }
+        gpio_export(cm_t3517_wlan_gpios[0].gpio, 0);
+        gpio_export(cm_t3517_wlan_gpios[1].gpio, 0);
+        msleep(100);
+        gpio_set_value(cm_t3517_wlan_gpios[1].gpio, 0);
+}
+static void __init omap3_sbc_t3517_legacy_init(void)
+{
+        omap3_sbc_t3x_usb_hub_init(152, "cm-t3517 usb hub");
+        omap3_sbc_t3x_usb_hub_init(98, "sb-t35 usb hub");
+        am35xx_emac_reset();
+        hsmmc2_internal_input_clk();
+        omap3_sbc_t3517_wifi_init();
+        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 145);
+        omap_ads7846_init(1, 57, 0, NULL);
+}
+static void __init am3517_evm_legacy_init(void)
+{
+        am35xx_emac_reset();
+}
 static void __init nokia_n900_legacy_init(void)
 {
        hsmmc2_internal_input_clk();
@@ -192,23 +246,34 @@ static void __init nokia_n900_legacy_init(void)
 #ifdef CONFIG_ARCH_OMAP4
 static void __init omap4_sdp_legacy_init(void)
 {
-        omap_4430sdp_display_init_of();
        legacy_init_wl12xx(WL12XX_REFCLOCK_26,
                           WL12XX_TCXOCLOCK_26, 53);
 }
 static void __init omap4_panda_legacy_init(void)
 {
-        omap4_panda_display_init_of();
-        legacy_init_ehci_clk("auxclk3_ck");
        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53);
 }
 #endif
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+static struct iommu_platform_data omap4_iommu_pdata = {
+        .reset_name = "mmu_cache",
+        .assert_reset = omap_device_assert_hardreset,
+        .deassert_reset = omap_device_deassert_hardreset,
+};
+#endif
+#ifdef CONFIG_SOC_AM33XX
+static void __init am335x_evmsk_legacy_init(void)
+{
+        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 31);
+}
+#endif
 #ifdef CONFIG_SOC_OMAP5
 static void __init omap5_uevm_legacy_init(void)
 {
-        legacy_init_ehci_clk("auxclk1_ck");
 }
 #endif
@@ -259,6 +324,8 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
        OF_DEV_AUXDATA("ti,omap3-padconf", 0x480025a0, "480025a0.pinmux", &pcs_pdata),
        OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata),
+        OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
+                       &omap3_iommu_pdata),
        /* Only on am3517 */
        OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
        OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
@@ -268,6 +335,12 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
        OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
        OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata),
 #endif
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+        OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu",
+                       &omap4_iommu_pdata),
+        OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu",
+                       &omap4_iommu_pdata),
+#endif
        { /* sentinel */ },
 };
@@ -277,6 +350,8 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
 */
 static struct pdata_init pdata_quirks[] __initdata = {
 #ifdef CONFIG_ARCH_OMAP3
+        { "compulab,omap3-sbc-t3517", omap3_sbc_t3517_legacy_init, },
+        { "compulab,omap3-sbc-t3530", omap3_sbc_t3530_legacy_init, },
        { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, },
        { "nokia,omap3-n900", nokia_n900_legacy_init, },
        { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
@@ -290,6 +365,9 @@ static struct pdata_init pdata_quirks[] __initdata = {
        { "ti,omap4-sdp", omap4_sdp_legacy_init, },
        { "ti,omap4-panda", omap4_panda_legacy_init, },
 #endif
+#ifdef CONFIG_SOC_AM33XX
+        { "ti,am335x-evmsk", am335x_evmsk_legacy_init, },
+#endif
 #ifdef CONFIG_SOC_OMAP5
        { "ti,omap5-uevm", omap5_uevm_legacy_init, },
 #endif
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 7bdd22afce69..d4d0fce325c7 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -103,7 +103,7 @@ static inline void enable_omap3630_toggle_l2_on_restore(void) { }
 #define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD      (1 << 0)
-#if defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
 extern u16 pm44xx_errata;
 #define IS_PM44XX_ERRATUM(id)           (pm44xx_errata & (id))
 #else
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 280f3c58abe5..05fcf6de44ee 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -25,6 +25,7 @@
 #include "prminst44xx.h"
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
+#include "prcm43xx.h"
 #include "prcm_mpu44xx.h"
 #include "soc.h"
@@ -176,6 +177,8 @@ void omap4_prminst_global_warm_sw_reset(void)
                dev_inst = OMAP54XX_PRM_DEVICE_INST;
        else if (soc_is_dra7xx())
                dev_inst = DRA7XX_PRM_DEVICE_INST;
+        else if (soc_is_am43xx())
+                dev_inst = AM43XX_PRM_DEVICE_INST;
        else
                return;
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 076bd90a6ce0..30abcc8b20e0 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -438,7 +438,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define AM335X_REV_ES2_1        (AM335X_CLASS | (0x2 << 8))
 #define AM437X_CLASS            0x43700000
-#define AM437X_REV_ES1_0        AM437X_CLASS
+#define AM437X_REV_ES1_0        (AM437X_CLASS | (0x10 << 8))
+#define AM437X_REV_ES1_1        (AM437X_CLASS | (0x11 << 8))
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 74044aaf438b..b62de9f9d05c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -604,7 +604,8 @@ OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP3 */
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
+        defined(CONFIG_SOC_AM43XX)
 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
                       1, "timer_sys_ck", "ti,timer-alwon");
 #endif
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 2cb2f06c20f5..14f2cae4109c 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -33,7 +33,6 @@ config MACH_KUROBOX_PRO
 config MACH_DNS323
        bool "D-Link DNS-323"
        select I2C_BOARDINFO
-        select PHYLIB
        help
          Say 'Y' here if you want your kernel to support the
          D-Link DNS-323 platform.
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 70974732cbf0..56edeab17b68 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -642,6 +642,8 @@ static void __init dns323_init(void)
                platform_device_register_simple("dns323c-fan", 0, NULL, 0);
                /* Register fixup for the PHY LEDs */
+                if (!IS_BUILTIN(CONFIG_PHYLIB))
+                        break;
                phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
                                           MARVELL_PHY_ID_MASK,
                                           dns323c_phy_fixup);
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index f727d03f1688..5766e3fbff69 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -18,6 +18,7 @@
 #define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE + 0x104)
 #define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE + 0x108)
+#define RSTOUTn_MASK_PHYS       (ORION5X_BRIDGE_PHYS_BASE + 0x108)
 #define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
diff --git a/arch/arm/mach-orion5x/include/mach/timex.h b/arch/arm/mach-orion5x/include/mach/timex.h
deleted file mode 100644
index 4c69820e0810..000000000000
--- a/arch/arm/mach-orion5x/include/mach/timex.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/timex.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index b1022f4315f7..62240f69b4ee 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -1,12 +1,7 @@
 config ARCH_PICOXCELL
        bool "Picochip PicoXcell" if ARCH_MULTI_V6
        select ARCH_REQUIRE_GPIOLIB
-        select ARM_PATCH_PHYS_VIRT
        select ARM_VIC
-        select CPU_V6K
        select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
        select HAVE_TCM
-        select NO_IOPORT
+        select NO_IOPORT_MAP
-        select SPARSE_IRQ
-        select USE_OF
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 6988b117fc17..e4e505f52ba0 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -1,10 +1,9 @@
 config ARCH_SIRF
        bool "CSR SiRF" if ARCH_MULTI_V7
+        select ARCH_HAS_RESET_CONTROLLER
        select ARCH_REQUIRE_GPIOLIB
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select MIGHT_HAVE_CACHE_L2X0
+        select NO_IOPORT_MAP
-        select NO_IOPORT
        select PINCTRL
        select PINCTRL_SIRF
        help
@@ -17,7 +16,6 @@ menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
 config ARCH_ATLAS6
        bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
        default y
-        select CPU_V7
        select SIRF_IRQ
        help
          Support for CSR SiRFSoC ARM Cortex A9 Platform
@@ -25,7 +23,6 @@ config ARCH_ATLAS6
 config ARCH_PRIMA2
        bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
        default y
-        select CPU_V7
        select SIRF_IRQ
        select ZONE_DMA
        help
@@ -35,9 +32,7 @@ config ARCH_MARCO
        bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
        default y
        select ARM_GIC
-        select CPU_V7
        select HAVE_ARM_SCU if SMP
-        select HAVE_SMP
        select SMP_ON_UP if SMP
        help
          Support for CSR SiRFSoC ARM Cortex A9 Platform
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index d49aff74de98..47c7819edb9b 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -15,7 +15,7 @@
 #include <linux/of_platform.h>
 #include "common.h"
-void __init sirfsoc_init_late(void)
+static void __init sirfsoc_init_late(void)
 {
        sirfsoc_pm_init();
 }
@@ -27,7 +27,7 @@ static __init void sirfsoc_map_io(void)
 }
 #ifdef CONFIG_ARCH_ATLAS6
-static const char *atlas6_dt_match[] __initdata = {
+static const char *atlas6_dt_match[] __initconst = {
        "sirf,atlas6",
        NULL
 };
@@ -37,12 +37,11 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
        .map_io         = sirfsoc_map_io,
        .init_late      = sirfsoc_init_late,
        .dt_compat      = atlas6_dt_match,
-        .restart        = sirfsoc_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_ARCH_PRIMA2
-static const char *prima2_dt_match[] __initdata = {
+static const char *prima2_dt_match[] __initconst = {
        "sirf,prima2",
        NULL
 };
@@ -53,12 +52,11 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
        .dma_zone_size  = SZ_256M,
        .init_late      = sirfsoc_init_late,
        .dt_compat      = prima2_dt_match,
-        .restart        = sirfsoc_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_ARCH_MARCO
-static const char *marco_dt_match[] __initdata = {
+static const char *marco_dt_match[] __initconst = {
        "sirf,marco",
        NULL
 };
@@ -69,6 +67,5 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
        .map_io         = sirfsoc_map_io,
        .init_late      = sirfsoc_init_late,
        .dt_compat      = marco_dt_match,
-        .restart        = sirfsoc_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 4b768060a858..07d3e5ed9264 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -23,7 +23,6 @@ extern void sirfsoc_secondary_startup(void);
 extern void sirfsoc_cpu_die(unsigned int cpu);
 extern void __init sirfsoc_of_irq_init(void);
-extern void sirfsoc_restart(enum reboot_mode, const char *);
 extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
 #ifndef CONFIG_DEBUG_LL
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
index cbcbe9cb094c..c7102539c0b0 100644
--- a/arch/arm/mach-prima2/l2x0.c
+++ b/arch/arm/mach-prima2/l2x0.c
@@ -11,24 +11,23 @@
 #include <linux/of.h>
 #include <asm/hardware/cache-l2x0.h>
-struct l2x0_aux
+struct l2x0_aux {
-{
        u32 val;
        u32 mask;
 };
-static struct l2x0_aux prima2_l2x0_aux __initconst = {
+static const struct l2x0_aux prima2_l2x0_aux __initconst = {
        .val = 2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT,
        .mask = 0,
 };
-static struct l2x0_aux marco_l2x0_aux __initconst = {
+static const struct l2x0_aux marco_l2x0_aux __initconst = {
        .val = (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
                (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT),
        .mask = L2X0_AUX_CTRL_MASK,
 };
-static struct of_device_id sirf_l2x0_ids[] __initconst = {
+static const struct of_device_id sirf_l2x0_ids[] __initconst = {
        { .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, },
        { .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, },
        {},
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index e358b0736dea..335c12e92262 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -138,9 +138,9 @@ static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
 }
 struct smp_operations sirfsoc_smp_ops __initdata = {
-        .smp_prepare_cpus       = sirfsoc_smp_prepare_cpus,
+        .smp_prepare_cpus       = sirfsoc_smp_prepare_cpus,
-        .smp_secondary_init     = sirfsoc_secondary_init,
+        .smp_secondary_init     = sirfsoc_secondary_init,
-        .smp_boot_secondary     = sirfsoc_boot_secondary,
+        .smp_boot_secondary     = sirfsoc_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
        .cpu_die                = sirfsoc_cpu_die,
 #endif
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index ccb53391147a..4887a2a4c698 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -13,57 +13,38 @@
 #include <linux/device.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/platform_device.h>
 #include <linux/reboot.h>
+#include <linux/reset-controller.h>
-void __iomem *sirfsoc_rstc_base;
+#include <asm/system_misc.h>
-static DEFINE_MUTEX(rstc_lock);
-static struct of_device_id rstc_ids[]  = {
-        { .compatible = "sirf,prima2-rstc" },
-        { .compatible = "sirf,marco-rstc" },
-        {},
-};
-static int __init sirfsoc_of_rstc_init(void)
+#define SIRFSOC_RSTBIT_NUM      64
-{
-        struct device_node *np;
-        np = of_find_matching_node(NULL, rstc_ids);
+static void __iomem *sirfsoc_rstc_base;
-        if (!np) {
+static DEFINE_MUTEX(rstc_lock);
-                pr_err("unable to find compatible sirf rstc node in dtb\n");
-                return -ENOENT;
-        }
-        sirfsoc_rstc_base = of_iomap(np, 0);
-        if (!sirfsoc_rstc_base)
-                panic("unable to map rstc cpu registers\n");
-        of_node_put(np);
-        return 0;
-}
-early_initcall(sirfsoc_of_rstc_init);
-int sirfsoc_reset_device(struct device *dev)
+static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
+                                        unsigned long sw_reset_idx)
 {
-        u32 reset_bit;
+        u32 reset_bit = sw_reset_idx;
-        if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
+        if (reset_bit >= SIRFSOC_RSTBIT_NUM)
                return -EINVAL;
        mutex_lock(&rstc_lock);
-        if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
+        if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
                /*
                 * Writing 1 to this bit resets corresponding block. Writing 0 to this
                 * bit de-asserts reset signal of the corresponding block.
                 * datasheet doesn't require explicit delay between the set and clear
                 * of reset bit. it could be shorter if tests pass.
                 */
-                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
+                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit),
                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
                msleep(10);
-                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
+                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit),
                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
        } else {
                /*
@@ -73,9 +54,9 @@ int sirfsoc_reset_device(struct device *dev)
                 * datasheet doesn't require explicit delay between the set and clear
                 * of reset bit. it could be shorter if tests pass.
                 */
-                writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
+                writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
                msleep(10);
-                writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
+                writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
        }
        mutex_unlock(&rstc_lock);
@@ -83,9 +64,57 @@ int sirfsoc_reset_device(struct device *dev)
        return 0;
 }
+static struct reset_control_ops sirfsoc_rstc_ops = {
+        .reset = sirfsoc_reset_module,
+};
+static struct reset_controller_dev sirfsoc_reset_controller = {
+        .ops = &sirfsoc_rstc_ops,
+        .nr_resets = SIRFSOC_RSTBIT_NUM,
+};
 #define SIRFSOC_SYS_RST_BIT  BIT(31)
-void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
+static void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
 {
        writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
 }
+static int sirfsoc_rstc_probe(struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        sirfsoc_rstc_base = of_iomap(np, 0);
+        if (!sirfsoc_rstc_base) {
+                dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
+                return -ENOMEM;
+        }
+        sirfsoc_reset_controller.of_node = np;
+        arm_pm_restart = sirfsoc_restart;
+        if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
+                reset_controller_register(&sirfsoc_reset_controller);
+        return 0;
+}
+static const struct of_device_id rstc_ids[]  = {
+        { .compatible = "sirf,prima2-rstc" },
+        { .compatible = "sirf,marco-rstc" },
+        {},
+};
+static struct platform_driver sirfsoc_rstc_driver = {
+        .probe          = sirfsoc_rstc_probe,
+        .driver         = {
+                .name   = "sirfsoc_rstc",
+                .owner  = THIS_MODULE,
+                .of_match_table = rstc_ids,
+        },
+};
+static int __init sirfsoc_rstc_init(void)
+{
+        return platform_driver_register(&sirfsoc_rstc_driver);
+}
+subsys_initcall(sirfsoc_rstc_init);
diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c
index 9f2da2eec4dc..a17c88b74fa1 100644
--- a/arch/arm/mach-prima2/rtciobrg.c
+++ b/arch/arm/mach-prima2/rtciobrg.c
@@ -137,4 +137,4 @@ postcore_initcall(sirfsoc_rtciobrg_init);
 MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>, "
                "Barry Song <baohua.song@csr.com>");
 MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 96100dbf5a2e..e6690a44917d 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -7,7 +7,6 @@ comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
 config MACH_PXA3XX_DT
        bool "Support PXA3xx platforms from device tree"
        select CPU_PXA300
-        select HAVE_PWM
        select POWER_SUPPLY
        select PXA3xx
        select USE_OF
@@ -23,12 +22,10 @@ config ARCH_LUBBOCK
 config MACH_MAINSTONE
        bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
-        select HAVE_PWM
        select PXA27x
 config MACH_ZYLONITE
        bool
-        select HAVE_PWM
        select PXA3xx
 config MACH_ZYLONITE300
@@ -53,12 +50,16 @@ config MACH_TAVOREVB
        select CPU_PXA930
        select CPU_PXA935
        select PXA3xx
+        select FB
+        select FB_PXA
 config MACH_SAAR
        bool "PXA930 Handheld Platform (aka SAAR)"
        select CPU_PXA930
        select CPU_PXA935
        select PXA3xx
+        select FB
+        select FB_PXA
 comment "Third Party Dev Platforms (sorted by vendor name)"
@@ -69,8 +70,7 @@ config ARCH_PXA_IDP
 config ARCH_VIPER
        bool "Arcom/Eurotech VIPER SBC"
        select ARCOM_PCMCIA
-        select HAVE_PWM
+        select I2C_GPIO if I2C=y
-        select I2C_GPIO
        select ISA
        select PXA25x
        select PXA_HAVE_ISA_IRQS
@@ -120,7 +120,6 @@ config MACH_CM_X300
        bool "CompuLab CM-X300 modules"
        select CPU_PXA300
        select CPU_PXA310
-        select HAVE_PWM
        select PXA3xx
 config MACH_CAPC7117
@@ -164,7 +163,6 @@ config MACH_XCEP
        select MTD_CFI_INTELEXT
        select MTD_PHYSMAP
        select PXA25x
-        select SMC91X
        help
          PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash.
          Tuned for usage in Libera instruments for particle accelerators.
@@ -181,6 +179,7 @@ config MACH_TRIZEPS4
 config MACH_TRIZEPS4WL
        bool "Keith und Koep Trizeps4-WL DIMM-Module"
        depends on TRIZEPS_PXA
+        select MACH_TRIZEPS4
        select PXA27x
        select TRIZEPS_PCMCIA
@@ -211,7 +210,6 @@ config TRIZEPS_PCMCIA
 config MACH_LOGICPD_PXA270
        bool "LogicPD PXA270 Card Engine Development Platform"
-        select HAVE_PWM
        select PXA27x
 config MACH_PCM027
@@ -222,7 +220,6 @@ config MACH_PCM027
 config MACH_PCM990_BASEBOARD
        bool "PHYTEC PCM-990 development board"
        depends on MACH_PCM027
-        select HAVE_PWM
 choice
        prompt "display on pcm990"
@@ -246,7 +243,6 @@ config MACH_COLIBRI
 config MACH_COLIBRI_PXA270_INCOME
        bool "Income s.r.o. PXA270 SBC"
        depends on MACH_COLIBRI
-        select HAVE_PWM
        select PXA27x
 config MACH_COLIBRI300
@@ -275,7 +271,6 @@ comment "End-user Products (sorted by vendor name)"
 config MACH_H4700
        bool "HP iPAQ hx4700"
-        select HAVE_PWM
        select IWMMXT
        select PXA27x
@@ -289,14 +284,12 @@ config MACH_HIMALAYA
 config MACH_MAGICIAN
        bool "Enable HTC Magician Support"
-        select HAVE_PWM
        select IWMMXT
        select PXA27x
 config MACH_MIOA701
        bool "Mitac Mio A701 Support"
        select GPIO_SYSFS
-        select HAVE_PWM
        select IWMMXT
        select PXA27x
        help
@@ -306,7 +299,6 @@ config MACH_MIOA701
 config PXA_EZX
        bool "Motorola EZX Platform"
-        select HAVE_PWM
        select IWMMXT
        select PXA27x
@@ -346,7 +338,6 @@ config MACH_MP900C
 config ARCH_PXA_PALM
        bool "PXA based Palm PDAs"
-        select HAVE_PWM
 config MACH_PALM27X
        bool
@@ -444,7 +435,6 @@ config MACH_TREO680
 config MACH_RAUMFELD_RC
        bool "Raumfeld Controller"
        select CPU_PXA300
-        select HAVE_PWM
        select POWER_SUPPLY
        select PXA3xx
@@ -608,7 +598,6 @@ config MACH_E800
 config MACH_ZIPIT2
        bool "Zipit Z2 Handheld"
-        select HAVE_PWM
        select PXA27x
 endmenu
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 2f71b3fbd319..43596e0ed051 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -331,7 +331,6 @@ static struct pxa2xx_udc_mach_info balloon3_udc_info __initdata = {
 static void __init balloon3_udc_init(void)
 {
        pxa_set_udc_info(&balloon3_udc_info);
-        platform_device_register(&balloon3_gpio_vbus);
 }
 #else
 static inline void balloon3_udc_init(void) {}
diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c
index 8404b24240ea..638b0bb88426 100644
--- a/arch/arm/mach-pxa/colibri-evalboard.c
+++ b/arch/arm/mach-pxa/colibri-evalboard.c
@@ -20,6 +20,7 @@
 #include <asm/mach/arch.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
+#include <asm/io.h>
 #include <mach/pxa27x.h>
 #include <mach/colibri.h>
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index f162f1b77cd2..57d60542f982 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -32,6 +32,7 @@
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/gpio_keys.h>
 #include <linux/module.h>
 #include <video/w100fb.h>
@@ -405,6 +406,44 @@ static struct platform_device corgikbd_device = {
        },
 };
+static struct gpio_keys_button corgi_gpio_keys[] = {
+        {
+                .type   = EV_SW,
+                .code   = SW_LID,
+                .gpio   = CORGI_GPIO_SWA,
+                .desc   = "Lid close switch",
+                .debounce_interval = 500,
+        },
+        {
+                .type   = EV_SW,
+                .code   = SW_TABLET_MODE,
+                .gpio   = CORGI_GPIO_SWB,
+                .desc   = "Tablet mode switch",
+                .debounce_interval = 500,
+        },
+        {
+                .type   = EV_SW,
+                .code   = SW_HEADPHONE_INSERT,
+                .gpio   = CORGI_GPIO_AK_INT,
+                .desc   = "HeadPhone insert",
+                .debounce_interval = 500,
+        },
+};
+static struct gpio_keys_platform_data corgi_gpio_keys_platform_data = {
+        .buttons        = corgi_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(corgi_gpio_keys),
+        .poll_interval  = 250,
+};
+static struct platform_device corgi_gpio_keys_device = {
+        .name   = "gpio-keys-polled",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &corgi_gpio_keys_platform_data,
+        },
+};
 /*
 * Corgi LEDs
 */
@@ -646,6 +685,7 @@ static struct platform_device sharpsl_rom_device = {
 static struct platform_device *devices[] __initdata = {
        &corgiscoop_device,
        &corgifb_device,
+        &corgi_gpio_keys_device,
        &corgikbd_device,
        &corgiled_device,
        &corgi_audio_device,
diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h
deleted file mode 100644
index af6760a50e1a..000000000000
--- a/arch/arm/mach-pxa/include/mach/timex.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/timex.h
- *
- * Author:      Nicolas Pitre
- * Created:     Jun 15, 2001
- * Copyright:   MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/* Various drivers are still using the constant of CLOCK_TICK_RATE, for
- * those drivers to at least work, the definition is provided here.
- *
- * NOTE: this is no longer accurate when multiple processors and boards
- * are selected, newer drivers should not depend on this any more.  Use
- * either the clocksource/clockevent or get this at run-time by calling
- * get_clock_tick_rate() (as defined in generic.c).
- */
-#if defined(CONFIG_PXA25x)
-/* PXA250/210 timer base */
-#define CLOCK_TICK_RATE 3686400
-#elif defined(CONFIG_PXA27x)
-/* PXA27x timer base */
-#ifdef CONFIG_MACH_MAINSTONE
-#define CLOCK_TICK_RATE 3249600
-#else
-#define CLOCK_TICK_RATE 3250000
-#endif
-#else
-#define CLOCK_TICK_RATE 3250000
-#endif
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 29905b127ad9..41f27f667ca8 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -885,9 +885,6 @@ static int viper_cpufreq_notifier(struct notifier_block *nb,
                        viper_set_core_cpu_voltage(freq->new, 0);
                }
                break;
-        case CPUFREQ_RESUMECHANGE:
-                viper_set_core_cpu_voltage(freq->new, 0);
-                break;
        default:
                /* ignore */
                break;
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
new file mode 100644
index 000000000000..a028be234334
--- /dev/null
+++ b/arch/arm/mach-qcom/Kconfig
@@ -0,0 +1,33 @@
+config ARCH_QCOM
+        bool "Qualcomm Support" if ARCH_MULTI_V7
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_GIC
+        select CLKSRC_OF
+        select GENERIC_CLOCKEVENTS
+        select HAVE_SMP
+        select QCOM_SCM if SMP
+        help
+          Support for Qualcomm's devicetree based systems.
+if ARCH_QCOM
+menu "Qualcomm SoC Selection"
+config ARCH_MSM8X60
+        bool "Enable support for MSM8X60"
+        select CLKSRC_QCOM
+config ARCH_MSM8960
+        bool "Enable support for MSM8960"
+        select CLKSRC_QCOM
+config ARCH_MSM8974
+        bool "Enable support for MSM8974"
+        select HAVE_ARM_ARCH_TIMER
+endmenu
+config QCOM_SCM
+        bool
+endif
diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile
new file mode 100644
index 000000000000..8f756ae1ae31
--- /dev/null
+++ b/arch/arm/mach-qcom/Makefile
@@ -0,0 +1,5 @@
+obj-y                   := board.o
+obj-$(CONFIG_SMP)       += platsmp.o
+obj-$(CONFIG_QCOM_SCM)  += scm.o scm-boot.o
+CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-qcom/board.c
index 1f11d93e700e..bae617ef0b31 100644
--- a/arch/arm/mach-msm/board-dt.c
+++ b/arch/arm/mach-qcom/board.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014 The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -11,31 +11,16 @@
 */
 #include <linux/init.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include "common.h"
+static const char * const qcom_dt_match[] __initconst = {
-static const char * const msm_dt_match[] __initconst = {
-        "qcom,msm8660-fluid",
        "qcom,msm8660-surf",
        "qcom,msm8960-cdp",
-        NULL
-};
-static const char * const apq8074_dt_match[] __initconst = {
        "qcom,apq8074-dragonboard",
        NULL
 };
-DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
+DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)")
-        .smp = smp_ops(msm_smp_ops),
+        .dt_compat = qcom_dt_match,
-        .dt_compat = msm_dt_match,
-MACHINE_END
-DT_MACHINE_START(APQ_DT, "Qualcomm MSM (Flattened Device Tree)")
-        .dt_compat = apq8074_dt_match,
 MACHINE_END
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
new file mode 100644
index 000000000000..d6908569ecaf
--- /dev/null
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -0,0 +1,378 @@
+/*
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *  Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/smp_plat.h>
+#include "scm-boot.h"
+#define VDD_SC1_ARRAY_CLAMP_GFS_CTL     0x35a0
+#define SCSS_CPU1CORE_RESET             0x2d80
+#define SCSS_DBG_STATUS_CORE_PWRDUP     0x2e64
+#define APCS_CPU_PWR_CTL        0x04
+#define PLL_CLAMP               BIT(8)
+#define CORE_PWRD_UP            BIT(7)
+#define COREPOR_RST             BIT(5)
+#define CORE_RST                BIT(4)
+#define L2DT_SLP                BIT(3)
+#define CLAMP                   BIT(0)
+#define APC_PWR_GATE_CTL        0x14
+#define BHS_CNT_SHIFT           24
+#define LDO_PWR_DWN_SHIFT       16
+#define LDO_BYP_SHIFT           8
+#define BHS_SEG_SHIFT           1
+#define BHS_EN                  BIT(0)
+#define APCS_SAW2_VCTL          0x14
+#define APCS_SAW2_2_VCTL        0x1c
+extern void secondary_startup(void);
+static DEFINE_SPINLOCK(boot_lock);
+#ifdef CONFIG_HOTPLUG_CPU
+static void __ref qcom_cpu_die(unsigned int cpu)
+{
+        wfi();
+}
+#endif
+static void qcom_secondary_init(unsigned int cpu)
+{
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+static int scss_release_secondary(unsigned int cpu)
+{
+        struct device_node *node;
+        void __iomem *base;
+        node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");
+        if (!node) {
+                pr_err("%s: can't find node\n", __func__);
+                return -ENXIO;
+        }
+        base = of_iomap(node, 0);
+        of_node_put(node);
+        if (!base)
+                return -ENOMEM;
+        writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
+        writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
+        writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
+        mb();
+        iounmap(base);
+        return 0;
+}
+static int kpssv1_release_secondary(unsigned int cpu)
+{
+        int ret = 0;
+        void __iomem *reg, *saw_reg;
+        struct device_node *cpu_node, *acc_node, *saw_node;
+        u32 val;
+        cpu_node = of_get_cpu_node(cpu, NULL);
+        if (!cpu_node)
+                return -ENODEV;
+        acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
+        if (!acc_node) {
+                ret = -ENODEV;
+                goto out_acc;
+        }
+        saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
+        if (!saw_node) {
+                ret = -ENODEV;
+                goto out_saw;
+        }
+        reg = of_iomap(acc_node, 0);
+        if (!reg) {
+                ret = -ENOMEM;
+                goto out_acc_map;
+        }
+        saw_reg = of_iomap(saw_node, 0);
+        if (!saw_reg) {
+                ret = -ENOMEM;
+                goto out_saw_map;
+        }
+        /* Turn on CPU rail */
+        writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
+        mb();
+        udelay(512);
+        /* Krait bring-up sequence */
+        val = PLL_CLAMP | L2DT_SLP | CLAMP;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        val &= ~L2DT_SLP;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        ndelay(300);
+        val |= COREPOR_RST;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(2);
+        val &= ~CLAMP;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(2);
+        val &= ~COREPOR_RST;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(100);
+        val |= CORE_PWRD_UP;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        iounmap(saw_reg);
+out_saw_map:
+        iounmap(reg);
+out_acc_map:
+        of_node_put(saw_node);
+out_saw:
+        of_node_put(acc_node);
+out_acc:
+        of_node_put(cpu_node);
+        return ret;
+}
+static int kpssv2_release_secondary(unsigned int cpu)
+{
+        void __iomem *reg;
+        struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
+        void __iomem *l2_saw_base;
+        unsigned reg_val;
+        int ret;
+        cpu_node = of_get_cpu_node(cpu, NULL);
+        if (!cpu_node)
+                return -ENODEV;
+        acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
+        if (!acc_node) {
+                ret = -ENODEV;
+                goto out_acc;
+        }
+        l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
+        if (!l2_node) {
+                ret = -ENODEV;
+                goto out_l2;
+        }
+        saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
+        if (!saw_node) {
+                ret = -ENODEV;
+                goto out_saw;
+        }
+        reg = of_iomap(acc_node, 0);
+        if (!reg) {
+                ret = -ENOMEM;
+                goto out_map;
+        }
+        l2_saw_base = of_iomap(saw_node, 0);
+        if (!l2_saw_base) {
+                ret = -ENOMEM;
+                goto out_saw_map;
+        }
+        /* Turn on the BHS, turn off LDO Bypass and power down LDO */
+        reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
+        writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
+        mb();
+        /* wait for the BHS to settle */
+        udelay(1);
+        /* Turn on BHS segments */
+        reg_val |= 0x3f << BHS_SEG_SHIFT;
+        writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
+        mb();
+         /* wait for the BHS to settle */
+        udelay(1);
+        /* Finally turn on the bypass so that BHS supplies power */
+        reg_val |= 0x3f << LDO_BYP_SHIFT;
+        writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
+        /* enable max phases */
+        writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
+        mb();
+        udelay(50);
+        reg_val = COREPOR_RST | CLAMP;
+        writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(2);
+        reg_val &= ~CLAMP;
+        writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(2);
+        reg_val &= ~COREPOR_RST;
+        writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        reg_val |= CORE_PWRD_UP;
+        writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        ret = 0;
+        iounmap(l2_saw_base);
+out_saw_map:
+        iounmap(reg);
+out_map:
+        of_node_put(saw_node);
+out_saw:
+        of_node_put(l2_node);
+out_l2:
+        of_node_put(acc_node);
+out_acc:
+        of_node_put(cpu_node);
+        return ret;
+}
+static DEFINE_PER_CPU(int, cold_boot_done);
+static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
+{
+        int ret = 0;
+        if (!per_cpu(cold_boot_done, cpu)) {
+                ret = func(cpu);
+                if (!ret)
+                        per_cpu(cold_boot_done, cpu) = true;
+        }
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+        /*
+         * Send the secondary CPU a soft interrupt, thereby causing
+         * the boot monitor to read the system wide flags register,
+         * and branch to the address found there.
+         */
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+        return ret;
+}
+static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        return qcom_boot_secondary(cpu, scss_release_secondary);
+}
+static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        return qcom_boot_secondary(cpu, kpssv1_release_secondary);
+}
+static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        return qcom_boot_secondary(cpu, kpssv2_release_secondary);
+}
+static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int cpu, map;
+        unsigned int flags = 0;
+        static const int cold_boot_flags[] = {
+                0,
+                SCM_FLAG_COLDBOOT_CPU1,
+                SCM_FLAG_COLDBOOT_CPU2,
+                SCM_FLAG_COLDBOOT_CPU3,
+        };
+        for_each_present_cpu(cpu) {
+                map = cpu_logical_map(cpu);
+                if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) {
+                        set_cpu_present(cpu, false);
+                        continue;
+                }
+                flags |= cold_boot_flags[map];
+        }
+        if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags)) {
+                for_each_present_cpu(cpu) {
+                        if (cpu == smp_processor_id())
+                                continue;
+                        set_cpu_present(cpu, false);
+                }
+                pr_warn("Failed to set CPU boot address, disabling SMP\n");
+        }
+}
+static struct smp_operations smp_msm8660_ops __initdata = {
+        .smp_prepare_cpus       = qcom_smp_prepare_cpus,
+        .smp_secondary_init     = qcom_secondary_init,
+        .smp_boot_secondary     = msm8660_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = qcom_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
+static struct smp_operations qcom_smp_kpssv1_ops __initdata = {
+        .smp_prepare_cpus       = qcom_smp_prepare_cpus,
+        .smp_secondary_init     = qcom_secondary_init,
+        .smp_boot_secondary     = kpssv1_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = qcom_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
+static struct smp_operations qcom_smp_kpssv2_ops __initdata = {
+        .smp_prepare_cpus       = qcom_smp_prepare_cpus,
+        .smp_secondary_init     = qcom_secondary_init,
+        .smp_boot_secondary     = kpssv2_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = qcom_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);
diff --git a/arch/arm/mach-msm/scm-boot.c b/arch/arm/mach-qcom/scm-boot.c
index 45cee3e469a5..45cee3e469a5 100644
--- a/arch/arm/mach-msm/scm-boot.c
+++ b/arch/arm/mach-qcom/scm-boot.c
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-qcom/scm-boot.h
index 7be32ff5d687..6aabb2428176 100644
--- a/arch/arm/mach-msm/scm-boot.h
+++ b/arch/arm/mach-qcom/scm-boot.h
@@ -13,9 +13,11 @@
 #define __MACH_SCM_BOOT_H
 #define SCM_BOOT_ADDR                   0x1
-#define SCM_FLAG_COLDBOOT_CPU1          0x1
+#define SCM_FLAG_COLDBOOT_CPU1          0x01
-#define SCM_FLAG_WARMBOOT_CPU1          0x2
+#define SCM_FLAG_COLDBOOT_CPU2          0x08
-#define SCM_FLAG_WARMBOOT_CPU0          0x4
+#define SCM_FLAG_COLDBOOT_CPU3          0x20
+#define SCM_FLAG_WARMBOOT_CPU0          0x04
+#define SCM_FLAG_WARMBOOT_CPU1          0x02
 int scm_set_boot_addr(phys_addr_t addr, int flags);
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-qcom/scm.c
index c536fd6bf827..c536fd6bf827 100644
--- a/arch/arm/mach-msm/scm.c
+++ b/arch/arm/mach-qcom/scm.c
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-qcom/scm.h
index 00b31ea58f29..00b31ea58f29 100644
--- a/arch/arm/mach-msm/scm.h
+++ b/arch/arm/mach-qcom/scm.h
diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
index 2022e092f0ca..db09170e3832 100644
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -56,6 +56,8 @@
 #define PAGE_OFFSET1    (PAGE_OFFSET + 0x10000000)
 #define PAGE_OFFSET2    (PAGE_OFFSET + 0x30000000)
+#define PHYS_OFFSET PLAT_PHYS_OFFSET
 #define __phys_to_virt(phys)                                            \
        ((phys) >= 0x80000000 ? (phys) - 0x80000000 + PAGE_OFFSET2 :    \
         (phys) >= 0x20000000 ? (phys) - 0x20000000 + PAGE_OFFSET1 :    \
diff --git a/arch/arm/mach-realview/include/mach/timex.h b/arch/arm/mach-realview/include/mach/timex.h
deleted file mode 100644
index 4eeb069373c2..000000000000
--- a/arch/arm/mach-realview/include/mach/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *  arch/arm/mach-realview/include/mach/timex.h
- *
- *  RealView architecture timex specifications
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index cf073dea5784..1caee6d548b8 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -5,10 +5,8 @@ config ARCH_ROCKCHIP
        select ARCH_REQUIRE_GPIOLIB
        select ARM_GIC
        select CACHE_L2X0
+        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select DW_APB_TIMER_OF
        select ARM_GLOBAL_TIMER
        select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 1547d4fc920a..4377a1436a98 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-lpc32xx/include/mach/timex.h b/arch/arm/mach-rockchip/core.h
index 8d4066b16b3f..e2e7c9dbb200 100644
--- a/arch/arm/mach-lpc32xx/include/mach/timex.h
+++ b/arch/arm/mach-rockchip/core.h
@@ -1,9 +1,6 @@
 /*
- * arch/arm/mach-lpc32xx/include/mach/timex.h
+ * Copyright (c) 2013 MundoReader S.L.
- *
+ * Author: Heiko Stuebner <heiko@sntech.de>
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -16,13 +13,10 @@
 * GNU General Public License for more details.
 */
-#ifndef __ASM_ARCH_TIMEX_H
+extern char rockchip_secondary_trampoline;
-#define __ASM_ARCH_TIMEX_H
+extern char rockchip_secondary_trampoline_end;
-/*
+extern unsigned long rockchip_boot_fn;
- * Rate in Hz of the main system oscillator. This value should match
+extern void rockchip_secondary_startup(void);
- * the value 'MAIN_OSC_FREQ' in platform.h
- */
-#define CLOCK_TICK_RATE 13000000
-#endif
+extern struct smp_operations rockchip_smp_ops;
diff --git a/arch/arm/mach-versatile/include/mach/timex.h b/arch/arm/mach-rockchip/headsmp.S
index 426199b1add5..73206e360e31 100644
--- a/arch/arm/mach-versatile/include/mach/timex.h
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -1,9 +1,6 @@
 /*
- *  arch/arm/mach-versatile/include/mach/timex.h
+ * Copyright (c) 2013 MundoReader S.L.
- *
+ * Author: Heiko Stuebner <heiko@sntech.de>
- *  Versatile architecture timex specifications
- *
- *  Copyright (C) 2003 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -14,10 +11,20 @@
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/linkage.h>
+#include <linux/init.h>
+ENTRY(rockchip_secondary_startup)
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(rockchip_secondary_startup)
+ENTRY(rockchip_secondary_trampoline)
+        ldr     pc, 1f
+ENDPROC(rockchip_secondary_trampoline)
+        .globl  rockchip_boot_fn
+rockchip_boot_fn:
+1:      .space  4
-#define CLOCK_TICK_RATE         (50000000 / 16)
+ENTRY(rockchip_secondary_trampoline_end)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
new file mode 100644
index 000000000000..dbfa5a26cfff
--- /dev/null
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+#include <asm/mach/map.h>
+#include "core.h"
+static void __iomem *scu_base_addr;
+static void __iomem *sram_base_addr;
+static int ncores;
+#define PMU_PWRDN_CON           0x08
+#define PMU_PWRDN_ST            0x0c
+#define PMU_PWRDN_SCU           4
+static void __iomem *pmu_base_addr;
+static inline bool pmu_power_domain_is_on(int pd)
+{
+        return !(readl_relaxed(pmu_base_addr + PMU_PWRDN_ST) & BIT(pd));
+}
+static void pmu_set_power_domain(int pd, bool on)
+{
+        u32 val = readl_relaxed(pmu_base_addr + PMU_PWRDN_CON);
+        if (on)
+                val &= ~BIT(pd);
+        else
+                val |=  BIT(pd);
+        writel(val, pmu_base_addr + PMU_PWRDN_CON);
+        while (pmu_power_domain_is_on(pd) != on) { }
+}
+/*
+ * Handling of CPU cores
+ */
+static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
+                                             struct task_struct *idle)
+{
+        if (!sram_base_addr || !pmu_base_addr) {
+                pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
+                return -ENXIO;
+        }
+        if (cpu >= ncores) {
+                pr_err("%s: cpu %d outside maximum number of cpus %d\n",
+                                                        __func__, cpu, ncores);
+                return -ENXIO;
+        }
+        /* start the core */
+        pmu_set_power_domain(0 + cpu, true);
+        return 0;
+}
+/**
+ * rockchip_smp_prepare_sram - populate necessary sram block
+ * Starting cores execute the code residing at the start of the on-chip sram
+ * after power-on. Therefore make sure, this sram region is reserved and
+ * big enough. After this check, copy the trampoline code that directs the
+ * core to the real startup code in ram into the sram-region.
+ * @node: mmio-sram device node
+ */
+static int __init rockchip_smp_prepare_sram(struct device_node *node)
+{
+        unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
+                                            &rockchip_secondary_trampoline;
+        struct resource res;
+        unsigned int rsize;
+        int ret;
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret < 0) {
+                pr_err("%s: could not get address for node %s\n",
+                       __func__, node->full_name);
+                return ret;
+        }
+        rsize = resource_size(&res);
+        if (rsize < trampoline_sz) {
+                pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
+                       __func__, rsize, trampoline_sz);
+                return -EINVAL;
+        }
+        sram_base_addr = of_iomap(node, 0);
+        /* set the boot function for the sram code */
+        rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
+        /* copy the trampoline to sram, that runs during startup of the core */
+        memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
+        flush_cache_all();
+        outer_clean_range(0, trampoline_sz);
+        dsb_sev();
+        return 0;
+}
+static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *node;
+        unsigned int i;
+        node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+        if (!node) {
+                pr_err("%s: missing scu\n", __func__);
+                return;
+        }
+        scu_base_addr = of_iomap(node, 0);
+        if (!scu_base_addr) {
+                pr_err("%s: could not map scu registers\n", __func__);
+                return;
+        }
+        node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
+        if (!node) {
+                pr_err("%s: could not find sram dt node\n", __func__);
+                return;
+        }
+        if (rockchip_smp_prepare_sram(node))
+                return;
+        node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
+        if (!node) {
+                pr_err("%s: could not find sram dt node\n", __func__);
+                return;
+        }
+        pmu_base_addr = of_iomap(node, 0);
+        if (!pmu_base_addr) {
+                pr_err("%s: could not map pmu registers\n", __func__);
+                return;
+        }
+        /* enable the SCU power domain */
+        pmu_set_power_domain(PMU_PWRDN_SCU, true);
+        /*
+         * While the number of cpus is gathered from dt, also get the number
+         * of cores from the scu to verify this value when booting the cores.
+         */
+        ncores = scu_get_core_count(scu_base_addr);
+        scu_enable(scu_base_addr);
+        /* Make sure that all cores except the first are really off */
+        for (i = 1; i < ncores; i++)
+                pmu_set_power_domain(0 + i, false);
+}
+struct smp_operations rockchip_smp_ops __initdata = {
+        .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
+        .smp_boot_secondary     = rockchip_boot_secondary,
+};
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 82c0b0709712..d211d6fa0d98 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -22,6 +22,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "core.h"
 static void __init rockchip_dt_init(void)
 {
@@ -38,6 +39,7 @@ static const char * const rockchip_board_dt_compat[] = {
 };
 DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
+        .smp            = smp_ops(rockchip_smp_ops),
        .init_machine   = rockchip_dt_init,
        .dt_compat      = rockchip_board_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
index 85883b2e0e49..6d3517dc4772 100644
--- a/arch/arm/mach-rpc/dma.c
+++ b/arch/arm/mach-rpc/dma.c
@@ -141,7 +141,7 @@ static int iomd_request_dma(unsigned int chan, dma_t *dma)
        struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
        return request_irq(idma->irq, iomd_dma_handle,
-                           IRQF_DISABLED, idma->dma.device_id, idma);
+                           0, idma->dma.device_id, idma);
 }
 static void iomd_free_dma(unsigned int chan, dma_t *dma)
diff --git a/arch/arm/mach-rpc/include/mach/timex.h b/arch/arm/mach-rpc/include/mach/timex.h
deleted file mode 100644
index dd75e7387bbe..000000000000
--- a/arch/arm/mach-rpc/include/mach/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *  arch/arm/mach-rpc/include/mach/timex.h
- *
- *  Copyright (C) 1997, 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  RiscPC architecture timex specifications
- */
-/*
- * On the RiscPC, the clock ticks at 2MHz.
- */
-#define CLOCK_TICK_RATE         2000000
diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c
index 9a6def14df01..2689771c1d38 100644
--- a/arch/arm/mach-rpc/time.c
+++ b/arch/arm/mach-rpc/time.c
@@ -24,6 +24,9 @@
 #include <asm/mach/time.h>
+#define RPC_CLOCK_FREQ 2000000
+#define RPC_LATCH DIV_ROUND_CLOSEST(RPC_CLOCK_FREQ, HZ)
 static u32 ioc_timer_gettimeoffset(void)
 {
        unsigned int count1, count2, status;
@@ -46,23 +49,23 @@ static u32 ioc_timer_gettimeoffset(void)
                 * and count2.
                 */
                if (status & (1 << 5))
-                        offset -= LATCH;
+                        offset -= RPC_LATCH;
        } else if (count2 > count1) {
                /*
                 * We have just had another interrupt between reading
                 * count1 and count2.
                 */
-                offset -= LATCH;
+                offset -= RPC_LATCH;
        }
-        offset = (LATCH - offset) * (tick_nsec / 1000);
+        offset = (RPC_LATCH - offset) * (tick_nsec / 1000);
-        return ((offset + LATCH/2) / LATCH) * 1000;
+        return DIV_ROUND_CLOSEST(offset, RPC_LATCH) * 1000;
 }
 void __init ioctime_init(void)
 {
-        ioc_writeb(LATCH & 255, IOC_T0LTCHL);
+        ioc_writeb(RPC_LATCH & 255, IOC_T0LTCHL);
-        ioc_writeb(LATCH >> 8, IOC_T0LTCHH);
+        ioc_writeb(RPC_LATCH >> 8, IOC_T0LTCHH);
        ioc_writeb(0, IOC_T0GO);
 }
@@ -75,7 +78,6 @@ ioc_timer_interrupt(int irq, void *dev_id)
 static struct irqaction ioc_timer_irq = {
        .name           = "timer",
-        .flags          = IRQF_DISABLED,
        .handler        = ioc_timer_interrupt
 };
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index d876431d64c0..40cf50b9940c 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -12,7 +12,7 @@ if ARCH_S3C24XX
 config PLAT_S3C24XX
        def_bool y
        select ARCH_REQUIRE_GPIOLIB
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        select S3C_DEV_NAND
        select IRQ_DOMAIN
        help
@@ -521,7 +521,6 @@ config MACH_ANUBIS
        select HAVE_PATA_PLATFORM
        select S3C2440_XTAL_12000000
        select S3C24XX_DCLK
-        select S3C24XX_GPIO_EXTRA64
        select S3C24XX_SIMTEC_PM if PM
        select S3C_DEV_USB_HOST
        help
@@ -537,7 +536,7 @@ config MACH_AT2440EVB
 config MACH_MINI2440
        bool "MINI2440 development board"
-        select EEPROM_AT24
+        select EEPROM_AT24 if I2C
        select LEDS_CLASS
        select LEDS_TRIGGERS
        select LEDS_TRIGGER_BACKLIGHT
@@ -562,7 +561,6 @@ config MACH_OSIRIS
        select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
        select S3C2440_XTAL_12000000
        select S3C24XX_DCLK
-        select S3C24XX_GPIO_EXTRA128
        select S3C24XX_SIMTEC_PM if PM
        select S3C_DEV_NAND
        select S3C_DEV_USB_HOST
@@ -573,7 +571,7 @@ config MACH_OSIRIS
 config MACH_OSIRIS_DVS
        tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
        depends on MACH_OSIRIS
-        select TPS65010
+        depends on TPS65010
        help
          Say Y/M here if you want to have dynamic voltage scaling support
          on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index d39d3c787580..d1afcf9252d1 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -30,13 +30,12 @@
 #include <linux/mutex.h>
 #include <linux/delay.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index 11b3b28457bb..192a5b2550b0 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
@@ -31,13 +31,12 @@
 #include <linux/mutex.h>
 #include <linux/delay.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index aaf006d1d6dc..5527226fd61f 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -34,6 +34,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <mach/hardware.h>
 #include <linux/atomic.h>
@@ -43,7 +44,6 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
-#include <plat/regs-serial.h>
 /* S3C2440 extended clock support */
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 4adaa4b43ffe..1bc8e73c94f9 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -27,6 +27,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <clocksource/samsung_pwm.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
@@ -44,7 +45,6 @@
 #include <asm/mach/map.h>
 #include <mach/regs-gpio.h>
-#include <plat/regs-serial.h>
 #include <mach/dma.h>
 #include <plat/cpu.h>
@@ -240,7 +240,6 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
        } else {
                samsung_cpu_id = s3c24xx_read_idcode_v4();
        }
-        s3c24xx_init_cpu();
        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
@@ -484,7 +483,7 @@ struct platform_device s3c2440_device_dma = {
 };
 #endif
-#if defined(CONFIG_CPUS_3C2443) || defined(CONFIG_CPU_S3C2416)
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
 static struct resource s3c2443_dma_resource[] = {
        [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
        [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 30aa53ff07a6..09aa12da1789 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <mach/map.h>
 #include <mach/dma.h>
@@ -23,7 +24,6 @@
 #include <plat/cpu.h>
 #include <plat/dma-s3c24xx.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index b7e094671522..0c0106d1a4d1 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
 #include <mach/dma.h>
@@ -23,7 +24,6 @@
 #include <plat/dma-s3c24xx.h>
 #include <plat/cpu.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index cd25de28804c..2f8e8a3017df 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <mach/map.h>
 #include <mach/dma.h>
@@ -23,7 +24,6 @@
 #include <plat/dma-s3c24xx.h>
 #include <plat/cpu.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 95b9f759fe97..f4096ec0700a 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
 #include <mach/dma.h>
@@ -23,7 +24,6 @@
 #include <plat/dma-s3c24xx.h>
 #include <plat/cpu.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 2558952e3147..2f39737544c0 100644
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <plat/regs-serial.h>
+#include <linux/serial_s3c.h>
 #define S3C2410_UART1_OFF (0x4000)
 #define SHIFT_2440TXF (14-9)
diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
index a6cc14a092fc..dedd3837c193 100644
--- a/arch/arm/mach-s3c24xx/include/mach/hardware.h
+++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/hardware.h
+/*
- *
 * Copyright (c) 2003 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
@@ -17,20 +16,9 @@
 extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
-#ifdef CONFIG_CPU_S3C2440
-extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
-#endif /* CONFIG_CPU_S3C2440 */
 #endif /* __ASSEMBLY__ */
 #include <asm/sizes.h>
 #include <mach/map.h>
-/* machine specific hardware definitions should go after this */
-/* currently here until moved into config (todo) */
-#define CONFIG_NO_MULTIWORD_IO
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/plat-samsung/include/plat/rtc-core.h b/arch/arm/mach-s3c24xx/include/mach/rtc-core.h
index 7b542f7b7938..4d5f5768f700 100644
--- a/arch/arm/plat-samsung/include/plat/rtc-core.h
+++ b/arch/arm/mach-s3c24xx/include/mach/rtc-core.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-samsung/include/plat/rtc-core.h
+/*
- *
 * Copyright (c) 2011 Heiko Stuebner <heiko@sntech.de>
 *
 * Samsung RTC Controller core functions
@@ -9,19 +8,19 @@
 * published by the Free Software Foundation.
 */
-#ifndef __ASM_PLAT_RTC_CORE_H
+#ifndef __RTC_CORE_H
-#define __ASM_PLAT_RTC_CORE_H __FILE__
+#define __RTC_CORE_H __FILE__
 /* These functions are only for use with the core support code, such as
 * the cpu specific initialisation code
 */
+extern struct platform_device s3c_device_rtc;
 /* re-define device name depending on support. */
 static inline void s3c_rtc_setname(char *name)
 {
-#if defined(CONFIG_S3C_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
        s3c_device_rtc.name = name;
-#endif
 }
-#endif /* __ASM_PLAT_RTC_CORE_H */
+#endif /* __RTC_CORE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/tick.h b/arch/arm/mach-s3c24xx/include/mach/tick.h
deleted file mode 100644
index 544da41979db..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/tick.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* linux/arch/arm/mach-s3c2410/include/mach/tick.h
- *
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C2410 - timer tick support
- */
-#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
-static inline int s3c24xx_ostimer_pending(void)
-{
-        return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4;
-}
diff --git a/arch/arm/mach-s3c24xx/include/mach/timex.h b/arch/arm/mach-s3c24xx/include/mach/timex.h
deleted file mode 100644
index fe9ca1ffd51b..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/timex.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/timex.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-#define CLOCK_TICK_RATE 12000000
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
deleted file mode 100644
index 7d2ce205dce8..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/uncompress.h
- *
- * Copyright (c) 2003-2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/regs-gpio.h>
-#include <mach/map.h>
-/* working in physical space... */
-#undef S3C2410_GPIOREG
-#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
-#include <plat/uncompress.h>
-static inline int is_arm926(void)
-{
-        unsigned int cpuid;
-        asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
-        return ((cpuid & 0xff0) == 0x260);
-}
-static void arch_detect_cpu(void)
-{
-        unsigned int cpuid;
-        cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
-        cpuid &= S3C2410_GSTATUS1_IDMASK;
-        if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
-            cpuid == S3C2410_GSTATUS1_2442 ||
-            cpuid == S3C2410_GSTATUS1_2416 ||
-            cpuid == S3C2410_GSTATUS1_2450) {
-                fifo_mask = S3C2440_UFSTAT_TXMASK;
-                fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-        } else {
-                fifo_mask = S3C2410_UFSTAT_TXMASK;
-                fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
-        }
-        uart_base = (volatile u8 *) S3C_PA_UART +
-                (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 284ea1f44205..8ac9554aa996 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -37,6 +37,7 @@
 #include <linux/platform_device.h>
 #include <linux/proc_fs.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
 #include <asm/mach/arch.h>
@@ -49,7 +50,6 @@
 #include <asm/mach-types.h>
 #include <mach/fb.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-gpio.h>
 #include <mach/gpio-samsung.h>
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 2a16f8fb3584..81a270af2336 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/gpio.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
@@ -32,7 +33,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 6beab674c147..d8f6bb1096cb 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/dm9000.h>
 #include <linux/platform_device.h>
@@ -33,7 +34,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 981ba1eb9fdc..e371ff53a408 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -19,6 +19,7 @@
 #include <linux/gpio.h>
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/dm9000.h>
 #include <linux/ata_platform.h>
@@ -55,7 +56,6 @@
 #include <plat/cpu-freq.h>
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-serial.h>
 #include <plat/samsung-time.h>
 #include "bast.h"
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index d9170e9f8ccd..dc4db849f0fd 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -35,6 +35,7 @@
 #include <linux/workqueue.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/input.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
@@ -81,7 +82,6 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/pm.h>
-#include <plat/regs-serial.h>
 #include <plat/samsung-time.h>
 #include "common.h"
@@ -196,7 +196,7 @@ static void gta02_charger_worker(struct work_struct *work)
         * If the PCF50633 ADC is disabled we fallback to a
         * 100mA limit for safety.
         */
-        pcf50633_mbc_usb_curlim_set(pcf, 100);
+        pcf50633_mbc_usb_curlim_set(gta02_pcf, 100);
 #endif
 }
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index de0832181d8c..e453acd92cbf 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -62,7 +63,6 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
-#include <plat/regs-serial.h>
 #include <plat/samsung-time.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 67cb8e948b7e..5faa7239e7d6 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -19,6 +19,7 @@
 #include <linux/gpio.h>
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
@@ -31,7 +32,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <plat/regs-serial.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 1f1559713d8b..9e57fd9f4f3b 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -23,6 +23,7 @@
 #include <linux/input.h>
 #include <linux/io.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/dm9000.h>
 #include <linux/platform_data/at24.h>
 #include <linux/platform_device.h>
@@ -37,7 +38,6 @@
 #include <mach/fb.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-lcd.h>
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 997684f17930..4cccaad34847 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -24,6 +24,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/timer.h>
 #include <linux/io.h>
 #include <linux/mmc/host.h>
@@ -43,7 +44,6 @@
 #include <asm/mach/map.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/regs-serial.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 575d28c9e6c6..3066851f584d 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -21,6 +21,7 @@
 #include <linux/gpio.h>
 #include <linux/string.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -38,7 +39,6 @@
 //#include <asm/debug-ll.h>
 #include <mach/regs-gpio.h>
 #include <mach/gpio-samsung.h>
-#include <plat/regs-serial.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index f84f2a4c0c6d..a4ae4bb3666d 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -18,6 +18,7 @@
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/clk.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
@@ -44,7 +45,6 @@
 #include <plat/cpu-freq.h>
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-serial.h>
 #include <plat/samsung-time.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 7e16b0740ec1..bdb3faac2d9b 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -15,6 +15,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -32,7 +33,6 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/regs-serial.h>
 #include <plat/samsung-time.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index b534b76812e3..8c12787a8fd3 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -31,6 +31,7 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_gpio.h>
 #include <linux/io.h>
@@ -49,7 +50,6 @@
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <mach/regs-lcd.h>
-#include <plat/regs-serial.h>
 #include <mach/fb.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 0a5456cda1bc..afb784e934c8 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -21,6 +21,7 @@
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 #include <linux/device.h>
@@ -57,7 +58,6 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/regs-serial.h>
 #include <plat/samsung-time.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index b36edce8b2b8..e6535ce1bc5c 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -23,6 +23,7 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/serial.h>
 #include <linux/io.h>
 #include <linux/mtd/mtd.h>
@@ -49,7 +50,6 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/regs-serial.h>
 #include <plat/samsung-time.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
index f50454a34f72..70f0900d4bca 100644
--- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -19,13 +19,13 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <asm/mach/arch.h>
 #include <mach/map.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/regs-serial.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index a773789e4f38..f32924ee0e9f 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -35,6 +35,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -46,7 +47,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index f5bc721217e3..233fe52d2015 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/gpio.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -33,7 +34,6 @@
 #include <asm/mach-types.h>
 //#include <asm/debug-ll.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 12023cae4378..b3b54d8e1410 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -18,6 +18,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/partitions.h>
@@ -34,7 +35,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-s3c2443-clock.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index de2e5d39a847..d071dcfea548 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -20,6 +20,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -31,7 +32,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index d9933fcc6cc8..06c4d77de3a5 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -20,6 +20,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -31,7 +32,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 7fad8f055cab..4108b2f0cede 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -33,6 +33,7 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
 #include <asm/mach/arch.h>
@@ -44,7 +45,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index 755df489a45f..1cc5b1bd51cd 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -25,6 +25,7 @@
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
 #include <asm/mach/arch.h>
@@ -45,7 +46,6 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/regs-serial.h>
 #include <plat/samsung-time.h>
 #include "bast.h"
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index f7ec9c550787..40868c0e0a68 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -16,6 +16,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/mtd.h>
@@ -32,7 +33,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-lcd.h>
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 052ca23393a7..68ea5b7e5dc7 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -33,9 +33,9 @@
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-irq.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index ffb92cbca08c..04b58cb49888 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -21,6 +21,7 @@
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/reboot.h>
 #include <linux/io.h>
@@ -37,7 +38,6 @@
 #include <plat/cpu-freq.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0251650cbf80..657cbaca80ac 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -20,6 +20,7 @@
 #include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/reboot.h>
@@ -43,7 +44,6 @@
 #include <plat/nand-core.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
-#include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 8e01b4f2df35..9fe260ae11e1 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -48,6 +48,7 @@
 #include <asm/system_misc.h>
 #include <mach/regs-s3c2443-clock.h>
+#include <mach/rtc-core.h>
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
@@ -61,7 +62,6 @@
 #include <plat/fb-core.h>
 #include <plat/nand-core.h>
 #include <plat/adc-core.h>
-#include <plat/rtc-core.h>
 #include <plat/spi-core.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 886c2147062b..c7a804d0348e 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -34,6 +34,7 @@
 #include <asm/system_misc.h>
 #include <mach/regs-s3c2443-clock.h>
+#include <mach/rtc-core.h>
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
@@ -43,7 +44,6 @@
 #include <plat/fb-core.h>
 #include <plat/nand-core.h>
 #include <plat/adc-core.h>
-#include <plat/rtc-core.h>
 #include <plat/spi-core.h>
 static struct map_desc s3c2443_iodesc[] __initdata = {
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 911b555029fc..fe30ebb234d2 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -17,6 +17,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/reboot.h>
 #include <linux/device.h>
@@ -35,7 +36,6 @@
 #include <plat/cpu-freq.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index dd47c8fa07fa..c9b91223697c 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
@@ -25,13 +25,13 @@
 */
 #include <linux/linkage.h>
+#include <linux/serial_s3c.h>
 #include <asm/assembler.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
 #include "regs-mem.h"
diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c24xx/sleep.S
index 7f378b662da6..d833d616bd2e 100644
--- a/arch/arm/mach-s3c24xx/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep.S
@@ -25,13 +25,13 @@
 */
 #include <linux/linkage.h>
+#include <linux/serial_s3c.h>
 #include <asm/assembler.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
 /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
 * reset the UART configuration, only enable if you really need this!
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 64f04e6f9c31..3136d86b0d6e 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -86,8 +86,7 @@ config MACH_SMDK6400
       bool "SMDK6400"
        select CPU_S3C6400
        select S3C64XX_SETUP_SDHCI
-        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
-        select S3C_DEV_NAND
        help
          Machine support for the Samsung SMDK6400
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 76ab595d849b..5c45aae675b6 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -25,6 +25,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/reboot.h>
 #include <linux/io.h>
@@ -50,7 +51,6 @@
 #include <plat/irq-uart.h>
 #include <plat/pwm-core.h>
 #include <plat/regs-irqtype.h>
-#include <plat/regs-serial.h>
 #include <plat/watchdog-reset.h>
 #include "common.h"
diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
index dd9ccca5de1f..c9b95325b672 100644
--- a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
@@ -12,8 +12,8 @@
 /* pull in the relevant register and map files. */
+#include <linux/serial_s3c.h>
 #include <mach/map.h>
-#include <plat/regs-serial.h>
        /* note, for the boot process to work we have to keep the UART
         * virtual address aligned to an 1MiB boundary for the L1
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index c0537f40a3d8..a30a1e3ffc6a 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -15,6 +15,8 @@
 #ifndef __MACH_S3C64XX_PM_CORE_H
 #define __MACH_S3C64XX_PM_CORE_H __FILE__
+#include <linux/serial_s3c.h>
 #include <mach/regs-gpio.h>
 static inline void s3c_pm_debug_init_uart(void)
diff --git a/arch/arm/mach-s3c64xx/include/mach/tick.h b/arch/arm/mach-s3c64xx/include/mach/tick.h
deleted file mode 100644
index db9c1b1d56a4..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/tick.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/arch/arm/mach-s3c6400/include/mach/tick.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C64XX - Timer tick support definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TICK_H
-#define __ASM_ARCH_TICK_H __FILE__
-#include <linux/irqchip/arm-vic.h>
-/* note, the timer interrutps turn up in 2 places, the vic and then
- * the timer block. We take the VIC as the base at the moment.
- */
-static inline u32 s3c24xx_ostimer_pending(void)
-{
-        u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
-        return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
-}
-#define TICK_MAX        (0xffffffff)
-#endif /* __ASM_ARCH_6400_TICK_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/timex.h b/arch/arm/mach-s3c64xx/include/mach/timex.h
deleted file mode 100644
index fb2e8cd40829..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/timex.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s3c64xx/include/mach/timex.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C6400 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-#define CLOCK_TICK_RATE 12000000
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
deleted file mode 100644
index 1c956738b42d..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* arch/arm/mach-s3c6400/include/mach/uncompress.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C6400 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/map.h>
-#include <plat/uncompress.h>
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
-        fifo_mask = S3C2440_UFSTAT_TXMASK;
-        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-        uart_base = (volatile u8 *)S3C_PA_UART +
-                (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index 1649c0d1c1b8..ae4ea7601f60 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -20,13 +20,13 @@
 #include <linux/syscore_ops.h>
 #include <linux/interrupt.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <mach/map.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
@@ -55,7 +55,13 @@ static struct irq_grp_save {
        u32     mask;
 } eint_grp_save[5];
-static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
+#ifndef CONFIG_SERIAL_SAMSUNG_UARTS
+#define SERIAL_SAMSUNG_UARTS 0
+#else
+#define SERIAL_SAMSUNG_UARTS CONFIG_SERIAL_SAMSUNG_UARTS
+#endif
+static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS];
 static int s3c64xx_irq_pm_suspend(void)
 {
@@ -66,7 +72,7 @@ static int s3c64xx_irq_pm_suspend(void)
        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
-        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+        for (i = 0; i < SERIAL_SAMSUNG_UARTS; i++)
                irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
@@ -87,7 +93,7 @@ static void s3c64xx_irq_pm_resume(void)
        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
-        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+        for (i = 0; i < SERIAL_SAMSUNG_UARTS; i++)
                __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index ddeb0e51a962..55eb6a69655b 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -20,6 +20,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
@@ -41,7 +42,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 7ccfef227c77..9c00d83f7151 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -401,4 +401,4 @@ static int __init wlf_gf_module_register(void)
 {
        return i2c_add_driver(&wlf_gf_module_driver);
 }
-module_init(wlf_gf_module_register);
+device_initcall(wlf_gf_module_register);
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 3df3c372ee1f..4b0199fff9f5 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/fb.h>
 #include <linux/io.h>
@@ -51,7 +52,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/gpio-samsung.h>
-#include <plat/regs-serial.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
 #include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 0431016925b9..72cee08c8bf5 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -11,6 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
@@ -33,7 +34,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/gpio-samsung.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 8d553a418e1c..9cbc07602ef3 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -22,6 +22,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/types.h>
 #include <asm/mach-types.h>
@@ -38,7 +39,6 @@
 #include <plat/fb.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 #include <linux/platform_data/mmc-sdhci-s3c.h>
-#include <plat/regs-serial.h>
 #include <plat/sdhci.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 2067b0bf55b4..67f06a9ae656 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -16,6 +16,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
@@ -36,7 +37,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 5152026f0e19..fbad2af1ef16 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -23,6 +23,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/types.h>
 #include <asm/mach-types.h>
@@ -38,7 +39,6 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/regs-serial.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <video/platform_lcd.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 6e72bd5c1d0c..78dd6f73c072 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/pwm_backlight.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/spi/spi_gpio.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/platform_data/s3c-hsotg.h>
@@ -33,7 +34,6 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
 #include <linux/platform_data/hwmon-s3c.h>
-#include <plat/regs-serial.h>
 #include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/sdhci.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 150f55fb9e33..c85d1cbe769f 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -16,6 +16,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <linux/io.h>
@@ -29,8 +30,6 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
-#include <plat/regs-serial.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 43261d24a0a5..c6a8b2ab0240 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/input.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
@@ -55,7 +56,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/gpio-samsung.h>
 #include <linux/platform_data/ata-samsung_cf.h>
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index b5a66986a529..6b37694fa335 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -332,7 +332,6 @@ static __init int s3c64xx_pm_initcall(void)
 {
        pm_cpu_prep = s3c64xx_pm_prepare;
        pm_cpu_sleep = s3c64xx_cpu_suspend;
-        pm_uart_udivslot = 1;
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
        gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 3db0c98222f7..8c42807bf579 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
@@ -34,7 +35,6 @@
 #include <asm/irq.h>
 #include <plat/cpu-freq.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 72b2278953a8..5be3f09bac92 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
@@ -35,7 +36,6 @@
 #include <asm/irq.h>
 #include <plat/cpu-freq.h>
-#include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 42e14f2e7ca7..9a43be002d78 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <clocksource/samsung_pwm.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
@@ -50,7 +51,6 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pwm-core.h>
 #include <plat/regs-irqtype.h>
-#include <plat/regs-serial.h>
 #include <plat/watchdog-reset.h>
 #include "common.h"
@@ -205,6 +205,7 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
        samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
 }
+#ifdef CONFIG_CPU_S5P6440
 void __init s5p6440_map_io(void)
 {
        /* initialize any device information early */
@@ -218,7 +219,9 @@ void __init s5p6440_map_io(void)
        iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
 }
+#endif
+#ifdef CONFIG_CPU_S5P6450
 void __init s5p6450_map_io(void)
 {
        /* initialize any device information early */
@@ -232,13 +235,14 @@ void __init s5p6450_map_io(void)
        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
 }
+#endif
 /*
 * s5p64x0_init_clocks
 *
 * register and setup the CPU clocks
 */
+#ifdef CONFIG_CPU_S5P6440
 void __init s5p6440_init_clocks(int xtal)
 {
        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -248,7 +252,9 @@ void __init s5p6440_init_clocks(int xtal)
        s5p6440_register_clocks();
        s5p6440_setup_clocks();
 }
+#endif
+#ifdef CONFIG_CPU_S5P6450
 void __init s5p6450_init_clocks(int xtal)
 {
        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -258,13 +264,14 @@ void __init s5p6450_init_clocks(int xtal)
        s5p6450_register_clocks();
        s5p6450_setup_clocks();
 }
+#endif
 /*
 * s5p64x0_init_irq
 *
 * register the CPU interrupts
 */
+#ifdef CONFIG_CPU_S5P6440
 void __init s5p6440_init_irq(void)
 {
        /* S5P6440 supports 2 VIC */
@@ -279,7 +286,9 @@ void __init s5p6440_init_irq(void)
        s5p_init_irq(vic, ARRAY_SIZE(vic));
 }
+#endif
+#ifdef CONFIG_CPU_S5P6450
 void __init s5p6450_init_irq(void)
 {
        /* S5P6450 supports only 2 VIC */
@@ -294,6 +303,7 @@ void __init s5p6450_init_irq(void)
        s5p_init_irq(vic, ARRAY_SIZE(vic));
 }
+#endif
 struct bus_type s5p64x0_subsys = {
        .name           = "s5p64x0-core",
@@ -321,6 +331,7 @@ int __init s5p64x0_init(void)
 }
 /* uart registration process */
+#ifdef CONFIG_CPU_S5P6440
 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
        int uart;
@@ -332,11 +343,14 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
+#endif
+#ifdef CONFIG_CPU_S5P6450
 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 }
+#endif
 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
index f3a9b43cba4a..cbe7f3d731d0 100644
--- a/arch/arm/mach-s5p64x0/common.h
+++ b/arch/arm/mach-s5p64x0/common.h
@@ -25,10 +25,10 @@ void s5p6450_register_clocks(void);
 void s5p6450_setup_clocks(void);
 void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
+extern  int s5p64x0_init(void);
 #ifdef CONFIG_CPU_S5P6440
-extern  int s5p64x0_init(void);
 extern void s5p6440_map_io(void);
 extern void s5p6440_init_clocks(int xtal);
@@ -38,12 +38,10 @@ extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 #define s5p6440_init_clocks NULL
 #define s5p6440_init_uarts NULL
 #define s5p6440_map_io NULL
-#define s5p64x0_init NULL
 #endif
 #ifdef CONFIG_CPU_S5P6450
-extern  int s5p64x0_init(void);
 extern void s5p6450_map_io(void);
 extern void s5p6450_init_clocks(int xtal);
@@ -53,7 +51,6 @@ extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 #define s5p6450_init_clocks NULL
 #define s5p6450_init_uarts NULL
 #define s5p6450_map_io NULL
-#define s5p64x0_init NULL
 #endif
 #endif /* __ARCH_ARM_MACH_S5P64X0_COMMON_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
index 5e2916fb19a9..8759e7882bcb 100644
--- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
@@ -10,11 +10,10 @@
 /* pull in the relevant register and map files. */
+#include <linux/serial_s3c.h>
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
-#include <plat/regs-serial.h>
        .macro addruart, rp, rv, tmp
                mov     \rp, #0xE0000000
                orr     \rp, \rp, #0x00100000
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
index e52f7545d3aa..1e0eb65b2b82 100644
--- a/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
@@ -12,6 +12,8 @@
 * published by the Free Software Foundation.
 */
+#include <linux/serial_s3c.h>
 #include <mach/regs-gpio.h>
 static inline void s3c_pm_debug_init_uart(void)
diff --git a/arch/arm/mach-s5p64x0/include/mach/timex.h b/arch/arm/mach-s5p64x0/include/mach/timex.h
deleted file mode 100644
index 4b91faa195a8..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/timex.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/timex.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S5P64X0 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-#define CLOCK_TICK_RATE 12000000
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
deleted file mode 100644
index bbcc3f669ee3..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/map.h>
-#include <plat/uncompress.h>
-static void arch_detect_cpu(void)
-{
-        unsigned int chipid;
-        chipid = *(const volatile unsigned int __force *) 0xE0100118;
-        if ((chipid & 0xff000) == 0x50000)
-                uart_base = (volatile u8 *)S5P6450_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
-        else
-                uart_base = (volatile u8 *)S5P6440_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
-        fifo_mask = S3C2440_UFSTAT_TXMASK;
-        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c
index 3e6f2456ee9d..2ed921e095dc 100644
--- a/arch/arm/mach-s5p64x0/irq-pm.c
+++ b/arch/arm/mach-s5p64x0/irq-pm.c
@@ -14,9 +14,9 @@
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
-#include <plat/regs-serial.h>
 #include <plat/pm.h>
 #include <mach/regs-gpio.h>
@@ -34,7 +34,9 @@ static struct irq_grp_save {
        u32     mask;
 } eint_grp_save[4];
+#ifdef CONFIG_SERIAL_SAMSUNG
 static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
+#endif
 static int s5p64x0_irq_pm_suspend(void)
 {
@@ -45,8 +47,10 @@ static int s5p64x0_irq_pm_suspend(void)
        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+#ifdef CONFIG_SERIAL_SAMSUNG
        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
                irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
+#endif
        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
                grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
@@ -66,8 +70,10 @@ static void s5p64x0_irq_pm_resume(void)
        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+#ifdef CONFIG_SERIAL_SAMSUNG
        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
                __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
+#endif
        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
                __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 9efdcc03df3b..6840e197cb2d 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/i2c.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -39,7 +40,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
-#include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index c3cacc067efe..fa1341c074ca 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/i2c.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -39,7 +40,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
-#include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 861e15cea691..ec8229cee716 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -161,7 +161,6 @@ static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
 {
        pm_cpu_prep = s5p64x0_pm_prepare;
        pm_cpu_sleep = s5p64x0_cpu_suspend;
-        pm_uart_udivslot = 1;
        return 0;
 }
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index c5a8eeacf81c..6a41bf7dacf6 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <clocksource/samsung_pwm.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
@@ -49,7 +50,6 @@
 #include <plat/onenand-core.h>
 #include <plat/pwm-core.h>
 #include <plat/spi-core.h>
-#include <plat/regs-serial.h>
 #include <plat/watchdog-reset.h>
 #include "common.h"
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index 66cb7f16bf2a..22c23859e45e 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -13,8 +13,8 @@
 /* pull in the relevant register and map files. */
+#include <linux/serial_s3c.h>
 #include <mach/map.h>
-#include <plat/regs-serial.h>
        /* note, for the boot process to work we have to keep the UART
         * virtual address aligned to an 1MiB boundary for the L1
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
deleted file mode 100644
index 0af8e41230ed..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/tick.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S3C64XX - Timer tick support definitions
- *
- * Based on mach-s3c6400/include/mach/tick.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TICK_H
-#define __ASM_ARCH_TICK_H __FILE__
-#include <linux/irqchip/arm-vic.h>
-/* note, the timer interrutps turn up in 2 places, the vic and then
- * the timer block. We take the VIC as the base at the moment.
- */
-static inline u32 s3c24xx_ostimer_pending(void)
-{
-        u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
-        return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
-}
-#define TICK_MAX        (0xffffffff)
-#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/timex.h b/arch/arm/mach-s5pc100/include/mach/timex.h
deleted file mode 100644
index 47ffb17aff96..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/timex.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/timex.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C6400 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-#define CLOCK_TICK_RATE 12000000
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h
deleted file mode 100644
index 720e1339425c..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/uncompress.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/uncompress.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - uncompress code
- *
- * Based on mach-s3c6400/include/mach/uncompress.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/map.h>
-#include <plat/uncompress.h>
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
-        fifo_mask = S3C2440_UFSTAT_TXMASK;
-        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
-        uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 9e256b9fc930..668af3ac31f3 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -16,6 +16,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -37,7 +38,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
-#include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index caaedafbbf5f..8c3abe521757 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -189,6 +189,7 @@ config MACH_TORBRECK
        select S5PV210_SETUP_I2C1
        select S5PV210_SETUP_I2C2
        select S5PV210_SETUP_SDHCI
+        select SAMSUNG_DEV_IDE
        help
          Machine support for aESOP Torbreck
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 26027a29b8a1..7024dcd0e40a 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -24,6 +24,7 @@
 #include <linux/sched.h>
 #include <linux/dma-mapping.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <asm/proc-fns.h>
 #include <asm/mach/arch.h>
@@ -46,7 +47,6 @@
 #include <plat/pwm-core.h>
 #include <plat/tv-core.h>
 #include <plat/spi-core.h>
-#include <plat/regs-serial.h>
 #include "common.h"
diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
index 80c21996c943..30b511a580aa 100644
--- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
@@ -12,8 +12,8 @@
 /* pull in the relevant register and map files. */
+#include <linux/serial_s3c.h>
 #include <mach/map.h>
-#include <plat/regs-serial.h>
        /* note, for the boot process to work we have to keep the UART
         * virtual address aligned to an 1MiB boundary for the L1
diff --git a/arch/arm/mach-s5pv210/include/mach/timex.h b/arch/arm/mach-s5pv210/include/mach/timex.h
deleted file mode 100644
index 73dc85496a83..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/timex.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/timex.h
- *
- * Copyright (c) 2003-2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Based on arch/arm/mach-s5p6442/include/mach/timex.h
- *
- * S5PV210 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H __FILE__
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-#define CLOCK_TICK_RATE 12000000
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h
deleted file mode 100644
index 231cb07de058..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/uncompress.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/uncompress.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/map.h>
-#include <plat/uncompress.h>
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
-        fifo_mask = S5PV210_UFSTAT_TXMASK;
-        fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT;
-        uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
-}
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index ad40ab0f5dbd..cc37edacda26 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/fb.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -32,7 +33,6 @@
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-serial.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e5cd9fbf19e9..b41a38a75844 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/fb.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -39,7 +40,6 @@
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-serial.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 7c0ed07a78a3..448e1d2eeed6 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/i2c.h>
 #include <linux/device.h>
@@ -23,7 +24,6 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/ata-samsung_cf.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index f52cc15c2d85..2a6655fb63e7 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -13,6 +13,7 @@
 #include <linux/i2c.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/device.h>
 #include <linux/dm9000.h>
 #include <linux/fb.h>
@@ -32,7 +33,6 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 579afe89842a..157805529f26 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -13,6 +13,7 @@
 #include <linux/i2c.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -22,7 +23,6 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 831a15824ec8..f9874ba60cc8 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -43,6 +43,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
+#include <asm/mach/irda.h>
 #include <asm/hardware/scoop.h>
 #include <asm/mach/sharpsl_param.h>
@@ -96,6 +97,37 @@ static struct mcp_plat_data collie_mcp_data = {
        .codec_pdata    = &collie_ucb1x00_data,
 };
+static int collie_ir_startup(struct device *dev)
+{
+        int rc = gpio_request(COLLIE_GPIO_IR_ON, "IrDA");
+        if (rc)
+                return rc;
+        rc = gpio_direction_output(COLLIE_GPIO_IR_ON, 1);
+        if (!rc)
+                return 0;
+        gpio_free(COLLIE_GPIO_IR_ON);
+        return rc;
+}
+static void collie_ir_shutdown(struct device *dev)
+{
+        gpio_free(COLLIE_GPIO_IR_ON);
+}
+static int collie_ir_set_power(struct device *dev, unsigned int state)
+{
+        gpio_set_value(COLLIE_GPIO_IR_ON, !state);
+        return 0;
+}
+static struct irda_platform_data collie_ir_data = {
+        .startup = collie_ir_startup,
+        .shutdown = collie_ir_shutdown,
+        .set_power = collie_ir_set_power,
+};
 /*
 * Collie AC IN
 */
@@ -400,6 +432,7 @@ static void __init collie_init(void)
        sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
                            ARRAY_SIZE(collie_flash_resources));
        sa11x0_register_mcp(&collie_mcp_data);
+        sa11x0_register_irda(&collie_ir_data);
        sharpsl_save_param();
 }
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index daa27c474c13..3c43219bc881 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -122,15 +122,8 @@ static struct irda_platform_data h3100_irda_data = {
        .shutdown       = h3100_irda_shutdown,
 };
-static struct gpio_default_state h3100_default_gpio[] = {
-        { H3XXX_GPIO_COM_DCD,   GPIO_MODE_IN,   "COM DCD" },
-        { H3XXX_GPIO_COM_CTS,   GPIO_MODE_IN,   "COM CTS" },
-        { H3XXX_GPIO_COM_RTS,   GPIO_MODE_OUT0, "COM RTS" },
-};
 static void __init h3100_mach_init(void)
 {
-        h3xxx_init_gpio(h3100_default_gpio, ARRAY_SIZE(h3100_default_gpio));
        h3xxx_mach_init();
        sa11x0_register_lcd(&h3100_lcd_info);
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index a663e7230141..5be54c214c7c 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -130,15 +130,8 @@ static struct irda_platform_data h3600_irda_data = {
        .shutdown       = h3600_irda_shutdown,
 };
-static struct gpio_default_state h3600_default_gpio[] = {
-        { H3XXX_GPIO_COM_DCD,   GPIO_MODE_IN,   "COM DCD" },
-        { H3XXX_GPIO_COM_CTS,   GPIO_MODE_IN,   "COM CTS" },
-        { H3XXX_GPIO_COM_RTS,   GPIO_MODE_OUT0, "COM RTS" },
-};
 static void __init h3600_mach_init(void)
 {
-        h3xxx_init_gpio(h3600_default_gpio, ARRAY_SIZE(h3600_default_gpio));
        h3xxx_mach_init();
        sa11x0_register_lcd(&h3600_lcd_info);
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
index f17e7382242a..c79bf467fb7f 100644
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -28,37 +28,6 @@
 #include "generic.h"
-void h3xxx_init_gpio(struct gpio_default_state *s, size_t n)
-{
-        while (n--) {
-                const char *name = s->name;
-                int err;
-                if (!name)
-                        name = "[init]";
-                err = gpio_request(s->gpio, name);
-                if (err) {
-                        printk(KERN_ERR "gpio%u: unable to request: %d\n",
-                                s->gpio, err);
-                        continue;
-                }
-                if (s->mode >= 0) {
-                        err = gpio_direction_output(s->gpio, s->mode);
-                } else {
-                        err = gpio_direction_input(s->gpio);
-                }
-                if (err) {
-                        printk(KERN_ERR "gpio%u: unable to set direction: %d\n",
-                                s->gpio, err);
-                        continue;
-                }
-                if (!s->name)
-                        gpio_free(s->gpio);
-                s++;
-        }
-}
 /*
 * H3xxx flash support
 */
@@ -116,9 +85,34 @@ static struct resource h3xxx_flash_resource =
 /*
 * H3xxx uart support
 */
+static struct gpio h3xxx_uart_gpio[] = {
+        { H3XXX_GPIO_COM_DCD,   GPIOF_IN,               "COM DCD" },
+        { H3XXX_GPIO_COM_CTS,   GPIOF_IN,               "COM CTS" },
+        { H3XXX_GPIO_COM_RTS,   GPIOF_OUT_INIT_LOW,     "COM RTS" },
+};
+static bool h3xxx_uart_request_gpios(void)
+{
+        static bool h3xxx_uart_gpio_ok;
+        int rc;
+        if (h3xxx_uart_gpio_ok)
+                return true;
+        rc = gpio_request_array(h3xxx_uart_gpio, ARRAY_SIZE(h3xxx_uart_gpio));
+        if (rc)
+                pr_err("h3xxx_uart_request_gpios: error %d\n", rc);
+        else
+                h3xxx_uart_gpio_ok = true;
+        return h3xxx_uart_gpio_ok;
+}
 static void h3xxx_uart_set_mctrl(struct uart_port *port, u_int mctrl)
 {
        if (port->mapbase == _Ser3UTCR0) {
+                if (!h3xxx_uart_request_gpios())
+                        return;
                gpio_set_value(H3XXX_GPIO_COM_RTS, !(mctrl & TIOCM_RTS));
        }
 }
@@ -128,6 +122,8 @@ static u_int h3xxx_uart_get_mctrl(struct uart_port *port)
        u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
        if (port->mapbase == _Ser3UTCR0) {
+                if (!h3xxx_uart_request_gpios())
+                        return ret;
                /*
                 * DCD and CTS bits are inverted in GPLR by RS232 transceiver
                 */
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
index 50e1d850ee2e..b478ca180c19 100644
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -80,7 +80,7 @@ extern void locomolcd_power(int on);
 #define COLLIE_TC35143_GPIO_VERSION0    UCB_IO_0
 #define COLLIE_TC35143_GPIO_TBL_CHK     UCB_IO_1
 #define COLLIE_TC35143_GPIO_VPEN_ON     UCB_IO_2
-#define COLLIE_TC35143_GPIO_IR_ON       UCB_IO_3
+#define COLLIE_GPIO_IR_ON               (COLLIE_TC35143_GPIO_BASE + 3)
 #define COLLIE_TC35143_GPIO_AMP_ON      UCB_IO_4
 #define COLLIE_TC35143_GPIO_VERSION1    UCB_IO_5
 #define COLLIE_TC35143_GPIO_FS8KLPF     UCB_IO_5
diff --git a/arch/arm/mach-sa1100/include/mach/h3xxx.h b/arch/arm/mach-sa1100/include/mach/h3xxx.h
index c810620db53d..603d4343f7f6 100644
--- a/arch/arm/mach-sa1100/include/mach/h3xxx.h
+++ b/arch/arm/mach-sa1100/include/mach/h3xxx.h
@@ -79,17 +79,6 @@
 #define H3600_EGPIO_LCD_5V_ON           (H3XXX_EGPIO_BASE + 14) /* enable 5V to LCD. active high. */
 #define H3600_EGPIO_LVDD_ON             (H3XXX_EGPIO_BASE + 15) /* enable 9V and -6.5V to LCD. */
-struct gpio_default_state {
-        int gpio;
-        int mode;
-        const char *name;
-};
-#define GPIO_MODE_IN    -1
-#define GPIO_MODE_OUT0  0
-#define GPIO_MODE_OUT1  1
-void h3xxx_init_gpio(struct gpio_default_state *s, size_t n);
 void __init h3xxx_map_io(void);
 void __init h3xxx_mach_init(void);
diff --git a/arch/arm/mach-sa1100/include/mach/timex.h b/arch/arm/mach-sa1100/include/mach/timex.h
deleted file mode 100644
index 7a5d017b58b3..000000000000
--- a/arch/arm/mach-sa1100/include/mach/timex.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/timex.h
- *
- * SA1100 architecture timex specifications
- *
- * Copyright (C) 1998 
- */
-/*
- * SA1100 timer
- */
-#define CLOCK_TICK_RATE         3686400
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 6fd4acb8f187..1dea6cfafb31 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -9,6 +9,7 @@
 *
 */
 #include <linux/init.h>
+#include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -20,6 +21,9 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#define SA1100_CLOCK_FREQ 3686400
+#define SA1100_LATCH DIV_ROUND_CLOSEST(SA1100_CLOCK_FREQ, HZ)
 static u64 notrace sa1100_read_sched_clock(void)
 {
        return readl_relaxed(OSCR);
@@ -93,7 +97,7 @@ static void sa1100_timer_resume(struct clock_event_device *cedev)
        /*
         * OSMR0 is the system timer: make sure OSCR is sufficiently behind
         */
-        writel_relaxed(OSMR0 - LATCH, OSCR);
+        writel_relaxed(OSMR0 - SA1100_LATCH, OSCR);
 }
 #else
 #define sa1100_timer_suspend NULL
@@ -112,7 +116,7 @@ static struct clock_event_device ckevt_sa1100_osmr0 = {
 static struct irqaction sa1100_timer_irq = {
        .name           = "ost0",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = sa1100_ost0_interrupt,
        .dev_id         = &ckevt_sa1100_osmr0,
 };
@@ -128,7 +132,7 @@ void __init sa1100_timer_init(void)
        setup_irq(IRQ_OST0, &sa1100_timer_irq);
-        clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
+        clocksource_mmio_init(OSCR, "oscr", SA1100_CLOCK_FREQ, 200, 32,
                clocksource_mmio_readl_up);
        clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400,
                                        MIN_OSCR_DELTA * 2, 0x7fffffff);
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f6db7dcae3f4..0f92ba8e7884 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -5,18 +5,14 @@ config ARCH_SHMOBILE_MULTI
        bool "Renesas ARM SoCs" if ARCH_MULTI_V7
        depends on MMU
        select ARCH_SHMOBILE
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select ARM_GIC
-        select MIGHT_HAVE_CACHE_L2X0
        select MIGHT_HAVE_PCI
-        select NO_IOPORT
+        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+        select NO_IOPORT_MAP
        select PINCTRL
        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
 if ARCH_SHMOBILE_MULTI
@@ -49,15 +45,12 @@ config MACH_GENMAI
 config MACH_KOELSCH
        bool "Koelsch board"
        depends on ARCH_R8A7791
+        select MICREL_PHY if SH_ETH
-config MACH_KZM9D
-        bool "KZM9D board"
-        depends on ARCH_EMEV2
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 config MACH_LAGER
        bool "Lager board"
        depends on ARCH_R8A7790
+        select MICREL_PHY if SH_ETH
 comment "Renesas ARM SoCs System Configuration"
 endif
@@ -114,8 +107,6 @@ config ARCH_R8A7778
        select CPU_V7
        select SH_CLK_CPG
        select ARM_GIC
-        select USB_ARCH_HAS_EHCI
-        select USB_ARCH_HAS_OHCI
        select SYS_SUPPORTS_SH_TMU
 config ARCH_R8A7779
@@ -124,8 +115,6 @@ config ARCH_R8A7779
        select ARM_GIC
        select CPU_V7
        select SH_CLK_CPG
-        select USB_ARCH_HAS_EHCI
-        select USB_ARCH_HAS_OHCI
        select RENESAS_INTC_IRQPIN
        select SYS_SUPPORTS_SH_TMU
@@ -138,6 +127,7 @@ config ARCH_R8A7790
        select SH_CLK_CPG
        select RENESAS_IRQC
        select SYS_SUPPORTS_SH_CMT
+        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
 config ARCH_R8A7791
        bool "R-Car M2 (R8A77910)"
@@ -148,6 +138,7 @@ config ARCH_R8A7791
        select SH_CLK_CPG
        select RENESAS_IRQC
        select SYS_SUPPORTS_SH_CMT
+        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
 config ARCH_EMEV2
        bool "Emma Mobile EV2"
@@ -172,11 +163,13 @@ comment "Renesas ARM SoCs Board Type"
 config MACH_APE6EVM
        bool "APE6EVM board"
        depends on ARCH_R8A73A4
+        select SMSC_PHY if SMSC911X
        select USE_OF
 config MACH_APE6EVM_REFERENCE
        bool "APE6EVM board - Reference Device Tree Implementation"
        depends on ARCH_R8A73A4
+        select SMSC_PHY if SMSC911X
        select USE_OF
        ---help---
           Use reference implementation of APE6EVM board support
@@ -190,6 +183,7 @@ config MACH_MACKEREL
        depends on ARCH_SH7372
        select ARCH_REQUIRE_GPIOLIB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select SMSC_PHY if SMSC911X
        select SND_SOC_AK4642 if SND_SIMPLE_CARD
        select USE_OF
@@ -198,6 +192,7 @@ config MACH_ARMADILLO800EVA
        depends on ARCH_R8A7740
        select ARCH_REQUIRE_GPIOLIB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select SMSC_PHY if SH_ETH
        select SND_SOC_WM8978 if SND_SIMPLE_CARD
        select USE_OF
@@ -206,6 +201,7 @@ config MACH_ARMADILLO800EVA_REFERENCE
        depends on ARCH_R8A7740
        select ARCH_REQUIRE_GPIOLIB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select SMSC_PHY if SH_ETH
        select SND_SOC_WM8978 if SND_SIMPLE_CARD
        select USE_OF
        ---help---
@@ -219,11 +215,11 @@ config MACH_BOCKW
        bool "BOCK-W platform"
        depends on ARCH_R8A7778
        select ARCH_REQUIRE_GPIOLIB
-        select RENESAS_INTC_IRQPIN
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select USE_OF
+        select RENESAS_INTC_IRQPIN
        select SND_SOC_AK4554 if SND_SIMPLE_CARD
        select SND_SOC_AK4642 if SND_SIMPLE_CARD
+        select USE_OF
 config MACH_BOCKW_REFERENCE
        bool "BOCK-W  - Reference Device Tree Implementation"
@@ -279,6 +275,8 @@ config MACH_LAGER
        bool "Lager board"
        depends on ARCH_R8A7790
        select USE_OF
+        select MICREL_PHY if SH_ETH
+        select SND_SOC_AK4642 if SND_SIMPLE_CARD
 config MACH_KOELSCH
        bool "Koelsch board"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index fe7d4ff706e4..4caffc912a81 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -52,13 +52,13 @@ obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 obj-$(CONFIG_ARCH_SH7372)       += pm-sh7372.o sleep-sh7372.o pm-rmobile.o
 obj-$(CONFIG_ARCH_SH73A0)       += pm-sh73a0.o
 obj-$(CONFIG_ARCH_R8A7740)      += pm-r8a7740.o pm-rmobile.o
-obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o
+obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o pm-rcar.o
+obj-$(CONFIG_ARCH_R8A7790)      += pm-r8a7790.o pm-rcar.o
 # Board objects
 ifdef CONFIG_ARCH_SHMOBILE_MULTI
 obj-$(CONFIG_MACH_GENMAI)       += board-genmai-reference.o
 obj-$(CONFIG_MACH_KOELSCH)      += board-koelsch-reference.o
-obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager-reference.o
 else
 obj-$(CONFIG_MACH_APE6EVM)      += board-ape6evm.o
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 93533e2710a8..2858f380beae 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -383,6 +383,8 @@ static struct platform_device sh_eth_device = {
        .id = -1,
        .dev = {
                .platform_data = &sh_eth_platdata,
+                .dma_mask = &sh_eth_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
        },
        .resource = sh_eth_resources,
        .num_resources = ARRAY_SIZE(sh_eth_resources),
@@ -988,14 +990,12 @@ static struct asoc_simple_card_info fsi_wm8978_info = {
        .card           = "FSI2A-WM8978",
        .codec          = "wm8978.0-001a",
        .platform       = "sh_fsi2",
-        .daifmt         = SND_SOC_DAIFMT_I2S,
+        .daifmt         = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
        .cpu_dai = {
                .name   = "fsia-dai",
-                .fmt    = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF,
        },
        .codec_dai = {
                .name   = "wm8978-hifi",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF,
                .sysclk = 12288000,
        },
 };
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index c475220545f2..b4122f8cb8d9 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -1,9 +1,9 @@
 /*
 * Bock-W board support
 *
- * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013-2014  Renesas Solutions Corp.
 * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- * Copyright (C) 2013  Cogent Embedded, Inc.
+ * Copyright (C) 2013-2014  Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -168,6 +168,8 @@ static struct renesas_usbhs_platform_info usbhs_info __initdata = {
        },
        .driver_param = {
                .buswait_bwait  = 4,
+                .d0_tx_id       = HPBDMA_SLAVE_USBFUNC_TX,
+                .d1_rx_id       = HPBDMA_SLAVE_USBFUNC_RX,
        },
 };
@@ -233,6 +235,17 @@ static struct sh_eth_plat_data ether_platform_data __initdata = {
        .no_ether_link  = 1,
 };
+static struct platform_device_info ether_info __initdata = {
+        .parent         = &platform_bus,
+        .name           = "r8a777x-ether",
+        .id             = -1,
+        .res            = ether_resources,
+        .num_res        = ARRAY_SIZE(ether_resources),
+        .data           = &ether_platform_data,
+        .size_data      = sizeof(ether_platform_data),
+        .dma_mask       = DMA_BIT_MASK(32),
+};
 /* I2C */
 static struct i2c_board_info i2c0_devices[] = {
        {
@@ -332,16 +345,24 @@ static struct rsnd_ssi_platform_info rsnd_ssi[] = {
        RSND_SSI_UNUSED, /* SSI 0 */
        RSND_SSI_UNUSED, /* SSI 1 */
        RSND_SSI_UNUSED, /* SSI 2 */
-        RSND_SSI_SET(1, 0, gic_iid(0x85), RSND_SSI_PLAY),
+        RSND_SSI_SET(1, HPBDMA_SLAVE_HPBIF3_TX, gic_iid(0x85), RSND_SSI_PLAY),
-        RSND_SSI_SET(2, 0, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
+        RSND_SSI_SET(2, HPBDMA_SLAVE_HPBIF4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
-        RSND_SSI_SET(0, 0, gic_iid(0x86), RSND_SSI_PLAY),
+        RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF5_TX, gic_iid(0x86), RSND_SSI_PLAY),
-        RSND_SSI_SET(0, 0, gic_iid(0x86), 0),
+        RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF6_RX, gic_iid(0x86), 0),
-        RSND_SSI_SET(3, 0, gic_iid(0x86), RSND_SSI_PLAY),
+        RSND_SSI_SET(3, HPBDMA_SLAVE_HPBIF7_TX, gic_iid(0x86), RSND_SSI_PLAY),
-        RSND_SSI_SET(4, 0, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
+        RSND_SSI_SET(4, HPBDMA_SLAVE_HPBIF8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
 };
 static struct rsnd_scu_platform_info rsnd_scu[9] = {
-        /* no member at this point */
+        { .flags = 0, }, /* SRU 0 */
+        { .flags = 0, }, /* SRU 1 */
+        { .flags = 0, }, /* SRU 2 */
+        { .flags = RSND_SCU_USE_HPBIF, },
+        { .flags = RSND_SCU_USE_HPBIF, },
+        { .flags = RSND_SCU_USE_HPBIF, },
+        { .flags = RSND_SCU_USE_HPBIF, },
+        { .flags = RSND_SCU_USE_HPBIF, },
+        { .flags = RSND_SCU_USE_HPBIF, },
 };
 enum {
@@ -429,14 +450,12 @@ static struct asoc_simple_card_info rsnd_card_info[] = {
                .card           = "SSI56-AK4643",
                .codec          = "ak4642-codec.0-0012",
                .platform       = "rcar_sound",
-                .daifmt         = SND_SOC_DAIFMT_LEFT_J,
+                .daifmt         = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
                .cpu_dai = {
                        .name   = "rsnd-dai.0",
-                        .fmt    = SND_SOC_DAIFMT_CBS_CFS,
                },
                .codec_dai = {
                        .name   = "ak4642-hifi",
-                        .fmt    = SND_SOC_DAIFMT_CBM_CFM,
                        .sysclk = 11289600,
                },
        },
@@ -446,10 +465,9 @@ static struct asoc_simple_card_info rsnd_card_info[] = {
                .card           = "SSI3-AK4554(playback)",
                .codec          = "ak4554-adc-dac.0",
                .platform       = "rcar_sound",
+                .daifmt         = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_RIGHT_J,
                .cpu_dai = {
                        .name   = "rsnd-dai.1",
-                        .fmt    = SND_SOC_DAIFMT_CBM_CFM |
-                                  SND_SOC_DAIFMT_RIGHT_J,
                },
                .codec_dai = {
                        .name   = "ak4554-hifi",
@@ -461,10 +479,9 @@ static struct asoc_simple_card_info rsnd_card_info[] = {
                .card           = "SSI4-AK4554(capture)",
                .codec          = "ak4554-adc-dac.0",
                .platform       = "rcar_sound",
+                .daifmt         = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_LEFT_J,
                .cpu_dai = {
                        .name   = "rsnd-dai.2",
-                        .fmt    = SND_SOC_DAIFMT_CBM_CFM |
-                                  SND_SOC_DAIFMT_LEFT_J,
                },
                .codec_dai = {
                        .name   = "ak4554-hifi",
@@ -476,10 +493,9 @@ static struct asoc_simple_card_info rsnd_card_info[] = {
                .card           = "SSI7-AK4554(playback)",
                .codec          = "ak4554-adc-dac.1",
                .platform       = "rcar_sound",
+                .daifmt         = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_RIGHT_J,
                .cpu_dai = {
                        .name   = "rsnd-dai.3",
-                        .fmt    = SND_SOC_DAIFMT_CBM_CFM |
-                                  SND_SOC_DAIFMT_RIGHT_J,
                },
                .codec_dai = {
                        .name   = "ak4554-hifi",
@@ -491,10 +507,9 @@ static struct asoc_simple_card_info rsnd_card_info[] = {
                .card           = "SSI8-AK4554(capture)",
                .codec          = "ak4554-adc-dac.1",
                .platform       = "rcar_sound",
+                .daifmt         = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_LEFT_J,
                .cpu_dai = {
                        .name   = "rsnd-dai.4",
-                        .fmt    = SND_SOC_DAIFMT_CBM_CFM |
-                                  SND_SOC_DAIFMT_LEFT_J,
                },
                .codec_dai = {
                        .name   = "ak4554-hifi",
@@ -582,11 +597,7 @@ static void __init bockw_init(void)
        r8a7778_init_irq_extpin(1);
        r8a7778_add_standard_devices();
-        platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
+        platform_device_register_full(&ether_info);
-                                          ether_resources,
-                                          ARRAY_SIZE(ether_resources),
-                                          &ether_platform_data,
-                                          sizeof(ether_platform_data));
        platform_device_register_full(&vin0_info);
        /* VIN1 has a pin conflict with Ether */
diff --git a/arch/arm/mach-shmobile/board-genmai.c b/arch/arm/mach-shmobile/board-genmai.c
index 3e92e3c62d4c..6c328d63b819 100644
--- a/arch/arm/mach-shmobile/board-genmai.c
+++ b/arch/arm/mach-shmobile/board-genmai.c
@@ -1,8 +1,9 @@
 /*
 * Genmai board support
 *
- * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013-2014  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2014  Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -20,15 +21,87 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/sh_eth.h>
+#include <linux/spi/rspi.h>
+#include <linux/spi/spi.h>
 #include <mach/common.h>
+#include <mach/irqs.h>
 #include <mach/r7s72100.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+/* Ether */
+static const struct sh_eth_plat_data ether_pdata __initconst = {
+        .phy                    = 0x00, /* PD60610 */
+        .edmac_endian           = EDMAC_LITTLE_ENDIAN,
+        .phy_interface          = PHY_INTERFACE_MODE_MII,
+        .no_ether_link          = 1
+};
+static const struct resource ether_resources[] __initconst = {
+        DEFINE_RES_MEM(0xe8203000, 0x800),
+        DEFINE_RES_MEM(0xe8204800, 0x200),
+        DEFINE_RES_IRQ(gic_iid(359)),
+};
+static const struct platform_device_info ether_info __initconst = {
+        .parent         = &platform_bus,
+        .name           = "r7s72100-ether",
+        .id             = -1,
+        .res            = ether_resources,
+        .num_res        = ARRAY_SIZE(ether_resources),
+        .data           = &ether_pdata,
+        .size_data      = sizeof(ether_pdata),
+        .dma_mask       = DMA_BIT_MASK(32),
+};
+/* RSPI */
+#define RSPI_RESOURCE(idx, baseaddr, irq)                               \
+static const struct resource rspi##idx##_resources[] __initconst = {    \
+        DEFINE_RES_MEM(baseaddr, 0x24),                                 \
+        DEFINE_RES_IRQ_NAMED(irq, "error"),                             \
+        DEFINE_RES_IRQ_NAMED(irq + 1, "rx"),                            \
+        DEFINE_RES_IRQ_NAMED(irq + 2, "tx"),                            \
+}
+RSPI_RESOURCE(0, 0xe800c800, gic_iid(270));
+RSPI_RESOURCE(1, 0xe800d000, gic_iid(273));
+RSPI_RESOURCE(2, 0xe800d800, gic_iid(276));
+RSPI_RESOURCE(3, 0xe800e000, gic_iid(279));
+RSPI_RESOURCE(4, 0xe800e800, gic_iid(282));
+static const struct rspi_plat_data rspi_pdata __initconst = {
+        .num_chipselect = 1,
+};
+#define r7s72100_register_rspi(idx)                                        \
+        platform_device_register_resndata(&platform_bus, "rspi-rz", idx,   \
+                                        rspi##idx##_resources,             \
+                                        ARRAY_SIZE(rspi##idx##_resources), \
+                                        &rspi_pdata, sizeof(rspi_pdata))
+static const struct spi_board_info spi_info[] __initconst = {
+        {
+                .modalias               = "wm8978",
+                .max_speed_hz           = 5000000,
+                .bus_num                = 4,
+                .chip_select            = 0,
+        },
+};
 static void __init genmai_add_standard_devices(void)
 {
        r7s72100_clock_init();
        r7s72100_add_dt_devices();
+        platform_device_register_full(&ether_info);
+        r7s72100_register_rspi(0);
+        r7s72100_register_rspi(1);
+        r7s72100_register_rspi(2);
+        r7s72100_register_rspi(3);
+        r7s72100_register_rspi(4);
+        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
 }
 static const char * const genmai_boards_compat_dt[] __initconst = {
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
index 652b59268416..a3fd30242bd8 100644
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ b/arch/arm/mach-shmobile/board-koelsch-reference.c
@@ -21,46 +21,114 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/dma-mapping.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/rcar-du.h>
 #include <mach/common.h>
+#include <mach/irqs.h>
 #include <mach/rcar-gen2.h>
 #include <mach/r8a7791.h>
 #include <asm/mach/arch.h>
+/* DU */
+static struct rcar_du_encoder_data koelsch_du_encoders[] = {
+        {
+                .type = RCAR_DU_ENCODER_NONE,
+                .output = RCAR_DU_OUTPUT_LVDS0,
+                .connector.lvds.panel = {
+                        .width_mm = 210,
+                        .height_mm = 158,
+                        .mode = {
+                                .clock = 65000,
+                                .hdisplay = 1024,
+                                .hsync_start = 1048,
+                                .hsync_end = 1184,
+                                .htotal = 1344,
+                                .vdisplay = 768,
+                                .vsync_start = 771,
+                                .vsync_end = 777,
+                                .vtotal = 806,
+                                .flags = 0,
+                        },
+                },
+        },
+};
+static struct rcar_du_platform_data koelsch_du_pdata = {
+        .encoders = koelsch_du_encoders,
+        .num_encoders = ARRAY_SIZE(koelsch_du_encoders),
+};
+static const struct resource du_resources[] __initconst = {
+        DEFINE_RES_MEM(0xfeb00000, 0x40000),
+        DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
+        DEFINE_RES_IRQ(gic_spi(256)),
+        DEFINE_RES_IRQ(gic_spi(268)),
+};
+static void __init koelsch_add_du_device(void)
+{
+        struct platform_device_info info = {
+                .name = "rcar-du-r8a7791",
+                .id = -1,
+                .res = du_resources,
+                .num_res = ARRAY_SIZE(du_resources),
+                .data = &koelsch_du_pdata,
+                .size_data = sizeof(koelsch_du_pdata),
+                .dma_mask = DMA_BIT_MASK(32),
+        };
+        platform_device_register_full(&info);
+}
 static void __init koelsch_add_standard_devices(void)
 {
-#ifdef CONFIG_COMMON_CLK
        /*
-         * This is a really crude hack to provide clkdev support to the SCIF
+         * This is a really crude hack to provide clkdev support to the CMT and
-         * and CMT devices until they get moved to DT.
+         * DU devices until they get moved to DT.
         */
-        static const char * const scif_names[] = {
+        static const struct clk_name {
-                "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifa2",
+                const char *clk;
-                "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scifa3",
+                const char *con_id;
-                "scifa4", "scifa5",
+                const char *dev_id;
+        } clk_names[] = {
+                { "cmt0", NULL, "sh_cmt.0" },
+                { "scifa0", NULL, "sh-sci.0" },
+                { "scifa1", NULL, "sh-sci.1" },
+                { "scifb0", NULL, "sh-sci.2" },
+                { "scifb1", NULL, "sh-sci.3" },
+                { "scifb2", NULL, "sh-sci.4" },
+                { "scifa2", NULL, "sh-sci.5" },
+                { "scif0", NULL, "sh-sci.6" },
+                { "scif1", NULL, "sh-sci.7" },
+                { "scif2", NULL, "sh-sci.8" },
+                { "scif3", NULL, "sh-sci.9" },
+                { "scif4", NULL, "sh-sci.10" },
+                { "scif5", NULL, "sh-sci.11" },
+                { "scifa3", NULL, "sh-sci.12" },
+                { "scifa4", NULL, "sh-sci.13" },
+                { "scifa5", NULL, "sh-sci.14" },
+                { "du0", "du.0", "rcar-du-r8a7791" },
+                { "du1", "du.1", "rcar-du-r8a7791" },
+                { "lvds0", "lvds.0", "rcar-du-r8a7791" },
        };
        struct clk *clk;
        unsigned int i;
-        for (i = 0; i < ARRAY_SIZE(scif_names); ++i) {
+        for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
-                clk = clk_get(NULL, scif_names[i]);
+                clk = clk_get(NULL, clk_names[i].clk);
-                if (clk) {
+                if (!IS_ERR(clk)) {
-                        clk_register_clkdev(clk, NULL, "sh-sci.%u", i);
+                        clk_register_clkdev(clk, clk_names[i].con_id,
+                                            clk_names[i].dev_id);
                        clk_put(clk);
                }
        }
-        clk = clk_get(NULL, "cmt0");
-        if (clk) {
-                clk_register_clkdev(clk, NULL, "sh_cmt.0");
-                clk_put(clk);
-        }
-#else
-        r8a7791_clock_init();
-#endif
        r8a7791_add_dt_devices();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        koelsch_add_du_device();
 }
 static const char * const koelsch_boards_compat_dt[] __initconst = {
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index de7cc64b1f37..5a034ff405d0 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -2,8 +2,9 @@
 * Koelsch board support
 *
 * Copyright (C) 2013  Renesas Electronics Corporation
- * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013-2014  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2014  Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -23,14 +24,27 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/leds.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/rcar-du.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/gpio-regulator.h>
+#include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/rspi.h>
+#include <linux/spi/spi.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7791.h>
@@ -92,6 +106,7 @@ static void __init koelsch_add_du_device(void)
 /* Ether */
 static const struct sh_eth_plat_data ether_pdata __initconst = {
        .phy                    = 0x1,
+        .phy_irq                = irq_pin(0),
        .edmac_endian           = EDMAC_LITTLE_ENDIAN,
        .phy_interface          = PHY_INTERFACE_MODE_RMII,
        .ether_link_active_low  = 1,
@@ -102,6 +117,17 @@ static const struct resource ether_resources[] __initconst = {
        DEFINE_RES_IRQ(gic_spi(162)),
 };
+static const struct platform_device_info ether_info __initconst = {
+        .parent         = &platform_bus,
+        .name           = "r8a7791-ether",
+        .id             = -1,
+        .res            = ether_resources,
+        .num_res        = ARRAY_SIZE(ether_resources),
+        .data           = &ether_pdata,
+        .size_data      = sizeof(ether_pdata),
+        .dma_mask       = DMA_BIT_MASK(32),
+};
 /* LEDS */
 static struct gpio_led koelsch_leds[] = {
        {
@@ -148,6 +174,199 @@ static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
        .nbuttons       = ARRAY_SIZE(gpio_buttons),
 };
+/* QSPI */
+static const struct resource qspi_resources[] __initconst = {
+        DEFINE_RES_MEM(0xe6b10000, 0x1000),
+        DEFINE_RES_IRQ_NAMED(gic_spi(184), "mux"),
+};
+static const struct rspi_plat_data qspi_pdata __initconst = {
+        .num_chipselect = 1,
+};
+/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64 MiB) */
+static struct mtd_partition spi_flash_part[] = {
+        {
+                .name           = "loader",
+                .offset         = 0x00000000,
+                .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "bootenv",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "data",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+static const struct flash_platform_data spi_flash_data = {
+        .name           = "m25p80",
+        .parts          = spi_flash_part,
+        .nr_parts       = ARRAY_SIZE(spi_flash_part),
+        .type           = "s25fl512s",
+};
+static const struct spi_board_info spi_info[] __initconst = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &spi_flash_data,
+                .mode           = SPI_MODE_0,
+                .max_speed_hz   = 30000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+/* SATA0 */
+static const struct resource sata0_resources[] __initconst = {
+        DEFINE_RES_MEM(0xee300000, 0x2000),
+        DEFINE_RES_IRQ(gic_spi(105)),
+};
+static const struct platform_device_info sata0_info __initconst = {
+        .parent         = &platform_bus,
+        .name           = "sata-r8a7791",
+        .id             = 0,
+        .res            = sata0_resources,
+        .num_res        = ARRAY_SIZE(sata0_resources),
+        .dma_mask       = DMA_BIT_MASK(32),
+};
+/* I2C */
+static const struct resource i2c_resources[] __initconst = {
+        /* I2C0 */
+        DEFINE_RES_MEM(0xE6508000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(287)),
+        /* I2C1 */
+        DEFINE_RES_MEM(0xE6518000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(288)),
+        /* I2C2 */
+        DEFINE_RES_MEM(0xE6530000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(286)),
+        /* I2C3 */
+        DEFINE_RES_MEM(0xE6540000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(290)),
+        /* I2C4 */
+        DEFINE_RES_MEM(0xE6520000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(19)),
+        /* I2C5 */
+        DEFINE_RES_MEM(0xE6528000, 0x40),
+        DEFINE_RES_IRQ(gic_spi(20)),
+};
+static void __init koelsch_add_i2c(unsigned idx)
+{
+        unsigned res_idx = idx * 2;
+        BUG_ON(res_idx >= ARRAY_SIZE(i2c_resources));
+        platform_device_register_simple("i2c-rcar_gen2", idx,
+                                        i2c_resources + res_idx, 2);
+}
+#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin)                          \
+static struct regulator_consumer_supply vcc_sdhi##idx##_consumer =      \
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx);               \
+                                                                        \
+static struct regulator_init_data vcc_sdhi##idx##_init_data = {         \
+        .constraints = {                                                \
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,              \
+        },                                                              \
+        .consumer_supplies      = &vcc_sdhi##idx##_consumer,            \
+        .num_consumer_supplies  = 1,                                    \
+};                                                                      \
+                                                                        \
+static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
+        .supply_name    = "SDHI" #idx "Vcc",                            \
+        .microvolts     = 3300000,                                      \
+        .gpio           = vdd_pin,                                      \
+        .enable_high    = 1,                                            \
+        .init_data      = &vcc_sdhi##idx##_init_data,                   \
+};                                                                      \
+                                                                        \
+static struct regulator_consumer_supply vccq_sdhi##idx##_consumer =     \
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx);              \
+                                                                        \
+static struct regulator_init_data vccq_sdhi##idx##_init_data = {        \
+        .constraints = {                                                \
+                .input_uV       = 3300000,                              \
+                .min_uV         = 1800000,                              \
+                .max_uV         = 3300000,                              \
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |            \
+                                  REGULATOR_CHANGE_STATUS,              \
+        },                                                              \
+        .consumer_supplies      = &vccq_sdhi##idx##_consumer,           \
+        .num_consumer_supplies  = 1,                                    \
+};                                                                      \
+                                                                        \
+static struct gpio vccq_sdhi##idx##_gpio =                              \
+        { vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx };            \
+                                                                        \
+static struct gpio_regulator_state vccq_sdhi##idx##_states[] = {        \
+        { .value = 1800000, .gpios = 0 },                               \
+        { .value = 3300000, .gpios = 1 },                               \
+};                                                                      \
+                                                                        \
+static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
+        .supply_name    = "vqmmc",                                      \
+        .gpios          = &vccq_sdhi##idx##_gpio,                       \
+        .nr_gpios       = 1,                                            \
+        .states         = vccq_sdhi##idx##_states,                      \
+        .nr_states      = ARRAY_SIZE(vccq_sdhi##idx##_states),          \
+        .type           = REGULATOR_VOLTAGE,                            \
+        .init_data      = &vccq_sdhi##idx##_init_data,                  \
+};
+SDHI_REGULATOR(0, RCAR_GP_PIN(7, 17), RCAR_GP_PIN(2, 12));
+SDHI_REGULATOR(1, RCAR_GP_PIN(7, 18), RCAR_GP_PIN(2, 13));
+SDHI_REGULATOR(2, RCAR_GP_PIN(7, 19), RCAR_GP_PIN(2, 26));
+/* SDHI0 */
+static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
+        .tmio_caps2     = MMC_CAP2_NO_MULTI_READ,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+};
+static struct resource sdhi0_resources[] __initdata = {
+        DEFINE_RES_MEM(0xee100000, 0x200),
+        DEFINE_RES_IRQ(gic_spi(165)),
+};
+/* SDHI1 */
+static struct sh_mobile_sdhi_info sdhi1_info __initdata = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
+        .tmio_caps2     = MMC_CAP2_NO_MULTI_READ,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+};
+static struct resource sdhi1_resources[] __initdata = {
+        DEFINE_RES_MEM(0xee140000, 0x100),
+        DEFINE_RES_IRQ(gic_spi(167)),
+};
+/* SDHI2 */
+static struct sh_mobile_sdhi_info sdhi2_info __initdata = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
+        .tmio_caps2     = MMC_CAP2_NO_MULTI_READ,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT |
+                          TMIO_MMC_WRPROTECT_DISABLE,
+};
+static struct resource sdhi2_resources[] __initdata = {
+        DEFINE_RES_MEM(0xee160000, 0x100),
+        DEFINE_RES_IRQ(gic_spi(168)),
+};
 static const struct pinctrl_map koelsch_pinctrl_map[] = {
        /* DU */
        PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
@@ -165,12 +384,51 @@ static const struct pinctrl_map koelsch_pinctrl_map[] = {
                                  "eth_rmii", "eth"),
        PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
                                  "intc_irq0", "intc"),
+        /* QSPI */
+        PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
+                                  "qspi_ctrl", "qspi"),
+        PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
+                                  "qspi_data4", "qspi"),
        /* SCIF0 (CN19: DEBUG SERIAL0) */
        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791",
                                  "scif0_data_d", "scif0"),
        /* SCIF1 (CN20: DEBUG SERIAL1) */
        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7791",
                                  "scif1_data_d", "scif1"),
+        /* I2C1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar_gen2.1", "pfc-r8a7791",
+                                  "i2c1_e", "i2c1"),
+        /* I2C2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar_gen2.2", "pfc-r8a7791",
+                                  "i2c2", "i2c2"),
+        /* I2C4 */
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar_gen2.4", "pfc-r8a7791",
+                                  "i2c4_c", "i2c4"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
+                                  "sdhi1_ctrl", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
+                                  "sdhi1_cd", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
+                                  "sdhi1_wp", "sdhi1"),
+        /* SDHI2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7791",
+                                  "sdhi2_data4", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7791",
+                                  "sdhi2_ctrl", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7791",
+                                  "sdhi2_cd", "sdhi2"),
 };
 static void __init koelsch_add_standard_devices(void)
@@ -180,18 +438,53 @@ static void __init koelsch_add_standard_devices(void)
                                  ARRAY_SIZE(koelsch_pinctrl_map));
        r8a7791_pinmux_init();
        r8a7791_add_standard_devices();
-        platform_device_register_resndata(&platform_bus, "r8a7791-ether", -1,
+        platform_device_register_full(&ether_info);
-                                          ether_resources,
-                                          ARRAY_SIZE(ether_resources),
-                                          &ether_pdata, sizeof(ether_pdata));
        platform_device_register_data(&platform_bus, "leds-gpio", -1,
                                      &koelsch_leds_pdata,
                                      sizeof(koelsch_leds_pdata));
        platform_device_register_data(&platform_bus, "gpio-keys", -1,
                                      &koelsch_keys_pdata,
                                      sizeof(koelsch_keys_pdata));
+        platform_device_register_resndata(&platform_bus, "qspi", 0,
+                                          qspi_resources,
+                                          ARRAY_SIZE(qspi_resources),
+                                          &qspi_pdata, sizeof(qspi_pdata));
+        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
        koelsch_add_du_device();
+        platform_device_register_full(&sata0_info);
+        koelsch_add_i2c(1);
+        koelsch_add_i2c(2);
+        koelsch_add_i2c(4);
+        koelsch_add_i2c(5);
+        platform_device_register_data(&platform_bus, "reg-fixed-voltage", 0,
+                                      &vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
+        platform_device_register_data(&platform_bus, "reg-fixed-voltage", 1,
+                                      &vcc_sdhi1_info, sizeof(struct fixed_voltage_config));
+        platform_device_register_data(&platform_bus, "reg-fixed-voltage", 2,
+                                      &vcc_sdhi2_info, sizeof(struct fixed_voltage_config));
+        platform_device_register_data(&platform_bus, "gpio-regulator", 0,
+                                      &vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
+        platform_device_register_data(&platform_bus, "gpio-regulator", 1,
+                                      &vccq_sdhi1_info, sizeof(struct gpio_regulator_config));
+        platform_device_register_data(&platform_bus, "gpio-regulator", 2,
+                                      &vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
+        platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 0,
+                                          sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
+                                          &sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
+        platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 1,
+                                          sdhi1_resources, ARRAY_SIZE(sdhi1_resources),
+                                          &sdhi1_info, sizeof(struct sh_mobile_sdhi_info));
+        platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 2,
+                                          sdhi2_resources, ARRAY_SIZE(sdhi2_resources),
+                                          &sdhi2_info, sizeof(struct sh_mobile_sdhi_info));
 }
 /*
@@ -215,6 +508,8 @@ static void __init koelsch_init(void)
 {
        koelsch_add_standard_devices();
+        irq_set_irq_type(irq_pin(0), IRQ_TYPE_LEVEL_LOW);
        if (IS_ENABLED(CONFIG_PHYLIB))
                phy_register_fixup_for_id("r8a7791-ether-ff:01",
                                          koelsch_ksz8041_fixup);
diff --git a/arch/arm/mach-shmobile/board-kzm9d-reference.c b/arch/arm/mach-shmobile/board-kzm9d-reference.c
deleted file mode 100644
index 054d8d5c8fc1..000000000000
--- a/arch/arm/mach-shmobile/board-kzm9d-reference.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * kzm9d board support - Reference DT implementation
- *
- * Copyright (C) 2013  Renesas Solutions Corp.
- * Copyright (C) 2013  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <mach/emev2.h>
-#include <mach/common.h>
-#include <asm/mach/arch.h>
-static void __init kzm9d_add_standard_devices(void)
-{
-        if (!IS_ENABLED(CONFIG_COMMON_CLK))
-                emev2_clock_init();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static const char *kzm9d_boards_compat_dt[] __initdata = {
-        "renesas,kzm9d",
-        "renesas,kzm9d-reference",
-        NULL,
-};
-DT_MACHINE_START(KZM9D_DT, "kzm9d")
-        .smp            = smp_ops(emev2_smp_ops),
-        .map_io         = emev2_map_io,
-        .init_early     = emev2_init_delay,
-        .init_machine   = kzm9d_add_standard_devices,
-        .init_late      = shmobile_init_late,
-        .dt_compat      = kzm9d_boards_compat_dt,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index bc40b853ffd3..03dc3ac84502 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -589,14 +589,12 @@ static struct asoc_simple_card_info fsi2_ak4648_info = {
        .card           = "FSI2A-AK4648",
        .codec          = "ak4642-codec.0-0012",
        .platform       = "sh_fsi2",
-        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
        .cpu_dai = {
                .name   = "fsia-dai",
-                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
        },
        .codec_dai = {
                .name   = "ak4642-hifi",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
                .sysclk = 11289600,
        },
 };
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index a6e271d92af0..440aac36d693 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -20,47 +20,116 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/rcar-du.h>
 #include <mach/common.h>
+#include <mach/irqs.h>
 #include <mach/rcar-gen2.h>
 #include <mach/r8a7790.h>
 #include <asm/mach/arch.h>
+/* DU */
+static struct rcar_du_encoder_data lager_du_encoders[] = {
+        {
+                .type = RCAR_DU_ENCODER_VGA,
+                .output = RCAR_DU_OUTPUT_DPAD0,
+        }, {
+                .type = RCAR_DU_ENCODER_NONE,
+                .output = RCAR_DU_OUTPUT_LVDS1,
+                .connector.lvds.panel = {
+                        .width_mm = 210,
+                        .height_mm = 158,
+                        .mode = {
+                                .clock = 65000,
+                                .hdisplay = 1024,
+                                .hsync_start = 1048,
+                                .hsync_end = 1184,
+                                .htotal = 1344,
+                                .vdisplay = 768,
+                                .vsync_start = 771,
+                                .vsync_end = 777,
+                                .vtotal = 806,
+                                .flags = 0,
+                        },
+                },
+        },
+};
+static struct rcar_du_platform_data lager_du_pdata = {
+        .encoders = lager_du_encoders,
+        .num_encoders = ARRAY_SIZE(lager_du_encoders),
+};
+static const struct resource du_resources[] __initconst = {
+        DEFINE_RES_MEM(0xfeb00000, 0x70000),
+        DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
+        DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"),
+        DEFINE_RES_IRQ(gic_spi(256)),
+        DEFINE_RES_IRQ(gic_spi(268)),
+        DEFINE_RES_IRQ(gic_spi(269)),
+};
+static void __init lager_add_du_device(void)
+{
+        struct platform_device_info info = {
+                .name = "rcar-du-r8a7790",
+                .id = -1,
+                .res = du_resources,
+                .num_res = ARRAY_SIZE(du_resources),
+                .data = &lager_du_pdata,
+                .size_data = sizeof(lager_du_pdata),
+                .dma_mask = DMA_BIT_MASK(32),
+        };
+        platform_device_register_full(&info);
+}
 static void __init lager_add_standard_devices(void)
 {
-#ifdef CONFIG_COMMON_CLK
        /*
-         * This is a really crude hack to provide clkdev support to the SCIF
+         * This is a really crude hack to provide clkdev support to platform
-         * and CMT devices until they get moved to DT.
+         * devices until they get moved to DT.
         */
-        static const char * const scif_names[] = {
+        static const struct clk_name {
-                "scifa0", "scifa1", "scifb0", "scifb1",
+                const char *clk;
-                "scifb2", "scifa2", "scif0", "scif1",
+                const char *con_id;
-                "hscif0", "hscif1",
+                const char *dev_id;
+        } clk_names[] = {
+                { "cmt0", NULL, "sh_cmt.0" },
+                { "scifa0", NULL, "sh-sci.0" },
+                { "scifa1", NULL, "sh-sci.1" },
+                { "scifb0", NULL, "sh-sci.2" },
+                { "scifb1", NULL, "sh-sci.3" },
+                { "scifb2", NULL, "sh-sci.4" },
+                { "scifa2", NULL, "sh-sci.5" },
+                { "scif0", NULL, "sh-sci.6" },
+                { "scif1", NULL, "sh-sci.7" },
+                { "hscif0", NULL, "sh-sci.8" },
+                { "hscif1", NULL, "sh-sci.9" },
+                { "du0", "du.0", "rcar-du-r8a7790" },
+                { "du1", "du.1", "rcar-du-r8a7790" },
+                { "du2", "du.2", "rcar-du-r8a7790" },
+                { "lvds0", "lvds.0", "rcar-du-r8a7790" },
+                { "lvds1", "lvds.1", "rcar-du-r8a7790" },
        };
        struct clk *clk;
        unsigned int i;
-        for (i = 0; i < ARRAY_SIZE(scif_names); ++i) {
+        for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
-                clk = clk_get(NULL, scif_names[i]);
+                clk = clk_get(NULL, clk_names[i].clk);
-                if (clk) {
+                if (!IS_ERR(clk)) {
-                        clk_register_clkdev(clk, NULL, "sh-sci.%u", i);
+                        clk_register_clkdev(clk, clk_names[i].con_id,
+                                            clk_names[i].dev_id);
                        clk_put(clk);
                }
        }
-        clk = clk_get(NULL, "cmt0");
-        if (clk) {
-                clk_register_clkdev(clk, NULL, "sh_cmt.0");
-                clk_put(clk);
-        }
-#else
-        r8a7790_clock_init();
-#endif
        r8a7790_add_dt_devices();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        lager_add_du_device();
 }
 static const char *lager_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f20c10a18543..f0104bfe544e 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -1,8 +1,9 @@
 /*
 * Lager board support
 *
- * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013-2014  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2014  Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -20,15 +21,21 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/i2c.h>
 #include <linux/input.h>
 #include <linux/interrupt.h>
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/leds.h>
+#include <linux/mfd/tmio.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/camera-rcar.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/rcar-du.h>
+#include <linux/platform_data/usb-rcar-gen2-phy.h>
 #include <linux/platform_device.h>
 #include <linux/phy.h>
 #include <linux/regulator/driver.h>
@@ -36,9 +43,12 @@
 #include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>
+#include <linux/usb/phy.h>
+#include <linux/usb/renesas_usbhs.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7790.h>
+#include <media/soc_camera.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <linux/mtd/partitions.h>
@@ -46,6 +56,33 @@
 #include <linux/spi/flash.h>
 #include <linux/spi/rspi.h>
 #include <linux/spi/spi.h>
+#include <sound/rcar_snd.h>
+#include <sound/simple_card.h>
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ *      2: CN22
+ *      3: ADV7511
+ *
+ * this command is required when playback.
+ *
+ * # amixer set "LINEOUT Mixer DACL" on
+ */
+/*
+ * SDHI0 (CN8)
+ *
+ * JP3:  pin1
+ * SW20: pin1
+ * GP5_24:      1:  VDD  3.3V (defult)
+ *              0:  VDD  0.0V
+ * GP5_29:      1:  VccQ 3.3V (defult)
+ *              0:  VccQ 1.8V
+ *
+ */
 /* DU */
 static struct rcar_du_encoder_data lager_du_encoders[] = {
@@ -228,6 +265,7 @@ static const struct resource mmcif1_resources[] __initconst = {
 /* Ether */
 static const struct sh_eth_plat_data ether_pdata __initconst = {
        .phy                    = 0x1,
+        .phy_irq                = irq_pin(0),
        .edmac_endian           = EDMAC_LITTLE_ENDIAN,
        .phy_interface          = PHY_INTERFACE_MODE_RMII,
        .ether_link_active_low  = 1,
@@ -238,6 +276,17 @@ static const struct resource ether_resources[] __initconst = {
        DEFINE_RES_IRQ(gic_spi(162)),
 };
+static const struct platform_device_info ether_info __initconst = {
+        .parent         = &platform_bus,
+        .name           = "r8a7790-ether",
+        .id             = -1,
+        .res            = ether_resources,
+        .num_res        = ARRAY_SIZE(ether_resources),
+        .data           = &ether_pdata,
+        .size_data      = sizeof(ether_pdata),
+        .dma_mask       = DMA_BIT_MASK(32),
+};
 /* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */
 static struct mtd_partition spi_flash_part[] = {
        /* Reserved for user loader program, read-only */
@@ -263,7 +312,7 @@ static struct mtd_partition spi_flash_part[] = {
        },
 };
-static struct flash_platform_data spi_flash_data = {
+static const struct flash_platform_data spi_flash_data = {
        .name           = "m25p80",
        .parts          = spi_flash_part,
        .nr_parts       = ARRAY_SIZE(spi_flash_part),
@@ -288,9 +337,361 @@ static const struct spi_board_info spi_info[] __initconst = {
 /* QSPI resource */
 static const struct resource qspi_resources[] __initconst = {
        DEFINE_RES_MEM(0xe6b10000, 0x1000),
-        DEFINE_RES_IRQ(gic_spi(184)),
+        DEFINE_RES_IRQ_NAMED(gic_spi(184), "mux"),
+};
+/* VIN */
+static const struct resource vin_resources[] __initconst = {
+        /* VIN0 */
+        DEFINE_RES_MEM(0xe6ef0000, 0x1000),
+        DEFINE_RES_IRQ(gic_spi(188)),
+        /* VIN1 */
+        DEFINE_RES_MEM(0xe6ef1000, 0x1000),
+        DEFINE_RES_IRQ(gic_spi(189)),
+};
+static void __init lager_add_vin_device(unsigned idx,
+                                        struct rcar_vin_platform_data *pdata)
+{
+        struct platform_device_info vin_info = {
+                .parent         = &platform_bus,
+                .name           = "r8a7790-vin",
+                .id             = idx,
+                .res            = &vin_resources[idx * 2],
+                .num_res        = 2,
+                .dma_mask       = DMA_BIT_MASK(32),
+                .data           = pdata,
+                .size_data      = sizeof(*pdata),
+        };
+        BUG_ON(idx > 1);
+        platform_device_register_full(&vin_info);
+}
+#define LAGER_CAMERA(idx, name, addr, pdata, flag)                      \
+static struct i2c_board_info i2c_cam##idx##_device = {                  \
+        I2C_BOARD_INFO(name, addr),                                     \
+};                                                                      \
+                                                                        \
+static struct rcar_vin_platform_data vin##idx##_pdata = {               \
+        .flags = flag,                                                  \
+};                                                                      \
+                                                                        \
+static struct soc_camera_link cam##idx##_link = {                       \
+        .bus_id = idx,                                                  \
+        .board_info = &i2c_cam##idx##_device,                           \
+        .i2c_adapter_id = 2,                                            \
+        .module_name = name,                                            \
+        .priv = pdata,                                                  \
+}
+/* Camera 0 is not currently supported due to adv7612 support missing */
+LAGER_CAMERA(1, "adv7180", 0x20, NULL, RCAR_VIN_BT656);
+static void __init lager_add_camera1_device(void)
+{
+        platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1,
+                                      &cam1_link, sizeof(cam1_link));
+        lager_add_vin_device(1, &vin1_pdata);
+}
+/* SATA1 */
+static const struct resource sata1_resources[] __initconst = {
+        DEFINE_RES_MEM(0xee500000, 0x2000),
+        DEFINE_RES_IRQ(gic_spi(106)),
+};
+static const struct platform_device_info sata1_info __initconst = {
+        .parent         = &platform_bus,
+        .name           = "sata-r8a7790",
+        .id             = 1,
+        .res            = sata1_resources,
+        .num_res        = ARRAY_SIZE(sata1_resources),
+        .dma_mask       = DMA_BIT_MASK(32),
+};
+/* USBHS */
+static const struct resource usbhs_resources[] __initconst = {
+        DEFINE_RES_MEM(0xe6590000, 0x100),
+        DEFINE_RES_IRQ(gic_spi(107)),
+};
+struct usbhs_private {
+        struct renesas_usbhs_platform_info info;
+        struct usb_phy *phy;
+};
+#define usbhs_get_priv(pdev) \
+        container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info)
+static int usbhs_power_ctrl(struct platform_device *pdev,
+                                void __iomem *base, int enable)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+        if (!priv->phy)
+                return -ENODEV;
+        if (enable) {
+                int retval = usb_phy_init(priv->phy);
+                if (!retval)
+                        retval = usb_phy_set_suspend(priv->phy, 0);
+                return retval;
+        }
+        usb_phy_set_suspend(priv->phy, 1);
+        usb_phy_shutdown(priv->phy);
+        return 0;
+}
+static int usbhs_hardware_init(struct platform_device *pdev)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+        struct usb_phy *phy;
+        int ret;
+        /* USB0 Function - use PWEN as GPIO input to detect DIP Switch SW5
+         * setting to avoid VBUS short circuit due to wrong cable.
+         * PWEN should be pulled up high if USB Function is selected by SW5
+         */
+        gpio_request_one(RCAR_GP_PIN(5, 18), GPIOF_IN, NULL); /* USB0_PWEN */
+        if (!gpio_get_value(RCAR_GP_PIN(5, 18))) {
+                pr_warn("Error: USB Function not selected - check SW5 + SW6\n");
+                ret = -ENOTSUPP;
+                goto error;
+        }
+        phy = usb_get_phy_dev(&pdev->dev, 0);
+        if (IS_ERR(phy)) {
+                ret = PTR_ERR(phy);
+                goto error;
+        }
+        priv->phy = phy;
+        return 0;
+ error:
+        gpio_free(RCAR_GP_PIN(5, 18));
+        return ret;
+}
+static int usbhs_hardware_exit(struct platform_device *pdev)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+        if (!priv->phy)
+                return 0;
+        usb_put_phy(priv->phy);
+        priv->phy = NULL;
+        gpio_free(RCAR_GP_PIN(5, 18));
+        return 0;
+}
+static int usbhs_get_id(struct platform_device *pdev)
+{
+        return USBHS_GADGET;
+}
+static u32 lager_usbhs_pipe_type[] = {
+        USB_ENDPOINT_XFER_CONTROL,
+        USB_ENDPOINT_XFER_ISOC,
+        USB_ENDPOINT_XFER_ISOC,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_INT,
+        USB_ENDPOINT_XFER_INT,
+        USB_ENDPOINT_XFER_INT,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
 };
+static struct usbhs_private usbhs_priv __initdata = {
+        .info = {
+                .platform_callback = {
+                        .power_ctrl     = usbhs_power_ctrl,
+                        .hardware_init  = usbhs_hardware_init,
+                        .hardware_exit  = usbhs_hardware_exit,
+                        .get_id         = usbhs_get_id,
+                },
+                .driver_param = {
+                        .buswait_bwait  = 4,
+                        .pipe_type = lager_usbhs_pipe_type,
+                        .pipe_size = ARRAY_SIZE(lager_usbhs_pipe_type),
+                },
+        }
+};
+static void __init lager_register_usbhs(void)
+{
+        usb_bind_phy("renesas_usbhs", 0, "usb_phy_rcar_gen2");
+        platform_device_register_resndata(&platform_bus,
+                                          "renesas_usbhs", -1,
+                                          usbhs_resources,
+                                          ARRAY_SIZE(usbhs_resources),
+                                          &usbhs_priv.info,
+                                          sizeof(usbhs_priv.info));
+}
+/* USBHS PHY */
+static const struct rcar_gen2_phy_platform_data usbhs_phy_pdata __initconst = {
+        .chan0_pci = 0, /* Channel 0 is USBHS */
+        .chan2_pci = 1, /* Channel 2 is PCI USB */
+};
+static const struct resource usbhs_phy_resources[] __initconst = {
+        DEFINE_RES_MEM(0xe6590100, 0x100),
+};
+/* I2C */
+static struct i2c_board_info i2c2_devices[] = {
+        {
+                I2C_BOARD_INFO("ak4643", 0x12),
+        }
+};
+/* Sound */
+static struct resource rsnd_resources[] __initdata = {
+        [RSND_GEN2_SCU]  = DEFINE_RES_MEM(0xec500000, 0x1000),
+        [RSND_GEN2_ADG]  = DEFINE_RES_MEM(0xec5a0000, 0x100),
+        [RSND_GEN2_SSIU] = DEFINE_RES_MEM(0xec540000, 0x1000),
+        [RSND_GEN2_SSI]  = DEFINE_RES_MEM(0xec541000, 0x1280),
+};
+static struct rsnd_ssi_platform_info rsnd_ssi[] = {
+        RSND_SSI_SET(0, 0, gic_spi(370), RSND_SSI_PLAY),
+        RSND_SSI_SET(0, 0, gic_spi(371), RSND_SSI_CLK_PIN_SHARE),
+};
+static struct rsnd_scu_platform_info rsnd_scu[2] = {
+        /* no member at this point */
+};
+static struct rcar_snd_info rsnd_info = {
+        .flags          = RSND_GEN2,
+        .ssi_info       = rsnd_ssi,
+        .ssi_info_nr    = ARRAY_SIZE(rsnd_ssi),
+        .scu_info       = rsnd_scu,
+        .scu_info_nr    = ARRAY_SIZE(rsnd_scu),
+};
+static struct asoc_simple_card_info rsnd_card_info = {
+        .name           = "AK4643",
+        .card           = "SSI01-AK4643",
+        .codec          = "ak4642-codec.2-0012",
+        .platform       = "rcar_sound",
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
+        .cpu_dai = {
+                .name   = "rcar_sound",
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
+        },
+        .codec_dai = {
+                .name   = "ak4642-hifi",
+                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+                .sysclk = 11289600,
+        },
+};
+static void __init lager_add_rsnd_device(void)
+{
+        struct platform_device_info cardinfo = {
+                .parent         = &platform_bus,
+                .name           = "asoc-simple-card",
+                .id             = -1,
+                .data           = &rsnd_card_info,
+                .size_data      = sizeof(struct asoc_simple_card_info),
+                .dma_mask       = DMA_BIT_MASK(32),
+        };
+        i2c_register_board_info(2, i2c2_devices,
+                                ARRAY_SIZE(i2c2_devices));
+        platform_device_register_resndata(
+                &platform_bus, "rcar_sound", -1,
+                rsnd_resources, ARRAY_SIZE(rsnd_resources),
+                &rsnd_info, sizeof(rsnd_info));
+        platform_device_register_full(&cardinfo);
+}
+/* SDHI0 */
+static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
+        .tmio_caps2     = MMC_CAP2_NO_MULTI_READ,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT |
+                          TMIO_MMC_WRPROTECT_DISABLE,
+};
+static struct resource sdhi0_resources[] __initdata = {
+        DEFINE_RES_MEM(0xee100000, 0x200),
+        DEFINE_RES_IRQ(gic_spi(165)),
+};
+/* SDHI2 */
+static struct sh_mobile_sdhi_info sdhi2_info __initdata = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
+        .tmio_caps2     = MMC_CAP2_NO_MULTI_READ,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT |
+                          TMIO_MMC_WRPROTECT_DISABLE,
+};
+static struct resource sdhi2_resources[] __initdata = {
+        DEFINE_RES_MEM(0xee140000, 0x100),
+        DEFINE_RES_IRQ(gic_spi(167)),
+};
+/* Internal PCI1 */
+static const struct resource pci1_resources[] __initconst = {
+        DEFINE_RES_MEM(0xee0b0000, 0x10000),    /* CFG */
+        DEFINE_RES_MEM(0xee0a0000, 0x10000),    /* MEM */
+        DEFINE_RES_IRQ(gic_spi(112)),
+};
+static const struct platform_device_info pci1_info __initconst = {
+        .parent         = &platform_bus,
+        .name           = "pci-rcar-gen2",
+        .id             = 1,
+        .res            = pci1_resources,
+        .num_res        = ARRAY_SIZE(pci1_resources),
+        .dma_mask       = DMA_BIT_MASK(32),
+};
+static void __init lager_add_usb1_device(void)
+{
+        platform_device_register_full(&pci1_info);
+}
+/* Internal PCI2 */
+static const struct resource pci2_resources[] __initconst = {
+        DEFINE_RES_MEM(0xee0d0000, 0x10000),    /* CFG */
+        DEFINE_RES_MEM(0xee0c0000, 0x10000),    /* MEM */
+        DEFINE_RES_IRQ(gic_spi(113)),
+};
+static const struct platform_device_info pci2_info __initconst = {
+        .parent         = &platform_bus,
+        .name           = "pci-rcar-gen2",
+        .id             = 2,
+        .res            = pci2_resources,
+        .num_res        = ARRAY_SIZE(pci2_resources),
+        .dma_mask       = DMA_BIT_MASK(32),
+};
+static void __init lager_add_usb2_device(void)
+{
+        platform_device_register_full(&pci2_info);
+}
 static const struct pinctrl_map lager_pinctrl_map[] = {
        /* DU (CN10: ARGB0, CN13: LVDS) */
        PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
@@ -299,12 +700,43 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
                                  "du_sync_1", "du"),
        PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
                                  "du_clk_out_0", "du"),
+        /* I2C2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar.2", "pfc-r8a7790",
+                                  "i2c2", "i2c2"),
+        /* QSPI */
+        PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
+                                  "qspi_ctrl", "qspi"),
+        PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
+                                  "qspi_data4", "qspi"),
        /* SCIF0 (CN19: DEBUG SERIAL0) */
        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
                                  "scif0_data", "scif0"),
        /* SCIF1 (CN20: DEBUG SERIAL1) */
        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
                                  "scif1_data", "scif1"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
+                                  "sdhi0_cd", "sdhi0"),
+        /* SDHI2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
+                                  "sdhi2_data4", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
+                                  "sdhi2_ctrl", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
+                                  "sdhi2_cd", "sdhi2"),
+        /* SSI (CN17: sound) */
+        PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
+                                  "ssi0129_ctrl", "ssi"),
+        PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
+                                  "ssi0_data", "ssi"),
+        PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
+                                  "ssi1_data", "ssi"),
+        PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
+                                  "audio_clk_a", "audio_clk"),
        /* MMCIF1 */
        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
                                  "mmc1_data8", "mmc1"),
@@ -319,6 +751,31 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
                                  "eth_rmii", "eth"),
        PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
                                  "intc_irq0", "intc"),
+        /* VIN0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+                                  "vin0_data24", "vin0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+                                  "vin0_sync", "vin0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+                                  "vin0_field", "vin0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+                                  "vin0_clkenb", "vin0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
+                                  "vin0_clk", "vin0"),
+        /* VIN1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
+                                  "vin1_data8", "vin1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
+                                  "vin1_clk", "vin1"),
+        /* USB0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790",
+                                  "usb0_ovc_vbus", "usb0"),
+        /* USB1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.1", "pfc-r8a7790",
+                                  "usb1", "usb1"),
+        /* USB2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.2", "pfc-r8a7790",
+                                  "usb2", "usb2"),
 };
 static void __init lager_add_standard_devices(void)
@@ -346,10 +803,7 @@ static void __init lager_add_standard_devices(void)
                                          mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
                                          &mmcif1_pdata, sizeof(mmcif1_pdata));
-        platform_device_register_resndata(&platform_bus, "r8a7790-ether", -1,
+        platform_device_register_full(&ether_info);
-                                          ether_resources,
-                                          ARRAY_SIZE(ether_resources),
-                                          &ether_pdata, sizeof(ether_pdata));
        lager_add_du_device();
@@ -368,6 +822,28 @@ static void __init lager_add_standard_devices(void)
                                      &vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
        platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
                                      &vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
+        lager_add_camera1_device();
+        platform_device_register_full(&sata1_info);
+        platform_device_register_resndata(&platform_bus, "usb_phy_rcar_gen2",
+                                          -1, usbhs_phy_resources,
+                                          ARRAY_SIZE(usbhs_phy_resources),
+                                          &usbhs_phy_pdata,
+                                          sizeof(usbhs_phy_pdata));
+        lager_register_usbhs();
+        lager_add_usb1_device();
+        lager_add_usb2_device();
+        lager_add_rsnd_device();
+        platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 0,
+                                          sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
+                                          &sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
+        platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 2,
+                                          sdhi2_resources, ARRAY_SIZE(sdhi2_resources),
+                                          &sdhi2_info, sizeof(struct sh_mobile_sdhi_info));
 }
 /*
@@ -391,6 +867,8 @@ static void __init lager_init(void)
 {
        lager_add_standard_devices();
+        irq_set_irq_type(irq_pin(0), IRQ_TYPE_LEVEL_LOW);
        if (IS_ENABLED(CONFIG_PHYLIB))
                phy_register_fixup_for_id("r8a7790-ether-ff:01",
                                          lager_ksz8041_fixup);
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 3aba0372f630..0ff4d8e45cf7 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -509,9 +509,9 @@ static struct asoc_simple_card_info fsi2_hdmi_info = {
        .card           = "FSI2B-HDMI",
        .codec          = "sh-mobile-hdmi",
        .platform       = "sh_fsi2",
+        .daifmt         = SND_SOC_DAIFMT_CBS_CFS,
        .cpu_dai = {
                .name   = "fsib-dai",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
        },
        .codec_dai = {
                .name   = "sh_mobile_hdmi-hifi",
@@ -905,14 +905,12 @@ static struct asoc_simple_card_info fsi2_ak4643_info = {
        .card           = "FSI2A-AK4643",
        .codec          = "ak4642-codec.0-0013",
        .platform       = "sh_fsi2",
-        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
        .cpu_dai = {
                .name   = "fsia-dai",
-                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
        },
        .codec_dai = {
                .name   = "ak4642-hifi",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
                .sysclk = 11289600,
        },
 };
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index e6ab0cd5b286..bee0073c9b64 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -22,12 +22,15 @@
 #include <mach/common.h>
 #include <mach/r7s72100.h>
-/* registers */
+/* Frequency Control Registers */
 #define FRQCR           0xfcfe0010
 #define FRQCR2          0xfcfe0014
+/* Standby Control Registers */
 #define STBCR3          0xfcfe0420
 #define STBCR4          0xfcfe0424
+#define STBCR7          0xfcfe0430
 #define STBCR9          0xfcfe0438
+#define STBCR10         0xfcfe043c
 #define PLL_RATE 30
@@ -67,7 +70,7 @@ static struct clk pll_clk = {
 static unsigned long bus_recalc(struct clk *clk)
 {
-        return clk->parent->rate * 2 / 3;
+        return clk->parent->rate / 3;
 }
 static struct sh_clk_ops bus_clk_ops = {
@@ -145,15 +148,25 @@ struct clk div4_clks[DIV4_NR] = {
                                        | CLK_ENABLE_ON_INIT),
 };
-enum {  MSTP97, MSTP96, MSTP95, MSTP94,
+enum {
+        MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
+        MSTP97, MSTP96, MSTP95, MSTP94,
+        MSTP74,
        MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
-        MSTP33, MSTP_NR };
+        MSTP33, MSTP_NR
+};
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
+        [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
+        [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
+        [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
+        [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
        [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
        [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
        [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
        [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
+        [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
        [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
        [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
        [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
@@ -176,6 +189,21 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
        /* MSTP clocks */
+        CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
+        CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
+        CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
+        CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
+        CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
+        CLKDEV_DEV_ID("e800c800.spi", &mstp_clks[MSTP107]),
+        CLKDEV_DEV_ID("e800d000.spi", &mstp_clks[MSTP106]),
+        CLKDEV_DEV_ID("e800d800.spi", &mstp_clks[MSTP105]),
+        CLKDEV_DEV_ID("e800e000.spi", &mstp_clks[MSTP104]),
+        CLKDEV_DEV_ID("e800e800.spi", &mstp_clks[MSTP103]),
+        CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
+        CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
+        CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
+        CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),
+        CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
        CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
        /* ICK */
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 9783945f8bc7..2009a9bc6356 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -221,6 +221,10 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
        CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
+        CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
+        CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
+        CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
+        CLKDEV_ICK_ID("clk_i", "rcar_sound", &s1_clk),
        CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
        CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
        CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index f1fb89b76786..8e403ae0c7b2 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -47,17 +47,10 @@
 #define MD(nr)  BIT(nr)
-#define FRQMR           IOMEM(0xffc80014)
 #define MSTPCR0         IOMEM(0xffc80030)
 #define MSTPCR1         IOMEM(0xffc80034)
 #define MSTPCR3         IOMEM(0xffc8003c)
 #define MSTPSR1         IOMEM(0xffc80044)
-#define MSTPSR4         IOMEM(0xffc80048)
-#define MSTPSR6         IOMEM(0xffc8004c)
-#define MSTPCR4         IOMEM(0xffc80050)
-#define MSTPCR5         IOMEM(0xffc80054)
-#define MSTPCR6         IOMEM(0xffc80058)
-#define MSTPCR7         IOMEM(0xffc80040)
 #define MODEMR          0xffcc0020
@@ -127,16 +120,16 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
        [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
        [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
-        [MSTP120] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 20, 0), /* VIN3 */
+        [MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */
-        [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
+        [MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */
-        [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
+        [MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */
-        [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
+        [MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */
-        [MSTP110] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 10, 0), /* VIN0 */
+        [MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */
-        [MSTP109] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  9, 0), /* VIN1 */
+        [MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1,  9, MSTPSR1, 0), /* VIN1 */
-        [MSTP108] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  8, 0), /* VIN2 */
+        [MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1,  8, MSTPSR1, 0), /* VIN2 */
-        [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */
+        [MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1,  3, MSTPSR1, 0), /* DU */
-        [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1,  1, 0), /* USB2 */
+        [MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1,  1, MSTPSR1, 0), /* USB2 */
-        [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1,  0, 0), /* USB0/1 */
+        [MSTP100] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1,  0, MSTPSR1, 0), /* USB0/1 */
        [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
        [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
        [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index f44987a92ad4..3f93503f5b96 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -43,17 +43,26 @@
 *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
 */
-#define CPG_BASE 0xe6150000
+#define CPG_BASE        0xe6150000
-#define CPG_LEN 0x1000
+#define CPG_LEN         0x1000
-#define SMSTPCR1 0xe6150134
+#define SMSTPCR1        0xe6150134
-#define SMSTPCR2 0xe6150138
+#define SMSTPCR2        0xe6150138
-#define SMSTPCR3 0xe615013c
+#define SMSTPCR3        0xe615013c
-#define SMSTPCR5 0xe6150144
+#define SMSTPCR5        0xe6150144
-#define SMSTPCR7 0xe615014c
+#define SMSTPCR7        0xe615014c
-#define SMSTPCR8 0xe6150990
+#define SMSTPCR8        0xe6150990
-#define SMSTPCR9 0xe6150994
+#define SMSTPCR9        0xe6150994
-#define SMSTPCR10 0xe6150998
+#define SMSTPCR10       0xe6150998
+#define MSTPSR1         IOMEM(0xe6150038)
+#define MSTPSR2         IOMEM(0xe6150040)
+#define MSTPSR3         IOMEM(0xe6150048)
+#define MSTPSR5         IOMEM(0xe615003c)
+#define MSTPSR7         IOMEM(0xe61501c4)
+#define MSTPSR8         IOMEM(0xe61509a0)
+#define MSTPSR9         IOMEM(0xe61509a4)
+#define MSTPSR10        IOMEM(0xe61509a8)
 #define SDCKCR          0xE6150074
 #define SD2CKCR         0xE6150078
@@ -82,6 +91,15 @@ static struct clk main_clk = {
        .ops    = &followparent_clk_ops,
 };
+static struct clk audio_clk_a = {
+};
+static struct clk audio_clk_b = {
+};
+static struct clk audio_clk_c = {
+};
 /*
 * clock ratio of these clock will be updated
 * on r8a7790_clock_init()
@@ -115,6 +133,9 @@ SH_FIXED_RATIO_CLK_SET(ddr_clk,			pll3_clk,	1, 8);
 SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
 static struct clk *main_clks[] = {
+        &audio_clk_a,
+        &audio_clk_b,
+        &audio_clk_c,
        &extal_clk,
        &extal_div2_clk,
        &main_clk,
@@ -183,15 +204,22 @@ static struct clk div6_clks[DIV6_NR] = {
 /* MSTP */
 enum {
+        MSTP1017, /* parent of SCU */
+        MSTP1031, MSTP1030,
+        MSTP1029, MSTP1028, MSTP1027, MSTP1026, MSTP1025, MSTP1024, MSTP1023, MSTP1022,
        MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
        MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
        MSTP931, MSTP930, MSTP929, MSTP928,
        MSTP917,
+        MSTP815, MSTP814,
        MSTP813,
+        MSTP811, MSTP810, MSTP809, MSTP808,
        MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
        MSTP717, MSTP716,
-        MSTP704,
+        MSTP704, MSTP703,
        MSTP522,
+        MSTP502, MSTP501,
        MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
        MSTP124,
@@ -199,53 +227,77 @@ enum {
 };
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */
+        [MSTP1031] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 31, MSTPSR10, 0), /* SCU0 */
-        [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */
+        [MSTP1030] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 30, MSTPSR10, 0), /* SCU1 */
-        [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */
+        [MSTP1029] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 29, MSTPSR10, 0), /* SCU2 */
-        [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */
+        [MSTP1028] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 28, MSTPSR10, 0), /* SCU3 */
-        [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */
+        [MSTP1027] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 27, MSTPSR10, 0), /* SCU4 */
-        [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */
+        [MSTP1026] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 26, MSTPSR10, 0), /* SCU5 */
-        [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  9, 0), /* SSI6 */
+        [MSTP1025] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 25, MSTPSR10, 0), /* SCU6 */
-        [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  8, 0), /* SSI7 */
+        [MSTP1024] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 24, MSTPSR10, 0), /* SCU7 */
-        [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  7, 0), /* SSI8 */
+        [MSTP1023] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 23, MSTPSR10, 0), /* SCU8 */
-        [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  6, 0), /* SSI9 */
+        [MSTP1022] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 22, MSTPSR10, 0), /* SCU9 */
-        [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  5, 0), /* SSI ALL */
+        [MSTP1017] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 17, MSTPSR10, 0), /* SCU */
-        [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */
+        [MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
-        [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */
+        [MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
-        [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
+        [MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
-        [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
+        [MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
-        [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
+        [MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
-        [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
+        [MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
-        [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
+        [MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
-        [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
+        [MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
-        [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
+        [MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
-        [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
+        [MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
-        [MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */
+        [MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
-        [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
+        [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
-        [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
-        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
+        [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
-        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
+        [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
-        [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */
+        [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
-        [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
+        [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
-        [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
+        [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
-        [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
-        [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
-        [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */
+        [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
-        [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */
+        [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  9, MSTPSR8, 0), /* VIN2 */
-        [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */
+        [MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  8, MSTPSR8, 0), /* VIN3 */
-        [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
+        [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
-        [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
+        [MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
-        [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
+        [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
-        [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
+        [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
-        [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
-        [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
-        [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
-        [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
+        [MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
+        [MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
+        [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
+        [MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
+        [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
+        [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
+        [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
+        [MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
+        [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
+        [MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
+        [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
+        [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
+        [MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
+        [MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
+        [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
+        [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
+        [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
+        [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
+        [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
+        [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
+        [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
 };
 static struct clk_lookup lookups[] = {
        /* main clocks */
+        CLKDEV_CON_ID("audio_clk_a",    &audio_clk_a),
+        CLKDEV_CON_ID("audio_clk_b",    &audio_clk_b),
+        CLKDEV_CON_ID("audio_clk_c",    &audio_clk_c),
+        CLKDEV_CON_ID("audio_clk_internal",     &m2_clk),
        CLKDEV_CON_ID("extal",          &extal_clk),
        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
        CLKDEV_CON_ID("main",           &main_clk),
@@ -291,32 +343,32 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
        CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
        CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
-        CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
        CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
-        CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
        CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
-        CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
        CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
-        CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
        CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
        CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
-        CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
+        CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
+        CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
+        CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
-        CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
+        CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
-        CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
-        CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
-        CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
-        CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]),
        CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
-        CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
        CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
        CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
        CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
        CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
+        CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
+        CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
+        CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
+        CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
+        CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
        /* ICK */
        CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
@@ -325,6 +377,20 @@ static struct clk_lookup lookups[] = {
        CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
        CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
        CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
+        CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
+        CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
+        CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
+        CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
+        CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP1031]),
+        CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP1030]),
+        CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP1029]),
+        CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP1028]),
+        CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP1027]),
+        CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP1026]),
+        CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP1025]),
+        CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP1024]),
+        CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP1023]),
+        CLKDEV_ICK_ID("scu.9", "rcar_sound", &mstp_clks[MSTP1022]),
        CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
        CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
        CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index f5461262ee25..701383fe3267 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -59,10 +59,19 @@
 #define SMSTPCR10       0xE6150998
 #define SMSTPCR11       0xE615099C
+#define MSTPSR1         IOMEM(0xe6150038)
+#define MSTPSR2         IOMEM(0xe6150040)
+#define MSTPSR3         IOMEM(0xe6150048)
+#define MSTPSR5         IOMEM(0xe615003c)
+#define MSTPSR7         IOMEM(0xe61501c4)
+#define MSTPSR8         IOMEM(0xe61509a0)
+#define MSTPSR9         IOMEM(0xe61509a4)
+#define MSTPSR11        IOMEM(0xe61509ac)
 #define MODEMR          0xE6160060
 #define SDCKCR          0xE6150074
-#define SD2CKCR         0xE6150078
+#define SD1CKCR         0xE6150078
-#define SD3CKCR         0xE615007C
+#define SD2CKCR         0xE615026c
 #define MMC0CKCR        0xE6150240
 #define MMC1CKCR        0xE6150244
 #define SSPCKCR         0xE6150248
@@ -93,6 +102,7 @@ static struct clk main_clk = {
 */
 SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
 SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
 /* fixed ratio clock */
 SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
@@ -103,7 +113,9 @@ SH_FIXED_RATIO_CLK_SET(hp_clk,			pll1_clk,	1, 12);
 SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
 SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
 SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
+SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
 SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
 static struct clk *main_clks[] = {
        &extal_clk,
@@ -114,46 +126,103 @@ static struct clk *main_clks[] = {
        &pll3_clk,
        &hp_clk,
        &p_clk,
+        &qspi_clk,
        &rclk_clk,
        &mp_clk,
        &cp_clk,
+        &zg_clk,
        &zx_clk,
+        &zs_clk,
+};
+/* SDHI (DIV4) clock */
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+enum {
+        DIV4_SDH, DIV4_SD0,
+        DIV4_NR
+};
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+};
+/* DIV6 clocks */
+enum {
+        DIV6_SD1, DIV6_SD2,
+        DIV6_NR
+};
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_SD1]      = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
+        [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
 };
 /* MSTP */
 enum {
+        MSTP1108, MSTP1107, MSTP1106,
+        MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
+        MSTP917,
+        MSTP815, MSTP814,
        MSTP813,
+        MSTP811, MSTP810, MSTP809,
        MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
        MSTP719, MSTP718, MSTP715, MSTP714,
        MSTP522,
+        MSTP314, MSTP312, MSTP311,
        MSTP216, MSTP207, MSTP206,
-        MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
+        MSTP204, MSTP203, MSTP202,
        MSTP124,
        MSTP_NR
 };
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
+        [MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */
-        [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
+        [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */
-        [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
+        [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */
-        [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
+        [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
-        [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
+        [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
-        [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
-        [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
+        [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
-        [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
+        [MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
-        [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
+        [MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
-        [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
+        [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
-        [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
+        [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
-        [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
+        [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
-        [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
+        [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
-        [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
+        [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
-        [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
-        [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
-        [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
-        [MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */
+        [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
-        [MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */
+        [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
-        [MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */
+        [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
-        [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
+        [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
+        [MSTP719] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 19, MSTPSR7, 0), /* SCIF2 */
+        [MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */
+        [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
+        [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
+        [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
+        [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
+        [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
+        [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */
+        [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
+        [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
+        [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
+        [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
+        [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
+        [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
+        [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
 };
 static struct clk_lookup lookups[] = {
@@ -165,8 +234,11 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("pll1",           &pll1_clk),
        CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
        CLKDEV_CON_ID("pll3",           &pll3_clk),
+        CLKDEV_CON_ID("zg",             &zg_clk),
+        CLKDEV_CON_ID("zs",             &zs_clk),
        CLKDEV_CON_ID("hp",             &hp_clk),
        CLKDEV_CON_ID("p",              &p_clk),
+        CLKDEV_CON_ID("qspi",           &qspi_clk),
        CLKDEV_CON_ID("rclk",           &rclk_clk),
        CLKDEV_CON_ID("mp",             &mp_clk),
        CLKDEV_CON_ID("cp",             &cp_clk),
@@ -188,13 +260,27 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */
        CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */
        CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */
-        CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
+        CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1106]), /* SCIFA3 */
-        CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
+        CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1107]), /* SCIFA4 */
-        CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
+        CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1108]), /* SCIFA5 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
        CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
-        CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.4", &mstp_clks[MSTP927]),
+        CLKDEV_DEV_ID("i2c-rcar_gen2.5", &mstp_clks[MSTP925]),
        CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
+        CLKDEV_DEV_ID("r8a7791-vin.0", &mstp_clks[MSTP811]),
+        CLKDEV_DEV_ID("r8a7791-vin.1", &mstp_clks[MSTP810]),
+        CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),
+        CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
+        CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
 };
 #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
@@ -232,10 +318,21 @@ void __init r8a7791_clock_init(void)
                break;
        }
+        if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+        else
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                ret = clk_register(main_clks[k]);
        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+        if (!ret)
                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index e31980590eb4..cb8e32deb2a3 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -25,7 +25,6 @@ extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu,
                                            struct task_struct *idle);
 extern void shmobile_smp_apmu_cpu_die(unsigned int cpu);
 extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu);
-extern void shmobile_invalidate_start(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
diff --git a/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt b/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt
new file mode 100644
index 000000000000..9531f46a822a
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/head-kzm9g.txt
@@ -0,0 +1,410 @@
+LIST "KZM9G low-level initialization routine."
+LIST "Adapted from u-boot KZM9G support code."
+LIST "Copyright (C) 2013 Ulrich Hecht"
+LIST "This program is free software; you can redistribute it and/or modify"
+LIST "it under the terms of the GNU General Public License version 2 as"
+LIST "published by the Free Software Foundation."
+LIST "This program is distributed in the hope that it will be useful,"
+LIST "but WITHOUT ANY WARRANTY; without even the implied warranty of"
+LIST "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the"
+LIST "GNU General Public License for more details."
+LIST "Register definitions:"
+LIST "Secure control register"
+#define LIFEC_SEC_SRC (0xE6110008)
+LIST "RWDT"
+#define RWDT_BASE   (0xE6020000)
+#define RWTCSRA0 (RWDT_BASE + 0x04)
+LIST "HPB Semaphore Control Registers"
+#define HPBSCR_BASE (0xE6000000)
+#define HPBCTRL6 (HPBSCR_BASE + 0x1030)
+#define SBSC1_BASE  (0xFE400000)
+#define SDCR0A          (SBSC1_BASE + 0x0008)
+#define SDCR1A          (SBSC1_BASE + 0x000C)
+#define SDPCRA          (SBSC1_BASE + 0x0010)
+#define SDCR0SA         (SBSC1_BASE + 0x0018)
+#define SDCR1SA         (SBSC1_BASE + 0x001C)
+#define RTCSRA          (SBSC1_BASE + 0x0020)
+#define RTCORA          (SBSC1_BASE + 0x0028)
+#define RTCORHA         (SBSC1_BASE + 0x002C)
+#define SDWCRC0A        (SBSC1_BASE + 0x0040)
+#define SDWCRC1A        (SBSC1_BASE + 0x0044)
+#define SDWCR00A        (SBSC1_BASE + 0x0048)
+#define SDWCR01A        (SBSC1_BASE + 0x004C)
+#define SDWCR10A        (SBSC1_BASE + 0x0050)
+#define SDWCR11A        (SBSC1_BASE + 0x0054)
+#define SDWCR2A         (SBSC1_BASE + 0x0060)
+#define SDWCRC2A        (SBSC1_BASE + 0x0064)
+#define ZQCCRA          (SBSC1_BASE + 0x0068)
+#define SDMRACR0A       (SBSC1_BASE + 0x0084)
+#define SDMRTMPCRA      (SBSC1_BASE + 0x008C)
+#define SDMRTMPMSKA     (SBSC1_BASE + 0x0094)
+#define SDGENCNTA       (SBSC1_BASE + 0x009C)
+#define SDDRVCR0A       (SBSC1_BASE + 0x00B4)
+#define DLLCNT0A        (SBSC1_BASE + 0x0354)
+#define SDMRA1  (0xFE500000)
+#define SDMRA2  (0xFE5C0000)
+#define SDMRA3  (0xFE504000)
+#define SBSC2_BASE  (0xFB400000)
+#define SDCR0B          (SBSC2_BASE + 0x0008)
+#define SDCR1B          (SBSC2_BASE + 0x000C)
+#define SDPCRB          (SBSC2_BASE + 0x0010)
+#define SDCR0SB         (SBSC2_BASE + 0x0018)
+#define SDCR1SB         (SBSC2_BASE + 0x001C)
+#define RTCSRB          (SBSC2_BASE + 0x0020)
+#define RTCORB          (SBSC2_BASE + 0x0028)
+#define RTCORHB         (SBSC2_BASE + 0x002C)
+#define SDWCRC0B        (SBSC2_BASE + 0x0040)
+#define SDWCRC1B        (SBSC2_BASE + 0x0044)
+#define SDWCR00B        (SBSC2_BASE + 0x0048)
+#define SDWCR01B        (SBSC2_BASE + 0x004C)
+#define SDWCR10B        (SBSC2_BASE + 0x0050)
+#define SDWCR11B        (SBSC2_BASE + 0x0054)
+#define SDPDCR0B        (SBSC2_BASE + 0x0058)
+#define SDWCR2B         (SBSC2_BASE + 0x0060)
+#define SDWCRC2B        (SBSC2_BASE + 0x0064)
+#define ZQCCRB          (SBSC2_BASE + 0x0068)
+#define SDMRACR0B       (SBSC2_BASE + 0x0084)
+#define SDMRTMPCRB      (SBSC2_BASE + 0x008C)
+#define SDMRTMPMSKB     (SBSC2_BASE + 0x0094)
+#define SDGENCNTB       (SBSC2_BASE + 0x009C)
+#define DPHYCNT0B       (SBSC2_BASE + 0x00A0)
+#define DPHYCNT1B       (SBSC2_BASE + 0x00A4)
+#define DPHYCNT2B       (SBSC2_BASE + 0x00A8)
+#define SDDRVCR0B       (SBSC2_BASE + 0x00B4)
+#define DLLCNT0B        (SBSC2_BASE + 0x0354)
+#define SDMRB1  (0xFB500000)
+#define SDMRB2  (0xFB5C0000)
+#define SDMRB3  (0xFB504000)
+#define CPG_BASE   (0xE6150000)
+#define FRQCRA          (CPG_BASE + 0x0000)
+#define FRQCRB          (CPG_BASE + 0x0004)
+#define FRQCRD          (CPG_BASE + 0x00E4)
+#define VCLKCR1         (CPG_BASE + 0x0008)
+#define VCLKCR2         (CPG_BASE + 0x000C)
+#define VCLKCR3         (CPG_BASE + 0x001C)
+#define ZBCKCR          (CPG_BASE + 0x0010)
+#define FLCKCR          (CPG_BASE + 0x0014)
+#define SD0CKCR         (CPG_BASE + 0x0074)
+#define SD1CKCR         (CPG_BASE + 0x0078)
+#define SD2CKCR         (CPG_BASE + 0x007C)
+#define FSIACKCR        (CPG_BASE + 0x0018)
+#define SUBCKCR         (CPG_BASE + 0x0080)
+#define SPUACKCR        (CPG_BASE + 0x0084)
+#define SPUVCKCR        (CPG_BASE + 0x0094)
+#define MSUCKCR         (CPG_BASE + 0x0088)
+#define HSICKCR         (CPG_BASE + 0x008C)
+#define FSIBCKCR        (CPG_BASE + 0x0090)
+#define MFCK1CR         (CPG_BASE + 0x0098)
+#define MFCK2CR         (CPG_BASE + 0x009C)
+#define DSITCKCR        (CPG_BASE + 0x0060)
+#define DSI0PCKCR       (CPG_BASE + 0x0064)
+#define DSI1PCKCR       (CPG_BASE + 0x0068)
+#define DSI0PHYCR       (CPG_BASE + 0x006C)
+#define DVFSCR3         (CPG_BASE + 0x0174)
+#define DVFSCR4         (CPG_BASE + 0x0178)
+#define DVFSCR5         (CPG_BASE + 0x017C)
+#define MPMODE          (CPG_BASE + 0x00CC)
+#define PLLECR          (CPG_BASE + 0x00D0)
+#define PLL0CR          (CPG_BASE + 0x00D8)
+#define PLL1CR          (CPG_BASE + 0x0028)
+#define PLL2CR          (CPG_BASE + 0x002C)
+#define PLL3CR          (CPG_BASE + 0x00DC)
+#define PLL0STPCR       (CPG_BASE + 0x00F0)
+#define PLL1STPCR       (CPG_BASE + 0x00C8)
+#define PLL2STPCR       (CPG_BASE + 0x00F8)
+#define PLL3STPCR       (CPG_BASE + 0x00FC)
+#define RMSTPCR0        (CPG_BASE + 0x0110)
+#define RMSTPCR1        (CPG_BASE + 0x0114)
+#define RMSTPCR2        (CPG_BASE + 0x0118)
+#define RMSTPCR3        (CPG_BASE + 0x011C)
+#define RMSTPCR4        (CPG_BASE + 0x0120)
+#define RMSTPCR5        (CPG_BASE + 0x0124)
+#define SMSTPCR0        (CPG_BASE + 0x0130)
+#define SMSTPCR2        (CPG_BASE + 0x0138)
+#define SMSTPCR3        (CPG_BASE + 0x013C)
+#define CPGXXCR4        (CPG_BASE + 0x0150)
+#define SRCR0           (CPG_BASE + 0x80A0)
+#define SRCR2           (CPG_BASE + 0x80B0)
+#define SRCR3           (CPG_BASE + 0x80A8)
+#define VREFCR          (CPG_BASE + 0x00EC)
+#define PCLKCR          (CPG_BASE + 0x1020)
+#define PORT32CR (0xE6051020)
+#define PORT33CR (0xE6051021)
+#define PORT34CR (0xE6051022)
+#define PORT35CR (0xE6051023)
+LIST "DRAM initialization code:"
+EW RWTCSRA0, 0xA507
+ED_AND LIFEC_SEC_SRC, 0xFFFF7FFF
+ED_AND SMSTPCR3,0xFFFF7FFF
+ED_AND SRCR3, 0xFFFF7FFF
+ED_AND SMSTPCR2,0xFFFBFFFF
+ED_AND SRCR2, 0xFFFBFFFF
+ED PLLECR, 0x00000000
+WAIT_MASK PLLECR, 0x00000F00, 0x00000000
+WAIT_MASK FRQCRB, 0x80000000, 0x00000000
+ED PLL0CR, 0x2D000000
+ED PLL1CR, 0x17100000
+ED FRQCRB, 0x96235880
+WAIT_MASK FRQCRB, 0x80000000, 0x00000000
+ED FLCKCR, 0x0000000B
+ED_AND SMSTPCR0, 0xFFFFFFFD
+ED_AND SRCR0, 0xFFFFFFFD
+ED 0xE6001628, 0x514
+ED 0xE6001648, 0x514
+ED 0xE6001658, 0x514
+ED 0xE6001678, 0x514
+ED DVFSCR4, 0x00092000
+ED DVFSCR5, 0x000000DC
+ED PLLECR, 0x00000000
+WAIT_MASK PLLECR, 0x00000F00, 0x00000000
+ED FRQCRA, 0x0012453C
+ED FRQCRB, 0x80431350
+WAIT_MASK FRQCRB, 0x80000000, 0x00000000
+ED FRQCRD, 0x00000B0B
+WAIT_MASK FRQCRD, 0x80000000, 0x00000000
+ED PCLKCR, 0x00000003
+ED VCLKCR1, 0x0000012F
+ED VCLKCR2, 0x00000119
+ED VCLKCR3, 0x00000119
+ED ZBCKCR, 0x00000002
+ED FLCKCR, 0x00000005
+ED SD0CKCR, 0x00000080
+ED SD1CKCR, 0x00000080
+ED SD2CKCR, 0x00000080
+ED FSIACKCR, 0x0000003F
+ED FSIBCKCR, 0x0000003F
+ED SUBCKCR, 0x00000080
+ED SPUACKCR, 0x0000000B
+ED SPUVCKCR, 0x0000000B
+ED MSUCKCR, 0x0000013F
+ED HSICKCR, 0x00000080
+ED MFCK1CR, 0x0000003F
+ED MFCK2CR, 0x0000003F
+ED DSITCKCR, 0x00000107
+ED DSI0PCKCR, 0x00000313
+ED DSI1PCKCR, 0x0000130D
+ED DSI0PHYCR, 0x2A800E0E
+ED PLL0CR, 0x1E000000
+ED PLL0CR, 0x2D000000
+ED PLL1CR, 0x17100000
+ED PLL2CR, 0x27000080
+ED PLL3CR, 0x1D000000
+ED PLL0STPCR, 0x00080000
+ED PLL1STPCR, 0x000120C0
+ED PLL2STPCR, 0x00012000
+ED PLL3STPCR, 0x00000030
+ED PLLECR, 0x0000000B
+WAIT_MASK PLLECR, 0x00000B00, 0x00000B00
+ED DVFSCR3, 0x000120F0
+ED MPMODE, 0x00000020
+ED VREFCR, 0x0000028A
+ED RMSTPCR0, 0xE4628087
+ED RMSTPCR1, 0xFFFFFFFF
+ED RMSTPCR2, 0x53FFFFFF
+ED RMSTPCR3, 0xFFFFFFFF
+ED RMSTPCR4, 0x00800D3D
+ED RMSTPCR5, 0xFFFFF3FF
+ED SMSTPCR2, 0x00000000
+ED SRCR2,  0x00040000
+ED_AND PLLECR, 0xFFFFFFF7
+WAIT_MASK PLLECR, 0x00000800, 0x00000000
+LIST "set SBSC operational"
+ED HPBCTRL6, 0x00000001
+WAIT_MASK HPBCTRL6, 0x00000001, 0x00000001
+LIST "set SBSC operating frequency"
+ED FRQCRD, 0x00001414
+WAIT_MASK FRQCRD, 0x80000000, 0x00000000
+ED PLL3CR, 0x1D000000
+ED_OR PLLECR, 0x00000008
+WAIT_MASK PLLECR, 0x00000800, 0x00000800
+LIST "enable DLL oscillation in DDRPHY"
+ED_OR DLLCNT0A, 0x00000002
+LIST "wait >= 100 ns"
+ED SDGENCNTA, 0x00000005
+WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
+LIST "target LPDDR2 device settings"
+ED SDCR0A, 0xACC90159
+ED SDCR1A, 0x00010059
+ED SDWCRC0A, 0x50874114
+ED SDWCRC1A, 0x33199B37
+ED SDWCRC2A, 0x008F2313
+ED SDWCR00A, 0x31020707
+ED SDWCR01A, 0x0017040A
+ED SDWCR10A, 0x31020707
+ED SDWCR11A, 0x0017040A
+ED SDDRVCR0A, 0x055557ff
+ED SDWCR2A, 0x30000000
+LIST "drive CKE high"
+ED_OR SDPCRA, 0x00000080
+WAIT_MASK SDPCRA, 0x00000080, 0x00000080
+LIST "wait >= 200 us"
+ED SDGENCNTA, 0x00002710
+WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
+LIST "issue reset command to LPDDR2 device"
+ED SDMRACR0A, 0x0000003F
+ED SDMRA1, 0x00000000
+LIST "wait >= 10 (or 1) us (docs inconsistent)"
+ED SDGENCNTA, 0x000001F4
+WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
+LIST "MRW ZS initialization calibration command"
+ED SDMRACR0A, 0x0000FF0A
+ED SDMRA3, 0x00000000
+LIST "wait >= 1 us"
+ED SDGENCNTA, 0x00000032
+WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
+LIST "specify operating mode in LPDDR2"
+ED SDMRACR0A, 0x00002201
+ED SDMRA1, 0x00000000
+ED SDMRACR0A, 0x00000402
+ED SDMRA1, 0x00000000
+ED SDMRACR0A, 0x00000203
+ED SDMRA1, 0x00000000
+LIST "initialize DDR interface"
+ED SDMRA2, 0x00000000
+LIST "temperature sensor control"
+ED SDMRTMPCRA, 0x88800004
+ED SDMRTMPMSKA,0x00000004
+LIST "auto-refreshing control"
+ED RTCORA, 0xA55A0032
+ED RTCORHA, 0xA55A000C
+ED RTCSRA, 0xA55A2048
+ED_OR SDCR0A, 0x00000800
+ED_OR SDCR1A, 0x00000400
+LIST "auto ZQ calibration control"
+ED ZQCCRA, 0xFFF20000
+ED_OR DLLCNT0B, 0x00000002
+ED SDGENCNTB, 0x00000005
+WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
+ED SDCR0B, 0xACC90159
+ED SDCR1B, 0x00010059
+ED SDWCRC0B, 0x50874114
+ED SDWCRC1B, 0x33199B37
+ED SDWCRC2B, 0x008F2313
+ED SDWCR00B, 0x31020707
+ED SDWCR01B, 0x0017040A
+ED SDWCR10B, 0x31020707
+ED SDWCR11B, 0x0017040A
+ED SDDRVCR0B, 0x055557ff
+ED SDWCR2B, 0x30000000
+ED_OR SDPCRB, 0x00000080
+WAIT_MASK SDPCRB, 0x00000080, 0x00000080
+ED SDGENCNTB, 0x00002710
+WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
+ED SDMRACR0B, 0x0000003F
+LIST "upstream u-boot writes to SDMRA1A for both SBSC 1 and 2, which does"
+LIST "not seem to make a lot of sense..."
+ED SDMRB1, 0x00000000
+ED SDGENCNTB, 0x000001F4
+WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
+ED SDMRACR0B, 0x0000FF0A
+ED SDMRB3, 0x00000000
+ED SDGENCNTB, 0x00000032
+WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
+ED SDMRACR0B, 0x00002201
+ED SDMRB1, 0x00000000
+ED SDMRACR0B, 0x00000402
+ED SDMRB1, 0x00000000
+ED SDMRACR0B, 0x00000203
+ED SDMRB1, 0x00000000
+ED SDMRB2, 0x00000000
+ED SDMRTMPCRB, 0x88800004
+ED SDMRTMPMSKB, 0x00000004
+ED RTCORB,  0xA55A0032
+ED RTCORHB, 0xA55A000C
+ED RTCSRB,  0xA55A2048
+ED_OR SDCR0B, 0x00000800
+ED_OR SDCR1B, 0x00000400
+ED ZQCCRB, 0xFFF20000
+ED_OR SDPDCR0B, 0x00030000
+ED DPHYCNT1B, 0xA5390000
+ED DPHYCNT0B, 0x00001200
+ED DPHYCNT1B, 0x07CE0000
+ED DPHYCNT0B, 0x00001247
+WAIT_MASK DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000
+ED_AND SDPDCR0B, 0xFFFCFFFF
+ED FRQCRD, 0x00000B0B
+WAIT_MASK FRQCRD, 0x80000000, 0x00000000
+ED CPGXXCR4, 0xfffffffc
+LIST "Setup SCIF4 / workaround"
+EB PORT32CR, 0x12
+EB PORT33CR, 0x22
+EB PORT34CR, 0x12
+EB PORT35CR, 0x22
+EW 0xE6C80000, 0
+EB 0xE6C80004, 0x19
+EW 0xE6C80008, 0x0030
+EW 0xE6C80018, 0
+EW 0xE6C80030, 0x0014
+LIST "Magic to avoid hangs and corruption on DRAM writes."
+LIST "It has been observed that the system would most often hang while"
+LIST "decompressing the kernel, and if it didn't it would always write"
+LIST "a corrupt image to DRAM."
+LIST "This problem does not occur in u-boot, and the reason is that"
+LIST "u-boot performs an additional cache invalidation after setting up"
+LIST "the DRAM controller. Such an invalidation should not be necessary at"
+LIST "this point, and attempts at removing parts of the routine to arrive"
+LIST "at the minimal snippet of code necessary to avoid the DRAM stability"
+LIST "problem yielded the following:"
+MRC p15, 0, r0, c1, c0, 0
+MCR p15, 0, r0, c1, c0, 0
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rcar.h b/arch/arm/mach-shmobile/include/mach/pm-rcar.h
new file mode 100644
index 000000000000..ef3a1ef628f1
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/pm-rcar.h
@@ -0,0 +1,15 @@
+#ifndef PM_RCAR_H
+#define PM_RCAR_H
+struct rcar_sysc_ch {
+        unsigned long chan_offs;
+        unsigned int chan_bit;
+        unsigned int isr_bit;
+};
+int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch);
+int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch);
+bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch);
+void __iomem *rcar_sysc_init(phys_addr_t base);
+#endif /* PM_RCAR_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index b40e13631f6a..88eeceaf1088 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -3,6 +3,7 @@
 #include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
+#include <mach/pm-rcar.h>
 /* HPB-DMA slave IDs */
 enum {
@@ -11,18 +12,12 @@ enum {
        HPBDMA_SLAVE_SDHI0_RX,
 };
-struct r8a7779_pm_ch {
-        unsigned long chan_offs;
-        unsigned int chan_bit;
-        unsigned int isr_bit;
-};
 struct r8a7779_pm_domain {
        struct generic_pm_domain genpd;
-        struct r8a7779_pm_ch ch;
+        struct rcar_sysc_ch ch;
 };
-static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
+static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d)
 {
        return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
 }
@@ -41,8 +36,6 @@ extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
 extern void r8a7779_register_twd(void);
-extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
-extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
 #ifdef CONFIG_PM
 extern void __init r8a7779_init_pm_domains(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 5fbfa28b40b6..0b95babe84ba 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -3,10 +3,36 @@
 #include <mach/rcar-gen2.h>
+/* DMA slave IDs */
+enum {
+        RCAR_DMA_SLAVE_INVALID,
+        AUDIO_DMAC_SLAVE_SSI0_TX,
+        AUDIO_DMAC_SLAVE_SSI0_RX,
+        AUDIO_DMAC_SLAVE_SSI1_TX,
+        AUDIO_DMAC_SLAVE_SSI1_RX,
+        AUDIO_DMAC_SLAVE_SSI2_TX,
+        AUDIO_DMAC_SLAVE_SSI2_RX,
+        AUDIO_DMAC_SLAVE_SSI3_TX,
+        AUDIO_DMAC_SLAVE_SSI3_RX,
+        AUDIO_DMAC_SLAVE_SSI4_TX,
+        AUDIO_DMAC_SLAVE_SSI4_RX,
+        AUDIO_DMAC_SLAVE_SSI5_TX,
+        AUDIO_DMAC_SLAVE_SSI5_RX,
+        AUDIO_DMAC_SLAVE_SSI6_TX,
+        AUDIO_DMAC_SLAVE_SSI6_RX,
+        AUDIO_DMAC_SLAVE_SSI7_TX,
+        AUDIO_DMAC_SLAVE_SSI7_RX,
+        AUDIO_DMAC_SLAVE_SSI8_TX,
+        AUDIO_DMAC_SLAVE_SSI8_RX,
+        AUDIO_DMAC_SLAVE_SSI9_TX,
+        AUDIO_DMAC_SLAVE_SSI9_RX,
+};
 void r8a7790_add_standard_devices(void);
 void r8a7790_add_dt_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
+void r8a7790_pm_init(void);
 void r8a7790_init_early(void);
 extern struct smp_operations r8a7790_smp_ops;
diff --git a/arch/arm/mach-shmobile/include/mach/timex.h b/arch/arm/mach-shmobile/include/mach/timex.h
deleted file mode 100644
index ae0d8d825c23..000000000000
--- a/arch/arm/mach-shmobile/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_MACH_TIMEX_H
-#define __ASM_MACH_TIMEX_H
-#define CLOCK_TICK_RATE         1193180 /* unused i8253 PIT value */
-#endif /* __ASM_MACH_TIMEX_H */
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index c3c4669a2d72..727cc78ac8ec 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -12,6 +12,9 @@
 #ifdef CONFIG_MACH_MACKEREL
 #define MEMORY_START    0x40000000
 #include "mach/head-mackerel.txt"
+#elif defined(CONFIG_MACH_KZM9G) || defined(CONFIG_MACH_KZM9G_REFERENCE)
+#define MEMORY_START    0x43000000
+#include "mach/head-kzm9g.txt"
 #else
 #error "unsupported board."
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/zboot_macros.h b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
index aa6111fbc989..14fd3d538e9a 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot_macros.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
@@ -62,4 +62,47 @@
 2 :
 .endm
+/* loop until a given value has been read (with mask) */
+.macro WAIT_MASK, addr, data, cmp
+        LDR     r0, 2f
+        LDR     r1, 3f
+        LDR     r2, 4f
+1:
+        LDR     r3, [r0, #0]
+        AND     r3, r1, r3
+        CMP     r2, r3
+        BNE     1b
+        B       5f
+2:      .long   \addr
+3:      .long   \data
+4:      .long   \cmp
+5:
+.endm
+/* read 32-bit value from addr, "or" an immediate and write back */
+.macro ED_OR, addr, data
+        LDR r4, 1f
+        LDR r5, 2f
+        LDR r6, [r4]
+        ORR r5, r6, r5
+        STR r5, [r4]
+        B       3f
+1:      .long   \addr
+2:      .long   \data
+3:
+.endm
+/* read 32-bit value from addr, "and" an immediate and write back */
+.macro ED_AND, addr, data
+        LDR r4, 1f
+        LDR r5, 2f
+        LDR r6, [r4]
+        AND r5, r6, r5
+        STR r5, [r4]
+        B       3f
+1:      .long \addr
+2:      .long \data
+3:
+.endm
 #endif /* __ZBOOT_MACRO_H */
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 1da5a72d9642..8cb641c00fdb 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -75,8 +75,7 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit)
        apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
        apmu_cpus[cpu].bit = bit;
-        pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit,
+        pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
-                 res->start, resource_size(res));
 }
 static struct {
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index d50a8e9b94a4..d6fe189b2df6 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -20,132 +20,22 @@
 #include <linux/console.h>
 #include <asm/io.h>
 #include <mach/common.h>
+#include <mach/pm-rcar.h>
 #include <mach/r8a7779.h>
-static void __iomem *r8a7779_sysc_base;
 /* SYSC */
-#define SYSCSR 0x00
-#define SYSCISR 0x04
-#define SYSCISCR 0x08
 #define SYSCIER 0x0c
 #define SYSCIMR 0x10
-#define PWRSR0 0x40
-#define PWRSR1 0x80
-#define PWRSR2 0xc0
-#define PWRSR3 0x100
-#define PWRSR4 0x140
-#define PWRSR_OFFS 0x00
-#define PWROFFCR_OFFS 0x04
-#define PWRONCR_OFFS 0x0c
-#define PWRER_OFFS 0x14
-#define SYSCSR_RETRIES 100
-#define SYSCSR_DELAY_US 1
-#define SYSCISR_RETRIES 1000
-#define SYSCISR_DELAY_US 1
 #if defined(CONFIG_PM) || defined(CONFIG_SMP)
-static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */
-static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
-                                   int sr_bit, int reg_offs)
-{
-        int k;
-        for (k = 0; k < SYSCSR_RETRIES; k++) {
-                if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit))
-                        break;
-                udelay(SYSCSR_DELAY_US);
-        }
-        if (k == SYSCSR_RETRIES)
-                return -EAGAIN;
-        iowrite32(1 << r8a7779_ch->chan_bit,
-                  r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs);
-        return 0;
-}
-static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch)
-{
-        return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS);
-}
-static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch)
-{
-        return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS);
-}
-static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
-                               int (*on_off_fn)(struct r8a7779_pm_ch *))
-{
-        unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
-        unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
-        unsigned int status;
-        unsigned long flags;
-        int ret = 0;
-        int k;
-        spin_lock_irqsave(&r8a7779_sysc_lock, flags);
-        iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
-        do {
-                ret = on_off_fn(r8a7779_ch);
-                if (ret)
-                        goto out;
-                status = ioread32(r8a7779_sysc_base +
-                                  r8a7779_ch->chan_offs + PWRER_OFFS);
-        } while (status & chan_mask);
-        for (k = 0; k < SYSCISR_RETRIES; k++) {
-                if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask)
-                        break;
-                udelay(SYSCISR_DELAY_US);
-        }
-        if (k == SYSCISR_RETRIES)
-                ret = -EIO;
-        iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
- out:
-        spin_unlock_irqrestore(&r8a7779_sysc_lock, flags);
-        pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
-                 r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
-                 ioread32(r8a7779_sysc_base + PWRSR1),
-                 ioread32(r8a7779_sysc_base + PWRSR2),
-                 ioread32(r8a7779_sysc_base + PWRSR3),
-                 ioread32(r8a7779_sysc_base + PWRSR4), ret);
-        return ret;
-}
-int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
-{
-        return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
-}
-int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
-{
-        return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
-}
 static void __init r8a7779_sysc_init(void)
 {
-        r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE);
+        void __iomem *base = rcar_sysc_init(0xffd85000);
-        if (!r8a7779_sysc_base)
-                panic("unable to ioremap r8a7779 SYSC hardware block\n");
        /* enable all interrupt sources, but do not use interrupt handler */
-        iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER);
+        iowrite32(0x0131000e, base + SYSCIER);
-        iowrite32(0, r8a7779_sysc_base + SYSCIMR);
+        iowrite32(0, base + SYSCIMR);
 }
 #else /* CONFIG_PM || CONFIG_SMP */
@@ -158,24 +48,17 @@ static inline void r8a7779_sysc_init(void) {}
 static int pd_power_down(struct generic_pm_domain *genpd)
 {
-        return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
+        return rcar_sysc_power_down(to_r8a7779_ch(genpd));
 }
 static int pd_power_up(struct generic_pm_domain *genpd)
 {
-        return r8a7779_sysc_power_up(to_r8a7779_ch(genpd));
+        return rcar_sysc_power_up(to_r8a7779_ch(genpd));
 }
 static bool pd_is_off(struct generic_pm_domain *genpd)
 {
-        struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd);
+        return rcar_sysc_power_is_off(to_r8a7779_ch(genpd));
-        unsigned int st;
-        st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS);
-        if (st & (1 << r8a7779_ch->chan_bit))
-                return true;
-        return false;
 }
 static bool pd_active_wakeup(struct device *dev)
diff --git a/arch/arm/mach-shmobile/pm-r8a7790.c b/arch/arm/mach-shmobile/pm-r8a7790.c
new file mode 100644
index 000000000000..fc82839e2c2a
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-r8a7790.c
@@ -0,0 +1,45 @@
+/*
+ * r8a7790 Power management support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include <mach/pm-rcar.h>
+#include <mach/r8a7790.h>
+/* SYSC */
+#define SYSCIER 0x0c
+#define SYSCIMR 0x10
+#if defined(CONFIG_SMP)
+static void __init r8a7790_sysc_init(void)
+{
+        void __iomem *base = rcar_sysc_init(0xe6180000);
+        /* enable all interrupt sources, but do not use interrupt handler */
+        iowrite32(0x0131000e, base + SYSCIER);
+        iowrite32(0, base + SYSCIMR);
+}
+#else /* CONFIG_SMP */
+static inline void r8a7790_sysc_init(void) {}
+#endif /* CONFIG_SMP */
+void __init r8a7790_pm_init(void)
+{
+        static int once;
+        if (!once++)
+                r8a7790_sysc_init();
+}
diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c
new file mode 100644
index 000000000000..1f465a12d1b1
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-rcar.c
@@ -0,0 +1,141 @@
+/*
+ * R-Car SYSC Power management support
+ *
+ * Copyright (C) 2014  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+#include <mach/pm-rcar.h>
+/* SYSC */
+#define SYSCSR 0x00
+#define SYSCISR 0x04
+#define SYSCISCR 0x08
+#define PWRSR_OFFS 0x00
+#define PWROFFCR_OFFS 0x04
+#define PWRONCR_OFFS 0x0c
+#define PWRER_OFFS 0x14
+#define SYSCSR_RETRIES 100
+#define SYSCSR_DELAY_US 1
+#define SYSCISR_RETRIES 1000
+#define SYSCISR_DELAY_US 1
+#if defined(CONFIG_PM) || defined(CONFIG_SMP)
+static void __iomem *rcar_sysc_base;
+static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
+static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch,
+                                int sr_bit, int reg_offs)
+{
+        int k;
+        for (k = 0; k < SYSCSR_RETRIES; k++) {
+                if (ioread32(rcar_sysc_base + SYSCSR) & (1 << sr_bit))
+                        break;
+                udelay(SYSCSR_DELAY_US);
+        }
+        if (k == SYSCSR_RETRIES)
+                return -EAGAIN;
+        iowrite32(1 << sysc_ch->chan_bit,
+                  rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
+        return 0;
+}
+static int rcar_sysc_pwr_off(struct rcar_sysc_ch *sysc_ch)
+{
+        return rcar_sysc_pwr_on_off(sysc_ch, 0, PWROFFCR_OFFS);
+}
+static int rcar_sysc_pwr_on(struct rcar_sysc_ch *sysc_ch)
+{
+        return rcar_sysc_pwr_on_off(sysc_ch, 1, PWRONCR_OFFS);
+}
+static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch,
+                            int (*on_off_fn)(struct rcar_sysc_ch *))
+{
+        unsigned int isr_mask = 1 << sysc_ch->isr_bit;
+        unsigned int chan_mask = 1 << sysc_ch->chan_bit;
+        unsigned int status;
+        unsigned long flags;
+        int ret = 0;
+        int k;
+        spin_lock_irqsave(&rcar_sysc_lock, flags);
+        iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
+        do {
+                ret = on_off_fn(sysc_ch);
+                if (ret)
+                        goto out;
+                status = ioread32(rcar_sysc_base +
+                                  sysc_ch->chan_offs + PWRER_OFFS);
+        } while (status & chan_mask);
+        for (k = 0; k < SYSCISR_RETRIES; k++) {
+                if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
+                        break;
+                udelay(SYSCISR_DELAY_US);
+        }
+        if (k == SYSCISR_RETRIES)
+                ret = -EIO;
+        iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
+ out:
+        spin_unlock_irqrestore(&rcar_sysc_lock, flags);
+        pr_debug("sysc power domain %d: %08x -> %d\n",
+                 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
+        return ret;
+}
+int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch)
+{
+        return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_off);
+}
+int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch)
+{
+        return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_on);
+}
+bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch)
+{
+        unsigned int st;
+        st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
+        if (st & (1 << sysc_ch->chan_bit))
+                return true;
+        return false;
+}
+void __iomem *rcar_sysc_init(phys_addr_t base)
+{
+        rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
+        if (!rcar_sysc_base)
+                panic("unable to ioremap R-Car SYSC hardware block\n");
+        return rcar_sysc_base;
+}
+#endif /* CONFIG_PM || CONFIG_SMP */
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index c8f2a1a69a52..c71d667007b8 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -58,7 +58,7 @@ static void __init emev2_add_standard_devices_dt(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-static const char *emev2_boards_compat_dt[] __initdata = {
+static const char *emev2_boards_compat_dt[] __initconst = {
        "renesas,emev2",
        NULL,
 };
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 6ab37aa1e919..c4616f0698c6 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -24,12 +24,100 @@
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
 #include <mach/common.h>
+#include <mach/dma-register.h>
 #include <mach/irqs.h>
 #include <mach/r8a7790.h>
 #include <asm/mach/arch.h>
+/* Audio-DMAC */
+#define AUDIO_DMAC_SLAVE(_id, _addr, t, r)                      \
+{                                                               \
+        .slave_id       = AUDIO_DMAC_SLAVE_## _id ##_TX,        \
+        .addr           = _addr + 0x8,                          \
+        .chcr           = CHCR_TX(XMIT_SZ_32BIT),               \
+        .mid_rid        = t,                                    \
+}, {                                                            \
+        .slave_id       = AUDIO_DMAC_SLAVE_## _id ##_RX,        \
+        .addr           = _addr + 0xc,                          \
+        .chcr           = CHCR_RX(XMIT_SZ_32BIT),               \
+        .mid_rid        = r,                                    \
+}
+static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
+        AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
+        AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
+        AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
+        AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
+        AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
+        AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
+        AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
+        AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
+        AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
+        AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
+};
+#define DMAE_CHANNEL(a, b)                      \
+{                                               \
+        .offset         = (a) - 0x20,           \
+        .dmars          = (a) - 0x20 + 0x40,    \
+        .chclr_bit      = (b),                  \
+        .chclr_offset   = 0x80 - 0x20,          \
+}
+static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
+        DMAE_CHANNEL(0x8000, 0),
+        DMAE_CHANNEL(0x8080, 1),
+        DMAE_CHANNEL(0x8100, 2),
+        DMAE_CHANNEL(0x8180, 3),
+        DMAE_CHANNEL(0x8200, 4),
+        DMAE_CHANNEL(0x8280, 5),
+        DMAE_CHANNEL(0x8300, 6),
+        DMAE_CHANNEL(0x8380, 7),
+        DMAE_CHANNEL(0x8400, 8),
+        DMAE_CHANNEL(0x8480, 9),
+        DMAE_CHANNEL(0x8500, 10),
+        DMAE_CHANNEL(0x8580, 11),
+        DMAE_CHANNEL(0x8600, 12),
+};
+static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
+        .slave          = r8a7790_audio_dmac_slaves,
+        .slave_num      = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
+        .channel        = r8a7790_audio_dmac_channels,
+        .channel_num    = ARRAY_SIZE(r8a7790_audio_dmac_channels),
+        .ts_low_shift   = TS_LOW_SHIFT,
+        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
+        .ts_high_shift  = TS_HI_SHIFT,
+        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
+        .ts_shift       = dma_ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
+        .dmaor_init     = DMAOR_DME,
+        .chclr_present  = 1,
+        .chclr_bitwise  = 1,
+};
+static struct resource r8a7790_audio_dmac_resources[] = {
+        /* Channel registers and DMAOR for low */
+        DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
+        DEFINE_RES_IRQ(gic_spi(346)),
+        DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
+        /* Channel registers and DMAOR for hi */
+        DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
+        DEFINE_RES_IRQ(gic_spi(347)),
+        DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
+};
+#define r8a7790_register_audio_dmac(id)                         \
+        platform_device_register_resndata(                      \
+                &platform_bus, "sh-dma-engine", id,             \
+                &r8a7790_audio_dmac_resources[id * 3],  3,      \
+                &r8a7790_audio_dmac_platform_data,              \
+                sizeof(r8a7790_audio_dmac_platform_data))
 static const struct resource pfc_resources[] __initconst = {
        DEFINE_RES_MEM(0xe6060000, 0x250),
 };
@@ -101,6 +189,8 @@ void __init r8a7790_pinmux_init(void)
        r8a7790_register_i2c(1);
        r8a7790_register_i2c(2);
        r8a7790_register_i2c(3);
+        r8a7790_register_audio_dmac(0);
+        r8a7790_register_audio_dmac(1);
 }
 #define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq)         \
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 69ccc6c6fd33..10604480f325 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -28,7 +28,7 @@
 #define MODEMR 0xe6160060
-u32 __init rcar_gen2_read_mode_pins(void)
+u32 rcar_gen2_read_mode_pins(void)
 {
        void __iomem *modemr = ioremap_nocache(MODEMR, 4);
        u32 mode;
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 627c1f0d9478..e7a3201473d0 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <mach/common.h>
+#include <mach/pm-rcar.h>
 #include <mach/r8a7779.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -33,25 +34,25 @@
 #define AVECR IOMEM(0xfe700040)
 #define R8A7779_SCU_BASE 0xf0000000
-static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
+static struct rcar_sysc_ch r8a7779_ch_cpu1 = {
        .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
        .chan_bit = 1, /* ARM1 */
        .isr_bit = 1, /* ARM1 */
 };
-static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
+static struct rcar_sysc_ch r8a7779_ch_cpu2 = {
        .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
        .chan_bit = 2, /* ARM2 */
        .isr_bit = 2, /* ARM2 */
 };
-static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
+static struct rcar_sysc_ch r8a7779_ch_cpu3 = {
        .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
        .chan_bit = 3, /* ARM3 */
        .isr_bit = 3, /* ARM3 */
 };
-static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
+static struct rcar_sysc_ch *r8a7779_ch_cpu[4] = {
        [1] = &r8a7779_ch_cpu1,
        [2] = &r8a7779_ch_cpu2,
        [3] = &r8a7779_ch_cpu3,
@@ -67,7 +68,7 @@ void __init r8a7779_register_twd(void)
 static int r8a7779_platform_cpu_kill(unsigned int cpu)
 {
-        struct r8a7779_pm_ch *ch = NULL;
+        struct rcar_sysc_ch *ch = NULL;
        int ret = -EIO;
        cpu = cpu_logical_map(cpu);
@@ -76,14 +77,14 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
                ch = r8a7779_ch_cpu[cpu];
        if (ch)
-                ret = r8a7779_sysc_power_down(ch);
+                ret = rcar_sysc_power_down(ch);
        return ret ? ret : 1;
 }
 static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        struct r8a7779_pm_ch *ch = NULL;
+        struct rcar_sysc_ch *ch = NULL;
        unsigned int lcpu = cpu_logical_map(cpu);
        int ret;
@@ -91,7 +92,7 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
                ch = r8a7779_ch_cpu[lcpu];
        if (ch)
-                ret = r8a7779_sysc_power_up(ch);
+                ret = rcar_sysc_power_up(ch);
        else
                ret = -EIO;
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index 015e2753de1f..591052799e8f 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -19,6 +19,8 @@
 #include <linux/io.h>
 #include <asm/smp_plat.h>
 #include <mach/common.h>
+#include <mach/pm-rcar.h>
+#include <mach/r8a7790.h>
 #define RST             0xe6160000
 #define CA15BAR         0x0020
@@ -27,6 +29,16 @@
 #define CA7RESCNT       0x0044
 #define MERAM           0xe8080000
+static struct rcar_sysc_ch r8a7790_ca15_scu = {
+        .chan_offs = 0x180, /* PWRSR5 .. PWRER5 */
+        .isr_bit = 12, /* CA15-SCU */
+};
+static struct rcar_sysc_ch r8a7790_ca7_scu = {
+        .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
+        .isr_bit = 21, /* CA7-SCU */
+};
 static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
 {
        void __iomem *p;
@@ -54,6 +66,11 @@ static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
        writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000,
                       p + CA7RESCNT);
        iounmap(p);
+        /* turn on power to SCU */
+        r8a7790_pm_init();
+        rcar_sysc_power_up(&r8a7790_ca15_scu);
+        rcar_sysc_power_up(&r8a7790_ca7_scu);
 }
 struct smp_operations r8a7790_smp_ops __initdata = {
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index aee77f06f887..b5f8d75d51a0 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,17 +1,10 @@
 config ARCH_SOCFPGA
        bool "Altera SOCFPGA family" if ARCH_MULTI_V7
-        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARM_AMBA
        select ARM_GIC
        select CACHE_L2X0
-        select COMMON_CLK
-        select CPU_V7
        select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
        select GPIO_PL061 if GPIOLIB
        select HAVE_ARM_SCU
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
        select MFD_SYSCON
-        select SPARSE_IRQ
-        select USE_OF
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index dd0d49cdbe09..d86231e11b34 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -29,7 +29,6 @@
 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
 void __iomem *rst_manager_base_addr;
-void __iomem *clk_mgr_base_addr;
 unsigned long cpu1start_addr;
 static struct map_desc scu_io_desc __initdata = {
@@ -78,9 +77,6 @@ void __init socfpga_sysmgr_init(void)
        np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
        rst_manager_base_addr = of_iomap(np, 0);
-        np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
-        clk_mgr_base_addr = of_iomap(np, 0);
 }
 static void __init socfpga_init_irq(void)
@@ -106,7 +102,6 @@ static void __init socfpga_cyclone5_init(void)
 {
        l2x0_of_init(0, ~0UL);
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-        socfpga_init_clocks();
 }
 static const char *altera_dt_match[] = {
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e64d9a..0786249b2832 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -8,8 +8,6 @@ menuconfig PLAT_SPEAR
        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
 if PLAT_SPEAR
@@ -18,14 +16,10 @@ config ARCH_SPEAR13XX
        depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
        select ARCH_HAS_CPUFREQ
        select ARM_GIC
-        select CPU_V7
        select GPIO_SPEAR_SPICS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
-        select USE_OF
        help
          Supports for ARM's SPEAR13XX family
@@ -50,9 +44,7 @@ config ARCH_SPEAR3XX
        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
        depends on !ARCH_SPEAR13XX
        select ARM_VIC
-        select CPU_ARM926T
        select PINCTRL
-        select USE_OF
        help
          Supports for ARM's SPEAR3XX family
@@ -83,16 +75,14 @@ config ARCH_SPEAR6XX
        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
        depends on !ARCH_SPEAR13XX
        select ARM_VIC
-        select CPU_ARM926T
        help
          Supports for ARM's SPEAR6XX family
 config MACH_SPEAR600
        def_bool y
        depends on ARCH_SPEAR6XX
-        select USE_OF
        help
-          Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig"
+          Supports ST SPEAr600 boards configured via the device-tree
 config ARCH_SPEAR_AUTO
        def_bool PLAT_SPEAR_SINGLE
diff --git a/arch/arm/mach-spear/include/mach/timex.h b/arch/arm/mach-spear/include/mach/timex.h
deleted file mode 100644
index ef95e5b780bd..000000000000
--- a/arch/arm/mach-spear/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/timex.h
- *
- * SPEAr platform specific timex definitions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __PLAT_TIMEX_H
-#define __PLAT_TIMEX_H
-#define CLOCK_TICK_RATE                 48000000
-#endif /* __PLAT_TIMEX_H */
diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 7ad003001ab7..824b12a56a42 100644
--- a/arch/arm/mach-spear/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -28,6 +28,7 @@
 static void __init spear1310_dt_init(void)
 {
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        platform_device_register_simple("spear-cpufreq", -1, NULL, 0);
 }
 static const char * const spear1310_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb683424729..7b6bff7154e1 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -143,6 +143,7 @@ static void __init spear1340_dt_init(void)
 {
        of_platform_populate(NULL, of_default_bus_match_table,
                        spear1340_auxdata_lookup, NULL);
+        platform_device_register_simple("spear-cpufreq", -1, NULL, 0);
 }
 static const char * const spear1340_dt_board_compat[] = {
diff --git a/arch/arm/mach-spear/time.c b/arch/arm/mach-spear/time.c
index d449673e40f7..218ba5b67d92 100644
--- a/arch/arm/mach-spear/time.c
+++ b/arch/arm/mach-spear/time.c
@@ -172,7 +172,7 @@ static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
 static struct irqaction spear_timer_irq = {
        .name = "timer",
-        .flags = IRQF_DISABLED | IRQF_TIMER,
+        .flags = IRQF_TIMER,
        .handler = spear_timer_interrupt
 };
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index d71654bc8d54..abf9ee9bbc3f 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -1,14 +1,11 @@
 menuconfig ARCH_STI
        bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
-        select GENERIC_CLOCKEVENTS
-        select CLKDEV_LOOKUP
        select ARM_GIC
        select ARM_GLOBAL_TIMER
        select PINCTRL
        select PINCTRL_ST
        select MFD_SYSCON
-        select MIGHT_HAVE_CACHE_L2X0
+        select ARCH_HAS_RESET_CONTROLLER
-        select HAVE_SMP
        select HAVE_ARM_SCU if SMP
        select ARCH_REQUIRE_GPIOLIB
        select ARM_ERRATA_754322
@@ -28,6 +25,7 @@ if ARCH_STI
 config SOC_STIH415
        bool "STiH415 STMicroelectronics Consumer Electronics family"
        default y
+        select STIH415_RESET
        help
          This enables support for STMicroelectronics Digital Consumer
          Electronics family StiH415 parts, primarily targeted at set-top-box
@@ -37,6 +35,7 @@ config SOC_STIH415
 config SOC_STIH416
        bool "STiH416 STMicroelectronics Consumer Electronics family"
        default y
+        select STIH416_RESET
        help
          This enables support for STMicroelectronics Digital Consumer
          Electronics family StiH416 parts, primarily targeted at set-top-box
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b9d6cad8669b..b57d7d53b9d3 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -5,14 +5,10 @@ config ARCH_SUNXI
        select ARM_GIC
        select ARM_PSCI
        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select GENERIC_IRQ_CHIP
-        select HAVE_SMP
+        select HAVE_ARM_ARCH_TIMER
        select PINCTRL
        select PINCTRL_SUNXI
        select RESET_CONTROLLER
-        select SPARSE_IRQ
        select SUN4I_TIMER
        select SUN5I_HSTIMER
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index d9397202d6ec..27b168f121a1 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,2 +1,2 @@
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
deleted file mode 100644
index a10d494fb37b..000000000000
--- a/arch/arm/mach-sunxi/headsmp.S
+++ /dev/null
@@ -1,9 +0,0 @@
-#include <linux/linkage.h>
-#include <linux/init.h>
-        .section ".text.head", "ax"
-ENTRY(sun6i_secondary_startup)
-        msr     cpsr_fsxc, #0xd3
-        b       secondary_startup
-ENDPROC(sun6i_secondary_startup)
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index 7b141d8342a1..0c7dbce033cc 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -82,7 +82,7 @@ static int sun6i_smp_boot_secondary(unsigned int cpu,
        spin_lock(&cpu_lock);
        /* Set CPU boot address */
-        writel(virt_to_phys(sun6i_secondary_startup),
+        writel(virt_to_phys(secondary_startup),
               cpucfg_membase + CPUCFG_PRIVATE0_REG);
        /* Assert the CPU core in reset */
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index aeea6ceea725..460b5a4962ef 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -94,8 +94,8 @@ static void sun6i_restart(enum reboot_mode mode, const char *cmd)
 }
 static struct of_device_id sunxi_restart_ids[] = {
-        { .compatible = "allwinner,sun4i-wdt" },
+        { .compatible = "allwinner,sun4i-a10-wdt" },
-        { .compatible = "allwinner,sun6i-wdt" },
+        { .compatible = "allwinner,sun6i-a31-wdt" },
        { /*sentinel*/ }
 };
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index b1232d8be6f5..92d660f9610f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -5,24 +5,15 @@ config ARCH_TEGRA
        select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
        select ARM_GIC
        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
        select MIGHT_HAVE_PCI
        select PINCTRL
        select ARCH_HAS_RESET_CONTROLLER
        select RESET_CONTROLLER
        select SOC_BUS
-        select SPARSE_IRQ
-        select USB_ARCH_HAS_EHCI if USB_SUPPORT
        select USB_ULPI if USB_PHY
        select USB_ULPI_VIEWPORT if USB_PHY
-        select USE_OF
        help
          This enables support for NVIDIA Tegra based systems.
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 019bb1758662..6fbfbb77dcd9 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -14,7 +14,6 @@ obj-y					+= sleep.o
 obj-y                                   += tegra.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pm-tegra20.o
 ifeq ($(CONFIG_CPU_IDLE),y)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index e0b87300243d..b5fb7c110c64 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -19,6 +19,7 @@
 #include <linux/cpuidle.h>
 #include <linux/cpu_pm.h>
 #include <linux/clockchips.h>
+#include <asm/firmware.h>
 #include <asm/cpuidle.h>
 #include <asm/suspend.h>
@@ -45,7 +46,11 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
-        cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+        call_firmware_op(prepare_idle);
+        /* Do suspend by ourselves if the firmware does not implement it */
+        if (call_firmware_op(do_idle) == -ENOSYS)
+                cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index eb72ae709124..929d1046e2b4 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -114,7 +114,7 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
                /* Wait for the power to come up. */
                timeout = jiffies + msecs_to_jiffies(100);
-                while (tegra_pmc_cpu_is_powered(cpu)) {
+                while (!tegra_pmc_cpu_is_powered(cpu)) {
                        if (time_after(jiffies, timeout))
                                return -ETIMEDOUT;
                        udelay(10);
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 3d0c537d9b94..4cefc5cd6bed 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -484,6 +484,7 @@ int tegra_io_rail_power_on(int id)
        return 0;
 }
+EXPORT_SYMBOL(tegra_io_rail_power_on);
 int tegra_io_rail_power_off(int id)
 {
@@ -511,3 +512,4 @@ int tegra_io_rail_power_off(int id)
        return 0;
 }
+EXPORT_SYMBOL(tegra_io_rail_power_off);
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
deleted file mode 100644
index 3ae4a7f1a2fb..000000000000
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * Copyright (C) 2011 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/tegra_emc.h>
-#include "tegra2_emc.h"
-#include "fuse.h"
-#ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
-static bool emc_enable = true;
-#else
-static bool emc_enable;
-#endif
-module_param(emc_enable, bool, 0644);
-static struct platform_device *emc_pdev;
-static void __iomem *emc_regbase;
-static inline void emc_writel(u32 val, unsigned long addr)
-{
-        writel(val, emc_regbase + addr);
-}
-static inline u32 emc_readl(unsigned long addr)
-{
-        return readl(emc_regbase + addr);
-}
-static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
-        0x2c,   /* RC */
-        0x30,   /* RFC */
-        0x34,   /* RAS */
-        0x38,   /* RP */
-        0x3c,   /* R2W */
-        0x40,   /* W2R */
-        0x44,   /* R2P */
-        0x48,   /* W2P */
-        0x4c,   /* RD_RCD */
-        0x50,   /* WR_RCD */
-        0x54,   /* RRD */
-        0x58,   /* REXT */
-        0x5c,   /* WDV */
-        0x60,   /* QUSE */
-        0x64,   /* QRST */
-        0x68,   /* QSAFE */
-        0x6c,   /* RDV */
-        0x70,   /* REFRESH */
-        0x74,   /* BURST_REFRESH_NUM */
-        0x78,   /* PDEX2WR */
-        0x7c,   /* PDEX2RD */
-        0x80,   /* PCHG2PDEN */
-        0x84,   /* ACT2PDEN */
-        0x88,   /* AR2PDEN */
-        0x8c,   /* RW2PDEN */
-        0x90,   /* TXSR */
-        0x94,   /* TCKE */
-        0x98,   /* TFAW */
-        0x9c,   /* TRPAB */
-        0xa0,   /* TCLKSTABLE */
-        0xa4,   /* TCLKSTOP */
-        0xa8,   /* TREFBW */
-        0xac,   /* QUSE_EXTRA */
-        0x114,  /* FBIO_CFG6 */
-        0xb0,   /* ODT_WRITE */
-        0xb4,   /* ODT_READ */
-        0x104,  /* FBIO_CFG5 */
-        0x2bc,  /* CFG_DIG_DLL */
-        0x2c0,  /* DLL_XFORM_DQS */
-        0x2c4,  /* DLL_XFORM_QUSE */
-        0x2e0,  /* ZCAL_REF_CNT */
-        0x2e4,  /* ZCAL_WAIT_CNT */
-        0x2a8,  /* AUTO_CAL_INTERVAL */
-        0x2d0,  /* CFG_CLKTRIM_0 */
-        0x2d4,  /* CFG_CLKTRIM_1 */
-        0x2d8,  /* CFG_CLKTRIM_2 */
-};
-/* Select the closest EMC rate that is higher than the requested rate */
-long tegra_emc_round_rate(unsigned long rate)
-{
-        struct tegra_emc_pdata *pdata;
-        int i;
-        int best = -1;
-        unsigned long distance = ULONG_MAX;
-        if (!emc_pdev)
-                return -EINVAL;
-        pdata = emc_pdev->dev.platform_data;
-        pr_debug("%s: %lu\n", __func__, rate);
-        /*
-         * The EMC clock rate is twice the bus rate, and the bus rate is
-         * measured in kHz
-         */
-        rate = rate / 2 / 1000;
-        for (i = 0; i < pdata->num_tables; i++) {
-                if (pdata->tables[i].rate >= rate &&
-                    (pdata->tables[i].rate - rate) < distance) {
-                        distance = pdata->tables[i].rate - rate;
-                        best = i;
-                }
-        }
-        if (best < 0)
-                return -EINVAL;
-        pr_debug("%s: using %lu\n", __func__, pdata->tables[best].rate);
-        return pdata->tables[best].rate * 2 * 1000;
-}
-/*
- * The EMC registers have shadow registers.  When the EMC clock is updated
- * in the clock controller, the shadow registers are copied to the active
- * registers, allowing glitchless memory bus frequency changes.
- * This function updates the shadow registers for a new clock frequency,
- * and relies on the clock lock on the emc clock to avoid races between
- * multiple frequency changes
- */
-int tegra_emc_set_rate(unsigned long rate)
-{
-        struct tegra_emc_pdata *pdata;
-        int i;
-        int j;
-        if (!emc_pdev)
-                return -EINVAL;
-        pdata = emc_pdev->dev.platform_data;
-        /*
-         * The EMC clock rate is twice the bus rate, and the bus rate is
-         * measured in kHz
-         */
-        rate = rate / 2 / 1000;
-        for (i = 0; i < pdata->num_tables; i++)
-                if (pdata->tables[i].rate == rate)
-                        break;
-        if (i >= pdata->num_tables)
-                return -EINVAL;
-        pr_debug("%s: setting to %lu\n", __func__, rate);
-        for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
-                emc_writel(pdata->tables[i].regs[j], emc_reg_addr[j]);
-        emc_readl(pdata->tables[i].regs[TEGRA_EMC_NUM_REGS - 1]);
-        return 0;
-}
-#ifdef CONFIG_OF
-static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
-{
-        struct device_node *iter;
-        u32 reg;
-        for_each_child_of_node(np, iter) {
-                if (of_property_read_u32(iter, "nvidia,ram-code", &reg))
-                        continue;
-                if (reg == tegra_bct_strapping)
-                        return of_node_get(iter);
-        }
-        return NULL;
-}
-static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
-                struct platform_device *pdev)
-{
-        struct device_node *np = pdev->dev.of_node;
-        struct device_node *tnp, *iter;
-        struct tegra_emc_pdata *pdata;
-        int ret, i, num_tables;
-        if (!np)
-                return NULL;
-        if (of_find_property(np, "nvidia,use-ram-code", NULL)) {
-                tnp = tegra_emc_ramcode_devnode(np);
-                if (!tnp)
-                        dev_warn(&pdev->dev,
-                                 "can't find emc table for ram-code 0x%02x\n",
-                                 tegra_bct_strapping);
-        } else
-                tnp = of_node_get(np);
-        if (!tnp)
-                return NULL;
-        num_tables = 0;
-        for_each_child_of_node(tnp, iter)
-                if (of_device_is_compatible(iter, "nvidia,tegra20-emc-table"))
-                        num_tables++;
-        if (!num_tables) {
-                pdata = NULL;
-                goto out;
-        }
-        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
-        pdata->tables = devm_kzalloc(&pdev->dev,
-                                     sizeof(*pdata->tables) * num_tables,
-                                     GFP_KERNEL);
-        i = 0;
-        for_each_child_of_node(tnp, iter) {
-                u32 prop;
-                ret = of_property_read_u32(iter, "clock-frequency", &prop);
-                if (ret) {
-                        dev_err(&pdev->dev, "no clock-frequency in %s\n",
-                                iter->full_name);
-                        continue;
-                }
-                pdata->tables[i].rate = prop;
-                ret = of_property_read_u32_array(iter, "nvidia,emc-registers",
-                                                 pdata->tables[i].regs,
-                                                 TEGRA_EMC_NUM_REGS);
-                if (ret) {
-                        dev_err(&pdev->dev,
-                                "malformed emc-registers property in %s\n",
-                                iter->full_name);
-                        continue;
-                }
-                i++;
-        }
-        pdata->num_tables = i;
-out:
-        of_node_put(tnp);
-        return pdata;
-}
-#else
-static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
-                struct platform_device *pdev)
-{
-        return NULL;
-}
-#endif
-static struct tegra_emc_pdata *tegra_emc_fill_pdata(struct platform_device *pdev)
-{
-        struct clk *c = clk_get_sys(NULL, "emc");
-        struct tegra_emc_pdata *pdata;
-        unsigned long khz;
-        int i;
-        WARN_ON(pdev->dev.platform_data);
-        BUG_ON(IS_ERR(c));
-        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
-        pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables),
-                                     GFP_KERNEL);
-        pdata->tables[0].rate = clk_get_rate(c) / 2 / 1000;
-        for (i = 0; i < TEGRA_EMC_NUM_REGS; i++)
-                pdata->tables[0].regs[i] = emc_readl(emc_reg_addr[i]);
-        pdata->num_tables = 1;
-        khz = pdata->tables[0].rate;
-        dev_info(&pdev->dev, "no tables provided, using %ld kHz emc, "
-                 "%ld kHz mem\n", khz * 2, khz);
-        return pdata;
-}
-static int tegra_emc_probe(struct platform_device *pdev)
-{
-        struct tegra_emc_pdata *pdata;
-        struct resource *res;
-        if (!emc_enable) {
-                dev_err(&pdev->dev, "disabled per module parameter\n");
-                return -ENODEV;
-        }
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        emc_regbase = devm_ioremap_resource(&pdev->dev, res);
-        if (IS_ERR(emc_regbase))
-                return PTR_ERR(emc_regbase);
-        pdata = pdev->dev.platform_data;
-        if (!pdata)
-                pdata = tegra_emc_dt_parse_pdata(pdev);
-        if (!pdata)
-                pdata = tegra_emc_fill_pdata(pdev);
-        pdev->dev.platform_data = pdata;
-        emc_pdev = pdev;
-        return 0;
-}
-static struct of_device_id tegra_emc_of_match[] = {
-        { .compatible = "nvidia,tegra20-emc", },
-        { },
-};
-static struct platform_driver tegra_emc_driver = {
-        .driver         = {
-                .name   = "tegra-emc",
-                .owner  = THIS_MODULE,
-                .of_match_table = tegra_emc_of_match,
-        },
-        .probe          = tegra_emc_probe,
-};
-static int __init tegra_emc_init(void)
-{
-        return platform_driver_register(&tegra_emc_driver);
-}
-device_initcall(tegra_emc_init);
diff --git a/arch/arm/mach-tegra/tegra2_emc.h b/arch/arm/mach-tegra/tegra2_emc.h
deleted file mode 100644
index f61409b54cb7..000000000000
--- a/arch/arm/mach-tegra/tegra2_emc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2011 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_TEGRA2_EMC_H_
-#define __MACH_TEGRA_TEGRA2_EMC_H
-int tegra_emc_set_rate(unsigned long rate);
-long tegra_emc_round_rate(unsigned long rate);
-#endif
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 8e23071bd1b3..e3a96d7302e9 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -3,20 +3,14 @@ config ARCH_U300
        depends on MMU
        select ARCH_REQUIRE_GPIOLIB
        select ARM_AMBA
-        select ARM_PATCH_PHYS_VIRT
        select ARM_VIC
        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
        select HAVE_TCM
        select PINCTRL
        select PINCTRL_COH901
        select PINCTRL_U300
-        select SPARSE_IRQ
        select MFD_SYSCON
-        select USE_OF
        help
          Support for ST-Ericsson U300 series mobile platforms.
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 0034d2cd6973..b41a42da1505 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,13 +11,8 @@ config ARCH_U8500
        select ARM_GIC
        select CACHE_L2X0
        select CLKSRC_NOMADIK_MTU
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
        select PINCTRL_ABX500
        select PINCTRL_NOMADIK
@@ -73,11 +68,6 @@ config UX500_AUTO_PLATFORM
          a working kernel. If everything else is disabled, this
          automatically enables MACH_MOP500.
-config MACH_UX500_DT
-        bool "Generic U8500 support using device tree"
-        depends on MACH_MOP500
-        select USE_OF
 endmenu
 config UX500_DEBUG_UART
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index d05ba759da30..de544aabf292 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_CACHE_L2X0)	+= cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o
 obj-$(CONFIG_MACH_MOP500)       += board-mop500-sdi.o \
                                board-mop500-regulators.o \
-                                board-mop500-pins.o \
                                board-mop500-audio.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 9309ad4cbd09..b2a0899e7453 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -9,7 +9,6 @@
 #include <linux/gpio.h>
 #include <linux/platform_data/dma-ste-dma40.h>
-#include "irqs.h"
 #include <linux/platform_data/asoc-ux500-msp.h>
 #include "ste-dma40-db8500.h"
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
deleted file mode 100644
index f63619b69113..000000000000
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL) version 2
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/bug.h>
-#include <linux/string.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <asm/mach-types.h>
-#include "board-mop500.h"
-/* These simply sets bias for pins */
-#define BIAS(a,b) static unsigned long a[] = { b }
-BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
-BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
-BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
-#define AB8500_MUX_HOG(group, func) \
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
-#define AB8500_PIN_HOG(pin, conf) \
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
-#define AB8500_MUX_STATE(group, func, dev, state) \
-        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
-#define AB8500_PIN_STATE(pin, conf, dev, state) \
-        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
-#define AB8505_MUX_HOG(group, func) \
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
-#define AB8505_PIN_HOG(pin, conf) \
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
-#define AB8505_MUX_STATE(group, func, dev, state) \
-        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
-#define AB8505_PIN_STATE(pin, conf, dev, state) \
-        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
-static struct pinctrl_map __initdata ab8500_pinmap[] = {
-        /* Sysclkreq2 */
-        AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
-        AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
-        /* sysclkreq2 disable, mux in gpio configured in input pulldown */
-        AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
-        AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
-        /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
-        AB8500_MUX_HOG("gpio2_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO2_T9", in_pd),
-        /* Sysclkreq4 */
-        AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
-        AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
-        /* sysclkreq4 disable, mux in gpio configured in input pulldown */
-        AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
-        AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
-        /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
-        AB8500_MUX_HOG("gpio4_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO4_W2", in_pd),
-        /*
-         * pins 6,7,8 and 9 are muxed in YCBCR0123
-         * configured in INPUT PULL UP
-         */
-        AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
-        AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
-        AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
-        AB8500_PIN_HOG("GPIO8_W18", in_nopull),
-        AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
-        /*
-         * pins 10,11,12 and 13 are muxed in GPIO
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("gpio10_d_1", "gpio"),
-        AB8500_PIN_HOG("GPIO10_U17", in_pd),
-        AB8500_MUX_HOG("gpio11_d_1", "gpio"),
-        AB8500_PIN_HOG("GPIO11_AA18", in_pd),
-        AB8500_MUX_HOG("gpio12_d_1", "gpio"),
-        AB8500_PIN_HOG("GPIO12_U16", in_pd),
-        AB8500_MUX_HOG("gpio13_d_1", "gpio"),
-        AB8500_PIN_HOG("GPIO13_W17", in_pd),
-        /*
-         * pins 14,15 are muxed in PWM1 and PWM2
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
-        AB8500_PIN_HOG("GPIO14_F14", in_pd),
-        AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
-        AB8500_PIN_HOG("GPIO15_B17", in_pd),
-        /*
-         * pins 16 is muxed in GPIO
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("gpio16_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO14_F14", in_pd),
-        /*
-         * pins 17,18,19 and 20 are muxed in AUDIO interface 1
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("adi1_d_1", "adi1"),
-        AB8500_PIN_HOG("GPIO17_P5", in_pd),
-        AB8500_PIN_HOG("GPIO18_R5", in_pd),
-        AB8500_PIN_HOG("GPIO19_U5", in_pd),
-        AB8500_PIN_HOG("GPIO20_T5", in_pd),
-        /*
-         * pins 21,22 and 23 are muxed in USB UICC
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
-        AB8500_PIN_HOG("GPIO21_H19", in_pd),
-        AB8500_PIN_HOG("GPIO22_G20", in_pd),
-        AB8500_PIN_HOG("GPIO23_G19", in_pd),
-        /*
-         * pins 24,25 are muxed in GPIO
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("gpio24_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO24_T14", in_pd),
-        AB8500_MUX_HOG("gpio25_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO25_R16", in_pd),
-        /*
-         * pins 26 is muxed in GPIO
-         * configured in OUTPUT LOW
-         */
-        AB8500_MUX_HOG("gpio26_d_1", "gpio"),
-        AB8500_PIN_HOG("GPIO26_M16", out_lo),
-        /*
-         * pins 27,28 are muxed in DMIC12
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("dmic12_d_1", "dmic"),
-        AB8500_PIN_HOG("GPIO27_J6", in_pd),
-        AB8500_PIN_HOG("GPIO28_K6", in_pd),
-        /*
-         * pins 29,30 are muxed in DMIC34
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("dmic34_d_1", "dmic"),
-        AB8500_PIN_HOG("GPIO29_G6", in_pd),
-        AB8500_PIN_HOG("GPIO30_H6", in_pd),
-        /*
-         * pins 31,32 are muxed in DMIC56
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("dmic56_d_1", "dmic"),
-        AB8500_PIN_HOG("GPIO31_F5", in_pd),
-        AB8500_PIN_HOG("GPIO32_G5", in_pd),
-        /*
-         * pins 34 is muxed in EXTCPENA
-         * configured INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
-        AB8500_PIN_HOG("GPIO34_R17", in_pd),
-        /*
-         * pins 35 is muxed in GPIO
-         * configured in OUTPUT LOW
-         */
-        AB8500_MUX_HOG("gpio35_d_1", "gpio"),
-        AB8500_PIN_HOG("GPIO35_W15", in_pd),
-        /*
-         * pins 36,37,38 and 39 are muxed in GPIO
-         * configured in INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("gpio36_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO36_A17", in_pd),
-        AB8500_MUX_HOG("gpio37_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO37_E15", in_pd),
-        AB8500_MUX_HOG("gpio38_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO38_C17", in_pd),
-        AB8500_MUX_HOG("gpio39_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO39_E16", in_pd),
-        /*
-         * pins 40 and 41 are muxed in MODCSLSDA
-         * configured INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
-        AB8500_PIN_HOG("GPIO40_T19", in_pd),
-        AB8500_PIN_HOG("GPIO41_U19", in_pd),
-        /*
-         * pins 42 is muxed in GPIO
-         * configured INPUT PULL DOWN
-         */
-        AB8500_MUX_HOG("gpio42_a_1", "gpio"),
-        AB8500_PIN_HOG("GPIO42_U2", in_pd),
-};
-static struct pinctrl_map __initdata ab8505_pinmap[] = {
-        /* Sysclkreq2 */
-        AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
-        AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
-        /* sysclkreq2 disable, mux in gpio configured in input pulldown */
-        AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
-        AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
-        /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
-        AB8505_MUX_HOG("gpio2_a_1", "gpio"),
-        AB8505_PIN_HOG("GPIO2_R5", in_pd),
-        /* Sysclkreq4 */
-        AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
-        AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
-        /* sysclkreq4 disable, mux in gpio configured in input pulldown */
-        AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
-        AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
-        AB8505_MUX_HOG("gpio10_d_1", "gpio"),
-        AB8505_PIN_HOG("GPIO10_B16", in_pd),
-        AB8505_MUX_HOG("gpio11_d_1", "gpio"),
-        AB8505_PIN_HOG("GPIO11_B17", in_pd),
-        AB8505_MUX_HOG("gpio13_d_1", "gpio"),
-        AB8505_PIN_HOG("GPIO13_D17", in_nopull),
-        AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
-        AB8505_PIN_HOG("GPIO14_C16", in_pd),
-        AB8505_MUX_HOG("adi2_d_1", "adi2"),
-        AB8505_PIN_HOG("GPIO17_P2", in_pd),
-        AB8505_PIN_HOG("GPIO18_N3", in_pd),
-        AB8505_PIN_HOG("GPIO19_T1", in_pd),
-        AB8505_PIN_HOG("GPIO20_P3", in_pd),
-        AB8505_MUX_HOG("gpio34_a_1", "gpio"),
-        AB8505_PIN_HOG("GPIO34_H14", in_pd),
-        AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
-        AB8505_PIN_HOG("GPIO40_J15", in_pd),
-        AB8505_PIN_HOG("GPIO41_J14", in_pd),
-        AB8505_MUX_HOG("gpio50_d_1", "gpio"),
-        AB8505_PIN_HOG("GPIO50_L4", in_nopull),
-        AB8505_MUX_HOG("resethw_d_1", "resethw"),
-        AB8505_PIN_HOG("GPIO52_D16", in_pd),
-        AB8505_MUX_HOG("service_d_1", "service"),
-        AB8505_PIN_HOG("GPIO53_D15", in_pd),
-};
-void __init mop500_pinmaps_init(void)
-{
-        if (machine_is_u8520())
-                pinctrl_register_mappings(ab8505_pinmap,
-                                          ARRAY_SIZE(ab8505_pinmap));
-        else
-                pinctrl_register_mappings(ab8500_pinmap,
-                                          ARRAY_SIZE(ab8500_pinmap));
-}
-void __init snowball_pinmaps_init(void)
-{
-        pinctrl_register_mappings(ab8500_pinmap,
-                                  ARRAY_SIZE(ab8500_pinmap));
-}
-void __init hrefv60_pinmaps_init(void)
-{
-        pinctrl_register_mappings(ab8500_pinmap,
-                                  ARRAY_SIZE(ab8500_pinmap));
-}
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index d48e8662c676..32cc0d8d8a0e 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,78 +7,9 @@
 #ifndef __BOARD_MOP500_H
 #define __BOARD_MOP500_H
-/* For NOMADIK_NR_GPIO */
-#include "irqs.h"
 #include <linux/platform_data/asoc-ux500-msp.h>
 #include <linux/amba/mmci.h>
-/* Snowball specific GPIO assignments, this board has no GPIO expander */
-#define SNOWBALL_ACCEL_INT1_GPIO        163
-#define SNOWBALL_ACCEL_INT2_GPIO        164
-#define SNOWBALL_MAGNET_DRDY_GPIO       165
-#define SNOWBALL_SDMMC_EN_GPIO          217
-#define SNOWBALL_SDMMC_1V8_3V_GPIO      228
-#define SNOWBALL_SDMMC_CD_GPIO          218
-/* HREFv60-specific GPIO assignments, this board has no GPIO expander */
-#define HREFV60_SDMMC_1V8_3V_GPIO       5
-#define HREFV60_CAMERA_FLASH_ENABLE     21
-#define HREFV60_MAGNET_DRDY_GPIO        32
-#define HREFV60_DISP1_RST_GPIO          65
-#define HREFV60_DISP2_RST_GPIO          66
-#define HREFV60_ACCEL_INT1_GPIO         82
-#define HREFV60_ACCEL_INT2_GPIO         83
-#define HREFV60_SDMMC_CD_GPIO           95
-#define HREFV60_XSHUTDOWN_SECONDARY_SENSOR 140
-#define HREFV60_TOUCH_RST_GPIO          143
-#define HREFV60_HAL_SW_GPIO             145
-#define HREFV60_SDMMC_EN_GPIO           169
-#define HREFV60_MMIO_XENON_CHARGE       170
-#define HREFV60_PROX_SENSE_GPIO         217
-/* MOP500 generic GPIOs */
-#define CAMERA_FLASH_INT_PIN            7
-#define CYPRESS_TOUCH_INT_PIN           84
-#define XSHUTDOWN_PRIMARY_SENSOR        141
-#define XSHUTDOWN_SECONDARY_SENSOR      142
-#define CYPRESS_TOUCH_RST_GPIO          143
-#define MOP500_HDMI_RST_GPIO            196
-#define CYPRESS_SLAVE_SELECT_GPIO       216
-/* GPIOs on the TC35892 expander */
-#define MOP500_EGPIO(x)                 (NOMADIK_NR_GPIO + (x))
-#define GPIO_MAGNET_DRDY                MOP500_EGPIO(1)
-#define GPIO_SDMMC_CD                   MOP500_EGPIO(3)
-#define GPIO_CAMERA_FLASH_ENABLE        MOP500_EGPIO(4)
-#define GPIO_MMIO_XENON_CHARGE          MOP500_EGPIO(5)
-#define GPIO_PROX_SENSOR                MOP500_EGPIO(7)
-#define GPIO_HAL_SENSOR                 MOP500_EGPIO(8)
-#define GPIO_ACCEL_INT1                 MOP500_EGPIO(10)
-#define GPIO_ACCEL_INT2                 MOP500_EGPIO(11)
-#define GPIO_BU21013_CS                 MOP500_EGPIO(13)
-#define MOP500_DISP2_RST_GPIO           MOP500_EGPIO(14)
-#define MOP500_DISP1_RST_GPIO           MOP500_EGPIO(15)
-#define GPIO_SDMMC_EN                   MOP500_EGPIO(17)
-#define GPIO_SDMMC_1V8_3V_SEL           MOP500_EGPIO(18)
-#define MOP500_EGPIO_END                MOP500_EGPIO(24)
-/*
- * GPIOs on the AB8500 mixed-signals circuit
- * Notice that we subtract 1 from the number passed into the macro, this is
- * because the AB8500 GPIO pins are enumbered starting from 1, so the value in
- * parens matches the GPIO pin number in the data sheet.
- */
-#define MOP500_AB8500_PIN_GPIO(x)       (MOP500_EGPIO_END + (x) - 1)
-/*Snowball AB8500 GPIO */
-#define SNOWBALL_VSMPS2_1V8_GPIO        MOP500_AB8500_PIN_GPIO(1)       /* SYSCLKREQ2/GPIO1 */
-#define SNOWBALL_PM_GPIO1_GPIO          MOP500_AB8500_PIN_GPIO(2)       /* SYSCLKREQ3/GPIO2 */
-#define SNOWBALL_WLAN_CLK_REQ_GPIO      MOP500_AB8500_PIN_GPIO(3)       /* SYSCLKREQ4/GPIO3 */
-#define SNOWBALL_PM_GPIO4_GPIO          MOP500_AB8500_PIN_GPIO(4)       /* SYSCLKREQ6/GPIO4 */
-#define SNOWBALL_EN_3V6_GPIO            MOP500_AB8500_PIN_GPIO(16)      /* PWMOUT3/GPIO16 */
-#define SNOWBALL_PME_ETH_GPIO           MOP500_AB8500_PIN_GPIO(24)      /* SYSCLKREQ7/GPIO24 */
-#define SNOWBALL_EN_3V3_ETH_GPIO        MOP500_AB8500_PIN_GPIO(26)      /* GPIO26 */
-struct device;
 extern struct mmci_platform_data mop500_sdi0_data;
 extern struct mmci_platform_data mop500_sdi1_data;
 extern struct mmci_platform_data mop500_sdi2_data;
@@ -88,8 +19,4 @@ extern struct msp_i2s_platform_data msp1_platform_data;
 extern struct msp_i2s_platform_data msp2_platform_data;
 extern struct msp_i2s_platform_data msp3_platform_data;
-void __init mop500_pinmaps_init(void);
-void __init snowball_pinmaps_init(void);
-void __init hrefv60_pinmaps_init(void);
 #endif
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index bc8a6183560d..8820f602fcd2 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -27,7 +27,6 @@
 #include <asm/mach/map.h>
 #include "setup.h"
-#include "irqs.h"
 #include "board-mop500-regulators.h"
 #include "board-mop500.h"
@@ -35,14 +34,11 @@
 #include "id.h"
 struct ab8500_platform_data ab8500_platdata = {
-        .irq_base       = MOP500_AB8500_IRQ_BASE,
        .regulator      = &ab8500_regulator_plat_data,
 };
 struct prcmu_pdata db8500_prcmu_pdata = {
        .ab_platdata    = &ab8500_platdata,
-        .ab_irq         = IRQ_DB8500_AB8500,
-        .irq_base       = IRQ_PRCMU_BASE,
        .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
        .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
 };
@@ -146,7 +142,6 @@ static struct device * __init db8500_soc_device_init(void)
        return ux500_soc_device_init(soc_id);
 }
-#ifdef CONFIG_MACH_UX500_DT
 static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
        /* Requires call-back bindings. */
        OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
@@ -191,16 +186,6 @@ static void __init u8500_init_machine(void)
 {
        struct device *parent = db8500_soc_device_init();
-        /* Pinmaps must be in place before devices register */
-        if (of_machine_is_compatible("st-ericsson,mop500"))
-                mop500_pinmaps_init();
-        else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-                snowball_pinmaps_init();
-        } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
-                hrefv60_pinmaps_init();
-        else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
-                /* TODO: Add pinmaps for ccu9540 board. */
        /* automatically probe child nodes of dbx5x0 devices */
        if (of_machine_is_compatible("st-ericsson,u8540"))
                of_platform_populate(NULL, u8500_local_bus_nodes,
@@ -229,5 +214,3 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
        .dt_compat      = stericsson_dt_platform_compat,
        .restart        = ux500_restart,
 MACHINE_END
-#endif
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index d11ac4bf336c..db16b5a04ad5 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -52,17 +52,7 @@ void ux500_restart(enum reboot_mode mode, const char *cmd)
 */
 void __init ux500_init_irq(void)
 {
-        void __iomem *dist_base;
-        void __iomem *cpu_base;
        gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
-        if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
-                dist_base = __io_address(U8500_GIC_DIST_BASE);
-                cpu_base = __io_address(U8500_GIC_CPU_BASE);
-        } else
-                ux500_unknown_soc();
        irqchip_init();
        /*
diff --git a/arch/arm/mach-ux500/irqs-board-mop500.h b/arch/arm/mach-ux500/irqs-board-mop500.h
deleted file mode 100644
index d526dd8e87d3..000000000000
--- a/arch/arm/mach-ux500/irqs-board-mop500.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com>
- * License terms: GNU General Public License (GPL) version 2
- */
-#ifndef __MACH_IRQS_BOARD_MOP500_H
-#define __MACH_IRQS_BOARD_MOP500_H
-/* Number of AB8500 irqs is taken from header file */
-#include <linux/mfd/abx500/ab8500.h>
-#define MOP500_AB8500_IRQ_BASE          IRQ_BOARD_START
-#define MOP500_AB8500_IRQ_END           (MOP500_AB8500_IRQ_BASE \
-                                         + AB8500_MAX_NR_IRQS)
-/* TC35892 */
-#define TC35892_NR_INTERNAL_IRQS        8
-#define TC35892_INT_GPIO(x)             (TC35892_NR_INTERNAL_IRQS + (x))
-#define TC35892_NR_GPIOS                24
-#define TC35892_NR_IRQS                 TC35892_INT_GPIO(TC35892_NR_GPIOS)
-#define MOP500_EGPIO_NR_IRQS            TC35892_NR_IRQS
-#define MOP500_EGPIO_IRQ_BASE           MOP500_AB8500_IRQ_END
-#define MOP500_EGPIO_IRQ_END            (MOP500_EGPIO_IRQ_BASE \
-                                         + MOP500_EGPIO_NR_IRQS)
-/* STMPE1601 irqs */
-#define STMPE_NR_INTERNAL_IRQS          9
-#define STMPE_INT_GPIO(x)               (STMPE_NR_INTERNAL_IRQS + (x))
-#define STMPE_NR_GPIOS                  24
-#define STMPE_NR_IRQS                   STMPE_INT_GPIO(STMPE_NR_GPIOS)
-#define MOP500_STMPE1601_IRQBASE        MOP500_EGPIO_IRQ_END
-#define MOP500_STMPE1601_IRQ(x)         (MOP500_STMPE1601_IRQBASE + (x))
-#define MOP500_STMPE1601_IRQ_END        \
-        MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
-#define MOP500_NR_IRQS          MOP500_STMPE1601_IRQ_END
-#define MOP500_IRQ_END          MOP500_NR_IRQS
-/*
- * We may have several boards, but only one will run at a
- * time, so the one with most IRQs will bump this ahead,
- * but the IRQ_BOARD_START remains the same for either board.
- */
-#if MOP500_IRQ_END > IRQ_BOARD_END
-#undef IRQ_BOARD_END
-#define IRQ_BOARD_END   MOP500_IRQ_END
-#endif
-#endif
diff --git a/arch/arm/mach-ux500/irqs-db8500.h b/arch/arm/mach-ux500/irqs-db8500.h
deleted file mode 100644
index f3a9d5947ef3..000000000000
--- a/arch/arm/mach-ux500/irqs-db8500.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com>
- * License terms: GNU General Public License (GPL) version 2
- */
-#ifndef __MACH_IRQS_DB8500_H
-#define __MACH_IRQS_DB8500_H
-#define IRQ_DB8500_MTU0                 (IRQ_SHPI_START + 4)
-#define IRQ_DB8500_SPI2                 (IRQ_SHPI_START + 6)
-#define IRQ_DB8500_PMU                  (IRQ_SHPI_START + 7)
-#define IRQ_DB8500_SPI0                 (IRQ_SHPI_START + 8)
-#define IRQ_DB8500_RTT                  (IRQ_SHPI_START + 9)
-#define IRQ_DB8500_PKA                  (IRQ_SHPI_START + 10)
-#define IRQ_DB8500_UART0                (IRQ_SHPI_START + 11)
-#define IRQ_DB8500_I2C3                 (IRQ_SHPI_START + 12)
-#define IRQ_DB8500_L2CC                 (IRQ_SHPI_START + 13)
-#define IRQ_DB8500_SSP0                 (IRQ_SHPI_START + 14)
-#define IRQ_DB8500_CRYP1                (IRQ_SHPI_START + 15)
-#define IRQ_DB8500_MSP1_RX              (IRQ_SHPI_START + 16)
-#define IRQ_DB8500_MTU1                 (IRQ_SHPI_START + 17)
-#define IRQ_DB8500_RTC                  (IRQ_SHPI_START + 18)
-#define IRQ_DB8500_UART1                (IRQ_SHPI_START + 19)
-#define IRQ_DB8500_USB_WAKEUP           (IRQ_SHPI_START + 20)
-#define IRQ_DB8500_I2C0                 (IRQ_SHPI_START + 21)
-#define IRQ_DB8500_I2C1                 (IRQ_SHPI_START + 22)
-#define IRQ_DB8500_USBOTG               (IRQ_SHPI_START + 23)
-#define IRQ_DB8500_DMA_SECURE           (IRQ_SHPI_START + 24)
-#define IRQ_DB8500_DMA                  (IRQ_SHPI_START + 25)
-#define IRQ_DB8500_UART2                (IRQ_SHPI_START + 26)
-#define IRQ_DB8500_ICN_PMU1             (IRQ_SHPI_START + 27)
-#define IRQ_DB8500_ICN_PMU2             (IRQ_SHPI_START + 28)
-#define IRQ_DB8500_HSIR_EXCEP           (IRQ_SHPI_START + 29)
-#define IRQ_DB8500_MSP0                 (IRQ_SHPI_START + 31)
-#define IRQ_DB8500_HSIR_CH0_OVRRUN      (IRQ_SHPI_START + 32)
-#define IRQ_DB8500_HSIR_CH1_OVRRUN      (IRQ_SHPI_START + 33)
-#define IRQ_DB8500_HSIR_CH2_OVRRUN      (IRQ_SHPI_START + 34)
-#define IRQ_DB8500_HSIR_CH3_OVRRUN      (IRQ_SHPI_START + 35)
-#define IRQ_DB8500_HSIR_CH4_OVRRUN      (IRQ_SHPI_START + 36)
-#define IRQ_DB8500_HSIR_CH5_OVRRUN      (IRQ_SHPI_START + 37)
-#define IRQ_DB8500_HSIR_CH6_OVRRUN      (IRQ_SHPI_START + 38)
-#define IRQ_DB8500_HSIR_CH7_OVRRUN      (IRQ_SHPI_START + 39)
-#define IRQ_DB8500_AB8500               (IRQ_SHPI_START + 40)
-#define IRQ_DB8500_SDMMC2               (IRQ_SHPI_START + 41)
-#define IRQ_DB8500_SIA                  (IRQ_SHPI_START + 42)
-#define IRQ_DB8500_SIA2                 (IRQ_SHPI_START + 43)
-#define IRQ_DB8500_SVA                  (IRQ_SHPI_START + 44)
-#define IRQ_DB8500_SVA2                 (IRQ_SHPI_START + 45)
-#define IRQ_DB8500_PRCMU0               (IRQ_SHPI_START + 46)
-#define IRQ_DB8500_PRCMU1               (IRQ_SHPI_START + 47)
-#define IRQ_DB8500_DISP                 (IRQ_SHPI_START + 48)
-#define IRQ_DB8500_SPI3                 (IRQ_SHPI_START + 49)
-#define IRQ_DB8500_SDMMC1               (IRQ_SHPI_START + 50)
-#define IRQ_DB8500_I2C4                 (IRQ_SHPI_START + 51)
-#define IRQ_DB8500_SSP1                 (IRQ_SHPI_START + 52)
-#define IRQ_DB8500_SKE                  (IRQ_SHPI_START + 53)
-#define IRQ_DB8500_KB                   (IRQ_SHPI_START + 54)
-#define IRQ_DB8500_I2C2                 (IRQ_SHPI_START + 55)
-#define IRQ_DB8500_B2R2                 (IRQ_SHPI_START + 56)
-#define IRQ_DB8500_CRYP0                (IRQ_SHPI_START + 57)
-#define IRQ_DB8500_SDMMC3               (IRQ_SHPI_START + 59)
-#define IRQ_DB8500_SDMMC0               (IRQ_SHPI_START + 60)
-#define IRQ_DB8500_HSEM                 (IRQ_SHPI_START + 61)
-#define IRQ_DB8500_MSP1                 (IRQ_SHPI_START + 62)
-#define IRQ_DB8500_SBAG                 (IRQ_SHPI_START + 63)
-#define IRQ_DB8500_SPI1                 (IRQ_SHPI_START + 96)
-#define IRQ_DB8500_SRPTIMER             (IRQ_SHPI_START + 97)
-#define IRQ_DB8500_MSP2                 (IRQ_SHPI_START + 98)
-#define IRQ_DB8500_SDMMC4               (IRQ_SHPI_START + 99)
-#define IRQ_DB8500_SDMMC5               (IRQ_SHPI_START + 100)
-#define IRQ_DB8500_HSIRD0               (IRQ_SHPI_START + 104)
-#define IRQ_DB8500_HSIRD1               (IRQ_SHPI_START + 105)
-#define IRQ_DB8500_HSITD0               (IRQ_SHPI_START + 106)
-#define IRQ_DB8500_HSITD1               (IRQ_SHPI_START + 107)
-#define IRQ_DB8500_CTI0                 (IRQ_SHPI_START + 108)
-#define IRQ_DB8500_CTI1                 (IRQ_SHPI_START + 109)
-#define IRQ_DB8500_ICN_ERR              (IRQ_SHPI_START + 110)
-#define IRQ_DB8500_MALI_PPMMU           (IRQ_SHPI_START + 112)
-#define IRQ_DB8500_MALI_PP              (IRQ_SHPI_START + 113)
-#define IRQ_DB8500_MALI_GPMMU           (IRQ_SHPI_START + 114)
-#define IRQ_DB8500_MALI_GP              (IRQ_SHPI_START + 115)
-#define IRQ_DB8500_MALI                 (IRQ_SHPI_START + 116)
-#define IRQ_DB8500_PRCMU_SEM            (IRQ_SHPI_START + 118)
-#define IRQ_DB8500_GPIO0                (IRQ_SHPI_START + 119)
-#define IRQ_DB8500_GPIO1                (IRQ_SHPI_START + 120)
-#define IRQ_DB8500_GPIO2                (IRQ_SHPI_START + 121)
-#define IRQ_DB8500_GPIO3                (IRQ_SHPI_START + 122)
-#define IRQ_DB8500_GPIO4                (IRQ_SHPI_START + 123)
-#define IRQ_DB8500_GPIO5                (IRQ_SHPI_START + 124)
-#define IRQ_DB8500_GPIO6                (IRQ_SHPI_START + 125)
-#define IRQ_DB8500_GPIO7                (IRQ_SHPI_START + 126)
-#define IRQ_DB8500_GPIO8                (IRQ_SHPI_START + 127)
-#define IRQ_CA_WAKE_REQ_ED                      (IRQ_SHPI_START + 71)
-#define IRQ_AC_READ_NOTIFICATION_0_ED           (IRQ_SHPI_START + 66)
-#define IRQ_AC_READ_NOTIFICATION_1_ED           (IRQ_SHPI_START + 64)
-#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED       (IRQ_SHPI_START + 67)
-#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED       (IRQ_SHPI_START + 65)
-#define IRQ_CA_WAKE_REQ_V1                      (IRQ_SHPI_START + 83)
-#define IRQ_AC_READ_NOTIFICATION_0_V1           (IRQ_SHPI_START + 78)
-#define IRQ_AC_READ_NOTIFICATION_1_V1           (IRQ_SHPI_START + 76)
-#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1       (IRQ_SHPI_START + 79)
-#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1       (IRQ_SHPI_START + 77)
-#ifdef CONFIG_UX500_SOC_DB8500
-/* Virtual interrupts corresponding to the PRCMU wakeups.  */
-#define IRQ_PRCMU_BASE IRQ_SOC_START
-#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
-/*
- * We may have several SoCs, but only one will run at a
- * time, so the one with most IRQs will bump this ahead,
- * but the IRQ_SOC_START remains the same for either SoC.
- */
-#if IRQ_SOC_END < IRQ_PRCMU_END
-#undef IRQ_SOC_END
-#define IRQ_SOC_END IRQ_PRCMU_END
-#endif
-#endif /* CONFIG_UX500_SOC_DB8500 */
-#endif
diff --git a/arch/arm/mach-ux500/irqs.h b/arch/arm/mach-ux500/irqs.h
deleted file mode 100644
index 15b2af698ed7..000000000000
--- a/arch/arm/mach-ux500/irqs.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *  Copyright (C) 2008 STMicroelectronics
- *  Copyright (C) 2009 ST-Ericsson.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef ASM_ARCH_IRQS_H
-#define ASM_ARCH_IRQS_H
-#define IRQ_LOCALTIMER                  29
-#define IRQ_LOCALWDOG                   30
-/* Shared Peripheral Interrupt (SHPI) */
-#define IRQ_SHPI_START                  32
-/*
- * MTU0 preserved for now until plat-nomadik is taught not to use it.  Don't
- * add any other IRQs here, use the irqs-dbx500.h files.
- */
-#define IRQ_MTU0                (IRQ_SHPI_START + 4)
-#define DBX500_NR_INTERNAL_IRQS         166
-/* After chip-specific IRQ numbers we have the GPIO ones */
-#define NOMADIK_NR_GPIO                 288
-#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + DBX500_NR_INTERNAL_IRQS)
-#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - DBX500_NR_INTERNAL_IRQS)
-#define IRQ_GPIO_END                    NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
-#define IRQ_SOC_START           IRQ_GPIO_END
-/* This will be overridden by SoC-specific irq headers */
-#define IRQ_SOC_END             IRQ_SOC_START
-#include "irqs-db8500.h"
-#define IRQ_BOARD_START         IRQ_SOC_END
-/* This will be overridden by board-specific irq headers */
-#define IRQ_BOARD_END           IRQ_BOARD_START
-#ifdef CONFIG_MACH_MOP500
-#include "irqs-board-mop500.h"
-#endif
-#define UX500_NR_IRQS           IRQ_BOARD_END
-#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index a335126ae18f..f2c89fb8fca9 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -108,7 +108,7 @@ void __init versatile_init_irq(void)
        np = of_find_matching_node_by_address(NULL, vic_of_match,
                                              VERSATILE_VIC_BASE);
-        __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
+        __vic_init(VA_VIC_BASE, 0, IRQ_VIC_START, ~0, 0, np);
        writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 4a70be485ff8..657d52d0391f 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -5,17 +5,12 @@ config ARCH_VEXPRESS
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
-        select COMMON_CLK
        select COMMON_CLK_VERSATILE
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
        select HAVE_PATA_PLATFORM
-        select HAVE_SMP
        select ICST
-        select MIGHT_HAVE_CACHE_L2X0
+        select NO_IOPORT_MAP
-        select NO_IOPORT
        select PLAT_VERSATILE
        select PLAT_VERSATILE_CLCD
        select POWER_RESET
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 0997e0b7494c..fc649bc09d0c 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -8,8 +8,11 @@ obj-y					:= v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
 obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)       += dcscb.o      dcscb_setup.o
 CFLAGS_dcscb.o                          += -march=armv7-a
+CFLAGS_REMOVE_dcscb.o                   = -pg
 obj-$(CONFIG_ARCH_VEXPRESS_SPC)         += spc.o
+CFLAGS_REMOVE_spc.o                     = -pg
 obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM)      += tc2_pm.o
 CFLAGS_tc2_pm.o                         += -march=armv7-a
+CFLAGS_REMOVE_tc2_pm.o                  = -pg
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 14d499688736..788495d35cf9 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -137,11 +137,16 @@ static void dcscb_power_down(void)
                v7_exit_coherency_flush(all);
                /*
-                 * This is a harmless no-op.  On platforms with a real
+                 * A full outer cache flush could be needed at this point
-                 * outer cache this might either be needed or not,
+                 * on platforms with such a cache, depending on where the
-                 * depending on where the outer cache sits.
+                 * outer cache sits. In some cases the notion of a "last
+                 * cluster standing" would need to be implemented if the
+                 * outer cache is shared across clusters. In any case, when
+                 * the outer cache needs flushing, there is no concurrent
+                 * access to the cache controller to worry about and no
+                 * special locking besides what is already provided by the
+                 * MCPM state machinery is needed.
                 */
-                outer_flush_all();
                /*
                 * Disable cluster-level coherency by masking
diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
deleted file mode 100644
index 081d46929436..000000000000
--- a/arch/arm/mach-virt/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-config ARCH_VIRT
-        bool "Dummy Virtual Machine" if ARCH_MULTI_V7
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_GIC
-        select HAVE_ARM_ARCH_TIMER
-        select ARM_PSCI
-        select HAVE_SMP
-        select CPU_V7
-        select SPARSE_IRQ
-        select USE_OF
diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile
deleted file mode 100644
index 7ddbfa60227f..000000000000
--- a/arch/arm/mach-virt/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-obj-y                                   := virt.o
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
deleted file mode 100644
index b184e57d1854..000000000000
--- a/arch/arm/mach-virt/virt.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Dummy Virtual Machine - does what it says on the tin.
- *
- * Copyright (C) 2012 ARM Ltd
- * Authors: Will Deacon <will.deacon@arm.com>,
- *          Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/smp.h>
-#include <asm/mach/arch.h>
-static void __init virt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-static const char *virt_dt_match[] = {
-        "linux,dummy-virt",
-        "xen,xenvm",
-        NULL
-};
-DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
-        .init_machine   = virt_init,
-        .dt_compat      = virt_dt_match,
-MACHINE_END
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 927be93b692e..08f56a41cb55 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -3,8 +3,6 @@ config ARCH_VT8500
        select ARCH_HAS_CPUFREQ
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
        select VT8500_TIMER
        select PINCTRL
        help
@@ -21,7 +19,6 @@ config ARCH_WM8750
        bool "WonderMedia WM8750"
        depends on ARCH_MULTI_V6
        select ARCH_VT8500
-        select CPU_V6
        help
          Support for WonderMedia WM8750 System-on-Chip.
@@ -29,6 +26,5 @@ config ARCH_WM8850
        bool "WonderMedia WM8850"
        depends on ARCH_MULTI_V7
        select ARCH_VT8500
-        select CPU_V7
        help
          Support for WonderMedia WM8850 System-on-Chip.
diff --git a/arch/arm/mach-w90x900/include/mach/timex.h b/arch/arm/mach-w90x900/include/mach/timex.h
deleted file mode 100644
index 164dce0b64db..000000000000
--- a/arch/arm/mach-w90x900/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-w90x900/include/mach/timex.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * Based on arch/arm/mach-s3c2410/include/mach/timex.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-/* CLOCK_TICK_RATE Now, I don't use it. */
-#define CLOCK_TICK_RATE 15000000
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index 30fbca844575..9230d3725599 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -111,7 +111,7 @@ static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
 static struct irqaction nuc900_timer0_irq = {
        .name           = "nuc900-timer0",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = nuc900_timer0_interrupt,
 };
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index f03e75bd0b2b..58c2b844e0a3 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -4,17 +4,11 @@ config ARCH_ZYNQ
        select ARM_GIC
        select ARCH_HAS_CPUFREQ
        select ARCH_HAS_OPP
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
        select ICST
-        select MIGHT_HAVE_CACHE_L2X0
-        select USE_OF
-        select HAVE_SMP
-        select SPARSE_IRQ
        select CADENCE_TTC_TIMER
        select ARM_GLOBAL_TIMER if !CPU_FREQ
+        select MFD_SYSCON
        help
          Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index a39be8e80856..6fcc584c1a11 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -19,6 +19,7 @@
 #include <linux/cpumask.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/clk/zynq.h>
 #include <linux/clocksource.h>
 #include <linux/of_address.h>
@@ -75,11 +76,16 @@ static void __init zynq_init_machine(void)
        platform_device_register(&zynq_cpuidle_device);
        platform_device_register_full(&devinfo);
+        zynq_slcr_init();
 }
 static void __init zynq_timer_init(void)
 {
-        zynq_slcr_init();
+        zynq_early_slcr_init();
+        zynq_clock_init();
+        of_clk_init(NULL);
        clocksource_of_init();
 }
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index c22c92cea8cb..b097844d3175 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -20,6 +20,7 @@
 void zynq_secondary_startup(void);
 extern int zynq_slcr_init(void);
+extern int zynq_early_slcr_init(void);
 extern void zynq_slcr_system_reset(void);
 extern void zynq_slcr_cpu_stop(int cpu);
 extern void zynq_slcr_cpu_start(int cpu);
@@ -33,7 +34,6 @@ extern int zynq_cpun_start(u32 address, int cpu);
 extern struct smp_operations zynq_smp_ops __initdata;
 #endif
-extern void __iomem *zynq_slcr_base;
 extern void __iomem *zynq_scu_base;
 /* Hotplug */
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 1836d5a34606..a37d49a6e657 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -15,7 +15,9 @@
 */
 #include <linux/io.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of_address.h>
+#include <linux/regmap.h>
 #include <linux/clk/zynq.h>
 #include "common.h"
@@ -29,7 +31,56 @@
 #define SLCR_A9_CPU_CLKSTOP             0x10
 #define SLCR_A9_CPU_RST                 0x1
-void __iomem *zynq_slcr_base;
+static void __iomem *zynq_slcr_base;
+static struct regmap *zynq_slcr_regmap;
+/**
+ * zynq_slcr_write - Write to a register in SLCR block
+ *
+ * @val:        Value to write to the register
+ * @offset:     Register offset in SLCR block
+ *
+ * Return:      a negative value on error, 0 on success
+ */
+static int zynq_slcr_write(u32 val, u32 offset)
+{
+        if (!zynq_slcr_regmap) {
+                writel(val, zynq_slcr_base + offset);
+                return 0;
+        }
+        return regmap_write(zynq_slcr_regmap, offset, val);
+}
+/**
+ * zynq_slcr_read - Read a register in SLCR block
+ *
+ * @val:        Pointer to value to be read from SLCR
+ * @offset:     Register offset in SLCR block
+ *
+ * Return:      a negative value on error, 0 on success
+ */
+static int zynq_slcr_read(u32 *val, u32 offset)
+{
+        if (zynq_slcr_regmap)
+                return regmap_read(zynq_slcr_regmap, offset, val);
+        *val = readl(zynq_slcr_base + offset);
+        return 0;
+}
+/**
+ * zynq_slcr_unlock - Unlock SLCR registers
+ *
+ * Return:      a negative value on error, 0 on success
+ */
+static inline int zynq_slcr_unlock(void)
+{
+        zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
+        return 0;
+}
 /**
 * zynq_slcr_system_reset - Reset the entire system.
@@ -43,16 +94,16 @@ void zynq_slcr_system_reset(void)
         * Note that this seems to require raw i/o
         * functions or there's a lockup?
         */
-        writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
+        zynq_slcr_unlock();
        /*
         * Clear 0x0F000000 bits of reboot status register to workaround
         * the FSBL not loading the bitstream after soft-reboot
         * This is a temporary solution until we know more.
         */
-        reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+        zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
-        writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
+        zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
-        writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
+        zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
 }
 /**
@@ -61,11 +112,13 @@ void zynq_slcr_system_reset(void)
 */
 void zynq_slcr_cpu_start(int cpu)
 {
-        u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        u32 reg;
+        zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
        reg &= ~(SLCR_A9_CPU_RST << cpu);
-        writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
        reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
-        writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 }
 /**
@@ -74,19 +127,40 @@ void zynq_slcr_cpu_start(int cpu)
 */
 void zynq_slcr_cpu_stop(int cpu)
 {
-        u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        u32 reg;
+        zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
        reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
-        writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
+        zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 }
 /**
- * zynq_slcr_init
+ * zynq_slcr_init - Regular slcr driver init
- * Returns 0 on success, negative errno otherwise.
+ *
+ * Return:      0 on success, negative errno otherwise.
 *
 * Called early during boot from platform code to remap SLCR area.
 */
 int __init zynq_slcr_init(void)
 {
+        zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
+        if (IS_ERR(zynq_slcr_regmap)) {
+                pr_err("%s: failed to find zynq-slcr\n", __func__);
+                return -ENODEV;
+        }
+        return 0;
+}
+/**
+ * zynq_early_slcr_init - Early slcr init function
+ *
+ * Return:      0 on success, negative errno otherwise.
+ *
+ * Called very early during boot from platform code to unlock SLCR.
+ */
+int __init zynq_early_slcr_init(void)
+{
        struct device_node *np;
        np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
@@ -101,13 +175,13 @@ int __init zynq_slcr_init(void)
                BUG();
        }
+        np->data = (__force void *)zynq_slcr_base;
        /* unlock the SLCR so that registers can be changed */
-        writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
+        zynq_slcr_unlock();
        pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
-        zynq_clock_init(zynq_slcr_base);
        of_node_put(np);
        return 0;
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 1f8fed94c2a4..f5ad9ee70426 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -264,7 +264,7 @@ config CPU_ARM1026
 # SA110
 config CPU_SA110
-        bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
+        bool
        select CPU_32v3 if ARCH_RPC
        select CPU_32v4 if !ARCH_RPC
        select CPU_ABRT_EV4
@@ -446,7 +446,6 @@ config CPU_32v5
 config CPU_32v6
        bool
-        select CPU_USE_DOMAINS if CPU_V6 && MMU
        select TLS_REG_EMUL if !CPU_32v6K && !MMU
 config CPU_32v6K
@@ -671,7 +670,7 @@ config ARM_VIRT_EXT
 config SWP_EMULATE
        bool "Emulate SWP/SWPB instructions"
-        depends on !CPU_USE_DOMAINS && CPU_V7
+        depends on CPU_V7
        default y if SMP
        select HAVE_PROC_CPU if PROC_FS
        help
@@ -855,7 +854,7 @@ config OUTER_CACHE_SYNC
 config CACHE_FEROCEON_L2
        bool "Enable the Feroceon L2 cache controller"
-        depends on ARCH_KIRKWOOD || ARCH_MV78XX0
+        depends on ARCH_KIRKWOOD || ARCH_MV78XX0 || ARCH_MVEBU
        default y
        select OUTER_CACHE
        help
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 48bc3c0a87ce..dc814a548056 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -13,10 +13,15 @@
 */
 #include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/highmem.h>
+#include <linux/io.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
-#include <plat/cache-feroceon-l2.h>
+#include <asm/hardware/cache-feroceon-l2.h>
+#define L2_WRITETHROUGH_KIRKWOOD        BIT(4)
 /*
 * Low-level cache maintenance operations.
@@ -331,7 +336,9 @@ static void __init enable_l2(void)
                        enable_icache();
                if (d)
                        enable_dcache();
-        }
+        } else
+                pr_err(FW_BUG
+                       "Feroceon L2: bootloader left the L2 cache on!\n");
 }
 void __init feroceon_l2_init(int __l2_wt_override)
@@ -350,3 +357,41 @@ void __init feroceon_l2_init(int __l2_wt_override)
        printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
                         l2_wt_override ? ", in WT override mode" : "");
 }
+#ifdef CONFIG_OF
+static const struct of_device_id feroceon_ids[] __initconst = {
+        { .compatible = "marvell,kirkwood-cache"},
+        { .compatible = "marvell,feroceon-cache"},
+        {}
+};
+int __init feroceon_of_init(void)
+{
+        struct device_node *node;
+        void __iomem *base;
+        bool l2_wt_override = false;
+        struct resource res;
+#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
+        l2_wt_override = true;
+#endif
+        node = of_find_matching_node(NULL, feroceon_ids);
+        if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) {
+                if (of_address_to_resource(node, 0, &res))
+                        return -ENODEV;
+                base = ioremap(res.start, resource_size(&res));
+                if (!base)
+                        return -ENOMEM;
+                if (l2_wt_override)
+                        writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
+                else
+                        writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
+        }
+        feroceon_l2_init(l2_wt_override);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 1be0f4e5e6eb..b273739e6359 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -33,7 +33,7 @@
 * outer cache operations into the kernel image if the kernel has been
 * configured to support a pre-v7 CPU.
 */
-#if __LINUX_ARM_ARCH__ < 7
+#ifdef CONFIG_CPU_32v5
 /*
 * Low-level cache maintenance operations.
 */
@@ -229,33 +229,6 @@ static void __init tauros2_internal_init(unsigned int features)
        }
 #endif
-#ifdef CONFIG_CPU_32v6
-        /*
-         * Check whether this CPU lacks support for the v7 hierarchical
-         * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
-         * register indicates no support for the v7 hierarchical cache
-         * ops.)
-         */
-        if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
-                /*
-                 * When Tauros2 is used in an ARMv6 system, the L2
-                 * enable bit is in the ARMv6 ARM-mandated position
-                 * (bit [26] of the System Control Register).
-                 */
-                if (!(get_cr() & 0x04000000)) {
-                        printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
-                        adjust_cr(0x04000000, 0x04000000);
-                }
-                mode = "ARMv6";
-                outer_cache.inv_range = tauros2_inv_range;
-                outer_cache.clean_range = tauros2_clean_range;
-                outer_cache.flush_range = tauros2_flush_range;
-                outer_cache.disable = tauros2_disable;
-                outer_cache.resume = tauros2_resume;
-        }
-#endif
 #ifdef CONFIG_CPU_32v7
        /*
         * Check whether this CPU has support for the v7 hierarchical
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 11b3914660d2..f62aa0677e5c 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -284,9 +284,6 @@ static void __dma_free_buffer(struct page *page, size_t size)
 }
 #ifdef CONFIG_MMU
-#ifdef CONFIG_HUGETLB_PAGE
-#warning ARM Coherent DMA allocator does not (yet) support huge TLB
-#endif
 static void *__alloc_from_contiguous(struct device *dev, size_t size,
                                     pgprot_t prot, struct page **ret_page,
@@ -1069,6 +1066,8 @@ fs_initcall(dma_debug_do_init);
 /* IOMMU */
+static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
                                      size_t size)
 {
@@ -1076,41 +1075,87 @@ static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
        unsigned int align = 0;
        unsigned int count, start;
        unsigned long flags;
+        dma_addr_t iova;
+        int i;
        if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
                order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
-        count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
+        count = PAGE_ALIGN(size) >> PAGE_SHIFT;
-                 (1 << mapping->order) - 1) >> mapping->order;
+        align = (1 << order) - 1;
-        if (order > mapping->order)
-                align = (1 << (order - mapping->order)) - 1;
        spin_lock_irqsave(&mapping->lock, flags);
-        start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
+        for (i = 0; i < mapping->nr_bitmaps; i++) {
-                                           count, align);
+                start = bitmap_find_next_zero_area(mapping->bitmaps[i],
-        if (start > mapping->bits) {
+                                mapping->bits, 0, count, align);
-                spin_unlock_irqrestore(&mapping->lock, flags);
-                return DMA_ERROR_CODE;
+                if (start > mapping->bits)
+                        continue;
+                bitmap_set(mapping->bitmaps[i], start, count);
+                break;
        }
-        bitmap_set(mapping->bitmap, start, count);
+        /*
+         * No unused range found. Try to extend the existing mapping
+         * and perform a second attempt to reserve an IO virtual
+         * address range of size bytes.
+         */
+        if (i == mapping->nr_bitmaps) {
+                if (extend_iommu_mapping(mapping)) {
+                        spin_unlock_irqrestore(&mapping->lock, flags);
+                        return DMA_ERROR_CODE;
+                }
+                start = bitmap_find_next_zero_area(mapping->bitmaps[i],
+                                mapping->bits, 0, count, align);
+                if (start > mapping->bits) {
+                        spin_unlock_irqrestore(&mapping->lock, flags);
+                        return DMA_ERROR_CODE;
+                }
+                bitmap_set(mapping->bitmaps[i], start, count);
+        }
        spin_unlock_irqrestore(&mapping->lock, flags);
-        return mapping->base + (start << (mapping->order + PAGE_SHIFT));
+        iova = mapping->base + (mapping->size * i);
+        iova += start << PAGE_SHIFT;
+        return iova;
 }
 static inline void __free_iova(struct dma_iommu_mapping *mapping,
                               dma_addr_t addr, size_t size)
 {
-        unsigned int start = (addr - mapping->base) >>
+        unsigned int start, count;
-                             (mapping->order + PAGE_SHIFT);
-        unsigned int count = ((size >> PAGE_SHIFT) +
-                              (1 << mapping->order) - 1) >> mapping->order;
        unsigned long flags;
+        dma_addr_t bitmap_base;
+        u32 bitmap_index;
+        if (!size)
+                return;
+        bitmap_index = (u32) (addr - mapping->base) / (u32) mapping->size;
+        BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
+        bitmap_base = mapping->base + mapping->size * bitmap_index;
+        start = (addr - bitmap_base) >> PAGE_SHIFT;
+        if (addr + size > bitmap_base + mapping->size) {
+                /*
+                 * The address range to be freed reaches into the iova
+                 * range of the next bitmap. This should not happen as
+                 * we don't allow this in __alloc_iova (at the
+                 * moment).
+                 */
+                BUG();
+        } else
+                count = size >> PAGE_SHIFT;
        spin_lock_irqsave(&mapping->lock, flags);
-        bitmap_clear(mapping->bitmap, start, count);
+        bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
        spin_unlock_irqrestore(&mapping->lock, flags);
 }
@@ -1875,8 +1920,7 @@ struct dma_map_ops iommu_coherent_ops = {
 * arm_iommu_create_mapping
 * @bus: pointer to the bus holding the client device (for IOMMU calls)
 * @base: start address of the valid IO address space
- * @size: size of the valid IO address space
+ * @size: maximum size of the valid IO address space
- * @order: accuracy of the IO addresses allocations
 *
 * Creates a mapping structure which holds information about used/unused
 * IO address ranges, which is required to perform memory allocation and
@@ -1886,38 +1930,54 @@ struct dma_map_ops iommu_coherent_ops = {
 * arm_iommu_attach_device function.
 */
 struct dma_iommu_mapping *
-arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
+arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size)
-                         int order)
 {
-        unsigned int count = size >> (PAGE_SHIFT + order);
+        unsigned int bits = size >> PAGE_SHIFT;
-        unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
+        unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
        struct dma_iommu_mapping *mapping;
+        int extensions = 1;
        int err = -ENOMEM;
-        if (!count)
+        if (!bitmap_size)
                return ERR_PTR(-EINVAL);
+        if (bitmap_size > PAGE_SIZE) {
+                extensions = bitmap_size / PAGE_SIZE;
+                bitmap_size = PAGE_SIZE;
+        }
        mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
        if (!mapping)
                goto err;
-        mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+        mapping->bitmap_size = bitmap_size;
-        if (!mapping->bitmap)
+        mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
+                                GFP_KERNEL);
+        if (!mapping->bitmaps)
                goto err2;
+        mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
+        if (!mapping->bitmaps[0])
+                goto err3;
+        mapping->nr_bitmaps = 1;
+        mapping->extensions = extensions;
        mapping->base = base;
+        mapping->size = bitmap_size << PAGE_SHIFT;
        mapping->bits = BITS_PER_BYTE * bitmap_size;
-        mapping->order = order;
        spin_lock_init(&mapping->lock);
        mapping->domain = iommu_domain_alloc(bus);
        if (!mapping->domain)
-                goto err3;
+                goto err4;
        kref_init(&mapping->kref);
        return mapping;
+err4:
+        kfree(mapping->bitmaps[0]);
 err3:
-        kfree(mapping->bitmap);
+        kfree(mapping->bitmaps);
 err2:
        kfree(mapping);
 err:
@@ -1927,14 +1987,35 @@ EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
 static void release_iommu_mapping(struct kref *kref)
 {
+        int i;
        struct dma_iommu_mapping *mapping =
                container_of(kref, struct dma_iommu_mapping, kref);
        iommu_domain_free(mapping->domain);
-        kfree(mapping->bitmap);
+        for (i = 0; i < mapping->nr_bitmaps; i++)
+                kfree(mapping->bitmaps[i]);
+        kfree(mapping->bitmaps);
        kfree(mapping);
 }
+static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
+{
+        int next_bitmap;
+        if (mapping->nr_bitmaps > mapping->extensions)
+                return -EINVAL;
+        next_bitmap = mapping->nr_bitmaps;
+        mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
+                                                GFP_ATOMIC);
+        if (!mapping->bitmaps[next_bitmap])
+                return -ENOMEM;
+        mapping->nr_bitmaps++;
+        return 0;
+}
 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
 {
        if (mapping)
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index ef69152f9b52..c508f41a43bc 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -120,34 +120,51 @@ static const struct prot_bits pte_bits[] = {
 };
 static const struct prot_bits section_bits[] = {
-#ifndef CONFIG_ARM_LPAE
+#ifdef CONFIG_ARM_LPAE
-        /* These are approximate */
+        {
+                .mask   = PMD_SECT_USER,
+                .val    = PMD_SECT_USER,
+                .set    = "USR",
+        }, {
+                .mask   = PMD_SECT_RDONLY,
+                .val    = PMD_SECT_RDONLY,
+                .set    = "ro",
+                .clear  = "RW",
+#elif __LINUX_ARM_ARCH__ >= 6
        {
-                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .mask   = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
-                .val    = 0,
+                .val    = PMD_SECT_APX | PMD_SECT_AP_WRITE,
                .set    = "    ro",
        }, {
-                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .mask   = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
                .val    = PMD_SECT_AP_WRITE,
                .set    = "    RW",
        }, {
-                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .mask   = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
                .val    = PMD_SECT_AP_READ,
                .set    = "USR ro",
        }, {
-                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .mask   = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
                .val    = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
                .set    = "USR RW",
-#else
+#else /* ARMv4/ARMv5  */
+        /* These are approximate */
        {
-                .mask   = PMD_SECT_USER,
+                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
-                .val    = PMD_SECT_USER,
+                .val    = 0,
-                .set    = "USR",
+                .set    = "    ro",
        }, {
-                .mask   = PMD_SECT_RDONLY,
+                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
-                .val    = PMD_SECT_RDONLY,
+                .val    = PMD_SECT_AP_WRITE,
-                .set    = "ro",
+                .set    = "    RW",
-                .clear  = "RW",
+        }, {
+                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .val    = PMD_SECT_AP_READ,
+                .set    = "USR ro",
+        }, {
+                .mask   = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .val    = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
+                .set    = "USR RW",
 #endif
        }, {
                .mask   = PMD_SECT_XN,
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 804d61566a53..2a77ba8796ae 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -323,6 +323,8 @@ void __init arm_memblock_init(struct meminfo *mi,
        if (mdesc->reserve)
                mdesc->reserve();
+        early_init_fdt_scan_reserved_mem();
        /*
         * reserve memory for DMA contigouos allocations,
         * must come from DMA area inside low memory
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index a623cb3ad012..b68c6b22e1c8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -516,6 +516,16 @@ static void __init build_mem_type_table(void)
        s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
        /*
+         * We don't use domains on ARMv6 (since this causes problems with
+         * v6/v7 kernels), so we must use a separate memory type for user
+         * r/o, kernel r/w to map the vectors page.
+         */
+#ifndef CONFIG_ARM_LPAE
+        if (cpu_arch == CPU_ARCH_ARMv6)
+                vecs_pgprot |= L_PTE_MT_VECTORS;
+#endif
+        /*
         * ARMv6 and above have extended page tables.
         */
        if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e3c48a3fe063..ee1d80593958 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -112,13 +112,9 @@
 *  100x   1   0   1    r/o     no acc
 *  10x0   1   0   1    r/o     no acc
 *  1011   0   0   1    r/w     no acc
- *  110x   0   1   0    r/w     r/o
- *  11x0   0   1   0    r/w     r/o
- *  1111   0   1   1    r/w     r/w
- *
- * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
 *  110x   1   1   1    r/o     r/o
 *  11x0   1   1   1    r/o     r/o
+ *  1111   0   1   1    r/w     r/w
 */
        .macro  armv6_mt_table pfx
 \pfx\()_mt_table:
@@ -137,7 +133,7 @@
        .long   PTE_EXT_TEX(2)                                  @ L_PTE_MT_DEV_NONSHARED
        .long   0x00                                            @ unused
        .long   0x00                                            @ unused
-        .long   0x00                                            @ unused
+        .long   PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX    @ L_PTE_MT_VECTORS
        .endm
        .macro  armv6_set_pte_ext pfx
@@ -158,24 +154,21 @@
        tst     r1, #L_PTE_USER
        orrne   r3, r3, #PTE_EXT_AP1
-#ifdef CONFIG_CPU_USE_DOMAINS
-        @ allow kernel read/write access to read-only user pages
        tstne   r3, #PTE_EXT_APX
-        bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
-#endif
+        @ user read-only -> kernel read-only
+        bicne   r3, r3, #PTE_EXT_AP0
        tst     r1, #L_PTE_XN
        orrne   r3, r3, #PTE_EXT_XN
-        orr     r3, r3, r2
+        eor     r3, r3, r2
        tst     r1, #L_PTE_YOUNG
        tstne   r1, #L_PTE_PRESENT
        moveq   r3, #0
-#ifndef CONFIG_CPU_USE_DOMAINS
        tstne   r1, #L_PTE_NONE
        movne   r3, #0
-#endif
        str     r3, [r0]
        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index bdd3be4be77a..1f52915f2b28 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -90,21 +90,14 @@ ENTRY(cpu_v7_set_pte_ext)
        tst     r1, #L_PTE_USER
        orrne   r3, r3, #PTE_EXT_AP1
-#ifdef CONFIG_CPU_USE_DOMAINS
-        @ allow kernel read/write access to read-only user pages
-        tstne   r3, #PTE_EXT_APX
-        bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
-#endif
        tst     r1, #L_PTE_XN
        orrne   r3, r3, #PTE_EXT_XN
        tst     r1, #L_PTE_YOUNG
        tstne   r1, #L_PTE_VALID
-#ifndef CONFIG_CPU_USE_DOMAINS
        eorne   r1, r1, #L_PTE_NONE
        tstne   r1, #L_PTE_NONE
-#endif
        moveq   r3, #0
 ARM(   str     r3, [r0, #2048]! )
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 74f6033e76dd..195731d3813b 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -192,6 +192,7 @@ __v7_cr7mp_setup:
        mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
        b       1f
 __v7_ca7mp_setup:
+__v7_ca12mp_setup:
 __v7_ca15mp_setup:
        mov     r10, #0
 1:
@@ -484,6 +485,16 @@ __v7_ca7mp_proc_info:
        .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
        /*
+         * ARM Ltd. Cortex A12 processor.
+         */
+        .type   __v7_ca12mp_proc_info, #object
+__v7_ca12mp_proc_info:
+        .long   0x410fc0d0
+        .long   0xff0ffff0
+        __v7_proc __v7_ca12mp_setup
+        .size   __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
+        /*
         * ARM Ltd. Cortex A15 processor.
         */
        .type   __v7_ca15mp_proc_info, #object
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index 271b5e971568..6f879c319a9d 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -825,8 +825,8 @@ b_epilogue:
                        break;
                case BPF_S_ANC_RXHASH:
                        ctx->seen |= SEEN_SKB;
-                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, rxhash) != 4);
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
-                        off = offsetof(struct sk_buff, rxhash);
+                        off = offsetof(struct sk_buff, hash);
                        emit(ARM_LDR_I(r_A, r_skb, off), ctx);
                        break;
                case BPF_S_ANC_VLAN_TAG:
@@ -925,6 +925,7 @@ void bpf_jit_compile(struct sk_filter *fp)
                bpf_jit_dump(fp->len, alloc_size, 2, ctx.target);
        fp->bpf_func = (void *)ctx.target;
+        fp->jited = 1;
 out:
        kfree(ctx.offsets);
        return;
@@ -932,7 +933,7 @@ out:
 void bpf_jit_free(struct sk_filter *fp)
 {
-        if (fp->bpf_func != sk_run_filter)
+        if (fp->jited)
                module_free(NULL, fp->bpf_func);
        kfree(fp);
 }
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index d70b73364a3f..6ad65d8ae237 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -127,7 +127,7 @@ iop_timer_interrupt(int irq, void *dev_id)
 static struct irqaction iop_timer_irq = {
        .name           = "IOP Timer Tick",
        .handler        = iop_timer_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .dev_id         = &iop_clockevent,
 };
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 436ea97074cd..02fc10d2d63b 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -86,9 +86,6 @@ config OMAP_MUX_WARNINGS
          to change the pin multiplexing setup.  When there are no warnings
          printed, it's safe to deselect OMAP_MUX for your product.
-config OMAP_IOMMU_IVA2
-        bool
 config OMAP_MPU_TIMER
        bool "Use mpu timer"
        depends on ARCH_OMAP1
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 01619c2910e3..5f5b975887fc 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2000,6 +2000,12 @@ void omap_dma_global_context_restore(void)
                        omap_clear_dma(ch);
 }
+struct omap_system_dma_plat_info *omap_get_plat_info(void)
+{
+        return p;
+}
+EXPORT_SYMBOL_GPL(omap_get_plat_info);
 static int omap_system_dma_probe(struct platform_device *pdev)
 {
        int ch, ret = 0;
@@ -2024,9 +2030,16 @@ static int omap_system_dma_probe(struct platform_device *pdev)
        dma_lch_count           = d->lch_count;
        dma_chan_count          = dma_lch_count;
-        dma_chan                = d->chan;
        enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
+        dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count,
+                                sizeof(struct omap_dma_lch), GFP_KERNEL);
+        if (!dma_chan) {
+                dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
+                return -ENOMEM;
+        }
        if (dma_omap2plus()) {
                dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
                                                dma_lch_count, GFP_KERNEL);
@@ -2111,7 +2124,6 @@ exit_dma_irq_fail:
        }
 exit_dma_lch_fail:
-        kfree(dma_chan);
        return ret;
 }
@@ -2131,7 +2143,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
                        free_irq(dma_irq, (void *)(irq_rel + 1));
                }
        }
-        kfree(dma_chan);
        return 0;
 }
diff --git a/arch/arm/plat-omap/include/plat/timex.h b/arch/arm/plat-omap/include/plat/timex.h
deleted file mode 100644
index e27d2daa7790..000000000000
--- a/arch/arm/plat-omap/include/plat/timex.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/timex.h
- *
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author:  Greg Lonnon <glonnon@ridgerun.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
-#define __ASM_ARCH_OMAP_TIMEX_H
-#define CLOCK_TICK_RATE         (HZ * 100000UL)
-#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 830ff07f3385..3ec6e8e8d368 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -595,14 +595,16 @@ void __init orion_spi_1_init(unsigned long mapbase)
 /*****************************************************************************
 * Watchdog
 ****************************************************************************/
-static struct resource orion_wdt_resource =
+static struct resource orion_wdt_resource[] = {
-                DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x28);
+                DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
+                DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
+};
 static struct platform_device orion_wdt_device = {
        .name           = "orion_wdt",
        .id             = -1,
-        .num_resources  = 1,
+        .num_resources  = ARRAY_SIZE(orion_wdt_resource),
-        .resource       = &orion_wdt_resource,
+        .resource       = orion_wdt_resource,
 };
 void __init orion_wdt_init(void)
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 58645a58d0d8..243dfcb2ca0e 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -9,7 +9,7 @@ config PLAT_SAMSUNG
        depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS
        default y
        select GENERIC_IRQ_CHIP
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        help
          Base platform code for all Samsung SoC based systems
@@ -19,7 +19,7 @@ config PLAT_S5P
        default y
        select ARCH_REQUIRE_GPIOLIB
        select ARM_VIC
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        select PLAT_SAMSUNG
        select S3C_GPIO_TRACK
        select S5P_GPIO_DRVSTR
@@ -427,8 +427,7 @@ comment "Power management"
 config SAMSUNG_PM_DEBUG
        bool "S3C2410 PM Suspend debug"
-        depends on PM
+        depends on PM && DEBUG_KERNEL && DEBUG_S3C_UART
-        select DEBUG_LL
        help
          Say Y here if you want verbose debugging from the PM Suspend and
          Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
@@ -445,7 +444,8 @@ config S3C_PM_DEBUG_LED_SMDK
 config SAMSUNG_PM_CHECK
        bool "S3C2410 PM Suspend Memory CRC"
-        depends on PM && CRC32
+        depends on PM
+        select CRC32
        help
          Enable the PM code's memory area checksum over sleep. This option
          will generate CRCs of all blocks of memory, and store them before
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 9267d29549b4..25c826ed3b65 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -47,9 +47,11 @@ obj-$(CONFIG_SAMSUNG_DMADEV)	+= dma-ops.o
 # PM support
+obj-$(CONFIG_PM_SLEEP)          += pm-common.o
 obj-$(CONFIG_SAMSUNG_PM)        += pm.o
 obj-$(CONFIG_SAMSUNG_PM_GPIO)   += pm-gpio.o
 obj-$(CONFIG_SAMSUNG_PM_CHECK)  += pm-check.o
+obj-$(CONFIG_SAMSUNG_PM_DEBUG)  += pm-debug.o
 obj-$(CONFIG_SAMSUNG_WAKEMASK)  += wakeup-mask.o
 obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 47c9fad43f00..d103ac1a52af 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -43,7 +43,6 @@
 #include <linux/debugfs.h>
 #endif
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <plat/cpu-freq.h>
@@ -52,7 +51,7 @@
 #include <plat/cpu.h>
 #include <linux/serial_core.h>
-#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
+#include <linux/serial_s3c.h> /* for s3c24xx_uart_devs */
 /* clock information */
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
index 46b426e8aff5..364963a0a344 100644
--- a/arch/arm/plat-samsung/cpu.c
+++ b/arch/arm/plat-samsung/cpu.c
@@ -28,13 +28,6 @@ unsigned int samsung_rev(void)
 }
 EXPORT_SYMBOL(samsung_rev);
-void __init s3c24xx_init_cpu(void)
-{
-        /* nothing here yet */
-        samsung_cpu_rev = 0;
-}
 void __init s3c64xx_init_cpu(void)
 {
        samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index ac07e871f6a7..ead4f1c94058 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -18,6 +18,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/slab.h>
@@ -30,6 +31,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mmc/host.h>
 #include <linux/ioport.h>
+#include <linux/sizes.h>
 #include <linux/platform_data/s3c-hsudc.h>
 #include <linux/platform_data/s3c-hsotg.h>
 #include <linux/platform_data/dma-s3c24xx.h>
@@ -41,7 +43,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
-#include <mach/hardware.h>
 #include <mach/dma.h>
 #include <mach/irqs.h>
 #include <mach/map.h>
@@ -64,7 +65,6 @@
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/usb-phy.h>
-#include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
 #include <linux/platform_data/spi-s3c64xx.h>
@@ -744,10 +744,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
        if (!pd) {
                pd = &default_i2c_data;
-                if (soc_is_exynos4210() ||
+                if (soc_is_s5pv210())
-                    soc_is_exynos4212() || soc_is_exynos4412())
-                        pd->bus_num = 8;
-                else if (soc_is_s5pv210())
                        pd->bus_num = 3;
                else
                        pd->bus_num = 0;
@@ -764,10 +761,7 @@ void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
 {
        struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
-        if (soc_is_exynos4210() ||
+        if (soc_is_s5pv210())
-            soc_is_exynos4212() || soc_is_exynos4412())
-                pd->hdmiphy_bus = 8;
-        else if (soc_is_s5pv210())
                pd->hdmiphy_bus = 3;
        else
                pd->hdmiphy_bus = 0;
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb341355..5992b8dd9b89 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -20,6 +20,9 @@
 extern unsigned long samsung_cpu_id;
+#define S3C2410_CPU_ID          0x32410000
+#define S3C2410_CPU_MASK        0xFFFFFFFF
 #define S3C24XX_CPU_ID          0x32400000
 #define S3C24XX_CPU_MASK        0xFFF00000
@@ -56,6 +59,7 @@ static inline int is_samsung_##name(void)	\
        return ((samsung_cpu_id & mask) == (id & mask));        \
 }
+IS_SAMSUNG_CPU(s3c2410, S3C2410_CPU_ID, S3C2410_CPU_MASK)
 IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
@@ -76,8 +80,10 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
    defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \
    defined(CONFIG_CPU_S3C2443)
 # define soc_is_s3c24xx()       is_samsung_s3c24xx()
+# define soc_is_s3c2410()       is_samsung_s3c2410()
 #else
 # define soc_is_s3c24xx()       0
+# define soc_is_s3c2410()       0
 #endif
 #if defined(CONFIG_CPU_S3C2412)
@@ -160,6 +166,10 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5440()    0
 #endif
+#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
+                          soc_is_exynos4412())
+#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 #ifndef KHZ
@@ -199,7 +209,6 @@ extern void s5p_init_irq(u32 *vic, u32 num_vic);
 extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
-extern void s3c24xx_init_cpu(void);
 extern void s3c64xx_init_cpu(void);
 extern void s5p_init_cpu(void __iomem *cpuid_addr);
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
index e6d7c42d68b6..033654e91e22 100644
--- a/arch/arm/plat-samsung/include/plat/mfc.h
+++ b/arch/arm/plat-samsung/include/plat/mfc.h
@@ -32,7 +32,4 @@ struct s5p_mfc_dt_meminfo {
 void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
                                phys_addr_t lbase, unsigned int lsize);
-int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
-                                int depth, void *data);
 #endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-samsung/include/plat/pm-common.h b/arch/arm/plat-samsung/include/plat/pm-common.h
new file mode 100644
index 000000000000..8705f9e0e288
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pm-common.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *      Tomasz Figa <t.figa@samsung.com>
+ * Copyright (c) 2004 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Written by Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __PLAT_SAMSUNG_PM_COMMON_H
+#define __PLAT_SAMSUNG_PM_COMMON_H __FILE__
+#include <linux/irq.h>
+/* sleep save info */
+/**
+ * struct sleep_save - save information for shared peripherals.
+ * @reg: Pointer to the register to save.
+ * @val: Holder for the value saved from reg.
+ *
+ * This describes a list of registers which is used by the pm core and
+ * other subsystem to save and restore register values over suspend.
+ */
+struct sleep_save {
+        void __iomem    *reg;
+        unsigned long   val;
+};
+#define SAVE_ITEM(x) \
+        { .reg = (x) }
+/* helper functions to save/restore lists of registers. */
+extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count);
+/* PM debug functions */
+/**
+ * struct pm_uart_save - save block for core UART
+ * @ulcon: Save value for S3C2410_ULCON
+ * @ucon: Save value for S3C2410_UCON
+ * @ufcon: Save value for S3C2410_UFCON
+ * @umcon: Save value for S3C2410_UMCON
+ * @ubrdiv: Save value for S3C2410_UBRDIV
+ *
+ * Save block for UART registers to be held over sleep and restored if they
+ * are needed (say by debug).
+*/
+struct pm_uart_save {
+        u32     ulcon;
+        u32     ucon;
+        u32     ufcon;
+        u32     umcon;
+        u32     ubrdiv;
+        u32     udivslot;
+};
+#ifdef CONFIG_SAMSUNG_PM_DEBUG
+/**
+ * s3c_pm_dbg() - low level debug function for use in suspend/resume.
+ * @msg: The message to print.
+ *
+ * This function is used mainly to debug the resume process before the system
+ * can rely on printk/console output. It uses the low-level debugging output
+ * routine printascii() to do its work.
+ */
+extern void s3c_pm_dbg(const char *msg, ...);
+/**
+ * s3c_pm_debug_init() - suspend/resume low level debug initialization.
+ * @base: Virtual base of UART to use for suspend/resume debugging.
+ *
+ * This function needs to be called before S3C_PMDBG() can be used, to set up
+ * UART port base address and configuration.
+ */
+extern void s3c_pm_debug_init(void);
+#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
+extern void s3c_pm_save_uarts(void);
+extern void s3c_pm_restore_uarts(void);
+#else
+#define S3C_PMDBG(fmt...) pr_debug(fmt)
+#define s3c_pm_debug_init() do { } while (0)
+static inline void s3c_pm_save_uarts(void) { }
+static inline void s3c_pm_restore_uarts(void) { }
+#endif
+/* suspend memory checking */
+#ifdef CONFIG_SAMSUNG_PM_CHECK
+extern void s3c_pm_check_prepare(void);
+extern void s3c_pm_check_restore(void);
+extern void s3c_pm_check_cleanup(void);
+extern void s3c_pm_check_store(void);
+#else
+#define s3c_pm_check_prepare() do { } while (0)
+#define s3c_pm_check_restore() do { } while (0)
+#define s3c_pm_check_cleanup() do { } while (0)
+#define s3c_pm_check_store()   do { } while (0)
+#endif
+#endif
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index ff6063f0d5ea..e17d871b934c 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -15,7 +15,7 @@
 * management
 */
-#include <linux/irq.h>
+#include <plat/pm-common.h>
 struct device;
@@ -54,56 +54,10 @@ extern int (*pm_cpu_sleep)(unsigned long);
 extern unsigned long s3c_pm_flags;
-extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
 /* from sleep.S */
 extern int s3c2410_cpu_suspend(unsigned long);
-/* sleep save info */
-/**
- * struct sleep_save - save information for shared peripherals.
- * @reg: Pointer to the register to save.
- * @val: Holder for the value saved from reg.
- *
- * This describes a list of registers which is used by the pm core and
- * other subsystem to save and restore register values over suspend.
- */
-struct sleep_save {
-        void __iomem    *reg;
-        unsigned long   val;
-};
-#define SAVE_ITEM(x) \
-        { .reg = (x) }
-/**
- * struct pm_uart_save - save block for core UART
- * @ulcon: Save value for S3C2410_ULCON
- * @ucon: Save value for S3C2410_UCON
- * @ufcon: Save value for S3C2410_UFCON
- * @umcon: Save value for S3C2410_UMCON
- * @ubrdiv: Save value for S3C2410_UBRDIV
- *
- * Save block for UART registers to be held over sleep and restored if they
- * are needed (say by debug).
-*/
-struct pm_uart_save {
-        u32     ulcon;
-        u32     ucon;
-        u32     ufcon;
-        u32     umcon;
-        u32     ubrdiv;
-        u32     udivslot;
-};
-/* helper functions to save/restore lists of registers. */
-extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
-extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count);
-extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count);
 #ifdef CONFIG_SAMSUNG_PM
 extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
 extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
@@ -114,24 +68,6 @@ extern void s3c_cpu_resume(void);
 #define s3c_cpu_resume NULL
 #endif
-/* PM debug functions */
-#ifdef CONFIG_SAMSUNG_PM_DEBUG
-/**
- * s3c_pm_dbg() - low level debug function for use in suspend/resume.
- * @msg: The message to print.
- *
- * This function is used mainly to debug the resume process before the system
- * can rely on printk/console output. It uses the low-level debugging output
- * routine printascii() to do its work.
- */
-extern void s3c_pm_dbg(const char *msg, ...);
-#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
-#else
-#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
-#endif
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
 /**
 * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
@@ -144,20 +80,6 @@ extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
 static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
 #endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
-/* suspend memory checking */
-#ifdef CONFIG_SAMSUNG_PM_CHECK
-extern void s3c_pm_check_prepare(void);
-extern void s3c_pm_check_restore(void);
-extern void s3c_pm_check_cleanup(void);
-extern void s3c_pm_check_store(void);
-#else
-#define s3c_pm_check_prepare() do { } while(0)
-#define s3c_pm_check_restore() do { } while(0)
-#define s3c_pm_check_cleanup() do { } while(0)
-#define s3c_pm_check_store()   do { } while(0)
-#endif
 /**
 * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
 *
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
deleted file mode 100644
index f05f2afa440d..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <linux/serial_s3c.h>
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
deleted file mode 100644
index f48dc0a4736c..000000000000
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/uncompress.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_PLAT_UNCOMPRESS_H
-#define __ASM_PLAT_UNCOMPRESS_H
-typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
-/* uart setup */
-unsigned int fifo_mask;
-unsigned int fifo_max;
-volatile u8 *uart_base;
-/* forward declerations */
-static void arch_detect_cpu(void);
-/* defines for UART registers */
-#include <plat/regs-serial.h>
-/* working in physical space... */
-#define S3C_WDOGREG(x)  ((S3C_PA_WDT + (x)))
-#define S3C2410_WTCON   S3C_WDOGREG(0x00)
-#define S3C2410_WTDAT   S3C_WDOGREG(0x04)
-#define S3C2410_WTCNT   S3C_WDOGREG(0x08)
-#define S3C2410_WTCON_RSTEN     (1 << 0)
-#define S3C2410_WTCON_ENABLE    (1 << 5)
-#define S3C2410_WTCON_DIV128    (3 << 3)
-#define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX         (14)
-static __inline__ void
-uart_wr(unsigned int reg, unsigned int val)
-{
-        volatile unsigned int *ptr;
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        *ptr = val;
-}
-static __inline__ unsigned int
-uart_rd(unsigned int reg)
-{
-        volatile unsigned int *ptr;
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        return *ptr;
-}
-/* we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
-*/
-static void putc(int ch)
-{
-        if (!config_enabled(CONFIG_DEBUG_LL))
-                return;
-        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-                int level;
-                while (1) {
-                        level = uart_rd(S3C2410_UFSTAT);
-                        level &= fifo_mask;
-                        if (level < fifo_max)
-                                break;
-                }
-        } else {
-                /* not using fifos */
-                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-                        barrier();
-        }
-        /* write byte to transmission register */
-        uart_wr(S3C2410_UTXH, ch);
-}
-static inline void flush(void)
-{
-}
-#define __raw_writel(d, ad)                     \
-        do {                                                    \
-                *((volatile unsigned int __force *)(ad)) = (d); \
-        } while (0)
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-static void arch_decomp_error(const char *x)
-{
-        putstr("\n\n");
-        putstr(x);
-        putstr("\n\n -- System resetting\n");
-        __raw_writel(0x4000, S3C2410_WTDAT);
-        __raw_writel(0x4000, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-        while(1);
-}
-#define arch_error arch_decomp_error
-#endif
-#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
-static inline void arch_enable_uart_fifo(void)
-{
-        u32 fifocon;
-        if (!config_enabled(CONFIG_DEBUG_LL))
-                return;
-        fifocon = uart_rd(S3C2410_UFCON);
-        if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
-                fifocon |= S3C2410_UFCON_RESETBOTH;
-                uart_wr(S3C2410_UFCON, fifocon);
-                /* wait for fifo reset to complete */
-                while (1) {
-                        fifocon = uart_rd(S3C2410_UFCON);
-                        if (!(fifocon & S3C2410_UFCON_RESETBOTH))
-                                break;
-                }
-                uart_wr(S3C2410_UFCON, S3C2410_UFCON_FIFOMODE);
-        }
-}
-#else
-#define arch_enable_uart_fifo() do { } while(0)
-#endif
-static void
-arch_decomp_setup(void)
-{
-        /* we may need to setup the uart(s) here if we are not running
-         * on an BAST... the BAST will have left the uarts configured
-         * after calling linux.
-         */
-        arch_detect_cpu();
-        /* Enable the UART FIFOs if they where not enabled and our
-         * configuration says we should turn them on.
-         */
-        arch_enable_uart_fifo();
-}
-#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index aa9511b6914a..a1f925f3121f 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -21,11 +21,10 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
-#include <mach/hardware.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -33,8 +32,6 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
-#include <plat/regs-serial.h>
 static struct cpu_table *cpu;
 static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
@@ -97,7 +94,9 @@ void __init s3c24xx_init_clocks(int xtal)
 #if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
 static int nr_uarts __initdata = 0;
+#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
 static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
+#endif
 /* s3c24xx_init_uartdevs
 *
@@ -112,6 +111,7 @@ void __init s3c24xx_init_uartdevs(char *name,
                                  struct s3c24xx_uart_resources *res,
                                  struct s3c2410_uartcfg *cfg, int no)
 {
+#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
        struct platform_device *platdev;
        struct s3c2410_uartcfg *cfgptr = uart_cfgs;
        struct s3c24xx_uart_resources *resp;
@@ -134,6 +134,7 @@ void __init s3c24xx_init_uartdevs(char *name,
        }
        nr_uarts = no;
+#endif
 }
 void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c
index 3cbd62666b1e..04aff2c31b46 100644
--- a/arch/arm/plat-samsung/pm-check.c
+++ b/arch/arm/plat-samsung/pm-check.c
@@ -19,7 +19,7 @@
 #include <linux/ioport.h>
 #include <linux/slab.h>
-#include <plat/pm.h>
+#include <plat/pm-common.h>
 #if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1
 #error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value
diff --git a/arch/arm/plat-samsung/pm-common.c b/arch/arm/plat-samsung/pm-common.c
new file mode 100644
index 000000000000..515cd53372bd
--- /dev/null
+++ b/arch/arm/plat-samsung/pm-common.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *      Tomasz Figa <t.figa@samsung.com>
+ * Copyright (C) 2008 Openmoko, Inc.
+ * Copyright (C) 2004-2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung common power management helper functions.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <plat/pm-common.h>
+/* helper functions to save and restore register state */
+/**
+ * s3c_pm_do_save() - save a set of registers for restoration on resume.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Run through the list of registers given, saving their contents in the
+ * array for later restoration when we wakeup.
+ */
+void s3c_pm_do_save(struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++) {
+                ptr->val = __raw_readl(ptr->reg);
+                S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
+        }
+}
+/**
+ * s3c_pm_do_restore() - restore register values from the save list.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Restore the register values saved from s3c_pm_do_save().
+ *
+ * Note, we do not use S3C_PMDBG() in here, as the system may not have
+ * restore the UARTs state yet
+*/
+void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++) {
+                pr_debug("restore %p (restore %08lx, was %08x)\n",
+                                ptr->reg, ptr->val, __raw_readl(ptr->reg));
+                __raw_writel(ptr->val, ptr->reg);
+        }
+}
+/**
+ * s3c_pm_do_restore_core() - early restore register values from save list.
+ *
+ * This is similar to s3c_pm_do_restore() except we try and minimise the
+ * side effects of the function in case registers that hardware might need
+ * to work has been restored.
+ *
+ * WARNING: Do not put any debug in here that may effect memory or use
+ * peripherals, as things may be changing!
+*/
+void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
+{
+        for (; count > 0; count--, ptr++)
+                __raw_writel(ptr->val, ptr->reg);
+}
diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c
new file mode 100644
index 000000000000..8f19f66388dd
--- /dev/null
+++ b/arch/arm/plat-samsung/pm-debug.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ *      Tomasz Figa <t.figa@samsung.com>
+ * Copyright (C) 2008 Openmoko, Inc.
+ * Copyright (C) 2004-2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung common power management (suspend to RAM) debug support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/serial_core.h>
+#include <linux/io.h>
+#include <asm/mach/map.h>
+#include <plat/cpu.h>
+#include <plat/pm-common.h>
+#ifdef CONFIG_SAMSUNG_ATAGS
+#include <mach/pm-core.h>
+#else
+static inline void s3c_pm_debug_init_uart(void) {}
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                           struct pm_uart_save *save) {}
+#endif
+static struct pm_uart_save uart_save;
+extern void printascii(const char *);
+void s3c_pm_dbg(const char *fmt, ...)
+{
+        va_list va;
+        char buff[256];
+        va_start(va, fmt);
+        vsnprintf(buff, sizeof(buff), fmt, va);
+        va_end(va);
+        printascii(buff);
+}
+void s3c_pm_debug_init(void)
+{
+        /* restart uart clocks so we can use them to output */
+        s3c_pm_debug_init_uart();
+}
+static inline void __iomem *s3c_pm_uart_base(void)
+{
+        unsigned long paddr;
+        unsigned long vaddr;
+        debug_ll_addr(&paddr, &vaddr);
+        return (void __iomem *)vaddr;
+}
+void s3c_pm_save_uarts(void)
+{
+        void __iomem *regs = s3c_pm_uart_base();
+        struct pm_uart_save *save = &uart_save;
+        save->ulcon = __raw_readl(regs + S3C2410_ULCON);
+        save->ucon = __raw_readl(regs + S3C2410_UCON);
+        save->ufcon = __raw_readl(regs + S3C2410_UFCON);
+        save->umcon = __raw_readl(regs + S3C2410_UMCON);
+        save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
+        if (!soc_is_s3c2410())
+                save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
+        S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
+                  regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
+}
+void s3c_pm_restore_uarts(void)
+{
+        void __iomem *regs = s3c_pm_uart_base();
+        struct pm_uart_save *save = &uart_save;
+        s3c_pm_arch_update_uart(regs, save);
+        __raw_writel(save->ulcon, regs + S3C2410_ULCON);
+        __raw_writel(save->ucon,  regs + S3C2410_UCON);
+        __raw_writel(save->ufcon, regs + S3C2410_UFCON);
+        __raw_writel(save->umcon, regs + S3C2410_UMCON);
+        __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
+        if (!soc_is_s3c2410())
+                __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
+}
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index dd4c15d0d68f..da268813901b 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -196,8 +196,7 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
        .resume = samsung_gpio_pm_2bit_resume,
 };
-#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) \
+#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
-        || defined(CONFIG_ARCH_EXYNOS)
 static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
 {
        chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -307,7 +306,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
        .save   = samsung_gpio_pm_4bit_save,
        .resume = samsung_gpio_pm_4bit_resume,
 };
-#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P || CONFIG_ARCH_EXYNOS */
+#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
 /**
 * samsung_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index e5b0f2c2d884..f8c0f9797dcf 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -17,16 +17,13 @@
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/of.h>
-#include <linux/serial_core.h>
+#include <linux/serial_s3c.h>
 #include <linux/io.h>
 #include <asm/cacheflush.h>
 #include <asm/suspend.h>
-#include <plat/regs-serial.h>
 #ifdef CONFIG_SAMSUNG_ATAGS
-#include <mach/hardware.h>
 #include <mach/map.h>
 #ifndef CONFIG_ARCH_EXYNOS
 #include <mach/regs-clock.h>
@@ -44,93 +41,6 @@
 unsigned long s3c_pm_flags;
-/* Debug code:
- *
- * This code supports debug output to the low level UARTs for use on
- * resume before the console layer is available.
-*/
-#ifdef CONFIG_SAMSUNG_PM_DEBUG
-extern void printascii(const char *);
-void s3c_pm_dbg(const char *fmt, ...)
-{
-        va_list va;
-        char buff[256];
-        va_start(va, fmt);
-        vsnprintf(buff, sizeof(buff), fmt, va);
-        va_end(va);
-        printascii(buff);
-}
-static inline void s3c_pm_debug_init(void)
-{
-        /* restart uart clocks so we can use them to output */
-        s3c_pm_debug_init_uart();
-}
-#else
-#define s3c_pm_debug_init() do { } while(0)
-#endif /* CONFIG_SAMSUNG_PM_DEBUG */
-/* Save the UART configurations if we are configured for debug. */
-unsigned char pm_uart_udivslot;
-#ifdef CONFIG_SAMSUNG_PM_DEBUG
-static struct pm_uart_save uart_save;
-static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
-{
-        void __iomem *regs = S3C_VA_UARTx(uart);
-        save->ulcon = __raw_readl(regs + S3C2410_ULCON);
-        save->ucon = __raw_readl(regs + S3C2410_UCON);
-        save->ufcon = __raw_readl(regs + S3C2410_UFCON);
-        save->umcon = __raw_readl(regs + S3C2410_UMCON);
-        save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
-        if (pm_uart_udivslot)
-                save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
-        S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
-                  uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
-}
-static void s3c_pm_save_uarts(void)
-{
-        s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
-}
-static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
-{
-        void __iomem *regs = S3C_VA_UARTx(uart);
-        s3c_pm_arch_update_uart(regs, save);
-        __raw_writel(save->ulcon, regs + S3C2410_ULCON);
-        __raw_writel(save->ucon,  regs + S3C2410_UCON);
-        __raw_writel(save->ufcon, regs + S3C2410_UFCON);
-        __raw_writel(save->umcon, regs + S3C2410_UMCON);
-        __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
-        if (pm_uart_udivslot)
-                __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
-}
-static void s3c_pm_restore_uarts(void)
-{
-        s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
-}
-#else
-static void s3c_pm_save_uarts(void) { }
-static void s3c_pm_restore_uarts(void) { }
-#endif
 /* The IRQ ext-int code goes here, it is too small to currently bother
 * with its own file. */
@@ -155,62 +65,6 @@ int s3c_irqext_wake(struct irq_data *data, unsigned int state)
        return 0;
 }
-/* helper functions to save and restore register state */
-/**
- * s3c_pm_do_save() - save a set of registers for restoration on resume.
- * @ptr: Pointer to an array of registers.
- * @count: Size of the ptr array.
- *
- * Run through the list of registers given, saving their contents in the
- * array for later restoration when we wakeup.
- */
-void s3c_pm_do_save(struct sleep_save *ptr, int count)
-{
-        for (; count > 0; count--, ptr++) {
-                ptr->val = __raw_readl(ptr->reg);
-                S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
-        }
-}
-/**
- * s3c_pm_do_restore() - restore register values from the save list.
- * @ptr: Pointer to an array of registers.
- * @count: Size of the ptr array.
- *
- * Restore the register values saved from s3c_pm_do_save().
- *
- * Note, we do not use S3C_PMDBG() in here, as the system may not have
- * restore the UARTs state yet
-*/
-void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
-{
-        for (; count > 0; count--, ptr++) {
-                printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
-                       ptr->reg, ptr->val, __raw_readl(ptr->reg));
-                __raw_writel(ptr->val, ptr->reg);
-        }
-}
-/**
- * s3c_pm_do_restore_core() - early restore register values from save list.
- *
- * This is similar to s3c_pm_do_restore() except we try and minimise the
- * side effects of the function in case registers that hardware might need
- * to work has been restored.
- *
- * WARNING: Do not put any debug in here that may effect memory or use
- * peripherals, as things may be changing!
-*/
-void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
-{
-        for (; count > 0; count--, ptr++)
-                __raw_writel(ptr->val, ptr->reg);
-}
 /* s3c2410_pm_show_resume_irqs
 *
 * print any IRQs asserted at resume time (ie, we woke from)
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index ad51f85fbd01..98087b655df0 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -122,32 +122,35 @@ device_initcall(s5p_mfc_memory_init);
 #endif
 #ifdef CONFIG_OF
-int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
+int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
                                int depth, void *data)
 {
        __be32 *prop;
        unsigned long len;
-        struct s5p_mfc_dt_meminfo *mfc_mem = data;
+        struct s5p_mfc_dt_meminfo mfc_mem;
        if (!data)
                return 0;
-        if (!of_flat_dt_is_compatible(node, mfc_mem->compatible))
+        if (!of_flat_dt_is_compatible(node, data))
                return 0;
        prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len);
        if (!prop || (len != 2 * sizeof(unsigned long)))
                return 0;
-        mfc_mem->loff = be32_to_cpu(prop[0]);
+        mfc_mem.loff = be32_to_cpu(prop[0]);
-        mfc_mem->lsize = be32_to_cpu(prop[1]);
+        mfc_mem.lsize = be32_to_cpu(prop[1]);
        prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len);
        if (!prop || (len != 2 * sizeof(unsigned long)))
                return 0;
-        mfc_mem->roff = be32_to_cpu(prop[0]);
+        mfc_mem.roff = be32_to_cpu(prop[0]);
-        mfc_mem->rsize = be32_to_cpu(prop[1]);
+        mfc_mem.rsize = be32_to_cpu(prop[1]);
+        s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize,
+                        mfc_mem.loff, mfc_mem.lsize);
        return 1;
 }
diff --git a/arch/arm/plat-samsung/s5p-dev-uart.c b/arch/arm/plat-samsung/s5p-dev-uart.c
index cafa3deddcc1..8c4487af98c8 100644
--- a/arch/arm/plat-samsung/s5p-dev-uart.c
+++ b/arch/arm/plat-samsung/s5p-dev-uart.c
@@ -18,7 +18,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
-#include <mach/hardware.h>
 #include <mach/map.h>
 #include <plat/devs.h>
diff --git a/arch/arm/plat-samsung/s5p-irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c
index 591498035916..52b16943617e 100644
--- a/arch/arm/plat-samsung/s5p-irq-pm.c
+++ b/arch/arm/plat-samsung/s5p-irq-pm.c
@@ -22,10 +22,7 @@
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#ifndef CONFIG_ARCH_EXYNOS
 #include <mach/regs-irq.h>
-#endif
 /* state for IRQs over sleep */
@@ -43,18 +40,8 @@ int s3c_irq_wake(struct irq_data *data, unsigned int state)
        unsigned long irqbit;
        unsigned int irq_rtc_tic, irq_rtc_alarm;
-#ifdef CONFIG_ARCH_EXYNOS
-        if (soc_is_exynos5250()) {
-                irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC;
-                irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM;
-        } else {
-                irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC;
-                irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM;
-        }
-#else
        irq_rtc_tic = IRQ_RTC_TIC;
        irq_rtc_alarm = IRQ_RTC_ALARM;
-#endif
        if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
                irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S
index a030e7301da8..c5001659bdf8 100644
--- a/arch/arm/plat-samsung/s5p-sleep.S
+++ b/arch/arm/plat-samsung/s5p-sleep.S
@@ -23,18 +23,7 @@
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
-#define CPU_MASK        0xff0ffff0
-#define CPU_CORTEX_A9   0x410fc090
-/*
- *       The following code is located into the .data section. This is to
- *       allow l2x0_regs_phys to be accessed with a relative load while we
- *       can't rely on any MMU translation. We could have put l2x0_regs_phys
- *       in the .text section as well, but some setups might insist on it to
- *       be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
- */
        .data
        .align
@@ -53,37 +42,5 @@
         */
 ENTRY(s3c_cpu_resume)
-#ifdef CONFIG_CACHE_L2X0
-        mrc     p15, 0, r0, c0, c0, 0
-        ldr     r1, =CPU_MASK
-        and     r0, r0, r1
-        ldr     r1, =CPU_CORTEX_A9
-        cmp     r0, r1
-        bne     resume_l2on
-        adr     r0, l2x0_regs_phys
-        ldr     r0, [r0]
-        ldr     r1, [r0, #L2X0_R_PHY_BASE]
-        ldr     r2, [r1, #L2X0_CTRL]
-        tst     r2, #0x1
-        bne     resume_l2on
-        ldr     r2, [r0, #L2X0_R_AUX_CTRL]
-        str     r2, [r1, #L2X0_AUX_CTRL]
-        ldr     r2, [r0, #L2X0_R_TAG_LATENCY]
-        str     r2, [r1, #L2X0_TAG_LATENCY_CTRL]
-        ldr     r2, [r0, #L2X0_R_DATA_LATENCY]
-        str     r2, [r1, #L2X0_DATA_LATENCY_CTRL]
-        ldr     r2, [r0, #L2X0_R_PREFETCH_CTRL]
-        str     r2, [r1, #L2X0_PREFETCH_CTRL]
-        ldr     r2, [r0, #L2X0_R_PWR_CTRL]
-        str     r2, [r1, #L2X0_POWER_CTRL]
-        mov     r2, #1
-        str     r2, [r1, #L2X0_CTRL]
-resume_l2on:
-#endif
        b       cpu_resume
 ENDPROC(s3c_cpu_resume)
-#ifdef CONFIG_CACHE_L2X0
-        .globl l2x0_regs_phys
-l2x0_regs_phys:
-        .long   0
-#endif
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index 46e17492fd1f..f0759e70fb86 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -8,9 +8,12 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
+#include <linux/init.h>
+#include <linux/linkage.h>
 #include <asm/thread_info.h>
 #include <asm/vfpmacros.h>
-#include "../kernel/entry-header.S"
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
 @ VFP entry point.
 @
@@ -22,11 +25,7 @@
 @  IRQs disabled.
 @
 ENTRY(do_vfp)
-#ifdef CONFIG_PREEMPT_COUNT
+        inc_preempt_count r10, r4
-        ldr     r4, [r10, #TI_PREEMPT]  @ get preempt count
-        add     r11, r4, #1             @ increment it
-        str     r11, [r10, #TI_PREEMPT]
-#endif
        enable_irq
        ldr     r4, .LCvfp
        ldr     r11, [r10, #TI_CPU]     @ CPU number
@@ -35,12 +34,7 @@ ENTRY(do_vfp)
 ENDPROC(do_vfp)
 ENTRY(vfp_null_entry)
-#ifdef CONFIG_PREEMPT_COUNT
+        dec_preempt_count_ti r10, r4
-        get_thread_info r10
-        ldr     r4, [r10, #TI_PREEMPT]  @ get preempt count
-        sub     r11, r4, #1             @ decrement it
-        str     r11, [r10, #TI_PREEMPT]
-#endif
        mov     pc, lr
 ENDPROC(vfp_null_entry)
@@ -53,12 +47,7 @@ ENDPROC(vfp_null_entry)
        __INIT
 ENTRY(vfp_testing_entry)
-#ifdef CONFIG_PREEMPT_COUNT
+        dec_preempt_count_ti r10, r4
-        get_thread_info r10
-        ldr     r4, [r10, #TI_PREEMPT]  @ get preempt count
-        sub     r11, r4, #1             @ decrement it
-        str     r11, [r10, #TI_PREEMPT]
-#endif
        ldr     r0, VFP_arch_address
        str     r0, [r0]                @ set to non-zero value
        mov     pc, r9                  @ we have handled the fault
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 3e5d3115a2a6..be807625ed8c 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -14,10 +14,13 @@
 * r10 points at the start of the private FP workspace in the thread structure
 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
 */
+#include <linux/init.h>
+#include <linux/linkage.h>
 #include <asm/thread_info.h>
 #include <asm/vfpmacros.h>
 #include <linux/kern_levels.h>
-#include "../kernel/entry-header.S"
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
        .macro  DBGSTR, str
 #ifdef DEBUG
@@ -179,12 +182,7 @@ vfp_hw_state_valid:
                                        @ else it's one 32-bit instruction, so
                                        @ always subtract 4 from the following
                                        @ instruction address.
-#ifdef CONFIG_PREEMPT_COUNT
+        dec_preempt_count_ti r10, r4
-        get_thread_info r10
-        ldr     r4, [r10, #TI_PREEMPT]  @ get preempt count
-        sub     r11, r4, #1             @ decrement it
-        str     r11, [r10, #TI_PREEMPT]
-#endif
        mov     pc, r9                  @ we think we have handled things
@@ -203,12 +201,7 @@ look_for_VFP_exceptions:
        @ not recognised by VFP
        DBGSTR  "not VFP"
-#ifdef CONFIG_PREEMPT_COUNT
+        dec_preempt_count_ti r10, r4
-        get_thread_info r10
-        ldr     r4, [r10, #TI_PREEMPT]  @ get preempt count
-        sub     r11, r4, #1             @ decrement it
-        str     r11, [r10, #TI_PREEMPT]
-#endif
        mov     pc, lr
 process_exception:
diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c
index b31ee1b275b0..97baf4427817 100644
--- a/arch/arm/xen/p2m.c
+++ b/arch/arm/xen/p2m.c
@@ -146,6 +146,38 @@ unsigned long __mfn_to_pfn(unsigned long mfn)
 }
 EXPORT_SYMBOL_GPL(__mfn_to_pfn);
+int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops,
+                            struct gnttab_map_grant_ref *kmap_ops,
+                            struct page **pages, unsigned int count)
+{
+        int i;
+        for (i = 0; i < count; i++) {
+                if (map_ops[i].status)
+                        continue;
+                set_phys_to_machine(map_ops[i].host_addr >> PAGE_SHIFT,
+                                    map_ops[i].dev_bus_addr >> PAGE_SHIFT);
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(set_foreign_p2m_mapping);
+int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops,
+                              struct gnttab_map_grant_ref *kmap_ops,
+                              struct page **pages, unsigned int count)
+{
+        int i;
+        for (i = 0; i < count; i++) {
+                set_phys_to_machine(unmap_ops[i].host_addr >> PAGE_SHIFT,
+                                    INVALID_P2M_ENTRY);
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(clear_foreign_p2m_mapping);
 bool __set_phys_to_machine_multi(unsigned long pfn,
                unsigned long mfn, unsigned long nr_pages)
 {
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 516d8a7ca697..e6e4d3749a6e 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -17,6 +17,7 @@ config ARM64
        select GENERIC_CLOCKEVENTS
        select GENERIC_CLOCKEVENTS_BROADCAST if SMP
        select GENERIC_CPU_AUTOPROBE
+        select GENERIC_EARLY_IOREMAP
        select GENERIC_IOMAP
        select GENERIC_IRQ_PROBE
        select GENERIC_IRQ_SHOW
@@ -47,6 +48,7 @@ config ARM64
        select NO_BOOTMEM
        select OF
        select OF_EARLY_FLATTREE
+        select OF_RESERVED_MEM
        select PERF_USE_VMALLOC
        select POWER_RESET
        select POWER_SUPPLY
@@ -65,7 +67,7 @@ config ARCH_PHYS_ADDR_T_64BIT
 config MMU
        def_bool y
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool y
 config STACKTRACE_SUPPORT
@@ -321,6 +323,8 @@ menu "CPU Power Management"
 source "drivers/cpuidle/Kconfig"
+source "kernel/power/Kconfig"
 source "drivers/cpufreq/Kconfig"
 endmenu
diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug
index 835c559786bd..d10ec334c93b 100644
--- a/arch/arm64/Kconfig.debug
+++ b/arch/arm64/Kconfig.debug
@@ -6,6 +6,20 @@ config FRAME_POINTER
        bool
        default y
+config STRICT_DEVMEM
+        bool "Filter access to /dev/mem"
+        depends on MMU
+        help
+          If this option is disabled, you allow userspace (root) access to all
+          of memory, including kernel and userspace memory. Accidental
+          access to this is obviously disastrous, but specific access can
+          be used by people debugging the kernel.
+          If this option is switched on, the /dev/mem file only allows
+          userspace access to memory mapped peripherals.
+          If in doubt, say Y.
 config EARLY_PRINTK
        bool "Early printk support"
        default y
diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
index 4bca4923fc0b..83f71b3004a8 100644
--- a/arch/arm64/include/asm/Kbuild
+++ b/arch/arm64/include/asm/Kbuild
@@ -10,6 +10,7 @@ generic-y += delay.h
 generic-y += div64.h
 generic-y += dma.h
 generic-y += emergency-restart.h
+generic-y += early_ioremap.h
 generic-y += errno.h
 generic-y += ftrace.h
 generic-y += hash.h
diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h
new file mode 100644
index 000000000000..5f7bfe6df723
--- /dev/null
+++ b/arch/arm64/include/asm/fixmap.h
@@ -0,0 +1,67 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ * Copyright (C) 2013 Mark Salter <msalter@redhat.com>
+ *
+ * Adapted from arch/x86_64 version.
+ *
+ */
+#ifndef _ASM_ARM64_FIXMAP_H
+#define _ASM_ARM64_FIXMAP_H
+#ifndef __ASSEMBLY__
+#include <linux/kernel.h>
+#include <asm/page.h>
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process.
+ *
+ * These 'compile-time allocated' memory buffers are
+ * page-sized. Use set_fixmap(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ */
+enum fixed_addresses {
+        FIX_EARLYCON_MEM_BASE,
+        __end_of_permanent_fixed_addresses,
+        /*
+         * Temporary boot-time mappings, used by early_ioremap(),
+         * before ioremap() is functional.
+         */
+#ifdef CONFIG_ARM64_64K_PAGES
+#define NR_FIX_BTMAPS           4
+#else
+#define NR_FIX_BTMAPS           64
+#endif
+#define FIX_BTMAPS_SLOTS        7
+#define TOTAL_FIX_BTMAPS        (NR_FIX_BTMAPS * FIX_BTMAPS_SLOTS)
+        FIX_BTMAP_END = __end_of_permanent_fixed_addresses,
+        FIX_BTMAP_BEGIN = FIX_BTMAP_END + TOTAL_FIX_BTMAPS - 1,
+        __end_of_fixed_addresses
+};
+#define FIXADDR_SIZE    (__end_of_permanent_fixed_addresses << PAGE_SHIFT)
+#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
+#define FIXMAP_PAGE_IO     __pgprot(PROT_DEVICE_nGnRE)
+extern void __early_set_fixmap(enum fixed_addresses idx,
+                               phys_addr_t phys, pgprot_t flags);
+#define __set_fixmap __early_set_fixmap
+#include <asm-generic/fixmap.h>
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASM_ARM64_FIXMAP_H */
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 7846a6bb0833..a1bef78f0303 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -27,6 +27,7 @@
 #include <asm/byteorder.h>
 #include <asm/barrier.h>
 #include <asm/pgtable.h>
+#include <asm/early_ioremap.h>
 #include <xen/xen.h>
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 21ef48d32ff2..3d6903006a8a 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -62,6 +62,7 @@
 * RW:          64bit by default, can be overriden for 32bit VMs
 * TAC:         Trap ACTLR
 * TSC:         Trap SMC
+ * TVM:         Trap VM ops (until M+C set in SCTLR_EL1)
 * TSW:         Trap cache operations by set/way
 * TWE:         Trap WFE
 * TWI:         Trap WFI
@@ -74,7 +75,7 @@
 * SWIO:        Turn set/way invalidates into set/way clean+invalidate
 */
 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
-                         HCR_BSU_IS | HCR_FB | HCR_TAC | \
+                         HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
                         HCR_AMO | HCR_IMO | HCR_FMO | \
                         HCR_SWIO | HCR_TIDCP | HCR_RW)
 #define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index b25763bc0ec4..9fcd54b1e16d 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -79,7 +79,8 @@
 #define c13_TID_URW     (TPIDR_EL0 * 2) /* Thread ID, User R/W */
 #define c13_TID_URO     (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
 #define c13_TID_PRIV    (TPIDR_EL1 * 2) /* Thread ID, Privileged */
-#define c10_AMAIR       (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
+#define c10_AMAIR0      (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
+#define c10_AMAIR1      (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
 #define c14_CNTKCTL     (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
 #define NR_CP15_REGS    (NR_SYS_REGS * 2)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 7f1f9408ff66..7d29847a893b 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -106,7 +106,6 @@ static inline bool kvm_is_write_fault(unsigned long esr)
        return true;
 }
-static inline void kvm_clean_dcache_area(void *addr, size_t size) {}
 static inline void kvm_clean_pgd(pgd_t *pgd) {}
 static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
 static inline void kvm_clean_pte(pte_t *pte) {}
@@ -122,11 +121,25 @@ static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
        pmd_val(*pmd) |= PMD_S2_RDWR;
 }
+#define kvm_pgd_addr_end(addr, end)     pgd_addr_end(addr, end)
+#define kvm_pud_addr_end(addr, end)     pud_addr_end(addr, end)
+#define kvm_pmd_addr_end(addr, end)     pmd_addr_end(addr, end)
 struct kvm;
-static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva,
+#define kvm_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
-                                              unsigned long size)
+static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
 {
+        return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
+}
+static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
+                                             unsigned long size)
+{
+        if (!vcpu_has_cache_enabled(vcpu))
+                kvm_flush_dcache_to_poc((void *)hva, size);
        if (!icache_is_aliasing()) {            /* PIPT */
                flush_icache_range(hva, hva + size);
        } else if (!icache_is_aivivt()) {       /* non ASID-tagged VIVT */
@@ -135,8 +148,9 @@ static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva,
        }
 }
-#define kvm_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
 #define kvm_virt_to_phys(x)             __virt_to_phys((unsigned long)(x))
+void stage2_flush_vm(struct kvm *kvm);
 #endif /* __ASSEMBLY__ */
 #endif /* __ARM64_KVM_MMU_H__ */
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 9dc5dc39fded..e94f9458aa6f 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -49,7 +49,7 @@
 #define PAGE_OFFSET             (UL(0xffffffffffffffff) << (VA_BITS - 1))
 #define MODULES_END             (PAGE_OFFSET)
 #define MODULES_VADDR           (MODULES_END - SZ_64M)
-#define EARLYCON_IOBASE         (MODULES_VADDR - SZ_4M)
+#define FIXADDR_TOP             (MODULES_VADDR - SZ_2M - PAGE_SIZE)
 #define TASK_SIZE_64            (UL(1) << VA_BITS)
 #ifdef CONFIG_COMPAT
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index 2494fc01896a..f600d400c07d 100644
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -27,5 +27,6 @@ typedef struct {
 extern void paging_init(void);
 extern void setup_mm_for_reboot(void);
 extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
+extern void init_mem_pgprot(void);
 #endif
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index f7af66b54cb2..5fc8a66c3924 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -120,8 +120,12 @@
 #define TCR_ORGN_WBnWA          ((UL(3) << 10) | (UL(3) << 26))
 #define TCR_ORGN_MASK           ((UL(3) << 10) | (UL(3) << 26))
 #define TCR_SHARED              ((UL(3) << 12) | (UL(3) << 28))
+#define TCR_TG0_4K              (UL(0) << 14)
 #define TCR_TG0_64K             (UL(1) << 14)
-#define TCR_TG1_64K             (UL(1) << 30)
+#define TCR_TG0_16K             (UL(2) << 14)
+#define TCR_TG1_16K             (UL(1) << 30)
+#define TCR_TG1_4K              (UL(2) << 30)
+#define TCR_TG1_64K             (UL(3) << 30)
 #define TCR_ASID16              (UL(1) << 36)
 #define TCR_TBI0                (UL(1) << 37)
diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
index 130e2be952cf..215ad4649dd7 100644
--- a/arch/arm64/include/asm/virt.h
+++ b/arch/arm64/include/asm/virt.h
@@ -22,7 +22,6 @@
 #define BOOT_CPU_MODE_EL2       (0xe12)
 #ifndef __ASSEMBLY__
-#include <asm/cacheflush.h>
 /*
 * __boot_cpu_mode records what mode CPUs were booted in.
@@ -38,20 +37,9 @@ extern u32 __boot_cpu_mode[2];
 void __hyp_set_vectors(phys_addr_t phys_vector_base);
 phys_addr_t __hyp_get_vectors(void);
-static inline void sync_boot_mode(void)
-{
-        /*
-         * As secondaries write to __boot_cpu_mode with caches disabled, we
-         * must flush the corresponding cache entries to ensure the visibility
-         * of their writes.
-         */
-        __flush_dcache_area(__boot_cpu_mode, sizeof(__boot_cpu_mode));
-}
 /* Reports the availability of HYP mode */
 static inline bool is_hyp_mode_available(void)
 {
-        sync_boot_mode();
        return (__boot_cpu_mode[0] == BOOT_CPU_MODE_EL2 &&
                __boot_cpu_mode[1] == BOOT_CPU_MODE_EL2);
 }
@@ -59,7 +47,6 @@ static inline bool is_hyp_mode_available(void)
 /* Check if the bootloader has booted CPUs in different modes */
 static inline bool is_hyp_mode_mismatched(void)
 {
-        sync_boot_mode();
        return __boot_cpu_mode[0] != __boot_cpu_mode[1];
 }
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index 14ba23c61153..ed3955a95747 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -154,13 +154,17 @@ static struct notifier_block os_lock_nb = {
 static int debug_monitors_init(void)
 {
+        cpu_notifier_register_begin();
        /* Clear the OS lock. */
        on_each_cpu(clear_os_lock, NULL, 1);
        isb();
        local_dbg_enable();
        /* Register hotplug handler. */
-        register_cpu_notifier(&os_lock_nb);
+        __register_cpu_notifier(&os_lock_nb);
+        cpu_notifier_register_done();
        return 0;
 }
 postcore_initcall(debug_monitors_init);
diff --git a/arch/arm64/kernel/early_printk.c b/arch/arm64/kernel/early_printk.c
index fbb6e1843659..ffbbdde7aba1 100644
--- a/arch/arm64/kernel/early_printk.c
+++ b/arch/arm64/kernel/early_printk.c
@@ -26,6 +26,8 @@
 #include <linux/amba/serial.h>
 #include <linux/serial_reg.h>
+#include <asm/fixmap.h>
 static void __iomem *early_base;
 static void (*printch)(char ch);
@@ -141,8 +143,10 @@ static int __init setup_early_printk(char *buf)
        }
        /* no options parsing yet */
-        if (paddr)
+        if (paddr) {
-                early_base = early_io_map(paddr, EARLYCON_IOBASE);
+                set_fixmap_io(FIX_EARLYCON_MEM_BASE, paddr);
+                early_base = (void __iomem *)fix_to_virt(FIX_EARLYCON_MEM_BASE);
+        }
        printch = match->printch;
        early_console = &early_console_dev;
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 61035d6814cb..0fd565000772 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -26,6 +26,7 @@
 #include <asm/assembler.h>
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
+#include <asm/cache.h>
 #include <asm/cputype.h>
 #include <asm/memory.h>
 #include <asm/thread_info.h>
@@ -229,7 +230,11 @@ ENTRY(set_cpu_boot_mode_flag)
        cmp     w20, #BOOT_CPU_MODE_EL2
        b.ne    1f
        add     x1, x1, #4
-1:      str     w20, [x1]                       // This CPU has booted in EL1
+1:      dc      cvac, x1                        // Clean potentially dirty cache line
+        dsb     sy
+        str     w20, [x1]                       // This CPU has booted in EL1
+        dc      civac, x1                       // Clean&invalidate potentially stale cache line
+        dsb     sy
        ret
 ENDPROC(set_cpu_boot_mode_flag)
@@ -240,8 +245,9 @@ ENDPROC(set_cpu_boot_mode_flag)
 * This is not in .bss, because we set it sufficiently early that the boot-time
 * zeroing of .bss would clobber it.
 */
-        .pushsection    .data
+        .pushsection    .data..cacheline_aligned
 ENTRY(__boot_cpu_mode)
+        .align  L1_CACHE_SHIFT
        .long   BOOT_CPU_MODE_EL2
        .long   0
        .popsection
@@ -404,10 +410,19 @@ ENDPROC(__calc_phys_offset)
 *   - identity mapping to enable the MMU (low address, TTBR0)
 *   - first few MB of the kernel linear mapping to jump to once the MMU has
 *     been enabled, including the FDT blob (TTBR1)
- *   - UART mapping if CONFIG_EARLY_PRINTK is enabled (TTBR1)
+ *   - pgd entry for fixed mappings (TTBR1)
 */
 __create_page_tables:
        pgtbl   x25, x26, x24                   // idmap_pg_dir and swapper_pg_dir addresses
+        mov     x27, lr
+        /*
+         * Invalidate the idmap and swapper page tables to avoid potential
+         * dirty cache lines being evicted.
+         */
+        mov     x0, x25
+        add     x1, x26, #SWAPPER_DIR_SIZE
+        bl      __inval_cache_range
        /*
         * Clear the idmap and swapper page tables.
@@ -461,15 +476,23 @@ __create_page_tables:
        sub     x6, x6, #1                      // inclusive range
        create_block_map x0, x7, x3, x5, x6
 1:
-#ifdef CONFIG_EARLY_PRINTK
        /*
-         * Create the pgd entry for the UART mapping. The full mapping is done
+         * Create the pgd entry for the fixed mappings.
-         * later based earlyprintk kernel parameter.
         */
-        ldr     x5, =EARLYCON_IOBASE            // UART virtual address
+        ldr     x5, =FIXADDR_TOP                // Fixed mapping virtual address
        add     x0, x26, #2 * PAGE_SIZE         // section table address
        create_pgd_entry x26, x0, x5, x6, x7
-#endif
+        /*
+         * Since the page tables have been populated with non-cacheable
+         * accesses (MMU disabled), invalidate the idmap and swapper page
+         * tables again to remove any speculatively loaded cache lines.
+         */
+        mov     x0, x25
+        add     x1, x26, #SWAPPER_DIR_SIZE
+        bl      __inval_cache_range
+        mov     lr, x27
        ret
 ENDPROC(__create_page_tables)
        .ltorg
diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
index f17f581116fc..bee789757806 100644
--- a/arch/arm64/kernel/hw_breakpoint.c
+++ b/arch/arm64/kernel/hw_breakpoint.c
@@ -913,6 +913,8 @@ static int __init arch_hw_breakpoint_init(void)
        pr_info("found %d breakpoint and %d watchpoint registers.\n",
                core_num_brps, core_num_wrps);
+        cpu_notifier_register_begin();
        /*
         * Reset the breakpoint resources. We assume that a halting
         * debugger will leave the world in a nice state for us.
@@ -927,7 +929,10 @@ static int __init arch_hw_breakpoint_init(void)
                              TRAP_HWBKPT, "hw-watchpoint handler");
        /* Register hotplug notifier. */
-        register_cpu_notifier(&hw_breakpoint_reset_nb);
+        __register_cpu_notifier(&hw_breakpoint_reset_nb);
+        cpu_notifier_register_done();
        /* Register cpu_suspend hw breakpoint restore hook */
        cpu_suspend_set_dbg_restorer(hw_breakpoint_reset);
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index e868c72a7938..baf5afb7e6a0 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1386,6 +1386,7 @@ user_backtrace(struct frame_tail __user *tail,
        return buftail.fp;
 }
+#ifdef CONFIG_COMPAT
 /*
 * The registers we're interested in are at the end of the variable
 * length saved register structure. The fp points at the end of this
@@ -1430,6 +1431,7 @@ compat_user_backtrace(struct compat_frame_tail __user *tail,
        return (struct compat_frame_tail __user *)compat_ptr(buftail.fp) - 1;
 }
+#endif /* CONFIG_COMPAT */
 void perf_callchain_user(struct perf_callchain_entry *entry,
                         struct pt_regs *regs)
@@ -1451,6 +1453,7 @@ void perf_callchain_user(struct perf_callchain_entry *entry,
                       tail && !((unsigned long)tail & 0xf))
                        tail = user_backtrace(tail, entry);
        } else {
+#ifdef CONFIG_COMPAT
                /* AARCH32 compat mode */
                struct compat_frame_tail __user *tail;
@@ -1459,6 +1462,7 @@ void perf_callchain_user(struct perf_callchain_entry *entry,
                while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
                        tail && !((unsigned long)tail & 0x3))
                        tail = compat_user_backtrace(tail, entry);
+#endif
        }
 }
diff --git a/arch/arm64/kernel/perf_regs.c b/arch/arm64/kernel/perf_regs.c
index f2d6f0a36d63..422ebd63b619 100644
--- a/arch/arm64/kernel/perf_regs.c
+++ b/arch/arm64/kernel/perf_regs.c
@@ -2,6 +2,8 @@
 #include <linux/kernel.h>
 #include <linux/perf_event.h>
 #include <linux/bug.h>
+#include <asm/compat.h>
 #include <asm/perf_regs.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 67da30741a1b..720853f70b6b 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -42,6 +42,7 @@
 #include <linux/of_fdt.h>
 #include <linux/of_platform.h>
+#include <asm/fixmap.h>
 #include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/cputable.h>
@@ -360,6 +361,9 @@ void __init setup_arch(char **cmdline_p)
        *cmdline_p = boot_command_line;
+        init_mem_pgprot();
+        early_ioremap_init();
        parse_early_param();
        arm64_memblock_init();
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 02e9d09e1d80..03244582bc55 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -27,6 +27,7 @@
 #include <asm/kvm_host.h>
 #include <asm/kvm_emulate.h>
 #include <asm/kvm_coproc.h>
+#include <asm/kvm_mmu.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
 #include <trace/events/kvm.h>
@@ -121,6 +122,48 @@ done:
 }
 /*
+ * Generic accessor for VM registers. Only called as long as HCR_TVM
+ * is set.
+ */
+static bool access_vm_reg(struct kvm_vcpu *vcpu,
+                          const struct sys_reg_params *p,
+                          const struct sys_reg_desc *r)
+{
+        unsigned long val;
+        BUG_ON(!p->is_write);
+        val = *vcpu_reg(vcpu, p->Rt);
+        if (!p->is_aarch32) {
+                vcpu_sys_reg(vcpu, r->reg) = val;
+        } else {
+                vcpu_cp15(vcpu, r->reg) = val & 0xffffffffUL;
+                if (!p->is_32bit)
+                        vcpu_cp15(vcpu, r->reg + 1) = val >> 32;
+        }
+        return true;
+}
+/*
+ * SCTLR_EL1 accessor. Only called as long as HCR_TVM is set.  If the
+ * guest enables the MMU, we stop trapping the VM sys_regs and leave
+ * it in complete control of the caches.
+ */
+static bool access_sctlr(struct kvm_vcpu *vcpu,
+                         const struct sys_reg_params *p,
+                         const struct sys_reg_desc *r)
+{
+        access_vm_reg(vcpu, p, r);
+        if (vcpu_has_cache_enabled(vcpu)) {     /* MMU+Caches enabled? */
+                vcpu->arch.hcr_el2 &= ~HCR_TVM;
+                stage2_flush_vm(vcpu->kvm);
+        }
+        return true;
+}
+/*
 * We could trap ID_DFR0 and tell the guest we don't support performance
 * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 * NAKed, so it will read the PMCR anyway.
@@ -185,32 +228,32 @@ static const struct sys_reg_desc sys_reg_descs[] = {
          NULL, reset_mpidr, MPIDR_EL1 },
        /* SCTLR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
-          NULL, reset_val, SCTLR_EL1, 0x00C50078 },
+          access_sctlr, reset_val, SCTLR_EL1, 0x00C50078 },
        /* CPACR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
          NULL, reset_val, CPACR_EL1, 0 },
        /* TTBR0_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
-          NULL, reset_unknown, TTBR0_EL1 },
+          access_vm_reg, reset_unknown, TTBR0_EL1 },
        /* TTBR1_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
-          NULL, reset_unknown, TTBR1_EL1 },
+          access_vm_reg, reset_unknown, TTBR1_EL1 },
        /* TCR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
-          NULL, reset_val, TCR_EL1, 0 },
+          access_vm_reg, reset_val, TCR_EL1, 0 },
        /* AFSR0_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
-          NULL, reset_unknown, AFSR0_EL1 },
+          access_vm_reg, reset_unknown, AFSR0_EL1 },
        /* AFSR1_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
-          NULL, reset_unknown, AFSR1_EL1 },
+          access_vm_reg, reset_unknown, AFSR1_EL1 },
        /* ESR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
-          NULL, reset_unknown, ESR_EL1 },
+          access_vm_reg, reset_unknown, ESR_EL1 },
        /* FAR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
-          NULL, reset_unknown, FAR_EL1 },
+          access_vm_reg, reset_unknown, FAR_EL1 },
        /* PAR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
          NULL, reset_unknown, PAR_EL1 },
@@ -224,17 +267,17 @@ static const struct sys_reg_desc sys_reg_descs[] = {
        /* MAIR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
-          NULL, reset_unknown, MAIR_EL1 },
+          access_vm_reg, reset_unknown, MAIR_EL1 },
        /* AMAIR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
-          NULL, reset_amair_el1, AMAIR_EL1 },
+          access_vm_reg, reset_amair_el1, AMAIR_EL1 },
        /* VBAR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
          NULL, reset_val, VBAR_EL1, 0 },
        /* CONTEXTIDR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
-          NULL, reset_val, CONTEXTIDR_EL1, 0 },
+          access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
        /* TPIDR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
          NULL, reset_unknown, TPIDR_EL1 },
@@ -305,14 +348,32 @@ static const struct sys_reg_desc sys_reg_descs[] = {
          NULL, reset_val, FPEXC32_EL2, 0x70 },
 };
-/* Trapped cp15 registers */
+/*
+ * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
+ * depending on the way they are accessed (as a 32bit or a 64bit
+ * register).
+ */
 static const struct sys_reg_desc cp15_regs[] = {
+        { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
+        { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR },
+        { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
+        { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
+        { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
+        { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
+        { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
+        { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
+        { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
+        { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
+        { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
+        { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
        /*
         * DC{C,I,CI}SW operations:
         */
        { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
        { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
        { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
        { Op1( 0), CRn( 9), CRm(12), Op2( 0), pm_fake },
        { Op1( 0), CRn( 9), CRm(12), Op2( 1), pm_fake },
        { Op1( 0), CRn( 9), CRm(12), Op2( 2), pm_fake },
@@ -326,6 +387,14 @@ static const struct sys_reg_desc cp15_regs[] = {
        { Op1( 0), CRn( 9), CRm(14), Op2( 0), pm_fake },
        { Op1( 0), CRn( 9), CRm(14), Op2( 1), pm_fake },
        { Op1( 0), CRn( 9), CRm(14), Op2( 2), pm_fake },
+        { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
+        { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
+        { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
+        { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
+        { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
+        { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
 };
 /* Target specific emulation tables */
@@ -437,6 +506,8 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
        u32 hsr = kvm_vcpu_get_hsr(vcpu);
        int Rt2 = (hsr >> 10) & 0xf;
+        params.is_aarch32 = true;
+        params.is_32bit = false;
        params.CRm = (hsr >> 1) & 0xf;
        params.Rt = (hsr >> 5) & 0xf;
        params.is_write = ((hsr & 1) == 0);
@@ -480,6 +551,8 @@ int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
        struct sys_reg_params params;
        u32 hsr = kvm_vcpu_get_hsr(vcpu);
+        params.is_aarch32 = true;
+        params.is_32bit = true;
        params.CRm = (hsr >> 1) & 0xf;
        params.Rt  = (hsr >> 5) & 0xf;
        params.is_write = ((hsr & 1) == 0);
@@ -549,6 +622,8 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
        struct sys_reg_params params;
        unsigned long esr = kvm_vcpu_get_hsr(vcpu);
+        params.is_aarch32 = false;
+        params.is_32bit = false;
        params.Op0 = (esr >> 20) & 3;
        params.Op1 = (esr >> 14) & 0x7;
        params.CRn = (esr >> 10) & 0xf;
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index d50d3722998e..d411e251412c 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -30,6 +30,8 @@ struct sys_reg_params {
        u8      Op2;
        u8      Rt;
        bool    is_write;
+        bool    is_aarch32;
+        bool    is_32bit;       /* Only valid if is_aarch32 is true */
 };
 struct sys_reg_desc {
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index c46f48b33c14..fda756875fa6 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -168,6 +168,14 @@ ENTRY(__flush_dcache_area)
 ENDPROC(__flush_dcache_area)
 /*
+ *      __inval_cache_range(start, end)
+ *      - start   - start address of region
+ *      - end     - end address of region
+ */
+ENTRY(__inval_cache_range)
+        /* FALLTHROUGH */
+/*
 *      __dma_inv_range(start, end)
 *      - start   - virtual start address of region
 *      - end     - virtual end address of region
@@ -175,14 +183,22 @@ ENDPROC(__flush_dcache_area)
 __dma_inv_range:
        dcache_line_size x2, x3
        sub     x3, x2, #1
-        bic     x0, x0, x3
+        tst     x1, x3                          // end cache line aligned?
        bic     x1, x1, x3
-1:      dc      ivac, x0                        // invalidate D / U line
+        b.eq    1f
-        add     x0, x0, x2
+        dc      civac, x1                       // clean & invalidate D / U line
+1:      tst     x0, x3                          // start cache line aligned?
+        bic     x0, x0, x3
+        b.eq    2f
+        dc      civac, x0                       // clean & invalidate D / U line
+        b       3f
+2:      dc      ivac, x0                        // invalidate D / U line
+3:      add     x0, x0, x2
        cmp     x0, x1
-        b.lo    1b
+        b.lo    2b
        dsb     sy
        ret
+ENDPROC(__inval_cache_range)
 ENDPROC(__dma_inv_range)
 /*
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 88627c450a6c..51d5352e6ad5 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -161,6 +161,7 @@ void __init arm64_memblock_init(void)
                memblock_reserve(base, size);
        }
+        early_init_fdt_scan_reserved_mem();
        dma_contiguous_reserve(0);
        memblock_allow_resize();
diff --git a/arch/arm64/mm/ioremap.c b/arch/arm64/mm/ioremap.c
index 2bb1d586664c..7ec328392ae0 100644
--- a/arch/arm64/mm/ioremap.c
+++ b/arch/arm64/mm/ioremap.c
@@ -25,6 +25,10 @@
 #include <linux/vmalloc.h>
 #include <linux/io.h>
+#include <asm/fixmap.h>
+#include <asm/tlbflush.h>
+#include <asm/pgalloc.h>
 static void __iomem *__ioremap_caller(phys_addr_t phys_addr, size_t size,
                                      pgprot_t prot, void *caller)
 {
@@ -98,3 +102,84 @@ void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size)
                                __builtin_return_address(0));
 }
 EXPORT_SYMBOL(ioremap_cache);
+#ifndef CONFIG_ARM64_64K_PAGES
+static pte_t bm_pte[PTRS_PER_PTE] __page_aligned_bss;
+#endif
+static inline pmd_t * __init early_ioremap_pmd(unsigned long addr)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pgd = pgd_offset_k(addr);
+        BUG_ON(pgd_none(*pgd) || pgd_bad(*pgd));
+        pud = pud_offset(pgd, addr);
+        BUG_ON(pud_none(*pud) || pud_bad(*pud));
+        return pmd_offset(pud, addr);
+}
+static inline pte_t * __init early_ioremap_pte(unsigned long addr)
+{
+        pmd_t *pmd = early_ioremap_pmd(addr);
+        BUG_ON(pmd_none(*pmd) || pmd_bad(*pmd));
+        return pte_offset_kernel(pmd, addr);
+}
+void __init early_ioremap_init(void)
+{
+        pmd_t *pmd;
+        pmd = early_ioremap_pmd(fix_to_virt(FIX_BTMAP_BEGIN));
+#ifndef CONFIG_ARM64_64K_PAGES
+        /* need to populate pmd for 4k pagesize only */
+        pmd_populate_kernel(&init_mm, pmd, bm_pte);
+#endif
+        /*
+         * The boot-ioremap range spans multiple pmds, for which
+         * we are not prepared:
+         */
+        BUILD_BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT)
+                     != (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT));
+        if (pmd != early_ioremap_pmd(fix_to_virt(FIX_BTMAP_END))) {
+                WARN_ON(1);
+                pr_warn("pmd %p != %p\n",
+                        pmd, early_ioremap_pmd(fix_to_virt(FIX_BTMAP_END)));
+                pr_warn("fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n",
+                        fix_to_virt(FIX_BTMAP_BEGIN));
+                pr_warn("fix_to_virt(FIX_BTMAP_END):   %08lx\n",
+                        fix_to_virt(FIX_BTMAP_END));
+                pr_warn("FIX_BTMAP_END:       %d\n", FIX_BTMAP_END);
+                pr_warn("FIX_BTMAP_BEGIN:     %d\n",
+                        FIX_BTMAP_BEGIN);
+        }
+        early_ioremap_setup();
+}
+void __init __early_set_fixmap(enum fixed_addresses idx,
+                               phys_addr_t phys, pgprot_t flags)
+{
+        unsigned long addr = __fix_to_virt(idx);
+        pte_t *pte;
+        if (idx >= __end_of_fixed_addresses) {
+                BUG();
+                return;
+        }
+        pte = early_ioremap_pte(addr);
+        if (pgprot_val(flags))
+                set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));
+        else {
+                pte_clear(&init_mm, addr, pte);
+                flush_tlb_kernel_range(addr, addr+PAGE_SIZE);
+        }
+}
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index f8dc7e8fce6f..6b7e89569a3a 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -125,7 +125,7 @@ early_param("cachepolicy", early_cachepolicy);
 /*
 * Adjust the PMD section entries according to the CPU in use.
 */
-static void __init init_mem_pgprot(void)
+void __init init_mem_pgprot(void)
 {
        pteval_t default_pgprot;
        int i;
@@ -260,47 +260,6 @@ static void __init create_mapping(phys_addr_t phys, unsigned long virt,
        } while (pgd++, addr = next, addr != end);
 }
-#ifdef CONFIG_EARLY_PRINTK
-/*
- * Create an early I/O mapping using the pgd/pmd entries already populated
- * in head.S as this function is called too early to allocated any memory. The
- * mapping size is 2MB with 4KB pages or 64KB or 64KB pages.
- */
-void __iomem * __init early_io_map(phys_addr_t phys, unsigned long virt)
-{
-        unsigned long size, mask;
-        bool page64k = IS_ENABLED(CONFIG_ARM64_64K_PAGES);
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        pte_t *pte;
-        /*
-         * No early pte entries with !ARM64_64K_PAGES configuration, so using
-         * sections (pmd).
-         */
-        size = page64k ? PAGE_SIZE : SECTION_SIZE;
-        mask = ~(size - 1);
-        pgd = pgd_offset_k(virt);
-        pud = pud_offset(pgd, virt);
-        if (pud_none(*pud))
-                return NULL;
-        pmd = pmd_offset(pud, virt);
-        if (page64k) {
-                if (pmd_none(*pmd))
-                        return NULL;
-                pte = pte_offset_kernel(pmd, virt);
-                set_pte(pte, __pte((phys & mask) | PROT_DEVICE_nGnRE));
-        } else {
-                set_pmd(pmd, __pmd((phys & mask) | PROT_SECT_DEVICE_nGnRE));
-        }
-        return (void __iomem *)((virt & mask) + (phys & ~mask));
-}
-#endif
 static void __init map_mem(void)
 {
        struct memblock_region *reg;
@@ -357,7 +316,6 @@ void __init paging_init(void)
 {
        void *zero_page;
-        init_mem_pgprot();
        map_mem();
        /*
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index e085ee6ef4e2..9042aff5e9e3 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -28,14 +28,21 @@
 #include "proc-macros.S"
-#ifndef CONFIG_SMP
+#ifdef CONFIG_ARM64_64K_PAGES
-/* PTWs cacheable, inner/outer WBWA not shareable */
+#define TCR_TG_FLAGS    TCR_TG0_64K | TCR_TG1_64K
-#define TCR_FLAGS       TCR_IRGN_WBWA | TCR_ORGN_WBWA
+#else
+#define TCR_TG_FLAGS    TCR_TG0_4K | TCR_TG1_4K
+#endif
+#ifdef CONFIG_SMP
+#define TCR_SMP_FLAGS   TCR_SHARED
 #else
-/* PTWs cacheable, inner/outer WBWA shareable */
+#define TCR_SMP_FLAGS   0
-#define TCR_FLAGS       TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED
 #endif
+/* PTWs cacheable, inner/outer WBWA */
+#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
 #define MAIR(attr, mt)  ((attr) << ((mt) * 8))
 /*
@@ -209,18 +216,14 @@ ENTRY(__cpu_setup)
         * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
         * both user and kernel.
         */
-        ldr     x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \
+        ldr     x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
-                      TCR_ASID16 | TCR_TBI0 | (1 << 31)
+                        TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0
        /*
         * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
         * TCR_EL1.
         */
        mrs     x9, ID_AA64MMFR0_EL1
        bfi     x10, x9, #32, #3
-#ifdef CONFIG_ARM64_64K_PAGES
-        orr     x10, x10, TCR_TG0_64K
-        orr     x10, x10, TCR_TG1_64K
-#endif
        msr     tcr_el1, x10
        ret                                     // return to head.S
 ENDPROC(__cpu_setup)
diff --git a/arch/avr32/boards/mimc200/Makefile b/arch/avr32/boards/mimc200/Makefile
index 79c076e168a8..c740aa116755 100644
--- a/arch/avr32/boards/mimc200/Makefile
+++ b/arch/avr32/boards/mimc200/Makefile
@@ -1 +1 @@
-obj-y                           += setup.o flash.o fram.o
+obj-y                           += setup.o flash.o
diff --git a/arch/avr32/boards/mimc200/fram.c b/arch/avr32/boards/mimc200/fram.c
deleted file mode 100644
index c1466a872b9c..000000000000
--- a/arch/avr32/boards/mimc200/fram.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * FRAM driver for MIMC200 board
- *
- * Copyright 2008 Mark Jackson <mpfj@mimc.co.uk>
- *
- * This module adds *very* simply support for the system's FRAM device.
- * At the moment, this is hard-coded to the MIMC200 platform, and only
- * supports mmap().
- */
-#define FRAM_VERSION    "1.0"
-#include <linux/miscdevice.h>
-#include <linux/module.h>
-#include <linux/proc_fs.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#define FRAM_BASE       0xac000000
-#define FRAM_SIZE       0x20000
-/*
- * The are the file operation function for user access to /dev/fram
- */
-static int fram_mmap(struct file *filp, struct vm_area_struct *vma)
-{
-        int ret;
-        ret = remap_pfn_range(vma,
-                vma->vm_start,
-                virt_to_phys((void *)((unsigned long)FRAM_BASE)) >> PAGE_SHIFT,
-                vma->vm_end-vma->vm_start,
-                PAGE_SHARED);
-        if (ret != 0)
-                return -EAGAIN;
-        return 0;
-}
-static const struct file_operations fram_fops = {
-        .owner                  = THIS_MODULE,
-        .mmap                   = fram_mmap,
-        .llseek                 = noop_llseek,
-};
-#define FRAM_MINOR      0
-static struct miscdevice fram_dev = {
-        FRAM_MINOR,
-        "fram",
-        &fram_fops
-};
-static int __init
-fram_init(void)
-{
-        int ret;
-        ret = misc_register(&fram_dev);
-        if (ret) {
-                printk(KERN_ERR "fram: can't misc_register on minor=%d\n",
-                    FRAM_MINOR);
-                return ret;
-        }
-        printk(KERN_INFO "FRAM memory driver v" FRAM_VERSION "\n");
-        return 0;
-}
-static void __exit
-fram_cleanup_module(void)
-{
-        misc_deregister(&fram_dev);
-}
-module_init(fram_init);
-module_exit(fram_cleanup_module);
-MODULE_LICENSE("GPL");
-MODULE_ALIAS_MISCDEV(FRAM_MINOR);
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 9ceccef9c649..f81e7b989fff 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -34,6 +34,7 @@ config BLACKFIN
        select ARCH_WANT_IPC_PARSE_VERSION
        select GENERIC_ATOMIC64
        select GENERIC_IRQ_PROBE
+        select GENERIC_IRQ_SHOW
        select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
        select GENERIC_SMP_IDLE_THREAD
        select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
@@ -51,9 +52,6 @@ config GENERIC_BUG
 config ZONE_DMA
        def_bool y
-config GENERIC_GPIO
-        def_bool y
 config FORCE_MAX_ZONEORDER
        int
        default "14"
@@ -870,14 +868,6 @@ config SYS_BFIN_SPINLOCK_L1
          If enabled, sys_bfin_spinlock function is linked
          into L1 instruction memory. (less latency)
-config IP_CHECKSUM_L1
-        bool "Locate IP Checksum function in L1 Memory"
-        default n
-        depends on !SMP
-        help
-          If enabled, the IP Checksum function is linked
-          into L1 instruction memory. (less latency)
 config CACHELINE_ALIGNED_L1
        bool "Locate cacheline_aligned data to L1 Data Memory"
        default y if !BF54x
diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h
deleted file mode 100644
index 75cef4dc85a1..000000000000
--- a/arch/blackfin/include/asm/bfin_crc.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * bfin_crc.h - interface to Blackfin CRC controllers
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __BFIN_CRC_H__
-#define __BFIN_CRC_H__
-/* Function driver which use hardware crc must initialize the structure */
-struct crc_info {
-        /* Input data address */
-        unsigned char *in_addr;
-        /* Output data address */
-        unsigned char *out_addr;
-        /* Input or output bytes */
-        unsigned long datasize;
-        union {
-        /* CRC to compare with that of input buffer */
-        unsigned long crc_compare;
-        /* Value to compare with input data */
-        unsigned long val_verify;
-        /* Value to fill */
-        unsigned long val_fill;
-        };
-        /* Value to program the 32b CRC Polynomial */
-        unsigned long crc_poly;
-        union {
-        /* CRC calculated from the input data */
-        unsigned long crc_result;
-        /* First failed position to verify input data */
-        unsigned long pos_verify;
-        };
-        /* CRC mirror flags */
-        unsigned int bitmirr:1;
-        unsigned int bytmirr:1;
-        unsigned int w16swp:1;
-        unsigned int fdsel:1;
-        unsigned int rsltmirr:1;
-        unsigned int polymirr:1;
-        unsigned int cmpmirr:1;
-};
-/* Userspace interface */
-#define CRC_IOC_MAGIC           'C'
-#define CRC_IOC_CALC_CRC        _IOWR('C', 0x01, unsigned int)
-#define CRC_IOC_MEMCPY_CRC      _IOWR('C', 0x02, unsigned int)
-#define CRC_IOC_VERIFY_VAL      _IOWR('C', 0x03, unsigned int)
-#define CRC_IOC_FILL_VAL        _IOWR('C', 0x04, unsigned int)
-#ifdef __KERNEL__
-#include <linux/types.h>
-#include <linux/spinlock.h>
-#include <linux/miscdevice.h>
-struct crc_register {
-        u32 control;
-        u32 datacnt;
-        u32 datacntrld;
-        u32 __pad_1[2];
-        u32 compare;
-        u32 fillval;
-        u32 datafifo;
-        u32 intren;
-        u32 intrenset;
-        u32 intrenclr;
-        u32 poly;
-        u32 __pad_2[4];
-        u32 status;
-        u32 datacntcap;
-        u32 __pad_3;
-        u32 result;
-        u32 curresult;
-        u32 __pad_4[3];
-        u32 revid;
-};
-/* CRC_STATUS Masks */
-#define CMPERR                  0x00000002      /* Compare error */
-#define DCNTEXP                 0x00000010      /* datacnt register expired */
-#define IBR                     0x00010000      /* Input buffer ready */
-#define OBR                     0x00020000      /* Output buffer ready */
-#define IRR                     0x00040000      /* Immediate result readt */
-#define LUTDONE                 0x00080000      /* Look-up table generation done */
-#define FSTAT                   0x00700000      /* FIFO status */
-#define MAX_FIFO                4               /* Max fifo size */
-/* CRC_CONTROL Masks */
-#define BLKEN                   0x00000001      /* Block enable */
-#define OPMODE                  0x000000F0      /* Operation mode */
-#define OPMODE_OFFSET           4               /* Operation mode mask offset*/
-#define MODE_DMACPY_CRC         1               /* MTM CRC compute and compare */
-#define MODE_DATA_FILL          2               /* MTM data fill */
-#define MODE_CALC_CRC           3               /* MSM CRC compute and compare */
-#define MODE_DATA_VERIFY        4               /* MSM data verify */
-#define AUTOCLRZ                0x00000100      /* Auto clear to zero */
-#define AUTOCLRF                0x00000200      /* Auto clear to one */
-#define OBRSTALL                0x00001000      /* Stall on output buffer ready */
-#define IRRSTALL                0x00002000      /* Stall on immediate result ready */
-#define BITMIRR                 0x00010000      /* Mirror bits within each byte of 32-bit input data */
-#define BITMIRR_OFFSET          16              /* Mirror bits offset */
-#define BYTMIRR                 0x00020000      /* Mirror bytes of 32-bit input data */
-#define BYTMIRR_OFFSET          17              /* Mirror bytes offset */
-#define W16SWP                  0x00040000      /* Mirror uppper and lower 16-bit word of 32-bit input data */
-#define W16SWP_OFFSET           18              /* Mirror 16-bit word offset */
-#define FDSEL                   0x00080000      /* FIFO is written after input data is mirrored */
-#define FDSEL_OFFSET            19              /* Mirror FIFO offset */
-#define RSLTMIRR                0x00100000      /* CRC result registers are mirrored. */
-#define RSLTMIRR_OFFSET         20              /* Mirror CRC result offset. */
-#define POLYMIRR                0x00200000      /* CRC poly register is mirrored. */
-#define POLYMIRR_OFFSET         21              /* Mirror CRC poly offset. */
-#define CMPMIRR                 0x00400000      /* CRC compare register is mirrored. */
-#define CMPMIRR_OFFSET          22              /* Mirror CRC compare offset. */
-/* CRC_INTREN Masks */
-#define CMPERRI                 0x02            /* CRC_ERROR_INTR */
-#define DCNTEXPI                0x10            /* CRC_STATUS_INTR */
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
index 90c3c006557d..aaa0834d34aa 100644
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -9,60 +9,7 @@
 #ifndef __ASM_BFIN_TWI_H__
 #define __ASM_BFIN_TWI_H__
-#include <linux/types.h>
+#include <asm/blackfin.h>
-#include <linux/i2c.h>
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits.  So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-/*
- * bfin twi registers layout
- */
-struct bfin_twi_regs {
-        __BFP(clkdiv);
-        __BFP(control);
-        __BFP(slave_ctl);
-        __BFP(slave_stat);
-        __BFP(slave_addr);
-        __BFP(master_ctl);
-        __BFP(master_stat);
-        __BFP(master_addr);
-        __BFP(int_stat);
-        __BFP(int_mask);
-        __BFP(fifo_ctl);
-        __BFP(fifo_stat);
-        u32 __pad[20];
-        __BFP(xmt_data8);
-        __BFP(xmt_data16);
-        __BFP(rcv_data8);
-        __BFP(rcv_data16);
-};
-#undef __BFP
-struct bfin_twi_iface {
-        int                     irq;
-        spinlock_t              lock;
-        char                    read_write;
-        u8                      command;
-        u8                      *transPtr;
-        int                     readNum;
-        int                     writeNum;
-        int                     cur_mode;
-        int                     manual_stop;
-        int                     result;
-        struct i2c_adapter      adap;
-        struct completion       complete;
-        struct i2c_msg          *pmsg;
-        int                     msg_num;
-        int                     cur_msg;
-        u16                     saved_clkdiv;
-        u16                     saved_control;
-        struct bfin_twi_regs __iomem *regs_base;
-};
 #define DEFINE_TWI_REG(reg_name, reg) \
 static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
@@ -71,7 +18,6 @@ static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
        { bfin_write16(&iface->regs_base->reg, v); }
 DEFINE_TWI_REG(CLKDIV, clkdiv)
-DEFINE_TWI_REG(CONTROL, control)
 DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
 DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
 DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
@@ -80,7 +26,6 @@ DEFINE_TWI_REG(MASTER_STAT, master_stat)
 DEFINE_TWI_REG(MASTER_ADDR, master_addr)
 DEFINE_TWI_REG(INT_STAT, int_stat)
 DEFINE_TWI_REG(INT_MASK, int_mask)
-DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
 DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
 DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
 DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
@@ -113,75 +58,25 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
 }
 #endif
+static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
+{
+        return bfin_read16(&iface->regs_base->fifo_ctl);
+}
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v)
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
+{
-#define CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
+        bfin_write16(&iface->regs_base->fifo_ctl, v);
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+        SSYNC();
+}
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080  /* TWI Enable                                                                   */
-#define SCCB            0x0200  /* SCCB Compatibility Enable                                    */
-/* TWI_SLAVE_CTL Masks                                                                                                                  */
-#define SEN                     0x0001  /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002  /* Slave Address Length                                                 */
-#define STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010  /* General Call Address Matching Enabled                */
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002  /* General Call Indicator                                               */
-/* TWI_MASTER_CTL Masks                                                                                                 */
-#define MEN                     0x0001  /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002  /* Master Address Length                                        */
-#define MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008  /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010  /* Issue Stop Condition                                         */
-#define RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000  /* Serial Data Override                                         */
-#define SCLOVR          0x8000  /* Serial Clock Override                                        */
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001  /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004  /* Address Not Acknowledged                                             */
-#define DNAK            0x0008  /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010  /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020  /* Buffer Write Error                                                   */
-#define SDASEN          0x0040  /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080  /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001  /* Slave Transfer Initiated     */
-#define SCOMP           0x0002  /* Slave Transfer Complete      */
-#define SERR            0x0004  /* Slave Transfer Error         */
-#define SOVF            0x0008  /* Slave Overflow                       */
-#define MCOMP           0x0010  /* Master Transfer Complete     */
-#define MERR            0x0020  /* Master Transfer Error        */
-#define XMTSERV         0x0040  /* Transmit FIFO Service        */
-#define RCVSERV         0x0080  /* Receive FIFO Service         */
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
-#define RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
+static inline u16 read_CONTROL(struct bfin_twi_iface *iface)
-#define RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
+{
-#define RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
+        return bfin_read16(&iface->regs_base->control);
-#define RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
+}
+static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v)
+{
+        SSYNC();
+        bfin_write16(&iface->regs_base->control, v);
+}
 #endif
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index 40e9c2bbc6e3..8d1e4c2d2c36 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -316,8 +316,6 @@ static inline void disable_dma(unsigned int channel)
 }
 static inline void enable_dma(unsigned int channel)
 {
-        dma_ch[channel].regs->curr_x_count = 0;
-        dma_ch[channel].regs->curr_y_count = 0;
        dma_ch[channel].regs->cfg |= DMAEN;
 }
 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 2fd04f10cc26..89de539ed010 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -20,15 +20,6 @@
 /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
 #include <mach/irq.h>
-/*
- * pm save bfin pint registers
- */
-struct adi_pm_pint_save {
-        u32 assign;
-        u32 edge_set;
-        u32 invert_set;
-};
 #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
 # define NOP_PAD_ANOMALY_05000244 "nop; nop;"
 #else
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
index 7aa20436e799..c8f0939419be 100644
--- a/arch/blackfin/include/asm/portmux.h
+++ b/arch/blackfin/include/asm/portmux.h
@@ -18,16 +18,14 @@
 #define P_DONTCARE      0x1000
 #ifdef CONFIG_PINCTRL
-#include <asm/irq_handler.h>
+int bfin_internal_set_wake(unsigned int irq, unsigned int state);
 #define gpio_pint_regs bfin_pint_regs
 #define adi_internal_set_wake bfin_internal_set_wake
-#define peripheral_request(per, label) 0
+#define peripheral_request(per, label) (0)
 #define peripheral_free(per)
-#define peripheral_request_list(per, label) \
+#define peripheral_request_list(per, label) (0)
-        (pdev ? (IS_ERR(devm_pinctrl_get_select_default(&pdev->dev)) \
-        ? -EINVAL : 0) : 0)
 #define peripheral_free_list(per)
 #else
 int peripheral_request(unsigned short per, const char *label);
@@ -39,7 +37,7 @@ void peripheral_free_list(const unsigned short per[]);
 #include <linux/err.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <mach/portmux.h>
-#include <linux/gpio.h>
+#include <mach/gpio.h>
 #ifndef P_SPORT2_TFS
 #define P_SPORT2_TFS P_UNDEF
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
index 01232a13470d..947ad0832338 100644
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -10,6 +10,7 @@
 #include <linux/fs.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/i2c/bfin_twi.h>
 #include <asm/blackfin.h>
 #include <asm/gpio.h>
diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c
index 9277905b82cf..095de0fa044d 100644
--- a/arch/blackfin/kernel/ftrace.c
+++ b/arch/blackfin/kernel/ftrace.c
@@ -65,11 +65,8 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
        return ftrace_modify_code(ip, call, sizeof(call));
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        /* return value is done indirectly via data */
-        *(unsigned long *)data = 0;
        return 0;
 }
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index ff3d747154ac..0ba25764b8c0 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -11,6 +11,7 @@
 #include <linux/kallsyms.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/seq_file.h>
 #include <asm/irq_handler.h>
 #include <asm/trace.h>
 #include <asm/pda.h>
@@ -33,37 +34,15 @@ static struct irq_desc bad_irq_desc = {
 #endif
 #ifdef CONFIG_PROC_FS
-int show_interrupts(struct seq_file *p, void *v)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
-        int i = *(loff_t *) v, j;
+        int j;
-        struct irqaction *action;
-        unsigned long flags;
+        seq_printf(p, "%*s: ", prec, "NMI");
+        for_each_online_cpu(j)
-        if (i < NR_IRQS) {
+                seq_printf(p, "%10u ", cpu_pda[j].__nmi_count);
-                struct irq_desc *desc = irq_to_desc(i);
+        seq_printf(p, "  CORE  Non Maskable Interrupt\n");
+        seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
-                raw_spin_lock_irqsave(&desc->lock, flags);
-                action = desc->action;
-                if (!action)
-                        goto skip;
-                seq_printf(p, "%3d: ", i);
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-                seq_printf(p, " %8s", irq_desc_get_chip(desc)->name);
-                seq_printf(p, "  %s", action->name);
-                for (action = action->next; action; action = action->next)
-                        seq_printf(p, "  %s", action->name);
-                seq_putc(p, '\n');
- skip:
-                raw_spin_unlock_irqrestore(&desc->lock, flags);
-        } else if (i == NR_IRQS) {
-                seq_printf(p, "NMI: ");
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10u ", cpu_pda[j].__nmi_count);
-                seq_printf(p, "     CORE  Non Maskable Interrupt\n");
-                seq_printf(p, "Err: %10u\n",  atomic_read(&irq_err_count));
-        }
        return 0;
 }
 #endif
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index f8047ca3b339..d022112927c2 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -36,7 +36,7 @@ const char bfin_board_name[] = "ADI BF518F-EZBRD";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition ezbrd_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -61,7 +61,7 @@ static struct physmap_flash_data ezbrd_flash_data = {
 static struct resource ezbrd_flash_resource = {
        .start = 0x20000000,
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        .end   = 0x202fffff,
 #else
        .end   = 0x203fffff,
@@ -80,14 +80,14 @@ static struct platform_device ezbrd_flash_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = {
        P_MII0_ETxD0,
@@ -105,7 +105,7 @@ static const unsigned short bfin_mac_peripherals[] = {
 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
        {
-#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
+#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
                .addr = 3,
 #else
                .addr = 1,
@@ -119,7 +119,7 @@ static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
        .phydev_data = bfin_phydev_data,
        .phy_mode = PHY_INTERFACE_MODE_MII,
        .mac_peripherals = bfin_mac_peripherals,
-#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
+#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
        .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
 #endif
        .vlan1_mask = 1,
@@ -140,7 +140,7 @@ static struct platform_device bfin_mac_device = {
        }
 };
-#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
+#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
 static struct dsa_chip_data ksz8893m_switch_chip_data = {
        .mii_bus = &bfin_mii_bus.dev,
        .port_names = {
@@ -165,8 +165,7 @@ static struct platform_device ksz8893m_switch_device = {
 #endif
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -193,13 +192,13 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -216,8 +215,7 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -230,9 +228,8 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
-#if defined(CONFIG_NET_DSA_KSZ8893M) \
+#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
-        || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
        {
                .modalias = "ksz8893m",
                .max_speed_hz = 5000000,
@@ -244,7 +241,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
@@ -254,7 +251,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
        {
                .modalias               = "ad7877",
                .platform_data          = &bfin_ad7877_ts_info,
@@ -264,7 +261,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select  = 2,
        },
 #endif
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
+#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
         && defined(CONFIG_SND_SOC_WM8731_SPI)
        {
                .modalias       = "wm8731",
@@ -274,7 +271,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_0,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -282,7 +279,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 1,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        {
                .modalias = "bfin-lq035q1-spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -294,7 +291,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 };
 /* SPI controller data */
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI (0) */
 static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 6,
@@ -366,7 +363,7 @@ static struct platform_device bfin_spi1_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -465,7 +462,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -520,7 +517,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -528,7 +525,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -556,25 +553,25 @@ static struct platform_device i2c_bfin_twi_device = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
        },
 #endif
-#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_PCF8574)
        {
                I2C_BOARD_INFO("pcf8574_keypad", 0x27),
                .irq = IRQ_PF8,
        },
 #endif
-#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
        {
                I2C_BOARD_INFO("ssm2602", 0x1b),
        },
 #endif
 };
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -645,7 +642,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -667,7 +664,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
 static struct bfin_sd_host bfin_sdh_data = {
        .dma_chan = CH_RSI,
@@ -710,24 +707,24 @@ static struct platform_device *stamp_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
-#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
+#if IS_ENABLED(CONFIG_NET_DSA_KSZ8893M)
        &ksz8893m_switch_device,
 #endif
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
        &bfin_spi1_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -736,7 +733,7 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -745,15 +742,15 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -762,15 +759,15 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
        &bf51x_sdh_device,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &ezbrd_flash_device,
 #endif
 };
@@ -784,7 +781,7 @@ static int __init ezbrd_init(void)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
        /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
        peripheral_request(P_AMS2, "ParaFlash");
-#if !defined(CONFIG_SPI_BFIN5XX) && !defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if !IS_ENABLED(CONFIG_SPI_BFIN5XX)
        peripheral_request(P_AMS3, "ParaFlash");
 #endif
        return 0;
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index 0bedc737566b..240d5cb1f02c 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -36,7 +36,7 @@ const char bfin_board_name[] = "Bluetechnix TCM-BF518";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition tcm_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -73,14 +73,14 @@ static struct platform_device tcm_flash_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_MII0;
@@ -113,8 +113,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -141,13 +140,13 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -164,8 +163,7 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -178,7 +176,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -188,7 +186,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
        {
                .modalias               = "ad7877",
                .platform_data          = &bfin_ad7877_ts_info,
@@ -198,7 +196,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select  = 2,
        },
 #endif
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
+#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
         && defined(CONFIG_SND_SOC_WM8731_SPI)
        {
                .modalias       = "wm8731",
@@ -208,7 +206,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_0,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -216,7 +214,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 1,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        {
                .modalias = "bfin-lq035q1-spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -228,7 +226,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 };
 /* SPI controller data */
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI (0) */
 static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 6,
@@ -300,7 +298,7 @@ static struct platform_device bfin_spi1_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -399,7 +397,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -454,7 +452,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -482,12 +480,12 @@ static struct platform_device i2c_bfin_twi_device = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
        },
 #endif
-#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_PCF8574)
        {
                I2C_BOARD_INFO("pcf8574_keypad", 0x27),
                .irq = IRQ_PF8,
@@ -495,7 +493,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 #endif
 };
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -566,7 +564,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -588,7 +586,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
 static struct bfin_sd_host bfin_sdh_data = {
        .dma_chan = CH_RSI,
@@ -631,21 +629,21 @@ static struct platform_device *tcm_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
        &bfin_spi1_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -654,7 +652,7 @@ static struct platform_device *tcm_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -663,11 +661,11 @@ static struct platform_device *tcm_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -676,15 +674,15 @@ static struct platform_device *tcm_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
        &bf51x_sdh_device,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &tcm_flash_device,
 #endif
 };
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index 1e7be62fccb6..9501bd8d9cd1 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -37,7 +37,7 @@ const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct resource musb_resources[] = {
        [0] = {
                .start  = 0xffc03800,
@@ -97,7 +97,7 @@ static struct platform_device musb_device = {
 };
 #endif
-#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
 static struct resource bf52x_ra158z_resources[] = {
        {
                .start = IRQ_PPI_ERROR,
@@ -114,7 +114,7 @@ static struct platform_device bf52x_ra158z_device = {
 };
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition ad7160eval_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -154,7 +154,7 @@ static struct platform_device ad7160eval_flash_device = {
 };
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
 static struct mtd_partition partition_info[] = {
        {
                .name = "linux kernel(nand)",
@@ -200,14 +200,14 @@ static struct platform_device bf5xx_nand_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
@@ -241,8 +241,7 @@ static struct platform_device bfin_mac_device = {
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -269,13 +268,13 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -284,8 +283,7 @@ static struct platform_device bfin_i2s = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -297,8 +295,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -306,7 +303,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 4,
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 30000000,     /* max spi clock (SCK) speed in HZ */
@@ -316,7 +313,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -326,7 +323,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
@@ -364,7 +361,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -475,7 +472,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -530,7 +527,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
 #include <linux/input/ad7160.h>
 static const struct ad7160_platform_data bfin_ad7160_ts_info = {
        .sensor_x_res = 854,
@@ -560,7 +557,7 @@ static const struct ad7160_platform_data bfin_ad7160_ts_info = {
 };
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -588,7 +585,7 @@ static struct platform_device i2c_bfin_twi_device = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
        {
                I2C_BOARD_INFO("ad7160", 0x33),
                .irq = IRQ_PH1,
@@ -597,7 +594,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 #endif
 };
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -668,7 +665,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
 #include <asm/bfin_rotary.h>
 static struct bfin_rotary_platform_data bfin_rotary_data = {
@@ -725,28 +722,28 @@ static struct platform_device *stamp_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
        &bf5xx_nand_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
        &musb_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -755,11 +752,11 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
        &bf52x_ra158z_device,
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -768,11 +765,11 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -781,15 +778,15 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
        &bfin_rotary_device,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &ad7160eval_flash_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s,
 #endif
 };
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 413d0132b66f..b1004b35db36 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -37,7 +37,7 @@ const char bfin_board_name[] = "Bluetechnix CM-BF527";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
 #include <linux/usb/isp1760.h>
 static struct resource bfin_isp1760_resources[] = {
        [0] = {
@@ -72,7 +72,7 @@ static struct platform_device bfin_isp1760_device = {
 };
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct resource musb_resources[] = {
        [0] = {
                .start  = 0xffc03800,
@@ -134,7 +134,7 @@ static struct platform_device musb_device = {
 };
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
 static struct mtd_partition partition_info[] = {
        {
                .name = "linux kernel(nand)",
@@ -180,7 +180,7 @@ static struct platform_device bf5xx_nand_device = {
 };
 #endif
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
 static struct resource bfin_pcmcia_cf_resources[] = {
        {
                .start = 0x20310000, /* IO PORT */
@@ -209,14 +209,14 @@ static struct platform_device bfin_pcmcia_cf_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -249,7 +249,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
 static struct resource dm9000_resources[] = {
        [0] = {
                .start  = 0x203FB800,
@@ -276,7 +276,7 @@ static struct platform_device dm9000_device = {
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
@@ -309,7 +309,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -330,8 +330,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -358,13 +357,13 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -381,8 +380,7 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -395,8 +393,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -404,7 +401,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 4,
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -414,7 +411,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
        {
                .modalias               = "ad7877",
                .platform_data          = &bfin_ad7877_ts_info,
@@ -424,7 +421,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select  = 2,
        },
 #endif
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
+#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
         && defined(CONFIG_SND_SOC_WM8731_SPI)
        {
                .modalias       = "wm8731",
@@ -434,7 +431,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_0,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -444,7 +441,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
@@ -482,7 +479,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
 static struct mtd_partition cm_partitions[] = {
        {
                .name   = "bootloader(nor)",
@@ -531,7 +528,7 @@ static struct platform_device cm_flash_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -642,7 +639,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -697,7 +694,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -725,25 +722,25 @@ static struct platform_device i2c_bfin_twi_device = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
        },
 #endif
-#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_PCF8574)
        {
                I2C_BOARD_INFO("pcf8574_keypad", 0x27),
                .irq = IRQ_PF8,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_7393)
        {
                I2C_BOARD_INFO("bfin-adv7393", 0x2B),
        },
 #endif
 };
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -814,7 +811,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -861,48 +858,48 @@ static struct platform_device *cmbf527_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
        &bf5xx_nand_device,
 #endif
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
        &bfin_pcmcia_cf_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
        &bfin_isp1760_device,
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
        &musb_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
        &dm9000_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -911,7 +908,7 @@ static struct platform_device *cmbf527_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -920,11 +917,11 @@ static struct platform_device *cmbf527_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -933,11 +930,11 @@ static struct platform_device *cmbf527_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
        &cm_flash_device,
 #endif
 };
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 50bda79194e5..a3a572352769 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -36,7 +36,7 @@ const char bfin_board_name[] = "ADI BF526-EZBRD";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct resource musb_resources[] = {
        [0] = {
                .start  = 0xffc03800,
@@ -98,7 +98,7 @@ static struct platform_device musb_device = {
 };
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition ezbrd_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -138,7 +138,7 @@ static struct platform_device ezbrd_flash_device = {
 };
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
 static struct mtd_partition partition_info[] = {
        {
                .name = "bootloader(nand)",
@@ -188,7 +188,7 @@ static struct platform_device bf5xx_nand_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
@@ -196,7 +196,7 @@ static struct platform_device rtc_device = {
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
@@ -229,8 +229,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -257,13 +256,13 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -279,7 +278,7 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
 #include <linux/spi/ad7879.h>
 static const struct ad7879_platform_data bfin_ad7879_ts_info = {
        .model                  = 7879, /* Model = AD7879 */
@@ -297,8 +296,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -311,7 +309,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
@@ -321,7 +319,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
        {
                .modalias               = "ad7877",
                .platform_data          = &bfin_ad7877_ts_info,
@@ -331,7 +329,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select  = 2,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
        {
                .modalias = "ad7879",
                .platform_data = &bfin_ad7879_ts_info,
@@ -342,7 +340,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
-#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
+#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
         && defined(CONFIG_SND_SOC_WM8731_SPI)
        {
                .modalias       = "wm8731",
@@ -352,7 +350,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_0,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -360,7 +358,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 1,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        {
                .modalias = "bfin-lq035q1-spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -371,7 +369,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
@@ -409,7 +407,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -520,7 +518,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -575,7 +573,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -603,12 +601,12 @@ static struct platform_device i2c_bfin_twi_device = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
        },
 #endif
-#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_PCF8574)
        {
                I2C_BOARD_INFO("pcf8574_keypad", 0x27),
                .irq = IRQ_PF8,
@@ -616,7 +614,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 #endif
 };
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -687,7 +685,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -731,7 +729,7 @@ static struct platform_device bfin_dpmc = {
        },
 };
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
 #include <asm/bfin-lq035q1.h>
 static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
@@ -764,28 +762,28 @@ static struct platform_device *stamp_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
        &bf5xx_nand_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
        &musb_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -794,11 +792,11 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        &bfin_lq035q1_device,
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -807,11 +805,11 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -820,11 +818,11 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &ezbrd_flash_device,
 #endif
 };
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index d0a0c5e527cd..d64f565dc2a0 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -42,7 +42,7 @@ const char bfin_board_name[] = "ADI BF527-EZKIT";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
 #include <linux/usb/isp1760.h>
 static struct resource bfin_isp1760_resources[] = {
        [0] = {
@@ -77,7 +77,7 @@ static struct platform_device bfin_isp1760_device = {
 };
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct resource musb_resources[] = {
        [0] = {
                .start  = 0xffc03800,
@@ -139,7 +139,7 @@ static struct platform_device musb_device = {
 };
 #endif
-#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
 static struct resource bf52x_t350mcqb_resources[] = {
        {
@@ -157,7 +157,7 @@ static struct platform_device bf52x_t350mcqb_device = {
 };
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
 #include <asm/bfin-lq035q1.h>
 static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
@@ -184,7 +184,7 @@ static struct platform_device bfin_lq035q1_device = {
 };
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition ezkit_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -224,7 +224,7 @@ static struct platform_device ezkit_flash_device = {
 };
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
 static struct mtd_partition partition_info[] = {
        {
                .name = "bootloader(nand)",
@@ -274,7 +274,7 @@ static struct platform_device bf5xx_nand_device = {
 };
 #endif
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
 static struct resource bfin_pcmcia_cf_resources[] = {
        {
                .start = 0x20310000, /* IO PORT */
@@ -303,14 +303,14 @@ static struct platform_device bfin_pcmcia_cf_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -343,7 +343,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
 static struct resource dm9000_resources[] = {
        [0] = {
                .start  = 0x203FB800,
@@ -370,7 +370,7 @@ static struct platform_device dm9000_device = {
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
@@ -403,7 +403,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -427,8 +427,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -455,13 +454,13 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -477,7 +476,7 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
 #include <linux/spi/ad7879.h>
 static const struct ad7879_platform_data bfin_ad7879_ts_info = {
        .model                  = 7879, /* Model = AD7879 */
@@ -493,7 +492,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static const u16 bfin_snd_pin[][7] = {
        {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
@@ -541,21 +540,21 @@ static struct resource bfin_snd_resources[][4] = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s_pcm = {
        .name = "bfin-i2s-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
 static struct platform_device bfin_ac97_pcm = {
        .name = "bfin-ac97-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -567,8 +566,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-                || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
        "bfin-i2s.0",
        "spi0.4",
@@ -583,8 +581,7 @@ static struct platform_device bfin_ad1836_machine = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -597,8 +594,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -608,7 +604,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -619,7 +615,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
        {
                .modalias               = "ad7877",
                .platform_data          = &bfin_ad7877_ts_info,
@@ -629,7 +625,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select  = 2,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
        {
                .modalias = "ad7879",
                .platform_data = &bfin_ad7879_ts_info,
@@ -640,7 +636,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -648,7 +644,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 1,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        {
                .modalias = "bfin-lq035q1-spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -659,7 +655,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
@@ -697,7 +693,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -808,7 +804,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -863,7 +859,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -890,7 +886,7 @@ static struct platform_device i2c_bfin_twi_device = {
 };
 #endif
-#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
+#if IS_ENABLED(CONFIG_PMIC_ADP5520)
 #include <linux/mfd/adp5520.h>
        /*
@@ -956,54 +952,54 @@ static struct adp5520_platform_data adp5520_pdev_data = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
        },
 #endif
-#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_PCF8574)
        {
                I2C_BOARD_INFO("pcf8574_keypad", 0x27),
                .irq = IRQ_PF8,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_7393)
        {
                I2C_BOARD_INFO("bfin-adv7393", 0x2B),
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
        {
                I2C_BOARD_INFO("ad7879", 0x2C),
                .irq = IRQ_PF8,
                .platform_data = (void *)&bfin_ad7879_ts_info,
        },
 #endif
-#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
+#if IS_ENABLED(CONFIG_PMIC_ADP5520)
        {
                I2C_BOARD_INFO("pmic-adp5520", 0x32),
                .irq = IRQ_PF9,
                .platform_data = (void *)&adp5520_pdev_data,
        },
 #endif
-#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
        {
                I2C_BOARD_INFO("ssm2602", 0x1b),
        },
 #endif
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("ad5252", 0x2f),
        },
 #endif
-#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
        {
                I2C_BOARD_INFO("adau1373", 0x1A),
        },
 #endif
 };
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -1074,7 +1070,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/gpio_keys.h>
 static struct gpio_keys_button bfin_gpio_keys_table[] = {
@@ -1095,7 +1091,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
-#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
 #include <asm/bfin_rotary.h>
 static struct bfin_rotary_platform_data bfin_rotary_data = {
@@ -1153,56 +1149,56 @@ static struct platform_device *stamp_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
        &bf5xx_nand_device,
 #endif
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
        &bfin_pcmcia_cf_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
        &bfin_isp1760_device,
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
        &musb_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
        &dm9000_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
        &bf52x_t350mcqb_device,
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        &bfin_lq035q1_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -1211,7 +1207,7 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -1220,11 +1216,11 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -1233,32 +1229,31 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
        &bfin_rotary_device,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &ezkit_flash_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
        &bfin_ac97_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-        defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
        &bfin_ad1836_machine,
 #endif
 };
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index 1509c5a8a3ff..a0f5856a5ff8 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -28,8 +28,7 @@
 #include <asm/portmux.h>
 #include <asm/dpmc.h>
-#if defined(CONFIG_TOUCHSCREEN_AD7879) \
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-        || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
 #include <linux/spi/ad7879.h>
 #define LCD_BACKLIGHT_GPIO 0x40
 /* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
@@ -45,7 +44,7 @@ const char bfin_board_name[] = "TLL6527M";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct resource musb_resources[] = {
        [0] = {
                .start  = 0xffc03800,
@@ -104,7 +103,7 @@ static struct platform_device musb_device = {
 };
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
 #include <asm/bfin-lq035q1.h>
 static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
@@ -133,7 +132,7 @@ static struct platform_device bfin_lq035q1_device = {
 };
 #endif
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
 static struct mtd_partition tll6527m_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -182,7 +181,7 @@ static struct platform_device tll6527m_flash_device = {
 };
 #endif
-#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
+#if IS_ENABLED(CONFIG_GPIO_DECODER)
 /* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
 * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
 * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
@@ -215,7 +214,7 @@ static struct platform_device spi_decoded_gpio = {
 #endif
-#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
 #include <linux/input/adxl34x.h>
 static const struct adxl34x_platform_data adxl345_info = {
        .x_axis_offset = 0,
@@ -250,14 +249,14 @@ static const struct adxl34x_platform_data adxl345_info = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
@@ -290,8 +289,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -318,14 +316,13 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879) \
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-        || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
 static const struct ad7879_platform_data bfin_ad7879_ts_info = {
        .model                  = 7879, /* Model = AD7879 */
        .x_plate_ohms           = 620,  /* 620 Ohm from the touch datasheet */
@@ -343,7 +340,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -351,7 +348,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
+#if IS_ENABLED(CONFIG_GPIO_MCP23S08)
 #include <linux/spi/mcp23s08.h>
 static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
        .chip[0].is_present = true,
@@ -364,8 +361,7 @@ static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -381,7 +377,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
 /*
@@ -396,8 +392,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_0,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
-        || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
        {
                .modalias = "ad7879",
                .platform_data = &bfin_ad7879_ts_info,
@@ -409,7 +404,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 10000000,
@@ -419,7 +414,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        {
                .modalias = "bfin-lq035q1-spi",
                .max_speed_hz = 20000000,
@@ -428,7 +423,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
-#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
+#if IS_ENABLED(CONFIG_GPIO_MCP23S08)
        {
                .modalias = "mcp23s08",
                .platform_data = &bfin_mcp23s08_sys_gpio_info,
@@ -448,7 +443,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
@@ -487,7 +482,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -600,7 +595,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -655,7 +650,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -683,26 +678,25 @@ static struct platform_device i2c_bfin_twi_device = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
        },
 #endif
-#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_7393)
        {
                I2C_BOARD_INFO("bfin-adv7393", 0x2B),
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) \
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
-        || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
        {
                I2C_BOARD_INFO("ad7879", 0x2C),
                .irq = IRQ_PH14,
                .platform_data = (void *)&bfin_ad7879_ts_info,
        },
 #endif
-#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
        {
                I2C_BOARD_INFO("ssm2602", 0x1b),
        },
@@ -714,8 +708,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        {
                I2C_BOARD_INFO("ltc3576", 0x09),
        },
-#if defined(CONFIG_INPUT_ADXL34X_I2C) \
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
-        || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
        {
                I2C_BOARD_INFO("adxl34x", 0x53),
                .irq = IRQ_PH13,
@@ -724,8 +717,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 #endif
 };
-#if defined(CONFIG_SERIAL_BFIN_SPORT) \
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-        || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -823,28 +815,28 @@ static struct platform_device *tll6527m_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
        &musb_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        &bfin_lq035q1_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -853,7 +845,7 @@ static struct platform_device *tll6527m_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -862,12 +854,11 @@ static struct platform_device *tll6527m_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) \
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-        || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -876,15 +867,15 @@ static struct platform_device *tll6527m_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
        &tll6527m_flash_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s,
 #endif
-#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
+#if IS_ENABLED(CONFIG_GPIO_DECODER)
        &spi_decoded_gpio,
 #endif
 };
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 6cb7b3ed9b3d..01300f40db15 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -14,7 +14,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/irq.h>
@@ -29,7 +29,7 @@
 */
 const char bfin_board_name[] = "HV Sistemas H8606";
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
@@ -39,7 +39,7 @@ static struct platform_device rtc_device = {
 /*
 *  Driver needs to know address, irq and flag pin.
 */
- #if    defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
 static struct resource dm9000_resources[] = {
        [0] = {
                .start  = 0x20300000,
@@ -67,7 +67,7 @@ static struct platform_device dm9000_device = {
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -104,7 +104,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -125,10 +125,10 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader (spi)",
@@ -166,7 +166,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 /* Notice: for blackfin, the speed_hz is the value of register
 * SPI_BAUD, not the real baudrate */
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -180,7 +180,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
        {
                .modalias = "ad183x",
                .max_speed_hz = 16,
@@ -229,7 +229,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -280,7 +280,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -309,7 +309,7 @@ static struct platform_device bfin_sir0_device = {
 #endif
 #endif
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_8250)
 #include <linux/serial_8250.h>
 #include <linux/serial.h>
@@ -353,7 +353,7 @@ static struct platform_device serial8250_device = {
 #endif
-#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
 /*
 * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
@@ -382,43 +382,43 @@ static struct platform_device opencores_kbd_device = {
 #endif
 static struct platform_device *h8606_devices[] __initdata = {
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if     defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
        &dm9000_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
 #endif
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_8250)
        &serial8250_device,
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
        &opencores_kbd_device,
 #endif
 };
@@ -428,7 +428,7 @@ static int __init H8606_init(void)
        printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
        return 0;
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index de44a3765e59..63b0e4fe760c 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -31,7 +31,7 @@
 */
 const char bfin_board_name[] = "BlackStamp";
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
@@ -41,7 +41,7 @@ static struct platform_device rtc_device = {
 /*
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -74,7 +74,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -105,14 +105,14 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -125,7 +125,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -136,7 +136,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -146,7 +146,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
        [0] = {
@@ -184,7 +184,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -235,7 +235,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -264,7 +264,7 @@ static struct platform_device bfin_sir0_device = {
 #endif
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -335,7 +335,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -358,7 +358,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_I2C_GPIO)
 #include <linux/i2c-gpio.h>
 static struct i2c_gpio_platform_data i2c_gpio_data = {
@@ -413,32 +413,32 @@ static struct platform_device *stamp_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -447,11 +447,11 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_I2C_GPIO)
        &i2c_gpio_device,
 #endif
 };
@@ -469,7 +469,7 @@ static int __init blackstamp_init(void)
        if (ret < 0)
                return ret;
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        /*
         * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
         * the bfin-async-map driver takes care of flipping between
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index fe47e048c4e6..4ef2fb0e48d5 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -15,7 +15,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/mmc_spi.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/irq.h>
@@ -29,9 +29,9 @@
 */
 const char bfin_board_name[] = "Bluetechnix CM BF533";
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -62,14 +62,14 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80",       /* Name of spi_driver for this device */
@@ -82,7 +82,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -91,7 +91,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -140,14 +140,14 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -178,7 +178,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
 #include <linux/smsc911x.h>
 static struct resource smsc911x_resources[] = {
@@ -212,7 +212,7 @@ static struct platform_device smsc911x_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -263,7 +263,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -292,7 +292,7 @@ static struct platform_device bfin_sir0_device = {
 #endif
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -363,7 +363,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 static struct resource isp1362_hcd_resources[] = {
        {
                .start = 0x20308000,
@@ -403,7 +403,7 @@ static struct platform_device isp1362_hcd_device = {
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -426,7 +426,7 @@ static struct platform_device net2272_bfin_device = {
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition para_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -495,19 +495,19 @@ static struct platform_device *cm_bf533_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -516,31 +516,31 @@ static struct platform_device *cm_bf533_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
        &isp1362_hcd_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
        &smsc911x_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &para_flash_device,
 #endif
 };
@@ -549,7 +549,7 @@ static int __init cm_bf533_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
        return 0;
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 90fb0d14b147..3625e9eaa8a8 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -14,7 +14,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/irq.h>
@@ -29,7 +29,7 @@
 */
 const char bfin_board_name[] = "ADI BF533-EZKIT";
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
@@ -40,7 +40,7 @@ static struct platform_device rtc_device = {
 *  USB-LAN EzExtender board
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -72,7 +72,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition ezkit_partitions_a[] = {
        {
                .name       = "bootloader(nor a)",
@@ -138,7 +138,7 @@ static struct platform_device ezkit_flash_device_b = {
 };
 #endif
-#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PLATRAM)
 static struct platdata_mtd_ram sram_data_a = {
        .mapname   = "Flash A SRAM",
        .bankwidth = 2,
@@ -182,7 +182,7 @@ static struct platform_device sram_device_b = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -214,7 +214,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -227,7 +227,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -235,7 +235,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 4,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -245,7 +245,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
        [0] = {
@@ -283,7 +283,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -334,7 +334,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -363,7 +363,7 @@ static struct platform_device bfin_sir0_device = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -387,7 +387,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_I2C_GPIO)
 #include <linux/i2c-gpio.h>
 static struct i2c_gpio_platform_data i2c_gpio_data = {
@@ -435,14 +435,14 @@ static struct platform_device bfin_dpmc = {
 };
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_7393)
        {
                I2C_BOARD_INFO("bfin-adv7393", 0x2B),
        },
 #endif
 };
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -450,7 +450,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
 static struct platform_device bfin_ac97 = {
        .name = "bfin-ac97",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -462,53 +462,53 @@ static struct platform_device *ezkit_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &ezkit_flash_device_a,
        &ezkit_flash_device_b,
 #endif
-#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PLATRAM)
        &sram_device_a,
        &sram_device_b,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_I2C_GPIO)
        &i2c_gpio_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s,
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
        &bfin_ac97,
 #endif
 };
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index e303dae4e2d9..39c8e8547b82 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -15,7 +15,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <asm/irq.h>
@@ -32,7 +32,7 @@ const char bfin_board_name[] = "IP04/IP08";
 *  Driver needs to know address, irq and flag pin.
 */
 #if defined(CONFIG_BFIN532_IP0X)
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
 #include <linux/dm9000.h>
@@ -104,10 +104,10 @@ static struct platform_device dm9000_device2 = {
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,                /* if 1 - block!!! */
 };
@@ -116,7 +116,7 @@ static struct bfin5xx_spi_chip mmc_spi_chip_info = {
 /* Notice: for blackfin, the speed_hz is the value of register
 * SPI_BAUD, not the real baudrate */
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 2,
@@ -142,7 +142,7 @@ static struct platform_device spi_bfin_master_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -193,7 +193,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -222,7 +222,7 @@ static struct platform_device bfin_sir0_device = {
 #endif
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 static struct resource isp1362_hcd_resources[] = {
        {
                .start = 0x20300000,
@@ -264,29 +264,29 @@ static struct platform_device isp1362_hcd_device = {
 static struct platform_device *ip0x_devices[] __initdata = {
 #if defined(CONFIG_BFIN532_IP0X)
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
        &dm9000_device1,
        &dm9000_device2,
 #endif
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &spi_bfin_master_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
        &isp1362_hcd_device,
 #endif
 };
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 4da70c47cc05..d0989290f54c 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -14,7 +14,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/mmc_spi.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/irq.h>
@@ -30,7 +30,7 @@
 */
 const char bfin_board_name[] = "ADI BF533-STAMP";
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
@@ -40,7 +40,7 @@ static struct platform_device rtc_device = {
 /*
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -73,7 +73,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -97,7 +97,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_MTD_BFIN_ASYNC) || defined(CONFIG_MTD_BFIN_ASYNC_MODULE)
+#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
 static struct mtd_partition stamp_partitions[] = {
        {
                .name   = "bootloader(nor)",
@@ -147,7 +147,7 @@ static struct platform_device stamp_flash_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -178,7 +178,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 #define MMC_SPI_CARD_DETECT_INT IRQ_PF5
 static int bfin_mmc_spi_init(struct device *dev,
        irqreturn_t (*detect_int)(int, void *), void *data)
@@ -206,7 +206,7 @@ static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -219,8 +219,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-        defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
        {
                .modalias = "ad1836",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -231,7 +230,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -239,7 +238,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 1,
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -252,7 +251,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
        [0] = {
@@ -290,7 +289,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -341,7 +340,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -370,8 +369,7 @@ static struct platform_device bfin_sir0_device = {
 #endif
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || \
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-        defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -442,7 +440,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SPORT)
 static struct resource bfin_sport0_resources[] = {
        {
                .start = SPORT0_TCR1,
@@ -486,7 +484,7 @@ static struct platform_device bfin_sport0_device = {
 };
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -509,7 +507,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_I2C_GPIO)
 #include <linux/i2c-gpio.h>
 static struct i2c_gpio_platform_data i2c_gpio_data = {
@@ -530,29 +528,29 @@ static struct platform_device i2c_gpio_device = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE)
+#if IS_ENABLED(CONFIG_JOYSTICK_AD7142)
        {
                I2C_BOARD_INFO("ad7142_joystick", 0x2C),
                .irq = 39,
        },
 #endif
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
        },
 #endif
-#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_PCF8574)
        {
                I2C_BOARD_INFO("pcf8574_keypad", 0x27),
                .irq = 39,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_7393)
        {
                I2C_BOARD_INFO("bfin-adv7393", 0x2B),
        },
 #endif
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("ad5252", 0x2f),
        },
@@ -586,9 +584,8 @@ static struct platform_device bfin_dpmc = {
        },
 };
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
-        defined(CONFIG_SND_BF5XX_AC97) || \
+        IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-        defined(CONFIG_SND_BF5XX_AC97_MODULE)
 #include <asm/bfin_sport.h>
@@ -640,22 +637,21 @@ static struct resource bfin_snd_resources[][4] = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s_pcm = {
        .name = "bfin-i2s-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
 static struct platform_device bfin_ac97_pcm = {
        .name = "bfin-ac97-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-                || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
        "bfin-i2s.0",
        "spi0.4",
@@ -669,8 +665,7 @@ static struct platform_device bfin_ad1836_machine = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-        defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
 static const unsigned ad73311_gpio[] = {
        GPIO_PF4,
 };
@@ -684,22 +679,21 @@ static struct platform_device bfin_ad73311_machine = {
 };
 #endif
-#if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
 static struct platform_device bfin_ad73311_codec_device = {
        .name = "ad73311",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_SOC_AD74111) || defined(CONFIG_SND_SOC_AD74111_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
 static struct platform_device bfin_ad74111_codec_device = {
        .name = "ad74111",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_I2S) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-        defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -712,8 +706,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AC97) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-        defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
 static struct platform_device bfin_ac97 = {
        .name = "bfin-ac97",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -730,36 +723,35 @@ static struct platform_device *stamp_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || \
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-        defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -768,58 +760,54 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_I2C_GPIO)
        &i2c_gpio_device,
 #endif
-#if defined(CONFIG_MTD_BFIN_ASYNC) || defined(CONFIG_MTD_BFIN_ASYNC_MODULE)
+#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
        &stamp_flash_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
        &bfin_ac97_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-        defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
        &bfin_ad1836_machine,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-        defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
        &bfin_ad73311_machine,
 #endif
-#if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
        &bfin_ad73311_codec_device,
 #endif
-#if defined(CONFIG_SND_SOC_AD74111) || defined(CONFIG_SND_SOC_AD74111_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
        &bfin_ad74111_codec_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_I2S) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-        defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
        &bfin_i2s,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AC97) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-        defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
        &bfin_ac97,
 #endif
 };
 static int __init net2272_init(void)
 {
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        int ret;
        /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */
@@ -865,7 +853,7 @@ static int __init stamp_init(void)
        if (ret < 0)
                return ret;
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        /*
         * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
         * the bfin-async-map driver takes care of flipping between
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 85e4fc9f9c22..c65c6dbda3da 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/ata_platform.h>
@@ -32,10 +32,10 @@
 */
 const char bfin_board_name[] = "Bluetechnix CM BF537E";
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -66,14 +66,14 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -86,7 +86,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -95,7 +95,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -144,7 +144,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
 /* SPORT SPI controller data */
 static struct bfin5xx_spi_master bfin_sport_spi0_info = {
@@ -209,20 +209,20 @@ static struct platform_device bfin_sport_spi1_device = {
 #endif  /* sport spi master and devices */
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
 static struct platform_device hitachi_fb_device = {
        .name = "hitachi-tx09",
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -254,7 +254,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 static struct resource isp1362_hcd_resources[] = {
        {
                .start = 0x20308000,
@@ -293,7 +293,7 @@ static struct platform_device isp1362_hcd_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -314,7 +314,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
 static struct mtd_partition cm_partitions[] = {
        {
                .name   = "bootloader(nor)",
@@ -363,7 +363,7 @@ static struct platform_device cm_flash_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -498,7 +498,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -551,7 +551,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -578,14 +578,14 @@ static struct platform_device i2c_bfin_twi_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) \
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+|| IS_ENABLED(CONFIG_BFIN_SPORT)
 unsigned short bfin_sport0_peripherals[] = {
        P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -650,7 +650,7 @@ static struct platform_device bfin_sport1_uart_device = {
 };
 #endif
 #endif
-#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SPORT)
 static struct resource bfin_sport0_resources[] = {
        {
                .start = SPORT0_TCR1,
@@ -694,7 +694,7 @@ static struct platform_device bfin_sport0_device = {
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_MII0;
@@ -727,7 +727,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
 #define PATA_INT        IRQ_PF14
 static struct pata_platform_info bfin_pata_platform_data = {
@@ -795,19 +795,19 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SPORT)
        &bfin_sport0_device,
 #endif
-#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
        &hitachi_fb_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -816,7 +816,7 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -825,11 +825,11 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -838,44 +838,44 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
        &isp1362_hcd_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
        &bfin_sport_spi0_device,
        &bfin_sport_spi1_device,
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
        &bfin_pata_device,
 #endif
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
        &cm_flash_device,
 #endif
 };
 static int __init net2272_init(void)
 {
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        int ret;
        ret = gpio_request(GPIO_PG14, "net2272");
@@ -895,11 +895,11 @@ static int __init cm_bf537e_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
        irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index 0143d8bef909..af58454b4bff 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/ata_platform.h>
@@ -32,10 +32,10 @@
 */
 const char bfin_board_name[] = "Bluetechnix CM BF537U";
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -66,14 +66,14 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -86,7 +86,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -95,7 +95,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -144,20 +144,20 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
 static struct platform_device hitachi_fb_device = {
        .name = "hitachi-tx09",
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -189,7 +189,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 static struct resource isp1362_hcd_resources[] = {
        {
                .start = 0x20308000,
@@ -228,7 +228,7 @@ static struct platform_device isp1362_hcd_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20200000,
@@ -249,7 +249,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
 static struct mtd_partition cm_partitions[] = {
        {
                .name   = "bootloader(nor)",
@@ -298,7 +298,7 @@ static struct platform_device cm_flash_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -397,7 +397,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -450,7 +450,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -477,7 +477,7 @@ static struct platform_device i2c_bfin_twi_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -548,7 +548,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_MII0;
@@ -581,7 +581,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
 #define PATA_INT        IRQ_PF14
 static struct pata_platform_info bfin_pata_platform_data = {
@@ -649,15 +649,15 @@ static struct platform_device *cm_bf537u_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
        &hitachi_fb_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -666,7 +666,7 @@ static struct platform_device *cm_bf537u_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -675,11 +675,11 @@ static struct platform_device *cm_bf537u_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -688,39 +688,39 @@ static struct platform_device *cm_bf537u_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
        &isp1362_hcd_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
        &bfin_pata_device,
 #endif
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
        &cm_flash_device,
 #endif
 };
 static int __init net2272_init(void)
 {
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        int ret;
        ret = gpio_request(GPIO_PH15, driver_name);
@@ -752,11 +752,11 @@ static int __init cm_bf537u_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
        irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
index 8bbf0a23fd49..e79b3b810c39 100644
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -41,14 +41,14 @@ const char bfin_board_name[] = "DNP/5370";
 #define FLASH_MAC               0x202f0000
 #define CONFIG_MTD_PHYSMAP_LEN  0x300000
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
@@ -81,7 +81,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition asmb_flash_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -125,9 +125,9 @@ static struct platform_device asmb_flash_device = {
 };
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma    = 0,      /* use no dma transfer with this chip*/
@@ -135,7 +135,7 @@ static struct bfin5xx_spi_chip mmc_spi_chip_info = {
 #endif
-#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
 /* This mapping is for at45db642 it has 1056 page size,
 * partition size and offset should be page aligned
 */
@@ -166,7 +166,7 @@ static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 /* SD/MMC card reader at SPI bus */
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias        = "mmc_spi",
                .max_speed_hz    = 20000000,
@@ -178,7 +178,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 /* 8 Megabyte Atmel NOR flash chip at SPI bus */
-#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
        {
        .modalias        = "mtd_dataflash",
        .max_speed_hz    = 16700000,
@@ -228,7 +228,7 @@ static struct platform_device spi_bfin_master_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -328,7 +328,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -357,7 +357,7 @@ static struct platform_device i2c_bfin_twi_device = {
 static struct platform_device *dnp5370_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -366,24 +366,24 @@ static struct platform_device *dnp5370_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &asmb_flash_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &spi_bfin_master_device,
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index a10f90e444bc..dd7bda07bf90 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -13,7 +13,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/ata_platform.h>
@@ -31,7 +31,7 @@
 */
 const char bfin_board_name[] = "CamSig Minotaur BF537";
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
 static struct resource bfin_pcmcia_cf_resources[] = {
        {
                .start = 0x20310000, /* IO PORT */
@@ -60,14 +60,14 @@ static struct platform_device bfin_pcmcia_cf_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_MII0;
@@ -100,7 +100,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -121,11 +121,10 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 /* Partition sizes */
 #define FLASH_SIZE       0x00400000
@@ -162,15 +161,14 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -183,7 +181,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
@@ -231,7 +229,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -330,7 +328,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -385,7 +383,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -412,7 +410,7 @@ static struct platform_device i2c_bfin_twi_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -484,28 +482,28 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 static struct platform_device *minotaur_devices[] __initdata = {
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
        &bfin_pcmcia_cf_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -514,7 +512,7 @@ static struct platform_device *minotaur_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -523,11 +521,11 @@ static struct platform_device *minotaur_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -542,7 +540,7 @@ static int __init minotaur_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bfin_spi_board_info,
                                ARRAY_SIZE(bfin_spi_board_info));
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 6b395510405b..06a50ddb54c0 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -30,7 +30,7 @@ const char bfin_board_name[] = "ADI PNAV-1.0";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
 static struct resource bfin_pcmcia_cf_resources[] = {
        {
                .start = 0x20310000, /* IO PORT */
@@ -59,14 +59,14 @@ static struct platform_device bfin_pcmcia_cf_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -99,7 +99,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
@@ -132,7 +132,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -153,11 +153,10 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -188,13 +187,13 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -211,8 +210,7 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -225,8 +223,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -234,7 +231,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 4,
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
@@ -244,7 +241,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 {
        .modalias               = "ad7877",
        .platform_data          = &bfin_ad7877_ts_info,
@@ -294,13 +291,13 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
+#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
 static struct platform_device bfin_fb_device = {
        .name = "bf537-lq035",
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -399,7 +396,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -455,36 +452,36 @@ static struct platform_device bfin_sir1_device = {
 #endif
 static struct platform_device *stamp_devices[] __initdata = {
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
        &bfin_pcmcia_cf_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
+#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
        &bfin_fb_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -493,7 +490,7 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -507,7 +504,7 @@ static int __init pnav_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bfin_spi_board_info,
                                ARRAY_SIZE(bfin_spi_board_info));
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 44fd1d4682ac..de19b8a56007 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -18,7 +18,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/i2c.h>
@@ -53,7 +53,7 @@ const char bfin_board_name[] = "ADI BF537-STAMP";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
 #include <linux/usb/isp1760.h>
 static struct resource bfin_isp1760_resources[] = {
        [0] = {
@@ -88,7 +88,7 @@ static struct platform_device bfin_isp1760_device = {
 };
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/gpio_keys.h>
 static struct gpio_keys_button bfin_gpio_keys_table[] = {
@@ -111,7 +111,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
 static struct resource bfin_pcmcia_cf_resources[] = {
        {
                .start = 0x20310000, /* IO PORT */
@@ -140,14 +140,14 @@ static struct platform_device bfin_pcmcia_cf_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -180,7 +180,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
 static struct resource dm9000_resources[] = {
        [0] = {
                .start  = 0x203FB800,
@@ -207,7 +207,7 @@ static struct platform_device dm9000_device = {
 };
 #endif
-#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_SL811_HCD)
 static struct resource sl811_hcd_resources[] = {
        {
                .start = 0x20340000,
@@ -251,7 +251,7 @@ static struct platform_device sl811_hcd_device = {
 };
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 static struct resource isp1362_hcd_resources[] = {
        {
                .start = 0x20360000,
@@ -290,7 +290,7 @@ static struct platform_device isp1362_hcd_device = {
 };
 #endif
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
 static unsigned short bfin_can_peripherals[] = {
        P_CAN0_RX, P_CAN0_TX, 0
 };
@@ -328,7 +328,7 @@ static struct platform_device bfin_can_device = {
 };
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_MII0;
@@ -361,7 +361,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -385,7 +385,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
 const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
 static struct mtd_partition bfin_plat_nand_partitions[] = {
@@ -461,7 +461,7 @@ static void bfin_plat_nand_init(void)
 static void bfin_plat_nand_init(void) {}
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition stamp_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -509,8 +509,7 @@ static struct platform_device stamp_flash_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -541,7 +540,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
 #include <linux/input/ad714x.h>
 static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
@@ -602,7 +601,7 @@ static struct ad714x_platform_data ad7147_spi_platform_data = {
 };
 #endif
-#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
 #include <linux/input/ad714x.h>
 static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
        {
@@ -649,24 +648,24 @@ static struct ad714x_platform_data ad7142_i2c_platform_data = {
 };
 #endif
-#if defined(CONFIG_AD2S90) || defined(CONFIG_AD2S90_MODULE)
+#if IS_ENABLED(CONFIG_AD2S90)
 static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
+#if IS_ENABLED(CONFIG_AD2S1200)
-static unsigned short ad2s120x_platform_data[] = {
+static unsigned short ad2s1200_platform_data[] = {
        /* used as SAMPLE and RDVEL */
        GPIO_PF5, GPIO_PF6, 0
 };
-static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
+static struct bfin5xx_spi_chip ad2s1200_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
+#if IS_ENABLED(CONFIG_AD2S1210)
 static unsigned short ad2s1210_platform_data[] = {
        /* use as SAMPLE, A0, A1 */
        GPIO_PF7, GPIO_PF8, GPIO_PF9,
@@ -682,13 +681,13 @@ static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
 };
 #endif
-#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
+#if IS_ENABLED(CONFIG_SENSORS_AD7314)
 static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
-#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE)
+#if IS_ENABLED(CONFIG_AD7816)
 static unsigned short ad7816_platform_data[] = {
        GPIO_PF4, /* rdwr_pin */
        GPIO_PF5, /* convert_pin */
@@ -701,7 +700,7 @@ static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
 };
 #endif
-#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE)
+#if IS_ENABLED(CONFIG_ADT7310)
 static unsigned long adt7310_platform_data[3] = {
 /* INT bound temperature alarm event. line 1 */
        IRQ_PG4, IRQF_TRIGGER_LOW,
@@ -714,14 +713,14 @@ static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
 };
 #endif
-#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE)
+#if IS_ENABLED(CONFIG_AD7298)
 static unsigned short ad7298_platform_data[] = {
        GPIO_PF7, /* busy_pin */
        0,
 };
 #endif
-#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
+#if IS_ENABLED(CONFIG_ADT7316_SPI)
 static unsigned long adt7316_spi_data[2] = {
        IRQF_TRIGGER_LOW, /* interrupt flags */
        GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
@@ -732,7 +731,7 @@ static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 #define MMC_SPI_CARD_DETECT_INT IRQ_PF5
 static int bfin_mmc_spi_init(struct device *dev,
@@ -759,7 +758,7 @@ static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 #include <linux/spi/ad7877.h>
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
@@ -776,7 +775,7 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
 #include <linux/spi/ad7879.h>
 static const struct ad7879_platform_data bfin_ad7879_ts_info = {
        .model                  = 7879, /* Model = AD7879 */
@@ -793,7 +792,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
-#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
 #include <linux/input/adxl34x.h>
 static const struct adxl34x_platform_data adxl34x_info = {
        .x_axis_offset = 0,
@@ -832,13 +831,13 @@ static const struct adxl34x_platform_data adxl34x_info = {
 };
 #endif
-#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
+#if IS_ENABLED(CONFIG_ENC28J60)
 static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
        .enable_dma     = 1,
 };
 #endif
-#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
+#if IS_ENABLED(CONFIG_ADF702X)
 #include <linux/spi/adf702x.h>
 #define TXREG 0x0160A470
 static const u32 adf7021_regs[] = {
@@ -880,7 +879,7 @@ static inline void adf702x_mac_init(void)
 static inline void adf702x_mac_init(void) {}
 #endif
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
 #include <linux/spi/ads7846.h>
 static int ads7873_get_pendown_state(void)
 {
@@ -899,8 +898,7 @@ static struct ads7846_platform_data __initdata ad7873_pdata = {
 };
 #endif
-#if defined(CONFIG_MTD_DATAFLASH) \
+#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-        || defined(CONFIG_MTD_DATAFLASH_MODULE)
 static struct mtd_partition bfin_spi_dataflash_partitions[] = {
        {
@@ -931,15 +929,14 @@ static struct bfin5xx_spi_chip data_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE)
+#if IS_ENABLED(CONFIG_AD7476)
 static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
 };
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -951,8 +948,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_MTD_DATAFLASH) \
+#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-        || defined(CONFIG_MTD_DATAFLASH_MODULE)
        {       /* DataFlash chip */
                .modalias = "mtd_dataflash",
                .max_speed_hz = 33250000,     /* max spi clock (SCK) speed in HZ */
@@ -964,8 +960,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-        || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
        {
                .modalias = "ad1836",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -986,7 +981,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_SOC_ADAV80X) || defined(CONFIG_SND_SOC_ADV80X_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
        {
                .modalias = "adav801",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -996,7 +991,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
        {
                .modalias = "ad714x_captouch",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1008,7 +1003,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_AD2S90) || defined(CONFIG_AD2S90_MODULE)
+#if IS_ENABLED(CONFIG_AD2S90)
        {
                .modalias = "ad2s90",
                .bus_num = 0,
@@ -1019,17 +1014,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
+#if IS_ENABLED(CONFIG_AD2S1200)
        {
-                .modalias = "ad2s120x",
+                .modalias = "ad2s1200",
                .bus_num = 0,
                .chip_select = 4,            /* CS, change it for your board */
-                .platform_data = ad2s120x_platform_data,
+                .platform_data = ad2s1200_platform_data,
-                .controller_data = &ad2s120x_spi_chip_info,
+                .controller_data = &ad2s1200_spi_chip_info,
        },
 #endif
-#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
+#if IS_ENABLED(CONFIG_AD2S1210)
        {
                .modalias = "ad2s1210",
                .max_speed_hz = 8192000,
@@ -1040,7 +1035,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
+#if IS_ENABLED(CONFIG_SENSORS_AD7314)
        {
                .modalias = "ad7314",
                .max_speed_hz = 1000000,
@@ -1051,7 +1046,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE)
+#if IS_ENABLED(CONFIG_AD7816)
        {
                .modalias = "ad7818",
                .max_speed_hz = 1000000,
@@ -1063,7 +1058,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE)
+#if IS_ENABLED(CONFIG_ADT7310)
        {
                .modalias = "adt7310",
                .max_speed_hz = 1000000,
@@ -1076,7 +1071,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE)
+#if IS_ENABLED(CONFIG_AD7298)
        {
                .modalias = "ad7298",
                .max_speed_hz = 1000000,
@@ -1087,7 +1082,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
+#if IS_ENABLED(CONFIG_ADT7316_SPI)
        {
                .modalias = "adt7316",
                .max_speed_hz = 1000000,
@@ -1100,7 +1095,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -1111,7 +1106,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
        {
                .modalias               = "ad7877",
                .platform_data          = &bfin_ad7877_ts_info,
@@ -1121,7 +1116,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select  = 1,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
        {
                .modalias = "ad7879",
                .platform_data = &bfin_ad7879_ts_info,
@@ -1132,7 +1127,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -1140,7 +1135,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 1,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        {
                .modalias = "bfin-lq035q1-spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -1149,7 +1144,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif
-#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
+#if IS_ENABLED(CONFIG_ENC28J60)
        {
                .modalias = "enc28j60",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -1160,7 +1155,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_0,
        },
 #endif
-#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
        {
                .modalias       = "adxl34x",
                .platform_data  = &adxl34x_info,
@@ -1171,7 +1166,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
+#if IS_ENABLED(CONFIG_ADF702X)
        {
                .modalias = "adf702x",
                .max_speed_hz = 16000000,     /* max spi clock (SCK) speed in HZ */
@@ -1181,7 +1176,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_0,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
        {
                .modalias = "ads7846",
                .max_speed_hz = 2000000,     /* max spi clock (SCK) speed in HZ */
@@ -1192,8 +1187,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_0,
        },
 #endif
-#if defined(CONFIG_AD7476) \
+#if IS_ENABLED(CONFIG_AD7476)
-        || defined(CONFIG_AD7476_MODULE)
        {
                .modalias = "ad7476", /* Name of spi_driver for this device */
                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
@@ -1204,8 +1198,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_ADE7753) \
+#if IS_ENABLED(CONFIG_ADE7753)
-        || defined(CONFIG_ADE7753_MODULE)
        {
                .modalias = "ade7753",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1215,8 +1208,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_1,
        },
 #endif
-#if defined(CONFIG_ADE7754) \
+#if IS_ENABLED(CONFIG_ADE7754)
-        || defined(CONFIG_ADE7754_MODULE)
        {
                .modalias = "ade7754",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1226,8 +1218,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_1,
        },
 #endif
-#if defined(CONFIG_ADE7758) \
+#if IS_ENABLED(CONFIG_ADE7758)
-        || defined(CONFIG_ADE7758_MODULE)
        {
                .modalias = "ade7758",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1237,8 +1228,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_1,
        },
 #endif
-#if defined(CONFIG_ADE7759) \
+#if IS_ENABLED(CONFIG_ADE7759)
-        || defined(CONFIG_ADE7759_MODULE)
        {
                .modalias = "ade7759",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1248,8 +1238,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_1,
        },
 #endif
-#if defined(CONFIG_ADE7854_SPI) \
+#if IS_ENABLED(CONFIG_ADE7854_SPI)
-        || defined(CONFIG_ADE7854_SPI_MODULE)
        {
                .modalias = "ade7854",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1259,8 +1248,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_ADIS16060) \
+#if IS_ENABLED(CONFIG_ADIS16060)
-        || defined(CONFIG_ADIS16060_MODULE)
        {
                .modalias = "adis16060_r",
                .max_speed_hz = 2900000,     /* max spi clock (SCK) speed in HZ */
@@ -1278,8 +1266,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_1,
        },
 #endif
-#if defined(CONFIG_ADIS16130) \
+#if IS_ENABLED(CONFIG_ADIS16130)
-        || defined(CONFIG_ADIS16130_MODULE)
        {
                .modalias = "adis16130",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1289,8 +1276,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_ADIS16201) \
+#if IS_ENABLED(CONFIG_ADIS16201)
-        || defined(CONFIG_ADIS16201_MODULE)
        {
                .modalias = "adis16201",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1301,8 +1287,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .irq = IRQ_PF4,
        },
 #endif
-#if defined(CONFIG_ADIS16203) \
+#if IS_ENABLED(CONFIG_ADIS16203)
-        || defined(CONFIG_ADIS16203_MODULE)
        {
                .modalias = "adis16203",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1313,8 +1298,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .irq = IRQ_PF4,
        },
 #endif
-#if defined(CONFIG_ADIS16204) \
+#if IS_ENABLED(CONFIG_ADIS16204)
-        || defined(CONFIG_ADIS16204_MODULE)
        {
                .modalias = "adis16204",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1325,8 +1309,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .irq = IRQ_PF4,
        },
 #endif
-#if defined(CONFIG_ADIS16209) \
+#if IS_ENABLED(CONFIG_ADIS16209)
-        || defined(CONFIG_ADIS16209_MODULE)
        {
                .modalias = "adis16209",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1337,8 +1320,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .irq = IRQ_PF4,
        },
 #endif
-#if defined(CONFIG_ADIS16220) \
+#if IS_ENABLED(CONFIG_ADIS16220)
-        || defined(CONFIG_ADIS16220_MODULE)
        {
                .modalias = "adis16220",
                .max_speed_hz = 2000000,     /* max spi clock (SCK) speed in HZ */
@@ -1349,8 +1331,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .irq = IRQ_PF4,
        },
 #endif
-#if defined(CONFIG_ADIS16240) \
+#if IS_ENABLED(CONFIG_ADIS16240)
-        || defined(CONFIG_ADIS16240_MODULE)
        {
                .modalias = "adis16240",
                .max_speed_hz = 1500000,     /* max spi clock (SCK) speed in HZ */
@@ -1361,8 +1342,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .irq = IRQ_PF4,
        },
 #endif
-#if defined(CONFIG_ADIS16260) \
+#if IS_ENABLED(CONFIG_ADIS16260)
-        || defined(CONFIG_ADIS16260_MODULE)
        {
                .modalias = "adis16260",
                .max_speed_hz = 1500000,     /* max spi clock (SCK) speed in HZ */
@@ -1373,8 +1353,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .irq = IRQ_PF4,
        },
 #endif
-#if defined(CONFIG_ADIS16261) \
+#if IS_ENABLED(CONFIG_ADIS16261)
-        || defined(CONFIG_ADIS16261_MODULE)
        {
                .modalias = "adis16261",
                .max_speed_hz = 2500000,     /* max spi clock (SCK) speed in HZ */
@@ -1384,8 +1363,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_ADIS16300) \
+#if IS_ENABLED(CONFIG_ADIS16300)
-        || defined(CONFIG_ADIS16300_MODULE)
        {
                .modalias = "adis16300",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1396,8 +1374,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .irq = IRQ_PF4,
        },
 #endif
-#if defined(CONFIG_ADIS16350) \
+#if IS_ENABLED(CONFIG_ADIS16350)
-        || defined(CONFIG_ADIS16350_MODULE)
        {
                .modalias = "adis16364",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1408,8 +1385,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .irq = IRQ_PF4,
        },
 #endif
-#if defined(CONFIG_ADIS16400) \
+#if IS_ENABLED(CONFIG_ADIS16400)
-        || defined(CONFIG_ADIS16400_MODULE)
        {
                .modalias = "adis16400",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
@@ -1421,7 +1397,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI controller data */
 static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
@@ -1459,7 +1435,7 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
 /* SPORT SPI controller data */
 static struct bfin5xx_spi_master bfin_sport_spi0_info = {
@@ -1524,13 +1500,13 @@ static struct platform_device bfin_sport_spi1_device = {
 #endif  /* sport spi master and devices */
-#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
+#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
 static struct platform_device bfin_fb_device = {
        .name = "bf537_lq035",
 };
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
 #include <asm/bfin-lq035q1.h>
 static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
@@ -1559,8 +1535,7 @@ static struct platform_device bfin_lq035q1_device = {
 };
 #endif
-#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
 #include <linux/videodev2.h>
 #include <media/blackfin/bfin_capture.h>
 #include <media/blackfin/ppi.h>
@@ -1580,8 +1555,7 @@ static const struct ppi_info ppi_info = {
        .pin_req = ppi_req,
 };
-#if defined(CONFIG_VIDEO_VS6624) \
+#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-        || defined(CONFIG_VIDEO_VS6624_MODULE)
 static struct v4l2_input vs6624_inputs[] = {
        {
                .index = 0,
@@ -1624,7 +1598,7 @@ static struct platform_device bfin_capture_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -1735,7 +1709,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -1790,7 +1764,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -1817,7 +1791,7 @@ static struct platform_device i2c_bfin_twi_device = {
 };
 #endif
-#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
 static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
        [0]      = KEY_GRAVE,
        [1]      = KEY_1,
@@ -1902,7 +1876,7 @@ static struct adp5588_kpad_platform_data adp5588_kpad_data = {
 };
 #endif
-#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
+#if IS_ENABLED(CONFIG_PMIC_ADP5520)
 #include <linux/mfd/adp5520.h>
        /*
@@ -2013,14 +1987,14 @@ static struct adp5520_platform_data adp5520_pdev_data = {
 #endif
-#if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE)
+#if IS_ENABLED(CONFIG_GPIO_ADP5588)
 static struct adp5588_gpio_platform_data adp5588_gpio_data = {
        .gpio_start = 50,
        .pullup_dis_mask = 0,
 };
 #endif
-#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
+#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
 #include <linux/i2c/adp8870.h>
 static struct led_info adp8870_leds[] = {
        {
@@ -2072,7 +2046,7 @@ static struct adp8870_backlight_platform_data adp8870_pdata = {
 };
 #endif
-#if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE)
+#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
 #include <linux/i2c/adp8860.h>
 static struct led_info adp8860_leds[] = {
        {
@@ -2114,7 +2088,7 @@ static struct adp8860_backlight_platform_data adp8860_pdata = {
 };
 #endif
-#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
+#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
 static struct regulator_consumer_supply ad5398_consumer = {
        .supply = "current",
 };
@@ -2129,8 +2103,7 @@ static struct regulator_init_data ad5398_regulator_data = {
        .consumer_supplies     = &ad5398_consumer,
 };
-#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
+#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
-        defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
 static struct platform_device ad5398_virt_consumer_device = {
        .name = "reg-virt-consumer",
        .id = 0,
@@ -2139,8 +2112,7 @@ static struct platform_device ad5398_virt_consumer_device = {
        },
 };
 #endif
-#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
+#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-        defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
 static struct regulator_bulk_data ad5398_bulk_data = {
        .supply = "current",
 };
@@ -2161,14 +2133,14 @@ static struct platform_device ad5398_userspace_consumer_device = {
 #endif
 #endif
-#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE)
+#if IS_ENABLED(CONFIG_ADT7410)
 /* INT bound temperature alarm event. line 1 */
 static unsigned long adt7410_platform_data[2] = {
        IRQ_PG4, IRQF_TRIGGER_LOW,
 };
 #endif
-#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE)
+#if IS_ENABLED(CONFIG_ADT7316_I2C)
 /* INT bound temperature alarm event. line 1 */
 static unsigned long adt7316_i2c_data[2] = {
        IRQF_TRIGGER_LOW, /* interrupt flags */
@@ -2183,13 +2155,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        },
 #endif
-#if defined(CONFIG_SND_SOC_ADAV80X) || defined(CONFIG_SND_SOC_ADAV80X_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
        {
                I2C_BOARD_INFO("adav803", 0x10),
        },
 #endif
-#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
        {
                I2C_BOARD_INFO("ad7142_captouch", 0x2C),
                .irq = IRQ_PG5,
@@ -2197,39 +2169,39 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        },
 #endif
-#if defined(CONFIG_AD7150) || defined(CONFIG_AD7150_MODULE)
+#if IS_ENABLED(CONFIG_AD7150)
        {
                I2C_BOARD_INFO("ad7150", 0x48),
                .irq = IRQ_PG5, /* fixme: use real interrupt number */
        },
 #endif
-#if defined(CONFIG_AD7152) || defined(CONFIG_AD7152_MODULE)
+#if IS_ENABLED(CONFIG_AD7152)
        {
                I2C_BOARD_INFO("ad7152", 0x48),
        },
 #endif
-#if defined(CONFIG_AD774X) || defined(CONFIG_AD774X_MODULE)
+#if IS_ENABLED(CONFIG_AD774X)
        {
                I2C_BOARD_INFO("ad774x", 0x48),
        },
 #endif
-#if defined(CONFIG_ADE7854_I2C) || defined(CONFIG_ADE7854_I2C_MODULE)
+#if IS_ENABLED(CONFIG_ADE7854_I2C)
        {
                I2C_BOARD_INFO("ade7854", 0x38),
        },
 #endif
-#if defined(CONFIG_ADT75) || defined(CONFIG_ADT75_MODULE)
+#if IS_ENABLED(CONFIG_SENSORS_LM75)
        {
                I2C_BOARD_INFO("adt75", 0x9),
                .irq = IRQ_PG5,
        },
 #endif
-#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE)
+#if IS_ENABLED(CONFIG_ADT7410)
        {
                I2C_BOARD_INFO("adt7410", 0x48),
                /* CT critical temperature event. line 0 */
@@ -2238,14 +2210,14 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        },
 #endif
-#if defined(CONFIG_AD7291) || defined(CONFIG_AD7291_MODULE)
+#if IS_ENABLED(CONFIG_AD7291)
        {
                I2C_BOARD_INFO("ad7291", 0x20),
                .irq = IRQ_PG5,
        },
 #endif
-#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE)
+#if IS_ENABLED(CONFIG_ADT7316_I2C)
        {
                I2C_BOARD_INFO("adt7316", 0x48),
                .irq = IRQ_PG6,
@@ -2253,128 +2225,128 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        },
 #endif
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
        },
 #endif
-#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_PCF8574)
        {
                I2C_BOARD_INFO("pcf8574_keypad", 0x27),
                .irq = IRQ_PG6,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
        {
                I2C_BOARD_INFO("ad7879", 0x2F),
                .irq = IRQ_PG5,
                .platform_data = (void *)&bfin_ad7879_ts_info,
        },
 #endif
-#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
        {
                I2C_BOARD_INFO("adp5588-keys", 0x34),
                .irq = IRQ_PG0,
                .platform_data = (void *)&adp5588_kpad_data,
        },
 #endif
-#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
+#if IS_ENABLED(CONFIG_PMIC_ADP5520)
        {
                I2C_BOARD_INFO("pmic-adp5520", 0x32),
                .irq = IRQ_PG0,
                .platform_data = (void *)&adp5520_pdev_data,
        },
 #endif
-#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
        {
                I2C_BOARD_INFO("adxl34x", 0x53),
                .irq = IRQ_PG3,
                .platform_data = (void *)&adxl34x_info,
        },
 #endif
-#if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE)
+#if IS_ENABLED(CONFIG_GPIO_ADP5588)
        {
                I2C_BOARD_INFO("adp5588-gpio", 0x34),
                .platform_data = (void *)&adp5588_gpio_data,
        },
 #endif
-#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_7393)
        {
                I2C_BOARD_INFO("bfin-adv7393", 0x2B),
        },
 #endif
-#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
+#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
        {
                I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F),
        },
 #endif
-#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
+#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
        {
                I2C_BOARD_INFO("adp8870", 0x2B),
                .platform_data = (void *)&adp8870_pdata,
        },
 #endif
-#if defined(CONFIG_SND_SOC_ADAU1371) || defined(CONFIG_SND_SOC_ADAU1371_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAU1371)
        {
                I2C_BOARD_INFO("adau1371", 0x1A),
        },
 #endif
-#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
        {
                I2C_BOARD_INFO("adau1761", 0x38),
        },
 #endif
-#if defined(CONFIG_SND_SOC_ADAU1361) || defined(CONFIG_SND_SOC_ADAU1361_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAU1361)
        {
                I2C_BOARD_INFO("adau1361", 0x38),
        },
 #endif
-#if defined(CONFIG_SND_SOC_ADAU1701) || defined(CONFIG_SND_SOC_ADAU1701_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAU1701)
        {
                I2C_BOARD_INFO("adau1701", 0x34),
        },
 #endif
-#if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE)
+#if IS_ENABLED(CONFIG_AD525X_DPOT)
        {
                I2C_BOARD_INFO("ad5258", 0x18),
        },
 #endif
-#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
        {
                I2C_BOARD_INFO("ssm2602", 0x1b),
        },
 #endif
-#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
+#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
        {
                I2C_BOARD_INFO("ad5398", 0xC),
                .platform_data = (void *)&ad5398_regulator_data,
        },
 #endif
-#if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE)
+#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
        {
                I2C_BOARD_INFO("adp8860", 0x2A),
                .platform_data = (void *)&adp8860_pdata,
        },
 #endif
-#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
        {
                I2C_BOARD_INFO("adau1373", 0x1A),
        },
 #endif
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("ad5252", 0x2e),
        },
 #endif
 };
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) \
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+|| IS_ENABLED(CONFIG_BFIN_SPORT)
 unsigned short bfin_sport0_peripherals[] = {
        P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -2439,7 +2411,7 @@ static struct platform_device bfin_sport1_uart_device = {
 };
 #endif
 #endif
-#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SPORT)
 static struct resource bfin_sport0_resources[] = {
        {
                .start = SPORT0_TCR1,
@@ -2482,7 +2454,7 @@ static struct platform_device bfin_sport0_device = {
        },
 };
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
 #define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
 /* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
@@ -2569,8 +2541,8 @@ static struct platform_device bfin_dpmc = {
        },
 };
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
-        defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        IS_ENABLED(CONFIG_SND_BF5XX_AC97)
 #define SPORT_REQ(x) \
        [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
@@ -2620,22 +2592,21 @@ static struct resource bfin_snd_resources[][4] = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s_pcm = {
        .name = "bfin-i2s-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
 static struct platform_device bfin_ac97_pcm = {
        .name = "bfin-ac97-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-                || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
        "bfin-i2s.0",
        "spi0.4",
@@ -2649,8 +2620,7 @@ static struct platform_device bfin_ad1836_machine = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-                                defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
 static const unsigned ad73311_gpio[] = {
        GPIO_PF4,
 };
@@ -2664,22 +2634,21 @@ static struct platform_device bfin_ad73311_machine = {
 };
 #endif
-#if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
 static struct platform_device bfin_ad73311_codec_device = {
        .name = "ad73311",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X) || \
+#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
-        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X_MODULE)
 static struct platform_device bfin_eval_adav801_device = {
        .name = "bfin-eval-adav801",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -2691,7 +2660,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
 static struct platform_device bfin_ac97 = {
        .name = "bfin-ac97",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -2703,7 +2672,7 @@ static struct platform_device bfin_ac97 = {
 };
 #endif
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
 #define REGULATOR_ADP122        "adp122"
 #define REGULATOR_ADP122_UV     2500000
@@ -2741,8 +2710,7 @@ static struct platform_device adp_switch_device = {
        },
 };
-#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
+#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-        defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
 static struct regulator_bulk_data adp122_bulk_data = {
        .supply = REGULATOR_ADP122,
 };
@@ -2763,8 +2731,7 @@ static struct platform_device adp122_userspace_consumer_device = {
 #endif
 #endif
-#if defined(CONFIG_IIO_GPIO_TRIGGER) || \
+#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
-        defined(CONFIG_IIO_GPIO_TRIGGER_MODULE)
 static struct resource iio_gpio_trigger_resources[] = {
        [0] = {
@@ -2781,15 +2748,13 @@ static struct platform_device iio_gpio_trigger = {
 };
 #endif
-#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373) || \
+#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
-        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373_MODULE)
 static struct platform_device bf5xx_adau1373_device = {
        .name = "bfin-eval-adau1373",
 };
 #endif
-#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701) || \
+#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
-        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701_MODULE)
 static struct platform_device bf5xx_adau1701_device = {
        .name = "bfin-eval-adau1701",
 };
@@ -2798,73 +2763,72 @@ static struct platform_device bf5xx_adau1701_device = {
 static struct platform_device *stamp_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SPORT)
        &bfin_sport0_device,
 #endif
-#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
        &bfin_pcmcia_cf_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_SL811_HCD)
        &sl811_hcd_device,
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
        &isp1362_hcd_device,
 #endif
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
        &bfin_isp1760_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+#if IS_ENABLED(CONFIG_DM9000)
        &dm9000_device,
 #endif
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
        &bfin_can_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
        &bfin_sport_spi0_device,
        &bfin_sport_spi1_device,
 #endif
-#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
+#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
        &bfin_fb_device,
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        &bfin_lq035q1_device,
 #endif
-#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
        &bfin_capture_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -2873,7 +2837,7 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -2882,11 +2846,11 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -2895,95 +2859,86 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
        &bfin_pata_device,
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
        &bfin_async_nand_device,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &stamp_flash_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
        &bfin_ac97_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-        defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
        &bfin_ad1836_machine,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-                defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
        &bfin_ad73311_machine,
 #endif
-#if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
        &bfin_ad73311_codec_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
        &bfin_i2s,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
        &bfin_ac97,
 #endif
-#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
+#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
-#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
+#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
-        defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
        &ad5398_virt_consumer_device,
 #endif
-#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
+#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-        defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
        &ad5398_userspace_consumer_device,
 #endif
 #endif
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
        &adp_switch_device,
-#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
+#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-        defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
        &adp122_userspace_consumer_device,
 #endif
 #endif
-#if defined(CONFIG_IIO_GPIO_TRIGGER) || \
+#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
-        defined(CONFIG_IIO_GPIO_TRIGGER_MODULE)
        &iio_gpio_trigger,
 #endif
-#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373) || \
+#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
-        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373_MODULE)
        &bf5xx_adau1373_device,
 #endif
-#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701) || \
+#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
-        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701_MODULE)
        &bf5xx_adau1701_device,
 #endif
-#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X) || \
+#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
-        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X_MODULE)
        &bfin_eval_adav801_device,
 #endif
 };
 static int __init net2272_init(void)
 {
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        int ret;
        ret = gpio_request(GPIO_PF6, "net2272");
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index e285c3675286..a0211225748d 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/ata_platform.h>
@@ -32,10 +32,10 @@
 */
 const char bfin_board_name[] = "Bluetechnix TCM BF537";
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -66,14 +66,14 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
        .enable_dma = 0,
 };
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -86,7 +86,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -95,7 +95,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
@@ -144,20 +144,20 @@ static struct platform_device bfin_spi0_device = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
 static struct platform_device hitachi_fb_device = {
        .name = "hitachi-tx09",
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -189,7 +189,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 static struct resource isp1362_hcd_resources[] = {
        {
                .start = 0x20308000,
@@ -228,7 +228,7 @@ static struct platform_device isp1362_hcd_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x20300000,
@@ -249,7 +249,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
 static struct mtd_partition cm_partitions[] = {
        {
                .name   = "bootloader(nor)",
@@ -298,7 +298,7 @@ static struct platform_device cm_flash_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -397,7 +397,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -452,7 +452,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -479,7 +479,7 @@ static struct platform_device i2c_bfin_twi_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -550,7 +550,7 @@ static struct platform_device bfin_sport1_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
 #include <linux/bfin_mac.h>
 static const unsigned short bfin_mac_peripherals[] = P_MII0;
@@ -583,7 +583,7 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
 #define PATA_INT        IRQ_PF14
 static struct pata_platform_info bfin_pata_platform_data = {
@@ -651,15 +651,15 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
        &hitachi_fb_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -668,7 +668,7 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -677,11 +677,11 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -690,39 +690,39 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
        &isp1362_hcd_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_MAC)
        &bfin_mii_bus,
        &bfin_mac_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
        &bfin_pata_device,
 #endif
-#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
+#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
        &cm_flash_device,
 #endif
 };
 static int __init net2272_init(void)
 {
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        int ret;
        ret = gpio_request(GPIO_PG14, "net2272");
@@ -742,11 +742,11 @@ static int __init tcm_bf537_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
        irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 755f0dc12010..ae2fcbb00119 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -33,14 +33,14 @@ const char bfin_board_name[] = "ADI BF538-EZKIT";
 */
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif  /* CONFIG_RTC_DRV_BFIN */
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -199,7 +199,7 @@ static struct platform_device bfin_uart2_device = {
 #endif  /* CONFIG_SERIAL_BFIN_UART2 */
 #endif  /* CONFIG_SERIAL_BFIN */
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -277,7 +277,7 @@ static struct platform_device bfin_sir2_device = {
 #endif  /* CONFIG_BFIN_SIR2 */
 #endif  /* CONFIG_BFIN_SIR */
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -416,7 +416,7 @@ static struct platform_device bfin_sport3_uart_device = {
 #endif  /* CONFIG_SERIAL_BFIN_SPORT3_UART */
 #endif  /* CONFIG_SERIAL_BFIN_SPORT */
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
 static unsigned short bfin_can_peripherals[] = {
        P_CAN0_RX, P_CAN0_TX, 0
 };
@@ -458,7 +458,7 @@ static struct platform_device bfin_can_device = {
 *  USB-LAN EzExtender board
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -490,10 +490,9 @@ static struct platform_device smc91x_device = {
 };
 #endif  /* CONFIG_SMC91X */
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 /* SPI flash chip (m25p16) */
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
@@ -521,7 +520,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 #endif  /* CONFIG_MTD_M25P80 */
 #endif  /* CONFIG_SPI_BFIN5XX */
-#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
 #include <linux/spi/ad7879.h>
 static const struct ad7879_platform_data bfin_ad7879_ts_info = {
        .model                  = 7879, /* Model = AD7879 */
@@ -538,7 +537,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif  /* CONFIG_TOUCHSCREEN_AD7879 */
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
 #include <asm/bfin-lq035q1.h>
 static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
@@ -568,8 +567,7 @@ static struct platform_device bfin_lq035q1_device = {
 #endif  /* CONFIG_FB_BFIN_LQ035Q1 */
 static struct spi_board_info bf538_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -581,7 +579,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif  /* CONFIG_MTD_M25P80 */
-#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
        {
                .modalias = "ad7879",
                .platform_data = &bfin_ad7879_ts_info,
@@ -592,7 +590,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif  /* CONFIG_TOUCHSCREEN_AD7879_SPI */
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        {
                .modalias = "bfin-lq035q1-spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -601,7 +599,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .mode = SPI_CPHA | SPI_CPOL,
        },
 #endif  /* CONFIG_FB_BFIN_LQ035Q1 */
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -717,7 +715,7 @@ static struct platform_device bf538_spi_master2 = {
                },
 };
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -766,7 +764,7 @@ static struct platform_device i2c_bfin_twi1_device = {
 };
 #endif  /* CONFIG_I2C_BLACKFIN_TWI */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/gpio_keys.h>
 static struct gpio_keys_button bfin_gpio_keys_table[] = {
@@ -814,7 +812,7 @@ static struct platform_device bfin_dpmc = {
        },
 };
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition ezkit_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -839,7 +837,7 @@ static struct physmap_flash_data ezkit_flash_data = {
 static struct resource ezkit_flash_resource = {
        .start = 0x20000000,
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        .end   = 0x202fffff,
 #else
        .end   = 0x203fffff,
@@ -862,11 +860,11 @@ static struct platform_device *cm_bf538_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -878,18 +876,18 @@ static struct platform_device *cm_bf538_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bf538_spi_master0,
        &bf538_spi_master1,
        &bf538_spi_master2,
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi0_device,
        &i2c_bfin_twi1_device,
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -901,7 +899,7 @@ static struct platform_device *cm_bf538_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -916,23 +914,23 @@ static struct platform_device *cm_bf538_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
        &bfin_can_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
+#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
        &bfin_lq035q1_device,
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &ezkit_flash_device,
 #endif
 };
@@ -942,7 +940,7 @@ static int __init ezkit_init(void)
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bf538_spi_board_info,
                        ARRAY_SIZE(bf538_spi_board_info));
 #endif
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index e92543362f35..6d5ffdead067 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -37,7 +37,7 @@ const char bfin_board_name[] = "Bluetechnix CM-BF548";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
+#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
 #include <mach/bf54x-lq043.h>
@@ -69,7 +69,7 @@ static struct platform_device bf54x_lq043_device = {
 };
 #endif
-#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
 static unsigned int bf548_keymap[] = {
        KEYVAL(0, 0, KEY_ENTER),
        KEYVAL(0, 1, KEY_HELP),
@@ -119,14 +119,14 @@ static struct platform_device bf54x_kpad_device = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -353,7 +353,7 @@ static struct platform_device bfin_uart3_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -456,7 +456,7 @@ static struct platform_device bfin_sir3_device = {
 #endif
 #endif
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
 #include <linux/smsc911x.h>
 static struct resource smsc911x_resources[] = {
@@ -491,7 +491,7 @@ static struct platform_device smsc911x_device = {
 };
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct resource musb_resources[] = {
        [0] = {
                .start  = 0xFFC03C00,
@@ -553,7 +553,7 @@ static struct platform_device musb_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -692,7 +692,7 @@ static struct platform_device bfin_sport3_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
+#if IS_ENABLED(CONFIG_PATA_BF54X)
 static struct resource bfin_atapi_resources[] = {
        {
                .start = 0xFFC03800,
@@ -714,7 +714,7 @@ static struct platform_device bfin_atapi_device = {
 };
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
 static struct mtd_partition partition_info[] = {
        {
                .name = "linux kernel(nand)",
@@ -760,7 +760,7 @@ static struct platform_device bf5xx_nand_device = {
 };
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
 static struct bfin_sd_host bfin_sdh_data = {
        .dma_chan = CH_SDH,
        .irq_int0 = IRQ_SDH_MASK0,
@@ -776,7 +776,7 @@ static struct platform_device bf54x_sdh_device = {
 };
 #endif
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
 static unsigned short bfin_can_peripherals[] = {
        P_CAN0_RX, P_CAN0_TX, 0
 };
@@ -814,7 +814,7 @@ static struct platform_device bfin_can_device = {
 };
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition para_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -854,10 +854,9 @@ static struct platform_device para_flash_device = {
 };
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 /* SPI flash chip (m25p16) */
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
@@ -884,7 +883,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -901,8 +900,7 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 #endif
 static struct spi_board_info bf54x_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -914,7 +912,7 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 {
        .modalias               = "ad7877",
        .platform_data          = &bfin_ad7877_ts_info,
@@ -924,7 +922,7 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
        .chip_select            = 2,
 },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -1006,7 +1004,7 @@ static struct platform_device bf54x_spi_master1 = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -1060,7 +1058,7 @@ static struct platform_device i2c_bfin_twi1_device = {
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/gpio_keys.h>
 static struct gpio_keys_button bfin_gpio_keys_table[] = {
@@ -1112,11 +1110,11 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -1131,7 +1129,7 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -1146,19 +1144,19 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
+#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
        &bf54x_lq043_device,
 #endif
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
        &smsc911x_device,
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
        &musb_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -1173,43 +1171,43 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
+#if IS_ENABLED(CONFIG_PATA_BF54X)
        &bfin_atapi_device,
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
        &bf5xx_nand_device,
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
        &bf54x_sdh_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bf54x_spi_master0,
        &bf54x_spi_master1,
 #endif
-#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
        &bf54x_kpad_device,
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi0_device,
 #if !defined(CONFIG_BF542)
        &i2c_bfin_twi1_device,
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &para_flash_device,
 #endif
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
        &bfin_can_device,
 #endif
@@ -1220,7 +1218,7 @@ static int __init cm_bf548_init(void)
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bf54x_spi_board_info,
                        ARRAY_SIZE(bf54x_spi_board_info));
 #endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index d495000b81a0..90138e6112c1 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -41,7 +41,7 @@ const char bfin_board_name[] = "ADI BF548-EZKIT";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
 #include <linux/usb/isp1760.h>
 static struct resource bfin_isp1760_resources[] = {
        [0] = {
@@ -76,7 +76,7 @@ static struct platform_device bfin_isp1760_device = {
 };
 #endif
-#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
+#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
 #include <mach/bf54x-lq043.h>
@@ -108,7 +108,7 @@ static struct platform_device bf54x_lq043_device = {
 };
 #endif
-#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
 static const unsigned int bf548_keymap[] = {
        KEYVAL(0, 0, KEY_ENTER),
        KEYVAL(0, 1, KEY_HELP),
@@ -158,7 +158,7 @@ static struct platform_device bf54x_kpad_device = {
 };
 #endif
-#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
 #include <asm/bfin_rotary.h>
 static struct bfin_rotary_platform_data bfin_rotary_data = {
@@ -190,7 +190,7 @@ static struct platform_device bfin_rotary_device = {
 };
 #endif
-#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
 #include <linux/input/adxl34x.h>
 static const struct adxl34x_platform_data adxl34x_info = {
        .x_axis_offset = 0,
@@ -229,14 +229,14 @@ static const struct adxl34x_platform_data adxl34x_info = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -491,7 +491,7 @@ static struct platform_device bfin_uart3_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -594,7 +594,7 @@ static struct platform_device bfin_sir3_device = {
 #endif
 #endif
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
 #include <linux/smsc911x.h>
 static struct resource smsc911x_resources[] = {
@@ -629,7 +629,7 @@ static struct platform_device smsc911x_device = {
 };
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct resource musb_resources[] = {
        [0] = {
                .start  = 0xFFC03C00,
@@ -691,7 +691,7 @@ static struct platform_device musb_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -830,7 +830,7 @@ static struct platform_device bfin_sport3_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
 static unsigned short bfin_can0_peripherals[] = {
        P_CAN0_RX, P_CAN0_TX, 0
@@ -908,7 +908,7 @@ static struct platform_device bfin_can1_device = {
 #endif
-#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
+#if IS_ENABLED(CONFIG_PATA_BF54X)
 static struct resource bfin_atapi_resources[] = {
        {
                .start = 0xFFC03800,
@@ -930,7 +930,7 @@ static struct platform_device bfin_atapi_device = {
 };
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
 static struct mtd_partition partition_info[] = {
        {
                .name = "bootloader(nand)",
@@ -980,7 +980,7 @@ static struct platform_device bf5xx_nand_device = {
 };
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
 static struct bfin_sd_host bfin_sdh_data = {
        .dma_chan = CH_SDH,
@@ -997,7 +997,7 @@ static struct platform_device bf54x_sdh_device = {
 };
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition ezkit_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -1045,8 +1045,7 @@ static struct platform_device ezkit_flash_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 /* SPI flash chip (m25p16) */
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
@@ -1073,7 +1072,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -1495,8 +1494,7 @@ static struct platform_device bfin_gpj_device = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -1508,8 +1506,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -1517,7 +1514,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
        {
                .modalias               = "ad7877",
                .platform_data          = &bfin_ad7877_ts_info,
@@ -1527,7 +1524,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select            = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -1535,7 +1532,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */
        },
 #endif
-#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
        {
                .modalias               = "adxl34x",
                .platform_data          = &adxl34x_info,
@@ -1547,7 +1544,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
 };
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
        [0] = {
@@ -1620,8 +1617,7 @@ static struct platform_device bf54x_spi_master1 = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
 #include <linux/videodev2.h>
 #include <media/blackfin/bfin_capture.h>
 #include <media/blackfin/ppi.h>
@@ -1641,8 +1637,7 @@ static const struct ppi_info ppi_info = {
        .pin_req = ppi_req,
 };
-#if defined(CONFIG_VIDEO_VS6624) \
+#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-        || defined(CONFIG_VIDEO_VS6624_MODULE)
 static struct v4l2_input vs6624_inputs[] = {
        {
                .index = 0,
@@ -1687,7 +1682,7 @@ static struct platform_device bfin_capture_device = {
 };
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -1742,7 +1737,7 @@ static struct platform_device i2c_bfin_twi1_device = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
        {
                I2C_BOARD_INFO("ssm2602", 0x1b),
        },
@@ -1751,25 +1746,25 @@ static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
 #if !defined(CONFIG_BF542)      /* The BF542 only has 1 TWI */
 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("pcf8574_lcd", 0x22),
        },
 #endif
-#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_PCF8574)
        {
                I2C_BOARD_INFO("pcf8574_keypad", 0x27),
                .irq = 212,
        },
 #endif
-#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
        {
                I2C_BOARD_INFO("adxl34x", 0x53),
                .irq = IRQ_PC5,
                .platform_data = (void *)&adxl34x_info,
        },
 #endif
-#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
        {
                I2C_BOARD_INFO("ad5252", 0x2f),
        },
@@ -1777,7 +1772,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
 };
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/gpio_keys.h>
 static struct gpio_keys_button bfin_gpio_keys_table[] = {
@@ -1828,8 +1823,8 @@ static struct platform_device bfin_dpmc = {
        },
 };
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
-        defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        IS_ENABLED(CONFIG_SND_BF5XX_AC97)
 #define SPORT_REQ(x) \
        [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
@@ -1889,35 +1884,35 @@ static struct resource bfin_snd_resources[][4] = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s_pcm = {
        .name = "bfin-i2s-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
 static struct platform_device bfin_ac97_pcm = {
        .name = "bfin-ac97-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
 static struct platform_device bfin_ad73311_codec_device = {
        .name = "ad73311",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
 static struct platform_device bfin_ad1980_codec_device = {
        .name = "ad1980",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -1929,7 +1924,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
 static struct platform_device bfin_ac97 = {
        .name = "bfin-ac97",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -1962,11 +1957,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
        &bfin_gpj_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -1981,7 +1976,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -1996,23 +1991,23 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
+#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
        &bf54x_lq043_device,
 #endif
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
        &smsc911x_device,
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
        &musb_device,
 #endif
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
        &bfin_isp1760_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -2027,72 +2022,71 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
        &bfin_can0_device,
        &bfin_can1_device,
 #endif
-#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
+#if IS_ENABLED(CONFIG_PATA_BF54X)
        &bfin_atapi_device,
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
        &bf5xx_nand_device,
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
        &bf54x_sdh_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bf54x_spi_master0,
        &bf54x_spi_master1,
 #endif
-#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
        &bfin_capture_device,
 #endif
-#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
        &bf54x_kpad_device,
 #endif
-#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
        &bfin_rotary_device,
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi0_device,
 #if !defined(CONFIG_BF542)
        &i2c_bfin_twi1_device,
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &ezkit_flash_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
        &bfin_ac97_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
        &bfin_ad1980_codec_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s,
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
        &bfin_ac97,
 #endif
 };
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index 329b2c58228b..018ebfc27f5a 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -601,36 +601,6 @@
 #define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
 #define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-/* Bit masks for HOST_CONTROL */
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-/* Bit masks for HOST_STATUS */
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                 HSTIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-/* Bit masks for HOST_TIMEOUT */
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
 /* Bit masks for TIMER_ENABLE1 */
 #define                    TIMEN8  0x1        /* Timer 8 Enable */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index e18de212ba1a..d55dcc0f5324 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -581,36 +581,6 @@
 #define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
 #define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-/* Bit masks for HOST_CONTROL */
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-/* Bit masks for HOST_STATUS */
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                 HSTIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-/* Bit masks for HOST_TIMEOUT */
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
 /* Bit masks for KPAD_CTL */
 #define                   KPAD_EN  0x1        /* Keypad Enable */
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 0b74218fdd3a..430b16d5ccb1 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -60,7 +60,7 @@
 */
 const char bfin_board_name[] = "Acvilon board";
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
 #include <linux/usb/isp1760.h>
 static struct resource bfin_isp1760_resources[] = {
        [0] = {
@@ -137,7 +137,7 @@ static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
         },
 };
-#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PLATRAM)
 static struct platdata_mtd_ram mtd_ram_data = {
        .mapname = "rootfs(RAM)",
        .bankwidth = 4,
@@ -160,7 +160,7 @@ static struct platform_device mtd_ram_device = {
 };
 #endif
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
 #include <linux/smsc911x.h>
 static struct resource smsc911x_resources[] = {
        {
@@ -194,7 +194,7 @@ static struct platform_device smsc911x_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -246,7 +246,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
 static struct mtd_partition bfin_plat_nand_partitions[] = {
        {
@@ -323,7 +323,7 @@ static void bfin_plat_nand_init(void)
 }
 #endif
-#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
 static struct mtd_partition bfin_spi_dataflash_partitions[] = {
        {
         .name = "bootloader",
@@ -369,7 +369,7 @@ static struct bfin5xx_spi_chip data_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
        [0] = {
@@ -408,7 +408,7 @@ static struct platform_device bfin_spi0_device = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
         .modalias = "spidev",
         .max_speed_hz = 3125000,       /* max spi clock (SCK) speed in HZ */
@@ -416,7 +416,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         .chip_select = 3,
         },
 #endif
-#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
        {                       /* DataFlash chip */
         .modalias = "mtd_dataflash",
         .max_speed_hz = 33250000,      /* max spi clock (SCK) speed in HZ */
@@ -472,11 +472,11 @@ static struct platform_device bfin_dpmc = {
 static struct platform_device *acvilon_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -484,17 +484,17 @@ static struct platform_device *acvilon_devices[] __initdata = {
        &bfin_gpios_device,
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
        &smsc911x_device,
 #endif
        &bfin_i2c_pca_device,
-#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
        &bfin_async_nand_device,
 #endif
-#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PLATRAM)
        &mtd_ram_device,
 #endif
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index d81450f635df..9f777df4cacc 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -13,7 +13,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 #endif
 #include <linux/ata_platform.h>
@@ -29,10 +29,10 @@
 */
 const char bfin_board_name[] = "Bluetechnix CM BF561";
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader(spi)",
@@ -64,7 +64,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if IS_ENABLED(CONFIG_MTD_M25P80)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -77,7 +77,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        },
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -85,7 +85,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select = 4,
        },
 #endif
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_SPI)
        {
                .modalias = "mmc_spi",
                .max_speed_hz = 20000000,     /* max spi clock (SCK) speed in HZ */
@@ -134,14 +134,14 @@ static struct platform_device bfin_spi0_device = {
 #endif  /* spi master and devices */
-#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
 static struct platform_device hitachi_fb_device = {
        .name = "hitachi-tx09",
 };
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -173,7 +173,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
 #include <linux/smsc911x.h>
 static struct resource smsc911x_resources[] = {
@@ -208,7 +208,7 @@ static struct platform_device smsc911x_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x24000000,
@@ -229,7 +229,7 @@ static struct platform_device net2272_bfin_device = {
 };
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 static struct resource isp1362_hcd_resources[] = {
        {
                .start = 0x24008000,
@@ -268,7 +268,7 @@ static struct platform_device isp1362_hcd_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -319,7 +319,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -348,7 +348,7 @@ static struct platform_device bfin_sir0_device = {
 #endif
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
 #define PATA_INT        IRQ_PF46
 static struct pata_platform_info bfin_pata_platform_data = {
@@ -385,7 +385,7 @@ static struct platform_device bfin_pata_device = {
 };
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition para_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -456,54 +456,54 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
        &hitachi_fb_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
        &isp1362_hcd_device,
 #endif
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#if IS_ENABLED(CONFIG_SMSC911X)
        &smsc911x_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
        &bfin_pata_device,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &para_flash_device,
 #endif
 };
 static int __init net2272_init(void)
 {
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        int ret;
        ret = gpio_request(GPIO_PF46, "net2272");
@@ -523,11 +523,11 @@ static int __init cm_bf561_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __func__);
        platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
-#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_PATA_PLATFORM)
        irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
 #endif
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 92938e79b9e3..88dee43e7abe 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -25,7 +25,7 @@
 */
 const char bfin_board_name[] = "ADI BF561-EZKIT";
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
 #include <linux/usb/isp1760.h>
 static struct resource bfin_isp1760_resources[] = {
        [0] = {
@@ -60,7 +60,7 @@ static struct platform_device bfin_isp1760_device = {
 };
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
 #include <linux/usb/isp1362.h>
 static struct resource isp1362_hcd_resources[] = {
@@ -101,7 +101,7 @@ static struct platform_device isp1362_hcd_device = {
 };
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
 static struct resource net2272_bfin_resources[] = {
        {
                .start = 0x2C000000,
@@ -129,7 +129,7 @@ static struct platform_device net2272_bfin_device = {
 *  USB-LAN EzExtender board
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 #include <linux/smc91x.h>
 static struct smc91x_platdata smc91x_info = {
@@ -163,7 +163,7 @@ static struct platform_device smc91x_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -214,7 +214,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -243,7 +243,7 @@ static struct platform_device bfin_sir0_device = {
 #endif
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition ezkit_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -291,7 +291,7 @@ static struct platform_device ezkit_flash_device = {
 };
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 /* SPI (0) */
 static struct resource bfin_spi0_resource[] = {
        [0] = {
@@ -330,8 +330,7 @@ static struct platform_device bfin_spi0_device = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
-        || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
        {
                .modalias = "ad183x",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -341,7 +340,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -351,7 +350,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -375,7 +374,7 @@ static struct platform_device bfin_device_gpiokeys = {
 };
 #endif
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_I2C_GPIO)
 #include <linux/i2c-gpio.h>
 static struct i2c_gpio_platform_data i2c_gpio_data = {
@@ -422,8 +421,7 @@ static struct platform_device bfin_dpmc = {
        },
 };
-#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
 #include <linux/videodev2.h>
 #include <media/blackfin/bfin_capture.h>
 #include <media/blackfin/ppi.h>
@@ -443,8 +441,7 @@ static const struct ppi_info ppi_info = {
        .pin_req = ppi_req,
 };
-#if defined(CONFIG_VIDEO_ADV7183) \
+#if IS_ENABLED(CONFIG_VIDEO_ADV7183)
-        || defined(CONFIG_VIDEO_ADV7183_MODULE)
 #include <media/adv7183.h>
 static struct v4l2_input adv7183_inputs[] = {
        {
@@ -515,7 +512,7 @@ static struct platform_device bfin_capture_device = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s = {
        .name = "bfin-i2s",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -523,7 +520,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
 static struct platform_device bfin_ac97 = {
        .name = "bfin-ac97",
        .id = CONFIG_SND_BF5XX_SPORT_NUM,
@@ -531,8 +528,7 @@ static struct platform_device bfin_ac97 = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-                || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
        "bfin-i2s.0",
        "spi0.4",
@@ -550,72 +546,70 @@ static struct platform_device *ezkit_devices[] __initdata = {
        &bfin_dpmc,
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        &smc91x_device,
 #endif
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        &net2272_bfin_device,
 #endif
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
        &bfin_isp1760_device,
 #endif
-#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
+#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
        &bfin_spi0_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_I2C_GPIO)
        &i2c_gpio_device,
 #endif
-#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
        &isp1362_hcd_device,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &ezkit_flash_device,
 #endif
-#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
        &bfin_capture_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s,
 #endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
        &bfin_ac97,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-        defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
        &bfin_ad1836_machine,
 #endif
 };
 static int __init net2272_init(void)
 {
-#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+#if IS_ENABLED(CONFIG_USB_NET2272)
        int ret;
        ret = gpio_request(GPIO_PF11, "net2272");
@@ -641,12 +635,12 @@ static int __init ezkit_init(void)
        if (ret < 0)
                return ret;
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
        bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12));
        SSYNC();
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
        bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15));
        bfin_write_FIO0_FLAG_S(1 << 15);
        SSYNC();
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index 1a57bc986aad..f87b8cc0cd4c 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -42,7 +42,7 @@ static struct platform_device smc91x_device = {
        .resource      = smc91x_resources,
 };
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -93,7 +93,7 @@ static struct platform_device bfin_uart0_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -125,13 +125,13 @@ static struct platform_device bfin_sir0_device = {
 static struct platform_device *tepla_devices[] __initdata = {
        &smc91x_device,
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index 8de8bc690b36..943f7e95ec15 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -39,7 +39,7 @@ const char bfin_board_name[] = "ADI BF609-EZKIT";
 *  Driver needs to know address, irq and flag pin.
 */
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
 #include <linux/usb/isp1760.h>
 static struct resource bfin_isp1760_resources[] = {
        [0] = {
@@ -74,7 +74,7 @@ static struct platform_device bfin_isp1760_device = {
 };
 #endif
-#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
 #include <asm/bfin_rotary.h>
 static struct bfin_rotary_platform_data bfin_rotary_data = {
@@ -105,7 +105,7 @@ static struct platform_device bfin_rotary_device = {
 };
 #endif
-#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
+#if IS_ENABLED(CONFIG_STMMAC_ETH)
 #include <linux/stmmac.h>
 #include <linux/phy.h>
@@ -159,7 +159,7 @@ static struct platform_device bfin_eth_device = {
 };
 #endif
-#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
 #include <linux/input/adxl34x.h>
 static const struct adxl34x_platform_data adxl34x_info = {
        .x_axis_offset = 0,
@@ -198,14 +198,14 @@ static const struct adxl34x_platform_data adxl34x_info = {
 };
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
 static struct resource bfin_uart0_resources[] = {
        {
@@ -355,7 +355,7 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
 static struct resource bfin_sir0_resources[] = {
        {
@@ -408,7 +408,7 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct resource musb_resources[] = {
        [0] = {
                .start  = 0xFFCC1000,
@@ -464,7 +464,7 @@ static struct platform_device musb_device = {
 };
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
        {
@@ -569,7 +569,7 @@ static struct platform_device bfin_sport2_uart_device = {
 #endif
 #endif
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
 static unsigned short bfin_can0_peripherals[] = {
        P_CAN0_RX, P_CAN0_TX, 0
@@ -610,7 +610,7 @@ static struct platform_device bfin_can0_device = {
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
 static struct mtd_partition partition_info[] = {
        {
                .name = "bootloader(nand)",
@@ -660,7 +660,7 @@ static struct platform_device bfin_nand_device = {
 };
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
 static struct bfin_sd_host bfin_sdh_data = {
        .dma_chan = CH_RSI,
@@ -677,7 +677,7 @@ static struct platform_device bfin_sdh_device = {
 };
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 static struct mtd_partition ezkit_partitions[] = {
        {
                .name       = "bootloader(nor)",
@@ -741,8 +741,7 @@ static struct platform_device ezkit_flash_device = {
 };
 #endif
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
 /* SPI flash chip (w25q32) */
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
@@ -773,21 +772,20 @@ static struct bfin_spi3_chip spi_flash_chip_info = {
 };
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
 static struct bfin_spi3_chip spidev_chip_info = {
        .enable_dma = true,
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
 static struct platform_device bfin_i2s_pcm = {
        .name = "bfin-i2s-pcm-audio",
        .id = -1,
 };
 #endif
-#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
+#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
-        defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
 #include <asm/bfin_sport3.h>
 static struct resource bfin_snd_resources[] = {
        {
@@ -841,8 +839,7 @@ static struct platform_device bfin_i2s = {
 };
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-                || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
        "bfin-i2s.0",
        "spi0.76",
@@ -856,14 +853,13 @@ static struct platform_device bfin_ad1836_machine = {
 };
 #endif
-#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
+#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
-        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
 static struct platform_device adau1761_device = {
        .name = "bfin-eval-adau1x61",
 };
 #endif
-#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
 #include <sound/adau17x1.h>
 static struct adau1761_platform_data adau1761_info = {
        .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
@@ -871,8 +867,7 @@ static struct adau1761_platform_data adau1761_info = {
 };
 #endif
-#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
 #include <linux/videodev2.h>
 #include <media/blackfin/bfin_capture.h>
 #include <media/blackfin/ppi.h>
@@ -882,7 +877,7 @@ static const unsigned short ppi_req[] = {
        P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
        P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
        P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
-#if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
+#if !IS_ENABLED(CONFIG_VIDEO_VS6624)
        P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
        P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
 #endif
@@ -898,8 +893,7 @@ static const struct ppi_info ppi_info = {
        .pin_req = ppi_req,
 };
-#if defined(CONFIG_VIDEO_VS6624) \
+#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-        || defined(CONFIG_VIDEO_VS6624_MODULE)
 static struct v4l2_input vs6624_inputs[] = {
        {
                .index = 0,
@@ -936,8 +930,7 @@ static struct bfin_capture_config bfin_capture_data = {
 };
 #endif
-#if defined(CONFIG_VIDEO_ADV7842) \
+#if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-        || defined(CONFIG_VIDEO_ADV7842_MODULE)
 #include <media/adv7842.h>
 static struct v4l2_input adv7842_inputs[] = {
@@ -1067,8 +1060,7 @@ static struct platform_device bfin_capture_device = {
 };
 #endif
-#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
-        || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
 #include <linux/videodev2.h>
 #include <media/blackfin/bfin_display.h>
 #include <media/blackfin/ppi.h>
@@ -1090,8 +1082,7 @@ static const struct ppi_info ppi_info = {
        .pin_req = ppi_req_disp,
 };
-#if defined(CONFIG_VIDEO_ADV7511) \
+#if IS_ENABLED(CONFIG_VIDEO_ADV7511)
-        || defined(CONFIG_VIDEO_ADV7511_MODULE)
 #include <media/adv7511.h>
 static struct v4l2_output adv7511_outputs[] = {
@@ -1313,7 +1304,7 @@ static struct platform_device bfin_crypto_crc_device = {
 };
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
        .model                  = 7877,
        .vref_delay_usecs       = 50,   /* internal, no capacitor */
@@ -1679,7 +1670,7 @@ static struct platform_device bfin_gpg_device = {
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -1702,8 +1693,7 @@ static struct platform_device bfin_device_gpiokeys = {
 #endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) \
+#if IS_ENABLED(CONFIG_MTD_M25P80)
-        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
@@ -1715,7 +1705,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
        {
                .modalias               = "ad7877",
                .platform_data          = &bfin_ad7877_ts_info,
@@ -1725,7 +1715,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .chip_select            = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
        },
 #endif
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+#if IS_ENABLED(CONFIG_SPI_SPIDEV)
        {
                .modalias = "spidev",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -1734,7 +1724,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                .controller_data = &spidev_chip_info,
        },
 #endif
-#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
        {
                .modalias               = "adxl34x",
                .platform_data          = &adxl34x_info,
@@ -1818,7 +1808,7 @@ static struct platform_device bf60x_spi_master1 = {
 };
 #endif  /* spi master and devices */
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
@@ -1871,20 +1861,20 @@ static struct platform_device i2c_bfin_twi1_device = {
 #endif
 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
        {
                I2C_BOARD_INFO("adxl34x", 0x53),
                .irq = IRQ_PC5,
                .platform_data = (void *)&adxl34x_info,
        },
 #endif
-#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
        {
                I2C_BOARD_INFO("adau1761", 0x38),
                .platform_data = (void *)&adau1761_info
        },
 #endif
-#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
        {
                I2C_BOARD_INFO("ssm2602", 0x1b),
        },
@@ -1942,11 +1932,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
        &bfin_gpg_device,
 #endif
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
        &rtc_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 #ifdef CONFIG_SERIAL_BFIN_UART0
        &bfin_uart0_device,
 #endif
@@ -1955,7 +1945,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#if IS_ENABLED(CONFIG_BFIN_SIR)
 #ifdef CONFIG_BFIN_SIR0
        &bfin_sir0_device,
 #endif
@@ -1964,19 +1954,19 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
+#if IS_ENABLED(CONFIG_STMMAC_ETH)
        &bfin_eth_device,
 #endif
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
        &musb_device,
 #endif
-#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
        &bfin_isp1760_device,
 #endif
-#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
        &bfin_sport0_uart_device,
 #endif
@@ -1988,15 +1978,15 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #endif
 #endif
-#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_CAN_BFIN)
        &bfin_can0_device,
 #endif
-#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
        &bfin_nand_device,
 #endif
-#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+#if IS_ENABLED(CONFIG_SDH_BFIN)
        &bfin_sdh_device,
 #endif
@@ -2005,11 +1995,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
        &bf60x_spi_master1,
 #endif
-#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
        &bfin_rotary_device,
 #endif
-#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
        &i2c_bfin_twi0_device,
 #if !defined(CONFIG_BF542)
        &i2c_bfin_twi1_device,
@@ -2024,34 +2014,29 @@ static struct platform_device *ezkit_devices[] __initdata = {
        &bfin_crypto_crc_device,
 #endif
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
        &bfin_device_gpiokeys,
 #endif
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
        &ezkit_flash_device,
 #endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
        &bfin_i2s_pcm,
 #endif
-#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
+#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
-        defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
        &bfin_i2s,
 #endif
-#if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
+#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-        defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
        &bfin_ad1836_machine,
 #endif
-#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
+#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
-        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
        &adau1761_device,
 #endif
-#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
        &bfin_capture_device,
 #endif
-#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
+#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
-        || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
        &bfin_display_device,
 #endif
@@ -2075,9 +2060,9 @@ static struct pinctrl_map __initdata bfin_pinmux_map[] = {
        PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0",  "pinctrl-adi2.0", NULL, "smc0"),
        PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2",  "pinctrl-adi2.0", NULL, "ppi2_16b"),
        PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0",  "pinctrl-adi2.0", NULL, "ppi0_16b"),
-#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
+#if IS_ENABLED(CONFIG_VIDEO_MT9M114)
        PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0",  "pinctrl-adi2.0", NULL, "ppi0_8b"),
-#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
+#elif IS_ENABLED(CONFIG_VIDEO_VS6624)
        PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0",  "pinctrl-adi2.0", NULL, "ppi0_16b"),
 #else
        PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0",  "pinctrl-adi2.0", NULL, "ppi0_24b"),
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
index 13644ed25489..56200f37cfc8 100644
--- a/arch/blackfin/mach-bf609/clock.c
+++ b/arch/blackfin/mach-bf609/clock.c
@@ -73,24 +73,6 @@ static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
        bfin_write32(reg, val2);
 }
-static void clk_reg_set_bits(u32 reg, uint32_t mask)
-{
-        u32 val;
-        val = bfin_read32(reg);
-        val |= mask;
-        bfin_write32(reg, val);
-}
-static void clk_reg_clear_bits(u32 reg, uint32_t mask)
-{
-        u32 val;
-        val = bfin_read32(reg);
-        val &= ~mask;
-        bfin_write32(reg, val);
-}
 int wait_for_pll_align(void)
 {
        int i = 10000;
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
index ad505d9db4a8..0cdd6955c7be 100644
--- a/arch/blackfin/mach-bf609/pm.c
+++ b/arch/blackfin/mach-bf609/pm.c
@@ -210,7 +210,7 @@ void bf609_cpu_pm_enter(suspend_state_t state)
 #ifdef CONFIG_PM_BFIN_WAKE_PB15
        wakeup |= PB15WE;
-# if CONFIG_PM_BFIN_WAKE_PA15_POL
+# if CONFIG_PM_BFIN_WAKE_PB15_POL
        wakeup_pol |= PB15WE;
 # endif
 #endif
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index ed0fcdf7e990..52731e221851 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -29,7 +29,7 @@ config GENERIC_CALIBRATE_DELAY
        bool
        default y
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool y
 config FORCE_MAX_ZONEORDER
@@ -138,6 +138,7 @@ config ETRAX_ARCH_V10
       bool
       default y if ETRAX100LX || ETRAX100LX_V2
       default n if !(ETRAX100LX || ETRAX100LX_V2)
+       select TTY
 config ETRAX_ARCH_V32
       bool
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
index 6792503aaf79..15a9ed1d579c 100644
--- a/arch/cris/arch-v32/drivers/Kconfig
+++ b/arch/cris/arch-v32/drivers/Kconfig
@@ -11,7 +11,6 @@ config ETRAX_ETHERNET
 config ETRAX_NO_PHY
        bool "PHY not present"
        depends on ETRAX_ETHERNET
-        default N
        help
          This option disables all MDIO communication with an ethernet
          transceiver connected to the MII interface. This option shall
@@ -116,7 +115,6 @@ config ETRAX_AXISFLASHMAP
 config ETRAX_AXISFLASHMAP_MTD0WHOLE
        bool "MTD0 is whole boot flash device"
        depends on ETRAX_AXISFLASHMAP
-        default N
        help
          When this option is not set, mtd0 refers to the first partition
          on the boot flash device. When set, mtd0 refers to the whole
diff --git a/arch/cris/kernel/setup.c b/arch/cris/kernel/setup.c
index 32c3d248868e..905b70ea9939 100644
--- a/arch/cris/kernel/setup.c
+++ b/arch/cris/kernel/setup.c
@@ -165,6 +165,7 @@ void __init setup_arch(char **cmdline_p)
        strcpy(init_utsname()->machine, cris_machine_name);
 }
+#ifdef CONFIG_PROC_FS
 static void *c_start(struct seq_file *m, loff_t *pos)
 {
        return *pos < nr_cpu_ids ? (void *)(int)(*pos + 1) : NULL;
@@ -188,6 +189,7 @@ const struct seq_operations cpuinfo_op = {
        .stop  = c_stop,
        .show  = show_cpuinfo,
 };
+#endif /* CONFIG_PROC_FS */
 static int __init topology_init(void)
 {
diff --git a/arch/frv/mb93090-mb00/pci-frv.c b/arch/frv/mb93090-mb00/pci-frv.c
index c28121765448..67b1d1685759 100644
--- a/arch/frv/mb93090-mb00/pci-frv.c
+++ b/arch/frv/mb93090-mb00/pci-frv.c
@@ -88,7 +88,7 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
        /* Depth-First Search on bus tree */
        for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
-                bus = pci_bus_b(ln);
+                bus = list_entry(ln, struct pci_bus, node);
                if ((dev = bus->self)) {
                        for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
                                r = &dev->resource[idx];
diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
index 09df2608f40a..0fd6138f6203 100644
--- a/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@ -19,7 +19,7 @@ config HEXAGON
        select GENERIC_IRQ_SHOW
        select HAVE_ARCH_KGDB
        select HAVE_ARCH_TRACEHOOK
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        select GENERIC_IOMAP
        select GENERIC_SMP_IDLE_THREAD
        select STACKTRACE_SUPPORT
@@ -28,6 +28,7 @@ config HEXAGON
        select GENERIC_CLOCKEVENTS_BROADCAST
        select MODULES_USE_ELF_RELA
        select GENERIC_CPU_DEVICES
+        select HAVE_DMA_ATTRS
        ---help---
          Qualcomm Hexagon is a processor architecture designed for high
          performance and low power across a wide variety of applications.
diff --git a/arch/hexagon/include/asm/Kbuild b/arch/hexagon/include/asm/Kbuild
index eadcc118f950..0e69796b58c7 100644
--- a/arch/hexagon/include/asm/Kbuild
+++ b/arch/hexagon/include/asm/Kbuild
@@ -41,6 +41,7 @@ generic-y += scatterlist.h
 generic-y += sections.h
 generic-y += segment.h
 generic-y += sembuf.h
+generic-y += serial.h
 generic-y += shmbuf.h
 generic-y += shmparam.h
 generic-y += siginfo.h
@@ -56,4 +57,5 @@ generic-y += trace_clock.h
 generic-y += types.h
 generic-y += ucontext.h
 generic-y += unaligned.h
+generic-y += vga.h
 generic-y += xor.h
diff --git a/arch/hexagon/include/asm/atomic.h b/arch/hexagon/include/asm/atomic.h
index 7aae4cb2a29a..17dc63780c06 100644
--- a/arch/hexagon/include/asm/atomic.h
+++ b/arch/hexagon/include/asm/atomic.h
@@ -26,7 +26,20 @@
 #include <asm/cmpxchg.h>
 #define ATOMIC_INIT(i)          { (i) }
-#define atomic_set(v, i)        ((v)->counter = (i))
+/*  Normal writes in our arch don't clear lock reservations  */
+static inline void atomic_set(atomic_t *v, int new)
+{
+        asm volatile(
+                "1:     r6 = memw_locked(%0);\n"
+                "       memw_locked(%0,p0) = %1;\n"
+                "       if (!P0) jump 1b;\n"
+                :
+                : "r" (&v->counter), "r" (new)
+                : "memory", "p0", "r6"
+        );
+}
 /**
 * atomic_read - reads a word, atomically
diff --git a/arch/hexagon/include/asm/delay.h b/arch/hexagon/include/asm/delay.h
index 53079719d667..8933b9b1a3bf 100644
--- a/arch/hexagon/include/asm/delay.h
+++ b/arch/hexagon/include/asm/delay.h
@@ -21,6 +21,7 @@
 #include <asm/param.h>
+extern void __delay(unsigned long cycles);
 extern void __udelay(unsigned long usecs);
 #define udelay(usecs) __udelay((usecs))
diff --git a/arch/hexagon/include/asm/dma-mapping.h b/arch/hexagon/include/asm/dma-mapping.h
index 85e9935660cb..16965427f6b4 100644
--- a/arch/hexagon/include/asm/dma-mapping.h
+++ b/arch/hexagon/include/asm/dma-mapping.h
@@ -25,7 +25,6 @@
 #include <linux/cache.h>
 #include <linux/mm.h>
 #include <linux/scatterlist.h>
-#include <linux/dma-mapping.h>
 #include <linux/dma-debug.h>
 #include <linux/dma-attrs.h>
 #include <asm/io.h>
diff --git a/arch/hexagon/include/asm/elf.h b/arch/hexagon/include/asm/elf.h
index e1b933a0e121..80311e7b8ca6 100644
--- a/arch/hexagon/include/asm/elf.h
+++ b/arch/hexagon/include/asm/elf.h
@@ -1,7 +1,7 @@
 /*
 * ELF definitions for the Hexagon architecture
 *
- * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -202,7 +202,7 @@ do {					\
 #define CORE_DUMP_USE_REGSET
 /* Hrm is this going to cause problems for changing PAGE_SIZE?  */
-#define ELF_EXEC_PAGESIZE       4096
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
 /*
 * This is the location that an ET_DYN program is loaded if exec'ed.  Typical
diff --git a/arch/hexagon/include/asm/hexagon_vm.h b/arch/hexagon/include/asm/hexagon_vm.h
index 67bb6d6f3337..1f6918b428de 100644
--- a/arch/hexagon/include/asm/hexagon_vm.h
+++ b/arch/hexagon/include/asm/hexagon_vm.h
@@ -55,27 +55,27 @@
 #ifndef __ASSEMBLY__
 enum VM_CACHE_OPS {
-        ickill,
+        hvmc_ickill,
-        dckill,
+        hvmc_dckill,
-        l2kill,
+        hvmc_l2kill,
-        dccleaninva,
+        hvmc_dccleaninva,
-        icinva,
+        hvmc_icinva,
-        idsync,
+        hvmc_idsync,
-        fetch_cfg
+        hvmc_fetch_cfg
 };
 enum VM_INT_OPS {
-        nop,
+        hvmi_nop,
-        globen,
+        hvmi_globen,
-        globdis,
+        hvmi_globdis,
-        locen,
+        hvmi_locen,
-        locdis,
+        hvmi_locdis,
-        affinity,
+        hvmi_affinity,
-        get,
+        hvmi_get,
-        peek,
+        hvmi_peek,
-        status,
+        hvmi_status,
-        post,
+        hvmi_post,
-        clear
+        hvmi_clear
 };
 extern void _K_VM_event_vector(void);
@@ -98,95 +98,95 @@ long __vmvpid(void);
 static inline long __vmcache_ickill(void)
 {
-        return __vmcache(ickill, 0, 0);
+        return __vmcache(hvmc_ickill, 0, 0);
 }
 static inline long __vmcache_dckill(void)
 {
-        return __vmcache(dckill, 0, 0);
+        return __vmcache(hvmc_dckill, 0, 0);
 }
 static inline long __vmcache_l2kill(void)
 {
-        return __vmcache(l2kill, 0, 0);
+        return __vmcache(hvmc_l2kill, 0, 0);
 }
 static inline long __vmcache_dccleaninva(unsigned long addr, unsigned long len)
 {
-        return __vmcache(dccleaninva, addr, len);
+        return __vmcache(hvmc_dccleaninva, addr, len);
 }
 static inline long __vmcache_icinva(unsigned long addr, unsigned long len)
 {
-        return __vmcache(icinva, addr, len);
+        return __vmcache(hvmc_icinva, addr, len);
 }
 static inline long __vmcache_idsync(unsigned long addr,
                                           unsigned long len)
 {
-        return __vmcache(idsync, addr, len);
+        return __vmcache(hvmc_idsync, addr, len);
 }
 static inline long __vmcache_fetch_cfg(unsigned long val)
 {
-        return __vmcache(fetch_cfg, val, 0);
+        return __vmcache(hvmc_fetch_cfg, val, 0);
 }
 /* interrupt operations  */
 static inline long __vmintop_nop(void)
 {
-        return __vmintop(nop, 0, 0, 0, 0);
+        return __vmintop(hvmi_nop, 0, 0, 0, 0);
 }
 static inline long __vmintop_globen(long i)
 {
-        return __vmintop(globen, i, 0, 0, 0);
+        return __vmintop(hvmi_globen, i, 0, 0, 0);
 }
 static inline long __vmintop_globdis(long i)
 {
-        return __vmintop(globdis, i, 0, 0, 0);
+        return __vmintop(hvmi_globdis, i, 0, 0, 0);
 }
 static inline long __vmintop_locen(long i)
 {
-        return __vmintop(locen, i, 0, 0, 0);
+        return __vmintop(hvmi_locen, i, 0, 0, 0);
 }
 static inline long __vmintop_locdis(long i)
 {
-        return __vmintop(locdis, i, 0, 0, 0);
+        return __vmintop(hvmi_locdis, i, 0, 0, 0);
 }
 static inline long __vmintop_affinity(long i, long cpu)
 {
-        return __vmintop(locdis, i, cpu, 0, 0);
+        return __vmintop(hvmi_affinity, i, cpu, 0, 0);
 }
 static inline long __vmintop_get(void)
 {
-        return __vmintop(get, 0, 0, 0, 0);
+        return __vmintop(hvmi_get, 0, 0, 0, 0);
 }
 static inline long __vmintop_peek(void)
 {
-        return __vmintop(peek, 0, 0, 0, 0);
+        return __vmintop(hvmi_peek, 0, 0, 0, 0);
 }
 static inline long __vmintop_status(long i)
 {
-        return __vmintop(status, i, 0, 0, 0);
+        return __vmintop(hvmi_status, i, 0, 0, 0);
 }
 static inline long __vmintop_post(long i)
 {
-        return __vmintop(post, i, 0, 0, 0);
+        return __vmintop(hvmi_post, i, 0, 0, 0);
 }
 static inline long __vmintop_clear(long i)
 {
-        return __vmintop(clear, i, 0, 0, 0);
+        return __vmintop(hvmi_clear, i, 0, 0, 0);
 }
 #else /* Only assembly code should reference these */
diff --git a/arch/hexagon/include/asm/io.h b/arch/hexagon/include/asm/io.h
index 1b7698e19139..70298996e9b2 100644
--- a/arch/hexagon/include/asm/io.h
+++ b/arch/hexagon/include/asm/io.h
@@ -189,6 +189,8 @@ static inline void writel(u32 data, volatile void __iomem *addr)
 #define writew_relaxed __raw_writew
 #define writel_relaxed __raw_writel
+#define mmiowb()
 /*
 * Need an mtype somewhere in here, for cache type deals?
 * This is probably too long for an inline.
diff --git a/arch/hexagon/include/asm/kgdb.h b/arch/hexagon/include/asm/kgdb.h
index 32a6fb66944a..ccd3ac336b24 100644
--- a/arch/hexagon/include/asm/kgdb.h
+++ b/arch/hexagon/include/asm/kgdb.h
@@ -34,10 +34,11 @@ static inline void arch_kgdb_breakpoint(void)
 * 32 gpr + sa0/1 + lc0/1 + m0/1 + gp + ugp + pred + pc = 42 total.
 * vm regs = psp+elr+est+badva = 4
 * syscall+restart = 2 more
- * so 48 = 42 +4 + 2
+ * also add cs0/1 = 2
+ * so 48 = 42 + 4 + 2 + 2
 */
 #define DBG_USER_REGS 42
-#define DBG_MAX_REG_NUM (DBG_USER_REGS + 6)
+#define DBG_MAX_REG_NUM (DBG_USER_REGS + 8)
 #define NUMREGBYTES  (DBG_MAX_REG_NUM*4)
 #endif /* __HEXAGON_KGDB_H__ */
diff --git a/arch/hexagon/include/asm/pgalloc.h b/arch/hexagon/include/asm/pgalloc.h
index 4c9d382d7798..77da3b0ae3c2 100644
--- a/arch/hexagon/include/asm/pgalloc.h
+++ b/arch/hexagon/include/asm/pgalloc.h
@@ -45,7 +45,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
         * map with a copy of the kernel's persistent map.
         */
-        memcpy(pgd, swapper_pg_dir, PTRS_PER_PGD*sizeof(pgd_t *));
+        memcpy(pgd, swapper_pg_dir, PTRS_PER_PGD*sizeof(pgd_t));
        mm->context.generation = kmap_generation;
        /* Physical version is what is passed to virtual machine on switch */
diff --git a/arch/hexagon/include/asm/smp.h b/arch/hexagon/include/asm/smp.h
index 2b9b974e0952..ca171c13891d 100644
--- a/arch/hexagon/include/asm/smp.h
+++ b/arch/hexagon/include/asm/smp.h
@@ -29,7 +29,6 @@ enum ipi_message_type {
        IPI_NOP = 0,
        IPI_RESCHEDULE = 1,
        IPI_CALL_FUNC,
-        IPI_CALL_FUNC_SINGLE,
        IPI_CPU_STOP,
        IPI_TIMER,
 };
diff --git a/arch/hexagon/include/uapi/asm/registers.h b/arch/hexagon/include/uapi/asm/registers.h
index 487d6ceca5e7..e7be31840a90 100644
--- a/arch/hexagon/include/uapi/asm/registers.h
+++ b/arch/hexagon/include/uapi/asm/registers.h
@@ -6,8 +6,6 @@
 #ifndef _ASM_REGISTERS_H
 #define _ASM_REGISTERS_H
-#define SP r29
 #ifndef __ASSEMBLY__
 /*  See kernel/entry.S for further documentation.  */
@@ -215,7 +213,7 @@ struct pt_regs {
 #define pt_clr_singlestep(regs) ((regs)->hvmer.vmest &= ~(1<<HVM_VMEST_SS_SFT))
 #define pt_set_rte_sp(regs, sp) do {\
-        pt_psp(regs) = (regs)->SP = (sp);\
+        pt_psp(regs) = (regs)->r29 = (sp);\
        } while (0)
 #define pt_set_kmode(regs) \
diff --git a/arch/hexagon/include/uapi/asm/setup.h b/arch/hexagon/include/uapi/asm/setup.h
index e48285e4af96..7e3952d6221c 100644
--- a/arch/hexagon/include/uapi/asm/setup.h
+++ b/arch/hexagon/include/uapi/asm/setup.h
@@ -19,7 +19,12 @@
 #ifndef _ASM_SETUP_H
 #define _ASM_SETUP_H
+#ifdef __KERNEL__
 #include <linux/init.h>
+#else
+#define __init
+#endif
 #include <asm-generic/setup.h>
 extern char external_cmdline_buffer;
diff --git a/arch/hexagon/kernel/Makefile b/arch/hexagon/kernel/Makefile
index 29fc933a7722..009228b8611c 100644
--- a/arch/hexagon/kernel/Makefile
+++ b/arch/hexagon/kernel/Makefile
@@ -15,3 +15,5 @@ obj-y += vm_vectors.o
 obj-$(CONFIG_HAS_DMA) += dma.o
 obj-$(CONFIG_STACKTRACE) += stacktrace.o
+obj-$(CONFIG_VGA_CONSOLE) += screen_info.o
diff --git a/arch/hexagon/kernel/hexagon_ksyms.c b/arch/hexagon/kernel/hexagon_ksyms.c
index 32b1379d6877..c041d8ecb1e2 100644
--- a/arch/hexagon/kernel/hexagon_ksyms.c
+++ b/arch/hexagon/kernel/hexagon_ksyms.c
@@ -18,23 +18,39 @@
 * 02110-1301, USA.
 */
+#include <linux/dma-mapping.h>
 #include <asm/hexagon_vm.h>
+#include <asm/io.h>
 #include <asm/uaccess.h>
+/* Additional functions */
+EXPORT_SYMBOL(__clear_user_hexagon);
 EXPORT_SYMBOL(__copy_from_user_hexagon);
 EXPORT_SYMBOL(__copy_to_user_hexagon);
+EXPORT_SYMBOL(__iounmap);
+EXPORT_SYMBOL(__strnlen_user);
 EXPORT_SYMBOL(__vmgetie);
 EXPORT_SYMBOL(__vmsetie);
+EXPORT_SYMBOL(__vmyield);
+EXPORT_SYMBOL(empty_zero_page);
+EXPORT_SYMBOL(ioremap_nocache);
 EXPORT_SYMBOL(memcpy);
 EXPORT_SYMBOL(memset);
+/* Additional variables */
+EXPORT_SYMBOL(__phys_offset);
+EXPORT_SYMBOL(_dflt_cache_att);
+EXPORT_SYMBOL(bad_dma_address);
 #define DECLARE_EXPORT(name)     \
        extern void name(void); EXPORT_SYMBOL(name)
 /* Symbols found in libgcc that assorted kernel modules need */
 DECLARE_EXPORT(__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes);
-DECLARE_EXPORT(__hexagon_divsi3);
+/* Additional functions */
-DECLARE_EXPORT(__hexagon_modsi3);
+DECLARE_EXPORT(__divsi3);
-DECLARE_EXPORT(__hexagon_udivsi3);
+DECLARE_EXPORT(__modsi3);
-DECLARE_EXPORT(__hexagon_umodsi3);
+DECLARE_EXPORT(__udivsi3);
+DECLARE_EXPORT(__umodsi3);
+DECLARE_EXPORT(csum_tcpudp_magic);
diff --git a/arch/hexagon/kernel/kgdb.c b/arch/hexagon/kernel/kgdb.c
index 82d5c2593323..038580cc5abf 100644
--- a/arch/hexagon/kernel/kgdb.c
+++ b/arch/hexagon/kernel/kgdb.c
@@ -18,6 +18,8 @@
 * 02110-1301, USA.
 */
+#include <linux/irq.h>
+#include <linux/sched.h>
 #include <linux/kdebug.h>
 #include <linux/kgdb.h>
diff --git a/arch/hexagon/kernel/ptrace.c b/arch/hexagon/kernel/ptrace.c
index de829eb7f185..390a9ad14ca1 100644
--- a/arch/hexagon/kernel/ptrace.c
+++ b/arch/hexagon/kernel/ptrace.c
@@ -183,6 +183,7 @@ static const struct user_regset_view hexagon_user_view = {
        .e_machine = ELF_ARCH,
        .ei_osabi = ELF_OSABI,
        .regsets = hexagon_regsets,
+        .e_flags = ELF_CORE_EFLAGS,
        .n = ARRAY_SIZE(hexagon_regsets)
 };
diff --git a/arch/hexagon/kernel/reset.c b/arch/hexagon/kernel/reset.c
index 6aeabc962b3b..76483c10130d 100644
--- a/arch/hexagon/kernel/reset.c
+++ b/arch/hexagon/kernel/reset.c
@@ -33,6 +33,5 @@ void machine_restart(char *cmd)
 {
 }
-void pm_power_off(void)
+void (*pm_power_off)(void) = NULL;
-{
+EXPORT_SYMBOL(pm_power_off);
-}
diff --git a/arch/hexagon/kernel/screen_info.c b/arch/hexagon/kernel/screen_info.c
new file mode 100644
index 000000000000..1e1ceb18bafe
--- /dev/null
+++ b/arch/hexagon/kernel/screen_info.c
@@ -0,0 +1,3 @@
+#include <linux/screen_info.h>
+struct screen_info screen_info;
diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c
index 9faaa940452b..ff759f26b96a 100644
--- a/arch/hexagon/kernel/smp.c
+++ b/arch/hexagon/kernel/smp.c
@@ -64,10 +64,6 @@ static inline void __handle_ipi(unsigned long *ops, struct ipi_data *ipi,
                        generic_smp_call_function_interrupt();
                        break;
-                case IPI_CALL_FUNC_SINGLE:
-                        generic_smp_call_function_single_interrupt();
-                        break;
                case IPI_CPU_STOP:
                        /*
                         * call vmstop()
@@ -248,7 +244,7 @@ void smp_send_stop(void)
 void arch_send_call_function_single_ipi(int cpu)
 {
-        send_ipi(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
+        send_ipi(cpumask_of(cpu), IPI_CALL_FUNC);
 }
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
diff --git a/arch/hexagon/kernel/time.c b/arch/hexagon/kernel/time.c
index 9903fad997f3..17fbf45bf150 100644
--- a/arch/hexagon/kernel/time.c
+++ b/arch/hexagon/kernel/time.c
@@ -191,9 +191,6 @@ void __init time_init_deferred(void)
 {
        struct resource *resource = NULL;
        struct clock_event_device *ce_dev = &hexagon_clockevent_dev;
-        struct device_node *dn;
-        struct resource r;
-        int err;
        ce_dev->cpumask = cpu_all_mask;
@@ -232,6 +229,15 @@ void __init time_init(void)
        late_time_init = time_init_deferred;
 }
+void __delay(unsigned long cycles)
+{
+        unsigned long long start = __vmgettime();
+        while ((__vmgettime() - start) < cycles)
+                cpu_relax();
+}
+EXPORT_SYMBOL(__delay);
 /*
 * This could become parametric or perhaps even computed at run-time,
 * but for now we take the observed simulator jitter.
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 0c8e553e0b9f..12c3afee0f6f 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -21,6 +21,7 @@ config IA64
        select HAVE_FUNCTION_TRACER
        select HAVE_DMA_ATTRS
        select HAVE_KVM
+        select TTY
        select HAVE_ARCH_TRACEHOOK
        select HAVE_DMA_API_DEBUG
        select HAVE_MEMBLOCK
@@ -44,6 +45,7 @@ config IA64
        select HAVE_MOD_ARCH_SPECIFIC
        select MODULES_USE_ELF_RELA
        select ARCH_USE_CMPXCHG_LOCKREF
+        select HAVE_ARCH_AUDITSYSCALL
        default y
        help
          The Itanium Processor Family is Intel's 64-bit successor to
diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig
index 6404acbb84b2..b4efaf2bc13e 100644
--- a/arch/ia64/configs/generic_defconfig
+++ b/arch/ia64/configs/generic_defconfig
@@ -25,7 +25,6 @@ CONFIG_KEXEC=y
 CONFIG_CRASH_DUMP=y
 CONFIG_EFI_VARS=y
 CONFIG_BINFMT_MISC=m
-CONFIG_ACPI_PROCFS=y
 CONFIG_ACPI_BUTTON=m
 CONFIG_ACPI_FAN=m
 CONFIG_ACPI_DOCK=y
diff --git a/arch/ia64/configs/tiger_defconfig b/arch/ia64/configs/tiger_defconfig
index 0f4e9e41f130..0fed9ae5a42a 100644
--- a/arch/ia64/configs/tiger_defconfig
+++ b/arch/ia64/configs/tiger_defconfig
@@ -26,7 +26,6 @@ CONFIG_IA64_PALINFO=y
 CONFIG_KEXEC=y
 CONFIG_EFI_VARS=y
 CONFIG_BINFMT_MISC=m
-CONFIG_ACPI_PROCFS=y
 CONFIG_ACPI_BUTTON=m
 CONFIG_ACPI_FAN=m
 CONFIG_ACPI_PROCESSOR=m
diff --git a/arch/ia64/configs/zx1_defconfig b/arch/ia64/configs/zx1_defconfig
index fc7aba07c2b4..54bc72eda30d 100644
--- a/arch/ia64/configs/zx1_defconfig
+++ b/arch/ia64/configs/zx1_defconfig
@@ -16,7 +16,6 @@ CONFIG_IA64_PALINFO=y
 CONFIG_CRASH_DUMP=y
 CONFIG_EFI_VARS=y
 CONFIG_BINFMT_MISC=y
-CONFIG_ACPI_PROCFS=y
 CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_ACPI=y
 CONFIG_PACKET=y
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index 30c43d39dede..1a871b78e570 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -1140,11 +1140,13 @@ sba_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
 #ifdef CONFIG_NUMA
        {
+                int node = ioc->node;
                struct page *page;
-                page = alloc_pages_exact_node(ioc->node == MAX_NUMNODES ?
-                                        numa_node_id() : ioc->node, flags,
-                                        get_order(size));
+                if (node == NUMA_NO_NODE)
+                        node = numa_node_id();
+                page = alloc_pages_exact_node(node, flags, get_order(size));
                if (unlikely(!page))
                        return NULL;
@@ -1914,7 +1916,7 @@ ioc_show(struct seq_file *s, void *v)
        seq_printf(s, "Hewlett Packard %s IOC rev %d.%d\n",
                ioc->name, ((ioc->rev >> 4) & 0xF), (ioc->rev & 0xF));
 #ifdef CONFIG_NUMA
-        if (ioc->node != MAX_NUMNODES)
+        if (ioc->node != NUMA_NO_NODE)
                seq_printf(s, "NUMA node       : %d\n", ioc->node);
 #endif
        seq_printf(s, "IOVA size       : %ld MB\n", ((ioc->pdir_size >> 3) * iovp_size)/(1024*1024));
@@ -2015,31 +2017,19 @@ sba_connect_bus(struct pci_bus *bus)
        printk(KERN_WARNING "No IOC for PCI Bus %04x:%02x in ACPI\n", pci_domain_nr(bus), bus->number);
 }
-#ifdef CONFIG_NUMA
 static void __init
 sba_map_ioc_to_node(struct ioc *ioc, acpi_handle handle)
 {
+#ifdef CONFIG_NUMA
        unsigned int node;
-        int pxm;
-        ioc->node = MAX_NUMNODES;
-        pxm = acpi_get_pxm(handle);
-        if (pxm < 0)
-                return;
-        node = pxm_to_node(pxm);
-        if (node >= MAX_NUMNODES || !node_online(node))
+        node = acpi_get_node(handle);
-                return;
+        if (node != NUMA_NO_NODE && !node_online(node))
+                node = NUMA_NO_NODE;
        ioc->node = node;
-        return;
-}
-#else
-#define sba_map_ioc_to_node(ioc, handle)
 #endif
+}
 static int
 acpi_sba_ioc_add(struct acpi_device *device,
diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
index 71fbaaa495cc..7d41cc089822 100644
--- a/arch/ia64/include/asm/pci.h
+++ b/arch/ia64/include/asm/pci.h
@@ -98,7 +98,7 @@ struct pci_controller {
        struct acpi_device *companion;
        void *iommu;
        int segment;
-        int node;               /* nearest node with memory or -1 for global allocation */
+        int node;               /* nearest node with memory or NUMA_NO_NODE for global allocation */
        void *platform_data;
 };
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 07d209c9507f..0d407b300762 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -54,10 +54,6 @@
 #include <asm/sal.h>
 #include <asm/cyclone.h>
-#define BAD_MADT_ENTRY(entry, end) (                                        \
-                (!entry) || (unsigned long)entry + sizeof(*entry) > end ||  \
-                ((struct acpi_subtable_header *)entry)->length < sizeof(*entry))
 #define PREFIX                  "ACPI: "
 unsigned int acpi_cpei_override;
@@ -803,14 +799,9 @@ int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi)
 *  ACPI based hotplug CPU support
 */
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
-static
+static int acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
-int acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
 {
 #ifdef CONFIG_ACPI_NUMA
-        int pxm_id;
-        int nid;
-        pxm_id = acpi_get_pxm(handle);
        /*
         * We don't have cpu-only-node hotadd. But if the system equips
         * SRAT table, pxm is already found and node is ready.
@@ -818,11 +809,10 @@ int acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
         * This code here is for the system which doesn't have full SRAT
         * table for possible cpus.
         */
-        nid = acpi_map_pxm_to_node(pxm_id);
        node_cpuid[cpu].phys_id = physid;
-        node_cpuid[cpu].nid = nid;
+        node_cpuid[cpu].nid = acpi_get_node(handle);
 #endif
-        return (0);
+        return 0;
 }
 int additional_cpus __initdata = -1;
@@ -929,7 +919,7 @@ static acpi_status acpi_map_iosapic(acpi_handle handle, u32 depth,
        union acpi_object *obj;
        struct acpi_madt_io_sapic *iosapic;
        unsigned int gsi_base;
-        int pxm, node;
+        int node;
        /* Only care about objects w/ a method that returns the MADT */
        if (ACPI_FAILURE(acpi_evaluate_object(handle, "_MAT", NULL, &buffer)))
@@ -956,17 +946,9 @@ static acpi_status acpi_map_iosapic(acpi_handle handle, u32 depth,
        kfree(buffer.pointer);
-        /*
+        /* OK, it's an IOSAPIC MADT entry; associate it with a node */
-         * OK, it's an IOSAPIC MADT entry, look for a _PXM value to tell
+        node = acpi_get_node(handle);
-         * us which node to associate this with.
+        if (node == NUMA_NO_NODE || !node_online(node) ||
-         */
-        pxm = acpi_get_pxm(handle);
-        if (pxm < 0)
-                return AE_OK;
-        node = pxm_to_node(pxm);
-        if (node >= MAX_NUMNODES || !node_online(node) ||
            cpumask_empty(cpumask_of_node(node)))
                return AE_OK;
diff --git a/arch/ia64/kernel/err_inject.c b/arch/ia64/kernel/err_inject.c
index f59c0b844e88..0c161ed6d18e 100644
--- a/arch/ia64/kernel/err_inject.c
+++ b/arch/ia64/kernel/err_inject.c
@@ -269,12 +269,17 @@ err_inject_init(void)
 #ifdef ERR_INJ_DEBUG
        printk(KERN_INFO "Enter error injection driver.\n");
 #endif
+        cpu_notifier_register_begin();
        for_each_online_cpu(i) {
                err_inject_cpu_callback(&err_inject_cpu_notifier, CPU_ONLINE,
                                (void *)(long)i);
        }
-        register_hotcpu_notifier(&err_inject_cpu_notifier);
+        __register_hotcpu_notifier(&err_inject_cpu_notifier);
+        cpu_notifier_register_done();
        return 0;
 }
@@ -288,11 +293,17 @@ err_inject_exit(void)
 #ifdef ERR_INJ_DEBUG
        printk(KERN_INFO "Exit error injection driver.\n");
 #endif
+        cpu_notifier_register_begin();
        for_each_online_cpu(i) {
                sys_dev = get_cpu_device(i);
                sysfs_remove_group(&sys_dev->kobj, &err_inject_attr_group);
        }
-        unregister_hotcpu_notifier(&err_inject_cpu_notifier);
+        __unregister_hotcpu_notifier(&err_inject_cpu_notifier);
+        cpu_notifier_register_done();
 }
 module_init(err_inject_init);
diff --git a/arch/ia64/kernel/ftrace.c b/arch/ia64/kernel/ftrace.c
index 7fc8c961b1f7..3b0c2aa07857 100644
--- a/arch/ia64/kernel/ftrace.c
+++ b/arch/ia64/kernel/ftrace.c
@@ -198,9 +198,7 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
 }
 /* run from kstop_machine */
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        *(unsigned long *)data = 0;
        return 0;
 }
diff --git a/arch/ia64/kernel/palinfo.c b/arch/ia64/kernel/palinfo.c
index ab333284f4b2..c39c3cd3ac34 100644
--- a/arch/ia64/kernel/palinfo.c
+++ b/arch/ia64/kernel/palinfo.c
@@ -996,13 +996,17 @@ palinfo_init(void)
        if (!palinfo_dir)
                return -ENOMEM;
+        cpu_notifier_register_begin();
        /* Create palinfo dirs in /proc for all online cpus */
        for_each_online_cpu(i) {
                create_palinfo_proc_entries(i);
        }
        /* Register for future delivery via notify registration */
-        register_hotcpu_notifier(&palinfo_cpu_notifier);
+        __register_hotcpu_notifier(&palinfo_cpu_notifier);
+        cpu_notifier_register_done();
        return 0;
 }
diff --git a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c
index 960a396f5929..ee9719eebb1e 100644
--- a/arch/ia64/kernel/salinfo.c
+++ b/arch/ia64/kernel/salinfo.c
@@ -635,6 +635,8 @@ salinfo_init(void)
                                           (void *)salinfo_entries[i].feature);
        }
+        cpu_notifier_register_begin();
        for (i = 0; i < ARRAY_SIZE(salinfo_log_name); i++) {
                data = salinfo_data + i;
                data->type = i;
@@ -669,7 +671,9 @@ salinfo_init(void)
        salinfo_timer.function = &salinfo_timeout;
        add_timer(&salinfo_timer);
-        register_hotcpu_notifier(&salinfo_cpu_notifier);
+        __register_hotcpu_notifier(&salinfo_cpu_notifier);
+        cpu_notifier_register_done();
        return 0;
 }
diff --git a/arch/ia64/kernel/topology.c b/arch/ia64/kernel/topology.c
index ca69a5a96dcc..f295f9abba4b 100644
--- a/arch/ia64/kernel/topology.c
+++ b/arch/ia64/kernel/topology.c
@@ -454,12 +454,16 @@ static int __init cache_sysfs_init(void)
 {
        int i;
+        cpu_notifier_register_begin();
        for_each_online_cpu(i) {
                struct device *sys_dev = get_cpu_device((unsigned int)i);
                cache_add_dev(sys_dev);
        }
-        register_hotcpu_notifier(&cache_cpu_notifier);
+        __register_hotcpu_notifier(&cache_cpu_notifier);
+        cpu_notifier_register_done();
        return 0;
 }
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 53f44bee9ebb..6a4309bb821a 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -199,6 +199,7 @@ int kvm_dev_ioctl_check_extension(long ext)
        case KVM_CAP_IRQCHIP:
        case KVM_CAP_MP_STATE:
        case KVM_CAP_IRQ_INJECT_STATUS:
+        case KVM_CAP_IOAPIC_POLARITY_IGNORED:
                r = 1;
                break;
        case KVM_CAP_COALESCED_MMIO:
diff --git a/arch/ia64/pci/fixup.c b/arch/ia64/pci/fixup.c
index 5dc969dd4ac0..eee069a0b539 100644
--- a/arch/ia64/pci/fixup.c
+++ b/arch/ia64/pci/fixup.c
@@ -5,6 +5,7 @@
 #include <linux/pci.h>
 #include <linux/init.h>
+#include <linux/vgaarb.h>
 #include <asm/machvec.h>
@@ -19,9 +20,10 @@
 * IORESOURCE_ROM_SHADOW is used to associate the boot video
 * card with this copy. On laptops this copy has to be used since
 * the main ROM may be compressed or combined with another image.
- * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
+ * See pci_map_rom() for use of this flag. Before marking the device
- * is marked here since the boot video device will be the only enabled
+ * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
- * video device at this point.
+ * by either arch cde or vga-arbitration, if so only apply the fixup to this
+ * already determined primary video card.
 */
 static void pci_fixup_video(struct pci_dev *pdev)
@@ -35,9 +37,6 @@ static void pci_fixup_video(struct pci_dev *pdev)
                return;
        /* Maybe, this machine supports legacy memory map. */
-        if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
-                return;
        /* Is VGA routed to us? */
        bus = pdev->bus;
        while (bus) {
@@ -60,10 +59,14 @@ static void pci_fixup_video(struct pci_dev *pdev)
                }
                bus = bus->parent;
        }
-        pci_read_config_word(pdev, PCI_COMMAND, &config);
+        if (!vga_default_device() || pdev == vga_default_device()) {
-        if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
+                pci_read_config_word(pdev, PCI_COMMAND, &config);
-                pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
+                if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
-                dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
+                        pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
+                        dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
+                        vga_set_default_device(pdev);
+                }
        }
 }
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
+                                PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 9e4938d8ca4d..291a582777cf 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -126,7 +126,6 @@ static struct pci_controller *alloc_pci_controller(int seg)
                return NULL;
        controller->segment = seg;
-        controller->node = -1;
        return controller;
 }
@@ -430,19 +429,14 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
        struct pci_root_info *info = NULL;
        int busnum = root->secondary.start;
        struct pci_bus *pbus;
-        int pxm, ret;
+        int ret;
        controller = alloc_pci_controller(domain);
        if (!controller)
                return NULL;
        controller->companion = device;
+        controller->node = acpi_get_node(device->handle);
-        pxm = acpi_get_pxm(device->handle);
-#ifdef CONFIG_NUMA
-        if (pxm >= 0)
-                controller->node = pxm_to_node(pxm);
-#endif
        info = kzalloc(sizeof(*info), GFP_KERNEL);
        if (!info) {
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index ca4504424dae..9e44bbd8051e 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -28,7 +28,7 @@ config ZONE_DMA
        bool
        default y
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool y
 config NO_DMA
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index b2e322939256..87b7c7581b1d 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -52,7 +52,7 @@ config TIME_LOW_RES
        bool
        default y
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool y
 config NO_DMA
diff --git a/arch/m68k/configs/m5208evb_defconfig b/arch/m68k/configs/m5208evb_defconfig
index c1616824e201..e7292f460af4 100644
--- a/arch/m68k/configs/m5208evb_defconfig
+++ b/arch/m68k/configs/m5208evb_defconfig
@@ -40,7 +40,6 @@ CONFIG_INET=y
 # CONFIG_IPV6 is not set
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_RAM=y
diff --git a/arch/m68k/configs/m5249evb_defconfig b/arch/m68k/configs/m5249evb_defconfig
index a6599e42facf..0cd4b39f325b 100644
--- a/arch/m68k/configs/m5249evb_defconfig
+++ b/arch/m68k/configs/m5249evb_defconfig
@@ -38,7 +38,6 @@ CONFIG_INET=y
 # CONFIG_IPV6 is not set
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_RAM=y
diff --git a/arch/m68k/configs/m5272c3_defconfig b/arch/m68k/configs/m5272c3_defconfig
index 3fa60a57a0f9..a60cb3509135 100644
--- a/arch/m68k/configs/m5272c3_defconfig
+++ b/arch/m68k/configs/m5272c3_defconfig
@@ -36,7 +36,6 @@ CONFIG_INET=y
 # CONFIG_IPV6 is not set
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_RAM=y
diff --git a/arch/m68k/configs/m5275evb_defconfig b/arch/m68k/configs/m5275evb_defconfig
index a1230e82bb1e..e6502ab7cb2f 100644
--- a/arch/m68k/configs/m5275evb_defconfig
+++ b/arch/m68k/configs/m5275evb_defconfig
@@ -39,7 +39,6 @@ CONFIG_INET=y
 # CONFIG_IPV6 is not set
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_RAM=y
diff --git a/arch/m68k/configs/m5307c3_defconfig b/arch/m68k/configs/m5307c3_defconfig
index 43795f41f7c7..023812abd2e6 100644
--- a/arch/m68k/configs/m5307c3_defconfig
+++ b/arch/m68k/configs/m5307c3_defconfig
@@ -38,7 +38,6 @@ CONFIG_INET=y
 # CONFIG_IPV6 is not set
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_RAM=y
diff --git a/arch/m68k/configs/m5407c3_defconfig b/arch/m68k/configs/m5407c3_defconfig
index 72746c57a571..557b39f3be90 100644
--- a/arch/m68k/configs/m5407c3_defconfig
+++ b/arch/m68k/configs/m5407c3_defconfig
@@ -38,7 +38,6 @@ CONFIG_INET=y
 # CONFIG_IPV6 is not set
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_RAM=y
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
index e1534783e94e..52f7e8499172 100644
--- a/arch/m68k/include/asm/io_no.h
+++ b/arch/m68k/include/asm/io_no.h
@@ -55,7 +55,7 @@ static inline unsigned int _swapl(volatile unsigned long v)
 #define __raw_writew writew
 #define __raw_writel writel
-static inline void io_outsb(unsigned int addr, void *buf, int len)
+static inline void io_outsb(unsigned int addr, const void *buf, int len)
 {
        volatile unsigned char *ap = (volatile unsigned char *) addr;
        unsigned char *bp = (unsigned char *) buf;
@@ -63,7 +63,7 @@ static inline void io_outsb(unsigned int addr, void *buf, int len)
                *ap = *bp++;
 }
-static inline void io_outsw(unsigned int addr, void *buf, int len)
+static inline void io_outsw(unsigned int addr, const void *buf, int len)
 {
        volatile unsigned short *ap = (volatile unsigned short *) addr;
        unsigned short *bp = (unsigned short *) buf;
@@ -71,7 +71,7 @@ static inline void io_outsw(unsigned int addr, void *buf, int len)
                *ap = _swapw(*bp++);
 }
-static inline void io_outsl(unsigned int addr, void *buf, int len)
+static inline void io_outsl(unsigned int addr, const void *buf, int len)
 {
        volatile unsigned int *ap = (volatile unsigned int *) addr;
        unsigned int *bp = (unsigned int *) buf;
diff --git a/arch/metag/Kconfig b/arch/metag/Kconfig
index e56abd2c1b4f..499b7610eaaf 100644
--- a/arch/metag/Kconfig
+++ b/arch/metag/Kconfig
@@ -9,6 +9,7 @@ config METAG
        select HAVE_ARCH_TRACEHOOK
        select HAVE_C_RECORDMCOUNT
        select HAVE_DEBUG_KMEMLEAK
+        select HAVE_DEBUG_STACKOVERFLOW
        select HAVE_DYNAMIC_FTRACE
        select HAVE_FTRACE_MCOUNT_RECORD
        select HAVE_FUNCTION_TRACER
@@ -29,7 +30,6 @@ config METAG
        select OF
        select OF_EARLY_FLATTREE
        select SPARSE_IRQ
-        select HAVE_DEBUG_STACKOVERFLOW
 config STACKTRACE_SUPPORT
        def_bool y
@@ -52,7 +52,7 @@ config GENERIC_HWEIGHT
 config GENERIC_CALIBRATE_DELAY
        def_bool y
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool y
 source "init/Kconfig"
diff --git a/arch/metag/include/asm/topology.h b/arch/metag/include/asm/topology.h
index 8e9c0b3b9691..e95f874ded1b 100644
--- a/arch/metag/include/asm/topology.h
+++ b/arch/metag/include/asm/topology.h
@@ -3,33 +3,6 @@
 #ifdef CONFIG_NUMA
-/* sched_domains SD_NODE_INIT for Meta machines */
-#define SD_NODE_INIT (struct sched_domain) {            \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
-        .min_interval           = 8,                    \
-        .max_interval           = 32,                   \
-        .busy_factor            = 32,                   \
-        .imbalance_pct          = 125,                  \
-        .cache_nice_tries       = 2,                    \
-        .busy_idx               = 3,                    \
-        .idle_idx               = 2,                    \
-        .newidle_idx            = 0,                    \
-        .wake_idx               = 0,                    \
-        .forkexec_idx           = 0,                    \
-        .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_FORK       \
-                                | SD_BALANCE_EXEC       \
-                                | SD_BALANCE_NEWIDLE    \
-                                | SD_SERIALIZE,         \
-        .last_balance           = jiffies,              \
-        .balance_interval       = 1,                    \
-        .nr_balance_failed      = 0,                    \
-        .max_newidle_lb_cost    = 0,                    \
-        .next_decay_max_lb_cost = jiffies,              \
-}
 #define cpu_to_node(cpu)        ((void)(cpu), 0)
 #define parent_node(node)       ((void)(node), 0)
diff --git a/arch/metag/kernel/ftrace.c b/arch/metag/kernel/ftrace.c
index a774f321643f..ed1d685157c2 100644
--- a/arch/metag/kernel/ftrace.c
+++ b/arch/metag/kernel/ftrace.c
@@ -117,10 +117,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
 }
 /* run from kstop_machine */
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        /* The return code is returned via data */
-        writel(0, data);
        return 0;
 }
diff --git a/arch/metag/kernel/irq.c b/arch/metag/kernel/irq.c
index 3b4b7f6c0950..5385dd1216b7 100644
--- a/arch/metag/kernel/irq.c
+++ b/arch/metag/kernel/irq.c
@@ -261,18 +261,6 @@ int __init arch_probe_nr_irqs(void)
 }
 #ifdef CONFIG_HOTPLUG_CPU
-static void route_irq(struct irq_data *data, unsigned int irq, unsigned int cpu)
-{
-        struct irq_desc *desc = irq_to_desc(irq);
-        struct irq_chip *chip = irq_data_get_irq_chip(data);
-        unsigned long flags;
-        raw_spin_lock_irqsave(&desc->lock, flags);
-        if (chip->irq_set_affinity)
-                chip->irq_set_affinity(data, cpumask_of(cpu), false);
-        raw_spin_unlock_irqrestore(&desc->lock, flags);
-}
 /*
 * The CPU has been marked offline.  Migrate IRQs off this CPU.  If
 * the affinity settings do not allow other CPUs, force them onto any
@@ -281,10 +269,9 @@ static void route_irq(struct irq_data *data, unsigned int irq, unsigned int cpu)
 void migrate_irqs(void)
 {
        unsigned int i, cpu = smp_processor_id();
-        struct irq_desc *desc;
-        for_each_irq_desc(i, desc) {
+        for_each_active_irq(i) {
-                struct irq_data *data = irq_desc_get_irq_data(desc);
+                struct irq_data *data = irq_get_irq_data(i);
                unsigned int newcpu;
                if (irqd_is_per_cpu(data))
@@ -300,11 +287,8 @@ void migrate_irqs(void)
                                            i, cpu);
                        cpumask_setall(data->affinity);
-                        newcpu = cpumask_any_and(data->affinity,
-                                                 cpu_online_mask);
                }
+                irq_set_affinity(i, data->affinity);
-                route_irq(data, i, newcpu);
        }
 }
 #endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/metag/kernel/signal.c b/arch/metag/kernel/signal.c
index 3be61cf0b147..b9e4a82d2bd4 100644
--- a/arch/metag/kernel/signal.c
+++ b/arch/metag/kernel/signal.c
@@ -152,18 +152,18 @@ static void __user *get_sigframe(struct k_sigaction *ka, unsigned long sp,
        return (void __user *)sp;
 }
-static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
-                          sigset_t *set, struct pt_regs *regs)
+                          struct pt_regs *regs)
 {
        struct rt_sigframe __user *frame;
-        int err = -EFAULT;
+        int err;
        unsigned long code;
-        frame = get_sigframe(ka, regs->REG_SP, sizeof(*frame));
+        frame = get_sigframe(&ksig->ka, regs->REG_SP, sizeof(*frame));
        if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
-                goto out;
+                return -EFAULT;
-        err = copy_siginfo_to_user(&frame->info, info);
+        err = copy_siginfo_to_user(&frame->info, &ksig->info);
        /* Create the ucontext.  */
        err |= __put_user(0, &frame->uc.uc_flags);
@@ -174,7 +174,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
        err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
        if (err)
-                goto out;
+                return -EFAULT;
        /* Set up to return from userspace.  */
@@ -187,15 +187,15 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
        err |= __put_user(code, (unsigned long __user *)(&frame->retcode[1]));
        if (err)
-                goto out;
+                return -EFAULT;
        /* Set up registers for signal handler */
        regs->REG_RTP = (unsigned long) frame->retcode;
        regs->REG_SP = (unsigned long) frame + sizeof(*frame);
-        regs->REG_ARG1 = sig;
+        regs->REG_ARG1 = ksig->sig;
        regs->REG_ARG2 = (unsigned long) &frame->info;
        regs->REG_ARG3 = (unsigned long) &frame->uc;
-        regs->REG_PC = (unsigned long) ka->sa.sa_handler;
+        regs->REG_PC = (unsigned long) ksig->ka.sa.sa_handler;
        pr_debug("SIG deliver (%s:%d): sp=%p pc=%08x pr=%08x\n",
                 current->comm, current->pid, frame, regs->REG_PC,
@@ -205,24 +205,19 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         * effective cache flush - directed rather than 'full flush'.
         */
        flush_cache_sigtramp(regs->REG_RTP, sizeof(frame->retcode));
-out:
-        if (err) {
-                force_sigsegv(sig, current);
-                return -EFAULT;
-        }
        return 0;
 }
-static void handle_signal(unsigned long sig, siginfo_t *info,
+static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-                          struct k_sigaction *ka, struct pt_regs *regs)
 {
        sigset_t *oldset = sigmask_to_save();
+        int ret;
        /* Set up the stack frame */
-        if (setup_rt_frame(sig, ka, info, oldset, regs))
+        ret = setup_rt_frame(ksig, oldset, regs);
-                return;
-        signal_delivered(sig, info, ka, regs, test_thread_flag(TIF_SINGLESTEP));
+        signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
 }
 /*
@@ -235,10 +230,8 @@ static void handle_signal(unsigned long sig, siginfo_t *info,
 static int do_signal(struct pt_regs *regs, int syscall)
 {
        unsigned int retval = 0, continue_addr = 0, restart_addr = 0;
-        struct k_sigaction ka;
-        siginfo_t info;
-        int signr;
        int restart = 0;
+        struct ksignal ksig;
        /*
         * By the end of rt_sigreturn the context describes the point that the
@@ -275,7 +268,8 @@ static int do_signal(struct pt_regs *regs, int syscall)
         * Get the signal to deliver. When running under ptrace, at this point
         * the debugger may change all our registers ...
         */
-        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+        get_signal(&ksig);
        /*
         * Depending on the signal settings we may need to revert the decision
         * to restart the system call. But skip this if a debugger has chosen to
@@ -283,19 +277,19 @@ static int do_signal(struct pt_regs *regs, int syscall)
         */
        if (regs->REG_PC != restart_addr)
                restart = 0;
-        if (signr > 0) {
+        if (ksig.sig > 0) {
                if (unlikely(restart)) {
                        if (retval == -ERESTARTNOHAND
                            || retval == -ERESTART_RESTARTBLOCK
                            || (retval == -ERESTARTSYS
-                                && !(ka.sa.sa_flags & SA_RESTART))) {
+                                && !(ksig.ka.sa.sa_flags & SA_RESTART))) {
                                regs->REG_RETVAL = -EINTR;
                                regs->REG_PC = continue_addr;
                        }
                }
                /* Whee! Actually deliver the signal.  */
-                handle_signal(signr, &info, &ka, regs);
+                handle_signal(&ksig, regs);
                return 0;
        }
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 79b9bcdfe498..9ae08541e30d 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -1,38 +1,38 @@
 config MICROBLAZE
        def_bool y
        select ARCH_MIGHT_HAVE_PC_PARPORT
-        select HAVE_MEMBLOCK
-        select HAVE_MEMBLOCK_NODE_MAP
-        select HAVE_FUNCTION_TRACER
-        select HAVE_FUNCTION_TRACE_MCOUNT_TEST
-        select HAVE_FUNCTION_GRAPH_TRACER
-        select HAVE_DYNAMIC_FTRACE
-        select HAVE_FTRACE_MCOUNT_RECORD
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select HAVE_OPROFILE
-        select HAVE_ARCH_KGDB
-        select HAVE_DMA_ATTRS
-        select HAVE_DMA_API_DEBUG
-        select TRACING_SUPPORT
-        select OF
-        select OF_EARLY_FLATTREE
        select ARCH_WANT_IPC_PARSE_VERSION
-        select HAVE_DEBUG_KMEMLEAK
+        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select IRQ_DOMAIN
+        select BUILDTIME_EXTABLE_SORT
-        select VIRT_TO_BUS
+        select CLKSRC_OF
+        select CLONE_BACKWARDS3
+        select COMMON_CLK
+        select GENERIC_ATOMIC64
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_CPU_DEVICES
+        select GENERIC_IDLE_POLL_SETUP
        select GENERIC_IRQ_PROBE
        select GENERIC_IRQ_SHOW
        select GENERIC_PCI_IOMAP
-        select GENERIC_CPU_DEVICES
-        select GENERIC_ATOMIC64
-        select GENERIC_CLOCKEVENTS
-        select COMMON_CLK
        select GENERIC_SCHED_CLOCK
-        select GENERIC_IDLE_POLL_SETUP
+        select HAVE_ARCH_KGDB
+        select HAVE_DEBUG_KMEMLEAK
+        select HAVE_DMA_API_DEBUG
+        select HAVE_DMA_ATTRS
+        select HAVE_DYNAMIC_FTRACE
+        select HAVE_FTRACE_MCOUNT_RECORD
+        select HAVE_FUNCTION_GRAPH_TRACER
+        select HAVE_FUNCTION_TRACE_MCOUNT_TEST
+        select HAVE_FUNCTION_TRACER
+        select HAVE_MEMBLOCK
+        select HAVE_MEMBLOCK_NODE_MAP
+        select HAVE_OPROFILE
+        select IRQ_DOMAIN
        select MODULES_USE_ELF_RELA
-        select CLONE_BACKWARDS3
+        select OF
-        select CLKSRC_OF
+        select OF_EARLY_FLATTREE
-        select BUILDTIME_EXTABLE_SORT
+        select TRACING_SUPPORT
+        select VIRT_TO_BUS
 config SWAP
        def_bool n
@@ -74,7 +74,7 @@ source "init/Kconfig"
 source "kernel/Kconfig.freezer"
-source "arch/microblaze/platform/Kconfig.platform"
+source "arch/microblaze/Kconfig.platform"
 menu "Processor type and features"
diff --git a/arch/microblaze/platform/Kconfig.platform b/arch/microblaze/Kconfig.platform
index db1aa5c22cea..1b3d8c849101 100644
--- a/arch/microblaze/platform/Kconfig.platform
+++ b/arch/microblaze/Kconfig.platform
@@ -5,18 +5,6 @@
 #
 menu "Platform options"
-choice
-        prompt "Platform"
-        default PLATFORM_MICROBLAZE_AUTO
-        help
-          Choose which hardware board/platform you are targeting.
-config PLATFORM_GENERIC
-        bool "Generic"
-        help
-          Choose this option for the Generic platform.
-endchoice
 config OPT_LIB_FUNCTION
        bool "Optimalized lib function"
@@ -37,8 +25,45 @@ config OPT_LIB_ASM
          Allows turn on optimalized library function (memcpy and memmove).
          Function are written in asm code.
-if PLATFORM_GENERIC=y
+# Definitions for MICROBLAZE0
-        source "arch/microblaze/platform/generic/Kconfig.auto"
+comment "Definitions for MICROBLAZE0"
-endif
+config KERNEL_BASE_ADDR
+        hex "Physical address where Linux Kernel is"
+        default "0x90000000"
+        help
+          BASE Address for kernel
+config XILINX_MICROBLAZE0_FAMILY
+        string "Targeted FPGA family"
+        default "virtex5"
+config XILINX_MICROBLAZE0_USE_MSR_INSTR
+        int "USE_MSR_INSTR range (0:1)"
+        default 0
+config XILINX_MICROBLAZE0_USE_PCMP_INSTR
+        int "USE_PCMP_INSTR range (0:1)"
+        default 0
+config XILINX_MICROBLAZE0_USE_BARREL
+        int "USE_BARREL range (0:1)"
+        default 0
+config XILINX_MICROBLAZE0_USE_DIV
+        int "USE_DIV range (0:1)"
+        default 0
+config XILINX_MICROBLAZE0_USE_HW_MUL
+        int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
+        default 0
+config XILINX_MICROBLAZE0_USE_FPU
+        int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)"
+        default 0
+config XILINX_MICROBLAZE0_HW_VER
+        string "Core version number"
+        default 7.10.d
 endmenu
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index a69eaf2ab130..740f2b82a182 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -48,7 +48,6 @@ head-y := arch/microblaze/kernel/head.o
 libs-y += arch/microblaze/lib/
 core-y += arch/microblaze/kernel/
 core-y += arch/microblaze/mm/
-core-y += arch/microblaze/platform/
 core-$(CONFIG_PCI) += arch/microblaze/pci/
 drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/
diff --git a/arch/microblaze/boot/dts/system.dts b/arch/microblaze/boot/dts/system.dts
index 7cb657892f21..b620da23febb 120000..100644
--- a/arch/microblaze/boot/dts/system.dts
+++ b/arch/microblaze/boot/dts/system.dts
@@ -1 +1,366 @@
-../../platform/generic/system.dts
-\ No newline at end of file
+/*
+ * Device Tree Generator version: 1.1
+ *
+ * (C) Copyright 2007-2008 Xilinx, Inc.
+ * (C) Copyright 2007-2009 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * CAUTION: This file is automatically generated by libgen.
+ * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
+ *
+ * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
+ */
+/dts-v1/;
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "xlnx,microblaze";
+        hard-reset-gpios = <&LEDs_8Bit 2 1>;
+        model = "testing";
+        DDR2_SDRAM: memory@90000000 {
+                device_type = "memory";
+                reg = < 0x90000000 0x10000000 >;
+        } ;
+        aliases {
+                ethernet0 = &Hard_Ethernet_MAC;
+                serial0 = &RS232_Uart_1;
+        } ;
+        chosen {
+                bootargs = "console=ttyUL0,115200 highres=on";
+                linux,stdout-path = "/plb@0/serial@84000000";
+        } ;
+        cpus {
+                #address-cells = <1>;
+                #cpus = <0x1>;
+                #size-cells = <0>;
+                microblaze_0: cpu@0 {
+                        clock-frequency = <125000000>;
+                        compatible = "xlnx,microblaze-7.10.d";
+                        d-cache-baseaddr = <0x90000000>;
+                        d-cache-highaddr = <0x9fffffff>;
+                        d-cache-line-size = <0x10>;
+                        d-cache-size = <0x2000>;
+                        device_type = "cpu";
+                        i-cache-baseaddr = <0x90000000>;
+                        i-cache-highaddr = <0x9fffffff>;
+                        i-cache-line-size = <0x10>;
+                        i-cache-size = <0x2000>;
+                        model = "microblaze,7.10.d";
+                        reg = <0>;
+                        timebase-frequency = <125000000>;
+                        xlnx,addr-tag-bits = <0xf>;
+                        xlnx,allow-dcache-wr = <0x1>;
+                        xlnx,allow-icache-wr = <0x1>;
+                        xlnx,area-optimized = <0x0>;
+                        xlnx,cache-byte-size = <0x2000>;
+                        xlnx,d-lmb = <0x1>;
+                        xlnx,d-opb = <0x0>;
+                        xlnx,d-plb = <0x1>;
+                        xlnx,data-size = <0x20>;
+                        xlnx,dcache-addr-tag = <0xf>;
+                        xlnx,dcache-always-used = <0x1>;
+                        xlnx,dcache-byte-size = <0x2000>;
+                        xlnx,dcache-line-len = <0x4>;
+                        xlnx,dcache-use-fsl = <0x1>;
+                        xlnx,debug-enabled = <0x1>;
+                        xlnx,div-zero-exception = <0x1>;
+                        xlnx,dopb-bus-exception = <0x0>;
+                        xlnx,dynamic-bus-sizing = <0x1>;
+                        xlnx,edge-is-positive = <0x1>;
+                        xlnx,family = "virtex5";
+                        xlnx,endianness = <0x1>;
+                        xlnx,fpu-exception = <0x1>;
+                        xlnx,fsl-data-size = <0x20>;
+                        xlnx,fsl-exception = <0x0>;
+                        xlnx,fsl-links = <0x0>;
+                        xlnx,i-lmb = <0x1>;
+                        xlnx,i-opb = <0x0>;
+                        xlnx,i-plb = <0x1>;
+                        xlnx,icache-always-used = <0x1>;
+                        xlnx,icache-line-len = <0x4>;
+                        xlnx,icache-use-fsl = <0x1>;
+                        xlnx,ill-opcode-exception = <0x1>;
+                        xlnx,instance = "microblaze_0";
+                        xlnx,interconnect = <0x1>;
+                        xlnx,interrupt-is-edge = <0x0>;
+                        xlnx,iopb-bus-exception = <0x0>;
+                        xlnx,mmu-dtlb-size = <0x4>;
+                        xlnx,mmu-itlb-size = <0x2>;
+                        xlnx,mmu-tlb-access = <0x3>;
+                        xlnx,mmu-zones = <0x10>;
+                        xlnx,number-of-pc-brk = <0x1>;
+                        xlnx,number-of-rd-addr-brk = <0x0>;
+                        xlnx,number-of-wr-addr-brk = <0x0>;
+                        xlnx,opcode-0x0-illegal = <0x1>;
+                        xlnx,pvr = <0x2>;
+                        xlnx,pvr-user1 = <0x0>;
+                        xlnx,pvr-user2 = <0x0>;
+                        xlnx,reset-msr = <0x0>;
+                        xlnx,sco = <0x0>;
+                        xlnx,unaligned-exceptions = <0x1>;
+                        xlnx,use-barrel = <0x1>;
+                        xlnx,use-dcache = <0x1>;
+                        xlnx,use-div = <0x1>;
+                        xlnx,use-ext-brk = <0x1>;
+                        xlnx,use-ext-nm-brk = <0x1>;
+                        xlnx,use-extended-fsl-instr = <0x0>;
+                        xlnx,use-fpu = <0x2>;
+                        xlnx,use-hw-mul = <0x2>;
+                        xlnx,use-icache = <0x1>;
+                        xlnx,use-interrupt = <0x1>;
+                        xlnx,use-mmu = <0x3>;
+                        xlnx,use-msr-instr = <0x1>;
+                        xlnx,use-pcmp-instr = <0x1>;
+                } ;
+        } ;
+        mb_plb: plb@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
+                ranges ;
+                FLASH: flash@a0000000 {
+                        bank-width = <2>;
+                        compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
+                        reg = < 0xa0000000 0x2000000 >;
+                        xlnx,family = "virtex5";
+                        xlnx,include-datawidth-matching-0 = <0x1>;
+                        xlnx,include-datawidth-matching-1 = <0x0>;
+                        xlnx,include-datawidth-matching-2 = <0x0>;
+                        xlnx,include-datawidth-matching-3 = <0x0>;
+                        xlnx,include-negedge-ioregs = <0x0>;
+                        xlnx,include-plb-ipif = <0x1>;
+                        xlnx,include-wrbuf = <0x1>;
+                        xlnx,max-mem-width = <0x10>;
+                        xlnx,mch-native-dwidth = <0x20>;
+                        xlnx,mch-plb-clk-period-ps = <0x1f40>;
+                        xlnx,mch-splb-awidth = <0x20>;
+                        xlnx,mch0-accessbuf-depth = <0x10>;
+                        xlnx,mch0-protocol = <0x0>;
+                        xlnx,mch0-rddatabuf-depth = <0x10>;
+                        xlnx,mch1-accessbuf-depth = <0x10>;
+                        xlnx,mch1-protocol = <0x0>;
+                        xlnx,mch1-rddatabuf-depth = <0x10>;
+                        xlnx,mch2-accessbuf-depth = <0x10>;
+                        xlnx,mch2-protocol = <0x0>;
+                        xlnx,mch2-rddatabuf-depth = <0x10>;
+                        xlnx,mch3-accessbuf-depth = <0x10>;
+                        xlnx,mch3-protocol = <0x0>;
+                        xlnx,mch3-rddatabuf-depth = <0x10>;
+                        xlnx,mem0-width = <0x10>;
+                        xlnx,mem1-width = <0x20>;
+                        xlnx,mem2-width = <0x20>;
+                        xlnx,mem3-width = <0x20>;
+                        xlnx,num-banks-mem = <0x1>;
+                        xlnx,num-channels = <0x0>;
+                        xlnx,priority-mode = <0x0>;
+                        xlnx,synch-mem-0 = <0x0>;
+                        xlnx,synch-mem-1 = <0x0>;
+                        xlnx,synch-mem-2 = <0x0>;
+                        xlnx,synch-mem-3 = <0x0>;
+                        xlnx,synch-pipedelay-0 = <0x2>;
+                        xlnx,synch-pipedelay-1 = <0x2>;
+                        xlnx,synch-pipedelay-2 = <0x2>;
+                        xlnx,synch-pipedelay-3 = <0x2>;
+                        xlnx,tavdv-ps-mem-0 = <0x1adb0>;
+                        xlnx,tavdv-ps-mem-1 = <0x3a98>;
+                        xlnx,tavdv-ps-mem-2 = <0x3a98>;
+                        xlnx,tavdv-ps-mem-3 = <0x3a98>;
+                        xlnx,tcedv-ps-mem-0 = <0x1adb0>;
+                        xlnx,tcedv-ps-mem-1 = <0x3a98>;
+                        xlnx,tcedv-ps-mem-2 = <0x3a98>;
+                        xlnx,tcedv-ps-mem-3 = <0x3a98>;
+                        xlnx,thzce-ps-mem-0 = <0x88b8>;
+                        xlnx,thzce-ps-mem-1 = <0x1b58>;
+                        xlnx,thzce-ps-mem-2 = <0x1b58>;
+                        xlnx,thzce-ps-mem-3 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-0 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-1 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-2 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-3 = <0x1b58>;
+                        xlnx,tlzwe-ps-mem-0 = <0x88b8>;
+                        xlnx,tlzwe-ps-mem-1 = <0x0>;
+                        xlnx,tlzwe-ps-mem-2 = <0x0>;
+                        xlnx,tlzwe-ps-mem-3 = <0x0>;
+                        xlnx,twc-ps-mem-0 = <0x2af8>;
+                        xlnx,twc-ps-mem-1 = <0x3a98>;
+                        xlnx,twc-ps-mem-2 = <0x3a98>;
+                        xlnx,twc-ps-mem-3 = <0x3a98>;
+                        xlnx,twp-ps-mem-0 = <0x11170>;
+                        xlnx,twp-ps-mem-1 = <0x2ee0>;
+                        xlnx,twp-ps-mem-2 = <0x2ee0>;
+                        xlnx,twp-ps-mem-3 = <0x2ee0>;
+                        xlnx,xcl0-linesize = <0x4>;
+                        xlnx,xcl0-writexfer = <0x1>;
+                        xlnx,xcl1-linesize = <0x4>;
+                        xlnx,xcl1-writexfer = <0x1>;
+                        xlnx,xcl2-linesize = <0x4>;
+                        xlnx,xcl2-writexfer = <0x1>;
+                        xlnx,xcl3-linesize = <0x4>;
+                        xlnx,xcl3-writexfer = <0x1>;
+                } ;
+                Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "xlnx,compound";
+                        ranges ;
+                        ethernet@81c00000 {
+                                compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
+                                interrupt-parent = <&xps_intc_0>;
+                                interrupts = < 5 2 >;
+                                llink-connected = <&PIM3>;
+                                local-mac-address = [ 00 0a 35 00 00 00 ];
+                                reg = < 0x81c00000 0x40 >;
+                                xlnx,bus2core-clk-ratio = <0x1>;
+                                xlnx,phy-type = <0x1>;
+                                xlnx,phyaddr = <0x1>;
+                                xlnx,rxcsum = <0x0>;
+                                xlnx,rxfifo = <0x1000>;
+                                xlnx,temac-type = <0x0>;
+                                xlnx,txcsum = <0x0>;
+                                xlnx,txfifo = <0x1000>;
+                        } ;
+                } ;
+                IIC_EEPROM: i2c@81600000 {
+                        compatible = "xlnx,xps-iic-2.00.a";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 6 2 >;
+                        reg = < 0x81600000 0x10000 >;
+                        xlnx,clk-freq = <0x7735940>;
+                        xlnx,family = "virtex5";
+                        xlnx,gpo-width = <0x1>;
+                        xlnx,iic-freq = <0x186a0>;
+                        xlnx,scl-inertial-delay = <0x0>;
+                        xlnx,sda-inertial-delay = <0x0>;
+                        xlnx,ten-bit-adr = <0x0>;
+                } ;
+                LEDs_8Bit: gpio@81400000 {
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 7 2 >;
+                        reg = < 0x81400000 0x10000 >;
+                        xlnx,all-inputs = <0x0>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,dout-default = <0x0>;
+                        xlnx,dout-default-2 = <0x0>;
+                        xlnx,family = "virtex5";
+                        xlnx,gpio-width = <0x8>;
+                        xlnx,interrupt-present = <0x1>;
+                        xlnx,is-bidir = <0x1>;
+                        xlnx,is-bidir-2 = <0x1>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xffffffff>;
+                        xlnx,tri-default-2 = <0xffffffff>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                } ;
+                gpio-leds {
+                        compatible = "gpio-leds";
+                        heartbeat {
+                                label = "Heartbeat";
+                                gpios = <&LEDs_8Bit 4 1>;
+                                linux,default-trigger = "heartbeat";
+                        };
+                        yellow {
+                                label = "Yellow";
+                                gpios = <&LEDs_8Bit 5 1>;
+                        };
+                        red {
+                                label = "Red";
+                                gpios = <&LEDs_8Bit 6 1>;
+                        };
+                        green {
+                                label = "Green";
+                                gpios = <&LEDs_8Bit 7 1>;
+                        };
+                } ;
+                RS232_Uart_1: serial@84000000 {
+                        clock-frequency = <125000000>;
+                        compatible = "xlnx,xps-uartlite-1.00.a";
+                        current-speed = <115200>;
+                        device_type = "serial";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 8 0 >;
+                        port-number = <0>;
+                        reg = < 0x84000000 0x10000 >;
+                        xlnx,baudrate = <0x1c200>;
+                        xlnx,data-bits = <0x8>;
+                        xlnx,family = "virtex5";
+                        xlnx,odd-parity = <0x0>;
+                        xlnx,use-parity = <0x0>;
+                } ;
+                SysACE_CompactFlash: sysace@83600000 {
+                        compatible = "xlnx,xps-sysace-1.00.a";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 4 2 >;
+                        reg = < 0x83600000 0x10000 >;
+                        xlnx,family = "virtex5";
+                        xlnx,mem-width = <0x10>;
+                } ;
+                debug_module: debug@84400000 {
+                        compatible = "xlnx,mdm-1.00.d";
+                        reg = < 0x84400000 0x10000 >;
+                        xlnx,family = "virtex5";
+                        xlnx,interconnect = <0x1>;
+                        xlnx,jtag-chain = <0x2>;
+                        xlnx,mb-dbg-ports = <0x1>;
+                        xlnx,uart-width = <0x8>;
+                        xlnx,use-uart = <0x1>;
+                        xlnx,write-fsl-ports = <0x0>;
+                } ;
+                mpmc@90000000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "xlnx,mpmc-4.02.a";
+                        ranges ;
+                        PIM3: sdma@84600180 {
+                                compatible = "xlnx,ll-dma-1.00.a";
+                                interrupt-parent = <&xps_intc_0>;
+                                interrupts = < 2 2 1 2 >;
+                                reg = < 0x84600180 0x80 >;
+                        } ;
+                } ;
+                xps_intc_0: interrupt-controller@81800000 {
+                        #interrupt-cells = <0x2>;
+                        compatible = "xlnx,xps-intc-1.00.a";
+                        interrupt-controller ;
+                        reg = < 0x81800000 0x10000 >;
+                        xlnx,kind-of-intr = <0x100>;
+                        xlnx,num-intr-inputs = <0x9>;
+                } ;
+                xps_timer_1: timer@83c00000 {
+                        compatible = "xlnx,xps-timer-1.00.a";
+                        interrupt-parent = <&xps_intc_0>;
+                        interrupts = < 3 2 >;
+                        reg = < 0x83c00000 0x10000 >;
+                        xlnx,count-width = <0x20>;
+                        xlnx,family = "virtex5";
+                        xlnx,gen0-assert = <0x1>;
+                        xlnx,gen1-assert = <0x1>;
+                        xlnx,one-timer-only = <0x0>;
+                        xlnx,trig0-assert = <0x1>;
+                        xlnx,trig1-assert = <0x1>;
+                } ;
+        } ;
+}  ;
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 3fbb7f1db3bc..1e4c3329f62e 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -15,7 +15,6 @@
 #include <asm/page.h>
 #include <linux/types.h>
 #include <linux/mm.h>          /* Get struct page {...} */
-#include <asm-generic/iomap.h>
 #ifndef CONFIG_PCI
 #define _IO_BASE        0
@@ -25,211 +24,32 @@
 #define _IO_BASE        isa_io_base
 #define _ISA_MEM_BASE   isa_mem_base
 #define PCI_DRAM_OFFSET pci_dram_offset
-#endif
+struct pci_dev;
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+#define pci_iounmap pci_iounmap
 extern unsigned long isa_io_base;
-extern unsigned long pci_io_base;
 extern unsigned long pci_dram_offset;
 extern resource_size_t isa_mem_base;
+#endif
+#define PCI_IOBASE      ((void __iomem *)_IO_BASE)
 #define IO_SPACE_LIMIT (0xFFFFFFFF)
-/* the following is needed to support PCI with some drivers */
-#define mmiowb()
-static inline unsigned char __raw_readb(const volatile void __iomem *addr)
-{
-        return *(volatile unsigned char __force *)addr;
-}
-static inline unsigned short __raw_readw(const volatile void __iomem *addr)
-{
-        return *(volatile unsigned short __force *)addr;
-}
-static inline unsigned int __raw_readl(const volatile void __iomem *addr)
-{
-        return *(volatile unsigned int __force *)addr;
-}
-static inline unsigned long __raw_readq(const volatile void __iomem *addr)
-{
-        return *(volatile unsigned long __force *)addr;
-}
-static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
-{
-        *(volatile unsigned char __force *)addr = v;
-}
-static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
-{
-        *(volatile unsigned short __force *)addr = v;
-}
-static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
-{
-        *(volatile unsigned int __force *)addr = v;
-}
-static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
-{
-        *(volatile unsigned long __force *)addr = v;
-}
-/*
- * read (readb, readw, readl, readq) and write (writeb, writew,
- * writel, writeq) accessors are for PCI and thus little endian.
- * Linux 2.4 for Microblaze had this wrong.
- */
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
-        return *(volatile unsigned char __force *)addr;
-}
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
-        return le16_to_cpu(*(volatile unsigned short __force *)addr);
-}
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
-        return le32_to_cpu(*(volatile unsigned int __force *)addr);
-}
-#define readq readq
-static inline u64 readq(const volatile void __iomem *addr)
-{
-        return le64_to_cpu(__raw_readq(addr));
-}
-static inline void writeb(unsigned char v, volatile void __iomem *addr)
-{
-        *(volatile unsigned char __force *)addr = v;
-}
-static inline void writew(unsigned short v, volatile void __iomem *addr)
-{
-        *(volatile unsigned short __force *)addr = cpu_to_le16(v);
-}
-static inline void writel(unsigned int v, volatile void __iomem *addr)
-{
-        *(volatile unsigned int __force *)addr = cpu_to_le32(v);
-}
-#define writeq(b, addr) __raw_writeq(cpu_to_le64(b), addr)
-/* ioread and iowrite variants. thease are for now same as __raw_
- * variants of accessors. we might check for endianess in the feature
- */
-#define ioread8(addr)           __raw_readb((u8 *)(addr))
-#define ioread16(addr)          __raw_readw((u16 *)(addr))
-#define ioread32(addr)          __raw_readl((u32 *)(addr))
-#define iowrite8(v, addr)       __raw_writeb((u8)(v), (u8 *)(addr))
-#define iowrite16(v, addr)      __raw_writew((u16)(v), (u16 *)(addr))
-#define iowrite32(v, addr)      __raw_writel((u32)(v), (u32 *)(addr))
-#define ioread16be(addr)        __raw_readw((u16 *)(addr))
-#define ioread32be(addr)        __raw_readl((u32 *)(addr))
-#define iowrite16be(v, addr)    __raw_writew((u16)(v), (u16 *)(addr))
-#define iowrite32be(v, addr)    __raw_writel((u32)(v), (u32 *)(addr))
-/* These are the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl, the "string" versions
- * insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
- * inb_p/inw_p/...
- * The macros don't do byte-swapping.
- */
-#define inb(port)               readb((u8 *)((unsigned long)(port)))
-#define outb(val, port)         writeb((val), (u8 *)((unsigned long)(port)))
-#define inw(port)               readw((u16 *)((unsigned long)(port)))
-#define outw(val, port)         writew((val), (u16 *)((unsigned long)(port)))
-#define inl(port)               readl((u32 *)((unsigned long)(port)))
-#define outl(val, port)         writel((val), (u32 *)((unsigned long)(port)))
-#define inb_p(port)             inb((port))
-#define outb_p(val, port)       outb((val), (port))
-#define inw_p(port)             inw((port))
-#define outw_p(val, port)       outw((val), (port))
-#define inl_p(port)             inl((port))
-#define outl_p(val, port)       outl((val), (port))
-#define memset_io(a, b, c)      memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c)  memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c)    memcpy((void *)(a), (b), (c))
 #ifdef CONFIG_MMU
-#define phys_to_virt(addr)      ((void *)__phys_to_virt(addr))
-#define virt_to_phys(addr)      ((unsigned long)__virt_to_phys(addr))
-#define virt_to_bus(addr)       ((unsigned long)__virt_to_phys(addr))
 #define page_to_bus(page)       (page_to_phys(page))
-#define bus_to_virt(addr)       (phys_to_virt(addr))
 extern void iounmap(void __iomem *addr);
-/*extern void *__ioremap(phys_addr_t address, unsigned long size,
-                unsigned long flags);*/
-extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
-#define ioremap_writethrough(addr, size) ioremap((addr), (size))
-#define ioremap_nocache(addr, size)      ioremap((addr), (size))
-#define ioremap_fullcache(addr, size)    ioremap((addr), (size))
-#else /* CONFIG_MMU */
-/**
- *      virt_to_phys - map virtual addresses to physical
- *      @address: address to remap
- *
- *      The returned physical address is the physical (CPU) mapping for
- *      the memory address given. It is only valid to use this function on
- *      addresses directly mapped or allocated via kmalloc.
- *
- *      This function does not give bus mappings for DMA transfers. In
- *      almost all conceivable cases a device driver should not be using
- *      this function
- */
-static inline unsigned long __iomem virt_to_phys(volatile void *address)
-{
-        return __pa((unsigned long)address);
-}
-#define virt_to_bus virt_to_phys
-/**
- *      phys_to_virt - map physical address to virtual
- *      @address: address to remap
- *
- *      The returned virtual address is a current CPU mapping for
- *      the memory address given. It is only valid to use this function on
- *      addresses that have a kernel mapping
- *
- *      This function does not handle bus mappings for DMA transfers. In
- *      almost all conceivable cases a device driver should not be using
- *      this function
- */
-static inline void *phys_to_virt(unsigned long address)
-{
-        return (void *)__va(address);
-}
-#define bus_to_virt(a) phys_to_virt(a)
+extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
+#define ioremap_writethrough(addr, size)        ioremap((addr), (size))
-static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
+#define ioremap_nocache(addr, size)             ioremap((addr), (size))
-                        unsigned long flags)
+#define ioremap_fullcache(addr, size)           ioremap((addr), (size))
-{
+#define ioremap_wc(addr, size)                  ioremap((addr), (size))
-        return (void *)address;
-}
-#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
-#define iounmap(addr)           ((void)0)
-#define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
 #endif /* CONFIG_MMU */
-/*
+/* Big Endian */
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-/*
- * Big Endian
- */
 #define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a))
 #define out_be16(a, v) __raw_writew((v), (a))
@@ -239,10 +59,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
 #define writel_be(v, a) out_be32((__force unsigned *)a, v)
 #define readl_be(a)     in_be32((__force unsigned *)a)
-/*
+/* Little endian */
- * Little endian
- */
 #define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a))
 #define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a))
@@ -253,100 +70,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
 #define out_8(a, v) __raw_writeb((v), (a))
 #define in_8(a) __raw_readb(a)
-#define mmiowb()
+#include <asm-generic/io.h>
-#define ioport_map(port, nr)    ((void __iomem *)(port))
-#define ioport_unmap(addr)
-/* from asm-generic/io.h */
-#ifndef insb
-static inline void insb(unsigned long addr, void *buffer, int count)
-{
-        if (count) {
-                u8 *buf = buffer;
-                do {
-                        u8 x = inb(addr);
-                        *buf++ = x;
-                } while (--count);
-        }
-}
-#endif
-#ifndef insw
-static inline void insw(unsigned long addr, void *buffer, int count)
-{
-        if (count) {
-                u16 *buf = buffer;
-                do {
-                        u16 x = inw(addr);
-                        *buf++ = x;
-                } while (--count);
-        }
-}
-#endif
-#ifndef insl
-static inline void insl(unsigned long addr, void *buffer, int count)
-{
-        if (count) {
-                u32 *buf = buffer;
-                do {
-                        u32 x = inl(addr);
-                        *buf++ = x;
-                } while (--count);
-        }
-}
-#endif
-#ifndef outsb
-static inline void outsb(unsigned long addr, const void *buffer, int count)
-{
-        if (count) {
-                const u8 *buf = buffer;
-                do {
-                        outb(*buf++, addr);
-                } while (--count);
-        }
-}
-#endif
-#ifndef outsw
-static inline void outsw(unsigned long addr, const void *buffer, int count)
-{
-        if (count) {
-                const u16 *buf = buffer;
-                do {
-                        outw(*buf++, addr);
-                } while (--count);
-        }
-}
-#endif
-#ifndef outsl
-static inline void outsl(unsigned long addr, const void *buffer, int count)
-{
-        if (count) {
-                const u32 *buf = buffer;
-                do {
-                        outl(*buf++, addr);
-                } while (--count);
-        }
-}
-#endif
-#define ioread8_rep(p, dst, count) \
-        insb((unsigned long) (p), (dst), (count))
-#define ioread16_rep(p, dst, count) \
-        insw((unsigned long) (p), (dst), (count))
-#define ioread32_rep(p, dst, count) \
-        insl((unsigned long) (p), (dst), (count))
-#define iowrite8_rep(p, src, count) \
-        outsb((unsigned long) (p), (src), (count))
-#define iowrite16_rep(p, src, count) \
-        outsw((unsigned long) (p), (src), (count))
-#define iowrite32_rep(p, src, count) \
-        outsl((unsigned long) (p), (src), (count))
 #define readb_relaxed   readb
 #define readw_relaxed   readw
diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h
index d6e0ffea28b6..9d31b057c355 100644
--- a/arch/microblaze/include/asm/processor.h
+++ b/arch/microblaze/include/asm/processor.h
@@ -122,7 +122,7 @@ struct thread_struct {
 }
 /* Free all resources held by a thread. */
-extern inline void release_thread(struct task_struct *dead_task)
+static inline void release_thread(struct task_struct *dead_task)
 {
 }
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index f05df5630c84..be84a4d3917f 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -19,14 +19,12 @@ extern char cmd_line[COMMAND_LINE_SIZE];
 extern char *klimit;
-void early_printk(const char *fmt, ...);
 int setup_early_printk(char *opt);
 void remap_early_printk(void);
 void disable_early_printk(void);
-void heartbeat(void);
+void microblaze_heartbeat(void);
-void setup_heartbeat(void);
+void microblaze_setup_heartbeat(void);
 #   ifdef CONFIG_MMU
 extern void mmu_reset(void);
diff --git a/arch/microblaze/include/uapi/asm/unistd.h b/arch/microblaze/include/uapi/asm/unistd.h
index 20043b67d158..8d0791b49b31 100644
--- a/arch/microblaze/include/uapi/asm/unistd.h
+++ b/arch/microblaze/include/uapi/asm/unistd.h
@@ -93,7 +93,7 @@
 #define __NR_settimeofday       79 /* ok */
 #define __NR_getgroups          80 /* ok */
 #define __NR_setgroups          81 /* ok */
-#define __NR_select             82 /* obsolete -> sys_pselect7 */
+#define __NR_select             82 /* obsolete -> sys_pselect6 */
 #define __NR_symlink            83 /* symlinkat */
 #define __NR_oldlstat           84 /* remove */
 #define __NR_readlink           85 /* obsolete -> sys_readlinkat */
@@ -320,7 +320,7 @@
 #define __NR_readlinkat         305 /* ok */
 #define __NR_fchmodat           306 /* ok */
 #define __NR_faccessat          307 /* ok */
-#define __NR_pselect6           308 /* obsolete -> sys_pselect7 */
+#define __NR_pselect6           308 /* ok */
 #define __NR_ppoll              309 /* ok */
 #define __NR_unshare            310 /* ok */
 #define __NR_set_robust_list    311 /* ok */
@@ -396,5 +396,7 @@
 #define __NR_process_vm_writev  378
 #define __NR_kcmp               379
 #define __NR_finit_module       380
+#define __NR_sched_setattr      381
+#define __NR_sched_getattr      382
 #endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index 5b0e512c78e5..08d50cc55e7d 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -16,7 +16,7 @@ extra-y := head.o vmlinux.lds
 obj-y += dma.o exceptions.o \
        hw_exception_handler.o intc.o irq.o \
-        process.o prom.o prom_parse.o ptrace.o \
+        platform.o process.o prom.o prom_parse.o ptrace.o \
        reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
 obj-y += cpu/
diff --git a/arch/microblaze/kernel/ftrace.c b/arch/microblaze/kernel/ftrace.c
index e8a5e9cf4ed1..bbcd2533766c 100644
--- a/arch/microblaze/kernel/ftrace.c
+++ b/arch/microblaze/kernel/ftrace.c
@@ -171,11 +171,8 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
        return ret;
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        /* The return code is retured via data */
-        *(unsigned long *)data = 0;
        return 0;
 }
diff --git a/arch/microblaze/kernel/heartbeat.c b/arch/microblaze/kernel/heartbeat.c
index 1879a0527776..4643e3ab9414 100644
--- a/arch/microblaze/kernel/heartbeat.c
+++ b/arch/microblaze/kernel/heartbeat.c
@@ -17,7 +17,7 @@
 static unsigned int base_addr;
-void heartbeat(void)
+void microblaze_heartbeat(void)
 {
        static unsigned int cnt, period, dist;
@@ -42,7 +42,7 @@ void heartbeat(void)
        }
 }
-void setup_heartbeat(void)
+void microblaze_setup_heartbeat(void)
 {
        struct device_node *gpio = NULL;
        int *prop;
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
index 581451ad4687..15c7c12ea0e7 100644
--- a/arch/microblaze/kernel/intc.c
+++ b/arch/microblaze/kernel/intc.c
@@ -32,6 +32,29 @@ static void __iomem *intc_baseaddr;
 #define MER_ME (1<<0)
 #define MER_HIE (1<<1)
+static unsigned int (*read_fn)(void __iomem *);
+static void (*write_fn)(u32, void __iomem *);
+static void intc_write32(u32 val, void __iomem *addr)
+{
+        iowrite32(val, addr);
+}
+static unsigned int intc_read32(void __iomem *addr)
+{
+        return ioread32(addr);
+}
+static void intc_write32_be(u32 val, void __iomem *addr)
+{
+        iowrite32be(val, addr);
+}
+static unsigned int intc_read32_be(void __iomem *addr)
+{
+        return ioread32be(addr);
+}
 static void intc_enable_or_unmask(struct irq_data *d)
 {
        unsigned long mask = 1 << d->hwirq;
@@ -43,21 +66,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
         * acks the irq before calling the interrupt handler
         */
        if (irqd_is_level_type(d))
-                out_be32(intc_baseaddr + IAR, mask);
+                write_fn(mask, intc_baseaddr + IAR);
-        out_be32(intc_baseaddr + SIE, mask);
+        write_fn(mask, intc_baseaddr + SIE);
 }
 static void intc_disable_or_mask(struct irq_data *d)
 {
        pr_debug("disable: %ld\n", d->hwirq);
-        out_be32(intc_baseaddr + CIE, 1 << d->hwirq);
+        write_fn(1 << d->hwirq, intc_baseaddr + CIE);
 }
 static void intc_ack(struct irq_data *d)
 {
        pr_debug("ack: %ld\n", d->hwirq);
-        out_be32(intc_baseaddr + IAR, 1 << d->hwirq);
+        write_fn(1 << d->hwirq, intc_baseaddr + IAR);
 }
 static void intc_mask_ack(struct irq_data *d)
@@ -65,8 +88,8 @@ static void intc_mask_ack(struct irq_data *d)
        unsigned long mask = 1 << d->hwirq;
        pr_debug("disable_and_ack: %ld\n", d->hwirq);
-        out_be32(intc_baseaddr + CIE, mask);
+        write_fn(mask, intc_baseaddr + CIE);
-        out_be32(intc_baseaddr + IAR, mask);
+        write_fn(mask, intc_baseaddr + IAR);
 }
 static struct irq_chip intc_dev = {
@@ -83,7 +106,7 @@ unsigned int get_irq(void)
 {
        unsigned int hwirq, irq = -1;
-        hwirq = in_be32(intc_baseaddr + IVR);
+        hwirq = read_fn(intc_baseaddr + IVR);
        if (hwirq != -1U)
                irq = irq_find_mapping(root_domain, hwirq);
@@ -140,17 +163,25 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
        pr_info("%s: num_irq=%d, edge=0x%x\n",
                intc->full_name, nr_irq, intr_mask);
+        write_fn = intc_write32;
+        read_fn = intc_read32;
        /*
         * Disable all external interrupts until they are
         * explicity requested.
         */
-        out_be32(intc_baseaddr + IER, 0);
+        write_fn(0, intc_baseaddr + IER);
        /* Acknowledge any pending interrupts just in case. */
-        out_be32(intc_baseaddr + IAR, 0xffffffff);
+        write_fn(0xffffffff, intc_baseaddr + IAR);
        /* Turn on the Master Enable. */
-        out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
+        write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
+        if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
+                write_fn = intc_write32_be;
+                read_fn = intc_read32_be;
+                write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
+        }
        /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
         * lazy and Michal can clean it up to something nicer when he tests
diff --git a/arch/microblaze/platform/platform.c b/arch/microblaze/kernel/platform.c
index b9529caa507a..b9529caa507a 100644
--- a/arch/microblaze/platform/platform.c
+++ b/arch/microblaze/kernel/platform.c
diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c
index 7d1a9c8b1f3d..b2dd37196b3b 100644
--- a/arch/microblaze/kernel/process.c
+++ b/arch/microblaze/kernel/process.c
@@ -8,6 +8,7 @@
 * for more details.
 */
+#include <linux/cpu.h>
 #include <linux/export.h>
 #include <linux/sched.h>
 #include <linux/pm.h>
diff --git a/arch/microblaze/kernel/signal.c b/arch/microblaze/kernel/signal.c
index d26d7e7a6913..49a07a4d76d0 100644
--- a/arch/microblaze/kernel/signal.c
+++ b/arch/microblaze/kernel/signal.c
@@ -216,7 +216,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                /* MS: I need add offset in page */
                address += ((unsigned long)frame->tramp) & ~PAGE_MASK;
                /* MS address is virtual */
-                address = virt_to_phys(address);
+                address = __virt_to_phys(address);
                invalidate_icache_range(address, address + 8);
                flush_dcache_range(address, address + 8);
        }
diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S
index b882ad50535b..329dfbad810b 100644
--- a/arch/microblaze/kernel/syscall_table.S
+++ b/arch/microblaze/kernel/syscall_table.S
@@ -308,7 +308,7 @@ ENTRY(sys_call_table)
        .long sys_readlinkat            /* 305 */
        .long sys_fchmodat
        .long sys_faccessat
-        .long sys_ni_syscall /* pselect6 */
+        .long sys_pselect6
        .long sys_ppoll
        .long sys_unshare               /* 310 */
        .long sys_set_robust_list
@@ -363,8 +363,8 @@ ENTRY(sys_call_table)
        .long sys_sendmsg               /* 360 */
        .long sys_recvmsg
        .long sys_accept4
-        .long sys_ni_syscall
+        .long sys_preadv
-        .long sys_ni_syscall
+        .long sys_pwritev
        .long sys_rt_tgsigqueueinfo     /* 365 */
        .long sys_perf_event_open
        .long sys_recvmmsg
@@ -381,3 +381,5 @@ ENTRY(sys_call_table)
        .long sys_process_vm_writev
        .long sys_kcmp
        .long sys_finit_module
+        .long sys_sched_setattr
+        .long sys_sched_getattr
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index fb0c61443f19..dd96f0e4bfa2 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -43,10 +43,33 @@ static unsigned int timer_clock_freq;
 #define TCSR_PWMA       (1<<9)
 #define TCSR_ENALL      (1<<10)
+static unsigned int (*read_fn)(void __iomem *);
+static void (*write_fn)(u32, void __iomem *);
+static void timer_write32(u32 val, void __iomem *addr)
+{
+        iowrite32(val, addr);
+}
+static unsigned int timer_read32(void __iomem *addr)
+{
+        return ioread32(addr);
+}
+static void timer_write32_be(u32 val, void __iomem *addr)
+{
+        iowrite32be(val, addr);
+}
+static unsigned int timer_read32_be(void __iomem *addr)
+{
+        return ioread32be(addr);
+}
 static inline void xilinx_timer0_stop(void)
 {
-        out_be32(timer_baseaddr + TCSR0,
+        write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
-                 in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT);
+                 timer_baseaddr + TCSR0);
 }
 static inline void xilinx_timer0_start_periodic(unsigned long load_val)
@@ -54,10 +77,10 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
        if (!load_val)
                load_val = 1;
        /* loading value to timer reg */
-        out_be32(timer_baseaddr + TLR0, load_val);
+        write_fn(load_val, timer_baseaddr + TLR0);
        /* load the initial value */
-        out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
+        write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
        /* see timer data sheet for detail
         * !ENALL - don't enable 'em all
@@ -72,8 +95,8 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
         * UDT - set the timer as down counter
         * !MDT0 - generate mode
         */
-        out_be32(timer_baseaddr + TCSR0,
+        write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
-                        TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
+                 timer_baseaddr + TCSR0);
 }
 static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
@@ -81,13 +104,13 @@ static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
        if (!load_val)
                load_val = 1;
        /* loading value to timer reg */
-        out_be32(timer_baseaddr + TLR0, load_val);
+        write_fn(load_val, timer_baseaddr + TLR0);
        /* load the initial value */
-        out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
+        write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
-        out_be32(timer_baseaddr + TCSR0,
+        write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
-                        TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
+                 timer_baseaddr + TCSR0);
 }
 static int xilinx_timer_set_next_event(unsigned long delta,
@@ -133,14 +156,14 @@ static struct clock_event_device clockevent_xilinx_timer = {
 static inline void timer_ack(void)
 {
-        out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0));
+        write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
 }
 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 {
        struct clock_event_device *evt = &clockevent_xilinx_timer;
 #ifdef CONFIG_HEART_BEAT
-        heartbeat();
+        microblaze_heartbeat();
 #endif
        timer_ack();
        evt->event_handler(evt);
@@ -169,7 +192,7 @@ static __init void xilinx_clockevent_init(void)
 static u64 xilinx_clock_read(void)
 {
-        return in_be32(timer_baseaddr + TCR1);
+        return read_fn(timer_baseaddr + TCR1);
 }
 static cycle_t xilinx_read(struct clocksource *cs)
@@ -217,10 +240,10 @@ static int __init xilinx_clocksource_init(void)
                panic("failed to register clocksource");
        /* stop timer1 */
-        out_be32(timer_baseaddr + TCSR1,
+        write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
-                 in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT);
+                 timer_baseaddr + TCSR1);
        /* start timer1 - up counting without interrupt */
-        out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
+        write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
        /* register timecounter - for ftrace support */
        init_xilinx_timecounter();
@@ -245,6 +268,15 @@ static void __init xilinx_timer_init(struct device_node *timer)
                BUG();
        }
+        write_fn = timer_write32;
+        read_fn = timer_read32;
+        write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
+        if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
+                write_fn = timer_write32_be;
+                read_fn = timer_read32_be;
+        }
        irq = irq_of_parse_and_map(timer, 0);
        of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
@@ -274,7 +306,7 @@ static void __init xilinx_timer_init(struct device_node *timer)
        setup_irq(irq, &timer_irqaction);
 #ifdef CONFIG_HEART_BEAT
-        setup_heartbeat();
+        microblaze_setup_heartbeat();
 #endif
        xilinx_clocksource_init();
        xilinx_clockevent_init();
diff --git a/arch/microblaze/mm/consistent.c b/arch/microblaze/mm/consistent.c
index dbbf2246a260..e10ad930895e 100644
--- a/arch/microblaze/mm/consistent.c
+++ b/arch/microblaze/mm/consistent.c
@@ -117,7 +117,7 @@ void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle)
        ret = (void *)va;
        /* This gives us the real physical address of the first page. */
-        *dma_handle = pa = virt_to_bus((void *)vaddr);
+        *dma_handle = pa = __virt_to_phys(vaddr);
 #endif
        /*
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index 89077d346714..77bc7c7e6522 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -369,7 +369,7 @@ asmlinkage void __init mmu_init(void)
        if (initrd_start) {
                unsigned long size;
                size = initrd_end - initrd_start;
-                memblock_reserve(virt_to_phys(initrd_start), size);
+                memblock_reserve(__virt_to_phys(initrd_start), size);
        }
 #endif /* CONFIG_BLK_DEV_INITRD */
diff --git a/arch/microblaze/mm/pgtable.c b/arch/microblaze/mm/pgtable.c
index 10b3bd0a980d..4f4520e779a5 100644
--- a/arch/microblaze/mm/pgtable.c
+++ b/arch/microblaze/mm/pgtable.c
@@ -69,10 +69,11 @@ static void __iomem *__ioremap(phys_addr_t addr, unsigned long size,
         *
         * However, allow remap of rootfs: TBD
         */
        if (mem_init_done &&
                p >= memory_start && p < virt_to_phys(high_memory) &&
-                !(p >= virt_to_phys((unsigned long)&__bss_stop) &&
+                !(p >= __virt_to_phys((phys_addr_t)__bss_stop) &&
-                p < virt_to_phys((unsigned long)__bss_stop))) {
+                p < __virt_to_phys((phys_addr_t)__bss_stop))) {
                pr_warn("__ioremap(): phys addr "PTE_FMT" is RAM lr %pf\n",
                        (unsigned long)p, __builtin_return_address(0));
                return NULL;
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 66804adcacf0..70996cc66aa2 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -1294,11 +1294,6 @@ void pcibios_finish_adding_to_bus(struct pci_bus *bus)
 }
 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
-        return pci_enable_resources(dev, mask);
-}
 static void pcibios_setup_phb_resources(struct pci_controller *hose,
                                        struct list_head *resources)
 {
diff --git a/arch/microblaze/platform/Makefile b/arch/microblaze/platform/Makefile
deleted file mode 100644
index ea1b75cc5775..000000000000
--- a/arch/microblaze/platform/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for arch/microblaze/platform directory
-#
-#obj-$(CONFIG_PLATFORM_GENERIC) += generic/
-obj-y   += platform.o
diff --git a/arch/microblaze/platform/generic/Kconfig.auto b/arch/microblaze/platform/generic/Kconfig.auto
deleted file mode 100644
index 25a6f019e94d..000000000000
--- a/arch/microblaze/platform/generic/Kconfig.auto
+++ /dev/null
@@ -1,61 +0,0 @@
-#
-# (C) Copyright 2007 Michal Simek
-#
-# Michal SIMEK <monstr@monstr.eu>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Definitions for MICROBLAZE0
-comment "Definitions for MICROBLAZE0"
-config KERNEL_BASE_ADDR
-        hex "Physical address where Linux Kernel is"
-        default "0x90000000"
-        help
-          BASE Address for kernel
-config XILINX_MICROBLAZE0_FAMILY
-        string "Targeted FPGA family"
-        default "virtex5"
-config XILINX_MICROBLAZE0_USE_MSR_INSTR
-        int "USE_MSR_INSTR range (0:1)"
-        default 0
-config XILINX_MICROBLAZE0_USE_PCMP_INSTR
-        int "USE_PCMP_INSTR range (0:1)"
-        default 0
-config XILINX_MICROBLAZE0_USE_BARREL
-        int "USE_BARREL range (0:1)"
-        default 0
-config XILINX_MICROBLAZE0_USE_DIV
-        int "USE_DIV range (0:1)"
-        default 0
-config XILINX_MICROBLAZE0_USE_HW_MUL
-        int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
-        default 0
-config XILINX_MICROBLAZE0_USE_FPU
-        int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)"
-        default 0
-config XILINX_MICROBLAZE0_HW_VER
-        string "Core version number"
-        default 7.10.d
diff --git a/arch/microblaze/platform/generic/Makefile b/arch/microblaze/platform/generic/Makefile
deleted file mode 100644
index 9a8b1bd3fa6d..000000000000
--- a/arch/microblaze/platform/generic/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-#
-# Empty Makefile to keep make clean happy
-#
diff --git a/arch/microblaze/platform/generic/system.dts b/arch/microblaze/platform/generic/system.dts
deleted file mode 100644
index b620da23febb..000000000000
--- a/arch/microblaze/platform/generic/system.dts
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Device Tree Generator version: 1.1
- *
- * (C) Copyright 2007-2008 Xilinx, Inc.
- * (C) Copyright 2007-2009 Michal Simek
- *
- * Michal SIMEK <monstr@monstr.eu>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
- *
- * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
- */
-/dts-v1/;
-/ {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        compatible = "xlnx,microblaze";
-        hard-reset-gpios = <&LEDs_8Bit 2 1>;
-        model = "testing";
-        DDR2_SDRAM: memory@90000000 {
-                device_type = "memory";
-                reg = < 0x90000000 0x10000000 >;
-        } ;
-        aliases {
-                ethernet0 = &Hard_Ethernet_MAC;
-                serial0 = &RS232_Uart_1;
-        } ;
-        chosen {
-                bootargs = "console=ttyUL0,115200 highres=on";
-                linux,stdout-path = "/plb@0/serial@84000000";
-        } ;
-        cpus {
-                #address-cells = <1>;
-                #cpus = <0x1>;
-                #size-cells = <0>;
-                microblaze_0: cpu@0 {
-                        clock-frequency = <125000000>;
-                        compatible = "xlnx,microblaze-7.10.d";
-                        d-cache-baseaddr = <0x90000000>;
-                        d-cache-highaddr = <0x9fffffff>;
-                        d-cache-line-size = <0x10>;
-                        d-cache-size = <0x2000>;
-                        device_type = "cpu";
-                        i-cache-baseaddr = <0x90000000>;
-                        i-cache-highaddr = <0x9fffffff>;
-                        i-cache-line-size = <0x10>;
-                        i-cache-size = <0x2000>;
-                        model = "microblaze,7.10.d";
-                        reg = <0>;
-                        timebase-frequency = <125000000>;
-                        xlnx,addr-tag-bits = <0xf>;
-                        xlnx,allow-dcache-wr = <0x1>;
-                        xlnx,allow-icache-wr = <0x1>;
-                        xlnx,area-optimized = <0x0>;
-                        xlnx,cache-byte-size = <0x2000>;
-                        xlnx,d-lmb = <0x1>;
-                        xlnx,d-opb = <0x0>;
-                        xlnx,d-plb = <0x1>;
-                        xlnx,data-size = <0x20>;
-                        xlnx,dcache-addr-tag = <0xf>;
-                        xlnx,dcache-always-used = <0x1>;
-                        xlnx,dcache-byte-size = <0x2000>;
-                        xlnx,dcache-line-len = <0x4>;
-                        xlnx,dcache-use-fsl = <0x1>;
-                        xlnx,debug-enabled = <0x1>;
-                        xlnx,div-zero-exception = <0x1>;
-                        xlnx,dopb-bus-exception = <0x0>;
-                        xlnx,dynamic-bus-sizing = <0x1>;
-                        xlnx,edge-is-positive = <0x1>;
-                        xlnx,family = "virtex5";
-                        xlnx,endianness = <0x1>;
-                        xlnx,fpu-exception = <0x1>;
-                        xlnx,fsl-data-size = <0x20>;
-                        xlnx,fsl-exception = <0x0>;
-                        xlnx,fsl-links = <0x0>;
-                        xlnx,i-lmb = <0x1>;
-                        xlnx,i-opb = <0x0>;
-                        xlnx,i-plb = <0x1>;
-                        xlnx,icache-always-used = <0x1>;
-                        xlnx,icache-line-len = <0x4>;
-                        xlnx,icache-use-fsl = <0x1>;
-                        xlnx,ill-opcode-exception = <0x1>;
-                        xlnx,instance = "microblaze_0";
-                        xlnx,interconnect = <0x1>;
-                        xlnx,interrupt-is-edge = <0x0>;
-                        xlnx,iopb-bus-exception = <0x0>;
-                        xlnx,mmu-dtlb-size = <0x4>;
-                        xlnx,mmu-itlb-size = <0x2>;
-                        xlnx,mmu-tlb-access = <0x3>;
-                        xlnx,mmu-zones = <0x10>;
-                        xlnx,number-of-pc-brk = <0x1>;
-                        xlnx,number-of-rd-addr-brk = <0x0>;
-                        xlnx,number-of-wr-addr-brk = <0x0>;
-                        xlnx,opcode-0x0-illegal = <0x1>;
-                        xlnx,pvr = <0x2>;
-                        xlnx,pvr-user1 = <0x0>;
-                        xlnx,pvr-user2 = <0x0>;
-                        xlnx,reset-msr = <0x0>;
-                        xlnx,sco = <0x0>;
-                        xlnx,unaligned-exceptions = <0x1>;
-                        xlnx,use-barrel = <0x1>;
-                        xlnx,use-dcache = <0x1>;
-                        xlnx,use-div = <0x1>;
-                        xlnx,use-ext-brk = <0x1>;
-                        xlnx,use-ext-nm-brk = <0x1>;
-                        xlnx,use-extended-fsl-instr = <0x0>;
-                        xlnx,use-fpu = <0x2>;
-                        xlnx,use-hw-mul = <0x2>;
-                        xlnx,use-icache = <0x1>;
-                        xlnx,use-interrupt = <0x1>;
-                        xlnx,use-mmu = <0x3>;
-                        xlnx,use-msr-instr = <0x1>;
-                        xlnx,use-pcmp-instr = <0x1>;
-                } ;
-        } ;
-        mb_plb: plb@0 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
-                ranges ;
-                FLASH: flash@a0000000 {
-                        bank-width = <2>;
-                        compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
-                        reg = < 0xa0000000 0x2000000 >;
-                        xlnx,family = "virtex5";
-                        xlnx,include-datawidth-matching-0 = <0x1>;
-                        xlnx,include-datawidth-matching-1 = <0x0>;
-                        xlnx,include-datawidth-matching-2 = <0x0>;
-                        xlnx,include-datawidth-matching-3 = <0x0>;
-                        xlnx,include-negedge-ioregs = <0x0>;
-                        xlnx,include-plb-ipif = <0x1>;
-                        xlnx,include-wrbuf = <0x1>;
-                        xlnx,max-mem-width = <0x10>;
-                        xlnx,mch-native-dwidth = <0x20>;
-                        xlnx,mch-plb-clk-period-ps = <0x1f40>;
-                        xlnx,mch-splb-awidth = <0x20>;
-                        xlnx,mch0-accessbuf-depth = <0x10>;
-                        xlnx,mch0-protocol = <0x0>;
-                        xlnx,mch0-rddatabuf-depth = <0x10>;
-                        xlnx,mch1-accessbuf-depth = <0x10>;
-                        xlnx,mch1-protocol = <0x0>;
-                        xlnx,mch1-rddatabuf-depth = <0x10>;
-                        xlnx,mch2-accessbuf-depth = <0x10>;
-                        xlnx,mch2-protocol = <0x0>;
-                        xlnx,mch2-rddatabuf-depth = <0x10>;
-                        xlnx,mch3-accessbuf-depth = <0x10>;
-                        xlnx,mch3-protocol = <0x0>;
-                        xlnx,mch3-rddatabuf-depth = <0x10>;
-                        xlnx,mem0-width = <0x10>;
-                        xlnx,mem1-width = <0x20>;
-                        xlnx,mem2-width = <0x20>;
-                        xlnx,mem3-width = <0x20>;
-                        xlnx,num-banks-mem = <0x1>;
-                        xlnx,num-channels = <0x0>;
-                        xlnx,priority-mode = <0x0>;
-                        xlnx,synch-mem-0 = <0x0>;
-                        xlnx,synch-mem-1 = <0x0>;
-                        xlnx,synch-mem-2 = <0x0>;
-                        xlnx,synch-mem-3 = <0x0>;
-                        xlnx,synch-pipedelay-0 = <0x2>;
-                        xlnx,synch-pipedelay-1 = <0x2>;
-                        xlnx,synch-pipedelay-2 = <0x2>;
-                        xlnx,synch-pipedelay-3 = <0x2>;
-                        xlnx,tavdv-ps-mem-0 = <0x1adb0>;
-                        xlnx,tavdv-ps-mem-1 = <0x3a98>;
-                        xlnx,tavdv-ps-mem-2 = <0x3a98>;
-                        xlnx,tavdv-ps-mem-3 = <0x3a98>;
-                        xlnx,tcedv-ps-mem-0 = <0x1adb0>;
-                        xlnx,tcedv-ps-mem-1 = <0x3a98>;
-                        xlnx,tcedv-ps-mem-2 = <0x3a98>;
-                        xlnx,tcedv-ps-mem-3 = <0x3a98>;
-                        xlnx,thzce-ps-mem-0 = <0x88b8>;
-                        xlnx,thzce-ps-mem-1 = <0x1b58>;
-                        xlnx,thzce-ps-mem-2 = <0x1b58>;
-                        xlnx,thzce-ps-mem-3 = <0x1b58>;
-                        xlnx,thzoe-ps-mem-0 = <0x1b58>;
-                        xlnx,thzoe-ps-mem-1 = <0x1b58>;
-                        xlnx,thzoe-ps-mem-2 = <0x1b58>;
-                        xlnx,thzoe-ps-mem-3 = <0x1b58>;
-                        xlnx,tlzwe-ps-mem-0 = <0x88b8>;
-                        xlnx,tlzwe-ps-mem-1 = <0x0>;
-                        xlnx,tlzwe-ps-mem-2 = <0x0>;
-                        xlnx,tlzwe-ps-mem-3 = <0x0>;
-                        xlnx,twc-ps-mem-0 = <0x2af8>;
-                        xlnx,twc-ps-mem-1 = <0x3a98>;
-                        xlnx,twc-ps-mem-2 = <0x3a98>;
-                        xlnx,twc-ps-mem-3 = <0x3a98>;
-                        xlnx,twp-ps-mem-0 = <0x11170>;
-                        xlnx,twp-ps-mem-1 = <0x2ee0>;
-                        xlnx,twp-ps-mem-2 = <0x2ee0>;
-                        xlnx,twp-ps-mem-3 = <0x2ee0>;
-                        xlnx,xcl0-linesize = <0x4>;
-                        xlnx,xcl0-writexfer = <0x1>;
-                        xlnx,xcl1-linesize = <0x4>;
-                        xlnx,xcl1-writexfer = <0x1>;
-                        xlnx,xcl2-linesize = <0x4>;
-                        xlnx,xcl2-writexfer = <0x1>;
-                        xlnx,xcl3-linesize = <0x4>;
-                        xlnx,xcl3-writexfer = <0x1>;
-                } ;
-                Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "xlnx,compound";
-                        ranges ;
-                        ethernet@81c00000 {
-                                compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
-                                interrupt-parent = <&xps_intc_0>;
-                                interrupts = < 5 2 >;
-                                llink-connected = <&PIM3>;
-                                local-mac-address = [ 00 0a 35 00 00 00 ];
-                                reg = < 0x81c00000 0x40 >;
-                                xlnx,bus2core-clk-ratio = <0x1>;
-                                xlnx,phy-type = <0x1>;
-                                xlnx,phyaddr = <0x1>;
-                                xlnx,rxcsum = <0x0>;
-                                xlnx,rxfifo = <0x1000>;
-                                xlnx,temac-type = <0x0>;
-                                xlnx,txcsum = <0x0>;
-                                xlnx,txfifo = <0x1000>;
-                        } ;
-                } ;
-                IIC_EEPROM: i2c@81600000 {
-                        compatible = "xlnx,xps-iic-2.00.a";
-                        interrupt-parent = <&xps_intc_0>;
-                        interrupts = < 6 2 >;
-                        reg = < 0x81600000 0x10000 >;
-                        xlnx,clk-freq = <0x7735940>;
-                        xlnx,family = "virtex5";
-                        xlnx,gpo-width = <0x1>;
-                        xlnx,iic-freq = <0x186a0>;
-                        xlnx,scl-inertial-delay = <0x0>;
-                        xlnx,sda-inertial-delay = <0x0>;
-                        xlnx,ten-bit-adr = <0x0>;
-                } ;
-                LEDs_8Bit: gpio@81400000 {
-                        compatible = "xlnx,xps-gpio-1.00.a";
-                        interrupt-parent = <&xps_intc_0>;
-                        interrupts = < 7 2 >;
-                        reg = < 0x81400000 0x10000 >;
-                        xlnx,all-inputs = <0x0>;
-                        xlnx,all-inputs-2 = <0x0>;
-                        xlnx,dout-default = <0x0>;
-                        xlnx,dout-default-2 = <0x0>;
-                        xlnx,family = "virtex5";
-                        xlnx,gpio-width = <0x8>;
-                        xlnx,interrupt-present = <0x1>;
-                        xlnx,is-bidir = <0x1>;
-                        xlnx,is-bidir-2 = <0x1>;
-                        xlnx,is-dual = <0x0>;
-                        xlnx,tri-default = <0xffffffff>;
-                        xlnx,tri-default-2 = <0xffffffff>;
-                        #gpio-cells = <2>;
-                        gpio-controller;
-                } ;
-                gpio-leds {
-                        compatible = "gpio-leds";
-                        heartbeat {
-                                label = "Heartbeat";
-                                gpios = <&LEDs_8Bit 4 1>;
-                                linux,default-trigger = "heartbeat";
-                        };
-                        yellow {
-                                label = "Yellow";
-                                gpios = <&LEDs_8Bit 5 1>;
-                        };
-                        red {
-                                label = "Red";
-                                gpios = <&LEDs_8Bit 6 1>;
-                        };
-                        green {
-                                label = "Green";
-                                gpios = <&LEDs_8Bit 7 1>;
-                        };
-                } ;
-                RS232_Uart_1: serial@84000000 {
-                        clock-frequency = <125000000>;
-                        compatible = "xlnx,xps-uartlite-1.00.a";
-                        current-speed = <115200>;
-                        device_type = "serial";
-                        interrupt-parent = <&xps_intc_0>;
-                        interrupts = < 8 0 >;
-                        port-number = <0>;
-                        reg = < 0x84000000 0x10000 >;
-                        xlnx,baudrate = <0x1c200>;
-                        xlnx,data-bits = <0x8>;
-                        xlnx,family = "virtex5";
-                        xlnx,odd-parity = <0x0>;
-                        xlnx,use-parity = <0x0>;
-                } ;
-                SysACE_CompactFlash: sysace@83600000 {
-                        compatible = "xlnx,xps-sysace-1.00.a";
-                        interrupt-parent = <&xps_intc_0>;
-                        interrupts = < 4 2 >;
-                        reg = < 0x83600000 0x10000 >;
-                        xlnx,family = "virtex5";
-                        xlnx,mem-width = <0x10>;
-                } ;
-                debug_module: debug@84400000 {
-                        compatible = "xlnx,mdm-1.00.d";
-                        reg = < 0x84400000 0x10000 >;
-                        xlnx,family = "virtex5";
-                        xlnx,interconnect = <0x1>;
-                        xlnx,jtag-chain = <0x2>;
-                        xlnx,mb-dbg-ports = <0x1>;
-                        xlnx,uart-width = <0x8>;
-                        xlnx,use-uart = <0x1>;
-                        xlnx,write-fsl-ports = <0x0>;
-                } ;
-                mpmc@90000000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "xlnx,mpmc-4.02.a";
-                        ranges ;
-                        PIM3: sdma@84600180 {
-                                compatible = "xlnx,ll-dma-1.00.a";
-                                interrupt-parent = <&xps_intc_0>;
-                                interrupts = < 2 2 1 2 >;
-                                reg = < 0x84600180 0x80 >;
-                        } ;
-                } ;
-                xps_intc_0: interrupt-controller@81800000 {
-                        #interrupt-cells = <0x2>;
-                        compatible = "xlnx,xps-intc-1.00.a";
-                        interrupt-controller ;
-                        reg = < 0x81800000 0x10000 >;
-                        xlnx,kind-of-intr = <0x100>;
-                        xlnx,num-intr-inputs = <0x9>;
-                } ;
-                xps_timer_1: timer@83c00000 {
-                        compatible = "xlnx,xps-timer-1.00.a";
-                        interrupt-parent = <&xps_intc_0>;
-                        interrupts = < 3 2 >;
-                        reg = < 0x83c00000 0x10000 >;
-                        xlnx,count-width = <0x20>;
-                        xlnx,family = "virtex5";
-                        xlnx,gen0-assert = <0x1>;
-                        xlnx,gen1-assert = <0x1>;
-                        xlnx,one-timer-only = <0x0>;
-                        xlnx,trig0-assert = <0x1>;
-                        xlnx,trig1-assert = <0x1>;
-                } ;
-        } ;
-}  ;
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 95fa1f1d5c8b..5cd695f905a1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -10,6 +10,7 @@ config MIPS
        select HAVE_PERF_EVENTS
        select PERF_USE_VMALLOC
        select HAVE_ARCH_KGDB
+        select HAVE_ARCH_SECCOMP_FILTER
        select HAVE_ARCH_TRACEHOOK
        select ARCH_HAVE_CUSTOM_GPIO_H
        select HAVE_FUNCTION_TRACER
@@ -62,13 +63,12 @@ config MIPS_ALCHEMY
        select CEVT_R4K
        select CSRC_R4K
        select IRQ_CPU
+        select DMA_MAYBE_COHERENT       # Au1000,1500,1100 aren't, rest is
        select SYS_HAS_CPU_MIPS32_R1
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_APM_EMULATION
        select ARCH_REQUIRE_GPIOLIB
        select SYS_SUPPORTS_ZBOOT
-        select USB_ARCH_HAS_OHCI
-        select USB_ARCH_HAS_EHCI
 config AR7
        bool "Texas Instruments AR7"
@@ -123,7 +123,7 @@ config BCM47XX
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_HAS_EARLY_PRINTK
-        select EARLY_PRINTK_8250 if EARLY_PRINTK
+        select USE_GENERIC_EARLY_PRINTK_8250
        help
         Support for BCM47XX based boards
@@ -150,7 +150,6 @@ config MIPS_COBALT
        select CSRC_R4K
        select CEVT_GT641XX
        select DMA_NONCOHERENT
-        select EARLY_PRINTK_8250 if EARLY_PRINTK
        select HW_HAS_PCI
        select I8253
        select I8259
@@ -163,6 +162,7 @@ config MIPS_COBALT
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select USE_GENERIC_EARLY_PRINTK_8250
 config MACH_DECSTATION
        bool "DECstations"
@@ -175,7 +175,7 @@ config MACH_DECSTATION
        select CPU_R4000_WORKAROUNDS if 64BIT
        select CPU_R4400_WORKAROUNDS if 64BIT
        select DMA_NONCOHERENT
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        select IRQ_CPU
        select SYS_HAS_CPU_R3000
        select SYS_HAS_CPU_R4X00
@@ -235,7 +235,6 @@ config MACH_JZ4740
        select IRQ_CPU
        select ARCH_REQUIRE_GPIOLIB
        select SYS_HAS_EARLY_PRINTK
-        select HAVE_PWM
        select HAVE_CLK
        select GENERIC_IRQ_CHIP
@@ -320,6 +319,7 @@ config MIPS_MALTA
        select SWAP_IO_SPACE
        select SYS_HAS_CPU_MIPS32_R1
        select SYS_HAS_CPU_MIPS32_R2
+        select SYS_HAS_CPU_MIPS32_R3_5
        select SYS_HAS_CPU_MIPS64_R1
        select SYS_HAS_CPU_MIPS64_R2
        select SYS_HAS_CPU_NEVADA
@@ -329,6 +329,7 @@ config MIPS_MALTA
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_SUPPORTS_MIPS_CMP
+        select SYS_SUPPORTS_MIPS_CPS
        select SYS_SUPPORTS_MULTITHREADING
        select SYS_SUPPORTS_SMARTMIPS
        select SYS_SUPPORTS_ZBOOT
@@ -360,7 +361,6 @@ config MIPS_SEAD3
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_SUPPORTS_SMARTMIPS
        select SYS_SUPPORTS_MICROMIPS
-        select USB_ARCH_HAS_EHCI
        select USB_EHCI_BIG_ENDIAN_DESC
        select USB_EHCI_BIG_ENDIAN_MMIO
        select USE_OF
@@ -674,6 +674,7 @@ config SNI_RM
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_HIGHMEM
        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select USE_GENERIC_EARLY_PRINTK_8250
        help
          The SNI RM200/300/400 are MIPS-based machines manufactured by
          Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
@@ -718,8 +719,6 @@ config CAVIUM_OCTEON_SOC
        select SWAP_IO_SPACE
        select HW_HAS_PCI
        select ZONE_DMA32
-        select USB_ARCH_HAS_OHCI
-        select USB_ARCH_HAS_EHCI
        select HOLES_IN_ZONE
        select ARCH_REQUIRE_GPIOLIB
        help
@@ -756,8 +755,6 @@ config NLM_XLR_BOARD
        select ZONE_DMA32 if 64BIT
        select SYNC_R4K
        select SYS_HAS_EARLY_PRINTK
-        select USB_ARCH_HAS_OHCI if USB_SUPPORT
-        select USB_ARCH_HAS_EHCI if USB_SUPPORT
        select SYS_SUPPORTS_ZBOOT
        select SYS_SUPPORTS_ZBOOT_UART16550
        help
@@ -782,7 +779,6 @@ config NLM_XLP_BOARD
        select CEVT_R4K
        select CSRC_R4K
        select IRQ_CPU
-        select ARCH_SUPPORTS_MSI
        select ZONE_DMA32 if 64BIT
        select SYNC_R4K
        select SYS_HAS_EARLY_PRINTK
@@ -868,6 +864,7 @@ config CEVT_R4K
        bool
 config CEVT_GIC
+        select MIPS_CM
        bool
 config CEVT_SB1250
@@ -886,6 +883,7 @@ config CSRC_R4K
        bool
 config CSRC_GIC
+        select MIPS_CM
        bool
 config CSRC_SB1250
@@ -949,7 +947,7 @@ config SYNC_R4K
 config MIPS_MACHINE
        def_bool n
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool n
 config GENERIC_ISA_DMA
@@ -1030,6 +1028,7 @@ config IRQ_GT641XX
        bool
 config IRQ_GIC
+        select MIPS_CM
        bool
 config PCI_GT64XXX_PCI0
@@ -1148,6 +1147,18 @@ choice
        prompt "CPU type"
        default CPU_R4X00
+config CPU_LOONGSON3
+        bool "Loongson 3 CPU"
+        depends on SYS_HAS_CPU_LOONGSON3
+        select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_HUGEPAGES
+        select WEAK_ORDERING
+        select WEAK_REORDERING_BEYOND_LLSC
+        help
+                The Loongson 3 processor implements the MIPS64R2 instruction
+                set with many extensions.
 config CPU_LOONGSON2E
        bool "Loongson 2E"
        depends on SYS_HAS_CPU_LOONGSON2E
@@ -1203,6 +1214,7 @@ config CPU_MIPS32_R2
        select CPU_HAS_PREFETCH
        select CPU_SUPPORTS_32BIT_KERNEL
        select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_MSA
        select HAVE_KVM
        help
          Choose this option to build a kernel for release 2 or later of the
@@ -1238,6 +1250,7 @@ config CPU_MIPS64_R2
        select CPU_SUPPORTS_64BIT_KERNEL
        select CPU_SUPPORTS_HIGHMEM
        select CPU_SUPPORTS_HUGEPAGES
+        select CPU_SUPPORTS_MSA
        help
          Choose this option to build a kernel for release 2 or later of the
          MIPS64 architecture.  Many modern embedded systems with a 64-bit
@@ -1396,7 +1409,6 @@ config CPU_CAVIUM_OCTEON
        select LIBFDT
        select USE_OF
        select USB_EHCI_BIG_ENDIAN_MMIO
-        select SYS_HAS_DMA_OPS
        select MIPS_L1_CACHE_SHIFT_7
        help
          The Cavium Octeon processor is a highly integrated chip containing
@@ -1448,6 +1460,26 @@ config CPU_XLP
          Netlogic Microsystems XLP processors.
 endchoice
+config CPU_MIPS32_3_5_FEATURES
+        bool "MIPS32 Release 3.5 Features"
+        depends on SYS_HAS_CPU_MIPS32_R3_5
+        depends on CPU_MIPS32_R2
+        help
+          Choose this option to build a kernel for release 2 or later of the
+          MIPS32 architecture including features from the 3.5 release such as
+          support for Enhanced Virtual Addressing (EVA).
+config CPU_MIPS32_3_5_EVA
+        bool "Enhanced Virtual Addressing (EVA)"
+        depends on CPU_MIPS32_3_5_FEATURES
+        select EVA
+        default y
+        help
+          Choose this option if you want to enable the Enhanced Virtual
+          Addressing (EVA) on your MIPS32 core (such as proAptiv).
+          One of its primary benefits is an increase in the maximum size
+          of lowmem (up to 3GB). If unsure, say 'N' here.
 if CPU_LOONGSON2F
 config CPU_NOP_WORKAROUNDS
        bool
@@ -1523,6 +1555,10 @@ config CPU_BMIPS5000
        select SYS_SUPPORTS_SMP
        select SYS_SUPPORTS_HOTPLUG_CPU
+config SYS_HAS_CPU_LOONGSON3
+        bool
+        select CPU_SUPPORTS_CPUFREQ
 config SYS_HAS_CPU_LOONGSON2E
        bool
@@ -1541,6 +1577,9 @@ config SYS_HAS_CPU_MIPS32_R1
 config SYS_HAS_CPU_MIPS32_R2
        bool
+config SYS_HAS_CPU_MIPS32_R3_5
+        bool
 config SYS_HAS_CPU_MIPS64_R1
        bool
@@ -1657,6 +1696,9 @@ config CPU_MIPSR2
        bool
        default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
+config EVA
+        bool
 config SYS_SUPPORTS_32BIT_KERNEL
        bool
 config SYS_SUPPORTS_64BIT_KERNEL
@@ -1729,7 +1771,7 @@ choice
 config PAGE_SIZE_4KB
        bool "4kB"
-        depends on !CPU_LOONGSON2
+        depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
        help
         This option select the standard 4kB Linux page size.  On some
         R3000-family processors this is the only available page size.  Using
@@ -1870,6 +1912,7 @@ config MIPS_MT_SMP
        select CPU_MIPSR2_IRQ_VI
        select CPU_MIPSR2_IRQ_EI
        select SYNC_R4K
+        select MIPS_GIC_IPI
        select MIPS_MT
        select SMP
        select SMP_UP
@@ -1887,6 +1930,7 @@ config MIPS_MT_SMTC
        bool "Use all TCs on all VPEs for SMP (DEPRECATED)"
        depends on CPU_MIPS32_R2
        depends on SYS_SUPPORTS_MULTITHREADING
+        depends on !MIPS_CPS
        select CPU_MIPSR2_IRQ_VI
        select CPU_MIPSR2_IRQ_EI
        select MIPS_MT
@@ -1994,13 +2038,45 @@ config MIPS_VPE_APSP_API_MT
        depends on MIPS_VPE_APSP_API && !MIPS_CMP
 config MIPS_CMP
-        bool "MIPS CMP support"
+        bool "MIPS CMP framework support (DEPRECATED)"
-        depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP
+        depends on SYS_SUPPORTS_MIPS_CMP && !MIPS_MT_SMTC
+        select MIPS_GIC_IPI
        select SYNC_R4K
        select WEAK_ORDERING
        default n
        help
-          Enable Coherency Manager processor (CMP) support.
+          Select this if you are using a bootloader which implements the "CMP
+          framework" protocol (ie. YAMON) and want your kernel to make use of
+          its ability to start secondary CPUs.
+          Unless you have a specific need, you should use CONFIG_MIPS_CPS
+          instead of this.
+config MIPS_CPS
+        bool "MIPS Coherent Processing System support"
+        depends on SYS_SUPPORTS_MIPS_CPS
+        select MIPS_CM
+        select MIPS_CPC
+        select MIPS_GIC_IPI
+        select SMP
+        select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
+        select SYS_SUPPORTS_SMP
+        select WEAK_ORDERING
+        help
+          Select this if you wish to run an SMP kernel across multiple cores
+          within a MIPS Coherent Processing System. When this option is
+          enabled the kernel will probe for other cores and boot them with
+          no external assistance. It is safe to enable this when hardware
+          support is unavailable.
+config MIPS_GIC_IPI
+        bool
+config MIPS_CM
+        bool
+config MIPS_CPC
+        bool
 config SB1_PASS_1_WORKAROUNDS
        bool
@@ -2043,6 +2119,21 @@ config CPU_MICROMIPS
          When this option is enabled the kernel will be built using the
          microMIPS ISA
+config CPU_HAS_MSA
+        bool "Support for the MIPS SIMD Architecture"
+        depends on CPU_SUPPORTS_MSA
+        default y
+        help
+          MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
+          and a set of SIMD instructions to operate on them. When this option
+          is enabled the kernel will support allocating & switching MSA
+          vector register contexts. If you know that your kernel will only be
+          running on CPUs which do not support MSA or that your userland will
+          not be making use of it then you may wish to say N here to reduce
+          the size & complexity of your kernel.
+          If unsure, say Y.
 config CPU_HAS_WB
        bool
@@ -2094,7 +2185,7 @@ config CPU_R4400_WORKAROUNDS
 #
 config HIGHMEM
        bool "High Memory Support"
-        depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
+        depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
 config CPU_SUPPORTS_HIGHMEM
        bool
@@ -2108,6 +2199,9 @@ config SYS_SUPPORTS_SMARTMIPS
 config SYS_SUPPORTS_MICROMIPS
        bool
+config CPU_SUPPORTS_MSA
+        bool
 config ARCH_FLATMEM_ENABLE
        def_bool y
        depends on !NUMA && !CPU_LOONGSON2
@@ -2181,6 +2275,9 @@ config SMP_UP
 config SYS_SUPPORTS_MIPS_CMP
        bool
+config SYS_SUPPORTS_MIPS_CPS
+        bool
 config SYS_SUPPORTS_SMP
        bool
@@ -2413,6 +2510,17 @@ config PCI
          your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
          say Y, otherwise N.
+config HT_PCI
+        bool "Support for HT-linked PCI"
+        default y
+        depends on CPU_LOONGSON3
+        select PCI
+        select PCI_DOMAINS
+        help
+          Loongson family machines use Hyper-Transport bus for inter-core
+          connection and device connection. The PCI bus is a subordinate
+          linked at HT. Choose Y for Loongson-3 based machines.
 config PCI_DOMAINS
        bool
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index b147e7038ff0..25de29211d76 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -21,13 +21,17 @@ config EARLY_PRINTK
          unless you want to debug such a crash.
 config EARLY_PRINTK_8250
-        bool "8250/16550 and compatible serial early printk driver"
+        bool
-        depends on EARLY_PRINTK
+        depends on EARLY_PRINTK && USE_GENERIC_EARLY_PRINTK_8250
-        default n
+        default y
        help
+          "8250/16550 and compatible serial early printk driver"
          If you say Y here, it will be possible to use a 8250/16550 serial
          port as the boot console.
+config USE_GENERIC_EARLY_PRINTK_8250
+        bool
 config CMDLINE_BOOL
        bool "Built-in kernel command line"
        default n
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9b8556de9993..1a5b4032cb66 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -119,6 +119,11 @@ cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
 cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
                                   -fno-omit-frame-pointer
+ifeq ($(CONFIG_CPU_HAS_MSA),y)
+toolchain-msa                   := $(call cc-option-yn,-mhard-float -mfp64 -mmsa)
+cflags-$(toolchain-msa)         += -DTOOLCHAIN_SUPPORTS_MSA
+endif
 #
 # CPU-dependent compiler/assembler options for optimization.
 #
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 7032ac7ecd1b..b9628983d620 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -16,36 +16,29 @@ config ALCHEMY_GPIO_INDIRECT
 choice
        prompt "Machine type"
        depends on MIPS_ALCHEMY
-        default MIPS_DB1000
+        default MIPS_DB1XXX
 config MIPS_MTX1
        bool "4G Systems MTX-1 board"
-        select DMA_NONCOHERENT
        select HW_HAS_PCI
        select ALCHEMY_GPIOINT_AU1000
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_HAS_EARLY_PRINTK
-config MIPS_DB1000
+config MIPS_DB1XXX
-        bool "Alchemy DB1000/DB1500/DB1100 PB1500/1100 boards"
+        bool "Alchemy DB1XXX / PB1XXX boards"
-        select ALCHEMY_GPIOINT_AU1000
-        select DMA_NONCOHERENT
-        select HW_HAS_PCI
-        select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_HAS_EARLY_PRINTK
-config MIPS_DB1235
-        bool "Alchemy DB1200/PB1200/DB1300/DB1550/PB1550 boards"
        select ARCH_REQUIRE_GPIOLIB
        select HW_HAS_PCI
-        select DMA_COHERENT
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_HAS_EARLY_PRINTK
+        help
+          Select this option if you have one of the following Alchemy
+          development boards:  DB1000 DB1500 DB1100 DB1550 DB1200 DB1300
+                               PB1500 PB1100 PB1550 PB1200
+          Board type is autodetected during boot.
 config MIPS_XXS1500
        bool "MyCable XXS1500 board"
-        select DMA_NONCOHERENT
        select ALCHEMY_GPIOINT_AU1000
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_HAS_EARLY_PRINTK
@@ -54,7 +47,6 @@ config MIPS_GPR
        bool "Trapeze ITS GPR board"
        select ALCHEMY_GPIOINT_AU1000
        select HW_HAS_PCI
-        select DMA_NONCOHERENT
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_HAS_EARLY_PRINTK
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index b3afcdd8d77a..33c9da3b077b 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -5,18 +5,12 @@ platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
 #
-# AMD Alchemy Db1000/Db1500/Pb1500/Db1100/Pb1100 eval boards
+# AMD Alchemy Db1000/Db1500/Pb1500/Db1100/Pb1100
+#             Db1550/Pb1550/Db1200/Pb1200/Db1300
 #
-platform-$(CONFIG_MIPS_DB1000)  += alchemy/devboards/
+platform-$(CONFIG_MIPS_DB1XXX)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1000)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+cflags-$(CONFIG_MIPS_DB1XXX)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1000)      += 0xffffffff80100000
+load-$(CONFIG_MIPS_DB1XXX)      += 0xffffffff80100000
-#
-# AMD Alchemy Db1200/Pb1200/Db1550/Pb1550/Db1300 eval boards
-#
-platform-$(CONFIG_MIPS_DB1235)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1235)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1235)      += 0xffffffff80100000
 #
 # 4G-Systems MTX-1 "MeshCube" wireless router
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 62b4e7bbeab9..566a1743f685 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -30,6 +30,7 @@
 #include <linux/jiffies.h>
 #include <linux/module.h>
+#include <asm/dma-coherence.h>
 #include <asm/mipsregs.h>
 #include <asm/time.h>
@@ -59,6 +60,15 @@ void __init plat_mem_setup(void)
                /* Clear to obtain best system bus performance */
                clear_c0_config(1 << 19); /* Clear Config[OD] */
+        hw_coherentio = 0;
+        coherentio = 1;
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+        case ALCHEMY_CPU_AU1500:
+        case ALCHEMY_CPU_AU1100:
+                coherentio = 0;
+        }
        board_setup();  /* board specific setup */
        /* IO/MEM resources. */
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 706d933e0085..c73d81270b42 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -95,7 +95,7 @@ LEAF(alchemy_sleep_au1000)
        /* cache following instructions, as memory gets put to sleep */
        la      t0, 1f
-        .set    mips3
+        .set    arch=r4000
        cache   0x14, 0(t0)
        cache   0x14, 32(t0)
        cache   0x14, 64(t0)
@@ -121,7 +121,7 @@ LEAF(alchemy_sleep_au1550)
        /* cache following instructions, as memory gets put to sleep */
        la      t0, 1f
-        .set    mips3
+        .set    arch=r4000
        cache   0x14, 0(t0)
        cache   0x14, 32(t0)
        cache   0x14, 64(t0)
@@ -163,7 +163,7 @@ LEAF(alchemy_sleep_au1300)
        la      t1, 4f
        subu    t2, t1, t0
-        .set    mips3
+        .set    arch=r4000
 1:      cache   0x14, 0(t0)
        subu    t2, t2, 32
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 15bf7306648b..9da3659a9d1c 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -2,7 +2,5 @@
 # Alchemy Develboards
 #
-obj-y += bcsr.o platform.o
+obj-y += bcsr.o platform.o db1000.o db1200.o db1300.o db1550.o db1xxx.o
 obj-$(CONFIG_PM)                += pm.o
-obj-$(CONFIG_MIPS_DB1000)       += db1000.o
-obj-$(CONFIG_MIPS_DB1235)       += db1235.o db1200.o db1300.o db1550.o
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
index 5483906e0f86..92dd929d4057 100644
--- a/arch/mips/alchemy/devboards/db1000.c
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -41,42 +41,27 @@
 #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
-struct pci_dev;
+const char *get_system_type(void);
-static const char *board_type_str(void)
+int __init db1000_board_setup(void)
 {
+        /* initialize board register space */
+        bcsr_init(DB1000_BCSR_PHYS_ADDR,
+                  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
        switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
        case BCSR_WHOAMI_DB1000:
-                return "DB1000";
        case BCSR_WHOAMI_DB1500:
-                return "DB1500";
        case BCSR_WHOAMI_DB1100:
-                return "DB1100";
        case BCSR_WHOAMI_PB1500:
        case BCSR_WHOAMI_PB1500R2:
-                return "PB1500";
        case BCSR_WHOAMI_PB1100:
-                return "PB1100";
+                pr_info("AMD Alchemy %s Board\n", get_system_type());
-        default:
+                return 0;
-                return "(unknown)";
        }
+        return -ENODEV;
 }
-const char *get_system_type(void)
-{
-        return board_type_str();
-}
-void __init board_setup(void)
-{
-        /* initialize board register space */
-        bcsr_init(DB1000_BCSR_PHYS_ADDR,
-                  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
-        printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str());
-}
 static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 {
        if ((slot < 12) || (slot > 13) || pin == 0)
@@ -114,17 +99,10 @@ static struct platform_device db1500_pci_host_dev = {
        .resource       = alchemy_pci_host_res,
 };
-static int __init db1500_pci_init(void)
+int __init db1500_pci_setup(void)
 {
-        int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
+        return platform_device_register(&db1500_pci_host_dev);
-        if ((id == BCSR_WHOAMI_DB1500) || (id == BCSR_WHOAMI_PB1500) ||
-            (id == BCSR_WHOAMI_PB1500R2))
-                return platform_device_register(&db1500_pci_host_dev);
-        return 0;
 }
-/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
-arch_initcall(db1500_pci_init);
 static struct resource au1100_lcd_resources[] = {
        [0] = {
@@ -513,7 +491,7 @@ static struct platform_device *db1100_devs[] = {
        &db1000_irda_dev,
 };
-static int __init db1000_dev_init(void)
+int __init db1000_dev_setup(void)
 {
        int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
        int c0, c1, d0, d1, s0, s1, flashsize = 32,  twosocks = 1;
@@ -623,4 +601,3 @@ static int __init db1000_dev_init(void)
        db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
        return 0;
 }
-device_initcall(db1000_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index a84d98b8f96e..9e46667f2597 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -35,16 +35,63 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/smc91x.h>
+#include <linux/ata_platform.h>
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/au1100_mmc.h>
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
+#include <asm/mach-au1x00/au1xxx_psc.h>
 #include <asm/mach-au1x00/au1200fb.h>
 #include <asm/mach-au1x00/au1550_spi.h>
 #include <asm/mach-db1x00/bcsr.h>
-#include <asm/mach-db1x00/db1200.h>
 #include "platform.h"
+#define BCSR_INT_IDE            0x0001
+#define BCSR_INT_ETH            0x0002
+#define BCSR_INT_PC0            0x0004
+#define BCSR_INT_PC0STSCHG      0x0008
+#define BCSR_INT_PC1            0x0010
+#define BCSR_INT_PC1STSCHG      0x0020
+#define BCSR_INT_DC             0x0040
+#define BCSR_INT_FLASHBUSY      0x0080
+#define BCSR_INT_PC0INSERT      0x0100
+#define BCSR_INT_PC0EJECT       0x0200
+#define BCSR_INT_PC1INSERT      0x0400
+#define BCSR_INT_PC1EJECT       0x0800
+#define BCSR_INT_SD0INSERT      0x1000
+#define BCSR_INT_SD0EJECT       0x2000
+#define BCSR_INT_SD1INSERT      0x4000
+#define BCSR_INT_SD1EJECT       0x8000
+#define DB1200_IDE_PHYS_ADDR    0x18800000
+#define DB1200_IDE_REG_SHIFT    5
+#define DB1200_IDE_PHYS_LEN     (16 << DB1200_IDE_REG_SHIFT)
+#define DB1200_ETH_PHYS_ADDR    0x19000300
+#define DB1200_NAND_PHYS_ADDR   0x20000000
+#define PB1200_IDE_PHYS_ADDR    0x0C800000
+#define PB1200_ETH_PHYS_ADDR    0x0D000300
+#define PB1200_NAND_PHYS_ADDR   0x1C000000
+#define DB1200_INT_BEGIN        (AU1000_MAX_INTR + 1)
+#define DB1200_IDE_INT          (DB1200_INT_BEGIN + 0)
+#define DB1200_ETH_INT          (DB1200_INT_BEGIN + 1)
+#define DB1200_PC0_INT          (DB1200_INT_BEGIN + 2)
+#define DB1200_PC0_STSCHG_INT   (DB1200_INT_BEGIN + 3)
+#define DB1200_PC1_INT          (DB1200_INT_BEGIN + 4)
+#define DB1200_PC1_STSCHG_INT   (DB1200_INT_BEGIN + 5)
+#define DB1200_DC_INT           (DB1200_INT_BEGIN + 6)
+#define DB1200_FLASHBUSY_INT    (DB1200_INT_BEGIN + 7)
+#define DB1200_PC0_INSERT_INT   (DB1200_INT_BEGIN + 8)
+#define DB1200_PC0_EJECT_INT    (DB1200_INT_BEGIN + 9)
+#define DB1200_PC1_INSERT_INT   (DB1200_INT_BEGIN + 10)
+#define DB1200_PC1_EJECT_INT    (DB1200_INT_BEGIN + 11)
+#define DB1200_SD0_INSERT_INT   (DB1200_INT_BEGIN + 12)
+#define DB1200_SD0_EJECT_INT    (DB1200_INT_BEGIN + 13)
+#define PB1200_SD1_INSERT_INT   (DB1200_INT_BEGIN + 14)
+#define PB1200_SD1_EJECT_INT    (DB1200_INT_BEGIN + 15)
+#define DB1200_INT_END          (DB1200_INT_BEGIN + 15)
 const char *get_system_type(void);
 static int __init db1200_detect_board(void)
@@ -89,6 +136,15 @@ int __init db1200_board_setup(void)
                return -ENODEV;
        whoami = bcsr_read(BCSR_WHOAMI);
+        switch (BCSR_WHOAMI_BOARD(whoami)) {
+        case BCSR_WHOAMI_PB1200_DDR1:
+        case BCSR_WHOAMI_PB1200_DDR2:
+        case BCSR_WHOAMI_DB1200:
+                break;
+        default:
+                return -ENODEV;
+        }
        printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
                "  Board-ID %d  Daughtercard ID %d\n", get_system_type(),
                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
@@ -275,32 +331,38 @@ static struct platform_device db1200_eth_dev = {
 /**********************************************************************/
+static struct pata_platform_info db1200_ide_info = {
+        .ioport_shift   = DB1200_IDE_REG_SHIFT,
+};
+#define IDE_ALT_START   (14 << DB1200_IDE_REG_SHIFT)
 static struct resource db1200_ide_res[] = {
        [0] = {
                .start  = DB1200_IDE_PHYS_ADDR,
-                .end    = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
+                .end    = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
+                .start  = DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
+                .end    = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
                .start  = DB1200_IDE_INT,
                .end    = DB1200_IDE_INT,
                .flags  = IORESOURCE_IRQ,
        },
-        [2] = {
-                .start  = AU1200_DSCR_CMD0_DMA_REQ1,
-                .end    = AU1200_DSCR_CMD0_DMA_REQ1,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
 static struct platform_device db1200_ide_dev = {
-        .name           = "au1200-ide",
+        .name           = "pata_platform",
        .id             = 0,
        .dev = {
                .dma_mask               = &au1200_ide_dmamask,
                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &db1200_ide_info,
        },
        .num_resources  = ARRAY_SIZE(db1200_ide_res),
        .resource       = db1200_ide_res,
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index 6167e73eef9c..1aed6be4de10 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -26,12 +26,44 @@
 #include <asm/mach-au1x00/au1200fb.h>
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
 #include <asm/mach-au1x00/au1xxx_psc.h>
-#include <asm/mach-db1x00/db1300.h>
 #include <asm/mach-db1x00/bcsr.h>
 #include <asm/mach-au1x00/prom.h>
 #include "platform.h"
+/* FPGA (external mux) interrupt sources */
+#define DB1300_FIRST_INT        (ALCHEMY_GPIC_INT_LAST + 1)
+#define DB1300_IDE_INT          (DB1300_FIRST_INT + 0)
+#define DB1300_ETH_INT          (DB1300_FIRST_INT + 1)
+#define DB1300_CF_INT           (DB1300_FIRST_INT + 2)
+#define DB1300_VIDEO_INT        (DB1300_FIRST_INT + 4)
+#define DB1300_HDMI_INT         (DB1300_FIRST_INT + 5)
+#define DB1300_DC_INT           (DB1300_FIRST_INT + 6)
+#define DB1300_FLASH_INT        (DB1300_FIRST_INT + 7)
+#define DB1300_CF_INSERT_INT    (DB1300_FIRST_INT + 8)
+#define DB1300_CF_EJECT_INT     (DB1300_FIRST_INT + 9)
+#define DB1300_AC97_INT         (DB1300_FIRST_INT + 10)
+#define DB1300_AC97_PEN_INT     (DB1300_FIRST_INT + 11)
+#define DB1300_SD1_INSERT_INT   (DB1300_FIRST_INT + 12)
+#define DB1300_SD1_EJECT_INT    (DB1300_FIRST_INT + 13)
+#define DB1300_OTG_VBUS_OC_INT  (DB1300_FIRST_INT + 14)
+#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
+#define DB1300_LAST_INT         (DB1300_FIRST_INT + 15)
+/* SMSC9210 CS */
+#define DB1300_ETH_PHYS_ADDR    0x19000000
+#define DB1300_ETH_PHYS_END     0x197fffff
+/* ATA CS */
+#define DB1300_IDE_PHYS_ADDR    0x18800000
+#define DB1300_IDE_REG_SHIFT    5
+#define DB1300_IDE_PHYS_LEN     (16 << DB1300_IDE_REG_SHIFT)
+/* NAND CS */
+#define DB1300_NAND_PHYS_ADDR   0x20000000
+#define DB1300_NAND_PHYS_END    0x20000fff
 static struct i2c_board_info db1300_i2c_devs[] __initdata = {
        { I2C_BOARD_INFO("wm8731", 0x1b), },    /* I2S audio codec */
        { I2C_BOARD_INFO("ne1619", 0x2d), },    /* adm1025-compat hwmon */
@@ -759,11 +791,15 @@ int __init db1300_board_setup(void)
 {
        unsigned short whoami;
-        db1300_gpio_config();
        bcsr_init(DB1300_BCSR_PHYS_ADDR,
                  DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
        whoami = bcsr_read(BCSR_WHOAMI);
+        if (BCSR_WHOAMI_BOARD(whoami) != BCSR_WHOAMI_DB1300)
+                return -ENODEV;
+        db1300_gpio_config();
        printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
                "BoardID %d   CPLD Rev %d   DaughtercardID %d\n",
                BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),
diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c
index 016cddacd7ea..bbd8d9884702 100644
--- a/arch/mips/alchemy/devboards/db1550.c
+++ b/arch/mips/alchemy/devboards/db1550.c
@@ -62,10 +62,16 @@ int __init db1550_board_setup(void)
                  DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
        whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
-        if ((BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_SDR) ||
+        switch (BCSR_WHOAMI_BOARD(whoami)) {
-            (BCSR_WHOAMI_BOARD(whoami) == BCSR_WHOAMI_PB1550_DDR))
+        case BCSR_WHOAMI_PB1550_SDR:
+        case BCSR_WHOAMI_PB1550_DDR:
                bcsr_init(PB1550_BCSR_PHYS_ADDR,
                          PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
+        case BCSR_WHOAMI_DB1550:
+                break;
+        default:
+                return -ENODEV;
+        }
        pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d  "       \
                "Daughtercard ID %d\n", get_system_type(),
diff --git a/arch/mips/alchemy/devboards/db1235.c b/arch/mips/alchemy/devboards/db1xxx.c
index bac19dc43d1d..2d47f951121a 100644
--- a/arch/mips/alchemy/devboards/db1235.c
+++ b/arch/mips/alchemy/devboards/db1xxx.c
@@ -1,12 +1,13 @@
 /*
- * DB1200/PB1200 / DB1550 / DB1300 board support.
+ * Alchemy DB/PB1xxx board support.
- *
- * These 4 boards can reliably be supported in a single kernel image.
 */
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-db1x00/bcsr.h>
+int __init db1000_board_setup(void);
+int __init db1000_dev_setup(void);
+int __init db1500_pci_setup(void);
 int __init db1200_board_setup(void);
 int __init db1200_dev_setup(void);
 int __init db1300_board_setup(void);
@@ -18,6 +19,17 @@ int __init db1550_pci_setup(int);
 static const char *board_type_str(void)
 {
        switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
+        case BCSR_WHOAMI_DB1000:
+                return "DB1000";
+        case BCSR_WHOAMI_DB1500:
+                return "DB1500";
+        case BCSR_WHOAMI_DB1100:
+                return "DB1100";
+        case BCSR_WHOAMI_PB1500:
+        case BCSR_WHOAMI_PB1500R2:
+                return "PB1500";
+        case BCSR_WHOAMI_PB1100:
+                return "PB1100";
        case BCSR_WHOAMI_PB1200_DDR1:
        case BCSR_WHOAMI_PB1200_DDR2:
                return "PB1200";
@@ -45,6 +57,11 @@ void __init board_setup(void)
        int ret;
        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+        case ALCHEMY_CPU_AU1500:
+        case ALCHEMY_CPU_AU1100:
+                ret = db1000_board_setup();
+                break;
        case ALCHEMY_CPU_AU1550:
                ret = db1550_board_setup();
                break;
@@ -62,7 +79,7 @@ void __init board_setup(void)
                panic("cannot initialize board support");
 }
-int __init db1235_arch_init(void)
+static int __init db1xxx_arch_init(void)
 {
        int id = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
        if (id == BCSR_WHOAMI_DB1550)
@@ -70,14 +87,24 @@ int __init db1235_arch_init(void)
        else if ((id == BCSR_WHOAMI_PB1550_SDR) ||
                 (id == BCSR_WHOAMI_PB1550_DDR))
                return db1550_pci_setup(1);
+        else if ((id == BCSR_WHOAMI_DB1500) || (id == BCSR_WHOAMI_PB1500) ||
+                 (id == BCSR_WHOAMI_PB1500R2))
+                return db1500_pci_setup();
        return 0;
 }
-arch_initcall(db1235_arch_init);
+arch_initcall(db1xxx_arch_init);
-int __init db1235_dev_init(void)
+static int __init db1xxx_dev_init(void)
 {
        switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
+        case BCSR_WHOAMI_DB1000:
+        case BCSR_WHOAMI_DB1500:
+        case BCSR_WHOAMI_DB1100:
+        case BCSR_WHOAMI_PB1500:
+        case BCSR_WHOAMI_PB1500R2:
+        case BCSR_WHOAMI_PB1100:
+                return db1000_dev_setup();
        case BCSR_WHOAMI_PB1200_DDR1:
        case BCSR_WHOAMI_PB1200_DDR2:
        case BCSR_WHOAMI_DB1200:
@@ -91,4 +118,4 @@ int __init db1235_dev_init(void)
        }
        return 0;
 }
-device_initcall(db1235_dev_init);
+device_initcall(db1xxx_dev_init);
diff --git a/arch/mips/ar7/time.c b/arch/mips/ar7/time.c
index 1dc6c3b37f91..22c93213b233 100644
--- a/arch/mips/ar7/time.c
+++ b/arch/mips/ar7/time.c
@@ -18,6 +18,7 @@
 * Setting up the clock on the MIPS boards.
 */
+#include <linux/init.h>
 #include <linux/time.h>
 #include <linux/err.h>
 #include <linux/clk.h>
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index 3995e31a73e2..dfc60209dc63 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -74,34 +74,26 @@ config ATH79_MACH_UBNT_XM
 endmenu
 config SOC_AR71XX
-        select USB_ARCH_HAS_EHCI
-        select USB_ARCH_HAS_OHCI
        select HW_HAS_PCI
        def_bool n
 config SOC_AR724X
-        select USB_ARCH_HAS_EHCI
-        select USB_ARCH_HAS_OHCI
        select HW_HAS_PCI
        select PCI_AR724X if PCI
        def_bool n
 config SOC_AR913X
-        select USB_ARCH_HAS_EHCI
        def_bool n
 config SOC_AR933X
-        select USB_ARCH_HAS_EHCI
        def_bool n
 config SOC_AR934X
-        select USB_ARCH_HAS_EHCI
        select HW_HAS_PCI
        select PCI_AR724X if PCI
        def_bool n
 config SOC_QCA955X
-        select USB_ARCH_HAS_EHCI
        select HW_HAS_PCI
        select PCI_AR724X if PCI
        def_bool n
diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile
index 4688b6a6211b..d58c51b5e501 100644
--- a/arch/mips/bcm47xx/Makefile
+++ b/arch/mips/bcm47xx/Makefile
@@ -4,4 +4,4 @@
 #
 obj-y                           += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
-obj-y                           += board.o buttons.o leds.o
+obj-y                           += board.o buttons.o leds.o workarounds.o
diff --git a/arch/mips/bcm47xx/bcm47xx_private.h b/arch/mips/bcm47xx/bcm47xx_private.h
index 5c94acebf76a..0194c3b9a729 100644
--- a/arch/mips/bcm47xx/bcm47xx_private.h
+++ b/arch/mips/bcm47xx/bcm47xx_private.h
@@ -9,4 +9,7 @@ int __init bcm47xx_buttons_register(void);
 /* leds.c */
 void __init bcm47xx_leds_register(void);
+/* workarounds.c */
+void __init bcm47xx_workarounds(void);
 #endif
diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
index cdd8246f92b3..44ab1be68c3c 100644
--- a/arch/mips/bcm47xx/board.c
+++ b/arch/mips/bcm47xx/board.c
@@ -72,7 +72,11 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initcons
        {{BCM47XX_BOARD_ASUS_WL500W, "Asus WL500W"}, "WL500gW-"},
        {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"},
        {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"},
+        {{BCM47XX_BOARD_BELKIN_F7D3301, "Belkin F7D3301"}, "F7D3301"},
+        {{BCM47XX_BOARD_BELKIN_F7D3302, "Belkin F7D3302"}, "F7D3302"},
        {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"},
+        {{BCM47XX_BOARD_BELKIN_F7D4302, "Belkin F7D4302"}, "F7D4302"},
+        {{BCM47XX_BOARD_BELKIN_F7D4401, "Belkin F7D4401"}, "F7D4401"},
        { {0}, NULL},
 };
@@ -176,7 +180,16 @@ struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
        {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
        {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
        {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"},
-        {{BCM47XX_BOARD_LINKSYS_WRT54GSV1, "Linksys WRT54GS V1"}, "0x0101", "42", "0x10"},
+        {{BCM47XX_BOARD_LINKSYS_WRT54G, "Linksys WRT54G/GS/GL"}, "0x0101", "42", "0x10"},
+        {{BCM47XX_BOARD_LINKSYS_WRT54G, "Linksys WRT54G/GS/GL"}, "0x0467", "42", "0x10"},
+        {{BCM47XX_BOARD_LINKSYS_WRT54G, "Linksys WRT54G/GS/GL"}, "0x0708", "42", "0x10"},
+        { {0}, NULL},
+};
+/* boardtype, boardrev */
+static const
+struct bcm47xx_board_type_list2 bcm47xx_board_list_board_type_rev[] __initconst = {
+        {{BCM47XX_BOARD_SIEMENS_SE505V2, "Siemens SE505 V2"}, "0x0101", "0x10"},
        { {0}, NULL},
 };
@@ -273,6 +286,16 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
                                return &e3->board;
                }
        }
+        if (bcm47xx_nvram_getenv("boardtype", buf1, sizeof(buf1)) >= 0 &&
+            bcm47xx_nvram_getenv("boardrev", buf2, sizeof(buf2)) >= 0 &&
+            bcm47xx_nvram_getenv("boardnum", buf3, sizeof(buf3)) ==  -ENOENT) {
+                for (e2 = bcm47xx_board_list_board_type_rev; e2->value1; e2++) {
+                        if (!strcmp(buf1, e2->value1) &&
+                            !strcmp(buf2, e2->value2))
+                                return &e2->board;
+                }
+        }
        return bcm47xx_board_unknown;
 }
diff --git a/arch/mips/bcm47xx/buttons.c b/arch/mips/bcm47xx/buttons.c
index 872c62e93e0e..49a1ce06844b 100644
--- a/arch/mips/bcm47xx/buttons.c
+++ b/arch/mips/bcm47xx/buttons.c
@@ -259,6 +259,18 @@ bcm47xx_buttons_linksys_wrt310nv1[] __initconst = {
 };
 static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {
+        BCM47XX_GPIO_KEY(5, KEY_WIMAX),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrt54gsv1[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
+static const struct gpio_keys_button
 bcm47xx_buttons_linksys_wrt610nv1[] __initconst = {
        BCM47XX_GPIO_KEY(6, KEY_RESTART),
        BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON),
@@ -270,6 +282,12 @@ bcm47xx_buttons_linksys_wrt610nv2[] __initconst = {
        BCM47XX_GPIO_KEY(6, KEY_RESTART),
 };
+static const struct gpio_keys_button
+bcm47xx_buttons_linksys_wrtsl54gs[] __initconst = {
+        BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
+        BCM47XX_GPIO_KEY(6, KEY_RESTART),
+};
 /* Motorola */
 static const struct gpio_keys_button
@@ -402,7 +420,11 @@ int __init bcm47xx_buttons_register(void)
                err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wlhdd);
                break;
+        case BCM47XX_BOARD_BELKIN_F7D3301:
+        case BCM47XX_BOARD_BELKIN_F7D3302:
        case BCM47XX_BOARD_BELKIN_F7D4301:
+        case BCM47XX_BOARD_BELKIN_F7D4302:
+        case BCM47XX_BOARD_BELKIN_F7D4401:
                err = bcm47xx_copy_bdata(bcm47xx_buttons_belkin_f7d4301);
                break;
@@ -479,12 +501,21 @@ int __init bcm47xx_buttons_register(void)
        case BCM47XX_BOARD_LINKSYS_WRT310NV1:
                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
                break;
+        case BCM47XX_BOARD_LINKSYS_WRT54G:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54gsv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
+                break;
        case BCM47XX_BOARD_LINKSYS_WRT610NV1:
                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv1);
                break;
        case BCM47XX_BOARD_LINKSYS_WRT610NV2:
                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv2);
                break;
+        case BCM47XX_BOARD_LINKSYS_WRTSL54GS:
+                err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrtsl54gs);
+                break;
        case BCM47XX_BOARD_MOTOROLA_WE800G:
                err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_we800g);
diff --git a/arch/mips/bcm47xx/leds.c b/arch/mips/bcm47xx/leds.c
index 647d15527066..adcb547a91c3 100644
--- a/arch/mips/bcm47xx/leds.c
+++ b/arch/mips/bcm47xx/leds.c
@@ -292,6 +292,21 @@ bcm47xx_leds_linksys_wrt310nv1[] __initconst = {
 };
 static const struct gpio_led
+bcm47xx_leds_linksys_wrt54gsv1[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(5, "white", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "orange", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
+static const struct gpio_led
+bcm47xx_leds_linksys_wrt54g3gv2[] __initconst = {
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(2, "green", "3g", 0, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "blue", "3g", 0, LEDS_GPIO_DEFSTATE_OFF),
+};
+static const struct gpio_led
 bcm47xx_leds_linksys_wrt610nv1[] __initconst = {
        BCM47XX_GPIO_LED(0, "unk", "usb",  1, LEDS_GPIO_DEFSTATE_OFF),
        BCM47XX_GPIO_LED(1, "unk", "power",  0, LEDS_GPIO_DEFSTATE_OFF),
@@ -308,6 +323,15 @@ bcm47xx_leds_linksys_wrt610nv2[] __initconst = {
        BCM47XX_GPIO_LED(7, "unk", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
 };
+static const struct gpio_led
+bcm47xx_leds_linksys_wrtsl54gs[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
+        BCM47XX_GPIO_LED(2, "white", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "orange", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(7, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
+};
 /* Motorola */
 static const struct gpio_led
@@ -359,6 +383,14 @@ bcm47xx_leds_netgear_wnr834bv2[] __initconst = {
        BCM47XX_GPIO_LED(7, "unk", "connected", 0, LEDS_GPIO_DEFSTATE_OFF),
 };
+/* Siemens */
+static const struct gpio_led
+bcm47xx_leds_siemens_se505v2[] __initconst = {
+        BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(3, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
+        BCM47XX_GPIO_LED(5, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
+};
 /* SimpleTech */
 static const struct gpio_led
@@ -425,7 +457,11 @@ void __init bcm47xx_leds_register(void)
                bcm47xx_set_pdata(bcm47xx_leds_asus_wlhdd);
                break;
+        case BCM47XX_BOARD_BELKIN_F7D3301:
+        case BCM47XX_BOARD_BELKIN_F7D3302:
        case BCM47XX_BOARD_BELKIN_F7D4301:
+        case BCM47XX_BOARD_BELKIN_F7D4302:
+        case BCM47XX_BOARD_BELKIN_F7D4401:
                bcm47xx_set_pdata(bcm47xx_leds_belkin_f7d4301);
                break;
@@ -502,12 +538,21 @@ void __init bcm47xx_leds_register(void)
        case BCM47XX_BOARD_LINKSYS_WRT310NV1:
                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
                break;
+        case BCM47XX_BOARD_LINKSYS_WRT54G:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54gsv1);
+                break;
+        case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2);
+                break;
        case BCM47XX_BOARD_LINKSYS_WRT610NV1:
                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv1);
                break;
        case BCM47XX_BOARD_LINKSYS_WRT610NV2:
                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv2);
                break;
+        case BCM47XX_BOARD_LINKSYS_WRTSL54GS:
+                bcm47xx_set_pdata(bcm47xx_leds_linksys_wrtsl54gs);
+                break;
        case BCM47XX_BOARD_MOTOROLA_WE800G:
                bcm47xx_set_pdata(bcm47xx_leds_motorola_we800g);
@@ -529,6 +574,10 @@ void __init bcm47xx_leds_register(void)
                bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2);
                break;
+        case BCM47XX_BOARD_SIEMENS_SE505V2:
+                bcm47xx_set_pdata(bcm47xx_leds_siemens_se505v2);
+                break;
        case BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE:
                bcm47xx_set_pdata(bcm47xx_leds_simpletech_simpleshare);
                break;
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 025be218ea15..63a4b0e915dc 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -212,7 +212,7 @@ void __init plat_mem_setup(void)
 {
        struct cpuinfo_mips *c = &current_cpu_data;
-        if (c->cputype == CPU_74K) {
+        if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) {
                printk(KERN_INFO "bcm47xx: using bcma bus\n");
 #ifdef CONFIG_BCM47XX_BCMA
                bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
@@ -282,6 +282,7 @@ static int __init bcm47xx_register_bus_complete(void)
        }
        bcm47xx_buttons_register();
        bcm47xx_leds_register();
+        bcm47xx_workarounds();
        fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
        return 0;
diff --git a/arch/mips/bcm47xx/workarounds.c b/arch/mips/bcm47xx/workarounds.c
new file mode 100644
index 000000000000..e81ce4623070
--- /dev/null
+++ b/arch/mips/bcm47xx/workarounds.c
@@ -0,0 +1,31 @@
+#include "bcm47xx_private.h"
+#include <linux/gpio.h>
+#include <bcm47xx_board.h>
+#include <bcm47xx.h>
+static void __init bcm47xx_workarounds_netgear_wnr3500l(void)
+{
+        const int usb_power = 12;
+        int err;
+        err = gpio_request_one(usb_power, GPIOF_OUT_INIT_HIGH, "usb_power");
+        if (err)
+                pr_err("Failed to request USB power gpio: %d\n", err);
+        else
+                gpio_free(usb_power);
+}
+void __init bcm47xx_workarounds(void)
+{
+        enum bcm47xx_board board = bcm47xx_board_get();
+        switch (board) {
+        case BCM47XX_BOARD_NETGEAR_WNR3500L:
+                bcm47xx_workarounds_netgear_wnr3500l();
+                break;
+        default:
+                /* No workaround(s) needed */
+                break;
+        }
+}
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 1b1b8a89959b..fd4e76c00a42 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -299,14 +299,13 @@ static unsigned int detect_memory_size(void)
 void __init bcm63xx_cpu_init(void)
 {
        unsigned int tmp;
-        struct cpuinfo_mips *c = &current_cpu_data;
        unsigned int cpu = smp_processor_id();
        u32 chipid_reg;
        /* soc registers location depends on cpu type */
        chipid_reg = 0;
-        switch (c->cputype) {
+        switch (current_cpu_type()) {
        case CPU_BMIPS3300:
                if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
                        __cpu_name[cpu] = "Broadcom BCM6338";
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
deleted file mode 100644
index bac26b971c5e..000000000000
--- a/arch/mips/configs/db1000_defconfig
+++ /dev/null
@@ -1,359 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_MIPS_ALCHEMY=y
-CONFIG_MIPS_DB1000=y
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_HZ_100=y
-CONFIG_HZ=100
-CONFIG_PREEMPT_NONE=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE=""
-CONFIG_LOCALVERSION="-db1x00"
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_DEFAULT_HOSTNAME="db1x00"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_FHANDLE=y
-CONFIG_AUDIT=y
-CONFIG_TINY_RCU=y
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_NAMESPACES=y
-CONFIG_UTS_NS=y
-CONFIG_IPC_NS=y
-CONFIG_USER_NS=y
-CONFIG_PID_NS=y
-CONFIG_NET_NS=y
-CONFIG_SYSCTL=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_EMBEDDED=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PCI_QUIRKS=y
-CONFIG_SLAB=y
-CONFIG_SLABINFO=y
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_IOSCHED_NOOP=y
-CONFIG_DEFAULT_NOOP=y
-CONFIG_DEFAULT_IOSCHED="noop"
-CONFIG_FREEZER=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA=y
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
-CONFIG_BINFMT_ELF=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=y
-CONFIG_INET_TUNNEL=y
-CONFIG_INET_LRO=y
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_IPV6=y
-CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-CONFIG_INET6_XFRM_MODE_TUNNEL=y
-CONFIG_INET6_XFRM_MODE_BEET=y
-CONFIG_IPV6_SIT=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_STP=y
-CONFIG_GARP=y
-CONFIG_BRIDGE=y
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_VLAN_8021Q=y
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_LLC=y
-CONFIG_LLC2=y
-CONFIG_DNS_RESOLVER=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIBTUSB=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_I4=y
-CONFIG_MTD_CFI_I8=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_SCSI_MOD=y
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-CONFIG_SCSI_PROC_FS=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_ATA=y
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_ATA_SFF=y
-CONFIG_ATA_BMDMA=y
-CONFIG_PATA_HPT37X=y
-CONFIG_PATA_PCMCIA=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_DM=y
-CONFIG_FIREWIRE=y
-CONFIG_FIREWIRE_OHCI=y
-CONFIG_FIREWIRE_OHCI_DEBUG=y
-CONFIG_FIREWIRE_NET=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MIPS_AU1X00_ENET=y
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_3C589=y
-CONFIG_PCMCIA_PCNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_SYNC_TTY=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_MPPE=y
-CONFIG_PPPOE=y
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
-CONFIG_DEVKMEM=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_TTY_PRINTK=y
-CONFIG_DEVPORT=y
-CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
-CONFIG_FB=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_AU1100=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x16=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_HRTIMER=y
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_VMASTER=y
-CONFIG_SND_AC97_CODEC=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_SOC_AU1XAUDIO=y
-CONFIG_SND_SOC_AU1XAC97C=y
-CONFIG_SND_SOC_DB1000=y
-CONFIG_SND_SOC_AC97_CODEC=y
-CONFIG_AC97_BUS=y
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-CONFIG_HIDRAW=y
-CONFIG_USB_HID=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_DRV_AU1XXX=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT23=y
-CONFIG_EXT4_FS_XATTR=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_JBD2=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_GENERIC_ACL=y
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_JFFS2_CMODE_PRIORITY=y
-CONFIG_SQUASHFS=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_PNFS_FILE_LAYOUT=y
-CONFIG_PNFS_BLOCK=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFS_USE_KERNEL_DNS=y
-CONFIG_NFS_USE_NEW_IDMAPPER=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_1250=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="noirqdebug rootwait root=/dev/sda1 rootfstype=ext4 console=ttyS0,115200 video=au1100fb:panel:CRT_800x600_16"
-CONFIG_DEBUG_ZBOOT=y
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_SECURITYFS=y
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_ANSI_CPRNG=y
-CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC32=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_XZ_DEC=y
diff --git a/arch/mips/configs/db1235_defconfig b/arch/mips/configs/db1235_defconfig
deleted file mode 100644
index 28e49f226dc0..000000000000
--- a/arch/mips/configs/db1235_defconfig
+++ /dev/null
@@ -1,434 +0,0 @@
-CONFIG_MIPS_ALCHEMY=y
-CONFIG_MIPS_DB1235=y
-CONFIG_COMPACTION=y
-CONFIG_KSM=y
-CONFIG_HZ_100=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-db1235"
-CONFIG_KERNEL_LZMA=y
-CONFIG_DEFAULT_HOSTNAME="db1235"
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_FHANDLE=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_AUDIT=y
-CONFIG_AUDIT_LOGINUID_IMMUTABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_NAMESPACES=y
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_JUMP_LABEL=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_LDM_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_PCI=y
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_UNIX_DIAG=y
-CONFIG_XFRM_USER=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=y
-CONFIG_NET_IPGRE_DEMUX=y
-CONFIG_NET_IPGRE=y
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_ARPD=y
-CONFIG_SYN_COOKIES=y
-CONFIG_NET_IPVTI=y
-CONFIG_INET_AH=y
-CONFIG_INET_ESP=y
-CONFIG_INET_IPCOMP=y
-CONFIG_INET_UDP_DIAG=y
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_HSTCP=y
-CONFIG_TCP_CONG_HYBLA=y
-CONFIG_TCP_CONG_SCALABLE=y
-CONFIG_TCP_CONG_LP=y
-CONFIG_TCP_CONG_VENO=y
-CONFIG_TCP_CONG_YEAH=y
-CONFIG_TCP_CONG_ILLINOIS=y
-CONFIG_DEFAULT_HYBLA=y
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6_PRIVACY=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=y
-CONFIG_INET6_ESP=y
-CONFIG_INET6_IPCOMP=y
-CONFIG_IPV6_MIP6=y
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
-CONFIG_IPV6_SIT_6RD=y
-CONFIG_IPV6_TUNNEL=y
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=y
-CONFIG_NF_CONNTRACK_FTP=y
-CONFIG_NF_CONNTRACK_H323=y
-CONFIG_NF_CONNTRACK_IRC=y
-CONFIG_NF_CONNTRACK_NETBIOS_NS=y
-CONFIG_NF_CONNTRACK_SNMP=y
-CONFIG_NF_CONNTRACK_PPTP=y
-CONFIG_NF_CONNTRACK_SANE=y
-CONFIG_NF_CONNTRACK_SIP=y
-CONFIG_NF_CONNTRACK_TFTP=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NF_CT_NETLINK_TIMEOUT=y
-CONFIG_NF_CT_NETLINK_HELPER=y
-CONFIG_NETFILTER_NETLINK_QUEUE_CT=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_HMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_LED=y
-CONFIG_NETFILTER_XT_TARGET_LOG=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_TARGET_NFLOG=y
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
-CONFIG_NETFILTER_XT_TARGET_TEE=y
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_CPU=y
-CONFIG_NETFILTER_XT_MATCH_DCCP=y
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y
-CONFIG_NETFILTER_XT_MATCH_DSCP=y
-CONFIG_NETFILTER_XT_MATCH_ESP=y
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_HELPER=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_LIMIT=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
-CONFIG_NETFILTER_XT_MATCH_NFACCT=y
-CONFIG_NETFILTER_XT_MATCH_OSF=y
-CONFIG_NETFILTER_XT_MATCH_OWNER=y
-CONFIG_NETFILTER_XT_MATCH_POLICY=y
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_QUOTA=y
-CONFIG_NETFILTER_XT_MATCH_RATEEST=y
-CONFIG_NETFILTER_XT_MATCH_REALM=y
-CONFIG_NETFILTER_XT_MATCH_RECENT=y
-CONFIG_NETFILTER_XT_MATCH_SCTP=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
-CONFIG_NETFILTER_XT_MATCH_STRING=y
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
-CONFIG_NETFILTER_XT_MATCH_TIME=y
-CONFIG_NETFILTER_XT_MATCH_U32=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_RPFILTER=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_ULOG=y
-CONFIG_NF_NAT=y
-CONFIG_IP_NF_TARGET_MASQUERADE=y
-CONFIG_IP_NF_TARGET_NETMAP=y
-CONFIG_IP_NF_TARGET_REDIRECT=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_TARGET_CLUSTERIP=y
-CONFIG_IP_NF_TARGET_ECN=y
-CONFIG_IP_NF_TARGET_TTL=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
-CONFIG_NF_CONNTRACK_IPV6=y
-CONFIG_IP6_NF_IPTABLES=y
-CONFIG_IP6_NF_MATCH_AH=y
-CONFIG_IP6_NF_MATCH_EUI64=y
-CONFIG_IP6_NF_MATCH_FRAG=y
-CONFIG_IP6_NF_MATCH_OPTS=y
-CONFIG_IP6_NF_MATCH_HL=y
-CONFIG_IP6_NF_MATCH_IPV6HEADER=y
-CONFIG_IP6_NF_MATCH_MH=y
-CONFIG_IP6_NF_MATCH_RPFILTER=y
-CONFIG_IP6_NF_MATCH_RT=y
-CONFIG_IP6_NF_TARGET_HL=y
-CONFIG_IP6_NF_FILTER=y
-CONFIG_IP6_NF_TARGET_REJECT=y
-CONFIG_IP6_NF_MANGLE=y
-CONFIG_IP6_NF_RAW=y
-CONFIG_BRIDGE_NF_EBTABLES=y
-CONFIG_BRIDGE_EBT_BROUTE=y
-CONFIG_BRIDGE_EBT_T_FILTER=y
-CONFIG_BRIDGE_EBT_T_NAT=y
-CONFIG_BRIDGE_EBT_802_3=y
-CONFIG_BRIDGE_EBT_AMONG=y
-CONFIG_BRIDGE_EBT_ARP=y
-CONFIG_BRIDGE_EBT_IP=y
-CONFIG_BRIDGE_EBT_IP6=y
-CONFIG_BRIDGE_EBT_LIMIT=y
-CONFIG_BRIDGE_EBT_MARK=y
-CONFIG_BRIDGE_EBT_PKTTYPE=y
-CONFIG_BRIDGE_EBT_STP=y
-CONFIG_BRIDGE_EBT_VLAN=y
-CONFIG_BRIDGE_EBT_ARPREPLY=y
-CONFIG_BRIDGE_EBT_DNAT=y
-CONFIG_BRIDGE_EBT_MARK_T=y
-CONFIG_BRIDGE_EBT_REDIRECT=y
-CONFIG_BRIDGE_EBT_SNAT=y
-CONFIG_BRIDGE_EBT_LOG=y
-CONFIG_BRIDGE_EBT_NFLOG=y
-CONFIG_L2TP=y
-CONFIG_L2TP_V3=y
-CONFIG_L2TP_IP=y
-CONFIG_L2TP_ETH=y
-CONFIG_BRIDGE=y
-CONFIG_VLAN_8021Q=y
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_LLC2=y
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=y
-CONFIG_NET_SCH_HTB=y
-CONFIG_NET_SCH_HFSC=y
-CONFIG_NET_SCH_PRIO=y
-CONFIG_NET_SCH_MULTIQ=y
-CONFIG_NET_SCH_RED=y
-CONFIG_NET_SCH_SFB=y
-CONFIG_NET_SCH_SFQ=y
-CONFIG_NET_SCH_TEQL=y
-CONFIG_NET_SCH_TBF=y
-CONFIG_NET_SCH_GRED=y
-CONFIG_NET_SCH_DSMARK=y
-CONFIG_NET_SCH_NETEM=y
-CONFIG_NET_SCH_DRR=y
-CONFIG_NET_SCH_MQPRIO=y
-CONFIG_NET_SCH_CHOKE=y
-CONFIG_NET_SCH_QFQ=y
-CONFIG_NET_SCH_CODEL=y
-CONFIG_NET_SCH_FQ_CODEL=y
-CONFIG_NET_SCH_INGRESS=y
-CONFIG_NET_SCH_PLUG=y
-CONFIG_NET_CLS_BASIC=y
-CONFIG_NET_CLS_TCINDEX=y
-CONFIG_NET_CLS_ROUTE4=y
-CONFIG_NET_CLS_FW=y
-CONFIG_NET_CLS_U32=y
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=y
-CONFIG_NET_CLS_RSVP6=y
-CONFIG_NET_CLS_FLOW=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_CMP=y
-CONFIG_NET_EMATCH_NBYTE=y
-CONFIG_NET_EMATCH_U32=y
-CONFIG_NET_EMATCH_META=y
-CONFIG_NET_EMATCH_TEXT=y
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=y
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=y
-CONFIG_NET_ACT_NAT=y
-CONFIG_NET_ACT_PEDIT=y
-CONFIG_NET_ACT_SIMP=y
-CONFIG_NET_ACT_SKBEDIT=y
-CONFIG_NET_ACT_CSUM=y
-CONFIG_NET_CLS_IND=y
-CONFIG_BT=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-CONFIG_BT_HCIBTUSB=y
-CONFIG_CFG80211=y
-CONFIG_CFG80211_CERTIFICATION_ONUS=y
-CONFIG_CFG80211_WEXT=y
-CONFIG_MAC80211=y
-CONFIG_MAC80211_LEDS=y
-CONFIG_RFKILL=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE_AU1XXX=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_ATA=y
-CONFIG_PATA_HPT37X=y
-CONFIG_PATA_PCMCIA=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_NETDEVICES=y
-CONFIG_MIPS_AU1X00_ENET=y
-CONFIG_SMC91X=y
-CONFIG_SMSC911X=y
-CONFIG_AMD_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_RT2X00=y
-CONFIG_RT73USB=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_WM97XX=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_TTY_PRINTK=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_AU1550=y
-CONFIG_SPI=y
-CONFIG_SPI_AU1550=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_SENSORS_ADM1025=y
-CONFIG_SENSORS_LM70=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_HRTIMER=y
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_AU1XPSC=y
-CONFIG_SND_SOC_DB1200=y
-CONFIG_HIDRAW=y
-CONFIG_UHID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB=y
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_AU1X=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AU1XXX=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_XFS_FS=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_CMODE_FAVOURLZO=y
-CONFIG_SQUASHFS=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_CODEPAGE_1250=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_SECURITYFS=y
-CONFIG_CRYPTO_USER=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_CCM=y
-CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_LRW=y
-CONFIG_CRYPTO_PCBC=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_XCBC=y
-CONFIG_CRYPTO_VMAC=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_RMD128=y
-CONFIG_CRYPTO_RMD160=y
-CONFIG_CRYPTO_RMD256=y
-CONFIG_CRYPTO_RMD320=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_TGR192=y
-CONFIG_CRYPTO_WP512=y
-CONFIG_CRYPTO_ANUBIS=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_CAMELLIA=y
-CONFIG_CRYPTO_CAST5=y
-CONFIG_CRYPTO_CAST6=y
-CONFIG_CRYPTO_FCRYPT=y
-CONFIG_CRYPTO_KHAZAD=y
-CONFIG_CRYPTO_SALSA20=y
-CONFIG_CRYPTO_SEED=y
-CONFIG_CRYPTO_SERPENT=y
-CONFIG_CRYPTO_TEA=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_ZLIB=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=y
diff --git a/arch/mips/configs/db1xxx_defconfig b/arch/mips/configs/db1xxx_defconfig
new file mode 100644
index 000000000000..c99b6eeda90b
--- /dev/null
+++ b/arch/mips/configs/db1xxx_defconfig
@@ -0,0 +1,245 @@
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_DB1XXX=y
+CONFIG_CMA=y
+CONFIG_CMA_DEBUG=y
+CONFIG_HZ_100=y
+CONFIG_LOCALVERSION="-db1xxx"
+CONFIG_KERNEL_XZ=y
+CONFIG_DEFAULT_HOSTNAME="db1xxx"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_DEFAULT_NOOP=y
+CONFIG_PCI=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_VENO=y
+CONFIG_DEFAULT_VENO=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
+CONFIG_IPV6_VTI=y
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_IPV6_GRE=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_BRIDGE=y
+CONFIG_NETLINK_MMAP=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_IRDA=y
+CONFIG_IRLAN=y
+CONFIG_IRCOMM=y
+CONFIG_IRDA_ULTRA=y
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+CONFIG_AU1000_FIR=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIBTUSB=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC_BCH=y
+CONFIG_MTD_NAND_AU1550=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+CONFIG_PATA_HPT37X=y
+CONFIG_PATA_HPT3X2N=y
+CONFIG_PATA_PCMCIA=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_NLMON=y
+CONFIG_PCMCIA_3C589=y
+CONFIG_MIPS_AU1X00_ENET=y
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+CONFIG_AMD_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_TOUCHSCREEN_WM97XX=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_TTY_PRINTK=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_AU1550=y
+CONFIG_SPI=y
+CONFIG_SPI_AU1550=y
+CONFIG_SPI_GPIO=y
+CONFIG_SENSORS_ADM1025=y
+CONFIG_SENSORS_LM70=y
+CONFIG_FB=y
+CONFIG_FB_AU1100=y
+CONFIG_FB_AU1200=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_HRTIMER=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=1
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AU1XPSC=y
+CONFIG_SND_SOC_AU1XAUDIO=y
+CONFIG_SND_SOC_DB1000=y
+CONFIG_SND_SOC_DB1200=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_LOGITECH_DJ=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_OTG=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_CLKGATE=y
+CONFIG_SDIO_UART=y
+CONFIG_MMC_AU1X=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_XFS_FS=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_FANOTIFY=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_FILE_DIRECT=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="local"
+CONFIG_NFS_V4_1_MIGRATION=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_SECURITYFS=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRC32_SLICEBY4=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig
new file mode 100644
index 000000000000..ea1761f0f917
--- /dev/null
+++ b/arch/mips/configs/loongson3_defconfig
@@ -0,0 +1,362 @@
+CONFIG_MACH_LOONGSON=y
+CONFIG_SWIOTLB=y
+CONFIG_LEMOTE_MACH3A=y
+CONFIG_CPU_LOONGSON3=y
+CONFIG_64BIT=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_KSM=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_HZ_256=y
+CONFIG_PREEMPT=y
+CONFIG_KEXEC=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CPUSETS=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_BLK_CGROUP=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_IOSCHED_DEADLINE=m
+CONFIG_CFQ_GROUP_IOSCHED=y
+CONFIG_PCI=y
+CONFIG_HT_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+# CONFIG_PCIEAER is not set
+CONFIG_PCIEASPM_PERFORMANCE=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_SHPC=m
+CONFIG_BINFMT_MISC=m
+CONFIG_MIPS32_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_IP_VS=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_IP_SCTP=m
+CONFIG_L2TP=m
+CONFIG_BRIDGE=m
+CONFIG_CFG80211=m
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=m
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=m
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_ISCSI_TCP=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_MM=y
+CONFIG_MEGARAID_MAILBOX=y
+CONFIG_MEGARAID_LEGACY=y
+CONFIG_MEGARAID_SAS=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_PATA_ATIIXP=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_ISCSI_TARGET=m
+CONFIG_NETDEVICES=y
+CONFIG_TUN=m
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_IGB=y
+CONFIG_IXGB=y
+CONFIG_IXGBE=y
+# CONFIG_NET_VENDOR_I825XX is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+CONFIG_8139CP=m
+CONFIG_8139TOO=m
+CONFIG_R8169=y
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_ATH_CARDS=m
+CONFIG_ATH9K=m
+CONFIG_HOSTAP=m
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_MOUSE_PS2_SENTELIC=y
+CONFIG_MOUSE_SERIAL=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=m
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_RAW=m
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=16
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_HW_RANDOM=y
+CONFIG_RAW_DRIVER=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_PIIX4=y
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM93=m
+CONFIG_SENSORS_W83627HF=m
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_DRM=y
+CONFIG_DRM_RADEON=y
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB_RADEON=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_PLATFORM=m
+CONFIG_BACKLIGHT_GENERIC=m
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+# CONFIG_SND_ISA is not set
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_CONEXANT=m
+# CONFIG_SND_USB is not set
+CONFIG_HID_A4TECH=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_UHCI_HCD=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_CMOS=y
+CONFIG_DMADEVICES=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_QUOTA=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=936
+CONFIG_FAT_DEFAULT_IOCHARSET="gb2312"
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=m
+CONFIG_NFSD=m
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_CIFS=m
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_FRAME_WARN=1024
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_RCU_CPU_STALL_VERBOSE is not set
+# CONFIG_FTRACE is not set
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_PATH=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_DEFLATE=m
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index ce1d3eeeb737..b745b6a9f322 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -1,7 +1,9 @@
 CONFIG_MIPS_MALTA=y
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R2=y
+CONFIG_PAGE_SIZE_16KB=y
 CONFIG_MIPS_MT_SMP=y
+CONFIG_NR_CPUS=8
 CONFIG_HZ_100=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
@@ -42,7 +44,6 @@ CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_IPV6_OPTIMISTIC_DAD=y
@@ -68,7 +69,6 @@ CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
 CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_TPROXY=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
@@ -125,7 +125,6 @@ CONFIG_IP_VS_SH=m
 CONFIG_IP_VS_SED=m
 CONFIG_IP_VS_NQ=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
@@ -185,7 +184,6 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_PHONET=m
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
@@ -226,9 +224,9 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
 CONFIG_MAC80211_MESH=y
 CONFIG_RFKILL=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 CONFIG_CONNECTOR=m
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_OOPS=m
 CONFIG_MTD_CFI=y
@@ -328,7 +326,6 @@ CONFIG_LIBERTAS=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO_I8042 is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_HWMON is not set
diff --git a/arch/mips/configs/malta_kvm_defconfig b/arch/mips/configs/malta_kvm_defconfig
index 341bb47204d6..4f7d952d8517 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -3,6 +3,7 @@ CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R2=y
 CONFIG_PAGE_SIZE_16KB=y
 CONFIG_MIPS_MT_SMP=y
+CONFIG_NR_CPUS=8
 CONFIG_HZ_100=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
@@ -44,7 +45,6 @@ CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_IPV6_OPTIMISTIC_DAD=y
@@ -70,7 +70,6 @@ CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
 CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_TPROXY=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
@@ -127,7 +126,6 @@ CONFIG_IP_VS_SH=m
 CONFIG_IP_VS_SED=m
 CONFIG_IP_VS_NQ=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
@@ -187,7 +185,6 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_PHONET=m
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
@@ -228,9 +225,9 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
 CONFIG_MAC80211_MESH=y
 CONFIG_RFKILL=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 CONFIG_CONNECTOR=m
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_OOPS=m
 CONFIG_MTD_CFI=y
@@ -300,6 +297,7 @@ CONFIG_IFB=m
 CONFIG_MACVLAN=m
 CONFIG_TUN=m
 CONFIG_VETH=m
+CONFIG_VHOST_NET=m
 CONFIG_PCNET32=y
 CONFIG_CHELSIO_T3=m
 CONFIG_AX88796=m
@@ -329,7 +327,6 @@ CONFIG_LIBERTAS=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO_I8042 is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_HWMON is not set
@@ -453,4 +450,3 @@ CONFIG_VIRTUALIZATION=y
 CONFIG_KVM=m
 CONFIG_KVM_MIPS_DYN_TRANS=y
 CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS=y
-CONFIG_VHOST_NET=m
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig b/arch/mips/configs/malta_kvm_guest_defconfig
index 2b8558b71080..e36681c24ddc 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -44,7 +44,6 @@ CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_IPV6_OPTIMISTIC_DAD=y
@@ -70,7 +69,6 @@ CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
 CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_TPROXY=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
@@ -127,7 +125,6 @@ CONFIG_IP_VS_SH=m
 CONFIG_IP_VS_SED=m
 CONFIG_IP_VS_NQ=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
@@ -187,7 +184,6 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_PHONET=m
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
@@ -228,9 +224,9 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
 CONFIG_MAC80211_MESH=y
 CONFIG_RFKILL=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 CONFIG_CONNECTOR=m
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_OOPS=m
 CONFIG_MTD_CFI=y
@@ -331,7 +327,6 @@ CONFIG_LIBERTAS=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO_I8042 is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_HWMON is not set
diff --git a/arch/mips/configs/maltaaprp_defconfig b/arch/mips/configs/maltaaprp_defconfig
index 93057a760dfa..fb042ce86b4b 100644
--- a/arch/mips/configs/maltaaprp_defconfig
+++ b/arch/mips/configs/maltaaprp_defconfig
@@ -44,7 +44,6 @@ CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 # CONFIG_INET_LRO is not set
-CONFIG_IPV6_PRIVACY=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
@@ -55,7 +54,6 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
 CONFIG_NET_SCH_HTB=m
@@ -80,6 +78,7 @@ CONFIG_NET_CLS_ACT=y
 CONFIG_NET_ACT_POLICE=y
 CONFIG_NET_CLS_IND=y
 # CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_IDE=y
diff --git a/arch/mips/configs/maltasmtc_defconfig b/arch/mips/configs/maltasmtc_defconfig
index 4e54b75d89be..eb316447588c 100644
--- a/arch/mips/configs/maltasmtc_defconfig
+++ b/arch/mips/configs/maltasmtc_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS_MALTA=y
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R2=y
+CONFIG_PAGE_SIZE_16KB=y
 CONFIG_MIPS_MT_SMTC=y
 # CONFIG_MIPS_MT_FPAFF is not set
 CONFIG_NR_CPUS=9
@@ -45,7 +46,6 @@ CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 # CONFIG_INET_LRO is not set
-CONFIG_IPV6_PRIVACY=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
@@ -56,7 +56,6 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
 CONFIG_NET_SCH_HTB=m
@@ -81,6 +80,7 @@ CONFIG_NET_CLS_ACT=y
 CONFIG_NET_ACT_POLICE=y
 CONFIG_NET_CLS_IND=y
 # CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_IDE=y
diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig
index d75931850392..10ef3bed5f43 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -1,10 +1,11 @@
 CONFIG_MIPS_MALTA=y
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R2=y
+CONFIG_PAGE_SIZE_16KB=y
 CONFIG_MIPS_MT_SMP=y
 CONFIG_SCHED_SMT=y
 CONFIG_MIPS_CMP=y
-CONFIG_NR_CPUS=2
+CONFIG_NR_CPUS=8
 CONFIG_HZ_100=y
 CONFIG_LOCALVERSION="cmp"
 CONFIG_SYSVIPC=y
@@ -47,7 +48,6 @@ CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 # CONFIG_INET_LRO is not set
-CONFIG_IPV6_PRIVACY=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
@@ -82,6 +82,7 @@ CONFIG_NET_CLS_ACT=y
 CONFIG_NET_ACT_POLICE=y
 CONFIG_NET_CLS_IND=y
 # CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_IDE=y
diff --git a/arch/mips/configs/maltasmvp_eva_defconfig b/arch/mips/configs/maltasmvp_eva_defconfig
new file mode 100644
index 000000000000..2d3002cba102
--- /dev/null
+++ b/arch/mips/configs/maltasmvp_eva_defconfig
@@ -0,0 +1,200 @@
+CONFIG_MIPS_MALTA=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPS32_3_5_FEATURES=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_MIPS_MT_SMP=y
+CONFIG_SCHED_SMT=y
+CONFIG_MIPS_CMP=y
+CONFIG_NR_CPUS=8
+CONFIG_HZ_100=y
+CONFIG_LOCALVERSION="cmp"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PCI=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=m
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+# CONFIG_INET_LRO is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=m
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+CONFIG_NET_CLS_IND=y
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_IDE=y
+# CONFIG_IDE_PROC_FS is not set
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+CONFIG_BLK_DEV_GENERIC=y
+CONFIG_BLK_DEV_PIIX=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+CONFIG_PCNET32=y
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_VT is not set
+CONFIG_LEGACY_PTY_COUNT=4
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_HW_RANDOM=y
+# CONFIG_HWMON is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_MATROX=y
+CONFIG_FB_MATROX_G=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_IDE_DISK=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_CMOS=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_XFS_FS=y
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_QUOTA=y
+CONFIG_QFMT_V2=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_CIFS=m
+CONFIG_CIFS_WEAK_PW_HASH=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_FTRACE is not set
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/configs/maltaup_defconfig b/arch/mips/configs/maltaup_defconfig
index 9868fc9c1133..62344648eb7a 100644
--- a/arch/mips/configs/maltaup_defconfig
+++ b/arch/mips/configs/maltaup_defconfig
@@ -43,7 +43,6 @@ CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 # CONFIG_INET_LRO is not set
-CONFIG_IPV6_PRIVACY=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
@@ -54,7 +53,6 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
 CONFIG_NET_SCH_HTB=m
@@ -79,6 +77,7 @@ CONFIG_NET_CLS_ACT=y
 CONFIG_NET_ACT_POLICE=y
 CONFIG_NET_CLS_IND=y
 # CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_IDE=y
diff --git a/arch/mips/include/asm/asm-eva.h b/arch/mips/include/asm/asm-eva.h
new file mode 100644
index 000000000000..e41c56e375b1
--- /dev/null
+++ b/arch/mips/include/asm/asm-eva.h
@@ -0,0 +1,135 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 Imagination Technologies Ltd.
+ *
+ */
+#ifndef __ASM_ASM_EVA_H
+#define __ASM_ASM_EVA_H
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_EVA
+#define __BUILD_EVA_INSN(insn, reg, addr)                               \
+                                "       .set    push\n"                 \
+                                "       .set    mips0\n"                \
+                                "       .set    eva\n"                  \
+                                "       "insn" "reg", "addr "\n"        \
+                                "       .set    pop\n"
+#define user_cache(op, base)            __BUILD_EVA_INSN("cachee", op, base)
+#define user_ll(reg, addr)              __BUILD_EVA_INSN("lle", reg, addr)
+#define user_sc(reg, addr)              __BUILD_EVA_INSN("sce", reg, addr)
+#define user_lw(reg, addr)              __BUILD_EVA_INSN("lwe", reg, addr)
+#define user_lwl(reg, addr)             __BUILD_EVA_INSN("lwle", reg, addr)
+#define user_lwr(reg, addr)             __BUILD_EVA_INSN("lwre", reg, addr)
+#define user_lh(reg, addr)              __BUILD_EVA_INSN("lhe", reg, addr)
+#define user_lb(reg, addr)              __BUILD_EVA_INSN("lbe", reg, addr)
+#define user_lbu(reg, addr)             __BUILD_EVA_INSN("lbue", reg, addr)
+/* No 64-bit EVA instruction for loading double words */
+#define user_ld(reg, addr)              user_lw(reg, addr)
+#define user_sw(reg, addr)              __BUILD_EVA_INSN("swe", reg, addr)
+#define user_swl(reg, addr)             __BUILD_EVA_INSN("swle", reg, addr)
+#define user_swr(reg, addr)             __BUILD_EVA_INSN("swre", reg, addr)
+#define user_sh(reg, addr)              __BUILD_EVA_INSN("she", reg, addr)
+#define user_sb(reg, addr)              __BUILD_EVA_INSN("sbe", reg, addr)
+/* No 64-bit EVA instruction for storing double words */
+#define user_sd(reg, addr)              user_sw(reg, addr)
+#else
+#define user_cache(op, base)            "cache " op ", " base "\n"
+#define user_ll(reg, addr)              "ll " reg ", " addr "\n"
+#define user_sc(reg, addr)              "sc " reg ", " addr "\n"
+#define user_lw(reg, addr)              "lw " reg ", " addr "\n"
+#define user_lwl(reg, addr)             "lwl " reg ", " addr "\n"
+#define user_lwr(reg, addr)             "lwr " reg ", " addr "\n"
+#define user_lh(reg, addr)              "lh " reg ", " addr "\n"
+#define user_lb(reg, addr)              "lb " reg ", " addr "\n"
+#define user_lbu(reg, addr)             "lbu " reg ", " addr "\n"
+#define user_sw(reg, addr)              "sw " reg ", " addr "\n"
+#define user_swl(reg, addr)             "swl " reg ", " addr "\n"
+#define user_swr(reg, addr)             "swr " reg ", " addr "\n"
+#define user_sh(reg, addr)              "sh " reg ", " addr "\n"
+#define user_sb(reg, addr)              "sb " reg ", " addr "\n"
+#ifdef CONFIG_32BIT
+/*
+ * No 'sd' or 'ld' instructions in 32-bit but the code will
+ * do the correct thing
+ */
+#define user_sd(reg, addr)              user_sw(reg, addr)
+#define user_ld(reg, addr)              user_lw(reg, addr)
+#else
+#define user_sd(reg, addr)              "sd " reg", " addr "\n"
+#define user_ld(reg, addr)              "ld " reg", " addr "\n"
+#endif /* CONFIG_32BIT */
+#endif /* CONFIG_EVA */
+#else /* __ASSEMBLY__ */
+#ifdef CONFIG_EVA
+#define __BUILD_EVA_INSN(insn, reg, addr)                       \
+                                .set    push;                   \
+                                .set    mips0;                  \
+                                .set    eva;                    \
+                                insn reg, addr;                 \
+                                .set    pop;
+#define user_cache(op, base)            __BUILD_EVA_INSN(cachee, op, base)
+#define user_ll(reg, addr)              __BUILD_EVA_INSN(lle, reg, addr)
+#define user_sc(reg, addr)              __BUILD_EVA_INSN(sce, reg, addr)
+#define user_lw(reg, addr)              __BUILD_EVA_INSN(lwe, reg, addr)
+#define user_lwl(reg, addr)             __BUILD_EVA_INSN(lwle, reg, addr)
+#define user_lwr(reg, addr)             __BUILD_EVA_INSN(lwre, reg, addr)
+#define user_lh(reg, addr)              __BUILD_EVA_INSN(lhe, reg, addr)
+#define user_lb(reg, addr)              __BUILD_EVA_INSN(lbe, reg, addr)
+#define user_lbu(reg, addr)             __BUILD_EVA_INSN(lbue, reg, addr)
+/* No 64-bit EVA instruction for loading double words */
+#define user_ld(reg, addr)              user_lw(reg, addr)
+#define user_sw(reg, addr)              __BUILD_EVA_INSN(swe, reg, addr)
+#define user_swl(reg, addr)             __BUILD_EVA_INSN(swle, reg, addr)
+#define user_swr(reg, addr)             __BUILD_EVA_INSN(swre, reg, addr)
+#define user_sh(reg, addr)              __BUILD_EVA_INSN(she, reg, addr)
+#define user_sb(reg, addr)              __BUILD_EVA_INSN(sbe, reg, addr)
+/* No 64-bit EVA instruction for loading double words */
+#define user_sd(reg, addr)              user_sw(reg, addr)
+#else
+#define user_cache(op, base)            cache op, base
+#define user_ll(reg, addr)              ll reg, addr
+#define user_sc(reg, addr)              sc reg, addr
+#define user_lw(reg, addr)              lw reg, addr
+#define user_lwl(reg, addr)             lwl reg, addr
+#define user_lwr(reg, addr)             lwr reg, addr
+#define user_lh(reg, addr)              lh reg, addr
+#define user_lb(reg, addr)              lb reg, addr
+#define user_lbu(reg, addr)             lbu reg, addr
+#define user_sw(reg, addr)              sw reg, addr
+#define user_swl(reg, addr)             swl reg, addr
+#define user_swr(reg, addr)             swr reg, addr
+#define user_sh(reg, addr)              sh reg, addr
+#define user_sb(reg, addr)              sb reg, addr
+#ifdef CONFIG_32BIT
+/*
+ * No 'sd' or 'ld' instructions in 32-bit but the code will
+ * do the correct thing
+ */
+#define user_sd(reg, addr)              user_sw(reg, addr)
+#define user_ld(reg, addr)              user_lw(reg, addr)
+#else
+#define user_sd(reg, addr)              sd reg, addr
+#define user_ld(reg, addr)              ld reg, addr
+#endif /* CONFIG_32BIT */
+#endif /* CONFIG_EVA */
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ASM_EVA_H */
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 879691d194af..7c26b28bf252 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -18,6 +18,7 @@
 #define __ASM_ASM_H
 #include <asm/sgidefs.h>
+#include <asm/asm-eva.h>
 #ifndef CAT
 #ifdef __STDC__
@@ -145,19 +146,27 @@ symbol		=	value
 #define PREF(hint,addr)                                 \
                .set    push;                           \
-                .set    mips4;                          \
+                .set    arch=r5000;                     \
                pref    hint, addr;                     \
                .set    pop
+#define PREFE(hint, addr)                               \
+                .set    push;                           \
+                .set    mips0;                          \
+                .set    eva;                            \
+                prefe   hint, addr;                     \
+                .set    pop
 #define PREFX(hint,addr)                                \
                .set    push;                           \
-                .set    mips4;                          \
+                .set    arch=r5000;                     \
                prefx   hint, addr;                     \
                .set    pop
 #else /* !CONFIG_CPU_HAS_PREFETCH */
 #define PREF(hint, addr)
+#define PREFE(hint, addr)
 #define PREFX(hint, addr)
 #endif /* !CONFIG_CPU_HAS_PREFETCH */
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index 70e1f176f123..e38c2811d4e2 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -14,75 +14,75 @@
        .macro  fpu_save_single thread tmp=t0
        cfc1    \tmp,  fcr31
-        swc1    $f0,  THREAD_FPR0(\thread)
+        swc1    $f0,  THREAD_FPR0_LS64(\thread)
-        swc1    $f1,  THREAD_FPR1(\thread)
+        swc1    $f1,  THREAD_FPR1_LS64(\thread)
-        swc1    $f2,  THREAD_FPR2(\thread)
+        swc1    $f2,  THREAD_FPR2_LS64(\thread)
-        swc1    $f3,  THREAD_FPR3(\thread)
+        swc1    $f3,  THREAD_FPR3_LS64(\thread)
-        swc1    $f4,  THREAD_FPR4(\thread)
+        swc1    $f4,  THREAD_FPR4_LS64(\thread)
-        swc1    $f5,  THREAD_FPR5(\thread)
+        swc1    $f5,  THREAD_FPR5_LS64(\thread)
-        swc1    $f6,  THREAD_FPR6(\thread)
+        swc1    $f6,  THREAD_FPR6_LS64(\thread)
-        swc1    $f7,  THREAD_FPR7(\thread)
+        swc1    $f7,  THREAD_FPR7_LS64(\thread)
-        swc1    $f8,  THREAD_FPR8(\thread)
+        swc1    $f8,  THREAD_FPR8_LS64(\thread)
-        swc1    $f9,  THREAD_FPR9(\thread)
+        swc1    $f9,  THREAD_FPR9_LS64(\thread)
-        swc1    $f10, THREAD_FPR10(\thread)
+        swc1    $f10, THREAD_FPR10_LS64(\thread)
-        swc1    $f11, THREAD_FPR11(\thread)
+        swc1    $f11, THREAD_FPR11_LS64(\thread)
-        swc1    $f12, THREAD_FPR12(\thread)
+        swc1    $f12, THREAD_FPR12_LS64(\thread)
-        swc1    $f13, THREAD_FPR13(\thread)
+        swc1    $f13, THREAD_FPR13_LS64(\thread)
-        swc1    $f14, THREAD_FPR14(\thread)
+        swc1    $f14, THREAD_FPR14_LS64(\thread)
-        swc1    $f15, THREAD_FPR15(\thread)
+        swc1    $f15, THREAD_FPR15_LS64(\thread)
-        swc1    $f16, THREAD_FPR16(\thread)
+        swc1    $f16, THREAD_FPR16_LS64(\thread)
-        swc1    $f17, THREAD_FPR17(\thread)
+        swc1    $f17, THREAD_FPR17_LS64(\thread)
-        swc1    $f18, THREAD_FPR18(\thread)
+        swc1    $f18, THREAD_FPR18_LS64(\thread)
-        swc1    $f19, THREAD_FPR19(\thread)
+        swc1    $f19, THREAD_FPR19_LS64(\thread)
-        swc1    $f20, THREAD_FPR20(\thread)
+        swc1    $f20, THREAD_FPR20_LS64(\thread)
-        swc1    $f21, THREAD_FPR21(\thread)
+        swc1    $f21, THREAD_FPR21_LS64(\thread)
-        swc1    $f22, THREAD_FPR22(\thread)
+        swc1    $f22, THREAD_FPR22_LS64(\thread)
-        swc1    $f23, THREAD_FPR23(\thread)
+        swc1    $f23, THREAD_FPR23_LS64(\thread)
-        swc1    $f24, THREAD_FPR24(\thread)
+        swc1    $f24, THREAD_FPR24_LS64(\thread)
-        swc1    $f25, THREAD_FPR25(\thread)
+        swc1    $f25, THREAD_FPR25_LS64(\thread)
-        swc1    $f26, THREAD_FPR26(\thread)
+        swc1    $f26, THREAD_FPR26_LS64(\thread)
-        swc1    $f27, THREAD_FPR27(\thread)
+        swc1    $f27, THREAD_FPR27_LS64(\thread)
-        swc1    $f28, THREAD_FPR28(\thread)
+        swc1    $f28, THREAD_FPR28_LS64(\thread)
-        swc1    $f29, THREAD_FPR29(\thread)
+        swc1    $f29, THREAD_FPR29_LS64(\thread)
-        swc1    $f30, THREAD_FPR30(\thread)
+        swc1    $f30, THREAD_FPR30_LS64(\thread)
-        swc1    $f31, THREAD_FPR31(\thread)
+        swc1    $f31, THREAD_FPR31_LS64(\thread)
        sw      \tmp, THREAD_FCR31(\thread)
        .endm
        .macro  fpu_restore_single thread tmp=t0
        lw      \tmp, THREAD_FCR31(\thread)
-        lwc1    $f0,  THREAD_FPR0(\thread)
+        lwc1    $f0,  THREAD_FPR0_LS64(\thread)
-        lwc1    $f1,  THREAD_FPR1(\thread)
+        lwc1    $f1,  THREAD_FPR1_LS64(\thread)
-        lwc1    $f2,  THREAD_FPR2(\thread)
+        lwc1    $f2,  THREAD_FPR2_LS64(\thread)
-        lwc1    $f3,  THREAD_FPR3(\thread)
+        lwc1    $f3,  THREAD_FPR3_LS64(\thread)
-        lwc1    $f4,  THREAD_FPR4(\thread)
+        lwc1    $f4,  THREAD_FPR4_LS64(\thread)
-        lwc1    $f5,  THREAD_FPR5(\thread)
+        lwc1    $f5,  THREAD_FPR5_LS64(\thread)
-        lwc1    $f6,  THREAD_FPR6(\thread)
+        lwc1    $f6,  THREAD_FPR6_LS64(\thread)
-        lwc1    $f7,  THREAD_FPR7(\thread)
+        lwc1    $f7,  THREAD_FPR7_LS64(\thread)
-        lwc1    $f8,  THREAD_FPR8(\thread)
+        lwc1    $f8,  THREAD_FPR8_LS64(\thread)
-        lwc1    $f9,  THREAD_FPR9(\thread)
+        lwc1    $f9,  THREAD_FPR9_LS64(\thread)
-        lwc1    $f10, THREAD_FPR10(\thread)
+        lwc1    $f10, THREAD_FPR10_LS64(\thread)
-        lwc1    $f11, THREAD_FPR11(\thread)
+        lwc1    $f11, THREAD_FPR11_LS64(\thread)
-        lwc1    $f12, THREAD_FPR12(\thread)
+        lwc1    $f12, THREAD_FPR12_LS64(\thread)
-        lwc1    $f13, THREAD_FPR13(\thread)
+        lwc1    $f13, THREAD_FPR13_LS64(\thread)
-        lwc1    $f14, THREAD_FPR14(\thread)
+        lwc1    $f14, THREAD_FPR14_LS64(\thread)
-        lwc1    $f15, THREAD_FPR15(\thread)
+        lwc1    $f15, THREAD_FPR15_LS64(\thread)
-        lwc1    $f16, THREAD_FPR16(\thread)
+        lwc1    $f16, THREAD_FPR16_LS64(\thread)
-        lwc1    $f17, THREAD_FPR17(\thread)
+        lwc1    $f17, THREAD_FPR17_LS64(\thread)
-        lwc1    $f18, THREAD_FPR18(\thread)
+        lwc1    $f18, THREAD_FPR18_LS64(\thread)
-        lwc1    $f19, THREAD_FPR19(\thread)
+        lwc1    $f19, THREAD_FPR19_LS64(\thread)
-        lwc1    $f20, THREAD_FPR20(\thread)
+        lwc1    $f20, THREAD_FPR20_LS64(\thread)
-        lwc1    $f21, THREAD_FPR21(\thread)
+        lwc1    $f21, THREAD_FPR21_LS64(\thread)
-        lwc1    $f22, THREAD_FPR22(\thread)
+        lwc1    $f22, THREAD_FPR22_LS64(\thread)
-        lwc1    $f23, THREAD_FPR23(\thread)
+        lwc1    $f23, THREAD_FPR23_LS64(\thread)
-        lwc1    $f24, THREAD_FPR24(\thread)
+        lwc1    $f24, THREAD_FPR24_LS64(\thread)
-        lwc1    $f25, THREAD_FPR25(\thread)
+        lwc1    $f25, THREAD_FPR25_LS64(\thread)
-        lwc1    $f26, THREAD_FPR26(\thread)
+        lwc1    $f26, THREAD_FPR26_LS64(\thread)
-        lwc1    $f27, THREAD_FPR27(\thread)
+        lwc1    $f27, THREAD_FPR27_LS64(\thread)
-        lwc1    $f28, THREAD_FPR28(\thread)
+        lwc1    $f28, THREAD_FPR28_LS64(\thread)
-        lwc1    $f29, THREAD_FPR29(\thread)
+        lwc1    $f29, THREAD_FPR29_LS64(\thread)
-        lwc1    $f30, THREAD_FPR30(\thread)
+        lwc1    $f30, THREAD_FPR30_LS64(\thread)
-        lwc1    $f31, THREAD_FPR31(\thread)
+        lwc1    $f31, THREAD_FPR31_LS64(\thread)
        ctc1    \tmp, fcr31
        .endm
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 4225e99bd7bf..b464b8b1147a 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -75,44 +75,44 @@
        .macro  fpu_save_16even thread tmp=t0
        cfc1    \tmp, fcr31
-        sdc1    $f0,  THREAD_FPR0(\thread)
+        sdc1    $f0,  THREAD_FPR0_LS64(\thread)
-        sdc1    $f2,  THREAD_FPR2(\thread)
+        sdc1    $f2,  THREAD_FPR2_LS64(\thread)
-        sdc1    $f4,  THREAD_FPR4(\thread)
+        sdc1    $f4,  THREAD_FPR4_LS64(\thread)
-        sdc1    $f6,  THREAD_FPR6(\thread)
+        sdc1    $f6,  THREAD_FPR6_LS64(\thread)
-        sdc1    $f8,  THREAD_FPR8(\thread)
+        sdc1    $f8,  THREAD_FPR8_LS64(\thread)
-        sdc1    $f10, THREAD_FPR10(\thread)
+        sdc1    $f10, THREAD_FPR10_LS64(\thread)
-        sdc1    $f12, THREAD_FPR12(\thread)
+        sdc1    $f12, THREAD_FPR12_LS64(\thread)
-        sdc1    $f14, THREAD_FPR14(\thread)
+        sdc1    $f14, THREAD_FPR14_LS64(\thread)
-        sdc1    $f16, THREAD_FPR16(\thread)
+        sdc1    $f16, THREAD_FPR16_LS64(\thread)
-        sdc1    $f18, THREAD_FPR18(\thread)
+        sdc1    $f18, THREAD_FPR18_LS64(\thread)
-        sdc1    $f20, THREAD_FPR20(\thread)
+        sdc1    $f20, THREAD_FPR20_LS64(\thread)
-        sdc1    $f22, THREAD_FPR22(\thread)
+        sdc1    $f22, THREAD_FPR22_LS64(\thread)
-        sdc1    $f24, THREAD_FPR24(\thread)
+        sdc1    $f24, THREAD_FPR24_LS64(\thread)
-        sdc1    $f26, THREAD_FPR26(\thread)
+        sdc1    $f26, THREAD_FPR26_LS64(\thread)
-        sdc1    $f28, THREAD_FPR28(\thread)
+        sdc1    $f28, THREAD_FPR28_LS64(\thread)
-        sdc1    $f30, THREAD_FPR30(\thread)
+        sdc1    $f30, THREAD_FPR30_LS64(\thread)
        sw      \tmp, THREAD_FCR31(\thread)
        .endm
        .macro  fpu_save_16odd thread
        .set    push
        .set    mips64r2
-        sdc1    $f1,  THREAD_FPR1(\thread)
+        sdc1    $f1,  THREAD_FPR1_LS64(\thread)
-        sdc1    $f3,  THREAD_FPR3(\thread)
+        sdc1    $f3,  THREAD_FPR3_LS64(\thread)
-        sdc1    $f5,  THREAD_FPR5(\thread)
+        sdc1    $f5,  THREAD_FPR5_LS64(\thread)
-        sdc1    $f7,  THREAD_FPR7(\thread)
+        sdc1    $f7,  THREAD_FPR7_LS64(\thread)
-        sdc1    $f9,  THREAD_FPR9(\thread)
+        sdc1    $f9,  THREAD_FPR9_LS64(\thread)
-        sdc1    $f11, THREAD_FPR11(\thread)
+        sdc1    $f11, THREAD_FPR11_LS64(\thread)
-        sdc1    $f13, THREAD_FPR13(\thread)
+        sdc1    $f13, THREAD_FPR13_LS64(\thread)
-        sdc1    $f15, THREAD_FPR15(\thread)
+        sdc1    $f15, THREAD_FPR15_LS64(\thread)
-        sdc1    $f17, THREAD_FPR17(\thread)
+        sdc1    $f17, THREAD_FPR17_LS64(\thread)
-        sdc1    $f19, THREAD_FPR19(\thread)
+        sdc1    $f19, THREAD_FPR19_LS64(\thread)
-        sdc1    $f21, THREAD_FPR21(\thread)
+        sdc1    $f21, THREAD_FPR21_LS64(\thread)
-        sdc1    $f23, THREAD_FPR23(\thread)
+        sdc1    $f23, THREAD_FPR23_LS64(\thread)
-        sdc1    $f25, THREAD_FPR25(\thread)
+        sdc1    $f25, THREAD_FPR25_LS64(\thread)
-        sdc1    $f27, THREAD_FPR27(\thread)
+        sdc1    $f27, THREAD_FPR27_LS64(\thread)
-        sdc1    $f29, THREAD_FPR29(\thread)
+        sdc1    $f29, THREAD_FPR29_LS64(\thread)
-        sdc1    $f31, THREAD_FPR31(\thread)
+        sdc1    $f31, THREAD_FPR31_LS64(\thread)
        .set    pop
        .endm
@@ -128,44 +128,44 @@
        .macro  fpu_restore_16even thread tmp=t0
        lw      \tmp, THREAD_FCR31(\thread)
-        ldc1    $f0,  THREAD_FPR0(\thread)
+        ldc1    $f0,  THREAD_FPR0_LS64(\thread)
-        ldc1    $f2,  THREAD_FPR2(\thread)
+        ldc1    $f2,  THREAD_FPR2_LS64(\thread)
-        ldc1    $f4,  THREAD_FPR4(\thread)
+        ldc1    $f4,  THREAD_FPR4_LS64(\thread)
-        ldc1    $f6,  THREAD_FPR6(\thread)
+        ldc1    $f6,  THREAD_FPR6_LS64(\thread)
-        ldc1    $f8,  THREAD_FPR8(\thread)
+        ldc1    $f8,  THREAD_FPR8_LS64(\thread)
-        ldc1    $f10, THREAD_FPR10(\thread)
+        ldc1    $f10, THREAD_FPR10_LS64(\thread)
-        ldc1    $f12, THREAD_FPR12(\thread)
+        ldc1    $f12, THREAD_FPR12_LS64(\thread)
-        ldc1    $f14, THREAD_FPR14(\thread)
+        ldc1    $f14, THREAD_FPR14_LS64(\thread)
-        ldc1    $f16, THREAD_FPR16(\thread)
+        ldc1    $f16, THREAD_FPR16_LS64(\thread)
-        ldc1    $f18, THREAD_FPR18(\thread)
+        ldc1    $f18, THREAD_FPR18_LS64(\thread)
-        ldc1    $f20, THREAD_FPR20(\thread)
+        ldc1    $f20, THREAD_FPR20_LS64(\thread)
-        ldc1    $f22, THREAD_FPR22(\thread)
+        ldc1    $f22, THREAD_FPR22_LS64(\thread)
-        ldc1    $f24, THREAD_FPR24(\thread)
+        ldc1    $f24, THREAD_FPR24_LS64(\thread)
-        ldc1    $f26, THREAD_FPR26(\thread)
+        ldc1    $f26, THREAD_FPR26_LS64(\thread)
-        ldc1    $f28, THREAD_FPR28(\thread)
+        ldc1    $f28, THREAD_FPR28_LS64(\thread)
-        ldc1    $f30, THREAD_FPR30(\thread)
+        ldc1    $f30, THREAD_FPR30_LS64(\thread)
        ctc1    \tmp, fcr31
        .endm
        .macro  fpu_restore_16odd thread
        .set    push
        .set    mips64r2
-        ldc1    $f1,  THREAD_FPR1(\thread)
+        ldc1    $f1,  THREAD_FPR1_LS64(\thread)
-        ldc1    $f3,  THREAD_FPR3(\thread)
+        ldc1    $f3,  THREAD_FPR3_LS64(\thread)
-        ldc1    $f5,  THREAD_FPR5(\thread)
+        ldc1    $f5,  THREAD_FPR5_LS64(\thread)
-        ldc1    $f7,  THREAD_FPR7(\thread)
+        ldc1    $f7,  THREAD_FPR7_LS64(\thread)
-        ldc1    $f9,  THREAD_FPR9(\thread)
+        ldc1    $f9,  THREAD_FPR9_LS64(\thread)
-        ldc1    $f11, THREAD_FPR11(\thread)
+        ldc1    $f11, THREAD_FPR11_LS64(\thread)
-        ldc1    $f13, THREAD_FPR13(\thread)
+        ldc1    $f13, THREAD_FPR13_LS64(\thread)
-        ldc1    $f15, THREAD_FPR15(\thread)
+        ldc1    $f15, THREAD_FPR15_LS64(\thread)
-        ldc1    $f17, THREAD_FPR17(\thread)
+        ldc1    $f17, THREAD_FPR17_LS64(\thread)
-        ldc1    $f19, THREAD_FPR19(\thread)
+        ldc1    $f19, THREAD_FPR19_LS64(\thread)
-        ldc1    $f21, THREAD_FPR21(\thread)
+        ldc1    $f21, THREAD_FPR21_LS64(\thread)
-        ldc1    $f23, THREAD_FPR23(\thread)
+        ldc1    $f23, THREAD_FPR23_LS64(\thread)
-        ldc1    $f25, THREAD_FPR25(\thread)
+        ldc1    $f25, THREAD_FPR25_LS64(\thread)
-        ldc1    $f27, THREAD_FPR27(\thread)
+        ldc1    $f27, THREAD_FPR27_LS64(\thread)
-        ldc1    $f29, THREAD_FPR29(\thread)
+        ldc1    $f29, THREAD_FPR29_LS64(\thread)
-        ldc1    $f31, THREAD_FPR31(\thread)
+        ldc1    $f31, THREAD_FPR31_LS64(\thread)
        .set    pop
        .endm
@@ -180,6 +180,17 @@
        fpu_restore_16even \thread \tmp
        .endm
+#ifdef CONFIG_CPU_MIPSR2
+        .macro  _EXT    rd, rs, p, s
+        ext     \rd, \rs, \p, \s
+        .endm
+#else /* !CONFIG_CPU_MIPSR2 */
+        .macro  _EXT    rd, rs, p, s
+        srl     \rd, \rs, \p
+        andi    \rd, \rd, (1 << \s) - 1
+        .endm
+#endif /* !CONFIG_CPU_MIPSR2 */
 /*
 * Temporary until all gas have MT ASE support
 */
@@ -207,4 +218,195 @@
         .word  0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
        .endm
+#ifdef TOOLCHAIN_SUPPORTS_MSA
+        .macro  ld_d    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    msa
+        ld.d    $w\wd, \off(\base)
+        .set    pop
+        .endm
+        .macro  st_d    wd, off, base
+        .set    push
+        .set    mips32r2
+        .set    msa
+        st.d    $w\wd, \off(\base)
+        .set    pop
+        .endm
+        .macro  copy_u_w        rd, ws, n
+        .set    push
+        .set    mips32r2
+        .set    msa
+        copy_u.w \rd, $w\ws[\n]
+        .set    pop
+        .endm
+        .macro  copy_u_d        rd, ws, n
+        .set    push
+        .set    mips64r2
+        .set    msa
+        copy_u.d \rd, $w\ws[\n]
+        .set    pop
+        .endm
+        .macro  insert_w        wd, n, rs
+        .set    push
+        .set    mips32r2
+        .set    msa
+        insert.w $w\wd[\n], \rs
+        .set    pop
+        .endm
+        .macro  insert_d        wd, n, rs
+        .set    push
+        .set    mips64r2
+        .set    msa
+        insert.d $w\wd[\n], \rs
+        .set    pop
+        .endm
+#else
+        /*
+         * Temporary until all toolchains in use include MSA support.
+         */
+        .macro  cfcmsa  rd, cs
+        .set    push
+        .set    noat
+        .word   0x787e0059 | (\cs << 11)
+        move    \rd, $1
+        .set    pop
+        .endm
+        .macro  ctcmsa  cd, rs
+        .set    push
+        .set    noat
+        move    $1, \rs
+        .word   0x783e0819 | (\cd << 6)
+        .set    pop
+        .endm
+        .macro  ld_d    wd, off, base
+        .set    push
+        .set    noat
+        add     $1, \base, \off
+        .word   0x78000823 | (\wd << 6)
+        .set    pop
+        .endm
+        .macro  st_d    wd, off, base
+        .set    push
+        .set    noat
+        add     $1, \base, \off
+        .word   0x78000827 | (\wd << 6)
+        .set    pop
+        .endm
+        .macro  copy_u_w        rd, ws, n
+        .set    push
+        .set    noat
+        .word   0x78f00059 | (\n << 16) | (\ws << 11)
+        /* move triggers an assembler bug... */
+        or      \rd, $1, zero
+        .set    pop
+        .endm
+        .macro  copy_u_d        rd, ws, n
+        .set    push
+        .set    noat
+        .word   0x78f80059 | (\n << 16) | (\ws << 11)
+        /* move triggers an assembler bug... */
+        or      \rd, $1, zero
+        .set    pop
+        .endm
+        .macro  insert_w        wd, n, rs
+        .set    push
+        .set    noat
+        /* move triggers an assembler bug... */
+        or      $1, \rs, zero
+        .word   0x79300819 | (\n << 16) | (\wd << 6)
+        .set    pop
+        .endm
+        .macro  insert_d        wd, n, rs
+        .set    push
+        .set    noat
+        /* move triggers an assembler bug... */
+        or      $1, \rs, zero
+        .word   0x79380819 | (\n << 16) | (\wd << 6)
+        .set    pop
+        .endm
+#endif
+        .macro  msa_save_all    thread
+        st_d    0, THREAD_FPR0, \thread
+        st_d    1, THREAD_FPR1, \thread
+        st_d    2, THREAD_FPR2, \thread
+        st_d    3, THREAD_FPR3, \thread
+        st_d    4, THREAD_FPR4, \thread
+        st_d    5, THREAD_FPR5, \thread
+        st_d    6, THREAD_FPR6, \thread
+        st_d    7, THREAD_FPR7, \thread
+        st_d    8, THREAD_FPR8, \thread
+        st_d    9, THREAD_FPR9, \thread
+        st_d    10, THREAD_FPR10, \thread
+        st_d    11, THREAD_FPR11, \thread
+        st_d    12, THREAD_FPR12, \thread
+        st_d    13, THREAD_FPR13, \thread
+        st_d    14, THREAD_FPR14, \thread
+        st_d    15, THREAD_FPR15, \thread
+        st_d    16, THREAD_FPR16, \thread
+        st_d    17, THREAD_FPR17, \thread
+        st_d    18, THREAD_FPR18, \thread
+        st_d    19, THREAD_FPR19, \thread
+        st_d    20, THREAD_FPR20, \thread
+        st_d    21, THREAD_FPR21, \thread
+        st_d    22, THREAD_FPR22, \thread
+        st_d    23, THREAD_FPR23, \thread
+        st_d    24, THREAD_FPR24, \thread
+        st_d    25, THREAD_FPR25, \thread
+        st_d    26, THREAD_FPR26, \thread
+        st_d    27, THREAD_FPR27, \thread
+        st_d    28, THREAD_FPR28, \thread
+        st_d    29, THREAD_FPR29, \thread
+        st_d    30, THREAD_FPR30, \thread
+        st_d    31, THREAD_FPR31, \thread
+        .endm
+        .macro  msa_restore_all thread
+        ld_d    0, THREAD_FPR0, \thread
+        ld_d    1, THREAD_FPR1, \thread
+        ld_d    2, THREAD_FPR2, \thread
+        ld_d    3, THREAD_FPR3, \thread
+        ld_d    4, THREAD_FPR4, \thread
+        ld_d    5, THREAD_FPR5, \thread
+        ld_d    6, THREAD_FPR6, \thread
+        ld_d    7, THREAD_FPR7, \thread
+        ld_d    8, THREAD_FPR8, \thread
+        ld_d    9, THREAD_FPR9, \thread
+        ld_d    10, THREAD_FPR10, \thread
+        ld_d    11, THREAD_FPR11, \thread
+        ld_d    12, THREAD_FPR12, \thread
+        ld_d    13, THREAD_FPR13, \thread
+        ld_d    14, THREAD_FPR14, \thread
+        ld_d    15, THREAD_FPR15, \thread
+        ld_d    16, THREAD_FPR16, \thread
+        ld_d    17, THREAD_FPR17, \thread
+        ld_d    18, THREAD_FPR18, \thread
+        ld_d    19, THREAD_FPR19, \thread
+        ld_d    20, THREAD_FPR20, \thread
+        ld_d    21, THREAD_FPR21, \thread
+        ld_d    22, THREAD_FPR22, \thread
+        ld_d    23, THREAD_FPR23, \thread
+        ld_d    24, THREAD_FPR24, \thread
+        ld_d    25, THREAD_FPR25, \thread
+        ld_d    26, THREAD_FPR26, \thread
+        ld_d    27, THREAD_FPR27, \thread
+        ld_d    28, THREAD_FPR28, \thread
+        ld_d    29, THREAD_FPR29, \thread
+        ld_d    30, THREAD_FPR30, \thread
+        ld_d    31, THREAD_FPR31, \thread
+        .endm
 #endif /* _ASM_ASMMACRO_H */
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 7eed2f261710..e8eb3d53a241 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -53,7 +53,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
                int temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     ll      %0, %1          # atomic_add            \n"
                "       addu    %0, %2                                  \n"
                "       sc      %0, %1                                  \n"
@@ -66,7 +66,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       ll      %0, %1          # atomic_add    \n"
                        "       addu    %0, %2                          \n"
                        "       sc      %0, %1                          \n"
@@ -96,7 +96,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
                int temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     ll      %0, %1          # atomic_sub            \n"
                "       subu    %0, %2                                  \n"
                "       sc      %0, %1                                  \n"
@@ -109,7 +109,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       ll      %0, %1          # atomic_sub    \n"
                        "       subu    %0, %2                          \n"
                        "       sc      %0, %1                          \n"
@@ -139,7 +139,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                int temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     ll      %1, %2          # atomic_add_return     \n"
                "       addu    %0, %1, %3                              \n"
                "       sc      %0, %2                                  \n"
@@ -153,7 +153,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       ll      %1, %2  # atomic_add_return     \n"
                        "       addu    %0, %1, %3                      \n"
                        "       sc      %0, %2                          \n"
@@ -188,7 +188,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                int temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     ll      %1, %2          # atomic_sub_return     \n"
                "       subu    %0, %1, %3                              \n"
                "       sc      %0, %2                                  \n"
@@ -205,7 +205,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       ll      %1, %2  # atomic_sub_return     \n"
                        "       subu    %0, %1, %3                      \n"
                        "       sc      %0, %2                          \n"
@@ -248,7 +248,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                int temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
                "       subu    %0, %1, %3                              \n"
                "       bltz    %0, 1f                                  \n"
@@ -266,7 +266,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                int temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
                "       subu    %0, %1, %3                              \n"
                "       bltz    %0, 1f                                  \n"
@@ -420,7 +420,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
                long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     lld     %0, %1          # atomic64_add          \n"
                "       daddu   %0, %2                                  \n"
                "       scd     %0, %1                                  \n"
@@ -433,7 +433,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       lld     %0, %1          # atomic64_add  \n"
                        "       daddu   %0, %2                          \n"
                        "       scd     %0, %1                          \n"
@@ -463,7 +463,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
                long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     lld     %0, %1          # atomic64_sub          \n"
                "       dsubu   %0, %2                                  \n"
                "       scd     %0, %1                                  \n"
@@ -476,7 +476,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       lld     %0, %1          # atomic64_sub  \n"
                        "       dsubu   %0, %2                          \n"
                        "       scd     %0, %1                          \n"
@@ -506,7 +506,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     lld     %1, %2          # atomic64_add_return   \n"
                "       daddu   %0, %1, %3                              \n"
                "       scd     %0, %2                                  \n"
@@ -520,7 +520,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       lld     %1, %2  # atomic64_add_return   \n"
                        "       daddu   %0, %1, %3                      \n"
                        "       scd     %0, %2                          \n"
@@ -556,7 +556,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     lld     %1, %2          # atomic64_sub_return   \n"
                "       dsubu   %0, %1, %3                              \n"
                "       scd     %0, %2                                  \n"
@@ -571,7 +571,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       lld     %1, %2  # atomic64_sub_return   \n"
                        "       dsubu   %0, %1, %3                      \n"
                        "       scd     %0, %2                          \n"
@@ -615,7 +615,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
                "       dsubu   %0, %1, %3                              \n"
                "       bltz    %0, 1f                                  \n"
@@ -633,7 +633,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
                "       dsubu   %0, %1, %3                              \n"
                "       bltz    %0, 1f                                  \n"
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 71305a8b3d78..6a65d49e2c0d 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -79,7 +79,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
        if (kernel_uses_llsc && R10000_LLSC_WAR) {
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     " __LL "%0, %1                  # set_bit       \n"
                "       or      %0, %2                                  \n"
                "       " __SC  "%0, %1                                 \n"
@@ -101,7 +101,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
        } else if (kernel_uses_llsc) {
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       " __LL "%0, %1          # set_bit       \n"
                        "       or      %0, %2                          \n"
                        "       " __SC  "%0, %1                         \n"
@@ -131,7 +131,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
        if (kernel_uses_llsc && R10000_LLSC_WAR) {
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     " __LL "%0, %1                  # clear_bit     \n"
                "       and     %0, %2                                  \n"
                "       " __SC "%0, %1                                  \n"
@@ -153,7 +153,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
        } else if (kernel_uses_llsc) {
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       " __LL "%0, %1          # clear_bit     \n"
                        "       and     %0, %2                          \n"
                        "       " __SC "%0, %1                          \n"
@@ -197,7 +197,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                unsigned long temp;
                __asm__ __volatile__(
-                "       .set    mips3                           \n"
+                "       .set    arch=r4000                      \n"
                "1:     " __LL "%0, %1          # change_bit    \n"
                "       xor     %0, %2                          \n"
                "       " __SC  "%0, %1                         \n"
@@ -211,7 +211,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       " __LL "%0, %1          # change_bit    \n"
                        "       xor     %0, %2                          \n"
                        "       " __SC  "%0, %1                         \n"
@@ -244,7 +244,7 @@ static inline int test_and_set_bit(unsigned long nr,
                unsigned long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
                "       or      %2, %0, %3                              \n"
                "       " __SC  "%2, %1                                 \n"
@@ -260,7 +260,7 @@ static inline int test_and_set_bit(unsigned long nr,
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       " __LL "%0, %1  # test_and_set_bit      \n"
                        "       or      %2, %0, %3                      \n"
                        "       " __SC  "%2, %1                         \n"
@@ -298,7 +298,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
                unsigned long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
                "       or      %2, %0, %3                              \n"
                "       " __SC  "%2, %1                                 \n"
@@ -314,7 +314,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       " __LL "%0, %1  # test_and_set_bit      \n"
                        "       or      %2, %0, %3                      \n"
                        "       " __SC  "%2, %1                         \n"
@@ -353,7 +353,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                unsigned long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
                "       or      %2, %0, %3                              \n"
                "       xor     %2, %3                                  \n"
@@ -386,7 +386,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       " __LL  "%0, %1 # test_and_clear_bit    \n"
                        "       or      %2, %0, %3                      \n"
                        "       xor     %2, %3                          \n"
@@ -427,7 +427,7 @@ static inline int test_and_change_bit(unsigned long nr,
                unsigned long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
                "       xor     %2, %0, %3                              \n"
                "       " __SC  "%2, %1                                 \n"
@@ -443,7 +443,7 @@ static inline int test_and_change_bit(unsigned long nr,
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       " __LL  "%0, %1 # test_and_change_bit   \n"
                        "       xor     %2, %0, %3                      \n"
                        "       " __SC  "\t%2, %1                       \n"
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 4d2cdea5aa37..1f7ca8b00404 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -61,15 +61,21 @@
 /*
 * Valid machtype for Loongson family
 */
-#define MACH_LOONGSON_UNKNOWN  0
+enum loongson_machine_type {
-#define MACH_LEMOTE_FL2E       1
+        MACH_LOONGSON_UNKNOWN,
-#define MACH_LEMOTE_FL2F       2
+        MACH_LEMOTE_FL2E,
-#define MACH_LEMOTE_ML2F7      3
+        MACH_LEMOTE_FL2F,
-#define MACH_LEMOTE_YL2F89     4
+        MACH_LEMOTE_ML2F7,
-#define MACH_DEXXON_GDIUM2F10  5
+        MACH_LEMOTE_YL2F89,
-#define MACH_LEMOTE_NAS        6
+        MACH_DEXXON_GDIUM2F10,
-#define MACH_LEMOTE_LL2F       7
+        MACH_LEMOTE_NAS,
-#define MACH_LOONGSON_END      8
+        MACH_LEMOTE_LL2F,
+        MACH_LEMOTE_A1004,
+        MACH_LEMOTE_A1101,
+        MACH_LEMOTE_A1201,
+        MACH_LEMOTE_A1205,
+        MACH_LOONGSON_END
+};
 /*
 * Valid machtype for group INGENIC
@@ -112,6 +118,8 @@ extern void prom_free_prom_memory(void);
 extern void free_init_pages(const char *what,
                            unsigned long begin, unsigned long end);
+extern void (*free_init_pages_eva)(void *begin, void *end);
 /*
 * Initial kernel command line, usually setup by prom_init()
 */
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
index ac3d2b8a20d4..3418c51e1151 100644
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -7,6 +7,7 @@
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Copyright (C) 2001 Thiemo Seufer.
 * Copyright (C) 2002 Maciej W. Rozycki
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 */
 #ifndef _ASM_CHECKSUM_H
 #define _ASM_CHECKSUM_H
@@ -29,9 +30,13 @@
 */
 __wsum csum_partial(const void *buff, int len, __wsum sum);
-__wsum __csum_partial_copy_user(const void *src, void *dst,
+__wsum __csum_partial_copy_kernel(const void *src, void *dst,
-                                int len, __wsum sum, int *err_ptr);
+                                  int len, __wsum sum, int *err_ptr);
+__wsum __csum_partial_copy_from_user(const void *src, void *dst,
+                                     int len, __wsum sum, int *err_ptr);
+__wsum __csum_partial_copy_to_user(const void *src, void *dst,
+                                   int len, __wsum sum, int *err_ptr);
 /*
 * this is a new version of the above that records errors it finds in *errp,
 * but continues and zeros the rest of the buffer.
@@ -41,8 +46,26 @@ __wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len,
                                   __wsum sum, int *err_ptr)
 {
        might_fault();
-        return __csum_partial_copy_user((__force void *)src, dst,
+        if (segment_eq(get_fs(), get_ds()))
-                                        len, sum, err_ptr);
+                return __csum_partial_copy_kernel((__force void *)src, dst,
+                                                  len, sum, err_ptr);
+        else
+                return __csum_partial_copy_from_user((__force void *)src, dst,
+                                                     len, sum, err_ptr);
+}
+#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
+static inline
+__wsum csum_and_copy_from_user(const void __user *src, void *dst,
+                               int len, __wsum sum, int *err_ptr)
+{
+        if (access_ok(VERIFY_READ, src, len))
+                return csum_partial_copy_from_user(src, dst, len, sum,
+                                                   err_ptr);
+        if (len)
+                *err_ptr = -EFAULT;
+        return sum;
 }
 /*
@@ -54,9 +77,16 @@ __wsum csum_and_copy_to_user(const void *src, void __user *dst, int len,
                             __wsum sum, int *err_ptr)
 {
        might_fault();
-        if (access_ok(VERIFY_WRITE, dst, len))
+        if (access_ok(VERIFY_WRITE, dst, len)) {
-                return __csum_partial_copy_user(src, (__force void *)dst,
+                if (segment_eq(get_fs(), get_ds()))
-                                                len, sum, err_ptr);
+                        return __csum_partial_copy_kernel(src,
+                                                          (__force void *)dst,
+                                                          len, sum, err_ptr);
+                else
+                        return __csum_partial_copy_to_user(src,
+                                                           (__force void *)dst,
+                                                           len, sum, err_ptr);
+        }
        if (len)
                *err_ptr = -EFAULT;
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 466069bd8465..eefcaa363a87 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -22,11 +22,11 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                unsigned long dummy;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     ll      %0, %3                  # xchg_u32      \n"
                "       .set    mips0                                   \n"
                "       move    %2, %z4                                 \n"
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "       sc      %2, %1                                  \n"
                "       beqzl   %2, 1b                                  \n"
                "       .set    mips0                                   \n"
@@ -38,11 +38,11 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       ll      %0, %3          # xchg_u32      \n"
                        "       .set    mips0                           \n"
                        "       move    %2, %z4                         \n"
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       sc      %2, %1                          \n"
                        "       .set    mips0                           \n"
                        : "=&r" (retval), "=m" (*m), "=&r" (dummy)
@@ -74,7 +74,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                unsigned long dummy;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     lld     %0, %3                  # xchg_u64      \n"
                "       move    %2, %z4                                 \n"
                "       scd     %2, %1                                  \n"
@@ -88,7 +88,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                do {
                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
+                        "       .set    arch=r4000                      \n"
                        "       lld     %0, %3          # xchg_u64      \n"
                        "       move    %2, %z4                         \n"
                        "       scd     %2, %1                          \n"
@@ -145,12 +145,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
                __asm__ __volatile__(                                   \
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
-                "       .set    mips3                           \n"     \
+                "       .set    arch=r4000                      \n"     \
                "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
                "       bne     %0, %z3, 2f                     \n"     \
                "       .set    mips0                           \n"     \
                "       move    $1, %z4                         \n"     \
-                "       .set    mips3                           \n"     \
+                "       .set    arch=r4000                      \n"     \
                "       " st "  $1, %1                          \n"     \
                "       beqzl   $1, 1b                          \n"     \
                "2:                                             \n"     \
@@ -162,12 +162,12 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
                __asm__ __volatile__(                                   \
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
-                "       .set    mips3                           \n"     \
+                "       .set    arch=r4000                      \n"     \
                "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
                "       bne     %0, %z3, 2f                     \n"     \
                "       .set    mips0                           \n"     \
                "       move    $1, %z4                         \n"     \
-                "       .set    mips3                           \n"     \
+                "       .set    arch=r4000                      \n"     \
                "       " st "  $1, %1                          \n"     \
                "       beqz    $1, 1b                          \n"     \
                "       .set    pop                             \n"     \
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 6e70b03b6aab..f56cc975b92f 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -26,7 +26,9 @@
 #ifndef cpu_has_segments
 #define cpu_has_segments        (cpu_data[0].options & MIPS_CPU_SEGMENTS)
 #endif
+#ifndef cpu_has_eva
+#define cpu_has_eva             (cpu_data[0].options & MIPS_CPU_EVA)
+#endif
 /*
 * For the moment we don't consider R6000 and R8000 so we can assume that
@@ -299,4 +301,10 @@
 #define cpu_has_vz              (cpu_data[0].ases & MIPS_ASE_VZ)
 #endif
+#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
+# define cpu_has_msa            (cpu_data[0].ases & MIPS_ASE_MSA)
+#elif !defined(cpu_has_msa)
+# define cpu_has_msa            0
+#endif
 #endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 8f7adf0ac1e3..dc2135be2a3a 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -49,6 +49,7 @@ struct cpuinfo_mips {
        unsigned long           ases;
        unsigned int            processor_id;
        unsigned int            fpu_id;
+        unsigned int            msa_id;
        unsigned int            cputype;
        int                     isa_level;
        int                     tlbsize;
@@ -95,4 +96,31 @@ extern void cpu_report(void);
 extern const char *__cpu_name[];
 #define cpu_name_string()       __cpu_name[smp_processor_id()]
+struct seq_file;
+struct notifier_block;
+extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
+extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
+#define proc_cpuinfo_notifier(fn, pri)                                  \
+({                                                                      \
+        static struct notifier_block fn##_nb = {                        \
+                .notifier_call = fn,                                    \
+                .priority = pri                                         \
+        };                                                              \
+                                                                        \
+        register_proc_cpuinfo_notifier(&fn##_nb);                       \
+})
+struct proc_cpuinfo_notifier_args {
+        struct seq_file *m;
+        unsigned long n;
+};
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
+# define cpu_vpe_id(cpuinfo)    ((cpuinfo)->vpe_id)
+#else
+# define cpu_vpe_id(cpuinfo)    0
+#endif
 #endif /* __ASM_CPU_INFO_H */
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 02f591bd95ca..721906130a57 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -20,6 +20,10 @@ static inline int __pure __get_cpu_type(const int cpu_type)
        case CPU_LOONGSON2:
 #endif
+#ifdef CONFIG_SYS_HAS_CPU_LOONGSON3
+        case CPU_LOONGSON3:
+#endif
 #ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
        case CPU_LOONGSON1:
 #endif
@@ -46,6 +50,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
        case CPU_M14KEC:
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
+        case CPU_P5600:
+        case CPU_M5150:
 #endif
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 76411df3d971..530eb8b3a68e 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -82,10 +82,10 @@
 #define PRID_IMP_RM7000         0x2700
 #define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
 #define PRID_IMP_RM9000         0x3400
-#define PRID_IMP_LOONGSON1      0x4200
+#define PRID_IMP_LOONGSON_32    0x4200  /* Loongson-1 */
 #define PRID_IMP_R5432          0x5400
 #define PRID_IMP_R5500          0x5500
-#define PRID_IMP_LOONGSON2      0x6300
+#define PRID_IMP_LOONGSON_64    0x6300  /* Loongson-2/3 */
 #define PRID_IMP_UNKNOWN        0xff00
@@ -115,6 +115,8 @@
 #define PRID_IMP_INTERAPTIV_MP  0xa100
 #define PRID_IMP_PROAPTIV_UP    0xa200
 #define PRID_IMP_PROAPTIV_MP    0xa300
+#define PRID_IMP_M5150          0xa700
+#define PRID_IMP_P5600          0xa800
 /*
 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -229,6 +231,7 @@
 #define PRID_REV_LOONGSON1B     0x0020
 #define PRID_REV_LOONGSON2E     0x0002
 #define PRID_REV_LOONGSON2F     0x0003
+#define PRID_REV_LOONGSON3A     0x0005
 /*
 * Older processors used to encode processor version and revision in two
@@ -296,14 +299,14 @@ enum cpu_type_enum {
        CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
        CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
-        CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,
+        CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
        /*
         * MIPS64 class processors
         */
        CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-        CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
+        CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
-        CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
+        CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
        CPU_LAST
 };
@@ -358,6 +361,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_MICROMIPS      0x01000000 /* CPU has microMIPS capability */
 #define MIPS_CPU_TLBINV         0x02000000 /* CPU supports TLBINV/F */
 #define MIPS_CPU_SEGMENTS       0x04000000 /* CPU supports Segmentation Control registers */
+#define MIPS_CPU_EVA            0x80000000 /* CPU supports Enhanced Virtual Addressing */
 /*
 * CPU ASE encodings
@@ -370,5 +374,6 @@ enum cpu_type_enum {
 #define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
 #define MIPS_ASE_DSP2P          0x00000040 /* Signal Processing ASE Rev 2 */
 #define MIPS_ASE_VZ             0x00000080 /* Virtualization ASE */
+#define MIPS_ASE_MSA            0x00000100 /* MIPS SIMD Architecture */
 #endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 84238c574d5e..06412aa9e3fb 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -49,9 +49,14 @@ static inline int dma_mapping_error(struct device *dev, u64 mask)
 static inline int
 dma_set_mask(struct device *dev, u64 mask)
 {
+        struct dma_map_ops *ops = get_dma_ops(dev);
        if(!dev->dma_mask || !dma_supported(dev, mask))
                return -EIO;
+        if (ops->set_dma_mask)
+                return ops->set_dma_mask(dev, mask);
        *dev->dma_mask = mask;
        return 0;
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 58e50cbdb1a6..4d86b72750c7 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -180,7 +180,7 @@ static inline void restore_fp(struct task_struct *tsk)
                _restore_fp(tsk);
 }
-static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
+static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
 {
        if (tsk == current) {
                preempt_disable();
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index 6ea15815d3ee..194cda0396a3 100644
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -12,6 +12,7 @@
 #include <linux/futex.h>
 #include <linux/uaccess.h>
+#include <asm/asm-eva.h>
 #include <asm/barrier.h>
 #include <asm/errno.h>
 #include <asm/war.h>
@@ -22,11 +23,11 @@
                __asm__ __volatile__(                                   \
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
-                "       .set    mips3                           \n"     \
+                "       .set    arch=r4000                      \n"     \
                "1:     ll      %1, %4  # __futex_atomic_op     \n"     \
                "       .set    mips0                           \n"     \
                "       " insn  "                               \n"     \
-                "       .set    mips3                           \n"     \
+                "       .set    arch=r4000                      \n"     \
                "2:     sc      $1, %2                          \n"     \
                "       beqzl   $1, 1b                          \n"     \
                __WEAK_LLSC_MB                                          \
@@ -48,12 +49,12 @@
                __asm__ __volatile__(                                   \
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
-                "       .set    mips3                           \n"     \
+                "       .set    arch=r4000                      \n"     \
-                "1:     ll      %1, %4  # __futex_atomic_op     \n"     \
+                "1:     "user_ll("%1", "%4")" # __futex_atomic_op\n"    \
                "       .set    mips0                           \n"     \
                "       " insn  "                               \n"     \
-                "       .set    mips3                           \n"     \
+                "       .set    arch=r4000                      \n"     \
-                "2:     sc      $1, %2                          \n"     \
+                "2:     "user_sc("$1", "%2")"                   \n"     \
                "       beqz    $1, 1b                          \n"     \
                __WEAK_LLSC_MB                                          \
                "3:                                             \n"     \
@@ -146,12 +147,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                "# futex_atomic_cmpxchg_inatomic                        \n"
                "       .set    push                                    \n"
                "       .set    noat                                    \n"
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:     ll      %1, %3                                  \n"
                "       bne     %1, %z4, 3f                             \n"
                "       .set    mips0                                   \n"
                "       move    $1, %z5                                 \n"
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "2:     sc      $1, %2                                  \n"
                "       beqzl   $1, 1b                                  \n"
                __WEAK_LLSC_MB
@@ -173,13 +174,13 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                "# futex_atomic_cmpxchg_inatomic                        \n"
                "       .set    push                                    \n"
                "       .set    noat                                    \n"
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
-                "1:     ll      %1, %3                                  \n"
+                "1:     "user_ll("%1", "%3")"                           \n"
                "       bne     %1, %z4, 3f                             \n"
                "       .set    mips0                                   \n"
                "       move    $1, %z5                                 \n"
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
-                "2:     sc      $1, %2                                  \n"
+                "2:     "user_sc("$1", "%2")"                           \n"
                "       beqz    $1, 1b                                  \n"
                __WEAK_LLSC_MB
                "3:                                                     \n"
diff --git a/arch/mips/include/asm/fw/fw.h b/arch/mips/include/asm/fw/fw.h
index d6c50a7e9ede..f3e6978aad70 100644
--- a/arch/mips/include/asm/fw/fw.h
+++ b/arch/mips/include/asm/fw/fw.h
@@ -38,7 +38,7 @@ extern int *_fw_envp;
 extern void fw_init_cmdline(void);
 extern char *fw_getcmdline(void);
-extern fw_memblock_t *fw_getmdesc(void);
+extern fw_memblock_t *fw_getmdesc(int);
 extern void fw_meminit(void);
 extern char *fw_getenv(char *name);
 extern unsigned long fw_getenvl(char *name);
diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h
deleted file mode 100644
index a7359f77a48e..000000000000
--- a/arch/mips/include/asm/gcmpregs.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- *
- * Multiprocessor Subsystem Register Definitions
- *
- */
-#ifndef _ASM_GCMPREGS_H
-#define _ASM_GCMPREGS_H
-/* Offsets to major blocks within GCMP from GCMP base */
-#define GCMP_GCB_OFS            0x0000 /* Global Control Block */
-#define GCMP_CLCB_OFS           0x2000 /* Core Local Control Block */
-#define GCMP_COCB_OFS           0x4000 /* Core Other Control Block */
-#define GCMP_GDB_OFS            0x8000 /* Global Debug Block */
-/* Offsets to individual GCMP registers from GCMP base */
-#define GCMPOFS(block, tag, reg)        \
-        (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
-#define GCMPOFSn(block, tag, reg, n) \
-        (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
-#define GCMPGCBOFS(reg)         GCMPOFS(GCB, GCB, reg)
-#define GCMPGCBOFSn(reg, n)     GCMPOFSn(GCB, GCB, reg, n)
-#define GCMPCLCBOFS(reg)        GCMPOFS(CLCB, CCB, reg)
-#define GCMPCOCBOFS(reg)        GCMPOFS(COCB, CCB, reg)
-#define GCMPGDBOFS(reg)         GCMPOFS(GDB, GDB, reg)
-/* GCMP register access */
-#define GCMPGCB(reg)                    REGP(_gcmp_base, GCMPGCBOFS(reg))
-#define GCMPGCBn(reg, n)               REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
-#define GCMPCLCB(reg)                   REGP(_gcmp_base, GCMPCLCBOFS(reg))
-#define GCMPCOCB(reg)                   REGP(_gcmp_base, GCMPCOCBOFS(reg))
-#define GCMPGDB(reg)                    REGP(_gcmp_base, GCMPGDBOFS(reg))
-/* Mask generation */
-#define GCMPMSK(block, reg, bits)       (MSK(bits)<<GCMP_##block##_##reg##_SHF)
-#define GCMPGCBMSK(reg, bits)           GCMPMSK(GCB, reg, bits)
-#define GCMPCCBMSK(reg, bits)           GCMPMSK(CCB, reg, bits)
-#define GCMPGDBMSK(reg, bits)           GCMPMSK(GDB, reg, bits)
-/* GCB registers */
-#define GCMP_GCB_GC_OFS                 0x0000  /* Global Config Register */
-#define  GCMP_GCB_GC_NUMIOCU_SHF        8
-#define  GCMP_GCB_GC_NUMIOCU_MSK        GCMPGCBMSK(GC_NUMIOCU, 4)
-#define  GCMP_GCB_GC_NUMCORES_SHF       0
-#define  GCMP_GCB_GC_NUMCORES_MSK       GCMPGCBMSK(GC_NUMCORES, 8)
-#define GCMP_GCB_GCMPB_OFS              0x0008          /* Global GCMP Base */
-#define  GCMP_GCB_GCMPB_GCMPBASE_SHF    15
-#define  GCMP_GCB_GCMPB_GCMPBASE_MSK    GCMPGCBMSK(GCMPB_GCMPBASE, 17)
-#define  GCMP_GCB_GCMPB_CMDEFTGT_SHF    0
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MSK    GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
-#define  GCMP_GCB_GCMPB_CMDEFTGT_DISABLED       0
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM            1
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1          2
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2          3
-#define GCMP_GCB_CCMC_OFS               0x0010  /* Global CM Control */
-#define GCMP_GCB_GCSRAP_OFS             0x0020  /* Global CSR Access Privilege */
-#define  GCMP_GCB_GCSRAP_CMACCESS_SHF   0
-#define  GCMP_GCB_GCSRAP_CMACCESS_MSK   GCMPGCBMSK(GCSRAP_CMACCESS, 8)
-#define GCMP_GCB_GCMPREV_OFS            0x0030  /* GCMP Revision Register */
-#define GCMP_GCB_GCMEM_OFS              0x0040  /* Global CM Error Mask */
-#define GCMP_GCB_GCMEC_OFS              0x0048  /* Global CM Error Cause */
-#define  GCMP_GCB_GMEC_ERROR_TYPE_SHF   27
-#define  GCMP_GCB_GMEC_ERROR_TYPE_MSK   GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
-#define  GCMP_GCB_GMEC_ERROR_INFO_SHF   0
-#define  GCMP_GCB_GMEC_ERROR_INFO_MSK   GCMPGCBMSK(GMEC_ERROR_INFO, 27)
-#define GCMP_GCB_GCMEA_OFS              0x0050  /* Global CM Error Address */
-#define GCMP_GCB_GCMEO_OFS              0x0058  /* Global CM Error Multiple */
-#define  GCMP_GCB_GMEO_ERROR_2ND_SHF    0
-#define  GCMP_GCB_GMEO_ERROR_2ND_MSK    GCMPGCBMSK(GMEO_ERROR_2ND, 5)
-#define GCMP_GCB_GICBA_OFS              0x0080  /* Global Interrupt Controller Base Address */
-#define  GCMP_GCB_GICBA_BASE_SHF        17
-#define  GCMP_GCB_GICBA_BASE_MSK        GCMPGCBMSK(GICBA_BASE, 15)
-#define  GCMP_GCB_GICBA_EN_SHF          0
-#define  GCMP_GCB_GICBA_EN_MSK          GCMPGCBMSK(GICBA_EN, 1)
-/* GCB Regions */
-#define GCMP_GCB_CMxBASE_OFS(n)         (0x0090+16*(n))         /* Global Region[0-3] Base Address */
-#define  GCMP_GCB_CMxBASE_BASE_SHF      16
-#define  GCMP_GCB_CMxBASE_BASE_MSK      GCMPGCBMSK(CMxBASE_BASE, 16)
-#define GCMP_GCB_CMxMASK_OFS(n)         (0x0098+16*(n))         /* Global Region[0-3] Address Mask */
-#define  GCMP_GCB_CMxMASK_MASK_SHF      16
-#define  GCMP_GCB_CMxMASK_MASK_MSK      GCMPGCBMSK(CMxMASK_MASK, 16)
-#define  GCMP_GCB_CMxMASK_CMREGTGT_SHF  0
-#define  GCMP_GCB_CMxMASK_CMREGTGT_MSK  GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
-#define  GCMP_GCB_CMxMASK_CMREGTGT_MEM   0
-#define  GCMP_GCB_CMxMASK_CMREGTGT_MEM1  1
-#define  GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
-#define  GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3
-/* Core local/Core other control block registers */
-#define GCMP_CCB_RESETR_OFS             0x0000                  /* Reset Release */
-#define  GCMP_CCB_RESETR_INRESET_SHF    0
-#define  GCMP_CCB_RESETR_INRESET_MSK    GCMPCCBMSK(RESETR_INRESET, 16)
-#define GCMP_CCB_COHCTL_OFS             0x0008                  /* Coherence Control */
-#define  GCMP_CCB_COHCTL_DOMAIN_SHF     0
-#define  GCMP_CCB_COHCTL_DOMAIN_MSK     GCMPCCBMSK(COHCTL_DOMAIN, 8)
-#define GCMP_CCB_CFG_OFS                0x0010                  /* Config */
-#define  GCMP_CCB_CFG_IOCUTYPE_SHF      10
-#define  GCMP_CCB_CFG_IOCUTYPE_MSK      GCMPCCBMSK(CFG_IOCUTYPE, 2)
-#define   GCMP_CCB_CFG_IOCUTYPE_CPU     0
-#define   GCMP_CCB_CFG_IOCUTYPE_NCIOCU  1
-#define   GCMP_CCB_CFG_IOCUTYPE_CIOCU   2
-#define  GCMP_CCB_CFG_NUMVPE_SHF        0
-#define  GCMP_CCB_CFG_NUMVPE_MSK        GCMPCCBMSK(CFG_NUMVPE, 10)
-#define GCMP_CCB_OTHER_OFS              0x0018          /* Other Address */
-#define  GCMP_CCB_OTHER_CORENUM_SHF     16
-#define  GCMP_CCB_OTHER_CORENUM_MSK     GCMPCCBMSK(OTHER_CORENUM, 16)
-#define GCMP_CCB_RESETBASE_OFS          0x0020          /* Reset Exception Base */
-#define  GCMP_CCB_RESETBASE_BEV_SHF     12
-#define  GCMP_CCB_RESETBASE_BEV_MSK     GCMPCCBMSK(RESETBASE_BEV, 20)
-#define GCMP_CCB_ID_OFS                 0x0028          /* Identification */
-#define GCMP_CCB_DINTGROUP_OFS          0x0030          /* DINT Group Participate */
-#define GCMP_CCB_DBGGROUP_OFS           0x0100          /* DebugBreak Group */
-extern int __init gcmp_probe(unsigned long, unsigned long);
-extern int __init gcmp_niocu(void);
-extern void __init gcmp_setregion(int, unsigned long, unsigned long, int);
-#endif /* _ASM_GCMPREGS_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index b2e3e93dd7d8..082716690589 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -11,6 +11,9 @@
 #ifndef _ASM_GICREGS_H
 #define _ASM_GICREGS_H
+#include <linux/bitmap.h>
+#include <linux/threads.h>
 #undef  GICISBYTELITTLEENDIAN
 /* Constants */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 3321dd5a8872..933b50e125a0 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -331,7 +331,7 @@ static inline void pfx##write##bwlq(type val,				\
                if (irq)                                                \
                        local_irq_save(__flags);                        \
                __asm__ __volatile__(                                   \
-                        ".set   mips3"          "\t\t# __writeq""\n\t"  \
+                        ".set   arch=r4000"     "\t\t# __writeq""\n\t"  \
                        "dsll32 %L0, %L0, 0"                    "\n\t"  \
                        "dsrl32 %L0, %L0, 0"                    "\n\t"  \
                        "dsll32 %M0, %M0, 0"                    "\n\t"  \
@@ -361,7 +361,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem)	\
                if (irq)                                                \
                        local_irq_save(__flags);                        \
                __asm__ __volatile__(                                   \
-                        ".set   mips3"          "\t\t# __readq" "\n\t"  \
+                        ".set   arch=r4000"     "\t\t# __readq" "\n\t"  \
                        "ld     %L0, %1"                        "\n\t"  \
                        "dsra32 %M0, %L0, 0"                    "\n\t"  \
                        "sll    %L0, %L0, 0"                    "\n\t"  \
@@ -584,7 +584,7 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
 *
 * This API used to be exported; it now is for arch code internal use only.
 */
-#ifdef CONFIG_DMA_NONCOHERENT
+#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
@@ -603,7 +603,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 #define dma_cache_inv(start,size)       \
        do { (void) (start); (void) (size); } while (0)
-#endif /* CONFIG_DMA_NONCOHERENT */
+#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
 /*
 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index a995fce87791..060aaa6348d7 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -30,16 +30,16 @@
 /* Special address that contains the comm page, used for reducing # of traps */
-#define KVM_GUEST_COMMPAGE_ADDR     0x0
+#define KVM_GUEST_COMMPAGE_ADDR         0x0
 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
                                        ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
-#define KVM_GUEST_KUSEG             0x00000000UL
+#define KVM_GUEST_KUSEG                 0x00000000UL
-#define KVM_GUEST_KSEG0             0x40000000UL
+#define KVM_GUEST_KSEG0                 0x40000000UL
-#define KVM_GUEST_KSEG23            0x60000000UL
+#define KVM_GUEST_KSEG23                0x60000000UL
-#define KVM_GUEST_KSEGX(a)          ((_ACAST32_(a)) & 0x60000000)
+#define KVM_GUEST_KSEGX(a)              ((_ACAST32_(a)) & 0x60000000)
-#define KVM_GUEST_CPHYSADDR(a)      ((_ACAST32_(a)) & 0x1fffffff)
+#define KVM_GUEST_CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
@@ -52,17 +52,17 @@
 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
-#define KVM_INVALID_PAGE            0xdeadbeef
+#define KVM_INVALID_PAGE                0xdeadbeef
-#define KVM_INVALID_INST            0xdeadbeef
+#define KVM_INVALID_INST                0xdeadbeef
-#define KVM_INVALID_ADDR            0xdeadbeef
+#define KVM_INVALID_ADDR                0xdeadbeef
-#define KVM_MALTA_GUEST_RTC_ADDR    0xb8000070UL
+#define KVM_MALTA_GUEST_RTC_ADDR        0xb8000070UL
-#define GUEST_TICKS_PER_JIFFY (40000000/HZ)
+#define GUEST_TICKS_PER_JIFFY           (40000000/HZ)
-#define MS_TO_NS(x) (x * 1E6L)
+#define MS_TO_NS(x)                     (x * 1E6L)
-#define CAUSEB_DC       27
+#define CAUSEB_DC                       27
-#define CAUSEF_DC       (_ULCAST_(1)   << 27)
+#define CAUSEF_DC                       (_ULCAST_(1) << 27)
 struct kvm;
 struct kvm_run;
@@ -126,8 +126,8 @@ struct kvm_arch {
        int commpage_tlb;
 };
-#define N_MIPS_COPROC_REGS      32
+#define N_MIPS_COPROC_REGS      32
-#define N_MIPS_COPROC_SEL       8
+#define N_MIPS_COPROC_SEL       8
 struct mips_coproc {
        unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
@@ -139,124 +139,124 @@ struct mips_coproc {
 /*
 * Coprocessor 0 register names
 */
-#define MIPS_CP0_TLB_INDEX          0
+#define MIPS_CP0_TLB_INDEX      0
-#define MIPS_CP0_TLB_RANDOM         1
+#define MIPS_CP0_TLB_RANDOM     1
-#define MIPS_CP0_TLB_LOW            2
+#define MIPS_CP0_TLB_LOW        2
-#define MIPS_CP0_TLB_LO0            2
+#define MIPS_CP0_TLB_LO0        2
-#define MIPS_CP0_TLB_LO1            3
+#define MIPS_CP0_TLB_LO1        3
-#define MIPS_CP0_TLB_CONTEXT    4
+#define MIPS_CP0_TLB_CONTEXT    4
-#define MIPS_CP0_TLB_PG_MASK    5
+#define MIPS_CP0_TLB_PG_MASK    5
-#define MIPS_CP0_TLB_WIRED          6
+#define MIPS_CP0_TLB_WIRED      6
-#define MIPS_CP0_HWRENA             7
+#define MIPS_CP0_HWRENA         7
-#define MIPS_CP0_BAD_VADDR          8
+#define MIPS_CP0_BAD_VADDR      8
-#define MIPS_CP0_COUNT          9
+#define MIPS_CP0_COUNT          9
-#define MIPS_CP0_TLB_HI         10
+#define MIPS_CP0_TLB_HI         10
-#define MIPS_CP0_COMPARE            11
+#define MIPS_CP0_COMPARE        11
-#define MIPS_CP0_STATUS         12
+#define MIPS_CP0_STATUS         12
-#define MIPS_CP0_CAUSE          13
+#define MIPS_CP0_CAUSE          13
-#define MIPS_CP0_EXC_PC         14
+#define MIPS_CP0_EXC_PC         14
-#define MIPS_CP0_PRID               15
+#define MIPS_CP0_PRID           15
-#define MIPS_CP0_CONFIG         16
+#define MIPS_CP0_CONFIG         16
-#define MIPS_CP0_LLADDR         17
+#define MIPS_CP0_LLADDR         17
-#define MIPS_CP0_WATCH_LO           18
+#define MIPS_CP0_WATCH_LO       18
-#define MIPS_CP0_WATCH_HI           19
+#define MIPS_CP0_WATCH_HI       19
-#define MIPS_CP0_TLB_XCONTEXT   20
+#define MIPS_CP0_TLB_XCONTEXT   20
-#define MIPS_CP0_ECC                26
+#define MIPS_CP0_ECC            26
-#define MIPS_CP0_CACHE_ERR          27
+#define MIPS_CP0_CACHE_ERR      27
-#define MIPS_CP0_TAG_LO         28
+#define MIPS_CP0_TAG_LO         28
-#define MIPS_CP0_TAG_HI         29
+#define MIPS_CP0_TAG_HI         29
-#define MIPS_CP0_ERROR_PC           30
+#define MIPS_CP0_ERROR_PC       30
-#define MIPS_CP0_DEBUG          23
+#define MIPS_CP0_DEBUG          23
-#define MIPS_CP0_DEPC               24
+#define MIPS_CP0_DEPC           24
-#define MIPS_CP0_PERFCNT            25
+#define MIPS_CP0_PERFCNT        25
-#define MIPS_CP0_ERRCTL         26
+#define MIPS_CP0_ERRCTL         26
-#define MIPS_CP0_DATA_LO            28
+#define MIPS_CP0_DATA_LO        28
-#define MIPS_CP0_DATA_HI            29
+#define MIPS_CP0_DATA_HI        29
-#define MIPS_CP0_DESAVE         31
+#define MIPS_CP0_DESAVE         31
-#define MIPS_CP0_CONFIG_SEL         0
+#define MIPS_CP0_CONFIG_SEL     0
-#define MIPS_CP0_CONFIG1_SEL    1
+#define MIPS_CP0_CONFIG1_SEL    1
-#define MIPS_CP0_CONFIG2_SEL    2
+#define MIPS_CP0_CONFIG2_SEL    2
-#define MIPS_CP0_CONFIG3_SEL    3
+#define MIPS_CP0_CONFIG3_SEL    3
 /* Config0 register bits */
-#define CP0C0_M    31
+#define CP0C0_M                 31
-#define CP0C0_K23  28
+#define CP0C0_K23               28
-#define CP0C0_KU   25
+#define CP0C0_KU                25
-#define CP0C0_MDU  20
+#define CP0C0_MDU               20
-#define CP0C0_MM   17
+#define CP0C0_MM                17
-#define CP0C0_BM   16
+#define CP0C0_BM                16
-#define CP0C0_BE   15
+#define CP0C0_BE                15
-#define CP0C0_AT   13
+#define CP0C0_AT                13
-#define CP0C0_AR   10
+#define CP0C0_AR                10
-#define CP0C0_MT   7
+#define CP0C0_MT                7
-#define CP0C0_VI   3
+#define CP0C0_VI                3
-#define CP0C0_K0   0
+#define CP0C0_K0                0
 /* Config1 register bits */
-#define CP0C1_M    31
+#define CP0C1_M                 31
-#define CP0C1_MMU  25
+#define CP0C1_MMU               25
-#define CP0C1_IS   22
+#define CP0C1_IS                22
-#define CP0C1_IL   19
+#define CP0C1_IL                19
-#define CP0C1_IA   16
+#define CP0C1_IA                16
-#define CP0C1_DS   13
+#define CP0C1_DS                13
-#define CP0C1_DL   10
+#define CP0C1_DL                10
-#define CP0C1_DA   7
+#define CP0C1_DA                7
-#define CP0C1_C2   6
+#define CP0C1_C2                6
-#define CP0C1_MD   5
+#define CP0C1_MD                5
-#define CP0C1_PC   4
+#define CP0C1_PC                4
-#define CP0C1_WR   3
+#define CP0C1_WR                3
-#define CP0C1_CA   2
+#define CP0C1_CA                2
-#define CP0C1_EP   1
+#define CP0C1_EP                1
-#define CP0C1_FP   0
+#define CP0C1_FP                0
 /* Config2 Register bits */
-#define CP0C2_M    31
+#define CP0C2_M                 31
-#define CP0C2_TU   28
+#define CP0C2_TU                28
-#define CP0C2_TS   24
+#define CP0C2_TS                24
-#define CP0C2_TL   20
+#define CP0C2_TL                20
-#define CP0C2_TA   16
+#define CP0C2_TA                16
-#define CP0C2_SU   12
+#define CP0C2_SU                12
-#define CP0C2_SS   8
+#define CP0C2_SS                8
-#define CP0C2_SL   4
+#define CP0C2_SL                4
-#define CP0C2_SA   0
+#define CP0C2_SA                0
 /* Config3 Register bits */
-#define CP0C3_M    31
+#define CP0C3_M                 31
-#define CP0C3_ISA_ON_EXC 16
+#define CP0C3_ISA_ON_EXC        16
-#define CP0C3_ULRI  13
+#define CP0C3_ULRI              13
-#define CP0C3_DSPP 10
+#define CP0C3_DSPP              10
-#define CP0C3_LPA  7
+#define CP0C3_LPA               7
-#define CP0C3_VEIC 6
+#define CP0C3_VEIC              6
-#define CP0C3_VInt 5
+#define CP0C3_VInt              5
-#define CP0C3_SP   4
+#define CP0C3_SP                4
-#define CP0C3_MT   2
+#define CP0C3_MT                2
-#define CP0C3_SM   1
+#define CP0C3_SM                1
-#define CP0C3_TL   0
+#define CP0C3_TL                0
 /* Have config1, Cacheable, noncoherent, write-back, write allocate*/
-#define MIPS_CONFIG0                                              \
+#define MIPS_CONFIG0                                            \
  ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
 /* Have config2, no coprocessor2 attached, no MDMX support attached,
   no performance counters, watch registers present,
   no code compression, EJTAG present, no FPU, no watch registers */
-#define MIPS_CONFIG1                                              \
+#define MIPS_CONFIG1                                            \
-((1 << CP0C1_M) |                                                 \
+((1 << CP0C1_M) |                                               \
- (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
+ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |          \
- (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
+ (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |          \
 (0 << CP0C1_FP))
 /* Have config3, no tertiary/secondary caches implemented */
-#define MIPS_CONFIG2                                              \
+#define MIPS_CONFIG2                                            \
 ((1 << CP0C2_M))
 /* No config4, no DSP ASE, no large physaddr (PABITS),
   no external interrupt controller, no vectored interrupts,
   no 1kb pages, no SmartMIPS ASE, no trace logic */
-#define MIPS_CONFIG3                                              \
+#define MIPS_CONFIG3                                            \
-((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
+((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |        \
- (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
+ (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |      \
 (0 << CP0C3_SM) | (0 << CP0C3_TL))
 /* MMU types, the first four entries have the same layout as the
@@ -274,36 +274,36 @@ enum mips_mmu_types {
 /*
 * Trap codes
 */
-#define T_INT           0       /* Interrupt pending */
+#define T_INT                   0       /* Interrupt pending */
-#define T_TLB_MOD       1       /* TLB modified fault */
+#define T_TLB_MOD               1       /* TLB modified fault */
-#define T_TLB_LD_MISS       2   /* TLB miss on load or ifetch */
+#define T_TLB_LD_MISS           2       /* TLB miss on load or ifetch */
-#define T_TLB_ST_MISS       3   /* TLB miss on a store */
+#define T_TLB_ST_MISS           3       /* TLB miss on a store */
-#define T_ADDR_ERR_LD       4   /* Address error on a load or ifetch */
+#define T_ADDR_ERR_LD           4       /* Address error on a load or ifetch */
-#define T_ADDR_ERR_ST       5   /* Address error on a store */
+#define T_ADDR_ERR_ST           5       /* Address error on a store */
-#define T_BUS_ERR_IFETCH    6   /* Bus error on an ifetch */
+#define T_BUS_ERR_IFETCH        6       /* Bus error on an ifetch */
-#define T_BUS_ERR_LD_ST     7   /* Bus error on a load or store */
+#define T_BUS_ERR_LD_ST         7       /* Bus error on a load or store */
-#define T_SYSCALL       8       /* System call */
+#define T_SYSCALL               8       /* System call */
-#define T_BREAK         9       /* Breakpoint */
+#define T_BREAK                 9       /* Breakpoint */
-#define T_RES_INST      10      /* Reserved instruction exception */
+#define T_RES_INST              10      /* Reserved instruction exception */
-#define T_COP_UNUSABLE      11  /* Coprocessor unusable */
+#define T_COP_UNUSABLE          11      /* Coprocessor unusable */
-#define T_OVFLOW        12      /* Arithmetic overflow */
+#define T_OVFLOW                12      /* Arithmetic overflow */
 /*
 * Trap definitions added for r4000 port.
 */
-#define T_TRAP          13      /* Trap instruction */
+#define T_TRAP                  13      /* Trap instruction */
-#define T_VCEI          14      /* Virtual coherency exception */
+#define T_VCEI                  14      /* Virtual coherency exception */
-#define T_FPE           15      /* Floating point exception */
+#define T_FPE                   15      /* Floating point exception */
-#define T_WATCH         23      /* Watch address reference */
+#define T_WATCH                 23      /* Watch address reference */
-#define T_VCED          31      /* Virtual coherency data */
+#define T_VCED                  31      /* Virtual coherency data */
 /* Resume Flags */
-#define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
+#define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
-#define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
+#define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
-#define RESUME_GUEST            0
+#define RESUME_GUEST            0
-#define RESUME_GUEST_DR         RESUME_FLAG_DR
+#define RESUME_GUEST_DR         RESUME_FLAG_DR
-#define RESUME_HOST             RESUME_FLAG_HOST
+#define RESUME_HOST             RESUME_FLAG_HOST
 enum emulation_result {
        EMULATE_DONE,           /* no further processing */
@@ -313,24 +313,27 @@ enum emulation_result {
        EMULATE_PRIV_FAIL,
 };
-#define MIPS3_PG_G  0x00000001  /* Global; ignore ASID if in lo0 & lo1 */
+#define MIPS3_PG_G      0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
-#define MIPS3_PG_V  0x00000002  /* Valid */
+#define MIPS3_PG_V      0x00000002 /* Valid */
-#define MIPS3_PG_NV 0x00000000
+#define MIPS3_PG_NV     0x00000000
-#define MIPS3_PG_D  0x00000004  /* Dirty */
+#define MIPS3_PG_D      0x00000004 /* Dirty */
 #define mips3_paddr_to_tlbpfn(x) \
-    (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
+        (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 #define mips3_tlbpfn_to_paddr(x) \
-    ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
+        ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
-#define MIPS3_PG_SHIFT      6
+#define MIPS3_PG_SHIFT          6
-#define MIPS3_PG_FRAME      0x3fffffc0
+#define MIPS3_PG_FRAME          0x3fffffc0
-#define VPN2_MASK           0xffffe000
+#define VPN2_MASK               0xffffe000
-#define TLB_IS_GLOBAL(x)    (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G))
+#define TLB_IS_GLOBAL(x)        (((x).tlb_lo0 & MIPS3_PG_G) &&  \
-#define TLB_VPN2(x)         ((x).tlb_hi & VPN2_MASK)
+                                 ((x).tlb_lo1 & MIPS3_PG_G))
-#define TLB_ASID(x)         ((x).tlb_hi & ASID_MASK)
+#define TLB_VPN2(x)             ((x).tlb_hi & VPN2_MASK)
-#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V))
+#define TLB_ASID(x)             ((x).tlb_hi & ASID_MASK)
+#define TLB_IS_VALID(x, va)     (((va) & (1 << PAGE_SHIFT))     \
+                                 ? ((x).tlb_lo1 & MIPS3_PG_V)   \
+                                 : ((x).tlb_lo0 & MIPS3_PG_V))
 struct kvm_mips_tlb {
        long tlb_mask;
@@ -339,7 +342,7 @@ struct kvm_mips_tlb {
        long tlb_lo1;
 };
-#define KVM_MIPS_GUEST_TLB_SIZE     64
+#define KVM_MIPS_GUEST_TLB_SIZE 64
 struct kvm_vcpu_arch {
        void *host_ebase, *guest_ebase;
        unsigned long host_stack;
@@ -400,65 +403,67 @@ struct kvm_vcpu_arch {
 };
-#define kvm_read_c0_guest_index(cop0)               (cop0->reg[MIPS_CP0_TLB_INDEX][0])
+#define kvm_read_c0_guest_index(cop0)           (cop0->reg[MIPS_CP0_TLB_INDEX][0])
-#define kvm_write_c0_guest_index(cop0, val)         (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
+#define kvm_write_c0_guest_index(cop0, val)     (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
-#define kvm_read_c0_guest_entrylo0(cop0)            (cop0->reg[MIPS_CP0_TLB_LO0][0])
+#define kvm_read_c0_guest_entrylo0(cop0)        (cop0->reg[MIPS_CP0_TLB_LO0][0])
-#define kvm_read_c0_guest_entrylo1(cop0)            (cop0->reg[MIPS_CP0_TLB_LO1][0])
+#define kvm_read_c0_guest_entrylo1(cop0)        (cop0->reg[MIPS_CP0_TLB_LO1][0])
-#define kvm_read_c0_guest_context(cop0)             (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
+#define kvm_read_c0_guest_context(cop0)         (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
-#define kvm_write_c0_guest_context(cop0, val)       (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
+#define kvm_write_c0_guest_context(cop0, val)   (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
-#define kvm_read_c0_guest_userlocal(cop0)           (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
+#define kvm_read_c0_guest_userlocal(cop0)       (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
-#define kvm_read_c0_guest_pagemask(cop0)            (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
+#define kvm_read_c0_guest_pagemask(cop0)        (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
-#define kvm_write_c0_guest_pagemask(cop0, val)      (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
+#define kvm_write_c0_guest_pagemask(cop0, val)  (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
-#define kvm_read_c0_guest_wired(cop0)               (cop0->reg[MIPS_CP0_TLB_WIRED][0])
+#define kvm_read_c0_guest_wired(cop0)           (cop0->reg[MIPS_CP0_TLB_WIRED][0])
-#define kvm_write_c0_guest_wired(cop0, val)         (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
+#define kvm_write_c0_guest_wired(cop0, val)     (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
-#define kvm_read_c0_guest_badvaddr(cop0)            (cop0->reg[MIPS_CP0_BAD_VADDR][0])
+#define kvm_read_c0_guest_hwrena(cop0)          (cop0->reg[MIPS_CP0_HWRENA][0])
-#define kvm_write_c0_guest_badvaddr(cop0, val)      (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
+#define kvm_write_c0_guest_hwrena(cop0, val)    (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
-#define kvm_read_c0_guest_count(cop0)               (cop0->reg[MIPS_CP0_COUNT][0])
+#define kvm_read_c0_guest_badvaddr(cop0)        (cop0->reg[MIPS_CP0_BAD_VADDR][0])
-#define kvm_write_c0_guest_count(cop0, val)         (cop0->reg[MIPS_CP0_COUNT][0] = (val))
+#define kvm_write_c0_guest_badvaddr(cop0, val)  (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
-#define kvm_read_c0_guest_entryhi(cop0)             (cop0->reg[MIPS_CP0_TLB_HI][0])
+#define kvm_read_c0_guest_count(cop0)           (cop0->reg[MIPS_CP0_COUNT][0])
-#define kvm_write_c0_guest_entryhi(cop0, val)       (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
+#define kvm_write_c0_guest_count(cop0, val)     (cop0->reg[MIPS_CP0_COUNT][0] = (val))
-#define kvm_read_c0_guest_compare(cop0)             (cop0->reg[MIPS_CP0_COMPARE][0])
+#define kvm_read_c0_guest_entryhi(cop0)         (cop0->reg[MIPS_CP0_TLB_HI][0])
-#define kvm_write_c0_guest_compare(cop0, val)       (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
+#define kvm_write_c0_guest_entryhi(cop0, val)   (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
-#define kvm_read_c0_guest_status(cop0)              (cop0->reg[MIPS_CP0_STATUS][0])
+#define kvm_read_c0_guest_compare(cop0)         (cop0->reg[MIPS_CP0_COMPARE][0])
-#define kvm_write_c0_guest_status(cop0, val)        (cop0->reg[MIPS_CP0_STATUS][0] = (val))
+#define kvm_write_c0_guest_compare(cop0, val)   (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
-#define kvm_read_c0_guest_intctl(cop0)              (cop0->reg[MIPS_CP0_STATUS][1])
+#define kvm_read_c0_guest_status(cop0)          (cop0->reg[MIPS_CP0_STATUS][0])
-#define kvm_write_c0_guest_intctl(cop0, val)        (cop0->reg[MIPS_CP0_STATUS][1] = (val))
+#define kvm_write_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] = (val))
-#define kvm_read_c0_guest_cause(cop0)               (cop0->reg[MIPS_CP0_CAUSE][0])
+#define kvm_read_c0_guest_intctl(cop0)          (cop0->reg[MIPS_CP0_STATUS][1])
-#define kvm_write_c0_guest_cause(cop0, val)         (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
+#define kvm_write_c0_guest_intctl(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][1] = (val))
-#define kvm_read_c0_guest_epc(cop0)                 (cop0->reg[MIPS_CP0_EXC_PC][0])
+#define kvm_read_c0_guest_cause(cop0)           (cop0->reg[MIPS_CP0_CAUSE][0])
-#define kvm_write_c0_guest_epc(cop0, val)           (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
+#define kvm_write_c0_guest_cause(cop0, val)     (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
-#define kvm_read_c0_guest_prid(cop0)                (cop0->reg[MIPS_CP0_PRID][0])
+#define kvm_read_c0_guest_epc(cop0)             (cop0->reg[MIPS_CP0_EXC_PC][0])
-#define kvm_write_c0_guest_prid(cop0, val)          (cop0->reg[MIPS_CP0_PRID][0] = (val))
+#define kvm_write_c0_guest_epc(cop0, val)       (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
-#define kvm_read_c0_guest_ebase(cop0)               (cop0->reg[MIPS_CP0_PRID][1])
+#define kvm_read_c0_guest_prid(cop0)            (cop0->reg[MIPS_CP0_PRID][0])
-#define kvm_write_c0_guest_ebase(cop0, val)         (cop0->reg[MIPS_CP0_PRID][1] = (val))
+#define kvm_write_c0_guest_prid(cop0, val)      (cop0->reg[MIPS_CP0_PRID][0] = (val))
-#define kvm_read_c0_guest_config(cop0)              (cop0->reg[MIPS_CP0_CONFIG][0])
+#define kvm_read_c0_guest_ebase(cop0)           (cop0->reg[MIPS_CP0_PRID][1])
-#define kvm_read_c0_guest_config1(cop0)             (cop0->reg[MIPS_CP0_CONFIG][1])
+#define kvm_write_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] = (val))
-#define kvm_read_c0_guest_config2(cop0)             (cop0->reg[MIPS_CP0_CONFIG][2])
+#define kvm_read_c0_guest_config(cop0)          (cop0->reg[MIPS_CP0_CONFIG][0])
-#define kvm_read_c0_guest_config3(cop0)             (cop0->reg[MIPS_CP0_CONFIG][3])
+#define kvm_read_c0_guest_config1(cop0)         (cop0->reg[MIPS_CP0_CONFIG][1])
-#define kvm_read_c0_guest_config7(cop0)             (cop0->reg[MIPS_CP0_CONFIG][7])
+#define kvm_read_c0_guest_config2(cop0)         (cop0->reg[MIPS_CP0_CONFIG][2])
-#define kvm_write_c0_guest_config(cop0, val)        (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
+#define kvm_read_c0_guest_config3(cop0)         (cop0->reg[MIPS_CP0_CONFIG][3])
-#define kvm_write_c0_guest_config1(cop0, val)       (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
+#define kvm_read_c0_guest_config7(cop0)         (cop0->reg[MIPS_CP0_CONFIG][7])
-#define kvm_write_c0_guest_config2(cop0, val)       (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
+#define kvm_write_c0_guest_config(cop0, val)    (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
-#define kvm_write_c0_guest_config3(cop0, val)       (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
+#define kvm_write_c0_guest_config1(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
-#define kvm_write_c0_guest_config7(cop0, val)       (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
+#define kvm_write_c0_guest_config2(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
-#define kvm_read_c0_guest_errorepc(cop0)            (cop0->reg[MIPS_CP0_ERROR_PC][0])
+#define kvm_write_c0_guest_config3(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
-#define kvm_write_c0_guest_errorepc(cop0, val)      (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
+#define kvm_write_c0_guest_config7(cop0, val)   (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
+#define kvm_read_c0_guest_errorepc(cop0)        (cop0->reg[MIPS_CP0_ERROR_PC][0])
-#define kvm_set_c0_guest_status(cop0, val)          (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
+#define kvm_write_c0_guest_errorepc(cop0, val)  (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
-#define kvm_clear_c0_guest_status(cop0, val)        (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
-#define kvm_set_c0_guest_cause(cop0, val)           (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
+#define kvm_set_c0_guest_status(cop0, val)      (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
-#define kvm_clear_c0_guest_cause(cop0, val)         (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
+#define kvm_clear_c0_guest_status(cop0, val)    (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
-#define kvm_change_c0_guest_cause(cop0, change, val)  \
+#define kvm_set_c0_guest_cause(cop0, val)       (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
-{                                                     \
+#define kvm_clear_c0_guest_cause(cop0, val)     (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
-    kvm_clear_c0_guest_cause(cop0, change);           \
+#define kvm_change_c0_guest_cause(cop0, change, val)                    \
-    kvm_set_c0_guest_cause(cop0, ((val) & (change))); \
+{                                                                       \
+        kvm_clear_c0_guest_cause(cop0, change);                         \
+        kvm_set_c0_guest_cause(cop0, ((val) & (change)));               \
 }
-#define kvm_set_c0_guest_ebase(cop0, val)           (cop0->reg[MIPS_CP0_PRID][1] |= (val))
+#define kvm_set_c0_guest_ebase(cop0, val)       (cop0->reg[MIPS_CP0_PRID][1] |= (val))
-#define kvm_clear_c0_guest_ebase(cop0, val)         (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
+#define kvm_clear_c0_guest_ebase(cop0, val)     (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
-#define kvm_change_c0_guest_ebase(cop0, change, val)  \
+#define kvm_change_c0_guest_ebase(cop0, change, val)                    \
-{                                                     \
+{                                                                       \
-    kvm_clear_c0_guest_ebase(cop0, change);           \
+        kvm_clear_c0_guest_ebase(cop0, change);                         \
-    kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
+        kvm_set_c0_guest_ebase(cop0, ((val) & (change)));               \
 }
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index d44622cd74be..46dfc3c1fd49 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -33,7 +33,7 @@ static __inline__ long local_add_return(long i, local_t * l)
                unsigned long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:"    __LL    "%1, %2         # local_add_return      \n"
                "       addu    %0, %1, %3                              \n"
                        __SC    "%0, %2                                 \n"
@@ -47,7 +47,7 @@ static __inline__ long local_add_return(long i, local_t * l)
                unsigned long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:"    __LL    "%1, %2         # local_add_return      \n"
                "       addu    %0, %1, %3                              \n"
                        __SC    "%0, %2                                 \n"
@@ -78,7 +78,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
                unsigned long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:"    __LL    "%1, %2         # local_sub_return      \n"
                "       subu    %0, %1, %3                              \n"
                        __SC    "%0, %2                                 \n"
@@ -92,7 +92,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
                unsigned long temp;
                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "1:"    __LL    "%1, %2         # local_sub_return      \n"
                "       subu    %0, %1, %3                              \n"
                        __SC    "%0, %2                                 \n"
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 54f9e84db8ac..b4c3ecb17d48 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -1161,18 +1161,6 @@ enum soc_au1200_ints {
 #define MAC_RX_BUFF3_STATUS     0x30
 #define MAC_RX_BUFF3_ADDR       0x34
-#define UART_RX         0       /* Receive buffer */
-#define UART_TX         4       /* Transmit buffer */
-#define UART_IER        8       /* Interrupt Enable Register */
-#define UART_IIR        0xC     /* Interrupt ID Register */
-#define UART_FCR        0x10    /* FIFO Control Register */
-#define UART_LCR        0x14    /* Line Control Register */
-#define UART_MCR        0x18    /* Modem Control Register */
-#define UART_LSR        0x1C    /* Line Status Register */
-#define UART_MSR        0x20    /* Modem Status Register */
-#define UART_CLK        0x28    /* Baud Rate Clock Divider */
-#define UART_MOD_CNTRL  0x100   /* Module Control */
 /* SSIO */
 #define SSI0_STATUS             0xB1600000
 #  define SSI_STATUS_BF         (1 << 4)
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
index 40005fb39618..bba7399a49a3 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -27,7 +27,11 @@ enum bcm47xx_board {
        BCM47XX_BOARD_ASUS_WL700GE,
        BCM47XX_BOARD_ASUS_WLHDD,
+        BCM47XX_BOARD_BELKIN_F7D3301,
+        BCM47XX_BOARD_BELKIN_F7D3302,
        BCM47XX_BOARD_BELKIN_F7D4301,
+        BCM47XX_BOARD_BELKIN_F7D4302,
+        BCM47XX_BOARD_BELKIN_F7D4401,
        BCM47XX_BOARD_BUFFALO_WBR2_G54,
        BCM47XX_BOARD_BUFFALO_WHR2_A54G54,
@@ -66,7 +70,7 @@ enum bcm47xx_board {
        BCM47XX_BOARD_LINKSYS_WRT310NV1,
        BCM47XX_BOARD_LINKSYS_WRT310NV2,
        BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
-        BCM47XX_BOARD_LINKSYS_WRT54GSV1,
+        BCM47XX_BOARD_LINKSYS_WRT54G,
        BCM47XX_BOARD_LINKSYS_WRT610NV1,
        BCM47XX_BOARD_LINKSYS_WRT610NV2,
        BCM47XX_BOARD_LINKSYS_WRTSL54GS,
@@ -94,6 +98,8 @@ enum bcm47xx_board {
        BCM47XX_BOARD_PHICOMM_M1,
+        BCM47XX_BOARD_SIEMENS_SE505V2,
        BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE,
        BCM47XX_BOARD_ZTE_H218N,
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
deleted file mode 100644
index d3cce7326dd4..000000000000
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * AMD Alchemy DBAu1200 Reference Board
- * Board register defines.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_DB1200_H
-#define __ASM_DB1200_H
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-/* Bit positions for the different interrupt sources */
-#define BCSR_INT_IDE            0x0001
-#define BCSR_INT_ETH            0x0002
-#define BCSR_INT_PC0            0x0004
-#define BCSR_INT_PC0STSCHG      0x0008
-#define BCSR_INT_PC1            0x0010
-#define BCSR_INT_PC1STSCHG      0x0020
-#define BCSR_INT_DC             0x0040
-#define BCSR_INT_FLASHBUSY      0x0080
-#define BCSR_INT_PC0INSERT      0x0100
-#define BCSR_INT_PC0EJECT       0x0200
-#define BCSR_INT_PC1INSERT      0x0400
-#define BCSR_INT_PC1EJECT       0x0800
-#define BCSR_INT_SD0INSERT      0x1000
-#define BCSR_INT_SD0EJECT       0x2000
-#define BCSR_INT_SD1INSERT      0x4000
-#define BCSR_INT_SD1EJECT       0x8000
-#define IDE_REG_SHIFT           5
-#define DB1200_IDE_PHYS_ADDR    0x18800000
-#define DB1200_IDE_PHYS_LEN     (16 << IDE_REG_SHIFT)
-#define DB1200_ETH_PHYS_ADDR    0x19000300
-#define DB1200_NAND_PHYS_ADDR   0x20000000
-#define PB1200_IDE_PHYS_ADDR    0x0C800000
-#define PB1200_ETH_PHYS_ADDR    0x0D000300
-#define PB1200_NAND_PHYS_ADDR   0x1C000000
-/*
- * External Interrupts for DBAu1200 as of 8/6/2004.
- * Bit positions in the CPLD registers can be calculated by taking
- * the interrupt define and subtracting the DB1200_INT_BEGIN value.
- *
- *   Example: IDE bis pos is  = 64 - 64
- *            ETH bit pos is  = 65 - 64
- */
-enum external_db1200_ints {
-        DB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
-        DB1200_IDE_INT          = DB1200_INT_BEGIN,
-        DB1200_ETH_INT,
-        DB1200_PC0_INT,
-        DB1200_PC0_STSCHG_INT,
-        DB1200_PC1_INT,
-        DB1200_PC1_STSCHG_INT,
-        DB1200_DC_INT,
-        DB1200_FLASHBUSY_INT,
-        DB1200_PC0_INSERT_INT,
-        DB1200_PC0_EJECT_INT,
-        DB1200_PC1_INSERT_INT,
-        DB1200_PC1_EJECT_INT,
-        DB1200_SD0_INSERT_INT,
-        DB1200_SD0_EJECT_INT,
-        PB1200_SD1_INSERT_INT,
-        PB1200_SD1_EJECT_INT,
-        DB1200_INT_END          = DB1200_INT_BEGIN + 15,
-};
-#endif /* __ASM_DB1200_H */
diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
deleted file mode 100644
index 3d1ede46f059..000000000000
--- a/arch/mips/include/asm/mach-db1x00/db1300.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * NetLogic DB1300 board constants
- */
-#ifndef _DB1300_H_
-#define _DB1300_H_
-/* FPGA (external mux) interrupt sources */
-#define DB1300_FIRST_INT        (ALCHEMY_GPIC_INT_LAST + 1)
-#define DB1300_IDE_INT          (DB1300_FIRST_INT + 0)
-#define DB1300_ETH_INT          (DB1300_FIRST_INT + 1)
-#define DB1300_CF_INT           (DB1300_FIRST_INT + 2)
-#define DB1300_VIDEO_INT        (DB1300_FIRST_INT + 4)
-#define DB1300_HDMI_INT         (DB1300_FIRST_INT + 5)
-#define DB1300_DC_INT           (DB1300_FIRST_INT + 6)
-#define DB1300_FLASH_INT        (DB1300_FIRST_INT + 7)
-#define DB1300_CF_INSERT_INT    (DB1300_FIRST_INT + 8)
-#define DB1300_CF_EJECT_INT     (DB1300_FIRST_INT + 9)
-#define DB1300_AC97_INT         (DB1300_FIRST_INT + 10)
-#define DB1300_AC97_PEN_INT     (DB1300_FIRST_INT + 11)
-#define DB1300_SD1_INSERT_INT   (DB1300_FIRST_INT + 12)
-#define DB1300_SD1_EJECT_INT    (DB1300_FIRST_INT + 13)
-#define DB1300_OTG_VBUS_OC_INT  (DB1300_FIRST_INT + 14)
-#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
-#define DB1300_LAST_INT         (DB1300_FIRST_INT + 15)
-/* SMSC9210 CS */
-#define DB1300_ETH_PHYS_ADDR    0x19000000
-#define DB1300_ETH_PHYS_END     0x197fffff
-/* ATA CS */
-#define DB1300_IDE_PHYS_ADDR    0x18800000
-#define DB1300_IDE_REG_SHIFT    5
-#define DB1300_IDE_PHYS_LEN     (16 << DB1300_IDE_REG_SHIFT)
-/* NAND CS */
-#define DB1300_NAND_PHYS_ADDR   0x20000000
-#define DB1300_NAND_PHYS_END    0x20000fff
-#endif  /* _DB1300_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/boot_param.h b/arch/mips/include/asm/mach-loongson/boot_param.h
new file mode 100644
index 000000000000..829a7ec185fb
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/boot_param.h
@@ -0,0 +1,163 @@
+#ifndef __ASM_MACH_LOONGSON_BOOT_PARAM_H_
+#define __ASM_MACH_LOONGSON_BOOT_PARAM_H_
+#define SYSTEM_RAM_LOW          1
+#define SYSTEM_RAM_HIGH         2
+#define MEM_RESERVED            3
+#define PCI_IO                  4
+#define PCI_MEM                 5
+#define LOONGSON_CFG_REG        6
+#define VIDEO_ROM               7
+#define ADAPTER_ROM             8
+#define ACPI_TABLE              9
+#define MAX_MEMORY_TYPE         10
+#define LOONGSON3_BOOT_MEM_MAP_MAX 128
+struct efi_memory_map_loongson {
+        u16 vers;       /* version of efi_memory_map */
+        u32 nr_map;     /* number of memory_maps */
+        u32 mem_freq;   /* memory frequence */
+        struct mem_map {
+                u32 node_id;    /* node_id which memory attached to */
+                u32 mem_type;   /* system memory, pci memory, pci io, etc. */
+                u64 mem_start;  /* memory map start address */
+                u32 mem_size;   /* each memory_map size, not the total size */
+        } map[LOONGSON3_BOOT_MEM_MAP_MAX];
+} __packed;
+enum loongson_cpu_type {
+        Loongson_2E = 0,
+        Loongson_2F = 1,
+        Loongson_3A = 2,
+        Loongson_3B = 3,
+        Loongson_1A = 4,
+        Loongson_1B = 5
+};
+/*
+ * Capability and feature descriptor structure for MIPS CPU
+ */
+struct efi_cpuinfo_loongson {
+        u16 vers;     /* version of efi_cpuinfo_loongson */
+        u32 processor_id; /* PRID, e.g. 6305, 6306 */
+        u32 cputype;  /* Loongson_3A/3B, etc. */
+        u32 total_node;   /* num of total numa nodes */
+        u32 cpu_startup_core_id; /* Core id */
+        u32 cpu_clock_freq; /* cpu_clock */
+        u32 nr_cpus;
+} __packed;
+struct system_loongson {
+        u16 vers;     /* version of system_loongson */
+        u32 ccnuma_smp; /* 0: no numa; 1: has numa */
+        u32 sing_double_channel; /* 1:single; 2:double */
+} __packed;
+struct irq_source_routing_table {
+        u16 vers;
+        u16 size;
+        u16 rtr_bus;
+        u16 rtr_devfn;
+        u32 vendor;
+        u32 device;
+        u32 PIC_type;   /* conform use HT or PCI to route to CPU-PIC */
+        u64 ht_int_bit; /* 3A: 1<<24; 3B: 1<<16 */
+        u64 ht_enable;  /* irqs used in this PIC */
+        u32 node_id;    /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
+        u64 pci_mem_start_addr;
+        u64 pci_mem_end_addr;
+        u64 pci_io_start_addr;
+        u64 pci_io_end_addr;
+        u64 pci_config_addr;
+        u32 dma_mask_bits;
+} __packed;
+struct interface_info {
+        u16 vers; /* version of the specificition */
+        u16 size;
+        u8  flag;
+        char description[64];
+} __packed;
+#define MAX_RESOURCE_NUMBER 128
+struct resource_loongson {
+        u64 start; /* resource start address */
+        u64 end;   /* resource end address */
+        char name[64];
+        u32 flags;
+};
+struct archdev_data {};  /* arch specific additions */
+struct board_devices {
+        char name[64];    /* hold the device name */
+        u32 num_resources; /* number of device_resource */
+        /* for each device's resource */
+        struct resource_loongson resource[MAX_RESOURCE_NUMBER];
+        /* arch specific additions */
+        struct archdev_data archdata;
+};
+struct loongson_special_attribute {
+        u16 vers;     /* version of this special */
+        char special_name[64]; /* special_atribute_name */
+        u32 loongson_special_type; /* type of special device */
+        /* for each device's resource */
+        struct resource_loongson resource[MAX_RESOURCE_NUMBER];
+};
+struct loongson_params {
+        u64 memory_offset;      /* efi_memory_map_loongson struct offset */
+        u64 cpu_offset;         /* efi_cpuinfo_loongson struct offset */
+        u64 system_offset;      /* system_loongson struct offset */
+        u64 irq_offset;         /* irq_source_routing_table struct offset */
+        u64 interface_offset;   /* interface_info struct offset */
+        u64 special_offset;     /* loongson_special_attribute struct offset */
+        u64 boarddev_table_offset;  /* board_devices offset */
+};
+struct smbios_tables {
+        u16 vers;     /* version of smbios */
+        u64 vga_bios; /* vga_bios address */
+        struct loongson_params lp;
+};
+struct efi_reset_system_t {
+        u64 ResetCold;
+        u64 ResetWarm;
+        u64 ResetType;
+        u64 Shutdown;
+        u64 DoSuspend; /* NULL if not support */
+};
+struct efi_loongson {
+        u64 mps;        /* MPS table */
+        u64 acpi;       /* ACPI table (IA64 ext 0.71) */
+        u64 acpi20;     /* ACPI table (ACPI 2.0) */
+        struct smbios_tables smbios;    /* SM BIOS table */
+        u64 sal_systab; /* SAL system table */
+        u64 boot_info;  /* boot info table */
+};
+struct boot_params {
+        struct efi_loongson efi;
+        struct efi_reset_system_t reset_system;
+};
+struct loongson_system_configuration {
+        u32 nr_cpus;
+        enum loongson_cpu_type cputype;
+        u64 ht_control_base;
+        u64 pci_mem_start_addr;
+        u64 pci_mem_end_addr;
+        u64 pci_io_base;
+        u64 restart_addr;
+        u64 poweroff_addr;
+        u64 suspend_addr;
+        u64 vgabios_addr;
+        u32 dma_mask_bits;
+};
+extern struct efi_memory_map_loongson *loongson_memmap;
+extern struct loongson_system_configuration loongson_sysconf;
+#endif
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index aeb2c05d6145..6a902751cc7f 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -11,24 +11,40 @@
 #ifndef __ASM_MACH_LOONGSON_DMA_COHERENCE_H
 #define __ASM_MACH_LOONGSON_DMA_COHERENCE_H
+#ifdef CONFIG_SWIOTLB
+#include <linux/swiotlb.h>
+#endif
 struct device;
+extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
+extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
 static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
                                          size_t size)
 {
+#ifdef CONFIG_CPU_LOONGSON3
+        return virt_to_phys(addr);
+#else
        return virt_to_phys(addr) | 0x80000000;
+#endif
 }
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
                                               struct page *page)
 {
+#ifdef CONFIG_CPU_LOONGSON3
+        return page_to_phys(page);
+#else
        return page_to_phys(page) | 0x80000000;
+#endif
 }
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
        dma_addr_t dma_addr)
 {
-#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
+#if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT)
+        return dma_addr;
+#elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
        return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
 #else
        return dma_addr & 0x7fffffff;
@@ -55,7 +71,11 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
 static inline int plat_device_is_coherent(struct device *dev)
 {
+#ifdef CONFIG_DMA_NONCOHERENT
        return 0;
+#else
+        return 1;
+#endif /* CONFIG_DMA_NONCOHERENT */
 }
 #endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-loongson/irq.h b/arch/mips/include/asm/mach-loongson/irq.h
new file mode 100644
index 000000000000..34560bda6626
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/irq.h
@@ -0,0 +1,44 @@
+#ifndef __ASM_MACH_LOONGSON_IRQ_H_
+#define __ASM_MACH_LOONGSON_IRQ_H_
+#include <boot_param.h>
+#ifdef CONFIG_CPU_LOONGSON3
+/* cpu core interrupt numbers */
+#define MIPS_CPU_IRQ_BASE 56
+#define LOONGSON_UART_IRQ   (MIPS_CPU_IRQ_BASE + 2) /* UART */
+#define LOONGSON_HT1_IRQ    (MIPS_CPU_IRQ_BASE + 3) /* HT1 */
+#define LOONGSON_TIMER_IRQ  (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
+#define LOONGSON_HT1_CFG_BASE           loongson_sysconf.ht_control_base
+#define LOONGSON_HT1_INT_VECTOR_BASE    (LOONGSON_HT1_CFG_BASE + 0x80)
+#define LOONGSON_HT1_INT_EN_BASE        (LOONGSON_HT1_CFG_BASE + 0xa0)
+#define LOONGSON_HT1_INT_VECTOR(n)      \
+                LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
+#define LOONGSON_HT1_INTN_EN(n)         \
+                LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
+#define LOONGSON_INT_ROUTER_OFFSET      0x1400
+#define LOONGSON_INT_ROUTER_INTEN       \
+          LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
+#define LOONGSON_INT_ROUTER_INTENSET    \
+          LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
+#define LOONGSON_INT_ROUTER_INTENCLR    \
+          LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
+#define LOONGSON_INT_ROUTER_ENTRY(n)    \
+          LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
+#define LOONGSON_INT_ROUTER_LPC         LOONGSON_INT_ROUTER_ENTRY(0x0a)
+#define LOONGSON_INT_ROUTER_HT1(n)      LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
+#define LOONGSON_INT_CORE0_INT0         0x11 /* route to int 0 of core 0 */
+#define LOONGSON_INT_CORE0_INT1         0x21 /* route to int 1 of core 0 */
+#endif
+extern void fixup_irqs(void);
+extern void loongson3_ipi_interrupt(struct pt_regs *regs);
+#include_next <irq.h>
+#endif /* __ASM_MACH_LOONGSON_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index b286534fef08..f3fd1eb8e3dd 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/kconfig.h>
+#include <boot_param.h>
 /* loongson internal northbridge initialization */
 extern void bonito_irq_init(void);
@@ -24,8 +25,9 @@ extern void mach_prepare_reboot(void);
 extern void mach_prepare_shutdown(void);
 /* environment arguments from bootloader */
-extern unsigned long cpu_clock_freq;
+extern u32 cpu_clock_freq;
-extern unsigned long memsize, highmemsize;
+extern u32 memsize, highmemsize;
+extern struct plat_smp_ops loongson3_smp_ops;
 /* loongson-specific command line, env and memory initialization */
 extern void __init prom_init_memory(void);
@@ -61,6 +63,12 @@ extern int mach_i8259_irq(void);
 #define LOONGSON_REG(x) \
        (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
+#define LOONGSON3_REG8(base, x) \
+        (*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
+#define LOONGSON3_REG32(base, x) \
+        (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))
 #define LOONGSON_IRQ_BASE       32
 #define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
@@ -86,6 +94,10 @@ static inline void do_perfcnt_IRQ(void)
 #define LOONGSON_REG_BASE       0x1fe00000
 #define LOONGSON_REG_SIZE       0x00100000      /* 256Bytes + 256Bytes + ??? */
 #define LOONGSON_REG_TOP        (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
+/* Loongson-3 specific registers */
+#define LOONGSON3_REG_BASE      0x3ff00000
+#define LOONGSON3_REG_SIZE      0x00100000      /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON3_REG_TOP       (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
 #define LOONGSON_LIO1_BASE      0x1ff00000
 #define LOONGSON_LIO1_SIZE      0x00100000      /* 1M */
@@ -101,7 +113,13 @@ static inline void do_perfcnt_IRQ(void)
 #define LOONGSON_PCICFG_BASE    0x1fe80000
 #define LOONGSON_PCICFG_SIZE    0x00000800      /* 2K */
 #define LOONGSON_PCICFG_TOP     (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
+#if defined(CONFIG_HT_PCI)
+#define LOONGSON_PCIIO_BASE     loongson_sysconf.pci_io_base
+#else
 #define LOONGSON_PCIIO_BASE     0x1fd00000
+#endif
 #define LOONGSON_PCIIO_SIZE     0x00100000      /* 1M */
 #define LOONGSON_PCIIO_TOP      (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
@@ -231,6 +249,9 @@ static inline void do_perfcnt_IRQ(void)
 #define LOONGSON_PXARB_CFG              LOONGSON_REG(LOONGSON_REGBASE + 0x68)
 #define LOONGSON_PXARB_STATUS           LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
+/* Chip Config */
+#define LOONGSON_CHIPCFG0               LOONGSON_REG(LOONGSON_REGBASE + 0x80)
 /* pcimap */
 #define LOONGSON_PCIMAP_PCIMAP_LO0      0x0000003f
@@ -246,9 +267,6 @@ static inline void do_perfcnt_IRQ(void)
 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
 #include <linux/cpufreq.h>
 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
-/* Chip Config */
-#define LOONGSON_CHIPCFG0               LOONGSON_REG(LOONGSON_REGBASE + 0x80)
 #endif
 /*
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 3810d5ca84ac..1b1f592fa2be 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -24,4 +24,10 @@
 #endif
+#ifdef CONFIG_LEMOTE_MACH3A
+#define LOONGSON_MACHTYPE MACH_LEMOTE_A1101
+#endif /* CONFIG_LEMOTE_MACH3A */
 #endif /* __ASM_MACH_LOONGSON_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index bc99dab4ef63..1212774f66ef 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -40,8 +40,13 @@ extern struct pci_ops loongson_pci_ops;
 #else   /* loongson2f/32bit & loongson2e */
 /* this pci memory space is mapped by pcimap in pci.c */
+#ifdef CONFIG_CPU_LOONGSON3
+#define LOONGSON_PCI_MEM_START  0x40000000UL
+#define LOONGSON_PCI_MEM_END    0x7effffffUL
+#else
 #define LOONGSON_PCI_MEM_START  LOONGSON_PCILO1_BASE
 #define LOONGSON_PCI_MEM_END    (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
+#endif
 /* this is an offset from mips_io_port_base */
 #define LOONGSON_PCI_IO_START   0x00004000UL
diff --git a/arch/mips/include/asm/mach-loongson/spaces.h b/arch/mips/include/asm/mach-loongson/spaces.h
new file mode 100644
index 000000000000..e2506ee90044
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/spaces.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_MACH_LOONGSON_SPACES_H_
+#define __ASM_MACH_LOONGSON_SPACES_H_
+#if defined(CONFIG_64BIT)
+#define CAC_BASE        _AC(0x9800000000000000, UL)
+#endif /* CONFIG_64BIT */
+#include <asm/mach-generic/spaces.h>
+#endif
diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
index 0b793e7bf67e..7c5e17a17849 100644
--- a/arch/mips/include/asm/mach-malta/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
@@ -5,10 +5,80 @@
 *
 * Chris Dearman (chris@mips.com)
 * Copyright (C) 2007 Mips Technologies, Inc.
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 */
 #ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
 #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+        /*
+         * Prepare segments for EVA boot:
+         *
+         * This is in case the processor boots in legacy configuration
+         * (SI_EVAReset is de-asserted and CONFIG5.K == 0)
+         *
+         * On entry, t1 is loaded with CP0_CONFIG
+         *
+         * ========================= Mappings =============================
+         * Virtual memory           Physical memory           Mapping
+         * 0x00000000 - 0x7fffffff  0x80000000 - 0xfffffffff   MUSUK (kuseg)
+         *                          Flat 2GB physical memory
+         *
+         * 0x80000000 - 0x9fffffff  0x00000000 - 0x1ffffffff   MUSUK (kseg0)
+         * 0xa0000000 - 0xbf000000  0x00000000 - 0x1ffffffff   MUSUK (kseg1)
+         * 0xc0000000 - 0xdfffffff             -                 MK  (kseg2)
+         * 0xe0000000 - 0xffffffff             -                 MK  (kseg3)
+         *
+         *
+         * Lowmem is expanded to 2GB
+         */
+        .macro  eva_entry
+        /*
+         * Get Config.K0 value and use it to program
+         * the segmentation registers
+         */
+        andi    t1, 0x7 /* CCA */
+        move    t2, t1
+        ins     t2, t1, 16, 3
+        /* SegCtl0 */
+        li      t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) |         \
+                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) |                          \
+                (((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) |            \
+                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
+        or      t0, t2
+        mtc0    t0, $5, 2
+        /* SegCtl1 */
+        li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |      \
+                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (2 << MIPS_SEGCFG_C_SHIFT) |                            \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) |                          \
+                (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |         \
+                (0 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
+        ins     t0, t1, 16, 3
+        mtc0    t0, $5, 3
+        /* SegCtl2 */
+        li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |      \
+                (6 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) |                          \
+                (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |         \
+                (4 << MIPS_SEGCFG_PA_SHIFT) |                           \
+                (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
+        or      t0, t2
+        mtc0    t0, $5, 4
+        jal     mips_ihb
+        mfc0    t0, $16, 5
+        li      t2, 0x40000000      /* K bit */
+        or      t0, t0, t2
+        mtc0    t0, $16, 5
+        sync
+        jal     mips_ihb
+        .endm
        .macro  kernel_entry_setup
 #ifdef CONFIG_MIPS_MT_SMTC
        mfc0    t0, CP0_CONFIG
@@ -39,14 +109,57 @@
 nonmt_processor:
        .asciz  "SMTC kernel requires the MT ASE to run\n"
        __FINIT
-0:
 #endif
+#ifdef CONFIG_EVA
+        sync
+        ehb
+        mfc0    t1, CP0_CONFIG
+        bgez    t1, 9f
+        mfc0    t0, CP0_CONFIG, 1
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 2
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 3
+        sll     t0, t0, 6   /* SC bit */
+        bgez    t0, 9f
+        eva_entry
+        b       0f
+9:
+        /* Assume we came from YAMON... */
+        PTR_LA  v0, 0x9fc00534  /* YAMON print */
+        lw      v0, (v0)
+        move    a0, zero
+        PTR_LA  a1, nonsc_processor
+        jal     v0
+        PTR_LA  v0, 0x9fc00520  /* YAMON exit */
+        lw      v0, (v0)
+        li      a0, 1
+        jal     v0
+1:      b       1b
+        nop
+        __INITDATA
+nonsc_processor:
+        .asciz  "EVA kernel requires a MIPS core with Segment Control implemented\n"
+        __FINIT
+#endif /* CONFIG_EVA */
+0:
        .endm
 /*
 * Do SMP slave processor setup necessary before we can safely execute C code.
 */
        .macro  smp_slave_setup
+#ifdef CONFIG_EVA
+        sync
+        ehb
+        mfc0    t1, CP0_CONFIG
+        eva_entry
+#endif
        .endm
 #endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-malta/spaces.h b/arch/mips/include/asm/mach-malta/spaces.h
new file mode 100644
index 000000000000..d7e54971ec66
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/spaces.h
@@ -0,0 +1,46 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 Imagination Technologies Ltd.
+ */
+#ifndef _ASM_MALTA_SPACES_H
+#define _ASM_MALTA_SPACES_H
+#ifdef CONFIG_EVA
+/*
+ * Traditional Malta Board Memory Map for EVA
+ *
+ * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
+ * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
+ * 0x1c000000 - 0x1fffffff: I/O And Flash
+ * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
+ * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
+ *
+ * The kernel is still located in 0x80000000(kseg0). However,
+ * the physical mask has been shifted to 0x80000000 which exploits the alias
+ * on the Malta board. As a result of which, we override the __pa_symbol
+ * to peform direct mapping from virtual to physical addresses. In other
+ * words, the 0x80000000 virtual address maps to 0x80000000 physical address
+ * which in turn aliases to 0x0. We do this in order to be able to use a flat
+ * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
+ * 0x10000000 - 0x1fffffff.
+ * The last 64KB of physical memory are reserved for correct HIGHMEM
+ * macros arithmetics.
+ *
+ */
+#define PAGE_OFFSET     _AC(0x0, UL)
+#define PHYS_OFFSET     _AC(0x80000000, UL)
+#define HIGHMEM_START   _AC(0xffff0000, UL)
+#define __pa_symbol(x)  (RELOC_HIDE((unsigned long)(x), 0))
+#endif /* CONFIG_EVA */
+#include <asm/mach-generic/spaces.h>
+#endif /* _ASM_MALTA_SPACES_H */
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
index 2dbc7a8cec1a..fc946c835995 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
@@ -76,7 +76,7 @@ static inline void set_value_reg32(volatile u32 *const addr,
        __asm__ __volatile__(
        "       .set    push                            \n"
-        "       .set    mips3                           \n"
+        "       .set    arch=r4000                      \n"
        "1:     ll      %0, %1  # set_value_reg32       \n"
        "       and     %0, %2                          \n"
        "       or      %0, %3                          \n"
@@ -98,7 +98,7 @@ static inline void set_reg32(volatile u32 *const addr,
        __asm__ __volatile__(
        "       .set    push                            \n"
-        "       .set    mips3                           \n"
+        "       .set    arch=r4000                      \n"
        "1:     ll      %0, %1          # set_reg32     \n"
        "       or      %0, %2                          \n"
        "       sc      %0, %1                          \n"
@@ -119,7 +119,7 @@ static inline void clear_reg32(volatile u32 *const addr,
        __asm__ __volatile__(
        "       .set    push                            \n"
-        "       .set    mips3                           \n"
+        "       .set    arch=r4000                      \n"
        "1:     ll      %0, %1          # clear_reg32   \n"
        "       and     %0, %2                          \n"
        "       sc      %0, %1                          \n"
@@ -140,7 +140,7 @@ static inline void toggle_reg32(volatile u32 *const addr,
        __asm__ __volatile__(
        "       .set    push                            \n"
-        "       .set    mips3                           \n"
+        "       .set    arch=r4000                      \n"
        "1:     ll      %0, %1          # toggle_reg32  \n"
        "       xor     %0, %2                          \n"
        "       sc      %0, %1                          \n"
@@ -216,7 +216,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
 #define custom_read_reg32(address, tmp)                         \
        __asm__ __volatile__(                                   \
        "       .set    push                            \n"     \
-        "       .set    mips3                           \n"     \
+        "       .set    arch=r4000                      \n"     \
        "1:     ll      %0, %1  #custom_read_reg32      \n"     \
        "       .set    pop                             \n"     \
        : "=r" (tmp), "=m" (*address)                           \
@@ -225,7 +225,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
 #define custom_write_reg32(address, tmp)                        \
        __asm__ __volatile__(                                   \
        "       .set    push                            \n"     \
-        "       .set    mips3                           \n"     \
+        "       .set    arch=r4000                      \n"     \
        "       sc      %0, %1  #custom_write_reg32     \n"     \
        "       "__beqz"%0, 1b                          \n"     \
        "       nop                                     \n"     \
diff --git a/arch/mips/include/asm/mips-boards/malta.h b/arch/mips/include/asm/mips-boards/malta.h
index 722bc889eab5..fd9774269a5e 100644
--- a/arch/mips/include/asm/mips-boards/malta.h
+++ b/arch/mips/include/asm/mips-boards/malta.h
@@ -64,6 +64,11 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
 #define GIC_ADDRSPACE_SZ                (128 * 1024)
 /*
+ * CPC Specific definitions
+ */
+#define CPC_BASE_ADDR                   0x1bde0000
+/*
 * MSC01 BIU Specific definitions
 * FIXME : These should be elsewhere ?
 */
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index 836e2ede24de..9cf54041d416 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -50,4 +50,9 @@
 #define PIIX4_FUNC1_IDETIM_SECONDARY_HI         0x43
 #define   PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
+/* Power Management Configuration Space */
+#define PIIX4_FUNC3_PMBA                        0x40
+#define PIIX4_FUNC3_PMREGMISC                   0x80
+#define   PIIX4_FUNC3_PMREGMISC_EN                      (1 << 0)
 #endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
new file mode 100644
index 000000000000..6a9d2dd005ca
--- /dev/null
+++ b/arch/mips/include/asm/mips-cm.h
@@ -0,0 +1,322 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __MIPS_ASM_MIPS_CM_H__
+#define __MIPS_ASM_MIPS_CM_H__
+#include <linux/io.h>
+#include <linux/types.h>
+/* The base address of the CM GCR block */
+extern void __iomem *mips_cm_base;
+/* The base address of the CM L2-only sync region */
+extern void __iomem *mips_cm_l2sync_base;
+/**
+ * __mips_cm_phys_base - retrieve the physical base address of the CM
+ *
+ * This function returns the physical base address of the Coherence Manager
+ * global control block, or 0 if no Coherence Manager is present. It provides
+ * a default implementation which reads the CMGCRBase register where available,
+ * and may be overriden by platforms which determine this address in a
+ * different way by defining a function with the same prototype except for the
+ * name mips_cm_phys_base (without underscores).
+ */
+extern phys_t __mips_cm_phys_base(void);
+/**
+ * mips_cm_probe - probe for a Coherence Manager
+ *
+ * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
+ * is successfully detected, else -errno.
+ */
+#ifdef CONFIG_MIPS_CM
+extern int mips_cm_probe(void);
+#else
+static inline int mips_cm_probe(void)
+{
+        return -ENODEV;
+}
+#endif
+/**
+ * mips_cm_present - determine whether a Coherence Manager is present
+ *
+ * Returns true if a CM is present in the system, else false.
+ */
+static inline bool mips_cm_present(void)
+{
+#ifdef CONFIG_MIPS_CM
+        return mips_cm_base != NULL;
+#else
+        return false;
+#endif
+}
+/**
+ * mips_cm_has_l2sync - determine whether an L2-only sync region is present
+ *
+ * Returns true if the system implements an L2-only sync region, else false.
+ */
+static inline bool mips_cm_has_l2sync(void)
+{
+#ifdef CONFIG_MIPS_CM
+        return mips_cm_l2sync_base != NULL;
+#else
+        return false;
+#endif
+}
+/* Offsets to register blocks from the CM base address */
+#define MIPS_CM_GCB_OFS         0x0000 /* Global Control Block */
+#define MIPS_CM_CLCB_OFS        0x2000 /* Core Local Control Block */
+#define MIPS_CM_COCB_OFS        0x4000 /* Core Other Control Block */
+#define MIPS_CM_GDB_OFS         0x6000 /* Global Debug Block */
+/* Total size of the CM memory mapped registers */
+#define MIPS_CM_GCR_SIZE        0x8000
+/* Size of the L2-only sync region */
+#define MIPS_CM_L2SYNC_SIZE     0x1000
+/* Macros to ease the creation of register access functions */
+#define BUILD_CM_R_(name, off)                                  \
+static inline u32 *addr_gcr_##name(void)                        \
+{                                                               \
+        return (u32 *)(mips_cm_base + (off));                   \
+}                                                               \
+                                                                \
+static inline u32 read_gcr_##name(void)                         \
+{                                                               \
+        return __raw_readl(addr_gcr_##name());                  \
+}
+#define BUILD_CM__W(name, off)                                  \
+static inline void write_gcr_##name(u32 value)                  \
+{                                                               \
+        __raw_writel(value, addr_gcr_##name());                 \
+}
+#define BUILD_CM_RW(name, off)                                  \
+        BUILD_CM_R_(name, off)                                  \
+        BUILD_CM__W(name, off)
+#define BUILD_CM_Cx_R_(name, off)                               \
+        BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off))        \
+        BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off))
+#define BUILD_CM_Cx__W(name, off)                               \
+        BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off))        \
+        BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off))
+#define BUILD_CM_Cx_RW(name, off)                               \
+        BUILD_CM_Cx_R_(name, off)                               \
+        BUILD_CM_Cx__W(name, off)
+/* GCB register accessor functions */
+BUILD_CM_R_(config,             MIPS_CM_GCB_OFS + 0x00)
+BUILD_CM_RW(base,               MIPS_CM_GCB_OFS + 0x08)
+BUILD_CM_RW(access,             MIPS_CM_GCB_OFS + 0x20)
+BUILD_CM_R_(rev,                MIPS_CM_GCB_OFS + 0x30)
+BUILD_CM_RW(error_mask,         MIPS_CM_GCB_OFS + 0x40)
+BUILD_CM_RW(error_cause,        MIPS_CM_GCB_OFS + 0x48)
+BUILD_CM_RW(error_addr,         MIPS_CM_GCB_OFS + 0x50)
+BUILD_CM_RW(error_mult,         MIPS_CM_GCB_OFS + 0x58)
+BUILD_CM_RW(l2_only_sync_base,  MIPS_CM_GCB_OFS + 0x70)
+BUILD_CM_RW(gic_base,           MIPS_CM_GCB_OFS + 0x80)
+BUILD_CM_RW(cpc_base,           MIPS_CM_GCB_OFS + 0x88)
+BUILD_CM_RW(reg0_base,          MIPS_CM_GCB_OFS + 0x90)
+BUILD_CM_RW(reg0_mask,          MIPS_CM_GCB_OFS + 0x98)
+BUILD_CM_RW(reg1_base,          MIPS_CM_GCB_OFS + 0xa0)
+BUILD_CM_RW(reg1_mask,          MIPS_CM_GCB_OFS + 0xa8)
+BUILD_CM_RW(reg2_base,          MIPS_CM_GCB_OFS + 0xb0)
+BUILD_CM_RW(reg2_mask,          MIPS_CM_GCB_OFS + 0xb8)
+BUILD_CM_RW(reg3_base,          MIPS_CM_GCB_OFS + 0xc0)
+BUILD_CM_RW(reg3_mask,          MIPS_CM_GCB_OFS + 0xc8)
+BUILD_CM_R_(gic_status,         MIPS_CM_GCB_OFS + 0xd0)
+BUILD_CM_R_(cpc_status,         MIPS_CM_GCB_OFS + 0xf0)
+/* Core Local & Core Other register accessor functions */
+BUILD_CM_Cx_RW(reset_release,   0x00)
+BUILD_CM_Cx_RW(coherence,       0x08)
+BUILD_CM_Cx_R_(config,          0x10)
+BUILD_CM_Cx_RW(other,           0x18)
+BUILD_CM_Cx_RW(reset_base,      0x20)
+BUILD_CM_Cx_R_(id,              0x28)
+BUILD_CM_Cx_RW(reset_ext_base,  0x30)
+BUILD_CM_Cx_R_(tcid_0_priority, 0x40)
+BUILD_CM_Cx_R_(tcid_1_priority, 0x48)
+BUILD_CM_Cx_R_(tcid_2_priority, 0x50)
+BUILD_CM_Cx_R_(tcid_3_priority, 0x58)
+BUILD_CM_Cx_R_(tcid_4_priority, 0x60)
+BUILD_CM_Cx_R_(tcid_5_priority, 0x68)
+BUILD_CM_Cx_R_(tcid_6_priority, 0x70)
+BUILD_CM_Cx_R_(tcid_7_priority, 0x78)
+BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
+/* GCR_CONFIG register fields */
+#define CM_GCR_CONFIG_NUMIOCU_SHF               8
+#define CM_GCR_CONFIG_NUMIOCU_MSK               (_ULCAST_(0xf) << 8)
+#define CM_GCR_CONFIG_PCORES_SHF                0
+#define CM_GCR_CONFIG_PCORES_MSK                (_ULCAST_(0xff) << 0)
+/* GCR_BASE register fields */
+#define CM_GCR_BASE_GCRBASE_SHF                 15
+#define CM_GCR_BASE_GCRBASE_MSK                 (_ULCAST_(0x1ffff) << 15)
+#define CM_GCR_BASE_CMDEFTGT_SHF                0
+#define CM_GCR_BASE_CMDEFTGT_MSK                (_ULCAST_(0x3) << 0)
+#define  CM_GCR_BASE_CMDEFTGT_DISABLED          0
+#define  CM_GCR_BASE_CMDEFTGT_MEM               1
+#define  CM_GCR_BASE_CMDEFTGT_IOCU0             2
+#define  CM_GCR_BASE_CMDEFTGT_IOCU1             3
+/* GCR_ACCESS register fields */
+#define CM_GCR_ACCESS_ACCESSEN_SHF              0
+#define CM_GCR_ACCESS_ACCESSEN_MSK              (_ULCAST_(0xff) << 0)
+/* GCR_REV register fields */
+#define CM_GCR_REV_MAJOR_SHF                    8
+#define CM_GCR_REV_MAJOR_MSK                    (_ULCAST_(0xff) << 8)
+#define CM_GCR_REV_MINOR_SHF                    0
+#define CM_GCR_REV_MINOR_MSK                    (_ULCAST_(0xff) << 0)
+/* GCR_ERROR_CAUSE register fields */
+#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF          27
+#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK          (_ULCAST_(0x1f) << 27)
+#define CM_GCR_ERROR_CAUSE_ERRINFO_SHF          0
+#define CM_GCR_ERROR_CAUSE_ERRINGO_MSK          (_ULCAST_(0x7ffffff) << 0)
+/* GCR_ERROR_MULT register fields */
+#define CM_GCR_ERROR_MULT_ERR2ND_SHF            0
+#define CM_GCR_ERROR_MULT_ERR2ND_MSK            (_ULCAST_(0x1f) << 0)
+/* GCR_L2_ONLY_SYNC_BASE register fields */
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF   12
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK   (_ULCAST_(0xfffff) << 12)
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF     0
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK     (_ULCAST_(0x1) << 0)
+/* GCR_GIC_BASE register fields */
+#define CM_GCR_GIC_BASE_GICBASE_SHF             17
+#define CM_GCR_GIC_BASE_GICBASE_MSK             (_ULCAST_(0x7fff) << 17)
+#define CM_GCR_GIC_BASE_GICEN_SHF               0
+#define CM_GCR_GIC_BASE_GICEN_MSK               (_ULCAST_(0x1) << 0)
+/* GCR_CPC_BASE register fields */
+#define CM_GCR_CPC_BASE_CPCBASE_SHF             17
+#define CM_GCR_CPC_BASE_CPCBASE_MSK             (_ULCAST_(0x7fff) << 17)
+#define CM_GCR_CPC_BASE_CPCEN_SHF               0
+#define CM_GCR_CPC_BASE_CPCEN_MSK               (_ULCAST_(0x1) << 0)
+/* GCR_REGn_BASE register fields */
+#define CM_GCR_REGn_BASE_BASEADDR_SHF           16
+#define CM_GCR_REGn_BASE_BASEADDR_MSK           (_ULCAST_(0xffff) << 16)
+/* GCR_REGn_MASK register fields */
+#define CM_GCR_REGn_MASK_ADDRMASK_SHF           16
+#define CM_GCR_REGn_MASK_ADDRMASK_MSK           (_ULCAST_(0xffff) << 16)
+#define CM_GCR_REGn_MASK_CCAOVR_SHF             5
+#define CM_GCR_REGn_MASK_CCAOVR_MSK             (_ULCAST_(0x3) << 5)
+#define CM_GCR_REGn_MASK_CCAOVREN_SHF           4
+#define CM_GCR_REGn_MASK_CCAOVREN_MSK           (_ULCAST_(0x1) << 4)
+#define CM_GCR_REGn_MASK_DROPL2_SHF             2
+#define CM_GCR_REGn_MASK_DROPL2_MSK             (_ULCAST_(0x1) << 2)
+#define CM_GCR_REGn_MASK_CMTGT_SHF              0
+#define CM_GCR_REGn_MASK_CMTGT_MSK              (_ULCAST_(0x3) << 0)
+#define  CM_GCR_REGn_MASK_CMTGT_DISABLED        (_ULCAST_(0x0) << 0)
+#define  CM_GCR_REGn_MASK_CMTGT_MEM             (_ULCAST_(0x1) << 0)
+#define  CM_GCR_REGn_MASK_CMTGT_IOCU0           (_ULCAST_(0x2) << 0)
+#define  CM_GCR_REGn_MASK_CMTGT_IOCU1           (_ULCAST_(0x3) << 0)
+/* GCR_GIC_STATUS register fields */
+#define CM_GCR_GIC_STATUS_EX_SHF                0
+#define CM_GCR_GIC_STATUS_EX_MSK                (_ULCAST_(0x1) << 0)
+/* GCR_CPC_STATUS register fields */
+#define CM_GCR_CPC_STATUS_EX_SHF                0
+#define CM_GCR_CPC_STATUS_EX_MSK                (_ULCAST_(0x1) << 0)
+/* GCR_Cx_COHERENCE register fields */
+#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF     0
+#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK     (_ULCAST_(0xff) << 0)
+/* GCR_Cx_CONFIG register fields */
+#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF           10
+#define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK           (_ULCAST_(0x3) << 10)
+#define CM_GCR_Cx_CONFIG_PVPE_SHF               0
+#define CM_GCR_Cx_CONFIG_PVPE_MSK               (_ULCAST_(0x1ff) << 0)
+/* GCR_Cx_OTHER register fields */
+#define CM_GCR_Cx_OTHER_CORENUM_SHF             16
+#define CM_GCR_Cx_OTHER_CORENUM_MSK             (_ULCAST_(0xffff) << 16)
+/* GCR_Cx_RESET_BASE register fields */
+#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF     12
+#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK     (_ULCAST_(0xfffff) << 12)
+/* GCR_Cx_RESET_EXT_BASE register fields */
+#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF   31
+#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK   (_ULCAST_(0x1) << 31)
+#define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF        30
+#define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK        (_ULCAST_(0x1) << 30)
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20)
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF   1
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK   (_ULCAST_(0x7f) << 1)
+#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF    0
+#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK    (_ULCAST_(0x1) << 0)
+/**
+ * mips_cm_numcores - return the number of cores present in the system
+ *
+ * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
+ * zero if no Coherence Manager is present.
+ */
+static inline unsigned mips_cm_numcores(void)
+{
+        if (!mips_cm_present())
+                return 0;
+        return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK)
+                >> CM_GCR_CONFIG_PCORES_SHF) + 1;
+}
+/**
+ * mips_cm_numiocu - return the number of IOCUs present in the system
+ *
+ * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
+ * if no Coherence Manager is present.
+ */
+static inline unsigned mips_cm_numiocu(void)
+{
+        if (!mips_cm_present())
+                return 0;
+        return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK)
+                >> CM_GCR_CONFIG_NUMIOCU_SHF;
+}
+/**
+ * mips_cm_l2sync - perform an L2-only sync operation
+ *
+ * If an L2-only sync region is present in the system then this function
+ * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
+ */
+static inline int mips_cm_l2sync(void)
+{
+        if (!mips_cm_has_l2sync())
+                return -ENODEV;
+        writel(0, mips_cm_l2sync_base);
+        return 0;
+}
+#endif /* __MIPS_ASM_MIPS_CM_H__ */
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h
new file mode 100644
index 000000000000..988507e46d42
--- /dev/null
+++ b/arch/mips/include/asm/mips-cpc.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __MIPS_ASM_MIPS_CPC_H__
+#define __MIPS_ASM_MIPS_CPC_H__
+#include <linux/io.h>
+#include <linux/types.h>
+/* The base address of the CPC registers */
+extern void __iomem *mips_cpc_base;
+/**
+ * mips_cpc_default_phys_base - retrieve the default physical base address of
+ *                              the CPC
+ *
+ * Returns the default physical base address of the Cluster Power Controller
+ * memory mapped registers. This is platform dependant & must therefore be
+ * implemented per-platform.
+ */
+extern phys_t mips_cpc_default_phys_base(void);
+/**
+ * mips_cpc_phys_base - retrieve the physical base address of the CPC
+ *
+ * This function returns the physical base address of the Cluster Power
+ * Controller memory mapped registers, or 0 if no Cluster Power Controller
+ * is present. It may be overriden by individual platforms which determine
+ * this address in a different way.
+ */
+extern phys_t __weak mips_cpc_phys_base(void);
+/**
+ * mips_cpc_probe - probe for a Cluster Power Controller
+ *
+ * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
+ * a CPC is successfully detected, else -errno.
+ */
+#ifdef CONFIG_MIPS_CPC
+extern int mips_cpc_probe(void);
+#else
+static inline int mips_cpc_probe(void)
+{
+        return -ENODEV;
+}
+#endif
+/**
+ * mips_cpc_present - determine whether a Cluster Power Controller is present
+ *
+ * Returns true if a CPC is present in the system, else false.
+ */
+static inline bool mips_cpc_present(void)
+{
+#ifdef CONFIG_MIPS_CPC
+        return mips_cpc_base != NULL;
+#else
+        return false;
+#endif
+}
+/* Offsets from the CPC base address to various control blocks */
+#define MIPS_CPC_GCB_OFS        0x0000
+#define MIPS_CPC_CLCB_OFS       0x2000
+#define MIPS_CPC_COCB_OFS       0x4000
+/* Macros to ease the creation of register access functions */
+#define BUILD_CPC_R_(name, off) \
+static inline u32 read_cpc_##name(void)                         \
+{                                                               \
+        return __raw_readl(mips_cpc_base + (off));              \
+}
+#define BUILD_CPC__W(name, off) \
+static inline void write_cpc_##name(u32 value)                  \
+{                                                               \
+        __raw_writel(value, mips_cpc_base + (off));             \
+}
+#define BUILD_CPC_RW(name, off)                                 \
+        BUILD_CPC_R_(name, off)                                 \
+        BUILD_CPC__W(name, off)
+#define BUILD_CPC_Cx_R_(name, off)                              \
+        BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off))      \
+        BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off))
+#define BUILD_CPC_Cx__W(name, off)                              \
+        BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off))      \
+        BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off))
+#define BUILD_CPC_Cx_RW(name, off)                              \
+        BUILD_CPC_Cx_R_(name, off)                              \
+        BUILD_CPC_Cx__W(name, off)
+/* GCB register accessor functions */
+BUILD_CPC_RW(access,            MIPS_CPC_GCB_OFS + 0x00)
+BUILD_CPC_RW(seqdel,            MIPS_CPC_GCB_OFS + 0x08)
+BUILD_CPC_RW(rail,              MIPS_CPC_GCB_OFS + 0x10)
+BUILD_CPC_RW(resetlen,          MIPS_CPC_GCB_OFS + 0x18)
+BUILD_CPC_R_(revision,          MIPS_CPC_GCB_OFS + 0x20)
+/* Core Local & Core Other accessor functions */
+BUILD_CPC_Cx_RW(cmd,            0x00)
+BUILD_CPC_Cx_RW(stat_conf,      0x08)
+BUILD_CPC_Cx_RW(other,          0x10)
+/* CPC_Cx_CMD register fields */
+#define CPC_Cx_CMD_SHF                          0
+#define CPC_Cx_CMD_MSK                          (_ULCAST_(0xf) << 0)
+#define  CPC_Cx_CMD_CLOCKOFF                    (_ULCAST_(0x1) << 0)
+#define  CPC_Cx_CMD_PWRDOWN                     (_ULCAST_(0x2) << 0)
+#define  CPC_Cx_CMD_PWRUP                       (_ULCAST_(0x3) << 0)
+#define  CPC_Cx_CMD_RESET                       (_ULCAST_(0x4) << 0)
+/* CPC_Cx_STAT_CONF register fields */
+#define CPC_Cx_STAT_CONF_PWRUPE_SHF             23
+#define CPC_Cx_STAT_CONF_PWRUPE_MSK             (_ULCAST_(0x1) << 23)
+#define CPC_Cx_STAT_CONF_SEQSTATE_SHF           19
+#define CPC_Cx_STAT_CONF_SEQSTATE_MSK           (_ULCAST_(0xf) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D0           (_ULCAST_(0x0) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U0           (_ULCAST_(0x1) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U1           (_ULCAST_(0x2) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U2           (_ULCAST_(0x3) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U3           (_ULCAST_(0x4) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U4           (_ULCAST_(0x5) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U5           (_ULCAST_(0x6) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U6           (_ULCAST_(0x7) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D1           (_ULCAST_(0x8) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D3           (_ULCAST_(0x9) << 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D2           (_ULCAST_(0xa) << 19)
+#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF        17
+#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK        (_ULCAST_(0x1) << 17)
+#define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF         16
+#define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK         (_ULCAST_(0x1) << 16)
+#define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF        15
+#define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK        (_ULCAST_(0x1) << 15)
+/* CPC_Cx_OTHER register fields */
+#define CPC_Cx_OTHER_CORENUM_SHF                16
+#define CPC_Cx_OTHER_CORENUM_MSK                (_ULCAST_(0xff) << 16)
+#endif /* __MIPS_ASM_MIPS_CPC_H__ */
diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h
index ac7935203f89..a3df0c3faa0e 100644
--- a/arch/mips/include/asm/mips_mt.h
+++ b/arch/mips/include/asm/mips_mt.h
@@ -18,7 +18,12 @@ extern cpumask_t mt_fpu_cpumask;
 extern unsigned long mt_fpemul_threshold;
 extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value);
+#ifdef CONFIG_MIPS_MT
 extern void mips_mt_set_cpuoptions(void);
+#else
+static inline void mips_mt_set_cpuoptions(void) { }
+#endif
 struct class;
 extern struct class *mt_class;
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index 38b7704ee376..6efa79a27b6a 100644
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -176,6 +176,17 @@
 #ifndef __ASSEMBLY__
+static inline unsigned core_nvpes(void)
+{
+        unsigned conf0;
+        if (!cpu_has_mipsmt)
+                return 1;
+        conf0 = read_c0_mvpconf0();
+        return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
+}
 static inline unsigned int dvpe(void)
 {
        int res = 0;
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4294bc..3e025b5311db 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -568,11 +568,23 @@
 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA_SHF       7
+#define MIPS_CONF1_DA_SZ        3
 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
+#define MIPS_CONF1_DL_SHF       10
+#define MIPS_CONF1_DL_SZ        3
 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS_SHF       13
+#define MIPS_CONF1_DS_SZ        3
 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA_SHF       16
+#define MIPS_CONF1_IA_SZ        3
 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL_SHF       19
+#define MIPS_CONF1_IL_SZ        3
 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS_SHF       22
+#define MIPS_CONF1_IS_SZ        3
 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 #define MIPS_CONF1_TLBS_SHIFT   (25)
 #define MIPS_CONF1_TLBS_SIZE    (6)
@@ -653,9 +665,16 @@
 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
+#define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
+/* CMGCRBase bit definitions */
+#define MIPS_CMGCRB_BASE        11
+#define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 /*
 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 */
@@ -1010,6 +1029,8 @@ do {									\
 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
+#define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
 #define read_c0_config()        __read_32bit_c0_register($16, 0)
 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
@@ -1883,6 +1904,7 @@ change_c0_##name(unsigned int change, unsigned int newbits)	\
 __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
+__BUILD_SET_C0(config5)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 44b705d08262..c2edae382d5d 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -126,6 +126,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "LOONGSON1 "
 #elif defined CONFIG_CPU_LOONGSON2
 #define MODULE_PROC_FAMILY "LOONGSON2 "
+#elif defined CONFIG_CPU_LOONGSON3
+#define MODULE_PROC_FAMILY "LOONGSON3 "
 #elif defined CONFIG_CPU_CAVIUM_OCTEON
 #define MODULE_PROC_FAMILY "OCTEON "
 #elif defined CONFIG_CPU_XLR
diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
new file mode 100644
index 000000000000..a2aba6c3ec05
--- /dev/null
+++ b/arch/mips/include/asm/msa.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_MSA_H
+#define _ASM_MSA_H
+#include <asm/mipsregs.h>
+extern void _save_msa(struct task_struct *);
+extern void _restore_msa(struct task_struct *);
+static inline void enable_msa(void)
+{
+        if (cpu_has_msa) {
+                set_c0_config5(MIPS_CONF5_MSAEN);
+                enable_fpu_hazard();
+        }
+}
+static inline void disable_msa(void)
+{
+        if (cpu_has_msa) {
+                clear_c0_config5(MIPS_CONF5_MSAEN);
+                disable_fpu_hazard();
+        }
+}
+static inline int is_msa_enabled(void)
+{
+        if (!cpu_has_msa)
+                return 0;
+        return read_c0_config5() & MIPS_CONF5_MSAEN;
+}
+static inline int thread_msa_context_live(void)
+{
+        /*
+         * Check cpu_has_msa only if it's a constant. This will allow the
+         * compiler to optimise out code for CPUs without MSA without adding
+         * an extra redundant check for CPUs with MSA.
+         */
+        if (__builtin_constant_p(cpu_has_msa) && !cpu_has_msa)
+                return 0;
+        return test_thread_flag(TIF_MSA_CTX_LIVE);
+}
+static inline void save_msa(struct task_struct *t)
+{
+        if (cpu_has_msa)
+                _save_msa(t);
+}
+static inline void restore_msa(struct task_struct *t)
+{
+        if (cpu_has_msa)
+                _restore_msa(t);
+}
+#ifdef TOOLCHAIN_SUPPORTS_MSA
+#define __BUILD_MSA_CTL_REG(name, cs)                           \
+static inline unsigned int read_msa_##name(void)                \
+{                                                               \
+        unsigned int reg;                                       \
+        __asm__ __volatile__(                                   \
+        "       .set    push\n"                                 \
+        "       .set    msa\n"                                  \
+        "       cfcmsa  %0, $" #cs "\n"                         \
+        "       .set    pop\n"                                  \
+        : "=r"(reg));                                           \
+        return reg;                                             \
+}                                                               \
+                                                                \
+static inline void write_msa_##name(unsigned int val)           \
+{                                                               \
+        __asm__ __volatile__(                                   \
+        "       .set    push\n"                                 \
+        "       .set    msa\n"                                  \
+        "       cfcmsa  $" #cs ", %0\n"                         \
+        "       .set    pop\n"                                  \
+        : : "r"(val));                                          \
+}
+#else /* !TOOLCHAIN_SUPPORTS_MSA */
+/*
+ * Define functions using .word for the c[ft]cmsa instructions in order to
+ * allow compilation with toolchains that do not support MSA. Once all
+ * toolchains in use support MSA these can be removed.
+ */
+#define __BUILD_MSA_CTL_REG(name, cs)                           \
+static inline unsigned int read_msa_##name(void)                \
+{                                                               \
+        unsigned int reg;                                       \
+        __asm__ __volatile__(                                   \
+        "       .set    push\n"                                 \
+        "       .set    noat\n"                                 \
+        "       .word   0x787e0059 | (" #cs " << 11)\n"         \
+        "       move    %0, $1\n"                               \
+        "       .set    pop\n"                                  \
+        : "=r"(reg));                                           \
+        return reg;                                             \
+}                                                               \
+                                                                \
+static inline void write_msa_##name(unsigned int val)           \
+{                                                               \
+        __asm__ __volatile__(                                   \
+        "       .set    push\n"                                 \
+        "       .set    noat\n"                                 \
+        "       move    $1, %0\n"                               \
+        "       .word   0x783e0819 | (" #cs " << 6)\n"          \
+        "       .set    pop\n"                                  \
+        : : "r"(val));                                          \
+}
+#endif /* !TOOLCHAIN_SUPPORTS_MSA */
+#define MSA_IR          0
+#define MSA_CSR         1
+#define MSA_ACCESS      2
+#define MSA_SAVE        3
+#define MSA_MODIFY      4
+#define MSA_REQUEST     5
+#define MSA_MAP         6
+#define MSA_UNMAP       7
+__BUILD_MSA_CTL_REG(ir, 0)
+__BUILD_MSA_CTL_REG(csr, 1)
+__BUILD_MSA_CTL_REG(access, 2)
+__BUILD_MSA_CTL_REG(save, 3)
+__BUILD_MSA_CTL_REG(modify, 4)
+__BUILD_MSA_CTL_REG(request, 5)
+__BUILD_MSA_CTL_REG(map, 6)
+__BUILD_MSA_CTL_REG(unmap, 7)
+/* MSA Implementation Register (MSAIR) */
+#define MSA_IR_REVB             0
+#define MSA_IR_REVF             (_ULCAST_(0xff) << MSA_IR_REVB)
+#define MSA_IR_PROCB            8
+#define MSA_IR_PROCF            (_ULCAST_(0xff) << MSA_IR_PROCB)
+#define MSA_IR_WRPB             16
+#define MSA_IR_WRPF             (_ULCAST_(0x1) << MSA_IR_WRPB)
+/* MSA Control & Status Register (MSACSR) */
+#define MSA_CSR_RMB             0
+#define MSA_CSR_RMF             (_ULCAST_(0x3) << MSA_CSR_RMB)
+#define MSA_CSR_RM_NEAREST      0
+#define MSA_CSR_RM_TO_ZERO      1
+#define MSA_CSR_RM_TO_POS       2
+#define MSA_CSR_RM_TO_NEG       3
+#define MSA_CSR_FLAGSB          2
+#define MSA_CSR_FLAGSF          (_ULCAST_(0x1f) << MSA_CSR_FLAGSB)
+#define MSA_CSR_FLAGS_IB        2
+#define MSA_CSR_FLAGS_IF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_IB)
+#define MSA_CSR_FLAGS_UB        3
+#define MSA_CSR_FLAGS_UF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_UB)
+#define MSA_CSR_FLAGS_OB        4
+#define MSA_CSR_FLAGS_OF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_OB)
+#define MSA_CSR_FLAGS_ZB        5
+#define MSA_CSR_FLAGS_ZF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_ZB)
+#define MSA_CSR_FLAGS_VB        6
+#define MSA_CSR_FLAGS_VF        (_ULCAST_(0x1) << MSA_CSR_FLAGS_VB)
+#define MSA_CSR_ENABLESB        7
+#define MSA_CSR_ENABLESF        (_ULCAST_(0x1f) << MSA_CSR_ENABLESB)
+#define MSA_CSR_ENABLES_IB      7
+#define MSA_CSR_ENABLES_IF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_IB)
+#define MSA_CSR_ENABLES_UB      8
+#define MSA_CSR_ENABLES_UF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_UB)
+#define MSA_CSR_ENABLES_OB      9
+#define MSA_CSR_ENABLES_OF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_OB)
+#define MSA_CSR_ENABLES_ZB      10
+#define MSA_CSR_ENABLES_ZF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_ZB)
+#define MSA_CSR_ENABLES_VB      11
+#define MSA_CSR_ENABLES_VF      (_ULCAST_(0x1) << MSA_CSR_ENABLES_VB)
+#define MSA_CSR_CAUSEB          12
+#define MSA_CSR_CAUSEF          (_ULCAST_(0x3f) << MSA_CSR_CAUSEB)
+#define MSA_CSR_CAUSE_IB        12
+#define MSA_CSR_CAUSE_IF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_IB)
+#define MSA_CSR_CAUSE_UB        13
+#define MSA_CSR_CAUSE_UF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_UB)
+#define MSA_CSR_CAUSE_OB        14
+#define MSA_CSR_CAUSE_OF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_OB)
+#define MSA_CSR_CAUSE_ZB        15
+#define MSA_CSR_CAUSE_ZF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_ZB)
+#define MSA_CSR_CAUSE_VB        16
+#define MSA_CSR_CAUSE_VF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_VB)
+#define MSA_CSR_CAUSE_EB        17
+#define MSA_CSR_CAUSE_EF        (_ULCAST_(0x1) << MSA_CSR_CAUSE_EB)
+#define MSA_CSR_NXB             18
+#define MSA_CSR_NXF             (_ULCAST_(0x1) << MSA_CSR_NXB)
+#define MSA_CSR_FSB             24
+#define MSA_CSR_FSF             (_ULCAST_(0x1) << MSA_CSR_FSB)
+#endif /* _ASM_MSA_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 5e08bcc74897..5699ec3a71af 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -190,7 +190,9 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 * https://patchwork.linux-mips.org/patch/1541/
 */
+#ifndef __pa_symbol
 #define __pa_symbol(x)  __pa(RELOC_HIDE((unsigned long)(x), 0))
+#endif
 #define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 32aea4852fb0..e592f3687d6f 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -235,6 +235,15 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
+#elif defined(CONFIG_CPU_LOONGSON3)
+/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
+#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)  /* LOONGSON       */
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
+#define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* LOONGSON       */
 #else
 #define _CACHE_CACHABLE_NO_WA       (0<<_CACHE_SHIFT)  /* R4600 only      */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 3605b844ad87..ad70cba8daff 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -97,18 +97,48 @@ extern unsigned int vced_count, vcei_count;
 #define NUM_FPU_REGS    32
-typedef __u64 fpureg_t;
+#ifdef CONFIG_CPU_HAS_MSA
+# define FPU_REG_WIDTH  128
+#else
+# define FPU_REG_WIDTH  64
+#endif
+union fpureg {
+        __u32   val32[FPU_REG_WIDTH / 32];
+        __u64   val64[FPU_REG_WIDTH / 64];
+};
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+# define FPR_IDX(width, idx)    (idx)
+#else
+# define FPR_IDX(width, idx)    ((FPU_REG_WIDTH / (width)) - 1 - (idx))
+#endif
+#define BUILD_FPR_ACCESS(width) \
+static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)  \
+{                                                                       \
+        return fpr->val##width[FPR_IDX(width, idx)];                    \
+}                                                                       \
+                                                                        \
+static inline void set_fpr##width(union fpureg *fpr, unsigned idx,      \
+                                  u##width val)                         \
+{                                                                       \
+        fpr->val##width[FPR_IDX(width, idx)] = val;                     \
+}
+BUILD_FPR_ACCESS(32)
+BUILD_FPR_ACCESS(64)
 /*
- * It would be nice to add some more fields for emulator statistics, but there
+ * It would be nice to add some more fields for emulator statistics,
- * are a number of fixed offsets in offset.h and elsewhere that would have to
+ * the additional information is private to the FPU emulator for now.
- * be recalculated by hand.  So the additional information will be private to
+ * See arch/mips/include/asm/fpu_emulator.h.
- * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 */
 struct mips_fpu_struct {
-        fpureg_t        fpr[NUM_FPU_REGS];
+        union fpureg    fpr[NUM_FPU_REGS];
        unsigned int    fcr31;
+        unsigned int    msacsr;
 };
 #define NUM_DSP_REGS   6
@@ -284,8 +314,9 @@ struct thread_struct {
         * Saved FPU/FPU emulator stuff                         \
         */                                                     \
        .fpu                    = {                             \
-                .fpr            = {0,},                         \
+                .fpr            = {{{0,},},},                   \
                .fcr31          = 0,                            \
+                .msacsr         = 0,                            \
        },                                                      \
        /*                                                      \
         * FPU affinity state (null if not FPAFF)               \
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 7bba9da110af..bf1ac8d35783 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -82,7 +82,7 @@ static inline long regs_return_value(struct pt_regs *regs)
 #define instruction_pointer(regs) ((regs)->cp0_epc)
 #define profile_pc(regs) instruction_pointer(regs)
-extern asmlinkage void syscall_trace_enter(struct pt_regs *regs);
+extern asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall);
 extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
 extern void die(const char *, struct pt_regs *) __noreturn;
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index c84caddb8bde..ca64cbe44493 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -17,6 +17,7 @@
 #include <asm/cpu-features.h>
 #include <asm/cpu-type.h>
 #include <asm/mipsmtregs.h>
+#include <asm/uaccess.h> /* for segment_eq() */
 /*
 * This macro return a properly sign-extended address suitable as base address
@@ -35,7 +36,7 @@
        __asm__ __volatile__(                                           \
        "       .set    push                                    \n"     \
        "       .set    noreorder                               \n"     \
-        "       .set    mips3\n\t                               \n"     \
+        "       .set    arch=r4000                              \n"     \
        "       cache   %0, %1                                  \n"     \
        "       .set    pop                                     \n"     \
        :                                                               \
@@ -203,7 +204,7 @@ static inline void flush_scache_line(unsigned long addr)
        __asm__ __volatile__(                                   \
        "       .set    push                    \n"             \
        "       .set    noreorder               \n"             \
-        "       .set    mips3                   \n"             \
+        "       .set    arch=r4000              \n"             \
        "1:     cache   %0, (%1)                \n"             \
        "2:     .set    pop                     \n"             \
        "       .section __ex_table,\"a\"       \n"             \
@@ -212,6 +213,20 @@ static inline void flush_scache_line(unsigned long addr)
        :                                                       \
        : "i" (op), "r" (addr))
+#define protected_cachee_op(op,addr)                            \
+        __asm__ __volatile__(                                   \
+        "       .set    push                    \n"             \
+        "       .set    noreorder               \n"             \
+        "       .set    mips0                   \n"             \
+        "       .set    eva                     \n"             \
+        "1:     cachee  %0, (%1)                \n"             \
+        "2:     .set    pop                     \n"             \
+        "       .section __ex_table,\"a\"       \n"             \
+        "       "STR(PTR)" 1b, 2b               \n"             \
+        "       .previous"                                      \
+        :                                                       \
+        : "i" (op), "r" (addr))
 /*
 * The next two are for badland addresses like signal trampolines.
 */
@@ -223,7 +238,11 @@ static inline void protected_flush_icache_line(unsigned long addr)
                break;
        default:
+#ifdef CONFIG_EVA
+                protected_cachee_op(Hit_Invalidate_I, addr);
+#else
                protected_cache_op(Hit_Invalidate_I, addr);
+#endif
                break;
        }
 }
@@ -356,6 +375,91 @@ static inline void invalidate_tcache_page(unsigned long addr)
                : "r" (base),                                           \
                  "i" (op));
+/*
+ * Perform the cache operation specified by op using a user mode virtual
+ * address while in kernel mode.
+ */
+#define cache16_unroll32_user(base,op)                                  \
+        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set noreorder                                  \n"     \
+        "       .set mips0                                      \n"     \
+        "       .set eva                                        \n"     \
+        "       cachee %1, 0x000(%0); cachee %1, 0x010(%0)      \n"     \
+        "       cachee %1, 0x020(%0); cachee %1, 0x030(%0)      \n"     \
+        "       cachee %1, 0x040(%0); cachee %1, 0x050(%0)      \n"     \
+        "       cachee %1, 0x060(%0); cachee %1, 0x070(%0)      \n"     \
+        "       cachee %1, 0x080(%0); cachee %1, 0x090(%0)      \n"     \
+        "       cachee %1, 0x0a0(%0); cachee %1, 0x0b0(%0)      \n"     \
+        "       cachee %1, 0x0c0(%0); cachee %1, 0x0d0(%0)      \n"     \
+        "       cachee %1, 0x0e0(%0); cachee %1, 0x0f0(%0)      \n"     \
+        "       cachee %1, 0x100(%0); cachee %1, 0x110(%0)      \n"     \
+        "       cachee %1, 0x120(%0); cachee %1, 0x130(%0)      \n"     \
+        "       cachee %1, 0x140(%0); cachee %1, 0x150(%0)      \n"     \
+        "       cachee %1, 0x160(%0); cachee %1, 0x170(%0)      \n"     \
+        "       cachee %1, 0x180(%0); cachee %1, 0x190(%0)      \n"     \
+        "       cachee %1, 0x1a0(%0); cachee %1, 0x1b0(%0)      \n"     \
+        "       cachee %1, 0x1c0(%0); cachee %1, 0x1d0(%0)      \n"     \
+        "       cachee %1, 0x1e0(%0); cachee %1, 0x1f0(%0)      \n"     \
+        "       .set pop                                        \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+#define cache32_unroll32_user(base, op)                                 \
+        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set noreorder                                  \n"     \
+        "       .set mips0                                      \n"     \
+        "       .set eva                                        \n"     \
+        "       cachee %1, 0x000(%0); cachee %1, 0x020(%0)      \n"     \
+        "       cachee %1, 0x040(%0); cachee %1, 0x060(%0)      \n"     \
+        "       cachee %1, 0x080(%0); cachee %1, 0x0a0(%0)      \n"     \
+        "       cachee %1, 0x0c0(%0); cachee %1, 0x0e0(%0)      \n"     \
+        "       cachee %1, 0x100(%0); cachee %1, 0x120(%0)      \n"     \
+        "       cachee %1, 0x140(%0); cachee %1, 0x160(%0)      \n"     \
+        "       cachee %1, 0x180(%0); cachee %1, 0x1a0(%0)      \n"     \
+        "       cachee %1, 0x1c0(%0); cachee %1, 0x1e0(%0)      \n"     \
+        "       cachee %1, 0x200(%0); cachee %1, 0x220(%0)      \n"     \
+        "       cachee %1, 0x240(%0); cachee %1, 0x260(%0)      \n"     \
+        "       cachee %1, 0x280(%0); cachee %1, 0x2a0(%0)      \n"     \
+        "       cachee %1, 0x2c0(%0); cachee %1, 0x2e0(%0)      \n"     \
+        "       cachee %1, 0x300(%0); cachee %1, 0x320(%0)      \n"     \
+        "       cachee %1, 0x340(%0); cachee %1, 0x360(%0)      \n"     \
+        "       cachee %1, 0x380(%0); cachee %1, 0x3a0(%0)      \n"     \
+        "       cachee %1, 0x3c0(%0); cachee %1, 0x3e0(%0)      \n"     \
+        "       .set pop                                        \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+#define cache64_unroll32_user(base, op)                                 \
+        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set noreorder                                  \n"     \
+        "       .set mips0                                      \n"     \
+        "       .set eva                                        \n"     \
+        "       cachee %1, 0x000(%0); cachee %1, 0x040(%0)      \n"     \
+        "       cachee %1, 0x080(%0); cachee %1, 0x0c0(%0)      \n"     \
+        "       cachee %1, 0x100(%0); cachee %1, 0x140(%0)      \n"     \
+        "       cachee %1, 0x180(%0); cachee %1, 0x1c0(%0)      \n"     \
+        "       cachee %1, 0x200(%0); cachee %1, 0x240(%0)      \n"     \
+        "       cachee %1, 0x280(%0); cachee %1, 0x2c0(%0)      \n"     \
+        "       cachee %1, 0x300(%0); cachee %1, 0x340(%0)      \n"     \
+        "       cachee %1, 0x380(%0); cachee %1, 0x3c0(%0)      \n"     \
+        "       cachee %1, 0x400(%0); cachee %1, 0x440(%0)      \n"     \
+        "       cachee %1, 0x480(%0); cachee %1, 0x4c0(%0)      \n"     \
+        "       cachee %1, 0x500(%0); cachee %1, 0x540(%0)      \n"     \
+        "       cachee %1, 0x580(%0); cachee %1, 0x5c0(%0)      \n"     \
+        "       cachee %1, 0x600(%0); cachee %1, 0x640(%0)      \n"     \
+        "       cachee %1, 0x680(%0); cachee %1, 0x6c0(%0)      \n"     \
+        "       cachee %1, 0x700(%0); cachee %1, 0x740(%0)      \n"     \
+        "       cachee %1, 0x780(%0); cachee %1, 0x7c0(%0)      \n"     \
+        "       .set pop                                        \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
 #define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)    \
 static inline void extra##blast_##pfx##cache##lsize(void)               \
@@ -429,6 +533,32 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32
 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
+#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
+static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
+{                                                                       \
+        unsigned long start = page;                                     \
+        unsigned long end = page + PAGE_SIZE;                           \
+                                                                        \
+        __##pfx##flush_prologue                                         \
+                                                                        \
+        do {                                                            \
+                cache##lsize##_unroll32_user(start, hitop);             \
+                start += lsize * 32;                                    \
+        } while (start < end);                                          \
+                                                                        \
+        __##pfx##flush_epilogue                                         \
+}
+__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
+                         16)
+__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
+__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
+                         32)
+__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
+__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
+                         64)
+__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 /* build blast_xxx_range, protected_blast_xxx_range */
 #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)        \
 static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
@@ -450,12 +580,51 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
        __##pfx##flush_epilogue                                         \
 }
+#ifndef CONFIG_EVA
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
+#else
+#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop)                \
+static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
+                                                        unsigned long end) \
+{                                                                       \
+        unsigned long lsize = cpu_##desc##_line_size();                 \
+        unsigned long addr = start & ~(lsize - 1);                      \
+        unsigned long aend = (end - 1) & ~(lsize - 1);                  \
+                                                                        \
+        __##pfx##flush_prologue                                         \
+                                                                        \
+        if (segment_eq(get_fs(), USER_DS)) {                            \
+                while (1) {                                             \
+                        protected_cachee_op(hitop, addr);               \
+                        if (addr == aend)                               \
+                                break;                                  \
+                        addr += lsize;                                  \
+                }                                                       \
+        } else {                                                        \
+                while (1) {                                             \
+                        protected_cache_op(hitop, addr);                \
+                        if (addr == aend)                               \
+                                break;                                  \
+                        addr += lsize;                                  \
+                }                                                       \
+                                                                        \
+        }                                                               \
+        __##pfx##flush_epilogue                                         \
+}
+__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
+__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
+#endif
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
        protected_, loongson2_)
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
 /* blast_inv_dcache_range */
 __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
diff --git a/arch/mips/include/asm/sigcontext.h b/arch/mips/include/asm/sigcontext.h
index eeeb0f48c767..f54bdbe85c0d 100644
--- a/arch/mips/include/asm/sigcontext.h
+++ b/arch/mips/include/asm/sigcontext.h
@@ -32,6 +32,8 @@ struct sigcontext32 {
        __u32           sc_lo2;
        __u32           sc_hi3;
        __u32           sc_lo3;
+        __u64           sc_msaregs[32]; /* Most significant 64 bits */
+        __u32           sc_msa_csr;
 };
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
 #endif /* _ASM_SIGCONTEXT_H */
diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h
new file mode 100644
index 000000000000..d60d1a2180d1
--- /dev/null
+++ b/arch/mips/include/asm/smp-cps.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __MIPS_ASM_SMP_CPS_H__
+#define __MIPS_ASM_SMP_CPS_H__
+#ifndef __ASSEMBLY__
+struct boot_config {
+        unsigned int core;
+        unsigned int vpe;
+        unsigned long pc;
+        unsigned long sp;
+        unsigned long gp;
+};
+extern struct boot_config mips_cps_bootcfg;
+extern void mips_cps_core_entry(void);
+#else /* __ASSEMBLY__ */
+.extern mips_cps_bootcfg;
+#endif /* __ASSEMBLY__ */
+#endif /* __MIPS_ASM_SMP_CPS_H__ */
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index ef2a8041e78b..73d35b18fb64 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -13,6 +13,8 @@
 #include <linux/errno.h>
+#include <asm/mips-cm.h>
 #ifdef CONFIG_SMP
 #include <linux/cpumask.h>
@@ -43,6 +45,9 @@ static inline void plat_smp_setup(void)
        mp_ops->smp_setup();
 }
+extern void gic_send_ipi_single(int cpu, unsigned int action);
+extern void gic_send_ipi_mask(const struct cpumask *mask, unsigned int action);
 #else /* !CONFIG_SMP */
 struct plat_smp_ops;
@@ -76,6 +81,9 @@ static inline int register_cmp_smp_ops(void)
 #ifdef CONFIG_MIPS_CMP
        extern struct plat_smp_ops cmp_smp_ops;
+        if (!mips_cm_present())
+                return -ENODEV;
        register_smp_ops(&cmp_smp_ops);
        return 0;
@@ -97,4 +105,13 @@ static inline int register_vsmp_smp_ops(void)
 #endif
 }
+#ifdef CONFIG_MIPS_CPS
+extern int register_cps_smp_ops(void);
+#else
+static inline int register_cps_smp_ops(void)
+{
+        return -ENODEV;
+}
+#endif
 #endif /* __ASM_SMP_OPS_H */
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index eb6008758484..efa02acd3dd5 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -42,6 +42,7 @@ extern int __cpu_logical_map[NR_CPUS];
 #define SMP_ICACHE_FLUSH        0x4
 /* Used by kexec crashdump to save all cpu's state */
 #define SMP_DUMP                0x8
+#define SMP_ASK_C0COUNT         0x10
 extern volatile cpumask_t cpu_callin_map;
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 4857e2c8df5a..d301e108d5b8 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -435,7 +435,7 @@
                .macro  RESTORE_SP_AND_RET
                LONG_L  sp, PT_R29(sp)
-                .set    mips3
+                .set    arch=r4000
                eret
                .set    mips0
                .endm
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index 278d45a09728..495c1041a2cc 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -16,22 +16,29 @@
 #include <asm/watch.h>
 #include <asm/dsp.h>
 #include <asm/cop2.h>
+#include <asm/msa.h>
 struct task_struct;
+enum {
+        FP_SAVE_NONE    = 0,
+        FP_SAVE_VECTOR  = -1,
+        FP_SAVE_SCALAR  = 1,
+};
 /**
 * resume - resume execution of a task
 * @prev:       The task previously executed.
 * @next:       The task to begin executing.
 * @next_ti:    task_thread_info(next).
- * @usedfpu:    Non-zero if prev's FP context should be saved.
+ * @fp_save:    Which, if any, FP context to save for prev.
 *
 * This function is used whilst scheduling to save the context of prev & load
 * the context of next. Returns prev.
 */
 extern asmlinkage struct task_struct *resume(struct task_struct *prev,
                struct task_struct *next, struct thread_info *next_ti,
-                u32 usedfpu);
+                s32 fp_save);
 extern unsigned int ll_bit;
 extern struct task_struct *ll_task;
@@ -75,7 +82,8 @@ do {									\
 #define switch_to(prev, next, last)                                     \
 do {                                                                    \
-        u32 __usedfpu, __c0_stat;                                       \
+        u32 __c0_stat;                                                  \
+        s32 __fpsave = FP_SAVE_NONE;                                    \
        __mips_mt_fpaff_switch_to(prev);                                \
        if (cpu_has_dsp)                                                \
                __save_dsp(prev);                                       \
@@ -88,8 +96,12 @@ do {									\
                write_c0_status(__c0_stat & ~ST0_CU2);                  \
        }                                                               \
        __clear_software_ll_bit();                                      \
-        __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU);  \
+        if (test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU))          \
-        (last) = resume(prev, next, task_thread_info(next), __usedfpu); \
+                __fpsave = FP_SAVE_SCALAR;                              \
+        if (test_and_clear_tsk_thread_flag(prev, TIF_USEDMSA))          \
+                __fpsave = FP_SAVE_VECTOR;                              \
+        (last) = resume(prev, next, task_thread_info(next), __fpsave);  \
+        disable_msa();                                                  \
 } while (0)
 #define finish_arch_switch(prev)                                        \
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index f35b131977e6..c6e9cd2bca8d 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -14,17 +14,28 @@
 #define __ASM_MIPS_SYSCALL_H
 #include <linux/compiler.h>
-#include <linux/audit.h>
+#include <uapi/linux/audit.h>
 #include <linux/elf-em.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/uaccess.h>
 #include <asm/ptrace.h>
+#include <asm/unistd.h>
+#ifndef __NR_syscall /* Only defined if _MIPS_SIM == _MIPS_SIM_ABI32 */
+#define __NR_syscall 4000
+#endif
 static inline long syscall_get_nr(struct task_struct *task,
                                  struct pt_regs *regs)
 {
-        return regs->regs[2];
+        /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
+        if ((config_enabled(CONFIG_32BIT) ||
+            test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
+            (regs->regs[2] == __NR_syscall))
+                return regs->regs[4];
+        else
+                return regs->regs[2];
 }
 static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
@@ -68,6 +79,12 @@ static inline long syscall_get_return_value(struct task_struct *task,
        return regs->regs[2];
 }
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        /* Do nothing */
+}
 static inline void syscall_set_return_value(struct task_struct *task,
                                            struct pt_regs *regs,
                                            int error, long val)
@@ -87,6 +104,13 @@ static inline void syscall_get_arguments(struct task_struct *task,
                                         unsigned long *args)
 {
        int ret;
+        /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
+        if ((config_enabled(CONFIG_32BIT) ||
+            test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
+            (regs->regs[2] == __NR_syscall)) {
+                i++;
+                n++;
+        }
        while (n--)
                ret |= mips_get_syscall_arg(args++, task, regs, i++);
@@ -103,11 +127,12 @@ extern const unsigned long sys_call_table[];
 extern const unsigned long sys32_call_table[];
 extern const unsigned long sysn32_call_table[];
-static inline int __syscall_get_arch(void)
+static inline int syscall_get_arch(void)
 {
        int arch = EM_MIPS;
 #ifdef CONFIG_64BIT
-        arch |=  __AUDIT_ARCH_64BIT;
+        if (!test_thread_flag(TIF_32BIT_REGS))
+                arch |= __AUDIT_ARCH_64BIT;
 #endif
 #if defined(__LITTLE_ENDIAN)
        arch |=  __AUDIT_ARCH_LE;
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 24846f9053fe..d2d961d6cb86 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -116,6 +116,8 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_LOAD_WATCH          25      /* If set, load watch registers */
 #define TIF_SYSCALL_TRACEPOINT  26      /* syscall tracepoint instrumentation */
 #define TIF_32BIT_FPREGS        27      /* 32-bit floating point registers */
+#define TIF_USEDMSA             29      /* MSA has been used this quantum */
+#define TIF_MSA_CTX_LIVE        30      /* MSA context must be preserved */
 #define TIF_SYSCALL_TRACE       31      /* syscall trace active */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
@@ -133,10 +135,13 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_FPUBOUND           (1<<TIF_FPUBOUND)
 #define _TIF_LOAD_WATCH         (1<<TIF_LOAD_WATCH)
 #define _TIF_32BIT_FPREGS       (1<<TIF_32BIT_FPREGS)
+#define _TIF_USEDMSA            (1<<TIF_USEDMSA)
+#define _TIF_MSA_CTX_LIVE       (1<<TIF_MSA_CTX_LIVE)
 #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
 #define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE |       \
-                                 _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
+                                 _TIF_SYSCALL_AUDIT | \
+                                 _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP)
 /* work to do in syscall_trace_leave() */
 #define _TIF_WORK_SYSCALL_EXIT  (_TIF_NOHZ | _TIF_SYSCALL_TRACE |       \
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index f3fa3750f577..a10951090234 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -6,6 +6,7 @@
 * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2007  Maciej W. Rozycki
+ * Copyright (C) 2014, Imagination Technologies Ltd.
 */
 #ifndef _ASM_UACCESS_H
 #define _ASM_UACCESS_H
@@ -13,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/thread_info.h>
+#include <asm/asm-eva.h>
 /*
 * The fs value determines whether argument validity checking should be
@@ -222,11 +224,44 @@ struct __large_struct { unsigned long buf[100]; };
 * Yuck.  We need two variants, one for 64bit operation and one
 * for 32 bit mode and old iron.
 */
+#ifndef CONFIG_EVA
+#define __get_kernel_common(val, size, ptr) __get_user_common(val, size, ptr)
+#else
+/*
+ * Kernel specific functions for EVA. We need to use normal load instructions
+ * to read data from kernel when operating in EVA mode. We use these macros to
+ * avoid redefining __get_user_asm for EVA.
+ */
+#undef _loadd
+#undef _loadw
+#undef _loadh
+#undef _loadb
 #ifdef CONFIG_32BIT
-#define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr)
+#define _loadd                  _loadw
+#else
+#define _loadd(reg, addr)       "ld " reg ", " addr
+#endif
+#define _loadw(reg, addr)       "lw " reg ", " addr
+#define _loadh(reg, addr)       "lh " reg ", " addr
+#define _loadb(reg, addr)       "lb " reg ", " addr
+#define __get_kernel_common(val, size, ptr)                             \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __get_data_asm(val, _loadb, ptr); break;                \
+        case 2: __get_data_asm(val, _loadh, ptr); break;                \
+        case 4: __get_data_asm(val, _loadw, ptr); break;                \
+        case 8: __GET_DW(val, _loadd, ptr); break;                      \
+        default: __get_user_unknown(); break;                           \
+        }                                                               \
+} while (0)
+#endif
+#ifdef CONFIG_32BIT
+#define __GET_DW(val, insn, ptr) __get_data_asm_ll32(val, insn, ptr)
 #endif
 #ifdef CONFIG_64BIT
-#define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr)
+#define __GET_DW(val, insn, ptr) __get_data_asm(val, insn, ptr)
 #endif
 extern void __get_user_unknown(void);
@@ -234,10 +269,10 @@ extern void __get_user_unknown(void);
 #define __get_user_common(val, size, ptr)                               \
 do {                                                                    \
        switch (size) {                                                 \
-        case 1: __get_user_asm(val, "lb", ptr); break;                  \
+        case 1: __get_data_asm(val, user_lb, ptr); break;               \
-        case 2: __get_user_asm(val, "lh", ptr); break;                  \
+        case 2: __get_data_asm(val, user_lh, ptr); break;               \
-        case 4: __get_user_asm(val, "lw", ptr); break;                  \
+        case 4: __get_data_asm(val, user_lw, ptr); break;               \
-        case 8: __GET_USER_DW(val, ptr); break;                         \
+        case 8: __GET_DW(val, user_ld, ptr); break;                     \
        default: __get_user_unknown(); break;                           \
        }                                                               \
 } while (0)
@@ -246,8 +281,12 @@ do {									\
 ({                                                                      \
        int __gu_err;                                                   \
                                                                        \
-        __chk_user_ptr(ptr);                                            \
+        if (segment_eq(get_fs(), get_ds())) {                           \
-        __get_user_common((x), size, ptr);                              \
+                __get_kernel_common((x), size, ptr);                    \
+        } else {                                                        \
+                __chk_user_ptr(ptr);                                    \
+                __get_user_common((x), size, ptr);                      \
+        }                                                               \
        __gu_err;                                                       \
 })
@@ -257,18 +296,22 @@ do {									\
        const __typeof__(*(ptr)) __user * __gu_ptr = (ptr);             \
                                                                        \
        might_fault();                                                  \
-        if (likely(access_ok(VERIFY_READ,  __gu_ptr, size)))            \
+        if (likely(access_ok(VERIFY_READ,  __gu_ptr, size))) {          \
-                __get_user_common((x), size, __gu_ptr);                 \
+                if (segment_eq(get_fs(), get_ds()))                     \
+                        __get_kernel_common((x), size, __gu_ptr);       \
+                else                                                    \
+                        __get_user_common((x), size, __gu_ptr);         \
+        }                                                               \
                                                                        \
        __gu_err;                                                       \
 })
-#define __get_user_asm(val, insn, addr)                                 \
+#define __get_data_asm(val, insn, addr)                                 \
 {                                                                       \
        long __gu_tmp;                                                  \
                                                                        \
        __asm__ __volatile__(                                           \
-        "1:     " insn "        %1, %3                          \n"     \
+        "1:     "insn("%1", "%3")"                              \n"     \
        "2:                                                     \n"     \
        "       .insn                                           \n"     \
        "       .section .fixup,\"ax\"                          \n"     \
@@ -287,7 +330,7 @@ do {									\
 /*
 * Get a long long 64 using 32 bit registers.
 */
-#define __get_user_asm_ll32(val, addr)                                  \
+#define __get_data_asm_ll32(val, insn, addr)                            \
 {                                                                       \
        union {                                                         \
                unsigned long long      l;                              \
@@ -295,8 +338,8 @@ do {									\
        } __gu_tmp;                                                     \
                                                                        \
        __asm__ __volatile__(                                           \
-        "1:     lw      %1, (%3)                                \n"     \
+        "1:     " insn("%1", "(%3)")"                           \n"     \
-        "2:     lw      %D1, 4(%3)                              \n"     \
+        "2:     " insn("%D1", "4(%3)")"                         \n"     \
        "3:                                                     \n"     \
        "       .insn                                           \n"     \
        "       .section        .fixup,\"ax\"                   \n"     \
@@ -315,30 +358,73 @@ do {									\
        (val) = __gu_tmp.t;                                             \
 }
+#ifndef CONFIG_EVA
+#define __put_kernel_common(ptr, size) __put_user_common(ptr, size)
+#else
+/*
+ * Kernel specific functions for EVA. We need to use normal load instructions
+ * to read data from kernel when operating in EVA mode. We use these macros to
+ * avoid redefining __get_data_asm for EVA.
+ */
+#undef _stored
+#undef _storew
+#undef _storeh
+#undef _storeb
+#ifdef CONFIG_32BIT
+#define _stored                 _storew
+#else
+#define _stored(reg, addr)      "ld " reg ", " addr
+#endif
+#define _storew(reg, addr)      "sw " reg ", " addr
+#define _storeh(reg, addr)      "sh " reg ", " addr
+#define _storeb(reg, addr)      "sb " reg ", " addr
+#define __put_kernel_common(ptr, size)                                  \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __put_data_asm(_storeb, ptr); break;                    \
+        case 2: __put_data_asm(_storeh, ptr); break;                    \
+        case 4: __put_data_asm(_storew, ptr); break;                    \
+        case 8: __PUT_DW(_stored, ptr); break;                          \
+        default: __put_user_unknown(); break;                           \
+        }                                                               \
+} while(0)
+#endif
 /*
 * Yuck.  We need two variants, one for 64bit operation and one
 * for 32 bit mode and old iron.
 */
 #ifdef CONFIG_32BIT
-#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr)
+#define __PUT_DW(insn, ptr) __put_data_asm_ll32(insn, ptr)
 #endif
 #ifdef CONFIG_64BIT
-#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
+#define __PUT_DW(insn, ptr) __put_data_asm(insn, ptr)
 #endif
+#define __put_user_common(ptr, size)                                    \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __put_data_asm(user_sb, ptr); break;                    \
+        case 2: __put_data_asm(user_sh, ptr); break;                    \
+        case 4: __put_data_asm(user_sw, ptr); break;                    \
+        case 8: __PUT_DW(user_sd, ptr); break;                          \
+        default: __put_user_unknown(); break;                           \
+        }                                                               \
+} while (0)
 #define __put_user_nocheck(x, ptr, size)                                \
 ({                                                                      \
        __typeof__(*(ptr)) __pu_val;                                    \
        int __pu_err = 0;                                               \
                                                                        \
-        __chk_user_ptr(ptr);                                            \
        __pu_val = (x);                                                 \
-        switch (size) {                                                 \
+        if (segment_eq(get_fs(), get_ds())) {                           \
-        case 1: __put_user_asm("sb", ptr); break;                       \
+                __put_kernel_common(ptr, size);                         \
-        case 2: __put_user_asm("sh", ptr); break;                       \
+        } else {                                                        \
-        case 4: __put_user_asm("sw", ptr); break;                       \
+                __chk_user_ptr(ptr);                                    \
-        case 8: __PUT_USER_DW(ptr); break;                              \
+                __put_user_common(ptr, size);                           \
-        default: __put_user_unknown(); break;                           \
        }                                                               \
        __pu_err;                                                       \
 })
@@ -351,21 +437,19 @@ do {									\
                                                                        \
        might_fault();                                                  \
        if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {        \
-                switch (size) {                                         \
+                if (segment_eq(get_fs(), get_ds()))                     \
-                case 1: __put_user_asm("sb", __pu_addr); break;         \
+                        __put_kernel_common(__pu_addr, size);           \
-                case 2: __put_user_asm("sh", __pu_addr); break;         \
+                else                                                    \
-                case 4: __put_user_asm("sw", __pu_addr); break;         \
+                        __put_user_common(__pu_addr, size);             \
-                case 8: __PUT_USER_DW(__pu_addr); break;                \
-                default: __put_user_unknown(); break;                   \
-                }                                                       \
        }                                                               \
+                                                                        \
        __pu_err;                                                       \
 })
-#define __put_user_asm(insn, ptr)                                       \
+#define __put_data_asm(insn, ptr)                                       \
 {                                                                       \
        __asm__ __volatile__(                                           \
-        "1:     " insn "        %z2, %3         # __put_user_asm\n"     \
+        "1:     "insn("%z2", "%3")"     # __put_data_asm        \n"     \
        "2:                                                     \n"     \
        "       .insn                                           \n"     \
        "       .section        .fixup,\"ax\"                   \n"     \
@@ -380,11 +464,11 @@ do {									\
          "i" (-EFAULT));                                               \
 }
-#define __put_user_asm_ll32(ptr)                                        \
+#define __put_data_asm_ll32(insn, ptr)                                  \
 {                                                                       \
        __asm__ __volatile__(                                           \
-        "1:     sw      %2, (%3)        # __put_user_asm_ll32   \n"     \
+        "1:     "insn("%2", "(%3)")"    # __put_data_asm_ll32   \n"     \
-        "2:     sw      %D2, 4(%3)                              \n"     \
+        "2:     "insn("%D2", "4(%3)")"                          \n"     \
        "3:                                                     \n"     \
        "       .insn                                           \n"     \
        "       .section        .fixup,\"ax\"                   \n"     \
@@ -403,6 +487,11 @@ do {									\
 extern void __put_user_unknown(void);
 /*
+ * ul{b,h,w} are macros and there are no equivalent macros for EVA.
+ * EVA unaligned access is handled in the ADE exception handler.
+ */
+#ifndef CONFIG_EVA
+/*
 * put_user_unaligned: - Write a simple value into user space.
 * @x:   Value to copy to user space.
 * @ptr: Destination address, in user space.
@@ -504,7 +593,7 @@ extern void __get_user_unaligned_unknown(void);
 #define __get_user_unaligned_common(val, size, ptr)                     \
 do {                                                                    \
        switch (size) {                                                 \
-        case 1: __get_user_asm(val, "lb", ptr); break;                  \
+        case 1: __get_data_asm(val, "lb", ptr); break;                  \
        case 2: __get_user_unaligned_asm(val, "ulh", ptr); break;       \
        case 4: __get_user_unaligned_asm(val, "ulw", ptr); break;       \
        case 8: __GET_USER_UNALIGNED_DW(val, ptr); break;               \
@@ -531,7 +620,7 @@ do {									\
        __gu_err;                                                       \
 })
-#define __get_user_unaligned_asm(val, insn, addr)                       \
+#define __get_data_unaligned_asm(val, insn, addr)                       \
 {                                                                       \
        long __gu_tmp;                                                  \
                                                                        \
@@ -594,19 +683,23 @@ do {									\
 #define __PUT_USER_UNALIGNED_DW(ptr) __put_user_unaligned_asm("usd", ptr)
 #endif
+#define __put_user_unaligned_common(ptr, size)                          \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __put_data_asm("sb", ptr); break;                       \
+        case 2: __put_user_unaligned_asm("ush", ptr); break;            \
+        case 4: __put_user_unaligned_asm("usw", ptr); break;            \
+        case 8: __PUT_USER_UNALIGNED_DW(ptr); break;                    \
+        default: __put_user_unaligned_unknown(); break;                 \
+} while (0)
 #define __put_user_unaligned_nocheck(x,ptr,size)                        \
 ({                                                                      \
        __typeof__(*(ptr)) __pu_val;                                    \
        int __pu_err = 0;                                               \
                                                                        \
        __pu_val = (x);                                                 \
-        switch (size) {                                                 \
+        __put_user_unaligned_common(ptr, size);                         \
-        case 1: __put_user_asm("sb", ptr); break;                       \
-        case 2: __put_user_unaligned_asm("ush", ptr); break;            \
-        case 4: __put_user_unaligned_asm("usw", ptr); break;            \
-        case 8: __PUT_USER_UNALIGNED_DW(ptr); break;                    \
-        default: __put_user_unaligned_unknown(); break;                 \
-        }                                                               \
        __pu_err;                                                       \
 })
@@ -616,15 +709,9 @@ do {									\
        __typeof__(*(ptr)) __pu_val = (x);                              \
        int __pu_err = -EFAULT;                                         \
                                                                        \
-        if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {        \
+        if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size)))          \
-                switch (size) {                                         \
+                __put_user_unaligned_common(__pu_addr, size);           \
-                case 1: __put_user_asm("sb", __pu_addr); break;         \
+                                                                        \
-                case 2: __put_user_unaligned_asm("ush", __pu_addr); break; \
-                case 4: __put_user_unaligned_asm("usw", __pu_addr); break; \
-                case 8: __PUT_USER_UNALGINED_DW(__pu_addr); break;      \
-                default: __put_user_unaligned_unknown(); break;         \
-                }                                                       \
-        }                                                               \
        __pu_err;                                                       \
 })
@@ -669,6 +756,7 @@ do {									\
 }
 extern void __put_user_unaligned_unknown(void);
+#endif
 /*
 * We're generating jump to subroutines which will be outside the range of
@@ -693,6 +781,7 @@ extern void __put_user_unaligned_unknown(void);
 extern size_t __copy_user(void *__to, const void *__from, size_t __n);
+#ifndef CONFIG_EVA
 #define __invoke_copy_to_user(to, from, n)                              \
 ({                                                                      \
        register void __user *__cu_to_r __asm__("$4");                  \
@@ -711,6 +800,11 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
        __cu_len_r;                                                     \
 })
+#define __invoke_copy_to_kernel(to, from, n)                            \
+        __invoke_copy_to_user(to, from, n)
+#endif
 /*
 * __copy_to_user: - Copy a block of data into user space, with less checking.
 * @to:   Destination address, in user space.
@@ -735,7 +829,12 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
        might_fault();                                                  \
-        __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
+        if (segment_eq(get_fs(), get_ds()))                             \
+                __cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from,  \
+                                                   __cu_len);           \
+        else                                                            \
+                __cu_len = __invoke_copy_to_user(__cu_to, __cu_from,    \
+                                                 __cu_len);             \
        __cu_len;                                                       \
 })
@@ -750,7 +849,12 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
-        __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
+        if (segment_eq(get_fs(), get_ds()))                             \
+                __cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from,  \
+                                                   __cu_len);           \
+        else                                                            \
+                __cu_len = __invoke_copy_to_user(__cu_to, __cu_from,    \
+                                                 __cu_len);             \
        __cu_len;                                                       \
 })
@@ -763,8 +867,14 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
-        __cu_len = __invoke_copy_from_user_inatomic(__cu_to, __cu_from, \
+        if (segment_eq(get_fs(), get_ds()))                             \
-                                                    __cu_len);          \
+                __cu_len = __invoke_copy_from_kernel_inatomic(__cu_to,  \
+                                                              __cu_from,\
+                                                              __cu_len);\
+        else                                                            \
+                __cu_len = __invoke_copy_from_user_inatomic(__cu_to,    \
+                                                            __cu_from,  \
+                                                            __cu_len);  \
        __cu_len;                                                       \
 })
@@ -790,14 +900,23 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
-        if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) {               \
+        if (segment_eq(get_fs(), get_ds())) {                           \
-                might_fault();                                          \
+                __cu_len = __invoke_copy_to_kernel(__cu_to,             \
-                __cu_len = __invoke_copy_to_user(__cu_to, __cu_from,    \
+                                                   __cu_from,           \
-                                                 __cu_len);             \
+                                                   __cu_len);           \
+        } else {                                                        \
+                if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) {       \
+                        might_fault();                                  \
+                        __cu_len = __invoke_copy_to_user(__cu_to,       \
+                                                         __cu_from,     \
+                                                         __cu_len);     \
+                }                                                       \
        }                                                               \
        __cu_len;                                                       \
 })
+#ifndef CONFIG_EVA
 #define __invoke_copy_from_user(to, from, n)                            \
 ({                                                                      \
        register void *__cu_to_r __asm__("$4");                         \
@@ -821,6 +940,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_len_r;                                                     \
 })
+#define __invoke_copy_from_kernel(to, from, n)                          \
+        __invoke_copy_from_user(to, from, n)
+/* For userland <-> userland operations */
+#define ___invoke_copy_in_user(to, from, n)                             \
+        __invoke_copy_from_user(to, from, n)
+/* For kernel <-> kernel operations */
+#define ___invoke_copy_in_kernel(to, from, n)                           \
+        __invoke_copy_from_user(to, from, n)
 #define __invoke_copy_from_user_inatomic(to, from, n)                   \
 ({                                                                      \
        register void *__cu_to_r __asm__("$4");                         \
@@ -844,6 +974,97 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_len_r;                                                     \
 })
+#define __invoke_copy_from_kernel_inatomic(to, from, n)                 \
+        __invoke_copy_from_user_inatomic(to, from, n)                   \
+#else
+/* EVA specific functions */
+extern size_t __copy_user_inatomic_eva(void *__to, const void *__from,
+                                       size_t __n);
+extern size_t __copy_from_user_eva(void *__to, const void *__from,
+                                   size_t __n);
+extern size_t __copy_to_user_eva(void *__to, const void *__from,
+                                 size_t __n);
+extern size_t __copy_in_user_eva(void *__to, const void *__from, size_t __n);
+#define __invoke_copy_from_user_eva_generic(to, from, n, func_ptr)      \
+({                                                                      \
+        register void *__cu_to_r __asm__("$4");                         \
+        register const void __user *__cu_from_r __asm__("$5");          \
+        register long __cu_len_r __asm__("$6");                         \
+                                                                        \
+        __cu_to_r = (to);                                               \
+        __cu_from_r = (from);                                           \
+        __cu_len_r = (n);                                               \
+        __asm__ __volatile__(                                           \
+        ".set\tnoreorder\n\t"                                           \
+        __MODULE_JAL(func_ptr)                                          \
+        ".set\tnoat\n\t"                                                \
+        __UA_ADDU "\t$1, %1, %2\n\t"                                    \
+        ".set\tat\n\t"                                                  \
+        ".set\treorder"                                                 \
+        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
+        :                                                               \
+        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
+          DADDI_SCRATCH, "memory");                                     \
+        __cu_len_r;                                                     \
+})
+#define __invoke_copy_to_user_eva_generic(to, from, n, func_ptr)        \
+({                                                                      \
+        register void *__cu_to_r __asm__("$4");                         \
+        register const void __user *__cu_from_r __asm__("$5");          \
+        register long __cu_len_r __asm__("$6");                         \
+                                                                        \
+        __cu_to_r = (to);                                               \
+        __cu_from_r = (from);                                           \
+        __cu_len_r = (n);                                               \
+        __asm__ __volatile__(                                           \
+        __MODULE_JAL(func_ptr)                                          \
+        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
+        :                                                               \
+        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
+          DADDI_SCRATCH, "memory");                                     \
+        __cu_len_r;                                                     \
+})
+/*
+ * Source or destination address is in userland. We need to go through
+ * the TLB
+ */
+#define __invoke_copy_from_user(to, from, n)                            \
+        __invoke_copy_from_user_eva_generic(to, from, n, __copy_from_user_eva)
+#define __invoke_copy_from_user_inatomic(to, from, n)                   \
+        __invoke_copy_from_user_eva_generic(to, from, n,                \
+                                            __copy_user_inatomic_eva)
+#define __invoke_copy_to_user(to, from, n)                              \
+        __invoke_copy_to_user_eva_generic(to, from, n, __copy_to_user_eva)
+#define ___invoke_copy_in_user(to, from, n)                             \
+        __invoke_copy_from_user_eva_generic(to, from, n, __copy_in_user_eva)
+/*
+ * Source or destination address in the kernel. We are not going through
+ * the TLB
+ */
+#define __invoke_copy_from_kernel(to, from, n)                          \
+        __invoke_copy_from_user_eva_generic(to, from, n, __copy_user)
+#define __invoke_copy_from_kernel_inatomic(to, from, n)                 \
+        __invoke_copy_from_user_eva_generic(to, from, n, __copy_user_inatomic)
+#define __invoke_copy_to_kernel(to, from, n)                            \
+        __invoke_copy_to_user_eva_generic(to, from, n, __copy_user)
+#define ___invoke_copy_in_kernel(to, from, n)                           \
+        __invoke_copy_from_user_eva_generic(to, from, n, __copy_user)
+#endif /* CONFIG_EVA */
 /*
 * __copy_from_user: - Copy a block of data from user space, with less checking.
 * @to:   Destination address, in kernel space.
@@ -901,10 +1122,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
-        if (access_ok(VERIFY_READ, __cu_from, __cu_len)) {              \
+        if (segment_eq(get_fs(), get_ds())) {                           \
-                might_fault();                                          \
+                __cu_len = __invoke_copy_from_kernel(__cu_to,           \
-                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
+                                                     __cu_from,         \
-                                                   __cu_len);           \
+                                                     __cu_len);         \
+        } else {                                                        \
+                if (access_ok(VERIFY_READ, __cu_from, __cu_len)) {      \
+                        might_fault();                                  \
+                        __cu_len = __invoke_copy_from_user(__cu_to,     \
+                                                           __cu_from,   \
+                                                           __cu_len);   \
+                }                                                       \
        }                                                               \
        __cu_len;                                                       \
 })
@@ -918,9 +1146,14 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
-        might_fault();                                                  \
+        if (segment_eq(get_fs(), get_ds())) {                           \
-        __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,          \
+                __cu_len = ___invoke_copy_in_kernel(__cu_to, __cu_from, \
-                                           __cu_len);                   \
+                                                    __cu_len);          \
+        } else {                                                        \
+                might_fault();                                          \
+                __cu_len = ___invoke_copy_in_user(__cu_to, __cu_from,   \
+                                                  __cu_len);            \
+        }                                                               \
        __cu_len;                                                       \
 })
@@ -933,11 +1166,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
-        if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&       \
+        if (segment_eq(get_fs(), get_ds())) {                           \
-                   access_ok(VERIFY_WRITE, __cu_to, __cu_len))) {       \
+                __cu_len = ___invoke_copy_in_kernel(__cu_to,__cu_from,  \
-                might_fault();                                          \
+                                                    __cu_len);          \
-                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
+        } else {                                                        \
-                                                   __cu_len);           \
+                if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&\
+                           access_ok(VERIFY_WRITE, __cu_to, __cu_len))) {\
+                        might_fault();                                  \
+                        __cu_len = ___invoke_copy_in_user(__cu_to,      \
+                                                          __cu_from,    \
+                                                          __cu_len);    \
+                }                                                       \
        }                                                               \
        __cu_len;                                                       \
 })
@@ -1007,16 +1246,28 @@ __strncpy_from_user(char *__to, const char __user *__from, long __len)
 {
        long res;
-        might_fault();
+        if (segment_eq(get_fs(), get_ds())) {
-        __asm__ __volatile__(
+                __asm__ __volatile__(
-                "move\t$4, %1\n\t"
+                        "move\t$4, %1\n\t"
-                "move\t$5, %2\n\t"
+                        "move\t$5, %2\n\t"
-                "move\t$6, %3\n\t"
+                        "move\t$6, %3\n\t"
-                __MODULE_JAL(__strncpy_from_user_nocheck_asm)
+                        __MODULE_JAL(__strncpy_from_kernel_nocheck_asm)
-                "move\t%0, $2"
+                        "move\t%0, $2"
-                : "=r" (res)
+                        : "=r" (res)
-                : "r" (__to), "r" (__from), "r" (__len)
+                        : "r" (__to), "r" (__from), "r" (__len)
-                : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+                        : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+        } else {
+                might_fault();
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, %2\n\t"
+                        "move\t$6, %3\n\t"
+                        __MODULE_JAL(__strncpy_from_user_nocheck_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (__to), "r" (__from), "r" (__len)
+                        : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+        }
        return res;
 }
@@ -1044,16 +1295,28 @@ strncpy_from_user(char *__to, const char __user *__from, long __len)
 {
        long res;
-        might_fault();
+        if (segment_eq(get_fs(), get_ds())) {
-        __asm__ __volatile__(
+                __asm__ __volatile__(
-                "move\t$4, %1\n\t"
+                        "move\t$4, %1\n\t"
-                "move\t$5, %2\n\t"
+                        "move\t$5, %2\n\t"
-                "move\t$6, %3\n\t"
+                        "move\t$6, %3\n\t"
-                __MODULE_JAL(__strncpy_from_user_asm)
+                        __MODULE_JAL(__strncpy_from_kernel_asm)
-                "move\t%0, $2"
+                        "move\t%0, $2"
-                : "=r" (res)
+                        : "=r" (res)
-                : "r" (__to), "r" (__from), "r" (__len)
+                        : "r" (__to), "r" (__from), "r" (__len)
-                : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+                        : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+        } else {
+                might_fault();
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, %2\n\t"
+                        "move\t$6, %3\n\t"
+                        __MODULE_JAL(__strncpy_from_user_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (__to), "r" (__from), "r" (__len)
+                        : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+        }
        return res;
 }
@@ -1063,14 +1326,24 @@ static inline long __strlen_user(const char __user *s)
 {
        long res;
-        might_fault();
+        if (segment_eq(get_fs(), get_ds())) {
-        __asm__ __volatile__(
+                __asm__ __volatile__(
-                "move\t$4, %1\n\t"
+                        "move\t$4, %1\n\t"
-                __MODULE_JAL(__strlen_user_nocheck_asm)
+                        __MODULE_JAL(__strlen_kernel_nocheck_asm)
-                "move\t%0, $2"
+                        "move\t%0, $2"
-                : "=r" (res)
+                        : "=r" (res)
-                : "r" (s)
+                        : "r" (s)
-                : "$2", "$4", __UA_t0, "$31");
+                        : "$2", "$4", __UA_t0, "$31");
+        } else {
+                might_fault();
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        __MODULE_JAL(__strlen_user_nocheck_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (s)
+                        : "$2", "$4", __UA_t0, "$31");
+        }
        return res;
 }
@@ -1093,14 +1366,24 @@ static inline long strlen_user(const char __user *s)
 {
        long res;
-        might_fault();
+        if (segment_eq(get_fs(), get_ds())) {
-        __asm__ __volatile__(
+                __asm__ __volatile__(
-                "move\t$4, %1\n\t"
+                        "move\t$4, %1\n\t"
-                __MODULE_JAL(__strlen_user_asm)
+                        __MODULE_JAL(__strlen_kernel_asm)
-                "move\t%0, $2"
+                        "move\t%0, $2"
-                : "=r" (res)
+                        : "=r" (res)
-                : "r" (s)
+                        : "r" (s)
-                : "$2", "$4", __UA_t0, "$31");
+                        : "$2", "$4", __UA_t0, "$31");
+        } else {
+                might_fault();
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        __MODULE_JAL(__strlen_kernel_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (s)
+                        : "$2", "$4", __UA_t0, "$31");
+        }
        return res;
 }
@@ -1110,15 +1393,26 @@ static inline long __strnlen_user(const char __user *s, long n)
 {
        long res;
-        might_fault();
+        if (segment_eq(get_fs(), get_ds())) {
-        __asm__ __volatile__(
+                __asm__ __volatile__(
-                "move\t$4, %1\n\t"
+                        "move\t$4, %1\n\t"
-                "move\t$5, %2\n\t"
+                        "move\t$5, %2\n\t"
-                __MODULE_JAL(__strnlen_user_nocheck_asm)
+                        __MODULE_JAL(__strnlen_kernel_nocheck_asm)
-                "move\t%0, $2"
+                        "move\t%0, $2"
-                : "=r" (res)
+                        : "=r" (res)
-                : "r" (s), "r" (n)
+                        : "r" (s), "r" (n)
-                : "$2", "$4", "$5", __UA_t0, "$31");
+                        : "$2", "$4", "$5", __UA_t0, "$31");
+        } else {
+                might_fault();
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, %2\n\t"
+                        __MODULE_JAL(__strnlen_user_nocheck_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (s), "r" (n)
+                        : "$2", "$4", "$5", __UA_t0, "$31");
+        }
        return res;
 }
@@ -1142,14 +1436,25 @@ static inline long strnlen_user(const char __user *s, long n)
        long res;
        might_fault();
-        __asm__ __volatile__(
+        if (segment_eq(get_fs(), get_ds())) {
-                "move\t$4, %1\n\t"
+                __asm__ __volatile__(
-                "move\t$5, %2\n\t"
+                        "move\t$4, %1\n\t"
-                __MODULE_JAL(__strnlen_user_asm)
+                        "move\t$5, %2\n\t"
-                "move\t%0, $2"
+                        __MODULE_JAL(__strnlen_kernel_asm)
-                : "=r" (res)
+                        "move\t%0, $2"
-                : "r" (s), "r" (n)
+                        : "=r" (res)
-                : "$2", "$4", "$5", __UA_t0, "$31");
+                        : "r" (s), "r" (n)
+                        : "$2", "$4", "$5", __UA_t0, "$31");
+        } else {
+                __asm__ __volatile__(
+                        "move\t$4, %1\n\t"
+                        "move\t$5, %2\n\t"
+                        __MODULE_JAL(__strnlen_user_asm)
+                        "move\t%0, $2"
+                        : "=r" (res)
+                        : "r" (s), "r" (n)
+                        : "$2", "$4", "$5", __UA_t0, "$31");
+        }
        return res;
 }
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index f25181b19941..df6e775f3fef 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -8,6 +8,7 @@
 * Copyright (C) 1996, 2000 by Ralf Baechle
 * Copyright (C) 2006 by Thiemo Seufer
 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 */
 #ifndef _UAPI_ASM_INST_H
 #define _UAPI_ASM_INST_H
@@ -73,10 +74,16 @@ enum spec2_op {
 enum spec3_op {
        ext_op, dextm_op, dextu_op, dext_op,
        ins_op, dinsm_op, dinsu_op, dins_op,
-        lx_op = 0x0a,
+        lx_op     = 0x0a, lwle_op   = 0x19,
-        bshfl_op = 0x20,
+        lwre_op   = 0x1a, cachee_op = 0x1b,
-        dbshfl_op = 0x24,
+        sbe_op    = 0x1c, she_op    = 0x1d,
-        rdhwr_op = 0x3b
+        sce_op    = 0x1e, swe_op    = 0x1f,
+        bshfl_op  = 0x20, swle_op   = 0x21,
+        swre_op   = 0x22, prefe_op  = 0x23,
+        dbshfl_op = 0x24, lbue_op   = 0x28,
+        lhue_op   = 0x29, lbe_op    = 0x2c,
+        lhe_op    = 0x2d, lle_op    = 0x2e,
+        lwe_op    = 0x2f, rdhwr_op  = 0x3b
 };
 /*
@@ -592,6 +599,15 @@ struct v_format {				/* MDMX vector format */
        ;)))))))
 };
+struct spec3_format {   /* SPEC3 */
+        BITFIELD_FIELD(unsigned int opcode:6,
+        BITFIELD_FIELD(unsigned int rs:5,
+        BITFIELD_FIELD(unsigned int rt:5,
+        BITFIELD_FIELD(signed int simmediate:9,
+        BITFIELD_FIELD(unsigned int func:7,
+        ;)))))
+};
 /*
 * microMIPS instruction formats (32-bit length)
 *
@@ -863,6 +879,7 @@ union mips_instruction {
        struct b_format b_format;
        struct ps_format ps_format;
        struct v_format v_format;
+        struct spec3_format spec3_format;
        struct fb_format fb_format;
        struct fp0_format fp0_format;
        struct mm_fp0_format mm_fp0_format;
diff --git a/arch/mips/include/uapi/asm/sigcontext.h b/arch/mips/include/uapi/asm/sigcontext.h
index 6c9906f59c6e..681c17603a48 100644
--- a/arch/mips/include/uapi/asm/sigcontext.h
+++ b/arch/mips/include/uapi/asm/sigcontext.h
@@ -12,6 +12,10 @@
 #include <linux/types.h>
 #include <asm/sgidefs.h>
+/* Bits which may be set in sc_used_math */
+#define USEDMATH_FP     (1 << 0)
+#define USEDMATH_MSA    (1 << 1)
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 /*
@@ -37,6 +41,8 @@ struct sigcontext {
        unsigned long           sc_lo2;
        unsigned long           sc_hi3;
        unsigned long           sc_lo3;
+        unsigned long long      sc_msaregs[32]; /* Most significant 64 bits */
+        unsigned long           sc_msa_csr;
 };
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
@@ -70,6 +76,8 @@ struct sigcontext {
        __u32   sc_used_math;
        __u32   sc_dsp;
        __u32   sc_reserved;
+        __u64   sc_msaregs[32];
+        __u32   sc_msa_csr;
 };
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 26c6175e1379..277dab301cea 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -53,6 +53,8 @@ obj-$(CONFIG_MIPS_MT_FPAFF)	+= mips-mt-fpaff.o
 obj-$(CONFIG_MIPS_MT_SMTC)      += smtc.o smtc-asm.o smtc-proc.o
 obj-$(CONFIG_MIPS_MT_SMP)       += smp-mt.o
 obj-$(CONFIG_MIPS_CMP)          += smp-cmp.o
+obj-$(CONFIG_MIPS_CPS)          += smp-cps.o cps-vec.o
+obj-$(CONFIG_MIPS_GIC_IPI)      += smp-gic.o
 obj-$(CONFIG_CPU_MIPSR2)        += spram.o
 obj-$(CONFIG_MIPS_VPE_LOADER)   += vpe.o
@@ -102,6 +104,9 @@ obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_mipsxx.o
 obj-$(CONFIG_JUMP_LABEL)        += jump_label.o
+obj-$(CONFIG_MIPS_CM)           += mips-cm.o
+obj-$(CONFIG_MIPS_CPC)          += mips-cpc.o
 #
 # DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
 # safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 0c2e853c3db4..0ea75c244b48 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -16,6 +16,7 @@
 #include <linux/suspend.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
+#include <asm/smp-cps.h>
 #include <linux/kvm_host.h>
@@ -168,6 +169,72 @@ void output_thread_fpu_defines(void)
        OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
        OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
+        /* the least significant 64 bits of each FP register */
+        OFFSET(THREAD_FPR0_LS64, task_struct,
+               thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR1_LS64, task_struct,
+               thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR2_LS64, task_struct,
+               thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR3_LS64, task_struct,
+               thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR4_LS64, task_struct,
+               thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR5_LS64, task_struct,
+               thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR6_LS64, task_struct,
+               thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR7_LS64, task_struct,
+               thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR8_LS64, task_struct,
+               thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR9_LS64, task_struct,
+               thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR10_LS64, task_struct,
+               thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR11_LS64, task_struct,
+               thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR12_LS64, task_struct,
+               thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR13_LS64, task_struct,
+               thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR14_LS64, task_struct,
+               thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR15_LS64, task_struct,
+               thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR16_LS64, task_struct,
+               thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR17_LS64, task_struct,
+               thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR18_LS64, task_struct,
+               thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR19_LS64, task_struct,
+               thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR20_LS64, task_struct,
+               thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR21_LS64, task_struct,
+               thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR22_LS64, task_struct,
+               thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR23_LS64, task_struct,
+               thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR24_LS64, task_struct,
+               thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR25_LS64, task_struct,
+               thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR26_LS64, task_struct,
+               thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR27_LS64, task_struct,
+               thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR28_LS64, task_struct,
+               thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR29_LS64, task_struct,
+               thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR30_LS64, task_struct,
+               thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]);
+        OFFSET(THREAD_FPR31_LS64, task_struct,
+               thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]);
        OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
        BLANK();
 }
@@ -228,6 +295,7 @@ void output_sc_defines(void)
        OFFSET(SC_LO2, sigcontext, sc_lo2);
        OFFSET(SC_HI3, sigcontext, sc_hi3);
        OFFSET(SC_LO3, sigcontext, sc_lo3);
+        OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
        BLANK();
 }
 #endif
@@ -242,6 +310,7 @@ void output_sc_defines(void)
        OFFSET(SC_MDLO, sigcontext, sc_mdlo);
        OFFSET(SC_PC, sigcontext, sc_pc);
        OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
+        OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
        BLANK();
 }
 #endif
@@ -253,6 +322,7 @@ void output_sc32_defines(void)
        OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
        OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
        OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
+        OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs);
        BLANK();
 }
 #endif
@@ -397,3 +467,15 @@ void output_kvm_defines(void)
        OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
        BLANK();
 }
+#ifdef CONFIG_MIPS_CPS
+void output_cps_defines(void)
+{
+        COMMENT(" MIPS CPS offsets. ");
+        OFFSET(BOOTCFG_CORE, boot_config, core);
+        OFFSET(BOOTCFG_VPE, boot_config, vpe);
+        OFFSET(BOOTCFG_PC, boot_config, pc);
+        OFFSET(BOOTCFG_SP, boot_config, sp);
+        OFFSET(BOOTCFG_GP, boot_config, gp);
+}
+#endif
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index a5bf73d22fcc..290c23b51678 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -122,7 +122,7 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
        jr      k0
        RESTORE_ALL
-        .set    mips3
+        .set    arch=r4000
        eret
 /***********************************************************************
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
new file mode 100644
index 000000000000..f7a46db4b161
--- /dev/null
+++ b/arch/mips/kernel/cps-vec.S
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/asmmacro.h>
+#include <asm/cacheops.h>
+#include <asm/mipsregs.h>
+#define GCR_CL_COHERENCE_OFS 0x2008
+.section .text.cps-vec
+.balign 0x1000
+.set noreorder
+LEAF(mips_cps_core_entry)
+        /*
+         * These first 8 bytes will be patched by cps_smp_setup to load the
+         * base address of the CM GCRs into register v1.
+         */
+        .quad   0
+        /* Check whether we're here due to an NMI */
+        mfc0    k0, CP0_STATUS
+        and     k0, k0, ST0_NMI
+        beqz    k0, not_nmi
+         nop
+        /* This is an NMI */
+        la      k0, nmi_handler
+        jr      k0
+         nop
+not_nmi:
+        /* Setup Cause */
+        li      t0, CAUSEF_IV
+        mtc0    t0, CP0_CAUSE
+        /* Setup Status */
+        li      t0, ST0_CU1 | ST0_CU0
+        mtc0    t0, CP0_STATUS
+        /*
+         * Clear the bits used to index the caches. Note that the architecture
+         * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
+         * be valid for all MIPS32 CPUs, even those for which said writes are
+         * unnecessary.
+         */
+        mtc0    zero, CP0_TAGLO, 0
+        mtc0    zero, CP0_TAGHI, 0
+        mtc0    zero, CP0_TAGLO, 2
+        mtc0    zero, CP0_TAGHI, 2
+        ehb
+        /* Primary cache configuration is indicated by Config1 */
+        mfc0    v0, CP0_CONFIG, 1
+        /* Detect I-cache line size */
+        _EXT    t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
+        beqz    t0, icache_done
+         li     t1, 2
+        sllv    t0, t1, t0
+        /* Detect I-cache size */
+        _EXT    t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
+        xori    t2, t1, 0x7
+        beqz    t2, 1f
+         li     t3, 32
+        addi    t1, t1, 1
+        sllv    t1, t3, t1
+1:      /* At this point t1 == I-cache sets per way */
+        _EXT    t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
+        addi    t2, t2, 1
+        mul     t1, t1, t0
+        mul     t1, t1, t2
+        li      a0, KSEG0
+        add     a1, a0, t1
+1:      cache   Index_Store_Tag_I, 0(a0)
+        add     a0, a0, t0
+        bne     a0, a1, 1b
+         nop
+icache_done:
+        /* Detect D-cache line size */
+        _EXT    t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
+        beqz    t0, dcache_done
+         li     t1, 2
+        sllv    t0, t1, t0
+        /* Detect D-cache size */
+        _EXT    t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
+        xori    t2, t1, 0x7
+        beqz    t2, 1f
+         li     t3, 32
+        addi    t1, t1, 1
+        sllv    t1, t3, t1
+1:      /* At this point t1 == D-cache sets per way */
+        _EXT    t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
+        addi    t2, t2, 1
+        mul     t1, t1, t0
+        mul     t1, t1, t2
+        li      a0, KSEG0
+        addu    a1, a0, t1
+        subu    a1, a1, t0
+1:      cache   Index_Store_Tag_D, 0(a0)
+        bne     a0, a1, 1b
+         add    a0, a0, t0
+dcache_done:
+        /* Set Kseg0 cacheable, coherent, write-back, write-allocate */
+        mfc0    t0, CP0_CONFIG
+        ori     t0, 0x7
+        xori    t0, 0x2
+        mtc0    t0, CP0_CONFIG
+        ehb
+        /* Enter the coherent domain */
+        li      t0, 0xff
+        sw      t0, GCR_CL_COHERENCE_OFS(v1)
+        ehb
+        /* Jump to kseg0 */
+        la      t0, 1f
+        jr      t0
+         nop
+1:      /* We're up, cached & coherent */
+        /*
+         * TODO: We should check the VPE number we intended to boot here, and
+         *       if non-zero we should start that VPE and stop this one. For
+         *       the moment this doesn't matter since CPUs are brought up
+         *       sequentially and in order, but once hotplug is implemented
+         *       this will need revisiting.
+         */
+        /* Off we go! */
+        la      t0, mips_cps_bootcfg
+        lw      t1, BOOTCFG_PC(t0)
+        lw      gp, BOOTCFG_GP(t0)
+        lw      sp, BOOTCFG_SP(t0)
+        jr      t1
+         nop
+        END(mips_cps_core_entry)
+.org 0x200
+LEAF(excep_tlbfill)
+        b       .
+         nop
+        END(excep_tlbfill)
+.org 0x280
+LEAF(excep_xtlbfill)
+        b       .
+         nop
+        END(excep_xtlbfill)
+.org 0x300
+LEAF(excep_cache)
+        b       .
+         nop
+        END(excep_cache)
+.org 0x380
+LEAF(excep_genex)
+        b       .
+         nop
+        END(excep_genex)
+.org 0x400
+LEAF(excep_intex)
+        b       .
+         nop
+        END(excep_intex)
+.org 0x480
+LEAF(excep_ejtag)
+        la      k0, ejtag_debug_handler
+        jr      k0
+         nop
+        END(excep_ejtag)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 530f832de02c..6e8fb85ce7c3 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -23,6 +23,8 @@
 #include <asm/cpu-type.h>
 #include <asm/fpu.h>
 #include <asm/mipsregs.h>
+#include <asm/mipsmtregs.h>
+#include <asm/msa.h>
 #include <asm/watch.h>
 #include <asm/elf.h>
 #include <asm/spram.h>
@@ -126,6 +128,20 @@ static inline int __cpu_has_fpu(void)
        return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
 }
+static inline unsigned long cpu_get_msa_id(void)
+{
+        unsigned long status, conf5, msa_id;
+        status = read_c0_status();
+        __enable_fpu(FPU_64BIT);
+        conf5 = read_c0_config5();
+        enable_msa();
+        msa_id = read_msa_ir();
+        write_c0_config5(conf5);
+        write_c0_status(status);
+        return msa_id;
+}
 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 {
 #ifdef __NEED_VMBITS_PROBE
@@ -166,11 +182,12 @@ static char unknown_isa[] = KERN_ERR \
 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 {
        unsigned int config6;
-        /*
-         * Config6 is implementation dependent and it's currently only
+        /* It's implementation dependent how the FTLB can be enabled */
-         * used by proAptiv
+        switch (c->cputype) {
-         */
+        case CPU_PROAPTIV:
-        if (c->cputype == CPU_PROAPTIV) {
+        case CPU_P5600:
+                /* proAptiv & related cores use Config6 to enable the FTLB */
                config6 = read_c0_config6();
                if (enable)
                        /* Enable FTLB */
@@ -179,6 +196,7 @@ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
                        /* Disable FTLB */
                        write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
                back_to_back_c0_hazard();
+                break;
        }
 }
@@ -301,6 +319,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                c->ases |= MIPS_ASE_VZ;
        if (config3 & MIPS_CONF3_SC)
                c->options |= MIPS_CPU_SEGMENTS;
+        if (config3 & MIPS_CONF3_MSA)
+                c->ases |= MIPS_ASE_MSA;
        return config3 & MIPS_CONF_M;
 }
@@ -367,6 +387,9 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
        config5 &= ~MIPS_CONF5_UFR;
        write_c0_config5(config5);
+        if (config5 & MIPS_CONF5_EVA)
+                c->options |= MIPS_CPU_EVA;
        return config5 & MIPS_CONF_M;
 }
@@ -398,8 +421,13 @@ static void decode_configs(struct cpuinfo_mips *c)
        mips_probe_watch_registers(c);
-        if (cpu_has_mips_r2)
+#ifndef CONFIG_MIPS_CPS
+        if (cpu_has_mips_r2) {
                c->core = read_c0_ebase() & 0x3ff;
+                if (cpu_has_mipsmt)
+                        c->core >>= fls(core_nvpes()) - 1;
+        }
+#endif
 }
 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
@@ -710,17 +738,23 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                             MIPS_CPU_LLSC;
                c->tlbsize = 64;
                break;
-        case PRID_IMP_LOONGSON2:
+        case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
-                c->cputype = CPU_LOONGSON2;
-                __cpu_name[cpu] = "ICT Loongson-2";
                switch (c->processor_id & PRID_REV_MASK) {
                case PRID_REV_LOONGSON2E:
+                        c->cputype = CPU_LOONGSON2;
+                        __cpu_name[cpu] = "ICT Loongson-2";
                        set_elf_platform(cpu, "loongson2e");
                        break;
                case PRID_REV_LOONGSON2F:
+                        c->cputype = CPU_LOONGSON2;
+                        __cpu_name[cpu] = "ICT Loongson-2";
                        set_elf_platform(cpu, "loongson2f");
                        break;
+                case PRID_REV_LOONGSON3A:
+                        c->cputype = CPU_LOONGSON3;
+                        __cpu_name[cpu] = "ICT Loongson-3";
+                        set_elf_platform(cpu, "loongson3a");
+                        break;
                }
                set_isa(c, MIPS_CPU_ISA_III);
@@ -729,7 +763,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                             MIPS_CPU_32FPR;
                c->tlbsize = 64;
                break;
-        case PRID_IMP_LOONGSON1:
+        case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
                decode_configs(c);
                c->cputype = CPU_LOONGSON1;
@@ -806,7 +840,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                __cpu_name[cpu] = "MIPS 1004Kc";
                break;
        case PRID_IMP_1074K:
-                c->cputype = CPU_74K;
+                c->cputype = CPU_1074K;
                __cpu_name[cpu] = "MIPS 1074Kc";
                break;
        case PRID_IMP_INTERAPTIV_UP:
@@ -825,6 +859,14 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                c->cputype = CPU_PROAPTIV;
                __cpu_name[cpu] = "MIPS proAptiv (multi)";
                break;
+        case PRID_IMP_P5600:
+                c->cputype = CPU_P5600;
+                __cpu_name[cpu] = "MIPS P5600";
+                break;
+        case PRID_IMP_M5150:
+                c->cputype = CPU_M5150;
+                __cpu_name[cpu] = "MIPS M5150";
+                break;
        }
        decode_configs(c);
@@ -1176,6 +1218,12 @@ void cpu_probe(void)
        else
                c->srsets = 1;
+        if (cpu_has_msa) {
+                c->msa_id = cpu_get_msa_id();
+                WARN(c->msa_id & MSA_IR_WRPF,
+                     "Vector register partitioning unimplemented!");
+        }
        cpu_probe_vmbits(c);
 #ifdef CONFIG_64BIT
@@ -1192,4 +1240,6 @@ void cpu_report(void)
                smp_processor_id(), c->processor_id, cpu_name_string());
        if (c->options & MIPS_CPU_FPU)
                printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
+        if (cpu_has_msa)
+                pr_info("MSA revision is: %08x\n", c->msa_id);
 }
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 374ed74cd516..60e7e5e45af1 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -90,6 +90,7 @@ static inline void ftrace_dyn_arch_init_insns(void)
 static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
 {
        int faulted;
+        mm_segment_t old_fs;
        /* *(unsigned int *)ip = new_code; */
        safe_store_code(new_code, ip, faulted);
@@ -97,7 +98,10 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
        if (unlikely(faulted))
                return -EFAULT;
+        old_fs = get_fs();
+        set_fs(get_ds());
        flush_icache_range(ip, ip + 8);
+        set_fs(old_fs);
        return 0;
 }
@@ -197,7 +201,7 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
        return ftrace_modify_code(FTRACE_CALL_IP, new);
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
        /* Encode the instructions when booting */
        ftrace_dyn_arch_init_insns();
@@ -205,9 +209,6 @@ int __init ftrace_dyn_arch_init(void *data)
        /* Remove "b ftrace_stub" to ensure ftrace_caller() is executed */
        ftrace_modify_code(MCOUNT_ADDR, INSN_NOP);
-        /* The return code is retured via data */
-        *(unsigned long *)data = 0;
        return 0;
 }
 #endif  /* CONFIG_DYNAMIC_FTRACE */
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index d84f6a509502..a9ce3408be25 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -67,7 +67,7 @@ NESTED(except_vec3_generic, 0, sp)
 */
 NESTED(except_vec3_r4000, 0, sp)
        .set    push
-        .set    mips3
+        .set    arch=r4000
        .set    noat
        mfc0    k1, CP0_CAUSE
        li      k0, 31<<2
@@ -139,7 +139,7 @@ LEAF(__r4k_wait)
        nop
        nop
 #endif
-        .set    mips3
+        .set    arch=r4000
        wait
        /* end of rollback region (the region size must be power of two) */
 1:
@@ -475,8 +475,10 @@ NESTED(nmi_handler, PT_SIZE, sp)
        BUILD_HANDLER cpu cpu sti silent                /* #11 */
        BUILD_HANDLER ov ov sti silent                  /* #12 */
        BUILD_HANDLER tr tr sti silent                  /* #13 */
+        BUILD_HANDLER msa_fpe msa_fpe sti silent        /* #14 */
        BUILD_HANDLER fpe fpe fpe silent                /* #15 */
        BUILD_HANDLER ftlb ftlb none silent             /* #16 */
+        BUILD_HANDLER msa msa sti silent                /* #21 */
        BUILD_HANDLER mdmx mdmx sti silent              /* #22 */
 #ifdef  CONFIG_HARDWARE_WATCHPOINTS
        /*
@@ -575,7 +577,7 @@ isrdhwr:
        ori     k1, _THREAD_MASK
        xori    k1, _THREAD_MASK
        LONG_L  v1, TI_TP_VALUE(k1)
-        .set    mips3
+        .set    arch=r4000
        eret
        .set    mips0
 #endif
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 7b6a5b3e3acf..e712dcf18b2d 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -175,8 +175,8 @@ NESTED(smp_bootstrap, 16, sp)
        DMT     10      # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
        jal     mips_ihb
 #endif /* CONFIG_MIPS_MT_SMTC */
-        setup_c0_status_sec
        smp_slave_setup
+        setup_c0_status_sec
 #ifdef CONFIG_MIPS_MT_SMTC
        andi    t2, t2, VPECONTROL_TE
        beqz    t2, 2f
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 3553243bf9d6..837ff27950bc 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -64,7 +64,7 @@ void r4k_wait_irqoff(void)
        if (!need_resched())
                __asm__(
                "       .set    push            \n"
-                "       .set    mips3           \n"
+                "       .set    arch=r4000      \n"
                "       wait                    \n"
                "       .set    pop             \n");
        local_irq_enable();
@@ -82,7 +82,7 @@ static void rm7k_wait_irqoff(void)
        if (!need_resched())
                __asm__(
                "       .set    push                                    \n"
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "       .set    noat                                    \n"
                "       mfc0    $1, $12                                 \n"
                "       sync                                            \n"
@@ -103,7 +103,7 @@ static void au1k_wait(void)
        unsigned long c0status = read_c0_status() | 1;  /* irqs on */
        __asm__(
-        "       .set    mips3                   \n"
+        "       .set    arch=r4000                      \n"
        "       cache   0x14, 0(%0)             \n"
        "       cache   0x14, 32(%0)            \n"
        "       sync                            \n"
@@ -184,8 +184,11 @@ void __init check_wait(void)
        case CPU_24K:
        case CPU_34K:
        case CPU_1004K:
+        case CPU_1074K:
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
+        case CPU_P5600:
+        case CPU_M5150:
                cpu_wait = r4k_wait;
                if (read_c0_config7() & MIPS_CONF7_WII)
                        cpu_wait = r4k_wait_irqoff;
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 5b5ddb231f26..8520dad6d4e3 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -16,7 +16,6 @@
 #include <asm/gic.h>
 #include <asm/setup.h>
 #include <asm/traps.h>
-#include <asm/gcmpregs.h>
 #include <linux/hardirq.h>
 #include <asm-generic/bitops/find.h>
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index fcaac2f132f0..7afcc2f22c0d 100644
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -32,6 +32,7 @@
 #include <asm/cacheflush.h>
 #include <asm/processor.h>
 #include <asm/sigcontext.h>
+#include <asm/uaccess.h>
 static struct hard_trap_info {
        unsigned char tt;       /* Trap type code for MIPS R3xxx and R4xxx */
@@ -208,7 +209,14 @@ void arch_kgdb_breakpoint(void)
 static void kgdb_call_nmi_hook(void *ignored)
 {
+        mm_segment_t old_fs;
+        old_fs = get_fs();
+        set_fs(get_ds());
        kgdb_nmicallback(raw_smp_processor_id(), NULL);
+        set_fs(old_fs);
 }
 void kgdb_roundup_cpus(unsigned long flags)
@@ -282,6 +290,7 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd,
        struct die_args *args = (struct die_args *)ptr;
        struct pt_regs *regs = args->regs;
        int trap = (regs->cp0_cause & 0x7c) >> 2;
+        mm_segment_t old_fs;
 #ifdef CONFIG_KPROBES
        /*
@@ -296,11 +305,17 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd,
        if (user_mode(regs))
                return NOTIFY_DONE;
+        /* Kernel mode. Set correct address limit */
+        old_fs = get_fs();
+        set_fs(get_ds());
        if (atomic_read(&kgdb_active) != -1)
                kgdb_nmicallback(smp_processor_id(), regs);
-        if (kgdb_handle_exception(trap, compute_signal(trap), cmd, regs))
+        if (kgdb_handle_exception(trap, compute_signal(trap), cmd, regs)) {
+                set_fs(old_fs);
                return NOTIFY_DONE;
+        }
        if (atomic_read(&kgdb_setting_breakpoint))
                if ((trap == 9) && (regs->cp0_epc == (unsigned long)breakinst))
@@ -310,6 +325,7 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd,
        local_irq_enable();
        __flush_cache_all();
+        set_fs(old_fs);
        return NOTIFY_STOP;
 }
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
new file mode 100644
index 000000000000..f76f7a08412d
--- /dev/null
+++ b/arch/mips/kernel/mips-cm.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/errno.h>
+#include <asm/mips-cm.h>
+#include <asm/mipsregs.h>
+void __iomem *mips_cm_base;
+void __iomem *mips_cm_l2sync_base;
+phys_t __mips_cm_phys_base(void)
+{
+        u32 config3 = read_c0_config3();
+        u32 cmgcr;
+        /* Check the CMGCRBase register is implemented */
+        if (!(config3 & MIPS_CONF3_CMGCR))
+                return 0;
+        /* Read the address from CMGCRBase */
+        cmgcr = read_c0_cmgcrbase();
+        return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
+}
+phys_t mips_cm_phys_base(void)
+        __attribute__((weak, alias("__mips_cm_phys_base")));
+phys_t __mips_cm_l2sync_phys_base(void)
+{
+        u32 base_reg;
+        /*
+         * If the L2-only sync region is already enabled then leave it at it's
+         * current location.
+         */
+        base_reg = read_gcr_l2_only_sync_base();
+        if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK)
+                return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK;
+        /* Default to following the CM */
+        return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
+}
+phys_t mips_cm_l2sync_phys_base(void)
+        __attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
+static void mips_cm_probe_l2sync(void)
+{
+        unsigned major_rev;
+        phys_t addr;
+        /* L2-only sync was introduced with CM major revision 6 */
+        major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
+                CM_GCR_REV_MAJOR_SHF;
+        if (major_rev < 6)
+                return;
+        /* Find a location for the L2 sync region */
+        addr = mips_cm_l2sync_phys_base();
+        BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK) != addr);
+        if (!addr)
+                return;
+        /* Set the region base address & enable it */
+        write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK);
+        /* Map the region */
+        mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
+}
+int mips_cm_probe(void)
+{
+        phys_t addr;
+        u32 base_reg;
+        addr = mips_cm_phys_base();
+        BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr);
+        if (!addr)
+                return -ENODEV;
+        mips_cm_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
+        if (!mips_cm_base)
+                return -ENXIO;
+        /* sanity check that we're looking at a CM */
+        base_reg = read_gcr_base();
+        if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) {
+                pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
+                       (unsigned long)addr);
+                mips_cm_base = NULL;
+                return -ENODEV;
+        }
+        /* set default target to memory */
+        base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
+        base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;
+        write_gcr_base(base_reg);
+        /* disable CM regions */
+        write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+        write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+        write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+        write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+        write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+        write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+        write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+        write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+        /* probe for an L2-only sync region */
+        mips_cm_probe_l2sync();
+        return 0;
+}
diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
new file mode 100644
index 000000000000..c9dc67402969
--- /dev/null
+++ b/arch/mips/kernel/mips-cpc.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/errno.h>
+#include <asm/mips-cm.h>
+#include <asm/mips-cpc.h>
+void __iomem *mips_cpc_base;
+phys_t __weak mips_cpc_phys_base(void)
+{
+        u32 cpc_base;
+        if (!mips_cm_present())
+                return 0;
+        if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK))
+                return 0;
+        /* If the CPC is already enabled, leave it so */
+        cpc_base = read_gcr_cpc_base();
+        if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK)
+                return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK;
+        /* Otherwise, give it the default address & enable it */
+        cpc_base = mips_cpc_default_phys_base();
+        write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK);
+        return cpc_base;
+}
+int mips_cpc_probe(void)
+{
+        phys_t addr;
+        addr = mips_cpc_phys_base();
+        if (!addr)
+                return -ENODEV;
+        mips_cpc_base = ioremap_nocache(addr, 0x8000);
+        if (!mips_cpc_base)
+                return -ENXIO;
+        return 0;
+}
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 6e58e97fcd39..2607c3a4ff7e 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -16,12 +16,20 @@
 #include <asm/ftrace.h>
 extern void *__bzero(void *__s, size_t __count);
+extern long __strncpy_from_kernel_nocheck_asm(char *__to,
+                                              const char *__from, long __len);
+extern long __strncpy_from_kernel_asm(char *__to, const char *__from,
+                                      long __len);
 extern long __strncpy_from_user_nocheck_asm(char *__to,
                                            const char *__from, long __len);
 extern long __strncpy_from_user_asm(char *__to, const char *__from,
                                    long __len);
+extern long __strlen_kernel_nocheck_asm(const char *s);
+extern long __strlen_kernel_asm(const char *s);
 extern long __strlen_user_nocheck_asm(const char *s);
 extern long __strlen_user_asm(const char *s);
+extern long __strnlen_kernel_nocheck_asm(const char *s);
+extern long __strnlen_kernel_asm(const char *s);
 extern long __strnlen_user_nocheck_asm(const char *s);
 extern long __strnlen_user_asm(const char *s);
@@ -43,17 +51,31 @@ EXPORT_SYMBOL(copy_page);
 */
 EXPORT_SYMBOL(__copy_user);
 EXPORT_SYMBOL(__copy_user_inatomic);
+#ifdef CONFIG_EVA
+EXPORT_SYMBOL(__copy_from_user_eva);
+EXPORT_SYMBOL(__copy_in_user_eva);
+EXPORT_SYMBOL(__copy_to_user_eva);
+EXPORT_SYMBOL(__copy_user_inatomic_eva);
+#endif
 EXPORT_SYMBOL(__bzero);
+EXPORT_SYMBOL(__strncpy_from_kernel_nocheck_asm);
+EXPORT_SYMBOL(__strncpy_from_kernel_asm);
 EXPORT_SYMBOL(__strncpy_from_user_nocheck_asm);
 EXPORT_SYMBOL(__strncpy_from_user_asm);
+EXPORT_SYMBOL(__strlen_kernel_nocheck_asm);
+EXPORT_SYMBOL(__strlen_kernel_asm);
 EXPORT_SYMBOL(__strlen_user_nocheck_asm);
 EXPORT_SYMBOL(__strlen_user_asm);
+EXPORT_SYMBOL(__strnlen_kernel_nocheck_asm);
+EXPORT_SYMBOL(__strnlen_kernel_asm);
 EXPORT_SYMBOL(__strnlen_user_nocheck_asm);
 EXPORT_SYMBOL(__strnlen_user_asm);
 EXPORT_SYMBOL(csum_partial);
 EXPORT_SYMBOL(csum_partial_copy_nocheck);
-EXPORT_SYMBOL(__csum_partial_copy_user);
+EXPORT_SYMBOL(__csum_partial_copy_kernel);
+EXPORT_SYMBOL(__csum_partial_copy_to_user);
+EXPORT_SYMBOL(__csum_partial_copy_from_user);
 EXPORT_SYMBOL(invalid_pte_table);
 #ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 24cdf64789c3..4f2d9dece7ab 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -805,7 +805,7 @@ static void reset_counters(void *arg)
        }
 }
-/* 24K/34K/1004K cores can share the same event map. */
+/* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
 static const struct mips_perf_event mipsxxcore_event_map
                                [PERF_COUNT_HW_MAX] = {
        [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
@@ -814,8 +814,8 @@ static const struct mips_perf_event mipsxxcore_event_map
        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
 };
-/* 74K core has different branch event code. */
+/* 74K/proAptiv core has different branch event code. */
-static const struct mips_perf_event mipsxx74Kcore_event_map
+static const struct mips_perf_event mipsxxcore_event_map2
                                [PERF_COUNT_HW_MAX] = {
        [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
@@ -849,7 +849,7 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
 };
-/* 24K/34K/1004K cores can share the same cache event map. */
+/* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
 static const struct mips_perf_event mipsxxcore_cache_map
                                [PERF_COUNT_HW_CACHE_MAX]
                                [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -930,8 +930,8 @@ static const struct mips_perf_event mipsxxcore_cache_map
 },
 };
-/* 74K core has completely different cache event map. */
+/* 74K/proAptiv core has completely different cache event map. */
-static const struct mips_perf_event mipsxx74Kcore_cache_map
+static const struct mips_perf_event mipsxxcore_cache_map2
                                [PERF_COUNT_HW_CACHE_MAX]
                                [PERF_COUNT_HW_CACHE_OP_MAX]
                                [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -978,6 +978,11 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
                [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN, P },
        },
 },
+/*
+ * 74K core does not have specific DTLB events. proAptiv core has
+ * "speculative" DTLB events which are numbered 0x63 (even/odd) and
+ * not included here. One can use raw events if really needed.
+ */
 [C(ITLB)] = {
        [C(OP_READ)] = {
                [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
@@ -1378,6 +1383,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
 #define IS_BOTH_COUNTERS_74K_EVENT(b)                                   \
        ((b) == 0 || (b) == 1)
+/* proAptiv */
+#define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b)                              \
+        ((b) == 0 || (b) == 1)
 /* 1004K */
 #define IS_BOTH_COUNTERS_1004K_EVENT(b)                                 \
        ((b) == 0 || (b) == 1 || (b) == 11)
@@ -1391,6 +1400,20 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
 #define IS_RANGE_V_1004K_EVENT(r)       ((r) == 47)
 #endif
+/* interAptiv */
+#define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b)                            \
+        ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+/* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
+#define IS_RANGE_P_INTERAPTIV_EVENT(r, b)                               \
+        ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
+         (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 ||            \
+         (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 &&         \
+         (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 ||          \
+         ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_INTERAPTIV_EVENT(r)  ((r) == 47 || (r) == 175)
+#endif
 /* BMIPS5000 */
 #define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b)                             \
        ((b) == 0 || (b) == 1)
@@ -1442,6 +1465,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 #endif
                break;
        case CPU_74K:
+        case CPU_1074K:
                if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
                else
@@ -1451,6 +1475,16 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
                raw_event.range = P;
 #endif
                break;
+        case CPU_PROAPTIV:
+                if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                raw_event.range = P;
+#endif
+                break;
        case CPU_1004K:
                if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
@@ -1466,6 +1500,21 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
                        raw_event.range = T;
 #endif
                break;
+        case CPU_INTERAPTIV:
+                if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
+                        raw_event.range = P;
+                else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
+                        raw_event.range = V;
+                else
+                        raw_event.range = T;
+#endif
+                break;
        case CPU_BMIPS5000:
                if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
@@ -1576,14 +1625,29 @@ init_hw_perf_events(void)
                break;
        case CPU_74K:
                mipspmu.name = "mips/74K";
-                mipspmu.general_event_map = &mipsxx74Kcore_event_map;
+                mipspmu.general_event_map = &mipsxxcore_event_map2;
-                mipspmu.cache_event_map = &mipsxx74Kcore_cache_map;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map2;
+                break;
+        case CPU_PROAPTIV:
+                mipspmu.name = "mips/proAptiv";
+                mipspmu.general_event_map = &mipsxxcore_event_map2;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map2;
                break;
        case CPU_1004K:
                mipspmu.name = "mips/1004K";
                mipspmu.general_event_map = &mipsxxcore_event_map;
                mipspmu.cache_event_map = &mipsxxcore_cache_map;
                break;
+        case CPU_1074K:
+                mipspmu.name = "mips/1074K";
+                mipspmu.general_event_map = &mipsxxcore_event_map;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map;
+                break;
+        case CPU_INTERAPTIV:
+                mipspmu.name = "mips/interAptiv";
+                mipspmu.general_event_map = &mipsxxcore_event_map;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map;
+                break;
        case CPU_LOONGSON1:
                mipspmu.name = "mips/loongson1";
                mipspmu.general_event_map = &mipsxxcore_event_map;
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 00d20974b3e7..e40971b51d2f 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -17,8 +17,24 @@
 unsigned int vced_count, vcei_count;
+/*
+ *  * No lock; only written during early bootup by CPU 0.
+ *   */
+static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain);
+int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb)
+{
+        return raw_notifier_chain_register(&proc_cpuinfo_chain, nb);
+}
+int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
+{
+        return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
+}
 static int show_cpuinfo(struct seq_file *m, void *v)
 {
+        struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
        unsigned long n = (unsigned long) v - 1;
        unsigned int version = cpu_data[n].processor_id;
        unsigned int fp_vers = cpu_data[n].fpu_id;
@@ -95,6 +111,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        if (cpu_has_mipsmt)     seq_printf(m, "%s", " mt");
        if (cpu_has_mmips)      seq_printf(m, "%s", " micromips");
        if (cpu_has_vz)         seq_printf(m, "%s", " vz");
+        if (cpu_has_msa)        seq_printf(m, "%s", " msa");
+        if (cpu_has_eva)        seq_printf(m, "%s", " eva");
        seq_printf(m, "\n");
        if (cpu_has_mmips) {
@@ -118,6 +136,13 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                      cpu_has_vce ? "%u" : "not available");
        seq_printf(m, fmt, 'D', vced_count);
        seq_printf(m, fmt, 'I', vcei_count);
+        proc_cpuinfo_notifier_args.m = m;
+        proc_cpuinfo_notifier_args.n = n;
+        raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
+                                &proc_cpuinfo_notifier_args);
        seq_printf(m, "\n");
        return 0;
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 6ae540e133b2..60e39dc7f1eb 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -32,6 +32,7 @@
 #include <asm/cpu.h>
 #include <asm/dsp.h>
 #include <asm/fpu.h>
+#include <asm/msa.h>
 #include <asm/pgtable.h>
 #include <asm/mipsregs.h>
 #include <asm/processor.h>
@@ -65,6 +66,8 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
        clear_used_math();
        clear_fpu_owner();
        init_dsp();
+        clear_thread_flag(TIF_MSA_CTX_LIVE);
+        disable_msa();
        regs->cp0_epc = pc;
        regs->regs[29] = sp;
 }
@@ -89,7 +92,9 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
        preempt_disable();
-        if (is_fpu_owner())
+        if (is_msa_enabled())
+                save_msa(p);
+        else if (is_fpu_owner())
                save_fp(p);
        if (cpu_has_dsp)
@@ -157,7 +162,13 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
 /* Fill in the fpu structure for a core dump.. */
 int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r)
 {
-        memcpy(r, &current->thread.fpu, sizeof(current->thread.fpu));
+        int i;
+        for (i = 0; i < NUM_FPU_REGS; i++)
+                memcpy(&r[i], &current->thread.fpu.fpr[i], sizeof(*r));
+        memcpy(&r[NUM_FPU_REGS], &current->thread.fpu.fcr31,
+               sizeof(current->thread.fpu.fcr31));
        return 1;
 }
@@ -192,7 +203,13 @@ int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
 int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr)
 {
-        memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu));
+        int i;
+        for (i = 0; i < NUM_FPU_REGS; i++)
+                memcpy(&fpr[i], &t->thread.fpu.fpr[i], sizeof(*fpr));
+        memcpy(&fpr[NUM_FPU_REGS], &t->thread.fpu.fcr31,
+               sizeof(t->thread.fpu.fcr31));
        return 1;
 }
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 7da9b76db4d9..71f85f427034 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -114,51 +114,30 @@ int ptrace_setregs(struct task_struct *child, __s64 __user *data)
 int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
 {
        int i;
-        unsigned int tmp;
        if (!access_ok(VERIFY_WRITE, data, 33 * 8))
                return -EIO;
        if (tsk_used_math(child)) {
-                fpureg_t *fregs = get_fpu_regs(child);
+                union fpureg *fregs = get_fpu_regs(child);
                for (i = 0; i < 32; i++)
-                        __put_user(fregs[i], i + (__u64 __user *) data);
+                        __put_user(get_fpr64(&fregs[i], 0),
+                                   i + (__u64 __user *)data);
        } else {
                for (i = 0; i < 32; i++)
                        __put_user((__u64) -1, i + (__u64 __user *) data);
        }
        __put_user(child->thread.fpu.fcr31, data + 64);
+        __put_user(current_cpu_data.fpu_id, data + 65);
-        preempt_disable();
-        if (cpu_has_fpu) {
-                unsigned int flags;
-                if (cpu_has_mipsmt) {
-                        unsigned int vpflags = dvpe();
-                        flags = read_c0_status();
-                        __enable_fpu(FPU_AS_IS);
-                        __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
-                        write_c0_status(flags);
-                        evpe(vpflags);
-                } else {
-                        flags = read_c0_status();
-                        __enable_fpu(FPU_AS_IS);
-                        __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
-                        write_c0_status(flags);
-                }
-        } else {
-                tmp = 0;
-        }
-        preempt_enable();
-        __put_user(tmp, data + 65);
        return 0;
 }
 int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
 {
-        fpureg_t *fregs;
+        union fpureg *fregs;
+        u64 fpr_val;
        int i;
        if (!access_ok(VERIFY_READ, data, 33 * 8))
@@ -166,8 +145,10 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
        fregs = get_fpu_regs(child);
-        for (i = 0; i < 32; i++)
+        for (i = 0; i < 32; i++) {
-                __get_user(fregs[i], i + (__u64 __user *) data);
+                __get_user(fpr_val, i + (__u64 __user *)data);
+                set_fpr64(&fregs[i], 0, fpr_val);
+        }
        __get_user(child->thread.fpu.fcr31, data + 64);
@@ -300,10 +281,27 @@ static int fpr_get(struct task_struct *target,
                   unsigned int pos, unsigned int count,
                   void *kbuf, void __user *ubuf)
 {
-        return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+        unsigned i;
-                                   &target->thread.fpu,
+        int err;
-                                   0, sizeof(elf_fpregset_t));
+        u64 fpr_val;
        /* XXX fcr31  */
+        if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
+                return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                           &target->thread.fpu,
+                                           0, sizeof(elf_fpregset_t));
+        for (i = 0; i < NUM_FPU_REGS; i++) {
+                fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);
+                err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                          &fpr_val, i * sizeof(elf_fpreg_t),
+                                          (i + 1) * sizeof(elf_fpreg_t));
+                if (err)
+                        return err;
+        }
+        return 0;
 }
 static int fpr_set(struct task_struct *target,
@@ -311,10 +309,27 @@ static int fpr_set(struct task_struct *target,
                   unsigned int pos, unsigned int count,
                   const void *kbuf, const void __user *ubuf)
 {
-        return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+        unsigned i;
-                                  &target->thread.fpu,
+        int err;
-                                  0, sizeof(elf_fpregset_t));
+        u64 fpr_val;
        /* XXX fcr31  */
+        if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
+                return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                          &target->thread.fpu,
+                                          0, sizeof(elf_fpregset_t));
+        for (i = 0; i < NUM_FPU_REGS; i++) {
+                err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                         &fpr_val, i * sizeof(elf_fpreg_t),
+                                         (i + 1) * sizeof(elf_fpreg_t));
+                if (err)
+                        return err;
+                set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
+        }
+        return 0;
 }
 enum mips_regset {
@@ -408,7 +423,7 @@ long arch_ptrace(struct task_struct *child, long request,
        /* Read the word at location addr in the USER area. */
        case PTRACE_PEEKUSR: {
                struct pt_regs *regs;
-                fpureg_t *fregs;
+                union fpureg *fregs;
                unsigned long tmp = 0;
                regs = task_pt_regs(child);
@@ -433,14 +448,12 @@ long arch_ptrace(struct task_struct *child, long request,
                                 * order bits of the values stored in the even
                                 * registers - unless we're using r2k_switch.S.
                                 */
-                                if (addr & 1)
+                                tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
-                                        tmp = fregs[(addr & ~1) - 32] >> 32;
+                                                addr & 1);
-                                else
-                                        tmp = fregs[addr - 32];
                                break;
                        }
 #endif
-                        tmp = fregs[addr - FPR_BASE];
+                        tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
                        break;
                case PC:
                        tmp = regs->cp0_epc;
@@ -465,44 +478,10 @@ long arch_ptrace(struct task_struct *child, long request,
                case FPC_CSR:
                        tmp = child->thread.fpu.fcr31;
                        break;
-                case FPC_EIR: { /* implementation / version register */
+                case FPC_EIR:
-                        unsigned int flags;
+                        /* implementation / version register */
-#ifdef CONFIG_MIPS_MT_SMTC
+                        tmp = current_cpu_data.fpu_id;
-                        unsigned long irqflags;
-                        unsigned int mtflags;
-#endif /* CONFIG_MIPS_MT_SMTC */
-                        preempt_disable();
-                        if (!cpu_has_fpu) {
-                                preempt_enable();
-                                break;
-                        }
-#ifdef CONFIG_MIPS_MT_SMTC
-                        /* Read-modify-write of Status must be atomic */
-                        local_irq_save(irqflags);
-                        mtflags = dmt();
-#endif /* CONFIG_MIPS_MT_SMTC */
-                        if (cpu_has_mipsmt) {
-                                unsigned int vpflags = dvpe();
-                                flags = read_c0_status();
-                                __enable_fpu(FPU_AS_IS);
-                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                                write_c0_status(flags);
-                                evpe(vpflags);
-                        } else {
-                                flags = read_c0_status();
-                                __enable_fpu(FPU_AS_IS);
-                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                                write_c0_status(flags);
-                        }
-#ifdef CONFIG_MIPS_MT_SMTC
-                        emt(mtflags);
-                        local_irq_restore(irqflags);
-#endif /* CONFIG_MIPS_MT_SMTC */
-                        preempt_enable();
                        break;
-                }
                case DSP_BASE ... DSP_BASE + 5: {
                        dspreg_t *dregs;
@@ -548,7 +527,7 @@ long arch_ptrace(struct task_struct *child, long request,
                        regs->regs[addr] = data;
                        break;
                case FPR_BASE ... FPR_BASE + 31: {
-                        fpureg_t *fregs = get_fpu_regs(child);
+                        union fpureg *fregs = get_fpu_regs(child);
                        if (!tsk_used_math(child)) {
                                /* FP not yet used  */
@@ -563,19 +542,12 @@ long arch_ptrace(struct task_struct *child, long request,
                                 * order bits of the values stored in the even
                                 * registers - unless we're using r2k_switch.S.
                                 */
-                                if (addr & 1) {
+                                set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
-                                        fregs[(addr & ~1) - FPR_BASE] &=
+                                          addr & 1, data);
-                                                0xffffffff;
-                                        fregs[(addr & ~1) - FPR_BASE] |=
-                                                ((u64)data) << 32;
-                                } else {
-                                        fregs[addr - FPR_BASE] &= ~0xffffffffLL;
-                                        fregs[addr - FPR_BASE] |= data;
-                                }
                                break;
                        }
 #endif
-                        fregs[addr - FPR_BASE] = data;
+                        set_fpr64(&fregs[addr - FPR_BASE], 0, data);
                        break;
                }
                case PC:
@@ -662,13 +634,13 @@ long arch_ptrace(struct task_struct *child, long request,
 * Notification of system call entry/exit
 * - triggered by current->work.syscall_trace
 */
-asmlinkage void syscall_trace_enter(struct pt_regs *regs)
+asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
 {
        long ret = 0;
        user_exit();
-        /* do the secure computing check first */
+        if (secure_computing(syscall) == -1)
-        secure_computing_strict(regs->regs[2]);
+                return -1;
        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
            tracehook_report_syscall_entry(regs))
@@ -677,10 +649,11 @@ asmlinkage void syscall_trace_enter(struct pt_regs *regs)
        if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
                trace_sys_enter(regs, regs->regs[2]);
-        audit_syscall_entry(__syscall_get_arch(),
+        audit_syscall_entry(syscall_get_arch(),
-                            regs->regs[2],
+                            syscall,
                            regs->regs[4], regs->regs[5],
                            regs->regs[6], regs->regs[7]);
+        return syscall;
 }
 /*
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index b8aa2dd5b00b..b40c3ca60ee5 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -80,7 +80,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
        /* Read the word at location addr in the USER area. */
        case PTRACE_PEEKUSR: {
                struct pt_regs *regs;
-                fpureg_t *fregs;
+                union fpureg *fregs;
                unsigned int tmp;
                regs = task_pt_regs(child);
@@ -103,13 +103,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                                 * order bits of the values stored in the even
                                 * registers - unless we're using r2k_switch.S.
                                 */
-                                if (addr & 1)
+                                tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
-                                        tmp = fregs[(addr & ~1) - 32] >> 32;
+                                                addr & 1);
-                                else
-                                        tmp = fregs[addr - 32];
                                break;
                        }
-                        tmp = fregs[addr - FPR_BASE];
+                        tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
                        break;
                case PC:
                        tmp = regs->cp0_epc;
@@ -129,46 +127,10 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                case FPC_CSR:
                        tmp = child->thread.fpu.fcr31;
                        break;
-                case FPC_EIR: { /* implementation / version register */
+                case FPC_EIR:
-                        unsigned int flags;
+                        /* implementation / version register */
-#ifdef CONFIG_MIPS_MT_SMTC
+                        tmp = current_cpu_data.fpu_id;
-                        unsigned int irqflags;
-                        unsigned int mtflags;
-#endif /* CONFIG_MIPS_MT_SMTC */
-                        preempt_disable();
-                        if (!cpu_has_fpu) {
-                                preempt_enable();
-                                tmp = 0;
-                                break;
-                        }
-#ifdef CONFIG_MIPS_MT_SMTC
-                        /* Read-modify-write of Status must be atomic */
-                        local_irq_save(irqflags);
-                        mtflags = dmt();
-#endif /* CONFIG_MIPS_MT_SMTC */
-                        if (cpu_has_mipsmt) {
-                                unsigned int vpflags = dvpe();
-                                flags = read_c0_status();
-                                __enable_fpu(FPU_AS_IS);
-                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                                write_c0_status(flags);
-                                evpe(vpflags);
-                        } else {
-                                flags = read_c0_status();
-                                __enable_fpu(FPU_AS_IS);
-                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                                write_c0_status(flags);
-                        }
-#ifdef CONFIG_MIPS_MT_SMTC
-                        emt(mtflags);
-                        local_irq_restore(irqflags);
-#endif /* CONFIG_MIPS_MT_SMTC */
-                        preempt_enable();
                        break;
-                }
                case DSP_BASE ... DSP_BASE + 5: {
                        dspreg_t *dregs;
@@ -233,7 +195,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                        regs->regs[addr] = data;
                        break;
                case FPR_BASE ... FPR_BASE + 31: {
-                        fpureg_t *fregs = get_fpu_regs(child);
+                        union fpureg *fregs = get_fpu_regs(child);
                        if (!tsk_used_math(child)) {
                                /* FP not yet used  */
@@ -247,18 +209,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                                 * order bits of the values stored in the even
                                 * registers - unless we're using r2k_switch.S.
                                 */
-                                if (addr & 1) {
+                                set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
-                                        fregs[(addr & ~1) - FPR_BASE] &=
+                                          addr & 1, data);
-                                                0xffffffff;
-                                        fregs[(addr & ~1) - FPR_BASE] |=
-                                                ((u64)data) << 32;
-                                } else {
-                                        fregs[addr - FPR_BASE] &= ~0xffffffffLL;
-                                        fregs[addr - FPR_BASE] |= data;
-                                }
                                break;
                        }
-                        fregs[addr - FPR_BASE] = data;
+                        set_fpr64(&fregs[addr - FPR_BASE], 0, data);
                        break;
                }
                case PC:
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 73b0ddf910d4..71814272d148 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -13,6 +13,7 @@
 * Copyright (C) 1999, 2001 Silicon Graphics, Inc.
 */
 #include <asm/asm.h>
+#include <asm/asmmacro.h>
 #include <asm/errno.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
@@ -30,7 +31,7 @@
        .endm
        .set    noreorder
-        .set    mips3
+        .set    arch=r4000
 LEAF(_save_fp_context)
        cfc1    t1, fcr31
@@ -245,6 +246,218 @@ LEAF(_restore_fp_context32)
        END(_restore_fp_context32)
 #endif
+#ifdef CONFIG_CPU_HAS_MSA
+        .macro  save_sc_msareg  wr, off, sc, tmp
+#ifdef CONFIG_64BIT
+        copy_u_d \tmp, \wr, 1
+        EX sd   \tmp, (\off+(\wr*8))(\sc)
+#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
+        copy_u_w \tmp, \wr, 2
+        EX sw   \tmp, (\off+(\wr*8)+0)(\sc)
+        copy_u_w \tmp, \wr, 3
+        EX sw   \tmp, (\off+(\wr*8)+4)(\sc)
+#else /* CONFIG_CPU_BIG_ENDIAN */
+        copy_u_w \tmp, \wr, 2
+        EX sw   \tmp, (\off+(\wr*8)+4)(\sc)
+        copy_u_w \tmp, \wr, 3
+        EX sw   \tmp, (\off+(\wr*8)+0)(\sc)
+#endif
+        .endm
+/*
+ * int _save_msa_context(struct sigcontext *sc)
+ *
+ * Save the upper 64 bits of each vector register along with the MSA_CSR
+ * register into sc. Returns zero on success, else non-zero.
+ */
+LEAF(_save_msa_context)
+        save_sc_msareg  0, SC_MSAREGS, a0, t0
+        save_sc_msareg  1, SC_MSAREGS, a0, t0
+        save_sc_msareg  2, SC_MSAREGS, a0, t0
+        save_sc_msareg  3, SC_MSAREGS, a0, t0
+        save_sc_msareg  4, SC_MSAREGS, a0, t0
+        save_sc_msareg  5, SC_MSAREGS, a0, t0
+        save_sc_msareg  6, SC_MSAREGS, a0, t0
+        save_sc_msareg  7, SC_MSAREGS, a0, t0
+        save_sc_msareg  8, SC_MSAREGS, a0, t0
+        save_sc_msareg  9, SC_MSAREGS, a0, t0
+        save_sc_msareg  10, SC_MSAREGS, a0, t0
+        save_sc_msareg  11, SC_MSAREGS, a0, t0
+        save_sc_msareg  12, SC_MSAREGS, a0, t0
+        save_sc_msareg  13, SC_MSAREGS, a0, t0
+        save_sc_msareg  14, SC_MSAREGS, a0, t0
+        save_sc_msareg  15, SC_MSAREGS, a0, t0
+        save_sc_msareg  16, SC_MSAREGS, a0, t0
+        save_sc_msareg  17, SC_MSAREGS, a0, t0
+        save_sc_msareg  18, SC_MSAREGS, a0, t0
+        save_sc_msareg  19, SC_MSAREGS, a0, t0
+        save_sc_msareg  20, SC_MSAREGS, a0, t0
+        save_sc_msareg  21, SC_MSAREGS, a0, t0
+        save_sc_msareg  22, SC_MSAREGS, a0, t0
+        save_sc_msareg  23, SC_MSAREGS, a0, t0
+        save_sc_msareg  24, SC_MSAREGS, a0, t0
+        save_sc_msareg  25, SC_MSAREGS, a0, t0
+        save_sc_msareg  26, SC_MSAREGS, a0, t0
+        save_sc_msareg  27, SC_MSAREGS, a0, t0
+        save_sc_msareg  28, SC_MSAREGS, a0, t0
+        save_sc_msareg  29, SC_MSAREGS, a0, t0
+        save_sc_msareg  30, SC_MSAREGS, a0, t0
+        save_sc_msareg  31, SC_MSAREGS, a0, t0
+        jr      ra
+         li     v0, 0
+        END(_save_msa_context)
+#ifdef CONFIG_MIPS32_COMPAT
+/*
+ * int _save_msa_context32(struct sigcontext32 *sc)
+ *
+ * Save the upper 64 bits of each vector register along with the MSA_CSR
+ * register into sc. Returns zero on success, else non-zero.
+ */
+LEAF(_save_msa_context32)
+        save_sc_msareg  0, SC32_MSAREGS, a0, t0
+        save_sc_msareg  1, SC32_MSAREGS, a0, t0
+        save_sc_msareg  2, SC32_MSAREGS, a0, t0
+        save_sc_msareg  3, SC32_MSAREGS, a0, t0
+        save_sc_msareg  4, SC32_MSAREGS, a0, t0
+        save_sc_msareg  5, SC32_MSAREGS, a0, t0
+        save_sc_msareg  6, SC32_MSAREGS, a0, t0
+        save_sc_msareg  7, SC32_MSAREGS, a0, t0
+        save_sc_msareg  8, SC32_MSAREGS, a0, t0
+        save_sc_msareg  9, SC32_MSAREGS, a0, t0
+        save_sc_msareg  10, SC32_MSAREGS, a0, t0
+        save_sc_msareg  11, SC32_MSAREGS, a0, t0
+        save_sc_msareg  12, SC32_MSAREGS, a0, t0
+        save_sc_msareg  13, SC32_MSAREGS, a0, t0
+        save_sc_msareg  14, SC32_MSAREGS, a0, t0
+        save_sc_msareg  15, SC32_MSAREGS, a0, t0
+        save_sc_msareg  16, SC32_MSAREGS, a0, t0
+        save_sc_msareg  17, SC32_MSAREGS, a0, t0
+        save_sc_msareg  18, SC32_MSAREGS, a0, t0
+        save_sc_msareg  19, SC32_MSAREGS, a0, t0
+        save_sc_msareg  20, SC32_MSAREGS, a0, t0
+        save_sc_msareg  21, SC32_MSAREGS, a0, t0
+        save_sc_msareg  22, SC32_MSAREGS, a0, t0
+        save_sc_msareg  23, SC32_MSAREGS, a0, t0
+        save_sc_msareg  24, SC32_MSAREGS, a0, t0
+        save_sc_msareg  25, SC32_MSAREGS, a0, t0
+        save_sc_msareg  26, SC32_MSAREGS, a0, t0
+        save_sc_msareg  27, SC32_MSAREGS, a0, t0
+        save_sc_msareg  28, SC32_MSAREGS, a0, t0
+        save_sc_msareg  29, SC32_MSAREGS, a0, t0
+        save_sc_msareg  30, SC32_MSAREGS, a0, t0
+        save_sc_msareg  31, SC32_MSAREGS, a0, t0
+        jr      ra
+         li     v0, 0
+        END(_save_msa_context32)
+#endif /* CONFIG_MIPS32_COMPAT */
+        .macro restore_sc_msareg        wr, off, sc, tmp
+#ifdef CONFIG_64BIT
+        EX ld   \tmp, (\off+(\wr*8))(\sc)
+        insert_d \wr, 1, \tmp
+#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
+        EX lw   \tmp, (\off+(\wr*8)+0)(\sc)
+        insert_w \wr, 2, \tmp
+        EX lw   \tmp, (\off+(\wr*8)+4)(\sc)
+        insert_w \wr, 3, \tmp
+#else /* CONFIG_CPU_BIG_ENDIAN */
+        EX lw   \tmp, (\off+(\wr*8)+4)(\sc)
+        insert_w \wr, 2, \tmp
+        EX lw   \tmp, (\off+(\wr*8)+0)(\sc)
+        insert_w \wr, 3, \tmp
+#endif
+        .endm
+/*
+ * int _restore_msa_context(struct sigcontext *sc)
+ */
+LEAF(_restore_msa_context)
+        restore_sc_msareg       0, SC_MSAREGS, a0, t0
+        restore_sc_msareg       1, SC_MSAREGS, a0, t0
+        restore_sc_msareg       2, SC_MSAREGS, a0, t0
+        restore_sc_msareg       3, SC_MSAREGS, a0, t0
+        restore_sc_msareg       4, SC_MSAREGS, a0, t0
+        restore_sc_msareg       5, SC_MSAREGS, a0, t0
+        restore_sc_msareg       6, SC_MSAREGS, a0, t0
+        restore_sc_msareg       7, SC_MSAREGS, a0, t0
+        restore_sc_msareg       8, SC_MSAREGS, a0, t0
+        restore_sc_msareg       9, SC_MSAREGS, a0, t0
+        restore_sc_msareg       10, SC_MSAREGS, a0, t0
+        restore_sc_msareg       11, SC_MSAREGS, a0, t0
+        restore_sc_msareg       12, SC_MSAREGS, a0, t0
+        restore_sc_msareg       13, SC_MSAREGS, a0, t0
+        restore_sc_msareg       14, SC_MSAREGS, a0, t0
+        restore_sc_msareg       15, SC_MSAREGS, a0, t0
+        restore_sc_msareg       16, SC_MSAREGS, a0, t0
+        restore_sc_msareg       17, SC_MSAREGS, a0, t0
+        restore_sc_msareg       18, SC_MSAREGS, a0, t0
+        restore_sc_msareg       19, SC_MSAREGS, a0, t0
+        restore_sc_msareg       20, SC_MSAREGS, a0, t0
+        restore_sc_msareg       21, SC_MSAREGS, a0, t0
+        restore_sc_msareg       22, SC_MSAREGS, a0, t0
+        restore_sc_msareg       23, SC_MSAREGS, a0, t0
+        restore_sc_msareg       24, SC_MSAREGS, a0, t0
+        restore_sc_msareg       25, SC_MSAREGS, a0, t0
+        restore_sc_msareg       26, SC_MSAREGS, a0, t0
+        restore_sc_msareg       27, SC_MSAREGS, a0, t0
+        restore_sc_msareg       28, SC_MSAREGS, a0, t0
+        restore_sc_msareg       29, SC_MSAREGS, a0, t0
+        restore_sc_msareg       30, SC_MSAREGS, a0, t0
+        restore_sc_msareg       31, SC_MSAREGS, a0, t0
+        jr      ra
+         li     v0, 0
+        END(_restore_msa_context)
+#ifdef CONFIG_MIPS32_COMPAT
+/*
+ * int _restore_msa_context32(struct sigcontext32 *sc)
+ */
+LEAF(_restore_msa_context32)
+        restore_sc_msareg       0, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       1, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       2, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       3, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       4, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       5, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       6, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       7, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       8, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       9, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       10, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       11, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       12, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       13, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       14, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       15, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       16, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       17, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       18, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       19, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       20, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       21, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       22, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       23, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       24, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       25, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       26, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       27, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       28, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       29, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       30, SC32_MSAREGS, a0, t0
+        restore_sc_msareg       31, SC32_MSAREGS, a0, t0
+        jr      ra
+         li     v0, 0
+        END(_restore_msa_context32)
+#endif /* CONFIG_MIPS32_COMPAT */
+#endif /* CONFIG_CPU_HAS_MSA */
        .set    reorder
        .type   fault@function
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index cc78dd9a17c7..abacac7c33ef 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -29,18 +29,8 @@
 #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
 /*
- * FPU context is saved iff the process has used it's FPU in the current
- * time slice as indicated by _TIF_USEDFPU.  In any case, the CU1 bit for user
- * space STATUS register should be 0, so that a process *always* starts its
- * userland with FPU disabled after each context switch.
- *
- * FPU will be enabled as soon as the process accesses FPU again, through
- * do_cpu() trap.
- */
-/*
 * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti, int usedfpu)
+ *                     struct thread_info *next_ti, s32 fp_save)
 */
        .align  5
        LEAF(resume)
@@ -50,23 +40,37 @@
        LONG_S  ra, THREAD_REG31(a0)
        /*
-         * check if we need to save FPU registers
+         * Check whether we need to save any FP context. FP context is saved
+         * iff the process has used the context with the scalar FPU or the MSA
+         * ASE in the current time slice, as indicated by _TIF_USEDFPU and
+         * _TIF_USEDMSA respectively. switch_to will have set fp_save
+         * accordingly to an FP_SAVE_ enum value.
         */
+        beqz    a3, 2f
-        beqz    a3, 1f
-        PTR_L   t3, TASK_THREAD_INFO(a0)
        /*
-         * clear saved user stack CU1 bit
+         * We do. Clear the saved CU1 bit for prev, such that next time it is
+         * scheduled it will start in userland with the FPU disabled. If the
+         * task uses the FPU then it will be enabled again via the do_cpu trap.
+         * This allows us to lazily restore the FP context.
         */
+        PTR_L   t3, TASK_THREAD_INFO(a0)
        LONG_L  t0, ST_OFF(t3)
        li      t1, ~ST0_CU1
        and     t0, t0, t1
        LONG_S  t0, ST_OFF(t3)
+        /* Check whether we're saving scalar or vector context. */
+        bgtz    a3, 1f
+        /* Save 128b MSA vector context. */
+        msa_save_all    a0
+        b       2f
+1:      /* Save 32b/64b scalar FP context. */
        fpu_save_double a0 t0 t1                # c0_status passed in t0
                                                # clobbers t1
-1:
+2:
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
        PTR_LA  t8, __stack_chk_guard
@@ -141,6 +145,26 @@ LEAF(_restore_fp)
        jr      ra
        END(_restore_fp)
+#ifdef CONFIG_CPU_HAS_MSA
+/*
+ * Save a thread's MSA vector context.
+ */
+LEAF(_save_msa)
+        msa_save_all    a0
+        jr      ra
+        END(_save_msa)
+/*
+ * Restore a thread's MSA vector context.
+ */
+LEAF(_restore_msa)
+        msa_restore_all a0
+        jr      ra
+        END(_restore_msa)
+#endif
 /*
 * Load the FPU with signalling NANS.  This bit pattern we're using has
 * the property that no matter whether considered as single or as double
@@ -270,7 +294,7 @@ LEAF(_init_fpu)
 1:      .set    pop
 #endif /* CONFIG_CPU_MIPS32_R2 */
 #else
-        .set    mips3
+        .set    arch=r4000
        dmtc1   t1, $f0
        dmtc1   t1, $f2
        dmtc1   t1, $f4
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index a5b14f48e1af..fdc70b400442 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -6,6 +6,7 @@
 * Copyright (C) 1995-99, 2000- 02, 06 Ralf Baechle <ralf@linux-mips.org>
 * Copyright (C) 2001 MIPS Technologies, Inc.
 * Copyright (C) 2004 Thiemo Seufer
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 */
 #include <linux/errno.h>
 #include <asm/asm.h>
@@ -74,10 +75,10 @@ NESTED(handle_sys, PT_SIZE, sp)
        .set    noreorder
        .set    nomacro
-1:      lw      t5, 16(t0)              # argument #5 from usp
+1:      user_lw(t5, 16(t0))             # argument #5 from usp
-4:      lw      t6, 20(t0)              # argument #6 from usp
+4:      user_lw(t6, 20(t0))             # argument #6 from usp
-3:      lw      t7, 24(t0)              # argument #7 from usp
+3:      user_lw(t7, 24(t0))             # argument #7 from usp
-2:      lw      t8, 28(t0)              # argument #8 from usp
+2:      user_lw(t8, 28(t0))             # argument #8 from usp
        sw      t5, 16(sp)              # argument #5 to ksp
        sw      t6, 20(sp)              # argument #6 to ksp
@@ -118,7 +119,18 @@ syscall_trace_entry:
        SAVE_STATIC
        move    s0, t2
        move    a0, sp
-        jal     syscall_trace_enter
+        /*
+         * syscall number is in v0 unless we called syscall(__NR_###)
+         * where the real syscall number is in a0
+         */
+        addiu   a1, v0,  __NR_O32_Linux
+        bnez    v0, 1f /* __NR_syscall at offset 0 */
+        lw      a1, PT_R4(sp)
+1:      jal     syscall_trace_enter
+        bltz    v0, 2f                  # seccomp failed? Skip syscall
        move    t0, s0
        RESTORE_STATIC
@@ -138,7 +150,7 @@ syscall_trace_entry:
        sw      t1, PT_R0(sp)           # save it for syscall restarting
 1:      sw      v0, PT_R2(sp)           # result
-        j       syscall_exit
+2:      j       syscall_exit
 /* ------------------------------------------------------------------------ */
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index b56e254beb15..dd99c3285aea 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -80,8 +80,11 @@ syscall_trace_entry:
        SAVE_STATIC
        move    s0, t2
        move    a0, sp
+        daddiu  a1, v0, __NR_64_Linux
        jal     syscall_trace_enter
+        bltz    v0, 2f                  # seccomp failed? Skip syscall
        move    t0, s0
        RESTORE_STATIC
        ld      a0, PT_R4(sp)           # Restore argument registers
@@ -102,7 +105,7 @@ syscall_trace_entry:
        sd      t1, PT_R0(sp)           # save it for syscall restarting
 1:      sd      v0, PT_R2(sp)           # result
-        j       syscall_exit
+2:      j       syscall_exit
 illegal_syscall:
        /* This also isn't a 64-bit syscall, throw an error.  */
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index f7e5b72cf481..f68d2f4f0090 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -72,8 +72,11 @@ n32_syscall_trace_entry:
        SAVE_STATIC
        move    s0, t2
        move    a0, sp
+        daddiu  a1, v0, __NR_N32_Linux
        jal     syscall_trace_enter
+        bltz    v0, 2f                  # seccomp failed? Skip syscall
        move    t0, s0
        RESTORE_STATIC
        ld      a0, PT_R4(sp)           # Restore argument registers
@@ -94,7 +97,7 @@ n32_syscall_trace_entry:
        sd      t1, PT_R0(sp)           # save it for syscall restarting
 1:      sd      v0, PT_R2(sp)           # result
-        j       syscall_exit
+2:      j       syscall_exit
 not_n32_scall:
        /* This is not an n32 compatibility syscall, pass it on to
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 6788727d91af..70f6acecd928 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -112,7 +112,20 @@ trace_a_syscall:
        move    s0, t2                  # Save syscall pointer
        move    a0, sp
-        jal     syscall_trace_enter
+        /*
+         * syscall number is in v0 unless we called syscall(__NR_###)
+         * where the real syscall number is in a0
+         * note: NR_syscall is the first O32 syscall but the macro is
+         * only defined when compiling with -mabi=32 (CONFIG_32BIT)
+         * therefore __NR_O32_Linux is used (4000)
+         */
+        addiu   a1, v0,  __NR_O32_Linux
+        bnez    v0, 1f /* __NR_syscall at offset 0 */
+        lw      a1, PT_R4(sp)
+1:      jal     syscall_trace_enter
+        bltz    v0, 2f                  # seccomp failed? Skip syscall
        move    t0, s0
        RESTORE_STATIC
@@ -136,7 +149,7 @@ trace_a_syscall:
        sd      t1, PT_R0(sp)           # save it for syscall restarting
 1:      sd      v0, PT_R2(sp)           # result
-        j       syscall_exit
+2:      j       syscall_exit
 /* ------------------------------------------------------------------------ */
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 5199563c4403..33133d3df3e5 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -6,6 +6,7 @@
 * Copyright (C) 1991, 1992  Linus Torvalds
 * Copyright (C) 1994 - 2000  Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2014, Imagination Technologies Ltd.
 */
 #include <linux/cache.h>
 #include <linux/context_tracking.h>
@@ -30,6 +31,7 @@
 #include <linux/bitops.h>
 #include <asm/cacheflush.h>
 #include <asm/fpu.h>
+#include <asm/msa.h>
 #include <asm/sim.h>
 #include <asm/ucontext.h>
 #include <asm/cpu-features.h>
@@ -46,8 +48,8 @@ static int (*restore_fp_context)(struct sigcontext __user *sc);
 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
-extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
+extern asmlinkage int _save_msa_context(struct sigcontext __user *sc);
-extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
+extern asmlinkage int _restore_msa_context(struct sigcontext __user *sc);
 struct sigframe {
        u32 sf_ass[4];          /* argument save space for o32 */
@@ -64,17 +66,95 @@ struct rt_sigframe {
 };
 /*
+ * Thread saved context copy to/from a signal context presumed to be on the
+ * user stack, and therefore accessed with appropriate macros from uaccess.h.
+ */
+static int copy_fp_to_sigcontext(struct sigcontext __user *sc)
+{
+        int i;
+        int err = 0;
+        for (i = 0; i < NUM_FPU_REGS; i++) {
+                err |=
+                    __put_user(get_fpr64(&current->thread.fpu.fpr[i], 0),
+                               &sc->sc_fpregs[i]);
+        }
+        err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
+        return err;
+}
+static int copy_fp_from_sigcontext(struct sigcontext __user *sc)
+{
+        int i;
+        int err = 0;
+        u64 fpr_val;
+        for (i = 0; i < NUM_FPU_REGS; i++) {
+                err |= __get_user(fpr_val, &sc->sc_fpregs[i]);
+                set_fpr64(&current->thread.fpu.fpr[i], 0, fpr_val);
+        }
+        err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
+        return err;
+}
+/*
+ * These functions will save only the upper 64 bits of the vector registers,
+ * since the lower 64 bits have already been saved as the scalar FP context.
+ */
+static int copy_msa_to_sigcontext(struct sigcontext __user *sc)
+{
+        int i;
+        int err = 0;
+        for (i = 0; i < NUM_FPU_REGS; i++) {
+                err |=
+                    __put_user(get_fpr64(&current->thread.fpu.fpr[i], 1),
+                               &sc->sc_msaregs[i]);
+        }
+        err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
+        return err;
+}
+static int copy_msa_from_sigcontext(struct sigcontext __user *sc)
+{
+        int i;
+        int err = 0;
+        u64 val;
+        for (i = 0; i < NUM_FPU_REGS; i++) {
+                err |= __get_user(val, &sc->sc_msaregs[i]);
+                set_fpr64(&current->thread.fpu.fpr[i], 1, val);
+        }
+        err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
+        return err;
+}
+/*
 * Helper routines
 */
-static int protected_save_fp_context(struct sigcontext __user *sc)
+static int protected_save_fp_context(struct sigcontext __user *sc,
+                                     unsigned used_math)
 {
        int err;
+        bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
+#ifndef CONFIG_EVA
        while (1) {
                lock_fpu_owner();
-                err = own_fpu_inatomic(1);
+                if (is_fpu_owner()) {
-                if (!err)
+                        err = save_fp_context(sc);
-                        err = save_fp_context(sc); /* this might fail */
+                        if (save_msa && !err)
-                unlock_fpu_owner();
+                                err = _save_msa_context(sc);
+                        unlock_fpu_owner();
+                } else {
+                        unlock_fpu_owner();
+                        err = copy_fp_to_sigcontext(sc);
+                        if (save_msa && !err)
+                                err = copy_msa_to_sigcontext(sc);
+                }
                if (likely(!err))
                        break;
                /* touch the sigcontext and try again */
@@ -84,18 +164,44 @@ static int protected_save_fp_context(struct sigcontext __user *sc)
                if (err)
                        break;  /* really bad sigcontext */
        }
+#else
+        /*
+         * EVA does not have FPU EVA instructions so saving fpu context directly
+         * does not work.
+         */
+        disable_msa();
+        lose_fpu(1);
+        err = save_fp_context(sc); /* this might fail */
+        if (save_msa && !err)
+                err = copy_msa_to_sigcontext(sc);
+#endif
        return err;
 }
-static int protected_restore_fp_context(struct sigcontext __user *sc)
+static int protected_restore_fp_context(struct sigcontext __user *sc,
+                                        unsigned used_math)
 {
        int err, tmp __maybe_unused;
+        bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
+#ifndef CONFIG_EVA
        while (1) {
                lock_fpu_owner();
-                err = own_fpu_inatomic(0);
+                if (is_fpu_owner()) {
-                if (!err)
+                        err = restore_fp_context(sc);
-                        err = restore_fp_context(sc); /* this might fail */
+                        if (restore_msa && !err) {
-                unlock_fpu_owner();
+                                enable_msa();
+                                err = _restore_msa_context(sc);
+                        } else {
+                                /* signal handler may have used MSA */
+                                disable_msa();
+                        }
+                        unlock_fpu_owner();
+                } else {
+                        unlock_fpu_owner();
+                        err = copy_fp_from_sigcontext(sc);
+                        if (!err && (used_math & USEDMATH_MSA))
+                                err = copy_msa_from_sigcontext(sc);
+                }
                if (likely(!err))
                        break;
                /* touch the sigcontext and try again */
@@ -105,6 +211,17 @@ static int protected_restore_fp_context(struct sigcontext __user *sc)
                if (err)
                        break;  /* really bad sigcontext */
        }
+#else
+        /*
+         * EVA does not have FPU EVA instructions so restoring fpu context
+         * directly does not work.
+         */
+        enable_msa();
+        lose_fpu(0);
+        err = restore_fp_context(sc); /* this might fail */
+        if (restore_msa && !err)
+                err = copy_msa_from_sigcontext(sc);
+#endif
        return err;
 }
@@ -135,7 +252,8 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
                err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
        }
-        used_math = !!used_math();
+        used_math = used_math() ? USEDMATH_FP : 0;
+        used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0;
        err |= __put_user(used_math, &sc->sc_used_math);
        if (used_math) {
@@ -143,7 +261,7 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
                 * Save FPU state to signal context. Signal handler
                 * will "inherit" current FPU state.
                 */
-                err |= protected_save_fp_context(sc);
+                err |= protected_save_fp_context(sc, used_math);
        }
        return err;
 }
@@ -168,14 +286,14 @@ int fpcsr_pending(unsigned int __user *fpcsr)
 }
 static int
-check_and_restore_fp_context(struct sigcontext __user *sc)
+check_and_restore_fp_context(struct sigcontext __user *sc, unsigned used_math)
 {
        int err, sig;
        err = sig = fpcsr_pending(&sc->sc_fpc_csr);
        if (err > 0)
                err = 0;
-        err |= protected_restore_fp_context(sc);
+        err |= protected_restore_fp_context(sc, used_math);
        return err ?: sig;
 }
@@ -215,9 +333,10 @@ int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
        if (used_math) {
                /* restore fpu context if we have used it before */
                if (!err)
-                        err = check_and_restore_fp_context(sc);
+                        err = check_and_restore_fp_context(sc, used_math);
        } else {
-                /* signal handler may have used FPU.  Give it up. */
+                /* signal handler may have used FPU or MSA. Disable them. */
+                disable_msa();
                lose_fpu(0);
        }
@@ -591,23 +710,26 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
 }
 #ifdef CONFIG_SMP
+#ifndef CONFIG_EVA
 static int smp_save_fp_context(struct sigcontext __user *sc)
 {
        return raw_cpu_has_fpu
               ? _save_fp_context(sc)
-               : fpu_emulator_save_context(sc);
+               : copy_fp_to_sigcontext(sc);
 }
 static int smp_restore_fp_context(struct sigcontext __user *sc)
 {
        return raw_cpu_has_fpu
               ? _restore_fp_context(sc)
-               : fpu_emulator_restore_context(sc);
+               : copy_fp_from_sigcontext(sc);
 }
+#endif /* CONFIG_EVA */
 #endif
 static int signal_setup(void)
 {
+#ifndef CONFIG_EVA
 #ifdef CONFIG_SMP
        /* For now just do the cpu_has_fpu check when the functions are invoked */
        save_fp_context = smp_save_fp_context;
@@ -617,9 +739,13 @@ static int signal_setup(void)
                save_fp_context = _save_fp_context;
                restore_fp_context = _restore_fp_context;
        } else {
-                save_fp_context = fpu_emulator_save_context;
+                save_fp_context = copy_fp_from_sigcontext;
-                restore_fp_context = fpu_emulator_restore_context;
+                restore_fp_context = copy_fp_to_sigcontext;
        }
+#endif /* CONFIG_SMP */
+#else
+        save_fp_context = copy_fp_from_sigcontext;;
+        restore_fp_context = copy_fp_to_sigcontext;
 #endif
        return 0;
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 3d60f7750fa8..299f956e4db3 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -30,6 +30,7 @@
 #include <asm/sim.h>
 #include <asm/ucontext.h>
 #include <asm/fpu.h>
+#include <asm/msa.h>
 #include <asm/war.h>
 #include <asm/vdso.h>
 #include <asm/dsp.h>
@@ -42,8 +43,8 @@ static int (*restore_fp_context32)(struct sigcontext32 __user *sc);
 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
-extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
+extern asmlinkage int _save_msa_context32(struct sigcontext32 __user *sc);
-extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
+extern asmlinkage int _restore_msa_context32(struct sigcontext32 __user *sc);
 /*
 * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
@@ -78,17 +79,96 @@ struct rt_sigframe32 {
 };
 /*
+ * Thread saved context copy to/from a signal context presumed to be on the
+ * user stack, and therefore accessed with appropriate macros from uaccess.h.
+ */
+static int copy_fp_to_sigcontext32(struct sigcontext32 __user *sc)
+{
+        int i;
+        int err = 0;
+        int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
+        for (i = 0; i < NUM_FPU_REGS; i += inc) {
+                err |=
+                    __put_user(get_fpr64(&current->thread.fpu.fpr[i], 0),
+                               &sc->sc_fpregs[i]);
+        }
+        err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
+        return err;
+}
+static int copy_fp_from_sigcontext32(struct sigcontext32 __user *sc)
+{
+        int i;
+        int err = 0;
+        int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
+        u64 fpr_val;
+        for (i = 0; i < NUM_FPU_REGS; i += inc) {
+                err |= __get_user(fpr_val, &sc->sc_fpregs[i]);
+                set_fpr64(&current->thread.fpu.fpr[i], 0, fpr_val);
+        }
+        err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
+        return err;
+}
+/*
+ * These functions will save only the upper 64 bits of the vector registers,
+ * since the lower 64 bits have already been saved as the scalar FP context.
+ */
+static int copy_msa_to_sigcontext32(struct sigcontext32 __user *sc)
+{
+        int i;
+        int err = 0;
+        for (i = 0; i < NUM_FPU_REGS; i++) {
+                err |=
+                    __put_user(get_fpr64(&current->thread.fpu.fpr[i], 1),
+                               &sc->sc_msaregs[i]);
+        }
+        err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
+        return err;
+}
+static int copy_msa_from_sigcontext32(struct sigcontext32 __user *sc)
+{
+        int i;
+        int err = 0;
+        u64 val;
+        for (i = 0; i < NUM_FPU_REGS; i++) {
+                err |= __get_user(val, &sc->sc_msaregs[i]);
+                set_fpr64(&current->thread.fpu.fpr[i], 1, val);
+        }
+        err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
+        return err;
+}
+/*
 * sigcontext handlers
 */
-static int protected_save_fp_context32(struct sigcontext32 __user *sc)
+static int protected_save_fp_context32(struct sigcontext32 __user *sc,
+                                       unsigned used_math)
 {
        int err;
+        bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
        while (1) {
                lock_fpu_owner();
-                err = own_fpu_inatomic(1);
+                if (is_fpu_owner()) {
-                if (!err)
+                        err = save_fp_context32(sc);
-                        err = save_fp_context32(sc); /* this might fail */
+                        if (save_msa && !err)
-                unlock_fpu_owner();
+                                err = _save_msa_context32(sc);
+                        unlock_fpu_owner();
+                } else {
+                        unlock_fpu_owner();
+                        err = copy_fp_to_sigcontext32(sc);
+                        if (save_msa && !err)
+                                err = copy_msa_to_sigcontext32(sc);
+                }
                if (likely(!err))
                        break;
                /* touch the sigcontext and try again */
@@ -101,15 +181,29 @@ static int protected_save_fp_context32(struct sigcontext32 __user *sc)
        return err;
 }
-static int protected_restore_fp_context32(struct sigcontext32 __user *sc)
+static int protected_restore_fp_context32(struct sigcontext32 __user *sc,
+                                          unsigned used_math)
 {
        int err, tmp __maybe_unused;
+        bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
        while (1) {
                lock_fpu_owner();
-                err = own_fpu_inatomic(0);
+                if (is_fpu_owner()) {
-                if (!err)
+                        err = restore_fp_context32(sc);
-                        err = restore_fp_context32(sc); /* this might fail */
+                        if (restore_msa && !err) {
-                unlock_fpu_owner();
+                                enable_msa();
+                                err = _restore_msa_context32(sc);
+                        } else {
+                                /* signal handler may have used MSA */
+                                disable_msa();
+                        }
+                        unlock_fpu_owner();
+                } else {
+                        unlock_fpu_owner();
+                        err = copy_fp_from_sigcontext32(sc);
+                        if (restore_msa && !err)
+                                err = copy_msa_from_sigcontext32(sc);
+                }
                if (likely(!err))
                        break;
                /* touch the sigcontext and try again */
@@ -147,7 +241,8 @@ static int setup_sigcontext32(struct pt_regs *regs,
                err |= __put_user(mflo3(), &sc->sc_lo3);
        }
-        used_math = !!used_math();
+        used_math = used_math() ? USEDMATH_FP : 0;
+        used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0;
        err |= __put_user(used_math, &sc->sc_used_math);
        if (used_math) {
@@ -155,20 +250,21 @@ static int setup_sigcontext32(struct pt_regs *regs,
                 * Save FPU state to signal context.  Signal handler
                 * will "inherit" current FPU state.
                 */
-                err |= protected_save_fp_context32(sc);
+                err |= protected_save_fp_context32(sc, used_math);
        }
        return err;
 }
 static int
-check_and_restore_fp_context32(struct sigcontext32 __user *sc)
+check_and_restore_fp_context32(struct sigcontext32 __user *sc,
+                               unsigned used_math)
 {
        int err, sig;
        err = sig = fpcsr_pending(&sc->sc_fpc_csr);
        if (err > 0)
                err = 0;
-        err |= protected_restore_fp_context32(sc);
+        err |= protected_restore_fp_context32(sc, used_math);
        return err ?: sig;
 }
@@ -205,9 +301,10 @@ static int restore_sigcontext32(struct pt_regs *regs,
        if (used_math) {
                /* restore fpu context if we have used it before */
                if (!err)
-                        err = check_and_restore_fp_context32(sc);
+                        err = check_and_restore_fp_context32(sc, used_math);
        } else {
-                /* signal handler may have used FPU.  Give it up. */
+                /* signal handler may have used FPU or MSA. Disable them. */
+                disable_msa();
                lose_fpu(0);
        }
@@ -566,8 +663,8 @@ static int signal32_init(void)
                save_fp_context32 = _save_fp_context32;
                restore_fp_context32 = _restore_fp_context32;
        } else {
-                save_fp_context32 = fpu_emulator_save_context32;
+                save_fp_context32 = copy_fp_to_sigcontext32;
-                restore_fp_context32 = fpu_emulator_restore_context32;
+                restore_fp_context32 = copy_fp_from_sigcontext32;
        }
        return 0;
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index 1b925d8a610c..3ef55fb7ac03 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -39,57 +39,9 @@
 #include <asm/amon.h>
 #include <asm/gic.h>
-static void ipi_call_function(unsigned int cpu)
-{
-        pr_debug("CPU%d: %s cpu %d status %08x\n",
-                 smp_processor_id(), __func__, cpu, read_c0_status());
-        gic_send_ipi(plat_ipi_call_int_xlate(cpu));
-}
-static void ipi_resched(unsigned int cpu)
-{
-        pr_debug("CPU%d: %s cpu %d status %08x\n",
-                 smp_processor_id(), __func__, cpu, read_c0_status());
-        gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
-}
-/*
- * FIXME: This isn't restricted to CMP
- * The SMVP kernel could use GIC interrupts if available
- */
-void cmp_send_ipi_single(int cpu, unsigned int action)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (action) {
-        case SMP_CALL_FUNCTION:
-                ipi_call_function(cpu);
-                break;
-        case SMP_RESCHEDULE_YOURSELF:
-                ipi_resched(cpu);
-                break;
-        }
-        local_irq_restore(flags);
-}
-static void cmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
-{
-        unsigned int i;
-        for_each_cpu(i, mask)
-                cmp_send_ipi_single(i, action);
-}
 static void cmp_init_secondary(void)
 {
-        struct cpuinfo_mips *c = &current_cpu_data;
+        struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
        /* Assume GIC is present */
        change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
@@ -97,7 +49,6 @@ static void cmp_init_secondary(void)
        /* Enable per-cpu interrupts: platform specific */
-        c->core = (read_c0_ebase() >> 1) & 0x1ff;
 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
        if (cpu_has_mipsmt)
                c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
@@ -210,8 +161,8 @@ void __init cmp_prepare_cpus(unsigned int max_cpus)
 }
 struct plat_smp_ops cmp_smp_ops = {
-        .send_ipi_single        = cmp_send_ipi_single,
+        .send_ipi_single        = gic_send_ipi_single,
-        .send_ipi_mask          = cmp_send_ipi_mask,
+        .send_ipi_mask          = gic_send_ipi_mask,
        .init_secondary         = cmp_init_secondary,
        .smp_finish             = cmp_smp_finish,
        .cpus_done              = cmp_cpus_done,
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
new file mode 100644
index 000000000000..536eec0d21b6
--- /dev/null
+++ b/arch/mips/kernel/smp-cps.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
+#include <linux/types.h>
+#include <asm/cacheflush.h>
+#include <asm/gic.h>
+#include <asm/mips-cm.h>
+#include <asm/mips-cpc.h>
+#include <asm/mips_mt.h>
+#include <asm/mipsregs.h>
+#include <asm/smp-cps.h>
+#include <asm/time.h>
+#include <asm/uasm.h>
+static DECLARE_BITMAP(core_power, NR_CPUS);
+struct boot_config mips_cps_bootcfg;
+static void init_core(void)
+{
+        unsigned int nvpes, t;
+        u32 mvpconf0, vpeconf0, vpecontrol, tcstatus, tcbind, status;
+        if (!cpu_has_mipsmt)
+                return;
+        /* Enter VPE configuration state */
+        dvpe();
+        set_c0_mvpcontrol(MVPCONTROL_VPC);
+        /* Retrieve the count of VPEs in this core */
+        mvpconf0 = read_c0_mvpconf0();
+        nvpes = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
+        smp_num_siblings = nvpes;
+        for (t = 1; t < nvpes; t++) {
+                /* Use a 1:1 mapping of TC index to VPE index */
+                settc(t);
+                /* Bind 1 TC to this VPE */
+                tcbind = read_tc_c0_tcbind();
+                tcbind &= ~TCBIND_CURVPE;
+                tcbind |= t << TCBIND_CURVPE_SHIFT;
+                write_tc_c0_tcbind(tcbind);
+                /* Set exclusive TC, non-active, master */
+                vpeconf0 = read_vpe_c0_vpeconf0();
+                vpeconf0 &= ~(VPECONF0_XTC | VPECONF0_VPA);
+                vpeconf0 |= t << VPECONF0_XTC_SHIFT;
+                vpeconf0 |= VPECONF0_MVP;
+                write_vpe_c0_vpeconf0(vpeconf0);
+                /* Declare TC non-active, non-allocatable & interrupt exempt */
+                tcstatus = read_tc_c0_tcstatus();
+                tcstatus &= ~(TCSTATUS_A | TCSTATUS_DA);
+                tcstatus |= TCSTATUS_IXMT;
+                write_tc_c0_tcstatus(tcstatus);
+                /* Halt the TC */
+                write_tc_c0_tchalt(TCHALT_H);
+                /* Allow only 1 TC to execute */
+                vpecontrol = read_vpe_c0_vpecontrol();
+                vpecontrol &= ~VPECONTROL_TE;
+                write_vpe_c0_vpecontrol(vpecontrol);
+                /* Copy (most of) Status from VPE 0 */
+                status = read_c0_status();
+                status &= ~(ST0_IM | ST0_IE | ST0_KSU);
+                status |= ST0_CU0;
+                write_vpe_c0_status(status);
+                /* Copy Config from VPE 0 */
+                write_vpe_c0_config(read_c0_config());
+                write_vpe_c0_config7(read_c0_config7());
+                /* Ensure no software interrupts are pending */
+                write_vpe_c0_cause(0);
+                /* Sync Count */
+                write_vpe_c0_count(read_c0_count());
+        }
+        /* Leave VPE configuration state */
+        clear_c0_mvpcontrol(MVPCONTROL_VPC);
+}
+static void __init cps_smp_setup(void)
+{
+        unsigned int ncores, nvpes, core_vpes;
+        int c, v;
+        u32 core_cfg, *entry_code;
+        /* Detect & record VPE topology */
+        ncores = mips_cm_numcores();
+        pr_info("VPE topology ");
+        for (c = nvpes = 0; c < ncores; c++) {
+                if (cpu_has_mipsmt && config_enabled(CONFIG_MIPS_MT_SMP)) {
+                        write_gcr_cl_other(c << CM_GCR_Cx_OTHER_CORENUM_SHF);
+                        core_cfg = read_gcr_co_config();
+                        core_vpes = ((core_cfg & CM_GCR_Cx_CONFIG_PVPE_MSK) >>
+                                     CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
+                } else {
+                        core_vpes = 1;
+                }
+                pr_cont("%c%u", c ? ',' : '{', core_vpes);
+                for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
+                        cpu_data[nvpes + v].core = c;
+#ifdef CONFIG_MIPS_MT_SMP
+                        cpu_data[nvpes + v].vpe_id = v;
+#endif
+                }
+                nvpes += core_vpes;
+        }
+        pr_cont("} total %u\n", nvpes);
+        /* Indicate present CPUs (CPU being synonymous with VPE) */
+        for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
+                set_cpu_possible(v, true);
+                set_cpu_present(v, true);
+                __cpu_number_map[v] = v;
+                __cpu_logical_map[v] = v;
+        }
+        /* Core 0 is powered up (we're running on it) */
+        bitmap_set(core_power, 0, 1);
+        /* Disable MT - we only want to run 1 TC per VPE */
+        if (cpu_has_mipsmt)
+                dmt();
+        /* Initialise core 0 */
+        init_core();
+        /* Patch the start of mips_cps_core_entry to provide the CM base */
+        entry_code = (u32 *)&mips_cps_core_entry;
+        UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
+        /* Make core 0 coherent with everything */
+        write_gcr_cl_coherence(0xff);
+}
+static void __init cps_prepare_cpus(unsigned int max_cpus)
+{
+        mips_mt_set_cpuoptions();
+}
+static void boot_core(struct boot_config *cfg)
+{
+        u32 access;
+        /* Select the appropriate core */
+        write_gcr_cl_other(cfg->core << CM_GCR_Cx_OTHER_CORENUM_SHF);
+        /* Set its reset vector */
+        write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
+        /* Ensure its coherency is disabled */
+        write_gcr_co_coherence(0);
+        /* Ensure the core can access the GCRs */
+        access = read_gcr_access();
+        access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + cfg->core);
+        write_gcr_access(access);
+        /* Copy cfg */
+        mips_cps_bootcfg = *cfg;
+        if (mips_cpc_present()) {
+                /* Select the appropriate core */
+                write_cpc_cl_other(cfg->core << CPC_Cx_OTHER_CORENUM_SHF);
+                /* Reset the core */
+                write_cpc_co_cmd(CPC_Cx_CMD_RESET);
+        } else {
+                /* Take the core out of reset */
+                write_gcr_co_reset_release(0);
+        }
+        /* The core is now powered up */
+        bitmap_set(core_power, cfg->core, 1);
+}
+static void boot_vpe(void *info)
+{
+        struct boot_config *cfg = info;
+        u32 tcstatus, vpeconf0;
+        /* Enter VPE configuration state */
+        dvpe();
+        set_c0_mvpcontrol(MVPCONTROL_VPC);
+        settc(cfg->vpe);
+        /* Set the TC restart PC */
+        write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
+        /* Activate the TC, allow interrupts */
+        tcstatus = read_tc_c0_tcstatus();
+        tcstatus &= ~TCSTATUS_IXMT;
+        tcstatus |= TCSTATUS_A;
+        write_tc_c0_tcstatus(tcstatus);
+        /* Clear the TC halt bit */
+        write_tc_c0_tchalt(0);
+        /* Activate the VPE */
+        vpeconf0 = read_vpe_c0_vpeconf0();
+        vpeconf0 |= VPECONF0_VPA;
+        write_vpe_c0_vpeconf0(vpeconf0);
+        /* Set the stack & global pointer registers */
+        write_tc_gpr_sp(cfg->sp);
+        write_tc_gpr_gp(cfg->gp);
+        /* Leave VPE configuration state */
+        clear_c0_mvpcontrol(MVPCONTROL_VPC);
+        /* Enable other VPEs to execute */
+        evpe(EVPE_ENABLE);
+}
+static void cps_boot_secondary(int cpu, struct task_struct *idle)
+{
+        struct boot_config cfg;
+        unsigned int remote;
+        int err;
+        cfg.core = cpu_data[cpu].core;
+        cfg.vpe = cpu_vpe_id(&cpu_data[cpu]);
+        cfg.pc = (unsigned long)&smp_bootstrap;
+        cfg.sp = __KSTK_TOS(idle);
+        cfg.gp = (unsigned long)task_thread_info(idle);
+        if (!test_bit(cfg.core, core_power)) {
+                /* Boot a VPE on a powered down core */
+                boot_core(&cfg);
+                return;
+        }
+        if (cfg.core != current_cpu_data.core) {
+                /* Boot a VPE on another powered up core */
+                for (remote = 0; remote < NR_CPUS; remote++) {
+                        if (cpu_data[remote].core != cfg.core)
+                                continue;
+                        if (cpu_online(remote))
+                                break;
+                }
+                BUG_ON(remote >= NR_CPUS);
+                err = smp_call_function_single(remote, boot_vpe, &cfg, 1);
+                if (err)
+                        panic("Failed to call remote CPU\n");
+                return;
+        }
+        BUG_ON(!cpu_has_mipsmt);
+        /* Boot a VPE on this core */
+        boot_vpe(&cfg);
+}
+static void cps_init_secondary(void)
+{
+        /* Disable MT - we only want to run 1 TC per VPE */
+        if (cpu_has_mipsmt)
+                dmt();
+        /* TODO: revisit this assumption once hotplug is implemented */
+        if (cpu_vpe_id(&current_cpu_data) == 0)
+                init_core();
+        change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
+                                 STATUSF_IP6 | STATUSF_IP7);
+}
+static void cps_smp_finish(void)
+{
+        write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
+#ifdef CONFIG_MIPS_MT_FPAFF
+        /* If we have an FPU, enroll ourselves in the FPU-full mask */
+        if (cpu_has_fpu)
+                cpu_set(smp_processor_id(), mt_fpu_cpumask);
+#endif /* CONFIG_MIPS_MT_FPAFF */
+        local_irq_enable();
+}
+static void cps_cpus_done(void)
+{
+}
+static struct plat_smp_ops cps_smp_ops = {
+        .smp_setup              = cps_smp_setup,
+        .prepare_cpus           = cps_prepare_cpus,
+        .boot_secondary         = cps_boot_secondary,
+        .init_secondary         = cps_init_secondary,
+        .smp_finish             = cps_smp_finish,
+        .send_ipi_single        = gic_send_ipi_single,
+        .send_ipi_mask          = gic_send_ipi_mask,
+        .cpus_done              = cps_cpus_done,
+};
+int register_cps_smp_ops(void)
+{
+        if (!mips_cm_present()) {
+                pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
+                return -ENODEV;
+        }
+        /* check we have a GIC - we need one for IPIs */
+        if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
+                pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
+                return -ENODEV;
+        }
+        register_smp_ops(&cps_smp_ops);
+        return 0;
+}
diff --git a/arch/mips/kernel/smp-gic.c b/arch/mips/kernel/smp-gic.c
new file mode 100644
index 000000000000..3bb1f92ab525
--- /dev/null
+++ b/arch/mips/kernel/smp-gic.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Based on smp-cmp.c:
+ *  Copyright (C) 2007 MIPS Technologies, Inc.
+ *  Author: Chris Dearman (chris@mips.com)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/printk.h>
+#include <asm/gic.h>
+#include <asm/smp-ops.h>
+void gic_send_ipi_single(int cpu, unsigned int action)
+{
+        unsigned long flags;
+        unsigned int intr;
+        pr_debug("CPU%d: %s cpu %d action %u status %08x\n",
+                 smp_processor_id(), __func__, cpu, action, read_c0_status());
+        local_irq_save(flags);
+        switch (action) {
+        case SMP_CALL_FUNCTION:
+                intr = plat_ipi_call_int_xlate(cpu);
+                break;
+        case SMP_RESCHEDULE_YOURSELF:
+                intr = plat_ipi_resched_int_xlate(cpu);
+                break;
+        default:
+                BUG();
+        }
+        gic_send_ipi(intr);
+        local_irq_restore(flags);
+}
+void gic_send_ipi_mask(const struct cpumask *mask, unsigned int action)
+{
+        unsigned int i;
+        for_each_cpu(i, mask)
+                gic_send_ipi_single(i, action);
+}
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 0fb8cefc9114..f8e13149604d 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -113,27 +113,6 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
        write_tc_c0_tchalt(TCHALT_H);
 }
-#ifdef CONFIG_IRQ_GIC
-static void mp_send_ipi_single(int cpu, unsigned int action)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        switch (action) {
-        case SMP_CALL_FUNCTION:
-                gic_send_ipi(plat_ipi_call_int_xlate(cpu));
-                break;
-        case SMP_RESCHEDULE_YOURSELF:
-                gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
-                break;
-        }
-        local_irq_restore(flags);
-}
-#endif
 static void vsmp_send_ipi_single(int cpu, unsigned int action)
 {
        int i;
@@ -142,7 +121,7 @@ static void vsmp_send_ipi_single(int cpu, unsigned int action)
 #ifdef CONFIG_IRQ_GIC
        if (gic_present) {
-                mp_send_ipi_single(cpu, action);
+                gic_send_ipi_single(cpu, action);
                return;
        }
 #endif
@@ -313,3 +292,25 @@ struct plat_smp_ops vsmp_smp_ops = {
        .smp_setup              = vsmp_smp_setup,
        .prepare_cpus           = vsmp_prepare_cpus,
 };
+static int proc_cpuinfo_chain_call(struct notifier_block *nfb,
+        unsigned long action_unused, void *data)
+{
+        struct proc_cpuinfo_notifier_args *pcn = data;
+        struct seq_file *m = pcn->m;
+        unsigned long n = pcn->n;
+        if (!cpu_has_mipsmt)
+                return NOTIFY_OK;
+        seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
+        return NOTIFY_OK;
+}
+static int __init proc_cpuinfo_notifier_init(void)
+{
+        return proc_cpuinfo_notifier(proc_cpuinfo_chain_call, 0);
+}
+subsys_initcall(proc_cpuinfo_notifier_init);
diff --git a/arch/mips/kernel/smtc-proc.c b/arch/mips/kernel/smtc-proc.c
index c10aa84c9fa9..38635a996cbf 100644
--- a/arch/mips/kernel/smtc-proc.c
+++ b/arch/mips/kernel/smtc-proc.c
@@ -77,3 +77,26 @@ void init_smtc_stats(void)
        proc_create("smtc", 0444, NULL, &smtc_proc_fops);
 }
+static int proc_cpuinfo_chain_call(struct notifier_block *nfb,
+        unsigned long action_unused, void *data)
+{
+        struct proc_cpuinfo_notifier_args *pcn = data;
+        struct seq_file *m = pcn->m;
+        unsigned long n = pcn->n;
+        if (!cpu_has_mipsmt)
+                return NOTIFY_OK;
+        seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
+        seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id);
+        return NOTIFY_OK;
+}
+static int __init proc_cpuinfo_notifier_init(void)
+{
+        return proc_cpuinfo_notifier(proc_cpuinfo_chain_call, 0);
+}
+subsys_initcall(proc_cpuinfo_notifier_init);
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index b242e2c10ea0..67f2495def1c 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -197,16 +197,17 @@ static void probe_spram(char *type,
 }
 void spram_config(void)
 {
-        struct cpuinfo_mips *c = &current_cpu_data;
        unsigned int config0;
-        switch (c->cputype) {
+        switch (current_cpu_type()) {
        case CPU_24K:
        case CPU_34K:
        case CPU_74K:
        case CPU_1004K:
+        case CPU_1074K:
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
+        case CPU_P5600:
                config0 = read_c0_config();
                /* FIXME: addresses are Malta specific */
                if (config0 & (1<<24)) {
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index b79d13f95bf0..4a4f9dda5658 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -110,7 +110,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                __asm__ __volatile__ (
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "       li      %[err], 0                               \n"
                "1:     ll      %[old], (%[addr])                       \n"
                "       move    %[tmp], %[new]                          \n"
@@ -135,7 +135,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
                : "memory");
        } else if (cpu_has_llsc) {
                __asm__ __volatile__ (
-                "       .set    mips3                                   \n"
+                "       .set    arch=r4000                              \n"
                "       li      %[err], 0                               \n"
                "1:     ll      %[old], (%[addr])                       \n"
                "       move    %[tmp], %[new]                          \n"
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e0b499694d18..074e857ced28 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -10,6 +10,7 @@
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2014, Imagination Technologies Ltd.
 */
 #include <linux/bug.h>
 #include <linux/compiler.h>
@@ -47,6 +48,7 @@
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/module.h>
+#include <asm/msa.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 #include <asm/sections.h>
@@ -77,8 +79,10 @@ extern asmlinkage void handle_ri_rdhwr(void);
 extern asmlinkage void handle_cpu(void);
 extern asmlinkage void handle_ov(void);
 extern asmlinkage void handle_tr(void);
+extern asmlinkage void handle_msa_fpe(void);
 extern asmlinkage void handle_fpe(void);
 extern asmlinkage void handle_ftlb(void);
+extern asmlinkage void handle_msa(void);
 extern asmlinkage void handle_mdmx(void);
 extern asmlinkage void handle_watch(void);
 extern asmlinkage void handle_mt(void);
@@ -861,6 +865,11 @@ asmlinkage void do_bp(struct pt_regs *regs)
        enum ctx_state prev_state;
        unsigned long epc;
        u16 instr[2];
+        mm_segment_t seg;
+        seg = get_fs();
+        if (!user_mode(regs))
+                set_fs(KERNEL_DS);
        prev_state = exception_enter();
        if (get_isa16_mode(regs->cp0_epc)) {
@@ -870,17 +879,19 @@ asmlinkage void do_bp(struct pt_regs *regs)
                        if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) ||
                            (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))))
                                goto out_sigsegv;
-                    opcode = (instr[0] << 16) | instr[1];
+                        opcode = (instr[0] << 16) | instr[1];
                } else {
-                    /* MIPS16e mode */
+                        /* MIPS16e mode */
-                    if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)))
+                        if (__get_user(instr[0],
+                                       (u16 __user *)msk_isa16_mode(epc)))
                                goto out_sigsegv;
-                    bcode = (instr[0] >> 6) & 0x3f;
+                        bcode = (instr[0] >> 6) & 0x3f;
-                    do_trap_or_bp(regs, bcode, "Break");
+                        do_trap_or_bp(regs, bcode, "Break");
-                    goto out;
+                        goto out;
                }
        } else {
-                if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
+                if (__get_user(opcode,
+                               (unsigned int __user *) exception_epc(regs)))
                        goto out_sigsegv;
        }
@@ -918,6 +929,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
        do_trap_or_bp(regs, bcode, "Break");
 out:
+        set_fs(seg);
        exception_exit(prev_state);
        return;
@@ -931,8 +943,13 @@ asmlinkage void do_tr(struct pt_regs *regs)
        u32 opcode, tcode = 0;
        enum ctx_state prev_state;
        u16 instr[2];
+        mm_segment_t seg;
        unsigned long epc = msk_isa16_mode(exception_epc(regs));
+        seg = get_fs();
+        if (!user_mode(regs))
+                set_fs(get_ds());
        prev_state = exception_enter();
        if (get_isa16_mode(regs->cp0_epc)) {
                if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
@@ -953,6 +970,7 @@ asmlinkage void do_tr(struct pt_regs *regs)
        do_trap_or_bp(regs, tcode, "Trap");
 out:
+        set_fs(seg);
        exception_exit(prev_state);
        return;
@@ -1074,6 +1092,76 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
        return NOTIFY_OK;
 }
+static int enable_restore_fp_context(int msa)
+{
+        int err, was_fpu_owner;
+        if (!used_math()) {
+                /* First time FP context user. */
+                err = init_fpu();
+                if (msa && !err)
+                        enable_msa();
+                if (!err)
+                        set_used_math();
+                return err;
+        }
+        /*
+         * This task has formerly used the FP context.
+         *
+         * If this thread has no live MSA vector context then we can simply
+         * restore the scalar FP context. If it has live MSA vector context
+         * (that is, it has or may have used MSA since last performing a
+         * function call) then we'll need to restore the vector context. This
+         * applies even if we're currently only executing a scalar FP
+         * instruction. This is because if we were to later execute an MSA
+         * instruction then we'd either have to:
+         *
+         *  - Restore the vector context & clobber any registers modified by
+         *    scalar FP instructions between now & then.
+         *
+         * or
+         *
+         *  - Not restore the vector context & lose the most significant bits
+         *    of all vector registers.
+         *
+         * Neither of those options is acceptable. We cannot restore the least
+         * significant bits of the registers now & only restore the most
+         * significant bits later because the most significant bits of any
+         * vector registers whose aliased FP register is modified now will have
+         * been zeroed. We'd have no way to know that when restoring the vector
+         * context & thus may load an outdated value for the most significant
+         * bits of a vector register.
+         */
+        if (!msa && !thread_msa_context_live())
+                return own_fpu(1);
+        /*
+         * This task is using or has previously used MSA. Thus we require
+         * that Status.FR == 1.
+         */
+        was_fpu_owner = is_fpu_owner();
+        err = own_fpu(0);
+        if (err)
+                return err;
+        enable_msa();
+        write_msa_csr(current->thread.fpu.msacsr);
+        set_thread_flag(TIF_USEDMSA);
+        /*
+         * If this is the first time that the task is using MSA and it has
+         * previously used scalar FP in this time slice then we already nave
+         * FP context which we shouldn't clobber.
+         */
+        if (!test_and_set_thread_flag(TIF_MSA_CTX_LIVE) && was_fpu_owner)
+                return 0;
+        /* We need to restore the vector context. */
+        restore_msa(current);
+        return 0;
+}
 asmlinkage void do_cpu(struct pt_regs *regs)
 {
        enum ctx_state prev_state;
@@ -1153,12 +1241,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
                /* Fall through.  */
        case 1:
-                if (used_math())        /* Using the FPU again.  */
+                err = enable_restore_fp_context(0);
-                        err = own_fpu(1);
-                else {                  /* First time FPU user.  */
-                        err = init_fpu();
-                        set_used_math();
-                }
                if (!raw_cpu_has_fpu || err) {
                        int sig;
@@ -1183,6 +1266,37 @@ out:
        exception_exit(prev_state);
 }
+asmlinkage void do_msa_fpe(struct pt_regs *regs)
+{
+        enum ctx_state prev_state;
+        prev_state = exception_enter();
+        die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
+        force_sig(SIGFPE, current);
+        exception_exit(prev_state);
+}
+asmlinkage void do_msa(struct pt_regs *regs)
+{
+        enum ctx_state prev_state;
+        int err;
+        prev_state = exception_enter();
+        if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
+                force_sig(SIGILL, current);
+                goto out;
+        }
+        die_if_kernel("do_msa invoked from kernel context!", regs);
+        err = enable_restore_fp_context(1);
+        if (err)
+                force_sig(SIGILL, current);
+out:
+        exception_exit(prev_state);
+}
 asmlinkage void do_mdmx(struct pt_regs *regs)
 {
        enum ctx_state prev_state;
@@ -1337,8 +1451,10 @@ static inline void parity_protection_init(void)
        case CPU_34K:
        case CPU_74K:
        case CPU_1004K:
+        case CPU_1074K:
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
+        case CPU_P5600:
                {
 #define ERRCTL_PE       0x80000000
 #define ERRCTL_L2P      0x00800000
@@ -2017,6 +2133,7 @@ void __init trap_init(void)
        set_except_vector(11, handle_cpu);
        set_except_vector(12, handle_ov);
        set_except_vector(13, handle_tr);
+        set_except_vector(14, handle_msa_fpe);
        if (current_cpu_type() == CPU_R6000 ||
            current_cpu_type() == CPU_R6000A) {
@@ -2040,6 +2157,7 @@ void __init trap_init(void)
                set_except_vector(15, handle_fpe);
        set_except_vector(16, handle_ftlb);
+        set_except_vector(21, handle_msa);
        set_except_vector(22, handle_mdmx);
        if (cpu_has_mcheck)
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index c369a5d35527..2b3517214d6d 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -7,6 +7,7 @@
 *
 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
 * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 *
 * This file contains exception handler for address error exception with the
 * special capability to execute faulting instructions in software.  The
@@ -110,8 +111,8 @@ extern void show_registers(struct pt_regs *regs);
 #ifdef __BIG_ENDIAN
 #define     LoadHW(addr, value, res)  \
                __asm__ __volatile__ (".set\tnoat\n"        \
-                        "1:\tlb\t%0, 0(%2)\n"               \
+                        "1:\t"user_lb("%0", "0(%2)")"\n"    \
-                        "2:\tlbu\t$1, 1(%2)\n\t"            \
+                        "2:\t"user_lbu("$1", "1(%2)")"\n\t" \
                        "sll\t%0, 0x8\n\t"                  \
                        "or\t%0, $1\n\t"                    \
                        "li\t%1, 0\n"                       \
@@ -130,8 +131,8 @@ extern void show_registers(struct pt_regs *regs);
 #define     LoadW(addr, value, res)   \
                __asm__ __volatile__ (                      \
-                        "1:\tlwl\t%0, (%2)\n"               \
+                        "1:\t"user_lwl("%0", "(%2)")"\n"    \
-                        "2:\tlwr\t%0, 3(%2)\n\t"            \
+                        "2:\t"user_lwr("%0", "3(%2)")"\n\t" \
                        "li\t%1, 0\n"                       \
                        "3:\n\t"                            \
                        ".insn\n\t"                         \
@@ -149,8 +150,8 @@ extern void show_registers(struct pt_regs *regs);
 #define     LoadHWU(addr, value, res) \
                __asm__ __volatile__ (                      \
                        ".set\tnoat\n"                      \
-                        "1:\tlbu\t%0, 0(%2)\n"              \
+                        "1:\t"user_lbu("%0", "0(%2)")"\n"   \
-                        "2:\tlbu\t$1, 1(%2)\n\t"            \
+                        "2:\t"user_lbu("$1", "1(%2)")"\n\t" \
                        "sll\t%0, 0x8\n\t"                  \
                        "or\t%0, $1\n\t"                    \
                        "li\t%1, 0\n"                       \
@@ -170,8 +171,8 @@ extern void show_registers(struct pt_regs *regs);
 #define     LoadWU(addr, value, res)  \
                __asm__ __volatile__ (                      \
-                        "1:\tlwl\t%0, (%2)\n"               \
+                        "1:\t"user_lwl("%0", "(%2)")"\n"    \
-                        "2:\tlwr\t%0, 3(%2)\n\t"            \
+                        "2:\t"user_lwr("%0", "3(%2)")"\n\t" \
                        "dsll\t%0, %0, 32\n\t"              \
                        "dsrl\t%0, %0, 32\n\t"              \
                        "li\t%1, 0\n"                       \
@@ -209,9 +210,9 @@ extern void show_registers(struct pt_regs *regs);
 #define     StoreHW(addr, value, res) \
                __asm__ __volatile__ (                      \
                        ".set\tnoat\n"                      \
-                        "1:\tsb\t%1, 1(%2)\n\t"             \
+                        "1:\t"user_sb("%1", "1(%2)")"\n"    \
                        "srl\t$1, %1, 0x8\n"                \
-                        "2:\tsb\t$1, 0(%2)\n\t"             \
+                        "2:\t"user_sb("$1", "0(%2)")"\n"    \
                        ".set\tat\n\t"                      \
                        "li\t%0, 0\n"                       \
                        "3:\n\t"                            \
@@ -229,8 +230,8 @@ extern void show_registers(struct pt_regs *regs);
 #define     StoreW(addr, value, res)  \
                __asm__ __volatile__ (                      \
-                        "1:\tswl\t%1,(%2)\n"                \
+                        "1:\t"user_swl("%1", "(%2)")"\n"    \
-                        "2:\tswr\t%1, 3(%2)\n\t"            \
+                        "2:\t"user_swr("%1", "3(%2)")"\n\t" \
                        "li\t%0, 0\n"                       \
                        "3:\n\t"                            \
                        ".insn\n\t"                         \
@@ -267,8 +268,8 @@ extern void show_registers(struct pt_regs *regs);
 #ifdef __LITTLE_ENDIAN
 #define     LoadHW(addr, value, res)  \
                __asm__ __volatile__ (".set\tnoat\n"        \
-                        "1:\tlb\t%0, 1(%2)\n"               \
+                        "1:\t"user_lb("%0", "1(%2)")"\n"    \
-                        "2:\tlbu\t$1, 0(%2)\n\t"            \
+                        "2:\t"user_lbu("$1", "0(%2)")"\n\t" \
                        "sll\t%0, 0x8\n\t"                  \
                        "or\t%0, $1\n\t"                    \
                        "li\t%1, 0\n"                       \
@@ -287,8 +288,8 @@ extern void show_registers(struct pt_regs *regs);
 #define     LoadW(addr, value, res)   \
                __asm__ __volatile__ (                      \
-                        "1:\tlwl\t%0, 3(%2)\n"              \
+                        "1:\t"user_lwl("%0", "3(%2)")"\n"   \
-                        "2:\tlwr\t%0, (%2)\n\t"             \
+                        "2:\t"user_lwr("%0", "(%2)")"\n\t"  \
                        "li\t%1, 0\n"                       \
                        "3:\n\t"                            \
                        ".insn\n\t"                         \
@@ -306,8 +307,8 @@ extern void show_registers(struct pt_regs *regs);
 #define     LoadHWU(addr, value, res) \
                __asm__ __volatile__ (                      \
                        ".set\tnoat\n"                      \
-                        "1:\tlbu\t%0, 1(%2)\n"              \
+                        "1:\t"user_lbu("%0", "1(%2)")"\n"   \
-                        "2:\tlbu\t$1, 0(%2)\n\t"            \
+                        "2:\t"user_lbu("$1", "0(%2)")"\n\t" \
                        "sll\t%0, 0x8\n\t"                  \
                        "or\t%0, $1\n\t"                    \
                        "li\t%1, 0\n"                       \
@@ -327,8 +328,8 @@ extern void show_registers(struct pt_regs *regs);
 #define     LoadWU(addr, value, res)  \
                __asm__ __volatile__ (                      \
-                        "1:\tlwl\t%0, 3(%2)\n"              \
+                        "1:\t"user_lwl("%0", "3(%2)")"\n"   \
-                        "2:\tlwr\t%0, (%2)\n\t"             \
+                        "2:\t"user_lwr("%0", "(%2)")"\n\t"  \
                        "dsll\t%0, %0, 32\n\t"              \
                        "dsrl\t%0, %0, 32\n\t"              \
                        "li\t%1, 0\n"                       \
@@ -366,9 +367,9 @@ extern void show_registers(struct pt_regs *regs);
 #define     StoreHW(addr, value, res) \
                __asm__ __volatile__ (                      \
                        ".set\tnoat\n"                      \
-                        "1:\tsb\t%1, 0(%2)\n\t"             \
+                        "1:\t"user_sb("%1", "0(%2)")"\n"    \
                        "srl\t$1,%1, 0x8\n"                 \
-                        "2:\tsb\t$1, 1(%2)\n\t"             \
+                        "2:\t"user_sb("$1", "1(%2)")"\n"    \
                        ".set\tat\n\t"                      \
                        "li\t%0, 0\n"                       \
                        "3:\n\t"                            \
@@ -386,8 +387,8 @@ extern void show_registers(struct pt_regs *regs);
 #define     StoreW(addr, value, res)  \
                __asm__ __volatile__ (                      \
-                        "1:\tswl\t%1, 3(%2)\n"              \
+                        "1:\t"user_swl("%1", "3(%2)")"\n"   \
-                        "2:\tswr\t%1, (%2)\n\t"             \
+                        "2:\t"user_swr("%1", "(%2)")"\n\t"  \
                        "li\t%0, 0\n"                       \
                        "3:\n\t"                            \
                        ".insn\n\t"                         \
@@ -430,7 +431,9 @@ static void emulate_load_store_insn(struct pt_regs *regs,
        unsigned long origpc;
        unsigned long orig31;
        void __user *fault_addr = NULL;
+#ifdef  CONFIG_EVA
+        mm_segment_t seg;
+#endif
        origpc = (unsigned long)pc;
        orig31 = regs->regs[31];
@@ -475,6 +478,88 @@ static void emulate_load_store_insn(struct pt_regs *regs,
                 * The remaining opcodes are the ones that are really of
                 * interest.
                 */
+#ifdef CONFIG_EVA
+        case spec3_op:
+                /*
+                 * we can land here only from kernel accessing user memory,
+                 * so we need to "switch" the address limit to user space, so
+                 * address check can work properly.
+                 */
+                seg = get_fs();
+                set_fs(USER_DS);
+                switch (insn.spec3_format.func) {
+                case lhe_op:
+                        if (!access_ok(VERIFY_READ, addr, 2)) {
+                                set_fs(seg);
+                                goto sigbus;
+                        }
+                        LoadHW(addr, value, res);
+                        if (res) {
+                                set_fs(seg);
+                                goto fault;
+                        }
+                        compute_return_epc(regs);
+                        regs->regs[insn.spec3_format.rt] = value;
+                        break;
+                case lwe_op:
+                        if (!access_ok(VERIFY_READ, addr, 4)) {
+                                set_fs(seg);
+                                goto sigbus;
+                        }
+                                LoadW(addr, value, res);
+                        if (res) {
+                                set_fs(seg);
+                                goto fault;
+                        }
+                        compute_return_epc(regs);
+                        regs->regs[insn.spec3_format.rt] = value;
+                        break;
+                case lhue_op:
+                        if (!access_ok(VERIFY_READ, addr, 2)) {
+                                set_fs(seg);
+                                goto sigbus;
+                        }
+                        LoadHWU(addr, value, res);
+                        if (res) {
+                                set_fs(seg);
+                                goto fault;
+                        }
+                        compute_return_epc(regs);
+                        regs->regs[insn.spec3_format.rt] = value;
+                        break;
+                case she_op:
+                        if (!access_ok(VERIFY_WRITE, addr, 2)) {
+                                set_fs(seg);
+                                goto sigbus;
+                        }
+                        compute_return_epc(regs);
+                        value = regs->regs[insn.spec3_format.rt];
+                        StoreHW(addr, value, res);
+                        if (res) {
+                                set_fs(seg);
+                                goto fault;
+                        }
+                        break;
+                case swe_op:
+                        if (!access_ok(VERIFY_WRITE, addr, 4)) {
+                                set_fs(seg);
+                                goto sigbus;
+                        }
+                        compute_return_epc(regs);
+                        value = regs->regs[insn.spec3_format.rt];
+                        StoreW(addr, value, res);
+                        if (res) {
+                                set_fs(seg);
+                                goto fault;
+                        }
+                        break;
+                default:
+                        set_fs(seg);
+                        goto sigill;
+                }
+                set_fs(seg);
+                break;
+#endif
        case lh_op:
                if (!access_ok(VERIFY_READ, addr, 2))
                        goto sigbus;
diff --git a/arch/mips/kvm/kvm_mips_emul.c b/arch/mips/kvm/kvm_mips_emul.c
index 4b6274b47f33..e3fec99941a7 100644
--- a/arch/mips/kvm/kvm_mips_emul.c
+++ b/arch/mips/kvm/kvm_mips_emul.c
@@ -436,13 +436,6 @@ kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc, uint32_t cause,
        sel = inst & 0x7;
        co_bit = (inst >> 25) & 1;
-        /* Verify that the register is valid */
-        if (rd > MIPS_CP0_DESAVE) {
-                printk("Invalid rd: %d\n", rd);
-                er = EMULATE_FAIL;
-                goto done;
-        }
        if (co_bit) {
                op = (inst) & 0xff;
@@ -1542,8 +1535,15 @@ kvm_mips_handle_ri(unsigned long cause, uint32_t *opc,
        }
        if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) {
+                int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
                int rd = (inst & RD) >> 11;
                int rt = (inst & RT) >> 16;
+                /* If usermode, check RDHWR rd is allowed by guest HWREna */
+                if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
+                        kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
+                                  rd, opc);
+                        goto emulate_ri;
+                }
                switch (rd) {
                case 0: /* CPU number */
                        arch->gprs[rt] = 0;
@@ -1567,31 +1567,27 @@ kvm_mips_handle_ri(unsigned long cause, uint32_t *opc,
                        }
                        break;
                case 29:
-#if 1
                        arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
-#else
-                        /* UserLocal not implemented */
-                        er = kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
-#endif
                        break;
                default:
-                        printk("RDHWR not supported\n");
+                        kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
-                        er = EMULATE_FAIL;
+                        goto emulate_ri;
-                        break;
                }
        } else {
-                printk("Emulate RI not supported @ %p: %#x\n", opc, inst);
+                kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);
-                er = EMULATE_FAIL;
+                goto emulate_ri;
        }
+        return EMULATE_DONE;
+emulate_ri:
        /*
-         * Rollback PC only if emulation was unsuccessful
+         * Rollback PC (if in branch delay slot then the PC already points to
+         * branch target), and pass the RI exception to the guest OS.
         */
-        if (er == EMULATE_FAIL) {
+        vcpu->arch.pc = curr_pc;
-                vcpu->arch.pc = curr_pc;
+        return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
-        }
-        return er;
 }
 enum emulation_result
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index 638c5db122c9..2bcd8391bc93 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -175,7 +175,7 @@ static void pvc_proc_cleanup(void)
        remove_proc_entry("scroll", pvc_display_dir);
        remove_proc_entry(DISPLAY_DIR_NAME, NULL);
-        del_timer(&timer);
+        del_timer_sync(&timer);
 }
 static int __init pvc_proc_init(void)
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index a6adffbb4e5f..2e4825e48388 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -8,6 +8,7 @@
 * Copyright (C) 1998, 1999 Ralf Baechle
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Copyright (C) 2007  Maciej W. Rozycki
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 */
 #include <linux/errno.h>
 #include <asm/asm.h>
@@ -296,7 +297,7 @@ LEAF(csum_partial)
 * checksum and copy routines based on memcpy.S
 *
 *      csum_partial_copy_nocheck(src, dst, len, sum)
- *      __csum_partial_copy_user(src, dst, len, sum, errp)
+ *      __csum_partial_copy_kernel(src, dst, len, sum, errp)
 *
 * See "Spec" in memcpy.S for details.  Unlike __copy_user, all
 * function in this file use the standard calling convention.
@@ -327,20 +328,58 @@ LEAF(csum_partial)
 * These handlers do not need to overwrite any data.
 */
-#define EXC(inst_reg,addr,handler)              \
+/* Instruction type */
-9:      inst_reg, addr;                         \
+#define LD_INSN 1
-        .section __ex_table,"a";                \
+#define ST_INSN 2
-        PTR     9b, handler;                    \
+#define LEGACY_MODE 1
-        .previous
+#define EVA_MODE    2
+#define USEROP   1
+#define KERNELOP 2
+/*
+ * Wrapper to add an entry in the exception table
+ * in case the insn causes a memory exception.
+ * Arguments:
+ * insn    : Load/store instruction
+ * type    : Instruction type
+ * reg     : Register
+ * addr    : Address
+ * handler : Exception handler
+ */
+#define EXC(insn, type, reg, addr, handler)     \
+        .if \mode == LEGACY_MODE;               \
+9:              insn reg, addr;                 \
+                .section __ex_table,"a";        \
+                PTR     9b, handler;            \
+                .previous;                      \
+        /* This is enabled in EVA mode */       \
+        .else;                                  \
+                /* If loading from user or storing to user */   \
+                .if ((\from == USEROP) && (type == LD_INSN)) || \
+                    ((\to == USEROP) && (type == ST_INSN));     \
+9:                      __BUILD_EVA_INSN(insn##e, reg, addr);   \
+                        .section __ex_table,"a";                \
+                        PTR     9b, handler;                    \
+                        .previous;                              \
+                .else;                                          \
+                        /* EVA without exception */             \
+                        insn reg, addr;                         \
+                .endif;                                         \
+        .endif
+#undef LOAD
 #ifdef USE_DOUBLE
-#define LOAD   ld
+#define LOADK   ld /* No exception */
-#define LOADL  ldl
+#define LOAD(reg, addr, handler)        EXC(ld, LD_INSN, reg, addr, handler)
-#define LOADR  ldr
+#define LOADBU(reg, addr, handler)      EXC(lbu, LD_INSN, reg, addr, handler)
-#define STOREL sdl
+#define LOADL(reg, addr, handler)       EXC(ldl, LD_INSN, reg, addr, handler)
-#define STORER sdr
+#define LOADR(reg, addr, handler)       EXC(ldr, LD_INSN, reg, addr, handler)
-#define STORE  sd
+#define STOREB(reg, addr, handler)      EXC(sb, ST_INSN, reg, addr, handler)
+#define STOREL(reg, addr, handler)      EXC(sdl, ST_INSN, reg, addr, handler)
+#define STORER(reg, addr, handler)      EXC(sdr, ST_INSN, reg, addr, handler)
+#define STORE(reg, addr, handler)       EXC(sd, ST_INSN, reg, addr, handler)
 #define ADD    daddu
 #define SUB    dsubu
 #define SRL    dsrl
@@ -352,12 +391,15 @@ LEAF(csum_partial)
 #else
-#define LOAD   lw
+#define LOADK   lw /* No exception */
-#define LOADL  lwl
+#define LOAD(reg, addr, handler)        EXC(lw, LD_INSN, reg, addr, handler)
-#define LOADR  lwr
+#define LOADBU(reg, addr, handler)      EXC(lbu, LD_INSN, reg, addr, handler)
-#define STOREL swl
+#define LOADL(reg, addr, handler)       EXC(lwl, LD_INSN, reg, addr, handler)
-#define STORER swr
+#define LOADR(reg, addr, handler)       EXC(lwr, LD_INSN, reg, addr, handler)
-#define STORE  sw
+#define STOREB(reg, addr, handler)      EXC(sb, ST_INSN, reg, addr, handler)
+#define STOREL(reg, addr, handler)      EXC(swl, ST_INSN, reg, addr, handler)
+#define STORER(reg, addr, handler)      EXC(swr, ST_INSN, reg, addr, handler)
+#define STORE(reg, addr, handler)       EXC(sw, ST_INSN, reg, addr, handler)
 #define ADD    addu
 #define SUB    subu
 #define SRL    srl
@@ -396,14 +438,20 @@ LEAF(csum_partial)
        .set    at=v1
 #endif
-LEAF(__csum_partial_copy_user)
+        .macro __BUILD_CSUM_PARTIAL_COPY_USER mode, from, to, __nocheck
        PTR_ADDU        AT, src, len    /* See (1) above. */
+        /* initialize __nocheck if this the first time we execute this
+         * macro
+         */
 #ifdef CONFIG_64BIT
        move    errptr, a4
 #else
        lw      errptr, 16(sp)
 #endif
-FEXPORT(csum_partial_copy_nocheck)
+        .if \__nocheck == 1
+        FEXPORT(csum_partial_copy_nocheck)
+        .endif
        move    sum, zero
        move    odd, zero
        /*
@@ -419,48 +467,48 @@ FEXPORT(csum_partial_copy_nocheck)
         */
        sltu    t2, len, NBYTES
        and     t1, dst, ADDRMASK
-        bnez    t2, .Lcopy_bytes_checklen
+        bnez    t2, .Lcopy_bytes_checklen\@
         and    t0, src, ADDRMASK
        andi    odd, dst, 0x1                   /* odd buffer? */
-        bnez    t1, .Ldst_unaligned
+        bnez    t1, .Ldst_unaligned\@
         nop
-        bnez    t0, .Lsrc_unaligned_dst_aligned
+        bnez    t0, .Lsrc_unaligned_dst_aligned\@
        /*
         * use delay slot for fall-through
         * src and dst are aligned; need to compute rem
         */
-.Lboth_aligned:
+.Lboth_aligned\@:
         SRL    t0, len, LOG_NBYTES+3    # +3 for 8 units/iter
-        beqz    t0, .Lcleanup_both_aligned # len < 8*NBYTES
+        beqz    t0, .Lcleanup_both_aligned\@ # len < 8*NBYTES
         nop
        SUB     len, 8*NBYTES           # subtract here for bgez loop
        .align  4
 1:
-EXC(    LOAD    t0, UNIT(0)(src),       .Ll_exc)
+        LOAD(t0, UNIT(0)(src), .Ll_exc\@)
-EXC(    LOAD    t1, UNIT(1)(src),       .Ll_exc_copy)
+        LOAD(t1, UNIT(1)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t2, UNIT(2)(src),       .Ll_exc_copy)
+        LOAD(t2, UNIT(2)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t3, UNIT(3)(src),       .Ll_exc_copy)
+        LOAD(t3, UNIT(3)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t4, UNIT(4)(src),       .Ll_exc_copy)
+        LOAD(t4, UNIT(4)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t5, UNIT(5)(src),       .Ll_exc_copy)
+        LOAD(t5, UNIT(5)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t6, UNIT(6)(src),       .Ll_exc_copy)
+        LOAD(t6, UNIT(6)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t7, UNIT(7)(src),       .Ll_exc_copy)
+        LOAD(t7, UNIT(7)(src), .Ll_exc_copy\@)
        SUB     len, len, 8*NBYTES
        ADD     src, src, 8*NBYTES
-EXC(    STORE   t0, UNIT(0)(dst),       .Ls_exc)
+        STORE(t0, UNIT(0)(dst), .Ls_exc\@)
        ADDC(sum, t0)
-EXC(    STORE   t1, UNIT(1)(dst),       .Ls_exc)
+        STORE(t1, UNIT(1)(dst), .Ls_exc\@)
        ADDC(sum, t1)
-EXC(    STORE   t2, UNIT(2)(dst),       .Ls_exc)
+        STORE(t2, UNIT(2)(dst), .Ls_exc\@)
        ADDC(sum, t2)
-EXC(    STORE   t3, UNIT(3)(dst),       .Ls_exc)
+        STORE(t3, UNIT(3)(dst), .Ls_exc\@)
        ADDC(sum, t3)
-EXC(    STORE   t4, UNIT(4)(dst),       .Ls_exc)
+        STORE(t4, UNIT(4)(dst), .Ls_exc\@)
        ADDC(sum, t4)
-EXC(    STORE   t5, UNIT(5)(dst),       .Ls_exc)
+        STORE(t5, UNIT(5)(dst), .Ls_exc\@)
        ADDC(sum, t5)
-EXC(    STORE   t6, UNIT(6)(dst),       .Ls_exc)
+        STORE(t6, UNIT(6)(dst), .Ls_exc\@)
        ADDC(sum, t6)
-EXC(    STORE   t7, UNIT(7)(dst),       .Ls_exc)
+        STORE(t7, UNIT(7)(dst), .Ls_exc\@)
        ADDC(sum, t7)
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, 8*NBYTES
@@ -471,44 +519,44 @@ EXC(	STORE	t7, UNIT(7)(dst),	.Ls_exc)
        /*
         * len == the number of bytes left to copy < 8*NBYTES
         */
-.Lcleanup_both_aligned:
+.Lcleanup_both_aligned\@:
 #define rem t7
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
         sltu   t0, len, 4*NBYTES
-        bnez    t0, .Lless_than_4units
+        bnez    t0, .Lless_than_4units\@
         and    rem, len, (NBYTES-1)    # rem = len % NBYTES
        /*
         * len >= 4*NBYTES
         */
-EXC(    LOAD    t0, UNIT(0)(src),       .Ll_exc)
+        LOAD(t0, UNIT(0)(src), .Ll_exc\@)
-EXC(    LOAD    t1, UNIT(1)(src),       .Ll_exc_copy)
+        LOAD(t1, UNIT(1)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t2, UNIT(2)(src),       .Ll_exc_copy)
+        LOAD(t2, UNIT(2)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t3, UNIT(3)(src),       .Ll_exc_copy)
+        LOAD(t3, UNIT(3)(src), .Ll_exc_copy\@)
        SUB     len, len, 4*NBYTES
        ADD     src, src, 4*NBYTES
-EXC(    STORE   t0, UNIT(0)(dst),       .Ls_exc)
+        STORE(t0, UNIT(0)(dst), .Ls_exc\@)
        ADDC(sum, t0)
-EXC(    STORE   t1, UNIT(1)(dst),       .Ls_exc)
+        STORE(t1, UNIT(1)(dst), .Ls_exc\@)
        ADDC(sum, t1)
-EXC(    STORE   t2, UNIT(2)(dst),       .Ls_exc)
+        STORE(t2, UNIT(2)(dst), .Ls_exc\@)
        ADDC(sum, t2)
-EXC(    STORE   t3, UNIT(3)(dst),       .Ls_exc)
+        STORE(t3, UNIT(3)(dst), .Ls_exc\@)
        ADDC(sum, t3)
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, 4*NBYTES
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
        .set    noreorder
-.Lless_than_4units:
+.Lless_than_4units\@:
        /*
         * rem = len % NBYTES
         */
-        beq     rem, len, .Lcopy_bytes
+        beq     rem, len, .Lcopy_bytes\@
         nop
 1:
-EXC(    LOAD    t0, 0(src),             .Ll_exc)
+        LOAD(t0, 0(src), .Ll_exc\@)
        ADD     src, src, NBYTES
        SUB     len, len, NBYTES
-EXC(    STORE   t0, 0(dst),             .Ls_exc)
+        STORE(t0, 0(dst), .Ls_exc\@)
        ADDC(sum, t0)
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, NBYTES
@@ -527,20 +575,20 @@ EXC(	STORE	t0, 0(dst),		.Ls_exc)
         * more instruction-level parallelism.
         */
 #define bits t2
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
         ADD    t1, dst, len    # t1 is just past last byte of dst
        li      bits, 8*NBYTES
        SLL     rem, len, 3     # rem = number of bits to keep
-EXC(    LOAD    t0, 0(src),             .Ll_exc)
+        LOAD(t0, 0(src), .Ll_exc\@)
        SUB     bits, bits, rem # bits = number of bits to discard
        SHIFT_DISCARD t0, t0, bits
-EXC(    STREST  t0, -1(t1),             .Ls_exc)
+        STREST(t0, -1(t1), .Ls_exc\@)
        SHIFT_DISCARD_REVERT t0, t0, bits
        .set reorder
        ADDC(sum, t0)
-        b       .Ldone
+        b       .Ldone\@
        .set noreorder
-.Ldst_unaligned:
+.Ldst_unaligned\@:
        /*
         * dst is unaligned
         * t0 = src & ADDRMASK
@@ -551,25 +599,25 @@ EXC(	STREST	t0, -1(t1),		.Ls_exc)
         * Set match = (src and dst have same alignment)
         */
 #define match rem
-EXC(    LDFIRST t3, FIRST(0)(src),      .Ll_exc)
+        LDFIRST(t3, FIRST(0)(src), .Ll_exc\@)
        ADD     t2, zero, NBYTES
-EXC(    LDREST  t3, REST(0)(src),       .Ll_exc_copy)
+        LDREST(t3, REST(0)(src), .Ll_exc_copy\@)
        SUB     t2, t2, t1      # t2 = number of bytes copied
        xor     match, t0, t1
-EXC(    STFIRST t3, FIRST(0)(dst),      .Ls_exc)
+        STFIRST(t3, FIRST(0)(dst), .Ls_exc\@)
        SLL     t4, t1, 3               # t4 = number of bits to discard
        SHIFT_DISCARD t3, t3, t4
        /* no SHIFT_DISCARD_REVERT to handle odd buffer properly */
        ADDC(sum, t3)
-        beq     len, t2, .Ldone
+        beq     len, t2, .Ldone\@
         SUB    len, len, t2
        ADD     dst, dst, t2
-        beqz    match, .Lboth_aligned
+        beqz    match, .Lboth_aligned\@
         ADD    src, src, t2
-.Lsrc_unaligned_dst_aligned:
+.Lsrc_unaligned_dst_aligned\@:
        SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
-        beqz    t0, .Lcleanup_src_unaligned
+        beqz    t0, .Lcleanup_src_unaligned\@
         and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
 1:
 /*
@@ -578,53 +626,53 @@ EXC(	STFIRST t3, FIRST(0)(dst),	.Ls_exc)
 * It's OK to load FIRST(N+1) before REST(N) because the two addresses
 * are to the same unit (unless src is aligned, but it's not).
 */
-EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
+        LDFIRST(t0, FIRST(0)(src), .Ll_exc\@)
-EXC(    LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
+        LDFIRST(t1, FIRST(1)(src), .Ll_exc_copy\@)
        SUB     len, len, 4*NBYTES
-EXC(    LDREST  t0, REST(0)(src),       .Ll_exc_copy)
+        LDREST(t0, REST(0)(src), .Ll_exc_copy\@)
-EXC(    LDREST  t1, REST(1)(src),       .Ll_exc_copy)
+        LDREST(t1, REST(1)(src), .Ll_exc_copy\@)
-EXC(    LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
+        LDFIRST(t2, FIRST(2)(src), .Ll_exc_copy\@)
-EXC(    LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)
+        LDFIRST(t3, FIRST(3)(src), .Ll_exc_copy\@)
-EXC(    LDREST  t2, REST(2)(src),       .Ll_exc_copy)
+        LDREST(t2, REST(2)(src), .Ll_exc_copy\@)
-EXC(    LDREST  t3, REST(3)(src),       .Ll_exc_copy)
+        LDREST(t3, REST(3)(src), .Ll_exc_copy\@)
        ADD     src, src, 4*NBYTES
 #ifdef CONFIG_CPU_SB1
        nop                             # improves slotting
 #endif
-EXC(    STORE   t0, UNIT(0)(dst),       .Ls_exc)
+        STORE(t0, UNIT(0)(dst), .Ls_exc\@)
        ADDC(sum, t0)
-EXC(    STORE   t1, UNIT(1)(dst),       .Ls_exc)
+        STORE(t1, UNIT(1)(dst), .Ls_exc\@)
        ADDC(sum, t1)
-EXC(    STORE   t2, UNIT(2)(dst),       .Ls_exc)
+        STORE(t2, UNIT(2)(dst), .Ls_exc\@)
        ADDC(sum, t2)
-EXC(    STORE   t3, UNIT(3)(dst),       .Ls_exc)
+        STORE(t3, UNIT(3)(dst), .Ls_exc\@)
        ADDC(sum, t3)
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, 4*NBYTES
        bne     len, rem, 1b
        .set    noreorder
-.Lcleanup_src_unaligned:
+.Lcleanup_src_unaligned\@:
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
         and    rem, len, NBYTES-1  # rem = len % NBYTES
-        beq     rem, len, .Lcopy_bytes
+        beq     rem, len, .Lcopy_bytes\@
         nop
 1:
-EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
+        LDFIRST(t0, FIRST(0)(src), .Ll_exc\@)
-EXC(    LDREST  t0, REST(0)(src),       .Ll_exc_copy)
+        LDREST(t0, REST(0)(src), .Ll_exc_copy\@)
        ADD     src, src, NBYTES
        SUB     len, len, NBYTES
-EXC(    STORE   t0, 0(dst),             .Ls_exc)
+        STORE(t0, 0(dst), .Ls_exc\@)
        ADDC(sum, t0)
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, NBYTES
        bne     len, rem, 1b
        .set    noreorder
-.Lcopy_bytes_checklen:
+.Lcopy_bytes_checklen\@:
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
         nop
-.Lcopy_bytes:
+.Lcopy_bytes\@:
        /* 0 < len < NBYTES  */
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define SHIFT_START 0
@@ -637,12 +685,12 @@ EXC(	STORE	t0, 0(dst),		.Ls_exc)
        li      t3, SHIFT_START # shift
 /* use .Ll_exc_copy here to return correct sum on fault */
 #define COPY_BYTE(N)                    \
-EXC(    lbu     t0, N(src), .Ll_exc_copy);      \
+        LOADBU(t0, N(src), .Ll_exc_copy\@);     \
        SUB     len, len, 1;            \
-EXC(    sb      t0, N(dst), .Ls_exc);   \
+        STOREB(t0, N(dst), .Ls_exc\@);  \
        SLLV    t0, t0, t3;             \
        addu    t3, SHIFT_INC;          \
-        beqz    len, .Lcopy_bytes_done; \
+        beqz    len, .Lcopy_bytes_done\@; \
         or     t2, t0
        COPY_BYTE(0)
@@ -653,14 +701,14 @@ EXC(	sb	t0, N(dst), .Ls_exc);	\
        COPY_BYTE(4)
        COPY_BYTE(5)
 #endif
-EXC(    lbu     t0, NBYTES-2(src), .Ll_exc_copy)
+        LOADBU(t0, NBYTES-2(src), .Ll_exc_copy\@)
        SUB     len, len, 1
-EXC(    sb      t0, NBYTES-2(dst), .Ls_exc)
+        STOREB(t0, NBYTES-2(dst), .Ls_exc\@)
        SLLV    t0, t0, t3
        or      t2, t0
-.Lcopy_bytes_done:
+.Lcopy_bytes_done\@:
        ADDC(sum, t2)
-.Ldone:
+.Ldone\@:
        /* fold checksum */
 #ifdef USE_DOUBLE
        dsll32  v1, sum, 0
@@ -689,7 +737,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
        jr      ra
        .set noreorder
-.Ll_exc_copy:
+.Ll_exc_copy\@:
        /*
         * Copy bytes from src until faulting load address (or until a
         * lb faults)
@@ -700,11 +748,11 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
         *
         * Assumes src < THREAD_BUADDR($28)
         */
-        LOAD    t0, TI_TASK($28)
+        LOADK   t0, TI_TASK($28)
         li     t2, SHIFT_START
-        LOAD    t0, THREAD_BUADDR(t0)
+        LOADK   t0, THREAD_BUADDR(t0)
 1:
-EXC(    lbu     t1, 0(src),     .Ll_exc)
+        LOADBU(t1, 0(src), .Ll_exc\@)
        ADD     src, src, 1
        sb      t1, 0(dst)      # can't fault -- we're copy_from_user
        SLLV    t1, t1, t2
@@ -714,10 +762,10 @@ EXC(	lbu	t1, 0(src),	.Ll_exc)
        ADD     dst, dst, 1
        bne     src, t0, 1b
        .set    noreorder
-.Ll_exc:
+.Ll_exc\@:
-        LOAD    t0, TI_TASK($28)
+        LOADK   t0, TI_TASK($28)
         nop
-        LOAD    t0, THREAD_BUADDR(t0)   # t0 is just past last good address
+        LOADK   t0, THREAD_BUADDR(t0)   # t0 is just past last good address
         nop
        SUB     len, AT, t0             # len number of uncopied bytes
        /*
@@ -733,7 +781,7 @@ EXC(	lbu	t1, 0(src),	.Ll_exc)
         */
        .set    reorder                         /* DADDI_WAR */
        SUB     src, len, 1
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
        .set    noreorder
 1:      sb      zero, 0(dst)
        ADD     dst, dst, 1
@@ -748,13 +796,31 @@ EXC(	lbu	t1, 0(src),	.Ll_exc)
         SUB    src, src, v1
 #endif
        li      v1, -EFAULT
-        b       .Ldone
+        b       .Ldone\@
         sw     v1, (errptr)
-.Ls_exc:
+.Ls_exc\@:
        li      v0, -1 /* invalid checksum */
        li      v1, -EFAULT
        jr      ra
         sw     v1, (errptr)
        .set    pop
-        END(__csum_partial_copy_user)
+        .endm
+LEAF(__csum_partial_copy_kernel)
+#ifndef CONFIG_EVA
+FEXPORT(__csum_partial_copy_to_user)
+FEXPORT(__csum_partial_copy_from_user)
+#endif
+__BUILD_CSUM_PARTIAL_COPY_USER LEGACY_MODE USEROP USEROP 1
+END(__csum_partial_copy_kernel)
+#ifdef CONFIG_EVA
+LEAF(__csum_partial_copy_to_user)
+__BUILD_CSUM_PARTIAL_COPY_USER EVA_MODE KERNELOP USEROP 0
+END(__csum_partial_copy_to_user)
+LEAF(__csum_partial_copy_from_user)
+__BUILD_CSUM_PARTIAL_COPY_USER EVA_MODE USEROP KERNELOP 0
+END(__csum_partial_copy_from_user)
+#endif
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index c5c40dad0bbf..c17ef80cf65a 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -10,6 +10,7 @@
 * Copyright (C) 2002 Broadcom, Inc.
 *   memcpy/copy_user author: Mark Vandevoorde
 * Copyright (C) 2007  Maciej W. Rozycki
+ * Copyright (C) 2014 Imagination Technologies Ltd.
 *
 * Mnemonic names for arguments to memcpy/__copy_user
 */
@@ -85,11 +86,51 @@
 * they're not protected.
 */
-#define EXC(inst_reg,addr,handler)              \
+/* Instruction type */
-9:      inst_reg, addr;                         \
+#define LD_INSN 1
-        .section __ex_table,"a";                \
+#define ST_INSN 2
-        PTR     9b, handler;                    \
+/* Pretech type */
-        .previous
+#define SRC_PREFETCH 1
+#define DST_PREFETCH 2
+#define LEGACY_MODE 1
+#define EVA_MODE    2
+#define USEROP   1
+#define KERNELOP 2
+/*
+ * Wrapper to add an entry in the exception table
+ * in case the insn causes a memory exception.
+ * Arguments:
+ * insn    : Load/store instruction
+ * type    : Instruction type
+ * reg     : Register
+ * addr    : Address
+ * handler : Exception handler
+ */
+#define EXC(insn, type, reg, addr, handler)                     \
+        .if \mode == LEGACY_MODE;                               \
+9:              insn reg, addr;                                 \
+                .section __ex_table,"a";                        \
+                PTR     9b, handler;                            \
+                .previous;                                      \
+        /* This is assembled in EVA mode */                     \
+        .else;                                                  \
+                /* If loading from user or storing to user */   \
+                .if ((\from == USEROP) && (type == LD_INSN)) || \
+                    ((\to == USEROP) && (type == ST_INSN));     \
+9:                      __BUILD_EVA_INSN(insn##e, reg, addr);   \
+                        .section __ex_table,"a";                \
+                        PTR     9b, handler;                    \
+                        .previous;                              \
+                .else;                                          \
+                        /*                                      \
+                         *  Still in EVA, but no need for       \
+                         * exception handler or EVA insn        \
+                         */                                     \
+                        insn reg, addr;                         \
+                .endif;                                         \
+        .endif
 /*
 * Only on the 64-bit kernel we can made use of 64-bit registers.
@@ -100,12 +141,13 @@
 #ifdef USE_DOUBLE
-#define LOAD   ld
+#define LOADK ld /* No exception */
-#define LOADL  ldl
+#define LOAD(reg, addr, handler)        EXC(ld, LD_INSN, reg, addr, handler)
-#define LOADR  ldr
+#define LOADL(reg, addr, handler)       EXC(ldl, LD_INSN, reg, addr, handler)
-#define STOREL sdl
+#define LOADR(reg, addr, handler)       EXC(ldr, LD_INSN, reg, addr, handler)
-#define STORER sdr
+#define STOREL(reg, addr, handler)      EXC(sdl, ST_INSN, reg, addr, handler)
-#define STORE  sd
+#define STORER(reg, addr, handler)      EXC(sdr, ST_INSN, reg, addr, handler)
+#define STORE(reg, addr, handler)       EXC(sd, ST_INSN, reg, addr, handler)
 #define ADD    daddu
 #define SUB    dsubu
 #define SRL    dsrl
@@ -136,12 +178,13 @@
 #else
-#define LOAD   lw
+#define LOADK lw /* No exception */
-#define LOADL  lwl
+#define LOAD(reg, addr, handler)        EXC(lw, LD_INSN, reg, addr, handler)
-#define LOADR  lwr
+#define LOADL(reg, addr, handler)       EXC(lwl, LD_INSN, reg, addr, handler)
-#define STOREL swl
+#define LOADR(reg, addr, handler)       EXC(lwr, LD_INSN, reg, addr, handler)
-#define STORER swr
+#define STOREL(reg, addr, handler)      EXC(swl, ST_INSN, reg, addr, handler)
-#define STORE  sw
+#define STORER(reg, addr, handler)      EXC(swr, ST_INSN, reg, addr, handler)
+#define STORE(reg, addr, handler)       EXC(sw, ST_INSN, reg, addr, handler)
 #define ADD    addu
 #define SUB    subu
 #define SRL    srl
@@ -154,6 +197,33 @@
 #endif /* USE_DOUBLE */
+#define LOADB(reg, addr, handler)       EXC(lb, LD_INSN, reg, addr, handler)
+#define STOREB(reg, addr, handler)      EXC(sb, ST_INSN, reg, addr, handler)
+#define _PREF(hint, addr, type)                                         \
+        .if \mode == LEGACY_MODE;                                       \
+                PREF(hint, addr);                                       \
+        .else;                                                          \
+                .if ((\from == USEROP) && (type == SRC_PREFETCH)) ||    \
+                    ((\to == USEROP) && (type == DST_PREFETCH));        \
+                        /*                                              \
+                         * PREFE has only 9 bits for the offset         \
+                         * compared to PREF which has 16, so it may     \
+                         * need to use the $at register but this        \
+                         * register should remain intact because it's   \
+                         * used later on. Therefore use $v1.            \
+                         */                                             \
+                        .set at=v1;                                     \
+                        PREFE(hint, addr);                              \
+                        .set noat;                                      \
+                .else;                                                  \
+                        PREF(hint, addr);                               \
+                .endif;                                                 \
+        .endif
+#define PREFS(hint, addr) _PREF(hint, addr, SRC_PREFETCH)
+#define PREFD(hint, addr) _PREF(hint, addr, DST_PREFETCH)
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR
 #define LDREST  LOADL
@@ -182,27 +252,23 @@
        .set    at=v1
 #endif
-/*
- * t6 is used as a flag to note inatomic mode.
- */
-LEAF(__copy_user_inatomic)
-        b       __copy_user_common
-         li     t6, 1
-        END(__copy_user_inatomic)
-/*
- * A combined memcpy/__copy_user
- * __copy_user sets len to 0 for success; else to an upper bound of
- * the number of uncopied bytes.
- * memcpy sets v0 to dst.
- */
        .align  5
-LEAF(memcpy)                                    /* a0=dst a1=src a2=len */
-        move    v0, dst                         /* return value */
+        /*
-.L__memcpy:
+         * Macro to build the __copy_user common code
-FEXPORT(__copy_user)
+         * Arguements:
-        li      t6, 0   /* not inatomic */
+         * mode : LEGACY_MODE or EVA_MODE
-__copy_user_common:
+         * from : Source operand. USEROP or KERNELOP
+         * to   : Destination operand. USEROP or KERNELOP
+         */
+        .macro __BUILD_COPY_USER mode, from, to
+        /* initialize __memcpy if this the first time we execute this macro */
+        .ifnotdef __memcpy
+        .set __memcpy, 1
+        .hidden __memcpy /* make sure it does not leak */
+        .endif
        /*
         * Note: dst & src may be unaligned, len may be 0
         * Temps
@@ -217,94 +283,94 @@ __copy_user_common:
         *
         * If len < NBYTES use byte operations.
         */
-        PREF(   0, 0(src) )
+        PREFS(  0, 0(src) )
-        PREF(   1, 0(dst) )
+        PREFD(  1, 0(dst) )
        sltu    t2, len, NBYTES
        and     t1, dst, ADDRMASK
-        PREF(   0, 1*32(src) )
+        PREFS(  0, 1*32(src) )
-        PREF(   1, 1*32(dst) )
+        PREFD(  1, 1*32(dst) )
-        bnez    t2, .Lcopy_bytes_checklen
+        bnez    t2, .Lcopy_bytes_checklen\@
         and    t0, src, ADDRMASK
-        PREF(   0, 2*32(src) )
+        PREFS(  0, 2*32(src) )
-        PREF(   1, 2*32(dst) )
+        PREFD(  1, 2*32(dst) )
-        bnez    t1, .Ldst_unaligned
+        bnez    t1, .Ldst_unaligned\@
         nop
-        bnez    t0, .Lsrc_unaligned_dst_aligned
+        bnez    t0, .Lsrc_unaligned_dst_aligned\@
        /*
         * use delay slot for fall-through
         * src and dst are aligned; need to compute rem
         */
-.Lboth_aligned:
+.Lboth_aligned\@:
         SRL    t0, len, LOG_NBYTES+3    # +3 for 8 units/iter
-        beqz    t0, .Lcleanup_both_aligned # len < 8*NBYTES
+        beqz    t0, .Lcleanup_both_aligned\@ # len < 8*NBYTES
         and    rem, len, (8*NBYTES-1)   # rem = len % (8*NBYTES)
-        PREF(   0, 3*32(src) )
+        PREFS(  0, 3*32(src) )
-        PREF(   1, 3*32(dst) )
+        PREFD(  1, 3*32(dst) )
        .align  4
 1:
        R10KCBARRIER(0(ra))
-EXC(    LOAD    t0, UNIT(0)(src),       .Ll_exc)
+        LOAD(t0, UNIT(0)(src), .Ll_exc\@)
-EXC(    LOAD    t1, UNIT(1)(src),       .Ll_exc_copy)
+        LOAD(t1, UNIT(1)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t2, UNIT(2)(src),       .Ll_exc_copy)
+        LOAD(t2, UNIT(2)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t3, UNIT(3)(src),       .Ll_exc_copy)
+        LOAD(t3, UNIT(3)(src), .Ll_exc_copy\@)
        SUB     len, len, 8*NBYTES
-EXC(    LOAD    t4, UNIT(4)(src),       .Ll_exc_copy)
+        LOAD(t4, UNIT(4)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t7, UNIT(5)(src),       .Ll_exc_copy)
+        LOAD(t7, UNIT(5)(src), .Ll_exc_copy\@)
-EXC(    STORE   t0, UNIT(0)(dst),       .Ls_exc_p8u)
+        STORE(t0, UNIT(0)(dst), .Ls_exc_p8u\@)
-EXC(    STORE   t1, UNIT(1)(dst),       .Ls_exc_p7u)
+        STORE(t1, UNIT(1)(dst), .Ls_exc_p7u\@)
-EXC(    LOAD    t0, UNIT(6)(src),       .Ll_exc_copy)
+        LOAD(t0, UNIT(6)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t1, UNIT(7)(src),       .Ll_exc_copy)
+        LOAD(t1, UNIT(7)(src), .Ll_exc_copy\@)
        ADD     src, src, 8*NBYTES
        ADD     dst, dst, 8*NBYTES
-EXC(    STORE   t2, UNIT(-6)(dst),      .Ls_exc_p6u)
+        STORE(t2, UNIT(-6)(dst), .Ls_exc_p6u\@)
-EXC(    STORE   t3, UNIT(-5)(dst),      .Ls_exc_p5u)
+        STORE(t3, UNIT(-5)(dst), .Ls_exc_p5u\@)
-EXC(    STORE   t4, UNIT(-4)(dst),      .Ls_exc_p4u)
+        STORE(t4, UNIT(-4)(dst), .Ls_exc_p4u\@)
-EXC(    STORE   t7, UNIT(-3)(dst),      .Ls_exc_p3u)
+        STORE(t7, UNIT(-3)(dst), .Ls_exc_p3u\@)
-EXC(    STORE   t0, UNIT(-2)(dst),      .Ls_exc_p2u)
+        STORE(t0, UNIT(-2)(dst), .Ls_exc_p2u\@)
-EXC(    STORE   t1, UNIT(-1)(dst),      .Ls_exc_p1u)
+        STORE(t1, UNIT(-1)(dst), .Ls_exc_p1u\@)
-        PREF(   0, 8*32(src) )
+        PREFS(  0, 8*32(src) )
-        PREF(   1, 8*32(dst) )
+        PREFD(  1, 8*32(dst) )
        bne     len, rem, 1b
         nop
        /*
         * len == rem == the number of bytes left to copy < 8*NBYTES
         */
-.Lcleanup_both_aligned:
+.Lcleanup_both_aligned\@:
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
         sltu   t0, len, 4*NBYTES
-        bnez    t0, .Lless_than_4units
+        bnez    t0, .Lless_than_4units\@
         and    rem, len, (NBYTES-1)    # rem = len % NBYTES
        /*
         * len >= 4*NBYTES
         */
-EXC(    LOAD    t0, UNIT(0)(src),       .Ll_exc)
+        LOAD( t0, UNIT(0)(src), .Ll_exc\@)
-EXC(    LOAD    t1, UNIT(1)(src),       .Ll_exc_copy)
+        LOAD( t1, UNIT(1)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t2, UNIT(2)(src),       .Ll_exc_copy)
+        LOAD( t2, UNIT(2)(src), .Ll_exc_copy\@)
-EXC(    LOAD    t3, UNIT(3)(src),       .Ll_exc_copy)
+        LOAD( t3, UNIT(3)(src), .Ll_exc_copy\@)
        SUB     len, len, 4*NBYTES
        ADD     src, src, 4*NBYTES
        R10KCBARRIER(0(ra))
-EXC(    STORE   t0, UNIT(0)(dst),       .Ls_exc_p4u)
+        STORE(t0, UNIT(0)(dst), .Ls_exc_p4u\@)
-EXC(    STORE   t1, UNIT(1)(dst),       .Ls_exc_p3u)
+        STORE(t1, UNIT(1)(dst), .Ls_exc_p3u\@)
-EXC(    STORE   t2, UNIT(2)(dst),       .Ls_exc_p2u)
+        STORE(t2, UNIT(2)(dst), .Ls_exc_p2u\@)
-EXC(    STORE   t3, UNIT(3)(dst),       .Ls_exc_p1u)
+        STORE(t3, UNIT(3)(dst), .Ls_exc_p1u\@)
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, 4*NBYTES
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
        .set    noreorder
-.Lless_than_4units:
+.Lless_than_4units\@:
        /*
         * rem = len % NBYTES
         */
-        beq     rem, len, .Lcopy_bytes
+        beq     rem, len, .Lcopy_bytes\@
         nop
 1:
        R10KCBARRIER(0(ra))
-EXC(    LOAD    t0, 0(src),             .Ll_exc)
+        LOAD(t0, 0(src), .Ll_exc\@)
        ADD     src, src, NBYTES
        SUB     len, len, NBYTES
-EXC(    STORE   t0, 0(dst),             .Ls_exc_p1u)
+        STORE(t0, 0(dst), .Ls_exc_p1u\@)
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, NBYTES
        bne     rem, len, 1b
@@ -322,17 +388,17 @@ EXC(	STORE	t0, 0(dst),		.Ls_exc_p1u)
         * more instruction-level parallelism.
         */
 #define bits t2
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
         ADD    t1, dst, len    # t1 is just past last byte of dst
        li      bits, 8*NBYTES
        SLL     rem, len, 3     # rem = number of bits to keep
-EXC(    LOAD    t0, 0(src),             .Ll_exc)
+        LOAD(t0, 0(src), .Ll_exc\@)
        SUB     bits, bits, rem # bits = number of bits to discard
        SHIFT_DISCARD t0, t0, bits
-EXC(    STREST  t0, -1(t1),             .Ls_exc)
+        STREST(t0, -1(t1), .Ls_exc\@)
        jr      ra
         move   len, zero
-.Ldst_unaligned:
+.Ldst_unaligned\@:
        /*
         * dst is unaligned
         * t0 = src & ADDRMASK
@@ -343,25 +409,25 @@ EXC(	STREST	t0, -1(t1),		.Ls_exc)
         * Set match = (src and dst have same alignment)
         */
 #define match rem
-EXC(    LDFIRST t3, FIRST(0)(src),      .Ll_exc)
+        LDFIRST(t3, FIRST(0)(src), .Ll_exc\@)
        ADD     t2, zero, NBYTES
-EXC(    LDREST  t3, REST(0)(src),       .Ll_exc_copy)
+        LDREST(t3, REST(0)(src), .Ll_exc_copy\@)
        SUB     t2, t2, t1      # t2 = number of bytes copied
        xor     match, t0, t1
        R10KCBARRIER(0(ra))
-EXC(    STFIRST t3, FIRST(0)(dst),      .Ls_exc)
+        STFIRST(t3, FIRST(0)(dst), .Ls_exc\@)
-        beq     len, t2, .Ldone
+        beq     len, t2, .Ldone\@
         SUB    len, len, t2
        ADD     dst, dst, t2
-        beqz    match, .Lboth_aligned
+        beqz    match, .Lboth_aligned\@
         ADD    src, src, t2
-.Lsrc_unaligned_dst_aligned:
+.Lsrc_unaligned_dst_aligned\@:
        SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
-        PREF(   0, 3*32(src) )
+        PREFS(  0, 3*32(src) )
-        beqz    t0, .Lcleanup_src_unaligned
+        beqz    t0, .Lcleanup_src_unaligned\@
         and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
-        PREF(   1, 3*32(dst) )
+        PREFD(  1, 3*32(dst) )
 1:
 /*
 * Avoid consecutive LD*'s to the same register since some mips
@@ -370,58 +436,58 @@ EXC(	STFIRST t3, FIRST(0)(dst),	.Ls_exc)
 * are to the same unit (unless src is aligned, but it's not).
 */
        R10KCBARRIER(0(ra))
-EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
+        LDFIRST(t0, FIRST(0)(src), .Ll_exc\@)
-EXC(    LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
+        LDFIRST(t1, FIRST(1)(src), .Ll_exc_copy\@)
        SUB     len, len, 4*NBYTES
-EXC(    LDREST  t0, REST(0)(src),       .Ll_exc_copy)
+        LDREST(t0, REST(0)(src), .Ll_exc_copy\@)
-EXC(    LDREST  t1, REST(1)(src),       .Ll_exc_copy)
+        LDREST(t1, REST(1)(src), .Ll_exc_copy\@)
-EXC(    LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
+        LDFIRST(t2, FIRST(2)(src), .Ll_exc_copy\@)
-EXC(    LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)
+        LDFIRST(t3, FIRST(3)(src), .Ll_exc_copy\@)
-EXC(    LDREST  t2, REST(2)(src),       .Ll_exc_copy)
+        LDREST(t2, REST(2)(src), .Ll_exc_copy\@)
-EXC(    LDREST  t3, REST(3)(src),       .Ll_exc_copy)
+        LDREST(t3, REST(3)(src), .Ll_exc_copy\@)
-        PREF(   0, 9*32(src) )          # 0 is PREF_LOAD  (not streamed)
+        PREFS(  0, 9*32(src) )          # 0 is PREF_LOAD  (not streamed)
        ADD     src, src, 4*NBYTES
 #ifdef CONFIG_CPU_SB1
        nop                             # improves slotting
 #endif
-EXC(    STORE   t0, UNIT(0)(dst),       .Ls_exc_p4u)
+        STORE(t0, UNIT(0)(dst), .Ls_exc_p4u\@)
-EXC(    STORE   t1, UNIT(1)(dst),       .Ls_exc_p3u)
+        STORE(t1, UNIT(1)(dst), .Ls_exc_p3u\@)
-EXC(    STORE   t2, UNIT(2)(dst),       .Ls_exc_p2u)
+        STORE(t2, UNIT(2)(dst), .Ls_exc_p2u\@)
-EXC(    STORE   t3, UNIT(3)(dst),       .Ls_exc_p1u)
+        STORE(t3, UNIT(3)(dst), .Ls_exc_p1u\@)
-        PREF(   1, 9*32(dst) )          # 1 is PREF_STORE (not streamed)
+        PREFD(  1, 9*32(dst) )          # 1 is PREF_STORE (not streamed)
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, 4*NBYTES
        bne     len, rem, 1b
        .set    noreorder
-.Lcleanup_src_unaligned:
+.Lcleanup_src_unaligned\@:
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
         and    rem, len, NBYTES-1  # rem = len % NBYTES
-        beq     rem, len, .Lcopy_bytes
+        beq     rem, len, .Lcopy_bytes\@
         nop
 1:
        R10KCBARRIER(0(ra))
-EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
+        LDFIRST(t0, FIRST(0)(src), .Ll_exc\@)
-EXC(    LDREST  t0, REST(0)(src),       .Ll_exc_copy)
+        LDREST(t0, REST(0)(src), .Ll_exc_copy\@)
        ADD     src, src, NBYTES
        SUB     len, len, NBYTES
-EXC(    STORE   t0, 0(dst),             .Ls_exc_p1u)
+        STORE(t0, 0(dst), .Ls_exc_p1u\@)
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, NBYTES
        bne     len, rem, 1b
        .set    noreorder
-.Lcopy_bytes_checklen:
+.Lcopy_bytes_checklen\@:
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
         nop
-.Lcopy_bytes:
+.Lcopy_bytes\@:
        /* 0 < len < NBYTES  */
        R10KCBARRIER(0(ra))
 #define COPY_BYTE(N)                    \
-EXC(    lb      t0, N(src), .Ll_exc);   \
+        LOADB(t0, N(src), .Ll_exc\@);   \
        SUB     len, len, 1;            \
-        beqz    len, .Ldone;            \
+        beqz    len, .Ldone\@;          \
-EXC(     sb     t0, N(dst), .Ls_exc_p1)
+        STOREB(t0, N(dst), .Ls_exc_p1\@)
        COPY_BYTE(0)
        COPY_BYTE(1)
@@ -431,16 +497,19 @@ EXC(	 sb	t0, N(dst), .Ls_exc_p1)
        COPY_BYTE(4)
        COPY_BYTE(5)
 #endif
-EXC(    lb      t0, NBYTES-2(src), .Ll_exc)
+        LOADB(t0, NBYTES-2(src), .Ll_exc\@)
        SUB     len, len, 1
        jr      ra
-EXC(     sb     t0, NBYTES-2(dst), .Ls_exc_p1)
+        STOREB(t0, NBYTES-2(dst), .Ls_exc_p1\@)
-.Ldone:
+.Ldone\@:
        jr      ra
-         nop
+        .if __memcpy == 1
        END(memcpy)
+        .set __memcpy, 0
+        .hidden __memcpy
+        .endif
-.Ll_exc_copy:
+.Ll_exc_copy\@:
        /*
         * Copy bytes from src until faulting load address (or until a
         * lb faults)
@@ -451,24 +520,24 @@ EXC(	 sb	t0, NBYTES-2(dst), .Ls_exc_p1)
         *
         * Assumes src < THREAD_BUADDR($28)
         */
-        LOAD    t0, TI_TASK($28)
+        LOADK   t0, TI_TASK($28)
         nop
-        LOAD    t0, THREAD_BUADDR(t0)
+        LOADK   t0, THREAD_BUADDR(t0)
 1:
-EXC(    lb      t1, 0(src),     .Ll_exc)
+        LOADB(t1, 0(src), .Ll_exc\@)
        ADD     src, src, 1
        sb      t1, 0(dst)      # can't fault -- we're copy_from_user
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, 1
        bne     src, t0, 1b
        .set    noreorder
-.Ll_exc:
+.Ll_exc\@:
-        LOAD    t0, TI_TASK($28)
+        LOADK   t0, TI_TASK($28)
         nop
-        LOAD    t0, THREAD_BUADDR(t0)   # t0 is just past last good address
+        LOADK   t0, THREAD_BUADDR(t0)   # t0 is just past last good address
         nop
        SUB     len, AT, t0             # len number of uncopied bytes
-        bnez    t6, .Ldone      /* Skip the zeroing part if inatomic */
+        bnez    t6, .Ldone\@    /* Skip the zeroing part if inatomic */
        /*
         * Here's where we rely on src and dst being incremented in tandem,
         *   See (3) above.
@@ -482,7 +551,7 @@ EXC(	lb	t1, 0(src),	.Ll_exc)
         */
        .set    reorder                         /* DADDI_WAR */
        SUB     src, len, 1
-        beqz    len, .Ldone
+        beqz    len, .Ldone\@
        .set    noreorder
 1:      sb      zero, 0(dst)
        ADD     dst, dst, 1
@@ -503,7 +572,7 @@ EXC(	lb	t1, 0(src),	.Ll_exc)
 #define SEXC(n)                                                 \
        .set    reorder;                        /* DADDI_WAR */ \
-.Ls_exc_p ## n ## u:                                            \
+.Ls_exc_p ## n ## u\@:                                          \
        ADD     len, len, n*NBYTES;                             \
        jr      ra;                                             \
        .set    noreorder
@@ -517,14 +586,15 @@ SEXC(3)
 SEXC(2)
 SEXC(1)
-.Ls_exc_p1:
+.Ls_exc_p1\@:
        .set    reorder                         /* DADDI_WAR */
        ADD     len, len, 1
        jr      ra
        .set    noreorder
-.Ls_exc:
+.Ls_exc\@:
        jr      ra
         nop
+        .endm
        .align  5
 LEAF(memmove)
@@ -575,3 +645,71 @@ LEAF(__rmemcpy)					/* a0=dst a1=src a2=len */
        jr      ra
         move   a2, zero
        END(__rmemcpy)
+/*
+ * t6 is used as a flag to note inatomic mode.
+ */
+LEAF(__copy_user_inatomic)
+        b       __copy_user_common
+        li      t6, 1
+        END(__copy_user_inatomic)
+/*
+ * A combined memcpy/__copy_user
+ * __copy_user sets len to 0 for success; else to an upper bound of
+ * the number of uncopied bytes.
+ * memcpy sets v0 to dst.
+ */
+        .align  5
+LEAF(memcpy)                                    /* a0=dst a1=src a2=len */
+        move    v0, dst                         /* return value */
+.L__memcpy:
+FEXPORT(__copy_user)
+        li      t6, 0   /* not inatomic */
+__copy_user_common:
+        /* Legacy Mode, user <-> user */
+        __BUILD_COPY_USER LEGACY_MODE USEROP USEROP
+#ifdef CONFIG_EVA
+/*
+ * For EVA we need distinct symbols for reading and writing to user space.
+ * This is because we need to use specific EVA instructions to perform the
+ * virtual <-> physical translation when a virtual address is actually in user
+ * space
+ */
+LEAF(__copy_user_inatomic_eva)
+        b       __copy_from_user_common
+        li      t6, 1
+        END(__copy_user_inatomic_eva)
+/*
+ * __copy_from_user (EVA)
+ */
+LEAF(__copy_from_user_eva)
+        li      t6, 0   /* not inatomic */
+__copy_from_user_common:
+        __BUILD_COPY_USER EVA_MODE USEROP KERNELOP
+END(__copy_from_user_eva)
+/*
+ * __copy_to_user (EVA)
+ */
+LEAF(__copy_to_user_eva)
+__BUILD_COPY_USER EVA_MODE KERNELOP USEROP
+END(__copy_to_user_eva)
+/*
+ * __copy_in_user (EVA)
+ */
+LEAF(__copy_in_user_eva)
+__BUILD_COPY_USER EVA_MODE USEROP USEROP
+END(__copy_in_user_eva)
+#endif
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 0580194e7402..7b0e5462ca51 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -34,13 +34,27 @@
 #define FILLPTRG t0
 #endif
+#define LEGACY_MODE 1
+#define EVA_MODE    2
+/*
+ * No need to protect it with EVA #ifdefery. The generated block of code
+ * will never be assembled if EVA is not enabled.
+ */
+#define __EVAFY(insn, reg, addr) __BUILD_EVA_INSN(insn##e, reg, addr)
+#define ___BUILD_EVA_INSN(insn, reg, addr) __EVAFY(insn, reg, addr)
 #define EX(insn,reg,addr,handler)                       \
-9:      insn    reg, addr;                              \
+        .if \mode == LEGACY_MODE;                       \
+9:              insn    reg, addr;                      \
+        .else;                                          \
+9:              ___BUILD_EVA_INSN(insn, reg, addr);     \
+        .endif;                                         \
        .section __ex_table,"a";                        \
        PTR     9b, handler;                            \
        .previous
-        .macro  f_fill64 dst, offset, val, fixup
+        .macro  f_fill64 dst, offset, val, fixup, mode
        EX(LONG_S, \val, (\offset +  0 * STORSIZE)(\dst), \fixup)
        EX(LONG_S, \val, (\offset +  1 * STORSIZE)(\dst), \fixup)
        EX(LONG_S, \val, (\offset +  2 * STORSIZE)(\dst), \fixup)
@@ -63,34 +77,24 @@
 #endif
        .endm
-/*
- * memset(void *s, int c, size_t n)
- *
- * a0: start of area to clear
- * a1: char to fill with
- * a2: size of area to clear
- */
        .set    noreorder
        .align  5
-LEAF(memset)
-        beqz            a1, 1f
-         move           v0, a0                  /* result */
-        andi            a1, 0xff                /* spread fillword */
+        /*
-        LONG_SLL                t1, a1, 8
+         * Macro to generate the __bzero{,_user} symbol
-        or              a1, t1
+         * Arguments:
-        LONG_SLL                t1, a1, 16
+         * mode: LEGACY_MODE or EVA_MODE
-#if LONGSIZE == 8
+         */
-        or              a1, t1
+        .macro __BUILD_BZERO mode
-        LONG_SLL                t1, a1, 32
+        /* Initialize __memset if this is the first time we call this macro */
-#endif
+        .ifnotdef __memset
-        or              a1, t1
+        .set __memset, 1
-1:
+        .hidden __memset /* Make sure it does not leak */
+        .endif
-FEXPORT(__bzero)
        sltiu           t0, a2, STORSIZE        /* very small region? */
-        bnez            t0, .Lsmall_memset
+        bnez            t0, .Lsmall_memset\@
-         andi           t0, a0, STORMASK        /* aligned? */
+        andi            t0, a0, STORMASK        /* aligned? */
 #ifdef CONFIG_CPU_MICROMIPS
        move            t8, a1                  /* used by 'swp' instruction */
@@ -98,39 +102,39 @@ FEXPORT(__bzero)
 #endif
 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
        beqz            t0, 1f
-         PTR_SUBU       t0, STORSIZE            /* alignment in bytes */
+        PTR_SUBU        t0, STORSIZE            /* alignment in bytes */
 #else
        .set            noat
        li              AT, STORSIZE
        beqz            t0, 1f
-         PTR_SUBU       t0, AT                  /* alignment in bytes */
+        PTR_SUBU        t0, AT                  /* alignment in bytes */
        .set            at
 #endif
        R10KCBARRIER(0(ra))
 #ifdef __MIPSEB__
-        EX(LONG_S_L, a1, (a0), .Lfirst_fixup)   /* make word/dword aligned */
+        EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
 #endif
 #ifdef __MIPSEL__
-        EX(LONG_S_R, a1, (a0), .Lfirst_fixup)   /* make word/dword aligned */
+        EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
 #endif
        PTR_SUBU        a0, t0                  /* long align ptr */
        PTR_ADDU        a2, t0                  /* correct size */
 1:      ori             t1, a2, 0x3f            /* # of full blocks */
        xori            t1, 0x3f
-        beqz            t1, .Lmemset_partial    /* no block to fill */
+        beqz            t1, .Lmemset_partial\@  /* no block to fill */
-         andi           t0, a2, 0x40-STORSIZE
+        andi            t0, a2, 0x40-STORSIZE
        PTR_ADDU        t1, a0                  /* end address */
        .set            reorder
 1:      PTR_ADDIU       a0, 64
        R10KCBARRIER(0(ra))
-        f_fill64 a0, -64, FILL64RG, .Lfwd_fixup
+        f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
        bne             t1, a0, 1b
        .set            noreorder
-.Lmemset_partial:
+.Lmemset_partial\@:
        R10KCBARRIER(0(ra))
        PTR_LA          t1, 2f                  /* where to start */
 #ifdef CONFIG_CPU_MICROMIPS
@@ -145,60 +149,100 @@ FEXPORT(__bzero)
        .set            at
 #endif
        jr              t1
-         PTR_ADDU       a0, t0                  /* dest ptr */
+        PTR_ADDU        a0, t0                  /* dest ptr */
        .set            push
        .set            noreorder
        .set            nomacro
-        f_fill64 a0, -64, FILL64RG, .Lpartial_fixup     /* ... but first do longs ... */
+        /* ... but first do longs ... */
+        f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
 2:      .set            pop
        andi            a2, STORMASK            /* At most one long to go */
        beqz            a2, 1f
-         PTR_ADDU       a0, a2                  /* What's left */
+        PTR_ADDU        a0, a2                  /* What's left */
        R10KCBARRIER(0(ra))
 #ifdef __MIPSEB__
-        EX(LONG_S_R, a1, -1(a0), .Llast_fixup)
+        EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
 #endif
 #ifdef __MIPSEL__
-        EX(LONG_S_L, a1, -1(a0), .Llast_fixup)
+        EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
 #endif
 1:      jr              ra
-         move           a2, zero
+        move            a2, zero
-.Lsmall_memset:
+.Lsmall_memset\@:
        beqz            a2, 2f
-         PTR_ADDU       t1, a0, a2
+        PTR_ADDU        t1, a0, a2
 1:      PTR_ADDIU       a0, 1                   /* fill bytewise */
        R10KCBARRIER(0(ra))
        bne             t1, a0, 1b
-         sb             a1, -1(a0)
+        sb              a1, -1(a0)
 2:      jr              ra                      /* done */
-         move           a2, zero
+        move            a2, zero
+        .if __memset == 1
        END(memset)
+        .set __memset, 0
+        .hidden __memset
+        .endif
-.Lfirst_fixup:
+.Lfirst_fixup\@:
        jr      ra
-         nop
+        nop
-.Lfwd_fixup:
+.Lfwd_fixup\@:
        PTR_L           t0, TI_TASK($28)
        andi            a2, 0x3f
        LONG_L          t0, THREAD_BUADDR(t0)
        LONG_ADDU       a2, t1
        jr              ra
-         LONG_SUBU      a2, t0
+        LONG_SUBU       a2, t0
-.Lpartial_fixup:
+.Lpartial_fixup\@:
        PTR_L           t0, TI_TASK($28)
        andi            a2, STORMASK
        LONG_L          t0, THREAD_BUADDR(t0)
        LONG_ADDU       a2, t1
        jr              ra
-         LONG_SUBU      a2, t0
+        LONG_SUBU       a2, t0
-.Llast_fixup:
+.Llast_fixup\@:
        jr              ra
-         andi           v1, a2, STORMASK
+        andi            v1, a2, STORMASK
+        .endm
+/*
+ * memset(void *s, int c, size_t n)
+ *
+ * a0: start of area to clear
+ * a1: char to fill with
+ * a2: size of area to clear
+ */
+LEAF(memset)
+        beqz            a1, 1f
+        move            v0, a0                  /* result */
+        andi            a1, 0xff                /* spread fillword */
+        LONG_SLL                t1, a1, 8
+        or              a1, t1
+        LONG_SLL                t1, a1, 16
+#if LONGSIZE == 8
+        or              a1, t1
+        LONG_SLL                t1, a1, 32
+#endif
+        or              a1, t1
+1:
+#ifndef CONFIG_EVA
+FEXPORT(__bzero)
+#endif
+        __BUILD_BZERO LEGACY_MODE
+#ifdef CONFIG_EVA
+LEAF(__bzero)
+        __BUILD_BZERO EVA_MODE
+END(__bzero)
+#endif
diff --git a/arch/mips/lib/strlen_user.S b/arch/mips/lib/strlen_user.S
index e362dcdc69d1..bef65c98df59 100644
--- a/arch/mips/lib/strlen_user.S
+++ b/arch/mips/lib/strlen_user.S
@@ -22,19 +22,43 @@
 *
 * Return 0 for error
 */
-LEAF(__strlen_user_asm)
+        .macro __BUILD_STRLEN_ASM func
+LEAF(__strlen_\func\()_asm)
        LONG_L          v0, TI_ADDR_LIMIT($28)  # pointer ok?
        and             v0, a0
-        bnez            v0, .Lfault
+        bnez            v0, .Lfault\@
-FEXPORT(__strlen_user_nocheck_asm)
+FEXPORT(__strlen_\func\()_nocheck_asm)
        move            v0, a0
-1:      EX(lbu, v1, (v0), .Lfault)
+.ifeqs "\func", "kernel"
+1:      EX(lbu, v1, (v0), .Lfault\@)
+.else
+1:      EX(lbue, v1, (v0), .Lfault\@)
+.endif
        PTR_ADDIU       v0, 1
        bnez            v1, 1b
        PTR_SUBU        v0, a0
        jr              ra
-        END(__strlen_user_asm)
+        END(__strlen_\func\()_asm)
-.Lfault:        move            v0, zero
+.Lfault\@:      move            v0, zero
        jr              ra
+        .endm
+#ifndef CONFIG_EVA
+        /* Set aliases */
+        .global __strlen_user_asm
+        .global __strlen_user_nocheck_asm
+        .set __strlen_user_asm, __strlen_kernel_asm
+        .set __strlen_user_nocheck_asm, __strlen_kernel_nocheck_asm
+#endif
+__BUILD_STRLEN_ASM kernel
+#ifdef CONFIG_EVA
+        .set push
+        .set eva
+__BUILD_STRLEN_ASM user
+        .set pop
+#endif
diff --git a/arch/mips/lib/strncpy_user.S b/arch/mips/lib/strncpy_user.S
index 92870b6b53ea..d3301cd1e9a5 100644
--- a/arch/mips/lib/strncpy_user.S
+++ b/arch/mips/lib/strncpy_user.S
@@ -28,16 +28,21 @@
 * it happens at most some bytes of the exceptions handlers will be copied.
 */
-LEAF(__strncpy_from_user_asm)
+        .macro __BUILD_STRNCPY_ASM func
+LEAF(__strncpy_from_\func\()_asm)
        LONG_L          v0, TI_ADDR_LIMIT($28)  # pointer ok?
        and             v0, a1
-        bnez            v0, .Lfault
+        bnez            v0, .Lfault\@
-FEXPORT(__strncpy_from_user_nocheck_asm)
+FEXPORT(__strncpy_from_\func\()_nocheck_asm)
        .set            noreorder
        move            t0, zero
        move            v1, a1
-1:      EX(lbu, v0, (v1), .Lfault)
+.ifeqs "\func","kernel"
+1:      EX(lbu, v0, (v1), .Lfault\@)
+.else
+1:      EX(lbue, v0, (v1), .Lfault\@)
+.endif
        PTR_ADDIU       v1, 1
        R10KCBARRIER(0(ra))
        beqz            v0, 2f
@@ -47,15 +52,34 @@ FEXPORT(__strncpy_from_user_nocheck_asm)
         PTR_ADDIU      a0, 1
 2:      PTR_ADDU        v0, a1, t0
        xor             v0, a1
-        bltz            v0, .Lfault
+        bltz            v0, .Lfault\@
         nop
        jr              ra                      # return n
         move           v0, t0
-        END(__strncpy_from_user_asm)
+        END(__strncpy_from_\func\()_asm)
-.Lfault: jr             ra
+.Lfault\@: jr           ra
          li            v0, -EFAULT
        .section        __ex_table,"a"
-        PTR             1b, .Lfault
+        PTR             1b, .Lfault\@
        .previous
+        .endm
+#ifndef CONFIG_EVA
+        /* Set aliases */
+        .global __strncpy_from_user_asm
+        .global __strncpy_from_user_nocheck_asm
+        .set __strncpy_from_user_asm, __strncpy_from_kernel_asm
+        .set __strncpy_from_user_nocheck_asm, __strncpy_from_kernel_nocheck_asm
+#endif
+__BUILD_STRNCPY_ASM kernel
+#ifdef CONFIG_EVA
+        .set push
+        .set eva
+__BUILD_STRNCPY_ASM user
+        .set pop
+#endif
diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S
index fcacea5e61f1..f3af6995e2a6 100644
--- a/arch/mips/lib/strnlen_user.S
+++ b/arch/mips/lib/strnlen_user.S
@@ -25,22 +25,46 @@
 *       bytes.  There's nothing secret there.  On 64-bit accessing beyond
 *       the maximum is a tad hairier ...
 */
-LEAF(__strnlen_user_asm)
+        .macro __BUILD_STRNLEN_ASM func
+LEAF(__strnlen_\func\()_asm)
        LONG_L          v0, TI_ADDR_LIMIT($28)  # pointer ok?
        and             v0, a0
-        bnez            v0, .Lfault
+        bnez            v0, .Lfault\@
-FEXPORT(__strnlen_user_nocheck_asm)
+FEXPORT(__strnlen_\func\()_nocheck_asm)
        move            v0, a0
        PTR_ADDU        a1, a0                  # stop pointer
 1:      beq             v0, a1, 1f              # limit reached?
-        EX(lb, t0, (v0), .Lfault)
+.ifeqs "\func", "kernel"
+        EX(lb, t0, (v0), .Lfault\@)
+.else
+        EX(lbe, t0, (v0), .Lfault\@)
+.endif
        PTR_ADDIU       v0, 1
        bnez            t0, 1b
 1:      PTR_SUBU        v0, a0
        jr              ra
-        END(__strnlen_user_asm)
+        END(__strnlen_\func\()_asm)
-.Lfault:
+.Lfault\@:
        move            v0, zero
        jr              ra
+        .endm
+#ifndef CONFIG_EVA
+        /* Set aliases */
+        .global __strnlen_user_asm
+        .global __strnlen_user_nocheck_asm
+        .set __strnlen_user_asm, __strnlen_kernel_asm
+        .set __strnlen_user_nocheck_asm, __strnlen_kernel_nocheck_asm
+#endif
+__BUILD_STRNLEN_ASM kernel
+#ifdef CONFIG_EVA
+        .set push
+        .set eva
+__BUILD_STRNLEN_ASM user
+        .set pop
+#endif
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index 263beb9322a8..7397be226a06 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -59,6 +59,36 @@ config LEMOTE_MACH2F
          These family machines include fuloong2f mini PC, yeeloong2f notebook,
          LingLoong allinone PC and so forth.
+config LEMOTE_MACH3A
+        bool "Lemote Loongson 3A family machines"
+        select ARCH_SPARSEMEM_ENABLE
+        select GENERIC_ISA_DMA_SUPPORT_BROKEN
+        select GENERIC_HARDIRQS_NO__DO_IRQ
+        select BOOT_ELF32
+        select BOARD_SCACHE
+        select CSRC_R4K
+        select CEVT_R4K
+        select CPU_HAS_WB
+        select HW_HAS_PCI
+        select ISA
+        select HT_PCI
+        select I8259
+        select IRQ_CPU
+        select NR_CPUS_DEFAULT_4
+        select SYS_HAS_CPU_LOONGSON3
+        select SYS_HAS_EARLY_PRINTK
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
+        select SYS_SUPPORTS_64BIT_KERNEL
+        select SYS_SUPPORTS_HIGHMEM
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select LOONGSON_MC146818
+        select ZONE_DMA32
+        select LEFI_FIRMWARE_INTERFACE
+        help
+                Lemote Loongson 3A family machines utilize the 3A revision of
+                Loongson processor and RS780/SBX00 chipset.
 endchoice
 config CS5536
@@ -86,8 +116,25 @@ config LOONGSON_UART_BASE
        default y
        depends on EARLY_PRINTK || SERIAL_8250
+config IOMMU_HELPER
+        bool
+config NEED_SG_DMA_LENGTH
+        bool
+config SWIOTLB
+        bool "Soft IOMMU Support for All-Memory DMA"
+        default y
+        depends on CPU_LOONGSON3
+        select IOMMU_HELPER
+        select NEED_SG_DMA_LENGTH
+        select NEED_DMA_MAP_STATE
 config LOONGSON_MC146818
        bool
        default n
+config LEFI_FIRMWARE_INTERFACE
+        bool
 endif # MACH_LOONGSON
diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile
index 0dc0055754cd..7429994e7604 100644
--- a/arch/mips/loongson/Makefile
+++ b/arch/mips/loongson/Makefile
@@ -15,3 +15,9 @@ obj-$(CONFIG_LEMOTE_FULOONG2E)	+= fuloong-2e/
 #
 obj-$(CONFIG_LEMOTE_MACH2F)  += lemote-2f/
+#
+# All Loongson-3 family machines
+#
+obj-$(CONFIG_CPU_LOONGSON3)  += loongson-3/
diff --git a/arch/mips/loongson/Platform b/arch/mips/loongson/Platform
index 29692e5433b1..6205372b6c2d 100644
--- a/arch/mips/loongson/Platform
+++ b/arch/mips/loongson/Platform
@@ -30,3 +30,4 @@ platform-$(CONFIG_MACH_LOONGSON) += loongson/
 cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson -mno-branch-likely
 load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
 load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
+load-$(CONFIG_CPU_LOONGSON3) += 0xffffffff80200000
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
index 9e4484ccbb03..0bb9cc9dc621 100644
--- a/arch/mips/loongson/common/Makefile
+++ b/arch/mips/loongson/common/Makefile
@@ -26,3 +26,8 @@ obj-$(CONFIG_CS5536) += cs5536/
 #
 obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
+#
+# Big Memory (SWIOTLB) Support
+#
+obj-$(CONFIG_SWIOTLB) += dma-swiotlb.o
diff --git a/arch/mips/loongson/common/dma-swiotlb.c b/arch/mips/loongson/common/dma-swiotlb.c
new file mode 100644
index 000000000000..c2be01f91575
--- /dev/null
+++ b/arch/mips/loongson/common/dma-swiotlb.c
@@ -0,0 +1,136 @@
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/scatterlist.h>
+#include <linux/swiotlb.h>
+#include <linux/bootmem.h>
+#include <asm/bootinfo.h>
+#include <boot_param.h>
+#include <dma-coherence.h>
+static void *loongson_dma_alloc_coherent(struct device *dev, size_t size,
+                dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs)
+{
+        void *ret;
+        if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
+                return ret;
+        /* ignore region specifiers */
+        gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
+#ifdef CONFIG_ISA
+        if (dev == NULL)
+                gfp |= __GFP_DMA;
+        else
+#endif
+#ifdef CONFIG_ZONE_DMA
+        if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
+                gfp |= __GFP_DMA;
+        else
+#endif
+#ifdef CONFIG_ZONE_DMA32
+        if (dev->coherent_dma_mask < DMA_BIT_MASK(40))
+                gfp |= __GFP_DMA32;
+        else
+#endif
+        ;
+        gfp |= __GFP_NORETRY;
+        ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
+        mb();
+        return ret;
+}
+static void loongson_dma_free_coherent(struct device *dev, size_t size,
+                void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs)
+{
+        int order = get_order(size);
+        if (dma_release_from_coherent(dev, order, vaddr))
+                return;
+        swiotlb_free_coherent(dev, size, vaddr, dma_handle);
+}
+static dma_addr_t loongson_dma_map_page(struct device *dev, struct page *page,
+                                unsigned long offset, size_t size,
+                                enum dma_data_direction dir,
+                                struct dma_attrs *attrs)
+{
+        dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
+                                        dir, attrs);
+        mb();
+        return daddr;
+}
+static int loongson_dma_map_sg(struct device *dev, struct scatterlist *sg,
+                                int nents, enum dma_data_direction dir,
+                                struct dma_attrs *attrs)
+{
+        int r = swiotlb_map_sg_attrs(dev, sg, nents, dir, NULL);
+        mb();
+        return r;
+}
+static void loongson_dma_sync_single_for_device(struct device *dev,
+                                dma_addr_t dma_handle, size_t size,
+                                enum dma_data_direction dir)
+{
+        swiotlb_sync_single_for_device(dev, dma_handle, size, dir);
+        mb();
+}
+static void loongson_dma_sync_sg_for_device(struct device *dev,
+                                struct scatterlist *sg, int nents,
+                                enum dma_data_direction dir)
+{
+        swiotlb_sync_sg_for_device(dev, sg, nents, dir);
+        mb();
+}
+static int loongson_dma_set_mask(struct device *dev, u64 mask)
+{
+        if (mask > DMA_BIT_MASK(loongson_sysconf.dma_mask_bits)) {
+                *dev->dma_mask = DMA_BIT_MASK(loongson_sysconf.dma_mask_bits);
+                return -EIO;
+        }
+        *dev->dma_mask = mask;
+        return 0;
+}
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        return paddr;
+}
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return daddr;
+}
+static struct dma_map_ops loongson_dma_map_ops = {
+        .alloc = loongson_dma_alloc_coherent,
+        .free = loongson_dma_free_coherent,
+        .map_page = loongson_dma_map_page,
+        .unmap_page = swiotlb_unmap_page,
+        .map_sg = loongson_dma_map_sg,
+        .unmap_sg = swiotlb_unmap_sg_attrs,
+        .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+        .sync_single_for_device = loongson_dma_sync_single_for_device,
+        .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+        .sync_sg_for_device = loongson_dma_sync_sg_for_device,
+        .mapping_error = swiotlb_dma_mapping_error,
+        .dma_supported = swiotlb_dma_supported,
+        .set_dma_mask = loongson_dma_set_mask
+};
+void __init plat_swiotlb_setup(void)
+{
+        swiotlb_init(1);
+        mips_dma_map_ops = &loongson_dma_map_ops;
+}
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index 0a18fcf2d372..0c543eae49bf 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -18,29 +18,30 @@
 * option) any later version.
 */
 #include <linux/module.h>
 #include <asm/bootinfo.h>
 #include <loongson.h>
+#include <boot_param.h>
-unsigned long cpu_clock_freq;
+u32 cpu_clock_freq;
 EXPORT_SYMBOL(cpu_clock_freq);
-unsigned long memsize, highmemsize;
+struct efi_memory_map_loongson *loongson_memmap;
+struct loongson_system_configuration loongson_sysconf;
 #define parse_even_earlier(res, option, p)                              \
 do {                                                                    \
        unsigned int tmp __maybe_unused;                                \
                                                                        \
        if (strncmp(option, (char *)p, strlen(option)) == 0)            \
-                tmp = strict_strtol((char *)p + strlen(option"="), 10, &res); \
+                tmp = kstrtou32((char *)p + strlen(option"="), 10, &res); \
 } while (0)
 void __init prom_init_env(void)
 {
        /* pmon passes arguments in 32bit pointers */
-        int *_prom_envp;
-        unsigned long bus_clock;
        unsigned int processor_id;
+#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
+        int *_prom_envp;
        long l;
        /* firmware arguments are initialized in head.S */
@@ -48,7 +49,6 @@ void __init prom_init_env(void)
        l = (long)*_prom_envp;
        while (l != 0) {
-                parse_even_earlier(bus_clock, "busclock", l);
                parse_even_earlier(cpu_clock_freq, "cpuclock", l);
                parse_even_earlier(memsize, "memsize", l);
                parse_even_earlier(highmemsize, "highmemsize", l);
@@ -57,8 +57,48 @@ void __init prom_init_env(void)
        }
        if (memsize == 0)
                memsize = 256;
-        if (bus_clock == 0)
+        pr_info("memsize=%u, highmemsize=%u\n", memsize, highmemsize);
-                bus_clock = 66000000;
+#else
+        struct boot_params *boot_p;
+        struct loongson_params *loongson_p;
+        struct efi_cpuinfo_loongson *ecpu;
+        struct irq_source_routing_table *eirq_source;
+        /* firmware arguments are initialized in head.S */
+        boot_p = (struct boot_params *)fw_arg2;
+        loongson_p = &(boot_p->efi.smbios.lp);
+        ecpu = (struct efi_cpuinfo_loongson *)
+                ((u64)loongson_p + loongson_p->cpu_offset);
+        eirq_source = (struct irq_source_routing_table *)
+                ((u64)loongson_p + loongson_p->irq_offset);
+        loongson_memmap = (struct efi_memory_map_loongson *)
+                ((u64)loongson_p + loongson_p->memory_offset);
+        cpu_clock_freq = ecpu->cpu_clock_freq;
+        loongson_sysconf.cputype = ecpu->cputype;
+        loongson_sysconf.nr_cpus = ecpu->nr_cpus;
+        if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)
+                loongson_sysconf.nr_cpus = NR_CPUS;
+        loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
+        loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
+        loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
+        loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits;
+        if (loongson_sysconf.dma_mask_bits < 32 ||
+                loongson_sysconf.dma_mask_bits > 64)
+                loongson_sysconf.dma_mask_bits = 32;
+        loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;
+        loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;
+        loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend;
+        loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
+        loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios;
+        pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n",
+                loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
+                loongson_sysconf.vgabios_addr);
+#endif
        if (cpu_clock_freq == 0) {
                processor_id = (&current_cpu_data)->processor_id;
                switch (processor_id & PRID_REV_MASK) {
@@ -68,12 +108,13 @@ void __init prom_init_env(void)
                case PRID_REV_LOONGSON2F:
                        cpu_clock_freq = 797000000;
                        break;
+                case PRID_REV_LOONGSON3A:
+                        cpu_clock_freq = 900000000;
+                        break;
                default:
                        cpu_clock_freq = 100000000;
                        break;
                }
        }
+        pr_info("CpuClock = %u\n", cpu_clock_freq);
-        pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n",
-                bus_clock, cpu_clock_freq, memsize, highmemsize);
 }
diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
index ae7af1fd5d59..f37fe5413b73 100644
--- a/arch/mips/loongson/common/init.c
+++ b/arch/mips/loongson/common/init.c
@@ -9,6 +9,7 @@
 */
 #include <linux/bootmem.h>
+#include <asm/smp-ops.h>
 #include <loongson.h>
@@ -17,10 +18,6 @@ unsigned long __maybe_unused _loongson_addrwincfg_base;
 void __init prom_init(void)
 {
-        /* init base address of io space */
-        set_io_port_base((unsigned long)
-                ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
 #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
        _loongson_addrwincfg_base = (unsigned long)
                ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE);
@@ -28,10 +25,16 @@ void __init prom_init(void)
        prom_init_cmdline();
        prom_init_env();
+        /* init base address of io space */
+        set_io_port_base((unsigned long)
+                ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
        prom_init_memory();
        /*init the uart base address */
        prom_init_uart_base();
+        register_smp_ops(&loongson3_smp_ops);
 }
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c
index 4becd4f9ef2e..1a4797984b8d 100644
--- a/arch/mips/loongson/common/machtype.c
+++ b/arch/mips/loongson/common/machtype.c
@@ -27,6 +27,10 @@ static const char *system_types[] = {
        [MACH_DEXXON_GDIUM2F10]         "dexxon-gdium-2f",
        [MACH_LEMOTE_NAS]               "lemote-nas-2f",
        [MACH_LEMOTE_LL2F]              "lemote-lynloong-2f",
+        [MACH_LEMOTE_A1004]             "lemote-3a-notebook-a1004",
+        [MACH_LEMOTE_A1101]             "lemote-3a-itx-a1101",
+        [MACH_LEMOTE_A1201]             "lemote-2gq-notebook-a1201",
+        [MACH_LEMOTE_A1205]             "lemote-2gq-aio-a1205",
        [MACH_LOONGSON_END]             NULL,
 };
diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c
index 8626a42f5b94..b01d52473da8 100644
--- a/arch/mips/loongson/common/mem.c
+++ b/arch/mips/loongson/common/mem.c
@@ -11,9 +11,14 @@
 #include <asm/bootinfo.h>
 #include <loongson.h>
+#include <boot_param.h>
 #include <mem.h>
 #include <pci.h>
+#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
+u32 memsize, highmemsize;
 void __init prom_init_memory(void)
 {
        add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
@@ -49,6 +54,43 @@ void __init prom_init_memory(void)
 #endif /* !CONFIG_64BIT */
 }
+#else /* CONFIG_LEFI_FIRMWARE_INTERFACE */
+void __init prom_init_memory(void)
+{
+        int i;
+        u32 node_id;
+        u32 mem_type;
+        /* parse memory information */
+        for (i = 0; i < loongson_memmap->nr_map; i++) {
+                node_id = loongson_memmap->map[i].node_id;
+                mem_type = loongson_memmap->map[i].mem_type;
+                if (node_id == 0) {
+                        switch (mem_type) {
+                        case SYSTEM_RAM_LOW:
+                                add_memory_region(loongson_memmap->map[i].mem_start,
+                                        (u64)loongson_memmap->map[i].mem_size << 20,
+                                        BOOT_MEM_RAM);
+                                break;
+                        case SYSTEM_RAM_HIGH:
+                                add_memory_region(loongson_memmap->map[i].mem_start,
+                                        (u64)loongson_memmap->map[i].mem_size << 20,
+                                        BOOT_MEM_RAM);
+                                break;
+                        case MEM_RESERVED:
+                                add_memory_region(loongson_memmap->map[i].mem_start,
+                                        (u64)loongson_memmap->map[i].mem_size << 20,
+                                        BOOT_MEM_RESERVED);
+                                break;
+                        }
+                }
+        }
+}
+#endif /* CONFIG_LEFI_FIRMWARE_INTERFACE */
 /* override of arch/mips/mm/cache.c: __uncached_access */
 int __uncached_access(struct file *file, unsigned long addr)
 {
diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
index fa7784459721..003ab4e618b3 100644
--- a/arch/mips/loongson/common/pci.c
+++ b/arch/mips/loongson/common/pci.c
@@ -11,6 +11,7 @@
 #include <pci.h>
 #include <loongson.h>
+#include <boot_param.h>
 static struct resource loongson_pci_mem_resource = {
        .name   = "pci memory space",
@@ -82,7 +83,10 @@ static int __init pcibios_init(void)
        setup_pcimap();
        loongson_pci_controller.io_map_base = mips_io_port_base;
+#ifdef CONFIG_LEFI_FIRMWARE_INTERFACE
+        loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr;
+        loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;
+#endif
        register_pci_controller(&loongson_pci_controller);
        return 0;
diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
index 65bfbb5d06f4..a60715e11306 100644
--- a/arch/mips/loongson/common/reset.c
+++ b/arch/mips/loongson/common/reset.c
@@ -16,6 +16,7 @@
 #include <asm/reboot.h>
 #include <loongson.h>
+#include <boot_param.h>
 static inline void loongson_reboot(void)
 {
@@ -37,17 +38,37 @@ static inline void loongson_reboot(void)
 static void loongson_restart(char *command)
 {
+#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
        /* do preparation for reboot */
        mach_prepare_reboot();
        /* reboot via jumping to boot base address */
        loongson_reboot();
+#else
+        void (*fw_restart)(void) = (void *)loongson_sysconf.restart_addr;
+        fw_restart();
+        while (1) {
+                if (cpu_wait)
+                        cpu_wait();
+        }
+#endif
 }
 static void loongson_poweroff(void)
 {
+#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
        mach_prepare_shutdown();
        unreachable();
+#else
+        void (*fw_poweroff)(void) = (void *)loongson_sysconf.poweroff_addr;
+        fw_poweroff();
+        while (1) {
+                if (cpu_wait)
+                        cpu_wait();
+        }
+#endif
 }
 static void loongson_halt(void)
diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c
index 5f2b78ae97cc..bd2b7095b6dc 100644
--- a/arch/mips/loongson/common/serial.c
+++ b/arch/mips/loongson/common/serial.c
@@ -19,19 +19,19 @@
 #include <loongson.h>
 #include <machine.h>
-#define PORT(int)                       \
+#define PORT(int, clk)                  \
 {                                                               \
        .irq            = int,                                  \
-        .uartclk        = 1843200,                              \
+        .uartclk        = clk,                                  \
        .iotype         = UPIO_PORT,                            \
        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
        .regshift       = 0,                                    \
 }
-#define PORT_M(int)                             \
+#define PORT_M(int, clk)                                \
 {                                                               \
        .irq            = MIPS_CPU_IRQ_BASE + (int),            \
-        .uartclk        = 3686400,                              \
+        .uartclk        = clk,                                  \
        .iotype         = UPIO_MEM,                             \
        .membase        = (void __iomem *)NULL,                 \
        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
@@ -40,13 +40,17 @@
 static struct plat_serial8250_port uart8250_data[][2] = {
        [MACH_LOONGSON_UNKNOWN]         {},
-        [MACH_LEMOTE_FL2E]              {PORT(4), {} },
+        [MACH_LEMOTE_FL2E]              {PORT(4, 1843200), {} },
-        [MACH_LEMOTE_FL2F]              {PORT(3), {} },
+        [MACH_LEMOTE_FL2F]              {PORT(3, 1843200), {} },
-        [MACH_LEMOTE_ML2F7]             {PORT_M(3), {} },
+        [MACH_LEMOTE_ML2F7]             {PORT_M(3, 3686400), {} },
-        [MACH_LEMOTE_YL2F89]            {PORT_M(3), {} },
+        [MACH_LEMOTE_YL2F89]            {PORT_M(3, 3686400), {} },
-        [MACH_DEXXON_GDIUM2F10]         {PORT_M(3), {} },
+        [MACH_DEXXON_GDIUM2F10]         {PORT_M(3, 3686400), {} },
-        [MACH_LEMOTE_NAS]               {PORT_M(3), {} },
+        [MACH_LEMOTE_NAS]               {PORT_M(3, 3686400), {} },
-        [MACH_LEMOTE_LL2F]              {PORT(3), {} },
+        [MACH_LEMOTE_LL2F]              {PORT(3, 1843200), {} },
+        [MACH_LEMOTE_A1004]             {PORT_M(2, 33177600), {} },
+        [MACH_LEMOTE_A1101]             {PORT_M(2, 25000000), {} },
+        [MACH_LEMOTE_A1201]             {PORT_M(2, 25000000), {} },
+        [MACH_LEMOTE_A1205]             {PORT_M(2, 25000000), {} },
        [MACH_LOONGSON_END]             {},
 };
diff --git a/arch/mips/loongson/common/setup.c b/arch/mips/loongson/common/setup.c
index 8223f8acfd59..bb4ac922e47a 100644
--- a/arch/mips/loongson/common/setup.c
+++ b/arch/mips/loongson/common/setup.c
@@ -18,9 +18,6 @@
 #include <linux/screen_info.h>
 #endif
-void (*__wbflush)(void);
-EXPORT_SYMBOL(__wbflush);
 static void wbflush_loongson(void)
 {
        asm(".set\tpush\n\t"
@@ -32,10 +29,11 @@ static void wbflush_loongson(void)
            ".set mips0\n\t");
 }
+void (*__wbflush)(void) = wbflush_loongson;
+EXPORT_SYMBOL(__wbflush);
 void __init plat_mem_setup(void)
 {
-        __wbflush = wbflush_loongson;
 #ifdef CONFIG_VT
 #if defined(CONFIG_VGA_CONSOLE)
        conswitchp = &vga_con;
diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c
index e192ad021edc..1e1eeea73fde 100644
--- a/arch/mips/loongson/common/uart_base.c
+++ b/arch/mips/loongson/common/uart_base.c
@@ -35,9 +35,16 @@ void prom_init_loongson_uart_base(void)
        case MACH_DEXXON_GDIUM2F10:
        case MACH_LEMOTE_NAS:
        default:
-                /* The CPU provided serial port */
+                /* The CPU provided serial port (LPC) */
                loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8;
                break;
+        case MACH_LEMOTE_A1004:
+        case MACH_LEMOTE_A1101:
+        case MACH_LEMOTE_A1201:
+        case MACH_LEMOTE_A1205:
+                /* The CPU provided serial port (CPU) */
+                loongson_uart_base = LOONGSON_REG_BASE + 0x1e0;
+                break;
        }
        _loongson_uart_base =
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index aed32b88576c..e1f427f4f5f3 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -28,16 +28,16 @@ enum {
 };
 struct cpufreq_frequency_table loongson2_clockmod_table[] = {
-        {DC_RESV, CPUFREQ_ENTRY_INVALID},
+        {0, DC_RESV, CPUFREQ_ENTRY_INVALID},
-        {DC_ZERO, CPUFREQ_ENTRY_INVALID},
+        {0, DC_ZERO, CPUFREQ_ENTRY_INVALID},
-        {DC_25PT, 0},
+        {0, DC_25PT, 0},
-        {DC_37PT, 0},
+        {0, DC_37PT, 0},
-        {DC_50PT, 0},
+        {0, DC_50PT, 0},
-        {DC_62PT, 0},
+        {0, DC_62PT, 0},
-        {DC_75PT, 0},
+        {0, DC_75PT, 0},
-        {DC_87PT, 0},
+        {0, DC_87PT, 0},
-        {DC_DISABLE, 0},
+        {0, DC_DISABLE, 0},
-        {DC_RESV, CPUFREQ_TABLE_END},
+        {0, DC_RESV, CPUFREQ_TABLE_END},
 };
 EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
diff --git a/arch/mips/loongson/loongson-3/Makefile b/arch/mips/loongson/loongson-3/Makefile
new file mode 100644
index 000000000000..70152b252ddc
--- /dev/null
+++ b/arch/mips/loongson/loongson-3/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for Loongson-3 family machines
+#
+obj-y                   += irq.o
+obj-$(CONFIG_SMP)       += smp.o
diff --git a/arch/mips/loongson/loongson-3/irq.c b/arch/mips/loongson/loongson-3/irq.c
new file mode 100644
index 000000000000..f240828181ff
--- /dev/null
+++ b/arch/mips/loongson/loongson-3/irq.c
@@ -0,0 +1,126 @@
+#include <loongson.h>
+#include <irq.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <asm/irq_cpu.h>
+#include <asm/i8259.h>
+#include <asm/mipsregs.h>
+unsigned int ht_irq[] = {1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
+static void ht_irqdispatch(void)
+{
+        unsigned int i, irq;
+        irq = LOONGSON_HT1_INT_VECTOR(0);
+        LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
+        for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
+                if (irq & (0x1 << ht_irq[i]))
+                        do_IRQ(ht_irq[i]);
+        }
+}
+void mach_irq_dispatch(unsigned int pending)
+{
+        if (pending & CAUSEF_IP7)
+                do_IRQ(LOONGSON_TIMER_IRQ);
+#if defined(CONFIG_SMP)
+        else if (pending & CAUSEF_IP6)
+                loongson3_ipi_interrupt(NULL);
+#endif
+        else if (pending & CAUSEF_IP3)
+                ht_irqdispatch();
+        else if (pending & CAUSEF_IP2)
+                do_IRQ(LOONGSON_UART_IRQ);
+        else {
+                pr_err("%s : spurious interrupt\n", __func__);
+                spurious_interrupt();
+        }
+}
+static struct irqaction cascade_irqaction = {
+        .handler = no_action,
+        .name = "cascade",
+};
+static inline void mask_loongson_irq(struct irq_data *d)
+{
+        clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+        irq_disable_hazard();
+        /* Workaround: UART IRQ may deliver to any core */
+        if (d->irq == LOONGSON_UART_IRQ) {
+                int cpu = smp_processor_id();
+                LOONGSON_INT_ROUTER_INTENCLR = 1 << 10;
+                LOONGSON_INT_ROUTER_LPC = 0x10 + (1<<cpu);
+        }
+}
+static inline void unmask_loongson_irq(struct irq_data *d)
+{
+        /* Workaround: UART IRQ may deliver to any core */
+        if (d->irq == LOONGSON_UART_IRQ) {
+                int cpu = smp_processor_id();
+                LOONGSON_INT_ROUTER_INTENSET = 1 << 10;
+                LOONGSON_INT_ROUTER_LPC = 0x10 + (1<<cpu);
+        }
+        set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
+        irq_enable_hazard();
+}
+ /* For MIPS IRQs which shared by all cores */
+static struct irq_chip loongson_irq_chip = {
+        .name           = "Loongson",
+        .irq_ack        = mask_loongson_irq,
+        .irq_mask       = mask_loongson_irq,
+        .irq_mask_ack   = mask_loongson_irq,
+        .irq_unmask     = unmask_loongson_irq,
+        .irq_eoi        = unmask_loongson_irq,
+};
+void irq_router_init(void)
+{
+        int i;
+        /* route LPC int to cpu core0 int 0 */
+        LOONGSON_INT_ROUTER_LPC = LOONGSON_INT_CORE0_INT0;
+        /* route HT1 int0 ~ int7 to cpu core0 INT1*/
+        for (i = 0; i < 8; i++)
+                LOONGSON_INT_ROUTER_HT1(i) = LOONGSON_INT_CORE0_INT1;
+        /* enable HT1 interrupt */
+        LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
+        /* enable router interrupt intenset */
+        LOONGSON_INT_ROUTER_INTENSET =
+                LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
+}
+void __init mach_init_irq(void)
+{
+        clear_c0_status(ST0_IM | ST0_BEV);
+        irq_router_init();
+        mips_cpu_irq_init();
+        init_i8259_irqs();
+        irq_set_chip_and_handler(LOONGSON_UART_IRQ,
+                        &loongson_irq_chip, handle_level_irq);
+        /* setup HT1 irq */
+        setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
+        set_c0_status(STATUSF_IP2 | STATUSF_IP6);
+}
+#ifdef CONFIG_HOTPLUG_CPU
+void fixup_irqs(void)
+{
+        irq_cpu_offline();
+        clear_c0_status(ST0_IM);
+}
+#endif
diff --git a/arch/mips/loongson/loongson-3/smp.c b/arch/mips/loongson/loongson-3/smp.c
new file mode 100644
index 000000000000..c665fe16d4c9
--- /dev/null
+++ b/arch/mips/loongson/loongson-3/smp.c
@@ -0,0 +1,443 @@
+/*
+ * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
+ * Author: Chen Huacai, chenhc@lemote.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/init.h>
+#include <linux/cpu.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/cpufreq.h>
+#include <asm/processor.h>
+#include <asm/time.h>
+#include <asm/clock.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+#include <loongson.h>
+#include "smp.h"
+DEFINE_PER_CPU(int, cpu_state);
+DEFINE_PER_CPU(uint32_t, core0_c0count);
+/* read a 32bit value from ipi register */
+#define loongson3_ipi_read32(addr) readl(addr)
+/* read a 64bit value from ipi register */
+#define loongson3_ipi_read64(addr) readq(addr)
+/* write a 32bit value to ipi register */
+#define loongson3_ipi_write32(action, addr)     \
+        do {                                    \
+                writel(action, addr);           \
+                __wbflush();                    \
+        } while (0)
+/* write a 64bit value to ipi register */
+#define loongson3_ipi_write64(action, addr)     \
+        do {                                    \
+                writeq(action, addr);           \
+                __wbflush();                    \
+        } while (0)
+static void *ipi_set0_regs[] = {
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0),
+};
+static void *ipi_clear0_regs[] = {
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0),
+};
+static void *ipi_status0_regs[] = {
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0),
+};
+static void *ipi_en0_regs[] = {
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0),
+};
+static void *ipi_mailbox_buf[] = {
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF),
+        (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF),
+};
+/*
+ * Simple enough, just poke the appropriate ipi register
+ */
+static void loongson3_send_ipi_single(int cpu, unsigned int action)
+{
+        loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
+}
+static void
+loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
+{
+        unsigned int i;
+        for_each_cpu(i, mask)
+                loongson3_ipi_write32((u32)action, ipi_set0_regs[i]);
+}
+void loongson3_ipi_interrupt(struct pt_regs *regs)
+{
+        int i, cpu = smp_processor_id();
+        unsigned int action, c0count;
+        /* Load the ipi register to figure out what we're supposed to do */
+        action = loongson3_ipi_read32(ipi_status0_regs[cpu]);
+        /* Clear the ipi register to clear the interrupt */
+        loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu]);
+        if (action & SMP_RESCHEDULE_YOURSELF)
+                scheduler_ipi();
+        if (action & SMP_CALL_FUNCTION)
+                smp_call_function_interrupt();
+        if (action & SMP_ASK_C0COUNT) {
+                BUG_ON(cpu != 0);
+                c0count = read_c0_count();
+                for (i = 1; i < loongson_sysconf.nr_cpus; i++)
+                        per_cpu(core0_c0count, i) = c0count;
+        }
+}
+#define MAX_LOOPS 1111
+/*
+ * SMP init and finish on secondary CPUs
+ */
+static void loongson3_init_secondary(void)
+{
+        int i;
+        uint32_t initcount;
+        unsigned int cpu = smp_processor_id();
+        unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
+                             STATUSF_IP3 | STATUSF_IP2;
+        /* Set interrupt mask, but don't enable */
+        change_c0_status(ST0_IM, imask);
+        for (i = 0; i < loongson_sysconf.nr_cpus; i++)
+                loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]);
+        per_cpu(cpu_state, cpu) = CPU_ONLINE;
+        i = 0;
+        __get_cpu_var(core0_c0count) = 0;
+        loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
+        while (!__get_cpu_var(core0_c0count)) {
+                i++;
+                cpu_relax();
+        }
+        if (i > MAX_LOOPS)
+                i = MAX_LOOPS;
+        initcount = __get_cpu_var(core0_c0count) + i;
+        write_c0_count(initcount);
+}
+static void loongson3_smp_finish(void)
+{
+        write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
+        local_irq_enable();
+        loongson3_ipi_write64(0,
+                        (void *)(ipi_mailbox_buf[smp_processor_id()]+0x0));
+        pr_info("CPU#%d finished, CP0_ST=%x\n",
+                        smp_processor_id(), read_c0_status());
+}
+static void __init loongson3_smp_setup(void)
+{
+        int i, num;
+        init_cpu_possible(cpu_none_mask);
+        set_cpu_possible(0, true);
+        __cpu_number_map[0] = 0;
+        __cpu_logical_map[0] = 0;
+        /* For unified kernel, NR_CPUS is the maximum possible value,
+         * loongson_sysconf.nr_cpus is the really present value */
+        for (i = 1, num = 0; i < loongson_sysconf.nr_cpus; i++) {
+                set_cpu_possible(i, true);
+                __cpu_number_map[i] = ++num;
+                __cpu_logical_map[num] = i;
+        }
+        pr_info("Detected %i available secondary CPU(s)\n", num);
+}
+static void __init loongson3_prepare_cpus(unsigned int max_cpus)
+{
+        init_cpu_present(cpu_possible_mask);
+        per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
+}
+/*
+ * Setup the PC, SP, and GP of a secondary processor and start it runing!
+ */
+static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
+{
+        unsigned long startargs[4];
+        pr_info("Booting CPU#%d...\n", cpu);
+        /* startargs[] are initial PC, SP and GP for secondary CPU */
+        startargs[0] = (unsigned long)&smp_bootstrap;
+        startargs[1] = (unsigned long)__KSTK_TOS(idle);
+        startargs[2] = (unsigned long)task_thread_info(idle);
+        startargs[3] = 0;
+        pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
+                        cpu, startargs[0], startargs[1], startargs[2]);
+        loongson3_ipi_write64(startargs[3], (void *)(ipi_mailbox_buf[cpu]+0x18));
+        loongson3_ipi_write64(startargs[2], (void *)(ipi_mailbox_buf[cpu]+0x10));
+        loongson3_ipi_write64(startargs[1], (void *)(ipi_mailbox_buf[cpu]+0x8));
+        loongson3_ipi_write64(startargs[0], (void *)(ipi_mailbox_buf[cpu]+0x0));
+}
+/*
+ * Final cleanup after all secondaries booted
+ */
+static void __init loongson3_cpus_done(void)
+{
+}
+#ifdef CONFIG_HOTPLUG_CPU
+static int loongson3_cpu_disable(void)
+{
+        unsigned long flags;
+        unsigned int cpu = smp_processor_id();
+        if (cpu == 0)
+                return -EBUSY;
+        set_cpu_online(cpu, false);
+        cpu_clear(cpu, cpu_callin_map);
+        local_irq_save(flags);
+        fixup_irqs();
+        local_irq_restore(flags);
+        flush_cache_all();
+        local_flush_tlb_all();
+        return 0;
+}
+static void loongson3_cpu_die(unsigned int cpu)
+{
+        while (per_cpu(cpu_state, cpu) != CPU_DEAD)
+                cpu_relax();
+        mb();
+}
+/* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
+ * flush all L1 entries at first. Then, another core (usually Core 0) can
+ * safely disable the clock of the target core. loongson3_play_dead() is
+ * called via CKSEG1 (uncached and unmmaped) */
+static void loongson3_play_dead(int *state_addr)
+{
+        register int val;
+        register long cpuid, core, node, count;
+        register void *addr, *base, *initfunc;
+        __asm__ __volatile__(
+                "   .set push                     \n"
+                "   .set noreorder                \n"
+                "   li %[addr], 0x80000000        \n" /* KSEG0 */
+                "1: cache 0, 0(%[addr])           \n" /* flush L1 ICache */
+                "   cache 0, 1(%[addr])           \n"
+                "   cache 0, 2(%[addr])           \n"
+                "   cache 0, 3(%[addr])           \n"
+                "   cache 1, 0(%[addr])           \n" /* flush L1 DCache */
+                "   cache 1, 1(%[addr])           \n"
+                "   cache 1, 2(%[addr])           \n"
+                "   cache 1, 3(%[addr])           \n"
+                "   addiu %[sets], %[sets], -1    \n"
+                "   bnez  %[sets], 1b             \n"
+                "   addiu %[addr], %[addr], 0x20  \n"
+                "   li    %[val], 0x7             \n" /* *state_addr = CPU_DEAD; */
+                "   sw    %[val], (%[state_addr]) \n"
+                "   sync                          \n"
+                "   cache 21, (%[state_addr])     \n" /* flush entry of *state_addr */
+                "   .set pop                      \n"
+                : [addr] "=&r" (addr), [val] "=&r" (val)
+                : [state_addr] "r" (state_addr),
+                  [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
+        __asm__ __volatile__(
+                "   .set push                         \n"
+                "   .set noreorder                    \n"
+                "   .set mips64                       \n"
+                "   mfc0  %[cpuid], $15, 1            \n"
+                "   andi  %[cpuid], 0x3ff             \n"
+                "   dli   %[base], 0x900000003ff01000 \n"
+                "   andi  %[core], %[cpuid], 0x3      \n"
+                "   sll   %[core], 8                  \n" /* get core id */
+                "   or    %[base], %[base], %[core]   \n"
+                "   andi  %[node], %[cpuid], 0xc      \n"
+                "   dsll  %[node], 42                 \n" /* get node id */
+                "   or    %[base], %[base], %[node]   \n"
+                "1: li    %[count], 0x100             \n" /* wait for init loop */
+                "2: bnez  %[count], 2b                \n" /* limit mailbox access */
+                "   addiu %[count], -1                \n"
+                "   ld    %[initfunc], 0x20(%[base])  \n" /* get PC via mailbox */
+                "   beqz  %[initfunc], 1b             \n"
+                "   nop                               \n"
+                "   ld    $sp, 0x28(%[base])          \n" /* get SP via mailbox */
+                "   ld    $gp, 0x30(%[base])          \n" /* get GP via mailbox */
+                "   ld    $a1, 0x38(%[base])          \n"
+                "   jr    %[initfunc]                 \n" /* jump to initial PC */
+                "   nop                               \n"
+                "   .set pop                          \n"
+                : [core] "=&r" (core), [node] "=&r" (node),
+                  [base] "=&r" (base), [cpuid] "=&r" (cpuid),
+                  [count] "=&r" (count), [initfunc] "=&r" (initfunc)
+                : /* No Input */
+                : "a1");
+}
+void play_dead(void)
+{
+        int *state_addr;
+        unsigned int cpu = smp_processor_id();
+        void (*play_dead_at_ckseg1)(int *);
+        idle_task_exit();
+        play_dead_at_ckseg1 =
+                (void *)CKSEG1ADDR((unsigned long)loongson3_play_dead);
+        state_addr = &per_cpu(cpu_state, cpu);
+        mb();
+        play_dead_at_ckseg1(state_addr);
+}
+#define CPU_POST_DEAD_FROZEN    (CPU_POST_DEAD | CPU_TASKS_FROZEN)
+static int loongson3_cpu_callback(struct notifier_block *nfb,
+        unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (unsigned long)hcpu;
+        switch (action) {
+        case CPU_POST_DEAD:
+        case CPU_POST_DEAD_FROZEN:
+                pr_info("Disable clock for CPU#%d\n", cpu);
+                LOONGSON_CHIPCFG0 &= ~(1 << (12 + cpu));
+                break;
+        case CPU_UP_PREPARE:
+        case CPU_UP_PREPARE_FROZEN:
+                pr_info("Enable clock for CPU#%d\n", cpu);
+                LOONGSON_CHIPCFG0 |= 1 << (12 + cpu);
+                break;
+        }
+        return NOTIFY_OK;
+}
+static int register_loongson3_notifier(void)
+{
+        hotcpu_notifier(loongson3_cpu_callback, 0);
+        return 0;
+}
+early_initcall(register_loongson3_notifier);
+#endif
+struct plat_smp_ops loongson3_smp_ops = {
+        .send_ipi_single = loongson3_send_ipi_single,
+        .send_ipi_mask = loongson3_send_ipi_mask,
+        .init_secondary = loongson3_init_secondary,
+        .smp_finish = loongson3_smp_finish,
+        .cpus_done = loongson3_cpus_done,
+        .boot_secondary = loongson3_boot_secondary,
+        .smp_setup = loongson3_smp_setup,
+        .prepare_cpus = loongson3_prepare_cpus,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable = loongson3_cpu_disable,
+        .cpu_die = loongson3_cpu_die,
+#endif
+};
diff --git a/arch/mips/loongson/loongson-3/smp.h b/arch/mips/loongson/loongson-3/smp.h
new file mode 100644
index 000000000000..3453e8c4f2f0
--- /dev/null
+++ b/arch/mips/loongson/loongson-3/smp.h
@@ -0,0 +1,29 @@
+#ifndef __LOONGSON_SMP_H_
+#define __LOONGSON_SMP_H_
+/* for Loongson-3A smp support */
+/* 4 groups(nodes) in maximum in numa case */
+#define  SMP_CORE_GROUP0_BASE    0x900000003ff01000
+#define  SMP_CORE_GROUP1_BASE    0x900010003ff01000
+#define  SMP_CORE_GROUP2_BASE    0x900020003ff01000
+#define  SMP_CORE_GROUP3_BASE    0x900030003ff01000
+/* 4 cores in each group(node) */
+#define  SMP_CORE0_OFFSET  0x000
+#define  SMP_CORE1_OFFSET  0x100
+#define  SMP_CORE2_OFFSET  0x200
+#define  SMP_CORE3_OFFSET  0x300
+/* ipi registers offsets */
+#define  STATUS0  0x00
+#define  EN0      0x04
+#define  SET0     0x08
+#define  CLEAR0   0x0c
+#define  STATUS1  0x10
+#define  MASK1    0x14
+#define  SET1     0x18
+#define  CLEAR1   0x1c
+#define  BUF      0x20
+#endif
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 0b4e2e38294b..7b3c9acae689 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -876,20 +876,43 @@ static inline int cop1_64bit(struct pt_regs *xcp)
 #endif
 }
-#define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
+#define SIFROMREG(si, x) do {                                           \
-                        (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
+        if (cop1_64bit(xcp))                                            \
+                (si) = get_fpr32(&ctx->fpr[x], 0);                      \
-#define SITOREG(si, x)  (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
+        else                                                            \
-                        cop1_64bit(xcp) || !(x & 1) ? \
+                (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);         \
-                        ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
+} while (0)
-                        ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
+#define SITOREG(si, x) do {                                             \
-#define SIFROMHREG(si, x)       ((si) = (int)(ctx->fpr[x] >> 32))
+        if (cop1_64bit(xcp)) {                                          \
-#define SITOHREG(si, x)         (ctx->fpr[x] = \
+                unsigned i;                                             \
-                                ctx->fpr[x] << 32 >> 32 | (u64)(si) << 32)
+                set_fpr32(&ctx->fpr[x], 0, si);                         \
+                for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
-#define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
+                        set_fpr32(&ctx->fpr[x], i, 0);                  \
-#define DITOREG(di, x)  (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
+        } else {                                                        \
+                set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
+        }                                                               \
+} while (0)
+#define SIFROMHREG(si, x)       ((si) = get_fpr32(&ctx->fpr[x], 1))
+#define SITOHREG(si, x) do {                                            \
+        unsigned i;                                                     \
+        set_fpr32(&ctx->fpr[x], 1, si);                                 \
+        for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
+                set_fpr32(&ctx->fpr[x], i, 0);                          \
+} while (0)
+#define DIFROMREG(di, x) \
+        ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
+#define DITOREG(di, x) do {                                             \
+        unsigned fpr, i;                                                \
+        fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
+        set_fpr64(&ctx->fpr[fpr], 0, di);                               \
+        for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
+                set_fpr64(&ctx->fpr[fpr], i, 0);                        \
+} while (0)
 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
@@ -1960,15 +1983,18 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 #if defined(__mips64)
        case l_fmt:{
+                u64 bits;
+                DIFROMREG(bits, MIPSInst_FS(ir));
                switch (MIPSInst_FUNC(ir)) {
                case fcvts_op:
                        /* convert long to single precision real */
-                        rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
+                        rv.s = ieee754sp_flong(bits);
                        rfmt = s_fmt;
                        goto copcsr;
                case fcvtd_op:
                        /* convert long to double precision real */
-                        rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
+                        rv.d = ieee754dp_flong(bits);
                        rfmt = d_fmt;
                        goto copcsr;
                default:
diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c
index 3aeae07ed5b8..eb58a85b3157 100644
--- a/arch/mips/math-emu/kernel_linkage.c
+++ b/arch/mips/math-emu/kernel_linkage.c
@@ -40,78 +40,6 @@ void fpu_emulator_init_fpu(void)
        }
        current->thread.fpu.fcr31 = 0;
-        for (i = 0; i < 32; i++) {
+        for (i = 0; i < 32; i++)
-                current->thread.fpu.fpr[i] = SIGNALLING_NAN;
+                set_fpr64(&current->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
-        }
-}
-/*
- * Emulator context save/restore to/from a signal context
- * presumed to be on the user stack, and therefore accessed
- * with appropriate macros from uaccess.h
- */
-int fpu_emulator_save_context(struct sigcontext __user *sc)
-{
-        int i;
-        int err = 0;
-        for (i = 0; i < 32; i++) {
-                err |=
-                    __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
-        }
-        err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
-        return err;
-}
-int fpu_emulator_restore_context(struct sigcontext __user *sc)
-{
-        int i;
-        int err = 0;
-        for (i = 0; i < 32; i++) {
-                err |=
-                    __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
-        }
-        err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
-        return err;
-}
-#ifdef CONFIG_64BIT
-/*
- * This is the o32 version
- */
-int fpu_emulator_save_context32(struct sigcontext32 __user *sc)
-{
-        int i;
-        int err = 0;
-        int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
-        for (i = 0; i < 32; i += inc) {
-                err |=
-                    __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
-        }
-        err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
-        return err;
-}
-int fpu_emulator_restore_context32(struct sigcontext32 __user *sc)
-{
-        int i;
-        int err = 0;
-        int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
-        for (i = 0; i < 32; i += inc) {
-                err |=
-                    __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
-        }
-        err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
-        return err;
 }
-#endif
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index c14259edd53f..1c74a6ad072a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -57,7 +57,7 @@ static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
        preempt_enable();
 }
-#if defined(CONFIG_MIPS_CMP)
+#if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS)
 #define cpu_has_safe_index_cacheops 0
 #else
 #define cpu_has_safe_index_cacheops 1
@@ -123,6 +123,28 @@ static void r4k_blast_dcache_page_setup(void)
                r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 }
+#ifndef CONFIG_EVA
+#define r4k_blast_dcache_user_page  r4k_blast_dcache_page
+#else
+static void (*r4k_blast_dcache_user_page)(unsigned long addr);
+static void r4k_blast_dcache_user_page_setup(void)
+{
+        unsigned long  dc_lsize = cpu_dcache_line_size();
+        if (dc_lsize == 0)
+                r4k_blast_dcache_user_page = (void *)cache_noop;
+        else if (dc_lsize == 16)
+                r4k_blast_dcache_user_page = blast_dcache16_user_page;
+        else if (dc_lsize == 32)
+                r4k_blast_dcache_user_page = blast_dcache32_user_page;
+        else if (dc_lsize == 64)
+                r4k_blast_dcache_user_page = blast_dcache64_user_page;
+}
+#endif
 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 static void r4k_blast_dcache_page_indexed_setup(void)
@@ -245,6 +267,27 @@ static void r4k_blast_icache_page_setup(void)
                r4k_blast_icache_page = blast_icache64_page;
 }
+#ifndef CONFIG_EVA
+#define r4k_blast_icache_user_page  r4k_blast_icache_page
+#else
+static void (*r4k_blast_icache_user_page)(unsigned long addr);
+static void __cpuinit r4k_blast_icache_user_page_setup(void)
+{
+        unsigned long ic_lsize = cpu_icache_line_size();
+        if (ic_lsize == 0)
+                r4k_blast_icache_user_page = (void *)cache_noop;
+        else if (ic_lsize == 16)
+                r4k_blast_icache_user_page = blast_icache16_user_page;
+        else if (ic_lsize == 32)
+                r4k_blast_icache_user_page = blast_icache32_user_page;
+        else if (ic_lsize == 64)
+                r4k_blast_icache_user_page = blast_icache64_user_page;
+}
+#endif
 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
@@ -355,6 +398,7 @@ static inline void local_r4k___flush_cache_all(void * args)
 {
        switch (current_cpu_type()) {
        case CPU_LOONGSON2:
+        case CPU_LOONGSON3:
        case CPU_R4000SC:
        case CPU_R4000MC:
        case CPU_R4400SC:
@@ -519,7 +563,8 @@ static inline void local_r4k_flush_cache_page(void *args)
        }
        if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
-                r4k_blast_dcache_page(addr);
+                vaddr ? r4k_blast_dcache_page(addr) :
+                        r4k_blast_dcache_user_page(addr);
                if (exec && !cpu_icache_snoops_remote_store)
                        r4k_blast_scache_page(addr);
        }
@@ -530,7 +575,8 @@ static inline void local_r4k_flush_cache_page(void *args)
                        if (cpu_context(cpu, mm) != 0)
                                drop_mmu_context(mm, cpu);
                } else
-                        r4k_blast_icache_page(addr);
+                        vaddr ? r4k_blast_icache_page(addr) :
+                                r4k_blast_icache_user_page(addr);
        }
        if (vaddr) {
@@ -595,6 +641,17 @@ static inline void local_r4k_flush_icache_range(unsigned long start, unsigned lo
                        break;
                }
        }
+#ifdef CONFIG_EVA
+        /*
+         * Due to all possible segment mappings, there might cache aliases
+         * caused by the bootloader being in non-EVA mode, and the CPU switching
+         * to EVA during early kernel init. It's best to flush the scache
+         * to avoid having secondary cores fetching stale data and lead to
+         * kernel crashes.
+         */
+        bc_wback_inv(start, (end - start));
+        __sync();
+#endif
 }
 static inline void local_r4k_flush_icache_range_ipi(void *args)
@@ -617,7 +674,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
        instruction_hazard();
 }
-#ifdef CONFIG_DMA_NONCOHERENT
+#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 {
@@ -688,7 +745,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
        bc_inv(addr, size);
        __sync();
 }
-#endif /* CONFIG_DMA_NONCOHERENT */
+#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
 /*
 * While we're protected against bad userland addresses we don't care
@@ -1010,6 +1067,33 @@ static void probe_pcache(void)
                c->dcache.waybit = 0;
                break;
+        case CPU_LOONGSON3:
+                config1 = read_c0_config1();
+                lsize = (config1 >> 19) & 7;
+                if (lsize)
+                        c->icache.linesz = 2 << lsize;
+                else
+                        c->icache.linesz = 0;
+                c->icache.sets = 64 << ((config1 >> 22) & 7);
+                c->icache.ways = 1 + ((config1 >> 16) & 7);
+                icache_size = c->icache.sets *
+                                          c->icache.ways *
+                                          c->icache.linesz;
+                c->icache.waybit = 0;
+                lsize = (config1 >> 10) & 7;
+                if (lsize)
+                        c->dcache.linesz = 2 << lsize;
+                else
+                        c->dcache.linesz = 0;
+                c->dcache.sets = 64 << ((config1 >> 13) & 7);
+                c->dcache.ways = 1 + ((config1 >> 7) & 7);
+                dcache_size = c->dcache.sets *
+                                          c->dcache.ways *
+                                          c->dcache.linesz;
+                c->dcache.waybit = 0;
+                break;
        default:
                if (!(config & MIPS_CONF_M))
                        panic("Don't know how to probe P-caches on this cpu.");
@@ -1113,13 +1197,21 @@ static void probe_pcache(void)
        case CPU_34K:
        case CPU_74K:
        case CPU_1004K:
+        case CPU_1074K:
        case CPU_INTERAPTIV:
+        case CPU_P5600:
        case CPU_PROAPTIV:
-                if (current_cpu_type() == CPU_74K)
+        case CPU_M5150:
+                if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K))
                        alias_74k_erratum(c);
-                if ((read_c0_config7() & (1 << 16))) {
+                if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
-                        /* effectively physically indexed dcache,
+                    (c->icache.waysize > PAGE_SIZE))
-                           thus no virtual aliases. */
+                        c->icache.flags |= MIPS_CACHE_ALIASES;
+                if (read_c0_config7() & MIPS_CONF7_AR) {
+                        /*
+                         * Effectively physically indexed dcache,
+                         * thus no virtual aliases.
+                        */
                        c->dcache.flags |= MIPS_CACHE_PINDEX;
                        break;
                }
@@ -1239,6 +1331,33 @@ static void __init loongson2_sc_init(void)
        c->options |= MIPS_CPU_INCLUSIVE_CACHES;
 }
+static void __init loongson3_sc_init(void)
+{
+        struct cpuinfo_mips *c = &current_cpu_data;
+        unsigned int config2, lsize;
+        config2 = read_c0_config2();
+        lsize = (config2 >> 4) & 15;
+        if (lsize)
+                c->scache.linesz = 2 << lsize;
+        else
+                c->scache.linesz = 0;
+        c->scache.sets = 64 << ((config2 >> 8) & 15);
+        c->scache.ways = 1 + (config2 & 15);
+        scache_size = c->scache.sets *
+                                  c->scache.ways *
+                                  c->scache.linesz;
+        /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
+        scache_size *= 4;
+        c->scache.waybit = 0;
+        pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
+               scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
+        if (scache_size)
+                c->options |= MIPS_CPU_INCLUSIVE_CACHES;
+        return;
+}
 extern int r5k_sc_init(void);
 extern int rm7k_sc_init(void);
 extern int mips_sc_init(void);
@@ -1291,6 +1410,10 @@ static void setup_scache(void)
                loongson2_sc_init();
                return;
+        case CPU_LOONGSON3:
+                loongson3_sc_init();
+                return;
        case CPU_XLP:
                /* don't need to worry about L2, fully coherent */
                return;
@@ -1461,6 +1584,10 @@ void r4k_cache_init(void)
        r4k_blast_scache_page_setup();
        r4k_blast_scache_page_indexed_setup();
        r4k_blast_scache_setup();
+#ifdef CONFIG_EVA
+        r4k_blast_dcache_user_page_setup();
+        r4k_blast_icache_user_page_setup();
+#endif
        /*
         * Some MIPS32 and MIPS64 processors have physically indexed caches.
@@ -1492,7 +1619,7 @@ void r4k_cache_init(void)
        flush_icache_range      = r4k_flush_icache_range;
        local_flush_icache_range        = local_r4k_flush_icache_range;
-#if defined(CONFIG_DMA_NONCOHERENT)
+#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
        if (coherentio) {
                _dma_cache_wback_inv    = (void *)cache_noop;
                _dma_cache_wback        = (void *)cache_noop;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index fde7e56d13fe..e422b38d3113 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -49,7 +49,7 @@ EXPORT_SYMBOL_GPL(local_flush_data_cache_page);
 EXPORT_SYMBOL(flush_data_cache_page);
 EXPORT_SYMBOL(flush_icache_all);
-#ifdef CONFIG_DMA_NONCOHERENT
+#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
 /* DMA cache operations. */
 void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
@@ -58,7 +58,7 @@ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 EXPORT_SYMBOL(_dma_cache_wback_inv);
-#endif /* CONFIG_DMA_NONCOHERENT */
+#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
 /*
 * We could optimize the case where the cache argument is not BCACHE but
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 6b59617760c1..4fc74c78265a 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -422,10 +422,20 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 }
 #endif
+void (*free_init_pages_eva)(void *begin, void *end) = NULL;
 void __init_refok free_initmem(void)
 {
        prom_free_prom_memory();
-        free_initmem_default(POISON_FREE_INITMEM);
+        /*
+         * Let the platform define a specific function to free the
+         * init section since EVA may have used any possible mapping
+         * between virtual and physical addresses.
+         */
+        if (free_init_pages_eva)
+                free_init_pages_eva((void *)&__init_begin, (void *)&__init_end);
+        else
+                free_initmem_default(POISON_FREE_INITMEM);
 }
 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 7a56aee5fce7..99eb8fabab60 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -76,8 +76,10 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
        case CPU_34K:
        case CPU_74K:
        case CPU_1004K:
+        case CPU_1074K:
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
+        case CPU_P5600:
        case CPU_BMIPS5000:
                if (config2 & (1 << 12))
                        return 0;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index ae4ca2450707..eeaf50f5df2b 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -48,13 +48,14 @@ extern void build_tlb_refill_handler(void);
 #endif /* CONFIG_MIPS_MT_SMTC */
 /*
- * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
+ * LOONGSON2/3 has a 4 entry itlb which is a subset of dtlb,
- * unfortrunately, itlb is not totally transparent to software.
+ * unfortunately, itlb is not totally transparent to software.
 */
 static inline void flush_itlb(void)
 {
        switch (current_cpu_type()) {
        case CPU_LOONGSON2:
+        case CPU_LOONGSON3:
                write_c0_diag(4);
                break;
        default:
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index b234b1b5ccad..ee88367ab3ad 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -509,7 +509,10 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
                switch (current_cpu_type()) {
                case CPU_M14KC:
                case CPU_74K:
+                case CPU_1074K:
                case CPU_PROAPTIV:
+                case CPU_P5600:
+                case CPU_M5150:
                        break;
                default:
@@ -579,6 +582,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
        case CPU_BMIPS4380:
        case CPU_BMIPS5000:
        case CPU_LOONGSON2:
+        case CPU_LOONGSON3:
        case CPU_R5500:
                if (m4kc_tlbp_war())
                        uasm_i_nop(p);
@@ -621,7 +625,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
        default:
                panic("No TLB refill handler yet (CPU type: %d)",
-                      current_cpu_data.cputype);
+                      current_cpu_type());
                break;
        }
 }
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index fcebfced26d0..4f9e44d358b7 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -20,7 +20,8 @@
 #include <asm/smp-ops.h>
 #include <asm/traps.h>
 #include <asm/fw/fw.h>
-#include <asm/gcmpregs.h>
+#include <asm/mips-cm.h>
+#include <asm/mips-cpc.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/malta.h>
@@ -110,6 +111,11 @@ static void __init mips_ejtag_setup(void)
        flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 }
+phys_t mips_cpc_default_phys_base(void)
+{
+        return CPC_BASE_ADDR;
+}
 extern struct plat_smp_ops msmtc_smp_ops;
 void __init prom_init(void)
@@ -238,10 +244,23 @@ mips_pci_controller:
                          MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
                          MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
 #endif
+#ifndef CONFIG_EVA
                /* Fix up target memory mapping.  */
                MSC_READ(MSC01_PCI_BAR0, mask);
                MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
+#else
+                /*
+                 * Setup the Malta max (2GB) memory for PCI DMA in host bridge
+                 * in transparent addressing mode, starting from 0x80000000.
+                 */
+                mask = PHYS_OFFSET | (1<<3);
+                MSC_WRITE(MSC01_PCI_BAR0, mask);
+                mask = PHYS_OFFSET;
+                MSC_WRITE(MSC01_PCI_HEAD4, mask);
+                MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
+                MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
+#endif
                /* Don't handle target retries indefinitely.  */
                if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
                    MSC01_PCI_CFG_MAXRTRY_MSK)
@@ -276,10 +295,13 @@ mips_pci_controller:
        console_config();
 #endif
        /* Early detection of CMP support */
-        if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ))
+        mips_cm_probe();
-                if (!register_cmp_smp_ops())
+        mips_cpc_probe();
-                        return;
+        if (!register_cps_smp_ops())
+                return;
+        if (!register_cmp_smp_ops())
+                return;
        if (!register_vsmp_smp_ops())
                return;
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 2242181a6284..b71ee809191a 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -26,6 +26,7 @@
 #include <asm/i8259.h>
 #include <asm/irq_cpu.h>
 #include <asm/irq_regs.h>
+#include <asm/mips-cm.h>
 #include <asm/mips-boards/malta.h>
 #include <asm/mips-boards/maltaint.h>
 #include <asm/gt64120.h>
@@ -33,13 +34,10 @@
 #include <asm/mips-boards/msc01_pci.h>
 #include <asm/msc01_ic.h>
 #include <asm/gic.h>
-#include <asm/gcmpregs.h>
 #include <asm/setup.h>
 #include <asm/rtlx.h>
-int gcmp_present = -1;
 static unsigned long _msc01_biu_base;
-static unsigned long _gcmp_base;
 static unsigned int ipi_map[NR_CPUS];
 static DEFINE_RAW_SPINLOCK(mips_irq_lock);
@@ -288,10 +286,6 @@ asmlinkage void plat_irq_dispatch(void)
 #ifdef CONFIG_MIPS_MT_SMP
-#define GIC_MIPS_CPU_IPI_RESCHED_IRQ    3
-#define GIC_MIPS_CPU_IPI_CALL_IRQ       4
 #define MIPS_CPU_IPI_RESCHED_IRQ 0      /* SW int 0 for resched */
 #define C_RESCHED C_SW0
 #define MIPS_CPU_IPI_CALL_IRQ 1         /* SW int 1 for resched */
@@ -308,6 +302,13 @@ static void ipi_call_dispatch(void)
        do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
 }
+#endif /* CONFIG_MIPS_MT_SMP */
+#ifdef CONFIG_MIPS_GIC_IPI
+#define GIC_MIPS_CPU_IPI_RESCHED_IRQ    3
+#define GIC_MIPS_CPU_IPI_CALL_IRQ       4
 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
 {
 #ifdef CONFIG_MIPS_VPE_APSP_API_CMP
@@ -338,7 +339,7 @@ static struct irqaction irq_call = {
        .flags          = IRQF_PERCPU,
        .name           = "IPI_call"
 };
-#endif /* CONFIG_MIPS_MT_SMP */
+#endif /* CONFIG_MIPS_GIC_IPI */
 static int gic_resched_int_base;
 static int gic_call_int_base;
@@ -418,49 +419,7 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
 };
 #undef X
-/*
+#ifdef CONFIG_MIPS_GIC_IPI
- * GCMP needs to be detected before any SMP initialisation
- */
-int __init gcmp_probe(unsigned long addr, unsigned long size)
-{
-        if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT)  &&
-            (mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) {
-                gcmp_present = 0;
-                pr_debug("GCMP NOT present\n");
-                return gcmp_present;
-        }
-        if (gcmp_present >= 0)
-                return gcmp_present;
-        _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR,
-                GCMP_ADDRSPACE_SZ);
-        _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE,
-                MSC01_BIU_ADDRSPACE_SZ);
-        gcmp_present = ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) ==
-                GCMP_BASE_ADDR);
-        if (gcmp_present)
-                pr_debug("GCMP present\n");
-        return gcmp_present;
-}
-/* Return the number of IOCU's present */
-int __init gcmp_niocu(void)
-{
-        return gcmp_present ? ((GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >>
-                GCMP_GCB_GC_NUMIOCU_SHF) : 0;
-}
-/* Set GCMP region attributes */
-void __init gcmp_setregion(int region, unsigned long base,
-                           unsigned long mask, int type)
-{
-        GCMPGCBn(CMxBASE, region) = base;
-        GCMPGCBn(CMxMASK, region) = mask | type;
-}
-#if defined(CONFIG_MIPS_MT_SMP)
 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
 {
        int intr = baseintr + cpu;
@@ -496,8 +455,8 @@ void __init arch_init_irq(void)
        if (!cpu_has_veic)
                mips_cpu_irq_init();
-        if (gcmp_present)  {
+        if (mips_cm_present()) {
-                GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
+                write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
                gic_present = 1;
        } else {
                if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
@@ -576,7 +535,7 @@ void __init arch_init_irq(void)
        if (gic_present) {
                /* FIXME */
                int i;
-#if defined(CONFIG_MIPS_MT_SMP)
+#if defined(CONFIG_MIPS_GIC_IPI)
                gic_call_int_base = GIC_NUM_INTRS -
                        (NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids;
                gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
@@ -584,14 +543,14 @@ void __init arch_init_irq(void)
 #endif
                gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
                                ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
-                if (!gcmp_present) {
+                if (!mips_cm_present()) {
                        /* Enable the GIC */
                        i = REG(_msc01_biu_base, MSC01_SC_CFG);
                        REG(_msc01_biu_base, MSC01_SC_CFG) =
                                (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
                        pr_debug("GIC Enabled\n");
                }
-#if defined(CONFIG_MIPS_MT_SMP)
+#if defined(CONFIG_MIPS_GIC_IPI)
                /* set up ipi interrupts */
                if (cpu_has_vint) {
                        set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
@@ -708,16 +667,16 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
        /* This duplicates the handling in do_be which seems wrong */
        int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
-        if (gcmp_present) {
+        if (mips_cm_present()) {
-                unsigned long cm_error = GCMPGCB(GCMEC);
+                unsigned long cm_error = read_gcr_error_cause();
-                unsigned long cm_addr = GCMPGCB(GCMEA);
+                unsigned long cm_addr = read_gcr_error_addr();
-                unsigned long cm_other = GCMPGCB(GCMEO);
+                unsigned long cm_other = read_gcr_error_mult();
                unsigned long cause, ocause;
                char buf[256];
-                cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
+                cause = cm_error & CM_GCR_ERROR_CAUSE_ERRTYPE_MSK;
                if (cause != 0) {
-                        cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
+                        cause >>= CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
                        if (cause < 16) {
                                unsigned long cca_bits = (cm_error >> 15) & 7;
                                unsigned long tr_bits = (cm_error >> 12) & 7;
@@ -748,8 +707,8 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
                                         mcmd[cmd_bits], sport_bits);
                        }
-                        ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
+                        ocause = (cm_other & CM_GCR_ERROR_MULT_ERR2ND_MSK) >>
-                                 GCMP_GCB_GMEO_ERROR_2ND_SHF;
+                                 CM_GCR_ERROR_MULT_ERR2ND_SHF;
                        pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error,
                               causes[cause], buf);
@@ -757,7 +716,7 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
                        pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
                        /* reprime cause register */
-                        GCMPGCB(GCMEC) = 0;
+                        write_gcr_error_cause(0);
                }
        }
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 1f73d63e92a7..6d0f4ab3632d 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -24,22 +24,30 @@ static fw_memblock_t mdesc[FW_MAX_MEMBLOCKS];
 /* determined physical memory size, not overridden by command line args  */
 unsigned long physical_memsize = 0L;
-fw_memblock_t * __init fw_getmdesc(void)
+fw_memblock_t * __init fw_getmdesc(int eva)
 {
-        char *memsize_str, *ptr;
+        char *memsize_str, *ememsize_str __maybe_unused = NULL, *ptr;
-        unsigned int memsize;
+        unsigned long memsize, ememsize __maybe_unused = 0;
        static char cmdline[COMMAND_LINE_SIZE] __initdata;
-        long val;
        int tmp;
        /* otherwise look in the environment */
        memsize_str = fw_getenv("memsize");
-        if (!memsize_str) {
+        if (memsize_str)
+                tmp = kstrtol(memsize_str, 0, &memsize);
+        if (eva) {
+        /* Look for ememsize for EVA */
+                ememsize_str = fw_getenv("ememsize");
+                if (ememsize_str)
+                        tmp = kstrtol(ememsize_str, 0, &ememsize);
+        }
+        if (!memsize && !ememsize) {
                pr_warn("memsize not set in YAMON, set to default (32Mb)\n");
                physical_memsize = 0x02000000;
        } else {
-                tmp = kstrtol(memsize_str, 0, &val);
+                /* If ememsize is set, then set physical_memsize to that */
-                physical_memsize = (unsigned long)val;
+                physical_memsize = ememsize ? : memsize;
        }
 #ifdef CONFIG_CPU_BIG_ENDIAN
@@ -54,20 +62,30 @@ fw_memblock_t * __init fw_getmdesc(void)
        ptr = strstr(cmdline, "memsize=");
        if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
                ptr = strstr(ptr, " memsize=");
+        /* And now look for ememsize */
+        if (eva) {
+                ptr = strstr(cmdline, "ememsize=");
+                if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
+                        ptr = strstr(ptr, " ememsize=");
+        }
        if (ptr)
-                memsize = memparse(ptr + 8, &ptr);
+                memsize = memparse(ptr + 8 + (eva ? 1 : 0), &ptr);
        else
                memsize = physical_memsize;
+        /* Last 64K for HIGHMEM arithmetics */
+        if (memsize > 0x7fff0000)
+                memsize = 0x7fff0000;
        memset(mdesc, 0, sizeof(mdesc));
        mdesc[0].type = fw_dontuse;
-        mdesc[0].base = 0x00000000;
+        mdesc[0].base = PHYS_OFFSET;
        mdesc[0].size = 0x00001000;
        mdesc[1].type = fw_code;
-        mdesc[1].base = 0x00001000;
+        mdesc[1].base = mdesc[0].base + 0x00001000UL;
        mdesc[1].size = 0x000ef000;
        /*
@@ -78,21 +96,27 @@ fw_memblock_t * __init fw_getmdesc(void)
         * devices.
         */
        mdesc[2].type = fw_dontuse;
-        mdesc[2].base = 0x000f0000;
+        mdesc[2].base = mdesc[0].base + 0x000f0000UL;
        mdesc[2].size = 0x00010000;
        mdesc[3].type = fw_dontuse;
-        mdesc[3].base = 0x00100000;
+        mdesc[3].base = mdesc[0].base + 0x00100000UL;
        mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) -
-                mdesc[3].base;
+                0x00100000UL;
        mdesc[4].type = fw_free;
-        mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end));
+        mdesc[4].base = mdesc[0].base + CPHYSADDR(PFN_ALIGN(&_end));
-        mdesc[4].size = memsize - mdesc[4].base;
+        mdesc[4].size = memsize - CPHYSADDR(mdesc[4].base);
        return &mdesc[0];
 }
+static void free_init_pages_eva_malta(void *begin, void *end)
+{
+        free_init_pages("unused kernel", __pa_symbol((unsigned long *)begin),
+                        __pa_symbol((unsigned long *)end));
+}
 static int __init fw_memtype_classify(unsigned int type)
 {
        switch (type) {
@@ -109,7 +133,9 @@ void __init fw_meminit(void)
 {
        fw_memblock_t *p;
-        p = fw_getmdesc();
+        p = fw_getmdesc(config_enabled(CONFIG_EVA));
+        free_init_pages_eva = (config_enabled(CONFIG_EVA) ?
+                               free_init_pages_eva_malta : NULL);
        while (p->size) {
                long type;
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index c72a06936781..bf621516afff 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -26,12 +26,12 @@
 #include <linux/time.h>
 #include <asm/fw/fw.h>
+#include <asm/mips-cm.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/malta.h>
 #include <asm/mips-boards/maltaint.h>
 #include <asm/dma.h>
 #include <asm/traps.h>
-#include <asm/gcmpregs.h>
 #ifdef CONFIG_VT
 #include <linux/console.h>
 #endif
@@ -127,7 +127,7 @@ static int __init plat_enable_iocoherency(void)
                                 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
                        pr_info("Enabled Bonito IOBC coherency\n");
                }
-        } else if (gcmp_niocu() != 0) {
+        } else if (mips_cm_numiocu() != 0) {
                /* Nothing special needs to be done to enable coherency */
                pr_info("CMP IOCU detected\n");
                if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
@@ -165,7 +165,6 @@ static void __init plat_setup_iocoherency(void)
 #endif
 }
-#ifdef CONFIG_BLK_DEV_IDE
 static void __init pci_clock_check(void)
 {
        unsigned int __iomem *jmpr_p =
@@ -175,18 +174,25 @@ static void __init pci_clock_check(void)
                33, 20, 25, 30, 12, 16, 37, 10
        };
        int pciclock = pciclocks[jmpr];
-        char *argptr = fw_getcmdline();
+        char *optptr, *argptr = fw_getcmdline();
-        if (pciclock != 33 && !strstr(argptr, "idebus=")) {
+        /*
-                pr_warn("WARNING: PCI clock is %dMHz, setting idebus\n",
+         * If user passed a pci_clock= option, don't tack on another one
+         */
+        optptr = strstr(argptr, "pci_clock=");
+        if (optptr && (optptr == argptr || optptr[-1] == ' '))
+                return;
+        if (pciclock != 33) {
+                pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
                        pciclock);
                argptr += strlen(argptr);
-                sprintf(argptr, " idebus=%d", pciclock);
+                sprintf(argptr, " pci_clock=%d", pciclock);
                if (pciclock < 20 || pciclock > 66)
-                        pr_warn("WARNING: IDE timing calculations will be incorrect\n");
+                        pr_warn("WARNING: IDE timing calculations will be "
+                                "incorrect\n");
        }
 }
-#endif
 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
 static void __init screen_info_setup(void)
@@ -247,6 +253,10 @@ void __init plat_mem_setup(void)
 {
        unsigned int i;
+        if (config_enabled(CONFIG_EVA))
+                /* EVA has already been configured in mach-malta/kernel-init.h */
+                pr_info("Enhanced Virtual Addressing (EVA) activated\n");
        mips_pcibios_init();
        /* Request I/O space for devices used on the Malta board. */
@@ -268,9 +278,7 @@ void __init plat_mem_setup(void)
        plat_setup_iocoherency();
-#ifdef CONFIG_BLK_DEV_IDE
        pci_clock_check();
-#endif
 #ifdef CONFIG_BLK_DEV_FD
        fd_activate();
diff --git a/arch/mips/mti-sead3/sead3-mtd.c b/arch/mips/mti-sead3/sead3-mtd.c
index ffa35f509789..f9c890d72677 100644
--- a/arch/mips/mti-sead3/sead3-mtd.c
+++ b/arch/mips/mti-sead3/sead3-mtd.c
@@ -50,5 +50,4 @@ static int __init sead3_mtd_init(void)
        return 0;
 }
+device_initcall(sead3_mtd_init);
-module_init(sead3_mtd_init)
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 2a86e38872a7..e74732449478 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -86,8 +86,11 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
        case CPU_34K:
        case CPU_1004K:
        case CPU_74K:
+        case CPU_1074K:
        case CPU_INTERAPTIV:
        case CPU_PROAPTIV:
+        case CPU_P5600:
+        case CPU_M5150:
        case CPU_LOONGSON1:
        case CPU_SB1:
        case CPU_SB1A:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 4d94d75ec6f9..42821ae2d77e 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -372,6 +372,7 @@ static int __init mipsxx_init(void)
                op_model_mipsxx_ops.cpu_type = "mips/34K";
                break;
+        case CPU_1074K:
        case CPU_74K:
                op_model_mipsxx_ops.cpu_type = "mips/74K";
                break;
@@ -384,6 +385,14 @@ static int __init mipsxx_init(void)
                op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
                break;
+        case CPU_P5600:
+                op_model_mipsxx_ops.cpu_type = "mips/P5600";
+                break;
+        case CPU_M5150:
+                op_model_mipsxx_ops.cpu_type = "mips/M5150";
+                break;
        case CPU_5KC:
                op_model_mipsxx_ops.cpu_type = "mips/5K";
                break;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 137f2a6feb25..d61138a177cc 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_LASAT)		+= pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)       += fixup-cobalt.o
 obj-$(CONFIG_LEMOTE_FULOONG2E)  += fixup-fuloong2e.o ops-loongson2.o
 obj-$(CONFIG_LEMOTE_MACH2F)     += fixup-lemote2f.o ops-loongson2.o
+obj-$(CONFIG_LEMOTE_MACH3A)     += fixup-loongson3.o ops-loongson3.o
 obj-$(CONFIG_MIPS_MALTA)        += fixup-malta.o pci-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)    += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)  += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
new file mode 100644
index 000000000000..d708ae46d325
--- /dev/null
+++ b/arch/mips/pci/fixup-loongson3.c
@@ -0,0 +1,66 @@
+/*
+ * fixup-loongson3.c
+ *
+ * Copyright (C) 2012 Lemote, Inc.
+ * Author: Xiang Yu, xiangy@lemote.com
+ *         Chen Huacai, chenhc@lemote.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <linux/pci.h>
+#include <boot_param.h>
+static void print_fixup_info(const struct pci_dev *pdev)
+{
+        dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
+                        pdev->vendor, pdev->device, pdev->irq);
+}
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        print_fixup_info(dev);
+        return dev->irq;
+}
+static void pci_fixup_radeon(struct pci_dev *pdev)
+{
+        if (pdev->resource[PCI_ROM_RESOURCE].start)
+                return;
+        if (!loongson_sysconf.vgabios_addr)
+                return;
+        pdev->resource[PCI_ROM_RESOURCE].start =
+                loongson_sysconf.vgabios_addr;
+        pdev->resource[PCI_ROM_RESOURCE].end   =
+                loongson_sysconf.vgabios_addr + 256*1024 - 1;
+        pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_COPY;
+        dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
+                        PCI_ROM_RESOURCE, &pdev->resource[PCI_ROM_RESOURCE]);
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
+                                PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 7a0eda782e35..2f9e52a1a750 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -51,6 +51,19 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
        return 0;
 }
+static void malta_piix_func3_base_fixup(struct pci_dev *dev)
+{
+        /* Set a sane PM I/O base address */
+        pci_write_config_word(dev, PIIX4_FUNC3_PMBA, 0x1000);
+        /* Enable access to the PM I/O region */
+        pci_write_config_byte(dev, PIIX4_FUNC3_PMREGMISC,
+                              PIIX4_FUNC3_PMREGMISC_EN);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
+                        malta_piix_func3_base_fixup);
 static void malta_piix_func0_fixup(struct pci_dev *pdev)
 {
        unsigned char reg_val;
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
new file mode 100644
index 000000000000..46ed541a3ec7
--- /dev/null
+++ b/arch/mips/pci/ops-loongson3.c
@@ -0,0 +1,101 @@
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <asm/mips-boards/bonito64.h>
+#include <loongson.h>
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+#define HT1LO_PCICFG_BASE      0x1a000000
+#define HT1LO_PCICFG_BASE_TP1  0x1b000000
+static int loongson3_pci_config_access(unsigned char access_type,
+                struct pci_bus *bus, unsigned int devfn,
+                int where, u32 *data)
+{
+        unsigned char busnum = bus->number;
+        u_int64_t addr, type;
+        void *addrp;
+        int device = PCI_SLOT(devfn);
+        int function = PCI_FUNC(devfn);
+        int reg = where & ~3;
+        addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
+        if (busnum == 0) {
+                if (device > 31)
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+                addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE) | (addr & 0xffff));
+                type = 0;
+        } else {
+                addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE_TP1) | (addr));
+                type = 0x10000;
+        }
+        if (access_type == PCI_ACCESS_WRITE)
+                writel(*data, addrp);
+        else {
+                *data = readl(addrp);
+                if (*data == 0xffffffff) {
+                        *data = -1;
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+                }
+        }
+        return PCIBIOS_SUCCESSFUL;
+}
+static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
+                                 int where, int size, u32 *val)
+{
+        u32 data = 0;
+        int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
+                        bus, devfn, where, &data);
+        if (ret != PCIBIOS_SUCCESSFUL)
+                return ret;
+        if (size == 1)
+                *val = (data >> ((where & 3) << 3)) & 0xff;
+        else if (size == 2)
+                *val = (data >> ((where & 3) << 3)) & 0xffff;
+        else
+                *val = data;
+        return PCIBIOS_SUCCESSFUL;
+}
+static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
+                                  int where, int size, u32 val)
+{
+        u32 data = 0;
+        int ret;
+        if (size == 4)
+                data = val;
+        else {
+                ret = loongson3_pci_config_access(PCI_ACCESS_READ,
+                                bus, devfn, where, &data);
+                if (ret != PCIBIOS_SUCCESSFUL)
+                        return ret;
+                if (size == 1)
+                        data = (data & ~(0xff << ((where & 3) << 3))) |
+                            (val << ((where & 3) << 3));
+                else if (size == 2)
+                        data = (data & ~(0xffff << ((where & 3) << 3))) |
+                            (val << ((where & 3) << 3));
+        }
+        ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
+                        bus, devfn, where, &data);
+        return ret;
+}
+struct pci_ops loongson_pci_ops = {
+        .read = loongson3_pci_pcibios_read,
+        .write = loongson3_pci_pcibios_write
+};
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index d1faece21b6a..563d1f61d6ee 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -16,6 +16,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/vmalloc.h>
+#include <asm/dma-coherence.h>
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/tlbmisc.h>
@@ -411,17 +412,15 @@ static int alchemy_pci_probe(struct platform_device *pdev)
        }
        ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
-#ifdef CONFIG_DMA_NONCOHERENT
        /* Au1500 revisions older than AD have borked coherent PCI */
        if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
-            (read_c0_prid() < 0x01030202)) {
+            (read_c0_prid() < 0x01030202) && !coherentio) {
                val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
                val |= PCI_CONFIG_NC;
                __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
                wmb();
                dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n");
        }
-#endif
        if (pd->board_map_irq)
                ctx->board_map_irq = pd->board_map_irq;
diff --git a/arch/mips/pci/pci-malta.c b/arch/mips/pci/pci-malta.c
index f1a73890dd4f..cfbbc3e3e914 100644
--- a/arch/mips/pci/pci-malta.c
+++ b/arch/mips/pci/pci-malta.c
@@ -27,7 +27,7 @@
 #include <linux/init.h>
 #include <asm/gt64120.h>
-#include <asm/gcmpregs.h>
+#include <asm/mips-cm.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/bonito64.h>
 #include <asm/mips-boards/msc01_pci.h>
@@ -201,11 +201,11 @@ void __init mips_pcibios_init(void)
                msc_mem_resource.start = start & mask;
                msc_mem_resource.end = (start & mask) | ~mask;
                msc_controller.mem_offset = (start & mask) - (map & mask);
-#ifdef CONFIG_MIPS_CMP
+                if (mips_cm_numiocu()) {
-                if (gcmp_niocu())
+                        write_gcr_reg0_base(start);
-                        gcmp_setregion(0, start, mask,
+                        write_gcr_reg0_mask(mask |
-                                GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
+                                            CM_GCR_REGn_MASK_CMTGT_IOCU0);
-#endif
+                }
                MSC_READ(MSC01_PCI_SC2PIOBASL, start);
                MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
                MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
@@ -213,11 +213,11 @@ void __init mips_pcibios_init(void)
                msc_io_resource.end = (map & mask) | ~mask;
                msc_controller.io_offset = 0;
                ioport_resource.end = ~mask;
-#ifdef CONFIG_MIPS_CMP
+                if (mips_cm_numiocu()) {
-                if (gcmp_niocu())
+                        write_gcr_reg1_base(start);
-                        gcmp_setregion(1, start, mask,
+                        write_gcr_reg1_mask(mask |
-                                GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
+                                            CM_GCR_REGn_MASK_CMTGT_IOCU0);
-#endif
+                }
                /* If ranges overlap I/O takes precedence.  */
                start = start & mask;
                end = start | ~mask;
diff --git a/arch/mips/pmcs-msp71xx/msp_setup.c b/arch/mips/pmcs-msp71xx/msp_setup.c
index 396b2967ad85..7e980767679c 100644
--- a/arch/mips/pmcs-msp71xx/msp_setup.c
+++ b/arch/mips/pmcs-msp71xx/msp_setup.c
@@ -49,7 +49,7 @@ void msp7120_reset(void)
        /* Cache the reset code of this function */
        __asm__ __volatile__ (
                "       .set    push                            \n"
-                "       .set    mips3                           \n"
+                "       .set    arch=r4000                      \n"
                "       la      %0,startpoint                   \n"
                "       la      %1,endpoint                     \n"
                "       .set    pop                             \n"
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index 7e0277a1048f..32a7c828f073 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -43,6 +43,7 @@ LEAF(swsusp_arch_resume)
        bne t1, t3, 1b
        PTR_L t0, PBE_NEXT(t0)
        bnez t0, 0b
+        jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
        PTR_LA t0, saved_regs
        PTR_L ra, PT_R31(t0)
        PTR_L sp, PT_R29(t0)
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 1bfd1c17b3c2..4a296655f446 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -20,19 +20,13 @@ choice
        config SOC_RT305X
                bool "RT305x"
                select USB_ARCH_HAS_HCD
-                select USB_ARCH_HAS_OHCI
-                select USB_ARCH_HAS_EHCI
        config SOC_RT3883
                bool "RT3883"
-                select USB_ARCH_HAS_OHCI
-                select USB_ARCH_HAS_EHCI
                select HW_HAS_PCI
        config SOC_MT7620
                bool "MT7620"
-                select USB_ARCH_HAS_OHCI
-                select USB_ARCH_HAS_EHCI
 endchoice
diff --git a/arch/mn10300/include/asm/highmem.h b/arch/mn10300/include/asm/highmem.h
index 7c137cd8aa37..2fbbe4d920aa 100644
--- a/arch/mn10300/include/asm/highmem.h
+++ b/arch/mn10300/include/asm/highmem.h
@@ -70,7 +70,7 @@ static inline void kunmap(struct page *page)
 * be used in IRQ contexts, so in some (very limited) cases we need
 * it.
 */
-static inline unsigned long kmap_atomic(struct page *page)
+static inline void *kmap_atomic(struct page *page)
 {
        unsigned long vaddr;
        int idx, type;
@@ -89,7 +89,7 @@ static inline unsigned long kmap_atomic(struct page *page)
        set_pte(kmap_pte - idx, mk_pte(page, kmap_prot));
        local_flush_tlb_one(vaddr);
-        return vaddr;
+        return (void *)vaddr;
 }
 static inline void __kunmap_atomic(unsigned long vaddr)
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 9488209a5253..e71d712afb79 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -41,7 +41,7 @@ config RWSEM_XCHGADD_ALGORITHM
 config GENERIC_HWEIGHT
        def_bool y
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool y
 config TRACE_IRQFLAGS_SUPPORT
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index bb2a8ec440e7..1faefed32749 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -28,6 +28,7 @@ config PARISC
        select CLONE_BACKWARDS
        select TTY # Needed for pdc_cons.c
        select HAVE_DEBUG_STACKOVERFLOW
+        select HAVE_ARCH_AUDITSYSCALL
        help
          The PA-RISC microprocessor is designed by Hewlett-Packard and used
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 957bf344c0f5..e0998997943b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -90,6 +90,7 @@ config PPC
        select BINFMT_ELF
        select OF
        select OF_EARLY_FLATTREE
+        select OF_RESERVED_MEM
        select HAVE_FTRACE_MCOUNT_RECORD
        select HAVE_DYNAMIC_FTRACE
        select HAVE_FUNCTION_TRACER
@@ -130,6 +131,8 @@ config PPC
        select GENERIC_CMOS_UPDATE
        select GENERIC_TIME_VSYSCALL_OLD
        select GENERIC_CLOCKEVENTS
+        select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+        select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
        select GENERIC_STRNCPY_FROM_USER
        select GENERIC_STRNLEN_USER
        select HAVE_MOD_ARCH_SPECIFIC
@@ -141,6 +144,7 @@ config PPC
        select HAVE_DEBUG_STACKOVERFLOW
        select HAVE_IRQ_EXIT_ON_IRQ_STACK
        select ARCH_USE_CMPXCHG_LOCKREF if PPC64
+        select HAVE_ARCH_AUDITSYSCALL
 config GENERIC_CSUM
        def_bool CPU_LITTLE_ENDIAN
@@ -618,6 +622,15 @@ config CMDLINE
          some command-line options at build time by entering them here.  In
          most cases you will need to specify the root device here.
+config CMDLINE_FORCE
+        bool "Always use the default kernel command string"
+        depends on CMDLINE_BOOL
+        help
+          Always use the default kernel command string, even if the boot
+          loader passes other arguments to the kernel.
+          This is useful if you cannot or don't want to change the
+          command-line options your boot loader passes to the kernel.
 config EXTRA_TARGETS
        string "Additional default image types"
        help
@@ -736,10 +749,6 @@ config FSL_LBC
          controller.  Also contains some common code used by
          drivers for specific local bus peripherals.
-config FSL_IFC
-        bool
-        depends on FSL_SOC
 config FSL_GTM
        bool
        depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 0f4344e6fbca..4c0cedf4e2c7 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -74,6 +74,7 @@ override CROSS32AS += -mlittle-endian
 LDEMULATION     := lppc
 GNUTARGET       := powerpcle
 MULTIPLEWORD    := -mno-multiple
+KBUILD_CFLAGS_MODULE += $(call cc-option,-mno-save-toc-indirect)
 else
 ifeq ($(call cc-option-yn,-mbig-endian),y)
 override CC     += -mbig-endian
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 90e9d9548660..a1f8c7f1ec60 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -54,7 +54,7 @@ zlib       := inffast.c inflate.c inftrees.c
 zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
 zliblinuxheader := zlib.h zconf.h zutil.h
-$(addprefix $(obj)/,$(zlib) cuboot-c2k.o gunzip_util.o main.o prpmc2800.o): \
+$(addprefix $(obj)/,$(zlib) cuboot-c2k.o gunzip_util.o main.o): \
        $(addprefix $(obj)/,$(zliblinuxheader)) $(addprefix $(obj)/,$(zlibheader))
 libfdt       := fdt.c fdt_ro.c fdt_wip.c fdt_sw.c fdt_rw.c fdt_strerror.c
@@ -95,7 +95,7 @@ src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
 src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
                                        cuboot-c2k.c gamecube-head.S \
                                        gamecube.c wii-head.S wii.c holly.c \
-                                        prpmc2800.c fixed-head.S mvme5100.c
+                                        fixed-head.S mvme5100.c
 src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
 src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
 src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
@@ -204,7 +204,6 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
 image-$(CONFIG_PPC_EFIKA)               += zImage.chrp
 image-$(CONFIG_PPC_PMAC)                += zImage.pmac
 image-$(CONFIG_PPC_HOLLY)               += dtbImage.holly
-image-$(CONFIG_PPC_PRPMC2800)           += dtbImage.prpmc2800
 image-$(CONFIG_DEFAULT_UIMAGE)          += uImage
 image-$(CONFIG_EPAPR_BOOT)              += zImage.epapr
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 5a6615d0ade2..60566f9927be 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -86,6 +86,42 @@
        clockgen: global-utilities@e1000 {
                compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
+                ranges = <0x0 0xe1000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-2.0";
+                        clock-output-names = "sysclk";
+                };
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 0x4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+                };
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 0x4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+                };
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-2.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                                <&pll1 0>, <&pll1 1>, <&pll1 2>;
+                        clock-names = "pll0", "pll0-div2", "pll0-div4",
+                                "pll1", "pll1-div2", "pll1-div4";
+                        clock-output-names = "cmux0";
+                };
        };
        rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index c6e451affb05..2419731c2c54 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -64,11 +64,13 @@
                cpu0: PowerPC,e6500@0 {
                        device_type = "cpu";
                        reg = <0 1>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
        };
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 981397518fc6..cbc354b05117 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -130,6 +130,42 @@
        clockgen: global-utilities@e1000 {
                compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
+                ranges = <0x0 0xe1000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-2.0";
+                        clock-output-names = "sysclk";
+                };
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 0x4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+                };
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 0x4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+                };
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-2.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                                <&pll1 0>, <&pll1 1>, <&pll1 2>;
+                        clock-names = "pll0", "pll0-div2", "pll0-div4",
+                                "pll1", "pll1-div2", "pll1-div4";
+                        clock-output-names = "cmux0";
+                };
        };
        rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 9bc26b147900..142ac862cacf 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -64,21 +64,25 @@
                cpu0: PowerPC,e6500@0 {
                        device_type = "cpu";
                        reg = <0 1>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
                cpu2: PowerPC,e6500@4 {
                        device_type = "cpu";
                        reg = <4 5>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
                cpu3: PowerPC,e6500@6 {
                        device_type = "cpu";
                        reg = <6 7>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2>;
                };
        };
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index dc6cc5afd189..e2987a33083c 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -306,8 +306,68 @@
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
+                ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-1.0";
+                        clock-output-names = "sysclk";
+                };
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2";
+                };
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2";
+                };
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux0";
+                };
+                mux1: mux1@20 {
+                        #clock-cells = <0>;
+                        reg = <0x20 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux1";
+                };
+                mux2: mux2@40 {
+                        #clock-cells = <0>;
+                        reg = <0x40 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                };
+                mux3: mux3@60 {
+                        #clock-cells = <0>;
+                        reg = <0x60 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux3";
+                };
        };
        rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 7a2697d04549..22f3b14517de 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -81,6 +81,7 @@
                cpu0: PowerPC,e500mc@0 {
                        device_type = "cpu";
                        reg = <0>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
                cpu1: PowerPC,e500mc@1 {
                        device_type = "cpu";
                        reg = <1>;
+                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
                cpu2: PowerPC,e500mc@2 {
                        device_type = "cpu";
                        reg = <2>;
+                        clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
                cpu3: PowerPC,e500mc@3 {
                        device_type = "cpu";
                        reg = <3>;
+                        clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 3fa1e22d544a..7af6d45fd998 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -333,8 +333,69 @@
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
+                ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-1.0";
+                        clock-output-names = "sysclk";
+                };
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2";
+                };
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2";
+                };
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux0";
+                };
+                mux1: mux1@20 {
+                        #clock-cells = <0>;
+                        reg = <0x20 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux1";
+                };
+                mux2: mux2@40 {
+                        #clock-cells = <0>;
+                        reg = <0x40 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux2";
+                };
+                mux3: mux3@60 {
+                        #clock-cells = <0>;
+                        reg = <0x60 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux3";
+                };
        };
        rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index c9ca2c305cfe..468e8be8ac6f 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -82,6 +82,7 @@
                cpu0: PowerPC,e500mc@0 {
                        device_type = "cpu";
                        reg = <0>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -90,6 +91,7 @@
                cpu1: PowerPC,e500mc@1 {
                        device_type = "cpu";
                        reg = <1>;
+                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
@@ -98,6 +100,7 @@
                cpu2: PowerPC,e500mc@2 {
                        device_type = "cpu";
                        reg = <2>;
+                        clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
@@ -106,6 +109,7 @@
                cpu3: PowerPC,e500mc@3 {
                        device_type = "cpu";
                        reg = <3>;
+                        clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 34769a7eafea..2415e1f1d3fa 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -353,8 +353,121 @@
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
+                ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-1.0";
+                        clock-output-names = "sysclk";
+                };
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2";
+                };
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2";
+                };
+                pll2: pll2@840 {
+                        #clock-cells = <1>;
+                        reg = <0x840 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll2", "pll2-div2";
+                };
+                pll3: pll3@860 {
+                        #clock-cells = <1>;
+                        reg = <0x860 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll3", "pll3-div2";
+                };
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux0";
+                };
+                mux1: mux1@20 {
+                        #clock-cells = <0>;
+                        reg = <0x20 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux1";
+                };
+                mux2: mux2@40 {
+                        #clock-cells = <0>;
+                        reg = <0x40 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux2";
+                };
+                mux3: mux3@60 {
+                        #clock-cells = <0>;
+                        reg = <0x60 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux3";
+                };
+                mux4: mux4@80 {
+                        #clock-cells = <0>;
+                        reg = <0x80 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                        clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                        clock-output-names = "cmux4";
+                };
+                mux5: mux5@a0 {
+                        #clock-cells = <0>;
+                        reg = <0xa0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                        clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                        clock-output-names = "cmux5";
+                };
+                mux6: mux6@c0 {
+                        #clock-cells = <0>;
+                        reg = <0xc0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                        clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                        clock-output-names = "cmux6";
+                };
+                mux7: mux7@e0 {
+                        #clock-cells = <0>;
+                        reg = <0xe0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+                        clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
+                        clock-output-names = "cmux7";
+                };
        };
        rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index 493d9a056b5c..0040b5a5379e 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -81,6 +81,7 @@
                cpu0: PowerPC,e500mc@0 {
                        device_type = "cpu";
                        reg = <0>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
                cpu1: PowerPC,e500mc@1 {
                        device_type = "cpu";
                        reg = <1>;
+                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
                cpu2: PowerPC,e500mc@2 {
                        device_type = "cpu";
                        reg = <2>;
+                        clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
                cpu3: PowerPC,e500mc@3 {
                        device_type = "cpu";
                        reg = <3>;
+                        clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
@@ -113,6 +117,7 @@
                cpu4: PowerPC,e500mc@4 {
                        device_type = "cpu";
                        reg = <4>;
+                        clocks = <&mux4>;
                        next-level-cache = <&L2_4>;
                        L2_4: l2-cache {
                                next-level-cache = <&cpc>;
@@ -121,6 +126,7 @@
                cpu5: PowerPC,e500mc@5 {
                        device_type = "cpu";
                        reg = <5>;
+                        clocks = <&mux5>;
                        next-level-cache = <&L2_5>;
                        L2_5: l2-cache {
                                next-level-cache = <&cpc>;
@@ -129,6 +135,7 @@
                cpu6: PowerPC,e500mc@6 {
                        device_type = "cpu";
                        reg = <6>;
+                        clocks = <&mux6>;
                        next-level-cache = <&L2_6>;
                        L2_6: l2-cache {
                                next-level-cache = <&cpc>;
@@ -137,6 +144,7 @@
                cpu7: PowerPC,e500mc@7 {
                        device_type = "cpu";
                        reg = <7>;
+                        clocks = <&mux7>;
                        next-level-cache = <&L2_7>;
                        L2_7: l2-cache {
                                next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index bc3ae5a2252f..2985de4ad6be 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -338,8 +338,51 @@
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+                ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-1.0";
+                        clock-output-names = "sysclk";
+                };
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2";
+                };
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2";
+                };
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux0";
+                };
+                mux1: mux1@20 {
+                        #clock-cells = <0>;
+                        reg = <0x20 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux1";
+                };
        };
        rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index 8df47fc45ab5..fe1a2e6613b4 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -88,6 +88,7 @@
                cpu0: PowerPC,e5500@0 {
                        device_type = "cpu";
                        reg = <0>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -96,6 +97,7 @@
                cpu1: PowerPC,e5500@1 {
                        device_type = "cpu";
                        reg = <1>;
+                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index a91897f6af09..546a899efe20 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -298,8 +298,69 @@
        clockgen: global-utilities@e1000 {
                compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
+                ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
                clock-frequency = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-1.0";
+                        clock-output-names = "sysclk";
+                };
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2";
+                };
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 0x4>;
+                        compatible = "fsl,qoriq-core-pll-1.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2";
+                };
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux0";
+                };
+                mux1: mux1@20 {
+                        #clock-cells = <0>;
+                        reg = <0x20 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux1";
+                };
+                mux2: mux2@40 {
+                        #clock-cells = <0>;
+                        reg = <0x40 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux2";
+                };
+                mux3: mux3@60 {
+                        #clock-cells = <0>;
+                        reg = <0x60 0x4>;
+                        compatible = "fsl,qoriq-core-mux-1.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+                        clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+                        clock-output-names = "cmux3";
+                };
        };
        rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index 40ca943f5d1c..3674686687cb 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -81,6 +81,7 @@
                cpu0: PowerPC,e5500@0 {
                        device_type = "cpu";
                        reg = <0>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
                cpu1: PowerPC,e5500@1 {
                        device_type = "cpu";
                        reg = <1>;
+                        clocks = <&mux1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
                cpu2: PowerPC,e5500@2 {
                        device_type = "cpu";
                        reg = <2>;
+                        clocks = <&mux2>;
                        next-level-cache = <&L2_2>;
                        L2_2: l2-cache {
                                next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
                cpu3: PowerPC,e5500@3 {
                        device_type = "cpu";
                        reg = <3>;
+                        clocks = <&mux3>;
                        next-level-cache = <&L2_3>;
                        L2_3: l2-cache {
                                next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 4143a9733cd0..f99d74ff11b4 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -369,7 +369,93 @@
        clockgen: global-utilities@e1000 {
                compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
+                ranges = <0x0 0xe1000 0x1000>;
                reg = <0xe1000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                sysclk: sysclk {
+                        #clock-cells = <0>;
+                        compatible = "fsl,qoriq-sysclk-2.0";
+                        clock-output-names = "sysclk";
+                };
+                pll0: pll0@800 {
+                        #clock-cells = <1>;
+                        reg = <0x800 0x4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+                };
+                pll1: pll1@820 {
+                        #clock-cells = <1>;
+                        reg = <0x820 0x4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+                };
+                pll2: pll2@840 {
+                        #clock-cells = <1>;
+                        reg = <0x840 0x4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll2", "pll2-div2", "pll2-div4";
+                };
+                pll3: pll3@860 {
+                        #clock-cells = <1>;
+                        reg = <0x860 0x4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll3", "pll3-div2", "pll3-div4";
+                };
+                pll4: pll4@880 {
+                        #clock-cells = <1>;
+                        reg = <0x880 0x4>;
+                        compatible = "fsl,qoriq-core-pll-2.0";
+                        clocks = <&sysclk>;
+                        clock-output-names = "pll4", "pll4-div2", "pll4-div4";
+                };
+                mux0: mux0@0 {
+                        #clock-cells = <0>;
+                        reg = <0x0 0x4>;
+                        compatible = "fsl,qoriq-core-mux-2.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                                <&pll1 0>, <&pll1 1>, <&pll1 2>,
+                                <&pll2 0>, <&pll2 1>, <&pll2 2>;
+                        clock-names = "pll0", "pll0-div2", "pll0-div4",
+                                "pll1", "pll1-div2", "pll1-div4",
+                                "pll2", "pll2-div2", "pll2-div4";
+                        clock-output-names = "cmux0";
+                };
+                mux1: mux1@20 {
+                        #clock-cells = <0>;
+                        reg = <0x20 0x4>;
+                        compatible = "fsl,qoriq-core-mux-2.0";
+                        clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+                                <&pll1 0>, <&pll1 1>, <&pll1 2>,
+                                <&pll2 0>, <&pll2 1>, <&pll2 2>;
+                        clock-names = "pll0", "pll0-div2", "pll0-div4",
+                                "pll1", "pll1-div2", "pll1-div4",
+                                "pll2", "pll2-div2", "pll2-div4";
+                        clock-output-names = "cmux1";
+                };
+                mux2: mux2@40 {
+                        #clock-cells = <0>;
+                        reg = <0x40 0x4>;
+                        compatible = "fsl,qoriq-core-mux-2.0";
+                        clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
+                                <&pll4 0>, <&pll4 1>, <&pll4 2>;
+                        clock-names = "pll3", "pll3-div2", "pll3-div4",
+                                "pll4", "pll4-div2", "pll4-div4";
+                        clock-output-names = "cmux2";
+                };
        };
        rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index a93c55a88560..0b8ccc5b4a46 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -67,61 +67,73 @@
                cpu0: PowerPC,e6500@0 {
                        device_type = "cpu";
                        reg = <0 1>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
                };
                cpu1: PowerPC,e6500@2 {
                        device_type = "cpu";
                        reg = <2 3>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
                };
                cpu2: PowerPC,e6500@4 {
                        device_type = "cpu";
                        reg = <4 5>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
                };
                cpu3: PowerPC,e6500@6 {
                        device_type = "cpu";
                        reg = <6 7>;
+                        clocks = <&mux0>;
                        next-level-cache = <&L2_1>;
                };
                cpu4: PowerPC,e6500@8 {
                        device_type = "cpu";
                        reg = <8 9>;
+                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
                };
                cpu5: PowerPC,e6500@10 {
                        device_type = "cpu";
                        reg = <10 11>;
+                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
                };
                cpu6: PowerPC,e6500@12 {
                        device_type = "cpu";
                        reg = <12 13>;
+                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
                };
                cpu7: PowerPC,e6500@14 {
                        device_type = "cpu";
                        reg = <14 15>;
+                        clocks = <&mux1>;
                        next-level-cache = <&L2_2>;
                };
                cpu8: PowerPC,e6500@16 {
                        device_type = "cpu";
                        reg = <16 17>;
+                        clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
                };
                cpu9: PowerPC,e6500@18 {
                        device_type = "cpu";
                        reg = <18 19>;
+                        clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
                };
                cpu10: PowerPC,e6500@20 {
                        device_type = "cpu";
                        reg = <20 21>;
+                        clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
                };
                cpu11: PowerPC,e6500@22 {
                        device_type = "cpu";
                        reg = <22 23>;
+                        clocks = <&mux2>;
                        next-level-cache = <&L2_3>;
                };
        };
diff --git a/arch/powerpc/boot/dts/t4240qds.dts b/arch/powerpc/boot/dts/t4240qds.dts
index 63e81b010804..97683f6a2936 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -159,6 +159,48 @@
                                                interrupts = <0x1 0x1 0 0>;
                                        };
                                };
+                                i2c@2 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0x2>;
+                                        ina220@40 {
+                                                compatible = "ti,ina220";
+                                                reg = <0x40>;
+                                                shunt-resistor = <1000>;
+                                        };
+                                        ina220@41 {
+                                                compatible = "ti,ina220";
+                                                reg = <0x41>;
+                                                shunt-resistor = <1000>;
+                                        };
+                                        ina220@44 {
+                                                compatible = "ti,ina220";
+                                                reg = <0x44>;
+                                                shunt-resistor = <1000>;
+                                        };
+                                        ina220@45 {
+                                                compatible = "ti,ina220";
+                                                reg = <0x45>;
+                                                shunt-resistor = <1000>;
+                                        };
+                                        ina220@46 {
+                                                compatible = "ti,ina220";
+                                                reg = <0x46>;
+                                                shunt-resistor = <1000>;
+                                        };
+                                        ina220@47 {
+                                                compatible = "ti,ina220";
+                                                reg = <0x47>;
+                                                shunt-resistor = <1000>;
+                                        };
+                                };
                        };
                };
diff --git a/arch/powerpc/configs/40x/acadia_defconfig b/arch/powerpc/configs/40x/acadia_defconfig
index ed3bab72a834..69e06eeae6a6 100644
--- a/arch/powerpc/configs/40x/acadia_defconfig
+++ b/arch/powerpc/configs/40x/acadia_defconfig
@@ -30,7 +30,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/40x/ep405_defconfig b/arch/powerpc/configs/40x/ep405_defconfig
index 17582a3420fb..cf06d42f2c03 100644
--- a/arch/powerpc/configs/40x/ep405_defconfig
+++ b/arch/powerpc/configs/40x/ep405_defconfig
@@ -29,7 +29,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig
index f2d4be936e08..5ff338f6443f 100644
--- a/arch/powerpc/configs/40x/kilauea_defconfig
+++ b/arch/powerpc/configs/40x/kilauea_defconfig
@@ -32,7 +32,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/40x/makalu_defconfig b/arch/powerpc/configs/40x/makalu_defconfig
index 42b979355f9b..84505e3aa0fb 100644
--- a/arch/powerpc/configs/40x/makalu_defconfig
+++ b/arch/powerpc/configs/40x/makalu_defconfig
@@ -29,7 +29,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/40x/walnut_defconfig b/arch/powerpc/configs/40x/walnut_defconfig
index aa1a4cac3708..0a19f4386ee9 100644
--- a/arch/powerpc/configs/40x/walnut_defconfig
+++ b/arch/powerpc/configs/40x/walnut_defconfig
@@ -27,7 +27,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/arches_defconfig b/arch/powerpc/configs/44x/arches_defconfig
index 329f9a3b892e..44355c53cd30 100644
--- a/arch/powerpc/configs/44x/arches_defconfig
+++ b/arch/powerpc/configs/44x/arches_defconfig
@@ -31,7 +31,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/bluestone_defconfig b/arch/powerpc/configs/44x/bluestone_defconfig
index 20c8d26d7fc0..ca7f1f32f2b2 100644
--- a/arch/powerpc/configs/44x/bluestone_defconfig
+++ b/arch/powerpc/configs/44x/bluestone_defconfig
@@ -26,7 +26,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig
index d5be93e6e92d..7b8abd1b88b0 100644
--- a/arch/powerpc/configs/44x/canyonlands_defconfig
+++ b/arch/powerpc/configs/44x/canyonlands_defconfig
@@ -31,7 +31,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/ebony_defconfig b/arch/powerpc/configs/44x/ebony_defconfig
index f9269fc4ffcc..31b58b0d52e2 100644
--- a/arch/powerpc/configs/44x/ebony_defconfig
+++ b/arch/powerpc/configs/44x/ebony_defconfig
@@ -28,7 +28,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/44x/eiger_defconfig b/arch/powerpc/configs/44x/eiger_defconfig
index 9be089038fd7..faccaf65f394 100644
--- a/arch/powerpc/configs/44x/eiger_defconfig
+++ b/arch/powerpc/configs/44x/eiger_defconfig
@@ -34,7 +34,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/icon_defconfig b/arch/powerpc/configs/44x/icon_defconfig
index 82f73035a7ce..05782c145141 100644
--- a/arch/powerpc/configs/44x/icon_defconfig
+++ b/arch/powerpc/configs/44x/icon_defconfig
@@ -33,7 +33,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/iss476-smp_defconfig b/arch/powerpc/configs/44x/iss476-smp_defconfig
index ca00cf750d3e..49a1518a4e69 100644
--- a/arch/powerpc/configs/44x/iss476-smp_defconfig
+++ b/arch/powerpc/configs/44x/iss476-smp_defconfig
@@ -42,7 +42,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/44x/katmai_defconfig b/arch/powerpc/configs/44x/katmai_defconfig
index 109562c3c6be..f1137972ed41 100644
--- a/arch/powerpc/configs/44x/katmai_defconfig
+++ b/arch/powerpc/configs/44x/katmai_defconfig
@@ -29,7 +29,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/rainier_defconfig b/arch/powerpc/configs/44x/rainier_defconfig
index 21c33faf61a2..4b91a44c4c32 100644
--- a/arch/powerpc/configs/44x/rainier_defconfig
+++ b/arch/powerpc/configs/44x/rainier_defconfig
@@ -30,7 +30,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/redwood_defconfig b/arch/powerpc/configs/44x/redwood_defconfig
index 48802811da76..b7113e114a14 100644
--- a/arch/powerpc/configs/44x/redwood_defconfig
+++ b/arch/powerpc/configs/44x/redwood_defconfig
@@ -34,7 +34,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/sequoia_defconfig b/arch/powerpc/configs/44x/sequoia_defconfig
index b7a653b626db..9642d99b47f1 100644
--- a/arch/powerpc/configs/44x/sequoia_defconfig
+++ b/arch/powerpc/configs/44x/sequoia_defconfig
@@ -31,7 +31,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/44x/taishan_defconfig b/arch/powerpc/configs/44x/taishan_defconfig
index 30de97f158a4..09e3075030bf 100644
--- a/arch/powerpc/configs/44x/taishan_defconfig
+++ b/arch/powerpc/configs/44x/taishan_defconfig
@@ -29,7 +29,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_CFI=y
diff --git a/arch/powerpc/configs/44x/warp_defconfig b/arch/powerpc/configs/44x/warp_defconfig
index 105bc56f4b2b..551e50a0be5e 100644
--- a/arch/powerpc/configs/44x/warp_defconfig
+++ b/arch/powerpc/configs/44x/warp_defconfig
@@ -34,7 +34,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_STANDALONE is not set
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/52xx/cm5200_defconfig b/arch/powerpc/configs/52xx/cm5200_defconfig
index 0b88c7b30bb9..4f84a0b2fbf3 100644
--- a/arch/powerpc/configs/52xx/cm5200_defconfig
+++ b/arch/powerpc/configs/52xx/cm5200_defconfig
@@ -30,7 +30,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/52xx/motionpro_defconfig b/arch/powerpc/configs/52xx/motionpro_defconfig
index 0d13ad7e4478..c05310a913be 100644
--- a/arch/powerpc/configs/52xx/motionpro_defconfig
+++ b/arch/powerpc/configs/52xx/motionpro_defconfig
@@ -31,7 +31,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/52xx/pcm030_defconfig b/arch/powerpc/configs/52xx/pcm030_defconfig
index 430aa182fa1c..2401e2554329 100644
--- a/arch/powerpc/configs/52xx/pcm030_defconfig
+++ b/arch/powerpc/configs/52xx/pcm030_defconfig
@@ -44,7 +44,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/52xx/tqm5200_defconfig b/arch/powerpc/configs/52xx/tqm5200_defconfig
index 7af4c5bb7c63..21c841e0f482 100644
--- a/arch/powerpc/configs/52xx/tqm5200_defconfig
+++ b/arch/powerpc/configs/52xx/tqm5200_defconfig
@@ -35,7 +35,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/83xx/asp8347_defconfig b/arch/powerpc/configs/83xx/asp8347_defconfig
index d2762d9dcb8e..985f95c7280a 100644
--- a/arch/powerpc/configs/83xx/asp8347_defconfig
+++ b/arch/powerpc/configs/83xx/asp8347_defconfig
@@ -32,7 +32,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_REDBOOT_PARTS=y
 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
 CONFIG_MTD_OF_PARTS=y
diff --git a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
index e4ad2e27551a..0b73b7f9d112 100644
--- a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
@@ -30,7 +30,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
index 34ff5686be08..97ac3b993cb6 100644
--- a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
@@ -30,7 +30,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
diff --git a/arch/powerpc/configs/83xx/mpc836x_mds_defconfig b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
index 10b5c4cd0e72..05710bbfd2ef 100644
--- a/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
+++ b/arch/powerpc/configs/83xx/mpc836x_mds_defconfig
@@ -31,7 +31,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig b/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig
index 45925d701d2a..0540d673a052 100644
--- a/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig
+++ b/arch/powerpc/configs/83xx/mpc836x_rdk_defconfig
@@ -29,7 +29,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/83xx/sbc834x_defconfig b/arch/powerpc/configs/83xx/sbc834x_defconfig
index 6d6463fe06fc..a3bcda67d2d9 100644
--- a/arch/powerpc/configs/83xx/sbc834x_defconfig
+++ b/arch/powerpc/configs/83xx/sbc834x_defconfig
@@ -31,7 +31,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/85xx/ksi8560_defconfig b/arch/powerpc/configs/85xx/ksi8560_defconfig
index 8f7c1061891a..aee0d17a9551 100644
--- a/arch/powerpc/configs/85xx/ksi8560_defconfig
+++ b/arch/powerpc/configs/85xx/ksi8560_defconfig
@@ -28,7 +28,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
diff --git a/arch/powerpc/configs/85xx/ppa8548_defconfig b/arch/powerpc/configs/85xx/ppa8548_defconfig
index a11337de8aa2..e80bb9b21eac 100644
--- a/arch/powerpc/configs/85xx/ppa8548_defconfig
+++ b/arch/powerpc/configs/85xx/ppa8548_defconfig
@@ -44,7 +44,6 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_I2C=y
diff --git a/arch/powerpc/configs/85xx/socrates_defconfig b/arch/powerpc/configs/85xx/socrates_defconfig
index 77506b5d5a41..e5147488c000 100644
--- a/arch/powerpc/configs/85xx/socrates_defconfig
+++ b/arch/powerpc/configs/85xx/socrates_defconfig
@@ -32,7 +32,6 @@ CONFIG_CAN_RAW=y
 CONFIG_CAN_BCM=y
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/85xx/tqm8540_defconfig b/arch/powerpc/configs/85xx/tqm8540_defconfig
index ddcb9f37fa1f..5a800e6e38e3 100644
--- a/arch/powerpc/configs/85xx/tqm8540_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8540_defconfig
@@ -26,7 +26,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_IPV6 is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/85xx/tqm8541_defconfig b/arch/powerpc/configs/85xx/tqm8541_defconfig
index 981abd6d4b57..2d936697d69e 100644
--- a/arch/powerpc/configs/85xx/tqm8541_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8541_defconfig
@@ -26,7 +26,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_IPV6 is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/85xx/tqm8548_defconfig b/arch/powerpc/configs/85xx/tqm8548_defconfig
index 37b3d7227cdd..ce8a67e89473 100644
--- a/arch/powerpc/configs/85xx/tqm8548_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8548_defconfig
@@ -34,7 +34,6 @@ CONFIG_SYN_COOKIES=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
diff --git a/arch/powerpc/configs/85xx/tqm8555_defconfig b/arch/powerpc/configs/85xx/tqm8555_defconfig
index 3593b320c97c..a4e12971ccac 100644
--- a/arch/powerpc/configs/85xx/tqm8555_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8555_defconfig
@@ -26,7 +26,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_IPV6 is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/85xx/tqm8560_defconfig b/arch/powerpc/configs/85xx/tqm8560_defconfig
index de413acc34d6..341abe18a74d 100644
--- a/arch/powerpc/configs/85xx/tqm8560_defconfig
+++ b/arch/powerpc/configs/85xx/tqm8560_defconfig
@@ -26,7 +26,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_IPV6 is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
index 1cd6fcb368e9..07bb81df27e0 100644
--- a/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
+++ b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
@@ -65,7 +65,6 @@ CONFIG_ARPD=y
 CONFIG_IPV6=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_REDBOOT_PARTS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
index f2f6734d5f76..e5a648115ada 100644
--- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
+++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
@@ -70,7 +70,6 @@ CONFIG_NET_PKTGEN=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
index be73219212b7..8317b6010ba6 100644
--- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
@@ -70,7 +70,6 @@ CONFIG_NET_PKTGEN=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
index b3e2b1058f27..124d66f0282c 100644
--- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
@@ -123,7 +123,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
index c09598b31de1..bcbe74716689 100644
--- a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
+++ b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
@@ -41,7 +41,6 @@ CONFIG_IP_PNP_RARP=y
 CONFIG_IPV6=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/86xx/sbc8641d_defconfig b/arch/powerpc/configs/86xx/sbc8641d_defconfig
index 1a62baf855e9..1e151594c691 100644
--- a/arch/powerpc/configs/86xx/sbc8641d_defconfig
+++ b/arch/powerpc/configs/86xx/sbc8641d_defconfig
@@ -120,7 +120,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
diff --git a/arch/powerpc/configs/c2k_defconfig b/arch/powerpc/configs/c2k_defconfig
index 671a8f960afa..c69f61620908 100644
--- a/arch/powerpc/configs/c2k_defconfig
+++ b/arch/powerpc/configs/c2k_defconfig
@@ -149,7 +149,6 @@ CONFIG_BT_HCIVHCI=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=m
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 63508ddee11c..5c7fa19ae4ef 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -26,7 +26,6 @@ CONFIG_CORENET_GENERIC=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y
-CONFIG_FSL_IFC=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
@@ -60,7 +59,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/linkstation_defconfig b/arch/powerpc/configs/linkstation_defconfig
index 8a874b999867..353435256f4c 100644
--- a/arch/powerpc/configs/linkstation_defconfig
+++ b/arch/powerpc/configs/linkstation_defconfig
@@ -59,7 +59,6 @@ CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 83d3550fdb54..19f0fbe5ba4b 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -49,7 +49,6 @@ CONFIG_HIGHMEM=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_FSL_IFC=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
@@ -82,7 +81,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 4b686294feb4..062312e1fe1a 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -52,7 +52,6 @@ CONFIG_HIGHMEM=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_FSL_IFC=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
@@ -85,7 +84,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/ppc40x_defconfig b/arch/powerpc/configs/ppc40x_defconfig
index 1eb19ac45d09..52908c7897d9 100644
--- a/arch/powerpc/configs/ppc40x_defconfig
+++ b/arch/powerpc/configs/ppc40x_defconfig
@@ -33,7 +33,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/ppc44x_defconfig b/arch/powerpc/configs/ppc44x_defconfig
index 3b98d7354341..ccf66b9060a6 100644
--- a/arch/powerpc/configs/ppc44x_defconfig
+++ b/arch/powerpc/configs/ppc44x_defconfig
@@ -44,7 +44,6 @@ CONFIG_BRIDGE=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index e015896b7e5c..f26b267eb71f 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -73,74 +73,8 @@ CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 # CONFIG_IPV6 is not set
 CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=m
+# CONFIG_NETFILTER_ADVANCED is not set
-CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_BRIDGE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_BPF_JIT=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
diff --git a/arch/powerpc/configs/ppc64e_defconfig b/arch/powerpc/configs/ppc64e_defconfig
index f627fda08953..438e813dc9cb 100644
--- a/arch/powerpc/configs/ppc64e_defconfig
+++ b/arch/powerpc/configs/ppc64e_defconfig
@@ -48,74 +48,8 @@ CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 # CONFIG_IPV6 is not set
 CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=m
+# CONFIG_NETFILTER_ADVANCED is not set
-CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_BRIDGE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig
index c2353bf059fd..175a8b99c196 100644
--- a/arch/powerpc/configs/ppc6xx_defconfig
+++ b/arch/powerpc/configs/ppc6xx_defconfig
@@ -1244,7 +1244,6 @@ CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_HIGHMEM=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_VM=y
-CONFIG_DEBUG_WRITECOUNT=y
 CONFIG_DEBUG_LIST=y
 CONFIG_DEBUG_SG=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/powerpc/configs/prpmc2800_defconfig b/arch/powerpc/configs/prpmc2800_defconfig
deleted file mode 100644
index cd80fb615d34..000000000000
--- a/arch/powerpc/configs/prpmc2800_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_ALTIVEC=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_PPC_CHRP is not set
-# CONFIG_PPC_PMAC is not set
-CONFIG_EMBEDDED6xx=y
-CONFIG_PPC_PRPMC2800=y
-CONFIG_HIGHMEM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_BINFMT_MISC=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_SECCOMP is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_PROC_DEVICETREE=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_IDE=y
-CONFIG_BLK_DEV_GENERIC=y
-CONFIG_BLK_DEV_PDC202XX_NEW=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_ATA=y
-CONFIG_SATA_MV=y
-CONFIG_MACINTOSH_DRIVERS=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
-CONFIG_E100=y
-CONFIG_8139TOO=y
-# CONFIG_8139TOO_PIO is not set
-CONFIG_E1000=y
-CONFIG_MV643XX_ETH=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_MPSC=y
-CONFIG_SERIAL_MPSC_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_ORTEK=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_ZEROPLUS_FF=y
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MAX6900=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_INOTIFY=y
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_CRC_T10DIF=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig
index 139a8308070c..fdee37fab81c 100644
--- a/arch/powerpc/configs/ps3_defconfig
+++ b/arch/powerpc/configs/ps3_defconfig
@@ -174,7 +174,6 @@ CONFIG_DETECT_HUNG_TASK=y
 CONFIG_PROVE_LOCKING=y
 CONFIG_DEBUG_LOCKDEP=y
 CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_WRITECOUNT=y
 CONFIG_DEBUG_MEMORY_INIT=y
 CONFIG_DEBUG_LIST=y
 CONFIG_RCU_CPU_STALL_TIMEOUT=60
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index e9a8b4e0a0f6..a905063281cc 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -65,57 +65,8 @@ CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 # CONFIG_IPV6 is not set
 CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=m
+# CONFIG_NETFILTER_ADVANCED is not set
-CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_BRIDGE=m
-CONFIG_NF_CT_PROTO_UDPLITE=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -353,3 +304,6 @@ CONFIG_CRYPTO_DEV_NX_ENCRYPT=m
 CONFIG_VIRTUALIZATION=y
 CONFIG_KVM_BOOK3S_64=m
 CONFIG_KVM_BOOK3S_64_HV=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
diff --git a/arch/powerpc/configs/pseries_le_defconfig b/arch/powerpc/configs/pseries_le_defconfig
index 62771e0adb7c..58e3dbf43ca4 100644
--- a/arch/powerpc/configs/pseries_le_defconfig
+++ b/arch/powerpc/configs/pseries_le_defconfig
@@ -67,57 +67,8 @@ CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 # CONFIG_IPV6 is not set
 CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=m
+# CONFIG_NETFILTER_ADVANCED is not set
-CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_BRIDGE=m
-CONFIG_NF_CT_PROTO_UDPLITE=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_ULOG=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -350,3 +301,4 @@ CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_DEV_NX=y
 CONFIG_CRYPTO_DEV_NX_ENCRYPT=m
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
diff --git a/arch/powerpc/configs/storcenter_defconfig b/arch/powerpc/configs/storcenter_defconfig
index ebb2a66c99d3..ba39c785445d 100644
--- a/arch/powerpc/configs/storcenter_defconfig
+++ b/arch/powerpc/configs/storcenter_defconfig
@@ -31,7 +31,6 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/configs/tqm8xx_defconfig b/arch/powerpc/configs/tqm8xx_defconfig
index 4b6f8bf104e0..7fe277a7b422 100644
--- a/arch/powerpc/configs/tqm8xx_defconfig
+++ b/arch/powerpc/configs/tqm8xx_defconfig
@@ -41,7 +41,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
 CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
diff --git a/arch/powerpc/include/asm/archrandom.h b/arch/powerpc/include/asm/archrandom.h
index d853d163ba47..bde531103638 100644
--- a/arch/powerpc/include/asm/archrandom.h
+++ b/arch/powerpc/include/asm/archrandom.h
@@ -25,8 +25,26 @@ static inline int arch_get_random_int(unsigned int *v)
        return rc;
 }
+static inline int arch_has_random(void)
+{
+        return !!ppc_md.get_random_long;
+}
 int powernv_get_random_long(unsigned long *v);
+static inline int arch_get_random_seed_long(unsigned long *v)
+{
+        return 0;
+}
+static inline int arch_get_random_seed_int(unsigned int *v)
+{
+        return 0;
+}
+static inline int arch_has_random_seed(void)
+{
+        return 0;
+}
 #endif /* CONFIG_ARCH_RANDOM */
 #endif /* _ASM_POWERPC_ARCHRANDOM_H */
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
index a613d2c82fd9..b142b8e0ed9e 100644
--- a/arch/powerpc/include/asm/compat.h
+++ b/arch/powerpc/include/asm/compat.h
@@ -8,7 +8,11 @@
 #include <linux/sched.h>
 #define COMPAT_USER_HZ          100
+#ifdef __BIG_ENDIAN__
 #define COMPAT_UTS_MACHINE      "ppc\0\0"
+#else
+#define COMPAT_UTS_MACHINE      "ppcle\0\0"
+#endif
 typedef u32             compat_size_t;
 typedef s32             compat_ssize_t;
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 617cc767c076..bc2347774f0a 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -189,6 +189,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 #define CPU_FTR_DAWR                    LONG_ASM_CONST(0x0400000000000000)
 #define CPU_FTR_DABRX                   LONG_ASM_CONST(0x0800000000000000)
+#define CPU_FTR_PMAO_BUG                LONG_ASM_CONST(0x1000000000000000)
 #ifndef __ASSEMBLY__
@@ -445,6 +446,7 @@ extern const char *powerpc_base_platform;
            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
            CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
            CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
+#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -466,8 +468,8 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_POSSIBLE       \
            (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
-            CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL |         \
+            CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 |      \
-            CPU_FTRS_PA6T | CPU_FTR_VSX)
+            CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_VSX)
 #endif
 #else
 enum {
diff --git a/arch/powerpc/include/asm/emulated_ops.h b/arch/powerpc/include/asm/emulated_ops.h
index 4358e3002f35..f00e10e2a335 100644
--- a/arch/powerpc/include/asm/emulated_ops.h
+++ b/arch/powerpc/include/asm/emulated_ops.h
@@ -54,6 +54,7 @@ extern struct ppc_emulated {
 #ifdef CONFIG_PPC64
        struct ppc_emulated_entry mfdscr;
        struct ppc_emulated_entry mtdscr;
+        struct ppc_emulated_entry lq_stq;
 #endif
 } ppc_emulated;
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
index 51fa43e536b9..a563d9afd179 100644
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -46,9 +46,8 @@
 #define EX_CR           (1 * 8)
 #define EX_R10          (2 * 8)
 #define EX_R11          (3 * 8)
-#define EX_R13          (4 * 8)
+#define EX_R14          (4 * 8)
-#define EX_R14          (5 * 8)
+#define EX_R15          (5 * 8)
-#define EX_R15          (6 * 8)
 /*
 * The TLB miss exception uses different slots.
@@ -173,16 +172,6 @@ exc_##label##_book3e:
        ld      r9,EX_TLB_R9(r12);                                          \
        ld      r8,EX_TLB_R8(r12);                                          \
        mtlr    r16;
-#define TLB_MISS_PROLOG_STATS_BOLTED                                                \
-        mflr    r10;                                                        \
-        std     r8,PACA_EXTLB+EX_TLB_R8(r13);                               \
-        std     r9,PACA_EXTLB+EX_TLB_R9(r13);                               \
-        std     r10,PACA_EXTLB+EX_TLB_LR(r13);
-#define TLB_MISS_RESTORE_STATS_BOLTED                                               \
-        ld      r16,PACA_EXTLB+EX_TLB_LR(r13);                              \
-        ld      r9,PACA_EXTLB+EX_TLB_R9(r13);                               \
-        ld      r8,PACA_EXTLB+EX_TLB_R8(r13);                               \
-        mtlr    r16;
 #define TLB_MISS_STATS_D(name)                                              \
        addi    r9,r13,MMSTAT_DSTATS+name;                                  \
        bl      .tlb_stat_inc;
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 66830618cc19..aeaa56cd9b54 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -147,6 +147,14 @@ BEGIN_FTR_SECTION_NESTED(943)						\
 END_FTR_SECTION_NESTED(ftr,ftr,943)
 /*
+ * Set an SPR from a register if the CPU has the given feature
+ */
+#define OPT_SET_SPR(ra, spr, ftr)                                       \
+BEGIN_FTR_SECTION_NESTED(943)                                           \
+        mtspr   spr,ra;                                                 \
+END_FTR_SECTION_NESTED(ftr,ftr,943)
+/*
 * Save a register to the PACA if the CPU has the given feature
 */
 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr)                           \
diff --git a/arch/powerpc/include/asm/fadump.h b/arch/powerpc/include/asm/fadump.h
index 88dbf9659185..a6774560afe3 100644
--- a/arch/powerpc/include/asm/fadump.h
+++ b/arch/powerpc/include/asm/fadump.h
@@ -210,7 +210,6 @@ extern int is_fadump_active(void);
 extern void crash_fadump(struct pt_regs *, const char *);
 extern void fadump_cleanup(void);
-extern void vmcore_cleanup(void);
 #else   /* CONFIG_FA_DUMP */
 static inline int is_fadump_active(void) { return 0; }
 static inline void crash_fadump(struct pt_regs *regs, const char *str) { }
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
deleted file mode 100644
index f49ddb1b2273..000000000000
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ /dev/null
@@ -1,838 +0,0 @@
-/* Freescale Integrated Flash Controller
- *
- * Copyright 2011 Freescale Semiconductor, Inc
- *
- * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_FSL_IFC_H
-#define __ASM_FSL_IFC_H
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/io.h>
-#include <linux/of_platform.h>
-#include <linux/interrupt.h>
-#define FSL_IFC_BANK_COUNT 4
-/*
- * CSPR - Chip Select Property Register
- */
-#define CSPR_BA                         0xFFFF0000
-#define CSPR_BA_SHIFT                   16
-#define CSPR_PORT_SIZE                  0x00000180
-#define CSPR_PORT_SIZE_SHIFT            7
-/* Port Size 8 bit */
-#define CSPR_PORT_SIZE_8                0x00000080
-/* Port Size 16 bit */
-#define CSPR_PORT_SIZE_16               0x00000100
-/* Port Size 32 bit */
-#define CSPR_PORT_SIZE_32               0x00000180
-/* Write Protect */
-#define CSPR_WP                         0x00000040
-#define CSPR_WP_SHIFT                   6
-/* Machine Select */
-#define CSPR_MSEL                       0x00000006
-#define CSPR_MSEL_SHIFT                 1
-/* NOR */
-#define CSPR_MSEL_NOR                   0x00000000
-/* NAND */
-#define CSPR_MSEL_NAND                  0x00000002
-/* GPCM */
-#define CSPR_MSEL_GPCM                  0x00000004
-/* Bank Valid */
-#define CSPR_V                          0x00000001
-#define CSPR_V_SHIFT                    0
-/*
- * Address Mask Register
- */
-#define IFC_AMASK_MASK                  0xFFFF0000
-#define IFC_AMASK_SHIFT                 16
-#define IFC_AMASK(n)                    (IFC_AMASK_MASK << \
-                                        (__ilog2(n) - IFC_AMASK_SHIFT))
-/*
- * Chip Select Option Register IFC_NAND Machine
- */
-/* Enable ECC Encoder */
-#define CSOR_NAND_ECC_ENC_EN            0x80000000
-#define CSOR_NAND_ECC_MODE_MASK         0x30000000
-/* 4 bit correction per 520 Byte sector */
-#define CSOR_NAND_ECC_MODE_4            0x00000000
-/* 8 bit correction per 528 Byte sector */
-#define CSOR_NAND_ECC_MODE_8            0x10000000
-/* Enable ECC Decoder */
-#define CSOR_NAND_ECC_DEC_EN            0x04000000
-/* Row Address Length */
-#define CSOR_NAND_RAL_MASK              0x01800000
-#define CSOR_NAND_RAL_SHIFT             20
-#define CSOR_NAND_RAL_1                 0x00000000
-#define CSOR_NAND_RAL_2                 0x00800000
-#define CSOR_NAND_RAL_3                 0x01000000
-#define CSOR_NAND_RAL_4                 0x01800000
-/* Page Size 512b, 2k, 4k */
-#define CSOR_NAND_PGS_MASK              0x00180000
-#define CSOR_NAND_PGS_SHIFT             16
-#define CSOR_NAND_PGS_512               0x00000000
-#define CSOR_NAND_PGS_2K                0x00080000
-#define CSOR_NAND_PGS_4K                0x00100000
-#define CSOR_NAND_PGS_8K                0x00180000
-/* Spare region Size */
-#define CSOR_NAND_SPRZ_MASK             0x0000E000
-#define CSOR_NAND_SPRZ_SHIFT            13
-#define CSOR_NAND_SPRZ_16               0x00000000
-#define CSOR_NAND_SPRZ_64               0x00002000
-#define CSOR_NAND_SPRZ_128              0x00004000
-#define CSOR_NAND_SPRZ_210              0x00006000
-#define CSOR_NAND_SPRZ_218              0x00008000
-#define CSOR_NAND_SPRZ_224              0x0000A000
-#define CSOR_NAND_SPRZ_CSOR_EXT         0x0000C000
-/* Pages Per Block */
-#define CSOR_NAND_PB_MASK               0x00000700
-#define CSOR_NAND_PB_SHIFT              8
-#define CSOR_NAND_PB(n)         ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
-/* Time for Read Enable High to Output High Impedance */
-#define CSOR_NAND_TRHZ_MASK             0x0000001C
-#define CSOR_NAND_TRHZ_SHIFT            2
-#define CSOR_NAND_TRHZ_20               0x00000000
-#define CSOR_NAND_TRHZ_40               0x00000004
-#define CSOR_NAND_TRHZ_60               0x00000008
-#define CSOR_NAND_TRHZ_80               0x0000000C
-#define CSOR_NAND_TRHZ_100              0x00000010
-/* Buffer control disable */
-#define CSOR_NAND_BCTLD                 0x00000001
-/*
- * Chip Select Option Register - NOR Flash Mode
- */
-/* Enable Address shift Mode */
-#define CSOR_NOR_ADM_SHFT_MODE_EN       0x80000000
-/* Page Read Enable from NOR device */
-#define CSOR_NOR_PGRD_EN                0x10000000
-/* AVD Toggle Enable during Burst Program */
-#define CSOR_NOR_AVD_TGL_PGM_EN         0x01000000
-/* Address Data Multiplexing Shift */
-#define CSOR_NOR_ADM_MASK               0x0003E000
-#define CSOR_NOR_ADM_SHIFT_SHIFT        13
-#define CSOR_NOR_ADM_SHIFT(n)   ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
-/* Type of the NOR device hooked */
-#define CSOR_NOR_NOR_MODE_AYSNC_NOR     0x00000000
-#define CSOR_NOR_NOR_MODE_AVD_NOR       0x00000020
-/* Time for Read Enable High to Output High Impedance */
-#define CSOR_NOR_TRHZ_MASK              0x0000001C
-#define CSOR_NOR_TRHZ_SHIFT             2
-#define CSOR_NOR_TRHZ_20                0x00000000
-#define CSOR_NOR_TRHZ_40                0x00000004
-#define CSOR_NOR_TRHZ_60                0x00000008
-#define CSOR_NOR_TRHZ_80                0x0000000C
-#define CSOR_NOR_TRHZ_100               0x00000010
-/* Buffer control disable */
-#define CSOR_NOR_BCTLD                  0x00000001
-/*
- * Chip Select Option Register - GPCM Mode
- */
-/* GPCM Mode - Normal */
-#define CSOR_GPCM_GPMODE_NORMAL         0x00000000
-/* GPCM Mode - GenericASIC */
-#define CSOR_GPCM_GPMODE_ASIC           0x80000000
-/* Parity Mode odd/even */
-#define CSOR_GPCM_PARITY_EVEN           0x40000000
-/* Parity Checking enable/disable */
-#define CSOR_GPCM_PAR_EN                0x20000000
-/* GPCM Timeout Count */
-#define CSOR_GPCM_GPTO_MASK             0x0F000000
-#define CSOR_GPCM_GPTO_SHIFT            24
-#define CSOR_GPCM_GPTO(n)       ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
-/* GPCM External Access Termination mode for read access */
-#define CSOR_GPCM_RGETA_EXT             0x00080000
-/* GPCM External Access Termination mode for write access */
-#define CSOR_GPCM_WGETA_EXT             0x00040000
-/* Address Data Multiplexing Shift */
-#define CSOR_GPCM_ADM_MASK              0x0003E000
-#define CSOR_GPCM_ADM_SHIFT_SHIFT       13
-#define CSOR_GPCM_ADM_SHIFT(n)  ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
-/* Generic ASIC Parity error indication delay */
-#define CSOR_GPCM_GAPERRD_MASK          0x00000180
-#define CSOR_GPCM_GAPERRD_SHIFT         7
-#define CSOR_GPCM_GAPERRD(n)    (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
-/* Time for Read Enable High to Output High Impedance */
-#define CSOR_GPCM_TRHZ_MASK             0x0000001C
-#define CSOR_GPCM_TRHZ_20               0x00000000
-#define CSOR_GPCM_TRHZ_40               0x00000004
-#define CSOR_GPCM_TRHZ_60               0x00000008
-#define CSOR_GPCM_TRHZ_80               0x0000000C
-#define CSOR_GPCM_TRHZ_100              0x00000010
-/* Buffer control disable */
-#define CSOR_GPCM_BCTLD                 0x00000001
-/*
- * Ready Busy Status Register (RB_STAT)
- */
-/* CSn is READY */
-#define IFC_RB_STAT_READY_CS0           0x80000000
-#define IFC_RB_STAT_READY_CS1           0x40000000
-#define IFC_RB_STAT_READY_CS2           0x20000000
-#define IFC_RB_STAT_READY_CS3           0x10000000
-/*
- * General Control Register (GCR)
- */
-#define IFC_GCR_MASK                    0x8000F800
-/* reset all IFC hardware */
-#define IFC_GCR_SOFT_RST_ALL            0x80000000
-/* Turnaroud Time of external buffer */
-#define IFC_GCR_TBCTL_TRN_TIME          0x0000F800
-#define IFC_GCR_TBCTL_TRN_TIME_SHIFT    11
-/*
- * Common Event and Error Status Register (CM_EVTER_STAT)
- */
-/* Chip select error */
-#define IFC_CM_EVTER_STAT_CSER          0x80000000
-/*
- * Common Event and Error Enable Register (CM_EVTER_EN)
- */
-/* Chip select error checking enable */
-#define IFC_CM_EVTER_EN_CSEREN          0x80000000
-/*
- * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
- */
-/* Chip select error interrupt enable */
-#define IFC_CM_EVTER_INTR_EN_CSERIREN   0x80000000
-/*
- * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
- */
-/* transaction type of error Read/Write */
-#define IFC_CM_ERATTR0_ERTYP_READ       0x80000000
-#define IFC_CM_ERATTR0_ERAID            0x0FF00000
-#define IFC_CM_ERATTR0_ERAID_SHIFT      20
-#define IFC_CM_ERATTR0_ESRCID           0x0000FF00
-#define IFC_CM_ERATTR0_ESRCID_SHIFT     8
-/*
- * Clock Control Register (CCR)
- */
-#define IFC_CCR_MASK                    0x0F0F8800
-/* Clock division ratio */
-#define IFC_CCR_CLK_DIV_MASK            0x0F000000
-#define IFC_CCR_CLK_DIV_SHIFT           24
-#define IFC_CCR_CLK_DIV(n)              ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
-/* IFC Clock Delay */
-#define IFC_CCR_CLK_DLY_MASK            0x000F0000
-#define IFC_CCR_CLK_DLY_SHIFT           16
-#define IFC_CCR_CLK_DLY(n)              ((n) << IFC_CCR_CLK_DLY_SHIFT)
-/* Invert IFC clock before sending out */
-#define IFC_CCR_INV_CLK_EN              0x00008000
-/* Fedback IFC Clock */
-#define IFC_CCR_FB_IFC_CLK_SEL          0x00000800
-/*
- * Clock Status Register (CSR)
- */
-/* Clk is stable */
-#define IFC_CSR_CLK_STAT_STABLE         0x80000000
-/*
- * IFC_NAND Machine Specific Registers
- */
-/*
- * NAND Configuration Register (NCFGR)
- */
-/* Auto Boot Mode */
-#define IFC_NAND_NCFGR_BOOT             0x80000000
-/* Addressing Mode-ROW0+n/COL0 */
-#define IFC_NAND_NCFGR_ADDR_MODE_RC0    0x00000000
-/* Addressing Mode-ROW0+n/COL0+n */
-#define IFC_NAND_NCFGR_ADDR_MODE_RC1    0x00400000
-/* Number of loop iterations of FIR sequences for multi page operations */
-#define IFC_NAND_NCFGR_NUM_LOOP_MASK    0x0000F000
-#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT   12
-#define IFC_NAND_NCFGR_NUM_LOOP(n)      ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
-/* Number of wait cycles */
-#define IFC_NAND_NCFGR_NUM_WAIT_MASK    0x000000FF
-#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT   0
-/*
- * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
- */
-/* General purpose FCM flash command bytes CMD0-CMD7 */
-#define IFC_NAND_FCR0_CMD0              0xFF000000
-#define IFC_NAND_FCR0_CMD0_SHIFT        24
-#define IFC_NAND_FCR0_CMD1              0x00FF0000
-#define IFC_NAND_FCR0_CMD1_SHIFT        16
-#define IFC_NAND_FCR0_CMD2              0x0000FF00
-#define IFC_NAND_FCR0_CMD2_SHIFT        8
-#define IFC_NAND_FCR0_CMD3              0x000000FF
-#define IFC_NAND_FCR0_CMD3_SHIFT        0
-#define IFC_NAND_FCR1_CMD4              0xFF000000
-#define IFC_NAND_FCR1_CMD4_SHIFT        24
-#define IFC_NAND_FCR1_CMD5              0x00FF0000
-#define IFC_NAND_FCR1_CMD5_SHIFT        16
-#define IFC_NAND_FCR1_CMD6              0x0000FF00
-#define IFC_NAND_FCR1_CMD6_SHIFT        8
-#define IFC_NAND_FCR1_CMD7              0x000000FF
-#define IFC_NAND_FCR1_CMD7_SHIFT        0
-/*
- * Flash ROW and COL Address Register (ROWn, COLn)
- */
-/* Main/spare region locator */
-#define IFC_NAND_COL_MS                 0x80000000
-/* Column Address */
-#define IFC_NAND_COL_CA_MASK            0x00000FFF
-/*
- * NAND Flash Byte Count Register (NAND_BC)
- */
-/* Byte Count for read/Write */
-#define IFC_NAND_BC                     0x000001FF
-/*
- * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
- */
-/* NAND Machine specific opcodes OP0-OP14*/
-#define IFC_NAND_FIR0_OP0               0xFC000000
-#define IFC_NAND_FIR0_OP0_SHIFT         26
-#define IFC_NAND_FIR0_OP1               0x03F00000
-#define IFC_NAND_FIR0_OP1_SHIFT         20
-#define IFC_NAND_FIR0_OP2               0x000FC000
-#define IFC_NAND_FIR0_OP2_SHIFT         14
-#define IFC_NAND_FIR0_OP3               0x00003F00
-#define IFC_NAND_FIR0_OP3_SHIFT         8
-#define IFC_NAND_FIR0_OP4               0x000000FC
-#define IFC_NAND_FIR0_OP4_SHIFT         2
-#define IFC_NAND_FIR1_OP5               0xFC000000
-#define IFC_NAND_FIR1_OP5_SHIFT         26
-#define IFC_NAND_FIR1_OP6               0x03F00000
-#define IFC_NAND_FIR1_OP6_SHIFT         20
-#define IFC_NAND_FIR1_OP7               0x000FC000
-#define IFC_NAND_FIR1_OP7_SHIFT         14
-#define IFC_NAND_FIR1_OP8               0x00003F00
-#define IFC_NAND_FIR1_OP8_SHIFT         8
-#define IFC_NAND_FIR1_OP9               0x000000FC
-#define IFC_NAND_FIR1_OP9_SHIFT         2
-#define IFC_NAND_FIR2_OP10              0xFC000000
-#define IFC_NAND_FIR2_OP10_SHIFT        26
-#define IFC_NAND_FIR2_OP11              0x03F00000
-#define IFC_NAND_FIR2_OP11_SHIFT        20
-#define IFC_NAND_FIR2_OP12              0x000FC000
-#define IFC_NAND_FIR2_OP12_SHIFT        14
-#define IFC_NAND_FIR2_OP13              0x00003F00
-#define IFC_NAND_FIR2_OP13_SHIFT        8
-#define IFC_NAND_FIR2_OP14              0x000000FC
-#define IFC_NAND_FIR2_OP14_SHIFT        2
-/*
- * Instruction opcodes to be programmed
- * in FIR registers- 6bits
- */
-enum ifc_nand_fir_opcodes {
-        IFC_FIR_OP_NOP,
-        IFC_FIR_OP_CA0,
-        IFC_FIR_OP_CA1,
-        IFC_FIR_OP_CA2,
-        IFC_FIR_OP_CA3,
-        IFC_FIR_OP_RA0,
-        IFC_FIR_OP_RA1,
-        IFC_FIR_OP_RA2,
-        IFC_FIR_OP_RA3,
-        IFC_FIR_OP_CMD0,
-        IFC_FIR_OP_CMD1,
-        IFC_FIR_OP_CMD2,
-        IFC_FIR_OP_CMD3,
-        IFC_FIR_OP_CMD4,
-        IFC_FIR_OP_CMD5,
-        IFC_FIR_OP_CMD6,
-        IFC_FIR_OP_CMD7,
-        IFC_FIR_OP_CW0,
-        IFC_FIR_OP_CW1,
-        IFC_FIR_OP_CW2,
-        IFC_FIR_OP_CW3,
-        IFC_FIR_OP_CW4,
-        IFC_FIR_OP_CW5,
-        IFC_FIR_OP_CW6,
-        IFC_FIR_OP_CW7,
-        IFC_FIR_OP_WBCD,
-        IFC_FIR_OP_RBCD,
-        IFC_FIR_OP_BTRD,
-        IFC_FIR_OP_RDSTAT,
-        IFC_FIR_OP_NWAIT,
-        IFC_FIR_OP_WFR,
-        IFC_FIR_OP_SBRD,
-        IFC_FIR_OP_UA,
-        IFC_FIR_OP_RB,
-};
-/*
- * NAND Chip Select Register (NAND_CSEL)
- */
-#define IFC_NAND_CSEL                   0x0C000000
-#define IFC_NAND_CSEL_SHIFT             26
-#define IFC_NAND_CSEL_CS0               0x00000000
-#define IFC_NAND_CSEL_CS1               0x04000000
-#define IFC_NAND_CSEL_CS2               0x08000000
-#define IFC_NAND_CSEL_CS3               0x0C000000
-/*
- * NAND Operation Sequence Start (NANDSEQ_STRT)
- */
-/* NAND Flash Operation Start */
-#define IFC_NAND_SEQ_STRT_FIR_STRT      0x80000000
-/* Automatic Erase */
-#define IFC_NAND_SEQ_STRT_AUTO_ERS      0x00800000
-/* Automatic Program */
-#define IFC_NAND_SEQ_STRT_AUTO_PGM      0x00100000
-/* Automatic Copyback */
-#define IFC_NAND_SEQ_STRT_AUTO_CPB      0x00020000
-/* Automatic Read Operation */
-#define IFC_NAND_SEQ_STRT_AUTO_RD       0x00004000
-/* Automatic Status Read */
-#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD  0x00000800
-/*
- * NAND Event and Error Status Register (NAND_EVTER_STAT)
- */
-/* Operation Complete */
-#define IFC_NAND_EVTER_STAT_OPC         0x80000000
-/* Flash Timeout Error */
-#define IFC_NAND_EVTER_STAT_FTOER       0x08000000
-/* Write Protect Error */
-#define IFC_NAND_EVTER_STAT_WPER        0x04000000
-/* ECC Error */
-#define IFC_NAND_EVTER_STAT_ECCER       0x02000000
-/* RCW Load Done */
-#define IFC_NAND_EVTER_STAT_RCW_DN      0x00008000
-/* Boot Loadr Done */
-#define IFC_NAND_EVTER_STAT_BOOT_DN     0x00004000
-/* Bad Block Indicator search select */
-#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
-/*
- * NAND Flash Page Read Completion Event Status Register
- * (PGRDCMPL_EVT_STAT)
- */
-#define PGRDCMPL_EVT_STAT_MASK          0xFFFF0000
-/* Small Page 0-15 Done */
-#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
-/* Large Page(2K) 0-3 Done */
-#define PGRDCMPL_EVT_STAT_LP_2K(n)      (0xF << (28 - (n)*4))
-/* Large Page(4K) 0-1 Done */
-#define PGRDCMPL_EVT_STAT_LP_4K(n)      (0xFF << (24 - (n)*8))
-/*
- * NAND Event and Error Enable Register (NAND_EVTER_EN)
- */
-/* Operation complete event enable */
-#define IFC_NAND_EVTER_EN_OPC_EN        0x80000000
-/* Page read complete event enable */
-#define IFC_NAND_EVTER_EN_PGRDCMPL_EN   0x20000000
-/* Flash Timeout error enable */
-#define IFC_NAND_EVTER_EN_FTOER_EN      0x08000000
-/* Write Protect error enable */
-#define IFC_NAND_EVTER_EN_WPER_EN       0x04000000
-/* ECC error logging enable */
-#define IFC_NAND_EVTER_EN_ECCER_EN      0x02000000
-/*
- * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
- */
-/* Enable interrupt for operation complete */
-#define IFC_NAND_EVTER_INTR_OPCIR_EN            0x80000000
-/* Enable interrupt for Page read complete */
-#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN       0x20000000
-/* Enable interrupt for Flash timeout error */
-#define IFC_NAND_EVTER_INTR_FTOERIR_EN          0x08000000
-/* Enable interrupt for Write protect error */
-#define IFC_NAND_EVTER_INTR_WPERIR_EN           0x04000000
-/* Enable interrupt for ECC error*/
-#define IFC_NAND_EVTER_INTR_ECCERIR_EN          0x02000000
-/*
- * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
- */
-#define IFC_NAND_ERATTR0_MASK           0x0C080000
-/* Error on CS0-3 for NAND */
-#define IFC_NAND_ERATTR0_ERCS_CS0       0x00000000
-#define IFC_NAND_ERATTR0_ERCS_CS1       0x04000000
-#define IFC_NAND_ERATTR0_ERCS_CS2       0x08000000
-#define IFC_NAND_ERATTR0_ERCS_CS3       0x0C000000
-/* Transaction type of error Read/Write */
-#define IFC_NAND_ERATTR0_ERTTYPE_READ   0x00080000
-/*
- * NAND Flash Status Register (NAND_FSR)
- */
-/* First byte of data read from read status op */
-#define IFC_NAND_NFSR_RS0               0xFF000000
-/* Second byte of data read from read status op */
-#define IFC_NAND_NFSR_RS1               0x00FF0000
-/*
- * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
- */
-/* Number of ECC errors on sector n (n = 0-15) */
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK   0x0F000000
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT  24
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK   0x000F0000
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT  16
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK   0x00000F00
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT  8
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK   0x0000000F
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT  0
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK   0x0F000000
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT  24
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK   0x000F0000
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT  16
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK   0x00000F00
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT  8
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK   0x0000000F
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT  0
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK   0x0F000000
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT  24
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK   0x000F0000
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT  16
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK  0x00000F00
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK  0x0000000F
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK  0x0F000000
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK  0x000F0000
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK  0x00000F00
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK  0x0000000F
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
-/*
- * NAND Control Register (NANDCR)
- */
-#define IFC_NAND_NCR_FTOCNT_MASK        0x1E000000
-#define IFC_NAND_NCR_FTOCNT_SHIFT       25
-#define IFC_NAND_NCR_FTOCNT(n)  ((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
-/*
- * NAND_AUTOBOOT_TRGR
- */
-/* Trigger RCW load */
-#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD   0x80000000
-/* Trigget Auto Boot */
-#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD  0x20000000
-/*
- * NAND_MDR
- */
-/* 1st read data byte when opcode SBRD */
-#define IFC_NAND_MDR_RDATA0             0xFF000000
-/* 2nd read data byte when opcode SBRD */
-#define IFC_NAND_MDR_RDATA1             0x00FF0000
-/*
- * NOR Machine Specific Registers
- */
-/*
- * NOR Event and Error Status Register (NOR_EVTER_STAT)
- */
-/* NOR Command Sequence Operation Complete */
-#define IFC_NOR_EVTER_STAT_OPC_NOR      0x80000000
-/* Write Protect Error */
-#define IFC_NOR_EVTER_STAT_WPER         0x04000000
-/* Command Sequence Timeout Error */
-#define IFC_NOR_EVTER_STAT_STOER        0x01000000
-/*
- * NOR Event and Error Enable Register (NOR_EVTER_EN)
- */
-/* NOR Command Seq complete event enable */
-#define IFC_NOR_EVTER_EN_OPCEN_NOR      0x80000000
-/* Write Protect Error Checking Enable */
-#define IFC_NOR_EVTER_EN_WPEREN         0x04000000
-/* Timeout Error Enable */
-#define IFC_NOR_EVTER_EN_STOEREN        0x01000000
-/*
- * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
- */
-/* Enable interrupt for OPC complete */
-#define IFC_NOR_EVTER_INTR_OPCEN_NOR    0x80000000
-/* Enable interrupt for write protect error */
-#define IFC_NOR_EVTER_INTR_WPEREN       0x04000000
-/* Enable interrupt for timeout error */
-#define IFC_NOR_EVTER_INTR_STOEREN      0x01000000
-/*
- * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
- */
-/* Source ID for error transaction */
-#define IFC_NOR_ERATTR0_ERSRCID         0xFF000000
-/* AXI ID for error transation */
-#define IFC_NOR_ERATTR0_ERAID           0x000FF000
-/* Chip select corresponds to NOR error */
-#define IFC_NOR_ERATTR0_ERCS_CS0        0x00000000
-#define IFC_NOR_ERATTR0_ERCS_CS1        0x00000010
-#define IFC_NOR_ERATTR0_ERCS_CS2        0x00000020
-#define IFC_NOR_ERATTR0_ERCS_CS3        0x00000030
-/* Type of transaction read/write */
-#define IFC_NOR_ERATTR0_ERTYPE_READ     0x00000001
-/*
- * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
- */
-#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP        0x000F0000
-#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER        0x00000F00
-/*
- * NOR Control Register (NORCR)
- */
-#define IFC_NORCR_MASK                  0x0F0F0000
-/* No. of Address/Data Phase */
-#define IFC_NORCR_NUM_PHASE_MASK        0x0F000000
-#define IFC_NORCR_NUM_PHASE_SHIFT       24
-#define IFC_NORCR_NUM_PHASE(n)  ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
-/* Sequence Timeout Count */
-#define IFC_NORCR_STOCNT_MASK           0x000F0000
-#define IFC_NORCR_STOCNT_SHIFT          16
-#define IFC_NORCR_STOCNT(n)     ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
-/*
- * GPCM Machine specific registers
- */
-/*
- * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
- */
-/* Timeout error */
-#define IFC_GPCM_EVTER_STAT_TOER        0x04000000
-/* Parity error */
-#define IFC_GPCM_EVTER_STAT_PER         0x01000000
-/*
- * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
- */
-/* Timeout error enable */
-#define IFC_GPCM_EVTER_EN_TOER_EN       0x04000000
-/* Parity error enable */
-#define IFC_GPCM_EVTER_EN_PER_EN        0x01000000
-/*
- * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
- */
-/* Enable Interrupt for timeout error */
-#define IFC_GPCM_EEIER_TOERIR_EN        0x04000000
-/* Enable Interrupt for Parity error */
-#define IFC_GPCM_EEIER_PERIR_EN         0x01000000
-/*
- * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
- */
-/* Source ID for error transaction */
-#define IFC_GPCM_ERATTR0_ERSRCID        0xFF000000
-/* AXI ID for error transaction */
-#define IFC_GPCM_ERATTR0_ERAID          0x000FF000
-/* Chip select corresponds to GPCM error */
-#define IFC_GPCM_ERATTR0_ERCS_CS0       0x00000000
-#define IFC_GPCM_ERATTR0_ERCS_CS1       0x00000040
-#define IFC_GPCM_ERATTR0_ERCS_CS2       0x00000080
-#define IFC_GPCM_ERATTR0_ERCS_CS3       0x000000C0
-/* Type of transaction read/Write */
-#define IFC_GPCM_ERATTR0_ERTYPE_READ    0x00000001
-/*
- * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
- */
-/* On which beat of address/data parity error is observed */
-#define IFC_GPCM_ERATTR2_PERR_BEAT              0x00000C00
-/* Parity Error on byte */
-#define IFC_GPCM_ERATTR2_PERR_BYTE              0x000000F0
-/* Parity Error reported in addr or data phase */
-#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE        0x00000001
-/*
- * GPCM Status Register (GPCM_STAT)
- */
-#define IFC_GPCM_STAT_BSY               0x80000000  /* GPCM is busy */
-/*
- * IFC Controller NAND Machine registers
- */
-struct fsl_ifc_nand {
-        __be32 ncfgr;
-        u32 res1[0x4];
-        __be32 nand_fcr0;
-        __be32 nand_fcr1;
-        u32 res2[0x8];
-        __be32 row0;
-        u32 res3;
-        __be32 col0;
-        u32 res4;
-        __be32 row1;
-        u32 res5;
-        __be32 col1;
-        u32 res6;
-        __be32 row2;
-        u32 res7;
-        __be32 col2;
-        u32 res8;
-        __be32 row3;
-        u32 res9;
-        __be32 col3;
-        u32 res10[0x24];
-        __be32 nand_fbcr;
-        u32 res11;
-        __be32 nand_fir0;
-        __be32 nand_fir1;
-        __be32 nand_fir2;
-        u32 res12[0x10];
-        __be32 nand_csel;
-        u32 res13;
-        __be32 nandseq_strt;
-        u32 res14;
-        __be32 nand_evter_stat;
-        u32 res15;
-        __be32 pgrdcmpl_evt_stat;
-        u32 res16[0x2];
-        __be32 nand_evter_en;
-        u32 res17[0x2];
-        __be32 nand_evter_intr_en;
-        u32 res18[0x2];
-        __be32 nand_erattr0;
-        __be32 nand_erattr1;
-        u32 res19[0x10];
-        __be32 nand_fsr;
-        u32 res20;
-        __be32 nand_eccstat[4];
-        u32 res21[0x20];
-        __be32 nanndcr;
-        u32 res22[0x2];
-        __be32 nand_autoboot_trgr;
-        u32 res23;
-        __be32 nand_mdr;
-        u32 res24[0x5C];
-};
-/*
- * IFC controller NOR Machine registers
- */
-struct fsl_ifc_nor {
-        __be32 nor_evter_stat;
-        u32 res1[0x2];
-        __be32 nor_evter_en;
-        u32 res2[0x2];
-        __be32 nor_evter_intr_en;
-        u32 res3[0x2];
-        __be32 nor_erattr0;
-        __be32 nor_erattr1;
-        __be32 nor_erattr2;
-        u32 res4[0x4];
-        __be32 norcr;
-        u32 res5[0xEF];
-};
-/*
- * IFC controller GPCM Machine registers
- */
-struct fsl_ifc_gpcm {
-        __be32 gpcm_evter_stat;
-        u32 res1[0x2];
-        __be32 gpcm_evter_en;
-        u32 res2[0x2];
-        __be32 gpcm_evter_intr_en;
-        u32 res3[0x2];
-        __be32 gpcm_erattr0;
-        __be32 gpcm_erattr1;
-        __be32 gpcm_erattr2;
-        __be32 gpcm_stat;
-        u32 res4[0x1F3];
-};
-/*
- * IFC Controller Registers
- */
-struct fsl_ifc_regs {
-        __be32 ifc_rev;
-        u32 res1[0x2];
-        struct {
-                __be32 cspr_ext;
-                __be32 cspr;
-                u32 res2;
-        } cspr_cs[FSL_IFC_BANK_COUNT];
-        u32 res3[0x19];
-        struct {
-                __be32 amask;
-                u32 res4[0x2];
-        } amask_cs[FSL_IFC_BANK_COUNT];
-        u32 res5[0x17];
-        struct {
-                __be32 csor_ext;
-                __be32 csor;
-                u32 res6;
-        } csor_cs[FSL_IFC_BANK_COUNT];
-        u32 res7[0x19];
-        struct {
-                __be32 ftim[4];
-                u32 res8[0x8];
-        } ftim_cs[FSL_IFC_BANK_COUNT];
-        u32 res9[0x60];
-        __be32 rb_stat;
-        u32 res10[0x2];
-        __be32 ifc_gcr;
-        u32 res11[0x2];
-        __be32 cm_evter_stat;
-        u32 res12[0x2];
-        __be32 cm_evter_en;
-        u32 res13[0x2];
-        __be32 cm_evter_intr_en;
-        u32 res14[0x2];
-        __be32 cm_erattr0;
-        __be32 cm_erattr1;
-        u32 res15[0x2];
-        __be32 ifc_ccr;
-        __be32 ifc_csr;
-        u32 res16[0x2EB];
-        struct fsl_ifc_nand ifc_nand;
-        struct fsl_ifc_nor ifc_nor;
-        struct fsl_ifc_gpcm ifc_gpcm;
-};
-extern unsigned int convert_ifc_address(phys_addr_t addr_base);
-extern int fsl_ifc_find(phys_addr_t addr_base);
-/* overview of the fsl ifc controller */
-struct fsl_ifc_ctrl {
-        /* device info */
-        struct device                   *dev;
-        struct fsl_ifc_regs __iomem     *regs;
-        int                             irq;
-        int                             nand_irq;
-        spinlock_t                      lock;
-        void                            *nand;
-        u32 nand_stat;
-        wait_queue_head_t nand_wait;
-};
-extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
-#endif /* __ASM_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index d8b600b3f058..5dbbb29f5c3e 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -274,6 +274,11 @@
 /* Platform specific hcalls, used by KVM */
 #define H_RTAS                  0xf000
+/* "Platform specific hcalls", provided by PHYP */
+#define H_GET_24X7_CATALOG_PAGE 0xF078
+#define H_GET_24X7_DATA         0xF07C
+#define H_GET_PERF_COUNTER_INFO 0xF080
 #ifndef __ASSEMBLY__
 /**
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index 83851aabfdc8..bb1e38a23ac7 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -304,6 +304,11 @@ static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)
        return vcpu->arch.fault_dar;
 }
+static inline bool is_kvmppc_resume_guest(int r)
+{
+        return (r == RESUME_GUEST || r == RESUME_GUEST_NV);
+}
 /* Magic register values loaded into r3 and r4 before the 'sc' assembly
 * instruction for the OSI hypercalls */
 #define OSI_SC_MAGIC_R3                 0x113724FA
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index bf0fa8b0a883..51388befeddb 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -289,6 +289,18 @@ static inline void note_hpte_modification(struct kvm *kvm,
        if (atomic_read(&kvm->arch.hpte_mod_interest))
                rev->guest_rpte |= HPTE_GR_MODIFIED;
 }
+/*
+ * Like kvm_memslots(), but for use in real mode when we can't do
+ * any RCU stuff (since the secondary threads are offline from the
+ * kernel's point of view), and we can't print anything.
+ * Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
+ */
+static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
+{
+        return rcu_dereference_raw_notrace(kvm->memslots);
+}
 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
 #endif /* __ASM_KVM_BOOK3S_64_H__ */
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index f3a91dc02c98..821725c1bf46 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -94,7 +94,7 @@ struct kvmppc_host_state {
        unsigned long xics_phys;
        u32 saved_xirr;
        u64 dabr;
-        u64 host_mmcr[3];
+        u64 host_mmcr[7];       /* MMCR 0,1,A, SIAR, SDAR, MMCR2, SIER */
        u32 host_pmc[8];
        u64 host_purr;
        u64 host_spurr;
diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
index 3a79f5325712..e5f048bbcb7c 100644
--- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h
+++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
@@ -36,26 +36,21 @@
 *   *(r8 + GPR11) = saved r11
 *
 * 64-bit host
- * Expected inputs (GEN/GDBELL/DBG/MC exception types):
+ * Expected inputs (GEN/GDBELL/DBG/CRIT/MC exception types):
 *  r10 = saved CR
 *  r13 = PACA_POINTER
 *  *(r13 + PACA_EX##type + EX_R10) = saved r10
 *  *(r13 + PACA_EX##type + EX_R11) = saved r11
 *  SPRN_SPRG_##type##_SCRATCH = saved r13
 *
-  * Expected inputs (CRIT exception type):
- *  r10 = saved CR
- *  r13 = PACA_POINTER
- *  *(r13 + PACA_EX##type + EX_R10) = saved r10
- *  *(r13 + PACA_EX##type + EX_R11) = saved r11
- *  *(r13 + PACA_EX##type + EX_R13) = saved r13
- *
 * Expected inputs (TLB exception type):
 *  r10 = saved CR
+ *  r12 = extlb pointer
 *  r13 = PACA_POINTER
- *  *(r13 + PACA_EX##type + EX_TLB_R10) = saved r10
+ *  *(r12 + EX_TLB_R10) = saved r10
- *  *(r13 + PACA_EX##type + EX_TLB_R11) = saved r11
+ *  *(r12 + EX_TLB_R11) = saved r11
- *  SPRN_SPRG_GEN_SCRATCH = saved r13
+ *  *(r12 + EX_TLB_R13) = saved r13
+ *  SPRN_SPRG_GEN_SCRATCH = saved r12
 *
 * Only the bolted version of TLB miss exception handlers is supported now.
 */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index fcd53f0d34ba..4096f16502a9 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -129,6 +129,8 @@ extern long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm,
                                struct kvm_create_spapr_tce *args);
 extern long kvmppc_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
                             unsigned long ioba, unsigned long tce);
+extern long kvmppc_h_get_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
+                             unsigned long ioba);
 extern struct kvm_rma_info *kvm_alloc_rma(void);
 extern void kvm_release_rma(struct kvm_rma_info *ri);
 extern struct page *kvm_alloc_hpt(unsigned long nr_pages);
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index ad3025d0880b..5b6c03f1058f 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -170,6 +170,9 @@ struct machdep_calls {
        int             (*system_reset_exception)(struct pt_regs *regs);
        int             (*machine_check_exception)(struct pt_regs *regs);
+        /* Called during machine check exception to retrive fixup address. */
+        bool            (*mce_check_early_recovery)(struct pt_regs *regs);
        /* Motherboard/chipset features. This is a kind of general purpose
         * hook used to control some machine specific features (like reset
         * lines, chip power control, etc...).
@@ -279,6 +282,10 @@ struct machdep_calls {
 #ifdef CONFIG_ARCH_RANDOM
        int (*get_random_long)(unsigned long *v);
 #endif
+#ifdef CONFIG_MEMORY_HOTREMOVE
+        int (*remove_memory)(u64, u64);
+#endif
 };
 extern void e500_idle(void);
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index 8e99edf6d966..f97d8cb6bdf6 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -187,7 +187,8 @@ struct mce_error_info {
 #define MCE_EVENT_DONTRELEASE   false
 extern void save_mce_event(struct pt_regs *regs, long handled,
-                           struct mce_error_info *mce_err, uint64_t addr);
+                           struct mce_error_info *mce_err, uint64_t nip,
+                           uint64_t addr);
 extern int get_mce_event(struct machine_check_event *mce, bool release);
 extern void release_mce_event(void);
 extern void machine_check_queue_event(void);
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 89b785d16846..901dac6b6cb7 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -287,11 +287,14 @@ extern int mmu_linear_psize;
 extern int mmu_vmemmap_psize;
 struct tlb_core_data {
+        /*
+         * Per-core spinlock for e6500 TLB handlers (no tlbsrx.)
+         * Must be the first struct element.
+         */
+        u8 lock;
        /* For software way selection, as on Freescale TLB1 */
        u8 esel_next, esel_max, esel_first;
-        /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
-        u8 lock;
 };
 #ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index ed82142a3251..a2efdaa020b0 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -83,8 +83,11 @@ extern int opal_enter_rtas(struct rtas_args *args,
 #define OPAL_INTERNAL_ERROR     -11
 #define OPAL_BUSY_EVENT         -12
 #define OPAL_HARDWARE_FROZEN    -13
+#define OPAL_WRONG_STATE        -14
+#define OPAL_ASYNC_COMPLETION   -15
 /* API Tokens (in r0) */
+#define OPAL_INVALID_CALL                       -1
 #define OPAL_CONSOLE_WRITE                      1
 #define OPAL_CONSOLE_READ                       2
 #define OPAL_RTC_READ                           3
@@ -151,15 +154,32 @@ extern int opal_enter_rtas(struct rtas_args *args,
 #define OPAL_LPC_READ                           67
 #define OPAL_LPC_WRITE                          68
 #define OPAL_RETURN_CPU                         69
+#define OPAL_ELOG_READ                          71
+#define OPAL_ELOG_WRITE                         72
+#define OPAL_ELOG_ACK                           73
+#define OPAL_ELOG_RESEND                        74
+#define OPAL_ELOG_SIZE                          75
 #define OPAL_FLASH_VALIDATE                     76
 #define OPAL_FLASH_MANAGE                       77
 #define OPAL_FLASH_UPDATE                       78
+#define OPAL_RESYNC_TIMEBASE                    79
+#define OPAL_DUMP_INIT                          81
+#define OPAL_DUMP_INFO                          82
+#define OPAL_DUMP_READ                          83
+#define OPAL_DUMP_ACK                           84
 #define OPAL_GET_MSG                            85
 #define OPAL_CHECK_ASYNC_COMPLETION             86
 #define OPAL_SYNC_HOST_REBOOT                   87
+#define OPAL_SENSOR_READ                        88
+#define OPAL_GET_PARAM                          89
+#define OPAL_SET_PARAM                          90
+#define OPAL_DUMP_RESEND                        91
+#define OPAL_DUMP_INFO2                         94
 #ifndef __ASSEMBLY__
+#include <linux/notifier.h>
 /* Other enums */
 enum OpalVendorApiTokens {
        OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
@@ -237,11 +257,14 @@ enum OpalPendingState {
        OPAL_EVENT_EPOW                 = 0x80,
        OPAL_EVENT_LED_STATUS           = 0x100,
        OPAL_EVENT_PCI_ERROR            = 0x200,
+        OPAL_EVENT_DUMP_AVAIL           = 0x400,
        OPAL_EVENT_MSG_PENDING          = 0x800,
 };
 enum OpalMessageType {
-        OPAL_MSG_ASYNC_COMP             = 0,
+        OPAL_MSG_ASYNC_COMP = 0,        /* params[0] = token, params[1] = rc,
+                                         * additional params function-specific
+                                         */
        OPAL_MSG_MEM_ERR,
        OPAL_MSG_EPOW,
        OPAL_MSG_SHUTDOWN,
@@ -394,10 +417,17 @@ enum OpalLPCAddressType {
        OPAL_LPC_FW     = 2,
 };
+/* System parameter permission */
+enum OpalSysparamPerm {
+        OPAL_SYSPARAM_READ      = 0x1,
+        OPAL_SYSPARAM_WRITE     = 0x2,
+        OPAL_SYSPARAM_RW        = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
+};
 struct opal_msg {
-        uint32_t msg_type;
+        __be32 msg_type;
-        uint32_t reserved;
+        __be32 reserved;
-        uint64_t params[8];
+        __be64 params[8];
 };
 struct opal_machine_check_event {
@@ -703,7 +733,11 @@ typedef struct oppanel_line {
 /* /sys/firmware/opal */
 extern struct kobject *opal_kobj;
+/* /ibm,opal */
+extern struct device_node *opal_node;
 /* API functions */
+int64_t opal_invalid_call(void);
 int64_t opal_console_write(int64_t term_number, __be64 *length,
                           const uint8_t *buffer);
 int64_t opal_console_read(int64_t term_number, __be64 *length,
@@ -823,16 +857,36 @@ int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
                       uint32_t addr, uint32_t data, uint32_t sz);
 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
                      uint32_t addr, __be32 *data, uint32_t sz);
+int64_t opal_read_elog(uint64_t buffer, size_t size, uint64_t log_id);
+int64_t opal_get_elog_size(uint64_t *log_id, size_t *size, uint64_t *elog_type);
+int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
+int64_t opal_send_ack_elog(uint64_t log_id);
+void opal_resend_pending_logs(void);
 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
 int64_t opal_manage_flash(uint8_t op);
 int64_t opal_update_flash(uint64_t blk_list);
+int64_t opal_dump_init(uint8_t dump_type);
+int64_t opal_dump_info(uint32_t *dump_id, uint32_t *dump_size);
+int64_t opal_dump_info2(uint32_t *dump_id, uint32_t *dump_size, uint32_t *dump_type);
+int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
+int64_t opal_dump_ack(uint32_t dump_id);
+int64_t opal_dump_resend_notification(void);
 int64_t opal_get_msg(uint64_t buffer, size_t size);
 int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
 int64_t opal_sync_host_reboot(void);
+int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
+                size_t length);
+int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
+                size_t length);
+int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
+extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
+                                 const char *uname, int depth, void *data);
 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
@@ -844,6 +898,8 @@ extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
                                   int depth, void *data);
 extern int opal_notifier_register(struct notifier_block *nb);
+extern int opal_notifier_unregister(struct notifier_block *nb);
 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
                                                struct notifier_block *nb);
 extern void opal_notifier_enable(void);
@@ -853,6 +909,13 @@ extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
+extern int __opal_async_get_token(void);
+extern int opal_async_get_token_interruptible(void);
+extern int __opal_async_release_token(int token);
+extern int opal_async_release_token(int token);
+extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
+extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
 extern void hvc_opal_init_early(void);
 struct rtc_time;
@@ -861,10 +924,16 @@ extern void opal_get_rtc_time(struct rtc_time *tm);
 extern unsigned long opal_get_boot_time(void);
 extern void opal_nvram_init(void);
 extern void opal_flash_init(void);
+extern int opal_elog_init(void);
+extern void opal_platform_dump_init(void);
+extern void opal_sys_param_init(void);
+extern void opal_msglog_init(void);
 extern int opal_machine_check(struct pt_regs *regs);
+extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
 extern void opal_shutdown(void);
+extern int opal_resync_timebase(void);
 extern void opal_lpc_init(void);
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 9c5dbc3833fb..8e956a0b6e85 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -116,8 +116,11 @@ struct paca_struct {
        /* Shared by all threads of a core -- points to tcd of first thread */
        struct tlb_core_data *tcd_ptr;
-        /* We can have up to 3 levels of reentrancy in the TLB miss handler */
+        /*
-        u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
+         * We can have up to 3 levels of reentrancy in the TLB miss handler,
+         * in each of four exception levels (normal, crit, mcheck, debug).
+         */
+        u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
        u64 exmc[8];            /* used for machine checks */
        u64 excrit[8];          /* used for crit interrupts */
        u64 exdbg[8];           /* used for debug interrupts */
@@ -146,7 +149,7 @@ struct paca_struct {
        u8 io_sync;                     /* writel() needs spin_unlock sync */
        u8 irq_work_pending;            /* IRQ_WORK interrupt while soft-disable */
        u8 nap_state_lost;              /* NV GPR values lost in power7_idle */
-        u64 sprg3;                      /* Saved user-visible sprg */
+        u64 sprg_vdso;                  /* Saved user-visible sprg */
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
        u64 tm_scratch;                 /* TM scratch area for reclaim */
 #endif
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 3fd2f1b6f906..9ed737146dbb 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -14,6 +14,7 @@
 #include <linux/device.h>
 #include <uapi/asm/perf_event.h>
+/* Update perf_event_print_debug() if this changes */
 #define MAX_HWEVENTS            8
 #define MAX_EVENT_ALTERNATIVES  8
 #define MAX_LIMITED_HWCOUNTERS  2
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index b62de43ae5f3..d660dc36831a 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -450,6 +450,7 @@ enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 extern void power7_nap(void);
+extern void power7_sleep(void);
 extern void flush_instruction_cache(void);
 extern void hard_reset_now(void);
 extern void poweroff_now(void);
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 90c06ec6eff5..e5d2e0bc7e03 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -213,6 +213,7 @@
 #define SPRN_ACOP       0x1F    /* Available Coprocessor Register */
 #define SPRN_TFIAR      0x81    /* Transaction Failure Inst Addr   */
 #define SPRN_TEXASR     0x82    /* Transaction EXception & Summary */
+#define   TEXASR_FS     __MASK(63-36)   /* Transaction Failure Summary */
 #define SPRN_TEXASRU    0x83    /* ''      ''      ''    Upper 32  */
 #define SPRN_TFHAR      0x80    /* Transaction Failure Handler Addr */
 #define SPRN_CTRLF      0x088
@@ -271,6 +272,10 @@
 #define SPRN_HSRR1      0x13B   /* Hypervisor Save/Restore 1 */
 #define SPRN_IC         0x350   /* Virtual Instruction Count */
 #define SPRN_VTB        0x351   /* Virtual Time Base */
+#define SPRN_PMICR      0x354   /* Power Management Idle Control Reg */
+#define SPRN_PMSR       0x355   /* Power Management Status Reg */
+#define SPRN_PMCR       0x374   /* Power Management Control Register */
 /* HFSCR and FSCR bit numbers are the same */
 #define FSCR_TAR_LG     8       /* Enable Target Address Register */
 #define FSCR_EBB_LG     7       /* Enable Event Based Branching */
@@ -577,9 +582,13 @@
 #define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
 #define SPRN_USPRG3     0x103   /* SPRG3 userspace read */
 #define SPRN_SPRG4      0x114   /* Special Purpose Register General 4 */
+#define SPRN_USPRG4     0x104   /* SPRG4 userspace read */
 #define SPRN_SPRG5      0x115   /* Special Purpose Register General 5 */
+#define SPRN_USPRG5     0x105   /* SPRG5 userspace read */
 #define SPRN_SPRG6      0x116   /* Special Purpose Register General 6 */
+#define SPRN_USPRG6     0x106   /* SPRG6 userspace read */
 #define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 */
+#define SPRN_USPRG7     0x107   /* SPRG7 userspace read */
 #define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
 #define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
 #define   SRR1_ISI_NOPT         0x40000000 /* ISI: Not found in hash */
@@ -664,12 +673,14 @@
 #define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
 #define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
 #define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
+#define   MMCR0_BHRBA   0x00200000UL /* BHRB Access allowed in userspace */
 #define   MMCR0_EBE     0x00100000UL /* Event based branch enable */
 #define   MMCR0_PMCC    0x000c0000UL /* PMC control */
 #define   MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
 #define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
 #define   MMCR0_PMCjCE  0x00004000UL /* PMCj count enable*/
 #define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+#define   MMCR0_PMAO_SYNC 0x00000800UL /* PMU interrupt is synchronous */
 #define   MMCR0_PMAO    0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
 #define   MMCR0_SHRFC   0x00000040UL /* SHRre freeze conditions between threads */
 #define   MMCR0_FC56    0x00000010UL /* freeze counters 5 and 6 */
@@ -703,6 +714,7 @@
 #define SPRN_EBBHR      804     /* Event based branch handler register */
 #define SPRN_EBBRR      805     /* Event based branch return register */
 #define SPRN_BESCR      806     /* Branch event status and control register */
+#define   BESCR_GE      0x8000000000000000ULL /* Global Enable */
 #define SPRN_WORT       895     /* Workload optimization register - thread */
 #define SPRN_PMC1       787
@@ -879,11 +891,10 @@
 * 64-bit embedded
 *      - SPRG0 generic exception scratch
 *      - SPRG2 TLB exception stack
- *      - SPRG3 critical exception scratch and
+ *      - SPRG3 critical exception scratch (user visible, sorry!)
- *        CPU and NUMA node for VDSO getcpu (user visible)
 *      - SPRG4 unused (user visible)
 *      - SPRG6 TLB miss scratch (user visible, sorry !)
- *      - SPRG7 critical exception scratch
+ *      - SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
 *      - SPRG8 machine check exception scratch
 *      - SPRG9 debug exception scratch
 *
@@ -940,6 +951,8 @@
 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG2
 #define SPRN_SPRG_HPACA         SPRN_HSPRG0
 #define SPRN_SPRG_HSCRATCH0     SPRN_HSPRG1
+#define SPRN_SPRG_VDSO_READ     SPRN_USPRG3
+#define SPRN_SPRG_VDSO_WRITE    SPRN_SPRG3
 #define GET_PACA(rX)                                    \
        BEGIN_FTR_SECTION_NESTED(66);                   \
@@ -983,6 +996,8 @@
 #define SPRN_SPRG_TLB_SCRATCH   SPRN_SPRG6
 #define SPRN_SPRG_GEN_SCRATCH   SPRN_SPRG0
 #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
+#define SPRN_SPRG_VDSO_READ     SPRN_USPRG7
+#define SPRN_SPRG_VDSO_WRITE    SPRN_SPRG7
 #define SET_PACA(rX)    mtspr   SPRN_SPRG_PACA,rX
 #define GET_PACA(rX)    mfspr   rX,SPRN_SPRG_PACA
@@ -1102,6 +1117,8 @@
 #define PVR_8560        0x80200000
 #define PVR_VER_E500V1  0x8020
 #define PVR_VER_E500V2  0x8021
+#define PVR_VER_E500MC  0x8023
+#define PVR_VER_E5500   0x8024
 #define PVR_VER_E6500   0x8040
 /*
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 9bd52c65e66f..b390f55b0df1 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -150,19 +150,53 @@ struct rtas_suspend_me_data {
 #define RTAS_VECTOR_EXTERNAL_INTERRUPT  0x500
 struct rtas_error_log {
-        unsigned long version:8;                /* Architectural version */
+        /* Byte 0 */
-        unsigned long severity:3;               /* Severity level of error */
+        uint8_t         byte0;                  /* Architectural version */
-        unsigned long disposition:2;            /* Degree of recovery */
-        unsigned long extended:1;               /* extended log present? */
+        /* Byte 1 */
-        unsigned long /* reserved */ :2;        /* Reserved for future use */
+        uint8_t         byte1;
-        unsigned long initiator:4;              /* Initiator of event */
+        /* XXXXXXXX
-        unsigned long target:4;                 /* Target of failed operation */
+         * XXX          3: Severity level of error
-        unsigned long type:8;                   /* General event or error*/
+         *    XX        2: Degree of recovery
-        unsigned long extended_log_length:32;   /* length in bytes */
+         *      X       1: Extended log present?
-        unsigned char buffer[1];                /* Start of extended log */
+         *       XX     2: Reserved
+         */
+        /* Byte 2 */
+        uint8_t         byte2;
+        /* XXXXXXXX
+         * XXXX         4: Initiator of event
+         *     XXXX     4: Target of failed operation
+         */
+        uint8_t         byte3;                  /* General event or error*/
+        __be32          extended_log_length;    /* length in bytes */
+        unsigned char   buffer[1];              /* Start of extended log */
                                                /* Variable length.      */
 };
+static inline uint8_t rtas_error_severity(const struct rtas_error_log *elog)
+{
+        return (elog->byte1 & 0xE0) >> 5;
+}
+static inline uint8_t rtas_error_disposition(const struct rtas_error_log *elog)
+{
+        return (elog->byte1 & 0x18) >> 3;
+}
+static inline uint8_t rtas_error_extended(const struct rtas_error_log *elog)
+{
+        return (elog->byte1 & 0x04) >> 2;
+}
+#define rtas_error_type(x)      ((x)->byte3)
+static inline
+uint32_t rtas_error_extended_log_length(const struct rtas_error_log *elog)
+{
+        return be32_to_cpu(elog->extended_log_length);
+}
 #define RTAS_V6EXT_LOG_FORMAT_EVENT_LOG 14
 #define RTAS_V6EXT_COMPANY_ID_IBM       (('I' << 24) | ('B' << 16) | ('M' << 8))
@@ -172,32 +206,35 @@ struct rtas_error_log {
 */
 struct rtas_ext_event_log_v6 {
        /* Byte 0 */
-        uint32_t log_valid:1;           /* 1:Log valid */
+        uint8_t byte0;
-        uint32_t unrecoverable_error:1; /* 1:Unrecoverable error */
+        /* XXXXXXXX
-        uint32_t recoverable_error:1;   /* 1:recoverable (correctable   */
+         * X            1: Log valid
-                                        /*   or successfully retried)   */
+         *  X           1: Unrecoverable error
-        uint32_t degraded_operation:1;  /* 1:Unrecoverable err, bypassed*/
+         *   X          1: Recoverable (correctable or successfully retried)
-                                        /*   - degraded operation (e.g. */
+         *    X         1: Bypassed unrecoverable error (degraded operation)
-                                        /*   CPU or mem taken off-line) */
+         *     X        1: Predictive error
-        uint32_t predictive_error:1;
+         *      X       1: "New" log (always 1 for data returned from RTAS)
-        uint32_t new_log:1;             /* 1:"New" log (Always 1 for    */
+         *       X      1: Big Endian
-                                        /*   data returned from RTAS    */
+         *        X     1: Reserved
-        uint32_t big_endian:1;          /* 1: Big endian */
+         */
-        uint32_t :1;                    /* reserved */
        /* Byte 1 */
-        uint32_t :8;                    /* reserved */
+        uint8_t byte1;                  /* reserved */
        /* Byte 2 */
-        uint32_t powerpc_format:1;      /* Set to 1 (indicating log is  */
+        uint8_t byte2;
-                                        /* in PowerPC format            */
+        /* XXXXXXXX
-        uint32_t :3;                    /* reserved */
+         * X            1: Set to 1 (indicating log is in PowerPC format)
-        uint32_t log_format:4;          /* Log format indicator. Define */
+         *  XXX         3: Reserved
-                                        /* format used for byte 12-2047 */
+         *     XXXX     4: Log format used for bytes 12-2047
+         */
        /* Byte 3 */
-        uint32_t :8;                    /* reserved */
+        uint8_t byte3;                  /* reserved */
        /* Byte 4-11 */
        uint8_t reserved[8];            /* reserved */
        /* Byte 12-15 */
-        uint32_t company_id;            /* Company ID of the company    */
+        __be32  company_id;             /* Company ID of the company    */
                                        /* that defines the format for  */
                                        /* the vendor specific log type */
        /* Byte 16-end of log */
@@ -205,6 +242,18 @@ struct rtas_ext_event_log_v6 {
                                        /* Variable length.             */
 };
+static
+inline uint8_t rtas_ext_event_log_format(struct rtas_ext_event_log_v6 *ext_log)
+{
+        return ext_log->byte2 & 0x0F;
+}
+static
+inline uint32_t rtas_ext_event_company_id(struct rtas_ext_event_log_v6 *ext_log)
+{
+        return be32_to_cpu(ext_log->company_id);
+}
 /* pSeries event log format */
 /* Two bytes ASCII section IDs */
@@ -227,14 +276,26 @@ struct rtas_ext_event_log_v6 {
 /* Vendor specific Platform Event Log Format, Version 6, section header */
 struct pseries_errorlog {
-        uint16_t id;                    /* 0x00 2-byte ASCII section ID */
+        __be16 id;                      /* 0x00 2-byte ASCII section ID */
-        uint16_t length;                /* 0x02 Section length in bytes */
+        __be16 length;                  /* 0x02 Section length in bytes */
        uint8_t version;                /* 0x04 Section version         */
        uint8_t subtype;                /* 0x05 Section subtype         */
-        uint16_t creator_component;     /* 0x06 Creator component ID    */
+        __be16 creator_component;       /* 0x06 Creator component ID    */
        uint8_t data[];                 /* 0x08 Start of section data   */
 };
+static
+inline uint16_t pseries_errorlog_id(struct pseries_errorlog *sect)
+{
+        return be16_to_cpu(sect->id);
+}
+static
+inline uint16_t pseries_errorlog_length(struct pseries_errorlog *sect)
+{
+        return be16_to_cpu(sect->length);
+}
 struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log,
                                              uint16_t section_id);
@@ -283,6 +344,7 @@ extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
 #ifdef CONFIG_PPC_PSERIES
 extern int pseries_devicetree_update(s32 scope);
+extern void post_mobility_fixup(void);
 #endif
 #ifdef CONFIG_PPC_RTAS_DAEMON
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index 084e0807db98..ff51046b6466 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -120,7 +120,7 @@ extern int cpu_to_core_id(int cpu);
 * in /proc/interrupts will be wrong!!! --Troy */
 #define PPC_MSG_CALL_FUNCTION   0
 #define PPC_MSG_RESCHEDULE      1
-#define PPC_MSG_CALL_FUNC_SINGLE        2
+#define PPC_MSG_TICK_BROADCAST  2
 #define PPC_MSG_DEBUGGER_BREAK  3
 /* for irq controllers that have dedicated ipis per message (4) */
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index c1f267694acb..1d428e6007ca 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -28,6 +28,7 @@ extern struct clock_event_device decrementer_clockevent;
 struct rtc_time;
 extern void to_tm(int tim, struct rtc_time * tm);
 extern void GregorianDay(struct rtc_time *tm);
+extern void tick_broadcast_ipi_handler(void);
 extern void generic_calibrate_decr(void);
diff --git a/arch/powerpc/include/asm/tm.h b/arch/powerpc/include/asm/tm.h
index 0c9f8b74dd97..c22d704b6d41 100644
--- a/arch/powerpc/include/asm/tm.h
+++ b/arch/powerpc/include/asm/tm.h
@@ -7,6 +7,8 @@
 #include <uapi/asm/tm.h>
+#ifndef __ASSEMBLY__
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 extern void do_load_up_transact_fpu(struct thread_struct *thread);
 extern void do_load_up_transact_altivec(struct thread_struct *thread);
@@ -21,3 +23,5 @@ extern void tm_recheckpoint(struct thread_struct *thread,
 extern void tm_abort(uint8_t cause);
 extern void tm_save_sprs(struct thread_struct *thread);
 extern void tm_restore_sprs(struct thread_struct *thread);
+#endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index de91f3ae631e..94908af308d8 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -73,7 +73,7 @@ static struct aligninfo aligninfo[128] = {
        { 8, LD+F },            /* 00 0 1001: lfd */
        { 4, ST+F+S },          /* 00 0 1010: stfs */
        { 8, ST+F },            /* 00 0 1011: stfd */
-        INVALID,                /* 00 0 1100 */
+        { 16, LD },             /* 00 0 1100: lq */
        { 8, LD },              /* 00 0 1101: ld/ldu/lwa */
        INVALID,                /* 00 0 1110 */
        { 8, ST },              /* 00 0 1111: std/stdu */
@@ -140,7 +140,7 @@ static struct aligninfo aligninfo[128] = {
        { 2, LD+SW },           /* 10 0 1100: lhbrx */
        { 4, LD+SE },           /* 10 0 1101  lwa */
        { 2, ST+SW },           /* 10 0 1110: sthbrx */
-        INVALID,                /* 10 0 1111 */
+        { 16, ST },             /* 10 0 1111: stq */
        INVALID,                /* 10 1 0000 */
        INVALID,                /* 10 1 0001 */
        INVALID,                /* 10 1 0010 */
@@ -385,8 +385,6 @@ static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg,
        char *ptr1 = (char *) &current->thread.TS_FPR(reg+1);
        int i, ret, sw = 0;
-        if (!(flags & F))
-                return 0;
        if (reg & 1)
                return 0;       /* invalid form: FRS/FRT must be even */
        if (flags & SW)
@@ -406,6 +404,34 @@ static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg,
        return 1;       /* exception handled and fixed up */
 }
+#ifdef CONFIG_PPC64
+static int emulate_lq_stq(struct pt_regs *regs, unsigned char __user *addr,
+                          unsigned int reg, unsigned int flags)
+{
+        char *ptr0 = (char *)&regs->gpr[reg];
+        char *ptr1 = (char *)&regs->gpr[reg+1];
+        int i, ret, sw = 0;
+        if (reg & 1)
+                return 0;       /* invalid form: GPR must be even */
+        if (flags & SW)
+                sw = 7;
+        ret = 0;
+        for (i = 0; i < 8; ++i) {
+                if (!(flags & ST)) {
+                        ret |= __get_user(ptr0[i^sw], addr + i);
+                        ret |= __get_user(ptr1[i^sw], addr + i + 8);
+                } else {
+                        ret |= __put_user(ptr0[i^sw], addr + i);
+                        ret |= __put_user(ptr1[i^sw], addr + i + 8);
+                }
+        }
+        if (ret)
+                return -EFAULT;
+        return 1;       /* exception handled and fixed up */
+}
+#endif /* CONFIG_PPC64 */
 #ifdef CONFIG_SPE
 static struct aligninfo spe_aligninfo[32] = {
@@ -914,10 +940,20 @@ int fix_alignment(struct pt_regs *regs)
                flush_fp_to_thread(current);
        }
-        /* Special case for 16-byte FP loads and stores */
+        if ((nb == 16)) {
-        if (nb == 16) {
+                if (flags & F) {
-                PPC_WARN_ALIGNMENT(fp_pair, regs);
+                        /* Special case for 16-byte FP loads and stores */
-                return emulate_fp_pair(addr, reg, flags);
+                        PPC_WARN_ALIGNMENT(fp_pair, regs);
+                        return emulate_fp_pair(addr, reg, flags);
+                } else {
+#ifdef CONFIG_PPC64
+                        /* Special case for 16-byte loads and stores */
+                        PPC_WARN_ALIGNMENT(lq_stq, regs);
+                        return emulate_lq_stq(regs, addr, reg, flags);
+#else
+                        return 0;
+#endif
+                }
        }
        PPC_WARN_ALIGNMENT(unaligned, regs);
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index b5aacf72ae6f..dba8140ebc20 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -253,7 +253,7 @@ int main(void)
        DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
        DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
        DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
-        DEFINE(PACA_SPRG3, offsetof(struct paca_struct, sprg3));
+        DEFINE(PACA_SPRG_VDSO, offsetof(struct paca_struct, sprg_vdso));
 #endif /* CONFIG_PPC64 */
        /* RTAS */
diff --git a/arch/powerpc/kernel/cacheinfo.c b/arch/powerpc/kernel/cacheinfo.c
index 2912b8787aa4..40198d50b4c2 100644
--- a/arch/powerpc/kernel/cacheinfo.c
+++ b/arch/powerpc/kernel/cacheinfo.c
@@ -756,7 +756,10 @@ void cacheinfo_cpu_online(unsigned int cpu_id)
        cacheinfo_sysfs_populate(cpu_id, cache);
 }
-#ifdef CONFIG_HOTPLUG_CPU /* functions needed for cpu offline */
+/* functions needed to remove cache entry for cpu offline or suspend/resume */
+#if (defined(CONFIG_PPC_PSERIES) && defined(CONFIG_SUSPEND)) || \
+    defined(CONFIG_HOTPLUG_CPU)
 static struct cache *cache_lookup_by_cpu(unsigned int cpu_id)
 {
@@ -843,4 +846,4 @@ void cacheinfo_cpu_offline(unsigned int cpu_id)
        if (cache)
                cache_cpu_clear(cache, cpu_id);
 }
-#endif /* CONFIG_HOTPLUG_CPU */
+#endif /* (CONFIG_PPC_PSERIES && CONFIG_SUSPEND) || CONFIG_HOTPLUG_CPU */
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 37d1bb002aa9..1557e7c2c7e1 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -56,7 +56,6 @@ _GLOBAL(__setup_cpu_power8)
        li      r0,0
        mtspr   SPRN_LPID,r0
        mfspr   r3,SPRN_LPCR
-        oris    r3, r3, LPCR_AIL_3@h
        bl      __init_LPCR
        bl      __init_HFSCR
        bl      __init_tlb_power8
@@ -75,7 +74,6 @@ _GLOBAL(__restore_cpu_power8)
        li      r0,0
        mtspr   SPRN_LPID,r0
        mfspr   r3,SPRN_LPCR
-        oris    r3, r3, LPCR_AIL_3@h
        bl      __init_LPCR
        bl      __init_HFSCR
        bl      __init_tlb_power8
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 6c8dd5da4de5..c1faade6506d 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -510,7 +510,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .pvr_mask               = 0xffff0000,
                .pvr_value              = 0x004b0000,
                .cpu_name               = "POWER8E (raw)",
-                .cpu_features           = CPU_FTRS_POWER8,
+                .cpu_features           = CPU_FTRS_POWER8E,
                .cpu_user_features      = COMMON_USER_POWER8,
                .cpu_user_features2     = COMMON_USER2_POWER8,
                .mmu_features           = MMU_FTRS_POWER8,
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 063b65dd4f27..c1bee3ce9d1f 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -34,7 +34,250 @@
 *     special interrupts from within a non-standard level will probably
 *     blow you up
 */
-#define SPECIAL_EXC_FRAME_SIZE  INT_FRAME_SIZE
+#define SPECIAL_EXC_SRR0        0
+#define SPECIAL_EXC_SRR1        1
+#define SPECIAL_EXC_SPRG_GEN    2
+#define SPECIAL_EXC_SPRG_TLB    3
+#define SPECIAL_EXC_MAS0        4
+#define SPECIAL_EXC_MAS1        5
+#define SPECIAL_EXC_MAS2        6
+#define SPECIAL_EXC_MAS3        7
+#define SPECIAL_EXC_MAS6        8
+#define SPECIAL_EXC_MAS7        9
+#define SPECIAL_EXC_MAS5        10      /* E.HV only */
+#define SPECIAL_EXC_MAS8        11      /* E.HV only */
+#define SPECIAL_EXC_IRQHAPPENED 12
+#define SPECIAL_EXC_DEAR        13
+#define SPECIAL_EXC_ESR         14
+#define SPECIAL_EXC_SOFTE       15
+#define SPECIAL_EXC_CSRR0       16
+#define SPECIAL_EXC_CSRR1       17
+/* must be even to keep 16-byte stack alignment */
+#define SPECIAL_EXC_END         18
+#define SPECIAL_EXC_FRAME_SIZE  (INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
+#define SPECIAL_EXC_FRAME_OFFS  (INT_FRAME_SIZE - 288)
+#define SPECIAL_EXC_STORE(reg, name) \
+        std     reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
+#define SPECIAL_EXC_LOAD(reg, name) \
+        ld      reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
+special_reg_save:
+        lbz     r9,PACAIRQHAPPENED(r13)
+        RECONCILE_IRQ_STATE(r3,r4)
+        /*
+         * We only need (or have stack space) to save this stuff if
+         * we interrupted the kernel.
+         */
+        ld      r3,_MSR(r1)
+        andi.   r3,r3,MSR_PR
+        bnelr
+        /* Copy info into temporary exception thread info */
+        ld      r11,PACAKSAVE(r13)
+        CURRENT_THREAD_INFO(r11, r11)
+        CURRENT_THREAD_INFO(r12, r1)
+        ld      r10,TI_FLAGS(r11)
+        std     r10,TI_FLAGS(r12)
+        ld      r10,TI_PREEMPT(r11)
+        std     r10,TI_PREEMPT(r12)
+        ld      r10,TI_TASK(r11)
+        std     r10,TI_TASK(r12)
+        /*
+         * Advance to the next TLB exception frame for handler
+         * types that don't do it automatically.
+         */
+        LOAD_REG_ADDR(r11,extlb_level_exc)
+        lwz     r12,0(r11)
+        mfspr   r10,SPRN_SPRG_TLB_EXFRAME
+        add     r10,r10,r12
+        mtspr   SPRN_SPRG_TLB_EXFRAME,r10
+        /*
+         * Save registers needed to allow nesting of certain exceptions
+         * (such as TLB misses) inside special exception levels
+         */
+        mfspr   r10,SPRN_SRR0
+        SPECIAL_EXC_STORE(r10,SRR0)
+        mfspr   r10,SPRN_SRR1
+        SPECIAL_EXC_STORE(r10,SRR1)
+        mfspr   r10,SPRN_SPRG_GEN_SCRATCH
+        SPECIAL_EXC_STORE(r10,SPRG_GEN)
+        mfspr   r10,SPRN_SPRG_TLB_SCRATCH
+        SPECIAL_EXC_STORE(r10,SPRG_TLB)
+        mfspr   r10,SPRN_MAS0
+        SPECIAL_EXC_STORE(r10,MAS0)
+        mfspr   r10,SPRN_MAS1
+        SPECIAL_EXC_STORE(r10,MAS1)
+        mfspr   r10,SPRN_MAS2
+        SPECIAL_EXC_STORE(r10,MAS2)
+        mfspr   r10,SPRN_MAS3
+        SPECIAL_EXC_STORE(r10,MAS3)
+        mfspr   r10,SPRN_MAS6
+        SPECIAL_EXC_STORE(r10,MAS6)
+        mfspr   r10,SPRN_MAS7
+        SPECIAL_EXC_STORE(r10,MAS7)
+BEGIN_FTR_SECTION
+        mfspr   r10,SPRN_MAS5
+        SPECIAL_EXC_STORE(r10,MAS5)
+        mfspr   r10,SPRN_MAS8
+        SPECIAL_EXC_STORE(r10,MAS8)
+        /* MAS5/8 could have inappropriate values if we interrupted KVM code */
+        li      r10,0
+        mtspr   SPRN_MAS5,r10
+        mtspr   SPRN_MAS8,r10
+END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
+        SPECIAL_EXC_STORE(r9,IRQHAPPENED)
+        mfspr   r10,SPRN_DEAR
+        SPECIAL_EXC_STORE(r10,DEAR)
+        mfspr   r10,SPRN_ESR
+        SPECIAL_EXC_STORE(r10,ESR)
+        lbz     r10,PACASOFTIRQEN(r13)
+        SPECIAL_EXC_STORE(r10,SOFTE)
+        ld      r10,_NIP(r1)
+        SPECIAL_EXC_STORE(r10,CSRR0)
+        ld      r10,_MSR(r1)
+        SPECIAL_EXC_STORE(r10,CSRR1)
+        blr
+ret_from_level_except:
+        ld      r3,_MSR(r1)
+        andi.   r3,r3,MSR_PR
+        beq     1f
+        b       ret_from_except
+1:
+        LOAD_REG_ADDR(r11,extlb_level_exc)
+        lwz     r12,0(r11)
+        mfspr   r10,SPRN_SPRG_TLB_EXFRAME
+        sub     r10,r10,r12
+        mtspr   SPRN_SPRG_TLB_EXFRAME,r10
+        /*
+         * It's possible that the special level exception interrupted a
+         * TLB miss handler, and inserted the same entry that the
+         * interrupted handler was about to insert.  On CPUs without TLB
+         * write conditional, this can result in a duplicate TLB entry.
+         * Wipe all non-bolted entries to be safe.
+         *
+         * Note that this doesn't protect against any TLB misses
+         * we may take accessing the stack from here to the end of
+         * the special level exception.  It's not clear how we can
+         * reasonably protect against that, but only CPUs with
+         * neither TLB write conditional nor bolted kernel memory
+         * are affected.  Do any such CPUs even exist?
+         */
+        PPC_TLBILX_ALL(0,R0)
+        REST_NVGPRS(r1)
+        SPECIAL_EXC_LOAD(r10,SRR0)
+        mtspr   SPRN_SRR0,r10
+        SPECIAL_EXC_LOAD(r10,SRR1)
+        mtspr   SPRN_SRR1,r10
+        SPECIAL_EXC_LOAD(r10,SPRG_GEN)
+        mtspr   SPRN_SPRG_GEN_SCRATCH,r10
+        SPECIAL_EXC_LOAD(r10,SPRG_TLB)
+        mtspr   SPRN_SPRG_TLB_SCRATCH,r10
+        SPECIAL_EXC_LOAD(r10,MAS0)
+        mtspr   SPRN_MAS0,r10
+        SPECIAL_EXC_LOAD(r10,MAS1)
+        mtspr   SPRN_MAS1,r10
+        SPECIAL_EXC_LOAD(r10,MAS2)
+        mtspr   SPRN_MAS2,r10
+        SPECIAL_EXC_LOAD(r10,MAS3)
+        mtspr   SPRN_MAS3,r10
+        SPECIAL_EXC_LOAD(r10,MAS6)
+        mtspr   SPRN_MAS6,r10
+        SPECIAL_EXC_LOAD(r10,MAS7)
+        mtspr   SPRN_MAS7,r10
+BEGIN_FTR_SECTION
+        SPECIAL_EXC_LOAD(r10,MAS5)
+        mtspr   SPRN_MAS5,r10
+        SPECIAL_EXC_LOAD(r10,MAS8)
+        mtspr   SPRN_MAS8,r10
+END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
+        lbz     r6,PACASOFTIRQEN(r13)
+        ld      r5,SOFTE(r1)
+        /* Interrupts had better not already be enabled... */
+        twnei   r6,0
+        cmpwi   cr0,r5,0
+        beq     1f
+        TRACE_ENABLE_INTS
+        stb     r5,PACASOFTIRQEN(r13)
+1:
+        /*
+         * Restore PACAIRQHAPPENED rather than setting it based on
+         * the return MSR[EE], since we could have interrupted
+         * __check_irq_replay() or other inconsistent transitory
+         * states that must remain that way.
+         */
+        SPECIAL_EXC_LOAD(r10,IRQHAPPENED)
+        stb     r10,PACAIRQHAPPENED(r13)
+        SPECIAL_EXC_LOAD(r10,DEAR)
+        mtspr   SPRN_DEAR,r10
+        SPECIAL_EXC_LOAD(r10,ESR)
+        mtspr   SPRN_ESR,r10
+        stdcx.  r0,0,r1         /* to clear the reservation */
+        REST_4GPRS(2, r1)
+        REST_4GPRS(6, r1)
+        ld      r10,_CTR(r1)
+        ld      r11,_XER(r1)
+        mtctr   r10
+        mtxer   r11
+        blr
+.macro ret_from_level srr0 srr1 paca_ex scratch
+        bl      ret_from_level_except
+        ld      r10,_LINK(r1)
+        ld      r11,_CCR(r1)
+        ld      r0,GPR13(r1)
+        mtlr    r10
+        mtcr    r11
+        ld      r10,GPR10(r1)
+        ld      r11,GPR11(r1)
+        ld      r12,GPR12(r1)
+        mtspr   \scratch,r0
+        std     r10,\paca_ex+EX_R10(r13);
+        std     r11,\paca_ex+EX_R11(r13);
+        ld      r10,_NIP(r1)
+        ld      r11,_MSR(r1)
+        ld      r0,GPR0(r1)
+        ld      r1,GPR1(r1)
+        mtspr   \srr0,r10
+        mtspr   \srr1,r11
+        ld      r10,\paca_ex+EX_R10(r13)
+        ld      r11,\paca_ex+EX_R11(r13)
+        mfspr   r13,\scratch
+.endm
+ret_from_crit_except:
+        ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
+        rfci
+ret_from_mc_except:
+        ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
+        rfmci
 /* Exception prolog code for all exceptions */
 #define EXCEPTION_PROLOG(n, intnum, type, addition)                         \
@@ -42,7 +285,6 @@
        mfspr   r13,SPRN_SPRG_PACA;     /* get PACA */                      \
        std     r10,PACA_EX##type+EX_R10(r13);                              \
        std     r11,PACA_EX##type+EX_R11(r13);                              \
-        PROLOG_STORE_RESTORE_SCRATCH_##type;                                \
        mfcr    r10;                    /* save CR */                       \
        mfspr   r11,SPRN_##type##_SRR1;/* what are we coming from */        \
        DO_KVM  intnum,SPRN_##type##_SRR1;    /* KVM hook */                \
@@ -69,19 +311,19 @@
 #define CRIT_SET_KSTACK                                                     \
        ld      r1,PACA_CRIT_STACK(r13);                                    \
-        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
+        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE
 #define SPRN_CRIT_SRR0  SPRN_CSRR0
 #define SPRN_CRIT_SRR1  SPRN_CSRR1
 #define DBG_SET_KSTACK                                                      \
        ld      r1,PACA_DBG_STACK(r13);                                     \
-        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
+        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE
 #define SPRN_DBG_SRR0   SPRN_DSRR0
 #define SPRN_DBG_SRR1   SPRN_DSRR1
 #define MC_SET_KSTACK                                                       \
        ld      r1,PACA_MC_STACK(r13);                                      \
-        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
+        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE
 #define SPRN_MC_SRR0    SPRN_MCSRR0
 #define SPRN_MC_SRR1    SPRN_MCSRR1
@@ -100,20 +342,6 @@
 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition)                        \
        EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
-/*
- * Store user-visible scratch in PACA exception slots and restore proper value
- */
-#define PROLOG_STORE_RESTORE_SCRATCH_GEN
-#define PROLOG_STORE_RESTORE_SCRATCH_GDBELL
-#define PROLOG_STORE_RESTORE_SCRATCH_DBG
-#define PROLOG_STORE_RESTORE_SCRATCH_MC
-#define PROLOG_STORE_RESTORE_SCRATCH_CRIT                                   \
-        mfspr   r10,SPRN_SPRG_CRIT_SCRATCH;     /* get r13 */               \
-        std     r10,PACA_EXCRIT+EX_R13(r13);                                \
-        ld      r11,PACA_SPRG3(r13);                                        \
-        mtspr   SPRN_SPRG_CRIT_SCRATCH,r11;
 /* Variants of the "addition" argument for the prolog
 */
 #define PROLOG_ADDITION_NONE_GEN(n)
@@ -147,10 +375,8 @@
        std     r15,PACA_EXMC+EX_R15(r13)
-/* Core exception code for all exceptions except TLB misses.
+/* Core exception code for all exceptions except TLB misses. */
- * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
+#define EXCEPTION_COMMON_LVL(n, scratch, excf)                              \
- */
-#define EXCEPTION_COMMON(n, excf, ints)                                     \
 exc_##n##_common:                                                           \
        std     r0,GPR0(r1);            /* save r0 in stackframe */         \
        std     r2,GPR2(r1);            /* save r2 in stackframe */         \
@@ -163,7 +389,7 @@ exc_##n##_common:							    \
        ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */      \
 2:      ld      r3,excf+EX_R10(r13);    /* get back r10 */                  \
        ld      r4,excf+EX_R11(r13);    /* get back r11 */                  \
-        mfspr   r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */                 \
+        mfspr   r5,scratch;             /* get back r13 */                  \
        std     r12,GPR12(r1);          /* save r12 in stackframe */        \
        ld      r2,PACATOC(r13);        /* get kernel TOC into r2 */        \
        mflr    r6;                     /* save LR in stackframe */         \
@@ -187,24 +413,29 @@ exc_##n##_common:							    \
        std     r11,SOFTE(r1);          /* and save it to stackframe */     \
        std     r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */       \
        std     r3,_TRAP(r1);           /* set trap number              */  \
-        std     r0,RESULT(r1);          /* clear regs->result */            \
+        std     r0,RESULT(r1);          /* clear regs->result */
-        ints;
-/* Variants for the "ints" argument. This one does nothing when we want
+#define EXCEPTION_COMMON(n) \
- * to keep interrupts in their original state
+        EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
- */
+#define EXCEPTION_COMMON_CRIT(n) \
-#define INTS_KEEP
+        EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
+#define EXCEPTION_COMMON_MC(n) \
+        EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
+#define EXCEPTION_COMMON_DBG(n) \
+        EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
-/* This second version is meant for exceptions that don't immediately
+/*
- * hard-enable. We set a bit in paca->irq_happened to ensure that
+ * This is meant for exceptions that don't immediately hard-enable.  We
- * a subsequent call to arch_local_irq_restore() will properly
+ * set a bit in paca->irq_happened to ensure that a subsequent call to
- * hard-enable and avoid the fast-path, and then reconcile irq state.
+ * arch_local_irq_restore() will properly hard-enable and avoid the
+ * fast-path, and then reconcile irq state.
 */
 #define INTS_DISABLE    RECONCILE_IRQ_STATE(r3,r4)
-/* This is called by exceptions that used INTS_KEEP (that did not touch
+/*
- * irq indicators in the PACA). This will restore MSR:EE to it's previous
+ * This is called by exceptions that don't use INTS_DISABLE (that did not
- * value
+ * touch irq indicators in the PACA).  This will restore MSR:EE to it's
+ * previous value
 *
 * XXX In the long run, we may want to open-code it in order to separate the
 *     load from the wrtee, thus limiting the latency caused by the dependency
@@ -262,7 +493,8 @@ exc_##n##_bad_stack:							    \
 #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack)           \
        START_EXCEPTION(label);                                         \
        NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
-        EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE)             \
+        EXCEPTION_COMMON(trapnum)                                       \
+        INTS_DISABLE;                                                   \
        ack(r8);                                                        \
        CHECK_NAPPING();                                                \
        addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
@@ -283,8 +515,8 @@ exception_marker:
        .balign 0x1000
        .globl interrupt_base_book3e
 interrupt_base_book3e:                                  /* fake trap */
-        EXCEPTION_STUB(0x000, machine_check)            /* 0x0200 */
+        EXCEPTION_STUB(0x000, machine_check)
-        EXCEPTION_STUB(0x020, critical_input)           /* 0x0580 */
+        EXCEPTION_STUB(0x020, critical_input)           /* 0x0100 */
        EXCEPTION_STUB(0x040, debug_crit)               /* 0x0d00 */
        EXCEPTION_STUB(0x060, data_storage)             /* 0x0300 */
        EXCEPTION_STUB(0x080, instruction_storage)      /* 0x0400 */
@@ -299,8 +531,8 @@ interrupt_base_book3e:					/* fake trap */
        EXCEPTION_STUB(0x1a0, watchdog)                 /* 0x09f0 */
        EXCEPTION_STUB(0x1c0, data_tlb_miss)
        EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
-        EXCEPTION_STUB(0x200, altivec_unavailable)      /* 0x0f20 */
+        EXCEPTION_STUB(0x200, altivec_unavailable)
-        EXCEPTION_STUB(0x220, altivec_assist)           /* 0x1700 */
+        EXCEPTION_STUB(0x220, altivec_assist)
        EXCEPTION_STUB(0x260, perfmon)
        EXCEPTION_STUB(0x280, doorbell)
        EXCEPTION_STUB(0x2a0, doorbell_crit)
@@ -317,25 +549,25 @@ interrupt_end_book3e:
        START_EXCEPTION(critical_input);
        CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
                              PROLOG_ADDITION_NONE)
-//      EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE)
+        EXCEPTION_COMMON_CRIT(0x100)
-//      bl      special_reg_save_crit
+        bl      .save_nvgprs
-//      CHECK_NAPPING();
+        bl      special_reg_save
-//      addi    r3,r1,STACK_FRAME_OVERHEAD
+        CHECK_NAPPING();
-//      bl      .critical_exception
+        addi    r3,r1,STACK_FRAME_OVERHEAD
-//      b       ret_from_crit_except
+        bl      .unknown_exception
-        b       .
+        b       ret_from_crit_except
 /* Machine Check Interrupt */
        START_EXCEPTION(machine_check);
-        MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK,
+        MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
                            PROLOG_ADDITION_NONE)
-//      EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
+        EXCEPTION_COMMON_MC(0x000)
-//      bl      special_reg_save_mc
+        bl      .save_nvgprs
-//      addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      special_reg_save
-//      CHECK_NAPPING();
+        CHECK_NAPPING();
-//      bl      .machine_check_exception
+        addi    r3,r1,STACK_FRAME_OVERHEAD
-//      b       ret_from_mc_except
+        bl      .machine_check_exception
-        b       .
+        b       ret_from_mc_except
 /* Data Storage Interrupt */
        START_EXCEPTION(data_storage)
@@ -343,7 +575,8 @@ interrupt_end_book3e:
                                PROLOG_ADDITION_2REGS)
        mfspr   r14,SPRN_DEAR
        mfspr   r15,SPRN_ESR
-        EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE)
+        EXCEPTION_COMMON(0x300)
+        INTS_DISABLE
        b       storage_fault_common
 /* Instruction Storage Interrupt */
@@ -352,7 +585,8 @@ interrupt_end_book3e:
                                PROLOG_ADDITION_2REGS)
        li      r15,0
        mr      r14,r10
-        EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE)
+        EXCEPTION_COMMON(0x400)
+        INTS_DISABLE
        b       storage_fault_common
 /* External Input Interrupt */
@@ -365,7 +599,7 @@ interrupt_end_book3e:
                                PROLOG_ADDITION_2REGS)
        mfspr   r14,SPRN_DEAR
        mfspr   r15,SPRN_ESR
-        EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
+        EXCEPTION_COMMON(0x600)
        b       alignment_more  /* no room, go out of line */
 /* Program Interrupt */
@@ -373,7 +607,8 @@ interrupt_end_book3e:
        NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
                                PROLOG_ADDITION_1REG)
        mfspr   r14,SPRN_ESR
-        EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE)
+        EXCEPTION_COMMON(0x700)
+        INTS_DISABLE
        std     r14,_DSISR(r1)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        ld      r14,PACA_EXGEN+EX_R14(r13)
@@ -386,7 +621,7 @@ interrupt_end_book3e:
        NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
                                PROLOG_ADDITION_NONE)
        /* we can probably do a shorter exception entry for that one... */
-        EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
+        EXCEPTION_COMMON(0x800)
        ld      r12,_MSR(r1)
        andi.   r0,r12,MSR_PR;
        beq-    1f
@@ -403,7 +638,7 @@ interrupt_end_book3e:
        NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL,
                                PROLOG_ADDITION_NONE)
        /* we can probably do a shorter exception entry for that one... */
-        EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP)
+        EXCEPTION_COMMON(0x200)
 #ifdef CONFIG_ALTIVEC
 BEGIN_FTR_SECTION
        ld      r12,_MSR(r1)
@@ -425,7 +660,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        NORMAL_EXCEPTION_PROLOG(0x220,
                                BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST,
                                PROLOG_ADDITION_NONE)
-        EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE)
+        EXCEPTION_COMMON(0x220)
+        INTS_DISABLE
        bl      .save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
 #ifdef CONFIG_ALTIVEC
@@ -450,13 +686,17 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        START_EXCEPTION(watchdog);
        CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
                              PROLOG_ADDITION_NONE)
-//      EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE)
+        EXCEPTION_COMMON_CRIT(0x9f0)
-//      bl      special_reg_save_crit
+        bl      .save_nvgprs
-//      CHECK_NAPPING();
+        bl      special_reg_save
-//      addi    r3,r1,STACK_FRAME_OVERHEAD
+        CHECK_NAPPING();
-//      bl      .unknown_exception
+        addi    r3,r1,STACK_FRAME_OVERHEAD
-//      b       ret_from_crit_except
+#ifdef CONFIG_BOOKE_WDT
-        b       .
+        bl      .WatchdogException
+#else
+        bl      .unknown_exception
+#endif
+        b       ret_from_crit_except
 /* System Call Interrupt */
        START_EXCEPTION(system_call)
@@ -470,7 +710,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        START_EXCEPTION(ap_unavailable);
        NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
                                PROLOG_ADDITION_NONE)
-        EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE)
+        EXCEPTION_COMMON(0xf20)
+        INTS_DISABLE
        bl      .save_nvgprs
        addi    r3,r1,STACK_FRAME_OVERHEAD
        bl      .unknown_exception
@@ -513,7 +754,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        mtcr    r10
        ld      r10,PACA_EXCRIT+EX_R10(r13)     /* restore registers */
        ld      r11,PACA_EXCRIT+EX_R11(r13)
-        ld      r13,PACA_EXCRIT+EX_R13(r13)
+        mfspr   r13,SPRN_SPRG_CRIT_SCRATCH
        rfci
        /* Normal debug exception */
@@ -526,10 +767,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        /* Now we mash up things to make it look like we are coming on a
         * normal exception
         */
-        ld      r15,PACA_EXCRIT+EX_R13(r13)
-        mtspr   SPRN_SPRG_GEN_SCRATCH,r15
        mfspr   r14,SPRN_DBSR
-        EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE)
+        EXCEPTION_COMMON_CRIT(0xd00)
        std     r14,_DSISR(r1)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        mr      r4,r14
@@ -592,10 +831,9 @@ kernel_dbg_exc:
        /* Now we mash up things to make it look like we are coming on a
         * normal exception
         */
-        mfspr   r15,SPRN_SPRG_DBG_SCRATCH
-        mtspr   SPRN_SPRG_GEN_SCRATCH,r15
        mfspr   r14,SPRN_DBSR
-        EXCEPTION_COMMON(0xd08, PACA_EXDBG, INTS_DISABLE)
+        EXCEPTION_COMMON_DBG(0xd08)
+        INTS_DISABLE
        std     r14,_DSISR(r1)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        mr      r4,r14
@@ -608,7 +846,8 @@ kernel_dbg_exc:
        START_EXCEPTION(perfmon);
        NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
                                PROLOG_ADDITION_NONE)
-        EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE)
+        EXCEPTION_COMMON(0x260)
+        INTS_DISABLE
        CHECK_NAPPING()
        addi    r3,r1,STACK_FRAME_OVERHEAD
        bl      .performance_monitor_exception
@@ -622,13 +861,13 @@ kernel_dbg_exc:
        START_EXCEPTION(doorbell_crit);
        CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
                              PROLOG_ADDITION_NONE)
-//      EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE)
+        EXCEPTION_COMMON_CRIT(0x2a0)
-//      bl      special_reg_save_crit
+        bl      .save_nvgprs
-//      CHECK_NAPPING();
+        bl      special_reg_save
-//      addi    r3,r1,STACK_FRAME_OVERHEAD
+        CHECK_NAPPING();
-//      bl      .doorbell_critical_exception
+        addi    r3,r1,STACK_FRAME_OVERHEAD
-//      b       ret_from_crit_except
+        bl      .unknown_exception
-        b       .
+        b       ret_from_crit_except
 /*
 *      Guest doorbell interrupt
@@ -637,7 +876,7 @@ kernel_dbg_exc:
        START_EXCEPTION(guest_doorbell);
        GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
                                PROLOG_ADDITION_NONE)
-        EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
+        EXCEPTION_COMMON(0x2c0)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        bl      .save_nvgprs
        INTS_RESTORE_HARD
@@ -648,19 +887,19 @@ kernel_dbg_exc:
        START_EXCEPTION(guest_doorbell_crit);
        CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
                              PROLOG_ADDITION_NONE)
-//      EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE)
+        EXCEPTION_COMMON_CRIT(0x2e0)
-//      bl      special_reg_save_crit
+        bl      .save_nvgprs
-//      CHECK_NAPPING();
+        bl      special_reg_save
-//      addi    r3,r1,STACK_FRAME_OVERHEAD
+        CHECK_NAPPING();
-//      bl      .guest_doorbell_critical_exception
+        addi    r3,r1,STACK_FRAME_OVERHEAD
-//      b       ret_from_crit_except
+        bl      .unknown_exception
-        b       .
+        b       ret_from_crit_except
 /* Hypervisor call */
        START_EXCEPTION(hypercall);
        NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
                                PROLOG_ADDITION_NONE)
-        EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP)
+        EXCEPTION_COMMON(0x310)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        bl      .save_nvgprs
        INTS_RESTORE_HARD
@@ -671,7 +910,7 @@ kernel_dbg_exc:
        START_EXCEPTION(ehpriv);
        NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
                                PROLOG_ADDITION_NONE)
-        EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP)
+        EXCEPTION_COMMON(0x320)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        bl      .save_nvgprs
        INTS_RESTORE_HARD
@@ -682,7 +921,7 @@ kernel_dbg_exc:
        START_EXCEPTION(lrat_error);
        NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
                                PROLOG_ADDITION_NONE)
-        EXCEPTION_COMMON(0x340, PACA_EXGEN, INTS_KEEP)
+        EXCEPTION_COMMON(0x340)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        bl      .save_nvgprs
        INTS_RESTORE_HARD
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 38d507306a11..3afd3915921a 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -54,14 +54,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)				\
        xori    r12,r12,MSR_LE ;                                \
        mtspr   SPRN_SRR1,r12 ;                                 \
        rfid ;          /* return to userspace */               \
-        b       . ;                                             \
-2:      mfspr   r12,SPRN_SRR1 ;                                 \
-        andi.   r12,r12,MSR_PR ;                                \
-        bne     0b ;                                            \
-        mtspr   SPRN_SRR0,r3 ;                                  \
-        mtspr   SPRN_SRR1,r4 ;                                  \
-        mtspr   SPRN_SDR1,r5 ;                                  \
-        rfid ;                                                  \
        b       . ;     /* prevent speculative execution */
 #if defined(CONFIG_RELOCATABLE)
@@ -121,9 +113,10 @@ BEGIN_FTR_SECTION
        cmpwi   cr1,r13,2
        /* Total loss of HV state is fatal, we could try to use the
         * PIR to locate a PACA, then use an emergency stack etc...
-         * but for now, let's just stay stuck here
+         * OPAL v3 based powernv platforms have new idle states
+         * which fall in this catagory.
         */
-        bgt     cr1,.
+        bgt     cr1,8f
        GET_PACA(r13)
 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
@@ -141,6 +134,11 @@ BEGIN_FTR_SECTION
        beq     cr1,2f
        b       .power7_wakeup_noloss
 2:      b       .power7_wakeup_loss
+        /* Fast Sleep wakeup on PowerNV */
+8:      GET_PACA(r13)
+        b       .power7_wakeup_tb_loss
 9:
 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 #endif /* CONFIG_PPC_P7_NAP */
@@ -164,13 +162,18 @@ BEGIN_FTR_SECTION
         */
        mfspr   r13,SPRN_SRR1
        rlwinm. r13,r13,47-31,30,31
+        OPT_GET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR)
        beq     9f
+        mfspr   r13,SPRN_SRR1
+        rlwinm. r13,r13,47-31,30,31
        /* waking up from powersave (nap) state */
        cmpwi   cr1,r13,2
        /* Total loss of HV state is fatal. let's just stay stuck here */
+        OPT_GET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR)
        bgt     cr1,.
 9:
+        OPT_SET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR)
 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
 #endif /* CONFIG_PPC_P7_NAP */
        EXCEPTION_PROLOG_0(PACA_EXMC)
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
index b0ded97ee4e1..6a014c763cc7 100644
--- a/arch/powerpc/kernel/ftrace.c
+++ b/arch/powerpc/kernel/ftrace.c
@@ -532,13 +532,8 @@ void arch_ftrace_update_code(int command)
                ftrace_disable_ftrace_graph_caller();
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        /* caller expects data to be zero */
-        unsigned long *p = data;
-        *p = 0;
        return 0;
 }
 #endif /* CONFIG_DYNAMIC_FTRACE */
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 3fdef0f0c67f..c3ab86975614 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -17,20 +17,31 @@
 #include <asm/ppc-opcode.h>
 #include <asm/hw_irq.h>
 #include <asm/kvm_book3s_asm.h>
+#include <asm/opal.h>
 #undef DEBUG
-        .text
+/* Idle state entry routines */
-_GLOBAL(power7_idle)
+#define IDLE_STATE_ENTER_SEQ(IDLE_INST)                         \
-        /* Now check if user or arch enabled NAP mode */
+        /* Magic NAP/SLEEP/WINKLE mode enter sequence */        \
-        LOAD_REG_ADDRBASE(r3,powersave_nap)
+        std     r0,0(r1);                                       \
-        lwz     r4,ADDROFF(powersave_nap)(r3)
+        ptesync;                                                \
-        cmpwi   0,r4,0
+        ld      r0,0(r1);                                       \
-        beqlr
+1:      cmp     cr0,r0,r0;                                      \
-        /* fall through */
+        bne     1b;                                             \
+        IDLE_INST;                                              \
+        b       .
-_GLOBAL(power7_nap)
+        .text
+/*
+ * Pass requested state in r3:
+ *      0 - nap
+ *      1 - sleep
+ */
+_GLOBAL(power7_powersave_common)
+        /* Use r3 to pass state nap/sleep/winkle */
        /* NAP is a state loss, we create a regs frame on the
         * stack, fill it up with the state we care about and
         * stick a pointer to it in PACAR1. We really only
@@ -79,8 +90,8 @@ _GLOBAL(power7_nap)
        /* Continue saving state */
        SAVE_GPR(2, r1)
        SAVE_NVGPRS(r1)
-        mfcr    r3
+        mfcr    r4
-        std     r3,_CCR(r1)
+        std     r4,_CCR(r1)
        std     r9,_MSR(r1)
        std     r1,PACAR1(r13)
@@ -90,15 +101,56 @@ _GLOBAL(power7_enter_nap_mode)
        li      r4,KVM_HWTHREAD_IN_NAP
        stb     r4,HSTATE_HWTHREAD_STATE(r13)
 #endif
+        cmpwi   cr0,r3,1
+        beq     2f
+        IDLE_STATE_ENTER_SEQ(PPC_NAP)
+        /* No return */
+2:      IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
+        /* No return */
-        /* Magic NAP mode enter sequence */
+_GLOBAL(power7_idle)
-        std     r0,0(r1)
+        /* Now check if user or arch enabled NAP mode */
-        ptesync
+        LOAD_REG_ADDRBASE(r3,powersave_nap)
-        ld      r0,0(r1)
+        lwz     r4,ADDROFF(powersave_nap)(r3)
-1:      cmp     cr0,r0,r0
+        cmpwi   0,r4,0
-        bne     1b
+        beqlr
-        PPC_NAP
+        /* fall through */
-        b       .
+_GLOBAL(power7_nap)
+        li      r3,0
+        b       power7_powersave_common
+        /* No return */
+_GLOBAL(power7_sleep)
+        li      r3,1
+        b       power7_powersave_common
+        /* No return */
+_GLOBAL(power7_wakeup_tb_loss)
+        ld      r2,PACATOC(r13);
+        ld      r1,PACAR1(r13)
+        /* Time base re-sync */
+        li      r0,OPAL_RESYNC_TIMEBASE
+        LOAD_REG_ADDR(r11,opal);
+        ld      r12,8(r11);
+        ld      r2,0(r11);
+        mtctr   r12
+        bctrl
+        /* TODO: Check r3 for failure */
+        REST_NVGPRS(r1)
+        REST_GPR(2, r1)
+        ld      r3,_CCR(r1)
+        ld      r4,_MSR(r1)
+        ld      r5,_NIP(r1)
+        addi    r1,r1,INT_FRAME_SIZE
+        mtcr    r3
+        mfspr   r3,SPRN_SRR1            /* Return SRR1 */
+        mtspr   SPRN_SRR1,r4
+        mtspr   SPRN_SRR0,r5
+        rfid
 _GLOBAL(power7_wakeup_loss)
        ld      r1,PACAR1(r13)
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index cadef7e64e42..a7fd4cb78b78 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -70,7 +70,7 @@ static void mce_set_error_info(struct machine_check_event *mce,
 */
 void save_mce_event(struct pt_regs *regs, long handled,
                    struct mce_error_info *mce_err,
-                    uint64_t addr)
+                    uint64_t nip, uint64_t addr)
 {
        uint64_t srr1;
        int index = __get_cpu_var(mce_nest_count)++;
@@ -86,7 +86,7 @@ void save_mce_event(struct pt_regs *regs, long handled,
        /* Populate generic machine check info */
        mce->version = MCE_V1;
-        mce->srr0 = regs->nip;
+        mce->srr0 = nip;
        mce->srr1 = regs->msr;
        mce->gpr3 = regs->gpr[3];
        mce->in_use = 1;
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
index 27c93f41166f..aa9aff3d6ad3 100644
--- a/arch/powerpc/kernel/mce_power.c
+++ b/arch/powerpc/kernel/mce_power.c
@@ -26,6 +26,7 @@
 #include <linux/ptrace.h>
 #include <asm/mmu.h>
 #include <asm/mce.h>
+#include <asm/machdep.h>
 /* flush SLBs and reload */
 static void flush_and_reload_slb(void)
@@ -197,13 +198,32 @@ static void mce_get_derror_p7(struct mce_error_info *mce_err, uint64_t dsisr)
        }
 }
+static long mce_handle_ue_error(struct pt_regs *regs)
+{
+        long handled = 0;
+        /*
+         * On specific SCOM read via MMIO we may get a machine check
+         * exception with SRR0 pointing inside opal. If that is the
+         * case OPAL may have recovery address to re-read SCOM data in
+         * different way and hence we can recover from this MC.
+         */
+        if (ppc_md.mce_check_early_recovery) {
+                if (ppc_md.mce_check_early_recovery(regs))
+                        handled = 1;
+        }
+        return handled;
+}
 long __machine_check_early_realmode_p7(struct pt_regs *regs)
 {
-        uint64_t srr1, addr;
+        uint64_t srr1, nip, addr;
        long handled = 1;
        struct mce_error_info mce_error_info = { 0 };
        srr1 = regs->msr;
+        nip = regs->nip;
        /*
         * Handle memory errors depending whether this was a load/store or
@@ -221,7 +241,11 @@ long __machine_check_early_realmode_p7(struct pt_regs *regs)
                addr = regs->nip;
        }
-        save_mce_event(regs, handled, &mce_error_info, addr);
+        /* Handle UE error. */
+        if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
+                handled = mce_handle_ue_error(regs);
+        save_mce_event(regs, handled, &mce_error_info, nip, addr);
        return handled;
 }
@@ -263,11 +287,12 @@ static long mce_handle_derror_p8(uint64_t dsisr)
 long __machine_check_early_realmode_p8(struct pt_regs *regs)
 {
-        uint64_t srr1, addr;
+        uint64_t srr1, nip, addr;
        long handled = 1;
        struct mce_error_info mce_error_info = { 0 };
        srr1 = regs->msr;
+        nip = regs->nip;
        if (P7_SRR1_MC_LOADSTORE(srr1)) {
                handled = mce_handle_derror_p8(regs->dsisr);
@@ -279,6 +304,10 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs)
                addr = regs->nip;
        }
-        save_mce_event(regs, handled, &mce_error_info, addr);
+        /* Handle UE error. */
+        if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
+                handled = mce_handle_ue_error(regs);
+        save_mce_event(regs, handled, &mce_error_info, nip, addr);
        return handled;
 }
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index bf0aada02fe4..ad302f845e5d 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -152,7 +152,8 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
        new_paca->paca_index = cpu;
        new_paca->kernel_toc = kernel_toc;
        new_paca->kernelbase = (unsigned long) _stext;
-        new_paca->kernel_msr = MSR_KERNEL;
+        /* Only set MSR:IR/DR when MMU is initialized */
+        new_paca->kernel_msr = MSR_KERNEL & ~(MSR_IR | MSR_DR);
        new_paca->hw_cpu_id = 0xffff;
        new_paca->kexec_state = KEXEC_STATE_NONE;
        new_paca->__current = &init_task;
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index a9e311f7a9dd..2a4779091a58 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -208,7 +208,6 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus,
                          unsigned long in_devfn)
 {
        struct pci_controller* hose;
-        struct list_head *ln;
        struct pci_bus *bus = NULL;
        struct device_node *hose_node;
@@ -230,8 +229,7 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus,
         * used on pre-domains setup. We return the first match
         */
-        for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
+        list_for_each_entry(bus, &pci_root_buses, node) {
-                bus = pci_bus_b(ln);
                if (in_bus >= bus->number && in_bus <= bus->busn_res.end)
                        break;
                bus = NULL;
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index af064d28b365..31d021506d21 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -610,6 +610,31 @@ out_and_saveregs:
        tm_save_sprs(thr);
 }
+extern void __tm_recheckpoint(struct thread_struct *thread,
+                              unsigned long orig_msr);
+void tm_recheckpoint(struct thread_struct *thread,
+                     unsigned long orig_msr)
+{
+        unsigned long flags;
+        /* We really can't be interrupted here as the TEXASR registers can't
+         * change and later in the trecheckpoint code, we have a userspace R1.
+         * So let's hard disable over this region.
+         */
+        local_irq_save(flags);
+        hard_irq_disable();
+        /* The TM SPRs are restored here, so that TEXASR.FS can be set
+         * before the trecheckpoint and no explosion occurs.
+         */
+        tm_restore_sprs(thread);
+        __tm_recheckpoint(thread, orig_msr);
+        local_irq_restore(flags);
+}
 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 {
        unsigned long msr;
@@ -628,13 +653,10 @@ static inline void tm_recheckpoint_new_task(struct task_struct *new)
        if (!new->thread.regs)
                return;
-        /* The TM SPRs are restored here, so that TEXASR.FS can be set
+        if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
-         * before the trecheckpoint and no explosion occurs.
+                tm_restore_sprs(&new->thread);
-         */
-        tm_restore_sprs(&new->thread);
-        if (!MSR_TM_ACTIVE(new->thread.regs->msr))
                return;
+        }
        msr = new->thread.tm_orig_msr;
        /* Recheckpoint to restore original checkpointed register state. */
        TM_DEBUG("*** tm_recheckpoint of pid %d "
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index f58c0d3aaeb4..668aa4791fd7 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -33,6 +33,7 @@
 #include <linux/irq.h>
 #include <linux/memblock.h>
 #include <linux/of.h>
+#include <linux/of_fdt.h>
 #include <asm/prom.h>
 #include <asm/rtas.h>
@@ -346,45 +347,45 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
 #endif
        }
-        if (found >= 0) {
+        /* Not the boot CPU */
-                DBG("boot cpu: logical %d physical %d\n", found,
+        if (found < 0)
-                        be32_to_cpu(intserv[found_thread]));
+                return 0;
-                boot_cpuid = found;
-                set_hard_smp_processor_id(found,
-                        be32_to_cpu(intserv[found_thread]));
-                /*
+        DBG("boot cpu: logical %d physical %d\n", found,
-                 * PAPR defines "logical" PVR values for cpus that
+            be32_to_cpu(intserv[found_thread]));
-                 * meet various levels of the architecture:
+        boot_cpuid = found;
-                 * 0x0f000001   Architecture version 2.04
+        set_hard_smp_processor_id(found, be32_to_cpu(intserv[found_thread]));
-                 * 0x0f000002   Architecture version 2.05
-                 * If the cpu-version property in the cpu node contains
-                 * such a value, we call identify_cpu again with the
-                 * logical PVR value in order to use the cpu feature
-                 * bits appropriate for the architecture level.
-                 *
-                 * A POWER6 partition in "POWER6 architected" mode
-                 * uses the 0x0f000002 PVR value; in POWER5+ mode
-                 * it uses 0x0f000001.
-                 */
-                prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
-                if (prop && (be32_to_cpup(prop) & 0xff000000) == 0x0f000000)
-                        identify_cpu(0, be32_to_cpup(prop));
-                identical_pvr_fixup(node);
+        /*
-        }
+         * PAPR defines "logical" PVR values for cpus that
+         * meet various levels of the architecture:
+         * 0x0f000001   Architecture version 2.04
+         * 0x0f000002   Architecture version 2.05
+         * If the cpu-version property in the cpu node contains
+         * such a value, we call identify_cpu again with the
+         * logical PVR value in order to use the cpu feature
+         * bits appropriate for the architecture level.
+         *
+         * A POWER6 partition in "POWER6 architected" mode
+         * uses the 0x0f000002 PVR value; in POWER5+ mode
+         * it uses 0x0f000001.
+         */
+        prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
+        if (prop && (be32_to_cpup(prop) & 0xff000000) == 0x0f000000)
+                identify_cpu(0, be32_to_cpup(prop));
+        identical_pvr_fixup(node);
        check_cpu_feature_properties(node);
        check_cpu_pa_features(node);
        check_cpu_slb_size(node);
-#ifdef CONFIG_PPC_PSERIES
+#ifdef CONFIG_PPC64
        if (nthreads > 1)
                cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
        else
                cur_cpu_spec->cpu_features &= ~CPU_FTR_SMT;
 #endif
        return 0;
 }
@@ -588,6 +589,8 @@ static void __init early_reserve_mem_dt(void)
                        memblock_reserve(base, size);
                }
        }
+        early_init_fdt_scan_reserved_mem();
 }
 static void __init early_reserve_mem(void)
@@ -744,6 +747,10 @@ void __init early_init_devtree(void *params)
         * (altivec support, boot CPU ID, ...)
         */
        of_scan_flat_dt(early_init_dt_scan_cpus, NULL);
+        if (boot_cpuid < 0) {
+                printk("Failed to indentify boot CPU !\n");
+                BUG();
+        }
 #if defined(CONFIG_SMP) && defined(CONFIG_PPC64)
        /* We'll later wait for secondaries to check in; there are
@@ -752,6 +759,11 @@ void __init early_init_devtree(void *params)
        spinning_secondaries = boot_cpu_count - 1;
 #endif
+#ifdef CONFIG_PPC_POWERNV
+        /* Scan and build the list of machine check recoverable ranges */
+        of_scan_flat_dt(early_init_dt_scan_recoverable_ranges, NULL);
+#endif
        DBG(" <- early_init_devtree()\n");
 }
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index 4cf674d7d5ae..8cd5ed049b5d 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -993,32 +993,36 @@ struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log,
                (struct rtas_ext_event_log_v6 *)log->buffer;
        struct pseries_errorlog *sect;
        unsigned char *p, *log_end;
+        uint32_t ext_log_length = rtas_error_extended_log_length(log);
+        uint8_t log_format = rtas_ext_event_log_format(ext_log);
+        uint32_t company_id = rtas_ext_event_company_id(ext_log);
        /* Check that we understand the format */
-        if (log->extended_log_length < sizeof(struct rtas_ext_event_log_v6) ||
+        if (ext_log_length < sizeof(struct rtas_ext_event_log_v6) ||
-            ext_log->log_format != RTAS_V6EXT_LOG_FORMAT_EVENT_LOG ||
+            log_format != RTAS_V6EXT_LOG_FORMAT_EVENT_LOG ||
-            ext_log->company_id != RTAS_V6EXT_COMPANY_ID_IBM)
+            company_id != RTAS_V6EXT_COMPANY_ID_IBM)
                return NULL;
-        log_end = log->buffer + log->extended_log_length;
+        log_end = log->buffer + ext_log_length;
        p = ext_log->vendor_log;
        while (p < log_end) {
                sect = (struct pseries_errorlog *)p;
-                if (sect->id == section_id)
+                if (pseries_errorlog_id(sect) == section_id)
                        return sect;
-                p += sect->length;
+                p += pseries_errorlog_length(sect);
        }
        return NULL;
 }
+/* We assume to be passed big endian arguments */
 asmlinkage int ppc_rtas(struct rtas_args __user *uargs)
 {
        struct rtas_args args;
        unsigned long flags;
        char *buff_copy, *errbuf = NULL;
-        int nargs;
+        int nargs, nret, token;
        int rc;
        if (!capable(CAP_SYS_ADMIN))
@@ -1027,10 +1031,13 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs)
        if (copy_from_user(&args, uargs, 3 * sizeof(u32)) != 0)
                return -EFAULT;
-        nargs = args.nargs;
+        nargs = be32_to_cpu(args.nargs);
+        nret  = be32_to_cpu(args.nret);
+        token = be32_to_cpu(args.token);
        if (nargs > ARRAY_SIZE(args.args)
-            || args.nret > ARRAY_SIZE(args.args)
+            || nret > ARRAY_SIZE(args.args)
-            || nargs + args.nret > ARRAY_SIZE(args.args))
+            || nargs + nret > ARRAY_SIZE(args.args))
                return -EINVAL;
        /* Copy in args. */
@@ -1038,14 +1045,14 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs)
                           nargs * sizeof(rtas_arg_t)) != 0)
                return -EFAULT;
-        if (args.token == RTAS_UNKNOWN_SERVICE)
+        if (token == RTAS_UNKNOWN_SERVICE)
                return -EINVAL;
        args.rets = &args.args[nargs];
-        memset(args.rets, 0, args.nret * sizeof(rtas_arg_t));
+        memset(args.rets, 0, nret * sizeof(rtas_arg_t));
        /* Need to handle ibm,suspend_me call specially */
-        if (args.token == ibm_suspend_me_token) {
+        if (token == ibm_suspend_me_token) {
                rc = rtas_ibm_suspend_me(&args);
                if (rc)
                        return rc;
@@ -1062,7 +1069,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs)
        /* A -1 return code indicates that the last command couldn't
           be completed due to a hardware error. */
-        if (args.rets[0] == -1)
+        if (be32_to_cpu(args.rets[0]) == -1)
                errbuf = __fetch_rtas_last_error(buff_copy);
        unlock_rtas(flags);
@@ -1077,7 +1084,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs)
        /* Copy out args. */
        if (copy_to_user(uargs->args + nargs,
                         args.args + nargs,
-                         args.nret * sizeof(rtas_arg_t)) != 0)
+                         nret * sizeof(rtas_arg_t)) != 0)
                return -EFAULT;
        return 0;
diff --git a/arch/powerpc/kernel/rtasd.c b/arch/powerpc/kernel/rtasd.c
index 1130c53ad652..e736387fee6a 100644
--- a/arch/powerpc/kernel/rtasd.c
+++ b/arch/powerpc/kernel/rtasd.c
@@ -150,8 +150,8 @@ static void printk_log_rtas(char *buf, int len)
                struct rtas_error_log *errlog = (struct rtas_error_log *)buf;
                printk(RTAS_DEBUG "event: %d, Type: %s, Severity: %d\n",
-                       error_log_cnt, rtas_event_type(errlog->type),
+                       error_log_cnt, rtas_event_type(rtas_error_type(errlog)),
-                       errlog->severity);
+                       rtas_error_severity(errlog));
        }
 }
@@ -159,14 +159,16 @@ static int log_rtas_len(char * buf)
 {
        int len;
        struct rtas_error_log *err;
+        uint32_t extended_log_length;
        /* rtas fixed header */
        len = 8;
        err = (struct rtas_error_log *)buf;
-        if (err->extended && err->extended_log_length) {
+        extended_log_length = rtas_error_extended_log_length(err);
+        if (rtas_error_extended(err) && extended_log_length) {
                /* extended header */
-                len += err->extended_log_length;
+                len += extended_log_length;
        }
        if (rtas_error_log_max == 0)
@@ -293,15 +295,13 @@ void prrn_schedule_update(u32 scope)
 static void handle_rtas_event(const struct rtas_error_log *log)
 {
-        if (log->type == RTAS_TYPE_PRRN) {
+        if (rtas_error_type(log) != RTAS_TYPE_PRRN || !prrn_is_enabled())
-                /* For PRRN Events the extended log length is used to denote
+                return;
-                 * the scope for calling rtas update-nodes.
-                 */
-                if (prrn_is_enabled())
-                        prrn_schedule_update(log->extended_log_length);
-        }
-        return;
+        /* For PRRN Events the extended log length is used to denote
+         * the scope for calling rtas update-nodes.
+         */
+        prrn_schedule_update(rtas_error_extended_log_length(log));
 }
 #else
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index bc76cc6b419c..79b7612ac6fa 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -76,6 +76,9 @@ EXPORT_SYMBOL(ppc_md);
 struct machdep_calls *machine_id;
 EXPORT_SYMBOL(machine_id);
+int boot_cpuid = -1;
+EXPORT_SYMBOL_GPL(boot_cpuid);
 unsigned long klimit = (unsigned long) _end;
 char cmd_line[COMMAND_LINE_SIZE];
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 04cc4fcca78b..ea4fda60e57b 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -44,8 +44,6 @@
 extern void bootx_init(unsigned long r4, unsigned long phys);
-int boot_cpuid = -1;
-EXPORT_SYMBOL_GPL(boot_cpuid);
 int boot_cpuid_phys;
 EXPORT_SYMBOL_GPL(boot_cpuid_phys);
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index f5f11a7d30e5..fbe24377eda3 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -74,7 +74,6 @@
 #define DBG(fmt...)
 #endif
-int boot_cpuid = 0;
 int spinning_secondaries;
 u64 ppc64_pft_size;
@@ -102,6 +101,8 @@ static void setup_tlb_core_data(void)
 {
        int cpu;
+        BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
        for_each_possible_cpu(cpu) {
                int first = cpu_first_thread_sibling(cpu);
@@ -194,6 +195,19 @@ static void fixup_boot_paca(void)
        get_paca()->data_offset = 0;
 }
+static void cpu_ready_for_interrupts(void)
+{
+        /* Set IR and DR in PACA MSR */
+        get_paca()->kernel_msr = MSR_KERNEL;
+        /* Enable AIL if supported */
+        if (cpu_has_feature(CPU_FTR_HVMODE) &&
+            cpu_has_feature(CPU_FTR_ARCH_207S)) {
+                unsigned long lpcr = mfspr(SPRN_LPCR);
+                mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
+        }
+}
 /*
 * Early initialization entry point. This is called by head.S
 * with MMU translation disabled. We rely on the "feature" of
@@ -260,6 +274,14 @@ void __init early_setup(unsigned long dt_ptr)
        /* Initialize the hash table or TLB handling */
        early_init_mmu();
+        /*
+         * At this point, we can let interrupts switch to virtual mode
+         * (the MMU has been setup), so adjust the MSR in the PACA to
+         * have IR and DR set and enable AIL if it exists
+         */
+        cpu_ready_for_interrupts();
+        /* Reserve large chunks of memory for use by CMA for KVM */
        kvm_cma_reserve();
        /*
@@ -292,6 +314,13 @@ void early_setup_secondary(void)
        /* Initialize the hash table or TLB handling */
        early_init_mmu_secondary();
+        /*
+         * At this point, we can let interrupts switch to virtual mode
+         * (the MMU has been setup), so adjust the MSR in the PACA to
+         * have IR and DR set.
+         */
+        cpu_ready_for_interrupts();
 }
 #endif /* CONFIG_SMP */
@@ -552,14 +581,20 @@ static void __init irqstack_early_init(void)
 static void __init exc_lvl_early_init(void)
 {
        unsigned int i;
+        unsigned long sp;
        for_each_possible_cpu(i) {
-                critirq_ctx[i] = (struct thread_info *)
+                sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
-                        __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
+                critirq_ctx[i] = (struct thread_info *)__va(sp);
-                dbgirq_ctx[i] = (struct thread_info *)
+                paca[i].crit_kstack = __va(sp + THREAD_SIZE);
-                        __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
-                mcheckirq_ctx[i] = (struct thread_info *)
+                sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
-                        __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
+                dbgirq_ctx[i] = (struct thread_info *)__va(sp);
+                paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
+                sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
+                mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
+                paca[i].mc_kstack = __va(sp + THREAD_SIZE);
        }
        if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index a67e00aa3caa..4e47db686b5d 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -881,6 +881,8 @@ static long restore_tm_user_regs(struct pt_regs *regs,
         * transactional versions should be loaded.
         */
        tm_enable();
+        /* Make sure the transaction is marked as failed */
+        current->thread.tm_texasr |= TEXASR_FS;
        /* This loads the checkpointed FP/VEC state, if used */
        tm_recheckpoint(&current->thread, msr);
        /* Get the top half of the MSR */
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index 8d253c29649b..d501dc4dc3e6 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -527,6 +527,8 @@ static long restore_tm_sigcontexts(struct pt_regs *regs,
        }
 #endif
        tm_enable();
+        /* Make sure the transaction is marked as failed */
+        current->thread.tm_texasr |= TEXASR_FS;
        /* This loads the checkpointed FP/VEC state, if used */
        tm_recheckpoint(&current->thread, msr);
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index ac2621af3154..e2a4232c5871 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -35,6 +35,7 @@
 #include <asm/ptrace.h>
 #include <linux/atomic.h>
 #include <asm/irq.h>
+#include <asm/hw_irq.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/prom.h>
@@ -145,9 +146,9 @@ static irqreturn_t reschedule_action(int irq, void *data)
        return IRQ_HANDLED;
 }
-static irqreturn_t call_function_single_action(int irq, void *data)
+static irqreturn_t tick_broadcast_ipi_action(int irq, void *data)
 {
-        generic_smp_call_function_single_interrupt();
+        tick_broadcast_ipi_handler();
        return IRQ_HANDLED;
 }
@@ -168,14 +169,14 @@ static irqreturn_t debug_ipi_action(int irq, void *data)
 static irq_handler_t smp_ipi_action[] = {
        [PPC_MSG_CALL_FUNCTION] =  call_function_action,
        [PPC_MSG_RESCHEDULE] = reschedule_action,
-        [PPC_MSG_CALL_FUNC_SINGLE] = call_function_single_action,
+        [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action,
        [PPC_MSG_DEBUGGER_BREAK] = debug_ipi_action,
 };
 const char *smp_ipi_name[] = {
        [PPC_MSG_CALL_FUNCTION] =  "ipi call function",
        [PPC_MSG_RESCHEDULE] = "ipi reschedule",
-        [PPC_MSG_CALL_FUNC_SINGLE] = "ipi call function single",
+        [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast",
        [PPC_MSG_DEBUGGER_BREAK] = "ipi debugger",
 };
@@ -251,8 +252,8 @@ irqreturn_t smp_ipi_demux(void)
                        generic_smp_call_function_interrupt();
                if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE))
                        scheduler_ipi();
-                if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNC_SINGLE))
+                if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST))
-                        generic_smp_call_function_single_interrupt();
+                        tick_broadcast_ipi_handler();
                if (all & IPI_MESSAGE(PPC_MSG_DEBUGGER_BREAK))
                        debug_ipi_action(0, NULL);
        } while (info->messages);
@@ -280,7 +281,7 @@ EXPORT_SYMBOL_GPL(smp_send_reschedule);
 void arch_send_call_function_single_ipi(int cpu)
 {
-        do_message_pass(cpu, PPC_MSG_CALL_FUNC_SINGLE);
+        do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
 }
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
@@ -291,6 +292,16 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask)
                do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
 }
+#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
+void tick_broadcast(const struct cpumask *mask)
+{
+        unsigned int cpu;
+        for_each_cpu(cpu, mask)
+                do_message_pass(cpu, PPC_MSG_TICK_BROADCAST);
+}
+#endif
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 void smp_send_debugger_break(void)
 {
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 97e1dc917683..d90d4b7810d6 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -975,7 +975,8 @@ static int __init topology_init(void)
        int cpu;
        register_nodes();
-        register_cpu_notifier(&sysfs_cpu_nb);
+        cpu_notifier_register_begin();
        for_each_possible_cpu(cpu) {
                struct cpu *c = &per_cpu(cpu_devices, cpu);
@@ -999,6 +1000,11 @@ static int __init topology_init(void)
                if (cpu_online(cpu))
                        register_cpu_online(cpu);
        }
+        __register_cpu_notifier(&sysfs_cpu_nb);
+        cpu_notifier_register_done();
 #ifdef CONFIG_PPC64
        sysfs_create_dscr_default();
 #endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index b3dab20acf34..122a580f7322 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -42,6 +42,7 @@
 #include <linux/timex.h>
 #include <linux/kernel_stat.h>
 #include <linux/time.h>
+#include <linux/clockchips.h>
 #include <linux/init.h>
 #include <linux/profile.h>
 #include <linux/cpu.h>
@@ -106,7 +107,7 @@ struct clock_event_device decrementer_clockevent = {
        .irq            = 0,
        .set_next_event = decrementer_set_next_event,
        .set_mode       = decrementer_set_mode,
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP,
 };
 EXPORT_SYMBOL(decrementer_clockevent);
@@ -478,6 +479,47 @@ void arch_irq_work_raise(void)
 #endif /* CONFIG_IRQ_WORK */
+void __timer_interrupt(void)
+{
+        struct pt_regs *regs = get_irq_regs();
+        u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
+        struct clock_event_device *evt = &__get_cpu_var(decrementers);
+        u64 now;
+        trace_timer_interrupt_entry(regs);
+        if (test_irq_work_pending()) {
+                clear_irq_work_pending();
+                irq_work_run();
+        }
+        now = get_tb_or_rtc();
+        if (now >= *next_tb) {
+                *next_tb = ~(u64)0;
+                if (evt->event_handler)
+                        evt->event_handler(evt);
+                __get_cpu_var(irq_stat).timer_irqs_event++;
+        } else {
+                now = *next_tb - now;
+                if (now <= DECREMENTER_MAX)
+                        set_dec((int)now);
+                /* We may have raced with new irq work */
+                if (test_irq_work_pending())
+                        set_dec(1);
+                __get_cpu_var(irq_stat).timer_irqs_others++;
+        }
+#ifdef CONFIG_PPC64
+        /* collect purr register values often, for accurate calculations */
+        if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
+                struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
+                cu->current_tb = mfspr(SPRN_PURR);
+        }
+#endif
+        trace_timer_interrupt_exit(regs);
+}
 /*
 * timer_interrupt - gets called when the decrementer overflows,
 * with interrupts disabled.
@@ -486,8 +528,6 @@ void timer_interrupt(struct pt_regs * regs)
 {
        struct pt_regs *old_regs;
        u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
-        struct clock_event_device *evt = &__get_cpu_var(decrementers);
-        u64 now;
        /* Ensure a positive value is written to the decrementer, or else
         * some CPUs will continue to take decrementer exceptions.
@@ -519,39 +559,7 @@ void timer_interrupt(struct pt_regs * regs)
        old_regs = set_irq_regs(regs);
        irq_enter();
-        trace_timer_interrupt_entry(regs);
+        __timer_interrupt();
-        if (test_irq_work_pending()) {
-                clear_irq_work_pending();
-                irq_work_run();
-        }
-        now = get_tb_or_rtc();
-        if (now >= *next_tb) {
-                *next_tb = ~(u64)0;
-                if (evt->event_handler)
-                        evt->event_handler(evt);
-                __get_cpu_var(irq_stat).timer_irqs_event++;
-        } else {
-                now = *next_tb - now;
-                if (now <= DECREMENTER_MAX)
-                        set_dec((int)now);
-                /* We may have raced with new irq work */
-                if (test_irq_work_pending())
-                        set_dec(1);
-                __get_cpu_var(irq_stat).timer_irqs_others++;
-        }
-#ifdef CONFIG_PPC64
-        /* collect purr register values often, for accurate calculations */
-        if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
-                struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array);
-                cu->current_tb = mfspr(SPRN_PURR);
-        }
-#endif
-        trace_timer_interrupt_exit(regs);
        irq_exit();
        set_irq_regs(old_regs);
 }
@@ -825,6 +833,15 @@ static void decrementer_set_mode(enum clock_event_mode mode,
                decrementer_set_next_event(DECREMENTER_MAX, dev);
 }
+/* Interrupt handler for the timer broadcast IPI */
+void tick_broadcast_ipi_handler(void)
+{
+        u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
+        *next_tb = get_tb_or_rtc();
+        __timer_interrupt();
+}
 static void register_decrementer_clockevent(int cpu)
 {
        struct clock_event_device *dec = &per_cpu(decrementers, cpu);
@@ -928,6 +945,7 @@ void __init time_init(void)
        clocksource_init();
        init_decrementer_clockevent();
+        tick_setup_hrtimer_broadcast();
 }
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index ef47bcbd4352..03567c05950a 100644
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/powerpc/kernel/tm.S
@@ -307,7 +307,7 @@ dont_backup_fp:
         *      Call with IRQs off, stacks get all out of sync for
         *      some periods in here!
         */
-_GLOBAL(tm_recheckpoint)
+_GLOBAL(__tm_recheckpoint)
        mfcr    r5
        mflr    r0
        stw     r5, 8(r1)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 33cd7a0b8e73..1bd7ca298fa1 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1379,8 +1379,9 @@ void facility_unavailable_exception(struct pt_regs *regs)
        if (!arch_irq_disabled_regs(regs))
                local_irq_enable();
-        pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
+        pr_err_ratelimited(
-               hv ? "Hypervisor " : "", facility, regs->nip, regs->msr);
+                "%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
+                hv ? "Hypervisor " : "", facility, regs->nip, regs->msr);
        if (user_mode(regs)) {
                _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
@@ -1867,6 +1868,7 @@ struct ppc_emulated ppc_emulated = {
 #ifdef CONFIG_PPC64
        WARN_EMULATED_SETUP(mfdscr),
        WARN_EMULATED_SETUP(mtdscr),
+        WARN_EMULATED_SETUP(lq_stq),
 #endif
 };
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index 094e45c16a17..ce74c335a6a4 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -715,8 +715,8 @@ int vdso_getcpu_init(void)
        unsigned long cpu, node, val;
        /*
-         * SPRG3 contains the CPU in the bottom 16 bits and the NUMA node in
+         * SPRG_VDSO contains the CPU in the bottom 16 bits and the NUMA node
-         * the next 16 bits. The VDSO uses this to implement getcpu().
+         * in the next 16 bits.  The VDSO uses this to implement getcpu().
         */
        cpu = get_cpu();
        WARN_ON_ONCE(cpu > 0xffff);
@@ -725,8 +725,8 @@ int vdso_getcpu_init(void)
        WARN_ON_ONCE(node > 0xffff);
        val = (cpu & 0xfff) | ((node & 0xffff) << 16);
-        mtspr(SPRN_SPRG3, val);
+        mtspr(SPRN_SPRG_VDSO_WRITE, val);
-        get_paca()->sprg3 = val;
+        get_paca()->sprg_vdso = val;
        put_cpu();
diff --git a/arch/powerpc/kernel/vdso32/getcpu.S b/arch/powerpc/kernel/vdso32/getcpu.S
index 47afd08c90f7..23eb9a9441bd 100644
--- a/arch/powerpc/kernel/vdso32/getcpu.S
+++ b/arch/powerpc/kernel/vdso32/getcpu.S
@@ -29,7 +29,7 @@
 */
 V_FUNCTION_BEGIN(__kernel_getcpu)
  .cfi_startproc
-        mfspr   r5,SPRN_USPRG3
+        mfspr   r5,SPRN_SPRG_VDSO_READ
        cmpdi   cr0,r3,0
        cmpdi   cr1,r4,0
        clrlwi  r6,r5,16
diff --git a/arch/powerpc/kernel/vdso64/getcpu.S b/arch/powerpc/kernel/vdso64/getcpu.S
index 47afd08c90f7..23eb9a9441bd 100644
--- a/arch/powerpc/kernel/vdso64/getcpu.S
+++ b/arch/powerpc/kernel/vdso64/getcpu.S
@@ -29,7 +29,7 @@
 */
 V_FUNCTION_BEGIN(__kernel_getcpu)
  .cfi_startproc
-        mfspr   r5,SPRN_USPRG3
+        mfspr   r5,SPRN_SPRG_VDSO_READ
        cmpdi   cr0,r3,0
        cmpdi   cr1,r4,0
        clrlwi  r6,r5,16
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index 826d8bd9e522..904c66128fae 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -1432,7 +1432,8 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
                /* needed to ensure proper operation of coherent allocations
                 * later, in case driver doesn't set it explicitly */
-                dma_coerce_mask_and_coherent(&viodev->dev, DMA_BIT_MASK(64));
+                viodev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
+                viodev->dev.dma_mask = &viodev->dev.coherent_dma_mask;
        }
        /* register with generic device framework */
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index 303ece75b8e4..fb25ebc0af0c 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -262,7 +262,14 @@ int kvmppc_mmu_hv_init(void)
 static void kvmppc_mmu_book3s_64_hv_reset_msr(struct kvm_vcpu *vcpu)
 {
-        kvmppc_set_msr(vcpu, vcpu->arch.intr_msr);
+        unsigned long msr = vcpu->arch.intr_msr;
+        /* If transactional, change to suspend mode on IRQ delivery */
+        if (MSR_TM_TRANSACTIONAL(vcpu->arch.shregs.msr))
+                msr |= MSR_TS_S;
+        else
+                msr |= vcpu->arch.shregs.msr & MSR_TS_MASK;
+        kvmppc_set_msr(vcpu, msr);
 }
 /*
diff --git a/arch/powerpc/kvm/book3s_64_vio_hv.c b/arch/powerpc/kvm/book3s_64_vio_hv.c
index 2c25f5412bdb..89e96b3e0039 100644
--- a/arch/powerpc/kvm/book3s_64_vio_hv.c
+++ b/arch/powerpc/kvm/book3s_64_vio_hv.c
@@ -75,3 +75,31 @@ long kvmppc_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
        return H_TOO_HARD;
 }
 EXPORT_SYMBOL_GPL(kvmppc_h_put_tce);
+long kvmppc_h_get_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
+                      unsigned long ioba)
+{
+        struct kvm *kvm = vcpu->kvm;
+        struct kvmppc_spapr_tce_table *stt;
+        list_for_each_entry(stt, &kvm->arch.spapr_tce_tables, list) {
+                if (stt->liobn == liobn) {
+                        unsigned long idx = ioba >> SPAPR_TCE_SHIFT;
+                        struct page *page;
+                        u64 *tbl;
+                        if (ioba >= stt->window_size)
+                                return H_PARAMETER;
+                        page = stt->pages[idx / TCES_PER_PAGE];
+                        tbl = (u64 *)page_address(page);
+                        vcpu->arch.gpr[4] = tbl[idx % TCES_PER_PAGE];
+                        return H_SUCCESS;
+                }
+        }
+        /* Didn't find the liobn, punt it to userspace */
+        return H_TOO_HARD;
+}
+EXPORT_SYMBOL_GPL(kvmppc_h_get_tce);
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 17fc9496b6ac..8227dba5af0f 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -86,7 +86,7 @@ static void kvmppc_fast_vcpu_kick_hv(struct kvm_vcpu *vcpu)
        /* CPU points to the first thread of the core */
        if (cpu != me && cpu >= 0 && cpu < nr_cpu_ids) {
-#ifdef CONFIG_KVM_XICS
+#ifdef CONFIG_PPC_ICP_NATIVE
                int real_cpu = cpu + vcpu->arch.ptid;
                if (paca[real_cpu].kvm_hstate.xics_phys)
                        xics_wake_cpu(real_cpu);
@@ -879,17 +879,6 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
        case KVM_REG_PPC_IAMR:
                *val = get_reg_val(id, vcpu->arch.iamr);
                break;
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-        case KVM_REG_PPC_TFHAR:
-                *val = get_reg_val(id, vcpu->arch.tfhar);
-                break;
-        case KVM_REG_PPC_TFIAR:
-                *val = get_reg_val(id, vcpu->arch.tfiar);
-                break;
-        case KVM_REG_PPC_TEXASR:
-                *val = get_reg_val(id, vcpu->arch.texasr);
-                break;
-#endif
        case KVM_REG_PPC_FSCR:
                *val = get_reg_val(id, vcpu->arch.fscr);
                break;
@@ -970,6 +959,69 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
        case KVM_REG_PPC_PPR:
                *val = get_reg_val(id, vcpu->arch.ppr);
                break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        case KVM_REG_PPC_TFHAR:
+                *val = get_reg_val(id, vcpu->arch.tfhar);
+                break;
+        case KVM_REG_PPC_TFIAR:
+                *val = get_reg_val(id, vcpu->arch.tfiar);
+                break;
+        case KVM_REG_PPC_TEXASR:
+                *val = get_reg_val(id, vcpu->arch.texasr);
+                break;
+        case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31:
+                i = id - KVM_REG_PPC_TM_GPR0;
+                *val = get_reg_val(id, vcpu->arch.gpr_tm[i]);
+                break;
+        case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63:
+        {
+                int j;
+                i = id - KVM_REG_PPC_TM_VSR0;
+                if (i < 32)
+                        for (j = 0; j < TS_FPRWIDTH; j++)
+                                val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j];
+                else {
+                        if (cpu_has_feature(CPU_FTR_ALTIVEC))
+                                val->vval = vcpu->arch.vr_tm.vr[i-32];
+                        else
+                                r = -ENXIO;
+                }
+                break;
+        }
+        case KVM_REG_PPC_TM_CR:
+                *val = get_reg_val(id, vcpu->arch.cr_tm);
+                break;
+        case KVM_REG_PPC_TM_LR:
+                *val = get_reg_val(id, vcpu->arch.lr_tm);
+                break;
+        case KVM_REG_PPC_TM_CTR:
+                *val = get_reg_val(id, vcpu->arch.ctr_tm);
+                break;
+        case KVM_REG_PPC_TM_FPSCR:
+                *val = get_reg_val(id, vcpu->arch.fp_tm.fpscr);
+                break;
+        case KVM_REG_PPC_TM_AMR:
+                *val = get_reg_val(id, vcpu->arch.amr_tm);
+                break;
+        case KVM_REG_PPC_TM_PPR:
+                *val = get_reg_val(id, vcpu->arch.ppr_tm);
+                break;
+        case KVM_REG_PPC_TM_VRSAVE:
+                *val = get_reg_val(id, vcpu->arch.vrsave_tm);
+                break;
+        case KVM_REG_PPC_TM_VSCR:
+                if (cpu_has_feature(CPU_FTR_ALTIVEC))
+                        *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]);
+                else
+                        r = -ENXIO;
+                break;
+        case KVM_REG_PPC_TM_DSCR:
+                *val = get_reg_val(id, vcpu->arch.dscr_tm);
+                break;
+        case KVM_REG_PPC_TM_TAR:
+                *val = get_reg_val(id, vcpu->arch.tar_tm);
+                break;
+#endif
        case KVM_REG_PPC_ARCH_COMPAT:
                *val = get_reg_val(id, vcpu->arch.vcore->arch_compat);
                break;
@@ -1039,17 +1091,6 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
        case KVM_REG_PPC_IAMR:
                vcpu->arch.iamr = set_reg_val(id, *val);
                break;
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-        case KVM_REG_PPC_TFHAR:
-                vcpu->arch.tfhar = set_reg_val(id, *val);
-                break;
-        case KVM_REG_PPC_TFIAR:
-                vcpu->arch.tfiar = set_reg_val(id, *val);
-                break;
-        case KVM_REG_PPC_TEXASR:
-                vcpu->arch.texasr = set_reg_val(id, *val);
-                break;
-#endif
        case KVM_REG_PPC_FSCR:
                vcpu->arch.fscr = set_reg_val(id, *val);
                break;
@@ -1144,6 +1185,68 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
        case KVM_REG_PPC_PPR:
                vcpu->arch.ppr = set_reg_val(id, *val);
                break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        case KVM_REG_PPC_TFHAR:
+                vcpu->arch.tfhar = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TFIAR:
+                vcpu->arch.tfiar = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TEXASR:
+                vcpu->arch.texasr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31:
+                i = id - KVM_REG_PPC_TM_GPR0;
+                vcpu->arch.gpr_tm[i] = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63:
+        {
+                int j;
+                i = id - KVM_REG_PPC_TM_VSR0;
+                if (i < 32)
+                        for (j = 0; j < TS_FPRWIDTH; j++)
+                                vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j];
+                else
+                        if (cpu_has_feature(CPU_FTR_ALTIVEC))
+                                vcpu->arch.vr_tm.vr[i-32] = val->vval;
+                        else
+                                r = -ENXIO;
+                break;
+        }
+        case KVM_REG_PPC_TM_CR:
+                vcpu->arch.cr_tm = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_LR:
+                vcpu->arch.lr_tm = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_CTR:
+                vcpu->arch.ctr_tm = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_FPSCR:
+                vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_AMR:
+                vcpu->arch.amr_tm = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_PPR:
+                vcpu->arch.ppr_tm = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_VRSAVE:
+                vcpu->arch.vrsave_tm = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_VSCR:
+                if (cpu_has_feature(CPU_FTR_ALTIVEC))
+                        vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val);
+                else
+                        r = - ENXIO;
+                break;
+        case KVM_REG_PPC_TM_DSCR:
+                vcpu->arch.dscr_tm = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TM_TAR:
+                vcpu->arch.tar_tm = set_reg_val(id, *val);
+                break;
+#endif
        case KVM_REG_PPC_ARCH_COMPAT:
                r = kvmppc_set_arch_compat(vcpu, set_reg_val(id, *val));
                break;
@@ -1360,9 +1463,7 @@ static void kvmppc_start_thread(struct kvm_vcpu *vcpu)
        smp_wmb();
 #if defined(CONFIG_PPC_ICP_NATIVE) && defined(CONFIG_SMP)
        if (cpu != smp_processor_id()) {
-#ifdef CONFIG_KVM_XICS
                xics_wake_cpu(cpu);
-#endif
                if (vcpu->arch.ptid)
                        ++vc->n_woken;
        }
@@ -1530,7 +1631,7 @@ static void kvmppc_run_core(struct kvmppc_vcore *vc)
                vcpu->arch.trap = 0;
                if (vcpu->arch.ceded) {
-                        if (ret != RESUME_GUEST)
+                        if (!is_kvmppc_resume_guest(ret))
                                kvmppc_end_cede(vcpu);
                        else
                                kvmppc_set_timer(vcpu);
@@ -1541,7 +1642,7 @@ static void kvmppc_run_core(struct kvmppc_vcore *vc)
        vc->vcore_state = VCORE_INACTIVE;
        list_for_each_entry_safe(vcpu, vnext, &vc->runnable_threads,
                                 arch.run_list) {
-                if (vcpu->arch.ret != RESUME_GUEST) {
+                if (!is_kvmppc_resume_guest(vcpu->arch.ret)) {
                        kvmppc_remove_runnable(vc, vcpu);
                        wake_up(&vcpu->arch.cpu_run);
                }
@@ -1731,7 +1832,7 @@ static int kvmppc_vcpu_run_hv(struct kvm_run *run, struct kvm_vcpu *vcpu)
                                vcpu->arch.fault_dar, vcpu->arch.fault_dsisr);
                        srcu_read_unlock(&vcpu->kvm->srcu, srcu_idx);
                }
-        } while (r == RESUME_GUEST);
+        } while (is_kvmppc_resume_guest(r));
 out:
        vcpu->arch.state = KVMPPC_VCPU_NOTREADY;
@@ -2366,7 +2467,7 @@ static int kvmppc_book3s_init_hv(void)
         */
        r = kvmppc_core_check_processor_compat_hv();
        if (r < 0)
-                return r;
+                return -ENODEV;
        kvm_ops_hv.owner = THIS_MODULE;
        kvmppc_hv_ops = &kvm_ops_hv;
diff --git a/arch/powerpc/kvm/book3s_hv_interrupts.S b/arch/powerpc/kvm/book3s_hv_interrupts.S
index e873796b1a29..e18e3cfc32de 100644
--- a/arch/powerpc/kvm/book3s_hv_interrupts.S
+++ b/arch/powerpc/kvm/book3s_hv_interrupts.S
@@ -71,6 +71,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
        mtmsrd  r10,1
        /* Save host PMU registers */
+BEGIN_FTR_SECTION
+        /* Work around P8 PMAE bug */
+        li      r3, -1
+        clrrdi  r3, r3, 10
+        mfspr   r8, SPRN_MMCR2
+        mtspr   SPRN_MMCR2, r3          /* freeze all counters using MMCR2 */
+        isync
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
        li      r3, 1
        sldi    r3, r3, 31              /* MMCR0_FC (freeze counters) bit */
        mfspr   r7, SPRN_MMCR0          /* save MMCR0 */
@@ -87,9 +95,18 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
        cmpwi   r5, 0
        beq     31f                     /* skip if not */
        mfspr   r5, SPRN_MMCR1
+        mfspr   r9, SPRN_SIAR
+        mfspr   r10, SPRN_SDAR
        std     r7, HSTATE_MMCR(r13)
        std     r5, HSTATE_MMCR + 8(r13)
        std     r6, HSTATE_MMCR + 16(r13)
+        std     r9, HSTATE_MMCR + 24(r13)
+        std     r10, HSTATE_MMCR + 32(r13)
+BEGIN_FTR_SECTION
+        mfspr   r9, SPRN_SIER
+        std     r8, HSTATE_MMCR + 40(r13)
+        std     r9, HSTATE_MMCR + 48(r13)
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
        mfspr   r3, SPRN_PMC1
        mfspr   r5, SPRN_PMC2
        mfspr   r6, SPRN_PMC3
@@ -110,6 +127,11 @@ BEGIN_FTR_SECTION
        stw     r10, HSTATE_PMC + 24(r13)
        stw     r11, HSTATE_PMC + 28(r13)
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
+BEGIN_FTR_SECTION
+        mfspr   r9, SPRN_SIER
+        std     r8, HSTATE_MMCR + 40(r13)
+        std     r9, HSTATE_MMCR + 48(r13)
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 31:
        /*
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 37fb3caa4c80..1d6c56ad5b60 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -111,7 +111,7 @@ static void remove_revmap_chain(struct kvm *kvm, long pte_index,
        rcbits = hpte_r & (HPTE_R_R | HPTE_R_C);
        ptel = rev->guest_rpte |= rcbits;
        gfn = hpte_rpn(ptel, hpte_page_size(hpte_v, ptel));
-        memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
+        memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
        if (!memslot)
                return;
@@ -192,7 +192,7 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
        /* Find the memslot (if any) for this address */
        gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
        gfn = gpa >> PAGE_SHIFT;
-        memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
+        memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
        pa = 0;
        is_io = ~0ul;
        rmap = NULL;
@@ -670,7 +670,7 @@ long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
                        psize = hpte_page_size(v, r);
                        gfn = ((r & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
-                        memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
+                        memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
                        if (memslot) {
                                hva = __gfn_to_hva_memslot(memslot, gfn);
                                pte = lookup_linux_pte_and_update(pgdir, hva,
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 818dce344e82..ffbb871c2bd8 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -28,6 +28,9 @@
 #include <asm/exception-64s.h>
 #include <asm/kvm_book3s_asm.h>
 #include <asm/mmu-hash64.h>
+#include <asm/tm.h>
+#define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
 #ifdef __LITTLE_ENDIAN__
 #error Need to fix lppaca and SLB shadow accesses in little endian mode
@@ -75,8 +78,8 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
        /* Restore SPRG3 */
-        ld      r3,PACA_SPRG3(r13)
+        ld      r3,PACA_SPRG_VDSO(r13)
-        mtspr   SPRN_SPRG3,r3
+        mtspr   SPRN_SPRG_VDSO_WRITE,r3
        /* Reload the host's PMU registers */
        ld      r3, PACALPPACAPTR(r13)  /* is the host using the PMU? */
@@ -106,8 +109,18 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
        ld      r3, HSTATE_MMCR(r13)
        ld      r4, HSTATE_MMCR + 8(r13)
        ld      r5, HSTATE_MMCR + 16(r13)
+        ld      r6, HSTATE_MMCR + 24(r13)
+        ld      r7, HSTATE_MMCR + 32(r13)
        mtspr   SPRN_MMCR1, r4
        mtspr   SPRN_MMCRA, r5
+        mtspr   SPRN_SIAR, r6
+        mtspr   SPRN_SDAR, r7
+BEGIN_FTR_SECTION
+        ld      r8, HSTATE_MMCR + 40(r13)
+        ld      r9, HSTATE_MMCR + 48(r13)
+        mtspr   SPRN_MMCR2, r8
+        mtspr   SPRN_SIER, r9
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
        mtspr   SPRN_MMCR0, r3
        isync
 23:
@@ -597,6 +610,116 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+BEGIN_FTR_SECTION
+        b       skip_tm
+END_FTR_SECTION_IFCLR(CPU_FTR_TM)
+        /* Turn on TM/FP/VSX/VMX so we can restore them. */
+        mfmsr   r5
+        li      r6, MSR_TM >> 32
+        sldi    r6, r6, 32
+        or      r5, r5, r6
+        ori     r5, r5, MSR_FP
+        oris    r5, r5, (MSR_VEC | MSR_VSX)@h
+        mtmsrd  r5
+        /*
+         * The user may change these outside of a transaction, so they must
+         * always be context switched.
+         */
+        ld      r5, VCPU_TFHAR(r4)
+        ld      r6, VCPU_TFIAR(r4)
+        ld      r7, VCPU_TEXASR(r4)
+        mtspr   SPRN_TFHAR, r5
+        mtspr   SPRN_TFIAR, r6
+        mtspr   SPRN_TEXASR, r7
+        ld      r5, VCPU_MSR(r4)
+        rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
+        beq     skip_tm /* TM not active in guest */
+        /* Make sure the failure summary is set, otherwise we'll program check
+         * when we trechkpt.  It's possible that this might have been not set
+         * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
+         * host.
+         */
+        oris    r7, r7, (TEXASR_FS)@h
+        mtspr   SPRN_TEXASR, r7
+        /*
+         * We need to load up the checkpointed state for the guest.
+         * We need to do this early as it will blow away any GPRs, VSRs and
+         * some SPRs.
+         */
+        mr      r31, r4
+        addi    r3, r31, VCPU_FPRS_TM
+        bl      .load_fp_state
+        addi    r3, r31, VCPU_VRS_TM
+        bl      .load_vr_state
+        mr      r4, r31
+        lwz     r7, VCPU_VRSAVE_TM(r4)
+        mtspr   SPRN_VRSAVE, r7
+        ld      r5, VCPU_LR_TM(r4)
+        lwz     r6, VCPU_CR_TM(r4)
+        ld      r7, VCPU_CTR_TM(r4)
+        ld      r8, VCPU_AMR_TM(r4)
+        ld      r9, VCPU_TAR_TM(r4)
+        mtlr    r5
+        mtcr    r6
+        mtctr   r7
+        mtspr   SPRN_AMR, r8
+        mtspr   SPRN_TAR, r9
+        /*
+         * Load up PPR and DSCR values but don't put them in the actual SPRs
+         * till the last moment to avoid running with userspace PPR and DSCR for
+         * too long.
+         */
+        ld      r29, VCPU_DSCR_TM(r4)
+        ld      r30, VCPU_PPR_TM(r4)
+        std     r2, PACATMSCRATCH(r13) /* Save TOC */
+        /* Clear the MSR RI since r1, r13 are all going to be foobar. */
+        li      r5, 0
+        mtmsrd  r5, 1
+        /* Load GPRs r0-r28 */
+        reg = 0
+        .rept   29
+        ld      reg, VCPU_GPRS_TM(reg)(r31)
+        reg = reg + 1
+        .endr
+        mtspr   SPRN_DSCR, r29
+        mtspr   SPRN_PPR, r30
+        /* Load final GPRs */
+        ld      29, VCPU_GPRS_TM(29)(r31)
+        ld      30, VCPU_GPRS_TM(30)(r31)
+        ld      31, VCPU_GPRS_TM(31)(r31)
+        /* TM checkpointed state is now setup.  All GPRs are now volatile. */
+        TRECHKPT
+        /* Now let's get back the state we need. */
+        HMT_MEDIUM
+        GET_PACA(r13)
+        ld      r29, HSTATE_DSCR(r13)
+        mtspr   SPRN_DSCR, r29
+        ld      r4, HSTATE_KVM_VCPU(r13)
+        ld      r1, HSTATE_HOST_R1(r13)
+        ld      r2, PACATMSCRATCH(r13)
+        /* Set the MSR RI since we have our registers back. */
+        li      r5, MSR_RI
+        mtmsrd  r5, 1
+skip_tm:
+#endif
        /* Load guest PMU registers */
        /* R4 is live here (vcpu pointer) */
        li      r3, 1
@@ -704,14 +827,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
        ld      r6, VCPU_VTB(r4)
        mtspr   SPRN_IC, r5
        mtspr   SPRN_VTB, r6
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-        ld      r5, VCPU_TFHAR(r4)
-        ld      r6, VCPU_TFIAR(r4)
-        ld      r7, VCPU_TEXASR(r4)
-        mtspr   SPRN_TFHAR, r5
-        mtspr   SPRN_TFIAR, r6
-        mtspr   SPRN_TEXASR, r7
-#endif
        ld      r8, VCPU_EBBHR(r4)
        mtspr   SPRN_EBBHR, r8
        ld      r5, VCPU_EBBRR(r4)
@@ -736,6 +851,10 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
         * Set the decrementer to the guest decrementer.
         */
        ld      r8,VCPU_DEC_EXPIRES(r4)
+        /* r8 is a host timebase value here, convert to guest TB */
+        ld      r5,HSTATE_KVM_VCORE(r13)
+        ld      r6,VCORE_TB_OFFSET(r5)
+        add     r8,r8,r6
        mftb    r7
        subf    r3,r7,r8
        mtspr   SPRN_DEC,r3
@@ -817,7 +936,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 12:     mtspr   SPRN_SRR0, r10
        mr      r10,r0
        mtspr   SPRN_SRR1, r11
-        ld      r11, VCPU_INTR_MSR(r4)
+        mr      r9, r4
+        bl      kvmppc_msr_interrupt
 5:
 /*
@@ -1098,17 +1218,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
        mftb    r6
        extsw   r5,r5
        add     r5,r5,r6
+        /* r5 is a guest timebase value here, convert to host TB */
+        ld      r3,HSTATE_KVM_VCORE(r13)
+        ld      r4,VCORE_TB_OFFSET(r3)
+        subf    r5,r4,r5
        std     r5,VCPU_DEC_EXPIRES(r9)
 BEGIN_FTR_SECTION
        b       8f
 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
-        /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
-        mfmsr   r8
-        li      r0, 1
-        rldimi  r8, r0, MSR_TM_LG, 63-MSR_TM_LG
-        mtmsrd  r8
        /* Save POWER8-specific registers */
        mfspr   r5, SPRN_IAMR
        mfspr   r6, SPRN_PSPB
@@ -1122,14 +1240,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
        std     r5, VCPU_IC(r9)
        std     r6, VCPU_VTB(r9)
        std     r7, VCPU_TAR(r9)
-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
-        mfspr   r5, SPRN_TFHAR
-        mfspr   r6, SPRN_TFIAR
-        mfspr   r7, SPRN_TEXASR
-        std     r5, VCPU_TFHAR(r9)
-        std     r6, VCPU_TFIAR(r9)
-        std     r7, VCPU_TEXASR(r9)
-#endif
        mfspr   r8, SPRN_EBBHR
        std     r8, VCPU_EBBHR(r9)
        mfspr   r5, SPRN_EBBRR
@@ -1387,7 +1497,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
        ld      r8,VCORE_TB_OFFSET(r5)
        cmpdi   r8,0
        beq     17f
-        mftb    r6                      /* current host timebase */
+        mftb    r6                      /* current guest timebase */
        subf    r8,r8,r6
        mtspr   SPRN_TBU40,r8           /* update upper 40 bits */
        mftb    r7                      /* check if lower 24 bits overflowed */
@@ -1557,7 +1667,7 @@ kvmppc_hdsi:
        mtspr   SPRN_SRR0, r10
        mtspr   SPRN_SRR1, r11
        li      r10, BOOK3S_INTERRUPT_DATA_STORAGE
-        ld      r11, VCPU_INTR_MSR(r9)
+        bl      kvmppc_msr_interrupt
 fast_interrupt_c_return:
 6:      ld      r7, VCPU_CTR(r9)
        lwz     r8, VCPU_XER(r9)
@@ -1626,7 +1736,7 @@ kvmppc_hisi:
 1:      mtspr   SPRN_SRR0, r10
        mtspr   SPRN_SRR1, r11
        li      r10, BOOK3S_INTERRUPT_INST_STORAGE
-        ld      r11, VCPU_INTR_MSR(r9)
+        bl      kvmppc_msr_interrupt
        b       fast_interrupt_c_return
 3:      ld      r6, VCPU_KVM(r9)        /* not relocated, use VRMA */
@@ -1669,7 +1779,7 @@ sc_1_fast_return:
        mtspr   SPRN_SRR0,r10
        mtspr   SPRN_SRR1,r11
        li      r10, BOOK3S_INTERRUPT_SYSCALL
-        ld      r11, VCPU_INTR_MSR(r9)
+        bl      kvmppc_msr_interrupt
        mr      r4,r9
        b       fast_guest_return
@@ -1691,7 +1801,7 @@ hcall_real_table:
        .long   0               /* 0x10 - H_CLEAR_MOD */
        .long   0               /* 0x14 - H_CLEAR_REF */
        .long   .kvmppc_h_protect - hcall_real_table
-        .long   0               /* 0x1c - H_GET_TCE */
+        .long   .kvmppc_h_get_tce - hcall_real_table
        .long   .kvmppc_h_put_tce - hcall_real_table
        .long   0               /* 0x24 - H_SET_SPRG0 */
        .long   .kvmppc_h_set_dabr - hcall_real_table
@@ -1997,7 +2107,7 @@ machine_check_realmode:
        beq     mc_cont
        /* If not, deliver a machine check.  SRR0/1 are already set */
        li      r10, BOOK3S_INTERRUPT_MACHINE_CHECK
-        ld      r11, VCPU_INTR_MSR(r9)
+        bl      kvmppc_msr_interrupt
        b       fast_interrupt_c_return
 /*
@@ -2138,8 +2248,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        mfspr   r6,SPRN_VRSAVE
        stw     r6,VCPU_VRSAVE(r31)
        mtlr    r30
-        mtmsrd  r5
-        isync
        blr
 /*
@@ -2186,3 +2294,20 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 */
 kvmppc_bad_host_intr:
        b       .
+/*
+ * This mimics the MSR transition on IRQ delivery.  The new guest MSR is taken
+ * from VCPU_INTR_MSR and is modified based on the required TM state changes.
+ *   r11 has the guest MSR value (in/out)
+ *   r9 has a vcpu pointer (in)
+ *   r0 is used as a scratch register
+ */
+kvmppc_msr_interrupt:
+        rldicl  r0, r11, 64 - MSR_TS_S_LG, 62
+        cmpwi   r0, 2 /* Check if we are in transactional state..  */
+        ld      r11, VCPU_INTR_MSR(r9)
+        bne     1f
+        /* ... if transactional, change to suspended */
+        li      r0, 1
+1:      rldimi  r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
+        blr
diff --git a/arch/powerpc/kvm/book3s_interrupts.S b/arch/powerpc/kvm/book3s_interrupts.S
index f779450cb07c..3533c999194a 100644
--- a/arch/powerpc/kvm/book3s_interrupts.S
+++ b/arch/powerpc/kvm/book3s_interrupts.S
@@ -153,8 +153,8 @@ kvm_start_lightweight:
         * Reload kernel SPRG3 value.
         * No need to save guest value as usermode can't modify SPRG3.
         */
-        ld      r3, PACA_SPRG3(r13)
+        ld      r3, PACA_SPRG_VDSO(r13)
-        mtspr   SPRN_SPRG3, r3
+        mtspr   SPRN_SPRG_VDSO_WRITE, r3
 #endif /* CONFIG_PPC_BOOK3S_64 */
        /* R7 = vcpu */
diff --git a/arch/powerpc/kvm/book3s_rtas.c b/arch/powerpc/kvm/book3s_rtas.c
index cf95cdef73c9..7a053157483b 100644
--- a/arch/powerpc/kvm/book3s_rtas.c
+++ b/arch/powerpc/kvm/book3s_rtas.c
@@ -213,8 +213,11 @@ int kvmppc_rtas_hcall(struct kvm_vcpu *vcpu)
        gpa_t args_phys;
        int rc;
-        /* r4 contains the guest physical address of the RTAS args */
+        /*
-        args_phys = kvmppc_get_gpr(vcpu, 4);
+         * r4 contains the guest physical address of the RTAS args
+         * Mask off the top 4 bits since this is a guest real address
+         */
+        args_phys = kvmppc_get_gpr(vcpu, 4) & KVM_PAM;
        rc = kvm_read_guest(vcpu->kvm, args_phys, &args, sizeof(args));
        if (rc)
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
index e4185f6b3309..a1712b818a5f 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -229,17 +229,20 @@
        stw     r10, VCPU_CR(r4)
        PPC_STL r11, VCPU_GPR(R4)(r4)
        PPC_STL r5, VCPU_GPR(R5)(r4)
-        .if \type == EX_CRIT
-        PPC_LL  r5, (\paca_ex + EX_R13)(r13)
-        .else
-        mfspr   r5, \scratch
-        .endif
        PPC_STL r6, VCPU_GPR(R6)(r4)
        PPC_STL r8, VCPU_GPR(R8)(r4)
        PPC_STL r9, VCPU_GPR(R9)(r4)
-        PPC_STL r5, VCPU_GPR(R13)(r4)
+        .if \type == EX_TLB
+        PPC_LL  r5, EX_TLB_R13(r12)
+        PPC_LL  r6, EX_TLB_R10(r12)
+        PPC_LL  r8, EX_TLB_R11(r12)
+        mfspr   r12, \scratch
+        .else
+        mfspr   r5, \scratch
        PPC_LL  r6, (\paca_ex + \ex_r10)(r13)
        PPC_LL  r8, (\paca_ex + \ex_r11)(r13)
+        .endif
+        PPC_STL r5, VCPU_GPR(R13)(r4)
        PPC_STL r3, VCPU_GPR(R3)(r4)
        PPC_STL r7, VCPU_GPR(R7)(r4)
        PPC_STL r12, VCPU_GPR(R12)(r4)
@@ -435,10 +438,16 @@ _GLOBAL(kvmppc_resume_host)
        PPC_STL r5, VCPU_LR(r4)
        mfspr   r7, SPRN_SPRG5
        stw     r3, VCPU_VRSAVE(r4)
+#ifdef CONFIG_64BIT
+        PPC_LL  r3, PACA_SPRG_VDSO(r13)
+#endif
        PPC_STD(r6, VCPU_SHARED_SPRG4, r11)
        mfspr   r8, SPRN_SPRG6
        PPC_STD(r7, VCPU_SHARED_SPRG5, r11)
        mfspr   r9, SPRN_SPRG7
+#ifdef CONFIG_64BIT
+        mtspr   SPRN_SPRG_VDSO_WRITE, r3
+#endif
        PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
        mfxer   r3
        PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S
index d2bbbc8d7dc0..72ad055168a3 100644
--- a/arch/powerpc/lib/memcpy_64.S
+++ b/arch/powerpc/lib/memcpy_64.S
@@ -14,7 +14,9 @@ _GLOBAL(memcpy)
 BEGIN_FTR_SECTION
        std     r3,48(r1)       /* save destination pointer for return value */
 FTR_SECTION_ELSE
+#ifndef SELFTEST
        b       memcpy_power7
+#endif
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
        PPC_MTOCRF(0x01,r5)
        cmpldi  cr1,r5,16
diff --git a/arch/powerpc/math-emu/mtfsf.c b/arch/powerpc/math-emu/mtfsf.c
index dbce92e4f046..44b0fc8214f4 100644
--- a/arch/powerpc/math-emu/mtfsf.c
+++ b/arch/powerpc/math-emu/mtfsf.c
@@ -11,48 +11,36 @@ mtfsf(unsigned int FM, u32 *frB)
        u32 mask;
        u32 fpscr;
-        if (FM == 0)
+        if (likely(FM == 1))
-                return 0;
+                mask = 0x0f;
+        else if (likely(FM == 0xff))
-        if (FM == 0xff)
+                mask = ~0;
-                mask = 0x9fffffff;
        else {
-                mask = 0;
+                mask = ((FM & 1) |
-                if (FM & (1 << 0))
+                                ((FM << 3) & 0x10) |
-                        mask |= 0x90000000;
+                                ((FM << 6) & 0x100) |
-                if (FM & (1 << 1))
+                                ((FM << 9) & 0x1000) |
-                        mask |= 0x0f000000;
+                                ((FM << 12) & 0x10000) |
-                if (FM & (1 << 2))
+                                ((FM << 15) & 0x100000) |
-                        mask |= 0x00f00000;
+                                ((FM << 18) & 0x1000000) |
-                if (FM & (1 << 3))
+                                ((FM << 21) & 0x10000000)) * 15;
-                        mask |= 0x000f0000;
-                if (FM & (1 << 4))
-                        mask |= 0x0000f000;
-                if (FM & (1 << 5))
-                        mask |= 0x00000f00;
-                if (FM & (1 << 6))
-                        mask |= 0x000000f0;
-                if (FM & (1 << 7))
-                        mask |= 0x0000000f;
        }
-        __FPU_FPSCR &= ~(mask);
+        fpscr = ((__FPU_FPSCR & ~mask) | (frB[1] & mask)) &
-        __FPU_FPSCR |= (frB[1] & mask);
+                ~(FPSCR_VX | FPSCR_FEX | 0x800);
-        __FPU_FPSCR &= ~(FPSCR_VX);
+        if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI |
-        if (__FPU_FPSCR & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI |
                     FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC |
                     FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI))
-                __FPU_FPSCR |= FPSCR_VX;
+                fpscr |= FPSCR_VX;
-        fpscr = __FPU_FPSCR;
+        /* The bit order of exception enables and exception status
-        fpscr &= ~(FPSCR_FEX);
+         * is the same. Simply shift and mask to check for enabled
-        if (((fpscr & FPSCR_VX) && (fpscr & FPSCR_VE)) ||
+         * exceptions.
-            ((fpscr & FPSCR_OX) && (fpscr & FPSCR_OE)) ||
+         */
-            ((fpscr & FPSCR_UX) && (fpscr & FPSCR_UE)) ||
+        if (fpscr & (fpscr >> 22) &  0xf8)
-            ((fpscr & FPSCR_ZX) && (fpscr & FPSCR_ZE)) ||
-            ((fpscr & FPSCR_XX) && (fpscr & FPSCR_XE)))
                fpscr |= FPSCR_FEX;
        __FPU_FPSCR = fpscr;
 #ifdef DEBUG
diff --git a/arch/powerpc/mm/gup.c b/arch/powerpc/mm/gup.c
index c5f734e20b0f..d8746684f606 100644
--- a/arch/powerpc/mm/gup.c
+++ b/arch/powerpc/mm/gup.c
@@ -36,6 +36,11 @@ static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
        do {
                pte_t pte = ACCESS_ONCE(*ptep);
                struct page *page;
+                /*
+                 * Similar to the PMD case, NUMA hinting must take slow path
+                 */
+                if (pte_numa(pte))
+                        return 0;
                if ((pte_val(pte) & mask) != result)
                        return 0;
@@ -75,6 +80,14 @@ static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
                if (pmd_none(pmd) || pmd_trans_splitting(pmd))
                        return 0;
                if (pmd_huge(pmd) || pmd_large(pmd)) {
+                        /*
+                         * NUMA hinting faults need to be handled in the GUP
+                         * slowpath for accounting purposes and so that they
+                         * can be serialised against THP migration.
+                         */
+                        if (pmd_numa(pmd))
+                                return 0;
                        if (!gup_hugepte((pte_t *)pmdp, PMD_SIZE, addr, next,
                                         write, pages, nr))
                                return 0;
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 4b5cd5c2594d..2c8e90f5789e 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -139,9 +139,14 @@ int arch_remove_memory(u64 start, u64 size)
        unsigned long start_pfn = start >> PAGE_SHIFT;
        unsigned long nr_pages = size >> PAGE_SHIFT;
        struct zone *zone;
+        int ret;
        zone = page_zone(pfn_to_page(start_pfn));
-        return __remove_pages(zone, start_pfn, nr_pages);
+        ret = __remove_pages(zone, start_pfn, nr_pages);
+        if (!ret && (ppc_md.remove_memory))
+                ret = ppc_md.remove_memory(start, size);
+        return ret;
 }
 #endif
 #endif /* CONFIG_MEMORY_HOTPLUG */
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 30a42e24bf14..4ebbb9e99286 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -1591,6 +1591,20 @@ int arch_update_cpu_topology(void)
                cpu = cpu_last_thread_sibling(cpu);
        }
+        /*
+         * In cases where we have nothing to update (because the updates list
+         * is too short or because the new topology is same as the old one),
+         * skip invoking update_cpu_topology() via stop-machine(). This is
+         * necessary (and not just a fast-path optimization) since stop-machine
+         * can end up electing a random CPU to run update_cpu_topology(), and
+         * thus trick us into setting up incorrect cpu-node mappings (since
+         * 'updates' is kzalloc()'ed).
+         *
+         * And for the similar reason, we will skip all the following updating.
+         */
+        if (!cpumask_weight(&updated_cpus))
+                goto out;
        stop_machine(update_cpu_topology, &updates[0], &updated_cpus);
        /*
@@ -1612,6 +1626,7 @@ int arch_update_cpu_topology(void)
                changed = 1;
        }
+out:
        kfree(updates);
        return changed;
 }
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 62bf5e8e78da..f6ce1f111f5b 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -647,6 +647,11 @@ void pmdp_splitting_flush(struct vm_area_struct *vma,
                if (old & _PAGE_HASHPTE)
                        hpte_do_hugepage_flush(vma->vm_mm, address, pmdp);
        }
+        /*
+         * This ensures that generic code that rely on IRQ disabling
+         * to prevent a parallel THP split work as expected.
+         */
+        kick_all_cpus_sync();
 }
 /*
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index c95eb323e9ae..356e8b41fb09 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -39,37 +39,49 @@
 *                                                                    *
 **********************************************************************/
+/*
+ * Note that, unlike non-bolted handlers, TLB_EXFRAME is not
+ * modified by the TLB miss handlers themselves, since the TLB miss
+ * handler code will not itself cause a recursive TLB miss.
+ *
+ * TLB_EXFRAME will be modified when crit/mc/debug exceptions are
+ * entered/exited.
+ */
 .macro tlb_prolog_bolted intnum addr
-        mtspr   SPRN_SPRG_GEN_SCRATCH,r13
+        mtspr   SPRN_SPRG_GEN_SCRATCH,r12
+        mfspr   r12,SPRN_SPRG_TLB_EXFRAME
+        std     r13,EX_TLB_R13(r12)
+        std     r10,EX_TLB_R10(r12)
        mfspr   r13,SPRN_SPRG_PACA
-        std     r10,PACA_EXTLB+EX_TLB_R10(r13)
        mfcr    r10
-        std     r11,PACA_EXTLB+EX_TLB_R11(r13)
+        std     r11,EX_TLB_R11(r12)
 #ifdef CONFIG_KVM_BOOKE_HV
 BEGIN_FTR_SECTION
        mfspr   r11, SPRN_SRR1
 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 #endif
        DO_KVM  \intnum, SPRN_SRR1
-        std     r16,PACA_EXTLB+EX_TLB_R16(r13)
+        std     r16,EX_TLB_R16(r12)
        mfspr   r16,\addr               /* get faulting address */
-        std     r14,PACA_EXTLB+EX_TLB_R14(r13)
+        std     r14,EX_TLB_R14(r12)
        ld      r14,PACAPGD(r13)
-        std     r15,PACA_EXTLB+EX_TLB_R15(r13)
+        std     r15,EX_TLB_R15(r12)
-        std     r10,PACA_EXTLB+EX_TLB_CR(r13)
+        std     r10,EX_TLB_CR(r12)
-        TLB_MISS_PROLOG_STATS_BOLTED
+        TLB_MISS_PROLOG_STATS
 .endm
 .macro tlb_epilog_bolted
-        ld      r14,PACA_EXTLB+EX_TLB_CR(r13)
+        ld      r14,EX_TLB_CR(r12)
-        ld      r10,PACA_EXTLB+EX_TLB_R10(r13)
+        ld      r10,EX_TLB_R10(r12)
-        ld      r11,PACA_EXTLB+EX_TLB_R11(r13)
+        ld      r11,EX_TLB_R11(r12)
+        ld      r13,EX_TLB_R13(r12)
        mtcr    r14
-        ld      r14,PACA_EXTLB+EX_TLB_R14(r13)
+        ld      r14,EX_TLB_R14(r12)
-        ld      r15,PACA_EXTLB+EX_TLB_R15(r13)
+        ld      r15,EX_TLB_R15(r12)
-        TLB_MISS_RESTORE_STATS_BOLTED
+        TLB_MISS_RESTORE_STATS
-        ld      r16,PACA_EXTLB+EX_TLB_R16(r13)
+        ld      r16,EX_TLB_R16(r12)
-        mfspr   r13,SPRN_SPRG_GEN_SCRATCH
+        mfspr   r12,SPRN_SPRG_GEN_SCRATCH
 .endm
 /* Data TLB miss */
@@ -284,7 +296,7 @@ itlb_miss_fault_bolted:
 * r14 = page table base
 * r13 = PACA
 * r11 = tlb_per_core ptr
- * r10 = crap (free to use)
+ * r10 = cpu number
 */
 tlb_miss_common_e6500:
        /*
@@ -293,15 +305,18 @@ tlb_miss_common_e6500:
         *
         * MAS6:IND should be already set based on MAS4
         */
-        addi    r10,r11,TCD_LOCK
+1:      lbarx   r15,0,r11
-1:      lbarx   r15,0,r10
+        lhz     r10,PACAPACAINDEX(r13)
        cmpdi   r15,0
+        cmpdi   cr1,r15,1       /* set cr1.eq = 0 for non-recursive */
        bne     2f
-        li      r15,1
+        stbcx.  r10,0,r11
-        stbcx.  r15,0,r10
        bne     1b
+3:
        .subsection 1
-2:      lbz     r15,0(r10)
+2:      cmpd    cr1,r15,r10     /* recursive lock due to mcheck/crit/etc? */
+        beq     cr1,3b          /* unlock will happen if cr1.eq = 0 */
+        lbz     r15,0(r11)
        cmpdi   r15,0
        bne     2b
        b       1b
@@ -379,9 +394,11 @@ tlb_miss_common_e6500:
 tlb_miss_done_e6500:
        .macro  tlb_unlock_e6500
+        beq     cr1,1f          /* no unlock if lock was recursively grabbed */
        li      r15,0
        isync
-        stb     r15,TCD_LOCK(r11)
+        stb     r15,0(r11)
+1:
        .endm
        tlb_unlock_e6500
@@ -1091,7 +1108,8 @@ tlb_load_linear:
        ld      r11,PACATOC(r13)
        ld      r11,linear_map_top@got(r11)
        ld      r10,0(r11)
-        cmpld   cr0,r10,r16
+        tovirt(10,10)
+        cmpld   cr0,r16,r10
        bge     tlb_load_linear_fault
        /* MAS1 need whole new setup. */
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index b37a58e1c92d..ae3d5b799b90 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -144,6 +144,15 @@ int mmu_vmemmap_psize;		/* Page size used for the virtual mem map */
 int book3e_htw_mode;            /* HW tablewalk?  Value is PPC_HTW_* */
 unsigned long linear_map_top;   /* Top of linear mapping */
+/*
+ * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug
+ * exceptions.  This is used for bolted and e6500 TLB miss handlers which
+ * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
+ * this is set to zero.
+ */
+int extlb_level_exc;
 #endif /* CONFIG_PPC64 */
 #ifdef CONFIG_PPC_FSL_BOOK3E
@@ -559,6 +568,7 @@ static void setup_mmu_htw(void)
                break;
 #ifdef CONFIG_PPC_FSL_BOOK3E
        case PPC_HTW_E6500:
+                extlb_level_exc = EX_TLB_SIZE;
                patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
                patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
                break;
@@ -652,6 +662,7 @@ static void __early_init_mmu(int boot_cpu)
                memblock_enforce_memory_limit(linear_map_top);
                if (book3e_htw_mode == PPC_HTW_NONE) {
+                        extlb_level_exc = EX_TLB_SIZE;
                        patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
                        patch_exception(0x1e0,
                                exc_instruction_tlb_miss_bolted_book3e);
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index 555034f8505e..808ce1cae21a 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -390,9 +390,9 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                                                          mark));
                        break;
                case BPF_S_ANC_RXHASH:
-                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, rxhash) != 4);
+                        BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
                        PPC_LWZ_OFFS(r_A, r_skb, offsetof(struct sk_buff,
-                                                          rxhash));
+                                                          hash));
                        break;
                case BPF_S_ANC_VLAN_TAG:
                case BPF_S_ANC_VLAN_TAG_PRESENT:
@@ -689,6 +689,7 @@ void bpf_jit_compile(struct sk_filter *fp)
                ((u64 *)image)[0] = (u64)code_base;
                ((u64 *)image)[1] = local_paca->kernel_toc;
                fp->bpf_func = (void *)image;
+                fp->jited = 1;
        }
 out:
        kfree(addrs);
@@ -697,7 +698,7 @@ out:
 void bpf_jit_free(struct sk_filter *fp)
 {
-        if (fp->bpf_func != sk_run_filter)
+        if (fp->jited)
                module_free(NULL, fp->bpf_func);
        kfree(fp);
 }
diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c
index 1f0ebdeea5f7..863d89386f60 100644
--- a/arch/powerpc/oprofile/op_model_cell.c
+++ b/arch/powerpc/oprofile/op_model_cell.c
@@ -1121,8 +1121,7 @@ oprof_cpufreq_notify(struct notifier_block *nb, unsigned long val, void *data)
        int ret = 0;
        struct cpufreq_freqs *frq = data;
        if ((val == CPUFREQ_PRECHANGE && frq->old < frq->new) ||
-            (val == CPUFREQ_POSTCHANGE && frq->old > frq->new) ||
+            (val == CPUFREQ_POSTCHANGE && frq->old > frq->new))
-            (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE))
                set_spu_profiling_frequency(frq->new, spu_cycle_reset);
        return ret;
 }
diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile
index 60d71eea919c..f9c083a5652a 100644
--- a/arch/powerpc/perf/Makefile
+++ b/arch/powerpc/perf/Makefile
@@ -11,5 +11,7 @@ obj32-$(CONFIG_PPC_PERF_CTRS)	+= mpc7450-pmu.o
 obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o
 obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
+obj-$(CONFIG_HV_PERF_CTRS) += hv-24x7.o hv-gpci.o hv-common.o
 obj-$(CONFIG_PPC64)             += $(obj64-y)
 obj-$(CONFIG_PPC32)             += $(obj32-y)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 67cf22083f4c..4520c9356b54 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -78,6 +78,7 @@ static unsigned int freeze_events_kernel = MMCR0_FCS;
 #define MMCR0_FC56              0
 #define MMCR0_PMAO              0
 #define MMCR0_EBE               0
+#define MMCR0_BHRBA             0
 #define MMCR0_PMCC              0
 #define MMCR0_PMCC_U6           0
@@ -120,6 +121,7 @@ static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
 void power_pmu_flush_branch_stack(void) {}
 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
+static void pmao_restore_workaround(bool ebb) { }
 #endif /* CONFIG_PPC32 */
 static bool regs_use_siar(struct pt_regs *regs)
@@ -502,8 +504,11 @@ static int ebb_event_check(struct perf_event *event)
                if (!leader->attr.pinned || !leader->attr.exclusive)
                        return -EINVAL;
-                if (event->attr.inherit || event->attr.sample_period ||
+                if (event->attr.freq ||
-                    event->attr.enable_on_exec || event->attr.freq)
+                    event->attr.inherit ||
+                    event->attr.sample_type ||
+                    event->attr.sample_period ||
+                    event->attr.enable_on_exec)
                        return -EINVAL;
        }
@@ -542,13 +547,21 @@ static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
        if (!ebb)
                goto out;
-        /* Enable EBB and read/write to all 6 PMCs for userspace */
+        /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
-        mmcr0 |= MMCR0_EBE | MMCR0_PMCC_U6;
+        mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
-        /* Add any bits from the user reg, FC or PMAO */
+        /*
+         * Add any bits from the user MMCR0, FC or PMAO. This is compatible
+         * with pmao_restore_workaround() because we may add PMAO but we never
+         * clear it here.
+         */
        mmcr0 |= current->thread.mmcr0;
-        /* Be careful not to set PMXE if userspace had it cleared */
+        /*
+         * Be careful not to set PMXE if userspace had it cleared. This is also
+         * compatible with pmao_restore_workaround() because it has already
+         * cleared PMXE and we leave PMAO alone.
+         */
        if (!(current->thread.mmcr0 & MMCR0_PMXE))
                mmcr0 &= ~MMCR0_PMXE;
@@ -559,13 +572,94 @@ static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
 out:
        return mmcr0;
 }
-#endif /* CONFIG_PPC64 */
-static void perf_event_interrupt(struct pt_regs *regs);
-void perf_event_print_debug(void)
+static void pmao_restore_workaround(bool ebb)
 {
+        unsigned pmcs[6];
+        if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
+                return;
+        /*
+         * On POWER8E there is a hardware defect which affects the PMU context
+         * switch logic, ie. power_pmu_disable/enable().
+         *
+         * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
+         * by the hardware. Sometime later the actual PMU exception is
+         * delivered.
+         *
+         * If we context switch, or simply disable/enable, the PMU prior to the
+         * exception arriving, the exception will be lost when we clear PMAO.
+         *
+         * When we reenable the PMU, we will write the saved MMCR0 with PMAO
+         * set, and this _should_ generate an exception. However because of the
+         * defect no exception is generated when we write PMAO, and we get
+         * stuck with no counters counting but no exception delivered.
+         *
+         * The workaround is to detect this case and tweak the hardware to
+         * create another pending PMU exception.
+         *
+         * We do that by setting up PMC6 (cycles) for an imminent overflow and
+         * enabling the PMU. That causes a new exception to be generated in the
+         * chip, but we don't take it yet because we have interrupts hard
+         * disabled. We then write back the PMU state as we want it to be seen
+         * by the exception handler. When we reenable interrupts the exception
+         * handler will be called and see the correct state.
+         *
+         * The logic is the same for EBB, except that the exception is gated by
+         * us having interrupts hard disabled as well as the fact that we are
+         * not in userspace. The exception is finally delivered when we return
+         * to userspace.
+         */
+        /* Only if PMAO is set and PMAO_SYNC is clear */
+        if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
+                return;
+        /* If we're doing EBB, only if BESCR[GE] is set */
+        if (ebb && !(current->thread.bescr & BESCR_GE))
+                return;
+        /*
+         * We are already soft-disabled in power_pmu_enable(). We need to hard
+         * enable to actually prevent the PMU exception from firing.
+         */
+        hard_irq_disable();
+        /*
+         * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
+         * Using read/write_pmc() in a for loop adds 12 function calls and
+         * almost doubles our code size.
+         */
+        pmcs[0] = mfspr(SPRN_PMC1);
+        pmcs[1] = mfspr(SPRN_PMC2);
+        pmcs[2] = mfspr(SPRN_PMC3);
+        pmcs[3] = mfspr(SPRN_PMC4);
+        pmcs[4] = mfspr(SPRN_PMC5);
+        pmcs[5] = mfspr(SPRN_PMC6);
+        /* Ensure all freeze bits are unset */
+        mtspr(SPRN_MMCR2, 0);
+        /* Set up PMC6 to overflow in one cycle */
+        mtspr(SPRN_PMC6, 0x7FFFFFFE);
+        /* Enable exceptions and unfreeze PMC6 */
+        mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
+        /* Now we need to refreeze and restore the PMCs */
+        mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
+        mtspr(SPRN_PMC1, pmcs[0]);
+        mtspr(SPRN_PMC2, pmcs[1]);
+        mtspr(SPRN_PMC3, pmcs[2]);
+        mtspr(SPRN_PMC4, pmcs[3]);
+        mtspr(SPRN_PMC5, pmcs[4]);
+        mtspr(SPRN_PMC6, pmcs[5]);
 }
+#endif /* CONFIG_PPC64 */
+static void perf_event_interrupt(struct pt_regs *regs);
 /*
 * Read one performance monitor counter (PMC).
@@ -645,6 +739,57 @@ static void write_pmc(int idx, unsigned long val)
        }
 }
+/* Called from sysrq_handle_showregs() */
+void perf_event_print_debug(void)
+{
+        unsigned long sdar, sier, flags;
+        u32 pmcs[MAX_HWEVENTS];
+        int i;
+        if (!ppmu->n_counter)
+                return;
+        local_irq_save(flags);
+        pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
+                 smp_processor_id(), ppmu->name, ppmu->n_counter);
+        for (i = 0; i < ppmu->n_counter; i++)
+                pmcs[i] = read_pmc(i + 1);
+        for (; i < MAX_HWEVENTS; i++)
+                pmcs[i] = 0xdeadbeef;
+        pr_info("PMC1:  %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
+                 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
+        if (ppmu->n_counter > 4)
+                pr_info("PMC5:  %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
+                         pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
+        pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
+                mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
+        sdar = sier = 0;
+#ifdef CONFIG_PPC64
+        sdar = mfspr(SPRN_SDAR);
+        if (ppmu->flags & PPMU_HAS_SIER)
+                sier = mfspr(SPRN_SIER);
+        if (ppmu->flags & PPMU_EBB) {
+                pr_info("MMCR2: %016lx EBBHR: %016lx\n",
+                        mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
+                pr_info("EBBRR: %016lx BESCR: %016lx\n",
+                        mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
+        }
+#endif
+        pr_info("SIAR:  %016lx SDAR:  %016lx SIER:  %016lx\n",
+                mfspr(SPRN_SIAR), sdar, sier);
+        local_irq_restore(flags);
+}
 /*
 * Check if a set of events can all go on the PMU at once.
 * If they can't, this will look at alternative codes for the events
@@ -973,11 +1118,12 @@ static void power_pmu_disable(struct pmu *pmu)
                }
                /*
-                 * Set the 'freeze counters' bit, clear EBE/PMCC/PMAO/FC56.
+                 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
                 */
                val  = mmcr0 = mfspr(SPRN_MMCR0);
                val |= MMCR0_FC;
-                val &= ~(MMCR0_EBE | MMCR0_PMCC | MMCR0_PMAO | MMCR0_FC56);
+                val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
+                         MMCR0_FC56);
                /*
                 * The barrier is to make sure the mtspr has been
@@ -1144,6 +1290,8 @@ static void power_pmu_enable(struct pmu *pmu)
        cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
 out_enable:
+        pmao_restore_workaround(ebb);
        mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]);
        mb();
diff --git a/arch/powerpc/perf/hv-24x7-catalog.h b/arch/powerpc/perf/hv-24x7-catalog.h
new file mode 100644
index 000000000000..21b19dd86d9c
--- /dev/null
+++ b/arch/powerpc/perf/hv-24x7-catalog.h
@@ -0,0 +1,33 @@
+#ifndef LINUX_POWERPC_PERF_HV_24X7_CATALOG_H_
+#define LINUX_POWERPC_PERF_HV_24X7_CATALOG_H_
+#include <linux/types.h>
+/* From document "24x7 Event and Group Catalog Formats Proposal" v0.15 */
+struct hv_24x7_catalog_page_0 {
+#define HV_24X7_CATALOG_MAGIC 0x32347837 /* "24x7" in ASCII */
+        __be32 magic;
+        __be32 length; /* In 4096 byte pages */
+        __be64 version; /* XXX: arbitrary? what's the meaning/useage/purpose? */
+        __u8 build_time_stamp[16]; /* "YYYYMMDDHHMMSS\0\0" */
+        __u8 reserved2[32];
+        __be16 schema_data_offs; /* in 4096 byte pages */
+        __be16 schema_data_len;  /* in 4096 byte pages */
+        __be16 schema_entry_count;
+        __u8 reserved3[2];
+        __be16 event_data_offs;
+        __be16 event_data_len;
+        __be16 event_entry_count;
+        __u8 reserved4[2];
+        __be16 group_data_offs; /* in 4096 byte pages */
+        __be16 group_data_len;  /* in 4096 byte pages */
+        __be16 group_entry_count;
+        __u8 reserved5[2];
+        __be16 formula_data_offs; /* in 4096 byte pages */
+        __be16 formula_data_len;  /* in 4096 byte pages */
+        __be16 formula_entry_count;
+        __u8 reserved6[2];
+} __packed;
+#endif
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
new file mode 100644
index 000000000000..297c91051413
--- /dev/null
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -0,0 +1,510 @@
+/*
+ * Hypervisor supplied "24x7" performance counter support
+ *
+ * Author: Cody P Schafer <cody@linux.vnet.ibm.com>
+ * Copyright 2014 IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#define pr_fmt(fmt) "hv-24x7: " fmt
+#include <linux/perf_event.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <asm/firmware.h>
+#include <asm/hvcall.h>
+#include <asm/io.h>
+#include "hv-24x7.h"
+#include "hv-24x7-catalog.h"
+#include "hv-common.h"
+/*
+ * TODO: Merging events:
+ * - Think of the hcall as an interface to a 4d array of counters:
+ *   - x = domains
+ *   - y = indexes in the domain (core, chip, vcpu, node, etc)
+ *   - z = offset into the counter space
+ *   - w = lpars (guest vms, "logical partitions")
+ * - A single request is: x,y,y_last,z,z_last,w,w_last
+ *   - this means we can retrieve a rectangle of counters in y,z for a single x.
+ *
+ * - Things to consider (ignoring w):
+ *   - input  cost_per_request = 16
+ *   - output cost_per_result(ys,zs)  = 8 + 8 * ys + ys * zs
+ *   - limited number of requests per hcall (must fit into 4K bytes)
+ *     - 4k = 16 [buffer header] - 16 [request size] * request_count
+ *     - 255 requests per hcall
+ *   - sometimes it will be more efficient to read extra data and discard
+ */
+/*
+ * Example usage:
+ *  perf stat -e 'hv_24x7/domain=2,offset=8,starting_index=0,lpar=0xffffffff/'
+ */
+/* u3 0-6, one of HV_24X7_PERF_DOMAIN */
+EVENT_DEFINE_RANGE_FORMAT(domain, config, 0, 3);
+/* u16 */
+EVENT_DEFINE_RANGE_FORMAT(starting_index, config, 16, 31);
+/* u32, see "data_offset" */
+EVENT_DEFINE_RANGE_FORMAT(offset, config, 32, 63);
+/* u16 */
+EVENT_DEFINE_RANGE_FORMAT(lpar, config1, 0, 15);
+EVENT_DEFINE_RANGE(reserved1, config,   4, 15);
+EVENT_DEFINE_RANGE(reserved2, config1, 16, 63);
+EVENT_DEFINE_RANGE(reserved3, config2,  0, 63);
+static struct attribute *format_attrs[] = {
+        &format_attr_domain.attr,
+        &format_attr_offset.attr,
+        &format_attr_starting_index.attr,
+        &format_attr_lpar.attr,
+        NULL,
+};
+static struct attribute_group format_group = {
+        .name = "format",
+        .attrs = format_attrs,
+};
+static struct kmem_cache *hv_page_cache;
+/*
+ * read_offset_data - copy data from one buffer to another while treating the
+ *                    source buffer as a small view on the total avaliable
+ *                    source data.
+ *
+ * @dest: buffer to copy into
+ * @dest_len: length of @dest in bytes
+ * @requested_offset: the offset within the source data we want. Must be > 0
+ * @src: buffer to copy data from
+ * @src_len: length of @src in bytes
+ * @source_offset: the offset in the sorce data that (src,src_len) refers to.
+ *                 Must be > 0
+ *
+ * returns the number of bytes copied.
+ *
+ * The following ascii art shows the various buffer possitioning we need to
+ * handle, assigns some arbitrary varibles to points on the buffer, and then
+ * shows how we fiddle with those values to get things we care about (copy
+ * start in src and copy len)
+ *
+ * s = @src buffer
+ * d = @dest buffer
+ * '.' areas in d are written to.
+ *
+ *                       u
+ *   x         w         v  z
+ * d           |.........|
+ * s |----------------------|
+ *
+ *                      u
+ *   x         w        z     v
+ * d           |........------|
+ * s |------------------|
+ *
+ *   x         w        u,z,v
+ * d           |........|
+ * s |------------------|
+ *
+ *   x,w                u,v,z
+ * d |..................|
+ * s |------------------|
+ *
+ *   x        u
+ *   w        v         z
+ * d |........|
+ * s |------------------|
+ *
+ *   x      z   w      v
+ * d            |------|
+ * s |------|
+ *
+ * x = source_offset
+ * w = requested_offset
+ * z = source_offset + src_len
+ * v = requested_offset + dest_len
+ *
+ * w_offset_in_s = w - x = requested_offset - source_offset
+ * z_offset_in_s = z - x = src_len
+ * v_offset_in_s = v - x = request_offset + dest_len - src_len
+ */
+static ssize_t read_offset_data(void *dest, size_t dest_len,
+                                loff_t requested_offset, void *src,
+                                size_t src_len, loff_t source_offset)
+{
+        size_t w_offset_in_s = requested_offset - source_offset;
+        size_t z_offset_in_s = src_len;
+        size_t v_offset_in_s = requested_offset + dest_len - src_len;
+        size_t u_offset_in_s = min(z_offset_in_s, v_offset_in_s);
+        size_t copy_len = u_offset_in_s - w_offset_in_s;
+        if (requested_offset < 0 || source_offset < 0)
+                return -EINVAL;
+        if (z_offset_in_s <= w_offset_in_s)
+                return 0;
+        memcpy(dest, src + w_offset_in_s, copy_len);
+        return copy_len;
+}
+static unsigned long h_get_24x7_catalog_page(char page[static 4096],
+                                             u32 version, u32 index)
+{
+        WARN_ON(!IS_ALIGNED((unsigned long)page, 4096));
+        return plpar_hcall_norets(H_GET_24X7_CATALOG_PAGE,
+                        virt_to_phys(page),
+                        version,
+                        index);
+}
+static ssize_t catalog_read(struct file *filp, struct kobject *kobj,
+                            struct bin_attribute *bin_attr, char *buf,
+                            loff_t offset, size_t count)
+{
+        unsigned long hret;
+        ssize_t ret = 0;
+        size_t catalog_len = 0, catalog_page_len = 0, page_count = 0;
+        loff_t page_offset = 0;
+        uint32_t catalog_version_num = 0;
+        void *page = kmem_cache_alloc(hv_page_cache, GFP_USER);
+        struct hv_24x7_catalog_page_0 *page_0 = page;
+        if (!page)
+                return -ENOMEM;
+        hret = h_get_24x7_catalog_page(page, 0, 0);
+        if (hret) {
+                ret = -EIO;
+                goto e_free;
+        }
+        catalog_version_num = be32_to_cpu(page_0->version);
+        catalog_page_len = be32_to_cpu(page_0->length);
+        catalog_len = catalog_page_len * 4096;
+        page_offset = offset / 4096;
+        page_count  = count  / 4096;
+        if (page_offset >= catalog_page_len)
+                goto e_free;
+        if (page_offset != 0) {
+                hret = h_get_24x7_catalog_page(page, catalog_version_num,
+                                               page_offset);
+                if (hret) {
+                        ret = -EIO;
+                        goto e_free;
+                }
+        }
+        ret = read_offset_data(buf, count, offset,
+                                page, 4096, page_offset * 4096);
+e_free:
+        if (hret)
+                pr_err("h_get_24x7_catalog_page(ver=%d, page=%lld) failed: rc=%ld\n",
+                                catalog_version_num, page_offset, hret);
+        kfree(page);
+        pr_devel("catalog_read: offset=%lld(%lld) count=%zu(%zu) catalog_len=%zu(%zu) => %zd\n",
+                        offset, page_offset, count, page_count, catalog_len,
+                        catalog_page_len, ret);
+        return ret;
+}
+#define PAGE_0_ATTR(_name, _fmt, _expr)                         \
+static ssize_t _name##_show(struct device *dev,                 \
+                            struct device_attribute *dev_attr,  \
+                            char *buf)                          \
+{                                                               \
+        unsigned long hret;                                     \
+        ssize_t ret = 0;                                        \
+        void *page = kmem_cache_alloc(hv_page_cache, GFP_USER); \
+        struct hv_24x7_catalog_page_0 *page_0 = page;           \
+        if (!page)                                              \
+                return -ENOMEM;                                 \
+        hret = h_get_24x7_catalog_page(page, 0, 0);             \
+        if (hret) {                                             \
+                ret = -EIO;                                     \
+                goto e_free;                                    \
+        }                                                       \
+        ret = sprintf(buf, _fmt, _expr);                        \
+e_free:                                                         \
+        kfree(page);                                            \
+        return ret;                                             \
+}                                                               \
+static DEVICE_ATTR_RO(_name)
+PAGE_0_ATTR(catalog_version, "%lld\n",
+                (unsigned long long)be32_to_cpu(page_0->version));
+PAGE_0_ATTR(catalog_len, "%lld\n",
+                (unsigned long long)be32_to_cpu(page_0->length) * 4096);
+static BIN_ATTR_RO(catalog, 0/* real length varies */);
+static struct bin_attribute *if_bin_attrs[] = {
+        &bin_attr_catalog,
+        NULL,
+};
+static struct attribute *if_attrs[] = {
+        &dev_attr_catalog_len.attr,
+        &dev_attr_catalog_version.attr,
+        NULL,
+};
+static struct attribute_group if_group = {
+        .name = "interface",
+        .bin_attrs = if_bin_attrs,
+        .attrs = if_attrs,
+};
+static const struct attribute_group *attr_groups[] = {
+        &format_group,
+        &if_group,
+        NULL,
+};
+static bool is_physical_domain(int domain)
+{
+        return  domain == HV_24X7_PERF_DOMAIN_PHYSICAL_CHIP ||
+                domain == HV_24X7_PERF_DOMAIN_PHYSICAL_CORE;
+}
+static unsigned long single_24x7_request(u8 domain, u32 offset, u16 ix,
+                                         u16 lpar, u64 *res,
+                                         bool success_expected)
+{
+        unsigned long ret;
+        /*
+         * request_buffer and result_buffer are not required to be 4k aligned,
+         * but are not allowed to cross any 4k boundary. Aligning them to 4k is
+         * the simplest way to ensure that.
+         */
+        struct reqb {
+                struct hv_24x7_request_buffer buf;
+                struct hv_24x7_request req;
+        } __packed __aligned(4096) request_buffer = {
+                .buf = {
+                        .interface_version = HV_24X7_IF_VERSION_CURRENT,
+                        .num_requests = 1,
+                },
+                .req = {
+                        .performance_domain = domain,
+                        .data_size = cpu_to_be16(8),
+                        .data_offset = cpu_to_be32(offset),
+                        .starting_lpar_ix = cpu_to_be16(lpar),
+                        .max_num_lpars = cpu_to_be16(1),
+                        .starting_ix = cpu_to_be16(ix),
+                        .max_ix = cpu_to_be16(1),
+                }
+        };
+        struct resb {
+                struct hv_24x7_data_result_buffer buf;
+                struct hv_24x7_result res;
+                struct hv_24x7_result_element elem;
+                __be64 result;
+        } __packed __aligned(4096) result_buffer = {};
+        ret = plpar_hcall_norets(H_GET_24X7_DATA,
+                        virt_to_phys(&request_buffer), sizeof(request_buffer),
+                        virt_to_phys(&result_buffer),  sizeof(result_buffer));
+        if (ret) {
+                if (success_expected)
+                        pr_err_ratelimited("hcall failed: %d %#x %#x %d => 0x%lx (%ld) detail=0x%x failing ix=%x\n",
+                                        domain, offset, ix, lpar,
+                                        ret, ret,
+                                        result_buffer.buf.detailed_rc,
+                                        result_buffer.buf.failing_request_ix);
+                return ret;
+        }
+        *res = be64_to_cpu(result_buffer.result);
+        return ret;
+}
+static unsigned long event_24x7_request(struct perf_event *event, u64 *res,
+                bool success_expected)
+{
+        return single_24x7_request(event_get_domain(event),
+                                event_get_offset(event),
+                                event_get_starting_index(event),
+                                event_get_lpar(event),
+                                res,
+                                success_expected);
+}
+static int h_24x7_event_init(struct perf_event *event)
+{
+        struct hv_perf_caps caps;
+        unsigned domain;
+        unsigned long hret;
+        u64 ct;
+        /* Not our event */
+        if (event->attr.type != event->pmu->type)
+                return -ENOENT;
+        /* Unused areas must be 0 */
+        if (event_get_reserved1(event) ||
+            event_get_reserved2(event) ||
+            event_get_reserved3(event)) {
+                pr_devel("reserved set when forbidden 0x%llx(0x%llx) 0x%llx(0x%llx) 0x%llx(0x%llx)\n",
+                                event->attr.config,
+                                event_get_reserved1(event),
+                                event->attr.config1,
+                                event_get_reserved2(event),
+                                event->attr.config2,
+                                event_get_reserved3(event));
+                return -EINVAL;
+        }
+        /* unsupported modes and filters */
+        if (event->attr.exclude_user   ||
+            event->attr.exclude_kernel ||
+            event->attr.exclude_hv     ||
+            event->attr.exclude_idle   ||
+            event->attr.exclude_host   ||
+            event->attr.exclude_guest  ||
+            is_sampling_event(event)) /* no sampling */
+                return -EINVAL;
+        /* no branch sampling */
+        if (has_branch_stack(event))
+                return -EOPNOTSUPP;
+        /* offset must be 8 byte aligned */
+        if (event_get_offset(event) % 8) {
+                pr_devel("bad alignment\n");
+                return -EINVAL;
+        }
+        /* Domains above 6 are invalid */
+        domain = event_get_domain(event);
+        if (domain > 6) {
+                pr_devel("invalid domain %d\n", domain);
+                return -EINVAL;
+        }
+        hret = hv_perf_caps_get(&caps);
+        if (hret) {
+                pr_devel("could not get capabilities: rc=%ld\n", hret);
+                return -EIO;
+        }
+        /* PHYSICAL domains & other lpars require extra capabilities */
+        if (!caps.collect_privileged && (is_physical_domain(domain) ||
+                (event_get_lpar(event) != event_get_lpar_max()))) {
+                pr_devel("hv permisions disallow: is_physical_domain:%d, lpar=0x%llx\n",
+                                is_physical_domain(domain),
+                                event_get_lpar(event));
+                return -EACCES;
+        }
+        /* see if the event complains */
+        if (event_24x7_request(event, &ct, false)) {
+                pr_devel("test hcall failed\n");
+                return -EIO;
+        }
+        return 0;
+}
+static u64 h_24x7_get_value(struct perf_event *event)
+{
+        unsigned long ret;
+        u64 ct;
+        ret = event_24x7_request(event, &ct, true);
+        if (ret)
+                /* We checked this in event init, shouldn't fail here... */
+                return 0;
+        return ct;
+}
+static void h_24x7_event_update(struct perf_event *event)
+{
+        s64 prev;
+        u64 now;
+        now = h_24x7_get_value(event);
+        prev = local64_xchg(&event->hw.prev_count, now);
+        local64_add(now - prev, &event->count);
+}
+static void h_24x7_event_start(struct perf_event *event, int flags)
+{
+        if (flags & PERF_EF_RELOAD)
+                local64_set(&event->hw.prev_count, h_24x7_get_value(event));
+}
+static void h_24x7_event_stop(struct perf_event *event, int flags)
+{
+        h_24x7_event_update(event);
+}
+static int h_24x7_event_add(struct perf_event *event, int flags)
+{
+        if (flags & PERF_EF_START)
+                h_24x7_event_start(event, flags);
+        return 0;
+}
+static int h_24x7_event_idx(struct perf_event *event)
+{
+        return 0;
+}
+static struct pmu h_24x7_pmu = {
+        .task_ctx_nr = perf_invalid_context,
+        .name = "hv_24x7",
+        .attr_groups = attr_groups,
+        .event_init  = h_24x7_event_init,
+        .add         = h_24x7_event_add,
+        .del         = h_24x7_event_stop,
+        .start       = h_24x7_event_start,
+        .stop        = h_24x7_event_stop,
+        .read        = h_24x7_event_update,
+        .event_idx   = h_24x7_event_idx,
+};
+static int hv_24x7_init(void)
+{
+        int r;
+        unsigned long hret;
+        struct hv_perf_caps caps;
+        if (!firmware_has_feature(FW_FEATURE_LPAR)) {
+                pr_info("not a virtualized system, not enabling\n");
+                return -ENODEV;
+        }
+        hret = hv_perf_caps_get(&caps);
+        if (hret) {
+                pr_info("could not obtain capabilities, error 0x%80lx, not enabling\n",
+                                hret);
+                return -ENODEV;
+        }
+        hv_page_cache = kmem_cache_create("hv-page-4096", 4096, 4096, 0, NULL);
+        if (!hv_page_cache)
+                return -ENOMEM;
+        r = perf_pmu_register(&h_24x7_pmu, h_24x7_pmu.name, -1);
+        if (r)
+                return r;
+        return 0;
+}
+device_initcall(hv_24x7_init);
diff --git a/arch/powerpc/perf/hv-24x7.h b/arch/powerpc/perf/hv-24x7.h
new file mode 100644
index 000000000000..720ebce4b435
--- /dev/null
+++ b/arch/powerpc/perf/hv-24x7.h
@@ -0,0 +1,109 @@
+#ifndef LINUX_POWERPC_PERF_HV_24X7_H_
+#define LINUX_POWERPC_PERF_HV_24X7_H_
+#include <linux/types.h>
+struct hv_24x7_request {
+        /* PHYSICAL domains require enabling via phyp/hmc. */
+#define HV_24X7_PERF_DOMAIN_PHYSICAL_CHIP 0x01
+#define HV_24X7_PERF_DOMAIN_PHYSICAL_CORE 0x02
+#define HV_24X7_PERF_DOMAIN_VIRTUAL_PROCESSOR_HOME_CORE   0x03
+#define HV_24X7_PERF_DOMAIN_VIRTUAL_PROCESSOR_HOME_CHIP   0x04
+#define HV_24X7_PERF_DOMAIN_VIRTUAL_PROCESSOR_HOME_NODE   0x05
+#define HV_24X7_PERF_DOMAIN_VIRTUAL_PROCESSOR_REMOTE_NODE 0x06
+        __u8 performance_domain;
+        __u8 reserved[0x1];
+        /* bytes to read starting at @data_offset. must be a multiple of 8 */
+        __be16 data_size;
+        /*
+         * byte offset within the perf domain to read from. must be 8 byte
+         * aligned
+         */
+        __be32 data_offset;
+        /*
+         * only valid for VIRTUAL_PROCESSOR domains, ignored for others.
+         * -1 means "current partition only"
+         *  Enabling via phyp/hmc required for non-"-1" values. 0 forbidden
+         *  unless requestor is 0.
+         */
+        __be16 starting_lpar_ix;
+        /*
+         * Ignored when @starting_lpar_ix == -1
+         * Ignored when @performance_domain is not VIRTUAL_PROCESSOR_*
+         * -1 means "infinite" or all
+         */
+        __be16 max_num_lpars;
+        /* chip, core, or virtual processor based on @performance_domain */
+        __be16 starting_ix;
+        __be16 max_ix;
+} __packed;
+struct hv_24x7_request_buffer {
+        /* 0 - ? */
+        /* 1 - ? */
+#define HV_24X7_IF_VERSION_CURRENT 0x01
+        __u8 interface_version;
+        __u8 num_requests;
+        __u8 reserved[0xE];
+        struct hv_24x7_request requests[];
+} __packed;
+struct hv_24x7_result_element {
+        __be16 lpar_ix;
+        /*
+         * represents the core, chip, or virtual processor based on the
+         * request's @performance_domain
+         */
+        __be16 domain_ix;
+        /* -1 if @performance_domain does not refer to a virtual processor */
+        __be32 lpar_cfg_instance_id;
+        /* size = @result_element_data_size of cointaining result. */
+        __u8 element_data[];
+} __packed;
+struct hv_24x7_result {
+        __u8 result_ix;
+        /*
+         * 0 = not all result elements fit into the buffer, additional requests
+         *     required
+         * 1 = all result elements were returned
+         */
+        __u8 results_complete;
+        __be16 num_elements_returned;
+        /* This is a copy of @data_size from the coresponding hv_24x7_request */
+        __be16 result_element_data_size;
+        __u8 reserved[0x2];
+        /* WARNING: only valid for first result element due to variable sizes
+         *          of result elements */
+        /* struct hv_24x7_result_element[@num_elements_returned] */
+        struct hv_24x7_result_element elements[];
+} __packed;
+struct hv_24x7_data_result_buffer {
+        /* See versioning for request buffer */
+        __u8 interface_version;
+        __u8 num_results;
+        __u8 reserved[0x1];
+        __u8 failing_request_ix;
+        __be32 detailed_rc;
+        __be64 cec_cfg_instance_id;
+        __be64 catalog_version_num;
+        __u8 reserved2[0x8];
+        /* WARNING: only valid for the first result due to variable sizes of
+         *          results */
+        struct hv_24x7_result results[]; /* [@num_results] */
+} __packed;
+#endif
diff --git a/arch/powerpc/perf/hv-common.c b/arch/powerpc/perf/hv-common.c
new file mode 100644
index 000000000000..47e02b366f58
--- /dev/null
+++ b/arch/powerpc/perf/hv-common.c
@@ -0,0 +1,39 @@
+#include <asm/io.h>
+#include <asm/hvcall.h>
+#include "hv-gpci.h"
+#include "hv-common.h"
+unsigned long hv_perf_caps_get(struct hv_perf_caps *caps)
+{
+        unsigned long r;
+        struct p {
+                struct hv_get_perf_counter_info_params params;
+                struct cv_system_performance_capabilities caps;
+        } __packed __aligned(sizeof(uint64_t));
+        struct p arg = {
+                .params = {
+                        .counter_request = cpu_to_be32(
+                                        CIR_SYSTEM_PERFORMANCE_CAPABILITIES),
+                        .starting_index = cpu_to_be32(-1),
+                        .counter_info_version_in = 0,
+                }
+        };
+        r = plpar_hcall_norets(H_GET_PERF_COUNTER_INFO,
+                               virt_to_phys(&arg), sizeof(arg));
+        if (r)
+                return r;
+        pr_devel("capability_mask: 0x%x\n", arg.caps.capability_mask);
+        caps->version = arg.params.counter_info_version_out;
+        caps->collect_privileged = !!arg.caps.perf_collect_privileged;
+        caps->ga = !!(arg.caps.capability_mask & CV_CM_GA);
+        caps->expanded = !!(arg.caps.capability_mask & CV_CM_EXPANDED);
+        caps->lab = !!(arg.caps.capability_mask & CV_CM_LAB);
+        return r;
+}
diff --git a/arch/powerpc/perf/hv-common.h b/arch/powerpc/perf/hv-common.h
new file mode 100644
index 000000000000..5d79cecbd73d
--- /dev/null
+++ b/arch/powerpc/perf/hv-common.h
@@ -0,0 +1,36 @@
+#ifndef LINUX_POWERPC_PERF_HV_COMMON_H_
+#define LINUX_POWERPC_PERF_HV_COMMON_H_
+#include <linux/perf_event.h>
+#include <linux/types.h>
+struct hv_perf_caps {
+        u16 version;
+        u16 collect_privileged:1,
+            ga:1,
+            expanded:1,
+            lab:1,
+            unused:12;
+};
+unsigned long hv_perf_caps_get(struct hv_perf_caps *caps);
+#define EVENT_DEFINE_RANGE_FORMAT(name, attr_var, bit_start, bit_end)   \
+PMU_FORMAT_ATTR(name, #attr_var ":" #bit_start "-" #bit_end);           \
+EVENT_DEFINE_RANGE(name, attr_var, bit_start, bit_end)
+#define EVENT_DEFINE_RANGE(name, attr_var, bit_start, bit_end)  \
+static u64 event_get_##name##_max(void)                                 \
+{                                                                       \
+        BUILD_BUG_ON((bit_start > bit_end)                              \
+                    || (bit_end >= (sizeof(1ull) * 8)));                \
+        return (((1ull << (bit_end - bit_start)) - 1) << 1) + 1;        \
+}                                                                       \
+static u64 event_get_##name(struct perf_event *event)                   \
+{                                                                       \
+        return (event->attr.attr_var >> (bit_start)) &                  \
+                event_get_##name##_max();                               \
+}
+#endif
diff --git a/arch/powerpc/perf/hv-gpci.c b/arch/powerpc/perf/hv-gpci.c
new file mode 100644
index 000000000000..278ba7b9c2b5
--- /dev/null
+++ b/arch/powerpc/perf/hv-gpci.c
@@ -0,0 +1,294 @@
+/*
+ * Hypervisor supplied "gpci" ("get performance counter info") performance
+ * counter support
+ *
+ * Author: Cody P Schafer <cody@linux.vnet.ibm.com>
+ * Copyright 2014 IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#define pr_fmt(fmt) "hv-gpci: " fmt
+#include <linux/init.h>
+#include <linux/perf_event.h>
+#include <asm/firmware.h>
+#include <asm/hvcall.h>
+#include <asm/io.h>
+#include "hv-gpci.h"
+#include "hv-common.h"
+/*
+ * Example usage:
+ *  perf stat -e 'hv_gpci/counter_info_version=3,offset=0,length=8,
+ *                secondary_index=0,starting_index=0xffffffff,request=0x10/' ...
+ */
+/* u32 */
+EVENT_DEFINE_RANGE_FORMAT(request, config, 0, 31);
+/* u32 */
+EVENT_DEFINE_RANGE_FORMAT(starting_index, config, 32, 63);
+/* u16 */
+EVENT_DEFINE_RANGE_FORMAT(secondary_index, config1, 0, 15);
+/* u8 */
+EVENT_DEFINE_RANGE_FORMAT(counter_info_version, config1, 16, 23);
+/* u8, bytes of data (1-8) */
+EVENT_DEFINE_RANGE_FORMAT(length, config1, 24, 31);
+/* u32, byte offset */
+EVENT_DEFINE_RANGE_FORMAT(offset, config1, 32, 63);
+static struct attribute *format_attrs[] = {
+        &format_attr_request.attr,
+        &format_attr_starting_index.attr,
+        &format_attr_secondary_index.attr,
+        &format_attr_counter_info_version.attr,
+        &format_attr_offset.attr,
+        &format_attr_length.attr,
+        NULL,
+};
+static struct attribute_group format_group = {
+        .name = "format",
+        .attrs = format_attrs,
+};
+#define HV_CAPS_ATTR(_name, _format)                            \
+static ssize_t _name##_show(struct device *dev,                 \
+                            struct device_attribute *attr,      \
+                            char *page)                         \
+{                                                               \
+        struct hv_perf_caps caps;                               \
+        unsigned long hret = hv_perf_caps_get(&caps);           \
+        if (hret)                                               \
+                return -EIO;                                    \
+                                                                \
+        return sprintf(page, _format, caps._name);              \
+}                                                               \
+static struct device_attribute hv_caps_attr_##_name = __ATTR_RO(_name)
+static ssize_t kernel_version_show(struct device *dev,
+                                   struct device_attribute *attr,
+                                   char *page)
+{
+        return sprintf(page, "0x%x\n", COUNTER_INFO_VERSION_CURRENT);
+}
+DEVICE_ATTR_RO(kernel_version);
+HV_CAPS_ATTR(version, "0x%x\n");
+HV_CAPS_ATTR(ga, "%d\n");
+HV_CAPS_ATTR(expanded, "%d\n");
+HV_CAPS_ATTR(lab, "%d\n");
+HV_CAPS_ATTR(collect_privileged, "%d\n");
+static struct attribute *interface_attrs[] = {
+        &dev_attr_kernel_version.attr,
+        &hv_caps_attr_version.attr,
+        &hv_caps_attr_ga.attr,
+        &hv_caps_attr_expanded.attr,
+        &hv_caps_attr_lab.attr,
+        &hv_caps_attr_collect_privileged.attr,
+        NULL,
+};
+static struct attribute_group interface_group = {
+        .name = "interface",
+        .attrs = interface_attrs,
+};
+static const struct attribute_group *attr_groups[] = {
+        &format_group,
+        &interface_group,
+        NULL,
+};
+#define GPCI_MAX_DATA_BYTES \
+        (1024 - sizeof(struct hv_get_perf_counter_info_params))
+static unsigned long single_gpci_request(u32 req, u32 starting_index,
+                u16 secondary_index, u8 version_in, u32 offset, u8 length,
+                u64 *value)
+{
+        unsigned long ret;
+        size_t i;
+        u64 count;
+        struct {
+                struct hv_get_perf_counter_info_params params;
+                uint8_t bytes[GPCI_MAX_DATA_BYTES];
+        } __packed __aligned(sizeof(uint64_t)) arg = {
+                .params = {
+                        .counter_request = cpu_to_be32(req),
+                        .starting_index = cpu_to_be32(starting_index),
+                        .secondary_index = cpu_to_be16(secondary_index),
+                        .counter_info_version_in = version_in,
+                }
+        };
+        ret = plpar_hcall_norets(H_GET_PERF_COUNTER_INFO,
+                        virt_to_phys(&arg), sizeof(arg));
+        if (ret) {
+                pr_devel("hcall failed: 0x%lx\n", ret);
+                return ret;
+        }
+        /*
+         * we verify offset and length are within the zeroed buffer at event
+         * init.
+         */
+        count = 0;
+        for (i = offset; i < offset + length; i++)
+                count |= arg.bytes[i] << (i - offset);
+        *value = count;
+        return ret;
+}
+static u64 h_gpci_get_value(struct perf_event *event)
+{
+        u64 count;
+        unsigned long ret = single_gpci_request(event_get_request(event),
+                                        event_get_starting_index(event),
+                                        event_get_secondary_index(event),
+                                        event_get_counter_info_version(event),
+                                        event_get_offset(event),
+                                        event_get_length(event),
+                                        &count);
+        if (ret)
+                return 0;
+        return count;
+}
+static void h_gpci_event_update(struct perf_event *event)
+{
+        s64 prev;
+        u64 now = h_gpci_get_value(event);
+        prev = local64_xchg(&event->hw.prev_count, now);
+        local64_add(now - prev, &event->count);
+}
+static void h_gpci_event_start(struct perf_event *event, int flags)
+{
+        local64_set(&event->hw.prev_count, h_gpci_get_value(event));
+}
+static void h_gpci_event_stop(struct perf_event *event, int flags)
+{
+        h_gpci_event_update(event);
+}
+static int h_gpci_event_add(struct perf_event *event, int flags)
+{
+        if (flags & PERF_EF_START)
+                h_gpci_event_start(event, flags);
+        return 0;
+}
+static int h_gpci_event_init(struct perf_event *event)
+{
+        u64 count;
+        u8 length;
+        /* Not our event */
+        if (event->attr.type != event->pmu->type)
+                return -ENOENT;
+        /* config2 is unused */
+        if (event->attr.config2) {
+                pr_devel("config2 set when reserved\n");
+                return -EINVAL;
+        }
+        /* unsupported modes and filters */
+        if (event->attr.exclude_user   ||
+            event->attr.exclude_kernel ||
+            event->attr.exclude_hv     ||
+            event->attr.exclude_idle   ||
+            event->attr.exclude_host   ||
+            event->attr.exclude_guest  ||
+            is_sampling_event(event)) /* no sampling */
+                return -EINVAL;
+        /* no branch sampling */
+        if (has_branch_stack(event))
+                return -EOPNOTSUPP;
+        length = event_get_length(event);
+        if (length < 1 || length > 8) {
+                pr_devel("length invalid\n");
+                return -EINVAL;
+        }
+        /* last byte within the buffer? */
+        if ((event_get_offset(event) + length) > GPCI_MAX_DATA_BYTES) {
+                pr_devel("request outside of buffer: %zu > %zu\n",
+                                (size_t)event_get_offset(event) + length,
+                                GPCI_MAX_DATA_BYTES);
+                return -EINVAL;
+        }
+        /* check if the request works... */
+        if (single_gpci_request(event_get_request(event),
+                                event_get_starting_index(event),
+                                event_get_secondary_index(event),
+                                event_get_counter_info_version(event),
+                                event_get_offset(event),
+                                length,
+                                &count)) {
+                pr_devel("gpci hcall failed\n");
+                return -EINVAL;
+        }
+        return 0;
+}
+static int h_gpci_event_idx(struct perf_event *event)
+{
+        return 0;
+}
+static struct pmu h_gpci_pmu = {
+        .task_ctx_nr = perf_invalid_context,
+        .name = "hv_gpci",
+        .attr_groups = attr_groups,
+        .event_init  = h_gpci_event_init,
+        .add         = h_gpci_event_add,
+        .del         = h_gpci_event_stop,
+        .start       = h_gpci_event_start,
+        .stop        = h_gpci_event_stop,
+        .read        = h_gpci_event_update,
+        .event_idx   = h_gpci_event_idx,
+};
+static int hv_gpci_init(void)
+{
+        int r;
+        unsigned long hret;
+        struct hv_perf_caps caps;
+        if (!firmware_has_feature(FW_FEATURE_LPAR)) {
+                pr_info("not a virtualized system, not enabling\n");
+                return -ENODEV;
+        }
+        hret = hv_perf_caps_get(&caps);
+        if (hret) {
+                pr_info("could not obtain capabilities, error 0x%80lx, not enabling\n",
+                                hret);
+                return -ENODEV;
+        }
+        r = perf_pmu_register(&h_gpci_pmu, h_gpci_pmu.name, -1);
+        if (r)
+                return r;
+        return 0;
+}
+device_initcall(hv_gpci_init);
diff --git a/arch/powerpc/perf/hv-gpci.h b/arch/powerpc/perf/hv-gpci.h
new file mode 100644
index 000000000000..b25f460c9cce
--- /dev/null
+++ b/arch/powerpc/perf/hv-gpci.h
@@ -0,0 +1,73 @@
+#ifndef LINUX_POWERPC_PERF_HV_GPCI_H_
+#define LINUX_POWERPC_PERF_HV_GPCI_H_
+#include <linux/types.h>
+/* From the document "H_GetPerformanceCounterInfo Interface" v1.07 */
+/* H_GET_PERF_COUNTER_INFO argument */
+struct hv_get_perf_counter_info_params {
+        __be32 counter_request; /* I */
+        __be32 starting_index;  /* IO */
+        __be16 secondary_index; /* IO */
+        __be16 returned_values; /* O */
+        __be32 detail_rc; /* O, only needed when called via *_norets() */
+        /*
+         * O, size each of counter_value element in bytes, only set for version
+         * >= 0x3
+         */
+        __be16 cv_element_size;
+        /* I, 0 (zero) for versions < 0x3 */
+        __u8 counter_info_version_in;
+        /* O, 0 (zero) if version < 0x3. Must be set to 0 when making hcall */
+        __u8 counter_info_version_out;
+        __u8 reserved[0xC];
+        __u8 counter_value[];
+} __packed;
+/*
+ * counter info version => fw version/reference (spec version)
+ *
+ * 8 => power8 (1.07)
+ * [7 is skipped by spec 1.07]
+ * 6 => TLBIE (1.07)
+ * 5 => v7r7m0.phyp (1.05)
+ * [4 skipped]
+ * 3 => v7r6m0.phyp (?)
+ * [1,2 skipped]
+ * 0 => v7r{2,3,4}m0.phyp (?)
+ */
+#define COUNTER_INFO_VERSION_CURRENT 0x8
+/*
+ * These determine the counter_value[] layout and the meaning of starting_index
+ * and secondary_index.
+ *
+ * Unless otherwise noted, @secondary_index is unused and ignored.
+ */
+enum counter_info_requests {
+        /* GENERAL */
+        /* @starting_index: must be -1 (to refer to the current partition)
+         */
+        CIR_SYSTEM_PERFORMANCE_CAPABILITIES = 0X40,
+};
+struct cv_system_performance_capabilities {
+        /* If != 0, allowed to collect data from other partitions */
+        __u8 perf_collect_privileged;
+        /* These following are only valid if counter_info_version >= 0x3 */
+#define CV_CM_GA       (1 << 7)
+#define CV_CM_EXPANDED (1 << 6)
+#define CV_CM_LAB      (1 << 5)
+        /* remaining bits are reserved */
+        __u8 capability_mask;
+        __u8 reserved[0xE];
+} __packed;
+#endif
diff --git a/arch/powerpc/perf/power7-events-list.h b/arch/powerpc/perf/power7-events-list.h
index 687790a2c0b8..64f13d9260a6 100644
--- a/arch/powerpc/perf/power7-events-list.h
+++ b/arch/powerpc/perf/power7-events-list.h
@@ -546,3 +546,13 @@ EVENT(PM_MRK_DATA_FROM_RL2L3_SHR,             0x1d04c)
 EVENT(PM_DTLB_MISS_16M,                       0x4c05e)
 EVENT(PM_LSU1_LMQ_LHR_MERGE,                  0x0d09a)
 EVENT(PM_IFU_FIN,                             0x40066)
+EVENT(PM_1THRD_CON_RUN_INSTR,                 0x30062)
+EVENT(PM_CMPLU_STALL_COUNT,                   0x4000B)
+EVENT(PM_MEM0_PB_RD_CL,                       0x30083)
+EVENT(PM_THRD_1_RUN_CYC,                      0x10060)
+EVENT(PM_THRD_2_CONC_RUN_INSTR,               0x40062)
+EVENT(PM_THRD_2_RUN_CYC,                      0x20060)
+EVENT(PM_THRD_3_CONC_RUN_INST,                0x10062)
+EVENT(PM_THRD_3_RUN_CYC,                      0x30060)
+EVENT(PM_THRD_4_CONC_RUN_INST,                0x20062)
+EVENT(PM_THRD_4_RUN_CYC,                      0x40060)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 96cee20dcd34..fe2763b6e039 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -10,6 +10,8 @@
 * 2 of the License, or (at your option) any later version.
 */
+#define pr_fmt(fmt)     "power8-pmu: " fmt
 #include <linux/kernel.h>
 #include <linux/perf_event.h>
 #include <asm/firmware.h>
@@ -62,9 +64,11 @@
 *
 *        60        56        52        48        44        40        36        32
 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- *   |                                 [      thresh_cmp     ]   [  thresh_ctl   ]
+ *   | | [ ]                           [      thresh_cmp     ]   [  thresh_ctl   ]
- *   |                                                                   |
+ *   | |  |                                                              |
- *   *- EBB (Linux)                      thresh start/stop OR FAB match -*
+ *   | |  *- IFM (Linux)                 thresh start/stop OR FAB match -*
+ *   | *- BHRB (Linux)
+ *   *- EBB (Linux)
 *
 *        28        24        20        16        12         8         4         0
 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
@@ -114,9 +118,18 @@
 *      MMCRA[57:59] = sample[0:2]      (RAND_SAMP_ELIG)
  *     MMCRA[61:62] = sample[3:4]      (RAND_SAMP_MODE)
 *
+ * if EBB and BHRB:
+ *      MMCRA[32:33] = IFM
+ *
 */
 #define EVENT_EBB_MASK          1ull
+#define EVENT_EBB_SHIFT         PERF_EVENT_CONFIG_EBB_SHIFT
+#define EVENT_BHRB_MASK         1ull
+#define EVENT_BHRB_SHIFT        62
+#define EVENT_WANTS_BHRB        (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)
+#define EVENT_IFM_MASK          3ull
+#define EVENT_IFM_SHIFT         60
 #define EVENT_THR_CMP_SHIFT     40      /* Threshold CMP value */
 #define EVENT_THR_CMP_MASK      0x3ff
 #define EVENT_THR_CTL_SHIFT     32      /* Threshold control value (start/stop) */
@@ -141,6 +154,12 @@
 #define EVENT_IS_MARKED         (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
 #define EVENT_PSEL_MASK         0xff    /* PMCxSEL value */
+/* Bits defined by Linux */
+#define EVENT_LINUX_MASK        \
+        ((EVENT_EBB_MASK  << EVENT_EBB_SHIFT)                   |       \
+         (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)                  |       \
+         (EVENT_IFM_MASK  << EVENT_IFM_SHIFT))
 #define EVENT_VALID_MASK        \
        ((EVENT_THRESH_MASK    << EVENT_THRESH_SHIFT)           |       \
         (EVENT_SAMPLE_MASK    << EVENT_SAMPLE_SHIFT)           |       \
@@ -149,7 +168,7 @@
         (EVENT_UNIT_MASK      << EVENT_UNIT_SHIFT)             |       \
         (EVENT_COMBINE_MASK   << EVENT_COMBINE_SHIFT)          |       \
         (EVENT_MARKED_MASK    << EVENT_MARKED_SHIFT)           |       \
-         (EVENT_EBB_MASK       << PERF_EVENT_CONFIG_EBB_SHIFT)  |       \
+          EVENT_LINUX_MASK                                      |       \
          EVENT_PSEL_MASK)
 /* MMCRA IFM bits - POWER8 */
@@ -173,10 +192,11 @@
 *
 *        28        24        20        16        12         8         4         0
 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- *                   |   [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
+ *               [ ] |   [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
- *              EBB -*    |                     |
+ *                |  |    |                     |
- *                        |                     |      Count of events for each PMC.
+ *      BHRB IFM -*  |    |                     |      Count of events for each PMC.
- *      L1 I/D qualifier -*                     |        p1, p2, p3, p4, p5, p6.
+ *              EBB -*    |                     |        p1, p2, p3, p4, p5, p6.
+ *      L1 I/D qualifier -*                     |
 *                     nc - number of counters -*
 *
 * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
@@ -195,6 +215,9 @@
 #define CNST_EBB_VAL(v)         (((v) & EVENT_EBB_MASK) << 24)
 #define CNST_EBB_MASK           CNST_EBB_VAL(EVENT_EBB_MASK)
+#define CNST_IFM_VAL(v)         (((v) & EVENT_IFM_MASK) << 25)
+#define CNST_IFM_MASK           CNST_IFM_VAL(EVENT_IFM_MASK)
 #define CNST_L1_QUAL_VAL(v)     (((v) & 3) << 22)
 #define CNST_L1_QUAL_MASK       CNST_L1_QUAL_VAL(3)
@@ -241,6 +264,7 @@
 #define MMCRA_THR_SEL_SHIFT             16
 #define MMCRA_THR_CMP_SHIFT             32
 #define MMCRA_SDAR_MODE_TLB             (1ull << 42)
+#define MMCRA_IFM_SHIFT                 30
 static inline bool event_is_fab_match(u64 event)
@@ -265,20 +289,22 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
        pmc   = (event >> EVENT_PMC_SHIFT)        & EVENT_PMC_MASK;
        unit  = (event >> EVENT_UNIT_SHIFT)       & EVENT_UNIT_MASK;
        cache = (event >> EVENT_CACHE_SEL_SHIFT)  & EVENT_CACHE_SEL_MASK;
-        ebb   = (event >> PERF_EVENT_CONFIG_EBB_SHIFT) & EVENT_EBB_MASK;
+        ebb   = (event >> EVENT_EBB_SHIFT)        & EVENT_EBB_MASK;
-        /* Clear the EBB bit in the event, so event checks work below */
-        event &= ~(EVENT_EBB_MASK << PERF_EVENT_CONFIG_EBB_SHIFT);
        if (pmc) {
+                u64 base_event;
                if (pmc > 6)
                        return -1;
-                mask  |= CNST_PMC_MASK(pmc);
+                /* Ignore Linux defined bits when checking event below */
-                value |= CNST_PMC_VAL(pmc);
+                base_event = event & ~EVENT_LINUX_MASK;
-                if (pmc >= 5 && event != 0x500fa && event != 0x600f4)
+                if (pmc >= 5 && base_event != 0x500fa && base_event != 0x600f4)
                        return -1;
+                mask  |= CNST_PMC_MASK(pmc);
+                value |= CNST_PMC_VAL(pmc);
        }
        if (pmc <= 4) {
@@ -299,9 +325,10 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
                 * HV writable, and there is no API for guest kernels to modify
                 * it. The solution is for the hypervisor to initialise the
                 * field to zeroes, and for us to only ever allow events that
-                 * have a cache selector of zero.
+                 * have a cache selector of zero. The bank selector (bit 3) is
+                 * irrelevant, as long as the rest of the value is 0.
                 */
-                if (cache)
+                if (cache & 0x7)
                        return -1;
        } else if (event & EVENT_IS_L1) {
@@ -342,6 +369,15 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
                /* EBB events must specify the PMC */
                return -1;
+        if (event & EVENT_WANTS_BHRB) {
+                if (!ebb)
+                        /* Only EBB events can request BHRB */
+                        return -1;
+                mask  |= CNST_IFM_MASK;
+                value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
+        }
        /*
         * All events must agree on EBB, either all request it or none.
         * EBB events are pinned & exclusive, so this should never actually
@@ -431,6 +467,11 @@ static int power8_compute_mmcr(u64 event[], int n_ev,
                        mmcra |= val << MMCRA_THR_CMP_SHIFT;
                }
+                if (event[i] & EVENT_WANTS_BHRB) {
+                        val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
+                        mmcra |= val << MMCRA_IFM_SHIFT;
+                }
                hwc[i] = pmc - 1;
        }
@@ -774,6 +815,9 @@ static int __init init_power8_pmu(void)
        /* Tell userspace that EBB is supported */
        cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
+        if (cpu_has_feature(CPU_FTR_PMAO_BUG))
+                pr_info("PMAO restore workaround active.\n");
        return 0;
 }
 early_initcall(init_power8_pmu);
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index d6c7506ec7d9..dc1a264ec6e6 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -265,7 +265,6 @@ config 440EP
        select PPC_FPU
        select IBM440EP_ERR42
        select IBM_EMAC_ZMII
-        select USB_ARCH_HAS_OHCI
 config 440EPX
        bool
diff --git a/arch/powerpc/platforms/85xx/c293pcie.c b/arch/powerpc/platforms/85xx/c293pcie.c
index 213d5b815827..84476b646005 100644
--- a/arch/powerpc/platforms/85xx/c293pcie.c
+++ b/arch/powerpc/platforms/85xx/c293pcie.c
@@ -68,6 +68,7 @@ define_machine(c293_pcie) {
        .init_IRQ               = c293_pcie_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 3b085c7ee539..b564b5e23f7c 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -107,6 +107,12 @@ void __init mpc85xx_qe_init(void)
        qe_reset();
        of_node_put(np);
+}
+void __init mpc85xx_qe_par_io_init(void)
+{
+        struct device_node *np;
        np = of_find_node_by_name(NULL, "par_io");
        if (np) {
                struct device_node *ucc;
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index fbd871e69754..8e4b1e1a4911 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -26,11 +26,13 @@
 #include <asm/udbg.h>
 #include <asm/mpic.h>
 #include <asm/ehv_pic.h>
+#include <asm/qe_ic.h>
 #include <linux/of_platform.h>
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
 #include "smp.h"
+#include "mpc85xx.h"
 void __init corenet_gen_pic_init(void)
 {
@@ -38,6 +40,8 @@ void __init corenet_gen_pic_init(void)
        unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
                MPIC_NO_RESET;
+        struct device_node *np;
        if (ppc_md.get_irq == mpic_get_coreint_irq)
                flags |= MPIC_ENABLE_COREINT;
@@ -45,6 +49,13 @@ void __init corenet_gen_pic_init(void)
        BUG_ON(mpic == NULL);
        mpic_init(mpic);
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+        if (np) {
+                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+                                qe_ic_cascade_high_mpic);
+                of_node_put(np);
+        }
 }
 /*
@@ -57,6 +68,8 @@ void __init corenet_gen_setup_arch(void)
        swiotlb_detect_4g();
        pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
+        mpc85xx_qe_init();
 }
 static const struct of_device_id of_device_ids[] = {
@@ -81,6 +94,9 @@ static const struct of_device_id of_device_ids[] = {
        {
                .compatible     = "fsl,qoriq-pcie-v3.0",
        },
+        {
+                .compatible     = "fsl,qe",
+        },
        /* The following two are for the Freescale hypervisor */
        {
                .name           = "hypervisor",
@@ -163,6 +179,7 @@ define_machine(corenet_generic) {
        .init_IRQ               = corenet_gen_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_coreint_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c b/arch/powerpc/platforms/85xx/ge_imp3a.c
index e6285ae6f423..11790e074c8a 100644
--- a/arch/powerpc/platforms/85xx/ge_imp3a.c
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -215,6 +215,7 @@ define_machine(ge_imp3a) {
        .show_cpuinfo           = ge_imp3a_show_cpuinfo,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 15ce4b55f117..a378ba3519e9 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -76,6 +76,7 @@ define_machine(mpc8536_ds) {
        .init_IRQ               = mpc8536_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
index fc51dd4092e5..39056f6befeb 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -10,8 +10,10 @@ static inline void __init mpc85xx_cpm2_pic_init(void) {}
 #ifdef CONFIG_QUICC_ENGINE
 extern void mpc85xx_qe_init(void);
+extern void mpc85xx_qe_par_io_init(void);
 #else
 static inline void __init mpc85xx_qe_init(void) {}
+static inline void __init mpc85xx_qe_par_io_init(void) {}
 #endif
 #endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 7a31a0e1df29..b0753e222086 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -385,6 +385,7 @@ define_machine(mpc85xx_cds) {
 #ifdef CONFIG_PCI
        .restart        = mpc85xx_cds_restart,
        .pcibios_fixup_bus      = mpc85xx_cds_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #else
        .restart        = fsl_rstcr_restart,
 #endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 9ebb91ed96a3..ffdf02121a7c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -209,6 +209,7 @@ define_machine(mpc8544_ds) {
        .init_IRQ               = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -223,6 +224,7 @@ define_machine(mpc8572_ds) {
        .init_IRQ               = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -237,6 +239,7 @@ define_machine(p2020_ds) {
        .init_IRQ               = mpc85xx_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 34f3c5eb3bee..a392e94a07fa 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -239,6 +239,7 @@ static void __init mpc85xx_mds_qe_init(void)
        struct device_node *np;
        mpc85xx_qe_init();
+        mpc85xx_qe_par_io_init();
        mpc85xx_mds_reset_ucc_phys();
        if (machine_is(p1021_mds)) {
@@ -391,6 +392,7 @@ define_machine(mpc8568_mds) {
        .progress       = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
@@ -412,6 +414,7 @@ define_machine(mpc8569_mds) {
        .progress       = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
@@ -434,6 +437,7 @@ define_machine(p1021_mds) {
        .progress       = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index e15bdd18fdb2..e358bed66d01 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -86,10 +86,6 @@ void __init mpc85xx_rdb_pic_init(void)
 */
 static void __init mpc85xx_rdb_setup_arch(void)
 {
-#ifdef CONFIG_QUICC_ENGINE
-        struct device_node *np;
-#endif
        if (ppc_md.progress)
                ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
@@ -99,8 +95,10 @@ static void __init mpc85xx_rdb_setup_arch(void)
 #ifdef CONFIG_QUICC_ENGINE
        mpc85xx_qe_init();
+        mpc85xx_qe_par_io_init();
 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
        if (machine_is(p1025_rdb)) {
+                struct device_node *np;
                struct ccsr_guts __iomem *guts;
@@ -233,6 +231,7 @@ define_machine(p2020_rdb) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -247,6 +246,7 @@ define_machine(p1020_rdb) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -261,6 +261,7 @@ define_machine(p1021_rdb_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -275,6 +276,7 @@ define_machine(p2020_rdb_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -289,6 +291,7 @@ define_machine(p1025_rdb) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -303,6 +306,7 @@ define_machine(p1020_mbg_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -317,6 +321,7 @@ define_machine(p1020_utm_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -331,6 +336,7 @@ define_machine(p1020_rdb_pc) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -345,6 +351,7 @@ define_machine(p1020_rdb_pd) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -359,6 +366,7 @@ define_machine(p1024_rdb) {
        .init_IRQ               = mpc85xx_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index d6a3dd311494..ad1a3d438a9e 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -78,6 +78,7 @@ define_machine(p1010_rdb) {
        .init_IRQ               = p1010_rdb_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index e611e79f23ce..6ac986d3f8a3 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -567,6 +567,7 @@ define_machine(p1022_ds) {
        .init_IRQ               = p1022_ds_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
index 8c9297112b30..7a180f0308d5 100644
--- a/arch/powerpc/platforms/85xx/p1022_rdk.c
+++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
@@ -147,6 +147,7 @@ define_machine(p1022_rdk) {
        .init_IRQ               = p1022_rdk_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c
index 2ae9d490c3d9..0e614007acfb 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rds.c
@@ -126,6 +126,7 @@ define_machine(p1023_rds) {
        .progress               = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
@@ -140,5 +141,6 @@ define_machine(p1023_rdb) {
        .progress               = udbg_progress,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
 };
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
index 5cefc5a9a144..7f2673293549 100644
--- a/arch/powerpc/platforms/85xx/qemu_e500.c
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -66,6 +66,7 @@ define_machine(qemu_e500) {
        .init_IRQ               = qemu_e500_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_coreint_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c
index f62121825914..b07214666d65 100644
--- a/arch/powerpc/platforms/85xx/sbc8548.c
+++ b/arch/powerpc/platforms/85xx/sbc8548.c
@@ -135,6 +135,7 @@ define_machine(sbc8548) {
        .restart        = fsl_rstcr_restart,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .calibrate_decr = generic_calibrate_decr,
        .progress       = udbg_progress,
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index c25ff10f05ee..1eadb6d0dc64 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -77,6 +77,7 @@ static void __init twr_p1025_setup_arch(void)
 #ifdef CONFIG_QUICC_ENGINE
        mpc85xx_qe_init();
+        mpc85xx_qe_par_io_init();
 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
        if (machine_is(twr_p1025)) {
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index dcbf7e42dce7..1a9c1085855f 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -170,6 +170,7 @@ define_machine(xes_mpc8572) {
        .init_IRQ               = xes_mpc85xx_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -184,6 +185,7 @@ define_machine(xes_mpc8548) {
        .init_IRQ               = xes_mpc85xx_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
@@ -198,6 +200,7 @@ define_machine(xes_mpc8540) {
        .init_IRQ               = xes_mpc85xx_pic_init,
 #ifdef CONFIG_PCI
        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 #endif
        .get_irq                = mpic_get_irq,
        .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 434fda39bf8b..d9e2b19b7c8d 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -73,6 +73,7 @@ config PPC_BOOK3S_64
        select SYS_SUPPORTS_HUGETLBFS
        select HAVE_ARCH_TRANSPARENT_HUGEPAGE if PPC_64K_PAGES
        select ARCH_SUPPORTS_NUMA_BALANCING
+        select IRQ_WORK
 config PPC_BOOK3E_64
        bool "Embedded processors"
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c
index 2d42f3bb66d6..8a106b4172e0 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -215,7 +215,7 @@ void iic_request_IPIs(void)
 {
        iic_request_ipi(PPC_MSG_CALL_FUNCTION);
        iic_request_ipi(PPC_MSG_RESCHEDULE);
-        iic_request_ipi(PPC_MSG_CALL_FUNC_SINGLE);
+        iic_request_ipi(PPC_MSG_TICK_BROADCAST);
        iic_request_ipi(PPC_MSG_DEBUGGER_BREAK);
 }
diff --git a/arch/powerpc/platforms/cell/spu_syscalls.c b/arch/powerpc/platforms/cell/spu_syscalls.c
index 3844f1397fc3..38e0a1a5cec3 100644
--- a/arch/powerpc/platforms/cell/spu_syscalls.c
+++ b/arch/powerpc/platforms/cell/spu_syscalls.c
@@ -170,7 +170,7 @@ EXPORT_SYMBOL_GPL(register_spu_syscalls);
 void unregister_spu_syscalls(struct spufs_calls *calls)
 {
        BUG_ON(spufs_calls->owner != calls->owner);
-        rcu_assign_pointer(spufs_calls, NULL);
+        RCU_INIT_POINTER(spufs_calls, NULL);
        synchronize_rcu();
 }
 EXPORT_SYMBOL_GPL(unregister_spu_syscalls);
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 6d3c7a9fd047..2a7024d8d8b1 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -34,7 +34,6 @@ config MPC7448HPC2
        select TSI108_BRIDGE
        select DEFAULT_UIMAGE
        select PPC_UDBG_16550
-        select TSI108_BRIDGE
        help
          Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga)
          platform
@@ -44,19 +43,10 @@ config PPC_HOLLY
        depends on EMBEDDED6xx
        select TSI108_BRIDGE
        select PPC_UDBG_16550
-        select TSI108_BRIDGE
        help
          Select PPC_HOLLY if configuring for an IBM 750GX/CL Eval
          Board with TSI108/9 bridge (Hickory/Holly)
-config PPC_PRPMC2800
-        bool "Motorola-PrPMC2800"
-        depends on EMBEDDED6xx
-        select MV64X60
-        select NOT_COHERENT_CACHE
-        help
-          This option enables support for the Motorola PrPMC2800 board
 config PPC_C2K
        bool "SBS/GEFanuc C2K board"
        depends on EMBEDDED6xx
diff --git a/arch/powerpc/platforms/embedded6xx/Makefile b/arch/powerpc/platforms/embedded6xx/Makefile
index cdd48d402b93..f126a2a09981 100644
--- a/arch/powerpc/platforms/embedded6xx/Makefile
+++ b/arch/powerpc/platforms/embedded6xx/Makefile
@@ -5,7 +5,6 @@ obj-$(CONFIG_MPC7448HPC2)	+= mpc7448_hpc2.o
 obj-$(CONFIG_LINKSTATION)       += linkstation.o ls_uart.o
 obj-$(CONFIG_STORCENTER)        += storcenter.o
 obj-$(CONFIG_PPC_HOLLY)         += holly.o
-obj-$(CONFIG_PPC_PRPMC2800)     += prpmc2800.o
 obj-$(CONFIG_PPC_C2K)           += c2k.o
 obj-$(CONFIG_USBGECKO_UDBG)     += usbgecko_udbg.o
 obj-$(CONFIG_GAMECUBE_COMMON)   += flipper-pic.o
diff --git a/arch/powerpc/platforms/embedded6xx/prpmc2800.c b/arch/powerpc/platforms/embedded6xx/prpmc2800.c
deleted file mode 100644
index d455f08bea53..000000000000
--- a/arch/powerpc/platforms/embedded6xx/prpmc2800.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Board setup routines for the Motorola PrPMC2800
- *
- * Author: Dale Farnsworth <dale@farnsworth.org>
- *
- * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/seq_file.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <mm/mmu_decl.h>
-#include <sysdev/mv64x60.h>
-#define MV64x60_MPP_CNTL_0      0x0000
-#define MV64x60_MPP_CNTL_2      0x0008
-#define MV64x60_GPP_IO_CNTL     0x0000
-#define MV64x60_GPP_LEVEL_CNTL  0x0010
-#define MV64x60_GPP_VALUE_SET   0x0018
-#define PLATFORM_NAME_MAX       32
-static char prpmc2800_platform_name[PLATFORM_NAME_MAX];
-static void __iomem *mv64x60_mpp_reg_base;
-static void __iomem *mv64x60_gpp_reg_base;
-static void __init prpmc2800_setup_arch(void)
-{
-        struct device_node *np;
-        phys_addr_t paddr;
-        const unsigned int *reg;
-        /*
-         * ioremap mpp and gpp registers in case they are later
-         * needed by prpmc2800_reset_board().
-         */
-        np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-mpp");
-        reg = of_get_property(np, "reg", NULL);
-        paddr = of_translate_address(np, reg);
-        of_node_put(np);
-        mv64x60_mpp_reg_base = ioremap(paddr, reg[1]);
-        np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
-        reg = of_get_property(np, "reg", NULL);
-        paddr = of_translate_address(np, reg);
-        of_node_put(np);
-        mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
-#ifdef CONFIG_PCI
-        mv64x60_pci_init();
-#endif
-        printk("Motorola %s\n", prpmc2800_platform_name);
-}
-static void prpmc2800_reset_board(void)
-{
-        u32 temp;
-        local_irq_disable();
-        temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0);
-        temp &= 0xFFFF0FFF;
-        out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0, temp);
-        temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
-        temp |= 0x00000004;
-        out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp);
-        temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
-        temp |= 0x00000004;
-        out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp);
-        temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2);
-        temp &= 0xFFFF0FFF;
-        out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2, temp);
-        temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
-        temp |= 0x00080000;
-        out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp);
-        temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
-        temp |= 0x00080000;
-        out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp);
-        out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_VALUE_SET, 0x00080004);
-}
-static void prpmc2800_restart(char *cmd)
-{
-        volatile ulong i = 10000000;
-        prpmc2800_reset_board();
-        while (i-- > 0);
-        panic("restart failed\n");
-}
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define PPRPM2800_COHERENCY_SETTING "off"
-#else
-#define PPRPM2800_COHERENCY_SETTING "on"
-#endif
-void prpmc2800_show_cpuinfo(struct seq_file *m)
-{
-        seq_printf(m, "Vendor\t\t: Motorola\n");
-        seq_printf(m, "coherency\t: %s\n", PPRPM2800_COHERENCY_SETTING);
-}
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init prpmc2800_probe(void)
-{
-        unsigned long root = of_get_flat_dt_root();
-        unsigned long len = PLATFORM_NAME_MAX;
-        void *m;
-        if (!of_flat_dt_is_compatible(root, "motorola,PrPMC2800"))
-                return 0;
-        /* Update ppc_md.name with name from dt */
-        m = of_get_flat_dt_prop(root, "model", &len);
-        if (m)
-                strncpy(prpmc2800_platform_name, m,
-                        min((int)len, PLATFORM_NAME_MAX - 1));
-        _set_L2CR(_get_L2CR() | L2CR_L2E);
-        return 1;
-}
-define_machine(prpmc2800){
-        .name                   = prpmc2800_platform_name,
-        .probe                  = prpmc2800_probe,
-        .setup_arch             = prpmc2800_setup_arch,
-        .init_early             = mv64x60_init_early,
-        .show_cpuinfo           = prpmc2800_show_cpuinfo,
-        .init_IRQ               = mv64x60_init_irq,
-        .get_irq                = mv64x60_get_irq,
-        .restart                = prpmc2800_restart,
-        .calibrate_decr         = generic_calibrate_decr,
-};
diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig
index 895e8a20a3fc..c252ee95bddf 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
@@ -11,6 +11,12 @@ config PPC_POWERNV
        select PPC_UDBG_16550
        select PPC_SCOM
        select ARCH_RANDOM
+        select CPU_FREQ
+        select CPU_FREQ_GOV_PERFORMANCE
+        select CPU_FREQ_GOV_POWERSAVE
+        select CPU_FREQ_GOV_USERSPACE
+        select CPU_FREQ_GOV_ONDEMAND
+        select CPU_FREQ_GOV_CONSERVATIVE
        default y
 config PPC_POWERNV_RTAS
diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
index 8d767fde5a6a..63cebb9b4d45 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -1,6 +1,7 @@
-obj-y                   += setup.o opal-takeover.o opal-wrappers.o opal.o
+obj-y                   += setup.o opal-takeover.o opal-wrappers.o opal.o opal-async.o
 obj-y                   += opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o
-obj-y                   += rng.o
+obj-y                   += rng.o opal-elog.o opal-dump.o opal-sysparam.o opal-sensor.o
+obj-y                   += opal-msglog.o
 obj-$(CONFIG_SMP)       += smp.o
 obj-$(CONFIG_PCI)       += pci.o pci-p5ioc2.o pci-ioda.o
diff --git a/arch/powerpc/platforms/powernv/opal-async.c b/arch/powerpc/platforms/powernv/opal-async.c
new file mode 100644
index 000000000000..32e2adfa5320
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-async.c
@@ -0,0 +1,204 @@
+/*
+ * PowerNV OPAL asynchronous completion interfaces
+ *
+ * Copyright 2013 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#undef DEBUG
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/semaphore.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+#include <linux/gfp.h>
+#include <linux/of.h>
+#include <asm/opal.h>
+#define N_ASYNC_COMPLETIONS     64
+static DECLARE_BITMAP(opal_async_complete_map, N_ASYNC_COMPLETIONS) = {~0UL};
+static DECLARE_BITMAP(opal_async_token_map, N_ASYNC_COMPLETIONS);
+static DECLARE_WAIT_QUEUE_HEAD(opal_async_wait);
+static DEFINE_SPINLOCK(opal_async_comp_lock);
+static struct semaphore opal_async_sem;
+static struct opal_msg *opal_async_responses;
+static unsigned int opal_max_async_tokens;
+int __opal_async_get_token(void)
+{
+        unsigned long flags;
+        int token;
+        spin_lock_irqsave(&opal_async_comp_lock, flags);
+        token = find_first_bit(opal_async_complete_map, opal_max_async_tokens);
+        if (token >= opal_max_async_tokens) {
+                token = -EBUSY;
+                goto out;
+        }
+        if (__test_and_set_bit(token, opal_async_token_map)) {
+                token = -EBUSY;
+                goto out;
+        }
+        __clear_bit(token, opal_async_complete_map);
+out:
+        spin_unlock_irqrestore(&opal_async_comp_lock, flags);
+        return token;
+}
+int opal_async_get_token_interruptible(void)
+{
+        int token;
+        /* Wait until a token is available */
+        if (down_interruptible(&opal_async_sem))
+                return -ERESTARTSYS;
+        token = __opal_async_get_token();
+        if (token < 0)
+                up(&opal_async_sem);
+        return token;
+}
+int __opal_async_release_token(int token)
+{
+        unsigned long flags;
+        if (token < 0 || token >= opal_max_async_tokens) {
+                pr_err("%s: Passed token is out of range, token %d\n",
+                                __func__, token);
+                return -EINVAL;
+        }
+        spin_lock_irqsave(&opal_async_comp_lock, flags);
+        __set_bit(token, opal_async_complete_map);
+        __clear_bit(token, opal_async_token_map);
+        spin_unlock_irqrestore(&opal_async_comp_lock, flags);
+        return 0;
+}
+int opal_async_release_token(int token)
+{
+        int ret;
+        ret = __opal_async_release_token(token);
+        if (ret)
+                return ret;
+        up(&opal_async_sem);
+        return 0;
+}
+int opal_async_wait_response(uint64_t token, struct opal_msg *msg)
+{
+        if (token >= opal_max_async_tokens) {
+                pr_err("%s: Invalid token passed\n", __func__);
+                return -EINVAL;
+        }
+        if (!msg) {
+                pr_err("%s: Invalid message pointer passed\n", __func__);
+                return -EINVAL;
+        }
+        wait_event(opal_async_wait, test_bit(token, opal_async_complete_map));
+        memcpy(msg, &opal_async_responses[token], sizeof(*msg));
+        return 0;
+}
+static int opal_async_comp_event(struct notifier_block *nb,
+                unsigned long msg_type, void *msg)
+{
+        struct opal_msg *comp_msg = msg;
+        unsigned long flags;
+        uint64_t token;
+        if (msg_type != OPAL_MSG_ASYNC_COMP)
+                return 0;
+        token = be64_to_cpu(comp_msg->params[0]);
+        memcpy(&opal_async_responses[token], comp_msg, sizeof(*comp_msg));
+        spin_lock_irqsave(&opal_async_comp_lock, flags);
+        __set_bit(token, opal_async_complete_map);
+        spin_unlock_irqrestore(&opal_async_comp_lock, flags);
+        wake_up(&opal_async_wait);
+        return 0;
+}
+static struct notifier_block opal_async_comp_nb = {
+                .notifier_call  = opal_async_comp_event,
+                .next           = NULL,
+                .priority       = 0,
+};
+static int __init opal_async_comp_init(void)
+{
+        struct device_node *opal_node;
+        const __be32 *async;
+        int err;
+        opal_node = of_find_node_by_path("/ibm,opal");
+        if (!opal_node) {
+                pr_err("%s: Opal node not found\n", __func__);
+                err = -ENOENT;
+                goto out;
+        }
+        async = of_get_property(opal_node, "opal-msg-async-num", NULL);
+        if (!async) {
+                pr_err("%s: %s has no opal-msg-async-num\n",
+                                __func__, opal_node->full_name);
+                err = -ENOENT;
+                goto out_opal_node;
+        }
+        opal_max_async_tokens = be32_to_cpup(async);
+        if (opal_max_async_tokens > N_ASYNC_COMPLETIONS)
+                opal_max_async_tokens = N_ASYNC_COMPLETIONS;
+        err = opal_message_notifier_register(OPAL_MSG_ASYNC_COMP,
+                        &opal_async_comp_nb);
+        if (err) {
+                pr_err("%s: Can't register OPAL event notifier (%d)\n",
+                                __func__, err);
+                goto out_opal_node;
+        }
+        opal_async_responses = kzalloc(
+                        sizeof(*opal_async_responses) * opal_max_async_tokens,
+                        GFP_KERNEL);
+        if (!opal_async_responses) {
+                pr_err("%s: Out of memory, failed to do asynchronous "
+                                "completion init\n", __func__);
+                err = -ENOMEM;
+                goto out_opal_node;
+        }
+        /* Initialize to 1 less than the maximum tokens available, as we may
+         * require to pop one during emergency through synchronous call to
+         * __opal_async_get_token()
+         */
+        sema_init(&opal_async_sem, opal_max_async_tokens - 1);
+out_opal_node:
+        of_node_put(opal_node);
+out:
+        return err;
+}
+subsys_initcall(opal_async_comp_init);
diff --git a/arch/powerpc/platforms/powernv/opal-dump.c b/arch/powerpc/platforms/powernv/opal-dump.c
new file mode 100644
index 000000000000..b9827b0d87e4
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-dump.c
@@ -0,0 +1,520 @@
+/*
+ * PowerNV OPAL Dump Interface
+ *
+ * Copyright 2013,2014 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kobject.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/pagemap.h>
+#include <linux/delay.h>
+#include <asm/opal.h>
+#define DUMP_TYPE_FSP   0x01
+struct dump_obj {
+        struct kobject  kobj;
+        struct bin_attribute dump_attr;
+        uint32_t        id;  /* becomes object name */
+        uint32_t        type;
+        uint32_t        size;
+        char            *buffer;
+};
+#define to_dump_obj(x) container_of(x, struct dump_obj, kobj)
+struct dump_attribute {
+        struct attribute attr;
+        ssize_t (*show)(struct dump_obj *dump, struct dump_attribute *attr,
+                        char *buf);
+        ssize_t (*store)(struct dump_obj *dump, struct dump_attribute *attr,
+                         const char *buf, size_t count);
+};
+#define to_dump_attr(x) container_of(x, struct dump_attribute, attr)
+static ssize_t dump_id_show(struct dump_obj *dump_obj,
+                            struct dump_attribute *attr,
+                            char *buf)
+{
+        return sprintf(buf, "0x%x\n", dump_obj->id);
+}
+static const char* dump_type_to_string(uint32_t type)
+{
+        switch (type) {
+        case 0x01: return "SP Dump";
+        case 0x02: return "System/Platform Dump";
+        case 0x03: return "SMA Dump";
+        default: return "unknown";
+        }
+}
+static ssize_t dump_type_show(struct dump_obj *dump_obj,
+                              struct dump_attribute *attr,
+                              char *buf)
+{
+        
+        return sprintf(buf, "0x%x %s\n", dump_obj->type,
+                       dump_type_to_string(dump_obj->type));
+}
+static ssize_t dump_ack_show(struct dump_obj *dump_obj,
+                             struct dump_attribute *attr,
+                             char *buf)
+{
+        return sprintf(buf, "ack - acknowledge dump\n");
+}
+/*
+ * Send acknowledgement to OPAL
+ */
+static int64_t dump_send_ack(uint32_t dump_id)
+{
+        int rc;
+        rc = opal_dump_ack(dump_id);
+        if (rc)
+                pr_warn("%s: Failed to send ack to Dump ID 0x%x (%d)\n",
+                        __func__, dump_id, rc);
+        return rc;
+}
+static ssize_t dump_ack_store(struct dump_obj *dump_obj,
+                              struct dump_attribute *attr,
+                              const char *buf,
+                              size_t count)
+{
+        dump_send_ack(dump_obj->id);
+        sysfs_remove_file_self(&dump_obj->kobj, &attr->attr);
+        kobject_put(&dump_obj->kobj);
+        return count;
+}
+/* Attributes of a dump
+ * The binary attribute of the dump itself is dynamic
+ * due to the dynamic size of the dump
+ */
+static struct dump_attribute id_attribute =
+        __ATTR(id, 0666, dump_id_show, NULL);
+static struct dump_attribute type_attribute =
+        __ATTR(type, 0666, dump_type_show, NULL);
+static struct dump_attribute ack_attribute =
+        __ATTR(acknowledge, 0660, dump_ack_show, dump_ack_store);
+static ssize_t init_dump_show(struct dump_obj *dump_obj,
+                              struct dump_attribute *attr,
+                              char *buf)
+{
+        return sprintf(buf, "1 - initiate dump\n");
+}
+static int64_t dump_fips_init(uint8_t type)
+{
+        int rc;
+        rc = opal_dump_init(type);
+        if (rc)
+                pr_warn("%s: Failed to initiate FipS dump (%d)\n",
+                        __func__, rc);
+        return rc;
+}
+static ssize_t init_dump_store(struct dump_obj *dump_obj,
+                               struct dump_attribute *attr,
+                               const char *buf,
+                               size_t count)
+{
+        dump_fips_init(DUMP_TYPE_FSP);
+        pr_info("%s: Initiated FSP dump\n", __func__);
+        return count;
+}
+static struct dump_attribute initiate_attribute =
+        __ATTR(initiate_dump, 0600, init_dump_show, init_dump_store);
+static struct attribute *initiate_attrs[] = {
+        &initiate_attribute.attr,
+        NULL,
+};
+static struct attribute_group initiate_attr_group = {
+        .attrs = initiate_attrs,
+};
+static struct kset *dump_kset;
+static ssize_t dump_attr_show(struct kobject *kobj,
+                              struct attribute *attr,
+                              char *buf)
+{
+        struct dump_attribute *attribute;
+        struct dump_obj *dump;
+        attribute = to_dump_attr(attr);
+        dump = to_dump_obj(kobj);
+        if (!attribute->show)
+                return -EIO;
+        return attribute->show(dump, attribute, buf);
+}
+static ssize_t dump_attr_store(struct kobject *kobj,
+                               struct attribute *attr,
+                               const char *buf, size_t len)
+{
+        struct dump_attribute *attribute;
+        struct dump_obj *dump;
+        attribute = to_dump_attr(attr);
+        dump = to_dump_obj(kobj);
+        if (!attribute->store)
+                return -EIO;
+        return attribute->store(dump, attribute, buf, len);
+}
+static const struct sysfs_ops dump_sysfs_ops = {
+        .show = dump_attr_show,
+        .store = dump_attr_store,
+};
+static void dump_release(struct kobject *kobj)
+{
+        struct dump_obj *dump;
+        dump = to_dump_obj(kobj);
+        vfree(dump->buffer);
+        kfree(dump);
+}
+static struct attribute *dump_default_attrs[] = {
+        &id_attribute.attr,
+        &type_attribute.attr,
+        &ack_attribute.attr,
+        NULL,
+};
+static struct kobj_type dump_ktype = {
+        .sysfs_ops = &dump_sysfs_ops,
+        .release = &dump_release,
+        .default_attrs = dump_default_attrs,
+};
+static void free_dump_sg_list(struct opal_sg_list *list)
+{
+        struct opal_sg_list *sg1;
+        while (list) {
+                sg1 = list->next;
+                kfree(list);
+                list = sg1;
+        }
+        list = NULL;
+}
+static struct opal_sg_list *dump_data_to_sglist(struct dump_obj *dump)
+{
+        struct opal_sg_list *sg1, *list = NULL;
+        void *addr;
+        int64_t size;
+        addr = dump->buffer;
+        size = dump->size;
+        sg1 = kzalloc(PAGE_SIZE, GFP_KERNEL);
+        if (!sg1)
+                goto nomem;
+        list = sg1;
+        sg1->num_entries = 0;
+        while (size > 0) {
+                /* Translate virtual address to physical address */
+                sg1->entry[sg1->num_entries].data =
+                        (void *)(vmalloc_to_pfn(addr) << PAGE_SHIFT);
+                if (size > PAGE_SIZE)
+                        sg1->entry[sg1->num_entries].length = PAGE_SIZE;
+                else
+                        sg1->entry[sg1->num_entries].length = size;
+                sg1->num_entries++;
+                if (sg1->num_entries >= SG_ENTRIES_PER_NODE) {
+                        sg1->next = kzalloc(PAGE_SIZE, GFP_KERNEL);
+                        if (!sg1->next)
+                                goto nomem;
+                        sg1 = sg1->next;
+                        sg1->num_entries = 0;
+                }
+                addr += PAGE_SIZE;
+                size -= PAGE_SIZE;
+        }
+        return list;
+nomem:
+        pr_err("%s : Failed to allocate memory\n", __func__);
+        free_dump_sg_list(list);
+        return NULL;
+}
+static void sglist_to_phy_addr(struct opal_sg_list *list)
+{
+        struct opal_sg_list *sg, *next;
+        for (sg = list; sg; sg = next) {
+                next = sg->next;
+                /* Don't translate NULL pointer for last entry */
+                if (sg->next)
+                        sg->next = (struct opal_sg_list *)__pa(sg->next);
+                else
+                        sg->next = NULL;
+                /* Convert num_entries to length */
+                sg->num_entries =
+                        sg->num_entries * sizeof(struct opal_sg_entry) + 16;
+        }
+}
+static int64_t dump_read_info(uint32_t *id, uint32_t *size, uint32_t *type)
+{
+        int rc;
+        *type = 0xffffffff;
+        rc = opal_dump_info2(id, size, type);
+        if (rc == OPAL_PARAMETER)
+                rc = opal_dump_info(id, size);
+        if (rc)
+                pr_warn("%s: Failed to get dump info (%d)\n",
+                        __func__, rc);
+        return rc;
+}
+static int64_t dump_read_data(struct dump_obj *dump)
+{
+        struct opal_sg_list *list;
+        uint64_t addr;
+        int64_t rc;
+        /* Allocate memory */
+        dump->buffer = vzalloc(PAGE_ALIGN(dump->size));
+        if (!dump->buffer) {
+                pr_err("%s : Failed to allocate memory\n", __func__);
+                rc = -ENOMEM;
+                goto out;
+        }
+        /* Generate SG list */
+        list = dump_data_to_sglist(dump);
+        if (!list) {
+                rc = -ENOMEM;
+                goto out;
+        }
+        /* Translate sg list addr to real address */
+        sglist_to_phy_addr(list);
+        /* First entry address */
+        addr = __pa(list);
+        /* Fetch data */
+        rc = OPAL_BUSY_EVENT;
+        while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
+                rc = opal_dump_read(dump->id, addr);
+                if (rc == OPAL_BUSY_EVENT) {
+                        opal_poll_events(NULL);
+                        msleep(20);
+                }
+        }
+        if (rc != OPAL_SUCCESS && rc != OPAL_PARTIAL)
+                pr_warn("%s: Extract dump failed for ID 0x%x\n",
+                        __func__, dump->id);
+        /* Free SG list */
+        free_dump_sg_list(list);
+out:
+        return rc;
+}
+static ssize_t dump_attr_read(struct file *filep, struct kobject *kobj,
+                              struct bin_attribute *bin_attr,
+                              char *buffer, loff_t pos, size_t count)
+{
+        ssize_t rc;
+        struct dump_obj *dump = to_dump_obj(kobj);
+        if (!dump->buffer) {
+                rc = dump_read_data(dump);
+                if (rc != OPAL_SUCCESS && rc != OPAL_PARTIAL) {
+                        vfree(dump->buffer);
+                        dump->buffer = NULL;
+                        return -EIO;
+                }
+                if (rc == OPAL_PARTIAL) {
+                        /* On a partial read, we just return EIO
+                         * and rely on userspace to ask us to try
+                         * again.
+                         */
+                        pr_info("%s: Platform dump partially read.ID = 0x%x\n",
+                                __func__, dump->id);
+                        return -EIO;
+                }
+        }
+        memcpy(buffer, dump->buffer + pos, count);
+        /* You may think we could free the dump buffer now and retrieve
+         * it again later if needed, but due to current firmware limitation,
+         * that's not the case. So, once read into userspace once,
+         * we keep the dump around until it's acknowledged by userspace.
+         */
+        return count;
+}
+static struct dump_obj *create_dump_obj(uint32_t id, size_t size,
+                                        uint32_t type)
+{
+        struct dump_obj *dump;
+        int rc;
+        dump = kzalloc(sizeof(*dump), GFP_KERNEL);
+        if (!dump)
+                return NULL;
+        dump->kobj.kset = dump_kset;
+        kobject_init(&dump->kobj, &dump_ktype);
+        sysfs_bin_attr_init(&dump->dump_attr);
+        dump->dump_attr.attr.name = "dump";
+        dump->dump_attr.attr.mode = 0400;
+        dump->dump_attr.size = size;
+        dump->dump_attr.read = dump_attr_read;
+        dump->id = id;
+        dump->size = size;
+        dump->type = type;
+        rc = kobject_add(&dump->kobj, NULL, "0x%x-0x%x", type, id);
+        if (rc) {
+                kobject_put(&dump->kobj);
+                return NULL;
+        }
+        rc = sysfs_create_bin_file(&dump->kobj, &dump->dump_attr);
+        if (rc) {
+                kobject_put(&dump->kobj);
+                return NULL;
+        }
+        pr_info("%s: New platform dump. ID = 0x%x Size %u\n",
+                __func__, dump->id, dump->size);
+        kobject_uevent(&dump->kobj, KOBJ_ADD);
+        return dump;
+}
+static int process_dump(void)
+{
+        int rc;
+        uint32_t dump_id, dump_size, dump_type;
+        struct dump_obj *dump;
+        char name[22];
+        rc = dump_read_info(&dump_id, &dump_size, &dump_type);
+        if (rc != OPAL_SUCCESS)
+                return rc;
+        sprintf(name, "0x%x-0x%x", dump_type, dump_id);
+        /* we may get notified twice, let's handle
+         * that gracefully and not create two conflicting
+         * entries.
+         */
+        if (kset_find_obj(dump_kset, name))
+                return 0;
+        dump = create_dump_obj(dump_id, dump_size, dump_type);
+        if (!dump)
+                return -1;
+        return 0;
+}
+static void dump_work_fn(struct work_struct *work)
+{
+        process_dump();
+}
+static DECLARE_WORK(dump_work, dump_work_fn);
+static void schedule_process_dump(void)
+{
+        schedule_work(&dump_work);
+}
+/*
+ * New dump available notification
+ *
+ * Once we get notification, we add sysfs entries for it.
+ * We only fetch the dump on demand, and create sysfs asynchronously.
+ */
+static int dump_event(struct notifier_block *nb,
+                      unsigned long events, void *change)
+{
+        if (events & OPAL_EVENT_DUMP_AVAIL)
+                schedule_process_dump();
+        return 0;
+}
+static struct notifier_block dump_nb = {
+        .notifier_call  = dump_event,
+        .next           = NULL,
+        .priority       = 0
+};
+void __init opal_platform_dump_init(void)
+{
+        int rc;
+        dump_kset = kset_create_and_add("dump", NULL, opal_kobj);
+        if (!dump_kset) {
+                pr_warn("%s: Failed to create dump kset\n", __func__);
+                return;
+        }
+        rc = sysfs_create_group(&dump_kset->kobj, &initiate_attr_group);
+        if (rc) {
+                pr_warn("%s: Failed to create initiate dump attr group\n",
+                        __func__);
+                kobject_put(&dump_kset->kobj);
+                return;
+        }
+        rc = opal_notifier_register(&dump_nb);
+        if (rc) {
+                pr_warn("%s: Can't register OPAL event notifier (%d)\n",
+                        __func__, rc);
+                return;
+        }
+        opal_dump_resend_notification();
+}
diff --git a/arch/powerpc/platforms/powernv/opal-elog.c b/arch/powerpc/platforms/powernv/opal-elog.c
new file mode 100644
index 000000000000..ef7bc2a97862
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-elog.c
@@ -0,0 +1,308 @@
+/*
+ * Error log support on PowerNV.
+ *
+ * Copyright 2013,2014 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/sysfs.h>
+#include <linux/fs.h>
+#include <linux/vmalloc.h>
+#include <linux/fcntl.h>
+#include <linux/kobject.h>
+#include <asm/uaccess.h>
+#include <asm/opal.h>
+struct elog_obj {
+        struct kobject kobj;
+        struct bin_attribute raw_attr;
+        uint64_t id;
+        uint64_t type;
+        size_t size;
+        char *buffer;
+};
+#define to_elog_obj(x) container_of(x, struct elog_obj, kobj)
+struct elog_attribute {
+        struct attribute attr;
+        ssize_t (*show)(struct elog_obj *elog, struct elog_attribute *attr,
+                        char *buf);
+        ssize_t (*store)(struct elog_obj *elog, struct elog_attribute *attr,
+                         const char *buf, size_t count);
+};
+#define to_elog_attr(x) container_of(x, struct elog_attribute, attr)
+static ssize_t elog_id_show(struct elog_obj *elog_obj,
+                            struct elog_attribute *attr,
+                            char *buf)
+{
+        return sprintf(buf, "0x%llx\n", elog_obj->id);
+}
+static const char *elog_type_to_string(uint64_t type)
+{
+        switch (type) {
+        case 0: return "PEL";
+        default: return "unknown";
+        }
+}
+static ssize_t elog_type_show(struct elog_obj *elog_obj,
+                              struct elog_attribute *attr,
+                              char *buf)
+{
+        return sprintf(buf, "0x%llx %s\n",
+                       elog_obj->type,
+                       elog_type_to_string(elog_obj->type));
+}
+static ssize_t elog_ack_show(struct elog_obj *elog_obj,
+                             struct elog_attribute *attr,
+                             char *buf)
+{
+        return sprintf(buf, "ack - acknowledge log message\n");
+}
+static ssize_t elog_ack_store(struct elog_obj *elog_obj,
+                              struct elog_attribute *attr,
+                              const char *buf,
+                              size_t count)
+{
+        opal_send_ack_elog(elog_obj->id);
+        sysfs_remove_file_self(&elog_obj->kobj, &attr->attr);
+        kobject_put(&elog_obj->kobj);
+        return count;
+}
+static struct elog_attribute id_attribute =
+        __ATTR(id, 0666, elog_id_show, NULL);
+static struct elog_attribute type_attribute =
+        __ATTR(type, 0666, elog_type_show, NULL);
+static struct elog_attribute ack_attribute =
+        __ATTR(acknowledge, 0660, elog_ack_show, elog_ack_store);
+static struct kset *elog_kset;
+static ssize_t elog_attr_show(struct kobject *kobj,
+                              struct attribute *attr,
+                              char *buf)
+{
+        struct elog_attribute *attribute;
+        struct elog_obj *elog;
+        attribute = to_elog_attr(attr);
+        elog = to_elog_obj(kobj);
+        if (!attribute->show)
+                return -EIO;
+        return attribute->show(elog, attribute, buf);
+}
+static ssize_t elog_attr_store(struct kobject *kobj,
+                               struct attribute *attr,
+                               const char *buf, size_t len)
+{
+        struct elog_attribute *attribute;
+        struct elog_obj *elog;
+        attribute = to_elog_attr(attr);
+        elog = to_elog_obj(kobj);
+        if (!attribute->store)
+                return -EIO;
+        return attribute->store(elog, attribute, buf, len);
+}
+static const struct sysfs_ops elog_sysfs_ops = {
+        .show = elog_attr_show,
+        .store = elog_attr_store,
+};
+static void elog_release(struct kobject *kobj)
+{
+        struct elog_obj *elog;
+        elog = to_elog_obj(kobj);
+        kfree(elog->buffer);
+        kfree(elog);
+}
+static struct attribute *elog_default_attrs[] = {
+        &id_attribute.attr,
+        &type_attribute.attr,
+        &ack_attribute.attr,
+        NULL,
+};
+static struct kobj_type elog_ktype = {
+        .sysfs_ops = &elog_sysfs_ops,
+        .release = &elog_release,
+        .default_attrs = elog_default_attrs,
+};
+/* Maximum size of a single log on FSP is 16KB */
+#define OPAL_MAX_ERRLOG_SIZE    16384
+static ssize_t raw_attr_read(struct file *filep, struct kobject *kobj,
+                             struct bin_attribute *bin_attr,
+                             char *buffer, loff_t pos, size_t count)
+{
+        int opal_rc;
+        struct elog_obj *elog = to_elog_obj(kobj);
+        /* We may have had an error reading before, so let's retry */
+        if (!elog->buffer) {
+                elog->buffer = kzalloc(elog->size, GFP_KERNEL);
+                if (!elog->buffer)
+                        return -EIO;
+                opal_rc = opal_read_elog(__pa(elog->buffer),
+                                         elog->size, elog->id);
+                if (opal_rc != OPAL_SUCCESS) {
+                        pr_err("ELOG: log read failed for log-id=%llx\n",
+                               elog->id);
+                        kfree(elog->buffer);
+                        elog->buffer = NULL;
+                        return -EIO;
+                }
+        }
+        memcpy(buffer, elog->buffer + pos, count);
+        return count;
+}
+static struct elog_obj *create_elog_obj(uint64_t id, size_t size, uint64_t type)
+{
+        struct elog_obj *elog;
+        int rc;
+        elog = kzalloc(sizeof(*elog), GFP_KERNEL);
+        if (!elog)
+                return NULL;
+        elog->kobj.kset = elog_kset;
+        kobject_init(&elog->kobj, &elog_ktype);
+        sysfs_bin_attr_init(&elog->raw_attr);
+        elog->raw_attr.attr.name = "raw";
+        elog->raw_attr.attr.mode = 0400;
+        elog->raw_attr.size = size;
+        elog->raw_attr.read = raw_attr_read;
+        elog->id = id;
+        elog->size = size;
+        elog->type = type;
+        elog->buffer = kzalloc(elog->size, GFP_KERNEL);
+        if (elog->buffer) {
+                rc = opal_read_elog(__pa(elog->buffer),
+                                         elog->size, elog->id);
+                if (rc != OPAL_SUCCESS) {
+                        pr_err("ELOG: log read failed for log-id=%llx\n",
+                               elog->id);
+                        kfree(elog->buffer);
+                        elog->buffer = NULL;
+                }
+        }
+        rc = kobject_add(&elog->kobj, NULL, "0x%llx", id);
+        if (rc) {
+                kobject_put(&elog->kobj);
+                return NULL;
+        }
+        rc = sysfs_create_bin_file(&elog->kobj, &elog->raw_attr);
+        if (rc) {
+                kobject_put(&elog->kobj);
+                return NULL;
+        }
+        kobject_uevent(&elog->kobj, KOBJ_ADD);
+        return elog;
+}
+static void elog_work_fn(struct work_struct *work)
+{
+        size_t elog_size;
+        uint64_t log_id;
+        uint64_t elog_type;
+        int rc;
+        char name[2+16+1];
+        rc = opal_get_elog_size(&log_id, &elog_size, &elog_type);
+        if (rc != OPAL_SUCCESS) {
+                pr_err("ELOG: Opal log read failed\n");
+                return;
+        }
+        BUG_ON(elog_size > OPAL_MAX_ERRLOG_SIZE);
+        if (elog_size >= OPAL_MAX_ERRLOG_SIZE)
+                elog_size  =  OPAL_MAX_ERRLOG_SIZE;
+        sprintf(name, "0x%llx", log_id);
+        /* we may get notified twice, let's handle
+         * that gracefully and not create two conflicting
+         * entries.
+         */
+        if (kset_find_obj(elog_kset, name))
+                return;
+        create_elog_obj(log_id, elog_size, elog_type);
+}
+static DECLARE_WORK(elog_work, elog_work_fn);
+static int elog_event(struct notifier_block *nb,
+                                unsigned long events, void *change)
+{
+        /* check for error log event */
+        if (events & OPAL_EVENT_ERROR_LOG_AVAIL)
+                schedule_work(&elog_work);
+        return 0;
+}
+static struct notifier_block elog_nb = {
+        .notifier_call  = elog_event,
+        .next           = NULL,
+        .priority       = 0
+};
+int __init opal_elog_init(void)
+{
+        int rc = 0;
+        elog_kset = kset_create_and_add("elog", NULL, opal_kobj);
+        if (!elog_kset) {
+                pr_warn("%s: failed to create elog kset\n", __func__);
+                return -1;
+        }
+        rc = opal_notifier_register(&elog_nb);
+        if (rc) {
+                pr_err("%s: Can't register OPAL event notifier (%d)\n",
+                __func__, rc);
+                return rc;
+        }
+        /* We are now ready to pull error logs from opal. */
+        opal_resend_pending_logs();
+        return 0;
+}
diff --git a/arch/powerpc/platforms/powernv/opal-msglog.c b/arch/powerpc/platforms/powernv/opal-msglog.c
new file mode 100644
index 000000000000..1bb25b952504
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-msglog.c
@@ -0,0 +1,120 @@
+/*
+ * PowerNV OPAL in-memory console interface
+ *
+ * Copyright 2014 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <asm/io.h>
+#include <asm/opal.h>
+#include <linux/debugfs.h>
+#include <linux/of.h>
+#include <linux/types.h>
+#include <asm/barrier.h>
+/* OPAL in-memory console. Defined in OPAL source at core/console.c */
+struct memcons {
+        __be64 magic;
+#define MEMCONS_MAGIC   0x6630696567726173L
+        __be64 obuf_phys;
+        __be64 ibuf_phys;
+        __be32 obuf_size;
+        __be32 ibuf_size;
+        __be32 out_pos;
+#define MEMCONS_OUT_POS_WRAP    0x80000000u
+#define MEMCONS_OUT_POS_MASK    0x00ffffffu
+        __be32 in_prod;
+        __be32 in_cons;
+};
+static ssize_t opal_msglog_read(struct file *file, struct kobject *kobj,
+                                struct bin_attribute *bin_attr, char *to,
+                                loff_t pos, size_t count)
+{
+        struct memcons *mc = bin_attr->private;
+        const char *conbuf;
+        size_t ret, first_read = 0;
+        uint32_t out_pos, avail;
+        if (!mc)
+                return -ENODEV;
+        out_pos = be32_to_cpu(ACCESS_ONCE(mc->out_pos));
+        /* Now we've read out_pos, put a barrier in before reading the new
+         * data it points to in conbuf. */
+        smp_rmb();
+        conbuf = phys_to_virt(be64_to_cpu(mc->obuf_phys));
+        /* When the buffer has wrapped, read from the out_pos marker to the end
+         * of the buffer, and then read the remaining data as in the un-wrapped
+         * case. */
+        if (out_pos & MEMCONS_OUT_POS_WRAP) {
+                out_pos &= MEMCONS_OUT_POS_MASK;
+                avail = be32_to_cpu(mc->obuf_size) - out_pos;
+                ret = memory_read_from_buffer(to, count, &pos,
+                                conbuf + out_pos, avail);
+                if (ret < 0)
+                        goto out;
+                first_read = ret;
+                to += first_read;
+                count -= first_read;
+                pos -= avail;
+        }
+        /* Sanity check. The firmware should not do this to us. */
+        if (out_pos > be32_to_cpu(mc->obuf_size)) {
+                pr_err("OPAL: memory console corruption. Aborting read.\n");
+                return -EINVAL;
+        }
+        ret = memory_read_from_buffer(to, count, &pos, conbuf, out_pos);
+        if (ret < 0)
+                goto out;
+        ret += first_read;
+out:
+        return ret;
+}
+static struct bin_attribute opal_msglog_attr = {
+        .attr = {.name = "msglog", .mode = 0444},
+        .read = opal_msglog_read
+};
+void __init opal_msglog_init(void)
+{
+        u64 mcaddr;
+        struct memcons *mc;
+        if (of_property_read_u64(opal_node, "ibm,opal-memcons", &mcaddr)) {
+                pr_warn("OPAL: Property ibm,opal-memcons not found, no message log\n");
+                return;
+        }
+        mc = phys_to_virt(mcaddr);
+        if (!mc) {
+                pr_warn("OPAL: memory console address is invalid\n");
+                return;
+        }
+        if (be64_to_cpu(mc->magic) != MEMCONS_MAGIC) {
+                pr_warn("OPAL: memory console version is invalid\n");
+                return;
+        }
+        opal_msglog_attr.private = mc;
+        if (sysfs_create_bin_file(opal_kobj, &opal_msglog_attr) != 0)
+                pr_warn("OPAL: sysfs file creation failed\n");
+}
diff --git a/arch/powerpc/platforms/powernv/opal-sensor.c b/arch/powerpc/platforms/powernv/opal-sensor.c
new file mode 100644
index 000000000000..10271ad1fac4
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-sensor.c
@@ -0,0 +1,66 @@
+/*
+ * PowerNV sensor code
+ *
+ * Copyright (C) 2013 IBM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/delay.h>
+#include <linux/mutex.h>
+#include <asm/opal.h>
+static DEFINE_MUTEX(opal_sensor_mutex);
+/*
+ * This will return sensor information to driver based on the requested sensor
+ * handle. A handle is an opaque id for the powernv, read by the driver from the
+ * device tree..
+ */
+int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data)
+{
+        int ret, token;
+        struct opal_msg msg;
+        __be32 data;
+        token = opal_async_get_token_interruptible();
+        if (token < 0) {
+                pr_err("%s: Couldn't get the token, returning\n", __func__);
+                ret = token;
+                goto out;
+        }
+        mutex_lock(&opal_sensor_mutex);
+        ret = opal_sensor_read(sensor_hndl, token, &data);
+        if (ret != OPAL_ASYNC_COMPLETION)
+                goto out_token;
+        ret = opal_async_wait_response(token, &msg);
+        if (ret) {
+                pr_err("%s: Failed to wait for the async response, %d\n",
+                                __func__, ret);
+                goto out_token;
+        }
+        *sensor_data = be32_to_cpu(data);
+        ret = be64_to_cpu(msg.params[1]);
+out_token:
+        mutex_unlock(&opal_sensor_mutex);
+        opal_async_release_token(token);
+out:
+        return ret;
+}
+EXPORT_SYMBOL_GPL(opal_get_sensor_data);
diff --git a/arch/powerpc/platforms/powernv/opal-sysparam.c b/arch/powerpc/platforms/powernv/opal-sysparam.c
new file mode 100644
index 000000000000..6b614726baf2
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-sysparam.c
@@ -0,0 +1,290 @@
+/*
+ * PowerNV system parameter code
+ *
+ * Copyright (C) 2013 IBM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kobject.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/gfp.h>
+#include <linux/stat.h>
+#include <asm/opal.h>
+#define MAX_PARAM_DATA_LEN      64
+static DEFINE_MUTEX(opal_sysparam_mutex);
+static struct kobject *sysparam_kobj;
+static void *param_data_buf;
+struct param_attr {
+        struct list_head list;
+        u32 param_id;
+        u32 param_size;
+        struct kobj_attribute kobj_attr;
+};
+static int opal_get_sys_param(u32 param_id, u32 length, void *buffer)
+{
+        struct opal_msg msg;
+        int ret, token;
+        token = opal_async_get_token_interruptible();
+        if (token < 0) {
+                if (token != -ERESTARTSYS)
+                        pr_err("%s: Couldn't get the token, returning\n",
+                                        __func__);
+                ret = token;
+                goto out;
+        }
+        ret = opal_get_param(token, param_id, (u64)buffer, length);
+        if (ret != OPAL_ASYNC_COMPLETION)
+                goto out_token;
+        ret = opal_async_wait_response(token, &msg);
+        if (ret) {
+                pr_err("%s: Failed to wait for the async response, %d\n",
+                                __func__, ret);
+                goto out_token;
+        }
+        ret = be64_to_cpu(msg.params[1]);
+out_token:
+        opal_async_release_token(token);
+out:
+        return ret;
+}
+static int opal_set_sys_param(u32 param_id, u32 length, void *buffer)
+{
+        struct opal_msg msg;
+        int ret, token;
+        token = opal_async_get_token_interruptible();
+        if (token < 0) {
+                if (token != -ERESTARTSYS)
+                        pr_err("%s: Couldn't get the token, returning\n",
+                                        __func__);
+                ret = token;
+                goto out;
+        }
+        ret = opal_set_param(token, param_id, (u64)buffer, length);
+        if (ret != OPAL_ASYNC_COMPLETION)
+                goto out_token;
+        ret = opal_async_wait_response(token, &msg);
+        if (ret) {
+                pr_err("%s: Failed to wait for the async response, %d\n",
+                                __func__, ret);
+                goto out_token;
+        }
+        ret = be64_to_cpu(msg.params[1]);
+out_token:
+        opal_async_release_token(token);
+out:
+        return ret;
+}
+static ssize_t sys_param_show(struct kobject *kobj,
+                struct kobj_attribute *kobj_attr, char *buf)
+{
+        struct param_attr *attr = container_of(kobj_attr, struct param_attr,
+                        kobj_attr);
+        int ret;
+        mutex_lock(&opal_sysparam_mutex);
+        ret = opal_get_sys_param(attr->param_id, attr->param_size,
+                        param_data_buf);
+        if (ret)
+                goto out;
+        memcpy(buf, param_data_buf, attr->param_size);
+out:
+        mutex_unlock(&opal_sysparam_mutex);
+        return ret ? ret : attr->param_size;
+}
+static ssize_t sys_param_store(struct kobject *kobj,
+                struct kobj_attribute *kobj_attr, const char *buf, size_t count)
+{
+        struct param_attr *attr = container_of(kobj_attr, struct param_attr,
+                        kobj_attr);
+        int ret;
+        mutex_lock(&opal_sysparam_mutex);
+        memcpy(param_data_buf, buf, count);
+        ret = opal_set_sys_param(attr->param_id, attr->param_size,
+                        param_data_buf);
+        mutex_unlock(&opal_sysparam_mutex);
+        return ret ? ret : count;
+}
+void __init opal_sys_param_init(void)
+{
+        struct device_node *sysparam;
+        struct param_attr *attr;
+        u32 *id, *size;
+        int count, i;
+        u8 *perm;
+        if (!opal_kobj) {
+                pr_warn("SYSPARAM: opal kobject is not available\n");
+                goto out;
+        }
+        sysparam_kobj = kobject_create_and_add("sysparams", opal_kobj);
+        if (!sysparam_kobj) {
+                pr_err("SYSPARAM: Failed to create sysparam kobject\n");
+                goto out;
+        }
+        /* Allocate big enough buffer for any get/set transactions */
+        param_data_buf = kzalloc(MAX_PARAM_DATA_LEN, GFP_KERNEL);
+        if (!param_data_buf) {
+                pr_err("SYSPARAM: Failed to allocate memory for param data "
+                                "buf\n");
+                goto out_kobj_put;
+        }
+        sysparam = of_find_node_by_path("/ibm,opal/sysparams");
+        if (!sysparam) {
+                pr_err("SYSPARAM: Opal sysparam node not found\n");
+                goto out_param_buf;
+        }
+        if (!of_device_is_compatible(sysparam, "ibm,opal-sysparams")) {
+                pr_err("SYSPARAM: Opal sysparam node not compatible\n");
+                goto out_node_put;
+        }
+        /* Number of parameters exposed through DT */
+        count = of_property_count_strings(sysparam, "param-name");
+        if (count < 0) {
+                pr_err("SYSPARAM: No string found of property param-name in "
+                                "the node %s\n", sysparam->name);
+                goto out_node_put;
+        }
+        id = kzalloc(sizeof(*id) * count, GFP_KERNEL);
+        if (!id) {
+                pr_err("SYSPARAM: Failed to allocate memory to read parameter "
+                                "id\n");
+                goto out_node_put;
+        }
+        size = kzalloc(sizeof(*size) * count, GFP_KERNEL);
+        if (!size) {
+                pr_err("SYSPARAM: Failed to allocate memory to read parameter "
+                                "size\n");
+                goto out_free_id;
+        }
+        perm = kzalloc(sizeof(*perm) * count, GFP_KERNEL);
+        if (!perm) {
+                pr_err("SYSPARAM: Failed to allocate memory to read supported "
+                                "action on the parameter");
+                goto out_free_size;
+        }
+        if (of_property_read_u32_array(sysparam, "param-id", id, count)) {
+                pr_err("SYSPARAM: Missing property param-id in the DT\n");
+                goto out_free_perm;
+        }
+        if (of_property_read_u32_array(sysparam, "param-len", size, count)) {
+                pr_err("SYSPARAM: Missing propery param-len in the DT\n");
+                goto out_free_perm;
+        }
+        if (of_property_read_u8_array(sysparam, "param-perm", perm, count)) {
+                pr_err("SYSPARAM: Missing propery param-perm in the DT\n");
+                goto out_free_perm;
+        }
+        attr = kzalloc(sizeof(*attr) * count, GFP_KERNEL);
+        if (!attr) {
+                pr_err("SYSPARAM: Failed to allocate memory for parameter "
+                                "attributes\n");
+                goto out_free_perm;
+        }
+        /* For each of the parameters, populate the parameter attributes */
+        for (i = 0; i < count; i++) {
+                sysfs_attr_init(&attr[i].kobj_attr.attr);
+                attr[i].param_id = id[i];
+                attr[i].param_size = size[i];
+                if (of_property_read_string_index(sysparam, "param-name", i,
+                                &attr[i].kobj_attr.attr.name))
+                        continue;
+                /* If the parameter is read-only or read-write */
+                switch (perm[i] & 3) {
+                case OPAL_SYSPARAM_READ:
+                        attr[i].kobj_attr.attr.mode = S_IRUGO;
+                        break;
+                case OPAL_SYSPARAM_WRITE:
+                        attr[i].kobj_attr.attr.mode = S_IWUGO;
+                        break;
+                case OPAL_SYSPARAM_RW:
+                        attr[i].kobj_attr.attr.mode = S_IRUGO | S_IWUGO;
+                        break;
+                default:
+                        break;
+                }
+                attr[i].kobj_attr.show = sys_param_show;
+                attr[i].kobj_attr.store = sys_param_store;
+                if (sysfs_create_file(sysparam_kobj, &attr[i].kobj_attr.attr)) {
+                        pr_err("SYSPARAM: Failed to create sysfs file %s\n",
+                                        attr[i].kobj_attr.attr.name);
+                        goto out_free_attr;
+                }
+        }
+        kfree(perm);
+        kfree(size);
+        kfree(id);
+        of_node_put(sysparam);
+        return;
+out_free_attr:
+        kfree(attr);
+out_free_perm:
+        kfree(perm);
+out_free_size:
+        kfree(size);
+out_free_id:
+        kfree(id);
+out_node_put:
+        of_node_put(sysparam);
+out_param_buf:
+        kfree(param_data_buf);
+out_kobj_put:
+        kobject_put(sysparam_kobj);
+out:
+        return;
+}
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index 3e8829c40fbb..f531ffe35b3e 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -61,6 +61,7 @@ _STATIC(opal_return)
        mtcr    r4;
        rfid
+OPAL_CALL(opal_invalid_call,                    OPAL_INVALID_CALL);
 OPAL_CALL(opal_console_write,                   OPAL_CONSOLE_WRITE);
 OPAL_CALL(opal_console_read,                    OPAL_CONSOLE_READ);
 OPAL_CALL(opal_console_write_buffer_space,      OPAL_CONSOLE_WRITE_BUFFER_SPACE);
@@ -123,9 +124,24 @@ OPAL_CALL(opal_xscom_write,			OPAL_XSCOM_WRITE);
 OPAL_CALL(opal_lpc_read,                        OPAL_LPC_READ);
 OPAL_CALL(opal_lpc_write,                       OPAL_LPC_WRITE);
 OPAL_CALL(opal_return_cpu,                      OPAL_RETURN_CPU);
+OPAL_CALL(opal_read_elog,                       OPAL_ELOG_READ);
+OPAL_CALL(opal_send_ack_elog,                   OPAL_ELOG_ACK);
+OPAL_CALL(opal_get_elog_size,                   OPAL_ELOG_SIZE);
+OPAL_CALL(opal_resend_pending_logs,             OPAL_ELOG_RESEND);
+OPAL_CALL(opal_write_elog,                      OPAL_ELOG_WRITE);
 OPAL_CALL(opal_validate_flash,                  OPAL_FLASH_VALIDATE);
 OPAL_CALL(opal_manage_flash,                    OPAL_FLASH_MANAGE);
 OPAL_CALL(opal_update_flash,                    OPAL_FLASH_UPDATE);
+OPAL_CALL(opal_resync_timebase,                 OPAL_RESYNC_TIMEBASE);
+OPAL_CALL(opal_dump_init,                       OPAL_DUMP_INIT);
+OPAL_CALL(opal_dump_info,                       OPAL_DUMP_INFO);
+OPAL_CALL(opal_dump_info2,                      OPAL_DUMP_INFO2);
+OPAL_CALL(opal_dump_read,                       OPAL_DUMP_READ);
+OPAL_CALL(opal_dump_ack,                        OPAL_DUMP_ACK);
 OPAL_CALL(opal_get_msg,                         OPAL_GET_MSG);
 OPAL_CALL(opal_check_completion,                OPAL_CHECK_ASYNC_COMPLETION);
+OPAL_CALL(opal_dump_resend_notification,        OPAL_DUMP_RESEND);
 OPAL_CALL(opal_sync_host_reboot,                OPAL_SYNC_HOST_REBOOT);
+OPAL_CALL(opal_sensor_read,                     OPAL_SENSOR_READ);
+OPAL_CALL(opal_get_param,                       OPAL_GET_PARAM);
+OPAL_CALL(opal_set_param,                       OPAL_SET_PARAM);
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index 65499adaecff..49d2f00019e5 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -21,6 +21,7 @@
 #include <linux/sched.h>
 #include <linux/kobject.h>
 #include <linux/delay.h>
+#include <linux/memblock.h>
 #include <asm/opal.h>
 #include <asm/firmware.h>
 #include <asm/mce.h>
@@ -33,9 +34,19 @@ struct kobject *opal_kobj;
 struct opal {
        u64 base;
        u64 entry;
+        u64 size;
 } opal;
-static struct device_node *opal_node;
+struct mcheck_recoverable_range {
+        u64 start_addr;
+        u64 end_addr;
+        u64 recover_addr;
+};
+static struct mcheck_recoverable_range *mc_recoverable_range;
+static int mc_recoverable_range_len;
+struct device_node *opal_node;
 static DEFINE_SPINLOCK(opal_write_lock);
 extern u64 opal_mc_secondary_handler[];
 static unsigned int *opal_irqs;
@@ -49,25 +60,29 @@ static atomic_t opal_notifier_hold = ATOMIC_INIT(0);
 int __init early_init_dt_scan_opal(unsigned long node,
                                   const char *uname, int depth, void *data)
 {
-        const void *basep, *entryp;
+        const void *basep, *entryp, *sizep;
-        unsigned long basesz, entrysz;
+        unsigned long basesz, entrysz, runtimesz;
        if (depth != 1 || strcmp(uname, "ibm,opal") != 0)
                return 0;
        basep  = of_get_flat_dt_prop(node, "opal-base-address", &basesz);
        entryp = of_get_flat_dt_prop(node, "opal-entry-address", &entrysz);
+        sizep = of_get_flat_dt_prop(node, "opal-runtime-size", &runtimesz);
-        if (!basep || !entryp)
+        if (!basep || !entryp || !sizep)
                return 1;
        opal.base = of_read_number(basep, basesz/4);
        opal.entry = of_read_number(entryp, entrysz/4);
+        opal.size = of_read_number(sizep, runtimesz/4);
        pr_debug("OPAL Base  = 0x%llx (basep=%p basesz=%ld)\n",
                 opal.base, basep, basesz);
        pr_debug("OPAL Entry = 0x%llx (entryp=%p basesz=%ld)\n",
                 opal.entry, entryp, entrysz);
+        pr_debug("OPAL Entry = 0x%llx (sizep=%p runtimesz=%ld)\n",
+                 opal.size, sizep, runtimesz);
        powerpc_firmware_features |= FW_FEATURE_OPAL;
        if (of_flat_dt_is_compatible(node, "ibm,opal-v3")) {
@@ -84,6 +99,65 @@ int __init early_init_dt_scan_opal(unsigned long node,
        return 1;
 }
+int __init early_init_dt_scan_recoverable_ranges(unsigned long node,
+                                   const char *uname, int depth, void *data)
+{
+        unsigned long i, psize, size;
+        const __be32 *prop;
+        if (depth != 1 || strcmp(uname, "ibm,opal") != 0)
+                return 0;
+        prop = of_get_flat_dt_prop(node, "mcheck-recoverable-ranges", &psize);
+        if (!prop)
+                return 1;
+        pr_debug("Found machine check recoverable ranges.\n");
+        /*
+         * Calculate number of available entries.
+         *
+         * Each recoverable address range entry is (start address, len,
+         * recovery address), 2 cells each for start and recovery address,
+         * 1 cell for len, totalling 5 cells per entry.
+         */
+        mc_recoverable_range_len = psize / (sizeof(*prop) * 5);
+        /* Sanity check */
+        if (!mc_recoverable_range_len)
+                return 1;
+        /* Size required to hold all the entries. */
+        size = mc_recoverable_range_len *
+                        sizeof(struct mcheck_recoverable_range);
+        /*
+         * Allocate a buffer to hold the MC recoverable ranges. We would be
+         * accessing them in real mode, hence it needs to be within
+         * RMO region.
+         */
+        mc_recoverable_range =__va(memblock_alloc_base(size, __alignof__(u64),
+                                                        ppc64_rma_size));
+        memset(mc_recoverable_range, 0, size);
+        for (i = 0; i < mc_recoverable_range_len; i++) {
+                mc_recoverable_range[i].start_addr =
+                                        of_read_number(prop + (i * 5) + 0, 2);
+                mc_recoverable_range[i].end_addr =
+                                        mc_recoverable_range[i].start_addr +
+                                        of_read_number(prop + (i * 5) + 2, 1);
+                mc_recoverable_range[i].recover_addr =
+                                        of_read_number(prop + (i * 5) + 3, 2);
+                pr_debug("Machine check recoverable range: %llx..%llx: %llx\n",
+                                mc_recoverable_range[i].start_addr,
+                                mc_recoverable_range[i].end_addr,
+                                mc_recoverable_range[i].recover_addr);
+        }
+        return 1;
+}
 static int __init opal_register_exception_handlers(void)
 {
 #ifdef __BIG_ENDIAN__
@@ -118,6 +192,20 @@ int opal_notifier_register(struct notifier_block *nb)
        atomic_notifier_chain_register(&opal_notifier_head, nb);
        return 0;
 }
+EXPORT_SYMBOL_GPL(opal_notifier_register);
+int opal_notifier_unregister(struct notifier_block *nb)
+{
+        if (!nb) {
+                pr_warning("%s: Invalid argument (%p)\n",
+                           __func__, nb);
+                return -EINVAL;
+        }
+        atomic_notifier_chain_unregister(&opal_notifier_head, nb);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(opal_notifier_unregister);
 static void opal_do_notifier(uint64_t events)
 {
@@ -205,6 +293,7 @@ static void opal_handle_message(void)
         * value in /proc/device-tree.
         */
        static struct opal_msg msg;
+        u32 type;
        ret = opal_get_msg(__pa(&msg), sizeof(msg));
        /* No opal message pending. */
@@ -218,13 +307,14 @@ static void opal_handle_message(void)
                return;
        }
+        type = be32_to_cpu(msg.msg_type);
        /* Sanity check */
-        if (msg.msg_type > OPAL_MSG_TYPE_MAX) {
+        if (type > OPAL_MSG_TYPE_MAX) {
-                pr_warning("%s: Unknown message type: %u\n",
+                pr_warning("%s: Unknown message type: %u\n", __func__, type);
-                                __func__, msg.msg_type);
                return;
        }
-        opal_message_do_notify(msg.msg_type, (void *)&msg);
+        opal_message_do_notify(type, (void *)&msg);
 }
 static int opal_message_notify(struct notifier_block *nb,
@@ -401,6 +491,38 @@ int opal_machine_check(struct pt_regs *regs)
        return 0;
 }
+static uint64_t find_recovery_address(uint64_t nip)
+{
+        int i;
+        for (i = 0; i < mc_recoverable_range_len; i++)
+                if ((nip >= mc_recoverable_range[i].start_addr) &&
+                    (nip < mc_recoverable_range[i].end_addr))
+                    return mc_recoverable_range[i].recover_addr;
+        return 0;
+}
+bool opal_mce_check_early_recovery(struct pt_regs *regs)
+{
+        uint64_t recover_addr = 0;
+        if (!opal.base || !opal.size)
+                goto out;
+        if ((regs->nip >= opal.base) &&
+                        (regs->nip <= (opal.base + opal.size)))
+                recover_addr = find_recovery_address(regs->nip);
+        /*
+         * Setup regs->nip to rfi into fixup address.
+         */
+        if (recover_addr)
+                regs->nip = recover_addr;
+out:
+        return !!recover_addr;
+}
 static irqreturn_t opal_interrupt(int irq, void *data)
 {
        __be64 events;
@@ -472,8 +594,16 @@ static int __init opal_init(void)
        /* Create "opal" kobject under /sys/firmware */
        rc = opal_sysfs_init();
        if (rc == 0) {
+                /* Setup error log interface */
+                rc = opal_elog_init();
                /* Setup code update interface */
                opal_flash_init();
+                /* Setup platform dump extract interface */
+                opal_platform_dump_init();
+                /* Setup system parameters interface */
+                opal_sys_param_init();
+                /* Setup message log interface. */
+                opal_msglog_init();
        }
        return 0;
@@ -505,3 +635,6 @@ void opal_shutdown(void)
                        mdelay(10);
        }
 }
+/* Export this so that test modules can use it */
+EXPORT_SYMBOL_GPL(opal_invalid_call);
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 81a7a0a79be7..61cf8fa9c61b 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -187,6 +187,7 @@ static void __init pnv_setup_machdep_opal(void)
        ppc_md.power_off = pnv_power_off;
        ppc_md.halt = pnv_halt;
        ppc_md.machine_check_exception = opal_machine_check;
+        ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
 }
 #ifdef CONFIG_PPC_POWERNV_RTAS
diff --git a/arch/powerpc/platforms/ps3/Kconfig b/arch/powerpc/platforms/ps3/Kconfig
index e87c19473973..56f274064d6c 100644
--- a/arch/powerpc/platforms/ps3/Kconfig
+++ b/arch/powerpc/platforms/ps3/Kconfig
@@ -2,10 +2,8 @@ config PPC_PS3
        bool "Sony PS3"
        depends on PPC64 && PPC_BOOK3S
        select PPC_CELL
-        select USB_ARCH_HAS_OHCI
        select USB_OHCI_LITTLE_ENDIAN
        select USB_OHCI_BIG_ENDIAN_MMIO
-        select USB_ARCH_HAS_EHCI
        select USB_EHCI_BIG_ENDIAN_MMIO
        select PPC_PCI_CHOICE
        help
diff --git a/arch/powerpc/platforms/ps3/smp.c b/arch/powerpc/platforms/ps3/smp.c
index 4b35166229fe..b358bec6c8cb 100644
--- a/arch/powerpc/platforms/ps3/smp.c
+++ b/arch/powerpc/platforms/ps3/smp.c
@@ -76,7 +76,7 @@ static int __init ps3_smp_probe(void)
                BUILD_BUG_ON(PPC_MSG_CALL_FUNCTION    != 0);
                BUILD_BUG_ON(PPC_MSG_RESCHEDULE       != 1);
-                BUILD_BUG_ON(PPC_MSG_CALL_FUNC_SINGLE != 2);
+                BUILD_BUG_ON(PPC_MSG_TICK_BROADCAST   != 2);
                BUILD_BUG_ON(PPC_MSG_DEBUGGER_BREAK   != 3);
                for (i = 0; i < MSG_COUNT; i++) {
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 80b1d57c306a..2cb8b776c84a 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -111,6 +111,18 @@ config CMM
          will be reused for other LPARs. The interface allows firmware to
          balance memory across many LPARs.
+config HV_PERF_CTRS
+       bool "Hypervisor supplied PMU events (24x7 & GPCI)"
+       default y
+       depends on PERF_EVENTS && PPC_PSERIES
+       help
+          Enable access to hypervisor supplied counters in perf. Currently,
+          this enables code that uses the hcall GetPerfCounterInfo and 24x7
+          interfaces to retrieve counters. GPCI exists on Power 6 and later
+          systems. 24x7 is available on Power 8 systems.
+          If unsure, select Y.
 config DTL
        bool "Dispatch Trace Log"
        depends on PPC_SPLPAR && DEBUG_FS
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index a8fe5aa3d34f..022b38e6a80b 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -11,7 +11,6 @@
 */
 #include <linux/kernel.h>
-#include <linux/kref.h>
 #include <linux/notifier.h>
 #include <linux/spinlock.h>
 #include <linux/cpu.h>
@@ -87,7 +86,6 @@ static struct device_node *dlpar_parse_cc_node(struct cc_workarea *ccwa,
        }
        of_node_set_flag(dn, OF_DYNAMIC);
-        kref_init(&dn->kref);
        return dn;
 }
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index 0ea99e3d4815..9b8e05078a63 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -420,4 +420,4 @@ static int __init pseries_cpu_hotplug_init(void)
        return 0;
 }
-arch_initcall(pseries_cpu_hotplug_init);
+machine_arch_initcall(pseries, pseries_cpu_hotplug_init);
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index 9590dbb756f2..573b488fc48b 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -14,6 +14,7 @@
 #include <linux/memblock.h>
 #include <linux/vmalloc.h>
 #include <linux/memory.h>
+#include <linux/memory_hotplug.h>
 #include <asm/firmware.h>
 #include <asm/machdep.h>
@@ -75,13 +76,27 @@ unsigned long memory_block_size_bytes(void)
 }
 #ifdef CONFIG_MEMORY_HOTREMOVE
-static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size)
+static int pseries_remove_memory(u64 start, u64 size)
 {
-        unsigned long start, start_pfn;
-        struct zone *zone;
        int ret;
-        unsigned long section;
-        unsigned long sections_to_remove;
+        /* Remove htab bolted mappings for this section of memory */
+        start = (unsigned long)__va(start);
+        ret = remove_section_mapping(start, start + size);
+        /* Ensure all vmalloc mappings are flushed in case they also
+         * hit that section of memory
+         */
+        vm_unmap_aliases();
+        return ret;
+}
+static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size)
+{
+        unsigned long block_sz, start_pfn;
+        int sections_per_block;
+        int i, nid;
        start_pfn = base >> PAGE_SHIFT;
@@ -90,45 +105,21 @@ static int pseries_remove_memblock(unsigned long base, unsigned int memblock_siz
                return 0;
        }
-        zone = page_zone(pfn_to_page(start_pfn));
+        block_sz = memory_block_size_bytes();
+        sections_per_block = block_sz / MIN_MEMORY_BLOCK_SIZE;
+        nid = memory_add_physaddr_to_nid(base);
-        /*
+        for (i = 0; i < sections_per_block; i++) {
-         * Remove section mappings and sysfs entries for the
+                remove_memory(nid, base, MIN_MEMORY_BLOCK_SIZE);
-         * section of the memory we are removing.
+                base += MIN_MEMORY_BLOCK_SIZE;
-         *
-         * NOTE: Ideally, this should be done in generic code like
-         * remove_memory(). But remove_memory() gets called by writing
-         * to sysfs "state" file and we can't remove sysfs entries
-         * while writing to it. So we have to defer it to here.
-         */
-        sections_to_remove = (memblock_size >> PAGE_SHIFT) / PAGES_PER_SECTION;
-        for (section = 0; section < sections_to_remove; section++) {
-                unsigned long pfn = start_pfn + section * PAGES_PER_SECTION;
-                ret = __remove_pages(zone, pfn, PAGES_PER_SECTION);
-                if (ret)
-                        return ret;
        }
-        /*
+        /* Update memory regions for memory remove */
-         * Update memory regions for memory remove
-         */
        memblock_remove(base, memblock_size);
+        return 0;
-        /*
-         * Remove htab bolted mappings for this section of memory
-         */
-        start = (unsigned long)__va(base);
-        ret = remove_section_mapping(start, start + memblock_size);
-        /* Ensure all vmalloc mappings are flushed in case they also
-         * hit that section of memory
-         */
-        vm_unmap_aliases();
-        return ret;
 }
-static int pseries_remove_memory(struct device_node *np)
+static int pseries_remove_mem_node(struct device_node *np)
 {
        const char *type;
        const unsigned int *regs;
@@ -153,8 +144,8 @@ static int pseries_remove_memory(struct device_node *np)
        base = *(unsigned long *)regs;
        lmb_size = regs[3];
-        ret = pseries_remove_memblock(base, lmb_size);
+        pseries_remove_memblock(base, lmb_size);
-        return ret;
+        return 0;
 }
 #else
 static inline int pseries_remove_memblock(unsigned long base,
@@ -162,13 +153,13 @@ static inline int pseries_remove_memblock(unsigned long base,
 {
        return -EOPNOTSUPP;
 }
-static inline int pseries_remove_memory(struct device_node *np)
+static inline int pseries_remove_mem_node(struct device_node *np)
 {
        return -EOPNOTSUPP;
 }
 #endif /* CONFIG_MEMORY_HOTREMOVE */
-static int pseries_add_memory(struct device_node *np)
+static int pseries_add_mem_node(struct device_node *np)
 {
        const char *type;
        const unsigned int *regs;
@@ -254,10 +245,10 @@ static int pseries_memory_notifier(struct notifier_block *nb,
        switch (action) {
        case OF_RECONFIG_ATTACH_NODE:
-                err = pseries_add_memory(node);
+                err = pseries_add_mem_node(node);
                break;
        case OF_RECONFIG_DETACH_NODE:
-                err = pseries_remove_memory(node);
+                err = pseries_remove_mem_node(node);
                break;
        case OF_RECONFIG_UPDATE_PROPERTY:
                pr = (struct of_prop_reconfig *)node;
@@ -277,6 +268,10 @@ static int __init pseries_memory_hotplug_init(void)
        if (firmware_has_feature(FW_FEATURE_LPAR))
                of_reconfig_notifier_register(&pseries_mem_nb);
+#ifdef CONFIG_MEMORY_HOTREMOVE
+        ppc_md.remove_memory = pseries_remove_memory;
+#endif
        return 0;
 }
 machine_device_initcall(pseries, pseries_memory_hotplug_init);
diff --git a/arch/powerpc/platforms/pseries/io_event_irq.c b/arch/powerpc/platforms/pseries/io_event_irq.c
index 5ea88d1541f7..0240c4ff878a 100644
--- a/arch/powerpc/platforms/pseries/io_event_irq.c
+++ b/arch/powerpc/platforms/pseries/io_event_irq.c
@@ -82,9 +82,9 @@ static struct pseries_io_event * ioei_find_event(struct rtas_error_log *elog)
         * RTAS_TYPE_IO only exists in extended event log version 6 or later.
         * No need to check event log version.
         */
-        if (unlikely(elog->type != RTAS_TYPE_IO)) {
+        if (unlikely(rtas_error_type(elog) != RTAS_TYPE_IO)) {
-                printk_once(KERN_WARNING "io_event_irq: Unexpected event type %d",
+                printk_once(KERN_WARNING"io_event_irq: Unexpected event type %d",
-                            elog->type);
+                            rtas_error_type(elog));
                return NULL;
        }
diff --git a/arch/powerpc/platforms/pseries/mobility.c b/arch/powerpc/platforms/pseries/mobility.c
index cde4e0a095ae..bde7ebad3949 100644
--- a/arch/powerpc/platforms/pseries/mobility.c
+++ b/arch/powerpc/platforms/pseries/mobility.c
@@ -290,13 +290,6 @@ void post_mobility_fixup(void)
        int rc;
        int activate_fw_token;
-        rc = pseries_devicetree_update(MIGRATION_SCOPE);
-        if (rc) {
-                printk(KERN_ERR "Initial post-mobility device tree update "
-                       "failed: %d\n", rc);
-                return;
-        }
        activate_fw_token = rtas_token("ibm,activate-firmware");
        if (activate_fw_token == RTAS_UNKNOWN_SERVICE) {
                printk(KERN_ERR "Could not make post-mobility "
@@ -304,16 +297,17 @@ void post_mobility_fixup(void)
                return;
        }
-        rc = rtas_call(activate_fw_token, 0, 1, NULL);
+        do {
-        if (!rc) {
+                rc = rtas_call(activate_fw_token, 0, 1, NULL);
-                rc = pseries_devicetree_update(MIGRATION_SCOPE);
+        } while (rtas_busy_delay(rc));
-                if (rc)
-                        printk(KERN_ERR "Secondary post-mobility device tree "
+        if (rc)
-                               "update failed: %d\n", rc);
-        } else {
                printk(KERN_ERR "Post-mobility activate-fw failed: %d\n", rc);
-                return;
-        }
+        rc = pseries_devicetree_update(MIGRATION_SCOPE);
+        if (rc)
+                printk(KERN_ERR "Post-mobility device tree update "
+                        "failed: %d\n", rc);
        return;
 }
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
index d7096f2f7751..0cc240b7f694 100644
--- a/arch/powerpc/platforms/pseries/nvram.c
+++ b/arch/powerpc/platforms/pseries/nvram.c
@@ -298,13 +298,13 @@ int nvram_write_os_partition(struct nvram_os_partition *part, char * buff,
        rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index);
        if (rc <= 0) {
-                pr_err("%s: Failed nvram_write (%d)\n", __FUNCTION__, rc);
+                pr_err("%s: Failed nvram_write (%d)\n", __func__, rc);
                return rc;
        }
        rc = ppc_md.nvram_write(buff, length, &tmp_index);
        if (rc <= 0) {
-                pr_err("%s: Failed nvram_write (%d)\n", __FUNCTION__, rc);
+                pr_err("%s: Failed nvram_write (%d)\n", __func__, rc);
                return rc;
        }
        
@@ -351,15 +351,14 @@ int nvram_read_partition(struct nvram_os_partition *part, char *buff,
                                        sizeof(struct err_log_info),
                                        &tmp_index);
                if (rc <= 0) {
-                        pr_err("%s: Failed nvram_read (%d)\n", __FUNCTION__,
+                        pr_err("%s: Failed nvram_read (%d)\n", __func__, rc);
-                                                                        rc);
                        return rc;
                }
        }
        rc = ppc_md.nvram_read(buff, length, &tmp_index);
        if (rc <= 0) {
-                pr_err("%s: Failed nvram_read (%d)\n", __FUNCTION__, rc);
+                pr_err("%s: Failed nvram_read (%d)\n", __func__, rc);
                return rc;
        }
@@ -869,7 +868,7 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
                break;
        default:
                pr_err("%s: ignoring unrecognized KMSG_DUMP_* reason %d\n",
-                                                __FUNCTION__, (int) reason);
+                       __func__, (int) reason);
                return;
        }
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index efe61374f6ea..203cbf0dc101 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -37,15 +37,15 @@ find_bus_among_children(struct pci_bus *bus,
                        struct device_node *dn)
 {
        struct pci_bus *child = NULL;
-        struct list_head *tmp;
+        struct pci_bus *tmp;
        struct device_node *busdn;
        busdn = pci_bus_to_OF_node(bus);
        if (busdn == dn)
                return bus;
-        list_for_each(tmp, &bus->children) {
+        list_for_each_entry(tmp, &bus->children, node) {
-                child = find_bus_among_children(pci_bus_b(tmp), dn);
+                child = find_bus_among_children(tmp, dn);
                if (child)
                        break;
        };
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index 721c0586b284..9c5778e6ed4b 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c
@@ -236,7 +236,8 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id)
        rtas_elog = (struct rtas_error_log *)ras_log_buf;
-        if ((status == 0) && (rtas_elog->severity >= RTAS_SEVERITY_ERROR_SYNC))
+        if (status == 0 &&
+            rtas_error_severity(rtas_elog) >= RTAS_SEVERITY_ERROR_SYNC)
                fatal = 1;
        else
                fatal = 0;
@@ -300,13 +301,14 @@ static struct rtas_error_log *fwnmi_get_errinfo(struct pt_regs *regs)
        /* If it isn't an extended log we can use the per cpu 64bit buffer */
        h = (struct rtas_error_log *)&savep[1];
-        if (!h->extended) {
+        if (!rtas_error_extended(h)) {
                memcpy(&__get_cpu_var(mce_data_buf), h, sizeof(__u64));
                errhdr = (struct rtas_error_log *)&__get_cpu_var(mce_data_buf);
        } else {
-                int len;
+                int len, error_log_length;
-                len = max_t(int, 8+h->extended_log_length, RTAS_ERROR_LOG_MAX);
+                error_log_length = 8 + rtas_error_extended_log_length(h);
+                len = max_t(int, error_log_length, RTAS_ERROR_LOG_MAX);
                memset(global_mce_data_buf, 0, RTAS_ERROR_LOG_MAX);
                memcpy(global_mce_data_buf, h, len);
                errhdr = (struct rtas_error_log *)global_mce_data_buf;
@@ -350,23 +352,24 @@ int pSeries_system_reset_exception(struct pt_regs *regs)
 static int recover_mce(struct pt_regs *regs, struct rtas_error_log *err)
 {
        int recovered = 0;
+        int disposition = rtas_error_disposition(err);
        if (!(regs->msr & MSR_RI)) {
                /* If MSR_RI isn't set, we cannot recover */
                recovered = 0;
-        } else if (err->disposition == RTAS_DISP_FULLY_RECOVERED) {
+        } else if (disposition == RTAS_DISP_FULLY_RECOVERED) {
                /* Platform corrected itself */
                recovered = 1;
-        } else if (err->disposition == RTAS_DISP_LIMITED_RECOVERY) {
+        } else if (disposition == RTAS_DISP_LIMITED_RECOVERY) {
                /* Platform corrected itself but could be degraded */
                printk(KERN_ERR "MCE: limited recovery, system may "
                       "be degraded\n");
                recovered = 1;
        } else if (user_mode(regs) && !is_global_init(current) &&
-                   err->severity == RTAS_SEVERITY_ERROR_SYNC) {
+                   rtas_error_severity(err) == RTAS_SEVERITY_ERROR_SYNC) {
                /*
                 * If we received a synchronous error when in userspace
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index f93cdf55628c..0435bb65d0aa 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -12,7 +12,6 @@
 */
 #include <linux/kernel.h>
-#include <linux/kref.h>
 #include <linux/notifier.h>
 #include <linux/proc_fs.h>
 #include <linux/slab.h>
@@ -70,7 +69,6 @@ static int pSeries_reconfig_add_node(const char *path, struct property *proplist
        np->properties = proplist;
        of_node_set_flag(np, OF_DYNAMIC);
-        kref_init(&np->kref);
        np->parent = derive_parent(path);
        if (IS_ERR(np->parent)) {
diff --git a/arch/powerpc/platforms/pseries/suspend.c b/arch/powerpc/platforms/pseries/suspend.c
index 16a255255d30..b87b97849d4c 100644
--- a/arch/powerpc/platforms/pseries/suspend.c
+++ b/arch/powerpc/platforms/pseries/suspend.c
@@ -26,6 +26,7 @@
 #include <asm/mmu.h>
 #include <asm/rtas.h>
 #include <asm/topology.h>
+#include "../../kernel/cacheinfo.h"
 static u64 stream_id;
 static struct device suspend_dev;
@@ -79,6 +80,23 @@ static int pseries_suspend_cpu(void)
 }
 /**
+ * pseries_suspend_enable_irqs
+ *
+ * Post suspend configuration updates
+ *
+ **/
+static void pseries_suspend_enable_irqs(void)
+{
+        /*
+         * Update configuration which can be modified based on device tree
+         * changes during resume.
+         */
+        cacheinfo_cpu_offline(smp_processor_id());
+        post_mobility_fixup();
+        cacheinfo_cpu_online(smp_processor_id());
+}
+/**
 * pseries_suspend_enter - Final phase of hibernation
 *
 * Return value:
@@ -174,7 +192,30 @@ out:
        return rc;
 }
-static DEVICE_ATTR(hibernate, S_IWUSR, NULL, store_hibernate);
+#define USER_DT_UPDATE  0
+#define KERN_DT_UPDATE  1
+/**
+ * show_hibernate - Report device tree update responsibilty
+ * @dev:                subsys root device
+ * @attr:               device attribute struct
+ * @buf:                buffer
+ *
+ * Report whether a device tree update is performed by the kernel after a
+ * resume, or if drmgr must coordinate the update from user space.
+ *
+ * Return value:
+ *      0 if drmgr is to initiate update, and 1 otherwise
+ **/
+static ssize_t show_hibernate(struct device *dev,
+                              struct device_attribute *attr,
+                              char *buf)
+{
+        return sprintf(buf, "%d\n", KERN_DT_UPDATE);
+}
+static DEVICE_ATTR(hibernate, S_IWUSR | S_IRUGO,
+                   show_hibernate, store_hibernate);
 static struct bus_type suspend_subsys = {
        .name = "power",
@@ -235,6 +276,7 @@ static int __init pseries_suspend_init(void)
                return rc;
        ppc_md.suspend_disable_cpu = pseries_suspend_cpu;
+        ppc_md.suspend_enable_irqs = pseries_suspend_enable_irqs;
        suspend_set_ops(&pseries_suspend_ops);
        return 0;
 }
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index f67ac900d870..afbcc37aa094 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_FSL_SOC)		+= fsl_soc.o fsl_mpic_err.o
 obj-$(CONFIG_FSL_PCI)           += fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_PMC)           += fsl_pmc.o
 obj-$(CONFIG_FSL_LBC)           += fsl_lbc.o
-obj-$(CONFIG_FSL_IFC)           += fsl_ifc.o
 obj-$(CONFIG_FSL_GTM)           += fsl_gtm.o
 obj-$(CONFIG_FSL_85XX_CACHE_SRAM)       += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
 obj-$(CONFIG_SIMPLE_GPIO)       += simple_gpio.o
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/arch/powerpc/sysdev/fsl_ifc.c
deleted file mode 100644
index fbc885b31946..000000000000
--- a/arch/powerpc/sysdev/fsl_ifc.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc
- *
- * Freescale Integrated Flash Controller
- *
- * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/compiler.h>
-#include <linux/spinlock.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <asm/prom.h>
-#include <asm/fsl_ifc.h>
-struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
-EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
-/*
- * convert_ifc_address - convert the base address
- * @addr_base:  base address of the memory bank
- */
-unsigned int convert_ifc_address(phys_addr_t addr_base)
-{
-        return addr_base & CSPR_BA;
-}
-EXPORT_SYMBOL(convert_ifc_address);
-/*
- * fsl_ifc_find - find IFC bank
- * @addr_base:  base address of the memory bank
- *
- * This function walks IFC banks comparing "Base address" field of the CSPR
- * registers with the supplied addr_base argument. When bases match this
- * function returns bank number (starting with 0), otherwise it returns
- * appropriate errno value.
- */
-int fsl_ifc_find(phys_addr_t addr_base)
-{
-        int i = 0;
-        if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
-                return -ENODEV;
-        for (i = 0; i < ARRAY_SIZE(fsl_ifc_ctrl_dev->regs->cspr_cs); i++) {
-                u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
-                if (cspr & CSPR_V && (cspr & CSPR_BA) ==
-                                convert_ifc_address(addr_base))
-                        return i;
-        }
-        return -ENOENT;
-}
-EXPORT_SYMBOL(fsl_ifc_find);
-static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
-{
-        struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
-        /*
-         * Clear all the common status and event registers
-         */
-        if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
-                out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
-        /* enable all error and events */
-        out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN);
-        /* enable all error and event interrupts */
-        out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN);
-        out_be32(&ifc->cm_erattr0, 0x0);
-        out_be32(&ifc->cm_erattr1, 0x0);
-        return 0;
-}
-static int fsl_ifc_ctrl_remove(struct platform_device *dev)
-{
-        struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
-        free_irq(ctrl->nand_irq, ctrl);
-        free_irq(ctrl->irq, ctrl);
-        irq_dispose_mapping(ctrl->nand_irq);
-        irq_dispose_mapping(ctrl->irq);
-        iounmap(ctrl->regs);
-        dev_set_drvdata(&dev->dev, NULL);
-        kfree(ctrl);
-        return 0;
-}
-/*
- * NAND events are split between an operational interrupt which only
- * receives OPC, and an error interrupt that receives everything else,
- * including non-NAND errors.  Whichever interrupt gets to it first
- * records the status and wakes the wait queue.
- */
-static DEFINE_SPINLOCK(nand_irq_lock);
-static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
-{
-        struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
-        unsigned long flags;
-        u32 stat;
-        spin_lock_irqsave(&nand_irq_lock, flags);
-        stat = in_be32(&ifc->ifc_nand.nand_evter_stat);
-        if (stat) {
-                out_be32(&ifc->ifc_nand.nand_evter_stat, stat);
-                ctrl->nand_stat = stat;
-                wake_up(&ctrl->nand_wait);
-        }
-        spin_unlock_irqrestore(&nand_irq_lock, flags);
-        return stat;
-}
-static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
-{
-        struct fsl_ifc_ctrl *ctrl = data;
-        if (check_nand_stat(ctrl))
-                return IRQ_HANDLED;
-        return IRQ_NONE;
-}
-/*
- * NOTE: This interrupt is used to report ifc events of various kinds,
- * such as transaction errors on the chipselects.
- */
-static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
-{
-        struct fsl_ifc_ctrl *ctrl = data;
-        struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
-        u32 err_axiid, err_srcid, status, cs_err, err_addr;
-        irqreturn_t ret = IRQ_NONE;
-        /* read for chip select error */
-        cs_err = in_be32(&ifc->cm_evter_stat);
-        if (cs_err) {
-                dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
-                                "any memory bank 0x%08X\n", cs_err);
-                /* clear the chip select error */
-                out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
-                /* read error attribute registers print the error information */
-                status = in_be32(&ifc->cm_erattr0);
-                err_addr = in_be32(&ifc->cm_erattr1);
-                if (status & IFC_CM_ERATTR0_ERTYP_READ)
-                        dev_err(ctrl->dev, "Read transaction error"
-                                "CM_ERATTR0 0x%08X\n", status);
-                else
-                        dev_err(ctrl->dev, "Write transaction error"
-                                "CM_ERATTR0 0x%08X\n", status);
-                err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
-                                        IFC_CM_ERATTR0_ERAID_SHIFT;
-                dev_err(ctrl->dev, "AXI ID of the error"
-                                        "transaction 0x%08X\n", err_axiid);
-                err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
-                                        IFC_CM_ERATTR0_ESRCID_SHIFT;
-                dev_err(ctrl->dev, "SRC ID of the error"
-                                        "transaction 0x%08X\n", err_srcid);
-                dev_err(ctrl->dev, "Transaction Address corresponding to error"
-                                        "ERADDR 0x%08X\n", err_addr);
-                ret = IRQ_HANDLED;
-        }
-        if (check_nand_stat(ctrl))
-                ret = IRQ_HANDLED;
-        return ret;
-}
-/*
- * fsl_ifc_ctrl_probe
- *
- * called by device layer when it finds a device matching
- * one our driver can handled. This code allocates all of
- * the resources needed for the controller only.  The
- * resources for the NAND banks themselves are allocated
- * in the chip probe function.
-*/
-static int fsl_ifc_ctrl_probe(struct platform_device *dev)
-{
-        int ret = 0;
-        dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
-        fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
-        if (!fsl_ifc_ctrl_dev)
-                return -ENOMEM;
-        dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
-        /* IOMAP the entire IFC region */
-        fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
-        if (!fsl_ifc_ctrl_dev->regs) {
-                dev_err(&dev->dev, "failed to get memory region\n");
-                ret = -ENODEV;
-                goto err;
-        }
-        /* get the Controller level irq */
-        fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
-        if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
-                dev_err(&dev->dev, "failed to get irq resource "
-                                                        "for IFC\n");
-                ret = -ENODEV;
-                goto err;
-        }
-        /* get the nand machine irq */
-        fsl_ifc_ctrl_dev->nand_irq =
-                        irq_of_parse_and_map(dev->dev.of_node, 1);
-        fsl_ifc_ctrl_dev->dev = &dev->dev;
-        ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
-        if (ret < 0)
-                goto err;
-        init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
-        ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
-                          "fsl-ifc", fsl_ifc_ctrl_dev);
-        if (ret != 0) {
-                dev_err(&dev->dev, "failed to install irq (%d)\n",
-                        fsl_ifc_ctrl_dev->irq);
-                goto err_irq;
-        }
-        if (fsl_ifc_ctrl_dev->nand_irq) {
-                ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
-                                0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
-                if (ret != 0) {
-                        dev_err(&dev->dev, "failed to install irq (%d)\n",
-                                fsl_ifc_ctrl_dev->nand_irq);
-                        goto err_nandirq;
-                }
-        }
-        return 0;
-err_nandirq:
-        free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
-        irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
-err_irq:
-        free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
-        irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
-err:
-        return ret;
-}
-static const struct of_device_id fsl_ifc_match[] = {
-        {
-                .compatible = "fsl,ifc",
-        },
-        {},
-};
-static struct platform_driver fsl_ifc_ctrl_driver = {
-        .driver = {
-                .name   = "fsl-ifc",
-                .of_match_table = fsl_ifc_match,
-        },
-        .probe       = fsl_ifc_ctrl_probe,
-        .remove      = fsl_ifc_ctrl_remove,
-};
-module_platform_driver(fsl_ifc_ctrl_driver);
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Freescale Semiconductor");
-MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a625dcf26b2b..3f415e252ea5 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -22,10 +22,13 @@
 #include <linux/delay.h>
 #include <linux/string.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/bootmem.h>
 #include <linux/memblock.h>
 #include <linux/log2.h>
 #include <linux/slab.h>
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
 #include <linux/uaccess.h>
 #include <asm/io.h>
@@ -868,6 +871,14 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
                pci_bus_read_config_dword(hose->bus,
                        PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
+                /*
+                 * For PEXCSRBAR, bit 3-0 indicate prefetchable and
+                 * address type. So when getting base address, these
+                 * bits should be masked
+                 */
+                base &= PCI_BASE_ADDRESS_MEM_MASK;
                return base;
        }
 #endif
@@ -1086,55 +1097,171 @@ void fsl_pci_assign_primary(void)
        }
 }
-static int fsl_pci_probe(struct platform_device *pdev)
+#ifdef CONFIG_PM_SLEEP
+static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
 {
-        int ret;
+        struct pci_controller *hose = dev_id;
-        struct device_node *node;
+        struct ccsr_pci __iomem *pci = hose->private_data;
+        u32 dr;
-        node = pdev->dev.of_node;
+        dr = in_be32(&pci->pex_pme_mes_dr);
-        ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
+        if (!dr)
+                return IRQ_NONE;
-        mpc85xx_pci_err_probe(pdev);
+        out_be32(&pci->pex_pme_mes_dr, dr);
-        return 0;
+        return IRQ_HANDLED;
 }
-#ifdef CONFIG_PM
+static int fsl_pci_pme_probe(struct pci_controller *hose)
-static int fsl_pci_resume(struct device *dev)
 {
-        struct pci_controller *hose;
+        struct ccsr_pci __iomem *pci;
-        struct resource pci_rsrc;
+        struct pci_dev *dev;
+        int pme_irq;
+        int res;
+        u16 pms;
-        hose = pci_find_hose_for_OF_device(dev->of_node);
+        /* Get hose's pci_dev */
-        if (!hose)
+        dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
-                return -ENODEV;
+        /* PME Disable */
+        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
+        pms &= ~PCI_PM_CTRL_PME_ENABLE;
+        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
+        pme_irq = irq_of_parse_and_map(hose->dn, 0);
+        if (!pme_irq) {
+                dev_err(&dev->dev, "Failed to map PME interrupt.\n");
+                return -ENXIO;
+        }
+        res = devm_request_irq(hose->parent, pme_irq,
+                        fsl_pci_pme_handle,
+                        IRQF_SHARED,
+                        "[PCI] PME", hose);
+        if (res < 0) {
+                dev_err(&dev->dev, "Unable to requiest irq %d for PME\n", pme_irq);
+                irq_dispose_mapping(pme_irq);
-        if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
-                dev_err(dev, "Get pci register base failed.");
                return -ENODEV;
        }
-        setup_pci_atmu(hose);
+        pci = hose->private_data;
+        /* Enable PTOD, ENL23D & EXL23D */
+        out_be32(&pci->pex_pme_mes_disr, 0);
+        setbits32(&pci->pex_pme_mes_disr,
+                  PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
+        out_be32(&pci->pex_pme_mes_ier, 0);
+        setbits32(&pci->pex_pme_mes_ier,
+                  PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
+        /* PME Enable */
+        pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
+        pms |= PCI_PM_CTRL_PME_ENABLE;
+        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
        return 0;
 }
-static const struct dev_pm_ops pci_pm_ops = {
+static void send_pme_turnoff_message(struct pci_controller *hose)
-        .resume = fsl_pci_resume,
+{
-};
+        struct ccsr_pci __iomem *pci = hose->private_data;
+        u32 dr;
+        int i;
-#define PCI_PM_OPS (&pci_pm_ops)
+        /* Send PME_Turn_Off Message Request */
+        setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
-#else
+        /* Wait trun off done */
+        for (i = 0; i < 150; i++) {
+                dr = in_be32(&pci->pex_pme_mes_dr);
+                if (dr) {
+                        out_be32(&pci->pex_pme_mes_dr, dr);
+                        break;
+                }
+                udelay(1000);
+        }
+}
+static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
+{
+        send_pme_turnoff_message(hose);
+}
+static int fsl_pci_syscore_suspend(void)
+{
+        struct pci_controller *hose, *tmp;
-#define PCI_PM_OPS NULL
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
+                fsl_pci_syscore_do_suspend(hose);
+        return 0;
+}
+static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
+{
+        struct ccsr_pci __iomem *pci = hose->private_data;
+        u32 dr;
+        int i;
+        /* Send Exit L2 State Message */
+        setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
+        /* Wait exit done */
+        for (i = 0; i < 150; i++) {
+                dr = in_be32(&pci->pex_pme_mes_dr);
+                if (dr) {
+                        out_be32(&pci->pex_pme_mes_dr, dr);
+                        break;
+                }
+                udelay(1000);
+        }
+        setup_pci_atmu(hose);
+}
+static void fsl_pci_syscore_resume(void)
+{
+        struct pci_controller *hose, *tmp;
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
+                fsl_pci_syscore_do_resume(hose);
+}
+static struct syscore_ops pci_syscore_pm_ops = {
+        .suspend = fsl_pci_syscore_suspend,
+        .resume = fsl_pci_syscore_resume,
+};
 #endif
+void fsl_pcibios_fixup_phb(struct pci_controller *phb)
+{
+#ifdef CONFIG_PM_SLEEP
+        fsl_pci_pme_probe(phb);
+#endif
+}
+static int fsl_pci_probe(struct platform_device *pdev)
+{
+        struct device_node *node;
+        int ret;
+        node = pdev->dev.of_node;
+        ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
+        mpc85xx_pci_err_probe(pdev);
+        return 0;
+}
 static struct platform_driver fsl_pci_driver = {
        .driver = {
                .name = "fsl-pci",
-                .pm = PCI_PM_OPS,
                .of_match_table = pci_ids,
        },
        .probe = fsl_pci_probe,
@@ -1142,6 +1269,9 @@ static struct platform_driver fsl_pci_driver = {
 static int __init fsl_pci_init(void)
 {
+#ifdef CONFIG_PM_SLEEP
+        register_syscore_ops(&pci_syscore_pm_ops);
+#endif
        return platform_driver_register(&fsl_pci_driver);
 }
 arch_initcall(fsl_pci_init);
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 8d455df58471..c1cec771d5ea 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -32,6 +32,13 @@ struct platform_device;
 #define PIWAR_WRITE_SNOOP       0x00005000
 #define PIWAR_SZ_MASK          0x0000003f
+#define PEX_PMCR_PTOMR          0x1
+#define PEX_PMCR_EXL2S          0x2
+#define PME_DISR_EN_PTOD        0x00008000
+#define PME_DISR_EN_ENL23D      0x00002000
+#define PME_DISR_EN_EXL23D      0x00001000
 /* PCI/PCI Express outbound window reg */
 struct pci_outbound_window_regs {
        __be32  potar;  /* 0x.0 - Outbound translation address register */
@@ -111,6 +118,7 @@ struct ccsr_pci {
 extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
 extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
+extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
 extern int mpc83xx_add_bridge(struct device_node *dev);
 u64 fsl_pci_immrbar_base(struct pci_controller *hose);
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 95dd892e9904..cf2b0840a672 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -531,6 +531,7 @@ int fsl_rio_setup(struct platform_device *dev)
                sprintf(port->name, "RIO mport %d", i);
                priv->dev = &dev->dev;
+                port->dev.parent = &dev->dev;
                port->ops = ops;
                port->priv = priv;
                port->phys_efptr = 0x100;
diff --git a/arch/powerpc/sysdev/msi_bitmap.c b/arch/powerpc/sysdev/msi_bitmap.c
index 0968b66b4cf9..2ff630267e9e 100644
--- a/arch/powerpc/sysdev/msi_bitmap.c
+++ b/arch/powerpc/sysdev/msi_bitmap.c
@@ -202,7 +202,7 @@ void __init test_of_node(void)
        /* There should really be a struct device_node allocator */
        memset(&of_node, 0, sizeof(of_node));
-        kref_init(&of_node.kref);
+        of_node_init(&of_node);
        of_node.full_name = node_name;
        check(0 == msi_bitmap_alloc(&bmp, size, &of_node));
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index b07909850f77..08504e75b2c7 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -171,7 +171,11 @@ extern void xmon_leave(void);
 #define REG             "%.8lx"
 #endif
+#ifdef __LITTLE_ENDIAN__
+#define GETWORD(v)      (((v)[3] << 24) + ((v)[2] << 16) + ((v)[1] << 8) + (v)[0])
+#else
 #define GETWORD(v)      (((v)[0] << 24) + ((v)[1] << 16) + ((v)[2] << 8) + (v)[3])
+#endif
 #define isxdigit(c)     (('0' <= (c) && (c) <= '9') \
                         || ('a' <= (c) && (c) <= 'f') \
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 953f17c8d17c..d68fe34799b0 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -52,7 +52,7 @@ config KEXEC
 config AUDIT_ARCH
        def_bool y
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool y
 config PCI_QUIRKS
@@ -103,6 +103,7 @@ config S390
        select GENERIC_SMP_IDLE_THREAD
        select GENERIC_TIME_VSYSCALL
        select HAVE_ALIGNED_STRUCT_PAGE if SLUB
+        select HAVE_ARCH_AUDITSYSCALL
        select HAVE_ARCH_JUMP_LABEL if !MARCH_G5
        select HAVE_ARCH_SECCOMP_FILTER
        select HAVE_ARCH_TRACEHOOK
diff --git a/arch/s390/configs/default_defconfig b/arch/s390/configs/default_defconfig
index ddaae2f5c913..8df022c43af7 100644
--- a/arch/s390/configs/default_defconfig
+++ b/arch/s390/configs/default_defconfig
@@ -581,7 +581,6 @@ CONFIG_LOCK_STAT=y
 CONFIG_DEBUG_LOCKDEP=y
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 CONFIG_DEBUG_LOCKING_API_SELFTESTS=y
-CONFIG_DEBUG_WRITECOUNT=y
 CONFIG_DEBUG_LIST=y
 CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_NOTIFIERS=y
diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h
index fa9aaf7144b7..1d4706114a45 100644
--- a/arch/s390/include/asm/atomic.h
+++ b/arch/s390/include/asm/atomic.h
@@ -15,23 +15,29 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <asm/barrier.h>
 #include <asm/cmpxchg.h>
 #define ATOMIC_INIT(i)  { (i) }
+#define __ATOMIC_NO_BARRIER     "\n"
 #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
 #define __ATOMIC_OR     "lao"
 #define __ATOMIC_AND    "lan"
 #define __ATOMIC_ADD    "laa"
+#define __ATOMIC_BARRIER "bcr   14,0\n"
-#define __ATOMIC_LOOP(ptr, op_val, op_string)                           \
+#define __ATOMIC_LOOP(ptr, op_val, op_string, __barrier)                \
 ({                                                                      \
        int old_val;                                                    \
                                                                        \
        typecheck(atomic_t *, ptr);                                     \
        asm volatile(                                                   \
+                __barrier                                               \
                op_string "     %0,%2,%1\n"                             \
+                __barrier                                               \
                : "=d" (old_val), "+Q" ((ptr)->counter)                 \
                : "d" (op_val)                                          \
                : "cc", "memory");                                      \
@@ -43,8 +49,9 @@
 #define __ATOMIC_OR     "or"
 #define __ATOMIC_AND    "nr"
 #define __ATOMIC_ADD    "ar"
+#define __ATOMIC_BARRIER "\n"
-#define __ATOMIC_LOOP(ptr, op_val, op_string)                           \
+#define __ATOMIC_LOOP(ptr, op_val, op_string, __barrier)                \
 ({                                                                      \
        int old_val, new_val;                                           \
                                                                        \
@@ -82,7 +89,7 @@ static inline void atomic_set(atomic_t *v, int i)
 static inline int atomic_add_return(int i, atomic_t *v)
 {
-        return __ATOMIC_LOOP(v, i, __ATOMIC_ADD) + i;
+        return __ATOMIC_LOOP(v, i, __ATOMIC_ADD, __ATOMIC_BARRIER) + i;
 }
 static inline void atomic_add(int i, atomic_t *v)
@@ -94,12 +101,10 @@ static inline void atomic_add(int i, atomic_t *v)
                        : "+Q" (v->counter)
                        : "i" (i)
                        : "cc", "memory");
-        } else {
+                return;
-                atomic_add_return(i, v);
        }
-#else
-        atomic_add_return(i, v);
 #endif
+        __ATOMIC_LOOP(v, i, __ATOMIC_ADD, __ATOMIC_NO_BARRIER);
 }
 #define atomic_add_negative(_i, _v)     (atomic_add_return(_i, _v) < 0)
@@ -115,12 +120,12 @@ static inline void atomic_add(int i, atomic_t *v)
 static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
 {
-        __ATOMIC_LOOP(v, ~mask, __ATOMIC_AND);
+        __ATOMIC_LOOP(v, ~mask, __ATOMIC_AND, __ATOMIC_NO_BARRIER);
 }
 static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
 {
-        __ATOMIC_LOOP(v, mask, __ATOMIC_OR);
+        __ATOMIC_LOOP(v, mask, __ATOMIC_OR, __ATOMIC_NO_BARRIER);
 }
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
@@ -157,19 +162,24 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
 #ifdef CONFIG_64BIT
+#define __ATOMIC64_NO_BARRIER   "\n"
 #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
 #define __ATOMIC64_OR   "laog"
 #define __ATOMIC64_AND  "lang"
 #define __ATOMIC64_ADD  "laag"
+#define __ATOMIC64_BARRIER "bcr 14,0\n"
-#define __ATOMIC64_LOOP(ptr, op_val, op_string)                         \
+#define __ATOMIC64_LOOP(ptr, op_val, op_string, __barrier)              \
 ({                                                                      \
        long long old_val;                                              \
                                                                        \
        typecheck(atomic64_t *, ptr);                                   \
        asm volatile(                                                   \
+                __barrier                                               \
                op_string "     %0,%2,%1\n"                             \
+                __barrier                                               \
                : "=d" (old_val), "+Q" ((ptr)->counter)                 \
                : "d" (op_val)                                          \
                : "cc", "memory");                                      \
@@ -181,8 +191,9 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
 #define __ATOMIC64_OR   "ogr"
 #define __ATOMIC64_AND  "ngr"
 #define __ATOMIC64_ADD  "agr"
+#define __ATOMIC64_BARRIER "\n"
-#define __ATOMIC64_LOOP(ptr, op_val, op_string)                         \
+#define __ATOMIC64_LOOP(ptr, op_val, op_string, __barrier)              \
 ({                                                                      \
        long long old_val, new_val;                                     \
                                                                        \
@@ -220,17 +231,32 @@ static inline void atomic64_set(atomic64_t *v, long long i)
 static inline long long atomic64_add_return(long long i, atomic64_t *v)
 {
-        return __ATOMIC64_LOOP(v, i, __ATOMIC64_ADD) + i;
+        return __ATOMIC64_LOOP(v, i, __ATOMIC64_ADD, __ATOMIC64_BARRIER) + i;
+}
+static inline void atomic64_add(long long i, atomic64_t *v)
+{
+#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
+        if (__builtin_constant_p(i) && (i > -129) && (i < 128)) {
+                asm volatile(
+                        "agsi   %0,%1\n"
+                        : "+Q" (v->counter)
+                        : "i" (i)
+                        : "cc", "memory");
+                return;
+        }
+#endif
+        __ATOMIC64_LOOP(v, i, __ATOMIC64_ADD, __ATOMIC64_NO_BARRIER);
 }
 static inline void atomic64_clear_mask(unsigned long mask, atomic64_t *v)
 {
-        __ATOMIC64_LOOP(v, ~mask, __ATOMIC64_AND);
+        __ATOMIC64_LOOP(v, ~mask, __ATOMIC64_AND, __ATOMIC64_NO_BARRIER);
 }
 static inline void atomic64_set_mask(unsigned long mask, atomic64_t *v)
 {
-        __ATOMIC64_LOOP(v, mask, __ATOMIC64_OR);
+        __ATOMIC64_LOOP(v, mask, __ATOMIC64_OR, __ATOMIC64_NO_BARRIER);
 }
 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
@@ -334,25 +360,13 @@ static inline void atomic64_clear_mask(unsigned long long mask, atomic64_t *v)
        } while (atomic64_cmpxchg(v, old, new) != old);
 }
-#endif /* CONFIG_64BIT */
 static inline void atomic64_add(long long i, atomic64_t *v)
 {
-#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
-        if (__builtin_constant_p(i) && (i > -129) && (i < 128)) {
-                asm volatile(
-                        "agsi   %0,%1\n"
-                        : "+Q" (v->counter)
-                        : "i" (i)
-                        : "cc", "memory");
-        } else {
-                atomic64_add_return(i, v);
-        }
-#else
        atomic64_add_return(i, v);
-#endif
 }
+#endif /* CONFIG_64BIT */
 static inline int atomic64_add_unless(atomic64_t *v, long long i, long long u)
 {
        long long c, old;
diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h
index ec5ef891db6b..520542477678 100644
--- a/arch/s390/include/asm/bitops.h
+++ b/arch/s390/include/asm/bitops.h
@@ -47,14 +47,18 @@
 #include <linux/typecheck.h>
 #include <linux/compiler.h>
+#include <asm/barrier.h>
+#define __BITOPS_NO_BARRIER     "\n"
 #ifndef CONFIG_64BIT
 #define __BITOPS_OR             "or"
 #define __BITOPS_AND            "nr"
 #define __BITOPS_XOR            "xr"
+#define __BITOPS_BARRIER        "\n"
-#define __BITOPS_LOOP(__addr, __val, __op_string)               \
+#define __BITOPS_LOOP(__addr, __val, __op_string, __barrier)    \
 ({                                                              \
        unsigned long __old, __new;                             \
                                                                \
@@ -67,7 +71,7 @@
                "       jl      0b"                             \
                : "=&d" (__old), "=&d" (__new), "+Q" (*(__addr))\
                : "d" (__val)                                   \
-                : "cc");                                        \
+                : "cc", "memory");                              \
        __old;                                                  \
 })
@@ -78,17 +82,20 @@
 #define __BITOPS_OR             "laog"
 #define __BITOPS_AND            "lang"
 #define __BITOPS_XOR            "laxg"
+#define __BITOPS_BARRIER        "bcr    14,0\n"
-#define __BITOPS_LOOP(__addr, __val, __op_string)               \
+#define __BITOPS_LOOP(__addr, __val, __op_string, __barrier)    \
 ({                                                              \
        unsigned long __old;                                    \
                                                                \
        typecheck(unsigned long *, (__addr));                   \
        asm volatile(                                           \
+                __barrier                                       \
                __op_string "   %0,%2,%1\n"                     \
+                __barrier                                       \
                : "=d" (__old), "+Q" (*(__addr))                \
                : "d" (__val)                                   \
-                : "cc");                                        \
+                : "cc", "memory");                              \
        __old;                                                  \
 })
@@ -97,8 +104,9 @@
 #define __BITOPS_OR             "ogr"
 #define __BITOPS_AND            "ngr"
 #define __BITOPS_XOR            "xgr"
+#define __BITOPS_BARRIER        "\n"
-#define __BITOPS_LOOP(__addr, __val, __op_string)               \
+#define __BITOPS_LOOP(__addr, __val, __op_string, __barrier)    \
 ({                                                              \
        unsigned long __old, __new;                             \
                                                                \
@@ -111,7 +119,7 @@
                "       jl      0b"                             \
                : "=&d" (__old), "=&d" (__new), "+Q" (*(__addr))\
                : "d" (__val)                                   \
-                : "cc");                                        \
+                : "cc", "memory");                              \
        __old;                                                  \
 })
@@ -149,12 +157,12 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *ptr)
                        "oi     %0,%b1\n"
                        : "+Q" (*caddr)
                        : "i" (1 << (nr & 7))
-                        : "cc");
+                        : "cc", "memory");
                return;
        }
 #endif
        mask = 1UL << (nr & (BITS_PER_LONG - 1));
-        __BITOPS_LOOP(addr, mask, __BITOPS_OR);
+        __BITOPS_LOOP(addr, mask, __BITOPS_OR, __BITOPS_NO_BARRIER);
 }
 static inline void clear_bit(unsigned long nr, volatile unsigned long *ptr)
@@ -170,12 +178,12 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *ptr)
                        "ni     %0,%b1\n"
                        : "+Q" (*caddr)
                        : "i" (~(1 << (nr & 7)))
-                        : "cc");
+                        : "cc", "memory");
                return;
        }
 #endif
        mask = ~(1UL << (nr & (BITS_PER_LONG - 1)));
-        __BITOPS_LOOP(addr, mask, __BITOPS_AND);
+        __BITOPS_LOOP(addr, mask, __BITOPS_AND, __BITOPS_NO_BARRIER);
 }
 static inline void change_bit(unsigned long nr, volatile unsigned long *ptr)
@@ -191,12 +199,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *ptr)
                        "xi     %0,%b1\n"
                        : "+Q" (*caddr)
                        : "i" (1 << (nr & 7))
-                        : "cc");
+                        : "cc", "memory");
                return;
        }
 #endif
        mask = 1UL << (nr & (BITS_PER_LONG - 1));
-        __BITOPS_LOOP(addr, mask, __BITOPS_XOR);
+        __BITOPS_LOOP(addr, mask, __BITOPS_XOR, __BITOPS_NO_BARRIER);
 }
 static inline int
@@ -206,8 +214,7 @@ test_and_set_bit(unsigned long nr, volatile unsigned long *ptr)
        unsigned long old, mask;
        mask = 1UL << (nr & (BITS_PER_LONG - 1));
-        old = __BITOPS_LOOP(addr, mask, __BITOPS_OR);
+        old = __BITOPS_LOOP(addr, mask, __BITOPS_OR, __BITOPS_BARRIER);
-        barrier();
        return (old & mask) != 0;
 }
@@ -218,8 +225,7 @@ test_and_clear_bit(unsigned long nr, volatile unsigned long *ptr)
        unsigned long old, mask;
        mask = ~(1UL << (nr & (BITS_PER_LONG - 1)));
-        old = __BITOPS_LOOP(addr, mask, __BITOPS_AND);
+        old = __BITOPS_LOOP(addr, mask, __BITOPS_AND, __BITOPS_BARRIER);
-        barrier();
        return (old & ~mask) != 0;
 }
@@ -230,8 +236,7 @@ test_and_change_bit(unsigned long nr, volatile unsigned long *ptr)
        unsigned long old, mask;
        mask = 1UL << (nr & (BITS_PER_LONG - 1));
-        old = __BITOPS_LOOP(addr, mask, __BITOPS_XOR);
+        old = __BITOPS_LOOP(addr, mask, __BITOPS_XOR, __BITOPS_BARRIER);
-        barrier();
        return (old & mask) != 0;
 }
diff --git a/arch/s390/include/asm/ccwgroup.h b/arch/s390/include/asm/ccwgroup.h
index 23723ce5ca7a..6e670f88d125 100644
--- a/arch/s390/include/asm/ccwgroup.h
+++ b/arch/s390/include/asm/ccwgroup.h
@@ -23,6 +23,7 @@ struct ccwgroup_device {
        unsigned int count;
        struct device   dev;
        struct ccw_device *cdev[0];
+        struct work_struct ungroup_work;
 };
 /**
diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h
index d42625053c37..096339207764 100644
--- a/arch/s390/include/asm/cio.h
+++ b/arch/s390/include/asm/cio.h
@@ -199,7 +199,7 @@ struct esw_eadm {
 /**
 * struct irb - interruption response block
 * @scsw: subchannel status word
- * @esw: extened status word
+ * @esw: extended status word
 * @ecw: extended control word
 *
 * The irb that is handed to the device driver when an interrupt occurs. For
diff --git a/arch/s390/include/asm/futex.h b/arch/s390/include/asm/futex.h
index fda46bd38c99..69cf5b5eddc9 100644
--- a/arch/s390/include/asm/futex.h
+++ b/arch/s390/include/asm/futex.h
@@ -1,12 +1,25 @@
 #ifndef _ASM_S390_FUTEX_H
 #define _ASM_S390_FUTEX_H
-#include <linux/futex.h>
 #include <linux/uaccess.h>
+#include <linux/futex.h>
+#include <asm/mmu_context.h>
 #include <asm/errno.h>
-int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval);
+#define __futex_atomic_op(insn, ret, oldval, newval, uaddr, oparg)      \
-int __futex_atomic_op_inuser(int op, u32 __user *uaddr, int oparg, int *old);
+        asm volatile(                                                   \
+                "   sacf  256\n"                                        \
+                "0: l     %1,0(%6)\n"                                   \
+                "1:"insn                                                \
+                "2: cs    %1,%2,0(%6)\n"                                \
+                "3: jl    1b\n"                                         \
+                "   lhi   %0,0\n"                                       \
+                "4: sacf  768\n"                                        \
+                EX_TABLE(0b,4b) EX_TABLE(2b,4b) EX_TABLE(3b,4b)         \
+                : "=d" (ret), "=&d" (oldval), "=&d" (newval),           \
+                  "=m" (*uaddr)                                         \
+                : "0" (-EFAULT), "d" (oparg), "a" (uaddr),              \
+                  "m" (*uaddr) : "cc");
 static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
 {
@@ -14,13 +27,37 @@ static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
        int cmp = (encoded_op >> 24) & 15;
        int oparg = (encoded_op << 8) >> 20;
        int cmparg = (encoded_op << 20) >> 20;
-        int oldval, ret;
+        int oldval = 0, newval, ret;
+        update_primary_asce(current);
        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
                oparg = 1 << oparg;
        pagefault_disable();
-        ret = __futex_atomic_op_inuser(op, uaddr, oparg, &oldval);
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op("lr %2,%5\n",
+                                  ret, oldval, newval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ADD:
+                __futex_atomic_op("lr %2,%1\nar %2,%5\n",
+                                  ret, oldval, newval, uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op("lr %2,%1\nor %2,%5\n",
+                                  ret, oldval, newval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op("lr %2,%1\nnr %2,%5\n",
+                                  ret, oldval, newval, uaddr, oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op("lr %2,%1\nxr %2,%5\n",
+                                  ret, oldval, newval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
        pagefault_enable();
        if (!ret) {
@@ -37,4 +74,23 @@ static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
        return ret;
 }
+static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+                                                u32 oldval, u32 newval)
+{
+        int ret;
+        update_primary_asce(current);
+        asm volatile(
+                "   sacf 256\n"
+                "0: cs   %1,%4,0(%5)\n"
+                "1: la   %0,0\n"
+                "2: sacf 768\n"
+                EX_TABLE(0b,2b) EX_TABLE(1b,2b)
+                : "=d" (ret), "+d" (oldval), "=m" (*uaddr)
+                : "0" (-EFAULT), "d" (newval), "a" (uaddr), "m" (*uaddr)
+                : "cc", "memory");
+        *uval = oldval;
+        return ret;
+}
 #endif /* _ASM_S390_FUTEX_H */
diff --git a/arch/s390/include/asm/irq.h b/arch/s390/include/asm/irq.h
index 5f8bcc5fe423..c4dd400a2791 100644
--- a/arch/s390/include/asm/irq.h
+++ b/arch/s390/include/asm/irq.h
@@ -16,6 +16,20 @@
 /* This number is used when no interrupt has been assigned */
 #define NO_IRQ          0
+/* External interruption codes */
+#define EXT_IRQ_INTERRUPT_KEY   0x0040
+#define EXT_IRQ_CLK_COMP        0x1004
+#define EXT_IRQ_CPU_TIMER       0x1005
+#define EXT_IRQ_WARNING_TRACK   0x1007
+#define EXT_IRQ_MALFUNC_ALERT   0x1200
+#define EXT_IRQ_EMERGENCY_SIG   0x1201
+#define EXT_IRQ_EXTERNAL_CALL   0x1202
+#define EXT_IRQ_TIMING_ALERT    0x1406
+#define EXT_IRQ_MEASURE_ALERT   0x1407
+#define EXT_IRQ_SERVICE_SIG     0x2401
+#define EXT_IRQ_CP_SERVICE      0x2603
+#define EXT_IRQ_IUCV            0x4000
 #ifndef __ASSEMBLY__
 #include <linux/hardirq.h>
@@ -53,6 +67,7 @@ enum interruption_class {
        IRQIO_PCI,
        IRQIO_MSI,
        IRQIO_VIR,
+        IRQIO_VAI,
        NMI_NMI,
        CPU_RST,
        NR_ARCH_IRQS
@@ -76,8 +91,8 @@ struct ext_code {
 typedef void (*ext_int_handler_t)(struct ext_code, unsigned int, unsigned long);
-int register_external_interrupt(u16 code, ext_int_handler_t handler);
+int register_external_irq(u16 code, ext_int_handler_t handler);
-int unregister_external_interrupt(u16 code, ext_int_handler_t handler);
+int unregister_external_irq(u16 code, ext_int_handler_t handler);
 enum irq_subclass {
        IRQ_SUBCLASS_MEASUREMENT_ALERT = 5,
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index 9bf95bb30f1a..154b60089be9 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -16,12 +16,22 @@
 #include <linux/hrtimer.h>
 #include <linux/interrupt.h>
 #include <linux/kvm_host.h>
+#include <linux/kvm.h>
 #include <asm/debug.h>
 #include <asm/cpu.h>
+#include <asm/isc.h>
 #define KVM_MAX_VCPUS 64
 #define KVM_USER_MEM_SLOTS 32
+/*
+ * These seem to be used for allocating ->chip in the routing table,
+ * which we don't use. 4096 is an out-of-thin-air value. If we need
+ * to look at ->chip later on, we'll need to revisit this.
+ */
+#define KVM_NR_IRQCHIPS 1
+#define KVM_IRQCHIP_NUM_PINS 4096
 struct sca_entry {
        atomic_t scn;
        __u32   reserved;
@@ -108,7 +118,9 @@ struct kvm_s390_sie_block {
        __u32   fac;                    /* 0x01a0 */
        __u8    reserved1a4[20];        /* 0x01a4 */
        __u64   cbrlo;                  /* 0x01b8 */
-        __u8    reserved1c0[40];        /* 0x01c0 */
+        __u8    reserved1c0[30];        /* 0x01c0 */
+        __u64   pp;                     /* 0x01de */
+        __u8    reserved1e6[2];         /* 0x01e6 */
        __u64   itdba;                  /* 0x01e8 */
        __u8    reserved1f0[16];        /* 0x01f0 */
 } __attribute__((packed));
@@ -171,18 +183,6 @@ struct kvm_vcpu_stat {
        u32 diagnose_9c;
 };
-struct kvm_s390_io_info {
-        __u16        subchannel_id;            /* 0x0b8 */
-        __u16        subchannel_nr;            /* 0x0ba */
-        __u32        io_int_parm;              /* 0x0bc */
-        __u32        io_int_word;              /* 0x0c0 */
-};
-struct kvm_s390_ext_info {
-        __u32 ext_params;
-        __u64 ext_params2;
-};
 #define PGM_OPERATION            0x01
 #define PGM_PRIVILEGED_OP        0x02
 #define PGM_EXECUTE              0x03
@@ -191,27 +191,6 @@ struct kvm_s390_ext_info {
 #define PGM_SPECIFICATION        0x06
 #define PGM_DATA                 0x07
-struct kvm_s390_pgm_info {
-        __u16 code;
-};
-struct kvm_s390_prefix_info {
-        __u32 address;
-};
-struct kvm_s390_extcall_info {
-        __u16 code;
-};
-struct kvm_s390_emerg_info {
-        __u16 code;
-};
-struct kvm_s390_mchk_info {
-        __u64 cr14;
-        __u64 mcic;
-};
 struct kvm_s390_interrupt_info {
        struct list_head list;
        u64     type;
@@ -246,9 +225,8 @@ struct kvm_s390_float_interrupt {
        struct list_head list;
        atomic_t active;
        int next_rr_cpu;
-        unsigned long idle_mask[(KVM_MAX_VCPUS + sizeof(long) - 1)
+        unsigned long idle_mask[BITS_TO_LONGS(KVM_MAX_VCPUS)];
-                                / sizeof(long)];
+        unsigned int irq_count;
-        struct kvm_s390_local_interrupt *local_int[KVM_MAX_VCPUS];
 };
@@ -265,6 +243,10 @@ struct kvm_vcpu_arch {
                u64             stidp_data;
        };
        struct gmap *gmap;
+#define KVM_S390_PFAULT_TOKEN_INVALID   (-1UL)
+        unsigned long pfault_token;
+        unsigned long pfault_select;
+        unsigned long pfault_compare;
 };
 struct kvm_vm_stat {
@@ -274,12 +256,36 @@ struct kvm_vm_stat {
 struct kvm_arch_memory_slot {
 };
+struct s390_map_info {
+        struct list_head list;
+        __u64 guest_addr;
+        __u64 addr;
+        struct page *page;
+};
+struct s390_io_adapter {
+        unsigned int id;
+        int isc;
+        bool maskable;
+        bool masked;
+        bool swap;
+        struct rw_semaphore maps_lock;
+        struct list_head maps;
+        atomic_t nr_maps;
+};
+#define MAX_S390_IO_ADAPTERS ((MAX_ISC + 1) * 8)
+#define MAX_S390_ADAPTER_MAPS 256
 struct kvm_arch{
        struct sca_block *sca;
        debug_info_t *dbf;
        struct kvm_s390_float_interrupt float_int;
+        struct kvm_device *flic;
        struct gmap *gmap;
        int css_support;
+        int use_irqchip;
+        struct s390_io_adapter *adapters[MAX_S390_IO_ADAPTERS];
 };
 #define KVM_HVA_ERR_BAD         (-1UL)
@@ -290,6 +296,24 @@ static inline bool kvm_is_error_hva(unsigned long addr)
        return IS_ERR_VALUE(addr);
 }
+#define ASYNC_PF_PER_VCPU       64
+struct kvm_vcpu;
+struct kvm_async_pf;
+struct kvm_arch_async_pf {
+        unsigned long pfault_token;
+};
+bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu);
+void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
+                               struct kvm_async_pf *work);
+void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
+                                     struct kvm_async_pf *work);
+void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
+                                 struct kvm_async_pf *work);
 extern int sie64a(struct kvm_s390_sie_block *, u64 *);
 extern char sie_exit;
 #endif
diff --git a/arch/s390/include/asm/mmu.h b/arch/s390/include/asm/mmu.h
index ff132ac64ddd..f77695a82f64 100644
--- a/arch/s390/include/asm/mmu.h
+++ b/arch/s390/include/asm/mmu.h
@@ -1,9 +1,11 @@
 #ifndef __MMU_H
 #define __MMU_H
+#include <linux/cpumask.h>
 #include <linux/errno.h>
 typedef struct {
+        cpumask_t cpu_attach_mask;
        atomic_t attach_count;
        unsigned int flush_mm;
        spinlock_t list_lock;
diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h
index 38149b63dc44..71be346d0e3c 100644
--- a/arch/s390/include/asm/mmu_context.h
+++ b/arch/s390/include/asm/mmu_context.h
@@ -15,6 +15,7 @@
 static inline int init_new_context(struct task_struct *tsk,
                                   struct mm_struct *mm)
 {
+        cpumask_clear(&mm->context.cpu_attach_mask);
        atomic_set(&mm->context.attach_count, 0);
        mm->context.flush_mm = 0;
        mm->context.asce_bits = _ASCE_TABLE_LENGTH | _ASCE_USER_BITS;
@@ -29,41 +30,61 @@ static inline int init_new_context(struct task_struct *tsk,
 #define destroy_context(mm)             do { } while (0)
-#ifndef CONFIG_64BIT
+static inline void update_user_asce(struct mm_struct *mm, int load_primary)
-#define LCTL_OPCODE "lctl"
-#else
-#define LCTL_OPCODE "lctlg"
-#endif
-static inline void update_mm(struct mm_struct *mm, struct task_struct *tsk)
 {
        pgd_t *pgd = mm->pgd;
        S390_lowcore.user_asce = mm->context.asce_bits | __pa(pgd);
-        /* Load primary space page table origin. */
+        if (load_primary)
-        asm volatile(LCTL_OPCODE" 1,1,%0\n" : : "m" (S390_lowcore.user_asce));
+                __ctl_load(S390_lowcore.user_asce, 1, 1);
        set_fs(current->thread.mm_segment);
 }
+static inline void clear_user_asce(struct mm_struct *mm, int load_primary)
+{
+        S390_lowcore.user_asce = S390_lowcore.kernel_asce;
+        if (load_primary)
+                __ctl_load(S390_lowcore.user_asce, 1, 1);
+        __ctl_load(S390_lowcore.user_asce, 7, 7);
+}
+static inline void update_primary_asce(struct task_struct *tsk)
+{
+        unsigned long asce;
+        __ctl_store(asce, 1, 1);
+        if (asce != S390_lowcore.kernel_asce)
+                __ctl_load(S390_lowcore.kernel_asce, 1, 1);
+        set_tsk_thread_flag(tsk, TIF_ASCE);
+}
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                             struct task_struct *tsk)
 {
        int cpu = smp_processor_id();
+        update_primary_asce(tsk);
        if (prev == next)
                return;
+        if (MACHINE_HAS_TLB_LC)
+                cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
        if (atomic_inc_return(&next->context.attach_count) >> 16) {
-                /* Delay update_mm until all TLB flushes are done. */
+                /* Delay update_user_asce until all TLB flushes are done. */
                set_tsk_thread_flag(tsk, TIF_TLB_WAIT);
+                /* Clear old ASCE by loading the kernel ASCE. */
+                clear_user_asce(next, 0);
        } else {
                cpumask_set_cpu(cpu, mm_cpumask(next));
-                update_mm(next, tsk);
+                update_user_asce(next, 0);
                if (next->context.flush_mm)
                        /* Flush pending TLBs */
                        __tlb_flush_mm(next);
        }
        atomic_dec(&prev->context.attach_count);
        WARN_ON(atomic_read(&prev->context.attach_count) < 0);
+        if (MACHINE_HAS_TLB_LC)
+                cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
 }
 #define finish_arch_post_lock_switch finish_arch_post_lock_switch
@@ -80,7 +101,7 @@ static inline void finish_arch_post_lock_switch(void)
                cpu_relax();
        cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
-        update_mm(mm, tsk);
+        update_user_asce(mm, 0);
        if (mm->context.flush_mm)
                __tlb_flush_mm(mm);
        preempt_enable();
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 1ab75eaacbd4..12f75313e086 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -782,6 +782,7 @@ static inline void pgste_set_pte(pte_t *ptep, pte_t entry)
 * @table: pointer to the page directory
 * @asce: address space control element for gmap page table
 * @crst_list: list of all crst tables used in the guest address space
+ * @pfault_enabled: defines if pfaults are applicable for the guest
 */
 struct gmap {
        struct list_head list;
@@ -790,6 +791,7 @@ struct gmap {
        unsigned long asce;
        void *private;
        struct list_head crst_list;
+        bool pfault_enabled;
 };
 /**
@@ -1068,12 +1070,35 @@ static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
                : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
 }
+static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep)
+{
+        unsigned long pto = (unsigned long) ptep;
+#ifndef CONFIG_64BIT
+        /* pto in ESA mode must point to the start of the segment table */
+        pto &= 0x7ffffc00;
+#endif
+        /* Invalidation + local TLB flush for the pte */
+        asm volatile(
+                "       .insn rrf,0xb2210000,%2,%3,0,1"
+                : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
+}
 static inline void ptep_flush_direct(struct mm_struct *mm,
                                     unsigned long address, pte_t *ptep)
 {
+        int active, count;
        if (pte_val(*ptep) & _PAGE_INVALID)
                return;
-        __ptep_ipte(address, ptep);
+        active = (mm == current->active_mm) ? 1 : 0;
+        count = atomic_add_return(0x10000, &mm->context.attach_count);
+        if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
+            cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
+                __ptep_ipte_local(address, ptep);
+        else
+                __ptep_ipte(address, ptep);
+        atomic_sub(0x10000, &mm->context.attach_count);
 }
 static inline void ptep_flush_lazy(struct mm_struct *mm,
@@ -1382,35 +1407,6 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
 #define pte_unmap(pte) do { } while (0)
-static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
-{
-        unsigned long sto = (unsigned long) pmdp -
-                            pmd_index(address) * sizeof(pmd_t);
-        if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)) {
-                asm volatile(
-                        "       .insn   rrf,0xb98e0000,%2,%3,0,0"
-                        : "=m" (*pmdp)
-                        : "m" (*pmdp), "a" (sto),
-                          "a" ((address & HPAGE_MASK))
-                        : "cc"
-                );
-        }
-}
-static inline void __pmd_csp(pmd_t *pmdp)
-{
-        register unsigned long reg2 asm("2") = pmd_val(*pmdp);
-        register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
-                                               _SEGMENT_ENTRY_INVALID;
-        register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
-        asm volatile(
-                "       csp %1,%3"
-                : "=m" (*pmdp)
-                : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
-}
 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
 {
@@ -1479,18 +1475,80 @@ static inline pmd_t pmd_mkwrite(pmd_t pmd)
 }
 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
+static inline void __pmdp_csp(pmd_t *pmdp)
+{
+        register unsigned long reg2 asm("2") = pmd_val(*pmdp);
+        register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
+                                               _SEGMENT_ENTRY_INVALID;
+        register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
+        asm volatile(
+                "       csp %1,%3"
+                : "=m" (*pmdp)
+                : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
+}
+static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp)
+{
+        unsigned long sto;
+        sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
+        asm volatile(
+                "       .insn   rrf,0xb98e0000,%2,%3,0,0"
+                : "=m" (*pmdp)
+                : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
+                : "cc" );
+}
+static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp)
+{
+        unsigned long sto;
+        sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
+        asm volatile(
+                "       .insn   rrf,0xb98e0000,%2,%3,0,1"
+                : "=m" (*pmdp)
+                : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
+                : "cc" );
+}
+static inline void pmdp_flush_direct(struct mm_struct *mm,
+                                     unsigned long address, pmd_t *pmdp)
+{
+        int active, count;
+        if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
+                return;
+        if (!MACHINE_HAS_IDTE) {
+                __pmdp_csp(pmdp);
+                return;
+        }
+        active = (mm == current->active_mm) ? 1 : 0;
+        count = atomic_add_return(0x10000, &mm->context.attach_count);
+        if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
+            cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
+                __pmdp_idte_local(address, pmdp);
+        else
+                __pmdp_idte(address, pmdp);
+        atomic_sub(0x10000, &mm->context.attach_count);
+}
 static inline void pmdp_flush_lazy(struct mm_struct *mm,
                                   unsigned long address, pmd_t *pmdp)
 {
        int active, count;
+        if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
+                return;
        active = (mm == current->active_mm) ? 1 : 0;
        count = atomic_add_return(0x10000, &mm->context.attach_count);
        if ((count & 0xffff) <= active) {
                pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID;
                mm->context.flush_mm = 1;
-        } else
+        } else if (MACHINE_HAS_IDTE)
-                __pmd_idte(address, pmdp);
+                __pmdp_idte(address, pmdp);
+        else
+                __pmdp_csp(pmdp);
        atomic_sub(0x10000, &mm->context.attach_count);
 }
@@ -1543,7 +1601,7 @@ static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
        pmd_t pmd;
        pmd = *pmdp;
-        __pmd_idte(address, pmdp);
+        pmdp_flush_direct(vma->vm_mm, address, pmdp);
        *pmdp = pmd_mkold(pmd);
        return pmd_young(pmd);
 }
@@ -1554,7 +1612,7 @@ static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
 {
        pmd_t pmd = *pmdp;
-        __pmd_idte(address, pmdp);
+        pmdp_flush_direct(mm, address, pmdp);
        pmd_clear(pmdp);
        return pmd;
 }
@@ -1570,7 +1628,7 @@ static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
 static inline void pmdp_invalidate(struct vm_area_struct *vma,
                                   unsigned long address, pmd_t *pmdp)
 {
-        __pmd_idte(address, pmdp);
+        pmdp_flush_direct(vma->vm_mm, address, pmdp);
 }
 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
@@ -1580,7 +1638,7 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm,
        pmd_t pmd = *pmdp;
        if (pmd_write(pmd)) {
-                __pmd_idte(address, pmdp);
+                pmdp_flush_direct(mm, address, pmdp);
                set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
        }
 }
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index 0a876bc543d3..dc5fc4f90e52 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -79,6 +79,7 @@ struct thread_struct {
        unsigned long ksp;              /* kernel stack pointer             */
        mm_segment_t mm_segment;
        unsigned long gmap_addr;        /* address of last gmap fault. */
+        unsigned int gmap_pfault;       /* signal of a pending guest pfault */
        struct per_regs per_user;       /* User specified PER registers */
        struct per_event per_event;     /* Cause of the last PER trap */
        unsigned long per_flags;        /* Flags to control debug behavior */
diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h
index 406f3a1e63ef..b31b22dba948 100644
--- a/arch/s390/include/asm/setup.h
+++ b/arch/s390/include/asm/setup.h
@@ -68,6 +68,7 @@ void create_mem_hole(struct mem_chunk mem_chunk[], unsigned long addr,
 #define MACHINE_FLAG_TOPOLOGY   (1UL << 14)
 #define MACHINE_FLAG_TE         (1UL << 15)
 #define MACHINE_FLAG_RRBM       (1UL << 16)
+#define MACHINE_FLAG_TLB_LC     (1UL << 17)
 #define MACHINE_IS_VM           (S390_lowcore.machine_flags & MACHINE_FLAG_VM)
 #define MACHINE_IS_KVM          (S390_lowcore.machine_flags & MACHINE_FLAG_KVM)
@@ -90,6 +91,7 @@ void create_mem_hole(struct mem_chunk mem_chunk[], unsigned long addr,
 #define MACHINE_HAS_TOPOLOGY    (0)
 #define MACHINE_HAS_TE          (0)
 #define MACHINE_HAS_RRBM        (0)
+#define MACHINE_HAS_TLB_LC      (0)
 #else /* CONFIG_64BIT */
 #define MACHINE_HAS_IEEE        (1)
 #define MACHINE_HAS_CSP         (1)
@@ -102,6 +104,7 @@ void create_mem_hole(struct mem_chunk mem_chunk[], unsigned long addr,
 #define MACHINE_HAS_TOPOLOGY    (S390_lowcore.machine_flags & MACHINE_FLAG_TOPOLOGY)
 #define MACHINE_HAS_TE          (S390_lowcore.machine_flags & MACHINE_FLAG_TE)
 #define MACHINE_HAS_RRBM        (S390_lowcore.machine_flags & MACHINE_FLAG_RRBM)
+#define MACHINE_HAS_TLB_LC      (S390_lowcore.machine_flags & MACHINE_FLAG_TLB_LC)
 #endif /* CONFIG_64BIT */
 /*
diff --git a/arch/s390/include/asm/switch_to.h b/arch/s390/include/asm/switch_to.h
index 29c81f82705e..e759181357fc 100644
--- a/arch/s390/include/asm/switch_to.h
+++ b/arch/s390/include/asm/switch_to.h
@@ -132,6 +132,7 @@ static inline void restore_access_regs(unsigned int *acrs)
                update_cr_regs(next);                                   \
        }                                                               \
        prev = __switch_to(prev,next);                                  \
+        update_primary_asce(current);                                   \
 } while (0)
 #define finish_arch_switch(prev) do {                                        \
diff --git a/arch/s390/include/asm/syscall.h b/arch/s390/include/asm/syscall.h
index cd29d2f4e4f3..777687055e7b 100644
--- a/arch/s390/include/asm/syscall.h
+++ b/arch/s390/include/asm/syscall.h
@@ -12,7 +12,7 @@
 #ifndef _ASM_SYSCALL_H
 #define _ASM_SYSCALL_H  1
-#include <linux/audit.h>
+#include <uapi/linux/audit.h>
 #include <linux/sched.h>
 #include <linux/err.h>
 #include <asm/ptrace.h>
@@ -89,11 +89,10 @@ static inline void syscall_set_arguments(struct task_struct *task,
                regs->orig_gpr2 = args[0];
 }
-static inline int syscall_get_arch(struct task_struct *task,
+static inline int syscall_get_arch(void)
-                                   struct pt_regs *regs)
 {
 #ifdef CONFIG_COMPAT
-        if (test_tsk_thread_flag(task, TIF_31BIT))
+        if (test_tsk_thread_flag(current, TIF_31BIT))
                return AUDIT_ARCH_S390;
 #endif
        return sizeof(long) == 8 ? AUDIT_ARCH_S390X : AUDIT_ARCH_S390;
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
index 3ccd71b90345..50630e6a35de 100644
--- a/arch/s390/include/asm/thread_info.h
+++ b/arch/s390/include/asm/thread_info.h
@@ -82,6 +82,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_SIGPENDING          2       /* signal pending */
 #define TIF_NEED_RESCHED        3       /* rescheduling necessary */
 #define TIF_TLB_WAIT            4       /* wait for TLB flush completion */
+#define TIF_ASCE                5       /* primary asce needs fixup / uaccess */
 #define TIF_PER_TRAP            6       /* deliver sigtrap on return to user */
 #define TIF_MCCK_PENDING        7       /* machine check handling is pending */
 #define TIF_SYSCALL_TRACE       8       /* syscall trace active */
@@ -99,6 +100,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_TLB_WAIT           (1<<TIF_TLB_WAIT)
+#define _TIF_ASCE               (1<<TIF_ASCE)
 #define _TIF_PER_TRAP           (1<<TIF_PER_TRAP)
 #define _TIF_MCCK_PENDING       (1<<TIF_MCCK_PENDING)
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
diff --git a/arch/s390/include/asm/tlb.h b/arch/s390/include/asm/tlb.h
index 2cb846c4b37f..c544b6f05d95 100644
--- a/arch/s390/include/asm/tlb.h
+++ b/arch/s390/include/asm/tlb.h
@@ -57,8 +57,6 @@ static inline void tlb_gather_mmu(struct mmu_gather *tlb,
        tlb->end = end;
        tlb->fullmm = !(start | (end+1));
        tlb->batch = NULL;
-        if (tlb->fullmm)
-                __tlb_flush_mm(mm);
 }
 static inline void tlb_flush_mmu(struct mmu_gather *tlb)
@@ -96,9 +94,7 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
                                unsigned long address)
 {
-        if (!tlb->fullmm)
+        page_table_free_rcu(tlb, (unsigned long *) pte);
-                return page_table_free_rcu(tlb, (unsigned long *) pte);
-        page_table_free(tlb->mm, (unsigned long *) pte);
 }
 /*
@@ -114,9 +110,7 @@ static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
 #ifdef CONFIG_64BIT
        if (tlb->mm->context.asce_limit <= (1UL << 31))
                return;
-        if (!tlb->fullmm)
+        tlb_remove_table(tlb, pmd);
-                return tlb_remove_table(tlb, pmd);
-        crst_table_free(tlb->mm, (unsigned long *) pmd);
 #endif
 }
@@ -133,9 +127,7 @@ static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
 #ifdef CONFIG_64BIT
        if (tlb->mm->context.asce_limit <= (1UL << 42))
                return;
-        if (!tlb->fullmm)
+        tlb_remove_table(tlb, pud);
-                return tlb_remove_table(tlb, pud);
-        crst_table_free(tlb->mm, (unsigned long *) pud);
 #endif
 }
diff --git a/arch/s390/include/asm/tlbflush.h b/arch/s390/include/asm/tlbflush.h
index f9fef0425fee..16c9c88658c8 100644
--- a/arch/s390/include/asm/tlbflush.h
+++ b/arch/s390/include/asm/tlbflush.h
@@ -7,19 +7,41 @@
 #include <asm/pgalloc.h>
 /*
- * Flush all tlb entries on the local cpu.
+ * Flush all TLB entries on the local CPU.
 */
 static inline void __tlb_flush_local(void)
 {
        asm volatile("ptlb" : : : "memory");
 }
-#ifdef CONFIG_SMP
 /*
- * Flush all tlb entries on all cpus.
+ * Flush TLB entries for a specific ASCE on all CPUs
 */
+static inline void __tlb_flush_idte(unsigned long asce)
+{
+        /* Global TLB flush for the mm */
+        asm volatile(
+                "       .insn   rrf,0xb98e0000,0,%0,%1,0"
+                : : "a" (2048), "a" (asce) : "cc");
+}
+/*
+ * Flush TLB entries for a specific ASCE on the local CPU
+ */
+static inline void __tlb_flush_idte_local(unsigned long asce)
+{
+        /* Local TLB flush for the mm */
+        asm volatile(
+                "       .insn   rrf,0xb98e0000,0,%0,%1,1"
+                : : "a" (2048), "a" (asce) : "cc");
+}
+#ifdef CONFIG_SMP
 void smp_ptlb_all(void);
+/*
+ * Flush all TLB entries on all CPUs.
+ */
 static inline void __tlb_flush_global(void)
 {
        register unsigned long reg2 asm("2");
@@ -42,36 +64,89 @@ static inline void __tlb_flush_global(void)
                : : "d" (reg2), "d" (reg3), "d" (reg4), "m" (dummy) : "cc" );
 }
+/*
+ * Flush TLB entries for a specific mm on all CPUs (in case gmap is used
+ * this implicates multiple ASCEs!).
+ */
 static inline void __tlb_flush_full(struct mm_struct *mm)
 {
-        cpumask_t local_cpumask;
        preempt_disable();
-        /*
+        atomic_add(0x10000, &mm->context.attach_count);
-         * If the process only ran on the local cpu, do a local flush.
+        if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
-         */
+                /* Local TLB flush */
-        cpumask_copy(&local_cpumask, cpumask_of(smp_processor_id()));
-        if (cpumask_equal(mm_cpumask(mm), &local_cpumask))
                __tlb_flush_local();
-        else
+        } else {
+                /* Global TLB flush */
                __tlb_flush_global();
+                /* Reset TLB flush mask */
+                if (MACHINE_HAS_TLB_LC)
+                        cpumask_copy(mm_cpumask(mm),
+                                     &mm->context.cpu_attach_mask);
+        }
+        atomic_sub(0x10000, &mm->context.attach_count);
        preempt_enable();
 }
+/*
+ * Flush TLB entries for a specific ASCE on all CPUs.
+ */
+static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
+{
+        int active, count;
+        preempt_disable();
+        active = (mm == current->active_mm) ? 1 : 0;
+        count = atomic_add_return(0x10000, &mm->context.attach_count);
+        if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
+            cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
+                __tlb_flush_idte_local(asce);
+        } else {
+                if (MACHINE_HAS_IDTE)
+                        __tlb_flush_idte(asce);
+                else
+                        __tlb_flush_global();
+                /* Reset TLB flush mask */
+                if (MACHINE_HAS_TLB_LC)
+                        cpumask_copy(mm_cpumask(mm),
+                                     &mm->context.cpu_attach_mask);
+        }
+        atomic_sub(0x10000, &mm->context.attach_count);
+        preempt_enable();
+}
+static inline void __tlb_flush_kernel(void)
+{
+        if (MACHINE_HAS_IDTE)
+                __tlb_flush_idte((unsigned long) init_mm.pgd |
+                                 init_mm.context.asce_bits);
+        else
+                __tlb_flush_global();
+}
 #else
-#define __tlb_flush_full(mm)    __tlb_flush_local()
 #define __tlb_flush_global()    __tlb_flush_local()
-#endif
+#define __tlb_flush_full(mm)    __tlb_flush_local()
 /*
- * Flush all tlb entries of a page table on all cpus.
+ * Flush TLB entries for a specific ASCE on all CPUs.
 */
-static inline void __tlb_flush_idte(unsigned long asce)
+static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
 {
-        asm volatile(
+        if (MACHINE_HAS_TLB_LC)
-                "       .insn   rrf,0xb98e0000,0,%0,%1,0"
+                __tlb_flush_idte_local(asce);
-                : : "a" (2048), "a" (asce) : "cc" );
+        else
+                __tlb_flush_local();
 }
+static inline void __tlb_flush_kernel(void)
+{
+        if (MACHINE_HAS_TLB_LC)
+                __tlb_flush_idte_local((unsigned long) init_mm.pgd |
+                                       init_mm.context.asce_bits);
+        else
+                __tlb_flush_local();
+}
+#endif
 static inline void __tlb_flush_mm(struct mm_struct * mm)
 {
        /*
@@ -80,7 +155,7 @@ static inline void __tlb_flush_mm(struct mm_struct * mm)
         * only ran on the local cpu.
         */
        if (MACHINE_HAS_IDTE && list_empty(&mm->context.gmap_list))
-                __tlb_flush_idte((unsigned long) mm->pgd |
+                __tlb_flush_asce(mm, (unsigned long) mm->pgd |
                                 mm->context.asce_bits);
        else
                __tlb_flush_full(mm);
@@ -130,7 +205,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
 static inline void flush_tlb_kernel_range(unsigned long start,
                                          unsigned long end)
 {
-        __tlb_flush_mm(&init_mm);
+        __tlb_flush_kernel();
 }
 #endif /* _S390_TLBFLUSH_H */
diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h
index 4133b3f72fb0..1be64a1506d0 100644
--- a/arch/s390/include/asm/uaccess.h
+++ b/arch/s390/include/asm/uaccess.h
@@ -92,8 +92,6 @@ static inline unsigned long extable_fixup(const struct exception_table_entry *x)
 #define ARCH_HAS_SORT_EXTABLE
 #define ARCH_HAS_SEARCH_EXTABLE
-int __handle_fault(unsigned long, unsigned long, int);
 /**
 * __copy_from_user: - Copy a block of data from user space, with less checking.
 * @to:   Destination address, in kernel space.
diff --git a/arch/s390/include/uapi/asm/kvm.h b/arch/s390/include/uapi/asm/kvm.h
index d25da598ec62..c003c6a73b1e 100644
--- a/arch/s390/include/uapi/asm/kvm.h
+++ b/arch/s390/include/uapi/asm/kvm.h
@@ -16,6 +16,44 @@
 #define __KVM_S390
+/* Device control API: s390-specific devices */
+#define KVM_DEV_FLIC_GET_ALL_IRQS       1
+#define KVM_DEV_FLIC_ENQUEUE            2
+#define KVM_DEV_FLIC_CLEAR_IRQS         3
+#define KVM_DEV_FLIC_APF_ENABLE         4
+#define KVM_DEV_FLIC_APF_DISABLE_WAIT   5
+#define KVM_DEV_FLIC_ADAPTER_REGISTER   6
+#define KVM_DEV_FLIC_ADAPTER_MODIFY     7
+/*
+ * We can have up to 4*64k pending subchannels + 8 adapter interrupts,
+ * as well as up  to ASYNC_PF_PER_VCPU*KVM_MAX_VCPUS pfault done interrupts.
+ * There are also sclp and machine checks. This gives us
+ * sizeof(kvm_s390_irq)*(4*65536+8+64*64+1+1) = 72 * 266250 = 19170000
+ * Lets round up to 8192 pages.
+ */
+#define KVM_S390_MAX_FLOAT_IRQS 266250
+#define KVM_S390_FLIC_MAX_BUFFER        0x2000000
+struct kvm_s390_io_adapter {
+        __u32 id;
+        __u8 isc;
+        __u8 maskable;
+        __u8 swap;
+        __u8 pad;
+};
+#define KVM_S390_IO_ADAPTER_MASK 1
+#define KVM_S390_IO_ADAPTER_MAP 2
+#define KVM_S390_IO_ADAPTER_UNMAP 3
+struct kvm_s390_io_adapter_req {
+        __u32 id;
+        __u8 type;
+        __u8 mask;
+        __u16 pad0;
+        __u64 addr;
+};
 /* for KVM_GET_REGS and KVM_SET_REGS */
 struct kvm_regs {
        /* general purpose regs for s390 */
@@ -57,4 +95,9 @@ struct kvm_sync_regs {
 #define KVM_REG_S390_EPOCHDIFF  (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x2)
 #define KVM_REG_S390_CPU_TIMER  (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x3)
 #define KVM_REG_S390_CLOCK_COMP (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x4)
+#define KVM_REG_S390_PFTOKEN    (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x5)
+#define KVM_REG_S390_PFCOMPARE  (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x6)
+#define KVM_REG_S390_PFSELECT   (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x7)
+#define KVM_REG_S390_PP         (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x8)
+#define KVM_REG_S390_GBEA       (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x9)
 #endif
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index e4c99a183651..cc10cdd4d6a2 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -136,6 +136,7 @@ int main(void)
        DEFINE(__LC_RESTART_FN, offsetof(struct _lowcore, restart_fn));
        DEFINE(__LC_RESTART_DATA, offsetof(struct _lowcore, restart_data));
        DEFINE(__LC_RESTART_SOURCE, offsetof(struct _lowcore, restart_source));
+        DEFINE(__LC_KERNEL_ASCE, offsetof(struct _lowcore, kernel_asce));
        DEFINE(__LC_USER_ASCE, offsetof(struct _lowcore, user_asce));
        DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
        DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock));
diff --git a/arch/s390/kernel/cache.c b/arch/s390/kernel/cache.c
index 3a414c0f93ed..c0b03c28d157 100644
--- a/arch/s390/kernel/cache.c
+++ b/arch/s390/kernel/cache.c
@@ -378,9 +378,12 @@ static int __init cache_init(void)
        if (!test_facility(34))
                return 0;
        cache_build_info();
+        cpu_notifier_register_begin();
        for_each_online_cpu(cpu)
                cache_add_cpu(cpu);
-        hotcpu_notifier(cache_hotplug, 0);
+        __hotcpu_notifier(cache_hotplug, 0);
+        cpu_notifier_register_done();
        return 0;
 }
 device_initcall(cache_init);
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index 6b594439cca5..a734f3585ceb 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -386,6 +386,8 @@ static __init void detect_machine_facilities(void)
                S390_lowcore.machine_flags |= MACHINE_FLAG_TE;
        if (test_facility(66))
                S390_lowcore.machine_flags |= MACHINE_FLAG_RRBM;
+        if (test_facility(51))
+                S390_lowcore.machine_flags |= MACHINE_FLAG_TLB_LC;
 #endif
 }
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 526d3735ed29..1662038516c0 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -38,9 +38,9 @@ __PT_R14     =	__PT_GPRS + 56
 __PT_R15     =  __PT_GPRS + 60
 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
-                 _TIF_MCCK_PENDING | _TIF_PER_TRAP )
+                 _TIF_MCCK_PENDING | _TIF_PER_TRAP | _TIF_ASCE)
 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
-                 _TIF_MCCK_PENDING)
+                 _TIF_MCCK_PENDING | _TIF_ASCE)
 _TIF_TRACE    = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
                 _TIF_SYSCALL_TRACEPOINT)
 _TIF_TRANSFER = (_TIF_MCCK_PENDING | _TIF_TLB_WAIT)
@@ -241,6 +241,8 @@ sysc_work:
        jo      sysc_sigpending
        tm      __TI_flags+3(%r12),_TIF_NOTIFY_RESUME
        jo      sysc_notify_resume
+        tm      __TI_flags+3(%r12),_TIF_ASCE
+        jo      sysc_uaccess
        j       sysc_return             # beware of critical section cleanup
 #
@@ -260,6 +262,14 @@ sysc_mcck_pending:
        br      %r1                     # TIF bit will be cleared by handler
 #
+# _TIF_ASCE is set, load user space asce
+#
+sysc_uaccess:
+        ni      __TI_flags+3(%r12),255-_TIF_ASCE
+        lctl    %c1,%c1,__LC_USER_ASCE  # load primary asce
+        j       sysc_return
+#
 # _TIF_SIGPENDING is set, call do_signal
 #
 sysc_sigpending:
@@ -522,6 +532,8 @@ io_work_tif:
        jo      io_sigpending
        tm      __TI_flags+3(%r12),_TIF_NOTIFY_RESUME
        jo      io_notify_resume
+        tm      __TI_flags+3(%r12),_TIF_ASCE
+        jo      io_uaccess
        j       io_return               # beware of critical section cleanup
 #
@@ -535,6 +547,14 @@ io_mcck_pending:
        j       io_return
 #
+# _TIF_ASCE is set, load user space asce
+#
+io_uaccess:
+        ni      __TI_flags+3(%r12),255-_TIF_ASCE
+        lctl    %c1,%c1,__LC_USER_ASCE  # load primary asce
+        j       io_return
+#
 # _TIF_NEED_RESCHED is set, call schedule
 #
 io_reschedule:
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index e09dbe5f2901..5963e43618bb 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -43,9 +43,9 @@ STACK_SIZE  = 1 << STACK_SHIFT
 STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
-                 _TIF_MCCK_PENDING | _TIF_PER_TRAP )
+                 _TIF_MCCK_PENDING | _TIF_PER_TRAP | _TIF_ASCE)
 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
-                 _TIF_MCCK_PENDING)
+                 _TIF_MCCK_PENDING | _TIF_ASCE)
 _TIF_TRACE    = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
                 _TIF_SYSCALL_TRACEPOINT)
 _TIF_TRANSFER = (_TIF_MCCK_PENDING | _TIF_TLB_WAIT)
@@ -275,6 +275,8 @@ sysc_work:
        jo      sysc_sigpending
        tm      __TI_flags+7(%r12),_TIF_NOTIFY_RESUME
        jo      sysc_notify_resume
+        tm      __TI_flags+7(%r12),_TIF_ASCE
+        jo      sysc_uaccess
        j       sysc_return             # beware of critical section cleanup
 #
@@ -292,6 +294,14 @@ sysc_mcck_pending:
        jg      s390_handle_mcck        # TIF bit will be cleared by handler
 #
+# _TIF_ASCE is set, load user space asce
+#
+sysc_uaccess:
+        ni      __TI_flags+7(%r12),255-_TIF_ASCE
+        lctlg   %c1,%c1,__LC_USER_ASCE          # load primary asce
+        j       sysc_return
+#
 # _TIF_SIGPENDING is set, call do_signal
 #
 sysc_sigpending:
@@ -559,6 +569,8 @@ io_work_tif:
        jo      io_sigpending
        tm      __TI_flags+7(%r12),_TIF_NOTIFY_RESUME
        jo      io_notify_resume
+        tm      __TI_flags+7(%r12),_TIF_ASCE
+        jo      io_uaccess
        j       io_return               # beware of critical section cleanup
 #
@@ -571,6 +583,14 @@ io_mcck_pending:
        j       io_return
 #
+# _TIF_ASCE is set, load user space asce
+#
+io_uaccess:
+        ni      __TI_flags+7(%r12),255-_TIF_ASCE
+        lctlg   %c1,%c1,__LC_USER_ASCE          # load primary asce
+        j       io_return
+#
 # _TIF_NEED_RESCHED is set, call schedule
 #
 io_reschedule:
diff --git a/arch/s390/kernel/ftrace.c b/arch/s390/kernel/ftrace.c
index 224db03e9518..54d6493c4a56 100644
--- a/arch/s390/kernel/ftrace.c
+++ b/arch/s390/kernel/ftrace.c
@@ -130,9 +130,8 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
        return 0;
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        *(unsigned long *) data = 0;
        return 0;
 }
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index a770be97db4d..c7463aa0014b 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -85,6 +85,7 @@ static const struct irq_class irqclass_sub_desc[NR_ARCH_IRQS] = {
        [IRQIO_PCI]  = {.name = "PCI", .desc = "[I/O] PCI Interrupt" },
        [IRQIO_MSI]  = {.name = "MSI", .desc = "[I/O] MSI Interrupt" },
        [IRQIO_VIR]  = {.name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
+        [IRQIO_VAI]  = {.name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"},
        [NMI_NMI]    = {.name = "NMI", .desc = "[NMI] Machine Check"},
        [CPU_RST]    = {.name = "RST", .desc = "[CPU] CPU Restart"},
 };
@@ -206,7 +207,7 @@ static inline int ext_hash(u16 code)
        return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
 }
-int register_external_interrupt(u16 code, ext_int_handler_t handler)
+int register_external_irq(u16 code, ext_int_handler_t handler)
 {
        struct ext_int_info *p;
        unsigned long flags;
@@ -224,9 +225,9 @@ int register_external_interrupt(u16 code, ext_int_handler_t handler)
        spin_unlock_irqrestore(&ext_int_hash_lock, flags);
        return 0;
 }
-EXPORT_SYMBOL(register_external_interrupt);
+EXPORT_SYMBOL(register_external_irq);
-int unregister_external_interrupt(u16 code, ext_int_handler_t handler)
+int unregister_external_irq(u16 code, ext_int_handler_t handler)
 {
        struct ext_int_info *p;
        unsigned long flags;
@@ -242,7 +243,7 @@ int unregister_external_interrupt(u16 code, ext_int_handler_t handler)
        spin_unlock_irqrestore(&ext_int_hash_lock, flags);
        return 0;
 }
-EXPORT_SYMBOL(unregister_external_interrupt);
+EXPORT_SYMBOL(unregister_external_irq);
 static irqreturn_t do_ext_interrupt(int irq, void *dummy)
 {
@@ -252,7 +253,7 @@ static irqreturn_t do_ext_interrupt(int irq, void *dummy)
        int index;
        ext_code = *(struct ext_code *) &regs->int_code;
-        if (ext_code.code != 0x1004)
+        if (ext_code.code != EXT_IRQ_CLK_COMP)
                __get_cpu_var(s390_idle).nohz_delay = 1;
        index = ext_hash(ext_code.code);
diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c
index f51214c04858..ea75d011a6fc 100644
--- a/arch/s390/kernel/perf_cpum_cf.c
+++ b/arch/s390/kernel/perf_cpum_cf.c
@@ -673,7 +673,8 @@ static int __init cpumf_pmu_init(void)
        ctl_clear_bit(0, 48);
        /* register handler for measurement-alert interruptions */
-        rc = register_external_interrupt(0x1407, cpumf_measurement_alert);
+        rc = register_external_irq(EXT_IRQ_MEASURE_ALERT,
+                                   cpumf_measurement_alert);
        if (rc) {
                pr_err("Registering for CPU-measurement alerts "
                       "failed with rc=%i\n", rc);
@@ -684,7 +685,8 @@ static int __init cpumf_pmu_init(void)
        rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", PERF_TYPE_RAW);
        if (rc) {
                pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc);
-                unregister_external_interrupt(0x1407, cpumf_measurement_alert);
+                unregister_external_irq(EXT_IRQ_MEASURE_ALERT,
+                                        cpumf_measurement_alert);
                goto out;
        }
        perf_cpu_notifier(cpumf_pmu_notifier);
diff --git a/arch/s390/kernel/perf_cpum_sf.c b/arch/s390/kernel/perf_cpum_sf.c
index 6c0d29827cb6..ea0c7b2ef030 100644
--- a/arch/s390/kernel/perf_cpum_sf.c
+++ b/arch/s390/kernel/perf_cpum_sf.c
@@ -1621,7 +1621,8 @@ static int __init init_cpum_sampling_pmu(void)
                pr_err("Registering for s390dbf failed\n");
        debug_register_view(sfdbg, &debug_sprintf_view);
-        err = register_external_interrupt(0x1407, cpumf_measurement_alert);
+        err = register_external_irq(EXT_IRQ_MEASURE_ALERT,
+                                    cpumf_measurement_alert);
        if (err) {
                pr_cpumsf_err(RS_INIT_FAILURE_ALRT);
                goto out;
@@ -1630,7 +1631,8 @@ static int __init init_cpum_sampling_pmu(void)
        err = perf_pmu_register(&cpumf_sampling, "cpum_sf", PERF_TYPE_RAW);
        if (err) {
                pr_cpumsf_err(RS_INIT_FAILURE_PERF);
-                unregister_external_interrupt(0x1407, cpumf_measurement_alert);
+                unregister_external_irq(EXT_IRQ_MEASURE_ALERT,
+                                        cpumf_measurement_alert);
                goto out;
        }
        perf_cpu_notifier(cpumf_pmu_notifier);
diff --git a/arch/s390/kernel/runtime_instr.c b/arch/s390/kernel/runtime_instr.c
index d817cce7e72d..26b4ae96fdd7 100644
--- a/arch/s390/kernel/runtime_instr.c
+++ b/arch/s390/kernel/runtime_instr.c
@@ -138,7 +138,8 @@ static int __init runtime_instr_init(void)
                return 0;
        irq_subclass_register(IRQ_SUBCLASS_MEASUREMENT_ALERT);
-        rc = register_external_interrupt(0x1407, runtime_instr_int_handler);
+        rc = register_external_irq(EXT_IRQ_MEASURE_ALERT,
+                                   runtime_instr_int_handler);
        if (rc)
                irq_subclass_unregister(IRQ_SUBCLASS_MEASUREMENT_ALERT);
        else
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index 29bd7bec4176..a41f2c99dcc8 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -9,6 +9,7 @@
 */
 #include <linux/linkage.h>
+#include <asm/irq.h>
 LC_EXT_NEW_PSW          = 0x58                  # addr of ext int handler
 LC_EXT_NEW_PSW_64       = 0x1b0                 # addr of ext int handler 64 bit
@@ -73,9 +74,9 @@ _sclp_wait_int:
        lpsw    .LwaitpswS1-.LbaseS1(%r13)      # wait until interrupt
 .LwaitS1:
        lh      %r7,LC_EXT_INT_CODE
-        chi     %r7,0x1004                      # timeout?
+        chi     %r7,EXT_IRQ_CLK_COMP            # timeout?
        je      .LtimeoutS1
-        chi     %r7,0x2401                      # service int?
+        chi     %r7,EXT_IRQ_SERVICE_SIG         # service int?
        jne     .LloopS1
        sr      %r2,%r2
        l       %r3,LC_EXT_INT_PARAM
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 8827883310dd..512ce1cde2a4 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -236,6 +236,9 @@ static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
 {
        struct _lowcore *lc = pcpu->lowcore;
+        if (MACHINE_HAS_TLB_LC)
+                cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
+        cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
        atomic_inc(&init_mm.context.attach_count);
        lc->cpu_nr = cpu;
        lc->percpu_offset = __per_cpu_offset[cpu];
@@ -760,6 +763,9 @@ void __cpu_die(unsigned int cpu)
                cpu_relax();
        pcpu_free_lowcore(pcpu);
        atomic_dec(&init_mm.context.attach_count);
+        cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
+        if (MACHINE_HAS_TLB_LC)
+                cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
 }
 void __noreturn cpu_die(void)
@@ -785,10 +791,10 @@ void __init smp_fill_possible_mask(void)
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
        /* request the 0x1201 emergency signal external interrupt */
-        if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0)
+        if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
                panic("Couldn't request external interrupt 0x1201");
        /* request the 0x1202 external call external interrupt */
-        if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0)
+        if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
                panic("Couldn't request external interrupt 0x1202");
        smp_detect_cpus();
 }
@@ -1057,19 +1063,24 @@ static DEVICE_ATTR(rescan, 0200, NULL, rescan_store);
 static int __init s390_smp_init(void)
 {
-        int cpu, rc;
+        int cpu, rc = 0;
-        hotcpu_notifier(smp_cpu_notify, 0);
 #ifdef CONFIG_HOTPLUG_CPU
        rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
        if (rc)
                return rc;
 #endif
+        cpu_notifier_register_begin();
        for_each_present_cpu(cpu) {
                rc = smp_add_present_cpu(cpu);
                if (rc)
-                        return rc;
+                        goto out;
        }
-        return 0;
+        __hotcpu_notifier(smp_cpu_notify, 0);
+out:
+        cpu_notifier_register_done();
+        return rc;
 }
 subsys_initcall(s390_smp_init);
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index dd95f1631621..386d37a228bb 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -262,11 +262,11 @@ void __init time_init(void)
        stp_reset();
        /* request the clock comparator external interrupt */
-        if (register_external_interrupt(0x1004, clock_comparator_interrupt))
+        if (register_external_irq(EXT_IRQ_CLK_COMP, clock_comparator_interrupt))
-                panic("Couldn't request external interrupt 0x1004");
+                panic("Couldn't request external interrupt 0x1004");
        /* request the timing alert external interrupt */
-        if (register_external_interrupt(0x1406, timing_alert_interrupt))
+        if (register_external_irq(EXT_IRQ_TIMING_ALERT, timing_alert_interrupt))
                panic("Couldn't request external interrupt 0x1406");
        if (clocksource_register(&clocksource_tod) != 0)
diff --git a/arch/s390/kvm/Kconfig b/arch/s390/kvm/Kconfig
index 70b46eacf8e1..10d529ac9821 100644
--- a/arch/s390/kvm/Kconfig
+++ b/arch/s390/kvm/Kconfig
@@ -23,6 +23,10 @@ config KVM
        select ANON_INODES
        select HAVE_KVM_CPU_RELAX_INTERCEPT
        select HAVE_KVM_EVENTFD
+        select KVM_ASYNC_PF
+        select KVM_ASYNC_PF_SYNC
+        select HAVE_KVM_IRQCHIP
+        select HAVE_KVM_IRQ_ROUTING
        ---help---
          Support hosting paravirtualized guest machines using the SIE
          virtualization capability on the mainframe. This should work
diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile
index 40b4c6470f88..d3adb37e93a4 100644
--- a/arch/s390/kvm/Makefile
+++ b/arch/s390/kvm/Makefile
@@ -7,7 +7,7 @@
 # as published by the Free Software Foundation.
 KVM := ../../../virt/kvm
-common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o
+common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o  $(KVM)/async_pf.o $(KVM)/irqchip.o
 ccflags-y := -Ivirt/kvm -Iarch/s390/kvm
diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c
index 6f9cfa500372..08dfc839a6cf 100644
--- a/arch/s390/kvm/diag.c
+++ b/arch/s390/kvm/diag.c
@@ -18,6 +18,7 @@
 #include "kvm-s390.h"
 #include "trace.h"
 #include "trace-s390.h"
+#include "gaccess.h"
 static int diag_release_pages(struct kvm_vcpu *vcpu)
 {
@@ -47,6 +48,87 @@ static int diag_release_pages(struct kvm_vcpu *vcpu)
        return 0;
 }
+static int __diag_page_ref_service(struct kvm_vcpu *vcpu)
+{
+        struct prs_parm {
+                u16 code;
+                u16 subcode;
+                u16 parm_len;
+                u16 parm_version;
+                u64 token_addr;
+                u64 select_mask;
+                u64 compare_mask;
+                u64 zarch;
+        };
+        struct prs_parm parm;
+        int rc;
+        u16 rx = (vcpu->arch.sie_block->ipa & 0xf0) >> 4;
+        u16 ry = (vcpu->arch.sie_block->ipa & 0x0f);
+        unsigned long hva_token = KVM_HVA_ERR_BAD;
+        if (vcpu->run->s.regs.gprs[rx] & 7)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+        if (copy_from_guest(vcpu, &parm, vcpu->run->s.regs.gprs[rx], sizeof(parm)))
+                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+        if (parm.parm_version != 2 || parm.parm_len < 5 || parm.code != 0x258)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+        switch (parm.subcode) {
+        case 0: /* TOKEN */
+                if (vcpu->arch.pfault_token != KVM_S390_PFAULT_TOKEN_INVALID) {
+                        /*
+                         * If the pagefault handshake is already activated,
+                         * the token must not be changed.  We have to return
+                         * decimal 8 instead, as mandated in SC24-6084.
+                         */
+                        vcpu->run->s.regs.gprs[ry] = 8;
+                        return 0;
+                }
+                if ((parm.compare_mask & parm.select_mask) != parm.compare_mask ||
+                    parm.token_addr & 7 || parm.zarch != 0x8000000000000000ULL)
+                        return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+                hva_token = gfn_to_hva(vcpu->kvm, gpa_to_gfn(parm.token_addr));
+                if (kvm_is_error_hva(hva_token))
+                        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+                vcpu->arch.pfault_token = parm.token_addr;
+                vcpu->arch.pfault_select = parm.select_mask;
+                vcpu->arch.pfault_compare = parm.compare_mask;
+                vcpu->run->s.regs.gprs[ry] = 0;
+                rc = 0;
+                break;
+        case 1: /*
+                 * CANCEL
+                 * Specification allows to let already pending tokens survive
+                 * the cancel, therefore to reduce code complexity, we assume
+                 * all outstanding tokens are already pending.
+                 */
+                if (parm.token_addr || parm.select_mask ||
+                    parm.compare_mask || parm.zarch)
+                        return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+                vcpu->run->s.regs.gprs[ry] = 0;
+                /*
+                 * If the pfault handling was not established or is already
+                 * canceled SC24-6084 requests to return decimal 4.
+                 */
+                if (vcpu->arch.pfault_token == KVM_S390_PFAULT_TOKEN_INVALID)
+                        vcpu->run->s.regs.gprs[ry] = 4;
+                else
+                        vcpu->arch.pfault_token = KVM_S390_PFAULT_TOKEN_INVALID;
+                rc = 0;
+                break;
+        default:
+                rc = -EOPNOTSUPP;
+                break;
+        }
+        return rc;
+}
 static int __diag_time_slice_end(struct kvm_vcpu *vcpu)
 {
        VCPU_EVENT(vcpu, 5, "%s", "diag time slice end");
@@ -85,6 +167,10 @@ static int __diag_ipl_functions(struct kvm_vcpu *vcpu)
        VCPU_EVENT(vcpu, 5, "diag ipl functions, subcode %lx", subcode);
        switch (subcode) {
+        case 0:
+        case 1:
+                page_table_reset_pgste(current->mm, 0, TASK_SIZE);
+                return -EOPNOTSUPP;
        case 3:
                vcpu->run->s390_reset_flags = KVM_S390_RESET_CLEAR;
                page_table_reset_pgste(current->mm, 0, TASK_SIZE);
@@ -153,6 +239,8 @@ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu)
                return __diag_time_slice_end(vcpu);
        case 0x9c:
                return __diag_time_slice_end_directed(vcpu);
+        case 0x258:
+                return __diag_page_ref_service(vcpu);
        case 0x308:
                return __diag_ipl_functions(vcpu);
        case 0x500:
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index 5f79d2d79ca7..200a8f9390b6 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -1,7 +1,7 @@
 /*
 * handling kvm guest interrupts
 *
- * Copyright IBM Corp. 2008
+ * Copyright IBM Corp. 2008,2014
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License (version 2 only)
@@ -13,6 +13,7 @@
 #include <linux/interrupt.h>
 #include <linux/kvm_host.h>
 #include <linux/hrtimer.h>
+#include <linux/mmu_context.h>
 #include <linux/signal.h>
 #include <linux/slab.h>
 #include <asm/asm-offsets.h>
@@ -31,7 +32,7 @@ static int is_ioint(u64 type)
        return ((type & 0xfffe0000u) != 0xfffe0000u);
 }
-static int psw_extint_disabled(struct kvm_vcpu *vcpu)
+int psw_extint_disabled(struct kvm_vcpu *vcpu)
 {
        return !(vcpu->arch.sie_block->gpsw.mask & PSW_MASK_EXT);
 }
@@ -78,11 +79,8 @@ static int __interrupt_is_deliverable(struct kvm_vcpu *vcpu,
                        return 1;
                return 0;
        case KVM_S390_INT_SERVICE:
-                if (psw_extint_disabled(vcpu))
+        case KVM_S390_INT_PFAULT_INIT:
-                        return 0;
+        case KVM_S390_INT_PFAULT_DONE:
-                if (vcpu->arch.sie_block->gcr[0] & 0x200ul)
-                        return 1;
-                return 0;
        case KVM_S390_INT_VIRTIO:
                if (psw_extint_disabled(vcpu))
                        return 0;
@@ -117,14 +115,12 @@ static int __interrupt_is_deliverable(struct kvm_vcpu *vcpu,
 static void __set_cpu_idle(struct kvm_vcpu *vcpu)
 {
-        BUG_ON(vcpu->vcpu_id > KVM_MAX_VCPUS - 1);
        atomic_set_mask(CPUSTAT_WAIT, &vcpu->arch.sie_block->cpuflags);
        set_bit(vcpu->vcpu_id, vcpu->arch.local_int.float_int->idle_mask);
 }
 static void __unset_cpu_idle(struct kvm_vcpu *vcpu)
 {
-        BUG_ON(vcpu->vcpu_id > KVM_MAX_VCPUS - 1);
        atomic_clear_mask(CPUSTAT_WAIT, &vcpu->arch.sie_block->cpuflags);
        clear_bit(vcpu->vcpu_id, vcpu->arch.local_int.float_int->idle_mask);
 }
@@ -150,6 +146,8 @@ static void __set_intercept_indicator(struct kvm_vcpu *vcpu,
        case KVM_S390_INT_EXTERNAL_CALL:
        case KVM_S390_INT_EMERGENCY:
        case KVM_S390_INT_SERVICE:
+        case KVM_S390_INT_PFAULT_INIT:
+        case KVM_S390_INT_PFAULT_DONE:
        case KVM_S390_INT_VIRTIO:
                if (psw_extint_disabled(vcpu))
                        __set_cpuflag(vcpu, CPUSTAT_EXT_INT);
@@ -223,6 +221,30 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                rc |= put_guest(vcpu, inti->ext.ext_params,
                                (u32 __user *)__LC_EXT_PARAMS);
                break;
+        case KVM_S390_INT_PFAULT_INIT:
+                trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, 0,
+                                                 inti->ext.ext_params2);
+                rc  = put_guest(vcpu, 0x2603, (u16 __user *) __LC_EXT_INT_CODE);
+                rc |= put_guest(vcpu, 0x0600, (u16 __user *) __LC_EXT_CPU_ADDR);
+                rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      __LC_EXT_NEW_PSW, sizeof(psw_t));
+                rc |= put_guest(vcpu, inti->ext.ext_params2,
+                                (u64 __user *) __LC_EXT_PARAMS2);
+                break;
+        case KVM_S390_INT_PFAULT_DONE:
+                trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, 0,
+                                                 inti->ext.ext_params2);
+                rc  = put_guest(vcpu, 0x2603, (u16 __user *) __LC_EXT_INT_CODE);
+                rc |= put_guest(vcpu, 0x0680, (u16 __user *) __LC_EXT_CPU_ADDR);
+                rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      __LC_EXT_NEW_PSW, sizeof(psw_t));
+                rc |= put_guest(vcpu, inti->ext.ext_params2,
+                                (u64 __user *) __LC_EXT_PARAMS2);
+                break;
        case KVM_S390_INT_VIRTIO:
                VCPU_EVENT(vcpu, 4, "interrupt: virtio parm:%x,parm64:%llx",
                           inti->ext.ext_params, inti->ext.ext_params2);
@@ -357,7 +379,7 @@ static int __try_deliver_ckc_interrupt(struct kvm_vcpu *vcpu)
        return 1;
 }
-static int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu)
+int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu)
 {
        struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int;
        struct kvm_s390_float_interrupt *fi = vcpu->arch.local_int.float_int;
@@ -482,11 +504,26 @@ enum hrtimer_restart kvm_s390_idle_wakeup(struct hrtimer *timer)
        struct kvm_vcpu *vcpu;
        vcpu = container_of(timer, struct kvm_vcpu, arch.ckc_timer);
+        vcpu->preempted = true;
        tasklet_schedule(&vcpu->arch.tasklet);
        return HRTIMER_NORESTART;
 }
+void kvm_s390_clear_local_irqs(struct kvm_vcpu *vcpu)
+{
+        struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int;
+        struct kvm_s390_interrupt_info  *n, *inti = NULL;
+        spin_lock_bh(&li->lock);
+        list_for_each_entry_safe(inti, n, &li->list, list) {
+                list_del(&inti->list);
+                kfree(inti);
+        }
+        atomic_set(&li->active, 0);
+        spin_unlock_bh(&li->lock);
+}
 void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu)
 {
        struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int;
@@ -528,6 +565,7 @@ void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu)
                        list_for_each_entry_safe(inti, n, &fi->list, list) {
                                if (__interrupt_is_deliverable(vcpu, inti)) {
                                        list_del(&inti->list);
+                                        fi->irq_count--;
                                        deliver = 1;
                                        break;
                                }
@@ -583,6 +621,7 @@ void kvm_s390_deliver_pending_machine_checks(struct kvm_vcpu *vcpu)
                                if ((inti->type == KVM_S390_MCHK) &&
                                    __interrupt_is_deliverable(vcpu, inti)) {
                                        list_del(&inti->list);
+                                        fi->irq_count--;
                                        deliver = 1;
                                        break;
                                }
@@ -650,8 +689,10 @@ struct kvm_s390_interrupt_info *kvm_s390_get_io_int(struct kvm *kvm,
                inti = iter;
                break;
        }
-        if (inti)
+        if (inti) {
                list_del_init(&inti->list);
+                fi->irq_count--;
+        }
        if (list_empty(&fi->list))
                atomic_set(&fi->active, 0);
        spin_unlock(&fi->lock);
@@ -659,53 +700,101 @@ struct kvm_s390_interrupt_info *kvm_s390_get_io_int(struct kvm *kvm,
        return inti;
 }
-int kvm_s390_inject_vm(struct kvm *kvm,
+static int __inject_vm(struct kvm *kvm, struct kvm_s390_interrupt_info *inti)
-                       struct kvm_s390_interrupt *s390int)
 {
        struct kvm_s390_local_interrupt *li;
        struct kvm_s390_float_interrupt *fi;
-        struct kvm_s390_interrupt_info *inti, *iter;
+        struct kvm_s390_interrupt_info *iter;
+        struct kvm_vcpu *dst_vcpu = NULL;
        int sigcpu;
+        int rc = 0;
+        mutex_lock(&kvm->lock);
+        fi = &kvm->arch.float_int;
+        spin_lock(&fi->lock);
+        if (fi->irq_count >= KVM_S390_MAX_FLOAT_IRQS) {
+                rc = -EINVAL;
+                goto unlock_fi;
+        }
+        fi->irq_count++;
+        if (!is_ioint(inti->type)) {
+                list_add_tail(&inti->list, &fi->list);
+        } else {
+                u64 isc_bits = int_word_to_isc_bits(inti->io.io_int_word);
+                /* Keep I/O interrupts sorted in isc order. */
+                list_for_each_entry(iter, &fi->list, list) {
+                        if (!is_ioint(iter->type))
+                                continue;
+                        if (int_word_to_isc_bits(iter->io.io_int_word)
+                            <= isc_bits)
+                                continue;
+                        break;
+                }
+                list_add_tail(&inti->list, &iter->list);
+        }
+        atomic_set(&fi->active, 1);
+        sigcpu = find_first_bit(fi->idle_mask, KVM_MAX_VCPUS);
+        if (sigcpu == KVM_MAX_VCPUS) {
+                do {
+                        sigcpu = fi->next_rr_cpu++;
+                        if (sigcpu == KVM_MAX_VCPUS)
+                                sigcpu = fi->next_rr_cpu = 0;
+                } while (kvm_get_vcpu(kvm, sigcpu) == NULL);
+        }
+        dst_vcpu = kvm_get_vcpu(kvm, sigcpu);
+        li = &dst_vcpu->arch.local_int;
+        spin_lock_bh(&li->lock);
+        atomic_set_mask(CPUSTAT_EXT_INT, li->cpuflags);
+        if (waitqueue_active(li->wq))
+                wake_up_interruptible(li->wq);
+        kvm_get_vcpu(kvm, sigcpu)->preempted = true;
+        spin_unlock_bh(&li->lock);
+unlock_fi:
+        spin_unlock(&fi->lock);
+        mutex_unlock(&kvm->lock);
+        return rc;
+}
+int kvm_s390_inject_vm(struct kvm *kvm,
+                       struct kvm_s390_interrupt *s390int)
+{
+        struct kvm_s390_interrupt_info *inti;
        inti = kzalloc(sizeof(*inti), GFP_KERNEL);
        if (!inti)
                return -ENOMEM;
-        switch (s390int->type) {
+        inti->type = s390int->type;
+        switch (inti->type) {
        case KVM_S390_INT_VIRTIO:
                VM_EVENT(kvm, 5, "inject: virtio parm:%x,parm64:%llx",
                         s390int->parm, s390int->parm64);
-                inti->type = s390int->type;
                inti->ext.ext_params = s390int->parm;
                inti->ext.ext_params2 = s390int->parm64;
                break;
        case KVM_S390_INT_SERVICE:
                VM_EVENT(kvm, 5, "inject: sclp parm:%x", s390int->parm);
-                inti->type = s390int->type;
                inti->ext.ext_params = s390int->parm;
                break;
-        case KVM_S390_PROGRAM_INT:
+        case KVM_S390_INT_PFAULT_DONE:
-        case KVM_S390_SIGP_STOP:
+                inti->type = s390int->type;
-        case KVM_S390_INT_EXTERNAL_CALL:
+                inti->ext.ext_params2 = s390int->parm64;
-        case KVM_S390_INT_EMERGENCY:
+                break;
-                kfree(inti);
-                return -EINVAL;
        case KVM_S390_MCHK:
                VM_EVENT(kvm, 5, "inject: machine check parm64:%llx",
                         s390int->parm64);
-                inti->type = s390int->type;
                inti->mchk.cr14 = s390int->parm; /* upper bits are not used */
                inti->mchk.mcic = s390int->parm64;
                break;
        case KVM_S390_INT_IO_MIN...KVM_S390_INT_IO_MAX:
-                if (s390int->type & IOINT_AI_MASK)
+                if (inti->type & IOINT_AI_MASK)
                        VM_EVENT(kvm, 5, "%s", "inject: I/O (AI)");
                else
                        VM_EVENT(kvm, 5, "inject: I/O css %x ss %x schid %04x",
                                 s390int->type & IOINT_CSSID_MASK,
                                 s390int->type & IOINT_SSID_MASK,
                                 s390int->type & IOINT_SCHID_MASK);
-                inti->type = s390int->type;
                inti->io.subchannel_id = s390int->parm >> 16;
                inti->io.subchannel_nr = s390int->parm & 0x0000ffffu;
                inti->io.io_int_parm = s390int->parm64 >> 32;
@@ -718,43 +807,7 @@ int kvm_s390_inject_vm(struct kvm *kvm,
        trace_kvm_s390_inject_vm(s390int->type, s390int->parm, s390int->parm64,
                                 2);
-        mutex_lock(&kvm->lock);
+        return __inject_vm(kvm, inti);
-        fi = &kvm->arch.float_int;
-        spin_lock(&fi->lock);
-        if (!is_ioint(inti->type))
-                list_add_tail(&inti->list, &fi->list);
-        else {
-                u64 isc_bits = int_word_to_isc_bits(inti->io.io_int_word);
-                /* Keep I/O interrupts sorted in isc order. */
-                list_for_each_entry(iter, &fi->list, list) {
-                        if (!is_ioint(iter->type))
-                                continue;
-                        if (int_word_to_isc_bits(iter->io.io_int_word)
-                            <= isc_bits)
-                                continue;
-                        break;
-                }
-                list_add_tail(&inti->list, &iter->list);
-        }
-        atomic_set(&fi->active, 1);
-        sigcpu = find_first_bit(fi->idle_mask, KVM_MAX_VCPUS);
-        if (sigcpu == KVM_MAX_VCPUS) {
-                do {
-                        sigcpu = fi->next_rr_cpu++;
-                        if (sigcpu == KVM_MAX_VCPUS)
-                                sigcpu = fi->next_rr_cpu = 0;
-                } while (fi->local_int[sigcpu] == NULL);
-        }
-        li = fi->local_int[sigcpu];
-        spin_lock_bh(&li->lock);
-        atomic_set_mask(CPUSTAT_EXT_INT, li->cpuflags);
-        if (waitqueue_active(li->wq))
-                wake_up_interruptible(li->wq);
-        spin_unlock_bh(&li->lock);
-        spin_unlock(&fi->lock);
-        mutex_unlock(&kvm->lock);
-        return 0;
 }
 int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
@@ -814,6 +867,10 @@ int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
                inti->type = s390int->type;
                inti->mchk.mcic = s390int->parm64;
                break;
+        case KVM_S390_INT_PFAULT_INIT:
+                inti->type = s390int->type;
+                inti->ext.ext_params2 = s390int->parm64;
+                break;
        case KVM_S390_INT_VIRTIO:
        case KVM_S390_INT_SERVICE:
        case KVM_S390_INT_IO_MIN...KVM_S390_INT_IO_MAX:
@@ -837,7 +894,528 @@ int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
        atomic_set_mask(CPUSTAT_EXT_INT, li->cpuflags);
        if (waitqueue_active(&vcpu->wq))
                wake_up_interruptible(&vcpu->wq);
+        vcpu->preempted = true;
        spin_unlock_bh(&li->lock);
        mutex_unlock(&vcpu->kvm->lock);
        return 0;
 }
+static void clear_floating_interrupts(struct kvm *kvm)
+{
+        struct kvm_s390_float_interrupt *fi;
+        struct kvm_s390_interrupt_info  *n, *inti = NULL;
+        mutex_lock(&kvm->lock);
+        fi = &kvm->arch.float_int;
+        spin_lock(&fi->lock);
+        list_for_each_entry_safe(inti, n, &fi->list, list) {
+                list_del(&inti->list);
+                kfree(inti);
+        }
+        fi->irq_count = 0;
+        atomic_set(&fi->active, 0);
+        spin_unlock(&fi->lock);
+        mutex_unlock(&kvm->lock);
+}
+static inline int copy_irq_to_user(struct kvm_s390_interrupt_info *inti,
+                                   u8 *addr)
+{
+        struct kvm_s390_irq __user *uptr = (struct kvm_s390_irq __user *) addr;
+        struct kvm_s390_irq irq = {0};
+        irq.type = inti->type;
+        switch (inti->type) {
+        case KVM_S390_INT_PFAULT_INIT:
+        case KVM_S390_INT_PFAULT_DONE:
+        case KVM_S390_INT_VIRTIO:
+        case KVM_S390_INT_SERVICE:
+                irq.u.ext = inti->ext;
+                break;
+        case KVM_S390_INT_IO_MIN...KVM_S390_INT_IO_MAX:
+                irq.u.io = inti->io;
+                break;
+        case KVM_S390_MCHK:
+                irq.u.mchk = inti->mchk;
+                break;
+        default:
+                return -EINVAL;
+        }
+        if (copy_to_user(uptr, &irq, sizeof(irq)))
+                return -EFAULT;
+        return 0;
+}
+static int get_all_floating_irqs(struct kvm *kvm, __u8 *buf, __u64 len)
+{
+        struct kvm_s390_interrupt_info *inti;
+        struct kvm_s390_float_interrupt *fi;
+        int ret = 0;
+        int n = 0;
+        mutex_lock(&kvm->lock);
+        fi = &kvm->arch.float_int;
+        spin_lock(&fi->lock);
+        list_for_each_entry(inti, &fi->list, list) {
+                if (len < sizeof(struct kvm_s390_irq)) {
+                        /* signal userspace to try again */
+                        ret = -ENOMEM;
+                        break;
+                }
+                ret = copy_irq_to_user(inti, buf);
+                if (ret)
+                        break;
+                buf += sizeof(struct kvm_s390_irq);
+                len -= sizeof(struct kvm_s390_irq);
+                n++;
+        }
+        spin_unlock(&fi->lock);
+        mutex_unlock(&kvm->lock);
+        return ret < 0 ? ret : n;
+}
+static int flic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+        int r;
+        switch (attr->group) {
+        case KVM_DEV_FLIC_GET_ALL_IRQS:
+                r = get_all_floating_irqs(dev->kvm, (u8 *) attr->addr,
+                                          attr->attr);
+                break;
+        default:
+                r = -EINVAL;
+        }
+        return r;
+}
+static inline int copy_irq_from_user(struct kvm_s390_interrupt_info *inti,
+                                     u64 addr)
+{
+        struct kvm_s390_irq __user *uptr = (struct kvm_s390_irq __user *) addr;
+        void *target = NULL;
+        void __user *source;
+        u64 size;
+        if (get_user(inti->type, (u64 __user *)addr))
+                return -EFAULT;
+        switch (inti->type) {
+        case KVM_S390_INT_PFAULT_INIT:
+        case KVM_S390_INT_PFAULT_DONE:
+        case KVM_S390_INT_VIRTIO:
+        case KVM_S390_INT_SERVICE:
+                target = (void *) &inti->ext;
+                source = &uptr->u.ext;
+                size = sizeof(inti->ext);
+                break;
+        case KVM_S390_INT_IO_MIN...KVM_S390_INT_IO_MAX:
+                target = (void *) &inti->io;
+                source = &uptr->u.io;
+                size = sizeof(inti->io);
+                break;
+        case KVM_S390_MCHK:
+                target = (void *) &inti->mchk;
+                source = &uptr->u.mchk;
+                size = sizeof(inti->mchk);
+                break;
+        default:
+                return -EINVAL;
+        }
+        if (copy_from_user(target, source, size))
+                return -EFAULT;
+        return 0;
+}
+static int enqueue_floating_irq(struct kvm_device *dev,
+                                struct kvm_device_attr *attr)
+{
+        struct kvm_s390_interrupt_info *inti = NULL;
+        int r = 0;
+        int len = attr->attr;
+        if (len % sizeof(struct kvm_s390_irq) != 0)
+                return -EINVAL;
+        else if (len > KVM_S390_FLIC_MAX_BUFFER)
+                return -EINVAL;
+        while (len >= sizeof(struct kvm_s390_irq)) {
+                inti = kzalloc(sizeof(*inti), GFP_KERNEL);
+                if (!inti)
+                        return -ENOMEM;
+                r = copy_irq_from_user(inti, attr->addr);
+                if (r) {
+                        kfree(inti);
+                        return r;
+                }
+                r = __inject_vm(dev->kvm, inti);
+                if (r) {
+                        kfree(inti);
+                        return r;
+                }
+                len -= sizeof(struct kvm_s390_irq);
+                attr->addr += sizeof(struct kvm_s390_irq);
+        }
+        return r;
+}
+static struct s390_io_adapter *get_io_adapter(struct kvm *kvm, unsigned int id)
+{
+        if (id >= MAX_S390_IO_ADAPTERS)
+                return NULL;
+        return kvm->arch.adapters[id];
+}
+static int register_io_adapter(struct kvm_device *dev,
+                               struct kvm_device_attr *attr)
+{
+        struct s390_io_adapter *adapter;
+        struct kvm_s390_io_adapter adapter_info;
+        if (copy_from_user(&adapter_info,
+                           (void __user *)attr->addr, sizeof(adapter_info)))
+                return -EFAULT;
+        if ((adapter_info.id >= MAX_S390_IO_ADAPTERS) ||
+            (dev->kvm->arch.adapters[adapter_info.id] != NULL))
+                return -EINVAL;
+        adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
+        if (!adapter)
+                return -ENOMEM;
+        INIT_LIST_HEAD(&adapter->maps);
+        init_rwsem(&adapter->maps_lock);
+        atomic_set(&adapter->nr_maps, 0);
+        adapter->id = adapter_info.id;
+        adapter->isc = adapter_info.isc;
+        adapter->maskable = adapter_info.maskable;
+        adapter->masked = false;
+        adapter->swap = adapter_info.swap;
+        dev->kvm->arch.adapters[adapter->id] = adapter;
+        return 0;
+}
+int kvm_s390_mask_adapter(struct kvm *kvm, unsigned int id, bool masked)
+{
+        int ret;
+        struct s390_io_adapter *adapter = get_io_adapter(kvm, id);
+        if (!adapter || !adapter->maskable)
+                return -EINVAL;
+        ret = adapter->masked;
+        adapter->masked = masked;
+        return ret;
+}
+static int kvm_s390_adapter_map(struct kvm *kvm, unsigned int id, __u64 addr)
+{
+        struct s390_io_adapter *adapter = get_io_adapter(kvm, id);
+        struct s390_map_info *map;
+        int ret;
+        if (!adapter || !addr)
+                return -EINVAL;
+        map = kzalloc(sizeof(*map), GFP_KERNEL);
+        if (!map) {
+                ret = -ENOMEM;
+                goto out;
+        }
+        INIT_LIST_HEAD(&map->list);
+        map->guest_addr = addr;
+        map->addr = gmap_translate(addr, kvm->arch.gmap);
+        if (map->addr == -EFAULT) {
+                ret = -EFAULT;
+                goto out;
+        }
+        ret = get_user_pages_fast(map->addr, 1, 1, &map->page);
+        if (ret < 0)
+                goto out;
+        BUG_ON(ret != 1);
+        down_write(&adapter->maps_lock);
+        if (atomic_inc_return(&adapter->nr_maps) < MAX_S390_ADAPTER_MAPS) {
+                list_add_tail(&map->list, &adapter->maps);
+                ret = 0;
+        } else {
+                put_page(map->page);
+                ret = -EINVAL;
+        }
+        up_write(&adapter->maps_lock);
+out:
+        if (ret)
+                kfree(map);
+        return ret;
+}
+static int kvm_s390_adapter_unmap(struct kvm *kvm, unsigned int id, __u64 addr)
+{
+        struct s390_io_adapter *adapter = get_io_adapter(kvm, id);
+        struct s390_map_info *map, *tmp;
+        int found = 0;
+        if (!adapter || !addr)
+                return -EINVAL;
+        down_write(&adapter->maps_lock);
+        list_for_each_entry_safe(map, tmp, &adapter->maps, list) {
+                if (map->guest_addr == addr) {
+                        found = 1;
+                        atomic_dec(&adapter->nr_maps);
+                        list_del(&map->list);
+                        put_page(map->page);
+                        kfree(map);
+                        break;
+                }
+        }
+        up_write(&adapter->maps_lock);
+        return found ? 0 : -EINVAL;
+}
+void kvm_s390_destroy_adapters(struct kvm *kvm)
+{
+        int i;
+        struct s390_map_info *map, *tmp;
+        for (i = 0; i < MAX_S390_IO_ADAPTERS; i++) {
+                if (!kvm->arch.adapters[i])
+                        continue;
+                list_for_each_entry_safe(map, tmp,
+                                         &kvm->arch.adapters[i]->maps, list) {
+                        list_del(&map->list);
+                        put_page(map->page);
+                        kfree(map);
+                }
+                kfree(kvm->arch.adapters[i]);
+        }
+}
+static int modify_io_adapter(struct kvm_device *dev,
+                             struct kvm_device_attr *attr)
+{
+        struct kvm_s390_io_adapter_req req;
+        struct s390_io_adapter *adapter;
+        int ret;
+        if (copy_from_user(&req, (void __user *)attr->addr, sizeof(req)))
+                return -EFAULT;
+        adapter = get_io_adapter(dev->kvm, req.id);
+        if (!adapter)
+                return -EINVAL;
+        switch (req.type) {
+        case KVM_S390_IO_ADAPTER_MASK:
+                ret = kvm_s390_mask_adapter(dev->kvm, req.id, req.mask);
+                if (ret > 0)
+                        ret = 0;
+                break;
+        case KVM_S390_IO_ADAPTER_MAP:
+                ret = kvm_s390_adapter_map(dev->kvm, req.id, req.addr);
+                break;
+        case KVM_S390_IO_ADAPTER_UNMAP:
+                ret = kvm_s390_adapter_unmap(dev->kvm, req.id, req.addr);
+                break;
+        default:
+                ret = -EINVAL;
+        }
+        return ret;
+}
+static int flic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+        int r = 0;
+        unsigned int i;
+        struct kvm_vcpu *vcpu;
+        switch (attr->group) {
+        case KVM_DEV_FLIC_ENQUEUE:
+                r = enqueue_floating_irq(dev, attr);
+                break;
+        case KVM_DEV_FLIC_CLEAR_IRQS:
+                r = 0;
+                clear_floating_interrupts(dev->kvm);
+                break;
+        case KVM_DEV_FLIC_APF_ENABLE:
+                dev->kvm->arch.gmap->pfault_enabled = 1;
+                break;
+        case KVM_DEV_FLIC_APF_DISABLE_WAIT:
+                dev->kvm->arch.gmap->pfault_enabled = 0;
+                /*
+                 * Make sure no async faults are in transition when
+                 * clearing the queues. So we don't need to worry
+                 * about late coming workers.
+                 */
+                synchronize_srcu(&dev->kvm->srcu);
+                kvm_for_each_vcpu(i, vcpu, dev->kvm)
+                        kvm_clear_async_pf_completion_queue(vcpu);
+                break;
+        case KVM_DEV_FLIC_ADAPTER_REGISTER:
+                r = register_io_adapter(dev, attr);
+                break;
+        case KVM_DEV_FLIC_ADAPTER_MODIFY:
+                r = modify_io_adapter(dev, attr);
+                break;
+        default:
+                r = -EINVAL;
+        }
+        return r;
+}
+static int flic_create(struct kvm_device *dev, u32 type)
+{
+        if (!dev)
+                return -EINVAL;
+        if (dev->kvm->arch.flic)
+                return -EINVAL;
+        dev->kvm->arch.flic = dev;
+        return 0;
+}
+static void flic_destroy(struct kvm_device *dev)
+{
+        dev->kvm->arch.flic = NULL;
+        kfree(dev);
+}
+/* s390 floating irq controller (flic) */
+struct kvm_device_ops kvm_flic_ops = {
+        .name = "kvm-flic",
+        .get_attr = flic_get_attr,
+        .set_attr = flic_set_attr,
+        .create = flic_create,
+        .destroy = flic_destroy,
+};
+static unsigned long get_ind_bit(__u64 addr, unsigned long bit_nr, bool swap)
+{
+        unsigned long bit;
+        bit = bit_nr + (addr % PAGE_SIZE) * 8;
+        return swap ? (bit ^ (BITS_PER_LONG - 1)) : bit;
+}
+static struct s390_map_info *get_map_info(struct s390_io_adapter *adapter,
+                                          u64 addr)
+{
+        struct s390_map_info *map;
+        if (!adapter)
+                return NULL;
+        list_for_each_entry(map, &adapter->maps, list) {
+                if (map->guest_addr == addr)
+                        return map;
+        }
+        return NULL;
+}
+static int adapter_indicators_set(struct kvm *kvm,
+                                  struct s390_io_adapter *adapter,
+                                  struct kvm_s390_adapter_int *adapter_int)
+{
+        unsigned long bit;
+        int summary_set, idx;
+        struct s390_map_info *info;
+        void *map;
+        info = get_map_info(adapter, adapter_int->ind_addr);
+        if (!info)
+                return -1;
+        map = page_address(info->page);
+        bit = get_ind_bit(info->addr, adapter_int->ind_offset, adapter->swap);
+        set_bit(bit, map);
+        idx = srcu_read_lock(&kvm->srcu);
+        mark_page_dirty(kvm, info->guest_addr >> PAGE_SHIFT);
+        set_page_dirty_lock(info->page);
+        info = get_map_info(adapter, adapter_int->summary_addr);
+        if (!info) {
+                srcu_read_unlock(&kvm->srcu, idx);
+                return -1;
+        }
+        map = page_address(info->page);
+        bit = get_ind_bit(info->addr, adapter_int->summary_offset,
+                          adapter->swap);
+        summary_set = test_and_set_bit(bit, map);
+        mark_page_dirty(kvm, info->guest_addr >> PAGE_SHIFT);
+        set_page_dirty_lock(info->page);
+        srcu_read_unlock(&kvm->srcu, idx);
+        return summary_set ? 0 : 1;
+}
+/*
+ * < 0 - not injected due to error
+ * = 0 - coalesced, summary indicator already active
+ * > 0 - injected interrupt
+ */
+static int set_adapter_int(struct kvm_kernel_irq_routing_entry *e,
+                           struct kvm *kvm, int irq_source_id, int level,
+                           bool line_status)
+{
+        int ret;
+        struct s390_io_adapter *adapter;
+        /* We're only interested in the 0->1 transition. */
+        if (!level)
+                return 0;
+        adapter = get_io_adapter(kvm, e->adapter.adapter_id);
+        if (!adapter)
+                return -1;
+        down_read(&adapter->maps_lock);
+        ret = adapter_indicators_set(kvm, adapter, &e->adapter);
+        up_read(&adapter->maps_lock);
+        if ((ret > 0) && !adapter->masked) {
+                struct kvm_s390_interrupt s390int = {
+                        .type = KVM_S390_INT_IO(1, 0, 0, 0),
+                        .parm = 0,
+                        .parm64 = (adapter->isc << 27) | 0x80000000,
+                };
+                ret = kvm_s390_inject_vm(kvm, &s390int);
+                if (ret == 0)
+                        ret = 1;
+        }
+        return ret;
+}
+int kvm_set_routing_entry(struct kvm_irq_routing_table *rt,
+                          struct kvm_kernel_irq_routing_entry *e,
+                          const struct kvm_irq_routing_entry *ue)
+{
+        int ret;
+        switch (ue->type) {
+        case KVM_IRQ_ROUTING_S390_ADAPTER:
+                e->set = set_adapter_int;
+                e->adapter.summary_addr = ue->u.adapter.summary_addr;
+                e->adapter.ind_addr = ue->u.adapter.ind_addr;
+                e->adapter.summary_offset = ue->u.adapter.summary_offset;
+                e->adapter.ind_offset = ue->u.adapter.ind_offset;
+                e->adapter.adapter_id = ue->u.adapter.adapter_id;
+                ret = 0;
+                break;
+        default:
+                ret = -EINVAL;
+        }
+        return ret;
+}
+int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, struct kvm *kvm,
+                int irq_source_id, int level, bool line_status)
+{
+        return -EINVAL;
+}
diff --git a/arch/s390/kvm/irq.h b/arch/s390/kvm/irq.h
new file mode 100644
index 000000000000..d98e4159643d
--- /dev/null
+++ b/arch/s390/kvm/irq.h
@@ -0,0 +1,22 @@
+/*
+ * s390 irqchip routines
+ *
+ * Copyright IBM Corp. 2014
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ *    Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
+ */
+#ifndef __KVM_IRQ_H
+#define __KVM_IRQ_H
+#include <linux/kvm_host.h>
+static inline int irqchip_in_kernel(struct kvm *kvm)
+{
+        return 1;
+}
+#endif
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index 10b5db3c9bc4..b3ecb8f5b6ce 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -153,11 +153,14 @@ int kvm_dev_ioctl_check_extension(long ext)
 #ifdef CONFIG_KVM_S390_UCONTROL
        case KVM_CAP_S390_UCONTROL:
 #endif
+        case KVM_CAP_ASYNC_PF:
        case KVM_CAP_SYNC_REGS:
        case KVM_CAP_ONE_REG:
        case KVM_CAP_ENABLE_CAP:
        case KVM_CAP_S390_CSS_SUPPORT:
        case KVM_CAP_IOEVENTFD:
+        case KVM_CAP_DEVICE_CTRL:
+        case KVM_CAP_ENABLE_CAP_VM:
                r = 1;
                break;
        case KVM_CAP_NR_VCPUS:
@@ -186,6 +189,25 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
        return 0;
 }
+static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap)
+{
+        int r;
+        if (cap->flags)
+                return -EINVAL;
+        switch (cap->cap) {
+        case KVM_CAP_S390_IRQCHIP:
+                kvm->arch.use_irqchip = 1;
+                r = 0;
+                break;
+        default:
+                r = -EINVAL;
+                break;
+        }
+        return r;
+}
 long kvm_arch_vm_ioctl(struct file *filp,
                       unsigned int ioctl, unsigned long arg)
 {
@@ -203,6 +225,26 @@ long kvm_arch_vm_ioctl(struct file *filp,
                r = kvm_s390_inject_vm(kvm, &s390int);
                break;
        }
+        case KVM_ENABLE_CAP: {
+                struct kvm_enable_cap cap;
+                r = -EFAULT;
+                if (copy_from_user(&cap, argp, sizeof(cap)))
+                        break;
+                r = kvm_vm_ioctl_enable_cap(kvm, &cap);
+                break;
+        }
+        case KVM_CREATE_IRQCHIP: {
+                struct kvm_irq_routing_entry routing;
+                r = -EINVAL;
+                if (kvm->arch.use_irqchip) {
+                        /* Set up dummy routing. */
+                        memset(&routing, 0, sizeof(routing));
+                        kvm_set_irq_routing(kvm, &routing, 0, 0);
+                        r = 0;
+                }
+                break;
+        }
        default:
                r = -ENOTTY;
        }
@@ -214,6 +256,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 {
        int rc;
        char debug_name[16];
+        static unsigned long sca_offset;
        rc = -EINVAL;
 #ifdef CONFIG_KVM_S390_UCONTROL
@@ -235,6 +278,10 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
        kvm->arch.sca = (struct sca_block *) get_zeroed_page(GFP_KERNEL);
        if (!kvm->arch.sca)
                goto out_err;
+        spin_lock(&kvm_lock);
+        sca_offset = (sca_offset + 16) & 0x7f0;
+        kvm->arch.sca = (struct sca_block *) ((char *) kvm->arch.sca + sca_offset);
+        spin_unlock(&kvm_lock);
        sprintf(debug_name, "kvm-%u", current->pid);
@@ -255,9 +302,11 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
                if (!kvm->arch.gmap)
                        goto out_nogmap;
                kvm->arch.gmap->private = kvm;
+                kvm->arch.gmap->pfault_enabled = 0;
        }
        kvm->arch.css_support = 0;
+        kvm->arch.use_irqchip = 0;
        return 0;
 out_nogmap:
@@ -272,6 +321,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 {
        VCPU_EVENT(vcpu, 3, "%s", "free cpu");
        trace_kvm_s390_destroy_vcpu(vcpu->vcpu_id);
+        kvm_clear_async_pf_completion_queue(vcpu);
        if (!kvm_is_ucontrol(vcpu->kvm)) {
                clear_bit(63 - vcpu->vcpu_id,
                          (unsigned long *) &vcpu->kvm->arch.sca->mcn);
@@ -320,11 +370,14 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
        debug_unregister(kvm->arch.dbf);
        if (!kvm_is_ucontrol(kvm))
                gmap_free(kvm->arch.gmap);
+        kvm_s390_destroy_adapters(kvm);
 }
 /* Section: vcpu related */
 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
 {
+        vcpu->arch.pfault_token = KVM_S390_PFAULT_TOKEN_INVALID;
+        kvm_clear_async_pf_completion_queue(vcpu);
        if (kvm_is_ucontrol(vcpu->kvm)) {
                vcpu->arch.gmap = gmap_alloc(current->mm);
                if (!vcpu->arch.gmap)
@@ -385,7 +438,11 @@ static void kvm_s390_vcpu_initial_reset(struct kvm_vcpu *vcpu)
        vcpu->arch.guest_fpregs.fpc = 0;
        asm volatile("lfpc %0" : : "Q" (vcpu->arch.guest_fpregs.fpc));
        vcpu->arch.sie_block->gbea = 1;
+        vcpu->arch.sie_block->pp = 0;
+        vcpu->arch.pfault_token = KVM_S390_PFAULT_TOKEN_INVALID;
+        kvm_clear_async_pf_completion_queue(vcpu);
        atomic_set_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags);
+        kvm_s390_clear_local_irqs(vcpu);
 }
 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
@@ -466,11 +523,8 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
        spin_lock_init(&vcpu->arch.local_int.lock);
        INIT_LIST_HEAD(&vcpu->arch.local_int.list);
        vcpu->arch.local_int.float_int = &kvm->arch.float_int;
-        spin_lock(&kvm->arch.float_int.lock);
-        kvm->arch.float_int.local_int[id] = &vcpu->arch.local_int;
        vcpu->arch.local_int.wq = &vcpu->wq;
        vcpu->arch.local_int.cpuflags = &vcpu->arch.sie_block->cpuflags;
-        spin_unlock(&kvm->arch.float_int.lock);
        rc = kvm_vcpu_init(vcpu, kvm, id);
        if (rc)
@@ -490,9 +544,7 @@ out:
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 {
-        /* kvm common code refers to this, but never calls it */
+        return kvm_cpu_has_interrupt(vcpu);
-        BUG();
-        return 0;
 }
 void s390_vcpu_block(struct kvm_vcpu *vcpu)
@@ -568,6 +620,26 @@ static int kvm_arch_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu,
                r = put_user(vcpu->arch.sie_block->ckc,
                             (u64 __user *)reg->addr);
                break;
+        case KVM_REG_S390_PFTOKEN:
+                r = put_user(vcpu->arch.pfault_token,
+                             (u64 __user *)reg->addr);
+                break;
+        case KVM_REG_S390_PFCOMPARE:
+                r = put_user(vcpu->arch.pfault_compare,
+                             (u64 __user *)reg->addr);
+                break;
+        case KVM_REG_S390_PFSELECT:
+                r = put_user(vcpu->arch.pfault_select,
+                             (u64 __user *)reg->addr);
+                break;
+        case KVM_REG_S390_PP:
+                r = put_user(vcpu->arch.sie_block->pp,
+                             (u64 __user *)reg->addr);
+                break;
+        case KVM_REG_S390_GBEA:
+                r = put_user(vcpu->arch.sie_block->gbea,
+                             (u64 __user *)reg->addr);
+                break;
        default:
                break;
        }
@@ -597,6 +669,26 @@ static int kvm_arch_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu,
                r = get_user(vcpu->arch.sie_block->ckc,
                             (u64 __user *)reg->addr);
                break;
+        case KVM_REG_S390_PFTOKEN:
+                r = get_user(vcpu->arch.pfault_token,
+                             (u64 __user *)reg->addr);
+                break;
+        case KVM_REG_S390_PFCOMPARE:
+                r = get_user(vcpu->arch.pfault_compare,
+                             (u64 __user *)reg->addr);
+                break;
+        case KVM_REG_S390_PFSELECT:
+                r = get_user(vcpu->arch.pfault_select,
+                             (u64 __user *)reg->addr);
+                break;
+        case KVM_REG_S390_PP:
+                r = get_user(vcpu->arch.sie_block->pp,
+                             (u64 __user *)reg->addr);
+                break;
+        case KVM_REG_S390_GBEA:
+                r = get_user(vcpu->arch.sie_block->gbea,
+                             (u64 __user *)reg->addr);
+                break;
        default:
                break;
        }
@@ -715,10 +807,100 @@ static int kvm_s390_handle_requests(struct kvm_vcpu *vcpu)
        return 0;
 }
+static long kvm_arch_fault_in_sync(struct kvm_vcpu *vcpu)
+{
+        long rc;
+        hva_t fault = gmap_fault(current->thread.gmap_addr, vcpu->arch.gmap);
+        struct mm_struct *mm = current->mm;
+        down_read(&mm->mmap_sem);
+        rc = get_user_pages(current, mm, fault, 1, 1, 0, NULL, NULL);
+        up_read(&mm->mmap_sem);
+        return rc;
+}
+static void __kvm_inject_pfault_token(struct kvm_vcpu *vcpu, bool start_token,
+                                      unsigned long token)
+{
+        struct kvm_s390_interrupt inti;
+        inti.parm64 = token;
+        if (start_token) {
+                inti.type = KVM_S390_INT_PFAULT_INIT;
+                WARN_ON_ONCE(kvm_s390_inject_vcpu(vcpu, &inti));
+        } else {
+                inti.type = KVM_S390_INT_PFAULT_DONE;
+                WARN_ON_ONCE(kvm_s390_inject_vm(vcpu->kvm, &inti));
+        }
+}
+void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
+                                     struct kvm_async_pf *work)
+{
+        trace_kvm_s390_pfault_init(vcpu, work->arch.pfault_token);
+        __kvm_inject_pfault_token(vcpu, true, work->arch.pfault_token);
+}
+void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
+                                 struct kvm_async_pf *work)
+{
+        trace_kvm_s390_pfault_done(vcpu, work->arch.pfault_token);
+        __kvm_inject_pfault_token(vcpu, false, work->arch.pfault_token);
+}
+void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
+                               struct kvm_async_pf *work)
+{
+        /* s390 will always inject the page directly */
+}
+bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
+{
+        /*
+         * s390 will always inject the page directly,
+         * but we still want check_async_completion to cleanup
+         */
+        return true;
+}
+static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu)
+{
+        hva_t hva;
+        struct kvm_arch_async_pf arch;
+        int rc;
+        if (vcpu->arch.pfault_token == KVM_S390_PFAULT_TOKEN_INVALID)
+                return 0;
+        if ((vcpu->arch.sie_block->gpsw.mask & vcpu->arch.pfault_select) !=
+            vcpu->arch.pfault_compare)
+                return 0;
+        if (psw_extint_disabled(vcpu))
+                return 0;
+        if (kvm_cpu_has_interrupt(vcpu))
+                return 0;
+        if (!(vcpu->arch.sie_block->gcr[0] & 0x200ul))
+                return 0;
+        if (!vcpu->arch.gmap->pfault_enabled)
+                return 0;
+        hva = gmap_fault(current->thread.gmap_addr, vcpu->arch.gmap);
+        if (copy_from_guest(vcpu, &arch.pfault_token, vcpu->arch.pfault_token, 8))
+                return 0;
+        rc = kvm_setup_async_pf(vcpu, current->thread.gmap_addr, hva, &arch);
+        return rc;
+}
 static int vcpu_pre_run(struct kvm_vcpu *vcpu)
 {
        int rc, cpuflags;
+        /*
+         * On s390 notifications for arriving pages will be delivered directly
+         * to the guest but the house keeping for completed pfaults is
+         * handled outside the worker.
+         */
+        kvm_check_async_pf_completion(vcpu);
        memcpy(&vcpu->arch.sie_block->gg14, &vcpu->run->s.regs.gprs[14], 16);
        if (need_resched())
@@ -744,7 +926,7 @@ static int vcpu_pre_run(struct kvm_vcpu *vcpu)
 static int vcpu_post_run(struct kvm_vcpu *vcpu, int exit_reason)
 {
-        int rc;
+        int rc = -1;
        VCPU_EVENT(vcpu, 6, "exit sie icptcode %d",
                   vcpu->arch.sie_block->icptcode);
@@ -758,7 +940,16 @@ static int vcpu_post_run(struct kvm_vcpu *vcpu, int exit_reason)
                                                current->thread.gmap_addr;
                vcpu->run->s390_ucontrol.pgm_code = 0x10;
                rc = -EREMOTE;
-        } else {
+        } else if (current->thread.gmap_pfault) {
+                trace_kvm_s390_major_guest_pfault(vcpu);
+                current->thread.gmap_pfault = 0;
+                if (kvm_arch_setup_async_pf(vcpu) ||
+                    (kvm_arch_fault_in_sync(vcpu) >= 0))
+                        rc = 0;
+        }
+        if (rc == -1) {
                VCPU_EVENT(vcpu, 3, "%s", "fault in sie instruction");
                trace_kvm_s390_sie_fault(vcpu);
                rc = kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
@@ -768,7 +959,8 @@ static int vcpu_post_run(struct kvm_vcpu *vcpu, int exit_reason)
        if (rc == 0) {
                if (kvm_is_ucontrol(vcpu->kvm))
-                        rc = -EOPNOTSUPP;
+                        /* Don't exit for host interrupts. */
+                        rc = vcpu->arch.sie_block->icptcode ? -EOPNOTSUPP : 0;
                else
                        rc = kvm_handle_sie_intercept(vcpu);
        }
@@ -831,8 +1023,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        atomic_clear_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags);
-        BUG_ON(vcpu->kvm->arch.float_int.local_int[vcpu->vcpu_id] == NULL);
        switch (kvm_run->exit_reason) {
        case KVM_EXIT_S390_SIEIC:
        case KVM_EXIT_UNKNOWN:
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index 564514f410f4..3c1e2274d9ea 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -129,6 +129,7 @@ enum hrtimer_restart kvm_s390_idle_wakeup(struct hrtimer *timer);
 void kvm_s390_tasklet(unsigned long parm);
 void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu);
 void kvm_s390_deliver_pending_machine_checks(struct kvm_vcpu *vcpu);
+void kvm_s390_clear_local_irqs(struct kvm_vcpu *vcpu);
 int __must_check kvm_s390_inject_vm(struct kvm *kvm,
                                    struct kvm_s390_interrupt *s390int);
 int __must_check kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
@@ -136,6 +137,7 @@ int __must_check kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
 int __must_check kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code);
 struct kvm_s390_interrupt_info *kvm_s390_get_io_int(struct kvm *kvm,
                                                    u64 cr6, u64 schid);
+int kvm_s390_mask_adapter(struct kvm *kvm, unsigned int id, bool masked);
 /* implemented in priv.c */
 int kvm_s390_handle_b2(struct kvm_vcpu *vcpu);
@@ -161,4 +163,9 @@ bool kvm_enabled_cmma(void);
 /* implemented in diag.c */
 int kvm_s390_handle_diag(struct kvm_vcpu *vcpu);
+/* implemented in interrupt.c */
+int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
+int psw_extint_disabled(struct kvm_vcpu *vcpu);
+void kvm_s390_destroy_adapters(struct kvm *kvm);
 #endif
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index aacb6b129914..476e9e218f43 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -396,15 +396,10 @@ static int handle_stidp(struct kvm_vcpu *vcpu)
 static void handle_stsi_3_2_2(struct kvm_vcpu *vcpu, struct sysinfo_3_2_2 *mem)
 {
-        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
        int cpus = 0;
        int n;
-        spin_lock(&fi->lock);
+        cpus = atomic_read(&vcpu->kvm->online_vcpus);
-        for (n = 0; n < KVM_MAX_VCPUS; n++)
-                if (fi->local_int[n])
-                        cpus++;
-        spin_unlock(&fi->lock);
        /* deal with other level 3 hypervisors */
        if (stsi(mem, 3, 2, 2))
diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c
index 87c2b3a3bd3e..26caeb530a78 100644
--- a/arch/s390/kvm/sigp.c
+++ b/arch/s390/kvm/sigp.c
@@ -23,29 +23,30 @@
 static int __sigp_sense(struct kvm_vcpu *vcpu, u16 cpu_addr,
                        u64 *reg)
 {
-        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
+        struct kvm_s390_local_interrupt *li;
+        struct kvm_vcpu *dst_vcpu = NULL;
+        int cpuflags;
        int rc;
        if (cpu_addr >= KVM_MAX_VCPUS)
                return SIGP_CC_NOT_OPERATIONAL;
-        spin_lock(&fi->lock);
+        dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
-        if (fi->local_int[cpu_addr] == NULL)
+        if (!dst_vcpu)
-                rc = SIGP_CC_NOT_OPERATIONAL;
+                return SIGP_CC_NOT_OPERATIONAL;
-        else if (!(atomic_read(fi->local_int[cpu_addr]->cpuflags)
+        li = &dst_vcpu->arch.local_int;
-                   & (CPUSTAT_ECALL_PEND | CPUSTAT_STOPPED)))
+        cpuflags = atomic_read(li->cpuflags);
+        if (!(cpuflags & (CPUSTAT_ECALL_PEND | CPUSTAT_STOPPED)))
                rc = SIGP_CC_ORDER_CODE_ACCEPTED;
        else {
                *reg &= 0xffffffff00000000UL;
-                if (atomic_read(fi->local_int[cpu_addr]->cpuflags)
+                if (cpuflags & CPUSTAT_ECALL_PEND)
-                    & CPUSTAT_ECALL_PEND)
                        *reg |= SIGP_STATUS_EXT_CALL_PENDING;
-                if (atomic_read(fi->local_int[cpu_addr]->cpuflags)
+                if (cpuflags & CPUSTAT_STOPPED)
-                    & CPUSTAT_STOPPED)
                        *reg |= SIGP_STATUS_STOPPED;
                rc = SIGP_CC_STATUS_STORED;
        }
-        spin_unlock(&fi->lock);
        VCPU_EVENT(vcpu, 4, "sensed status of cpu %x rc %x", cpu_addr, rc);
        return rc;
@@ -53,12 +54,13 @@ static int __sigp_sense(struct kvm_vcpu *vcpu, u16 cpu_addr,
 static int __sigp_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr)
 {
-        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
        struct kvm_s390_local_interrupt *li;
        struct kvm_s390_interrupt_info *inti;
-        int rc;
+        struct kvm_vcpu *dst_vcpu = NULL;
-        if (cpu_addr >= KVM_MAX_VCPUS)
+        if (cpu_addr < KVM_MAX_VCPUS)
+                dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
+        if (!dst_vcpu)
                return SIGP_CC_NOT_OPERATIONAL;
        inti = kzalloc(sizeof(*inti), GFP_KERNEL);
@@ -68,13 +70,7 @@ static int __sigp_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr)
        inti->type = KVM_S390_INT_EMERGENCY;
        inti->emerg.code = vcpu->vcpu_id;
-        spin_lock(&fi->lock);
+        li = &dst_vcpu->arch.local_int;
-        li = fi->local_int[cpu_addr];
-        if (li == NULL) {
-                rc = SIGP_CC_NOT_OPERATIONAL;
-                kfree(inti);
-                goto unlock;
-        }
        spin_lock_bh(&li->lock);
        list_add_tail(&inti->list, &li->list);
        atomic_set(&li->active, 1);
@@ -82,11 +78,9 @@ static int __sigp_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr)
        if (waitqueue_active(li->wq))
                wake_up_interruptible(li->wq);
        spin_unlock_bh(&li->lock);
-        rc = SIGP_CC_ORDER_CODE_ACCEPTED;
        VCPU_EVENT(vcpu, 4, "sent sigp emerg to cpu %x", cpu_addr);
-unlock:
-        spin_unlock(&fi->lock);
+        return SIGP_CC_ORDER_CODE_ACCEPTED;
-        return rc;
 }
 static int __sigp_conditional_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr,
@@ -122,12 +116,13 @@ static int __sigp_conditional_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr,
 static int __sigp_external_call(struct kvm_vcpu *vcpu, u16 cpu_addr)
 {
-        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
        struct kvm_s390_local_interrupt *li;
        struct kvm_s390_interrupt_info *inti;
-        int rc;
+        struct kvm_vcpu *dst_vcpu = NULL;
-        if (cpu_addr >= KVM_MAX_VCPUS)
+        if (cpu_addr < KVM_MAX_VCPUS)
+                dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
+        if (!dst_vcpu)
                return SIGP_CC_NOT_OPERATIONAL;
        inti = kzalloc(sizeof(*inti), GFP_KERNEL);
@@ -137,13 +132,7 @@ static int __sigp_external_call(struct kvm_vcpu *vcpu, u16 cpu_addr)
        inti->type = KVM_S390_INT_EXTERNAL_CALL;
        inti->extcall.code = vcpu->vcpu_id;
-        spin_lock(&fi->lock);
+        li = &dst_vcpu->arch.local_int;
-        li = fi->local_int[cpu_addr];
-        if (li == NULL) {
-                rc = SIGP_CC_NOT_OPERATIONAL;
-                kfree(inti);
-                goto unlock;
-        }
        spin_lock_bh(&li->lock);
        list_add_tail(&inti->list, &li->list);
        atomic_set(&li->active, 1);
@@ -151,11 +140,9 @@ static int __sigp_external_call(struct kvm_vcpu *vcpu, u16 cpu_addr)
        if (waitqueue_active(li->wq))
                wake_up_interruptible(li->wq);
        spin_unlock_bh(&li->lock);
-        rc = SIGP_CC_ORDER_CODE_ACCEPTED;
        VCPU_EVENT(vcpu, 4, "sent sigp ext call to cpu %x", cpu_addr);
-unlock:
-        spin_unlock(&fi->lock);
+        return SIGP_CC_ORDER_CODE_ACCEPTED;
-        return rc;
 }
 static int __inject_sigp_stop(struct kvm_s390_local_interrupt *li, int action)
@@ -189,31 +176,26 @@ out:
 static int __sigp_stop(struct kvm_vcpu *vcpu, u16 cpu_addr, int action)
 {
-        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
        struct kvm_s390_local_interrupt *li;
+        struct kvm_vcpu *dst_vcpu = NULL;
        int rc;
        if (cpu_addr >= KVM_MAX_VCPUS)
                return SIGP_CC_NOT_OPERATIONAL;
-        spin_lock(&fi->lock);
+        dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
-        li = fi->local_int[cpu_addr];
+        if (!dst_vcpu)
-        if (li == NULL) {
+                return SIGP_CC_NOT_OPERATIONAL;
-                rc = SIGP_CC_NOT_OPERATIONAL;
+        li = &dst_vcpu->arch.local_int;
-                goto unlock;
-        }
        rc = __inject_sigp_stop(li, action);
-unlock:
-        spin_unlock(&fi->lock);
        VCPU_EVENT(vcpu, 4, "sent sigp stop to cpu %x", cpu_addr);
        if ((action & ACTION_STORE_ON_STOP) != 0 && rc == -ESHUTDOWN) {
                /* If the CPU has already been stopped, we still have
                 * to save the status when doing stop-and-store. This
                 * has to be done after unlocking all spinlocks. */
-                struct kvm_vcpu *dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
                rc = kvm_s390_store_status_unloaded(dst_vcpu,
                                                KVM_S390_STORE_STATUS_NOADDR);
        }
@@ -224,6 +206,8 @@ unlock:
 static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter)
 {
        int rc;
+        unsigned int i;
+        struct kvm_vcpu *v;
        switch (parameter & 0xff) {
        case 0:
@@ -231,6 +215,11 @@ static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter)
                break;
        case 1:
        case 2:
+                kvm_for_each_vcpu(i, v, vcpu->kvm) {
+                        v->arch.pfault_token = KVM_S390_PFAULT_TOKEN_INVALID;
+                        kvm_clear_async_pf_completion_queue(v);
+                }
                rc = SIGP_CC_ORDER_CODE_ACCEPTED;
                break;
        default:
@@ -242,12 +231,18 @@ static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter)
 static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
                             u64 *reg)
 {
-        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
+        struct kvm_s390_local_interrupt *li;
-        struct kvm_s390_local_interrupt *li = NULL;
+        struct kvm_vcpu *dst_vcpu = NULL;
        struct kvm_s390_interrupt_info *inti;
        int rc;
        u8 tmp;
+        if (cpu_addr < KVM_MAX_VCPUS)
+                dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
+        if (!dst_vcpu)
+                return SIGP_CC_NOT_OPERATIONAL;
+        li = &dst_vcpu->arch.local_int;
        /* make sure that the new value is valid memory */
        address = address & 0x7fffe000u;
        if (copy_from_guest_absolute(vcpu, &tmp, address, 1) ||
@@ -261,18 +256,6 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
        if (!inti)
                return SIGP_CC_BUSY;
-        spin_lock(&fi->lock);
-        if (cpu_addr < KVM_MAX_VCPUS)
-                li = fi->local_int[cpu_addr];
-        if (li == NULL) {
-                *reg &= 0xffffffff00000000UL;
-                *reg |= SIGP_STATUS_INCORRECT_STATE;
-                rc = SIGP_CC_STATUS_STORED;
-                kfree(inti);
-                goto out_fi;
-        }
        spin_lock_bh(&li->lock);
        /* cpu must be in stopped state */
        if (!(atomic_read(li->cpuflags) & CPUSTAT_STOPPED)) {
@@ -295,8 +278,6 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
        VCPU_EVENT(vcpu, 4, "set prefix of cpu %02x to %x", cpu_addr, address);
 out_li:
        spin_unlock_bh(&li->lock);
-out_fi:
-        spin_unlock(&fi->lock);
        return rc;
 }
@@ -334,28 +315,26 @@ static int __sigp_store_status_at_addr(struct kvm_vcpu *vcpu, u16 cpu_id,
 static int __sigp_sense_running(struct kvm_vcpu *vcpu, u16 cpu_addr,
                                u64 *reg)
 {
+        struct kvm_s390_local_interrupt *li;
+        struct kvm_vcpu *dst_vcpu = NULL;
        int rc;
-        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
        if (cpu_addr >= KVM_MAX_VCPUS)
                return SIGP_CC_NOT_OPERATIONAL;
-        spin_lock(&fi->lock);
+        dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
-        if (fi->local_int[cpu_addr] == NULL)
+        if (!dst_vcpu)
-                rc = SIGP_CC_NOT_OPERATIONAL;
+                return SIGP_CC_NOT_OPERATIONAL;
-        else {
+        li = &dst_vcpu->arch.local_int;
-                if (atomic_read(fi->local_int[cpu_addr]->cpuflags)
+        if (atomic_read(li->cpuflags) & CPUSTAT_RUNNING) {
-                    & CPUSTAT_RUNNING) {
+                /* running */
-                        /* running */
+                rc = SIGP_CC_ORDER_CODE_ACCEPTED;
-                        rc = SIGP_CC_ORDER_CODE_ACCEPTED;
+        } else {
-                } else {
+                /* not running */
-                        /* not running */
+                *reg &= 0xffffffff00000000UL;
-                        *reg &= 0xffffffff00000000UL;
+                *reg |= SIGP_STATUS_NOT_RUNNING;
-                        *reg |= SIGP_STATUS_NOT_RUNNING;
+                rc = SIGP_CC_STATUS_STORED;
-                        rc = SIGP_CC_STATUS_STORED;
-                }
        }
-        spin_unlock(&fi->lock);
        VCPU_EVENT(vcpu, 4, "sensed running status of cpu %x rc %x", cpu_addr,
                   rc);
@@ -366,26 +345,22 @@ static int __sigp_sense_running(struct kvm_vcpu *vcpu, u16 cpu_addr,
 /* Test whether the destination CPU is available and not busy */
 static int sigp_check_callable(struct kvm_vcpu *vcpu, u16 cpu_addr)
 {
-        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
        struct kvm_s390_local_interrupt *li;
        int rc = SIGP_CC_ORDER_CODE_ACCEPTED;
+        struct kvm_vcpu *dst_vcpu = NULL;
        if (cpu_addr >= KVM_MAX_VCPUS)
                return SIGP_CC_NOT_OPERATIONAL;
-        spin_lock(&fi->lock);
+        dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr);
-        li = fi->local_int[cpu_addr];
+        if (!dst_vcpu)
-        if (li == NULL) {
+                return SIGP_CC_NOT_OPERATIONAL;
-                rc = SIGP_CC_NOT_OPERATIONAL;
+        li = &dst_vcpu->arch.local_int;
-                goto out;
-        }
        spin_lock_bh(&li->lock);
        if (li->action_bits & ACTION_STOP_ON_STOP)
                rc = SIGP_CC_BUSY;
        spin_unlock_bh(&li->lock);
-out:
-        spin_unlock(&fi->lock);
        return rc;
 }
diff --git a/arch/s390/kvm/trace.h b/arch/s390/kvm/trace.h
index 3db76b2daed7..e8e7213d4cc5 100644
--- a/arch/s390/kvm/trace.h
+++ b/arch/s390/kvm/trace.h
@@ -30,6 +30,52 @@
        TP_printk("%02d[%016lx-%016lx]: " p_str, __entry->id,           \
                  __entry->pswmask, __entry->pswaddr, p_args)
+TRACE_EVENT(kvm_s390_major_guest_pfault,
+            TP_PROTO(VCPU_PROTO_COMMON),
+            TP_ARGS(VCPU_ARGS_COMMON),
+            TP_STRUCT__entry(
+                    VCPU_FIELD_COMMON
+                    ),
+            TP_fast_assign(
+                    VCPU_ASSIGN_COMMON
+                    ),
+            VCPU_TP_PRINTK("%s", "major fault, maybe applicable for pfault")
+        );
+TRACE_EVENT(kvm_s390_pfault_init,
+            TP_PROTO(VCPU_PROTO_COMMON, long pfault_token),
+            TP_ARGS(VCPU_ARGS_COMMON, pfault_token),
+            TP_STRUCT__entry(
+                    VCPU_FIELD_COMMON
+                    __field(long, pfault_token)
+                    ),
+            TP_fast_assign(
+                    VCPU_ASSIGN_COMMON
+                    __entry->pfault_token = pfault_token;
+                    ),
+            VCPU_TP_PRINTK("init pfault token %ld", __entry->pfault_token)
+        );
+TRACE_EVENT(kvm_s390_pfault_done,
+            TP_PROTO(VCPU_PROTO_COMMON, long pfault_token),
+            TP_ARGS(VCPU_ARGS_COMMON, pfault_token),
+            TP_STRUCT__entry(
+                    VCPU_FIELD_COMMON
+                    __field(long, pfault_token)
+                    ),
+            TP_fast_assign(
+                    VCPU_ASSIGN_COMMON
+                    __entry->pfault_token = pfault_token;
+                    ),
+            VCPU_TP_PRINTK("done pfault token %ld", __entry->pfault_token)
+        );
 /*
 * Tracepoints for SIE entry and exit.
 */
diff --git a/arch/s390/lib/Makefile b/arch/s390/lib/Makefile
index e3fffe1dff51..c6d752e8bf28 100644
--- a/arch/s390/lib/Makefile
+++ b/arch/s390/lib/Makefile
@@ -2,7 +2,7 @@
 # Makefile for s390-specific library files..
 #
-lib-y += delay.o string.o uaccess_pt.o uaccess_mvcos.o find.o
+lib-y += delay.o string.o uaccess.o find.o
 obj-$(CONFIG_32BIT) += div64.o qrnnd.o ucmpdi2.o mem32.o
 obj-$(CONFIG_64BIT) += mem64.o
 lib-$(CONFIG_SMP) += spinlock.o
diff --git a/arch/s390/lib/uaccess.c b/arch/s390/lib/uaccess.c
new file mode 100644
index 000000000000..23f866b4c7f1
--- /dev/null
+++ b/arch/s390/lib/uaccess.c
@@ -0,0 +1,407 @@
+/*
+ *  Standard user space access functions based on mvcp/mvcs and doing
+ *  interesting things in the secondary space mode.
+ *
+ *    Copyright IBM Corp. 2006,2014
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
+ *               Gerald Schaefer (gerald.schaefer@de.ibm.com)
+ */
+#include <linux/jump_label.h>
+#include <linux/uaccess.h>
+#include <linux/export.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <asm/mmu_context.h>
+#include <asm/facility.h>
+#ifndef CONFIG_64BIT
+#define AHI     "ahi"
+#define ALR     "alr"
+#define CLR     "clr"
+#define LHI     "lhi"
+#define SLR     "slr"
+#else
+#define AHI     "aghi"
+#define ALR     "algr"
+#define CLR     "clgr"
+#define LHI     "lghi"
+#define SLR     "slgr"
+#endif
+static struct static_key have_mvcos = STATIC_KEY_INIT_FALSE;
+static inline unsigned long copy_from_user_mvcos(void *x, const void __user *ptr,
+                                                 unsigned long size)
+{
+        register unsigned long reg0 asm("0") = 0x81UL;
+        unsigned long tmp1, tmp2;
+        tmp1 = -4096UL;
+        asm volatile(
+                "0: .insn ss,0xc80000000000,0(%0,%2),0(%1),0\n"
+                "9: jz    7f\n"
+                "1:"ALR"  %0,%3\n"
+                "  "SLR"  %1,%3\n"
+                "  "SLR"  %2,%3\n"
+                "   j     0b\n"
+                "2: la    %4,4095(%1)\n"/* %4 = ptr + 4095 */
+                "   nr    %4,%3\n"      /* %4 = (ptr + 4095) & -4096 */
+                "  "SLR"  %4,%1\n"
+                "  "CLR"  %0,%4\n"      /* copy crosses next page boundary? */
+                "   jnh   4f\n"
+                "3: .insn ss,0xc80000000000,0(%4,%2),0(%1),0\n"
+                "10:"SLR"  %0,%4\n"
+                "  "ALR"  %2,%4\n"
+                "4:"LHI"  %4,-1\n"
+                "  "ALR"  %4,%0\n"      /* copy remaining size, subtract 1 */
+                "   bras  %3,6f\n"      /* memset loop */
+                "   xc    0(1,%2),0(%2)\n"
+                "5: xc    0(256,%2),0(%2)\n"
+                "   la    %2,256(%2)\n"
+                "6:"AHI"  %4,-256\n"
+                "   jnm   5b\n"
+                "   ex    %4,0(%3)\n"
+                "   j     8f\n"
+                "7:"SLR"  %0,%0\n"
+                "8:\n"
+                EX_TABLE(0b,2b) EX_TABLE(3b,4b) EX_TABLE(9b,2b) EX_TABLE(10b,4b)
+                : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2)
+                : "d" (reg0) : "cc", "memory");
+        return size;
+}
+static inline unsigned long copy_from_user_mvcp(void *x, const void __user *ptr,
+                                                unsigned long size)
+{
+        unsigned long tmp1, tmp2;
+        update_primary_asce(current);
+        tmp1 = -256UL;
+        asm volatile(
+                "   sacf  0\n"
+                "0: mvcp  0(%0,%2),0(%1),%3\n"
+                "10:jz    8f\n"
+                "1:"ALR"  %0,%3\n"
+                "   la    %1,256(%1)\n"
+                "   la    %2,256(%2)\n"
+                "2: mvcp  0(%0,%2),0(%1),%3\n"
+                "11:jnz   1b\n"
+                "   j     8f\n"
+                "3: la    %4,255(%1)\n" /* %4 = ptr + 255 */
+                "  "LHI"  %3,-4096\n"
+                "   nr    %4,%3\n"      /* %4 = (ptr + 255) & -4096 */
+                "  "SLR"  %4,%1\n"
+                "  "CLR"  %0,%4\n"      /* copy crosses next page boundary? */
+                "   jnh   5f\n"
+                "4: mvcp  0(%4,%2),0(%1),%3\n"
+                "12:"SLR"  %0,%4\n"
+                "  "ALR"  %2,%4\n"
+                "5:"LHI"  %4,-1\n"
+                "  "ALR"  %4,%0\n"      /* copy remaining size, subtract 1 */
+                "   bras  %3,7f\n"      /* memset loop */
+                "   xc    0(1,%2),0(%2)\n"
+                "6: xc    0(256,%2),0(%2)\n"
+                "   la    %2,256(%2)\n"
+                "7:"AHI"  %4,-256\n"
+                "   jnm   6b\n"
+                "   ex    %4,0(%3)\n"
+                "   j     9f\n"
+                "8:"SLR"  %0,%0\n"
+                "9: sacf  768\n"
+                EX_TABLE(0b,3b) EX_TABLE(2b,3b) EX_TABLE(4b,5b)
+                EX_TABLE(10b,3b) EX_TABLE(11b,3b) EX_TABLE(12b,5b)
+                : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2)
+                : : "cc", "memory");
+        return size;
+}
+unsigned long __copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        if (static_key_false(&have_mvcos))
+                return copy_from_user_mvcos(to, from, n);
+        return copy_from_user_mvcp(to, from, n);
+}
+EXPORT_SYMBOL(__copy_from_user);
+static inline unsigned long copy_to_user_mvcos(void __user *ptr, const void *x,
+                                               unsigned long size)
+{
+        register unsigned long reg0 asm("0") = 0x810000UL;
+        unsigned long tmp1, tmp2;
+        tmp1 = -4096UL;
+        asm volatile(
+                "0: .insn ss,0xc80000000000,0(%0,%1),0(%2),0\n"
+                "6: jz    4f\n"
+                "1:"ALR"  %0,%3\n"
+                "  "SLR"  %1,%3\n"
+                "  "SLR"  %2,%3\n"
+                "   j     0b\n"
+                "2: la    %4,4095(%1)\n"/* %4 = ptr + 4095 */
+                "   nr    %4,%3\n"      /* %4 = (ptr + 4095) & -4096 */
+                "  "SLR"  %4,%1\n"
+                "  "CLR"  %0,%4\n"      /* copy crosses next page boundary? */
+                "   jnh   5f\n"
+                "3: .insn ss,0xc80000000000,0(%4,%1),0(%2),0\n"
+                "7:"SLR"  %0,%4\n"
+                "   j     5f\n"
+                "4:"SLR"  %0,%0\n"
+                "5:\n"
+                EX_TABLE(0b,2b) EX_TABLE(3b,5b) EX_TABLE(6b,2b) EX_TABLE(7b,5b)
+                : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2)
+                : "d" (reg0) : "cc", "memory");
+        return size;
+}
+static inline unsigned long copy_to_user_mvcs(void __user *ptr, const void *x,
+                                              unsigned long size)
+{
+        unsigned long tmp1, tmp2;
+        update_primary_asce(current);
+        tmp1 = -256UL;
+        asm volatile(
+                "   sacf  0\n"
+                "0: mvcs  0(%0,%1),0(%2),%3\n"
+                "7: jz    5f\n"
+                "1:"ALR"  %0,%3\n"
+                "   la    %1,256(%1)\n"
+                "   la    %2,256(%2)\n"
+                "2: mvcs  0(%0,%1),0(%2),%3\n"
+                "8: jnz   1b\n"
+                "   j     5f\n"
+                "3: la    %4,255(%1)\n" /* %4 = ptr + 255 */
+                "  "LHI"  %3,-4096\n"
+                "   nr    %4,%3\n"      /* %4 = (ptr + 255) & -4096 */
+                "  "SLR"  %4,%1\n"
+                "  "CLR"  %0,%4\n"      /* copy crosses next page boundary? */
+                "   jnh   6f\n"
+                "4: mvcs  0(%4,%1),0(%2),%3\n"
+                "9:"SLR"  %0,%4\n"
+                "   j     6f\n"
+                "5:"SLR"  %0,%0\n"
+                "6: sacf  768\n"
+                EX_TABLE(0b,3b) EX_TABLE(2b,3b) EX_TABLE(4b,6b)
+                EX_TABLE(7b,3b) EX_TABLE(8b,3b) EX_TABLE(9b,6b)
+                : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2)
+                : : "cc", "memory");
+        return size;
+}
+unsigned long __copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        if (static_key_false(&have_mvcos))
+                return copy_to_user_mvcos(to, from, n);
+        return copy_to_user_mvcs(to, from, n);
+}
+EXPORT_SYMBOL(__copy_to_user);
+static inline unsigned long copy_in_user_mvcos(void __user *to, const void __user *from,
+                                               unsigned long size)
+{
+        register unsigned long reg0 asm("0") = 0x810081UL;
+        unsigned long tmp1, tmp2;
+        tmp1 = -4096UL;
+        /* FIXME: copy with reduced length. */
+        asm volatile(
+                "0: .insn ss,0xc80000000000,0(%0,%1),0(%2),0\n"
+                "   jz    2f\n"
+                "1:"ALR"  %0,%3\n"
+                "  "SLR"  %1,%3\n"
+                "  "SLR"  %2,%3\n"
+                "   j     0b\n"
+                "2:"SLR"  %0,%0\n"
+                "3: \n"
+                EX_TABLE(0b,3b)
+                : "+a" (size), "+a" (to), "+a" (from), "+a" (tmp1), "=a" (tmp2)
+                : "d" (reg0) : "cc", "memory");
+        return size;
+}
+static inline unsigned long copy_in_user_mvc(void __user *to, const void __user *from,
+                                             unsigned long size)
+{
+        unsigned long tmp1;
+        update_primary_asce(current);
+        asm volatile(
+                "   sacf  256\n"
+                "  "AHI"  %0,-1\n"
+                "   jo    5f\n"
+                "   bras  %3,3f\n"
+                "0:"AHI"  %0,257\n"
+                "1: mvc   0(1,%1),0(%2)\n"
+                "   la    %1,1(%1)\n"
+                "   la    %2,1(%2)\n"
+                "  "AHI"  %0,-1\n"
+                "   jnz   1b\n"
+                "   j     5f\n"
+                "2: mvc   0(256,%1),0(%2)\n"
+                "   la    %1,256(%1)\n"
+                "   la    %2,256(%2)\n"
+                "3:"AHI"  %0,-256\n"
+                "   jnm   2b\n"
+                "4: ex    %0,1b-0b(%3)\n"
+                "5: "SLR"  %0,%0\n"
+                "6: sacf  768\n"
+                EX_TABLE(1b,6b) EX_TABLE(2b,0b) EX_TABLE(4b,0b)
+                : "+a" (size), "+a" (to), "+a" (from), "=a" (tmp1)
+                : : "cc", "memory");
+        return size;
+}
+unsigned long __copy_in_user(void __user *to, const void __user *from, unsigned long n)
+{
+        if (static_key_false(&have_mvcos))
+                return copy_in_user_mvcos(to, from, n);
+        return copy_in_user_mvc(to, from, n);
+}
+EXPORT_SYMBOL(__copy_in_user);
+static inline unsigned long clear_user_mvcos(void __user *to, unsigned long size)
+{
+        register unsigned long reg0 asm("0") = 0x810000UL;
+        unsigned long tmp1, tmp2;
+        tmp1 = -4096UL;
+        asm volatile(
+                "0: .insn ss,0xc80000000000,0(%0,%1),0(%4),0\n"
+                "   jz    4f\n"
+                "1:"ALR"  %0,%2\n"
+                "  "SLR"  %1,%2\n"
+                "   j     0b\n"
+                "2: la    %3,4095(%1)\n"/* %4 = to + 4095 */
+                "   nr    %3,%2\n"      /* %4 = (to + 4095) & -4096 */
+                "  "SLR"  %3,%1\n"
+                "  "CLR"  %0,%3\n"      /* copy crosses next page boundary? */
+                "   jnh   5f\n"
+                "3: .insn ss,0xc80000000000,0(%3,%1),0(%4),0\n"
+                "  "SLR"  %0,%3\n"
+                "   j     5f\n"
+                "4:"SLR"  %0,%0\n"
+                "5:\n"
+                EX_TABLE(0b,2b) EX_TABLE(3b,5b)
+                : "+a" (size), "+a" (to), "+a" (tmp1), "=a" (tmp2)
+                : "a" (empty_zero_page), "d" (reg0) : "cc", "memory");
+        return size;
+}
+static inline unsigned long clear_user_xc(void __user *to, unsigned long size)
+{
+        unsigned long tmp1, tmp2;
+        update_primary_asce(current);
+        asm volatile(
+                "   sacf  256\n"
+                "  "AHI"  %0,-1\n"
+                "   jo    5f\n"
+                "   bras  %3,3f\n"
+                "   xc    0(1,%1),0(%1)\n"
+                "0:"AHI"  %0,257\n"
+                "   la    %2,255(%1)\n" /* %2 = ptr + 255 */
+                "   srl   %2,12\n"
+                "   sll   %2,12\n"      /* %2 = (ptr + 255) & -4096 */
+                "  "SLR"  %2,%1\n"
+                "  "CLR"  %0,%2\n"      /* clear crosses next page boundary? */
+                "   jnh   5f\n"
+                "  "AHI"  %2,-1\n"
+                "1: ex    %2,0(%3)\n"
+                "  "AHI"  %2,1\n"
+                "  "SLR"  %0,%2\n"
+                "   j     5f\n"
+                "2: xc    0(256,%1),0(%1)\n"
+                "   la    %1,256(%1)\n"
+                "3:"AHI"  %0,-256\n"
+                "   jnm   2b\n"
+                "4: ex    %0,0(%3)\n"
+                "5: "SLR"  %0,%0\n"
+                "6: sacf  768\n"
+                EX_TABLE(1b,6b) EX_TABLE(2b,0b) EX_TABLE(4b,0b)
+                : "+a" (size), "+a" (to), "=a" (tmp1), "=a" (tmp2)
+                : : "cc", "memory");
+        return size;
+}
+unsigned long __clear_user(void __user *to, unsigned long size)
+{
+        if (static_key_false(&have_mvcos))
+                        return clear_user_mvcos(to, size);
+        return clear_user_xc(to, size);
+}
+EXPORT_SYMBOL(__clear_user);
+static inline unsigned long strnlen_user_srst(const char __user *src,
+                                              unsigned long size)
+{
+        register unsigned long reg0 asm("0") = 0;
+        unsigned long tmp1, tmp2;
+        if (unlikely(!size))
+                return 0;
+        update_primary_asce(current);
+        asm volatile(
+                "   la    %2,0(%1)\n"
+                "   la    %3,0(%0,%1)\n"
+                "  "SLR"  %0,%0\n"
+                "   sacf  256\n"
+                "0: srst  %3,%2\n"
+                "   jo    0b\n"
+                "   la    %0,1(%3)\n"   /* strnlen_user results includes \0 */
+                "  "SLR"  %0,%1\n"
+                "1: sacf  768\n"
+                EX_TABLE(0b,1b)
+                : "+a" (size), "+a" (src), "=a" (tmp1), "=a" (tmp2)
+                : "d" (reg0) : "cc", "memory");
+        return size;
+}
+unsigned long __strnlen_user(const char __user *src, unsigned long size)
+{
+        update_primary_asce(current);
+        return strnlen_user_srst(src, size);
+}
+EXPORT_SYMBOL(__strnlen_user);
+long __strncpy_from_user(char *dst, const char __user *src, long size)
+{
+        size_t done, len, offset, len_str;
+        if (unlikely(size <= 0))
+                return 0;
+        done = 0;
+        do {
+                offset = (size_t)src & ~PAGE_MASK;
+                len = min(size - done, PAGE_SIZE - offset);
+                if (copy_from_user(dst, src, len))
+                        return -EFAULT;
+                len_str = strnlen(dst, len);
+                done += len_str;
+                src += len_str;
+                dst += len_str;
+        } while ((len_str == len) && (done < size));
+        return done;
+}
+EXPORT_SYMBOL(__strncpy_from_user);
+/*
+ * The "old" uaccess variant without mvcos can be enforced with the
+ * uaccess_primary kernel parameter. This is mainly for debugging purposes.
+ */
+static int uaccess_primary __initdata;
+static int __init parse_uaccess_pt(char *__unused)
+{
+        uaccess_primary = 1;
+        return 0;
+}
+early_param("uaccess_primary", parse_uaccess_pt);
+static int __init uaccess_init(void)
+{
+        if (IS_ENABLED(CONFIG_64BIT) && !uaccess_primary && test_facility(27))
+                static_key_slow_inc(&have_mvcos);
+        return 0;
+}
+early_initcall(uaccess_init);
diff --git a/arch/s390/lib/uaccess.h b/arch/s390/lib/uaccess.h
deleted file mode 100644
index c7e0e81f4b4e..000000000000
--- a/arch/s390/lib/uaccess.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *    Copyright IBM Corp. 2007
- *
- */
-#ifndef __ARCH_S390_LIB_UACCESS_H
-#define __ARCH_S390_LIB_UACCESS_H
-unsigned long copy_from_user_pt(void *to, const void __user *from, unsigned long n);
-unsigned long copy_to_user_pt(void __user *to, const void *from, unsigned long n);
-unsigned long copy_in_user_pt(void __user *to, const void __user *from, unsigned long n);
-unsigned long clear_user_pt(void __user *to, unsigned long n);
-unsigned long strnlen_user_pt(const char __user *src, unsigned long count);
-long strncpy_from_user_pt(char *dst, const char __user *src, long count);
-#endif /* __ARCH_S390_LIB_UACCESS_H */
diff --git a/arch/s390/lib/uaccess_mvcos.c b/arch/s390/lib/uaccess_mvcos.c
deleted file mode 100644
index ae97b8df11aa..000000000000
--- a/arch/s390/lib/uaccess_mvcos.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- *  Optimized user space space access functions based on mvcos.
- *
- *    Copyright IBM Corp. 2006
- *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
- *               Gerald Schaefer (gerald.schaefer@de.ibm.com)
- */
-#include <linux/jump_label.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <asm/facility.h>
-#include <asm/uaccess.h>
-#include <asm/futex.h>
-#include "uaccess.h"
-#ifndef CONFIG_64BIT
-#define AHI     "ahi"
-#define ALR     "alr"
-#define CLR     "clr"
-#define LHI     "lhi"
-#define SLR     "slr"
-#else
-#define AHI     "aghi"
-#define ALR     "algr"
-#define CLR     "clgr"
-#define LHI     "lghi"
-#define SLR     "slgr"
-#endif
-static struct static_key have_mvcos = STATIC_KEY_INIT_TRUE;
-static inline unsigned long copy_from_user_mvcos(void *x, const void __user *ptr,
-                                                 unsigned long size)
-{
-        register unsigned long reg0 asm("0") = 0x81UL;
-        unsigned long tmp1, tmp2;
-        tmp1 = -4096UL;
-        asm volatile(
-                "0: .insn ss,0xc80000000000,0(%0,%2),0(%1),0\n"
-                "9: jz    7f\n"
-                "1:"ALR"  %0,%3\n"
-                "  "SLR"  %1,%3\n"
-                "  "SLR"  %2,%3\n"
-                "   j     0b\n"
-                "2: la    %4,4095(%1)\n"/* %4 = ptr + 4095 */
-                "   nr    %4,%3\n"      /* %4 = (ptr + 4095) & -4096 */
-                "  "SLR"  %4,%1\n"
-                "  "CLR"  %0,%4\n"      /* copy crosses next page boundary? */
-                "   jnh   4f\n"
-                "3: .insn ss,0xc80000000000,0(%4,%2),0(%1),0\n"
-                "10:"SLR"  %0,%4\n"
-                "  "ALR"  %2,%4\n"
-                "4:"LHI"  %4,-1\n"
-                "  "ALR"  %4,%0\n"      /* copy remaining size, subtract 1 */
-                "   bras  %3,6f\n"      /* memset loop */
-                "   xc    0(1,%2),0(%2)\n"
-                "5: xc    0(256,%2),0(%2)\n"
-                "   la    %2,256(%2)\n"
-                "6:"AHI"  %4,-256\n"
-                "   jnm   5b\n"
-                "   ex    %4,0(%3)\n"
-                "   j     8f\n"
-                "7:"SLR"  %0,%0\n"
-                "8: \n"
-                EX_TABLE(0b,2b) EX_TABLE(3b,4b) EX_TABLE(9b,2b) EX_TABLE(10b,4b)
-                : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2)
-                : "d" (reg0) : "cc", "memory");
-        return size;
-}
-unsigned long __copy_from_user(void *to, const void __user *from, unsigned long n)
-{
-        if (static_key_true(&have_mvcos))
-                return copy_from_user_mvcos(to, from, n);
-        return copy_from_user_pt(to, from, n);
-}
-EXPORT_SYMBOL(__copy_from_user);
-static inline unsigned long copy_to_user_mvcos(void __user *ptr, const void *x,
-                                               unsigned long size)
-{
-        register unsigned long reg0 asm("0") = 0x810000UL;
-        unsigned long tmp1, tmp2;
-        tmp1 = -4096UL;
-        asm volatile(
-                "0: .insn ss,0xc80000000000,0(%0,%1),0(%2),0\n"
-                "6: jz    4f\n"
-                "1:"ALR"  %0,%3\n"
-                "  "SLR"  %1,%3\n"
-                "  "SLR"  %2,%3\n"
-                "   j     0b\n"
-                "2: la    %4,4095(%1)\n"/* %4 = ptr + 4095 */
-                "   nr    %4,%3\n"      /* %4 = (ptr + 4095) & -4096 */
-                "  "SLR"  %4,%1\n"
-                "  "CLR"  %0,%4\n"      /* copy crosses next page boundary? */
-                "   jnh   5f\n"
-                "3: .insn ss,0xc80000000000,0(%4,%1),0(%2),0\n"
-                "7:"SLR"  %0,%4\n"
-                "   j     5f\n"
-                "4:"SLR"  %0,%0\n"
-                "5: \n"
-                EX_TABLE(0b,2b) EX_TABLE(3b,5b) EX_TABLE(6b,2b) EX_TABLE(7b,5b)
-                : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2)
-                : "d" (reg0) : "cc", "memory");
-        return size;
-}
-unsigned long __copy_to_user(void __user *to, const void *from, unsigned long n)
-{
-        if (static_key_true(&have_mvcos))
-                return copy_to_user_mvcos(to, from, n);
-        return copy_to_user_pt(to, from, n);
-}
-EXPORT_SYMBOL(__copy_to_user);
-static inline unsigned long copy_in_user_mvcos(void __user *to, const void __user *from,
-                                               unsigned long size)
-{
-        register unsigned long reg0 asm("0") = 0x810081UL;
-        unsigned long tmp1, tmp2;
-        tmp1 = -4096UL;
-        /* FIXME: copy with reduced length. */
-        asm volatile(
-                "0: .insn ss,0xc80000000000,0(%0,%1),0(%2),0\n"
-                "   jz    2f\n"
-                "1:"ALR"  %0,%3\n"
-                "  "SLR"  %1,%3\n"
-                "  "SLR"  %2,%3\n"
-                "   j     0b\n"
-                "2:"SLR"  %0,%0\n"
-                "3: \n"
-                EX_TABLE(0b,3b)
-                : "+a" (size), "+a" (to), "+a" (from), "+a" (tmp1), "=a" (tmp2)
-                : "d" (reg0) : "cc", "memory");
-        return size;
-}
-unsigned long __copy_in_user(void __user *to, const void __user *from, unsigned long n)
-{
-        if (static_key_true(&have_mvcos))
-                return copy_in_user_mvcos(to, from, n);
-        return copy_in_user_pt(to, from, n);
-}
-EXPORT_SYMBOL(__copy_in_user);
-static inline unsigned long clear_user_mvcos(void __user *to, unsigned long size)
-{
-        register unsigned long reg0 asm("0") = 0x810000UL;
-        unsigned long tmp1, tmp2;
-        tmp1 = -4096UL;
-        asm volatile(
-                "0: .insn ss,0xc80000000000,0(%0,%1),0(%4),0\n"
-                "   jz    4f\n"
-                "1:"ALR"  %0,%2\n"
-                "  "SLR"  %1,%2\n"
-                "   j     0b\n"
-                "2: la    %3,4095(%1)\n"/* %4 = to + 4095 */
-                "   nr    %3,%2\n"      /* %4 = (to + 4095) & -4096 */
-                "  "SLR"  %3,%1\n"
-                "  "CLR"  %0,%3\n"      /* copy crosses next page boundary? */
-                "   jnh   5f\n"
-                "3: .insn ss,0xc80000000000,0(%3,%1),0(%4),0\n"
-                "  "SLR"  %0,%3\n"
-                "   j     5f\n"
-                "4:"SLR"  %0,%0\n"
-                "5: \n"
-                EX_TABLE(0b,2b) EX_TABLE(3b,5b)
-                : "+a" (size), "+a" (to), "+a" (tmp1), "=a" (tmp2)
-                : "a" (empty_zero_page), "d" (reg0) : "cc", "memory");
-        return size;
-}
-unsigned long __clear_user(void __user *to, unsigned long size)
-{
-        if (static_key_true(&have_mvcos))
-                return clear_user_mvcos(to, size);
-        return clear_user_pt(to, size);
-}
-EXPORT_SYMBOL(__clear_user);
-static inline unsigned long strnlen_user_mvcos(const char __user *src,
-                                               unsigned long count)
-{
-        unsigned long done, len, offset, len_str;
-        char buf[256];
-        done = 0;
-        do {
-                offset = (unsigned long)src & ~PAGE_MASK;
-                len = min(256UL, PAGE_SIZE - offset);
-                len = min(count - done, len);
-                if (copy_from_user_mvcos(buf, src, len))
-                        return 0;
-                len_str = strnlen(buf, len);
-                done += len_str;
-                src += len_str;
-        } while ((len_str == len) && (done < count));
-        return done + 1;
-}
-unsigned long __strnlen_user(const char __user *src, unsigned long count)
-{
-        if (static_key_true(&have_mvcos))
-                return strnlen_user_mvcos(src, count);
-        return strnlen_user_pt(src, count);
-}
-EXPORT_SYMBOL(__strnlen_user);
-static inline long strncpy_from_user_mvcos(char *dst, const char __user *src,
-                                           long count)
-{
-        unsigned long done, len, offset, len_str;
-        if (unlikely(count <= 0))
-                return 0;
-        done = 0;
-        do {
-                offset = (unsigned long)src & ~PAGE_MASK;
-                len = min(count - done, PAGE_SIZE - offset);
-                if (copy_from_user_mvcos(dst, src, len))
-                        return -EFAULT;
-                len_str = strnlen(dst, len);
-                done += len_str;
-                src += len_str;
-                dst += len_str;
-        } while ((len_str == len) && (done < count));
-        return done;
-}
-long __strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        if (static_key_true(&have_mvcos))
-                return strncpy_from_user_mvcos(dst, src, count);
-        return strncpy_from_user_pt(dst, src, count);
-}
-EXPORT_SYMBOL(__strncpy_from_user);
-/*
- * The uaccess page tabe walk variant can be enforced with the "uaccesspt"
- * kernel parameter. This is mainly for debugging purposes.
- */
-static int force_uaccess_pt __initdata;
-static int __init parse_uaccess_pt(char *__unused)
-{
-        force_uaccess_pt = 1;
-        return 0;
-}
-early_param("uaccesspt", parse_uaccess_pt);
-static int __init uaccess_init(void)
-{
-        if (IS_ENABLED(CONFIG_32BIT) || force_uaccess_pt || !test_facility(27))
-                static_key_slow_dec(&have_mvcos);
-        return 0;
-}
-early_initcall(uaccess_init);
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
deleted file mode 100644
index 8d39760bae68..000000000000
--- a/arch/s390/lib/uaccess_pt.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/*
- *  User access functions based on page table walks for enhanced
- *  system layout without hardware support.
- *
- *    Copyright IBM Corp. 2006, 2012
- *    Author(s): Gerald Schaefer (gerald.schaefer@de.ibm.com)
- */
-#include <linux/errno.h>
-#include <linux/hardirq.h>
-#include <linux/mm.h>
-#include <linux/hugetlb.h>
-#include <asm/uaccess.h>
-#include <asm/futex.h>
-#include "uaccess.h"
-#ifndef CONFIG_64BIT
-#define AHI     "ahi"
-#define SLR     "slr"
-#else
-#define AHI     "aghi"
-#define SLR     "slgr"
-#endif
-static unsigned long strnlen_kernel(const char __user *src, unsigned long count)
-{
-        register unsigned long reg0 asm("0") = 0UL;
-        unsigned long tmp1, tmp2;
-        asm volatile(
-                "   la    %2,0(%1)\n"
-                "   la    %3,0(%0,%1)\n"
-                "  "SLR"  %0,%0\n"
-                "0: srst  %3,%2\n"
-                "   jo    0b\n"
-                "   la    %0,1(%3)\n"   /* strnlen_kernel results includes \0 */
-                "  "SLR"  %0,%1\n"
-                "1:\n"
-                EX_TABLE(0b,1b)
-                : "+a" (count), "+a" (src), "=a" (tmp1), "=a" (tmp2)
-                : "d" (reg0) : "cc", "memory");
-        return count;
-}
-static unsigned long copy_in_kernel(void __user *to, const void __user *from,
-                                    unsigned long count)
-{
-        unsigned long tmp1;
-        asm volatile(
-                "  "AHI"  %0,-1\n"
-                "   jo    5f\n"
-                "   bras  %3,3f\n"
-                "0:"AHI"  %0,257\n"
-                "1: mvc   0(1,%1),0(%2)\n"
-                "   la    %1,1(%1)\n"
-                "   la    %2,1(%2)\n"
-                "  "AHI"  %0,-1\n"
-                "   jnz   1b\n"
-                "   j     5f\n"
-                "2: mvc   0(256,%1),0(%2)\n"
-                "   la    %1,256(%1)\n"
-                "   la    %2,256(%2)\n"
-                "3:"AHI"  %0,-256\n"
-                "   jnm   2b\n"
-                "4: ex    %0,1b-0b(%3)\n"
-                "5:"SLR"  %0,%0\n"
-                "6:\n"
-                EX_TABLE(1b,6b) EX_TABLE(2b,0b) EX_TABLE(4b,0b)
-                : "+a" (count), "+a" (to), "+a" (from), "=a" (tmp1)
-                : : "cc", "memory");
-        return count;
-}
-/*
- * Returns kernel address for user virtual address. If the returned address is
- * >= -4095 (IS_ERR_VALUE(x) returns true), a fault has occurred and the
- * address contains the (negative) exception code.
- */
-#ifdef CONFIG_64BIT
-static unsigned long follow_table(struct mm_struct *mm,
-                                  unsigned long address, int write)
-{
-        unsigned long *table = (unsigned long *)__pa(mm->pgd);
-        if (unlikely(address > mm->context.asce_limit - 1))
-                return -0x38UL;
-        switch (mm->context.asce_bits & _ASCE_TYPE_MASK) {
-        case _ASCE_TYPE_REGION1:
-                table = table + ((address >> 53) & 0x7ff);
-                if (unlikely(*table & _REGION_ENTRY_INVALID))
-                        return -0x39UL;
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                /* fallthrough */
-        case _ASCE_TYPE_REGION2:
-                table = table + ((address >> 42) & 0x7ff);
-                if (unlikely(*table & _REGION_ENTRY_INVALID))
-                        return -0x3aUL;
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                /* fallthrough */
-        case _ASCE_TYPE_REGION3:
-                table = table + ((address >> 31) & 0x7ff);
-                if (unlikely(*table & _REGION_ENTRY_INVALID))
-                        return -0x3bUL;
-                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
-                /* fallthrough */
-        case _ASCE_TYPE_SEGMENT:
-                table = table + ((address >> 20) & 0x7ff);
-                if (unlikely(*table & _SEGMENT_ENTRY_INVALID))
-                        return -0x10UL;
-                if (unlikely(*table & _SEGMENT_ENTRY_LARGE)) {
-                        if (write && (*table & _SEGMENT_ENTRY_PROTECT))
-                                return -0x04UL;
-                        return (*table & _SEGMENT_ENTRY_ORIGIN_LARGE) +
-                                (address & ~_SEGMENT_ENTRY_ORIGIN_LARGE);
-                }
-                table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
-        }
-        table = table + ((address >> 12) & 0xff);
-        if (unlikely(*table & _PAGE_INVALID))
-                return -0x11UL;
-        if (write && (*table & _PAGE_PROTECT))
-                return -0x04UL;
-        return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
-}
-#else /* CONFIG_64BIT */
-static unsigned long follow_table(struct mm_struct *mm,
-                                  unsigned long address, int write)
-{
-        unsigned long *table = (unsigned long *)__pa(mm->pgd);
-        table = table + ((address >> 20) & 0x7ff);
-        if (unlikely(*table & _SEGMENT_ENTRY_INVALID))
-                return -0x10UL;
-        table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
-        table = table + ((address >> 12) & 0xff);
-        if (unlikely(*table & _PAGE_INVALID))
-                return -0x11UL;
-        if (write && (*table & _PAGE_PROTECT))
-                return -0x04UL;
-        return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
-}
-#endif /* CONFIG_64BIT */
-static inline unsigned long __user_copy_pt(unsigned long uaddr, void *kptr,
-                                           unsigned long n, int write_user)
-{
-        struct mm_struct *mm = current->mm;
-        unsigned long offset, done, size, kaddr;
-        void *from, *to;
-        if (!mm)
-                return n;
-        done = 0;
-retry:
-        spin_lock(&mm->page_table_lock);
-        do {
-                kaddr = follow_table(mm, uaddr, write_user);
-                if (IS_ERR_VALUE(kaddr))
-                        goto fault;
-                offset = uaddr & ~PAGE_MASK;
-                size = min(n - done, PAGE_SIZE - offset);
-                if (write_user) {
-                        to = (void *) kaddr;
-                        from = kptr + done;
-                } else {
-                        from = (void *) kaddr;
-                        to = kptr + done;
-                }
-                memcpy(to, from, size);
-                done += size;
-                uaddr += size;
-        } while (done < n);
-        spin_unlock(&mm->page_table_lock);
-        return n - done;
-fault:
-        spin_unlock(&mm->page_table_lock);
-        if (__handle_fault(uaddr, -kaddr, write_user))
-                return n - done;
-        goto retry;
-}
-/*
- * Do DAT for user address by page table walk, return kernel address.
- * This function needs to be called with current->mm->page_table_lock held.
- */
-static inline unsigned long __dat_user_addr(unsigned long uaddr, int write)
-{
-        struct mm_struct *mm = current->mm;
-        unsigned long kaddr;
-        int rc;
-retry:
-        kaddr = follow_table(mm, uaddr, write);
-        if (IS_ERR_VALUE(kaddr))
-                goto fault;
-        return kaddr;
-fault:
-        spin_unlock(&mm->page_table_lock);
-        rc = __handle_fault(uaddr, -kaddr, write);
-        spin_lock(&mm->page_table_lock);
-        if (!rc)
-                goto retry;
-        return 0;
-}
-unsigned long copy_from_user_pt(void *to, const void __user *from, unsigned long n)
-{
-        unsigned long rc;
-        if (segment_eq(get_fs(), KERNEL_DS))
-                return copy_in_kernel((void __user *) to, from, n);
-        rc = __user_copy_pt((unsigned long) from, to, n, 0);
-        if (unlikely(rc))
-                memset(to + n - rc, 0, rc);
-        return rc;
-}
-unsigned long copy_to_user_pt(void __user *to, const void *from, unsigned long n)
-{
-        if (segment_eq(get_fs(), KERNEL_DS))
-                return copy_in_kernel(to, (void __user *) from, n);
-        return __user_copy_pt((unsigned long) to, (void *) from, n, 1);
-}
-unsigned long clear_user_pt(void __user *to, unsigned long n)
-{
-        void *zpage = (void *) empty_zero_page;
-        unsigned long done, size, ret;
-        done = 0;
-        do {
-                if (n - done > PAGE_SIZE)
-                        size = PAGE_SIZE;
-                else
-                        size = n - done;
-                if (segment_eq(get_fs(), KERNEL_DS))
-                        ret = copy_in_kernel(to, (void __user *) zpage, n);
-                else
-                        ret = __user_copy_pt((unsigned long) to, zpage, size, 1);
-                done += size;
-                to += size;
-                if (ret)
-                        return ret + n - done;
-        } while (done < n);
-        return 0;
-}
-unsigned long strnlen_user_pt(const char __user *src, unsigned long count)
-{
-        unsigned long uaddr = (unsigned long) src;
-        struct mm_struct *mm = current->mm;
-        unsigned long offset, done, len, kaddr;
-        unsigned long len_str;
-        if (unlikely(!count))
-                return 0;
-        if (segment_eq(get_fs(), KERNEL_DS))
-                return strnlen_kernel(src, count);
-        if (!mm)
-                return 0;
-        done = 0;
-retry:
-        spin_lock(&mm->page_table_lock);
-        do {
-                kaddr = follow_table(mm, uaddr, 0);
-                if (IS_ERR_VALUE(kaddr))
-                        goto fault;
-                offset = uaddr & ~PAGE_MASK;
-                len = min(count - done, PAGE_SIZE - offset);
-                len_str = strnlen((char *) kaddr, len);
-                done += len_str;
-                uaddr += len_str;
-        } while ((len_str == len) && (done < count));
-        spin_unlock(&mm->page_table_lock);
-        return done + 1;
-fault:
-        spin_unlock(&mm->page_table_lock);
-        if (__handle_fault(uaddr, -kaddr, 0))
-                return 0;
-        goto retry;
-}
-long strncpy_from_user_pt(char *dst, const char __user *src, long count)
-{
-        unsigned long done, len, offset, len_str;
-        if (unlikely(count <= 0))
-                return 0;
-        done = 0;
-        do {
-                offset = (unsigned long)src & ~PAGE_MASK;
-                len = min(count - done, PAGE_SIZE - offset);
-                if (segment_eq(get_fs(), KERNEL_DS)) {
-                        if (copy_in_kernel((void __user *) dst, src, len))
-                                return -EFAULT;
-                } else {
-                        if (__user_copy_pt((unsigned long) src, dst, len, 0))
-                                return -EFAULT;
-                }
-                len_str = strnlen(dst, len);
-                done += len_str;
-                src += len_str;
-                dst += len_str;
-        } while ((len_str == len) && (done < count));
-        return done;
-}
-unsigned long copy_in_user_pt(void __user *to, const void __user *from,
-                              unsigned long n)
-{
-        struct mm_struct *mm = current->mm;
-        unsigned long offset_max, uaddr, done, size, error_code;
-        unsigned long uaddr_from = (unsigned long) from;
-        unsigned long uaddr_to = (unsigned long) to;
-        unsigned long kaddr_to, kaddr_from;
-        int write_user;
-        if (segment_eq(get_fs(), KERNEL_DS))
-                return copy_in_kernel(to, from, n);
-        if (!mm)
-                return n;
-        done = 0;
-retry:
-        spin_lock(&mm->page_table_lock);
-        do {
-                write_user = 0;
-                uaddr = uaddr_from;
-                kaddr_from = follow_table(mm, uaddr_from, 0);
-                error_code = kaddr_from;
-                if (IS_ERR_VALUE(error_code))
-                        goto fault;
-                write_user = 1;
-                uaddr = uaddr_to;
-                kaddr_to = follow_table(mm, uaddr_to, 1);
-                error_code = (unsigned long) kaddr_to;
-                if (IS_ERR_VALUE(error_code))
-                        goto fault;
-                offset_max = max(uaddr_from & ~PAGE_MASK,
-                                 uaddr_to & ~PAGE_MASK);
-                size = min(n - done, PAGE_SIZE - offset_max);
-                memcpy((void *) kaddr_to, (void *) kaddr_from, size);
-                done += size;
-                uaddr_from += size;
-                uaddr_to += size;
-        } while (done < n);
-        spin_unlock(&mm->page_table_lock);
-        return n - done;
-fault:
-        spin_unlock(&mm->page_table_lock);
-        if (__handle_fault(uaddr, -error_code, write_user))
-                return n - done;
-        goto retry;
-}
-#define __futex_atomic_op(insn, ret, oldval, newval, uaddr, oparg)      \
-        asm volatile("0: l   %1,0(%6)\n"                                \
-                     "1: " insn                                         \
-                     "2: cs  %1,%2,0(%6)\n"                             \
-                     "3: jl  1b\n"                                      \
-                     "   lhi %0,0\n"                                    \
-                     "4:\n"                                             \
-                     EX_TABLE(0b,4b) EX_TABLE(2b,4b) EX_TABLE(3b,4b)    \
-                     : "=d" (ret), "=&d" (oldval), "=&d" (newval),      \
-                       "=m" (*uaddr)                                    \
-                     : "0" (-EFAULT), "d" (oparg), "a" (uaddr),         \
-                       "m" (*uaddr) : "cc" );
-static int __futex_atomic_op_pt(int op, u32 __user *uaddr, int oparg, int *old)
-{
-        int oldval = 0, newval, ret;
-        switch (op) {
-        case FUTEX_OP_SET:
-                __futex_atomic_op("lr %2,%5\n",
-                                  ret, oldval, newval, uaddr, oparg);
-                break;
-        case FUTEX_OP_ADD:
-                __futex_atomic_op("lr %2,%1\nar %2,%5\n",
-                                  ret, oldval, newval, uaddr, oparg);
-                break;
-        case FUTEX_OP_OR:
-                __futex_atomic_op("lr %2,%1\nor %2,%5\n",
-                                  ret, oldval, newval, uaddr, oparg);
-                break;
-        case FUTEX_OP_ANDN:
-                __futex_atomic_op("lr %2,%1\nnr %2,%5\n",
-                                  ret, oldval, newval, uaddr, oparg);
-                break;
-        case FUTEX_OP_XOR:
-                __futex_atomic_op("lr %2,%1\nxr %2,%5\n",
-                                  ret, oldval, newval, uaddr, oparg);
-                break;
-        default:
-                ret = -ENOSYS;
-        }
-        if (ret == 0)
-                *old = oldval;
-        return ret;
-}
-int __futex_atomic_op_inuser(int op, u32 __user *uaddr, int oparg, int *old)
-{
-        int ret;
-        if (segment_eq(get_fs(), KERNEL_DS))
-                return __futex_atomic_op_pt(op, uaddr, oparg, old);
-        if (unlikely(!current->mm))
-                return -EFAULT;
-        spin_lock(&current->mm->page_table_lock);
-        uaddr = (u32 __force __user *)
-                __dat_user_addr((__force unsigned long) uaddr, 1);
-        if (!uaddr) {
-                spin_unlock(&current->mm->page_table_lock);
-                return -EFAULT;
-        }
-        get_page(virt_to_page(uaddr));
-        spin_unlock(&current->mm->page_table_lock);
-        ret = __futex_atomic_op_pt(op, uaddr, oparg, old);
-        put_page(virt_to_page(uaddr));
-        return ret;
-}
-static int __futex_atomic_cmpxchg_pt(u32 *uval, u32 __user *uaddr,
-                                     u32 oldval, u32 newval)
-{
-        int ret;
-        asm volatile("0: cs   %1,%4,0(%5)\n"
-                     "1: la   %0,0\n"
-                     "2:\n"
-                     EX_TABLE(0b,2b) EX_TABLE(1b,2b)
-                     : "=d" (ret), "+d" (oldval), "=m" (*uaddr)
-                     : "0" (-EFAULT), "d" (newval), "a" (uaddr), "m" (*uaddr)
-                     : "cc", "memory" );
-        *uval = oldval;
-        return ret;
-}
-int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
-                                  u32 oldval, u32 newval)
-{
-        int ret;
-        if (segment_eq(get_fs(), KERNEL_DS))
-                return __futex_atomic_cmpxchg_pt(uval, uaddr, oldval, newval);
-        if (unlikely(!current->mm))
-                return -EFAULT;
-        spin_lock(&current->mm->page_table_lock);
-        uaddr = (u32 __force __user *)
-                __dat_user_addr((__force unsigned long) uaddr, 1);
-        if (!uaddr) {
-                spin_unlock(&current->mm->page_table_lock);
-                return -EFAULT;
-        }
-        get_page(virt_to_page(uaddr));
-        spin_unlock(&current->mm->page_table_lock);
-        ret = __futex_atomic_cmpxchg_pt(uval, uaddr, oldval, newval);
-        put_page(virt_to_page(uaddr));
-        return ret;
-}
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index d95265b2719f..19f623f1f21c 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -50,6 +50,7 @@
 #define VM_FAULT_BADMAP         0x020000
 #define VM_FAULT_BADACCESS      0x040000
 #define VM_FAULT_SIGNAL         0x080000
+#define VM_FAULT_PFAULT         0x100000
 static unsigned long store_indication __read_mostly;
@@ -105,21 +106,24 @@ void bust_spinlocks(int yes)
 * Returns the address space associated with the fault.
 * Returns 0 for kernel space and 1 for user space.
 */
-static inline int user_space_fault(unsigned long trans_exc_code)
+static inline int user_space_fault(struct pt_regs *regs)
 {
+        unsigned long trans_exc_code;
        /*
         * The lowest two bits of the translation exception
         * identification indicate which paging table was used.
         */
-        trans_exc_code &= 3;
+        trans_exc_code = regs->int_parm_long & 3;
-        if (trans_exc_code == 2)
+        if (trans_exc_code == 3) /* home space -> kernel */
-                /* Access via secondary space, set_fs setting decides */
+                return 0;
+        if (user_mode(regs))
+                return 1;
+        if (trans_exc_code == 2) /* secondary space -> set_fs */
                return current->thread.mm_segment.ar4;
-        /*
+        if (current->flags & PF_VCPU)
-         * Access via primary space or access register is from user space
+                return 1;
-         * and access via home space is from the kernel.
+        return 0;
-         */
-        return trans_exc_code != 3;
 }
 static inline void report_user_fault(struct pt_regs *regs, long signr)
@@ -171,7 +175,7 @@ static noinline void do_no_context(struct pt_regs *regs)
         * terminate things with extreme prejudice.
         */
        address = regs->int_parm_long & __FAIL_ADDR_MASK;
-        if (!user_space_fault(regs->int_parm_long))
+        if (!user_space_fault(regs))
                printk(KERN_ALERT "Unable to handle kernel pointer dereference"
                       " at virtual kernel address %p\n", (void *)address);
        else
@@ -227,6 +231,7 @@ static noinline void do_fault_error(struct pt_regs *regs, int fault)
                        return;
                }
        case VM_FAULT_BADCONTEXT:
+        case VM_FAULT_PFAULT:
                do_no_context(regs);
                break;
        case VM_FAULT_SIGNAL:
@@ -264,6 +269,9 @@ static noinline void do_fault_error(struct pt_regs *regs, int fault)
 */
 static inline int do_exception(struct pt_regs *regs, int access)
 {
+#ifdef CONFIG_PGSTE
+        struct gmap *gmap;
+#endif
        struct task_struct *tsk;
        struct mm_struct *mm;
        struct vm_area_struct *vma;
@@ -291,7 +299,7 @@ static inline int do_exception(struct pt_regs *regs, int access)
         * user context.
         */
        fault = VM_FAULT_BADCONTEXT;
-        if (unlikely(!user_space_fault(trans_exc_code) || in_atomic() || !mm))
+        if (unlikely(!user_space_fault(regs) || in_atomic() || !mm))
                goto out;
        address = trans_exc_code & __FAIL_ADDR_MASK;
@@ -304,9 +312,10 @@ static inline int do_exception(struct pt_regs *regs, int access)
        down_read(&mm->mmap_sem);
 #ifdef CONFIG_PGSTE
-        if ((current->flags & PF_VCPU) && S390_lowcore.gmap) {
+        gmap = (struct gmap *)
-                address = __gmap_fault(address,
+                ((current->flags & PF_VCPU) ? S390_lowcore.gmap : 0);
-                                     (struct gmap *) S390_lowcore.gmap);
+        if (gmap) {
+                address = __gmap_fault(address, gmap);
                if (address == -EFAULT) {
                        fault = VM_FAULT_BADMAP;
                        goto out_up;
@@ -315,6 +324,8 @@ static inline int do_exception(struct pt_regs *regs, int access)
                        fault = VM_FAULT_OOM;
                        goto out_up;
                }
+                if (gmap->pfault_enabled)
+                        flags |= FAULT_FLAG_RETRY_NOWAIT;
        }
 #endif
@@ -371,9 +382,19 @@ retry:
                                      regs, address);
                }
                if (fault & VM_FAULT_RETRY) {
+#ifdef CONFIG_PGSTE
+                        if (gmap && (flags & FAULT_FLAG_RETRY_NOWAIT)) {
+                                /* FAULT_FLAG_RETRY_NOWAIT has been set,
+                                 * mmap_sem has not been released */
+                                current->thread.gmap_pfault = 1;
+                                fault = VM_FAULT_PFAULT;
+                                goto out_up;
+                        }
+#endif
                        /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk
                         * of starvation. */
-                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+                        flags &= ~(FAULT_FLAG_ALLOW_RETRY |
+                                   FAULT_FLAG_RETRY_NOWAIT);
                        flags |= FAULT_FLAG_TRIED;
                        down_read(&mm->mmap_sem);
                        goto retry;
@@ -423,30 +444,6 @@ void __kprobes do_dat_exception(struct pt_regs *regs)
                do_fault_error(regs, fault);
 }
-int __handle_fault(unsigned long uaddr, unsigned long pgm_int_code, int write)
-{
-        struct pt_regs regs;
-        int access, fault;
-        /* Emulate a uaccess fault from kernel mode. */
-        regs.psw.mask = PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK;
-        if (!irqs_disabled())
-                regs.psw.mask |= PSW_MASK_IO | PSW_MASK_EXT;
-        regs.psw.addr = (unsigned long) __builtin_return_address(0);
-        regs.psw.addr |= PSW_ADDR_AMODE;
-        regs.int_code = pgm_int_code;
-        regs.int_parm_long = (uaddr & PAGE_MASK) | 2;
-        access = write ? VM_WRITE : VM_READ;
-        fault = do_exception(&regs, access);
-        /*
-         * Since the fault happened in kernel mode while performing a uaccess
-         * all we need to do now is emulating a fixup in case "fault" is not
-         * zero.
-         * For the calling uaccess functions this results always in -EFAULT.
-         */
-        return fault ? -EFAULT : 0;
-}
 #ifdef CONFIG_PFAULT 
 /*
 * 'pfault' pseudo page faults routines.
@@ -627,7 +624,7 @@ static int __init pfault_irq_init(void)
 {
        int rc;
-        rc = register_external_interrupt(0x2603, pfault_interrupt);
+        rc = register_external_irq(EXT_IRQ_CP_SERVICE, pfault_interrupt);
        if (rc)
                goto out_extint;
        rc = pfault_init() == 0 ? 0 : -EOPNOTSUPP;
@@ -638,7 +635,7 @@ static int __init pfault_irq_init(void)
        return 0;
 out_pfault:
-        unregister_external_interrupt(0x2603, pfault_interrupt);
+        unregister_external_irq(EXT_IRQ_CP_SERVICE, pfault_interrupt);
 out_extint:
        pfault_disable = 1;
        return rc;
diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c
index d261c62e40a6..0727a55d87d9 100644
--- a/arch/s390/mm/hugetlbpage.c
+++ b/arch/s390/mm/hugetlbpage.c
@@ -123,10 +123,7 @@ pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
        pmd_t *pmdp = (pmd_t *) ptep;
        pte_t pte = huge_ptep_get(ptep);
-        if (MACHINE_HAS_IDTE)
+        pmdp_flush_direct(mm, addr, pmdp);
-                __pmd_idte(addr, pmdp);
-        else
-                __pmd_csp(pmdp);
        pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
        return pte;
 }
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index ad446b0c55b6..0c1073ed1e84 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -124,8 +124,6 @@ void __init paging_init(void)
        __ctl_load(S390_lowcore.kernel_asce, 13, 13);
        arch_local_irq_restore(4UL << (BITS_PER_LONG - 8));
-        atomic_set(&init_mm.context.attach_count, 1);
        sparse_memory_present_with_active_regions(MAX_NUMNODES);
        sparse_init();
        memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
@@ -136,6 +134,11 @@ void __init paging_init(void)
 void __init mem_init(void)
 {
+        if (MACHINE_HAS_TLB_LC)
+                cpumask_set_cpu(0, &init_mm.context.cpu_attach_mask);
+        cpumask_set_cpu(0, mm_cpumask(&init_mm));
+        atomic_set(&init_mm.context.attach_count, 1);
        max_mapnr = max_low_pfn;
        high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 796c9320c709..d7cfd57815fb 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -54,7 +54,7 @@ static void __crst_table_upgrade(void *arg)
        struct mm_struct *mm = arg;
        if (current->active_mm == mm)
-                update_mm(mm, current);
+                update_user_asce(mm, 1);
        __tlb_flush_local();
 }
@@ -107,8 +107,10 @@ void crst_table_downgrade(struct mm_struct *mm, unsigned long limit)
 {
        pgd_t *pgd;
-        if (current->active_mm == mm)
+        if (current->active_mm == mm) {
+                clear_user_asce(mm, 1);
                __tlb_flush_mm(mm);
+        }
        while (mm->context.asce_limit > limit) {
                pgd = mm->pgd;
                switch (pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) {
@@ -132,7 +134,7 @@ void crst_table_downgrade(struct mm_struct *mm, unsigned long limit)
                crst_table_free(mm, (unsigned long *) pgd);
        }
        if (current->active_mm == mm)
-                update_mm(mm, current);
+                update_user_asce(mm, 1);
 }
 #endif
@@ -198,7 +200,7 @@ static int gmap_unlink_segment(struct gmap *gmap, unsigned long *table)
 static void gmap_flush_tlb(struct gmap *gmap)
 {
        if (MACHINE_HAS_IDTE)
-                __tlb_flush_idte((unsigned long) gmap->table |
+                __tlb_flush_asce(gmap->mm, (unsigned long) gmap->table |
                                 _ASCE_TYPE_REGION1);
        else
                __tlb_flush_global();
@@ -217,7 +219,7 @@ void gmap_free(struct gmap *gmap)
        /* Flush tlb. */
        if (MACHINE_HAS_IDTE)
-                __tlb_flush_idte((unsigned long) gmap->table |
+                __tlb_flush_asce(gmap->mm, (unsigned long) gmap->table |
                                 _ASCE_TYPE_REGION1);
        else
                __tlb_flush_global();
@@ -505,6 +507,9 @@ static int gmap_connect_pgtable(unsigned long address, unsigned long segment,
        if (!pmd_present(*pmd) &&
            __pte_alloc(mm, vma, pmd, vmaddr))
                return -ENOMEM;
+        /* large pmds cannot yet be handled */
+        if (pmd_large(*pmd))
+                return -EFAULT;
        /* pmd now points to a valid segment table entry. */
        rmap = kmalloc(sizeof(*rmap), GFP_KERNEL|__GFP_REPEAT);
        if (!rmap)
diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c
index bcfb70b60be6..72b04de18283 100644
--- a/arch/s390/mm/vmem.c
+++ b/arch/s390/mm/vmem.c
@@ -138,7 +138,6 @@ static int vmem_add_mem(unsigned long start, unsigned long size, int ro)
        }
        ret = 0;
 out:
-        flush_tlb_kernel_range(start, end);
        return ret;
 }
@@ -265,7 +264,6 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
        memset((void *)start, 0, end - start);
        ret = 0;
 out:
-        flush_tlb_kernel_range(start, end);
        return ret;
 }
diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c
index 708d60e40066..9c36dc398f90 100644
--- a/arch/s390/net/bpf_jit_comp.c
+++ b/arch/s390/net/bpf_jit_comp.c
@@ -737,10 +737,10 @@ call_fn:	/* lg %r1,<d(function)>(%r13) */
                /* icm  %r5,3,<d(type)>(%r1) */
                EMIT4_DISP(0xbf531000, offsetof(struct net_device, type));
                break;
-        case BPF_S_ANC_RXHASH: /* A = skb->rxhash */
+        case BPF_S_ANC_RXHASH: /* A = skb->hash */
-                BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, rxhash) != 4);
+                BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
-                /* l %r5,<d(rxhash)>(%r2) */
+                /* l %r5,<d(hash)>(%r2) */
-                EMIT4_DISP(0x58502000, offsetof(struct sk_buff, rxhash));
+                EMIT4_DISP(0x58502000, offsetof(struct sk_buff, hash));
                break;
        case BPF_S_ANC_VLAN_TAG:
        case BPF_S_ANC_VLAN_TAG_PRESENT:
@@ -877,6 +877,7 @@ void bpf_jit_compile(struct sk_filter *fp)
        if (jit.start) {
                set_memory_ro((unsigned long)header, header->pages);
                fp->bpf_func = (void *) jit.start;
+                fp->jited = 1;
        }
 out:
        kfree(addrs);
@@ -887,10 +888,12 @@ void bpf_jit_free(struct sk_filter *fp)
        unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
        struct bpf_binary_header *header = (void *)addr;
-        if (fp->bpf_func == sk_run_filter)
+        if (!fp->jited)
                goto free_filter;
        set_memory_rw(addr, header->pages);
        module_free(NULL, header);
 free_filter:
        kfree(fp);
 }
diff --git a/arch/s390/oprofile/hwsampler.c b/arch/s390/oprofile/hwsampler.c
index a32c96761eab..276f2e26c761 100644
--- a/arch/s390/oprofile/hwsampler.c
+++ b/arch/s390/oprofile/hwsampler.c
@@ -1033,7 +1033,7 @@ int hwsampler_setup(void)
                                max_sampler_rate = cb->qsi.max_sampl_rate;
                }
        }
-        register_external_interrupt(0x1407, hws_ext_handler);
+        register_external_irq(EXT_IRQ_MEASURE_ALERT, hws_ext_handler);
        hws_state = HWS_DEALLOCATED;
        rc = 0;
@@ -1068,7 +1068,7 @@ int hwsampler_shutdown(void)
                        hws_wq = NULL;
                }
-                unregister_external_interrupt(0x1407, hws_ext_handler);
+                unregister_external_irq(EXT_IRQ_MEASURE_ALERT, hws_ext_handler);
                hws_state = HWS_INIT;
                rc = 0;
        }
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
index 66670ff262a0..1df1d29ac81d 100644
--- a/arch/s390/pci/pci.c
+++ b/arch/s390/pci/pci.c
@@ -686,27 +686,13 @@ int pcibios_add_device(struct pci_dev *pdev)
 int pcibios_enable_device(struct pci_dev *pdev, int mask)
 {
        struct zpci_dev *zdev = get_zdev(pdev);
-        struct resource *res;
-        u16 cmd;
-        int i;
        zdev->pdev = pdev;
        zpci_debug_init_device(zdev);
        zpci_fmb_enable_device(zdev);
        zpci_map_resources(zdev);
-        pci_read_config_word(pdev, PCI_COMMAND, &cmd);
+        return pci_enable_resources(pdev, mask);
-        for (i = 0; i < PCI_BAR_COUNT; i++) {
-                res = &pdev->resource[i];
-                if (res->flags & IORESOURCE_IO)
-                        return -EINVAL;
-                if (res->flags & IORESOURCE_MEM)
-                        cmd |= PCI_COMMAND_MEMORY;
-        }
-        pci_write_config_word(pdev, PCI_COMMAND, cmd);
-        return 0;
 }
 void pcibios_disable_device(struct pci_dev *pdev)
diff --git a/arch/s390/pci/pci_sysfs.c b/arch/s390/pci/pci_sysfs.c
index cf8a12ff733b..ab4a91393005 100644
--- a/arch/s390/pci/pci_sysfs.c
+++ b/arch/s390/pci/pci_sysfs.c
@@ -48,29 +48,27 @@ static ssize_t show_pfgid(struct device *dev, struct device_attribute *attr,
 }
 static DEVICE_ATTR(pfgid, S_IRUGO, show_pfgid, NULL);
-static void recover_callback(struct device *dev)
+static ssize_t store_recover(struct device *dev, struct device_attribute *attr,
+                             const char *buf, size_t count)
 {
        struct pci_dev *pdev = to_pci_dev(dev);
        struct zpci_dev *zdev = get_zdev(pdev);
        int ret;
+        if (!device_remove_file_self(dev, attr))
+                return count;
        pci_stop_and_remove_bus_device(pdev);
        ret = zpci_disable_device(zdev);
        if (ret)
-                return;
+                return ret;
        ret = zpci_enable_device(zdev);
        if (ret)
-                return;
+                return ret;
        pci_rescan_bus(zdev->bus);
-}
+        return count;
-static ssize_t store_recover(struct device *dev, struct device_attribute *attr,
-                             const char *buf, size_t count)
-{
-        int rc = device_schedule_callback(dev, recover_callback);
-        return rc ? rc : count;
 }
 static DEVICE_ATTR(recover, S_IWUSR, NULL, store_recover);
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index c75d06aa27c3..4ac8cae5727c 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -22,27 +22,21 @@ choice
 config ARCH_SCORE7
        bool "SCORE7 processor"
        select SYS_SUPPORTS_32BIT_KERNEL
-        select CPU_SCORE7
        select GENERIC_HAS_IOMAP
 config MACH_SPCT6600
        bool "SPCT6600 series based machines"
        select SYS_SUPPORTS_32BIT_KERNEL
-        select CPU_SCORE7
        select GENERIC_HAS_IOMAP
 config SCORE_SIM
        bool "Score simulator"
        select SYS_SUPPORTS_32BIT_KERNEL
-        select CPU_SCORE7
        select GENERIC_HAS_IOMAP
 endchoice
 endmenu
-config CPU_SCORE7
-        bool
 config NO_DMA
        bool
        default y
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 364d204298fa..834b67c4db5a 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -3,7 +3,7 @@ config SUPERH
        select ARCH_MIGHT_HAVE_PC_PARPORT
        select EXPERT
        select CLKDEV_LOOKUP
-        select HAVE_IDE if HAS_IOPORT
+        select HAVE_IDE if HAS_IOPORT_MAP
        select HAVE_MEMBLOCK
        select HAVE_MEMBLOCK_NODE_MAP
        select ARCH_DISCARD_MEMBLOCK
@@ -42,6 +42,7 @@ config SUPERH
        select MODULES_USE_ELF_RELA
        select OLD_SIGSUSPEND
        select OLD_SIGACTION
+        select HAVE_ARCH_AUDITSYSCALL
        help
          The SuperH is a RISC processor targeted for use in embedded systems
          and consumer electronics; it was also used in the Sega Dreamcast
@@ -138,7 +139,7 @@ config ARCH_HAS_ILOG2_U32
 config ARCH_HAS_ILOG2_U64
        def_bool n
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool !PCI
        depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN && \
                   !SH_HP6XX && !SH_SOLUTION_ENGINE
@@ -347,7 +348,6 @@ config CPU_SUBTYPE_SH7720
        select CPU_HAS_DSP
        select SYS_SUPPORTS_SH_CMT
        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select USB_ARCH_HAS_OHCI
        select USB_OHCI_SH if USB_OHCI_HCD
        select PINCTRL
        help
@@ -358,7 +358,6 @@ config CPU_SUBTYPE_SH7721
        select CPU_SH3
        select CPU_HAS_DSP
        select SYS_SUPPORTS_SH_CMT
-        select USB_ARCH_HAS_OHCI
        select USB_OHCI_SH if USB_OHCI_HCD
        help
          Select SH7721 if you have a SH3-DSP SH7721 CPU.
@@ -436,8 +435,6 @@ config CPU_SUBTYPE_SH7734
        select CPU_SH4A
        select CPU_SHX2
        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select USB_ARCH_HAS_OHCI
-        select USB_ARCH_HAS_EHCI
        select PINCTRL
        help
          Select SH7734 if you have a SH4A SH7734 CPU.
@@ -447,8 +444,6 @@ config CPU_SUBTYPE_SH7757
        select CPU_SH4A
        select CPU_SHX2
        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select USB_ARCH_HAS_OHCI
-        select USB_ARCH_HAS_EHCI
        select PINCTRL
        help
          Select SH7757 if you have a SH4A SH7757 CPU.
@@ -456,7 +451,6 @@ config CPU_SUBTYPE_SH7757
 config CPU_SUBTYPE_SH7763
        bool "Support SH7763 processor"
        select CPU_SH4A
-        select USB_ARCH_HAS_OHCI
        select USB_OHCI_SH if USB_OHCI_HCD
        help
          Select SH7763 if you have a SH4A SH7763(R5S77631) CPU.
@@ -485,9 +479,7 @@ config CPU_SUBTYPE_SH7786
        select CPU_HAS_PTEAEX
        select GENERIC_CLOCKEVENTS_BROADCAST if SMP
        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select USB_ARCH_HAS_OHCI
        select USB_OHCI_SH if USB_OHCI_HCD
-        select USB_ARCH_HAS_EHCI
        select USB_EHCI_SH if USB_EHCI_HCD
        select PINCTRL
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index eb1cf84231a2..e331e5373b8e 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -158,7 +158,7 @@ config SH_SDK7786
        bool "SDK7786"
        depends on CPU_SUBTYPE_SH7786
        select SYS_SUPPORTS_PCI
-        select NO_IOPORT if !PCI
+        select NO_IOPORT_MAP if !PCI
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select HAVE_SRAM_POOL
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
@@ -204,7 +204,7 @@ config SH_URQUELL
        depends on CPU_SUBTYPE_SH7786
        select ARCH_REQUIRE_GPIOLIB
        select SYS_SUPPORTS_PCI
-        select NO_IOPORT if !PCI
+        select NO_IOPORT_MAP if !PCI
 config SH_MIGOR
        bool "Migo-R"
@@ -306,7 +306,7 @@ config SH_LBOX_RE2
 config SH_X3PROTO
        bool "SH-X3 Prototype board"
        depends on CPU_SUBTYPE_SHX3
-        select NO_IOPORT if !PCI
+        select NO_IOPORT_MAP if !PCI
        select IRQ_DOMAIN
 config SH_MAGIC_PANEL_R2
@@ -333,7 +333,7 @@ config SH_POLARIS
 config SH_SH2007
        bool "SH-2007 board"
-        select NO_IOPORT
+        select NO_IOPORT_MAP
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
        depends on CPU_SUBTYPE_SH7780
        help
diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c
index 25c5a932f9fe..669df51a82e3 100644
--- a/arch/sh/boards/board-sh7757lcr.c
+++ b/arch/sh/boards/board-sh7757lcr.c
@@ -252,7 +252,7 @@ static struct sh_mobile_sdhi_info sdhi_info = {
 static struct resource sdhi_resources[] = {
        [0] = {
                .start  = 0xffe50000,
-                .end    = 0xffe501ff,
+                .end    = 0xffe500ff,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 5bc3a15465c7..85d5255d259f 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -861,14 +861,12 @@ static struct asoc_simple_card_info fsi_da7210_info = {
        .card           = "FSIB-DA7210",
        .codec          = "da7210.0-001a",
        .platform       = "sh_fsi.0",
-        .daifmt         = SND_SOC_DAIFMT_I2S,
+        .daifmt         = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
        .cpu_dai = {
                .name   = "fsib-dai",
-                .fmt    = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF,
        },
        .codec_dai = {
                .name   = "da7210-hifi",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
        },
 };
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 21e4230659a5..1162bc6945a3 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -304,14 +304,12 @@ static struct asoc_simple_card_info fsi_ak4642_info = {
        .card           = "FSIA-AK4642",
        .codec          = "ak4642-codec.0-0012",
        .platform       = "sh_fsi.0",
-        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
+        .daifmt         = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
        .cpu_dai = {
                .name   = "fsia-dai",
-                .fmt    = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF,
        },
        .codec_dai = {
                .name   = "ak4642-hifi",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
                .sysclk = 11289600,
        },
 };
diff --git a/arch/sh/configs/rsk7203_defconfig b/arch/sh/configs/rsk7203_defconfig
index 4e5229b0c5bb..47236573db83 100644
--- a/arch/sh/configs/rsk7203_defconfig
+++ b/arch/sh/configs/rsk7203_defconfig
@@ -128,7 +128,6 @@ CONFIG_DEBUG_MUTEXES=y
 CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_VM=y
-CONFIG_DEBUG_WRITECOUNT=y
 CONFIG_DEBUG_LIST=y
 CONFIG_DEBUG_SG=y
 CONFIG_FRAME_POINTER=y
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 60ed3e1c4b75..1bc09ee7948f 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -186,11 +186,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
        return start;
 }
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
-        return pci_enable_resources(dev, mask);
-}
 static void __init
 pcibios_bus_report_status_early(struct pci_channel *hose,
                                int top_bus, int current_bus,
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
index 1ee054e47eae..4a6ff55f759b 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.h
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -145,9 +145,6 @@
 /*      PCIERMSGIER     */
 #define SH4A_PCIERMSGIER        (0x004040)      /* R/W - 0x0000 0000 32 */
-/*      PCIEPHYCTLR     */
-#define SH4A_PCIEPHYCTLR        (0x010000)      /* R/W - 0x0000 0000 32 */
 /*      PCIEPHYADRR     */
 #define SH4A_PCIEPHYADRR        (0x010004)      /* R/W - 0x0000 0000 32 */
 #define         BITS_ACK        (24)                    // Rev1.171
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 629db2ad7916..728c4c571f40 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -122,7 +122,7 @@ __BUILD_MEMORY_STRING(__raw_, l, u32)
 __BUILD_MEMORY_STRING(__raw_, q, u64)
-#ifdef CONFIG_HAS_IOPORT
+#ifdef CONFIG_HAS_IOPORT_MAP
 /*
 * Slowdown I/O port space accesses for antique hardware.
@@ -218,7 +218,7 @@ __BUILD_IOPORT_STRING(w, u16)
 __BUILD_IOPORT_STRING(l, u32)
 __BUILD_IOPORT_STRING(q, u64)
-#else /* !CONFIG_HAS_IOPORT */
+#else /* !CONFIG_HAS_IOPORT_MAP */
 #include <asm/io_noioport.h>
diff --git a/arch/sh/include/asm/io_trapped.h b/arch/sh/include/asm/io_trapped.h
index f1251d4f0ba9..4ab94ef51071 100644
--- a/arch/sh/include/asm/io_trapped.h
+++ b/arch/sh/include/asm/io_trapped.h
@@ -36,7 +36,7 @@ __ioremap_trapped(unsigned long offset, unsigned long size)
 #define __ioremap_trapped(offset, size) NULL
 #endif
-#ifdef CONFIG_HAS_IOPORT
+#ifdef CONFIG_HAS_IOPORT_MAP
 extern struct list_head trapped_io;
 static inline void __iomem *
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index eb9c20d971dd..d3324e4f372e 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -21,7 +21,7 @@ struct sh_machine_vector {
        int (*mv_irq_demux)(int irq);
        void (*mv_init_irq)(void);
-#ifdef CONFIG_HAS_IOPORT
+#ifdef CONFIG_HAS_IOPORT_MAP
        void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
        void (*mv_ioport_unmap)(void __iomem *);
 #endif
diff --git a/arch/sh/include/asm/syscalls_32.h b/arch/sh/include/asm/syscalls_32.h
index 4f97df87d7d5..4f643aa718e3 100644
--- a/arch/sh/include/asm/syscalls_32.h
+++ b/arch/sh/include/asm/syscalls_32.h
@@ -9,15 +9,9 @@
 struct pt_regs;
-asmlinkage int sys_sigreturn(unsigned long r4, unsigned long r5,
+asmlinkage int sys_sigreturn(void);
-                             unsigned long r6, unsigned long r7,
+asmlinkage int sys_rt_sigreturn(void);
-                             struct pt_regs __regs);
+asmlinkage int sys_sh_pipe(void);
-asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5,
-                                unsigned long r6, unsigned long r7,
-                                struct pt_regs __regs);
-asmlinkage int sys_sh_pipe(unsigned long r4, unsigned long r5,
-                           unsigned long r6, unsigned long r7,
-                           struct pt_regs __regs);
 asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char __user *buf,
                                     size_t count, long dummy, loff_t pos);
 asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char __user *buf,
diff --git a/arch/sh/include/asm/traps_32.h b/arch/sh/include/asm/traps_32.h
index cfd55ff9dff2..17e129fe459c 100644
--- a/arch/sh/include/asm/traps_32.h
+++ b/arch/sh/include/asm/traps_32.h
@@ -42,18 +42,10 @@ static inline void trigger_address_error(void)
 asmlinkage void do_address_error(struct pt_regs *regs,
                                 unsigned long writeaccess,
                                 unsigned long address);
-asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
+asmlinkage void do_divide_error(unsigned long r4);
-                                unsigned long r6, unsigned long r7,
+asmlinkage void do_reserved_inst(void);
-                                struct pt_regs __regs);
+asmlinkage void do_illegal_slot_inst(void);
-asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
+asmlinkage void do_exception_error(void);
-                                unsigned long r6, unsigned long r7,
-                                struct pt_regs __regs);
-asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
-                                unsigned long r6, unsigned long r7,
-                                struct pt_regs __regs);
-asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
-                                   unsigned long r6, unsigned long r7,
-                                   struct pt_regs __regs);
 #define BUILD_TRAP_HANDLER(name)                                        \
 asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 261c8bfd75ce..2ccf36c824c6 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -22,7 +22,7 @@ obj-y	:= debugtraps.o dma-nommu.o dumpstack.o 		\
 ifndef CONFIG_GENERIC_IOMAP
 obj-y                           += iomap.o
-obj-$(CONFIG_HAS_IOPORT)        += ioport.o
+obj-$(CONFIG_HAS_IOPORT_MAP)    += ioport.o
 endif
 obj-$(CONFIG_SUPERH32)          += sys_sh32.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index e84a43229b9c..5c0e3c335161 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -132,7 +132,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]),
        CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]),
        CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
-        CLKDEV_CON_ID("rspi2", &mstp_clks[MSTP127]),
+        CLKDEV_DEV_ID("rspi.2", &mstp_clks[MSTP127]),
 };
 int __init arch_clk_init(void)
diff --git a/arch/sh/kernel/dumpstack.c b/arch/sh/kernel/dumpstack.c
index b959f5592604..8dfe645bcc4b 100644
--- a/arch/sh/kernel/dumpstack.c
+++ b/arch/sh/kernel/dumpstack.c
@@ -115,7 +115,7 @@ static int print_trace_stack(void *data, char *name)
 */
 static void print_trace_address(void *data, unsigned long addr, int reliable)
 {
-        printk(data);
+        printk("%s", (char *)data);
        printk_address(addr, reliable);
 }
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index ca46834294b7..13047a4facd2 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -193,10 +193,10 @@ syscall_trace_entry:
        !                       Reload R0-R4 from kernel stack, where the
        !                       parent may have modified them using
        !                       ptrace(POKEUSR).  (Note that R0-R2 are
-        !                       used by the system call handler directly
+        !                       reloaded from the kernel stack by syscall_call
-        !                       from the kernel stack anyway, so don't need
+        !                       below, so don't need to be reloaded here.)
-        !                       to be reloaded here.)  This allows the parent
+        !                       This allows the parent to rewrite system calls
-        !                       to rewrite system calls and args on the fly.
+        !                       and args on the fly.
        mov.l   @(OFF_R4,r15), r4   ! arg0
        mov.l   @(OFF_R5,r15), r5
        mov.l   @(OFF_R6,r15), r6
@@ -357,8 +357,15 @@ syscall_call:
        mov.l   3f, r8          ! Load the address of sys_call_table
        add     r8, r3
        mov.l   @r3, r8
+        mov.l   @(OFF_R2,r15), r2
+        mov.l   @(OFF_R1,r15), r1
+        mov.l   @(OFF_R0,r15), r0
+        mov.l   r2, @-r15
+        mov.l   r1, @-r15
+        mov.l   r0, @-r15
        jsr     @r8             ! jump to specific syscall handler
         nop
+        add     #12, r15
        mov.l   @(OFF_R0,r15), r12              ! save r0
        mov.l   r0, @(OFF_R0,r15)               ! save the return value
        !
diff --git a/arch/sh/kernel/ftrace.c b/arch/sh/kernel/ftrace.c
index 30e13196d35b..3c74f53db6db 100644
--- a/arch/sh/kernel/ftrace.c
+++ b/arch/sh/kernel/ftrace.c
@@ -272,11 +272,8 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
        return ftrace_modify_code(rec->ip, old, new);
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        /* The return code is retured via data */
-        __raw_writel(0, (unsigned long)data);
        return 0;
 }
 #endif /* CONFIG_DYNAMIC_FTRACE */
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index c0a9761f2f8a..f8ce36286cea 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -22,7 +22,7 @@
 #define TRAPPED_PAGES_MAX 16
-#ifdef CONFIG_HAS_IOPORT
+#ifdef CONFIG_HAS_IOPORT_MAP
 LIST_HEAD(trapped_io);
 EXPORT_SYMBOL_GPL(trapped_io);
 #endif
@@ -90,7 +90,7 @@ int register_trapped_io(struct trapped_io *tiop)
        tiop->magic = IO_TRAPPED_MAGIC;
        INIT_LIST_HEAD(&tiop->list);
        spin_lock_irq(&trapped_lock);
-#ifdef CONFIG_HAS_IOPORT
+#ifdef CONFIG_HAS_IOPORT_MAP
        if (flags & IORESOURCE_IO)
                list_add(&tiop->list, &trapped_io);
 #endif
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index 6af6e7c5cac8..594cd371aa28 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -148,11 +148,9 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *r0_p
        return err;
 }
-asmlinkage int sys_sigreturn(unsigned long r4, unsigned long r5,
+asmlinkage int sys_sigreturn(void)
-                             unsigned long r6, unsigned long r7,
-                             struct pt_regs __regs)
 {
-        struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
+        struct pt_regs *regs = current_pt_regs();
        struct sigframe __user *frame = (struct sigframe __user *)regs->regs[15];
        sigset_t set;
        int r0;
@@ -180,11 +178,9 @@ badframe:
        return 0;
 }
-asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5,
+asmlinkage int sys_rt_sigreturn(void)
-                                unsigned long r6, unsigned long r7,
-                                struct pt_regs __regs)
 {
-        struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
+        struct pt_regs *regs = current_pt_regs();
        struct rt_sigframe __user *frame = (struct rt_sigframe __user *)regs->regs[15];
        sigset_t set;
        int r0;
diff --git a/arch/sh/kernel/sys_sh32.c b/arch/sh/kernel/sys_sh32.c
index 497bab3a0401..b66d1c62eb19 100644
--- a/arch/sh/kernel/sys_sh32.c
+++ b/arch/sh/kernel/sys_sh32.c
@@ -21,17 +21,14 @@
 * sys_pipe() is the normal C calling standard for creating
 * a pipe. It's not the way Unix traditionally does this, though.
 */
-asmlinkage int sys_sh_pipe(unsigned long r4, unsigned long r5,
+asmlinkage int sys_sh_pipe(void)
-        unsigned long r6, unsigned long r7,
-        struct pt_regs __regs)
 {
-        struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
        int fd[2];
        int error;
        error = do_pipe_flags(fd, 0);
        if (!error) {
-                regs->regs[1] = fd[1];
+                current_pt_regs()->regs[1] = fd[1];
                return fd[0];
        }
        return error;
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 68e99f09171d..ff639342a8be 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -594,9 +594,7 @@ int is_dsp_inst(struct pt_regs *regs)
 #endif /* CONFIG_SH_DSP */
 #ifdef CONFIG_CPU_SH2A
-asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
+asmlinkage void do_divide_error(unsigned long r4)
-                                unsigned long r6, unsigned long r7,
-                                struct pt_regs __regs)
 {
        siginfo_t info;
@@ -613,11 +611,9 @@ asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 }
 #endif
-asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
+asmlinkage void do_reserved_inst(void)
-                                unsigned long r6, unsigned long r7,
-                                struct pt_regs __regs)
 {
-        struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
+        struct pt_regs *regs = current_pt_regs();
        unsigned long error_code;
        struct task_struct *tsk = current;
@@ -701,11 +697,9 @@ static int emulate_branch(unsigned short inst, struct pt_regs *regs)
 }
 #endif
-asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
+asmlinkage void do_illegal_slot_inst(void)
-                                unsigned long r6, unsigned long r7,
-                                struct pt_regs __regs)
 {
-        struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
+        struct pt_regs *regs = current_pt_regs();
        unsigned long inst;
        struct task_struct *tsk = current;
@@ -730,15 +724,12 @@ asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
        die_if_no_fixup("illegal slot instruction", regs, inst);
 }
-asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
+asmlinkage void do_exception_error(void)
-                                   unsigned long r6, unsigned long r7,
-                                   struct pt_regs __regs)
 {
-        struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
        long ex;
        ex = lookup_exception_vector();
-        die_if_kernel("exception", regs, ex);
+        die_if_kernel("exception", current_pt_regs(), ex);
 }
 void per_cpu_trap_init(void)
diff --git a/arch/sh/math-emu/math.c b/arch/sh/math-emu/math.c
index b876780c1e1c..04aa55fa8c75 100644
--- a/arch/sh/math-emu/math.c
+++ b/arch/sh/math-emu/math.c
@@ -574,24 +574,6 @@ static int ieee_fpe_handler(struct pt_regs *regs)
        return 0;
 }
-asmlinkage void do_fpu_error(unsigned long r4, unsigned long r5,
-                             unsigned long r6, unsigned long r7,
-                             struct pt_regs regs)
-{
-        struct task_struct *tsk = current;
-        siginfo_t info;
-        if (ieee_fpe_handler (&regs))
-                return;
-        regs.pc += 2;
-        info.si_signo = SIGFPE;
-        info.si_errno = 0;
-        info.si_code = FPE_FLTINV;
-        info.si_addr = (void __user *)regs.pc;
-        force_sig_info(SIGFPE, &info, tsk);
-}
 /**
 * fpu_init - Initialize FPU registers
 * @fpu: Pointer to software emulated FPU registers.
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 7d8b7e94b93b..29f2e988c56a 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -77,6 +77,7 @@ config SPARC64
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
        select HAVE_C_RECORDMCOUNT
        select NO_BOOTMEM
+        select HAVE_ARCH_AUDITSYSCALL
 config ARCH_DEFCONFIG
        string
diff --git a/arch/sparc/kernel/ftrace.c b/arch/sparc/kernel/ftrace.c
index 03ab022e51c5..0a2d2ddff543 100644
--- a/arch/sparc/kernel/ftrace.c
+++ b/arch/sparc/kernel/ftrace.c
@@ -82,12 +82,8 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
        return ftrace_modify_code(ip, old, new);
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        unsigned long *p = data;
-        *p = 0;
        return 0;
 }
 #endif
diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c
index 88aaaa57bb64..e16c4157e1ae 100644
--- a/arch/sparc/kernel/leon_pci.c
+++ b/arch/sparc/kernel/leon_pci.c
@@ -99,11 +99,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
        return res->start;
 }
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
-        return pci_enable_resources(dev, mask);
-}
 /* in/out routines taken from pcic.c
 *
 * This probably belongs here rather than ioport.c because
diff --git a/arch/sparc/kernel/leon_pci_grpci2.c b/arch/sparc/kernel/leon_pci_grpci2.c
index 5f0402aab7fb..24d6a4446349 100644
--- a/arch/sparc/kernel/leon_pci_grpci2.c
+++ b/arch/sparc/kernel/leon_pci_grpci2.c
@@ -8,6 +8,7 @@
 #include <linux/of_device.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/export.h>
 #include <asm/io.h>
diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c
index c5ade9d27a1d..8bb3b3fddea7 100644
--- a/arch/sparc/kernel/sun4m_irq.c
+++ b/arch/sparc/kernel/sun4m_irq.c
@@ -9,6 +9,8 @@
 *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
 */
+#include <linux/slab.h>
 #include <asm/timer.h>
 #include <asm/traps.h>
 #include <asm/pgalloc.h>
diff --git a/arch/sparc/kernel/sysfs.c b/arch/sparc/kernel/sysfs.c
index c21c673e5f7c..a364000ca1aa 100644
--- a/arch/sparc/kernel/sysfs.c
+++ b/arch/sparc/kernel/sysfs.c
@@ -300,7 +300,7 @@ static int __init topology_init(void)
        check_mmu_stats();
-        register_cpu_notifier(&sysfs_cpu_nb);
+        cpu_notifier_register_begin();
        for_each_possible_cpu(cpu) {
                struct cpu *c = &per_cpu(cpu_devices, cpu);
@@ -310,6 +310,10 @@ static int __init topology_init(void)
                        register_cpu_online(cpu);
        }
+        __register_cpu_notifier(&sysfs_cpu_nb);
+        cpu_notifier_register_done();
        return 0;
 }
diff --git a/arch/sparc/kernel/time_64.c b/arch/sparc/kernel/time_64.c
index 24e8b8705e7f..3fddf64c7fc6 100644
--- a/arch/sparc/kernel/time_64.c
+++ b/arch/sparc/kernel/time_64.c
@@ -659,8 +659,7 @@ static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val
                ft->clock_tick_ref = cpu_data(cpu).clock_tick;
        }
        if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
-            (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
+            (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
-            (val == CPUFREQ_RESUMECHANGE)) {
                cpu_data(cpu).clock_tick =
                        cpufreq_scale(ft->clock_tick_ref,
                                      ft->ref_freq,
diff --git a/arch/sparc/net/bpf_jit_comp.c b/arch/sparc/net/bpf_jit_comp.c
index 01fe9946d388..a82c6b2a9780 100644
--- a/arch/sparc/net/bpf_jit_comp.c
+++ b/arch/sparc/net/bpf_jit_comp.c
@@ -618,7 +618,7 @@ void bpf_jit_compile(struct sk_filter *fp)
                                emit_load16(r_A, struct net_device, type, r_A);
                                break;
                        case BPF_S_ANC_RXHASH:
-                                emit_skb_load32(rxhash, r_A);
+                                emit_skb_load32(hash, r_A);
                                break;
                        case BPF_S_ANC_VLAN_TAG:
                        case BPF_S_ANC_VLAN_TAG_PRESENT:
@@ -809,6 +809,7 @@ cond_branch:			f_offset = addrs[i + filter[i].jf];
        if (image) {
                bpf_flush_icache(image, image + proglen);
                fp->bpf_func = (void *)image;
+                fp->jited = 1;
        }
 out:
        kfree(addrs);
@@ -817,7 +818,7 @@ out:
 void bpf_jit_free(struct sk_filter *fp)
 {
-        if (fp->bpf_func != sk_run_filter)
+        if (fp->jited)
                module_free(NULL, fp->bpf_func);
        kfree(fp);
 }
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index b3692ce78f90..85258ca43ff5 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -3,6 +3,8 @@
 config TILE
        def_bool y
+        select HAVE_PERF_EVENTS
+        select USE_PMC if PERF_EVENTS
        select HAVE_DMA_ATTRS
        select HAVE_DMA_API_DEBUG
        select HAVE_KVM if !TILEGX
@@ -66,6 +68,10 @@ config HUGETLB_SUPER_PAGES
 config GENERIC_TIME_VSYSCALL
        def_bool y
+# Enable PMC if PERF_EVENTS, OPROFILE, or WATCHPOINTS are enabled.
+config USE_PMC
+        bool
 # FIXME: tilegx can implement a more efficient rwsem.
 config RWSEM_GENERIC_SPINLOCK
        def_bool y
@@ -405,7 +411,7 @@ config PCI_DOMAINS
 config NO_IOMEM
        def_bool !PCI
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool !PCI
 config TILE_PCI_IO
diff --git a/arch/tile/include/asm/perf_event.h b/arch/tile/include/asm/perf_event.h
new file mode 100644
index 000000000000..59c5b164e5b6
--- /dev/null
+++ b/arch/tile/include/asm/perf_event.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+#ifndef _ASM_TILE_PERF_EVENT_H
+#define _ASM_TILE_PERF_EVENT_H
+#include <linux/percpu.h>
+DECLARE_PER_CPU(u64, perf_irqs);
+unsigned long handle_syscall_link_address(void);
+#endif /* _ASM_TILE_PERF_EVENT_H */
diff --git a/arch/tile/include/asm/pmc.h b/arch/tile/include/asm/pmc.h
new file mode 100644
index 000000000000..7ae3956d9008
--- /dev/null
+++ b/arch/tile/include/asm/pmc.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2014 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+#ifndef _ASM_TILE_PMC_H
+#define _ASM_TILE_PMC_H
+#include <linux/ptrace.h>
+#define TILE_BASE_COUNTERS      2
+/* Bitfields below are derived from SPR PERF_COUNT_CTL*/
+#ifndef __tilegx__
+/* PERF_COUNT_CTL on TILEPro */
+#define TILE_CTL_EXCL_USER      (1 << 7) /* exclude user level */
+#define TILE_CTL_EXCL_KERNEL    (1 << 8) /* exclude kernel level */
+#define TILE_CTL_EXCL_HV        (1 << 9) /* exclude hypervisor level */
+#define TILE_SEL_MASK           0x7f    /* 7 bits for event SEL,
+                                        COUNT_0_SEL */
+#define TILE_PLM_MASK           0x780   /* 4 bits priv level msks,
+                                        COUNT_0_MASK*/
+#define TILE_EVENT_MASK (TILE_SEL_MASK | TILE_PLM_MASK)
+#else /* __tilegx__*/
+/* PERF_COUNT_CTL on TILEGx*/
+#define TILE_CTL_EXCL_USER      (1 << 10) /* exclude user level */
+#define TILE_CTL_EXCL_KERNEL    (1 << 11) /* exclude kernel level */
+#define TILE_CTL_EXCL_HV        (1 << 12) /* exclude hypervisor level */
+#define TILE_SEL_MASK           0x3f    /* 6 bits for event SEL,
+                                        COUNT_0_SEL*/
+#define TILE_BOX_MASK           0x1c0   /* 3 bits box msks,
+                                        COUNT_0_BOX */
+#define TILE_PLM_MASK           0x3c00  /* 4 bits priv level msks,
+                                        COUNT_0_MASK */
+#define TILE_EVENT_MASK (TILE_SEL_MASK | TILE_BOX_MASK | TILE_PLM_MASK)
+#endif /* __tilegx__*/
+/* Takes register and fault number.  Returns error to disable the interrupt. */
+typedef int (*perf_irq_t)(struct pt_regs *, int);
+int userspace_perf_handler(struct pt_regs *regs, int fault);
+perf_irq_t reserve_pmc_hardware(perf_irq_t new_perf_irq);
+void release_pmc_hardware(void);
+unsigned long pmc_get_overflow(void);
+void pmc_ack_overflow(unsigned long status);
+void unmask_pmc_interrupts(void);
+void mask_pmc_interrupts(void);
+#endif /* _ASM_TILE_PMC_H */
diff --git a/arch/tile/kernel/Makefile b/arch/tile/kernel/Makefile
index 27a2bf39dae8..21f77bf68c69 100644
--- a/arch/tile/kernel/Makefile
+++ b/arch/tile/kernel/Makefile
@@ -25,6 +25,8 @@ obj-$(CONFIG_PCI)		+= pci_gx.o
 else
 obj-$(CONFIG_PCI)               += pci.o
 endif
+obj-$(CONFIG_PERF_EVENTS)       += perf_event.o
+obj-$(CONFIG_USE_PMC)           += pmc.o
 obj-$(CONFIG_TILE_USB)          += usb.o
 obj-$(CONFIG_TILE_HVGLUE_TRACE) += hvglue_trace.o
 obj-$(CONFIG_FUNCTION_TRACER)   += ftrace.o mcount_64.o
diff --git a/arch/tile/kernel/ftrace.c b/arch/tile/kernel/ftrace.c
index f1c452092eeb..8d52d83cc516 100644
--- a/arch/tile/kernel/ftrace.c
+++ b/arch/tile/kernel/ftrace.c
@@ -167,10 +167,8 @@ int ftrace_make_nop(struct module *mod,
        return ret;
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        *(unsigned long *)data = 0;
        return 0;
 }
 #endif /* CONFIG_DYNAMIC_FTRACE */
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
index 2cbe6d5dd6b0..cdbda45a4e4b 100644
--- a/arch/tile/kernel/intvec_32.S
+++ b/arch/tile/kernel/intvec_32.S
@@ -313,13 +313,13 @@ intvec_\vecname:
         movei  r3, 0
        }
        .else
-        .ifc \c_routine, op_handle_perf_interrupt
+        .ifc \c_routine, handle_perf_interrupt
        {
         mfspr  r2, PERF_COUNT_STS
         movei  r3, -1   /* not used, but set for consistency */
        }
        .else
-        .ifc \c_routine, op_handle_aux_perf_interrupt
+        .ifc \c_routine, handle_perf_interrupt
        {
         mfspr  r2, AUX_PERF_COUNT_STS
         movei  r3, -1   /* not used, but set for consistency */
@@ -946,6 +946,13 @@ STD_ENTRY(interrupt_return)
        bzt     r30, .Lrestore_regs
 3:
+        /* We are relying on INT_PERF_COUNT at 33, and AUX_PERF_COUNT at 48 */
+        {
+         moveli r0, lo16(1 << (INT_PERF_COUNT - 32))
+         bz     r31, .Lrestore_regs
+        }
+        auli    r0, r0, ha16(1 << (INT_AUX_PERF_COUNT - 32))
+        mtspr   SPR_INTERRUPT_MASK_RESET_K_1, r0
        /*
         * We now commit to returning from this interrupt, since we will be
@@ -1171,6 +1178,10 @@ handle_nmi:
         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
        }
        FEEDBACK_REENTER(handle_nmi)
+        {
+         movei  r30, 1
+         seq    r31, r0, zero
+        }
        j       interrupt_return
        STD_ENDPROC(handle_nmi)
@@ -1835,8 +1846,9 @@ int_unalign:
 /* Include .intrpt array of interrupt vectors */
        .section ".intrpt", "ax"
-#define op_handle_perf_interrupt bad_intr
+#ifndef CONFIG_USE_PMC
-#define op_handle_aux_perf_interrupt bad_intr
+#define handle_perf_interrupt bad_intr
+#endif
 #ifndef CONFIG_HARDWALL
 #define do_hardwall_trap bad_intr
@@ -1877,7 +1889,7 @@ int_unalign:
        int_hand     INT_IDN_AVAIL, IDN_AVAIL, bad_intr
        int_hand     INT_UDN_AVAIL, UDN_AVAIL, bad_intr
        int_hand     INT_PERF_COUNT, PERF_COUNT, \
-                     op_handle_perf_interrupt, handle_nmi
+                     handle_perf_interrupt, handle_nmi
        int_hand     INT_INTCTRL_3, INTCTRL_3, bad_intr
 #if CONFIG_KERNEL_PL == 2
        dc_dispatch  INT_INTCTRL_2, INTCTRL_2
@@ -1902,7 +1914,7 @@ int_unalign:
        int_hand     INT_SN_CPL, SN_CPL, bad_intr
        int_hand     INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
        int_hand     INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
-                     op_handle_aux_perf_interrupt, handle_nmi
+                     handle_perf_interrupt, handle_nmi
        /* Synthetic interrupt delivered only by the simulator */
        int_hand     INT_BREAKPOINT, BREAKPOINT, do_breakpoint
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
index b8fc497f2437..5b67efcecabd 100644
--- a/arch/tile/kernel/intvec_64.S
+++ b/arch/tile/kernel/intvec_64.S
@@ -509,10 +509,10 @@ intvec_\vecname:
        .ifc \c_routine, do_trap
        mfspr   r2, GPV_REASON
        .else
-        .ifc \c_routine, op_handle_perf_interrupt
+        .ifc \c_routine, handle_perf_interrupt
        mfspr   r2, PERF_COUNT_STS
        .else
-        .ifc \c_routine, op_handle_aux_perf_interrupt
+        .ifc \c_routine, handle_perf_interrupt
        mfspr   r2, AUX_PERF_COUNT_STS
        .endif
        .endif
@@ -971,6 +971,15 @@ STD_ENTRY(interrupt_return)
        beqzt   r30, .Lrestore_regs
 3:
+#if INT_PERF_COUNT + 1 != INT_AUX_PERF_COUNT
+# error Bad interrupt assumption
+#endif
+        {
+         movei  r0, 3   /* two adjacent bits for the PERF_COUNT mask */
+         beqz   r31, .Lrestore_regs
+        }
+        shli    r0, r0, INT_PERF_COUNT
+        mtspr   SPR_INTERRUPT_MASK_RESET_K, r0
        /*
         * We now commit to returning from this interrupt, since we will be
@@ -1187,7 +1196,7 @@ handle_nmi:
        FEEDBACK_REENTER(handle_nmi)
        {
         movei  r30, 1
-         move   r31, r0
+         cmpeq  r31, r0, zero
        }
        j       interrupt_return
        STD_ENDPROC(handle_nmi)
@@ -1491,8 +1500,9 @@ STD_ENTRY(fill_ra_stack)
        .global intrpt_start
 intrpt_start:
-#define op_handle_perf_interrupt bad_intr
+#ifndef CONFIG_USE_PMC
-#define op_handle_aux_perf_interrupt bad_intr
+#define handle_perf_interrupt bad_intr
+#endif
 #ifndef CONFIG_HARDWALL
 #define do_hardwall_trap bad_intr
@@ -1540,9 +1550,9 @@ intrpt_start:
 #endif
        int_hand     INT_IPI_0, IPI_0, bad_intr
        int_hand     INT_PERF_COUNT, PERF_COUNT, \
-                     op_handle_perf_interrupt, handle_nmi
+                     handle_perf_interrupt, handle_nmi
        int_hand     INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
-                     op_handle_perf_interrupt, handle_nmi
+                     handle_perf_interrupt, handle_nmi
        int_hand     INT_INTCTRL_3, INTCTRL_3, bad_intr
 #if CONFIG_KERNEL_PL == 2
        dc_dispatch  INT_INTCTRL_2, INTCTRL_2
diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c
index 0586fdb9352d..906a76bdb31d 100644
--- a/arch/tile/kernel/irq.c
+++ b/arch/tile/kernel/irq.c
@@ -21,6 +21,7 @@
 #include <hv/drv_pcie_rc_intf.h>
 #include <arch/spr_def.h>
 #include <asm/traps.h>
+#include <linux/perf_event.h>
 /* Bit-flag stored in irq_desc->chip_data to indicate HW-cleared irqs. */
 #define IS_HW_CLEARED 1
@@ -261,6 +262,23 @@ void ack_bad_irq(unsigned int irq)
 }
 /*
+ * /proc/interrupts printing:
+ */
+int arch_show_interrupts(struct seq_file *p, int prec)
+{
+#ifdef CONFIG_PERF_EVENTS
+        int i;
+        seq_printf(p, "%*s: ", prec, "PMI");
+        for_each_online_cpu(i)
+                seq_printf(p, "%10llu ", per_cpu(perf_irqs, i));
+        seq_puts(p, "  perf_events\n");
+#endif
+        return 0;
+}
+/*
 * Generic, controller-independent functions:
 */
diff --git a/arch/tile/kernel/messaging.c b/arch/tile/kernel/messaging.c
index 00331af9525d..7867266f9716 100644
--- a/arch/tile/kernel/messaging.c
+++ b/arch/tile/kernel/messaging.c
@@ -68,8 +68,8 @@ void hv_message_intr(struct pt_regs *regs, int intnum)
 #endif
        while (1) {
-                rmi = hv_receive_message(__get_cpu_var(msg_state),
+                HV_MsgState *state = this_cpu_ptr(&msg_state);
-                                         (HV_VirtAddr) message,
+                rmi = hv_receive_message(*state, (HV_VirtAddr) message,
                                         sizeof(message));
                if (rmi.msglen == 0)
                        break;
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index c45593db7718..1f80a88c75a6 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -250,8 +250,6 @@ static void fixup_read_and_payload_sizes(void)
        /* Scan for the smallest maximum payload size. */
        for_each_pci_dev(dev) {
-                u32 devcap;
                if (!pci_is_pcie(dev))
                        continue;
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c
index a97a6452b812..077b7bc437e5 100644
--- a/arch/tile/kernel/pci_gx.c
+++ b/arch/tile/kernel/pci_gx.c
@@ -1065,18 +1065,6 @@ char *__init pcibios_setup(char *str)
 }
 /*
- * Enable memory address decoding, as appropriate, for the
- * device described by the 'dev' struct.
- *
- * This is called from the generic PCI layer, and can be called
- * for bridges or endpoints.
- */
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
-        return pci_enable_resources(dev, mask);
-}
-/*
 * Called for each device after PCI setup is done.
 * We initialize the PCI device capabilities conservatively, assuming that
 * all devices can only address the 32-bit DMA space. The exception here is
diff --git a/arch/tile/kernel/perf_event.c b/arch/tile/kernel/perf_event.c
new file mode 100644
index 000000000000..2bf6c9c135c1
--- /dev/null
+++ b/arch/tile/kernel/perf_event.c
@@ -0,0 +1,1005 @@
+/*
+ * Copyright 2014 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ *
+ * Perf_events support for Tile processor.
+ *
+ * This code is based upon the x86 perf event
+ * code, which is:
+ *
+ *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
+ *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
+ *  Copyright (C) 2009 Jaswinder Singh Rajput
+ *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
+ *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
+ *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
+ *  Copyright (C) 2009 Google, Inc., Stephane Eranian
+ */
+#include <linux/kprobes.h>
+#include <linux/kernel.h>
+#include <linux/kdebug.h>
+#include <linux/mutex.h>
+#include <linux/bitmap.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/perf_event.h>
+#include <linux/atomic.h>
+#include <asm/traps.h>
+#include <asm/stack.h>
+#include <asm/pmc.h>
+#include <hv/hypervisor.h>
+#define TILE_MAX_COUNTERS       4
+#define PERF_COUNT_0_IDX        0
+#define PERF_COUNT_1_IDX        1
+#define AUX_PERF_COUNT_0_IDX    2
+#define AUX_PERF_COUNT_1_IDX    3
+struct cpu_hw_events {
+        int                     n_events;
+        struct perf_event       *events[TILE_MAX_COUNTERS]; /* counter order */
+        struct perf_event       *event_list[TILE_MAX_COUNTERS]; /* enabled
+                                                                order */
+        int                     assign[TILE_MAX_COUNTERS];
+        unsigned long           active_mask[BITS_TO_LONGS(TILE_MAX_COUNTERS)];
+        unsigned long           used_mask;
+};
+/* TILE arch specific performance monitor unit */
+struct tile_pmu {
+        const char      *name;
+        int             version;
+        const int       *hw_events;     /* generic hw events table */
+        /* generic hw cache events table */
+        const int       (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
+                                       [PERF_COUNT_HW_CACHE_OP_MAX]
+                                       [PERF_COUNT_HW_CACHE_RESULT_MAX];
+        int             (*map_hw_event)(u64);    /*method used to map
+                                                  hw events */
+        int             (*map_cache_event)(u64); /*method used to map
+                                                  cache events */
+        u64             max_period;             /* max sampling period */
+        u64             cntval_mask;            /* counter width mask */
+        int             cntval_bits;            /* counter width */
+        int             max_events;             /* max generic hw events
+                                                in map */
+        int             num_counters;           /* number base + aux counters */
+        int             num_base_counters;      /* number base counters */
+};
+DEFINE_PER_CPU(u64, perf_irqs);
+static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
+#define TILE_OP_UNSUPP          (-1)
+#ifndef __tilegx__
+/* TILEPro hardware events map */
+static const int tile_hw_event_map[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 0x01, /* ONE */
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 0x06, /* MP_BUNDLE_RETIRED */
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = TILE_OP_UNSUPP,
+        [PERF_COUNT_HW_CACHE_MISSES]            = TILE_OP_UNSUPP,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x16, /*
+                                          MP_CONDITIONAL_BRANCH_ISSUED */
+        [PERF_COUNT_HW_BRANCH_MISSES]           = 0x14, /*
+                                          MP_CONDITIONAL_BRANCH_MISSPREDICT */
+        [PERF_COUNT_HW_BUS_CYCLES]              = TILE_OP_UNSUPP,
+};
+#else
+/* TILEGx hardware events map */
+static const int tile_hw_event_map[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 0x181, /* ONE */
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 0xdb, /* INSTRUCTION_BUNDLE */
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = TILE_OP_UNSUPP,
+        [PERF_COUNT_HW_CACHE_MISSES]            = TILE_OP_UNSUPP,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0xd9, /*
+                                                COND_BRANCH_PRED_CORRECT */
+        [PERF_COUNT_HW_BRANCH_MISSES]           = 0xda, /*
+                                                COND_BRANCH_PRED_INCORRECT */
+        [PERF_COUNT_HW_BUS_CYCLES]              = TILE_OP_UNSUPP,
+};
+#endif
+#define C(x) PERF_COUNT_HW_CACHE_##x
+/*
+ * Generalized hw caching related hw_event table, filled
+ * in on a per model basis. A value of -1 means
+ * 'not supported', any other value means the
+ * raw hw_event ID.
+ */
+#ifndef __tilegx__
+/* TILEPro hardware cache event map */
+static const int tile_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
+                                     [PERF_COUNT_HW_CACHE_OP_MAX]
+                                     [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = 0x21, /* RD_MISS */
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = 0x22, /* WR_MISS */
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(L1I)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = 0x12, /* MP_ICACHE_HIT_ISSUED */
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(LL)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(DTLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = 0x1d, /* TLB_CNT */
+                [C(RESULT_MISS)] = 0x20, /* TLB_EXCEPTION */
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(ITLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = 0x13, /* MP_ITLB_HIT_ISSUED */
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(BPU)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+};
+#else
+/* TILEGx hardware events map */
+static const int tile_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
+                                     [PERF_COUNT_HW_CACHE_OP_MAX]
+                                     [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+        /*
+         * Like some other architectures (e.g. ARM), the performance
+         * counters don't differentiate between read and write
+         * accesses/misses, so this isn't strictly correct, but it's the
+         * best we can do. Writes and reads get combined.
+         */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = 0x44, /* RD_MISS */
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = 0x45, /* WR_MISS */
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(L1I)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(LL)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(DTLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = 0x40, /* TLB_CNT */
+                [C(RESULT_MISS)] = 0x43, /* TLB_EXCEPTION */
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = 0x40, /* TLB_CNT */
+                [C(RESULT_MISS)] = 0x43, /* TLB_EXCEPTION */
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(ITLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = 0xd4, /* ITLB_MISS_INT */
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = 0xd4, /* ITLB_MISS_INT */
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+[C(BPU)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
+                [C(RESULT_MISS)] = TILE_OP_UNSUPP,
+        },
+},
+};
+#endif
+static atomic_t tile_active_events;
+static DEFINE_MUTEX(perf_intr_reserve_mutex);
+static int tile_map_hw_event(u64 config);
+static int tile_map_cache_event(u64 config);
+static int tile_pmu_handle_irq(struct pt_regs *regs, int fault);
+/*
+ * To avoid new_raw_count getting larger then pre_raw_count
+ * in tile_perf_event_update(), we limit the value of max_period to 2^31 - 1.
+ */
+static const struct tile_pmu tilepmu = {
+#ifndef __tilegx__
+        .name = "tilepro",
+#else
+        .name = "tilegx",
+#endif
+        .max_events = ARRAY_SIZE(tile_hw_event_map),
+        .map_hw_event = tile_map_hw_event,
+        .hw_events = tile_hw_event_map,
+        .map_cache_event = tile_map_cache_event,
+        .cache_events = &tile_cache_event_map,
+        .cntval_bits = 32,
+        .cntval_mask = (1ULL << 32) - 1,
+        .max_period = (1ULL << 31) - 1,
+        .num_counters = TILE_MAX_COUNTERS,
+        .num_base_counters = TILE_BASE_COUNTERS,
+};
+static const struct tile_pmu *tile_pmu __read_mostly;
+/*
+ * Check whether perf event is enabled.
+ */
+int tile_perf_enabled(void)
+{
+        return atomic_read(&tile_active_events) != 0;
+}
+/*
+ * Read Performance Counters.
+ */
+static inline u64 read_counter(int idx)
+{
+        u64 val = 0;
+        /* __insn_mfspr() only takes an immediate argument */
+        switch (idx) {
+        case PERF_COUNT_0_IDX:
+                val = __insn_mfspr(SPR_PERF_COUNT_0);
+                break;
+        case PERF_COUNT_1_IDX:
+                val = __insn_mfspr(SPR_PERF_COUNT_1);
+                break;
+        case AUX_PERF_COUNT_0_IDX:
+                val = __insn_mfspr(SPR_AUX_PERF_COUNT_0);
+                break;
+        case AUX_PERF_COUNT_1_IDX:
+                val = __insn_mfspr(SPR_AUX_PERF_COUNT_1);
+                break;
+        default:
+                WARN_ON_ONCE(idx > AUX_PERF_COUNT_1_IDX ||
+                                idx < PERF_COUNT_0_IDX);
+        }
+        return val;
+}
+/*
+ * Write Performance Counters.
+ */
+static inline void write_counter(int idx, u64 value)
+{
+        /* __insn_mtspr() only takes an immediate argument */
+        switch (idx) {
+        case PERF_COUNT_0_IDX:
+                __insn_mtspr(SPR_PERF_COUNT_0, value);
+                break;
+        case PERF_COUNT_1_IDX:
+                __insn_mtspr(SPR_PERF_COUNT_1, value);
+                break;
+        case AUX_PERF_COUNT_0_IDX:
+                __insn_mtspr(SPR_AUX_PERF_COUNT_0, value);
+                break;
+        case AUX_PERF_COUNT_1_IDX:
+                __insn_mtspr(SPR_AUX_PERF_COUNT_1, value);
+                break;
+        default:
+                WARN_ON_ONCE(idx > AUX_PERF_COUNT_1_IDX ||
+                                idx < PERF_COUNT_0_IDX);
+        }
+}
+/*
+ * Enable performance event by setting
+ * Performance Counter Control registers.
+ */
+static inline void tile_pmu_enable_event(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        unsigned long cfg, mask;
+        int shift, idx = hwc->idx;
+        /*
+         * prevent early activation from tile_pmu_start() in hw_perf_enable
+         */
+        if (WARN_ON_ONCE(idx == -1))
+                return;
+        if (idx < tile_pmu->num_base_counters)
+                cfg = __insn_mfspr(SPR_PERF_COUNT_CTL);
+        else
+                cfg = __insn_mfspr(SPR_AUX_PERF_COUNT_CTL);
+        switch (idx) {
+        case PERF_COUNT_0_IDX:
+        case AUX_PERF_COUNT_0_IDX:
+                mask = TILE_EVENT_MASK;
+                shift = 0;
+                break;
+        case PERF_COUNT_1_IDX:
+        case AUX_PERF_COUNT_1_IDX:
+                mask = TILE_EVENT_MASK << 16;
+                shift = 16;
+                break;
+        default:
+                WARN_ON_ONCE(idx < PERF_COUNT_0_IDX ||
+                        idx > AUX_PERF_COUNT_1_IDX);
+                return;
+        }
+        /* Clear mask bits to enable the event. */
+        cfg &= ~mask;
+        cfg |= hwc->config << shift;
+        if (idx < tile_pmu->num_base_counters)
+                __insn_mtspr(SPR_PERF_COUNT_CTL, cfg);
+        else
+                __insn_mtspr(SPR_AUX_PERF_COUNT_CTL, cfg);
+}
+/*
+ * Disable performance event by clearing
+ * Performance Counter Control registers.
+ */
+static inline void tile_pmu_disable_event(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        unsigned long cfg, mask;
+        int idx = hwc->idx;
+        if (idx == -1)
+                return;
+        if (idx < tile_pmu->num_base_counters)
+                cfg = __insn_mfspr(SPR_PERF_COUNT_CTL);
+        else
+                cfg = __insn_mfspr(SPR_AUX_PERF_COUNT_CTL);
+        switch (idx) {
+        case PERF_COUNT_0_IDX:
+        case AUX_PERF_COUNT_0_IDX:
+                mask = TILE_PLM_MASK;
+                break;
+        case PERF_COUNT_1_IDX:
+        case AUX_PERF_COUNT_1_IDX:
+                mask = TILE_PLM_MASK << 16;
+                break;
+        default:
+                WARN_ON_ONCE(idx < PERF_COUNT_0_IDX ||
+                        idx > AUX_PERF_COUNT_1_IDX);
+                return;
+        }
+        /* Set mask bits to disable the event. */
+        cfg |= mask;
+        if (idx < tile_pmu->num_base_counters)
+                __insn_mtspr(SPR_PERF_COUNT_CTL, cfg);
+        else
+                __insn_mtspr(SPR_AUX_PERF_COUNT_CTL, cfg);
+}
+/*
+ * Propagate event elapsed time into the generic event.
+ * Can only be executed on the CPU where the event is active.
+ * Returns the delta events processed.
+ */
+static u64 tile_perf_event_update(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        int shift = 64 - tile_pmu->cntval_bits;
+        u64 prev_raw_count, new_raw_count;
+        u64 oldval;
+        int idx = hwc->idx;
+        u64 delta;
+        /*
+         * Careful: an NMI might modify the previous event value.
+         *
+         * Our tactic to handle this is to first atomically read and
+         * exchange a new raw count - then add that new-prev delta
+         * count to the generic event atomically:
+         */
+again:
+        prev_raw_count = local64_read(&hwc->prev_count);
+        new_raw_count = read_counter(idx);
+        oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                                 new_raw_count);
+        if (oldval != prev_raw_count)
+                goto again;
+        /*
+         * Now we have the new raw value and have updated the prev
+         * timestamp already. We can now calculate the elapsed delta
+         * (event-)time and add that to the generic event.
+         *
+         * Careful, not all hw sign-extends above the physical width
+         * of the count.
+         */
+        delta = (new_raw_count << shift) - (prev_raw_count << shift);
+        delta >>= shift;
+        local64_add(delta, &event->count);
+        local64_sub(delta, &hwc->period_left);
+        return new_raw_count;
+}
+/*
+ * Set the next IRQ period, based on the hwc->period_left value.
+ * To be called with the event disabled in hw:
+ */
+static int tile_event_set_period(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+        s64 left = local64_read(&hwc->period_left);
+        s64 period = hwc->sample_period;
+        int ret = 0;
+        /*
+         * If we are way outside a reasonable range then just skip forward:
+         */
+        if (unlikely(left <= -period)) {
+                left = period;
+                local64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+        if (unlikely(left <= 0)) {
+                left += period;
+                local64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+        if (left > tile_pmu->max_period)
+                left = tile_pmu->max_period;
+        /*
+         * The hw event starts counting from this event offset,
+         * mark it to be able to extra future deltas:
+         */
+        local64_set(&hwc->prev_count, (u64)-left);
+        write_counter(idx, (u64)(-left) & tile_pmu->cntval_mask);
+        perf_event_update_userpage(event);
+        return ret;
+}
+/*
+ * Stop the event but do not release the PMU counter
+ */
+static void tile_pmu_stop(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+        if (__test_and_clear_bit(idx, cpuc->active_mask)) {
+                tile_pmu_disable_event(event);
+                cpuc->events[hwc->idx] = NULL;
+                WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+                hwc->state |= PERF_HES_STOPPED;
+        }
+        if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
+                /*
+                 * Drain the remaining delta count out of a event
+                 * that we are disabling:
+                 */
+                tile_perf_event_update(event);
+                hwc->state |= PERF_HES_UPTODATE;
+        }
+}
+/*
+ * Start an event (without re-assigning counter)
+ */
+static void tile_pmu_start(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        int idx = event->hw.idx;
+        if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
+                return;
+        if (WARN_ON_ONCE(idx == -1))
+                return;
+        if (flags & PERF_EF_RELOAD) {
+                WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
+                tile_event_set_period(event);
+        }
+        event->hw.state = 0;
+        cpuc->events[idx] = event;
+        __set_bit(idx, cpuc->active_mask);
+        unmask_pmc_interrupts();
+        tile_pmu_enable_event(event);
+        perf_event_update_userpage(event);
+}
+/*
+ * Add a single event to the PMU.
+ *
+ * The event is added to the group of enabled events
+ * but only if it can be scehduled with existing events.
+ */
+static int tile_pmu_add(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc;
+        unsigned long mask;
+        int b, max_cnt;
+        hwc = &event->hw;
+        /*
+         * We are full.
+         */
+        if (cpuc->n_events == tile_pmu->num_counters)
+                return -ENOSPC;
+        cpuc->event_list[cpuc->n_events] = event;
+        cpuc->n_events++;
+        hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+        if (!(flags & PERF_EF_START))
+                hwc->state |= PERF_HES_ARCH;
+        /*
+         * Find first empty counter.
+         */
+        max_cnt = tile_pmu->num_counters;
+        mask = ~cpuc->used_mask;
+        /* Find next free counter. */
+        b = find_next_bit(&mask, max_cnt, 0);
+        /* Should not happen. */
+        if (WARN_ON_ONCE(b == max_cnt))
+                return -ENOSPC;
+        /*
+         * Assign counter to event.
+         */
+        event->hw.idx = b;
+        __set_bit(b, &cpuc->used_mask);
+        /*
+         * Start if requested.
+         */
+        if (flags & PERF_EF_START)
+                tile_pmu_start(event, PERF_EF_RELOAD);
+        return 0;
+}
+/*
+ * Delete a single event from the PMU.
+ *
+ * The event is deleted from the group of enabled events.
+ * If it is the last event, disable PMU interrupt.
+ */
+static void tile_pmu_del(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        int i;
+        /*
+         * Remove event from list, compact list if necessary.
+         */
+        for (i = 0; i < cpuc->n_events; i++) {
+                if (cpuc->event_list[i] == event) {
+                        while (++i < cpuc->n_events)
+                                cpuc->event_list[i-1] = cpuc->event_list[i];
+                        --cpuc->n_events;
+                        cpuc->events[event->hw.idx] = NULL;
+                        __clear_bit(event->hw.idx, &cpuc->used_mask);
+                        tile_pmu_stop(event, PERF_EF_UPDATE);
+                        break;
+                }
+        }
+        /*
+         * If there are no events left, then mask PMU interrupt.
+         */
+        if (cpuc->n_events == 0)
+                mask_pmc_interrupts();
+        perf_event_update_userpage(event);
+}
+/*
+ * Propagate event elapsed time into the event.
+ */
+static inline void tile_pmu_read(struct perf_event *event)
+{
+        tile_perf_event_update(event);
+}
+/*
+ * Map generic events to Tile PMU.
+ */
+static int tile_map_hw_event(u64 config)
+{
+        if (config >= tile_pmu->max_events)
+                return -EINVAL;
+        return tile_pmu->hw_events[config];
+}
+/*
+ * Map generic hardware cache events to Tile PMU.
+ */
+static int tile_map_cache_event(u64 config)
+{
+        unsigned int cache_type, cache_op, cache_result;
+        int code;
+        if (!tile_pmu->cache_events)
+                return -ENOENT;
+        cache_type = (config >>  0) & 0xff;
+        if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+                return -EINVAL;
+        cache_op = (config >>  8) & 0xff;
+        if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+                return -EINVAL;
+        cache_result = (config >> 16) & 0xff;
+        if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+                return -EINVAL;
+        code = (*tile_pmu->cache_events)[cache_type][cache_op][cache_result];
+        if (code == TILE_OP_UNSUPP)
+                return -EINVAL;
+        return code;
+}
+static void tile_event_destroy(struct perf_event *event)
+{
+        if (atomic_dec_return(&tile_active_events) == 0)
+                release_pmc_hardware();
+}
+static int __tile_event_init(struct perf_event *event)
+{
+        struct perf_event_attr *attr = &event->attr;
+        struct hw_perf_event *hwc = &event->hw;
+        int code;
+        switch (attr->type) {
+        case PERF_TYPE_HARDWARE:
+                code = tile_pmu->map_hw_event(attr->config);
+                break;
+        case PERF_TYPE_HW_CACHE:
+                code = tile_pmu->map_cache_event(attr->config);
+                break;
+        case PERF_TYPE_RAW:
+                code = attr->config & TILE_EVENT_MASK;
+                break;
+        default:
+                /* Should not happen. */
+                return -EOPNOTSUPP;
+        }
+        if (code < 0)
+                return code;
+        hwc->config = code;
+        hwc->idx = -1;
+        if (attr->exclude_user)
+                hwc->config |= TILE_CTL_EXCL_USER;
+        if (attr->exclude_kernel)
+                hwc->config |= TILE_CTL_EXCL_KERNEL;
+        if (attr->exclude_hv)
+                hwc->config |= TILE_CTL_EXCL_HV;
+        if (!hwc->sample_period) {
+                hwc->sample_period = tile_pmu->max_period;
+                hwc->last_period = hwc->sample_period;
+                local64_set(&hwc->period_left, hwc->sample_period);
+        }
+        event->destroy = tile_event_destroy;
+        return 0;
+}
+static int tile_event_init(struct perf_event *event)
+{
+        int err = 0;
+        perf_irq_t old_irq_handler = NULL;
+        if (atomic_inc_return(&tile_active_events) == 1)
+                old_irq_handler = reserve_pmc_hardware(tile_pmu_handle_irq);
+        if (old_irq_handler) {
+                pr_warn("PMC hardware busy (reserved by oprofile)\n");
+                atomic_dec(&tile_active_events);
+                return -EBUSY;
+        }
+        switch (event->attr.type) {
+        case PERF_TYPE_RAW:
+        case PERF_TYPE_HARDWARE:
+        case PERF_TYPE_HW_CACHE:
+                break;
+        default:
+                return -ENOENT;
+        }
+        err = __tile_event_init(event);
+        if (err) {
+                if (event->destroy)
+                        event->destroy(event);
+        }
+        return err;
+}
+static struct pmu tilera_pmu = {
+        .event_init     = tile_event_init,
+        .add            = tile_pmu_add,
+        .del            = tile_pmu_del,
+        .start          = tile_pmu_start,
+        .stop           = tile_pmu_stop,
+        .read           = tile_pmu_read,
+};
+/*
+ * PMU's IRQ handler, PMU has 2 interrupts, they share the same handler.
+ */
+int tile_pmu_handle_irq(struct pt_regs *regs, int fault)
+{
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct perf_event *event;
+        struct hw_perf_event *hwc;
+        u64 val;
+        unsigned long status;
+        int bit;
+        __get_cpu_var(perf_irqs)++;
+        if (!atomic_read(&tile_active_events))
+                return 0;
+        status = pmc_get_overflow();
+        pmc_ack_overflow(status);
+        for_each_set_bit(bit, &status, tile_pmu->num_counters) {
+                event = cpuc->events[bit];
+                if (!event)
+                        continue;
+                if (!test_bit(bit, cpuc->active_mask))
+                        continue;
+                hwc = &event->hw;
+                val = tile_perf_event_update(event);
+                if (val & (1ULL << (tile_pmu->cntval_bits - 1)))
+                        continue;
+                perf_sample_data_init(&data, 0, event->hw.last_period);
+                if (!tile_event_set_period(event))
+                        continue;
+                if (perf_event_overflow(event, &data, regs))
+                        tile_pmu_stop(event, 0);
+        }
+        return 0;
+}
+static bool __init supported_pmu(void)
+{
+        tile_pmu = &tilepmu;
+        return true;
+}
+int __init init_hw_perf_events(void)
+{
+        supported_pmu();
+        perf_pmu_register(&tilera_pmu, "cpu", PERF_TYPE_RAW);
+        return 0;
+}
+arch_initcall(init_hw_perf_events);
+/* Callchain handling code. */
+/*
+ * Tile specific backtracing code for perf_events.
+ */
+static inline void perf_callchain(struct perf_callchain_entry *entry,
+                    struct pt_regs *regs)
+{
+        struct KBacktraceIterator kbt;
+        unsigned int i;
+        /*
+         * Get the address just after the "jalr" instruction that
+         * jumps to the handler for a syscall.  When we find this
+         * address in a backtrace, we silently ignore it, which gives
+         * us a one-step backtrace connection from the sys_xxx()
+         * function in the kernel to the xxx() function in libc.
+         * Otherwise, we lose the ability to properly attribute time
+         * from the libc calls to the kernel implementations, since
+         * oprofile only considers PCs from backtraces a pair at a time.
+         */
+        unsigned long handle_syscall_pc = handle_syscall_link_address();
+        KBacktraceIterator_init(&kbt, NULL, regs);
+        kbt.profile = 1;
+        /*
+         * The sample for the pc is already recorded.  Now we are adding the
+         * address of the callsites on the stack.  Our iterator starts
+         * with the frame of the (already sampled) call site.  If our
+         * iterator contained a "return address" field, we could have just
+         * used it and wouldn't have needed to skip the first
+         * frame.  That's in effect what the arm and x86 versions do.
+         * Instead we peel off the first iteration to get the equivalent
+         * behavior.
+         */
+        if (KBacktraceIterator_end(&kbt))
+                return;
+        KBacktraceIterator_next(&kbt);
+        /*
+         * Set stack depth to 16 for user and kernel space respectively, that
+         * is, total 32 stack frames.
+         */
+        for (i = 0; i < 16; ++i) {
+                unsigned long pc;
+                if (KBacktraceIterator_end(&kbt))
+                        break;
+                pc = kbt.it.pc;
+                if (pc != handle_syscall_pc)
+                        perf_callchain_store(entry, pc);
+                KBacktraceIterator_next(&kbt);
+        }
+}
+void perf_callchain_user(struct perf_callchain_entry *entry,
+                    struct pt_regs *regs)
+{
+        perf_callchain(entry, regs);
+}
+void perf_callchain_kernel(struct perf_callchain_entry *entry,
+                      struct pt_regs *regs)
+{
+        perf_callchain(entry, regs);
+}
diff --git a/arch/tile/kernel/pmc.c b/arch/tile/kernel/pmc.c
new file mode 100644
index 000000000000..db62cc34b955
--- /dev/null
+++ b/arch/tile/kernel/pmc.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2014 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <linux/atomic.h>
+#include <linux/interrupt.h>
+#include <asm/processor.h>
+#include <asm/pmc.h>
+perf_irq_t perf_irq = NULL;
+int handle_perf_interrupt(struct pt_regs *regs, int fault)
+{
+        int retval;
+        if (!perf_irq)
+                panic("Unexpected PERF_COUNT interrupt %d\n", fault);
+        nmi_enter();
+        retval = perf_irq(regs, fault);
+        nmi_exit();
+        return retval;
+}
+/* Reserve PMC hardware if it is available. */
+perf_irq_t reserve_pmc_hardware(perf_irq_t new_perf_irq)
+{
+        return cmpxchg(&perf_irq, NULL, new_perf_irq);
+}
+EXPORT_SYMBOL(reserve_pmc_hardware);
+/* Release PMC hardware. */
+void release_pmc_hardware(void)
+{
+        perf_irq = NULL;
+}
+EXPORT_SYMBOL(release_pmc_hardware);
+/*
+ * Get current overflow status of each performance counter,
+ * and auxiliary performance counter.
+ */
+unsigned long
+pmc_get_overflow(void)
+{
+        unsigned long status;
+        /*
+         * merge base+aux into a single vector
+         */
+        status = __insn_mfspr(SPR_PERF_COUNT_STS);
+        status |= __insn_mfspr(SPR_AUX_PERF_COUNT_STS) << TILE_BASE_COUNTERS;
+        return status;
+}
+/*
+ * Clear the status bit for the corresponding counter, if written
+ * with a one.
+ */
+void
+pmc_ack_overflow(unsigned long status)
+{
+        /*
+         * clear overflow status by writing ones
+         */
+        __insn_mtspr(SPR_PERF_COUNT_STS, status);
+        __insn_mtspr(SPR_AUX_PERF_COUNT_STS, status >> TILE_BASE_COUNTERS);
+}
+/*
+ * The perf count interrupts are masked and unmasked explicitly,
+ * and only here.  The normal irq_enable() does not enable them,
+ * and irq_disable() does not disable them.  That lets these
+ * routines drive the perf count interrupts orthogonally.
+ *
+ * We also mask the perf count interrupts on entry to the perf count
+ * interrupt handler in assembly code, and by default unmask them
+ * again (with interrupt critical section protection) just before
+ * returning from the interrupt.  If the perf count handler returns
+ * a non-zero error code, then we don't re-enable them before returning.
+ *
+ * For Pro, we rely on both interrupts being in the same word to update
+ * them atomically so we never have one enabled and one disabled.
+ */
+#if CHIP_HAS_SPLIT_INTR_MASK()
+# if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32
+#  error Fix assumptions about which word PERF_COUNT interrupts are in
+# endif
+#endif
+static inline unsigned long long pmc_mask(void)
+{
+        unsigned long long mask = 1ULL << INT_PERF_COUNT;
+        mask |= 1ULL << INT_AUX_PERF_COUNT;
+        return mask;
+}
+void unmask_pmc_interrupts(void)
+{
+        interrupt_mask_reset_mask(pmc_mask());
+}
+void mask_pmc_interrupts(void)
+{
+        interrupt_mask_set_mask(pmc_mask());
+}
diff --git a/arch/tile/kernel/time.c b/arch/tile/kernel/time.c
index 5d10642db63e..462dcd0c1700 100644
--- a/arch/tile/kernel/time.c
+++ b/arch/tile/kernel/time.c
@@ -236,7 +236,15 @@ cycles_t ns2cycles(unsigned long nsecs)
         * clock frequency.
         */
        struct clock_event_device *dev = &__raw_get_cpu_var(tile_timer);
-        return ((u64)nsecs * dev->mult) >> dev->shift;
+        /*
+         * as in clocksource.h and x86's timer.h, we split the calculation
+         * into 2 parts to avoid unecessary overflow of the intermediate
+         * value. This will not lead to any loss of precision.
+         */
+        u64 quot = (u64)nsecs >> dev->shift;
+        u64 rem  = (u64)nsecs & ((1ULL << dev->shift) - 1);
+        return quot * dev->mult + ((rem * dev->mult) >> dev->shift);
 }
 void update_vsyscall_tz(void)
diff --git a/arch/tile/kernel/vdso/Makefile b/arch/tile/kernel/vdso/Makefile
index e2b7a2f4ee41..a025f63d54cd 100644
--- a/arch/tile/kernel/vdso/Makefile
+++ b/arch/tile/kernel/vdso/Makefile
@@ -104,7 +104,7 @@ $(obj-vdso32:%=%): KBUILD_AFLAGS = $(KBUILD_AFLAGS_32)
 $(obj-vdso32:%=%): KBUILD_CFLAGS = $(KBUILD_CFLAGS_32)
 $(obj)/vgettimeofday32.o: $(obj)/vgettimeofday.c
-        $(call if_changed,cc_o_c)
+        $(call if_changed_rule,cc_o_c)
 $(obj)/vrt_sigreturn32.o: $(obj)/vrt_sigreturn.S
        $(call if_changed,as_o_S)
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common
index 21ca44c4f6d5..6915d28cf118 100644
--- a/arch/um/Kconfig.common
+++ b/arch/um/Kconfig.common
@@ -1,6 +1,7 @@
 config UML
        bool
        default y
+        select HAVE_ARCH_AUDITSYSCALL
        select HAVE_UID16
        select GENERIC_IRQ_SHOW
        select GENERIC_CPU_DEVICES
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index 39f186252e02..7d26d9c0b2fb 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -240,7 +240,7 @@ static int uml_net_start_xmit(struct sk_buff *skb, struct net_device *dev)
        spin_unlock_irqrestore(&lp->lock, flags);
-        dev_kfree_skb(skb);
+        dev_consume_skb_any(skb);
        return NETDEV_TX_OK;
 }
diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c
index eecc4142764c..f17bca8ed2ce 100644
--- a/arch/um/kernel/process.c
+++ b/arch/um/kernel/process.c
@@ -359,7 +359,7 @@ int singlestepping(void * t)
 /*
 * Only x86 and x86_64 have an arch_align_stack().
 * All other arches have "#define arch_align_stack(x) (x)"
- * in their asm/system.h
+ * in their asm/exec.h
 * As this is included in UML from asm-um/system-generic.h,
 * we can use it to behave as the subarch does.
 */
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index 25c0dba508cc..aafad6fa1667 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -27,7 +27,7 @@ config UNICORE32
 config GENERIC_CSUM
        def_bool y
-config NO_IOPORT
+config NO_IOPORT_MAP
        bool
 config STACKTRACE_SUPPORT
diff --git a/arch/unicore32/include/asm/mmu_context.h b/arch/unicore32/include/asm/mmu_context.h
index fb5e4c658f7a..ef470a7a3d0f 100644
--- a/arch/unicore32/include/asm/mmu_context.h
+++ b/arch/unicore32/include/asm/mmu_context.h
@@ -14,6 +14,8 @@
 #include <linux/compiler.h>
 #include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/vmacache.h>
 #include <linux/io.h>
 #include <asm/cacheflush.h>
@@ -73,7 +75,7 @@ do { \
                else \
                        mm->mmap = NULL; \
                rb_erase(&high_vma->vm_rb, &mm->mm_rb); \
-                mm->mmap_cache = NULL; \
+                vmacache_invalidate(mm); \
                mm->map_count--; \
                remove_vma(high_vma); \
        } \
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 8453fe1342ea..25d2c6f7325e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -43,6 +43,7 @@ config X86
        select HAVE_DMA_ATTRS
        select HAVE_DMA_CONTIGUOUS if !SWIOTLB
        select HAVE_KRETPROBES
+        select GENERIC_EARLY_IOREMAP
        select HAVE_OPTPROBES
        select HAVE_KPROBES_ON_FTRACE
        select HAVE_FTRACE_MCOUNT_RECORD
@@ -107,9 +108,9 @@ config X86
        select HAVE_ARCH_SOFT_DIRTY
        select CLOCKSOURCE_WATCHDOG
        select GENERIC_CLOCKEVENTS
-        select ARCH_CLOCKSOURCE_DATA if X86_64
+        select ARCH_CLOCKSOURCE_DATA
        select GENERIC_CLOCKEVENTS_BROADCAST if X86_64 || (X86_32 && X86_LOCAL_APIC)
-        select GENERIC_TIME_VSYSCALL if X86_64
+        select GENERIC_TIME_VSYSCALL
        select KTIME_SCALAR if X86_32
        select GENERIC_STRNCPY_FROM_USER
        select GENERIC_STRNLEN_USER
@@ -127,6 +128,8 @@ config X86
        select HAVE_DEBUG_STACKOVERFLOW
        select HAVE_IRQ_EXIT_ON_IRQ_STACK if X86_64
        select HAVE_CC_STACKPROTECTOR
+        select GENERIC_CPU_AUTOPROBE
+        select HAVE_ARCH_AUDITSYSCALL
 config INSTRUCTION_DECODER
        def_bool y
@@ -195,9 +198,6 @@ config ARCH_HAS_CPU_RELAX
 config ARCH_HAS_CACHE_LINE_SIZE
        def_bool y
-config ARCH_HAS_CPU_AUTOPROBE
-        def_bool y
 config HAVE_SETUP_PER_CPU_AREA
        def_bool y
@@ -346,12 +346,9 @@ config X86_EXTENDED_PLATFORM
          for the following (non-PC) 32 bit x86 platforms:
                Goldfish (Android emulator)
                AMD Elan
-                NUMAQ (IBM/Sequent)
                RDC R-321x SoC
                SGI 320/540 (Visual Workstation)
                STA2X11-based (e.g. Northville)
-                Summit/EXA (IBM x440)
-                Unisys ES7000 IA32 series
                Moorestown MID devices
          If you have one of these systems, or if you want to build a
@@ -489,49 +486,22 @@ config X86_32_NON_STANDARD
        depends on X86_32 && SMP
        depends on X86_EXTENDED_PLATFORM
        ---help---
-          This option compiles in the NUMAQ, Summit, bigsmp, ES7000,
+          This option compiles in the bigsmp and STA2X11 default
-          STA2X11, default subarchitectures.  It is intended for a generic
+          subarchitectures.  It is intended for a generic binary
-          binary kernel. If you select them all, kernel will probe it
+          kernel. If you select them all, kernel will probe it one by
-          one by one and will fallback to default.
+          one and will fallback to default.
 # Alphabetically sorted list of Non standard 32 bit platforms
-config X86_NUMAQ
-        bool "NUMAQ (IBM/Sequent)"
-        depends on X86_32_NON_STANDARD
-        depends on PCI
-        select NUMA
-        select X86_MPPARSE
-        ---help---
-          This option is used for getting Linux to run on a NUMAQ (IBM/Sequent)
-          NUMA multiquad box. This changes the way that processors are
-          bootstrapped, and uses Clustered Logical APIC addressing mode instead
-          of Flat Logical.  You will need a new lynxer.elf file to flash your
-          firmware with - send email to <Martin.Bligh@us.ibm.com>.
 config X86_SUPPORTS_MEMORY_FAILURE
        def_bool y
        # MCE code calls memory_failure():
        depends on X86_MCE
        # On 32-bit this adds too big of NODES_SHIFT and we run out of page flags:
-        depends on !X86_NUMAQ
        # On 32-bit SPARSEMEM adds too big of SECTIONS_WIDTH:
        depends on X86_64 || !SPARSEMEM
        select ARCH_SUPPORTS_MEMORY_FAILURE
-config X86_VISWS
-        bool "SGI 320/540 (Visual Workstation)"
-        depends on X86_32 && PCI && X86_MPPARSE && PCI_GODIRECT
-        depends on X86_32_NON_STANDARD
-        ---help---
-          The SGI Visual Workstation series is an IA32-based workstation
-          based on SGI systems chips with some legacy PC hardware attached.
-          Say Y here to create a kernel to run on the SGI 320 or 540.
-          A kernel compiled for the Visual Workstation will run on general
-          PCs as well. See <file:Documentation/sgi-visws.txt> for details.
 config STA2X11
        bool "STA2X11 Companion Chip Support"
        depends on X86_32_NON_STANDARD && PCI
@@ -548,20 +518,6 @@ config STA2X11
          option is selected the kernel will still be able to boot on
          standard PC machines.
-config X86_SUMMIT
-        bool "Summit/EXA (IBM x440)"
-        depends on X86_32_NON_STANDARD
-        ---help---
-          This option is needed for IBM systems that use the Summit/EXA chipset.
-          In particular, it is needed for the x440.
-config X86_ES7000
-        bool "Unisys ES7000 IA32 series"
-        depends on X86_32_NON_STANDARD && X86_BIGSMP
-        ---help---
-          Support for Unisys ES7000 systems.  Say 'Y' here if this kernel is
-          supposed to run on an IA32-based Unisys ES7000 system.
 config X86_32_IRIS
        tristate "Eurobraille/Iris poweroff module"
        depends on X86_32
@@ -684,14 +640,6 @@ config MEMTEST
                memtest=4, mean do 4 test patterns.
          If you are unsure how to answer this question, answer N.
-config X86_SUMMIT_NUMA
-        def_bool y
-        depends on X86_32 && NUMA && X86_32_NON_STANDARD
-config X86_CYCLONE_TIMER
-        def_bool y
-        depends on X86_SUMMIT
 source "arch/x86/Kconfig.cpu"
 config HPET_TIMER
@@ -820,7 +768,7 @@ config NR_CPUS
        range 2 8192 if SMP && !MAXSMP && CPUMASK_OFFSTACK && X86_64
        default "1" if !SMP
        default "8192" if MAXSMP
-        default "32" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000)
+        default "32" if SMP && X86_BIGSMP
        default "8" if SMP
        ---help---
          This allows you to specify the maximum number of CPUs which this
@@ -884,10 +832,6 @@ config X86_IO_APIC
        def_bool y
        depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC || PCI_MSI
-config X86_VISWS_APIC
-        def_bool y
-        depends on X86_32 && X86_VISWS
 config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
        bool "Reroute for broken boot IRQs"
        depends on X86_IO_APIC
@@ -1105,13 +1049,11 @@ config X86_CPUID
 choice
        prompt "High Memory Support"
-        default HIGHMEM64G if X86_NUMAQ
        default HIGHMEM4G
        depends on X86_32
 config NOHIGHMEM
        bool "off"
-        depends on !X86_NUMAQ
        ---help---
          Linux can use up to 64 Gigabytes of physical memory on x86 systems.
          However, the address space of 32-bit x86 processors is only 4
@@ -1148,7 +1090,6 @@ config NOHIGHMEM
 config HIGHMEM4G
        bool "4GB"
-        depends on !X86_NUMAQ
        ---help---
          Select this if you have a 32-bit processor and between 1 and 4
          gigabytes of physical RAM.
@@ -1240,8 +1181,8 @@ config DIRECT_GBPAGES
 config NUMA
        bool "Numa Memory Allocation and Scheduler Support"
        depends on SMP
-        depends on X86_64 || (X86_32 && HIGHMEM64G && (X86_NUMAQ || X86_BIGSMP || X86_SUMMIT && ACPI))
+        depends on X86_64 || (X86_32 && HIGHMEM64G && X86_BIGSMP)
-        default y if (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP)
+        default y if X86_BIGSMP
        ---help---
          Enable NUMA (Non Uniform Memory Access) support.
@@ -1252,15 +1193,11 @@ config NUMA
          For 64-bit this is recommended if the system is Intel Core i7
          (or later), AMD Opteron, or EM64T NUMA.
-          For 32-bit this is only needed on (rare) 32-bit-only platforms
+          For 32-bit this is only needed if you boot a 32-bit
-          that support NUMA topologies, such as NUMAQ / Summit, or if you
+          kernel on a 64-bit NUMA platform.
-          boot a 32-bit kernel on a 64-bit NUMA platform.
          Otherwise, you should say N.
-comment "NUMA (Summit) requires SMP, 64GB highmem support, ACPI"
-        depends on X86_32 && X86_SUMMIT && (!HIGHMEM64G || !ACPI)
 config AMD_NUMA
        def_bool y
        prompt "Old style AMD Opteron NUMA detection"
@@ -1302,7 +1239,6 @@ config NODES_SHIFT
        range 1 10
        default "10" if MAXSMP
        default "6" if X86_64
-        default "4" if X86_NUMAQ
        default "3"
        depends on NEED_MULTIPLE_NODES
        ---help---
@@ -1850,17 +1786,29 @@ config DEBUG_HOTPLUG_CPU0
          If unsure, say N.
 config COMPAT_VDSO
-        def_bool y
+        def_bool n
-        prompt "Compat VDSO support"
+        prompt "Disable the 32-bit vDSO (needed for glibc 2.3.3)"
        depends on X86_32 || IA32_EMULATION
        ---help---
-          Map the 32-bit VDSO to the predictable old-style address too.
+          Certain buggy versions of glibc will crash if they are
+          presented with a 32-bit vDSO that is not mapped at the address
+          indicated in its segment table.
-          Say N here if you are running a sufficiently recent glibc
+          The bug was introduced by f866314b89d56845f55e6f365e18b31ec978ec3a
-          version (2.3.3 or later), to remove the high-mapped
+          and fixed by 3b3ddb4f7db98ec9e912ccdf54d35df4aa30e04a and
-          VDSO mapping and to exclusively use the randomized VDSO.
+          49ad572a70b8aeb91e57483a11dd1b77e31c4468.  Glibc 2.3.3 is
+          the only released version with the bug, but OpenSUSE 9
+          contains a buggy "glibc 2.3.2".
-          If unsure, say Y.
+          The symptom of the bug is that everything crashes on startup, saying:
+          dl_main: Assertion `(void *) ph->p_vaddr == _rtld_local._dl_sysinfo_dso' failed!
+          Saying Y here changes the default value of the vdso32 boot
+          option from 1 to 0, which turns off the 32-bit vDSO entirely.
+          This works around the glibc bug but hurts performance.
+          If unsure, say N: if you are compiling your own kernel, you
+          are unlikely to be using a buggy version of glibc.
 config CMDLINE_BOOL
        bool "Built-in kernel command line"
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index f3aaf231b4e5..6983314c8b37 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -359,7 +359,7 @@ config X86_P6_NOP
 config X86_TSC
        def_bool y
-        depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) && !X86_NUMAQ) || X86_64
+        depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
 config X86_CMPXCHG64
        def_bool y
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 3b9348a0c1a4..602f57e590b5 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -108,7 +108,7 @@ else
        # this works around some issues with generating unwind tables in older gccs
        # newer gccs do it by default
-        KBUILD_CFLAGS += -maccumulate-outgoing-args
+        KBUILD_CFLAGS += $(call cc-option,-maccumulate-outgoing-args)
 endif
 # Make sure compiler does not have buggy stack-protector support.
diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h
index 50f8c5e0f37e..bd49ec61255c 100644
--- a/arch/x86/boot/boot.h
+++ b/arch/x86/boot/boot.h
@@ -177,14 +177,6 @@ static inline void wrgs32(u32 v, addr_t addr)
 }
 /* Note: these only return true/false, not a signed return value! */
-static inline int memcmp(const void *s1, const void *s2, size_t len)
-{
-        u8 diff;
-        asm("repe; cmpsb; setnz %0"
-            : "=qm" (diff), "+D" (s1), "+S" (s2), "+c" (len));
-        return diff;
-}
 static inline int memcmp_fs(const void *s1, addr_t s2, size_t len)
 {
        u8 diff;
@@ -228,11 +220,6 @@ void copy_to_fs(addr_t dst, void *src, size_t len);
 void *copy_from_fs(void *dst, addr_t src, size_t len);
 void copy_to_gs(addr_t dst, void *src, size_t len);
 void *copy_from_gs(void *dst, addr_t src, size_t len);
-void *memcpy(void *dst, void *src, size_t len);
-void *memset(void *dst, int c, size_t len);
-#define memcpy(d,s,l) __builtin_memcpy(d,s,l)
-#define memset(d,c,l) __builtin_memset(d,c,l)
 /* a20.c */
 int enable_a20(void);
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 1e6146137f8e..4703a6c4b8e3 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -112,7 +112,7 @@ __file_size64(void *__fh, efi_char16_t *filename_16,
        efi_file_info_t *info;
        efi_status_t status;
        efi_guid_t info_guid = EFI_FILE_INFO_ID;
-        u32 info_sz;
+        u64 info_sz;
        status = efi_early->call((unsigned long)fh->open, fh, &h, filename_16,
                                 EFI_FILE_MODE_READ, (u64)0);
@@ -167,31 +167,31 @@ efi_file_size(efi_system_table_t *sys_table, void *__fh,
 }
 static inline efi_status_t
-efi_file_read(void *__fh, void *handle, unsigned long *size, void *addr)
+efi_file_read(void *handle, unsigned long *size, void *addr)
 {
        unsigned long func;
        if (efi_early->is64) {
-                efi_file_handle_64_t *fh = __fh;
+                efi_file_handle_64_t *fh = handle;
                func = (unsigned long)fh->read;
                return efi_early->call(func, handle, size, addr);
        } else {
-                efi_file_handle_32_t *fh = __fh;
+                efi_file_handle_32_t *fh = handle;
                func = (unsigned long)fh->read;
                return efi_early->call(func, handle, size, addr);
        }
 }
-static inline efi_status_t efi_file_close(void *__fh, void *handle)
+static inline efi_status_t efi_file_close(void *handle)
 {
        if (efi_early->is64) {
-                efi_file_handle_64_t *fh = __fh;
+                efi_file_handle_64_t *fh = handle;
                return efi_early->call((unsigned long)fh->close, handle);
        } else {
-                efi_file_handle_32_t *fh = __fh;
+                efi_file_handle_32_t *fh = handle;
                return efi_early->call((unsigned long)fh->close, handle);
        }
@@ -1016,6 +1016,9 @@ void setup_graphics(struct boot_params *boot_params)
 * Because the x86 boot code expects to be passed a boot_params we
 * need to create one ourselves (usually the bootloader would create
 * one for us).
+ *
+ * The caller is responsible for filling out ->code32_start in the
+ * returned boot_params.
 */
 struct boot_params *make_boot_params(struct efi_config *c)
 {
@@ -1081,8 +1084,6 @@ struct boot_params *make_boot_params(struct efi_config *c)
        hdr->vid_mode = 0xffff;
        hdr->boot_flag = 0xAA55;
-        hdr->code32_start = (__u64)(unsigned long)image->image_base;
        hdr->type_of_loader = 0x21;
        /* Convert unicode cmdline to ascii */
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index de9d4200d305..cbed1407a5cd 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -59,6 +59,7 @@ ENTRY(efi_pe_entry)
        call    make_boot_params
        cmpl    $0, %eax
        je      fail
+        movl    %esi, BP_code32_start(%eax)
        popl    %ecx
        pushl   %eax
        pushl   %ecx
@@ -90,12 +91,7 @@ fail:
        hlt
        jmp     fail
 2:
-        call    3f
+        movl    BP_code32_start(%esi), %eax
-3:
-        popl    %eax
-        subl    $3b, %eax
-        subl    BP_pref_address(%esi), %eax
-        add     BP_code32_start(%esi), %eax
        leal    preferred_addr(%eax), %eax
        jmp     *%eax
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 57e58a5fa210..0d558ee899ae 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -261,6 +261,8 @@ ENTRY(efi_pe_entry)
        cmpq    $0,%rax
        je      fail
        mov     %rax, %rsi
+        leaq    startup_32(%rip), %rax
+        movl    %eax, BP_code32_start(%rsi)
        jmp     2f              /* Skip the relocation */
 handover_entry:
@@ -284,12 +286,7 @@ fail:
        hlt
        jmp     fail
 2:
-        call    3f
+        movl    BP_code32_start(%esi), %eax
-3:
-        popq    %rax
-        subq    $3b, %rax
-        subq    BP_pref_address(%rsi), %rax
-        add     BP_code32_start(%esi), %eax
        leaq    preferred_addr(%rax), %rax
        jmp     *%rax
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 196eaf373a06..17684615374b 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -10,6 +10,7 @@
 */
 #include "misc.h"
+#include "../string.h"
 /* WARNING!!
 * This code is compiled with -fPIC and it is relocated dynamically
@@ -97,8 +98,14 @@
 */
 #define STATIC          static
-#undef memset
 #undef memcpy
+/*
+ * Use a normal definition of memset() from string.c. There are already
+ * included header files which expect a definition of memset() and by
+ * the time we define memset macro, it is too late.
+ */
+#undef memset
 #define memzero(s, n)   memset((s), 0, (n))
@@ -109,9 +116,6 @@ static void error(char *m);
 */
 struct boot_params *real_mode;          /* Pointer to real-mode data */
-void *memset(void *s, int c, size_t n);
-void *memcpy(void *dest, const void *src, size_t n);
 memptr free_mem_ptr;
 memptr free_mem_end_ptr;
@@ -216,45 +220,6 @@ void __putstr(const char *s)
        outb(0xff & (pos >> 1), vidport+1);
 }
-void *memset(void *s, int c, size_t n)
-{
-        int i;
-        char *ss = s;
-        for (i = 0; i < n; i++)
-                ss[i] = c;
-        return s;
-}
-#ifdef CONFIG_X86_32
-void *memcpy(void *dest, const void *src, size_t n)
-{
-        int d0, d1, d2;
-        asm volatile(
-                "rep ; movsl\n\t"
-                "movl %4,%%ecx\n\t"
-                "rep ; movsb\n\t"
-                : "=&c" (d0), "=&D" (d1), "=&S" (d2)
-                : "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src)
-                : "memory");
-        return dest;
-}
-#else
-void *memcpy(void *dest, const void *src, size_t n)
-{
-        long d0, d1, d2;
-        asm volatile(
-                "rep ; movsq\n\t"
-                "movq %4,%%rcx\n\t"
-                "rep ; movsb\n\t"
-                : "=&c" (d0), "=&D" (d1), "=&S" (d2)
-                : "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src)
-                : "memory");
-        return dest;
-}
-#endif
 static void error(char *x)
 {
        error_putstr("\n\n");
diff --git a/arch/x86/boot/compressed/string.c b/arch/x86/boot/compressed/string.c
index ffb9c5c9d748..f3c57e341402 100644
--- a/arch/x86/boot/compressed/string.c
+++ b/arch/x86/boot/compressed/string.c
@@ -1,11 +1,45 @@
 #include "misc.h"
+#include "../string.c"
+/* misc.h might pull in string_32.h which has a macro for memcpy. undef that */
+#undef memcpy
-int memcmp(const void *s1, const void *s2, size_t len)
+#ifdef CONFIG_X86_32
+void *memcpy(void *dest, const void *src, size_t n)
 {
-        u8 diff;
+        int d0, d1, d2;
-        asm("repe; cmpsb; setnz %0"
+        asm volatile(
-            : "=qm" (diff), "+D" (s1), "+S" (s2), "+c" (len));
+                "rep ; movsl\n\t"
-        return diff;
+                "movl %4,%%ecx\n\t"
+                "rep ; movsb\n\t"
+                : "=&c" (d0), "=&D" (d1), "=&S" (d2)
+                : "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src)
+                : "memory");
+        return dest;
 }
+#else
+void *memcpy(void *dest, const void *src, size_t n)
+{
+        long d0, d1, d2;
+        asm volatile(
+                "rep ; movsq\n\t"
+                "movq %4,%%rcx\n\t"
+                "rep ; movsb\n\t"
+                : "=&c" (d0), "=&D" (d1), "=&S" (d2)
+                : "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src)
+                : "memory");
-#include "../string.c"
+        return dest;
+}
+#endif
+void *memset(void *s, int c, size_t n)
+{
+        int i;
+        char *ss = s;
+        for (i = 0; i < n; i++)
+                ss[i] = c;
+        return s;
+}
diff --git a/arch/x86/boot/cpucheck.c b/arch/x86/boot/cpucheck.c
index f0d0b20fe149..1fd7d575092e 100644
--- a/arch/x86/boot/cpucheck.c
+++ b/arch/x86/boot/cpucheck.c
@@ -27,6 +27,7 @@
 #include <asm/processor-flags.h>
 #include <asm/required-features.h>
 #include <asm/msr-index.h>
+#include "string.h"
 static u32 err_flags[NCAPINTS];
diff --git a/arch/x86/boot/edd.c b/arch/x86/boot/edd.c
index c501a5b466f8..223e42527077 100644
--- a/arch/x86/boot/edd.c
+++ b/arch/x86/boot/edd.c
@@ -15,6 +15,7 @@
 #include "boot.h"
 #include <linux/edd.h>
+#include "string.h"
 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
diff --git a/arch/x86/boot/main.c b/arch/x86/boot/main.c
index cf6083d444f4..fd6c9f236996 100644
--- a/arch/x86/boot/main.c
+++ b/arch/x86/boot/main.c
@@ -14,6 +14,7 @@
 */
 #include "boot.h"
+#include "string.h"
 struct boot_params boot_params __attribute__((aligned(16)));
diff --git a/arch/x86/boot/regs.c b/arch/x86/boot/regs.c
index 958019b1cfa5..c0fb356a3092 100644
--- a/arch/x86/boot/regs.c
+++ b/arch/x86/boot/regs.c
@@ -17,6 +17,7 @@
 */
 #include "boot.h"
+#include "string.h"
 void initregs(struct biosregs *reg)
 {
diff --git a/arch/x86/boot/string.c b/arch/x86/boot/string.c
index 574dedfe2890..5339040ef86e 100644
--- a/arch/x86/boot/string.c
+++ b/arch/x86/boot/string.c
@@ -14,6 +14,20 @@
 #include "boot.h"
+/*
+ * This file gets included in compressed/string.c which might pull in
+ * string_32.h and which in turn maps memcmp to __builtin_memcmp(). Undo
+ * that first.
+ */
+#undef memcmp
+int memcmp(const void *s1, const void *s2, size_t len)
+{
+        u8 diff;
+        asm("repe; cmpsb; setnz %0"
+            : "=qm" (diff), "+D" (s1), "+S" (s2), "+c" (len));
+        return diff;
+}
 int strcmp(const char *str1, const char *str2)
 {
        const unsigned char *s1 = (const unsigned char *)str1;
diff --git a/arch/x86/boot/string.h b/arch/x86/boot/string.h
new file mode 100644
index 000000000000..725e820602b1
--- /dev/null
+++ b/arch/x86/boot/string.h
@@ -0,0 +1,21 @@
+#ifndef BOOT_STRING_H
+#define BOOT_STRING_H
+/* Undef any of these macros coming from string_32.h. */
+#undef memcpy
+#undef memset
+#undef memcmp
+void *memcpy(void *dst, const void *src, size_t len);
+void *memset(void *dst, int c, size_t len);
+int memcmp(const void *s1, const void *s2, size_t len);
+/*
+ * Access builtin version by default. If one needs to use optimized version,
+ * do "undef memcpy" in .c file and link against right string.c
+ */
+#define memcpy(d,s,l) __builtin_memcpy(d,s,l)
+#define memset(d,c,l) __builtin_memset(d,c,l)
+#define memcmp  __builtin_memcmp
+#endif /* BOOT_STRING_H */
diff --git a/arch/x86/boot/video-vesa.c b/arch/x86/boot/video-vesa.c
index 11e8c6eb80a1..ba3e100654db 100644
--- a/arch/x86/boot/video-vesa.c
+++ b/arch/x86/boot/video-vesa.c
@@ -16,6 +16,7 @@
 #include "boot.h"
 #include "video.h"
 #include "vesa.h"
+#include "string.h"
 /* VESA information */
 static struct vesa_general_info vginfo;
diff --git a/arch/x86/configs/i386_defconfig b/arch/x86/configs/i386_defconfig
index a7fef2621cc9..619e7f7426c6 100644
--- a/arch/x86/configs/i386_defconfig
+++ b/arch/x86/configs/i386_defconfig
@@ -60,7 +60,6 @@ CONFIG_CRASH_DUMP=y
 CONFIG_HIBERNATION=y
 CONFIG_PM_DEBUG=y
 CONFIG_PM_TRACE_RTC=y
-CONFIG_ACPI_PROCFS=y
 CONFIG_ACPI_DOCK=y
 CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
diff --git a/arch/x86/configs/x86_64_defconfig b/arch/x86/configs/x86_64_defconfig
index c1119d4c1281..6181c69b786b 100644
--- a/arch/x86/configs/x86_64_defconfig
+++ b/arch/x86/configs/x86_64_defconfig
@@ -58,7 +58,6 @@ CONFIG_CRASH_DUMP=y
 CONFIG_HIBERNATION=y
 CONFIG_PM_DEBUG=y
 CONFIG_PM_TRACE_RTC=y
-CONFIG_ACPI_PROCFS=y
 CONFIG_ACPI_DOCK=y
 CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index 6ba54d640383..61d6e281898b 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -79,6 +79,9 @@ aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o fpu.o
 aesni-intel-$(CONFIG_64BIT) += aesni-intel_avx-x86_64.o
 ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o
 sha1-ssse3-y := sha1_ssse3_asm.o sha1_ssse3_glue.o
+ifeq ($(avx2_supported),yes)
+sha1-ssse3-y += sha1_avx2_x86_64_asm.o
+endif
 crc32c-intel-y := crc32c-intel_glue.o
 crc32c-intel-$(CONFIG_64BIT) += crc32c-pcl-intel-asm_64.o
 crc32-pclmul-y := crc32-pclmul_asm.o crc32-pclmul_glue.o
diff --git a/arch/x86/crypto/blowfish_glue.c b/arch/x86/crypto/blowfish_glue.c
index 50ec333b70e6..8af519ed73d1 100644
--- a/arch/x86/crypto/blowfish_glue.c
+++ b/arch/x86/crypto/blowfish_glue.c
@@ -223,9 +223,6 @@ static unsigned int __cbc_decrypt(struct blkcipher_desc *desc,
                        src -= 1;
                        dst -= 1;
                } while (nbytes >= bsize * 4);
-                if (nbytes < bsize)
-                        goto done;
        }
        /* Handle leftovers */
diff --git a/arch/x86/crypto/cast5_avx_glue.c b/arch/x86/crypto/cast5_avx_glue.c
index e6a3700489b9..e57e20ab5e0b 100644
--- a/arch/x86/crypto/cast5_avx_glue.c
+++ b/arch/x86/crypto/cast5_avx_glue.c
@@ -203,9 +203,6 @@ static unsigned int __cbc_decrypt(struct blkcipher_desc *desc,
                        src -= 1;
                        dst -= 1;
                } while (nbytes >= bsize * CAST5_PARALLEL_BLOCKS);
-                if (nbytes < bsize)
-                        goto done;
        }
        /* Handle leftovers */
diff --git a/arch/x86/crypto/ghash-clmulni-intel_asm.S b/arch/x86/crypto/ghash-clmulni-intel_asm.S
index 586f41aac361..185fad49d86f 100644
--- a/arch/x86/crypto/ghash-clmulni-intel_asm.S
+++ b/arch/x86/crypto/ghash-clmulni-intel_asm.S
@@ -24,10 +24,6 @@
 .align 16
 .Lbswap_mask:
        .octa 0x000102030405060708090a0b0c0d0e0f
-.Lpoly:
-        .octa 0xc2000000000000000000000000000001
-.Ltwo_one:
-        .octa 0x00000001000000000000000000000001
 #define DATA    %xmm0
 #define SHASH   %xmm1
@@ -134,28 +130,3 @@ ENTRY(clmul_ghash_update)
 .Lupdate_just_ret:
        ret
 ENDPROC(clmul_ghash_update)
-/*
- * void clmul_ghash_setkey(be128 *shash, const u8 *key);
- *
- * Calculate hash_key << 1 mod poly
- */
-ENTRY(clmul_ghash_setkey)
-        movaps .Lbswap_mask, BSWAP
-        movups (%rsi), %xmm0
-        PSHUFB_XMM BSWAP %xmm0
-        movaps %xmm0, %xmm1
-        psllq $1, %xmm0
-        psrlq $63, %xmm1
-        movaps %xmm1, %xmm2
-        pslldq $8, %xmm1
-        psrldq $8, %xmm2
-        por %xmm1, %xmm0
-        # reduction
-        pshufd $0b00100100, %xmm2, %xmm1
-        pcmpeqd .Ltwo_one, %xmm1
-        pand .Lpoly, %xmm1
-        pxor %xmm1, %xmm0
-        movups %xmm0, (%rdi)
-        ret
-ENDPROC(clmul_ghash_setkey)
diff --git a/arch/x86/crypto/ghash-clmulni-intel_glue.c b/arch/x86/crypto/ghash-clmulni-intel_glue.c
index 6759dd1135be..d785cf2c529c 100644
--- a/arch/x86/crypto/ghash-clmulni-intel_glue.c
+++ b/arch/x86/crypto/ghash-clmulni-intel_glue.c
@@ -30,8 +30,6 @@ void clmul_ghash_mul(char *dst, const be128 *shash);
 void clmul_ghash_update(char *dst, const char *src, unsigned int srclen,
                        const be128 *shash);
-void clmul_ghash_setkey(be128 *shash, const u8 *key);
 struct ghash_async_ctx {
        struct cryptd_ahash *cryptd_tfm;
 };
@@ -58,13 +56,23 @@ static int ghash_setkey(struct crypto_shash *tfm,
                        const u8 *key, unsigned int keylen)
 {
        struct ghash_ctx *ctx = crypto_shash_ctx(tfm);
+        be128 *x = (be128 *)key;
+        u64 a, b;
        if (keylen != GHASH_BLOCK_SIZE) {
                crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
                return -EINVAL;
        }
-        clmul_ghash_setkey(&ctx->shash, key);
+        /* perform multiplication by 'x' in GF(2^128) */
+        a = be64_to_cpu(x->a);
+        b = be64_to_cpu(x->b);
+        ctx->shash.a = (__be64)((b << 1) | (a >> 63));
+        ctx->shash.b = (__be64)((a << 1) | (b >> 63));
+        if (a >> 63)
+                ctx->shash.b ^= cpu_to_be64(0xc2);
        return 0;
 }
diff --git a/arch/x86/crypto/sha1_avx2_x86_64_asm.S b/arch/x86/crypto/sha1_avx2_x86_64_asm.S
new file mode 100644
index 000000000000..1cd792db15ef
--- /dev/null
+++ b/arch/x86/crypto/sha1_avx2_x86_64_asm.S
@@ -0,0 +1,708 @@
+/*
+ *      Implement fast SHA-1 with AVX2 instructions. (x86_64)
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2014 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * Contact Information:
+ * Ilya Albrekht <ilya.albrekht@intel.com>
+ * Maxim Locktyukhin <maxim.locktyukhin@intel.com>
+ * Ronen Zohar <ronen.zohar@intel.com>
+ * Chandramouli Narayanan <mouli@linux.intel.com>
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2014 Intel Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * SHA-1 implementation with Intel(R) AVX2 instruction set extensions.
+ *
+ *This implementation is based on the previous SSSE3 release:
+ *Visit http://software.intel.com/en-us/articles/
+ *and refer to improving-the-performance-of-the-secure-hash-algorithm-1/
+ *
+ *Updates 20-byte SHA-1 record in 'hash' for even number of
+ *'num_blocks' consecutive 64-byte blocks
+ *
+ *extern "C" void sha1_transform_avx2(
+ *      int *hash, const char* input, size_t num_blocks );
+ */
+#include <linux/linkage.h>
+#define CTX     %rdi    /* arg1 */
+#define BUF     %rsi    /* arg2 */
+#define CNT     %rdx    /* arg3 */
+#define REG_A   %ecx
+#define REG_B   %esi
+#define REG_C   %edi
+#define REG_D   %eax
+#define REG_E   %edx
+#define REG_TB  %ebx
+#define REG_TA  %r12d
+#define REG_RA  %rcx
+#define REG_RB  %rsi
+#define REG_RC  %rdi
+#define REG_RD  %rax
+#define REG_RE  %rdx
+#define REG_RTA %r12
+#define REG_RTB %rbx
+#define REG_T1  %ebp
+#define xmm_mov vmovups
+#define avx2_zeroupper  vzeroupper
+#define RND_F1  1
+#define RND_F2  2
+#define RND_F3  3
+.macro REGALLOC
+        .set A, REG_A
+        .set B, REG_B
+        .set C, REG_C
+        .set D, REG_D
+        .set E, REG_E
+        .set TB, REG_TB
+        .set TA, REG_TA
+        .set RA, REG_RA
+        .set RB, REG_RB
+        .set RC, REG_RC
+        .set RD, REG_RD
+        .set RE, REG_RE
+        .set RTA, REG_RTA
+        .set RTB, REG_RTB
+        .set T1, REG_T1
+.endm
+#define K_BASE          %r8
+#define HASH_PTR        %r9
+#define BUFFER_PTR      %r10
+#define BUFFER_PTR2     %r13
+#define BUFFER_END      %r11
+#define PRECALC_BUF     %r14
+#define WK_BUF          %r15
+#define W_TMP           %xmm0
+#define WY_TMP          %ymm0
+#define WY_TMP2         %ymm9
+# AVX2 variables
+#define WY0             %ymm3
+#define WY4             %ymm5
+#define WY08            %ymm7
+#define WY12            %ymm8
+#define WY16            %ymm12
+#define WY20            %ymm13
+#define WY24            %ymm14
+#define WY28            %ymm15
+#define YMM_SHUFB_BSWAP %ymm10
+/*
+ * Keep 2 iterations precalculated at a time:
+ *    - 80 DWORDs per iteration * 2
+ */
+#define W_SIZE          (80*2*2 +16)
+#define WK(t)   ((((t) % 80) / 4)*32 + ( (t) % 4)*4 + ((t)/80)*16 )(WK_BUF)
+#define PRECALC_WK(t)   ((t)*2*2)(PRECALC_BUF)
+.macro UPDATE_HASH  hash, val
+        add     \hash, \val
+        mov     \val, \hash
+.endm
+.macro PRECALC_RESET_WY
+        .set WY_00, WY0
+        .set WY_04, WY4
+        .set WY_08, WY08
+        .set WY_12, WY12
+        .set WY_16, WY16
+        .set WY_20, WY20
+        .set WY_24, WY24
+        .set WY_28, WY28
+        .set WY_32, WY_00
+.endm
+.macro PRECALC_ROTATE_WY
+        /* Rotate macros */
+        .set WY_32, WY_28
+        .set WY_28, WY_24
+        .set WY_24, WY_20
+        .set WY_20, WY_16
+        .set WY_16, WY_12
+        .set WY_12, WY_08
+        .set WY_08, WY_04
+        .set WY_04, WY_00
+        .set WY_00, WY_32
+        /* Define register aliases */
+        .set WY, WY_00
+        .set WY_minus_04, WY_04
+        .set WY_minus_08, WY_08
+        .set WY_minus_12, WY_12
+        .set WY_minus_16, WY_16
+        .set WY_minus_20, WY_20
+        .set WY_minus_24, WY_24
+        .set WY_minus_28, WY_28
+        .set WY_minus_32, WY
+.endm
+.macro PRECALC_00_15
+        .if (i == 0) # Initialize and rotate registers
+                PRECALC_RESET_WY
+                PRECALC_ROTATE_WY
+        .endif
+        /* message scheduling pre-compute for rounds 0-15 */
+        .if   ((i & 7) == 0)
+                /*
+                 * blended AVX2 and ALU instruction scheduling
+                 * 1 vector iteration per 8 rounds
+                 */
+                vmovdqu ((i * 2) + PRECALC_OFFSET)(BUFFER_PTR), W_TMP
+        .elseif ((i & 7) == 1)
+                vinsertf128 $1, (((i-1) * 2)+PRECALC_OFFSET)(BUFFER_PTR2),\
+                         WY_TMP, WY_TMP
+        .elseif ((i & 7) == 2)
+                vpshufb YMM_SHUFB_BSWAP, WY_TMP, WY
+        .elseif ((i & 7) == 4)
+                vpaddd  K_XMM(K_BASE), WY, WY_TMP
+        .elseif ((i & 7) == 7)
+                vmovdqu  WY_TMP, PRECALC_WK(i&~7)
+                PRECALC_ROTATE_WY
+        .endif
+.endm
+.macro PRECALC_16_31
+        /*
+         * message scheduling pre-compute for rounds 16-31
+         * calculating last 32 w[i] values in 8 XMM registers
+         * pre-calculate K+w[i] values and store to mem
+         * for later load by ALU add instruction
+         *
+         * "brute force" vectorization for rounds 16-31 only
+         * due to w[i]->w[i-3] dependency
+         */
+        .if   ((i & 7) == 0)
+                /*
+                 * blended AVX2 and ALU instruction scheduling
+                 * 1 vector iteration per 8 rounds
+                 */
+                /* w[i-14] */
+                vpalignr        $8, WY_minus_16, WY_minus_12, WY
+                vpsrldq $4, WY_minus_04, WY_TMP               /* w[i-3] */
+        .elseif ((i & 7) == 1)
+                vpxor   WY_minus_08, WY, WY
+                vpxor   WY_minus_16, WY_TMP, WY_TMP
+        .elseif ((i & 7) == 2)
+                vpxor   WY_TMP, WY, WY
+                vpslldq $12, WY, WY_TMP2
+        .elseif ((i & 7) == 3)
+                vpslld  $1, WY, WY_TMP
+                vpsrld  $31, WY, WY
+        .elseif ((i & 7) == 4)
+                vpor    WY, WY_TMP, WY_TMP
+                vpslld  $2, WY_TMP2, WY
+        .elseif ((i & 7) == 5)
+                vpsrld  $30, WY_TMP2, WY_TMP2
+                vpxor   WY, WY_TMP, WY_TMP
+        .elseif ((i & 7) == 7)
+                vpxor   WY_TMP2, WY_TMP, WY
+                vpaddd  K_XMM(K_BASE), WY, WY_TMP
+                vmovdqu WY_TMP, PRECALC_WK(i&~7)
+                PRECALC_ROTATE_WY
+        .endif
+.endm
+.macro PRECALC_32_79
+        /*
+         * in SHA-1 specification:
+         * w[i] = (w[i-3] ^ w[i-8]  ^ w[i-14] ^ w[i-16]) rol 1
+         * instead we do equal:
+         * w[i] = (w[i-6] ^ w[i-16] ^ w[i-28] ^ w[i-32]) rol 2
+         * allows more efficient vectorization
+         * since w[i]=>w[i-3] dependency is broken
+         */
+        .if   ((i & 7) == 0)
+        /*
+         * blended AVX2 and ALU instruction scheduling
+         * 1 vector iteration per 8 rounds
+         */
+                vpalignr        $8, WY_minus_08, WY_minus_04, WY_TMP
+        .elseif ((i & 7) == 1)
+                /* W is W_minus_32 before xor */
+                vpxor   WY_minus_28, WY, WY
+        .elseif ((i & 7) == 2)
+                vpxor   WY_minus_16, WY_TMP, WY_TMP
+        .elseif ((i & 7) == 3)
+                vpxor   WY_TMP, WY, WY
+        .elseif ((i & 7) == 4)
+                vpslld  $2, WY, WY_TMP
+        .elseif ((i & 7) == 5)
+                vpsrld  $30, WY, WY
+                vpor    WY, WY_TMP, WY
+        .elseif ((i & 7) == 7)
+                vpaddd  K_XMM(K_BASE), WY, WY_TMP
+                vmovdqu WY_TMP, PRECALC_WK(i&~7)
+                PRECALC_ROTATE_WY
+        .endif
+.endm
+.macro PRECALC r, s
+        .set i, \r
+        .if (i < 40)
+                .set K_XMM, 32*0
+        .elseif (i < 80)
+                .set K_XMM, 32*1
+        .elseif (i < 120)
+                .set K_XMM, 32*2
+        .else
+                .set K_XMM, 32*3
+        .endif
+        .if (i<32)
+                PRECALC_00_15   \s
+        .elseif (i<64)
+                PRECALC_16_31   \s
+        .elseif (i < 160)
+                PRECALC_32_79   \s
+        .endif
+.endm
+.macro ROTATE_STATE
+        .set T_REG, E
+        .set E, D
+        .set D, C
+        .set C, B
+        .set B, TB
+        .set TB, A
+        .set A, T_REG
+        .set T_REG, RE
+        .set RE, RD
+        .set RD, RC
+        .set RC, RB
+        .set RB, RTB
+        .set RTB, RA
+        .set RA, T_REG
+.endm
+/* Macro relies on saved ROUND_Fx */
+.macro RND_FUN f, r
+        .if (\f == RND_F1)
+                ROUND_F1        \r
+        .elseif (\f == RND_F2)
+                ROUND_F2        \r
+        .elseif (\f == RND_F3)
+                ROUND_F3        \r
+        .endif
+.endm
+.macro RR r
+        .set round_id, (\r % 80)
+        .if (round_id == 0)        /* Precalculate F for first round */
+                .set ROUND_FUNC, RND_F1
+                mov     B, TB
+                rorx    $(32-30), B, B    /* b>>>2 */
+                andn    D, TB, T1
+                and     C, TB
+                xor     T1, TB
+        .endif
+        RND_FUN ROUND_FUNC, \r
+        ROTATE_STATE
+        .if   (round_id == 18)
+                .set ROUND_FUNC, RND_F2
+        .elseif (round_id == 38)
+                .set ROUND_FUNC, RND_F3
+        .elseif (round_id == 58)
+                .set ROUND_FUNC, RND_F2
+        .endif
+        .set round_id, ( (\r+1) % 80)
+        RND_FUN ROUND_FUNC, (\r+1)
+        ROTATE_STATE
+.endm
+.macro ROUND_F1 r
+        add     WK(\r), E
+        andn    C, A, T1                        /* ~b&d */
+        lea     (RE,RTB), E             /* Add F from the previous round */
+        rorx    $(32-5), A, TA          /* T2 = A >>> 5 */
+        rorx    $(32-30),A, TB          /* b>>>2 for next round */
+        PRECALC (\r)                    /* msg scheduling for next 2 blocks */
+        /*
+         * Calculate F for the next round
+         * (b & c) ^ andn[b, d]
+         */
+        and     B, A                    /* b&c */
+        xor     T1, A                   /* F1 = (b&c) ^ (~b&d) */
+        lea     (RE,RTA), E             /* E += A >>> 5 */
+.endm
+.macro ROUND_F2 r
+        add     WK(\r), E
+        lea     (RE,RTB), E             /* Add F from the previous round */
+        /* Calculate F for the next round */
+        rorx    $(32-5), A, TA          /* T2 = A >>> 5 */
+        .if ((round_id) < 79)
+                rorx    $(32-30), A, TB /* b>>>2 for next round */
+        .endif
+        PRECALC (\r)                    /* msg scheduling for next 2 blocks */
+        .if ((round_id) < 79)
+                xor     B, A
+        .endif
+        add     TA, E                   /* E += A >>> 5 */
+        .if ((round_id) < 79)
+                xor     C, A
+        .endif
+.endm
+.macro ROUND_F3 r
+        add     WK(\r), E
+        PRECALC (\r)                    /* msg scheduling for next 2 blocks */
+        lea     (RE,RTB), E             /* Add F from the previous round */
+        mov     B, T1
+        or      A, T1
+        rorx    $(32-5), A, TA          /* T2 = A >>> 5 */
+        rorx    $(32-30), A, TB         /* b>>>2 for next round */
+        /* Calculate F for the next round
+         * (b and c) or (d and (b or c))
+         */
+        and     C, T1
+        and     B, A
+        or      T1, A
+        add     TA, E                   /* E += A >>> 5 */
+.endm
+/*
+ * macro implements 80 rounds of SHA-1, for multiple blocks with s/w pipelining
+ */
+.macro SHA1_PIPELINED_MAIN_BODY
+        REGALLOC
+        mov     (HASH_PTR), A
+        mov     4(HASH_PTR), B
+        mov     8(HASH_PTR), C
+        mov     12(HASH_PTR), D
+        mov     16(HASH_PTR), E
+        mov     %rsp, PRECALC_BUF
+        lea     (2*4*80+32)(%rsp), WK_BUF
+        # Precalc WK for first 2 blocks
+        PRECALC_OFFSET = 0
+        .set i, 0
+        .rept    160
+                PRECALC i
+                .set i, i + 1
+        .endr
+        PRECALC_OFFSET = 128
+        xchg    WK_BUF, PRECALC_BUF
+        .align 32
+_loop:
+        /*
+         * code loops through more than one block
+         * we use K_BASE value as a signal of a last block,
+         * it is set below by: cmovae BUFFER_PTR, K_BASE
+         */
+        cmp     K_BASE, BUFFER_PTR
+        jne     _begin
+        .align 32
+        jmp     _end
+        .align 32
+_begin:
+        /*
+         * Do first block
+         * rounds: 0,2,4,6,8
+         */
+        .set j, 0
+        .rept 5
+                RR      j
+                .set j, j+2
+        .endr
+        jmp _loop0
+_loop0:
+        /*
+         * rounds:
+         * 10,12,14,16,18
+         * 20,22,24,26,28
+         * 30,32,34,36,38
+         * 40,42,44,46,48
+         * 50,52,54,56,58
+         */
+        .rept 25
+                RR      j
+                .set j, j+2
+        .endr
+        add     $(2*64), BUFFER_PTR       /* move to next odd-64-byte block */
+        cmp     BUFFER_END, BUFFER_PTR    /* is current block the last one? */
+        cmovae  K_BASE, BUFFER_PTR      /* signal the last iteration smartly */
+        /*
+         * rounds
+         * 60,62,64,66,68
+         * 70,72,74,76,78
+         */
+        .rept 10
+                RR      j
+                .set j, j+2
+        .endr
+        UPDATE_HASH     (HASH_PTR), A
+        UPDATE_HASH     4(HASH_PTR), TB
+        UPDATE_HASH     8(HASH_PTR), C
+        UPDATE_HASH     12(HASH_PTR), D
+        UPDATE_HASH     16(HASH_PTR), E
+        cmp     K_BASE, BUFFER_PTR      /* is current block the last one? */
+        je      _loop
+        mov     TB, B
+        /* Process second block */
+        /*
+         * rounds
+         *  0+80, 2+80, 4+80, 6+80, 8+80
+         * 10+80,12+80,14+80,16+80,18+80
+         */
+        .set j, 0
+        .rept 10
+                RR      j+80
+                .set j, j+2
+        .endr
+        jmp     _loop1
+_loop1:
+        /*
+         * rounds
+         * 20+80,22+80,24+80,26+80,28+80
+         * 30+80,32+80,34+80,36+80,38+80
+         */
+        .rept 10
+                RR      j+80
+                .set j, j+2
+        .endr
+        jmp     _loop2
+_loop2:
+        /*
+         * rounds
+         * 40+80,42+80,44+80,46+80,48+80
+         * 50+80,52+80,54+80,56+80,58+80
+         */
+        .rept 10
+                RR      j+80
+                .set j, j+2
+        .endr
+        add     $(2*64), BUFFER_PTR2      /* move to next even-64-byte block */
+        cmp     BUFFER_END, BUFFER_PTR2   /* is current block the last one */
+        cmovae  K_BASE, BUFFER_PTR       /* signal the last iteration smartly */
+        jmp     _loop3
+_loop3:
+        /*
+         * rounds
+         * 60+80,62+80,64+80,66+80,68+80
+         * 70+80,72+80,74+80,76+80,78+80
+         */
+        .rept 10
+                RR      j+80
+                .set j, j+2
+        .endr
+        UPDATE_HASH     (HASH_PTR), A
+        UPDATE_HASH     4(HASH_PTR), TB
+        UPDATE_HASH     8(HASH_PTR), C
+        UPDATE_HASH     12(HASH_PTR), D
+        UPDATE_HASH     16(HASH_PTR), E
+        /* Reset state for AVX2 reg permutation */
+        mov     A, TA
+        mov     TB, A
+        mov     C, TB
+        mov     E, C
+        mov     D, B
+        mov     TA, D
+        REGALLOC
+        xchg    WK_BUF, PRECALC_BUF
+        jmp     _loop
+        .align 32
+        _end:
+.endm
+/*
+ * macro implements SHA-1 function's body for several 64-byte blocks
+ * param: function's name
+ */
+.macro SHA1_VECTOR_ASM  name
+        ENTRY(\name)
+        push    %rbx
+        push    %rbp
+        push    %r12
+        push    %r13
+        push    %r14
+        push    %r15
+        RESERVE_STACK  = (W_SIZE*4 + 8+24)
+        /* Align stack */
+        mov     %rsp, %rbx
+        and     $~(0x20-1), %rsp
+        push    %rbx
+        sub     $RESERVE_STACK, %rsp
+        avx2_zeroupper
+        lea     K_XMM_AR(%rip), K_BASE
+        mov     CTX, HASH_PTR
+        mov     BUF, BUFFER_PTR
+        lea     64(BUF), BUFFER_PTR2
+        shl     $6, CNT                 /* mul by 64 */
+        add     BUF, CNT
+        add     $64, CNT
+        mov     CNT, BUFFER_END
+        cmp     BUFFER_END, BUFFER_PTR2
+        cmovae  K_BASE, BUFFER_PTR2
+        xmm_mov BSWAP_SHUFB_CTL(%rip), YMM_SHUFB_BSWAP
+        SHA1_PIPELINED_MAIN_BODY
+        avx2_zeroupper
+        add     $RESERVE_STACK, %rsp
+        pop     %rsp
+        pop     %r15
+        pop     %r14
+        pop     %r13
+        pop     %r12
+        pop     %rbp
+        pop     %rbx
+        ret
+        ENDPROC(\name)
+.endm
+.section .rodata
+#define K1 0x5a827999
+#define K2 0x6ed9eba1
+#define K3 0x8f1bbcdc
+#define K4 0xca62c1d6
+.align 128
+K_XMM_AR:
+        .long K1, K1, K1, K1
+        .long K1, K1, K1, K1
+        .long K2, K2, K2, K2
+        .long K2, K2, K2, K2
+        .long K3, K3, K3, K3
+        .long K3, K3, K3, K3
+        .long K4, K4, K4, K4
+        .long K4, K4, K4, K4
+BSWAP_SHUFB_CTL:
+        .long 0x00010203
+        .long 0x04050607
+        .long 0x08090a0b
+        .long 0x0c0d0e0f
+        .long 0x00010203
+        .long 0x04050607
+        .long 0x08090a0b
+        .long 0x0c0d0e0f
+.text
+SHA1_VECTOR_ASM     sha1_transform_avx2
diff --git a/arch/x86/crypto/sha1_ssse3_glue.c b/arch/x86/crypto/sha1_ssse3_glue.c
index 4a11a9d72451..74d16ef707c7 100644
--- a/arch/x86/crypto/sha1_ssse3_glue.c
+++ b/arch/x86/crypto/sha1_ssse3_glue.c
@@ -10,6 +10,7 @@
 * Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
 * Copyright (c) Jean-Francois Dive <jef@linuxbe.org>
 * Copyright (c) Mathias Krause <minipli@googlemail.com>
+ * Copyright (c) Chandramouli Narayanan <mouli@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
@@ -39,6 +40,12 @@ asmlinkage void sha1_transform_ssse3(u32 *digest, const char *data,
 asmlinkage void sha1_transform_avx(u32 *digest, const char *data,
                                   unsigned int rounds);
 #endif
+#ifdef CONFIG_AS_AVX2
+#define SHA1_AVX2_BLOCK_OPTSIZE 4       /* optimal 4*64 bytes of SHA1 blocks */
+asmlinkage void sha1_transform_avx2(u32 *digest, const char *data,
+                                unsigned int rounds);
+#endif
 static asmlinkage void (*sha1_transform_asm)(u32 *, const char *, unsigned int);
@@ -165,6 +172,18 @@ static int sha1_ssse3_import(struct shash_desc *desc, const void *in)
        return 0;
 }
+#ifdef CONFIG_AS_AVX2
+static void sha1_apply_transform_avx2(u32 *digest, const char *data,
+                                unsigned int rounds)
+{
+        /* Select the optimal transform based on data block size */
+        if (rounds >= SHA1_AVX2_BLOCK_OPTSIZE)
+                sha1_transform_avx2(digest, data, rounds);
+        else
+                sha1_transform_avx(digest, data, rounds);
+}
+#endif
 static struct shash_alg alg = {
        .digestsize     =       SHA1_DIGEST_SIZE,
        .init           =       sha1_ssse3_init,
@@ -201,27 +220,49 @@ static bool __init avx_usable(void)
        return true;
 }
+#ifdef CONFIG_AS_AVX2
+static bool __init avx2_usable(void)
+{
+        if (avx_usable() && cpu_has_avx2 && boot_cpu_has(X86_FEATURE_BMI1) &&
+            boot_cpu_has(X86_FEATURE_BMI2))
+                return true;
+        return false;
+}
+#endif
 #endif
 static int __init sha1_ssse3_mod_init(void)
 {
+        char *algo_name;
        /* test for SSSE3 first */
-        if (cpu_has_ssse3)
+        if (cpu_has_ssse3) {
                sha1_transform_asm = sha1_transform_ssse3;
+                algo_name = "SSSE3";
+        }
 #ifdef CONFIG_AS_AVX
        /* allow AVX to override SSSE3, it's a little faster */
-        if (avx_usable())
+        if (avx_usable()) {
                sha1_transform_asm = sha1_transform_avx;
+                algo_name = "AVX";
+#ifdef CONFIG_AS_AVX2
+                /* allow AVX2 to override AVX, it's a little faster */
+                if (avx2_usable()) {
+                        sha1_transform_asm = sha1_apply_transform_avx2;
+                        algo_name = "AVX2";
+                }
+#endif
+        }
 #endif
        if (sha1_transform_asm) {
-                pr_info("Using %s optimized SHA-1 implementation\n",
+                pr_info("Using %s optimized SHA-1 implementation\n", algo_name);
-                        sha1_transform_asm == sha1_transform_ssse3 ? "SSSE3"
-                                                                   : "AVX");
                return crypto_register_shash(&alg);
        }
-        pr_info("Neither AVX nor SSSE3 is available/usable.\n");
+        pr_info("Neither AVX nor AVX2 nor SSSE3 is available/usable.\n");
        return -ENODEV;
 }
diff --git a/arch/x86/include/asm/Kbuild b/arch/x86/include/asm/Kbuild
index 4acddc43ee0c..3ca9762e1649 100644
--- a/arch/x86/include/asm/Kbuild
+++ b/arch/x86/include/asm/Kbuild
@@ -5,5 +5,6 @@ genhdr-y += unistd_64.h
 genhdr-y += unistd_x32.h
 generic-y += clkdev.h
+generic-y += early_ioremap.h
 generic-y += cputime.h
 generic-y += mcs_spinlock.h
diff --git a/arch/x86/include/asm/archrandom.h b/arch/x86/include/asm/archrandom.h
index e6a92455740e..69f1366f1aa3 100644
--- a/arch/x86/include/asm/archrandom.h
+++ b/arch/x86/include/asm/archrandom.h
@@ -1,7 +1,7 @@
 /*
 * This file is part of the Linux kernel.
 *
- * Copyright (c) 2011, Intel Corporation
+ * Copyright (c) 2011-2014, Intel Corporation
 * Authors: Fenghua Yu <fenghua.yu@intel.com>,
 *          H. Peter Anvin <hpa@linux.intel.com>
 *
@@ -31,10 +31,13 @@
 #define RDRAND_RETRY_LOOPS      10
 #define RDRAND_INT      ".byte 0x0f,0xc7,0xf0"
+#define RDSEED_INT      ".byte 0x0f,0xc7,0xf8"
 #ifdef CONFIG_X86_64
 # define RDRAND_LONG    ".byte 0x48,0x0f,0xc7,0xf0"
+# define RDSEED_LONG    ".byte 0x48,0x0f,0xc7,0xf8"
 #else
 # define RDRAND_LONG    RDRAND_INT
+# define RDSEED_LONG    RDSEED_INT
 #endif
 #ifdef CONFIG_ARCH_RANDOM
@@ -53,6 +56,16 @@ static inline int rdrand_long(unsigned long *v)
        return ok;
 }
+/* A single attempt at RDSEED */
+static inline bool rdseed_long(unsigned long *v)
+{
+        unsigned char ok;
+        asm volatile(RDSEED_LONG "\n\t"
+                     "setc %0"
+                     : "=qm" (ok), "=a" (*v));
+        return ok;
+}
 #define GET_RANDOM(name, type, rdrand, nop)                     \
 static inline int name(type *v)                                 \
 {                                                               \
@@ -70,18 +83,40 @@ static inline int name(type *v)					\
        return ok;                                              \
 }
+#define GET_SEED(name, type, rdseed, nop)                       \
+static inline int name(type *v)                                 \
+{                                                               \
+        unsigned char ok;                                       \
+        alternative_io("movb $0, %0\n\t"                        \
+                       nop,                                     \
+                       rdseed "\n\t"                            \
+                       "setc %0",                               \
+                       X86_FEATURE_RDSEED,                      \
+                       ASM_OUTPUT2("=q" (ok), "=a" (*v)));      \
+        return ok;                                              \
+}
 #ifdef CONFIG_X86_64
 GET_RANDOM(arch_get_random_long, unsigned long, RDRAND_LONG, ASM_NOP5);
 GET_RANDOM(arch_get_random_int, unsigned int, RDRAND_INT, ASM_NOP4);
+GET_SEED(arch_get_random_seed_long, unsigned long, RDSEED_LONG, ASM_NOP5);
+GET_SEED(arch_get_random_seed_int, unsigned int, RDSEED_INT, ASM_NOP4);
 #else
 GET_RANDOM(arch_get_random_long, unsigned long, RDRAND_LONG, ASM_NOP3);
 GET_RANDOM(arch_get_random_int, unsigned int, RDRAND_INT, ASM_NOP3);
+GET_SEED(arch_get_random_seed_long, unsigned long, RDSEED_LONG, ASM_NOP4);
+GET_SEED(arch_get_random_seed_int, unsigned int, RDSEED_INT, ASM_NOP4);
 #endif /* CONFIG_X86_64 */
+#define arch_has_random()       static_cpu_has(X86_FEATURE_RDRAND)
+#define arch_has_random_seed()  static_cpu_has(X86_FEATURE_RDSEED)
 #else
 static inline int rdrand_long(unsigned long *v)
@@ -89,6 +124,11 @@ static inline int rdrand_long(unsigned long *v)
        return 0;
 }
+static inline bool rdseed_long(unsigned long *v)
+{
+        return 0;
+}
 #endif  /* CONFIG_ARCH_RANDOM */
 extern void x86_init_rdrand(struct cpuinfo_x86 *c);
diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h
index 2f03ff018d36..ba38ebbaced3 100644
--- a/arch/x86/include/asm/bug.h
+++ b/arch/x86/include/asm/bug.h
@@ -1,7 +1,6 @@
 #ifndef _ASM_X86_BUG_H
 #define _ASM_X86_BUG_H
-#ifdef CONFIG_BUG
 #define HAVE_ARCH_BUG
 #ifdef CONFIG_DEBUG_BUGVERBOSE
@@ -33,8 +32,6 @@ do {								\
 } while (0)
 #endif
-#endif /* !CONFIG_BUG */
 #include <asm-generic/bug.h>
 #endif /* _ASM_X86_BUG_H */
diff --git a/arch/x86/include/asm/clocksource.h b/arch/x86/include/asm/clocksource.h
index 16a57f4ed64d..eda81dc0f4ae 100644
--- a/arch/x86/include/asm/clocksource.h
+++ b/arch/x86/include/asm/clocksource.h
@@ -3,8 +3,6 @@
 #ifndef _ASM_X86_CLOCKSOURCE_H
 #define _ASM_X86_CLOCKSOURCE_H
-#ifdef CONFIG_X86_64
 #define VCLOCK_NONE 0  /* No vDSO clock available.      */
 #define VCLOCK_TSC  1  /* vDSO should use vread_tsc.    */
 #define VCLOCK_HPET 2  /* vDSO should use vread_hpet.   */
@@ -14,6 +12,4 @@ struct arch_clocksource_data {
        int vclock_mode;
 };
-#endif /* CONFIG_X86_64 */
 #endif /* _ASM_X86_CLOCKSOURCE_H */
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 63211ef5046a..e265ff95d16d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -546,6 +546,13 @@ static __always_inline __pure bool _static_cpu_has_safe(u16 bit)
 #define static_cpu_has_bug(bit) static_cpu_has((bit))
 #define boot_cpu_has_bug(bit)   cpu_has_bug(&boot_cpu_data, (bit))
+#define MAX_CPU_FEATURES        (NCAPINTS * 32)
+#define cpu_have_feature        boot_cpu_has
+#define CPU_FEATURE_TYPEFMT     "x86,ven%04Xfam%04Xmod%04X"
+#define CPU_FEATURE_TYPEVAL     boot_cpu_data.x86_vendor, boot_cpu_data.x86, \
+                                boot_cpu_data.x86_model
 #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
 #endif /* _ASM_X86_CPUFEATURE_H */
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index 9c999c1674fa..2c71182d30ef 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -281,16 +281,12 @@ do {									\
 #define STACK_RND_MASK (0x7ff)
-#define VDSO_HIGH_BASE          (__fix_to_virt(FIX_VDSO))
 #define ARCH_DLINFO             ARCH_DLINFO_IA32(vdso_enabled)
 /* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
 #else /* CONFIG_X86_32 */
-#define VDSO_HIGH_BASE          0xffffe000U /* CONFIG_COMPAT_VDSO address */
 /* 1GB for 64bit, 8MB for 32bit */
 #define STACK_RND_MASK (test_thread_flag(TIF_ADDR32) ? 0x7ff : 0x3fffff)
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 7252cd339175..43f482a0db37 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -40,15 +40,8 @@
 */
 extern unsigned long __FIXADDR_TOP;
 #define FIXADDR_TOP     ((unsigned long)__FIXADDR_TOP)
-#define FIXADDR_USER_START     __fix_to_virt(FIX_VDSO)
-#define FIXADDR_USER_END       __fix_to_virt(FIX_VDSO - 1)
 #else
 #define FIXADDR_TOP     (VSYSCALL_END-PAGE_SIZE)
-/* Only covers 32bit vsyscalls currently. Need another set for 64bit. */
-#define FIXADDR_USER_START      ((unsigned long)VSYSCALL32_VSYSCALL)
-#define FIXADDR_USER_END        (FIXADDR_USER_START + PAGE_SIZE)
 #endif
@@ -74,7 +67,6 @@ extern unsigned long __FIXADDR_TOP;
 enum fixed_addresses {
 #ifdef CONFIG_X86_32
        FIX_HOLE,
-        FIX_VDSO,
 #else
        VSYSCALL_LAST_PAGE,
        VSYSCALL_FIRST_PAGE = VSYSCALL_LAST_PAGE
@@ -98,12 +90,6 @@ enum fixed_addresses {
        FIX_IO_APIC_BASE_0,
        FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
 #endif
-#ifdef CONFIG_X86_VISWS_APIC
-        FIX_CO_CPU,     /* Cobalt timer */
-        FIX_CO_APIC,    /* Cobalt APIC Redirection Table */
-        FIX_LI_PCIA,    /* Lithium PCI Bridge A */
-        FIX_LI_PCIB,    /* Lithium PCI Bridge B */
-#endif
        FIX_RO_IDT,     /* Virtual mapping for read-only IDT */
 #ifdef CONFIG_X86_32
        FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
@@ -177,5 +163,11 @@ static inline void __set_fixmap(enum fixed_addresses idx,
 #include <asm-generic/fixmap.h>
+#define __late_set_fixmap(idx, phys, flags) __set_fixmap(idx, phys, flags)
+#define __late_clear_fixmap(idx) __set_fixmap(idx, 0, __pgprot(0))
+void __early_set_fixmap(enum fixed_addresses idx,
+                        phys_addr_t phys, pgprot_t flags);
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASM_X86_FIXMAP_H */
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index 67d69b8e2d20..a307b7530e54 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -98,7 +98,6 @@ extern void trace_call_function_single_interrupt(void);
 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs))
 extern unsigned long io_apic_irqs;
-extern void init_VISWS_APIC_irqs(void);
 extern void setup_IO_APIC(void);
 extern void disable_IO_APIC(void);
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 91d9c69a629e..b8237d8a1e0c 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -39,6 +39,7 @@
 #include <linux/string.h>
 #include <linux/compiler.h>
 #include <asm/page.h>
+#include <asm/early_ioremap.h>
 #define build_mmio_read(name, size, type, reg, barrier) \
 static inline type name(const volatile void __iomem *addr) \
@@ -316,19 +317,6 @@ extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
                                unsigned long prot_val);
 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
-/*
- * early_ioremap() and early_iounmap() are for temporary early boot-time
- * mappings, before the real ioremap() is functional.
- * A boot-time mapping is currently limited to at most 16 pages.
- */
-extern void early_ioremap_init(void);
-extern void early_ioremap_reset(void);
-extern void __iomem *early_ioremap(resource_size_t phys_addr,
-                                   unsigned long size);
-extern void __iomem *early_memremap(resource_size_t phys_addr,
-                                    unsigned long size);
-extern void early_iounmap(void __iomem *addr, unsigned long size);
-extern void fixup_early_ioremap(void);
 extern bool is_early_ioremap_ptep(pte_t *ptep);
 #ifdef CONFIG_XEN
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index fdf83afbb7d9..fcaf9c961265 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -337,6 +337,11 @@ struct kvm_pmu {
        u64 reprogram_pmi;
 };
+enum {
+        KVM_DEBUGREG_BP_ENABLED = 1,
+        KVM_DEBUGREG_WONT_EXIT = 2,
+};
 struct kvm_vcpu_arch {
        /*
         * rip and regs accesses must go through
@@ -444,7 +449,6 @@ struct kvm_vcpu_arch {
        } st;
        u64 last_guest_tsc;
-        u64 last_kernel_ns;
        u64 last_host_tsc;
        u64 tsc_offset_adjustment;
        u64 this_tsc_nsec;
@@ -464,7 +468,7 @@ struct kvm_vcpu_arch {
        struct mtrr_state_type mtrr_state;
        u32 pat;
-        int switch_db_regs;
+        unsigned switch_db_regs;
        unsigned long db[KVM_NR_DB_REGS];
        unsigned long dr6;
        unsigned long dr7;
@@ -599,6 +603,8 @@ struct kvm_arch {
        bool use_master_clock;
        u64 master_kernel_ns;
        cycle_t master_cycle_now;
+        struct delayed_work kvmclock_update_work;
+        struct delayed_work kvmclock_sync_work;
        struct kvm_xen_hvm_config xen_hvm_config;
@@ -702,6 +708,7 @@ struct kvm_x86_ops {
        void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
        u64 (*get_dr6)(struct kvm_vcpu *vcpu);
        void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value);
+        void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu);
        void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
        void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
        unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
@@ -728,8 +735,8 @@ struct kvm_x86_ops {
        int (*nmi_allowed)(struct kvm_vcpu *vcpu);
        bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
        void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
-        int (*enable_nmi_window)(struct kvm_vcpu *vcpu);
+        void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
-        int (*enable_irq_window)(struct kvm_vcpu *vcpu);
+        void (*enable_irq_window)(struct kvm_vcpu *vcpu);
        void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
        int (*vm_has_apicv)(struct kvm *kvm);
        void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
@@ -765,6 +772,9 @@ struct kvm_x86_ops {
                               struct x86_instruction_info *info,
                               enum x86_intercept_stage stage);
        void (*handle_external_intr)(struct kvm_vcpu *vcpu);
+        bool (*mpx_supported)(void);
+        int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr);
 };
 struct kvm_arch_async_pf {
diff --git a/arch/x86/include/asm/mmzone_32.h b/arch/x86/include/asm/mmzone_32.h
index 8a9b3e288cb4..1ec990bd7dc0 100644
--- a/arch/x86/include/asm/mmzone_32.h
+++ b/arch/x86/include/asm/mmzone_32.h
@@ -11,9 +11,6 @@
 #ifdef CONFIG_NUMA
 extern struct pglist_data *node_data[];
 #define NODE_DATA(nid)  (node_data[nid])
-#include <asm/numaq.h>
 #endif /* CONFIG_NUMA */
 #ifdef CONFIG_DISCONTIGMEM
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index 3e6b4920ef5d..f5a617956735 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -25,12 +25,6 @@ extern int pic_mode;
 extern unsigned int def_to_bigsmp;
-#ifdef CONFIG_X86_NUMAQ
-extern int mp_bus_id_to_node[MAX_MP_BUSSES];
-extern int mp_bus_id_to_local[MAX_MP_BUSSES];
-extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
-#endif
 #else /* CONFIG_X86_64: */
 #define MAX_MP_BUSSES           256
diff --git a/arch/x86/include/asm/numaq.h b/arch/x86/include/asm/numaq.h
deleted file mode 100644
index c3b3c322fd87..000000000000
--- a/arch/x86/include/asm/numaq.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Written by: Patricia Gaughen, IBM Corporation
- *
- * Copyright (C) 2002, IBM Corp.
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Send feedback to <gone@us.ibm.com>
- */
-#ifndef _ASM_X86_NUMAQ_H
-#define _ASM_X86_NUMAQ_H
-#ifdef CONFIG_X86_NUMAQ
-extern int found_numaq;
-extern int numaq_numa_init(void);
-extern int pci_numaq_init(void);
-extern void *xquad_portio;
-#define XQUAD_PORTIO_BASE 0xfe400000
-#define XQUAD_PORTIO_QUAD 0x40000  /* 256k per quad. */
-#define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
-/*
- * SYS_CFG_DATA_PRIV_ADDR, struct eachquadmem, and struct sys_cfg_data are the
- */
-#define SYS_CFG_DATA_PRIV_ADDR          0x0009d000 /* place for scd in private
-                                                      quad space */
-/*
- * Communication area for each processor on lynxer-processor tests.
- *
- * NOTE: If you change the size of this eachproc structure you need
- *       to change the definition for EACH_QUAD_SIZE.
- */
-struct eachquadmem {
-        unsigned int    priv_mem_start;         /* Starting address of this */
-                                                /* quad's private memory. */
-                                                /* This is always 0. */
-                                                /* In MB. */
-        unsigned int    priv_mem_size;          /* Size of this quad's */
-                                                /* private memory. */
-                                                /* In MB. */
-        unsigned int    low_shrd_mem_strp_start;/* Starting address of this */
-                                                /* quad's low shared block */
-                                                /* (untranslated). */
-                                                /* In MB. */
-        unsigned int    low_shrd_mem_start;     /* Starting address of this */
-                                                /* quad's low shared memory */
-                                                /* (untranslated). */
-                                                /* In MB. */
-        unsigned int    low_shrd_mem_size;      /* Size of this quad's low */
-                                                /* shared memory. */
-                                                /* In MB. */
-        unsigned int    lmmio_copb_start;       /* Starting address of this */
-                                                /* quad's local memory */
-                                                /* mapped I/O in the */
-                                                /* compatibility OPB. */
-                                                /* In MB. */
-        unsigned int    lmmio_copb_size;        /* Size of this quad's local */
-                                                /* memory mapped I/O in the */
-                                                /* compatibility OPB. */
-                                                /* In MB. */
-        unsigned int    lmmio_nopb_start;       /* Starting address of this */
-                                                /* quad's local memory */
-                                                /* mapped I/O in the */
-                                                /* non-compatibility OPB. */
-                                                /* In MB. */
-        unsigned int    lmmio_nopb_size;        /* Size of this quad's local */
-                                                /* memory mapped I/O in the */
-                                                /* non-compatibility OPB. */
-                                                /* In MB. */
-        unsigned int    io_apic_0_start;        /* Starting address of I/O */
-                                                /* APIC 0. */
-        unsigned int    io_apic_0_sz;           /* Size I/O APIC 0. */
-        unsigned int    io_apic_1_start;        /* Starting address of I/O */
-                                                /* APIC 1. */
-        unsigned int    io_apic_1_sz;           /* Size I/O APIC 1. */
-        unsigned int    hi_shrd_mem_start;      /* Starting address of this */
-                                                /* quad's high shared memory.*/
-                                                /* In MB. */
-        unsigned int    hi_shrd_mem_size;       /* Size of this quad's high */
-                                                /* shared memory. */
-                                                /* In MB. */
-        unsigned int    mps_table_addr;         /* Address of this quad's */
-                                                /* MPS tables from BIOS, */
-                                                /* in system space.*/
-        unsigned int    lcl_MDC_pio_addr;       /* Port-I/O address for */
-                                                /* local access of MDC. */
-        unsigned int    rmt_MDC_mmpio_addr;     /* MM-Port-I/O address for */
-                                                /* remote access of MDC. */
-        unsigned int    mm_port_io_start;       /* Starting address of this */
-                                                /* quad's memory mapped Port */
-                                                /* I/O space. */
-        unsigned int    mm_port_io_size;        /* Size of this quad's memory*/
-                                                /* mapped Port I/O space. */
-        unsigned int    mm_rmt_io_apic_start;   /* Starting address of this */
-                                                /* quad's memory mapped */
-                                                /* remote I/O APIC space. */
-        unsigned int    mm_rmt_io_apic_size;    /* Size of this quad's memory*/
-                                                /* mapped remote I/O APIC */
-                                                /* space. */
-        unsigned int    mm_isa_start;           /* Starting address of this */
-                                                /* quad's memory mapped ISA */
-                                                /* space (contains MDC */
-                                                /* memory space). */
-        unsigned int    mm_isa_size;            /* Size of this quad's memory*/
-                                                /* mapped ISA space (contains*/
-                                                /* MDC memory space). */
-        unsigned int    rmt_qmi_addr;           /* Remote addr to access QMI.*/
-        unsigned int    lcl_qmi_addr;           /* Local addr to access QMI. */
-};
-/*
- * Note: This structure must be NOT be changed unless the multiproc and
- * OS are changed to reflect the new structure.
- */
-struct sys_cfg_data {
-        unsigned int    quad_id;
-        unsigned int    bsp_proc_id; /* Boot Strap Processor in this quad. */
-        unsigned int    scd_version; /* Version number of this table. */
-        unsigned int    first_quad_id;
-        unsigned int    quads_present31_0; /* 1 bit for each quad */
-        unsigned int    quads_present63_32; /* 1 bit for each quad */
-        unsigned int    config_flags;
-        unsigned int    boot_flags;
-        unsigned int    csr_start_addr; /* Absolute value (not in MB) */
-        unsigned int    csr_size; /* Absolute value (not in MB) */
-        unsigned int    lcl_apic_start_addr; /* Absolute value (not in MB) */
-        unsigned int    lcl_apic_size; /* Absolute value (not in MB) */
-        unsigned int    low_shrd_mem_base; /* 0 or 512MB or 1GB */
-        unsigned int    low_shrd_mem_quad_offset; /* 0,128M,256M,512M,1G */
-                                        /* may not be totally populated */
-        unsigned int    split_mem_enbl; /* 0 for no low shared memory */
-        unsigned int    mmio_sz; /* Size of total system memory mapped I/O */
-                                 /* (in MB). */
-        unsigned int    quad_spin_lock; /* Spare location used for quad */
-                                        /* bringup. */
-        unsigned int    nonzero55; /* For checksumming. */
-        unsigned int    nonzeroaa; /* For checksumming. */
-        unsigned int    scd_magic_number;
-        unsigned int    system_type;
-        unsigned int    checksum;
-        /*
-         *      memory configuration area for each quad
-         */
-        struct          eachquadmem eq[MAX_NUMNODES];   /* indexed by quad id */
-};
-void numaq_tsc_disable(void);
-#endif /* CONFIG_X86_NUMAQ */
-#endif /* _ASM_X86_NUMAQ_H */
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 1ac6114c9ea5..96ae4f4040bb 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -26,11 +26,6 @@ extern int pci_routeirq;
 extern int noioapicquirk;
 extern int noioapicreroute;
-/* scan a bus after allocating a pci_sysdata for it */
-extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops,
-                                            int node);
-extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);
 #ifdef CONFIG_PCI
 #ifdef CONFIG_PCI_DOMAINS
@@ -70,7 +65,7 @@ extern unsigned long pci_mem_start;
 extern int pcibios_enabled;
 void pcibios_config_init(void);
-struct pci_bus *pcibios_scan_root(int bus);
+void pcibios_scan_root(int bus);
 void pcibios_set_master(struct pci_dev *dev);
 void pcibios_penalize_isa_irq(int irq, int active);
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index 94220d14d5cc..851bcdc5db04 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -52,7 +52,7 @@
 * Compared to the generic __my_cpu_offset version, the following
 * saves one instruction and avoids clobbering a temp register.
 */
-#define __this_cpu_ptr(ptr)                             \
+#define raw_cpu_ptr(ptr)                                \
 ({                                                      \
        unsigned long tcp_ptr__;                        \
        __verify_pcpu_ptr(ptr);                         \
@@ -362,25 +362,25 @@ do {									\
 */
 #define this_cpu_read_stable(var)       percpu_from_op("mov", var, "p" (&(var)))
-#define __this_cpu_read_1(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
+#define raw_cpu_read_1(pcp)             percpu_from_op("mov", (pcp), "m"(pcp))
-#define __this_cpu_read_2(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
+#define raw_cpu_read_2(pcp)             percpu_from_op("mov", (pcp), "m"(pcp))
-#define __this_cpu_read_4(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
+#define raw_cpu_read_4(pcp)             percpu_from_op("mov", (pcp), "m"(pcp))
-#define __this_cpu_write_1(pcp, val)    percpu_to_op("mov", (pcp), val)
+#define raw_cpu_write_1(pcp, val)       percpu_to_op("mov", (pcp), val)
-#define __this_cpu_write_2(pcp, val)    percpu_to_op("mov", (pcp), val)
+#define raw_cpu_write_2(pcp, val)       percpu_to_op("mov", (pcp), val)
-#define __this_cpu_write_4(pcp, val)    percpu_to_op("mov", (pcp), val)
+#define raw_cpu_write_4(pcp, val)       percpu_to_op("mov", (pcp), val)
-#define __this_cpu_add_1(pcp, val)      percpu_add_op((pcp), val)
+#define raw_cpu_add_1(pcp, val)         percpu_add_op((pcp), val)
-#define __this_cpu_add_2(pcp, val)      percpu_add_op((pcp), val)
+#define raw_cpu_add_2(pcp, val)         percpu_add_op((pcp), val)
-#define __this_cpu_add_4(pcp, val)      percpu_add_op((pcp), val)
+#define raw_cpu_add_4(pcp, val)         percpu_add_op((pcp), val)
-#define __this_cpu_and_1(pcp, val)      percpu_to_op("and", (pcp), val)
+#define raw_cpu_and_1(pcp, val)         percpu_to_op("and", (pcp), val)
-#define __this_cpu_and_2(pcp, val)      percpu_to_op("and", (pcp), val)
+#define raw_cpu_and_2(pcp, val)         percpu_to_op("and", (pcp), val)
-#define __this_cpu_and_4(pcp, val)      percpu_to_op("and", (pcp), val)
+#define raw_cpu_and_4(pcp, val)         percpu_to_op("and", (pcp), val)
-#define __this_cpu_or_1(pcp, val)       percpu_to_op("or", (pcp), val)
+#define raw_cpu_or_1(pcp, val)          percpu_to_op("or", (pcp), val)
-#define __this_cpu_or_2(pcp, val)       percpu_to_op("or", (pcp), val)
+#define raw_cpu_or_2(pcp, val)          percpu_to_op("or", (pcp), val)
-#define __this_cpu_or_4(pcp, val)       percpu_to_op("or", (pcp), val)
+#define raw_cpu_or_4(pcp, val)          percpu_to_op("or", (pcp), val)
-#define __this_cpu_xchg_1(pcp, val)     percpu_xchg_op(pcp, val)
+#define raw_cpu_xchg_1(pcp, val)        percpu_xchg_op(pcp, val)
-#define __this_cpu_xchg_2(pcp, val)     percpu_xchg_op(pcp, val)
+#define raw_cpu_xchg_2(pcp, val)        percpu_xchg_op(pcp, val)
-#define __this_cpu_xchg_4(pcp, val)     percpu_xchg_op(pcp, val)
+#define raw_cpu_xchg_4(pcp, val)        percpu_xchg_op(pcp, val)
 #define this_cpu_read_1(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
 #define this_cpu_read_2(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
@@ -401,16 +401,16 @@ do {									\
 #define this_cpu_xchg_2(pcp, nval)      percpu_xchg_op(pcp, nval)
 #define this_cpu_xchg_4(pcp, nval)      percpu_xchg_op(pcp, nval)
-#define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
+#define raw_cpu_add_return_1(pcp, val)          percpu_add_return_op(pcp, val)
-#define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
+#define raw_cpu_add_return_2(pcp, val)          percpu_add_return_op(pcp, val)
-#define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
+#define raw_cpu_add_return_4(pcp, val)          percpu_add_return_op(pcp, val)
-#define __this_cpu_cmpxchg_1(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
+#define raw_cpu_cmpxchg_1(pcp, oval, nval)      percpu_cmpxchg_op(pcp, oval, nval)
-#define __this_cpu_cmpxchg_2(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
+#define raw_cpu_cmpxchg_2(pcp, oval, nval)      percpu_cmpxchg_op(pcp, oval, nval)
-#define __this_cpu_cmpxchg_4(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
+#define raw_cpu_cmpxchg_4(pcp, oval, nval)      percpu_cmpxchg_op(pcp, oval, nval)
-#define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
+#define this_cpu_add_return_1(pcp, val)         percpu_add_return_op(pcp, val)
-#define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
+#define this_cpu_add_return_2(pcp, val)         percpu_add_return_op(pcp, val)
-#define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
+#define this_cpu_add_return_4(pcp, val)         percpu_add_return_op(pcp, val)
 #define this_cpu_cmpxchg_1(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 #define this_cpu_cmpxchg_2(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 #define this_cpu_cmpxchg_4(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
@@ -427,7 +427,7 @@ do {									\
        __ret;                                                          \
 })
-#define __this_cpu_cmpxchg_double_4     percpu_cmpxchg8b_double
+#define raw_cpu_cmpxchg_double_4        percpu_cmpxchg8b_double
 #define this_cpu_cmpxchg_double_4       percpu_cmpxchg8b_double
 #endif /* CONFIG_X86_CMPXCHG64 */
@@ -436,22 +436,22 @@ do {									\
 * 32 bit must fall back to generic operations.
 */
 #ifdef CONFIG_X86_64
-#define __this_cpu_read_8(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
+#define raw_cpu_read_8(pcp)                     percpu_from_op("mov", (pcp), "m"(pcp))
-#define __this_cpu_write_8(pcp, val)    percpu_to_op("mov", (pcp), val)
+#define raw_cpu_write_8(pcp, val)               percpu_to_op("mov", (pcp), val)
-#define __this_cpu_add_8(pcp, val)      percpu_add_op((pcp), val)
+#define raw_cpu_add_8(pcp, val)                 percpu_add_op((pcp), val)
-#define __this_cpu_and_8(pcp, val)      percpu_to_op("and", (pcp), val)
+#define raw_cpu_and_8(pcp, val)                 percpu_to_op("and", (pcp), val)
-#define __this_cpu_or_8(pcp, val)       percpu_to_op("or", (pcp), val)
+#define raw_cpu_or_8(pcp, val)                  percpu_to_op("or", (pcp), val)
-#define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
+#define raw_cpu_add_return_8(pcp, val)          percpu_add_return_op(pcp, val)
-#define __this_cpu_xchg_8(pcp, nval)    percpu_xchg_op(pcp, nval)
+#define raw_cpu_xchg_8(pcp, nval)               percpu_xchg_op(pcp, nval)
-#define __this_cpu_cmpxchg_8(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
+#define raw_cpu_cmpxchg_8(pcp, oval, nval)      percpu_cmpxchg_op(pcp, oval, nval)
-#define this_cpu_read_8(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
+#define this_cpu_read_8(pcp)                    percpu_from_op("mov", (pcp), "m"(pcp))
-#define this_cpu_write_8(pcp, val)      percpu_to_op("mov", (pcp), val)
+#define this_cpu_write_8(pcp, val)              percpu_to_op("mov", (pcp), val)
-#define this_cpu_add_8(pcp, val)        percpu_add_op((pcp), val)
+#define this_cpu_add_8(pcp, val)                percpu_add_op((pcp), val)
-#define this_cpu_and_8(pcp, val)        percpu_to_op("and", (pcp), val)
+#define this_cpu_and_8(pcp, val)                percpu_to_op("and", (pcp), val)
-#define this_cpu_or_8(pcp, val)         percpu_to_op("or", (pcp), val)
+#define this_cpu_or_8(pcp, val)                 percpu_to_op("or", (pcp), val)
-#define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
+#define this_cpu_add_return_8(pcp, val)         percpu_add_return_op(pcp, val)
-#define this_cpu_xchg_8(pcp, nval)      percpu_xchg_op(pcp, nval)
+#define this_cpu_xchg_8(pcp, nval)              percpu_xchg_op(pcp, nval)
 #define this_cpu_cmpxchg_8(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 /*
@@ -474,7 +474,7 @@ do {									\
        __ret;                                                          \
 })
-#define __this_cpu_cmpxchg_double_8     percpu_cmpxchg16b_double
+#define raw_cpu_cmpxchg_double_8        percpu_cmpxchg16b_double
 #define this_cpu_cmpxchg_double_8       percpu_cmpxchg16b_double
 #endif
@@ -495,9 +495,9 @@ static __always_inline int x86_this_cpu_constant_test_bit(unsigned int nr,
        unsigned long __percpu *a = (unsigned long *)addr + nr / BITS_PER_LONG;
 #ifdef CONFIG_X86_64
-        return ((1UL << (nr % BITS_PER_LONG)) & __this_cpu_read_8(*a)) != 0;
+        return ((1UL << (nr % BITS_PER_LONG)) & raw_cpu_read_8(*a)) != 0;
 #else
-        return ((1UL << (nr % BITS_PER_LONG)) & __this_cpu_read_4(*a)) != 0;
+        return ((1UL << (nr % BITS_PER_LONG)) & raw_cpu_read_4(*a)) != 0;
 #endif
 }
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 708f19fb4fc7..eb3d44945133 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -214,13 +214,8 @@
 #ifdef CONFIG_X86_64
 #define __PAGE_KERNEL_IDENT_LARGE_EXEC  __PAGE_KERNEL_LARGE_EXEC
 #else
-/*
- * For PDE_IDENT_ATTR include USER bit. As the PDE and PTE protection
- * bits are combined, this will alow user to access the high address mapped
- * VDSO in the presence of CONFIG_COMPAT_VDSO
- */
 #define PTE_IDENT_ATTR   0x003          /* PRESENT+RW */
-#define PDE_IDENT_ATTR   0x067          /* PRESENT+RW+USER+DIRTY+ACCESSED */
+#define PDE_IDENT_ATTR   0x063          /* PRESENT+RW+DIRTY+ACCESSED */
 #define PGD_IDENT_ATTR   0x001          /* PRESENT (no other attributes) */
 #endif
diff --git a/arch/x86/include/asm/preempt.h b/arch/x86/include/asm/preempt.h
index c8b051933b1b..7024c12f7bfe 100644
--- a/arch/x86/include/asm/preempt.h
+++ b/arch/x86/include/asm/preempt.h
@@ -19,12 +19,12 @@ DECLARE_PER_CPU(int, __preempt_count);
 */
 static __always_inline int preempt_count(void)
 {
-        return __this_cpu_read_4(__preempt_count) & ~PREEMPT_NEED_RESCHED;
+        return raw_cpu_read_4(__preempt_count) & ~PREEMPT_NEED_RESCHED;
 }
 static __always_inline void preempt_count_set(int pc)
 {
-        __this_cpu_write_4(__preempt_count, pc);
+        raw_cpu_write_4(__preempt_count, pc);
 }
 /*
@@ -53,17 +53,17 @@ static __always_inline void preempt_count_set(int pc)
 static __always_inline void set_preempt_need_resched(void)
 {
-        __this_cpu_and_4(__preempt_count, ~PREEMPT_NEED_RESCHED);
+        raw_cpu_and_4(__preempt_count, ~PREEMPT_NEED_RESCHED);
 }
 static __always_inline void clear_preempt_need_resched(void)
 {
-        __this_cpu_or_4(__preempt_count, PREEMPT_NEED_RESCHED);
+        raw_cpu_or_4(__preempt_count, PREEMPT_NEED_RESCHED);
 }
 static __always_inline bool test_preempt_need_resched(void)
 {
-        return !(__this_cpu_read_4(__preempt_count) & PREEMPT_NEED_RESCHED);
+        return !(raw_cpu_read_4(__preempt_count) & PREEMPT_NEED_RESCHED);
 }
 /*
@@ -72,12 +72,12 @@ static __always_inline bool test_preempt_need_resched(void)
 static __always_inline void __preempt_count_add(int val)
 {
-        __this_cpu_add_4(__preempt_count, val);
+        raw_cpu_add_4(__preempt_count, val);
 }
 static __always_inline void __preempt_count_sub(int val)
 {
-        __this_cpu_add_4(__preempt_count, -val);
+        raw_cpu_add_4(__preempt_count, -val);
 }
 /*
@@ -95,7 +95,7 @@ static __always_inline bool __preempt_count_dec_and_test(void)
 */
 static __always_inline bool should_resched(void)
 {
-        return unlikely(!__this_cpu_read_4(__preempt_count));
+        return unlikely(!raw_cpu_read_4(__preempt_count));
 }
 #ifdef CONFIG_PREEMPT
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index d62c9f809bc5..9264f04a4c55 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -39,12 +39,6 @@ static inline void vsmp_init(void) { }
 void setup_bios_corruption_check(void);
-#ifdef CONFIG_X86_VISWS
-extern void visws_early_detect(void);
-#else
-static inline void visws_early_detect(void) { }
-#endif
 extern unsigned long saved_video_mode;
 extern void reserve_standard_io_resources(void);
diff --git a/arch/x86/include/asm/syscall.h b/arch/x86/include/asm/syscall.h
index aea284b41312..d6a756ae04c8 100644
--- a/arch/x86/include/asm/syscall.h
+++ b/arch/x86/include/asm/syscall.h
@@ -13,7 +13,7 @@
 #ifndef _ASM_X86_SYSCALL_H
 #define _ASM_X86_SYSCALL_H
-#include <linux/audit.h>
+#include <uapi/linux/audit.h>
 #include <linux/sched.h>
 #include <linux/err.h>
 #include <asm/asm-offsets.h>    /* For NR_syscalls */
@@ -91,8 +91,7 @@ static inline void syscall_set_arguments(struct task_struct *task,
        memcpy(&regs->bx + i, args, n * sizeof(args[0]));
 }
-static inline int syscall_get_arch(struct task_struct *task,
+static inline int syscall_get_arch(void)
-                                   struct pt_regs *regs)
 {
        return AUDIT_ARCH_I386;
 }
@@ -221,8 +220,7 @@ static inline void syscall_set_arguments(struct task_struct *task,
                }
 }
-static inline int syscall_get_arch(struct task_struct *task,
+static inline int syscall_get_arch(void)
-                                   struct pt_regs *regs)
 {
 #ifdef CONFIG_IA32_EMULATION
        /*
@@ -234,7 +232,7 @@ static inline int syscall_get_arch(struct task_struct *task,
         *
         * x32 tasks should be considered AUDIT_ARCH_X86_64.
         */
-        if (task_thread_info(task)->status & TS_COMPAT)
+        if (task_thread_info(current)->status & TS_COMPAT)
                return AUDIT_ARCH_I386;
 #endif
        /* Both x32 and x86_64 are considered "64-bit". */
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index b28097e4c8c3..0e8f04f2c26f 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -132,19 +132,7 @@ static inline void arch_fix_phys_package_id(int num, u32 slot)
 }
 struct pci_bus;
+int x86_pci_root_bus_node(int bus);
 void x86_pci_root_bus_resources(int bus, struct list_head *resources);
-#ifdef CONFIG_NUMA
-extern int get_mp_bus_to_node(int busnum);
-extern void set_mp_bus_to_node(int busnum, int node);
-#else
-static inline int get_mp_bus_to_node(int busnum)
-{
-        return 0;
-}
-static inline void set_mp_bus_to_node(int busnum, int node)
-{
-}
-#endif
 #endif /* _ASM_X86_TOPOLOGY_H */
diff --git a/arch/x86/include/asm/vdso.h b/arch/x86/include/asm/vdso.h
index fddb53d63915..d1dc55404ff1 100644
--- a/arch/x86/include/asm/vdso.h
+++ b/arch/x86/include/asm/vdso.h
@@ -1,8 +1,45 @@
 #ifndef _ASM_X86_VDSO_H
 #define _ASM_X86_VDSO_H
+#include <asm/page_types.h>
+#include <linux/linkage.h>
+#ifdef __ASSEMBLER__
+#define DEFINE_VDSO_IMAGE(symname, filename)                            \
+__PAGE_ALIGNED_DATA ;                                                   \
+        .globl symname##_start, symname##_end ;                         \
+        .align PAGE_SIZE ;                                              \
+        symname##_start: ;                                              \
+        .incbin filename ;                                              \
+        symname##_end: ;                                                \
+        .align PAGE_SIZE /* extra data here leaks to userspace. */ ;    \
+                                                                        \
+.previous ;                                                             \
+                                                                        \
+        .globl symname##_pages ;                                        \
+        .bss ;                                                          \
+        .align 8 ;                                                      \
+        .type symname##_pages, @object ;                                \
+        symname##_pages: ;                                              \
+        .zero (symname##_end - symname##_start + PAGE_SIZE - 1) / PAGE_SIZE * (BITS_PER_LONG / 8) ; \
+        .size symname##_pages, .-symname##_pages
+#else
+#define DECLARE_VDSO_IMAGE(symname)                             \
+        extern char symname##_start[], symname##_end[];         \
+        extern struct page *symname##_pages[]
 #if defined CONFIG_X86_32 || defined CONFIG_COMPAT
-extern const char VDSO32_PRELINK[];
+#include <asm/vdso32.h>
+DECLARE_VDSO_IMAGE(vdso32_int80);
+#ifdef CONFIG_COMPAT
+DECLARE_VDSO_IMAGE(vdso32_syscall);
+#endif
+DECLARE_VDSO_IMAGE(vdso32_sysenter);
 /*
 * Given a pointer to the vDSO image, find the pointer to VDSO32_name
@@ -11,8 +48,7 @@ extern const char VDSO32_PRELINK[];
 #define VDSO32_SYMBOL(base, name)                                       \
 ({                                                                      \
        extern const char VDSO32_##name[];                              \
-        (void __user *)(VDSO32_##name - VDSO32_PRELINK +                \
+        (void __user *)(VDSO32_##name + (unsigned long)(base));         \
-                        (unsigned long)(base));                         \
 })
 #endif
@@ -23,12 +59,8 @@ extern const char VDSO32_PRELINK[];
 extern void __user __kernel_sigreturn;
 extern void __user __kernel_rt_sigreturn;
-/*
+void __init patch_vdso32(void *vdso, size_t len);
- * These symbols are defined by vdso32.S to mark the bounds
- * of the ELF DSO images included therein.
+#endif /* __ASSEMBLER__ */
- */
-extern const char vdso32_int80_start, vdso32_int80_end;
-extern const char vdso32_syscall_start, vdso32_syscall_end;
-extern const char vdso32_sysenter_start, vdso32_sysenter_end;
 #endif /* _ASM_X86_VDSO_H */
diff --git a/arch/x86/include/asm/vdso32.h b/arch/x86/include/asm/vdso32.h
new file mode 100644
index 000000000000..7efb7018406e
--- /dev/null
+++ b/arch/x86/include/asm/vdso32.h
@@ -0,0 +1,11 @@
+#ifndef _ASM_X86_VDSO32_H
+#define _ASM_X86_VDSO32_H
+#define VDSO_BASE_PAGE  0
+#define VDSO_VVAR_PAGE  1
+#define VDSO_HPET_PAGE  2
+#define VDSO_PAGES      3
+#define VDSO_PREV_PAGES 2
+#define VDSO_OFFSET(x)  ((x) * PAGE_SIZE)
+#endif
diff --git a/arch/x86/include/asm/vgtod.h b/arch/x86/include/asm/vgtod.h
index 46e24d36b7da..3c3366c2e37f 100644
--- a/arch/x86/include/asm/vgtod.h
+++ b/arch/x86/include/asm/vgtod.h
@@ -1,30 +1,73 @@
 #ifndef _ASM_X86_VGTOD_H
 #define _ASM_X86_VGTOD_H
-#include <asm/vsyscall.h>
+#include <linux/compiler.h>
 #include <linux/clocksource.h>
+#ifdef BUILD_VDSO32_64
+typedef u64 gtod_long_t;
+#else
+typedef unsigned long gtod_long_t;
+#endif
+/*
+ * vsyscall_gtod_data will be accessed by 32 and 64 bit code at the same time
+ * so be carefull by modifying this structure.
+ */
 struct vsyscall_gtod_data {
-        seqcount_t      seq;
+        unsigned seq;
-        struct { /* extract of a clocksource struct */
+        int vclock_mode;
-                int vclock_mode;
+        cycle_t cycle_last;
-                cycle_t cycle_last;
+        cycle_t mask;
-                cycle_t mask;
+        u32     mult;
-                u32     mult;
+        u32     shift;
-                u32     shift;
-        } clock;
        /* open coded 'struct timespec' */
-        time_t          wall_time_sec;
        u64             wall_time_snsec;
+        gtod_long_t     wall_time_sec;
+        gtod_long_t     monotonic_time_sec;
        u64             monotonic_time_snsec;
-        time_t          monotonic_time_sec;
+        gtod_long_t     wall_time_coarse_sec;
+        gtod_long_t     wall_time_coarse_nsec;
+        gtod_long_t     monotonic_time_coarse_sec;
+        gtod_long_t     monotonic_time_coarse_nsec;
-        struct timezone sys_tz;
+        int             tz_minuteswest;
-        struct timespec wall_time_coarse;
+        int             tz_dsttime;
-        struct timespec monotonic_time_coarse;
 };
 extern struct vsyscall_gtod_data vsyscall_gtod_data;
+static inline unsigned gtod_read_begin(const struct vsyscall_gtod_data *s)
+{
+        unsigned ret;
+repeat:
+        ret = ACCESS_ONCE(s->seq);
+        if (unlikely(ret & 1)) {
+                cpu_relax();
+                goto repeat;
+        }
+        smp_rmb();
+        return ret;
+}
+static inline int gtod_read_retry(const struct vsyscall_gtod_data *s,
+                                        unsigned start)
+{
+        smp_rmb();
+        return unlikely(s->seq != start);
+}
+static inline void gtod_write_begin(struct vsyscall_gtod_data *s)
+{
+        ++s->seq;
+        smp_wmb();
+}
+static inline void gtod_write_end(struct vsyscall_gtod_data *s)
+{
+        smp_wmb();
+        ++s->seq;
+}
 #endif /* _ASM_X86_VGTOD_H */
diff --git a/arch/x86/include/asm/visws/cobalt.h b/arch/x86/include/asm/visws/cobalt.h
deleted file mode 100644
index 2edb37637ead..000000000000
--- a/arch/x86/include/asm/visws/cobalt.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef _ASM_X86_VISWS_COBALT_H
-#define _ASM_X86_VISWS_COBALT_H
-#include <asm/fixmap.h>
-/*
- * Cobalt SGI Visual Workstation system ASIC
- */ 
-#define CO_CPU_NUM_PHYS 0x1e00
-#define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2)
-#define CO_CPU_MAX 4
-#define CO_CPU_PHYS             0xc2000000
-#define CO_APIC_PHYS            0xc4000000
-/* see set_fixmap() and asm/fixmap.h */
-#define CO_CPU_VADDR            (fix_to_virt(FIX_CO_CPU))
-#define CO_APIC_VADDR           (fix_to_virt(FIX_CO_APIC))
-/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */
-#define CO_CPU_REV              0x08
-#define CO_CPU_CTRL             0x10
-#define CO_CPU_STAT             0x20
-#define CO_CPU_TIMEVAL          0x30
-/* CO_CPU_CTRL bits */
-#define CO_CTRL_TIMERUN         0x04            /* 0 == disabled */
-#define CO_CTRL_TIMEMASK        0x08            /* 0 == unmasked */
-/* CO_CPU_STATUS bits */
-#define CO_STAT_TIMEINTR        0x02    /* (r) 1 == int pend, (w) 0 == clear */
-/* CO_CPU_TIMEVAL value */
-#define CO_TIME_HZ              100000000       /* Cobalt core rate */
-/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */
-#define CO_APIC_HI(n)           (((n) * 0x10) + 4)
-#define CO_APIC_LO(n)           ((n) * 0x10)
-#define CO_APIC_ID              0x0ffc
-/* CO_APIC_ID bits */
-#define CO_APIC_ENABLE          0x00000100
-/* CO_APIC_LO bits */
-#define CO_APIC_MASK            0x00010000      /* 0 = enabled */
-#define CO_APIC_LEVEL           0x00008000      /* 0 = edge */
-/*
- * Where things are physically wired to Cobalt
- * #defines with no board _<type>_<rev>_ are common to all (thus far)
- */
-#define CO_APIC_IDE0            4
-#define CO_APIC_IDE1            2               /* Only on 320 */
-#define CO_APIC_8259            12              /* serial, floppy, par-l-l */
-/* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */
-#define CO_APIC_PCIA_BASE0      0 /* and 1 */   /* slot 0, line 0 */
-#define CO_APIC_PCIA_BASE123    5 /* and 6 */   /* slot 0, line 1 */
-#define CO_APIC_PIIX4_USB       7               /* this one is weird */
-/* Lithium PCI Bridge B -- "the one with PIIX4" */
-#define CO_APIC_PCIB_BASE0      8 /* and 9-12 *//* slot 0, line 0 */
-#define CO_APIC_PCIB_BASE123    13 /* 14.15 */  /* slot 0, line 1 */
-#define CO_APIC_VIDOUT0         16
-#define CO_APIC_VIDOUT1         17
-#define CO_APIC_VIDIN0          18
-#define CO_APIC_VIDIN1          19
-#define CO_APIC_LI_AUDIO        22
-#define CO_APIC_AS              24
-#define CO_APIC_RE              25
-#define CO_APIC_CPU             28              /* Timer and Cache interrupt */
-#define CO_APIC_NMI             29
-#define CO_APIC_LAST            CO_APIC_NMI
-/*
- * This is how irqs are assigned on the Visual Workstation.
- * Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU).
- * All other devices (including PCI) go to Cobalt and are irq's 16 on up.
- */
-#define CO_IRQ_APIC0    16                      /* irq of apic entry 0 */
-#define IS_CO_APIC(irq) ((irq) >= CO_IRQ_APIC0)
-#define CO_IRQ(apic)    (CO_IRQ_APIC0 + (apic)) /* apic ent to irq */
-#define CO_APIC(irq)    ((irq) - CO_IRQ_APIC0)  /* irq to apic ent */
-#define CO_IRQ_IDE0     14                      /* knowledge of... */
-#define CO_IRQ_IDE1     15                      /* ... ide driver defaults! */
-#define CO_IRQ_8259     CO_IRQ(CO_APIC_8259)
-#ifdef CONFIG_X86_VISWS_APIC
-static inline void co_cpu_write(unsigned long reg, unsigned long v)
-{
-        *((volatile unsigned long *)(CO_CPU_VADDR+reg))=v;
-}
-static inline unsigned long co_cpu_read(unsigned long reg)
-{
-        return *((volatile unsigned long *)(CO_CPU_VADDR+reg));
-}            
-             
-static inline void co_apic_write(unsigned long reg, unsigned long v)
-{
-        *((volatile unsigned long *)(CO_APIC_VADDR+reg))=v;
-}            
-             
-static inline unsigned long co_apic_read(unsigned long reg)
-{
-        return *((volatile unsigned long *)(CO_APIC_VADDR+reg));
-}
-#endif
-extern char visws_board_type;
-#define VISWS_320       0
-#define VISWS_540       1
-extern char visws_board_rev;
-extern int pci_visws_init(void);
-#endif /* _ASM_X86_VISWS_COBALT_H */
diff --git a/arch/x86/include/asm/visws/lithium.h b/arch/x86/include/asm/visws/lithium.h
deleted file mode 100644
index a10d89bc1270..000000000000
--- a/arch/x86/include/asm/visws/lithium.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef _ASM_X86_VISWS_LITHIUM_H
-#define _ASM_X86_VISWS_LITHIUM_H
-#include <asm/fixmap.h>
-/*
- * Lithium is the SGI Visual Workstation I/O ASIC
- */
-#define LI_PCI_A_PHYS           0xfc000000      /* Enet is dev 3 */
-#define LI_PCI_B_PHYS           0xfd000000      /* PIIX4 is here */
-/* see set_fixmap() and asm/fixmap.h */
-#define LI_PCIA_VADDR   (fix_to_virt(FIX_LI_PCIA))
-#define LI_PCIB_VADDR   (fix_to_virt(FIX_LI_PCIB))
-/* Not a standard PCI? (not in linux/pci.h) */
-#define LI_PCI_BUSNUM   0x44                    /* lo8: primary, hi8: sub */
-#define LI_PCI_INTEN    0x46
-/* LI_PCI_INTENT bits */
-#define LI_INTA_0       0x0001
-#define LI_INTA_1       0x0002
-#define LI_INTA_2       0x0004
-#define LI_INTA_3       0x0008
-#define LI_INTA_4       0x0010
-#define LI_INTB         0x0020
-#define LI_INTC         0x0040
-#define LI_INTD         0x0080
-/* More special purpose macros... */
-static inline void li_pcia_write16(unsigned long reg, unsigned short v)
-{
-        *((volatile unsigned short *)(LI_PCIA_VADDR+reg))=v;
-}
-static inline unsigned short li_pcia_read16(unsigned long reg)
-{
-         return *((volatile unsigned short *)(LI_PCIA_VADDR+reg));
-}
-static inline void li_pcib_write16(unsigned long reg, unsigned short v)
-{
-        *((volatile unsigned short *)(LI_PCIB_VADDR+reg))=v;
-}
-static inline unsigned short li_pcib_read16(unsigned long reg)
-{
-        return *((volatile unsigned short *)(LI_PCIB_VADDR+reg));
-}
-#endif /* _ASM_X86_VISWS_LITHIUM_H */
diff --git a/arch/x86/include/asm/visws/piix4.h b/arch/x86/include/asm/visws/piix4.h
deleted file mode 100644
index d0af4d338e7f..000000000000
--- a/arch/x86/include/asm/visws/piix4.h
+++ /dev/null
@@ -1,107 +0,0 @@
-#ifndef _ASM_X86_VISWS_PIIX4_H
-#define _ASM_X86_VISWS_PIIX4_H
-/*
- * PIIX4 as used on SGI Visual Workstations
- */
-#define PIIX_PM_START           0x0F80
-#define SIO_GPIO_START          0x0FC0
-#define SIO_PM_START            0x0FC8
-#define PMBASE                  PIIX_PM_START
-#define GPIREG0                 (PMBASE+0x30)
-#define GPIREG(x)               (GPIREG0+((x)/8))
-#define GPIBIT(x)               (1 << ((x)%8))
-#define PIIX_GPI_BD_ID1         18
-#define PIIX_GPI_BD_ID2         19
-#define PIIX_GPI_BD_ID3         20
-#define PIIX_GPI_BD_ID4         21
-#define PIIX_GPI_BD_REG         GPIREG(PIIX_GPI_BD_ID1)
-#define PIIX_GPI_BD_MASK        (GPIBIT(PIIX_GPI_BD_ID1) | \
-                                GPIBIT(PIIX_GPI_BD_ID2) | \
-                                GPIBIT(PIIX_GPI_BD_ID3) | \
-                                GPIBIT(PIIX_GPI_BD_ID4) )
-#define PIIX_GPI_BD_SHIFT       (PIIX_GPI_BD_ID1 % 8)
-#define SIO_INDEX               0x2e
-#define SIO_DATA                0x2f
-#define SIO_DEV_SEL             0x7
-#define SIO_DEV_ENB             0x30
-#define SIO_DEV_MSB             0x60
-#define SIO_DEV_LSB             0x61
-#define SIO_GP_DEV              0x7
-#define SIO_GP_BASE             SIO_GPIO_START
-#define SIO_GP_MSB              (SIO_GP_BASE>>8)
-#define SIO_GP_LSB              (SIO_GP_BASE&0xff)
-#define SIO_GP_DATA1            (SIO_GP_BASE+0)
-#define SIO_PM_DEV              0x8
-#define SIO_PM_BASE             SIO_PM_START
-#define SIO_PM_MSB              (SIO_PM_BASE>>8)
-#define SIO_PM_LSB              (SIO_PM_BASE&0xff)
-#define SIO_PM_INDEX            (SIO_PM_BASE+0)
-#define SIO_PM_DATA             (SIO_PM_BASE+1)
-#define SIO_PM_FER2             0x1
-#define SIO_PM_GP_EN            0x80
-/*
- * This is the dev/reg where generating a config cycle will
- * result in a PCI special cycle.
- */
-#define SPECIAL_DEV             0xff
-#define SPECIAL_REG             0x00
-/*
- * PIIX4 needs to see a special cycle with the following data
- * to be convinced the processor has gone into the stop grant
- * state.  PIIX4 insists on seeing this before it will power
- * down a system.
- */
-#define PIIX_SPECIAL_STOP               0x00120002
-#define PIIX4_RESET_PORT        0xcf9
-#define PIIX4_RESET_VAL         0x6
-#define PMSTS_PORT              0xf80   // 2 bytes      PM Status
-#define PMEN_PORT               0xf82   // 2 bytes      PM Enable
-#define PMCNTRL_PORT            0xf84   // 2 bytes      PM Control
-#define PM_SUSPEND_ENABLE       0x2000  // start sequence to suspend state
-/*
- * PMSTS and PMEN I/O bit definitions.
- * (Bits are the same in both registers)
- */
-#define PM_STS_RSM              (1<<15) // Resume Status
-#define PM_STS_PWRBTNOR         (1<<11) // Power Button Override
-#define PM_STS_RTC              (1<<10) // RTC status
-#define PM_STS_PWRBTN           (1<<8)  // Power Button Pressed?
-#define PM_STS_GBL              (1<<5)  // Global Status
-#define PM_STS_BM               (1<<4)  // Bus Master Status
-#define PM_STS_TMROF            (1<<0)  // Timer Overflow Status.
-/*
- * Stop clock GPI register
- */
-#define PIIX_GPIREG0                    (0xf80 + 0x30)
-/*
- * Stop clock GPI bit in GPIREG0
- */
-#define PIIX_GPI_STPCLK         0x4     // STPCLK signal routed back in
-#endif /* _ASM_X86_VISWS_PIIX4_H */
diff --git a/arch/x86/include/asm/visws/sgivw.h b/arch/x86/include/asm/visws/sgivw.h
deleted file mode 100644
index 5fbf63e1003c..000000000000
--- a/arch/x86/include/asm/visws/sgivw.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * Frame buffer position and size:
- */
-extern unsigned long sgivwfb_mem_phys;
-extern unsigned long sgivwfb_mem_size;
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 2067264fb7f5..7004d21e6219 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -85,6 +85,7 @@
 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
+#define VM_EXIT_CLEAR_BNDCFGS                   0x00800000
 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR       0x00036dff
@@ -95,6 +96,7 @@
 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
+#define VM_ENTRY_LOAD_BNDCFGS                   0x00010000
 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR      0x000011ff
@@ -174,6 +176,8 @@ enum vmcs_field {
        GUEST_PDPTR2_HIGH               = 0x0000280f,
        GUEST_PDPTR3                    = 0x00002810,
        GUEST_PDPTR3_HIGH               = 0x00002811,
+        GUEST_BNDCFGS                   = 0x00002812,
+        GUEST_BNDCFGS_HIGH              = 0x00002813,
        HOST_IA32_PAT                   = 0x00002c00,
        HOST_IA32_PAT_HIGH              = 0x00002c01,
        HOST_IA32_EFER                  = 0x00002c02,
diff --git a/arch/x86/include/asm/vvar.h b/arch/x86/include/asm/vvar.h
index d76ac40da206..081d909bc495 100644
--- a/arch/x86/include/asm/vvar.h
+++ b/arch/x86/include/asm/vvar.h
@@ -16,8 +16,8 @@
 * you mess up, the linker will catch it.)
 */
-/* Base address of vvars.  This is not ABI. */
+#ifndef _ASM_X86_VVAR_H
-#define VVAR_ADDRESS (-10*1024*1024 - 4096)
+#define _ASM_X86_VVAR_H
 #if defined(__VVAR_KERNEL_LDS)
@@ -29,16 +29,35 @@
 #else
+#ifdef BUILD_VDSO32
+#define DECLARE_VVAR(offset, type, name)                                \
+        extern type vvar_ ## name __attribute__((visibility("hidden")));
+#define VVAR(name) (vvar_ ## name)
+#else
+extern char __vvar_page;
+/* Base address of vvars.  This is not ABI. */
+#ifdef CONFIG_X86_64
+#define VVAR_ADDRESS (-10*1024*1024 - 4096)
+#else
+#define VVAR_ADDRESS (&__vvar_page)
+#endif
 #define DECLARE_VVAR(offset, type, name)                                \
        static type const * const vvaraddr_ ## name =                   \
                (void *)(VVAR_ADDRESS + (offset));
+#define VVAR(name) (*vvaraddr_ ## name)
+#endif
 #define DEFINE_VVAR(type, name)                                         \
        type name                                                       \
        __attribute__((section(".vvar_" #name), aligned(16))) __visible
-#define VVAR(name) (*vvaraddr_ ## name)
 #endif
 /* DECLARE_VVAR(offset, type, name) */
@@ -48,3 +67,5 @@ DECLARE_VVAR(16, int, vgetcpu_mode)
 DECLARE_VVAR(128, struct vsyscall_gtod_data, vsyscall_gtod_data)
 #undef DECLARE_VVAR
+#endif
diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h
index 3e276eb23d1b..c949923a5668 100644
--- a/arch/x86/include/asm/xen/page.h
+++ b/arch/x86/include/asm/xen/page.h
@@ -49,10 +49,17 @@ extern bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn);
 extern unsigned long set_phys_range_identity(unsigned long pfn_s,
                                             unsigned long pfn_e);
+extern int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops,
+                                   struct gnttab_map_grant_ref *kmap_ops,
+                                   struct page **pages, unsigned int count);
 extern int m2p_add_override(unsigned long mfn, struct page *page,
                            struct gnttab_map_grant_ref *kmap_op);
+extern int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops,
+                                     struct gnttab_map_grant_ref *kmap_ops,
+                                     struct page **pages, unsigned int count);
 extern int m2p_remove_override(struct page *page,
-                                struct gnttab_map_grant_ref *kmap_op);
+                               struct gnttab_map_grant_ref *kmap_op,
+                               unsigned long mfn);
 extern struct page *m2p_find_override(unsigned long mfn);
 extern unsigned long m2p_find_override_pfn(unsigned long mfn, unsigned long pfn);
@@ -121,7 +128,7 @@ static inline unsigned long mfn_to_pfn(unsigned long mfn)
                pfn = m2p_find_override_pfn(mfn, ~0);
        }
-        /* 
+        /*
         * pfn is ~0 if there are no entries in the m2p for mfn or if the
         * entry doesn't map back to the mfn and m2p_override doesn't have a
         * valid entry for it.
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 6c1d7411eb00..d949ef28c48b 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -16,6 +16,8 @@
 #define XSTATE_Hi16_ZMM         0x80
 #define XSTATE_FPSSE    (XSTATE_FP | XSTATE_SSE)
+/* Bit 63 of XCR0 is reserved for future expansion */
+#define XSTATE_EXTEND_MASK      (~(XSTATE_FPSSE | (1ULL << 63)))
 #define FXSAVE_SIZE     512
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 4924f4be2b99..c827ace3121b 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -295,6 +295,7 @@
 #define MSR_SMI_COUNT                   0x00000034
 #define MSR_IA32_FEATURE_CONTROL        0x0000003a
 #define MSR_IA32_TSC_ADJUST             0x0000003b
+#define MSR_IA32_BNDCFGS                0x00000d90
 #define FEATURE_CONTROL_LOCKED                          (1<<0)
 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX        (1<<1)
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index cb648c84b327..f4d96000d33a 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_IRQ_WORK)  += irq_work.o
 obj-y                   += probe_roms.o
 obj-$(CONFIG_X86_32)    += i386_ksyms_32.o
 obj-$(CONFIG_X86_64)    += sys_x86_64.o x8664_ksyms_64.o
-obj-y                   += syscall_$(BITS).o
+obj-y                   += syscall_$(BITS).o vsyscall_gtod.o
 obj-$(CONFIG_X86_64)    += vsyscall_64.o
 obj-$(CONFIG_X86_64)    += vsyscall_emu_64.o
 obj-$(CONFIG_SYSFS)     += ksysfs.o
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 9f46f2b1cfc2..86281ffb96d6 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -53,10 +53,6 @@ EXPORT_SYMBOL(acpi_disabled);
 # include <asm/proto.h>
 #endif                          /* X86 */
-#define BAD_MADT_ENTRY(entry, end) (                                        \
-                (!entry) || (unsigned long)entry + sizeof(*entry) > end ||  \
-                ((struct acpi_subtable_header *)entry)->length < sizeof(*entry))
 #define PREFIX                  "ACPI: "
 int acpi_noirq;                         /* skip ACPI IRQ initialization */
@@ -907,10 +903,6 @@ static int __init acpi_parse_madt_lapic_entries(void)
 #ifdef  CONFIG_X86_IO_APIC
 #define MP_ISA_BUS              0
-#ifdef CONFIG_X86_ES7000
-extern int es7000_plat;
-#endif
 void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
 {
        int ioapic;
@@ -960,14 +952,6 @@ void __init mp_config_acpi_legacy_irqs(void)
        set_bit(MP_ISA_BUS, mp_bus_not_pci);
        pr_debug("Bus #%d is ISA\n", MP_ISA_BUS);
-#ifdef CONFIG_X86_ES7000
-        /*
-         * Older generations of ES7000 have no legacy identity mappings
-         */
-        if (es7000_plat == 1)
-                return;
-#endif
        /*
         * Use the default configuration for the IRQs 0-15.  Unless
         * overridden by (MADT) interrupt source override entries.
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index e69182fd01cf..4b28159e0421 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -87,7 +87,9 @@ static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
        num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
        retval = 0;
-        if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
+        /* If the HW does not support any sub-states in this C-state */
+        if (num_cstate_subtype == 0) {
+                pr_warn(FW_BUG "ACPI MWAIT C-state 0x%x not supported by HW (0x%x)\n", cx->address, edx_part);
                retval = -1;
                goto out;
        }
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index dec8de4e1663..f04dbb3069b8 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -22,6 +22,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
        {}
 };
 EXPORT_SYMBOL(amd_nb_misc_ids);
@@ -30,6 +31,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
        {}
 };
diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile
index 0ae0323b1f9c..dcb5b15401ce 100644
--- a/arch/x86/kernel/apic/Makefile
+++ b/arch/x86/kernel/apic/Makefile
@@ -18,10 +18,7 @@ obj-y				+= apic_flat_64.o
 endif
 # APIC probe will depend on the listing order here
-obj-$(CONFIG_X86_NUMAQ)         += numaq_32.o
-obj-$(CONFIG_X86_SUMMIT)        += summit_32.o
 obj-$(CONFIG_X86_BIGSMP)        += bigsmp_32.o
-obj-$(CONFIG_X86_ES7000)        += es7000_32.o
 # For 32bit, probe_32 need to be listed last
 obj-$(CONFIG_X86_LOCAL_APIC)    += probe_$(BITS).o
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 53e20531470e..ad28db7e6bde 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1996,7 +1996,8 @@ static inline void __smp_error_interrupt(struct pt_regs *regs)
        };
        /* First tickle the hardware, only then report what went on. -- REW */
-        apic_write(APIC_ESR, 0);
+        if (lapic_get_maxlvt() > 3)     /* Due to the Pentium erratum 3AP. */
+                apic_write(APIC_ESR, 0);
        v = apic_read(APIC_ESR);
        ack_APIC_irq();
        atomic_inc(&irq_err_count);
@@ -2136,7 +2137,6 @@ int generic_processor_info(int apicid, int version)
         *
         * - arch/x86/kernel/mpparse.c: MP_processor_info()
         * - arch/x86/mm/amdtopology.c: amd_numa_init()
-         * - arch/x86/platform/visws/visws_quirks.c: MP_processor_info()
         *
         * This function is executed with the modified
         * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
deleted file mode 100644
index 6f8f8b348a39..000000000000
--- a/arch/x86/kernel/apic/es7000_32.c
+++ /dev/null
@@ -1,738 +0,0 @@
-/*
- * Written by: Garry Forsgren, Unisys Corporation
- *             Natalie Protasevich, Unisys Corporation
- *
- * This file contains the code to configure and interface
- * with Unisys ES7000 series hardware system manager.
- *
- * Copyright (c) 2003 Unisys Corporation.
- * Copyright (C) 2009, Red Hat, Inc., Ingo Molnar
- *
- *   All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it would be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Contact information: Unisys Corporation, Township Line & Union Meeting
- * Roads-A, Unisys Way, Blue Bell, Pennsylvania, 19424, or:
- *
- * http://www.unisys.com
- */
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-#include <linux/notifier.h>
-#include <linux/spinlock.h>
-#include <linux/cpumask.h>
-#include <linux/threads.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/reboot.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/acpi.h>
-#include <linux/init.h>
-#include <linux/gfp.h>
-#include <linux/nmi.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-#include <asm/apicdef.h>
-#include <linux/atomic.h>
-#include <asm/fixmap.h>
-#include <asm/mpspec.h>
-#include <asm/setup.h>
-#include <asm/apic.h>
-#include <asm/ipi.h>
-/*
- * ES7000 chipsets
- */
-#define NON_UNISYS                      0
-#define ES7000_CLASSIC                  1
-#define ES7000_ZORRO                    2
-#define MIP_REG                         1
-#define MIP_PSAI_REG                    4
-#define MIP_BUSY                        1
-#define MIP_SPIN                        0xf0000
-#define MIP_VALID                       0x0100000000000000ULL
-#define MIP_SW_APIC                     0x1020b
-#define MIP_PORT(val)                   ((val >> 32) & 0xffff)
-#define MIP_RD_LO(val)                  (val & 0xffffffff)
-struct mip_reg {
-        unsigned long long              off_0x00;
-        unsigned long long              off_0x08;
-        unsigned long long              off_0x10;
-        unsigned long long              off_0x18;
-        unsigned long long              off_0x20;
-        unsigned long long              off_0x28;
-        unsigned long long              off_0x30;
-        unsigned long long              off_0x38;
-};
-struct mip_reg_info {
-        unsigned long long              mip_info;
-        unsigned long long              delivery_info;
-        unsigned long long              host_reg;
-        unsigned long long              mip_reg;
-};
-struct psai {
-        unsigned long long              entry_type;
-        unsigned long long              addr;
-        unsigned long long              bep_addr;
-};
-#ifdef CONFIG_ACPI
-struct es7000_oem_table {
-        struct acpi_table_header        Header;
-        u32                             OEMTableAddr;
-        u32                             OEMTableSize;
-};
-static unsigned long                    oem_addrX;
-static unsigned long                    oem_size;
-#endif
-/*
- * ES7000 Globals
- */
-static volatile unsigned long           *psai;
-static struct mip_reg                   *mip_reg;
-static struct mip_reg                   *host_reg;
-static int                              mip_port;
-static unsigned long                    mip_addr;
-static unsigned long                    host_addr;
-int                                     es7000_plat;
-/*
- * GSI override for ES7000 platforms.
- */
-static int wakeup_secondary_cpu_via_mip(int cpu, unsigned long eip)
-{
-        unsigned long vect = 0, psaival = 0;
-        if (psai == NULL)
-                return -1;
-        vect = ((unsigned long)__pa(eip)/0x1000) << 16;
-        psaival = (0x1000000 | vect | cpu);
-        while (*psai & 0x1000000)
-                ;
-        *psai = psaival;
-        return 0;
-}
-static int es7000_apic_is_cluster(void)
-{
-        /* MPENTIUMIII */
-        if (boot_cpu_data.x86 == 6 &&
-            (boot_cpu_data.x86_model >= 7 && boot_cpu_data.x86_model <= 11))
-                return 1;
-        return 0;
-}
-static void setup_unisys(void)
-{
-        /*
-         * Determine the generation of the ES7000 currently running.
-         *
-         * es7000_plat = 1 if the machine is a 5xx ES7000 box
-         * es7000_plat = 2 if the machine is a x86_64 ES7000 box
-         *
-         */
-        if (!(boot_cpu_data.x86 <= 15 && boot_cpu_data.x86_model <= 2))
-                es7000_plat = ES7000_ZORRO;
-        else
-                es7000_plat = ES7000_CLASSIC;
-}
-/*
- * Parse the OEM Table:
- */
-static int parse_unisys_oem(char *oemptr)
-{
-        int                     i;
-        int                     success = 0;
-        unsigned char           type, size;
-        unsigned long           val;
-        char                    *tp = NULL;
-        struct psai             *psaip = NULL;
-        struct mip_reg_info     *mi;
-        struct mip_reg          *host, *mip;
-        tp = oemptr;
-        tp += 8;
-        for (i = 0; i <= 6; i++) {
-                type = *tp++;
-                size = *tp++;
-                tp -= 2;
-                switch (type) {
-                case MIP_REG:
-                        mi = (struct mip_reg_info *)tp;
-                        val = MIP_RD_LO(mi->host_reg);
-                        host_addr = val;
-                        host = (struct mip_reg *)val;
-                        host_reg = __va(host);
-                        val = MIP_RD_LO(mi->mip_reg);
-                        mip_port = MIP_PORT(mi->mip_info);
-                        mip_addr = val;
-                        mip = (struct mip_reg *)val;
-                        mip_reg = __va(mip);
-                        pr_debug("host_reg = 0x%lx\n",
-                                 (unsigned long)host_reg);
-                        pr_debug("mip_reg = 0x%lx\n",
-                                 (unsigned long)mip_reg);
-                        success++;
-                        break;
-                case MIP_PSAI_REG:
-                        psaip = (struct psai *)tp;
-                        if (tp != NULL) {
-                                if (psaip->addr)
-                                        psai = __va(psaip->addr);
-                                else
-                                        psai = NULL;
-                                success++;
-                        }
-                        break;
-                default:
-                        break;
-                }
-                tp += size;
-        }
-        if (success < 2)
-                es7000_plat = NON_UNISYS;
-        else
-                setup_unisys();
-        return es7000_plat;
-}
-#ifdef CONFIG_ACPI
-static int __init find_unisys_acpi_oem_table(unsigned long *oem_addr)
-{
-        struct acpi_table_header *header = NULL;
-        struct es7000_oem_table *table;
-        acpi_size tbl_size;
-        acpi_status ret;
-        int i = 0;
-        for (;;) {
-                ret = acpi_get_table_with_size("OEM1", i++, &header, &tbl_size);
-                if (!ACPI_SUCCESS(ret))
-                        return -1;
-                if (!memcmp((char *) &header->oem_id, "UNISYS", 6))
-                        break;
-                early_acpi_os_unmap_memory(header, tbl_size);
-        }
-        table = (void *)header;
-        oem_addrX       = table->OEMTableAddr;
-        oem_size        = table->OEMTableSize;
-        early_acpi_os_unmap_memory(header, tbl_size);
-        *oem_addr       = (unsigned long)__acpi_map_table(oem_addrX, oem_size);
-        return 0;
-}
-static void __init unmap_unisys_acpi_oem_table(unsigned long oem_addr)
-{
-        if (!oem_addr)
-                return;
-        __acpi_unmap_table((char *)oem_addr, oem_size);
-}
-static int es7000_check_dsdt(void)
-{
-        struct acpi_table_header header;
-        if (ACPI_SUCCESS(acpi_get_table_header(ACPI_SIG_DSDT, 0, &header)) &&
-            !strncmp(header.oem_id, "UNISYS", 6))
-                return 1;
-        return 0;
-}
-static int es7000_acpi_ret;
-/* Hook from generic ACPI tables.c */
-static int __init es7000_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
-{
-        unsigned long oem_addr = 0;
-        int check_dsdt;
-        int ret = 0;
-        /* check dsdt at first to avoid clear fix_map for oem_addr */
-        check_dsdt = es7000_check_dsdt();
-        if (!find_unisys_acpi_oem_table(&oem_addr)) {
-                if (check_dsdt) {
-                        ret = parse_unisys_oem((char *)oem_addr);
-                } else {
-                        setup_unisys();
-                        ret = 1;
-                }
-                /*
-                 * we need to unmap it
-                 */
-                unmap_unisys_acpi_oem_table(oem_addr);
-        }
-        es7000_acpi_ret = ret;
-        return ret && !es7000_apic_is_cluster();
-}
-static int es7000_acpi_madt_oem_check_cluster(char *oem_id, char *oem_table_id)
-{
-        int ret = es7000_acpi_ret;
-        return ret && es7000_apic_is_cluster();
-}
-#else /* !CONFIG_ACPI: */
-static int es7000_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
-{
-        return 0;
-}
-static int es7000_acpi_madt_oem_check_cluster(char *oem_id, char *oem_table_id)
-{
-        return 0;
-}
-#endif /* !CONFIG_ACPI */
-static void es7000_spin(int n)
-{
-        int i = 0;
-        while (i++ < n)
-                rep_nop();
-}
-static int es7000_mip_write(struct mip_reg *mip_reg)
-{
-        int status = 0;
-        int spin;
-        spin = MIP_SPIN;
-        while ((host_reg->off_0x38 & MIP_VALID) != 0) {
-                if (--spin <= 0) {
-                        WARN(1, "Timeout waiting for Host Valid Flag\n");
-                        return -1;
-                }
-                es7000_spin(MIP_SPIN);
-        }
-        memcpy(host_reg, mip_reg, sizeof(struct mip_reg));
-        outb(1, mip_port);
-        spin = MIP_SPIN;
-        while ((mip_reg->off_0x38 & MIP_VALID) == 0) {
-                if (--spin <= 0) {
-                        WARN(1, "Timeout waiting for MIP Valid Flag\n");
-                        return -1;
-                }
-                es7000_spin(MIP_SPIN);
-        }
-        status = (mip_reg->off_0x00 & 0xffff0000000000ULL) >> 48;
-        mip_reg->off_0x38 &= ~MIP_VALID;
-        return status;
-}
-static void es7000_enable_apic_mode(void)
-{
-        struct mip_reg es7000_mip_reg;
-        int mip_status;
-        if (!es7000_plat)
-                return;
-        pr_info("Enabling APIC mode.\n");
-        memset(&es7000_mip_reg, 0, sizeof(struct mip_reg));
-        es7000_mip_reg.off_0x00 = MIP_SW_APIC;
-        es7000_mip_reg.off_0x38 = MIP_VALID;
-        while ((mip_status = es7000_mip_write(&es7000_mip_reg)) != 0)
-                WARN(1, "Command failed, status = %x\n", mip_status);
-}
-static unsigned int es7000_get_apic_id(unsigned long x)
-{
-        return (x >> 24) & 0xFF;
-}
-static void es7000_send_IPI_mask(const struct cpumask *mask, int vector)
-{
-        default_send_IPI_mask_sequence_phys(mask, vector);
-}
-static void es7000_send_IPI_allbutself(int vector)
-{
-        default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
-}
-static void es7000_send_IPI_all(int vector)
-{
-        es7000_send_IPI_mask(cpu_online_mask, vector);
-}
-static int es7000_apic_id_registered(void)
-{
-        return 1;
-}
-static const struct cpumask *target_cpus_cluster(void)
-{
-        return cpu_all_mask;
-}
-static const struct cpumask *es7000_target_cpus(void)
-{
-        return cpumask_of(smp_processor_id());
-}
-static unsigned long es7000_check_apicid_used(physid_mask_t *map, int apicid)
-{
-        return 0;
-}
-static unsigned long es7000_check_apicid_present(int bit)
-{
-        return physid_isset(bit, phys_cpu_present_map);
-}
-static int es7000_early_logical_apicid(int cpu)
-{
-        /* on es7000, logical apicid is the same as physical */
-        return early_per_cpu(x86_bios_cpu_apicid, cpu);
-}
-static unsigned long calculate_ldr(int cpu)
-{
-        unsigned long id = per_cpu(x86_bios_cpu_apicid, cpu);
-        return SET_APIC_LOGICAL_ID(id);
-}
-/*
- * Set up the logical destination ID.
- *
- * Intel recommends to set DFR, LdR and TPR before enabling
- * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
- * document number 292116).  So here it goes...
- */
-static void es7000_init_apic_ldr_cluster(void)
-{
-        unsigned long val;
-        int cpu = smp_processor_id();
-        apic_write(APIC_DFR, APIC_DFR_CLUSTER);
-        val = calculate_ldr(cpu);
-        apic_write(APIC_LDR, val);
-}
-static void es7000_init_apic_ldr(void)
-{
-        unsigned long val;
-        int cpu = smp_processor_id();
-        apic_write(APIC_DFR, APIC_DFR_FLAT);
-        val = calculate_ldr(cpu);
-        apic_write(APIC_LDR, val);
-}
-static void es7000_setup_apic_routing(void)
-{
-        int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
-        pr_info("Enabling APIC mode:  %s. Using %d I/O APICs, target cpus %lx\n",
-                (apic_version[apic] == 0x14) ?
-                        "Physical Cluster" : "Logical Cluster",
-                nr_ioapics, cpumask_bits(es7000_target_cpus())[0]);
-}
-static int es7000_cpu_present_to_apicid(int mps_cpu)
-{
-        if (!mps_cpu)
-                return boot_cpu_physical_apicid;
-        else if (mps_cpu < nr_cpu_ids)
-                return per_cpu(x86_bios_cpu_apicid, mps_cpu);
-        else
-                return BAD_APICID;
-}
-static int cpu_id;
-static void es7000_apicid_to_cpu_present(int phys_apicid, physid_mask_t *retmap)
-{
-        physid_set_mask_of_physid(cpu_id, retmap);
-        ++cpu_id;
-}
-static void es7000_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
-{
-        /* For clustered we don't have a good way to do this yet - hack */
-        physids_promote(0xFFL, retmap);
-}
-static int es7000_check_phys_apicid_present(int cpu_physical_apicid)
-{
-        boot_cpu_physical_apicid = read_apic_id();
-        return 1;
-}
-static inline int
-es7000_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id)
-{
-        unsigned int round = 0;
-        unsigned int cpu, uninitialized_var(apicid);
-        /*
-         * The cpus in the mask must all be on the apic cluster.
-         */
-        for_each_cpu_and(cpu, cpumask, cpu_online_mask) {
-                int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
-                if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
-                        WARN(1, "Not a valid mask!");
-                        return -EINVAL;
-                }
-                apicid |= new_apicid;
-                round++;
-        }
-        if (!round)
-                return -EINVAL;
-        *dest_id = apicid;
-        return 0;
-}
-static int
-es7000_cpu_mask_to_apicid_and(const struct cpumask *inmask,
-                              const struct cpumask *andmask,
-                              unsigned int *apicid)
-{
-        cpumask_var_t cpumask;
-        *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
-        if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
-                return 0;
-        cpumask_and(cpumask, inmask, andmask);
-        es7000_cpu_mask_to_apicid(cpumask, apicid);
-        free_cpumask_var(cpumask);
-        return 0;
-}
-static int es7000_phys_pkg_id(int cpuid_apic, int index_msb)
-{
-        return cpuid_apic >> index_msb;
-}
-static int probe_es7000(void)
-{
-        /* probed later in mptable/ACPI hooks */
-        return 0;
-}
-static int es7000_mps_ret;
-static int es7000_mps_oem_check(struct mpc_table *mpc, char *oem,
-                char *productid)
-{
-        int ret = 0;
-        if (mpc->oemptr) {
-                struct mpc_oemtable *oem_table =
-                        (struct mpc_oemtable *)mpc->oemptr;
-                if (!strncmp(oem, "UNISYS", 6))
-                        ret = parse_unisys_oem((char *)oem_table);
-        }
-        es7000_mps_ret = ret;
-        return ret && !es7000_apic_is_cluster();
-}
-static int es7000_mps_oem_check_cluster(struct mpc_table *mpc, char *oem,
-                char *productid)
-{
-        int ret = es7000_mps_ret;
-        return ret && es7000_apic_is_cluster();
-}
-/* We've been warned by a false positive warning.Use __refdata to keep calm. */
-static struct apic __refdata apic_es7000_cluster = {
-        .name                           = "es7000",
-        .probe                          = probe_es7000,
-        .acpi_madt_oem_check            = es7000_acpi_madt_oem_check_cluster,
-        .apic_id_valid                  = default_apic_id_valid,
-        .apic_id_registered             = es7000_apic_id_registered,
-        .irq_delivery_mode              = dest_LowestPrio,
-        /* logical delivery broadcast to all procs: */
-        .irq_dest_mode                  = 1,
-        .target_cpus                    = target_cpus_cluster,
-        .disable_esr                    = 1,
-        .dest_logical                   = 0,
-        .check_apicid_used              = es7000_check_apicid_used,
-        .check_apicid_present           = es7000_check_apicid_present,
-        .vector_allocation_domain       = flat_vector_allocation_domain,
-        .init_apic_ldr                  = es7000_init_apic_ldr_cluster,
-        .ioapic_phys_id_map             = es7000_ioapic_phys_id_map,
-        .setup_apic_routing             = es7000_setup_apic_routing,
-        .multi_timer_check              = NULL,
-        .cpu_present_to_apicid          = es7000_cpu_present_to_apicid,
-        .apicid_to_cpu_present          = es7000_apicid_to_cpu_present,
-        .setup_portio_remap             = NULL,
-        .check_phys_apicid_present      = es7000_check_phys_apicid_present,
-        .enable_apic_mode               = es7000_enable_apic_mode,
-        .phys_pkg_id                    = es7000_phys_pkg_id,
-        .mps_oem_check                  = es7000_mps_oem_check_cluster,
-        .get_apic_id                    = es7000_get_apic_id,
-        .set_apic_id                    = NULL,
-        .apic_id_mask                   = 0xFF << 24,
-        .cpu_mask_to_apicid_and         = es7000_cpu_mask_to_apicid_and,
-        .send_IPI_mask                  = es7000_send_IPI_mask,
-        .send_IPI_mask_allbutself       = NULL,
-        .send_IPI_allbutself            = es7000_send_IPI_allbutself,
-        .send_IPI_all                   = es7000_send_IPI_all,
-        .send_IPI_self                  = default_send_IPI_self,
-        .wakeup_secondary_cpu           = wakeup_secondary_cpu_via_mip,
-        .trampoline_phys_low            = 0x467,
-        .trampoline_phys_high           = 0x469,
-        .wait_for_init_deassert         = false,
-        /* Nothing to do for most platforms, since cleared by the INIT cycle: */
-        .smp_callin_clear_local_apic    = NULL,
-        .inquire_remote_apic            = default_inquire_remote_apic,
-        .read                           = native_apic_mem_read,
-        .write                          = native_apic_mem_write,
-        .eoi_write                      = native_apic_mem_write,
-        .icr_read                       = native_apic_icr_read,
-        .icr_write                      = native_apic_icr_write,
-        .wait_icr_idle                  = native_apic_wait_icr_idle,
-        .safe_wait_icr_idle             = native_safe_apic_wait_icr_idle,
-        .x86_32_early_logical_apicid    = es7000_early_logical_apicid,
-};
-static struct apic __refdata apic_es7000 = {
-        .name                           = "es7000",
-        .probe                          = probe_es7000,
-        .acpi_madt_oem_check            = es7000_acpi_madt_oem_check,
-        .apic_id_valid                  = default_apic_id_valid,
-        .apic_id_registered             = es7000_apic_id_registered,
-        .irq_delivery_mode              = dest_Fixed,
-        /* phys delivery to target CPUs: */
-        .irq_dest_mode                  = 0,
-        .target_cpus                    = es7000_target_cpus,
-        .disable_esr                    = 1,
-        .dest_logical                   = 0,
-        .check_apicid_used              = es7000_check_apicid_used,
-        .check_apicid_present           = es7000_check_apicid_present,
-        .vector_allocation_domain       = flat_vector_allocation_domain,
-        .init_apic_ldr                  = es7000_init_apic_ldr,
-        .ioapic_phys_id_map             = es7000_ioapic_phys_id_map,
-        .setup_apic_routing             = es7000_setup_apic_routing,
-        .multi_timer_check              = NULL,
-        .cpu_present_to_apicid          = es7000_cpu_present_to_apicid,
-        .apicid_to_cpu_present          = es7000_apicid_to_cpu_present,
-        .setup_portio_remap             = NULL,
-        .check_phys_apicid_present      = es7000_check_phys_apicid_present,
-        .enable_apic_mode               = es7000_enable_apic_mode,
-        .phys_pkg_id                    = es7000_phys_pkg_id,
-        .mps_oem_check                  = es7000_mps_oem_check,
-        .get_apic_id                    = es7000_get_apic_id,
-        .set_apic_id                    = NULL,
-        .apic_id_mask                   = 0xFF << 24,
-        .cpu_mask_to_apicid_and         = es7000_cpu_mask_to_apicid_and,
-        .send_IPI_mask                  = es7000_send_IPI_mask,
-        .send_IPI_mask_allbutself       = NULL,
-        .send_IPI_allbutself            = es7000_send_IPI_allbutself,
-        .send_IPI_all                   = es7000_send_IPI_all,
-        .send_IPI_self                  = default_send_IPI_self,
-        .trampoline_phys_low            = 0x467,
-        .trampoline_phys_high           = 0x469,
-        .wait_for_init_deassert         = true,
-        /* Nothing to do for most platforms, since cleared by the INIT cycle: */
-        .smp_callin_clear_local_apic    = NULL,
-        .inquire_remote_apic            = default_inquire_remote_apic,
-        .read                           = native_apic_mem_read,
-        .write                          = native_apic_mem_write,
-        .eoi_write                      = native_apic_mem_write,
-        .icr_read                       = native_apic_icr_read,
-        .icr_write                      = native_apic_icr_write,
-        .wait_icr_idle                  = native_apic_wait_icr_idle,
-        .safe_wait_icr_idle             = native_safe_apic_wait_icr_idle,
-        .x86_32_early_logical_apicid    = es7000_early_logical_apicid,
-};
-/*
- * Need to check for es7000 followed by es7000_cluster, so this order
- * in apic_drivers is important.
- */
-apic_drivers(apic_es7000, apic_es7000_cluster);
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c
deleted file mode 100644
index 030ea1c04f72..000000000000
--- a/arch/x86/kernel/apic/numaq_32.c
+++ /dev/null
@@ -1,524 +0,0 @@
-/*
- * Written by: Patricia Gaughen, IBM Corporation
- *
- * Copyright (C) 2002, IBM Corp.
- * Copyright (C) 2009, Red Hat, Inc., Ingo Molnar
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Send feedback to <gone@us.ibm.com>
- */
-#include <linux/nodemask.h>
-#include <linux/topology.h>
-#include <linux/bootmem.h>
-#include <linux/memblock.h>
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <linux/kernel.h>
-#include <linux/mmzone.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/init.h>
-#include <linux/numa.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-#include <linux/mm.h>
-#include <asm/processor.h>
-#include <asm/fixmap.h>
-#include <asm/mpspec.h>
-#include <asm/numaq.h>
-#include <asm/setup.h>
-#include <asm/apic.h>
-#include <asm/e820.h>
-#include <asm/ipi.h>
-int found_numaq;
-/*
- * Have to match translation table entries to main table entries by counter
- * hence the mpc_record variable .... can't see a less disgusting way of
- * doing this ....
- */
-struct mpc_trans {
-        unsigned char                   mpc_type;
-        unsigned char                   trans_len;
-        unsigned char                   trans_type;
-        unsigned char                   trans_quad;
-        unsigned char                   trans_global;
-        unsigned char                   trans_local;
-        unsigned short                  trans_reserved;
-};
-static int                              mpc_record;
-static struct mpc_trans                 *translation_table[MAX_MPC_ENTRY];
-int                                     mp_bus_id_to_node[MAX_MP_BUSSES];
-int                                     mp_bus_id_to_local[MAX_MP_BUSSES];
-int                                     quad_local_to_mp_bus_id[NR_CPUS/4][4];
-static inline void numaq_register_node(int node, struct sys_cfg_data *scd)
-{
-        struct eachquadmem *eq = scd->eq + node;
-        u64 start = (u64)(eq->hi_shrd_mem_start - eq->priv_mem_size) << 20;
-        u64 end = (u64)(eq->hi_shrd_mem_start + eq->hi_shrd_mem_size) << 20;
-        int ret;
-        node_set(node, numa_nodes_parsed);
-        ret = numa_add_memblk(node, start, end);
-        BUG_ON(ret < 0);
-}
-/*
- * Function: smp_dump_qct()
- *
- * Description: gets memory layout from the quad config table.  This
- * function also updates numa_nodes_parsed with the nodes (quads) present.
- */
-static void __init smp_dump_qct(void)
-{
-        struct sys_cfg_data *scd;
-        int node;
-        scd = (void *)__va(SYS_CFG_DATA_PRIV_ADDR);
-        for_each_node(node) {
-                if (scd->quads_present31_0 & (1 << node))
-                        numaq_register_node(node, scd);
-        }
-}
-void numaq_tsc_disable(void)
-{
-        if (!found_numaq)
-                return;
-        if (num_online_nodes() > 1) {
-                printk(KERN_DEBUG "NUMAQ: disabling TSC\n");
-                setup_clear_cpu_cap(X86_FEATURE_TSC);
-        }
-}
-static void __init numaq_tsc_init(void)
-{
-        numaq_tsc_disable();
-}
-static inline int generate_logical_apicid(int quad, int phys_apicid)
-{
-        return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1);
-}
-/* x86_quirks member */
-static int mpc_apic_id(struct mpc_cpu *m)
-{
-        int quad = translation_table[mpc_record]->trans_quad;
-        int logical_apicid = generate_logical_apicid(quad, m->apicid);
-        printk(KERN_DEBUG
-                "Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
-                 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
-                (m->cpufeature & CPU_MODEL_MASK) >> 4,
-                 m->apicver, quad, logical_apicid);
-        return logical_apicid;
-}
-/* x86_quirks member */
-static void mpc_oem_bus_info(struct mpc_bus *m, char *name)
-{
-        int quad = translation_table[mpc_record]->trans_quad;
-        int local = translation_table[mpc_record]->trans_local;
-        mp_bus_id_to_node[m->busid] = quad;
-        mp_bus_id_to_local[m->busid] = local;
-        printk(KERN_INFO "Bus #%d is %s (node %d)\n", m->busid, name, quad);
-}
-/* x86_quirks member */
-static void mpc_oem_pci_bus(struct mpc_bus *m)
-{
-        int quad = translation_table[mpc_record]->trans_quad;
-        int local = translation_table[mpc_record]->trans_local;
-        quad_local_to_mp_bus_id[quad][local] = m->busid;
-}
-/*
- * Called from mpparse code.
- * mode = 0: prescan
- * mode = 1: one mpc entry scanned
- */
-static void numaq_mpc_record(unsigned int mode)
-{
-        if (!mode)
-                mpc_record = 0;
-        else
-                mpc_record++;
-}
-static void __init MP_translation_info(struct mpc_trans *m)
-{
-        printk(KERN_INFO
-            "Translation: record %d, type %d, quad %d, global %d, local %d\n",
-               mpc_record, m->trans_type, m->trans_quad, m->trans_global,
-               m->trans_local);
-        if (mpc_record >= MAX_MPC_ENTRY)
-                printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
-        else
-                translation_table[mpc_record] = m; /* stash this for later */
-        if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
-                node_set_online(m->trans_quad);
-}
-static int __init mpf_checksum(unsigned char *mp, int len)
-{
-        int sum = 0;
-        while (len--)
-                sum += *mp++;
-        return sum & 0xFF;
-}
-/*
- * Read/parse the MPC oem tables
- */
-static void __init smp_read_mpc_oem(struct mpc_table *mpc)
-{
-        struct mpc_oemtable *oemtable = (void *)(long)mpc->oemptr;
-        int count = sizeof(*oemtable);  /* the header size */
-        unsigned char *oemptr = ((unsigned char *)oemtable) + count;
-        mpc_record = 0;
-        printk(KERN_INFO
-                "Found an OEM MPC table at %8p - parsing it...\n", oemtable);
-        if (memcmp(oemtable->signature, MPC_OEM_SIGNATURE, 4)) {
-                printk(KERN_WARNING
-                       "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
-                       oemtable->signature[0], oemtable->signature[1],
-                       oemtable->signature[2], oemtable->signature[3]);
-                return;
-        }
-        if (mpf_checksum((unsigned char *)oemtable, oemtable->length)) {
-                printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
-                return;
-        }
-        while (count < oemtable->length) {
-                switch (*oemptr) {
-                case MP_TRANSLATION:
-                        {
-                                struct mpc_trans *m = (void *)oemptr;
-                                MP_translation_info(m);
-                                oemptr += sizeof(*m);
-                                count += sizeof(*m);
-                                ++mpc_record;
-                                break;
-                        }
-                default:
-                        printk(KERN_WARNING
-                               "Unrecognised OEM table entry type! - %d\n",
-                               (int)*oemptr);
-                        return;
-                }
-        }
-}
-static __init void early_check_numaq(void)
-{
-        /*
-         * get boot-time SMP configuration:
-         */
-        if (smp_found_config)
-                early_get_smp_config();
-        if (found_numaq) {
-                x86_init.mpparse.mpc_record = numaq_mpc_record;
-                x86_init.mpparse.setup_ioapic_ids = x86_init_noop;
-                x86_init.mpparse.mpc_apic_id = mpc_apic_id;
-                x86_init.mpparse.smp_read_mpc_oem = smp_read_mpc_oem;
-                x86_init.mpparse.mpc_oem_pci_bus = mpc_oem_pci_bus;
-                x86_init.mpparse.mpc_oem_bus_info = mpc_oem_bus_info;
-                x86_init.timers.tsc_pre_init = numaq_tsc_init;
-                x86_init.pci.init = pci_numaq_init;
-        }
-}
-int __init numaq_numa_init(void)
-{
-        early_check_numaq();
-        if (!found_numaq)
-                return -ENOENT;
-        smp_dump_qct();
-        return 0;
-}
-#define NUMAQ_APIC_DFR_VALUE    (APIC_DFR_CLUSTER)
-static inline unsigned int numaq_get_apic_id(unsigned long x)
-{
-        return (x >> 24) & 0x0F;
-}
-static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector)
-{
-        default_send_IPI_mask_sequence_logical(mask, vector);
-}
-static inline void numaq_send_IPI_allbutself(int vector)
-{
-        default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
-}
-static inline void numaq_send_IPI_all(int vector)
-{
-        numaq_send_IPI_mask(cpu_online_mask, vector);
-}
-#define NUMAQ_TRAMPOLINE_PHYS_LOW       (0x8)
-#define NUMAQ_TRAMPOLINE_PHYS_HIGH      (0xa)
-/*
- * Because we use NMIs rather than the INIT-STARTUP sequence to
- * bootstrap the CPUs, the APIC may be in a weird state. Kick it:
- */
-static inline void numaq_smp_callin_clear_local_apic(void)
-{
-        clear_local_APIC();
-}
-static inline const struct cpumask *numaq_target_cpus(void)
-{
-        return cpu_all_mask;
-}
-static unsigned long numaq_check_apicid_used(physid_mask_t *map, int apicid)
-{
-        return physid_isset(apicid, *map);
-}
-static inline unsigned long numaq_check_apicid_present(int bit)
-{
-        return physid_isset(bit, phys_cpu_present_map);
-}
-static inline int numaq_apic_id_registered(void)
-{
-        return 1;
-}
-static inline void numaq_init_apic_ldr(void)
-{
-        /* Already done in NUMA-Q firmware */
-}
-static inline void numaq_setup_apic_routing(void)
-{
-        printk(KERN_INFO
-                "Enabling APIC mode:  NUMA-Q.  Using %d I/O APICs\n",
-                nr_ioapics);
-}
-/*
- * Skip adding the timer int on secondary nodes, which causes
- * a small but painful rift in the time-space continuum.
- */
-static inline int numaq_multi_timer_check(int apic, int irq)
-{
-        return apic != 0 && irq == 0;
-}
-static inline void numaq_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
-{
-        /* We don't have a good way to do this yet - hack */
-        return physids_promote(0xFUL, retmap);
-}
-/*
- * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
- * cpu to APIC ID relation to properly interact with the intelligent
- * mode of the cluster controller.
- */
-static inline int numaq_cpu_present_to_apicid(int mps_cpu)
-{
-        if (mps_cpu < 60)
-                return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
-        else
-                return BAD_APICID;
-}
-static inline int numaq_apicid_to_node(int logical_apicid)
-{
-        return logical_apicid >> 4;
-}
-static int numaq_numa_cpu_node(int cpu)
-{
-        int logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
-        if (logical_apicid != BAD_APICID)
-                return numaq_apicid_to_node(logical_apicid);
-        return NUMA_NO_NODE;
-}
-static void numaq_apicid_to_cpu_present(int logical_apicid, physid_mask_t *retmap)
-{
-        int node = numaq_apicid_to_node(logical_apicid);
-        int cpu = __ffs(logical_apicid & 0xf);
-        physid_set_mask_of_physid(cpu + 4*node, retmap);
-}
-/* Where the IO area was mapped on multiquad, always 0 otherwise */
-void *xquad_portio;
-static inline int numaq_check_phys_apicid_present(int phys_apicid)
-{
-        return 1;
-}
-/*
- * We use physical apicids here, not logical, so just return the default
- * physical broadcast to stop people from breaking us
- */
-static int
-numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                             const struct cpumask *andmask,
-                             unsigned int *apicid)
-{
-        *apicid = 0x0F;
-        return 0;
-}
-/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
-static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb)
-{
-        return cpuid_apic >> index_msb;
-}
-static int
-numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
-{
-        if (strncmp(oem, "IBM NUMA", 8))
-                printk(KERN_ERR "Warning! Not a NUMA-Q system!\n");
-        else
-                found_numaq = 1;
-        return found_numaq;
-}
-static int probe_numaq(void)
-{
-        /* already know from get_memcfg_numaq() */
-        return found_numaq;
-}
-static void numaq_setup_portio_remap(void)
-{
-        int num_quads = num_online_nodes();
-        if (num_quads <= 1)
-                return;
-        printk(KERN_INFO
-                "Remapping cross-quad port I/O for %d quads\n", num_quads);
-        xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
-        printk(KERN_INFO
-                "xquad_portio vaddr 0x%08lx, len %08lx\n",
-                (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
-}
-/* Use __refdata to keep false positive warning calm.  */
-static struct apic __refdata apic_numaq = {
-        .name                           = "NUMAQ",
-        .probe                          = probe_numaq,
-        .acpi_madt_oem_check            = NULL,
-        .apic_id_valid                  = default_apic_id_valid,
-        .apic_id_registered             = numaq_apic_id_registered,
-        .irq_delivery_mode              = dest_LowestPrio,
-        /* physical delivery on LOCAL quad: */
-        .irq_dest_mode                  = 0,
-        .target_cpus                    = numaq_target_cpus,
-        .disable_esr                    = 1,
-        .dest_logical                   = APIC_DEST_LOGICAL,
-        .check_apicid_used              = numaq_check_apicid_used,
-        .check_apicid_present           = numaq_check_apicid_present,
-        .vector_allocation_domain       = flat_vector_allocation_domain,
-        .init_apic_ldr                  = numaq_init_apic_ldr,
-        .ioapic_phys_id_map             = numaq_ioapic_phys_id_map,
-        .setup_apic_routing             = numaq_setup_apic_routing,
-        .multi_timer_check              = numaq_multi_timer_check,
-        .cpu_present_to_apicid          = numaq_cpu_present_to_apicid,
-        .apicid_to_cpu_present          = numaq_apicid_to_cpu_present,
-        .setup_portio_remap             = numaq_setup_portio_remap,
-        .check_phys_apicid_present      = numaq_check_phys_apicid_present,
-        .enable_apic_mode               = NULL,
-        .phys_pkg_id                    = numaq_phys_pkg_id,
-        .mps_oem_check                  = numaq_mps_oem_check,
-        .get_apic_id                    = numaq_get_apic_id,
-        .set_apic_id                    = NULL,
-        .apic_id_mask                   = 0x0F << 24,
-        .cpu_mask_to_apicid_and         = numaq_cpu_mask_to_apicid_and,
-        .send_IPI_mask                  = numaq_send_IPI_mask,
-        .send_IPI_mask_allbutself       = NULL,
-        .send_IPI_allbutself            = numaq_send_IPI_allbutself,
-        .send_IPI_all                   = numaq_send_IPI_all,
-        .send_IPI_self                  = default_send_IPI_self,
-        .wakeup_secondary_cpu           = wakeup_secondary_cpu_via_nmi,
-        .trampoline_phys_low            = NUMAQ_TRAMPOLINE_PHYS_LOW,
-        .trampoline_phys_high           = NUMAQ_TRAMPOLINE_PHYS_HIGH,
-        /* We don't do anything here because we use NMI's to boot instead */
-        .wait_for_init_deassert         = false,
-        .smp_callin_clear_local_apic    = numaq_smp_callin_clear_local_apic,
-        .inquire_remote_apic            = NULL,
-        .read                           = native_apic_mem_read,
-        .write                          = native_apic_mem_write,
-        .eoi_write                      = native_apic_mem_write,
-        .icr_read                       = native_apic_icr_read,
-        .icr_write                      = native_apic_icr_write,
-        .wait_icr_idle                  = native_apic_wait_icr_idle,
-        .safe_wait_icr_idle             = native_safe_apic_wait_icr_idle,
-        .x86_32_early_logical_apicid    = noop_x86_32_early_logical_apicid,
-        .x86_32_numa_cpu_node           = numaq_numa_cpu_node,
-};
-apic_driver(apic_numaq);
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c
deleted file mode 100644
index b656128611cd..000000000000
--- a/arch/x86/kernel/apic/summit_32.c
+++ /dev/null
@@ -1,550 +0,0 @@
-/*
- * IBM Summit-Specific Code
- *
- * Written By: Matthew Dobson, IBM Corporation
- *
- * Copyright (c) 2003 IBM Corp.
- *
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Send feedback to <colpatch@us.ibm.com>
- *
- */
-#define pr_fmt(fmt) "summit: %s: " fmt, __func__
-#include <linux/mm.h>
-#include <asm/io.h>
-#include <asm/bios_ebda.h>
-/*
- * APIC driver for the IBM "Summit" chipset.
- */
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <asm/mpspec.h>
-#include <asm/apic.h>
-#include <asm/smp.h>
-#include <asm/fixmap.h>
-#include <asm/apicdef.h>
-#include <asm/ipi.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/gfp.h>
-#include <linux/smp.h>
-static unsigned summit_get_apic_id(unsigned long x)
-{
-        return (x >> 24) & 0xFF;
-}
-static inline void summit_send_IPI_mask(const struct cpumask *mask, int vector)
-{
-        default_send_IPI_mask_sequence_logical(mask, vector);
-}
-static void summit_send_IPI_allbutself(int vector)
-{
-        default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
-}
-static void summit_send_IPI_all(int vector)
-{
-        summit_send_IPI_mask(cpu_online_mask, vector);
-}
-#include <asm/tsc.h>
-extern int use_cyclone;
-#ifdef CONFIG_X86_SUMMIT_NUMA
-static void setup_summit(void);
-#else
-static inline void setup_summit(void) {}
-#endif
-static int summit_mps_oem_check(struct mpc_table *mpc, char *oem,
-                char *productid)
-{
-        if (!strncmp(oem, "IBM ENSW", 8) &&
-                        (!strncmp(productid, "VIGIL SMP", 9)
-                         || !strncmp(productid, "EXA", 3)
-                         || !strncmp(productid, "RUTHLESS SMP", 12))){
-                mark_tsc_unstable("Summit based system");
-                use_cyclone = 1; /*enable cyclone-timer*/
-                setup_summit();
-                return 1;
-        }
-        return 0;
-}
-/* Hook from generic ACPI tables.c */
-static int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
-{
-        if (!strncmp(oem_id, "IBM", 3) &&
-            (!strncmp(oem_table_id, "SERVIGIL", 8)
-             || !strncmp(oem_table_id, "EXA", 3))){
-                mark_tsc_unstable("Summit based system");
-                use_cyclone = 1; /*enable cyclone-timer*/
-                setup_summit();
-                return 1;
-        }
-        return 0;
-}
-struct rio_table_hdr {
-        unsigned char version;      /* Version number of this data structure           */
-                                    /* Version 3 adds chassis_num & WP_index           */
-        unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil)   */
-        unsigned char num_rio_dev;  /* # of RIO I/O devices (Cyclones and Winnipegs)   */
-} __attribute__((packed));
-struct scal_detail {
-        unsigned char node_id;      /* Scalability Node ID                             */
-        unsigned long CBAR;         /* Address of 1MB register space                   */
-        unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
-        unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-        unsigned char port1node;    /* Node ID port connected to: 0xFF = None          */
-        unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-        unsigned char port2node;    /* Node ID port connected to: 0xFF = None          */
-        unsigned char port2port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-        unsigned char chassis_num;  /* 1 based Chassis number (1 = boot node)          */
-} __attribute__((packed));
-struct rio_detail {
-        unsigned char node_id;      /* RIO Node ID                                     */
-        unsigned long BBAR;         /* Address of 1MB register space                   */
-        unsigned char type;         /* Type of device                                  */
-        unsigned char owner_id;     /* For WPEG: Node ID of Cyclone that owns this WPEG*/
-                                    /* For CYC:  Node ID of Twister that owns this CYC */
-        unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
-        unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-        unsigned char port1node;    /* Node ID port connected to: 0xFF=None            */
-        unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
-        unsigned char first_slot;   /* For WPEG: Lowest slot number below this WPEG    */
-                                    /* For CYC:  0                                     */
-        unsigned char status;       /* For WPEG: Bit 0 = 1 : the XAPIC is used         */
-                                    /*                 = 0 : the XAPIC is not used, ie:*/
-                                    /*                     ints fwded to another XAPIC */
-                                    /*           Bits1:7 Reserved                      */
-                                    /* For CYC:  Bits0:7 Reserved                      */
-        unsigned char WP_index;     /* For WPEG: WPEG instance index - lower ones have */
-                                    /*           lower slot numbers/PCI bus numbers    */
-                                    /* For CYC:  No meaning                            */
-        unsigned char chassis_num;  /* 1 based Chassis number                          */
-                                    /* For LookOut WPEGs this field indicates the      */
-                                    /* Expansion Chassis #, enumerated from Boot       */
-                                    /* Node WPEG external port, then Boot Node CYC     */
-                                    /* external port, then Next Vigil chassis WPEG     */
-                                    /* external port, etc.                             */
-                                    /* Shared Lookouts have only 1 chassis number (the */
-                                    /* first one assigned)                             */
-} __attribute__((packed));
-typedef enum {
-        CompatTwister = 0,  /* Compatibility Twister               */
-        AltTwister    = 1,  /* Alternate Twister of internal 8-way */
-        CompatCyclone = 2,  /* Compatibility Cyclone               */
-        AltCyclone    = 3,  /* Alternate Cyclone of internal 8-way */
-        CompatWPEG    = 4,  /* Compatibility WPEG                  */
-        AltWPEG       = 5,  /* Second Planar WPEG                  */
-        LookOutAWPEG  = 6,  /* LookOut WPEG                        */
-        LookOutBWPEG  = 7,  /* LookOut WPEG                        */
-} node_type;
-static inline int is_WPEG(struct rio_detail *rio){
-        return (rio->type == CompatWPEG || rio->type == AltWPEG ||
-                rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
-}
-#define SUMMIT_APIC_DFR_VALUE   (APIC_DFR_CLUSTER)
-static const struct cpumask *summit_target_cpus(void)
-{
-        /* CPU_MASK_ALL (0xff) has undefined behaviour with
-         * dest_LowestPrio mode logical clustered apic interrupt routing
-         * Just start on cpu 0.  IRQ balancing will spread load
-         */
-        return cpumask_of(0);
-}
-static unsigned long summit_check_apicid_used(physid_mask_t *map, int apicid)
-{
-        return 0;
-}
-/* we don't use the phys_cpu_present_map to indicate apicid presence */
-static unsigned long summit_check_apicid_present(int bit)
-{
-        return 1;
-}
-static int summit_early_logical_apicid(int cpu)
-{
-        int count = 0;
-        u8 my_id = early_per_cpu(x86_cpu_to_apicid, cpu);
-        u8 my_cluster = APIC_CLUSTER(my_id);
-#ifdef CONFIG_SMP
-        u8 lid;
-        int i;
-        /* Create logical APIC IDs by counting CPUs already in cluster. */
-        for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
-                lid = early_per_cpu(x86_cpu_to_logical_apicid, i);
-                if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)
-                        ++count;
-        }
-#endif
-        /* We only have a 4 wide bitmap in cluster mode.  If a deranged
-         * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
-        BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
-        return my_cluster | (1UL << count);
-}
-static void summit_init_apic_ldr(void)
-{
-        int cpu = smp_processor_id();
-        unsigned long id = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
-        unsigned long val;
-        apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE);
-        val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
-        val |= SET_APIC_LOGICAL_ID(id);
-        apic_write(APIC_LDR, val);
-}
-static int summit_apic_id_registered(void)
-{
-        return 1;
-}
-static void summit_setup_apic_routing(void)
-{
-        pr_info("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
-                nr_ioapics);
-}
-static int summit_cpu_present_to_apicid(int mps_cpu)
-{
-        if (mps_cpu < nr_cpu_ids)
-                return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
-        else
-                return BAD_APICID;
-}
-static void summit_ioapic_phys_id_map(physid_mask_t *phys_id_map, physid_mask_t *retmap)
-{
-        /* For clustered we don't have a good way to do this yet - hack */
-        physids_promote(0x0FL, retmap);
-}
-static void summit_apicid_to_cpu_present(int apicid, physid_mask_t *retmap)
-{
-        physid_set_mask_of_physid(0, retmap);
-}
-static int summit_check_phys_apicid_present(int physical_apicid)
-{
-        return 1;
-}
-static inline int
-summit_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id)
-{
-        unsigned int round = 0;
-        unsigned int cpu, apicid = 0;
-        /*
-         * The cpus in the mask must all be on the apic cluster.
-         */
-        for_each_cpu_and(cpu, cpumask, cpu_online_mask) {
-                int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
-                if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
-                        pr_err("Not a valid mask!\n");
-                        return -EINVAL;
-                }
-                apicid |= new_apicid;
-                round++;
-        }
-        if (!round)
-                return -EINVAL;
-        *dest_id = apicid;
-        return 0;
-}
-static int
-summit_cpu_mask_to_apicid_and(const struct cpumask *inmask,
-                              const struct cpumask *andmask,
-                              unsigned int *apicid)
-{
-        cpumask_var_t cpumask;
-        *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
-        if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
-                return 0;
-        cpumask_and(cpumask, inmask, andmask);
-        summit_cpu_mask_to_apicid(cpumask, apicid);
-        free_cpumask_var(cpumask);
-        return 0;
-}
-/*
- * cpuid returns the value latched in the HW at reset, not the APIC ID
- * register's value.  For any box whose BIOS changes APIC IDs, like
- * clustered APIC systems, we must use hard_smp_processor_id.
- *
- * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
- */
-static int summit_phys_pkg_id(int cpuid_apic, int index_msb)
-{
-        return hard_smp_processor_id() >> index_msb;
-}
-static int probe_summit(void)
-{
-        /* probed later in mptable/ACPI hooks */
-        return 0;
-}
-#ifdef CONFIG_X86_SUMMIT_NUMA
-static struct rio_table_hdr *rio_table_hdr;
-static struct scal_detail   *scal_devs[MAX_NUMNODES];
-static struct rio_detail    *rio_devs[MAX_NUMNODES*4];
-#ifndef CONFIG_X86_NUMAQ
-static int mp_bus_id_to_node[MAX_MP_BUSSES];
-#endif
-static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
-{
-        int twister = 0, node = 0;
-        int i, bus, num_buses;
-        for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
-                if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) {
-                        twister = rio_devs[i]->owner_id;
-                        break;
-                }
-        }
-        if (i == rio_table_hdr->num_rio_dev) {
-                pr_err("Couldn't find owner Cyclone for Winnipeg!\n");
-                return last_bus;
-        }
-        for (i = 0; i < rio_table_hdr->num_scal_dev; i++) {
-                if (scal_devs[i]->node_id == twister) {
-                        node = scal_devs[i]->node_id;
-                        break;
-                }
-        }
-        if (i == rio_table_hdr->num_scal_dev) {
-                pr_err("Couldn't find owner Twister for Cyclone!\n");
-                return last_bus;
-        }
-        switch (rio_devs[wpeg_num]->type) {
-        case CompatWPEG:
-                /*
-                 * The Compatibility Winnipeg controls the 2 legacy buses,
-                 * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case
-                 * a PCI-PCI bridge card is used in either slot: total 5 buses.
-                 */
-                num_buses = 5;
-                break;
-        case AltWPEG:
-                /*
-                 * The Alternate Winnipeg controls the 2 133MHz buses [1 slot
-                 * each], their 2 "extra" buses, the 100MHz bus [2 slots] and
-                 * the "extra" buses for each of those slots: total 7 buses.
-                 */
-                num_buses = 7;
-                break;
-        case LookOutAWPEG:
-        case LookOutBWPEG:
-                /*
-                 * A Lookout Winnipeg controls 3 100MHz buses [2 slots each]
-                 * & the "extra" buses for each of those slots: total 9 buses.
-                 */
-                num_buses = 9;
-                break;
-        default:
-                pr_info("Unsupported Winnipeg type!\n");
-                return last_bus;
-        }
-        for (bus = last_bus; bus < last_bus + num_buses; bus++)
-                mp_bus_id_to_node[bus] = node;
-        return bus;
-}
-static int build_detail_arrays(void)
-{
-        unsigned long ptr;
-        int i, scal_detail_size, rio_detail_size;
-        if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) {
-                pr_warn("MAX_NUMNODES too low!  Defined as %d, but system has %d nodes\n",
-                        MAX_NUMNODES, rio_table_hdr->num_scal_dev);
-                return 0;
-        }
-        switch (rio_table_hdr->version) {
-        default:
-                pr_warn("Invalid Rio Grande Table Version: %d\n",
-                        rio_table_hdr->version);
-                return 0;
-        case 2:
-                scal_detail_size = 11;
-                rio_detail_size = 13;
-                break;
-        case 3:
-                scal_detail_size = 12;
-                rio_detail_size = 15;
-                break;
-        }
-        ptr = (unsigned long)rio_table_hdr + 3;
-        for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size)
-                scal_devs[i] = (struct scal_detail *)ptr;
-        for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size)
-                rio_devs[i] = (struct rio_detail *)ptr;
-        return 1;
-}
-void setup_summit(void)
-{
-        unsigned long           ptr;
-        unsigned short          offset;
-        int                     i, next_wpeg, next_bus = 0;
-        /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */
-        ptr = get_bios_ebda();
-        ptr = (unsigned long)phys_to_virt(ptr);
-        rio_table_hdr = NULL;
-        offset = 0x180;
-        while (offset) {
-                /* The block id is stored in the 2nd word */
-                if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) {
-                        /* set the pointer past the offset & block id */
-                        rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
-                        break;
-                }
-                /* The next offset is stored in the 1st word.  0 means no more */
-                offset = *((unsigned short *)(ptr + offset));
-        }
-        if (!rio_table_hdr) {
-                pr_err("Unable to locate Rio Grande Table in EBDA - bailing!\n");
-                return;
-        }
-        if (!build_detail_arrays())
-                return;
-        /* The first Winnipeg we're looking for has an index of 0 */
-        next_wpeg = 0;
-        do {
-                for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
-                        if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) {
-                                /* It's the Winnipeg we're looking for! */
-                                next_bus = setup_pci_node_map_for_wpeg(i, next_bus);
-                                next_wpeg++;
-                                break;
-                        }
-                }
-                /*
-                 * If we go through all Rio devices and don't find one with
-                 * the next index, it means we've found all the Winnipegs,
-                 * and thus all the PCI buses.
-                 */
-                if (i == rio_table_hdr->num_rio_dev)
-                        next_wpeg = 0;
-        } while (next_wpeg != 0);
-}
-#endif
-static struct apic apic_summit = {
-        .name                           = "summit",
-        .probe                          = probe_summit,
-        .acpi_madt_oem_check            = summit_acpi_madt_oem_check,
-        .apic_id_valid                  = default_apic_id_valid,
-        .apic_id_registered             = summit_apic_id_registered,
-        .irq_delivery_mode              = dest_LowestPrio,
-        /* logical delivery broadcast to all CPUs: */
-        .irq_dest_mode                  = 1,
-        .target_cpus                    = summit_target_cpus,
-        .disable_esr                    = 1,
-        .dest_logical                   = APIC_DEST_LOGICAL,
-        .check_apicid_used              = summit_check_apicid_used,
-        .check_apicid_present           = summit_check_apicid_present,
-        .vector_allocation_domain       = flat_vector_allocation_domain,
-        .init_apic_ldr                  = summit_init_apic_ldr,
-        .ioapic_phys_id_map             = summit_ioapic_phys_id_map,
-        .setup_apic_routing             = summit_setup_apic_routing,
-        .multi_timer_check              = NULL,
-        .cpu_present_to_apicid          = summit_cpu_present_to_apicid,
-        .apicid_to_cpu_present          = summit_apicid_to_cpu_present,
-        .setup_portio_remap             = NULL,
-        .check_phys_apicid_present      = summit_check_phys_apicid_present,
-        .enable_apic_mode               = NULL,
-        .phys_pkg_id                    = summit_phys_pkg_id,
-        .mps_oem_check                  = summit_mps_oem_check,
-        .get_apic_id                    = summit_get_apic_id,
-        .set_apic_id                    = NULL,
-        .apic_id_mask                   = 0xFF << 24,
-        .cpu_mask_to_apicid_and         = summit_cpu_mask_to_apicid_and,
-        .send_IPI_mask                  = summit_send_IPI_mask,
-        .send_IPI_mask_allbutself       = NULL,
-        .send_IPI_allbutself            = summit_send_IPI_allbutself,
-        .send_IPI_all                   = summit_send_IPI_all,
-        .send_IPI_self                  = default_send_IPI_self,
-        .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
-        .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
-        .wait_for_init_deassert         = true,
-        .smp_callin_clear_local_apic    = NULL,
-        .inquire_remote_apic            = default_inquire_remote_apic,
-        .read                           = native_apic_mem_read,
-        .write                          = native_apic_mem_write,
-        .eoi_write                      = native_apic_mem_write,
-        .icr_read                       = native_apic_icr_read,
-        .icr_write                      = native_apic_icr_write,
-        .wait_icr_idle                  = native_apic_wait_icr_idle,
-        .safe_wait_icr_idle             = native_safe_apic_wait_icr_idle,
-        .x86_32_early_logical_apicid    = summit_early_logical_apicid,
-};
-apic_driver(apic_summit);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 897d6201ef10..a80029035bf2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -274,10 +274,6 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
        }
 #endif
-#ifdef CONFIG_X86_NUMAQ
-        numaq_tsc_disable();
-#endif
        intel_smp_check(c);
 }
 #else
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 0641113e2965..a952e9c85b6f 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -1225,21 +1225,24 @@ static struct notifier_block cacheinfo_cpu_notifier = {
 static int __init cache_sysfs_init(void)
 {
-        int i;
+        int i, err = 0;
        if (num_cache_leaves == 0)
                return 0;
+        cpu_notifier_register_begin();
        for_each_online_cpu(i) {
-                int err;
                struct device *dev = get_cpu_device(i);
                err = cache_add_dev(dev);
                if (err)
-                        return err;
+                        goto out;
        }
-        register_hotcpu_notifier(&cacheinfo_cpu_notifier);
+        __register_hotcpu_notifier(&cacheinfo_cpu_notifier);
-        return 0;
+out:
+        cpu_notifier_register_done();
+        return err;
 }
 device_initcall(cache_sysfs_init);
diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c
index 36565373af87..afa9f0d487ea 100644
--- a/arch/x86/kernel/cpu/match.c
+++ b/arch/x86/kernel/cpu/match.c
@@ -47,45 +47,3 @@ const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match)
        return NULL;
 }
 EXPORT_SYMBOL(x86_match_cpu);
-ssize_t arch_print_cpu_modalias(struct device *dev,
-                                struct device_attribute *attr,
-                                char *bufptr)
-{
-        int size = PAGE_SIZE;
-        int i, n;
-        char *buf = bufptr;
-        n = snprintf(buf, size, "x86cpu:vendor:%04X:family:%04X:"
-                     "model:%04X:feature:",
-                boot_cpu_data.x86_vendor,
-                boot_cpu_data.x86,
-                boot_cpu_data.x86_model);
-        size -= n;
-        buf += n;
-        size -= 1;
-        for (i = 0; i < NCAPINTS*32; i++) {
-                if (boot_cpu_has(i)) {
-                        n = snprintf(buf, size, ",%04X", i);
-                        if (n >= size) {
-                                WARN(1, "x86 features overflow page\n");
-                                break;
-                        }
-                        size -= n;
-                        buf += n;
-                }
-        }
-        *buf++ = '\n';
-        return buf - bufptr;
-}
-int arch_cpu_uevent(struct device *dev, struct kobj_uevent_env *env)
-{
-        char *buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
-        if (buf) {
-                arch_print_cpu_modalias(NULL, NULL, buf);
-                add_uevent_var(env, "MODALIAS=%s", buf);
-                kfree(buf);
-        }
-        return 0;
-}
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 4d5419b249da..eeee23ff75ef 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -89,6 +89,9 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
 static DEFINE_PER_CPU(struct mce, mces_seen);
 static int                      cpu_missing;
+/* CMCI storm detection filter */
+static DEFINE_PER_CPU(unsigned long, mce_polled_error);
 /*
 * MCA banks polled by the period polling timer for corrected events.
 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
@@ -595,6 +598,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
 {
        struct mce m;
        int i;
+        unsigned long *v;
        this_cpu_inc(mce_poll_count);
@@ -614,6 +618,8 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                if (!(m.status & MCI_STATUS_VAL))
                        continue;
+                v = &get_cpu_var(mce_polled_error);
+                set_bit(0, v);
                /*
                 * Uncorrected or signalled events are handled by the exception
                 * handler when it is enabled, so don't process those here.
@@ -1278,10 +1284,18 @@ static unsigned long mce_adjust_timer_default(unsigned long interval)
 static unsigned long (*mce_adjust_timer)(unsigned long interval) =
        mce_adjust_timer_default;
+static int cmc_error_seen(void)
+{
+        unsigned long *v = &__get_cpu_var(mce_polled_error);
+        return test_and_clear_bit(0, v);
+}
 static void mce_timer_fn(unsigned long data)
 {
        struct timer_list *t = &__get_cpu_var(mce_timer);
        unsigned long iv;
+        int notify;
        WARN_ON(smp_processor_id() != data);
@@ -1296,7 +1310,9 @@ static void mce_timer_fn(unsigned long data)
         * polling interval, otherwise increase the polling interval.
         */
        iv = __this_cpu_read(mce_next_interval);
-        if (mce_notify_irq()) {
+        notify = mce_notify_irq();
+        notify |= cmc_error_seen();
+        if (notify) {
                iv = max(iv / 2, (unsigned long) HZ/100);
        } else {
                iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
@@ -2434,14 +2450,18 @@ static __init int mcheck_init_device(void)
        if (err)
                return err;
+        cpu_notifier_register_begin();
        for_each_online_cpu(i) {
                err = mce_device_create(i);
-                if (err)
+                if (err) {
+                        cpu_notifier_register_done();
                        return err;
+                }
        }
        register_syscore_ops(&mce_syscore_ops);
-        register_hotcpu_notifier(&mce_cpu_notifier);
+        __register_hotcpu_notifier(&mce_cpu_notifier);
+        cpu_notifier_register_done();
        /* register character device /dev/mcelog */
        misc_register(&mce_chrdev_device);
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index fb6156fee6f7..3bdb95ae8c43 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -9,6 +9,7 @@
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
 #include <linux/sched.h>
+#include <linux/cpumask.h>
 #include <asm/apic.h>
 #include <asm/processor.h>
 #include <asm/msr.h>
@@ -137,6 +138,22 @@ unsigned long mce_intel_adjust_timer(unsigned long interval)
        }
 }
+static void cmci_storm_disable_banks(void)
+{
+        unsigned long flags, *owned;
+        int bank;
+        u64 val;
+        raw_spin_lock_irqsave(&cmci_discover_lock, flags);
+        owned = __get_cpu_var(mce_banks_owned);
+        for_each_set_bit(bank, owned, MAX_NR_BANKS) {
+                rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
+                val &= ~MCI_CTL2_CMCI_EN;
+                wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
+        }
+        raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
+}
 static bool cmci_storm_detect(void)
 {
        unsigned int cnt = __this_cpu_read(cmci_storm_cnt);
@@ -158,7 +175,7 @@ static bool cmci_storm_detect(void)
        if (cnt <= CMCI_STORM_THRESHOLD)
                return false;
-        cmci_clear();
+        cmci_storm_disable_banks();
        __this_cpu_write(cmci_storm_state, CMCI_STORM_ACTIVE);
        r = atomic_add_return(1, &cmci_storm_on_cpus);
        mce_timer_kick(CMCI_POLL_INTERVAL);
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index 3eec7de76efb..d921b7ee6595 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -271,9 +271,6 @@ static void thermal_throttle_remove_dev(struct device *dev)
        sysfs_remove_group(&dev->kobj, &thermal_attr_group);
 }
-/* Mutex protecting device creation against CPU hotplug: */
-static DEFINE_MUTEX(therm_cpu_lock);
 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
 static int
 thermal_throttle_cpu_callback(struct notifier_block *nfb,
@@ -289,18 +286,14 @@ thermal_throttle_cpu_callback(struct notifier_block *nfb,
        switch (action) {
        case CPU_UP_PREPARE:
        case CPU_UP_PREPARE_FROZEN:
-                mutex_lock(&therm_cpu_lock);
                err = thermal_throttle_add_dev(dev, cpu);
-                mutex_unlock(&therm_cpu_lock);
                WARN_ON(err);
                break;
        case CPU_UP_CANCELED:
        case CPU_UP_CANCELED_FROZEN:
        case CPU_DEAD:
        case CPU_DEAD_FROZEN:
-                mutex_lock(&therm_cpu_lock);
                thermal_throttle_remove_dev(dev);
-                mutex_unlock(&therm_cpu_lock);
                break;
        }
        return notifier_from_errno(err);
@@ -319,19 +312,16 @@ static __init int thermal_throttle_init_device(void)
        if (!atomic_read(&therm_throt_en))
                return 0;
-        register_hotcpu_notifier(&thermal_throttle_cpu_notifier);
+        cpu_notifier_register_begin();
-#ifdef CONFIG_HOTPLUG_CPU
-        mutex_lock(&therm_cpu_lock);
-#endif
        /* connect live CPUs to sysfs */
        for_each_online_cpu(cpu) {
                err = thermal_throttle_add_dev(get_cpu_device(cpu), cpu);
                WARN_ON(err);
        }
-#ifdef CONFIG_HOTPLUG_CPU
-        mutex_unlock(&therm_cpu_lock);
+        __register_hotcpu_notifier(&thermal_throttle_cpu_notifier);
-#endif
+        cpu_notifier_register_done();
        return 0;
 }
diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
index 4b8e4d3cd6ea..4c36bbe3173a 100644
--- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
@@ -926,13 +926,13 @@ static __init int amd_ibs_init(void)
                goto out;
        perf_ibs_pm_init();
-        get_online_cpus();
+        cpu_notifier_register_begin();
        ibs_caps = caps;
        /* make ibs_caps visible to other cpus: */
        smp_mb();
-        perf_cpu_notifier(perf_ibs_cpu_notifier);
        smp_call_function(setup_APIC_ibs, NULL, 1);
-        put_online_cpus();
+        __perf_cpu_notifier(perf_ibs_cpu_notifier);
+        cpu_notifier_register_done();
        ret = perf_event_ibs_init();
 out:
diff --git a/arch/x86/kernel/cpu/perf_event_amd_uncore.c b/arch/x86/kernel/cpu/perf_event_amd_uncore.c
index 754291adec33..3bbdf4cd38b9 100644
--- a/arch/x86/kernel/cpu/perf_event_amd_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_uncore.c
@@ -531,15 +531,16 @@ static int __init amd_uncore_init(void)
        if (ret)
                return -ENODEV;
-        get_online_cpus();
+        cpu_notifier_register_begin();
        /* init cpus already online before registering for hotplug notifier */
        for_each_online_cpu(cpu) {
                amd_uncore_cpu_up_prepare(cpu);
                smp_call_function_single(cpu, init_cpu_already_online, NULL, 1);
        }
-        register_cpu_notifier(&amd_uncore_cpu_notifier_block);
+        __register_cpu_notifier(&amd_uncore_cpu_notifier_block);
-        put_online_cpus();
+        cpu_notifier_register_done();
        return 0;
 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_rapl.c b/arch/x86/kernel/cpu/perf_event_intel_rapl.c
index 3cec947e3b98..4b9a9e9466bd 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_rapl.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_rapl.c
@@ -673,19 +673,20 @@ static int __init rapl_pmu_init(void)
                /* unsupported */
                return 0;
        }
-        get_online_cpus();
+        cpu_notifier_register_begin();
        for_each_online_cpu(cpu) {
                rapl_cpu_prepare(cpu);
                rapl_cpu_init(cpu);
        }
-        perf_cpu_notifier(rapl_cpu_notifier);
+        __perf_cpu_notifier(rapl_cpu_notifier);
        ret = perf_pmu_register(&rapl_pmu_class, "power", -1);
        if (WARN_ON(ret)) {
                pr_info("RAPL PMU detected, registration failed (%d), RAPL PMU disabled\n", ret);
-                put_online_cpus();
+                cpu_notifier_register_done();
                return -1;
        }
@@ -699,7 +700,7 @@ static int __init rapl_pmu_init(void)
                hweight32(rapl_cntr_mask),
                ktime_to_ms(pmu->timer_interval));
-        put_online_cpus();
+        cpu_notifier_register_done();
        return 0;
 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index bd2253d40cff..65bbbea38b9c 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -4244,7 +4244,7 @@ static void __init uncore_cpumask_init(void)
        if (!cpumask_empty(&uncore_cpu_mask))
                return;
-        get_online_cpus();
+        cpu_notifier_register_begin();
        for_each_online_cpu(cpu) {
                int i, phys_id = topology_physical_package_id(cpu);
@@ -4263,9 +4263,9 @@ static void __init uncore_cpumask_init(void)
        }
        on_each_cpu(uncore_cpu_setup, NULL, 1);
-        register_cpu_notifier(&uncore_cpu_nb);
+        __register_cpu_notifier(&uncore_cpu_nb);
-        put_online_cpus();
+        cpu_notifier_register_done();
 }
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 7d9481c743f8..3225ae6c5180 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -198,14 +198,15 @@ static int __init cpuid_init(void)
                goto out_chrdev;
        }
        cpuid_class->devnode = cpuid_devnode;
-        get_online_cpus();
+        cpu_notifier_register_begin();
        for_each_online_cpu(i) {
                err = cpuid_device_create(i);
                if (err != 0)
                        goto out_class;
        }
-        register_hotcpu_notifier(&cpuid_class_cpu_notifier);
+        __register_hotcpu_notifier(&cpuid_class_cpu_notifier);
-        put_online_cpus();
+        cpu_notifier_register_done();
        err = 0;
        goto out;
@@ -215,7 +216,7 @@ out_class:
        for_each_online_cpu(i) {
                cpuid_device_destroy(i);
        }
-        put_online_cpus();
+        cpu_notifier_register_done();
        class_destroy(cpuid_class);
 out_chrdev:
        __unregister_chrdev(CPUID_MAJOR, 0, NR_CPUS, "cpu/cpuid");
@@ -227,13 +228,13 @@ static void __exit cpuid_exit(void)
 {
        int cpu = 0;
-        get_online_cpus();
+        cpu_notifier_register_begin();
        for_each_online_cpu(cpu)
                cpuid_device_destroy(cpu);
        class_destroy(cpuid_class);
        __unregister_chrdev(CPUID_MAJOR, 0, NR_CPUS, "cpu/cpuid");
-        unregister_hotcpu_notifier(&cpuid_class_cpu_notifier);
+        __unregister_hotcpu_notifier(&cpuid_class_cpu_notifier);
-        put_online_cpus();
+        cpu_notifier_register_done();
 }
 module_init(cpuid_init);
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index 346b1df2412e..1abcb50b48ae 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -115,27 +115,26 @@ enum stack_type {
 };
 static enum stack_type
-analyze_stack(int cpu, struct task_struct *task,
+analyze_stack(int cpu, struct task_struct *task, unsigned long *stack,
-              unsigned long *stack, unsigned long **stack_end, char **id)
+              unsigned long **stack_end, unsigned long *irq_stack,
+              unsigned *used, char **id)
 {
-        unsigned long *irq_stack;
        unsigned long addr;
-        unsigned used = 0;
        addr = ((unsigned long)stack & (~(THREAD_SIZE - 1)));
        if ((unsigned long)task_stack_page(task) == addr)
                return STACK_IS_NORMAL;
        *stack_end = in_exception_stack(cpu, (unsigned long)stack,
-                                         &used, id);
+                                        used, id);
        if (*stack_end)
                return STACK_IS_EXCEPTION;
-        *stack_end = (unsigned long *)per_cpu(irq_stack_ptr, cpu);
+        if (!irq_stack)
-        if (!*stack_end)
+                return STACK_IS_NORMAL;
-                return STACK_IS_UNKNOWN;
-        irq_stack = *stack_end - irq_stack_size;
+        *stack_end = irq_stack;
+        irq_stack = irq_stack - irq_stack_size;
        if (in_irq_stack(stack, irq_stack, *stack_end))
                return STACK_IS_IRQ;
@@ -156,8 +155,9 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
 {
        const unsigned cpu = get_cpu();
        struct thread_info *tinfo;
-        unsigned long *irq_stack;
+        unsigned long *irq_stack = (unsigned long *)per_cpu(irq_stack_ptr, cpu);
        unsigned long dummy;
+        unsigned used = 0;
        int graph = 0;
        int done = 0;
@@ -186,7 +186,8 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                enum stack_type stype;
                char *id;
-                stype = analyze_stack(cpu, task, stack, &stack_end, &id);
+                stype = analyze_stack(cpu, task, stack, &stack_end,
+                                      irq_stack, &used, &id);
                /* Default finish unless specified to continue */
                done = 1;
@@ -226,7 +227,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                         * pointer (index -1 to end) in the IRQ stack:
                         */
                        stack = (unsigned long *) (stack_end[-1]);
-                        irq_stack = stack_end - irq_stack_size;
+                        irq_stack = NULL;
                        ops->stack(data, "EOI");
                        done = 0;
                        break;
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6d7d5a1260a6..b0cc3809723d 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -225,7 +225,7 @@ static void __init intel_remapping_check(int num, int slot, int func)
 *
 * And yes, so far on current devices the base addr is always under 4G.
 */
-static u32 __init intel_stolen_base(int num, int slot, int func)
+static u32 __init intel_stolen_base(int num, int slot, int func, size_t stolen_size)
 {
        u32 base;
@@ -244,6 +244,114 @@ static u32 __init intel_stolen_base(int num, int slot, int func)
 #define MB(x)   (KB (KB (x)))
 #define GB(x)   (MB (KB (x)))
+static size_t __init i830_tseg_size(void)
+{
+        u8 tmp = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
+        if (!(tmp & TSEG_ENABLE))
+                return 0;
+        if (tmp & I830_TSEG_SIZE_1M)
+                return MB(1);
+        else
+                return KB(512);
+}
+static size_t __init i845_tseg_size(void)
+{
+        u8 tmp = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
+        if (!(tmp & TSEG_ENABLE))
+                return 0;
+        switch (tmp & I845_TSEG_SIZE_MASK) {
+        case I845_TSEG_SIZE_512K:
+                return KB(512);
+        case I845_TSEG_SIZE_1M:
+                return MB(1);
+        default:
+                WARN_ON(1);
+                return 0;
+        }
+}
+static size_t __init i85x_tseg_size(void)
+{
+        u8 tmp = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
+        if (!(tmp & TSEG_ENABLE))
+                return 0;
+        return MB(1);
+}
+static size_t __init i830_mem_size(void)
+{
+        return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
+}
+static size_t __init i85x_mem_size(void)
+{
+        return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
+}
+/*
+ * On 830/845/85x the stolen memory base isn't available in any
+ * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
+ */
+static u32 __init i830_stolen_base(int num, int slot, int func, size_t stolen_size)
+{
+        return i830_mem_size() - i830_tseg_size() - stolen_size;
+}
+static u32 __init i845_stolen_base(int num, int slot, int func, size_t stolen_size)
+{
+        return i830_mem_size() - i845_tseg_size() - stolen_size;
+}
+static u32 __init i85x_stolen_base(int num, int slot, int func, size_t stolen_size)
+{
+        return i85x_mem_size() - i85x_tseg_size() - stolen_size;
+}
+static u32 __init i865_stolen_base(int num, int slot, int func, size_t stolen_size)
+{
+        /*
+         * FIXME is the graphics stolen memory region
+         * always at TOUD? Ie. is it always the last
+         * one to be allocated by the BIOS?
+         */
+        return read_pci_config_16(0, 0, 0, I865_TOUD) << 16;
+}
+static size_t __init i830_stolen_size(int num, int slot, int func)
+{
+        size_t stolen_size;
+        u16 gmch_ctrl;
+        gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
+        switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
+        case I830_GMCH_GMS_STOLEN_512:
+                stolen_size = KB(512);
+                break;
+        case I830_GMCH_GMS_STOLEN_1024:
+                stolen_size = MB(1);
+                break;
+        case I830_GMCH_GMS_STOLEN_8192:
+                stolen_size = MB(8);
+                break;
+        case I830_GMCH_GMS_LOCAL:
+                /* local memory isn't part of the normal address space */
+                stolen_size = 0;
+                break;
+        default:
+                return 0;
+        }
+        return stolen_size;
+}
 static size_t __init gen3_stolen_size(int num, int slot, int func)
 {
        size_t stolen_size;
@@ -310,7 +418,7 @@ static size_t __init gen6_stolen_size(int num, int slot, int func)
        return gmch_ctrl << 25; /* 32 MB units */
 }
-static inline size_t gen8_stolen_size(int num, int slot, int func)
+static size_t gen8_stolen_size(int num, int slot, int func)
 {
        u16 gmch_ctrl;
@@ -320,31 +428,74 @@ static inline size_t gen8_stolen_size(int num, int slot, int func)
        return gmch_ctrl << 25; /* 32 MB units */
 }
-typedef size_t (*stolen_size_fn)(int num, int slot, int func);
+struct intel_stolen_funcs {
+        size_t (*size)(int num, int slot, int func);
+        u32 (*base)(int num, int slot, int func, size_t size);
+};
+static const struct intel_stolen_funcs i830_stolen_funcs = {
+        .base = i830_stolen_base,
+        .size = i830_stolen_size,
+};
+static const struct intel_stolen_funcs i845_stolen_funcs = {
+        .base = i845_stolen_base,
+        .size = i830_stolen_size,
+};
+static const struct intel_stolen_funcs i85x_stolen_funcs = {
+        .base = i85x_stolen_base,
+        .size = gen3_stolen_size,
+};
+static const struct intel_stolen_funcs i865_stolen_funcs = {
+        .base = i865_stolen_base,
+        .size = gen3_stolen_size,
+};
+static const struct intel_stolen_funcs gen3_stolen_funcs = {
+        .base = intel_stolen_base,
+        .size = gen3_stolen_size,
+};
+static const struct intel_stolen_funcs gen6_stolen_funcs = {
+        .base = intel_stolen_base,
+        .size = gen6_stolen_size,
+};
+static const struct intel_stolen_funcs gen8_stolen_funcs = {
+        .base = intel_stolen_base,
+        .size = gen8_stolen_size,
+};
 static struct pci_device_id intel_stolen_ids[] __initdata = {
-        INTEL_I915G_IDS(gen3_stolen_size),
+        INTEL_I830_IDS(&i830_stolen_funcs),
-        INTEL_I915GM_IDS(gen3_stolen_size),
+        INTEL_I845G_IDS(&i845_stolen_funcs),
-        INTEL_I945G_IDS(gen3_stolen_size),
+        INTEL_I85X_IDS(&i85x_stolen_funcs),
-        INTEL_I945GM_IDS(gen3_stolen_size),
+        INTEL_I865G_IDS(&i865_stolen_funcs),
-        INTEL_VLV_M_IDS(gen6_stolen_size),
+        INTEL_I915G_IDS(&gen3_stolen_funcs),
-        INTEL_VLV_D_IDS(gen6_stolen_size),
+        INTEL_I915GM_IDS(&gen3_stolen_funcs),
-        INTEL_PINEVIEW_IDS(gen3_stolen_size),
+        INTEL_I945G_IDS(&gen3_stolen_funcs),
-        INTEL_I965G_IDS(gen3_stolen_size),
+        INTEL_I945GM_IDS(&gen3_stolen_funcs),
-        INTEL_G33_IDS(gen3_stolen_size),
+        INTEL_VLV_M_IDS(&gen6_stolen_funcs),
-        INTEL_I965GM_IDS(gen3_stolen_size),
+        INTEL_VLV_D_IDS(&gen6_stolen_funcs),
-        INTEL_GM45_IDS(gen3_stolen_size),
+        INTEL_PINEVIEW_IDS(&gen3_stolen_funcs),
-        INTEL_G45_IDS(gen3_stolen_size),
+        INTEL_I965G_IDS(&gen3_stolen_funcs),
-        INTEL_IRONLAKE_D_IDS(gen3_stolen_size),
+        INTEL_G33_IDS(&gen3_stolen_funcs),
-        INTEL_IRONLAKE_M_IDS(gen3_stolen_size),
+        INTEL_I965GM_IDS(&gen3_stolen_funcs),
-        INTEL_SNB_D_IDS(gen6_stolen_size),
+        INTEL_GM45_IDS(&gen3_stolen_funcs),
-        INTEL_SNB_M_IDS(gen6_stolen_size),
+        INTEL_G45_IDS(&gen3_stolen_funcs),
-        INTEL_IVB_M_IDS(gen6_stolen_size),
+        INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs),
-        INTEL_IVB_D_IDS(gen6_stolen_size),
+        INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs),
-        INTEL_HSW_D_IDS(gen6_stolen_size),
+        INTEL_SNB_D_IDS(&gen6_stolen_funcs),
-        INTEL_HSW_M_IDS(gen6_stolen_size),
+        INTEL_SNB_M_IDS(&gen6_stolen_funcs),
-        INTEL_BDW_M_IDS(gen8_stolen_size),
+        INTEL_IVB_M_IDS(&gen6_stolen_funcs),
-        INTEL_BDW_D_IDS(gen8_stolen_size)
+        INTEL_IVB_D_IDS(&gen6_stolen_funcs),
+        INTEL_HSW_D_IDS(&gen6_stolen_funcs),
+        INTEL_HSW_M_IDS(&gen6_stolen_funcs),
+        INTEL_BDW_M_IDS(&gen8_stolen_funcs),
+        INTEL_BDW_D_IDS(&gen8_stolen_funcs)
 };
 static void __init intel_graphics_stolen(int num, int slot, int func)
@@ -361,11 +512,13 @@ static void __init intel_graphics_stolen(int num, int slot, int func)
        for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
                if (intel_stolen_ids[i].device == device) {
-                        stolen_size_fn stolen_size =
+                        const struct intel_stolen_funcs *stolen_funcs =
-                                (stolen_size_fn)intel_stolen_ids[i].driver_data;
+                                (const struct intel_stolen_funcs *)intel_stolen_ids[i].driver_data;
-                        size = stolen_size(num, slot, func);
+                        size = stolen_funcs->size(num, slot, func);
-                        start = intel_stolen_base(num, slot, func);
+                        start = stolen_funcs->base(num, slot, func, size);
                        if (size && start) {
+                                printk(KERN_INFO "Reserving Intel graphics stolen memory at 0x%x-0x%x\n",
+                                       start, start + (u32)size - 1);
                                /* Mark this space as reserved */
                                e820_add_region(start, size, E820_RESERVED);
                                sanitize_e820_map(e820.map,
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
index e6253195a301..52819e816f87 100644
--- a/arch/x86/kernel/ftrace.c
+++ b/arch/x86/kernel/ftrace.c
@@ -308,7 +308,10 @@ static int ftrace_write(unsigned long ip, const char *val, int size)
        if (within(ip, (unsigned long)_text, (unsigned long)_etext))
                ip = (unsigned long)__va(__pa_symbol(ip));
-        return probe_kernel_write((void *)ip, val, size);
+        if (probe_kernel_write((void *)ip, val, size))
+                return -EPERM;
+        return 0;
 }
 static int add_break(unsigned long ip, const char *old)
@@ -323,10 +326,7 @@ static int add_break(unsigned long ip, const char *old)
        if (memcmp(replaced, old, MCOUNT_INSN_SIZE) != 0)
                return -EINVAL;
-        if (ftrace_write(ip, &brk, 1))
+        return ftrace_write(ip, &brk, 1);
-                return -EPERM;
-        return 0;
 }
 static int add_brk_on_call(struct dyn_ftrace *rec, unsigned long addr)
@@ -425,7 +425,7 @@ static int remove_breakpoint(struct dyn_ftrace *rec)
        /* If this does not have a breakpoint, we are done */
        if (ins[0] != brk)
-                return -1;
+                return 0;
        nop = ftrace_nop_replace();
@@ -455,7 +455,7 @@ static int remove_breakpoint(struct dyn_ftrace *rec)
        }
 update:
-        return probe_kernel_write((void *)ip, &nop[0], 1);
+        return ftrace_write(ip, nop, 1);
 }
 static int add_update_code(unsigned long ip, unsigned const char *new)
@@ -463,9 +463,7 @@ static int add_update_code(unsigned long ip, unsigned const char *new)
        /* skip breakpoint */
        ip++;
        new++;
-        if (ftrace_write(ip, new, MCOUNT_INSN_SIZE - 1))
+        return ftrace_write(ip, new, MCOUNT_INSN_SIZE - 1);
-                return -EPERM;
-        return 0;
 }
 static int add_update_call(struct dyn_ftrace *rec, unsigned long addr)
@@ -520,10 +518,7 @@ static int finish_update_call(struct dyn_ftrace *rec, unsigned long addr)
        new = ftrace_call_replace(ip, addr);
-        if (ftrace_write(ip, new, 1))
+        return ftrace_write(ip, new, 1);
-                return -EPERM;
-        return 0;
 }
 static int finish_update_nop(struct dyn_ftrace *rec)
@@ -533,9 +528,7 @@ static int finish_update_nop(struct dyn_ftrace *rec)
        new = ftrace_nop_replace();
-        if (ftrace_write(ip, new, 1))
+        return ftrace_write(ip, new, 1);
-                return -EPERM;
-        return 0;
 }
 static int finish_update(struct dyn_ftrace *rec, int enable)
@@ -632,8 +625,14 @@ void ftrace_replace_code(int enable)
        printk(KERN_WARNING "Failed on %s (%d):\n", report, count);
        for_ftrace_rec_iter(iter) {
                rec = ftrace_rec_iter_record(iter);
-                remove_breakpoint(rec);
+                /*
+                 * Breakpoints are handled only when this function is in
+                 * progress. The system could not work with them.
+                 */
+                if (remove_breakpoint(rec))
+                        BUG();
        }
+        run_sync();
 }
 static int
@@ -655,16 +654,19 @@ ftrace_modify_code(unsigned long ip, unsigned const char *old_code,
        run_sync();
        ret = ftrace_write(ip, new_code, 1);
-        if (ret) {
+        /*
-                ret = -EPERM;
+         * The breakpoint is handled only when this function is in progress.
-                goto out;
+         * The system could not work if we could not remove it.
-        }
+         */
-        run_sync();
+        BUG_ON(ret);
 out:
+        run_sync();
        return ret;
 fail_update:
-        probe_kernel_write((void *)ip, &old_code[0], 1);
+        /* Also here the system could not work with the breakpoint */
+        if (ftrace_write(ip, old_code, 1))
+                BUG();
        goto out;
 }
@@ -678,11 +680,8 @@ void arch_ftrace_update_code(int command)
        atomic_dec(&modifying_ftrace_code);
 }
-int __init ftrace_dyn_arch_init(void *data)
+int __init ftrace_dyn_arch_init(void)
 {
-        /* The return code is retured via data */
-        *(unsigned long *)data = 0;
        return 0;
 }
 #endif
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 014618dbaa7b..8d80ae011603 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -752,9 +752,7 @@ static struct clocksource clocksource_hpet = {
        .mask           = HPET_MASK,
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
        .resume         = hpet_resume_counter,
-#ifdef CONFIG_X86_64
        .archdata       = { .vclock_mode = VCLOCK_HPET },
-#endif
 };
 static int hpet_clocksource_register(void)
@@ -943,12 +941,14 @@ static __init int hpet_late_init(void)
        if (boot_cpu_has(X86_FEATURE_ARAT))
                return 0;
+        cpu_notifier_register_begin();
        for_each_online_cpu(cpu) {
                hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
        }
        /* This notifier should be called after workqueue is ready */
-        hotcpu_notifier(hpet_cpuhp_notify, -20);
+        __hotcpu_notifier(hpet_cpuhp_notify, -20);
+        cpu_notifier_register_done();
        return 0;
 }
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 42805fac0092..283a76a9cc40 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -125,7 +125,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
                seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
        seq_printf(p, "  Machine check polls\n");
 #endif
-#if defined(CONFIG_HYPERV) || defined(CONFIG_XEN)
+#if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
        seq_printf(p, "%*s: ", prec, "THR");
        for_each_online_cpu(j)
                seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count);
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index 713f1b3bad52..0331cb389d68 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -417,7 +417,6 @@ void kvm_disable_steal_time(void)
 #ifdef CONFIG_SMP
 static void __init kvm_smp_prepare_boot_cpu(void)
 {
-        WARN_ON(kvm_register_clock("primary cpu clock"));
        kvm_guest_cpu_init();
        native_smp_prepare_boot_cpu();
        kvm_spinlock_init();
diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c
index e6041094ff26..d9156ceecdff 100644
--- a/arch/x86/kernel/kvmclock.c
+++ b/arch/x86/kernel/kvmclock.c
@@ -242,7 +242,7 @@ void __init kvmclock_init(void)
        hv_clock = __va(mem);
        memset(hv_clock, 0, size);
-        if (kvm_register_clock("boot clock")) {
+        if (kvm_register_clock("primary cpu clock")) {
                hv_clock = NULL;
                memblock_free(mem, size);
                return;
diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c
index ebc987398923..af1d14a9ebda 100644
--- a/arch/x86/kernel/ldt.c
+++ b/arch/x86/kernel/ldt.c
@@ -229,6 +229,17 @@ static int write_ldt(void __user *ptr, unsigned long bytecount, int oldmode)
                }
        }
+        /*
+         * On x86-64 we do not support 16-bit segments due to
+         * IRET leaking the high bits of the kernel stack address.
+         */
+#ifdef CONFIG_X86_64
+        if (!ldt_info.seg_32bit) {
+                error = -EINVAL;
+                goto out_unlock;
+        }
+#endif
        fill_ldt(&ldt, &ldt_info);
        if (oldmode)
                ldt.avl = 0;
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index 05266b5aae22..c9603ac80de5 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -259,14 +259,15 @@ static int __init msr_init(void)
                goto out_chrdev;
        }
        msr_class->devnode = msr_devnode;
-        get_online_cpus();
+        cpu_notifier_register_begin();
        for_each_online_cpu(i) {
                err = msr_device_create(i);
                if (err != 0)
                        goto out_class;
        }
-        register_hotcpu_notifier(&msr_class_cpu_notifier);
+        __register_hotcpu_notifier(&msr_class_cpu_notifier);
-        put_online_cpus();
+        cpu_notifier_register_done();
        err = 0;
        goto out;
@@ -275,7 +276,7 @@ out_class:
        i = 0;
        for_each_online_cpu(i)
                msr_device_destroy(i);
-        put_online_cpus();
+        cpu_notifier_register_done();
        class_destroy(msr_class);
 out_chrdev:
        __unregister_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr");
@@ -286,13 +287,14 @@ out:
 static void __exit msr_exit(void)
 {
        int cpu = 0;
-        get_online_cpus();
+        cpu_notifier_register_begin();
        for_each_online_cpu(cpu)
                msr_device_destroy(cpu);
        class_destroy(msr_class);
        __unregister_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr");
-        unregister_hotcpu_notifier(&msr_class_cpu_notifier);
+        __unregister_hotcpu_notifier(&msr_class_cpu_notifier);
-        put_online_cpus();
+        cpu_notifier_register_done();
 }
 module_init(msr_init);
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index 299d49302e7d..0497f719977d 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -1207,23 +1207,31 @@ error:
        return ret;
 }
-static inline int __init determine_tce_table_size(u64 ram)
+static inline int __init determine_tce_table_size(void)
 {
        int ret;
        if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
                return specified_table_size;
-        /*
+        if (is_kdump_kernel() && saved_max_pfn) {
-         * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
+                /*
-         * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
+                 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
-         * larger table size has twice as many entries, so shift the
+                 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
-         * max ram address by 13 to divide by 8K and then look at the
+                 * larger table size has twice as many entries, so shift the
-         * order of the result to choose between 0-7.
+                 * max ram address by 13 to divide by 8K and then look at the
-         */
+                 * order of the result to choose between 0-7.
-        ret = get_order(ram >> 13);
+                 */
-        if (ret > TCE_TABLE_SIZE_8M)
+                ret = get_order((saved_max_pfn * PAGE_SIZE) >> 13);
+                if (ret > TCE_TABLE_SIZE_8M)
+                        ret = TCE_TABLE_SIZE_8M;
+        } else {
+                /*
+                 * Use 8M by default (suggested by Muli) if it's not
+                 * kdump kernel and saved_max_pfn isn't set.
+                 */
                ret = TCE_TABLE_SIZE_8M;
+        }
        return ret;
 }
@@ -1418,8 +1426,7 @@ int __init detect_calgary(void)
                return -ENOMEM;
        }
-        specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
+        specified_table_size = determine_tce_table_size();
-                                        saved_max_pfn : max_pfn) * PAGE_SIZE);
        for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
                struct calgary_bus_info *info = &bus_info[bus];
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index fa511acff7e6..09c76d265550 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -869,7 +869,6 @@ void __init setup_arch(char **cmdline_p)
 #ifdef CONFIG_X86_32
        memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data));
-        visws_early_detect();
        /*
         * copy kernel address range established so far and switch
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index cfbe99f88830..57e5ce126d5a 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -914,8 +914,7 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
                tsc_khz_ref = tsc_khz;
        }
        if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
-                        (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
+                        (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
-                        (val == CPUFREQ_RESUMECHANGE)) {
                *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
                tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
@@ -985,9 +984,7 @@ static struct clocksource clocksource_tsc = {
        .mask                   = CLOCKSOURCE_MASK(64),
        .flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
                                  CLOCK_SOURCE_MUST_VERIFY,
-#ifdef CONFIG_X86_64
        .archdata               = { .vclock_mode = VCLOCK_TSC },
-#endif
 };
 void mark_tsc_unstable(char *reason)
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index da6b35a98260..49edf2dd3613 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -147,7 +147,6 @@ SECTIONS
                _edata = .;
        } :data
-#ifdef CONFIG_X86_64
        . = ALIGN(PAGE_SIZE);
        __vvar_page = .;
@@ -165,12 +164,15 @@ SECTIONS
 #undef __VVAR_KERNEL_LDS
 #undef EMIT_VVAR
+                /*
+                 * Pad the rest of the page with zeros.  Otherwise the loader
+                 * can leave garbage here.
+                 */
+                . = __vvar_beginning_hack + PAGE_SIZE;
        } :data
       . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE);
-#endif /* CONFIG_X86_64 */
        /* Init code and data - will be freed after init */
        . = ALIGN(PAGE_SIZE);
        .init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) {
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c
index 1f96f9347ed9..8b3b3eb3cead 100644
--- a/arch/x86/kernel/vsyscall_64.c
+++ b/arch/x86/kernel/vsyscall_64.c
@@ -47,14 +47,12 @@
 #include <asm/segment.h>
 #include <asm/desc.h>
 #include <asm/topology.h>
-#include <asm/vgtod.h>
 #include <asm/traps.h>
 #define CREATE_TRACE_POINTS
 #include "vsyscall_trace.h"
 DEFINE_VVAR(int, vgetcpu_mode);
-DEFINE_VVAR(struct vsyscall_gtod_data, vsyscall_gtod_data);
 static enum { EMULATE, NATIVE, NONE } vsyscall_mode = EMULATE;
@@ -77,48 +75,6 @@ static int __init vsyscall_setup(char *str)
 }
 early_param("vsyscall", vsyscall_setup);
-void update_vsyscall_tz(void)
-{
-        vsyscall_gtod_data.sys_tz = sys_tz;
-}
-void update_vsyscall(struct timekeeper *tk)
-{
-        struct vsyscall_gtod_data *vdata = &vsyscall_gtod_data;
-        write_seqcount_begin(&vdata->seq);
-        /* copy vsyscall data */
-        vdata->clock.vclock_mode        = tk->clock->archdata.vclock_mode;
-        vdata->clock.cycle_last         = tk->clock->cycle_last;
-        vdata->clock.mask               = tk->clock->mask;
-        vdata->clock.mult               = tk->mult;
-        vdata->clock.shift              = tk->shift;
-        vdata->wall_time_sec            = tk->xtime_sec;
-        vdata->wall_time_snsec          = tk->xtime_nsec;
-        vdata->monotonic_time_sec       = tk->xtime_sec
-                                        + tk->wall_to_monotonic.tv_sec;
-        vdata->monotonic_time_snsec     = tk->xtime_nsec
-                                        + (tk->wall_to_monotonic.tv_nsec
-                                                << tk->shift);
-        while (vdata->monotonic_time_snsec >=
-                                        (((u64)NSEC_PER_SEC) << tk->shift)) {
-                vdata->monotonic_time_snsec -=
-                                        ((u64)NSEC_PER_SEC) << tk->shift;
-                vdata->monotonic_time_sec++;
-        }
-        vdata->wall_time_coarse.tv_sec  = tk->xtime_sec;
-        vdata->wall_time_coarse.tv_nsec = (long)(tk->xtime_nsec >> tk->shift);
-        vdata->monotonic_time_coarse    = timespec_add(vdata->wall_time_coarse,
-                                                        tk->wall_to_monotonic);
-        write_seqcount_end(&vdata->seq);
-}
 static void warn_bad_vsyscall(const char *level, struct pt_regs *regs,
                              const char *message)
 {
@@ -374,7 +330,6 @@ void __init map_vsyscall(void)
 {
        extern char __vsyscall_page;
        unsigned long physaddr_vsyscall = __pa_symbol(&__vsyscall_page);
-        extern char __vvar_page;
        unsigned long physaddr_vvar_page = __pa_symbol(&__vvar_page);
        __set_fixmap(VSYSCALL_FIRST_PAGE, physaddr_vsyscall,
@@ -393,9 +348,13 @@ static int __init vsyscall_init(void)
 {
        BUG_ON(VSYSCALL_ADDR(0) != __fix_to_virt(VSYSCALL_FIRST_PAGE));
+        cpu_notifier_register_begin();
        on_each_cpu(cpu_vsyscall_init, NULL, 1);
        /* notifier priority > KVM */
-        hotcpu_notifier(cpu_vsyscall_notifier, 30);
+        __hotcpu_notifier(cpu_vsyscall_notifier, 30);
+        cpu_notifier_register_done();
        return 0;
 }
diff --git a/arch/x86/kernel/vsyscall_gtod.c b/arch/x86/kernel/vsyscall_gtod.c
new file mode 100644
index 000000000000..f9c6e56e14b5
--- /dev/null
+++ b/arch/x86/kernel/vsyscall_gtod.c
@@ -0,0 +1,69 @@
+/*
+ *  Copyright (C) 2001 Andrea Arcangeli <andrea@suse.de> SuSE
+ *  Copyright 2003 Andi Kleen, SuSE Labs.
+ *
+ *  Modified for x86 32 bit architecture by
+ *  Stefani Seibold <stefani@seibold.net>
+ *  sponsored by Rohde & Schwarz GmbH & Co. KG Munich/Germany
+ *
+ *  Thanks to hpa@transmeta.com for some useful hint.
+ *  Special thanks to Ingo Molnar for his early experience with
+ *  a different vsyscall implementation for Linux/IA32 and for the name.
+ *
+ */
+#include <linux/timekeeper_internal.h>
+#include <asm/vgtod.h>
+#include <asm/vvar.h>
+DEFINE_VVAR(struct vsyscall_gtod_data, vsyscall_gtod_data);
+void update_vsyscall_tz(void)
+{
+        vsyscall_gtod_data.tz_minuteswest = sys_tz.tz_minuteswest;
+        vsyscall_gtod_data.tz_dsttime = sys_tz.tz_dsttime;
+}
+void update_vsyscall(struct timekeeper *tk)
+{
+        struct vsyscall_gtod_data *vdata = &vsyscall_gtod_data;
+        gtod_write_begin(vdata);
+        /* copy vsyscall data */
+        vdata->vclock_mode      = tk->clock->archdata.vclock_mode;
+        vdata->cycle_last       = tk->clock->cycle_last;
+        vdata->mask             = tk->clock->mask;
+        vdata->mult             = tk->mult;
+        vdata->shift            = tk->shift;
+        vdata->wall_time_sec            = tk->xtime_sec;
+        vdata->wall_time_snsec          = tk->xtime_nsec;
+        vdata->monotonic_time_sec       = tk->xtime_sec
+                                        + tk->wall_to_monotonic.tv_sec;
+        vdata->monotonic_time_snsec     = tk->xtime_nsec
+                                        + (tk->wall_to_monotonic.tv_nsec
+                                                << tk->shift);
+        while (vdata->monotonic_time_snsec >=
+                                        (((u64)NSEC_PER_SEC) << tk->shift)) {
+                vdata->monotonic_time_snsec -=
+                                        ((u64)NSEC_PER_SEC) << tk->shift;
+                vdata->monotonic_time_sec++;
+        }
+        vdata->wall_time_coarse_sec     = tk->xtime_sec;
+        vdata->wall_time_coarse_nsec    = (long)(tk->xtime_nsec >> tk->shift);
+        vdata->monotonic_time_coarse_sec =
+                vdata->wall_time_coarse_sec + tk->wall_to_monotonic.tv_sec;
+        vdata->monotonic_time_coarse_nsec =
+                vdata->wall_time_coarse_nsec + tk->wall_to_monotonic.tv_nsec;
+        while (vdata->monotonic_time_coarse_nsec >= NSEC_PER_SEC) {
+                vdata->monotonic_time_coarse_nsec -= NSEC_PER_SEC;
+                vdata->monotonic_time_coarse_sec++;
+        }
+        gtod_write_end(vdata);
+}
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index e5503d8aec1d..bea60671ef8a 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -28,7 +28,7 @@ static u32 xstate_required_size(u64 xstate_bv)
        int feature_bit = 0;
        u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
-        xstate_bv &= ~XSTATE_FPSSE;
+        xstate_bv &= XSTATE_EXTEND_MASK;
        while (xstate_bv) {
                if (xstate_bv & 0x1) {
                        u32 eax, ebx, ecx, edx;
@@ -43,6 +43,16 @@ static u32 xstate_required_size(u64 xstate_bv)
        return ret;
 }
+u64 kvm_supported_xcr0(void)
+{
+        u64 xcr0 = KVM_SUPPORTED_XCR0 & host_xcr0;
+        if (!kvm_x86_ops->mpx_supported())
+                xcr0 &= ~(XSTATE_BNDREGS | XSTATE_BNDCSR);
+        return xcr0;
+}
 void kvm_update_cpuid(struct kvm_vcpu *vcpu)
 {
        struct kvm_cpuid_entry2 *best;
@@ -73,9 +83,9 @@ void kvm_update_cpuid(struct kvm_vcpu *vcpu)
        } else {
                vcpu->arch.guest_supported_xcr0 =
                        (best->eax | ((u64)best->edx << 32)) &
-                        host_xcr0 & KVM_SUPPORTED_XCR0;
+                        kvm_supported_xcr0();
-                vcpu->arch.guest_xstate_size =
+                vcpu->arch.guest_xstate_size = best->ebx =
-                        xstate_required_size(vcpu->arch.guest_supported_xcr0);
+                        xstate_required_size(vcpu->arch.xcr0);
        }
        kvm_pmu_cpuid_update(vcpu);
@@ -210,13 +220,6 @@ static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
        entry->flags = 0;
 }
-static bool supported_xcr0_bit(unsigned bit)
-{
-        u64 mask = ((u64)1 << bit);
-        return mask & KVM_SUPPORTED_XCR0 & host_xcr0;
-}
 #define F(x) bit(X86_FEATURE_##x)
 static int __do_cpuid_ent_emulated(struct kvm_cpuid_entry2 *entry,
@@ -256,6 +259,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 #endif
        unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
        unsigned f_invpcid = kvm_x86_ops->invpcid_supported() ? F(INVPCID) : 0;
+        unsigned f_mpx = kvm_x86_ops->mpx_supported() ? F(MPX) : 0;
        /* cpuid 1.edx */
        const u32 kvm_supported_word0_x86_features =
@@ -303,7 +307,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
        /* cpuid 7.0.ebx */
        const u32 kvm_supported_word9_x86_features =
                F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
-                F(BMI2) | F(ERMS) | f_invpcid | F(RTM);
+                F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | f_mpx | F(RDSEED) |
+                F(ADX);
        /* all calls to cpuid_count() should be made on the same cpu */
        get_cpu();
@@ -436,16 +441,18 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
        }
        case 0xd: {
                int idx, i;
+                u64 supported = kvm_supported_xcr0();
-                entry->eax &= host_xcr0 & KVM_SUPPORTED_XCR0;
+                entry->eax &= supported;
-                entry->edx &= (host_xcr0 & KVM_SUPPORTED_XCR0) >> 32;
+                entry->edx &= supported >> 32;
                entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
                for (idx = 1, i = 1; idx < 64; ++idx) {
+                        u64 mask = ((u64)1 << idx);
                        if (*nent >= maxnent)
                                goto out;
                        do_cpuid_1_ent(&entry[i], function, idx);
-                        if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
+                        if (entry[i].eax == 0 || !(supported & mask))
                                continue;
                        entry[i].flags |=
                               KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 07ffca0a89e9..205b17eed93c 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -3668,6 +3668,10 @@ static const struct gprefix pfx_vmovntpx = {
        I(0, em_mov), N, N, N,
 };
+static const struct gprefix pfx_0f_28_0f_29 = {
+        I(Aligned, em_mov), I(Aligned, em_mov), N, N,
+};
 static const struct escape escape_d9 = { {
        N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
 }, {
@@ -3870,7 +3874,9 @@ static const struct opcode twobyte_table[256] = {
        IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
        IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
        N, N, N, N,
-        N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
+        GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
+        GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
+        N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
        N, N, N, N,
        /* 0x30 - 0x3F */
        II(ImplicitOps | Priv, em_wrmsr, wrmsr),
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 9b531351a587..f5704d9e5ddc 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -3329,7 +3329,7 @@ static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
        arch.direct_map = vcpu->arch.mmu.direct_map;
        arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
-        return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
+        return kvm_setup_async_pf(vcpu, gva, gfn_to_hva(vcpu->kvm, gfn), &arch);
 }
 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index cba218a2f08d..b1e6c1bf68d3 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -913,7 +913,8 @@ static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
 *   and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
 *   used by guest then tlbs are not flushed, so guest is allowed to access the
 *   freed pages.
- *   And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
+ *   We set tlbs_dirty to let the notifier know this change and delay the flush
+ *   until such a case actually happens.
 */
 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 {
@@ -942,7 +943,7 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
                        return -EINVAL;
                if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
-                        vcpu->kvm->tlbs_dirty++;
+                        vcpu->kvm->tlbs_dirty = true;
                        continue;
                }
@@ -957,7 +958,7 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
                if (gfn != sp->gfns[i]) {
                        drop_spte(vcpu->kvm, &sp->spt[i]);
-                        vcpu->kvm->tlbs_dirty++;
+                        vcpu->kvm->tlbs_dirty = true;
                        continue;
                }
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 2de1bc09a8d4..7f4f9c2badae 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -34,6 +34,7 @@
 #include <asm/perf_event.h>
 #include <asm/tlbflush.h>
 #include <asm/desc.h>
+#include <asm/debugreg.h>
 #include <asm/kvm_para.h>
 #include <asm/virtext.h>
@@ -303,20 +304,35 @@ static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
        return vmcb->control.intercept_cr & (1U << bit);
 }
-static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
+static inline void set_dr_intercepts(struct vcpu_svm *svm)
 {
        struct vmcb *vmcb = get_host_vmcb(svm);
-        vmcb->control.intercept_dr |= (1U << bit);
+        vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
+                | (1 << INTERCEPT_DR1_READ)
+                | (1 << INTERCEPT_DR2_READ)
+                | (1 << INTERCEPT_DR3_READ)
+                | (1 << INTERCEPT_DR4_READ)
+                | (1 << INTERCEPT_DR5_READ)
+                | (1 << INTERCEPT_DR6_READ)
+                | (1 << INTERCEPT_DR7_READ)
+                | (1 << INTERCEPT_DR0_WRITE)
+                | (1 << INTERCEPT_DR1_WRITE)
+                | (1 << INTERCEPT_DR2_WRITE)
+                | (1 << INTERCEPT_DR3_WRITE)
+                | (1 << INTERCEPT_DR4_WRITE)
+                | (1 << INTERCEPT_DR5_WRITE)
+                | (1 << INTERCEPT_DR6_WRITE)
+                | (1 << INTERCEPT_DR7_WRITE);
        recalc_intercepts(svm);
 }
-static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
+static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 {
        struct vmcb *vmcb = get_host_vmcb(svm);
-        vmcb->control.intercept_dr &= ~(1U << bit);
+        vmcb->control.intercept_dr = 0;
        recalc_intercepts(svm);
 }
@@ -1080,23 +1096,7 @@ static void init_vmcb(struct vcpu_svm *svm)
        set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
        set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
-        set_dr_intercept(svm, INTERCEPT_DR0_READ);
+        set_dr_intercepts(svm);
-        set_dr_intercept(svm, INTERCEPT_DR1_READ);
-        set_dr_intercept(svm, INTERCEPT_DR2_READ);
-        set_dr_intercept(svm, INTERCEPT_DR3_READ);
-        set_dr_intercept(svm, INTERCEPT_DR4_READ);
-        set_dr_intercept(svm, INTERCEPT_DR5_READ);
-        set_dr_intercept(svm, INTERCEPT_DR6_READ);
-        set_dr_intercept(svm, INTERCEPT_DR7_READ);
-        set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
-        set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
-        set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
-        set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
-        set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
-        set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
-        set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
-        set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
        set_exception_intercept(svm, PF_VECTOR);
        set_exception_intercept(svm, UD_VECTOR);
@@ -1684,6 +1684,21 @@ static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
        mark_dirty(svm->vmcb, VMCB_DR);
 }
+static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
+{
+        struct vcpu_svm *svm = to_svm(vcpu);
+        get_debugreg(vcpu->arch.db[0], 0);
+        get_debugreg(vcpu->arch.db[1], 1);
+        get_debugreg(vcpu->arch.db[2], 2);
+        get_debugreg(vcpu->arch.db[3], 3);
+        vcpu->arch.dr6 = svm_get_dr6(vcpu);
+        vcpu->arch.dr7 = svm->vmcb->save.dr7;
+        vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
+        set_dr_intercepts(svm);
+}
 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
 {
        struct vcpu_svm *svm = to_svm(vcpu);
@@ -2842,6 +2857,7 @@ static int iret_interception(struct vcpu_svm *svm)
        clr_intercept(svm, INTERCEPT_IRET);
        svm->vcpu.arch.hflags |= HF_IRET_MASK;
        svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
+        kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
        return 1;
 }
@@ -2974,6 +2990,17 @@ static int dr_interception(struct vcpu_svm *svm)
        unsigned long val;
        int err;
+        if (svm->vcpu.guest_debug == 0) {
+                /*
+                 * No more DR vmexits; force a reload of the debug registers
+                 * and reenter on this instruction.  The next vmexit will
+                 * retrieve the full state of the debug registers.
+                 */
+                clr_dr_intercepts(svm);
+                svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
+                return 1;
+        }
        if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
                return emulate_on_interception(svm);
@@ -3649,7 +3676,7 @@ static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
        return ret;
 }
-static int enable_irq_window(struct kvm_vcpu *vcpu)
+static void enable_irq_window(struct kvm_vcpu *vcpu)
 {
        struct vcpu_svm *svm = to_svm(vcpu);
@@ -3663,16 +3690,15 @@ static int enable_irq_window(struct kvm_vcpu *vcpu)
                svm_set_vintr(svm);
                svm_inject_irq(svm, 0x0);
        }
-        return 0;
 }
-static int enable_nmi_window(struct kvm_vcpu *vcpu)
+static void enable_nmi_window(struct kvm_vcpu *vcpu)
 {
        struct vcpu_svm *svm = to_svm(vcpu);
        if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
            == HF_NMI_MASK)
-                return 0; /* IRET will cause a vm exit */
+                return; /* IRET will cause a vm exit */
        /*
         * Something prevents NMI from been injected. Single step over possible
@@ -3681,7 +3707,6 @@ static int enable_nmi_window(struct kvm_vcpu *vcpu)
        svm->nmi_singlestep = true;
        svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
        update_db_bp_intercept(vcpu);
-        return 0;
 }
 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
@@ -4064,6 +4089,11 @@ static bool svm_invpcid_supported(void)
        return false;
 }
+static bool svm_mpx_supported(void)
+{
+        return false;
+}
 static bool svm_has_wbinvd_exit(void)
 {
        return true;
@@ -4302,6 +4332,7 @@ static struct kvm_x86_ops svm_x86_ops = {
        .get_dr6 = svm_get_dr6,
        .set_dr6 = svm_set_dr6,
        .set_dr7 = svm_set_dr7,
+        .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
        .cache_reg = svm_cache_reg,
        .get_rflags = svm_get_rflags,
        .set_rflags = svm_set_rflags,
@@ -4345,6 +4376,7 @@ static struct kvm_x86_ops svm_x86_ops = {
        .rdtscp_supported = svm_rdtscp_supported,
        .invpcid_supported = svm_invpcid_supported,
+        .mpx_supported = svm_mpx_supported,
        .set_supported_cpuid = svm_set_supported_cpuid,
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 392752834751..1320e0f8e611 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -31,6 +31,7 @@
 #include <linux/ftrace_event.h>
 #include <linux/slab.h>
 #include <linux/tboot.h>
+#include <linux/hrtimer.h>
 #include "kvm_cache_regs.h"
 #include "x86.h"
@@ -42,6 +43,7 @@
 #include <asm/i387.h>
 #include <asm/xcr.h>
 #include <asm/perf_event.h>
+#include <asm/debugreg.h>
 #include <asm/kexec.h>
 #include "trace.h"
@@ -110,6 +112,8 @@ module_param(nested, bool, S_IRUGO);
 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
+#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 /*
 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 * ple_gap:    upper bound on the amount of time between two successive
@@ -202,6 +206,7 @@ struct __packed vmcs12 {
        u64 guest_pdptr1;
        u64 guest_pdptr2;
        u64 guest_pdptr3;
+        u64 guest_bndcfgs;
        u64 host_ia32_pat;
        u64 host_ia32_efer;
        u64 host_ia32_perf_global_ctrl;
@@ -374,6 +379,9 @@ struct nested_vmx {
         */
        struct page *apic_access_page;
        u64 msr_ia32_feature_control;
+        struct hrtimer preemption_timer;
+        bool preemption_timer_expired;
 };
 #define POSTED_INTR_ON  0
@@ -441,6 +449,7 @@ struct vcpu_vmx {
 #endif
                int           gs_ldt_reload_needed;
                int           fs_reload_needed;
+                u64           msr_host_bndcfgs;
        } host_state;
        struct {
                int vm86_active;
@@ -533,6 +542,7 @@ static const unsigned long shadow_read_write_fields[] = {
        GUEST_CS_LIMIT,
        GUEST_CS_BASE,
        GUEST_ES_BASE,
+        GUEST_BNDCFGS,
        CR0_GUEST_HOST_MASK,
        CR0_READ_SHADOW,
        CR4_READ_SHADOW,
@@ -588,6 +598,7 @@ static const unsigned short vmcs_field_to_offset_table[] = {
        FIELD64(GUEST_PDPTR1, guest_pdptr1),
        FIELD64(GUEST_PDPTR2, guest_pdptr2),
        FIELD64(GUEST_PDPTR3, guest_pdptr3),
+        FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
        FIELD64(HOST_IA32_PAT, host_ia32_pat),
        FIELD64(HOST_IA32_EFER, host_ia32_efer),
        FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
@@ -718,6 +729,7 @@ static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 static u64 construct_eptp(unsigned long root_hpa);
 static void kvm_cpu_vmxon(u64 addr);
 static void kvm_cpu_vmxoff(void);
+static bool vmx_mpx_supported(void);
 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 static void vmx_set_segment(struct kvm_vcpu *vcpu,
                            struct kvm_segment *var, int seg);
@@ -728,6 +740,7 @@ static u32 vmx_segment_access_rights(struct kvm_segment *var);
 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
+static bool vmx_mpx_supported(void);
 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
@@ -1047,6 +1060,12 @@ static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
        return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 }
+static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
+{
+        return vmcs12->pin_based_vm_exec_control &
+                PIN_BASED_VMX_PREEMPTION_TIMER;
+}
 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
 {
        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
@@ -1710,6 +1729,8 @@ static void vmx_save_host_state(struct kvm_vcpu *vcpu)
        if (is_long_mode(&vmx->vcpu))
                wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 #endif
+        if (boot_cpu_has(X86_FEATURE_MPX))
+                rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
        for (i = 0; i < vmx->save_nmsrs; ++i)
                kvm_set_shared_msr(vmx->guest_msrs[i].index,
                                   vmx->guest_msrs[i].data,
@@ -1747,6 +1768,8 @@ static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 #ifdef CONFIG_X86_64
        wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 #endif
+        if (vmx->host_state.msr_host_bndcfgs)
+                wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
        /*
         * If the FPU is not active (through the host task or
         * the guest vcpu), then restore the cr0.TS bit.
@@ -2248,9 +2271,9 @@ static __init void nested_vmx_setup_ctls_msrs(void)
         */
        nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
        nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
-                PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
+                PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
+        nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
                PIN_BASED_VMX_PREEMPTION_TIMER;
-        nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
        /*
         * Exit controls
@@ -2265,15 +2288,12 @@ static __init void nested_vmx_setup_ctls_msrs(void)
 #ifdef CONFIG_X86_64
                VM_EXIT_HOST_ADDR_SPACE_SIZE |
 #endif
-                VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
+                VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
+        nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
+                VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
                VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
-        if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
+        if (vmx_mpx_supported())
-            !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
+                nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
-                nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
-                nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
-        }
-        nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
-                VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
        /* entry controls */
        rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
@@ -2287,6 +2307,8 @@ static __init void nested_vmx_setup_ctls_msrs(void)
                VM_ENTRY_LOAD_IA32_PAT;
        nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
                                       VM_ENTRY_LOAD_IA32_EFER);
+        if (vmx_mpx_supported())
+                nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
        /* cpu-based controls */
        rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
@@ -2342,9 +2364,9 @@ static __init void nested_vmx_setup_ctls_msrs(void)
        /* miscellaneous data */
        rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
-        nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
+        nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
-                VMX_MISC_SAVE_EFER_LMA;
+        nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
-        nested_vmx_misc_low |= VMX_MISC_ACTIVITY_HLT;
+                VMX_MISC_ACTIVITY_HLT;
        nested_vmx_misc_high = 0;
 }
@@ -2479,6 +2501,11 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
        case MSR_IA32_SYSENTER_ESP:
                data = vmcs_readl(GUEST_SYSENTER_ESP);
                break;
+        case MSR_IA32_BNDCFGS:
+                if (!vmx_mpx_supported())
+                        return 1;
+                data = vmcs_read64(GUEST_BNDCFGS);
+                break;
        case MSR_IA32_FEATURE_CONTROL:
                if (!nested_vmx_allowed(vcpu))
                        return 1;
@@ -2547,6 +2574,11 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
        case MSR_IA32_SYSENTER_ESP:
                vmcs_writel(GUEST_SYSENTER_ESP, data);
                break;
+        case MSR_IA32_BNDCFGS:
+                if (!vmx_mpx_supported())
+                        return 1;
+                vmcs_write64(GUEST_BNDCFGS, data);
+                break;
        case MSR_IA32_TSC:
                kvm_write_tsc(vcpu, msr_info);
                break;
@@ -2832,12 +2864,12 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
                      vmx_capability.ept, vmx_capability.vpid);
        }
-        min = 0;
+        min = VM_EXIT_SAVE_DEBUG_CONTROLS;
 #ifdef CONFIG_X86_64
        min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
 #endif
        opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
-                VM_EXIT_ACK_INTR_ON_EXIT;
+                VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
        if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
                                &_vmexit_control) < 0)
                return -EIO;
@@ -2853,8 +2885,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
                !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
                _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
-        min = 0;
+        min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
-        opt = VM_ENTRY_LOAD_IA32_PAT;
+        opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
        if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
                                &_vmentry_control) < 0)
                return -EIO;
@@ -4223,6 +4255,10 @@ static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
 {
        u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
+        if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
+                exec_control &= ~CPU_BASED_MOV_DR_EXITING;
        if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
                exec_control &= ~CPU_BASED_TPR_SHADOW;
 #ifdef CONFIG_X86_64
@@ -4496,39 +4532,28 @@ static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
                PIN_BASED_NMI_EXITING;
 }
-static int enable_irq_window(struct kvm_vcpu *vcpu)
+static void enable_irq_window(struct kvm_vcpu *vcpu)
 {
        u32 cpu_based_vm_exec_control;
-        if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
-                /*
-                 * We get here if vmx_interrupt_allowed() said we can't
-                 * inject to L1 now because L2 must run. The caller will have
-                 * to make L2 exit right after entry, so we can inject to L1
-                 * more promptly.
-                 */
-                return -EBUSY;
        cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
        cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
        vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
-        return 0;
 }
-static int enable_nmi_window(struct kvm_vcpu *vcpu)
+static void enable_nmi_window(struct kvm_vcpu *vcpu)
 {
        u32 cpu_based_vm_exec_control;
-        if (!cpu_has_virtual_nmis())
+        if (!cpu_has_virtual_nmis() ||
-                return enable_irq_window(vcpu);
+            vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
+                enable_irq_window(vcpu);
-        if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
+                return;
-                return enable_irq_window(vcpu);
+        }
        cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
        cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
        vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
-        return 0;
 }
 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
@@ -4620,22 +4645,8 @@ static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
 {
-        if (is_guest_mode(vcpu)) {
+        if (to_vmx(vcpu)->nested.nested_run_pending)
-                if (to_vmx(vcpu)->nested.nested_run_pending)
+                return 0;
-                        return 0;
-                if (nested_exit_on_nmi(vcpu)) {
-                        nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
-                                          NMI_VECTOR | INTR_TYPE_NMI_INTR |
-                                          INTR_INFO_VALID_MASK, 0);
-                        /*
-                         * The NMI-triggered VM exit counts as injection:
-                         * clear this one and block further NMIs.
-                         */
-                        vcpu->arch.nmi_pending = 0;
-                        vmx_set_nmi_mask(vcpu, true);
-                        return 0;
-                }
-        }
        if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
                return 0;
@@ -4647,19 +4658,8 @@ static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
 {
-        if (is_guest_mode(vcpu)) {
+        return (!to_vmx(vcpu)->nested.nested_run_pending &&
-                if (to_vmx(vcpu)->nested.nested_run_pending)
+                vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
-                        return 0;
-                if (nested_exit_on_intr(vcpu)) {
-                        nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT,
-                                          0, 0);
-                        /*
-                         * fall through to normal code, but now in L1, not L2
-                         */
-                }
-        }
-        return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
                !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
                        (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
 }
@@ -5102,6 +5102,22 @@ static int handle_dr(struct kvm_vcpu *vcpu)
                }
        }
+        if (vcpu->guest_debug == 0) {
+                u32 cpu_based_vm_exec_control;
+                cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
+                cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
+                vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
+                /*
+                 * No more DR vmexits; force a reload of the debug registers
+                 * and reenter on this instruction.  The next vmexit will
+                 * retrieve the full state of the debug registers.
+                 */
+                vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
+                return 1;
+        }
        exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
        dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
        reg = DEBUG_REG_ACCESS_REG(exit_qualification);
@@ -5128,6 +5144,24 @@ static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
 {
 }
+static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
+{
+        u32 cpu_based_vm_exec_control;
+        get_debugreg(vcpu->arch.db[0], 0);
+        get_debugreg(vcpu->arch.db[1], 1);
+        get_debugreg(vcpu->arch.db[2], 2);
+        get_debugreg(vcpu->arch.db[3], 3);
+        get_debugreg(vcpu->arch.dr6, 6);
+        vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
+        vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
+        cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
+        cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
+        vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
+}
 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
 {
        vmcs_writel(GUEST_DR7, val);
@@ -5727,6 +5761,18 @@ static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
         */
 }
+static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
+{
+        struct vcpu_vmx *vmx =
+                container_of(timer, struct vcpu_vmx, nested.preemption_timer);
+        vmx->nested.preemption_timer_expired = true;
+        kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
+        kvm_vcpu_kick(&vmx->vcpu);
+        return HRTIMER_NORESTART;
+}
 /*
 * Emulate the VMXON instruction.
 * Currently, we just remember that VMX is active, and do not save or even
@@ -5791,6 +5837,10 @@ static int handle_vmon(struct kvm_vcpu *vcpu)
        INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
        vmx->nested.vmcs02_num = 0;
+        hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
+                     HRTIMER_MODE_REL);
+        vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
        vmx->nested.vmxon = true;
        skip_emulated_instruction(vcpu);
@@ -6767,9 +6817,6 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
                 * table is L0's fault.
                 */
                return 0;
-        case EXIT_REASON_PREEMPTION_TIMER:
-                return vmcs12->pin_based_vm_exec_control &
-                        PIN_BASED_VMX_PREEMPTION_TIMER;
        case EXIT_REASON_WBINVD:
                return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
        case EXIT_REASON_XSETBV:
@@ -6785,27 +6832,6 @@ static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
        *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
 }
-static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
-{
-        u64 delta_tsc_l1;
-        u32 preempt_val_l1, preempt_val_l2, preempt_scale;
-        if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
-                        PIN_BASED_VMX_PREEMPTION_TIMER))
-                return;
-        preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
-                        MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
-        preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
-        delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
-                - vcpu->arch.last_guest_tsc;
-        preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
-        if (preempt_val_l2 <= preempt_val_l1)
-                preempt_val_l2 = 0;
-        else
-                preempt_val_l2 -= preempt_val_l1;
-        vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
-}
 /*
 * The guest has exited.  See if we can fix it or if we need userspace
 * assistance.
@@ -7052,6 +7078,12 @@ static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
                local_irq_enable();
 }
+static bool vmx_mpx_supported(void)
+{
+        return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
+                (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
+}
 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
 {
        u32 exit_intr_info;
@@ -7218,8 +7250,6 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
        atomic_switch_perf_msrs(vmx);
        debugctlmsr = get_debugctlmsr();
-        if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
-                nested_adjust_preemption_timer(vcpu);
        vmx->__launched = vmx->loaded_vmcs->launched;
        asm(
                /* Store host registers */
@@ -7616,6 +7646,28 @@ static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
                kvm_inject_page_fault(vcpu, fault);
 }
+static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
+{
+        u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
+        if (vcpu->arch.virtual_tsc_khz == 0)
+                return;
+        /* Make sure short timeouts reliably trigger an immediate vmexit.
+         * hrtimer_start does not guarantee this. */
+        if (preemption_timeout <= 1) {
+                vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
+                return;
+        }
+        preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
+        preemption_timeout *= 1000000;
+        do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
+        hrtimer_start(&vmx->nested.preemption_timer,
+                      ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
+}
 /*
 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
@@ -7629,7 +7681,6 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
 {
        struct vcpu_vmx *vmx = to_vmx(vcpu);
        u32 exec_control;
-        u32 exit_control;
        vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
        vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
@@ -7687,13 +7738,14 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
        vmcs_write64(VMCS_LINK_POINTER, -1ull);
-        vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
+        exec_control = vmcs12->pin_based_vm_exec_control;
-                (vmcs_config.pin_based_exec_ctrl |
+        exec_control |= vmcs_config.pin_based_exec_ctrl;
-                 vmcs12->pin_based_vm_exec_control));
+        exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
+        vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
-        if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
+        vmx->nested.preemption_timer_expired = false;
-                vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
+        if (nested_cpu_has_preemption_timer(vmcs12))
-                             vmcs12->vmx_preemption_timer_value);
+                vmx_start_preemption_timer(vcpu);
        /*
         * Whether page-faults are trapped is determined by a combination of
@@ -7721,7 +7773,7 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
                enable_ept ? vmcs12->page_fault_error_code_match : 0);
        if (cpu_has_secondary_exec_ctrls()) {
-                u32 exec_control = vmx_secondary_exec_control(vmx);
+                exec_control = vmx_secondary_exec_control(vmx);
                if (!vmx->rdtscp_enabled)
                        exec_control &= ~SECONDARY_EXEC_RDTSCP;
                /* Take the following fields only from vmcs12 */
@@ -7808,10 +7860,7 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
         * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
         * bits are further modified by vmx_set_efer() below.
         */
-        exit_control = vmcs_config.vmexit_ctrl;
+        vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
-        if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
-                exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
-        vm_exit_controls_init(vmx, exit_control);
        /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
         * emulated by vmx_set_efer(), below.
@@ -7830,6 +7879,9 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
        set_cr4_guest_host_mask(vmx);
+        if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
+                vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
        if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
                vmcs_write64(TSC_OFFSET,
                        vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
@@ -8155,6 +8207,58 @@ static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
        }
 }
+static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
+{
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
+        if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
+            vmx->nested.preemption_timer_expired) {
+                if (vmx->nested.nested_run_pending)
+                        return -EBUSY;
+                nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
+                return 0;
+        }
+        if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
+                if (vmx->nested.nested_run_pending ||
+                    vcpu->arch.interrupt.pending)
+                        return -EBUSY;
+                nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
+                                  NMI_VECTOR | INTR_TYPE_NMI_INTR |
+                                  INTR_INFO_VALID_MASK, 0);
+                /*
+                 * The NMI-triggered VM exit counts as injection:
+                 * clear this one and block further NMIs.
+                 */
+                vcpu->arch.nmi_pending = 0;
+                vmx_set_nmi_mask(vcpu, true);
+                return 0;
+        }
+        if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
+            nested_exit_on_intr(vcpu)) {
+                if (vmx->nested.nested_run_pending)
+                        return -EBUSY;
+                nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
+        }
+        return 0;
+}
+static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
+{
+        ktime_t remaining =
+                hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
+        u64 value;
+        if (ktime_to_ns(remaining) <= 0)
+                return 0;
+        value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
+        do_div(value, 1000000);
+        return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
+}
 /*
 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
@@ -8225,10 +8329,13 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
        else
                vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
-        if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
+        if (nested_cpu_has_preemption_timer(vmcs12)) {
-            (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
+                if (vmcs12->vm_exit_controls &
-                vmcs12->vmx_preemption_timer_value =
+                    VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
-                        vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
+                        vmcs12->vmx_preemption_timer_value =
+                                vmx_get_preemption_timer_value(vcpu);
+                hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
+        }
        /*
         * In some cases (usually, nested EPT), L2 is allowed to change its
@@ -8260,6 +8367,8 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
        vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
        vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
        vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
+        if (vmx_mpx_supported())
+                vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
        /* update exit information fields: */
@@ -8369,6 +8478,10 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
        vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
        vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
+        /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
+        if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
+                vmcs_write64(GUEST_BNDCFGS, 0);
        if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
                vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
                vcpu->arch.pat = vmcs12->host_ia32_pat;
@@ -8495,6 +8608,9 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
                nested_vmx_succeed(vcpu);
        if (enable_shadow_vmcs)
                vmx->nested.sync_shadow_vmcs = true;
+        /* in case we halted in L2 */
+        vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
 }
 /*
@@ -8573,6 +8689,7 @@ static struct kvm_x86_ops vmx_x86_ops = {
        .get_dr6 = vmx_get_dr6,
        .set_dr6 = vmx_set_dr6,
        .set_dr7 = vmx_set_dr7,
+        .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
        .cache_reg = vmx_cache_reg,
        .get_rflags = vmx_get_rflags,
        .set_rflags = vmx_set_rflags,
@@ -8634,6 +8751,9 @@ static struct kvm_x86_ops vmx_x86_ops = {
        .check_intercept = vmx_check_intercept,
        .handle_external_intr = vmx_handle_external_intr,
+        .mpx_supported = vmx_mpx_supported,
+        .check_nested_events = vmx_check_nested_events,
 };
 static int __init vmx_init(void)
@@ -8721,6 +8841,8 @@ static int __init vmx_init(void)
        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
+        vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
        memcpy(vmx_msr_bitmap_legacy_x2apic,
                        vmx_msr_bitmap_legacy, PAGE_SIZE);
        memcpy(vmx_msr_bitmap_longmode_x2apic,
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 2b8578432d5b..9d1b5cd4d34c 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -595,13 +595,13 @@ static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 {
-        u64 xcr0;
+        u64 xcr0 = xcr;
+        u64 old_xcr0 = vcpu->arch.xcr0;
        u64 valid_bits;
        /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
        if (index != XCR_XFEATURE_ENABLED_MASK)
                return 1;
-        xcr0 = xcr;
        if (!(xcr0 & XSTATE_FP))
                return 1;
        if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
@@ -616,8 +616,14 @@ int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
        if (xcr0 & ~valid_bits)
                return 1;
+        if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
+                return 1;
        kvm_put_guest_xcr0(vcpu);
        vcpu->arch.xcr0 = xcr0;
+        if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
+                kvm_update_cpuid(vcpu);
        return 0;
 }
@@ -753,7 +759,9 @@ static void kvm_update_dr7(struct kvm_vcpu *vcpu)
        else
                dr7 = vcpu->arch.dr7;
        kvm_x86_ops->set_dr7(vcpu, dr7);
-        vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
+        vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
+        if (dr7 & DR7_BP_EN_MASK)
+                vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
 }
 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
@@ -879,7 +887,7 @@ static u32 msrs_to_save[] = {
        MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
 #endif
        MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
-        MSR_IA32_FEATURE_CONTROL
+        MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
 };
 static unsigned num_msrs_to_save;
@@ -1581,7 +1589,6 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
        /* With all the info we got, fill in the values */
        vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
        vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
-        vcpu->last_kernel_ns = kernel_ns;
        vcpu->last_guest_tsc = tsc_timestamp;
        /*
@@ -1623,14 +1630,21 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
 * the others.
 *
 * So in those cases, request a kvmclock update for all vcpus.
- * The worst case for a remote vcpu to update its kvmclock
+ * We need to rate-limit these requests though, as they can
- * is then bounded by maximum nohz sleep latency.
+ * considerably slow guests that have a large number of vcpus.
+ * The time for a remote vcpu to update its kvmclock is bound
+ * by the delay we use to rate-limit the updates.
 */
-static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
+#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
+static void kvmclock_update_fn(struct work_struct *work)
 {
        int i;
-        struct kvm *kvm = v->kvm;
+        struct delayed_work *dwork = to_delayed_work(work);
+        struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
+                                           kvmclock_update_work);
+        struct kvm *kvm = container_of(ka, struct kvm, arch);
        struct kvm_vcpu *vcpu;
        kvm_for_each_vcpu(i, vcpu, kvm) {
@@ -1639,6 +1653,29 @@ static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
        }
 }
+static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
+{
+        struct kvm *kvm = v->kvm;
+        set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
+        schedule_delayed_work(&kvm->arch.kvmclock_update_work,
+                                        KVMCLOCK_UPDATE_DELAY);
+}
+#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
+static void kvmclock_sync_fn(struct work_struct *work)
+{
+        struct delayed_work *dwork = to_delayed_work(work);
+        struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
+                                           kvmclock_sync_work);
+        struct kvm *kvm = container_of(ka, struct kvm, arch);
+        schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
+        schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
+                                        KVMCLOCK_SYNC_PERIOD);
+}
 static bool msr_mtrr_valid(unsigned msr)
 {
        switch (msr) {
@@ -2323,9 +2360,12 @@ static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
        case HV_X64_MSR_VP_INDEX: {
                int r;
                struct kvm_vcpu *v;
-                kvm_for_each_vcpu(r, v, vcpu->kvm)
+                kvm_for_each_vcpu(r, v, vcpu->kvm) {
-                        if (v == vcpu)
+                        if (v == vcpu) {
                                data = r;
+                                break;
+                        }
+                }
                break;
        }
        case HV_X64_MSR_EOI:
@@ -2617,6 +2657,7 @@ int kvm_dev_ioctl_check_extension(long ext)
        case KVM_CAP_KVMCLOCK_CTRL:
        case KVM_CAP_READONLY_MEM:
        case KVM_CAP_HYPERV_TIME:
+        case KVM_CAP_IOAPIC_POLARITY_IGNORED:
 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
        case KVM_CAP_ASSIGN_DEV_IRQ:
        case KVM_CAP_PCI_2_3:
@@ -3043,9 +3084,7 @@ static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
                 * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
                 * with old userspace.
                 */
-                if (xstate_bv & ~KVM_SUPPORTED_XCR0)
+                if (xstate_bv & ~kvm_supported_xcr0())
-                        return -EINVAL;
-                if (xstate_bv & ~host_xcr0)
                        return -EINVAL;
                memcpy(&vcpu->arch.guest_fpu.state->xsave,
                        guest_xsave->region, vcpu->arch.guest_xstate_size);
@@ -3898,6 +3937,23 @@ static void kvm_init_msr_list(void)
        for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
                if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
                        continue;
+                /*
+                 * Even MSRs that are valid in the host may not be exposed
+                 * to the guests in some cases.  We could work around this
+                 * in VMX with the generic MSR save/load machinery, but it
+                 * is not really worthwhile since it will really only
+                 * happen with nested virtualization.
+                 */
+                switch (msrs_to_save[i]) {
+                case MSR_IA32_BNDCFGS:
+                        if (!kvm_x86_ops->mpx_supported())
+                                continue;
+                        break;
+                default:
+                        break;
+                }
                if (j < i)
                        msrs_to_save[j] = msrs_to_save[i];
                j++;
@@ -4394,6 +4450,7 @@ static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
        if (!exchanged)
                return X86EMUL_CMPXCHG_FAILED;
+        mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
        kvm_mmu_pte_write(vcpu, gpa, new, bytes);
        return X86EMUL_CONTINUE;
@@ -5365,7 +5422,8 @@ static void kvm_timer_init(void)
        int cpu;
        max_tsc_khz = tsc_khz;
-        register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
+        cpu_notifier_register_begin();
        if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
 #ifdef CONFIG_CPU_FREQ
                struct cpufreq_policy policy;
@@ -5382,6 +5440,10 @@ static void kvm_timer_init(void)
        pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
        for_each_online_cpu(cpu)
                smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
+        __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
+        cpu_notifier_register_done();
 }
 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
@@ -5537,9 +5599,10 @@ int kvm_arch_init(void *opaque)
                goto out_free_percpu;
        kvm_set_mmio_spte_mask();
-        kvm_init_msr_list();
        kvm_x86_ops = ops;
+        kvm_init_msr_list();
        kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
                        PT_DIRTY_MASK, PT64_NX_MASK, 0);
@@ -5782,8 +5845,10 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu)
        kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
 }
-static void inject_pending_event(struct kvm_vcpu *vcpu)
+static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
 {
+        int r;
        /* try to reinject previous events if any */
        if (vcpu->arch.exception.pending) {
                trace_kvm_inj_exception(vcpu->arch.exception.nr,
@@ -5793,17 +5858,23 @@ static void inject_pending_event(struct kvm_vcpu *vcpu)
                                          vcpu->arch.exception.has_error_code,
                                          vcpu->arch.exception.error_code,
                                          vcpu->arch.exception.reinject);
-                return;
+                return 0;
        }
        if (vcpu->arch.nmi_injected) {
                kvm_x86_ops->set_nmi(vcpu);
-                return;
+                return 0;
        }
        if (vcpu->arch.interrupt.pending) {
                kvm_x86_ops->set_irq(vcpu);
-                return;
+                return 0;
+        }
+        if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
+                r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
+                if (r != 0)
+                        return r;
        }
        /* try to inject new event if pending */
@@ -5820,6 +5891,7 @@ static void inject_pending_event(struct kvm_vcpu *vcpu)
                        kvm_x86_ops->set_irq(vcpu);
                }
        }
+        return 0;
 }
 static void process_nmi(struct kvm_vcpu *vcpu)
@@ -5924,15 +5996,13 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
                        goto out;
                }
-                inject_pending_event(vcpu);
+                if (inject_pending_event(vcpu, req_int_win) != 0)
+                        req_immediate_exit = true;
                /* enable NMI/IRQ window open exits if needed */
-                if (vcpu->arch.nmi_pending)
+                else if (vcpu->arch.nmi_pending)
-                        req_immediate_exit =
+                        kvm_x86_ops->enable_nmi_window(vcpu);
-                                kvm_x86_ops->enable_nmi_window(vcpu) != 0;
                else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
-                        req_immediate_exit =
+                        kvm_x86_ops->enable_irq_window(vcpu);
-                                kvm_x86_ops->enable_irq_window(vcpu) != 0;
                if (kvm_lapic_enabled(vcpu)) {
                        /*
@@ -5992,12 +6062,28 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
                set_debugreg(vcpu->arch.eff_db[1], 1);
                set_debugreg(vcpu->arch.eff_db[2], 2);
                set_debugreg(vcpu->arch.eff_db[3], 3);
+                set_debugreg(vcpu->arch.dr6, 6);
        }
        trace_kvm_entry(vcpu->vcpu_id);
        kvm_x86_ops->run(vcpu);
        /*
+         * Do this here before restoring debug registers on the host.  And
+         * since we do this before handling the vmexit, a DR access vmexit
+         * can (a) read the correct value of the debug registers, (b) set
+         * KVM_DEBUGREG_WONT_EXIT again.
+         */
+        if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
+                int i;
+                WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
+                kvm_x86_ops->sync_dirty_debug_regs(vcpu);
+                for (i = 0; i < KVM_NR_DB_REGS; i++)
+                        vcpu->arch.eff_db[i] = vcpu->arch.db[i];
+        }
+        /*
         * If the guest has used debug registers, at least dr7
         * will be disabled while returning to the host.
         * If we don't have active breakpoints in the host, we don't
@@ -6711,6 +6797,7 @@ int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
 {
        int r;
        struct msr_data msr;
+        struct kvm *kvm = vcpu->kvm;
        r = vcpu_load(vcpu);
        if (r)
@@ -6721,6 +6808,9 @@ int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
        kvm_write_tsc(vcpu, &msr);
        vcpu_put(vcpu);
+        schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
+                                        KVMCLOCK_SYNC_PERIOD);
        return r;
 }
@@ -7013,6 +7103,9 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
        pvclock_update_vm_gtod_copy(kvm);
+        INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
+        INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
        return 0;
 }
@@ -7050,6 +7143,8 @@ static void kvm_free_vcpus(struct kvm *kvm)
 void kvm_arch_sync_events(struct kvm *kvm)
 {
+        cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
+        cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
        kvm_free_all_assigned_devices(kvm);
        kvm_free_pit(kvm);
 }
@@ -7248,6 +7343,9 @@ void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 {
+        if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
+                kvm_x86_ops->check_nested_events(vcpu, false);
        return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
                !vcpu->arch.apf.halted)
                || !list_empty_careful(&vcpu->async_pf.done)
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index 8da5823bcde6..8c97bac9a895 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -122,9 +122,12 @@ int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
        gva_t addr, void *val, unsigned int bytes,
        struct x86_exception *exception);
-#define KVM_SUPPORTED_XCR0      (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+#define KVM_SUPPORTED_XCR0     (XSTATE_FP | XSTATE_SSE | XSTATE_YMM \
+                                | XSTATE_BNDREGS | XSTATE_BNDCSR)
 extern u64 host_xcr0;
+extern u64 kvm_supported_xcr0(void);
 extern unsigned int min_timer_period_us;
 extern struct static_key kvm_no_apic_vcpu;
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 799580cabc78..597ac155c91c 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -328,17 +328,6 @@ void unxlate_dev_mem_ptr(unsigned long phys, void *addr)
        return;
 }
-static int __initdata early_ioremap_debug;
-static int __init early_ioremap_debug_setup(char *str)
-{
-        early_ioremap_debug = 1;
-        return 0;
-}
-early_param("early_ioremap_debug", early_ioremap_debug_setup);
-static __initdata int after_paging_init;
 static pte_t bm_pte[PAGE_SIZE/sizeof(pte_t)] __page_aligned_bss;
 static inline pmd_t * __init early_ioremap_pmd(unsigned long addr)
@@ -362,18 +351,11 @@ bool __init is_early_ioremap_ptep(pte_t *ptep)
        return ptep >= &bm_pte[0] && ptep < &bm_pte[PAGE_SIZE/sizeof(pte_t)];
 }
-static unsigned long slot_virt[FIX_BTMAPS_SLOTS] __initdata;
 void __init early_ioremap_init(void)
 {
        pmd_t *pmd;
-        int i;
-        if (early_ioremap_debug)
+        early_ioremap_setup();
-                printk(KERN_INFO "early_ioremap_init()\n");
-        for (i = 0; i < FIX_BTMAPS_SLOTS; i++)
-                slot_virt[i] = __fix_to_virt(FIX_BTMAP_BEGIN - NR_FIX_BTMAPS*i);
        pmd = early_ioremap_pmd(fix_to_virt(FIX_BTMAP_BEGIN));
        memset(bm_pte, 0, sizeof(bm_pte));
@@ -402,13 +384,8 @@ void __init early_ioremap_init(void)
        }
 }
-void __init early_ioremap_reset(void)
+void __init __early_set_fixmap(enum fixed_addresses idx,
-{
+                               phys_addr_t phys, pgprot_t flags)
-        after_paging_init = 1;
-}
-static void __init __early_set_fixmap(enum fixed_addresses idx,
-                                      phys_addr_t phys, pgprot_t flags)
 {
        unsigned long addr = __fix_to_virt(idx);
        pte_t *pte;
@@ -425,198 +402,3 @@ static void __init __early_set_fixmap(enum fixed_addresses idx,
                pte_clear(&init_mm, addr, pte);
        __flush_tlb_one(addr);
 }
-static inline void __init early_set_fixmap(enum fixed_addresses idx,
-                                           phys_addr_t phys, pgprot_t prot)
-{
-        if (after_paging_init)
-                __set_fixmap(idx, phys, prot);
-        else
-                __early_set_fixmap(idx, phys, prot);
-}
-static inline void __init early_clear_fixmap(enum fixed_addresses idx)
-{
-        if (after_paging_init)
-                clear_fixmap(idx);
-        else
-                __early_set_fixmap(idx, 0, __pgprot(0));
-}
-static void __iomem *prev_map[FIX_BTMAPS_SLOTS] __initdata;
-static unsigned long prev_size[FIX_BTMAPS_SLOTS] __initdata;
-void __init fixup_early_ioremap(void)
-{
-        int i;
-        for (i = 0; i < FIX_BTMAPS_SLOTS; i++) {
-                if (prev_map[i]) {
-                        WARN_ON(1);
-                        break;
-                }
-        }
-        early_ioremap_init();
-}
-static int __init check_early_ioremap_leak(void)
-{
-        int count = 0;
-        int i;
-        for (i = 0; i < FIX_BTMAPS_SLOTS; i++)
-                if (prev_map[i])
-                        count++;
-        if (!count)
-                return 0;
-        WARN(1, KERN_WARNING
-               "Debug warning: early ioremap leak of %d areas detected.\n",
-                count);
-        printk(KERN_WARNING
-                "please boot with early_ioremap_debug and report the dmesg.\n");
-        return 1;
-}
-late_initcall(check_early_ioremap_leak);
-static void __init __iomem *
-__early_ioremap(resource_size_t phys_addr, unsigned long size, pgprot_t prot)
-{
-        unsigned long offset;
-        resource_size_t last_addr;
-        unsigned int nrpages;
-        enum fixed_addresses idx;
-        int i, slot;
-        WARN_ON(system_state != SYSTEM_BOOTING);
-        slot = -1;
-        for (i = 0; i < FIX_BTMAPS_SLOTS; i++) {
-                if (!prev_map[i]) {
-                        slot = i;
-                        break;
-                }
-        }
-        if (slot < 0) {
-                printk(KERN_INFO "%s(%08llx, %08lx) not found slot\n",
-                       __func__, (u64)phys_addr, size);
-                WARN_ON(1);
-                return NULL;
-        }
-        if (early_ioremap_debug) {
-                printk(KERN_INFO "%s(%08llx, %08lx) [%d] => ",
-                       __func__, (u64)phys_addr, size, slot);
-                dump_stack();
-        }
-        /* Don't allow wraparound or zero size */
-        last_addr = phys_addr + size - 1;
-        if (!size || last_addr < phys_addr) {
-                WARN_ON(1);
-                return NULL;
-        }
-        prev_size[slot] = size;
-        /*
-         * Mappings have to be page-aligned
-         */
-        offset = phys_addr & ~PAGE_MASK;
-        phys_addr &= PAGE_MASK;
-        size = PAGE_ALIGN(last_addr + 1) - phys_addr;
-        /*
-         * Mappings have to fit in the FIX_BTMAP area.
-         */
-        nrpages = size >> PAGE_SHIFT;
-        if (nrpages > NR_FIX_BTMAPS) {
-                WARN_ON(1);
-                return NULL;
-        }
-        /*
-         * Ok, go for it..
-         */
-        idx = FIX_BTMAP_BEGIN - NR_FIX_BTMAPS*slot;
-        while (nrpages > 0) {
-                early_set_fixmap(idx, phys_addr, prot);
-                phys_addr += PAGE_SIZE;
-                --idx;
-                --nrpages;
-        }
-        if (early_ioremap_debug)
-                printk(KERN_CONT "%08lx + %08lx\n", offset, slot_virt[slot]);
-        prev_map[slot] = (void __iomem *)(offset + slot_virt[slot]);
-        return prev_map[slot];
-}
-/* Remap an IO device */
-void __init __iomem *
-early_ioremap(resource_size_t phys_addr, unsigned long size)
-{
-        return __early_ioremap(phys_addr, size, PAGE_KERNEL_IO);
-}
-/* Remap memory */
-void __init __iomem *
-early_memremap(resource_size_t phys_addr, unsigned long size)
-{
-        return __early_ioremap(phys_addr, size, PAGE_KERNEL);
-}
-void __init early_iounmap(void __iomem *addr, unsigned long size)
-{
-        unsigned long virt_addr;
-        unsigned long offset;
-        unsigned int nrpages;
-        enum fixed_addresses idx;
-        int i, slot;
-        slot = -1;
-        for (i = 0; i < FIX_BTMAPS_SLOTS; i++) {
-                if (prev_map[i] == addr) {
-                        slot = i;
-                        break;
-                }
-        }
-        if (slot < 0) {
-                printk(KERN_INFO "early_iounmap(%p, %08lx) not found slot\n",
-                         addr, size);
-                WARN_ON(1);
-                return;
-        }
-        if (prev_size[slot] != size) {
-                printk(KERN_INFO "early_iounmap(%p, %08lx) [%d] size not consistent %08lx\n",
-                         addr, size, slot, prev_size[slot]);
-                WARN_ON(1);
-                return;
-        }
-        if (early_ioremap_debug) {
-                printk(KERN_INFO "early_iounmap(%p, %08lx) [%d]\n", addr,
-                       size, slot);
-                dump_stack();
-        }
-        virt_addr = (unsigned long)addr;
-        if (virt_addr < fix_to_virt(FIX_BTMAP_BEGIN)) {
-                WARN_ON(1);
-                return;
-        }
-        offset = virt_addr & ~PAGE_MASK;
-        nrpages = PAGE_ALIGN(offset + size) >> PAGE_SHIFT;
-        idx = FIX_BTMAP_BEGIN - NR_FIX_BTMAPS*slot;
-        while (nrpages > 0) {
-                early_clear_fixmap(idx);
-                --idx;
-                --nrpages;
-        }
-        prev_map[slot] = NULL;
-}
diff --git a/arch/x86/mm/kmemcheck/kmemcheck.c b/arch/x86/mm/kmemcheck/kmemcheck.c
index d87dd6d042d6..dd89a13f1051 100644
--- a/arch/x86/mm/kmemcheck/kmemcheck.c
+++ b/arch/x86/mm/kmemcheck/kmemcheck.c
@@ -78,10 +78,16 @@ early_initcall(kmemcheck_init);
 */
 static int __init param_kmemcheck(char *str)
 {
+        int val;
+        int ret;
        if (!str)
                return -EINVAL;
-        sscanf(str, "%d", &kmemcheck_enabled);
+        ret = kstrtoint(str, 0, &val);
+        if (ret)
+                return ret;
+        kmemcheck_enabled = val;
        return 0;
 }
diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
index 27aa0455fab3..1d045f9c390f 100644
--- a/arch/x86/mm/numa.c
+++ b/arch/x86/mm/numa.c
@@ -687,10 +687,6 @@ static int __init dummy_numa_init(void)
 void __init x86_numa_init(void)
 {
        if (!numa_off) {
-#ifdef CONFIG_X86_NUMAQ
-                if (!numa_init(numaq_numa_init))
-                        return;
-#endif
 #ifdef CONFIG_ACPI_NUMA
                if (!numa_init(x86_acpi_numa_init))
                        return;
diff --git a/arch/x86/mm/pgtable_32.c b/arch/x86/mm/pgtable_32.c
index a69bcb8c7621..4dd8cf652579 100644
--- a/arch/x86/mm/pgtable_32.c
+++ b/arch/x86/mm/pgtable_32.c
@@ -127,7 +127,7 @@ static int __init parse_reservetop(char *arg)
        address = memparse(arg, &arg);
        reserve_top_address(address);
-        fixup_early_ioremap();
+        early_ioremap_init();
        return 0;
 }
 early_param("reservetop", parse_reservetop);
diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
index 4ed75dd81d05..dc017735bb91 100644
--- a/arch/x86/net/bpf_jit_comp.c
+++ b/arch/x86/net/bpf_jit_comp.c
@@ -553,13 +553,13 @@ void bpf_jit_compile(struct sk_filter *fp)
                                }
                                break;
                        case BPF_S_ANC_RXHASH:
-                                BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, rxhash) != 4);
+                                BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
-                                if (is_imm8(offsetof(struct sk_buff, rxhash))) {
+                                if (is_imm8(offsetof(struct sk_buff, hash))) {
                                        /* mov off8(%rdi),%eax */
-                                        EMIT3(0x8b, 0x47, offsetof(struct sk_buff, rxhash));
+                                        EMIT3(0x8b, 0x47, offsetof(struct sk_buff, hash));
                                } else {
                                        EMIT2(0x8b, 0x87);
-                                        EMIT(offsetof(struct sk_buff, rxhash), 4);
+                                        EMIT(offsetof(struct sk_buff, hash), 4);
                                }
                                break;
                        case BPF_S_ANC_QUEUE:
@@ -772,6 +772,7 @@ cond_branch:			f_offset = addrs[i + filter[i].jf] - addrs[i];
                bpf_flush_icache(header, image + proglen);
                set_memory_ro((unsigned long)header, header->pages);
                fp->bpf_func = (void *)image;
+                fp->jited = 1;
        }
 out:
        kfree(addrs);
@@ -791,7 +792,7 @@ static void bpf_jit_free_deferred(struct work_struct *work)
 void bpf_jit_free(struct sk_filter *fp)
 {
-        if (fp->bpf_func != sk_run_filter) {
+        if (fp->jited) {
                INIT_WORK(&fp->work, bpf_jit_free_deferred);
                schedule_work(&fp->work);
        } else {
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 6890d8498e0b..379e8bd0deea 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -494,14 +494,19 @@ static int nmi_setup(void)
        if (err)
                goto fail;
+        cpu_notifier_register_begin();
+        /* Use get/put_online_cpus() to protect 'nmi_enabled' */
        get_online_cpus();
-        register_cpu_notifier(&oprofile_cpu_nb);
        nmi_enabled = 1;
        /* make nmi_enabled visible to the nmi handler: */
        smp_mb();
        on_each_cpu(nmi_cpu_setup, NULL, 1);
+        __register_cpu_notifier(&oprofile_cpu_nb);
        put_online_cpus();
+        cpu_notifier_register_done();
        return 0;
 fail:
        free_msrs();
@@ -512,12 +517,18 @@ static void nmi_shutdown(void)
 {
        struct op_msrs *msrs;
+        cpu_notifier_register_begin();
+        /* Use get/put_online_cpus() to protect 'nmi_enabled' & 'ctr_running' */
        get_online_cpus();
-        unregister_cpu_notifier(&oprofile_cpu_nb);
        on_each_cpu(nmi_cpu_shutdown, NULL, 1);
        nmi_enabled = 0;
        ctr_running = 0;
+        __unregister_cpu_notifier(&oprofile_cpu_nb);
        put_online_cpus();
+        cpu_notifier_register_done();
        /* make variables visible to the nmi handler: */
        smp_mb();
        unregister_nmi_handler(NMI_LOCAL, "oprofile");
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index e063eed0f912..5c6fc3577a49 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -13,9 +13,6 @@ obj-y				+= legacy.o irq.o
 obj-$(CONFIG_STA2X11)           += sta2x11-fixup.o
-obj-$(CONFIG_X86_VISWS)         += visws.o
-obj-$(CONFIG_X86_NUMAQ)         += numaq_32.o
 obj-$(CONFIG_X86_NUMACHIP)      += numachip.o
 obj-$(CONFIG_X86_INTEL_MID)     += intel_mid_pci.o
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 4f25ec077552..01edac6c5e18 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -218,9 +218,8 @@ static void teardown_mcfg_map(struct pci_root_info *info)
 }
 #endif
-static acpi_status
+static acpi_status resource_to_addr(struct acpi_resource *resource,
-resource_to_addr(struct acpi_resource *resource,
+                                    struct acpi_resource_address64 *addr)
-                        struct acpi_resource_address64 *addr)
 {
        acpi_status status;
        struct acpi_resource_memory24 *memory24;
@@ -265,8 +264,7 @@ resource_to_addr(struct acpi_resource *resource,
        return AE_ERROR;
 }
-static acpi_status
+static acpi_status count_resource(struct acpi_resource *acpi_res, void *data)
-count_resource(struct acpi_resource *acpi_res, void *data)
 {
        struct pci_root_info *info = data;
        struct acpi_resource_address64 addr;
@@ -278,8 +276,7 @@ count_resource(struct acpi_resource *acpi_res, void *data)
        return AE_OK;
 }
-static acpi_status
+static acpi_status setup_resource(struct acpi_resource *acpi_res, void *data)
-setup_resource(struct acpi_resource *acpi_res, void *data)
 {
        struct pci_root_info *info = data;
        struct resource *res;
@@ -435,9 +432,9 @@ static void release_pci_root_info(struct pci_host_bridge *bridge)
        __release_pci_root_info(info);
 }
-static void
+static void probe_pci_root_info(struct pci_root_info *info,
-probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
+                                struct acpi_device *device,
-                    int busnum, int domain)
+                                int busnum, int domain)
 {
        size_t size;
@@ -473,16 +470,13 @@ probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
 struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 {
        struct acpi_device *device = root->device;
-        struct pci_root_info *info = NULL;
+        struct pci_root_info *info;
        int domain = root->segment;
        int busnum = root->secondary.start;
        LIST_HEAD(resources);
-        struct pci_bus *bus = NULL;
+        struct pci_bus *bus;
        struct pci_sysdata *sd;
        int node;
-#ifdef CONFIG_ACPI_NUMA
-        int pxm;
-#endif
        if (pci_ignore_seg)
                domain = 0;
@@ -494,19 +488,12 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
                return NULL;
        }
-        node = -1;
+        node = acpi_get_node(device->handle);
-#ifdef CONFIG_ACPI_NUMA
+        if (node == NUMA_NO_NODE)
-        pxm = acpi_get_pxm(device->handle);
+                node = x86_pci_root_bus_node(busnum);
-        if (pxm >= 0)
-                node = pxm_to_node(pxm);
-        if (node != -1)
-                set_mp_bus_to_node(busnum, node);
-        else
-#endif
-                node = get_mp_bus_to_node(busnum);
-        if (node != -1 && !node_online(node))
+        if (node != NUMA_NO_NODE && !node_online(node))
-                node = -1;
+                node = NUMA_NO_NODE;
        info = kzalloc(sizeof(*info), GFP_KERNEL);
        if (!info) {
@@ -519,15 +506,12 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
        sd->domain = domain;
        sd->node = node;
        sd->companion = device;
-        /*
-         * Maybe the desired pci bus has been already scanned. In such case
-         * it is unnecessary to scan the pci bus with the given domain,busnum.
-         */
        bus = pci_find_bus(domain, busnum);
        if (bus) {
                /*
-                 * If the desired bus exits, the content of bus->sysdata will
+                 * If the desired bus has been scanned already, replace
-                 * be replaced by sd.
+                 * its bus->sysdata.
                 */
                memcpy(bus->sysdata, sd, sizeof(*sd));
                kfree(info);
@@ -572,15 +556,8 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
                        pcie_bus_configure_settings(child);
        }
-        if (bus && node != -1) {
+        if (bus && node != NUMA_NO_NODE)
-#ifdef CONFIG_ACPI_NUMA
-                if (pxm >= 0)
-                        dev_printk(KERN_DEBUG, &bus->dev,
-                                   "on NUMA node %d (pxm %d)\n", node, pxm);
-#else
                dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
-#endif
-        }
        return bus;
 }
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index a48be98e9ded..e88f4c53d7f6 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -44,15 +44,6 @@ static struct pci_root_info __init *find_pci_root_info(int node, int link)
        return NULL;
 }
-static void __init set_mp_bus_range_to_node(int min_bus, int max_bus, int node)
-{
-#ifdef CONFIG_NUMA
-        int j;
-        for (j = min_bus; j <= max_bus; j++)
-                set_mp_bus_to_node(j, node);
-#endif
-}
 /**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
@@ -117,7 +108,6 @@ static int __init early_fill_mp_bus_info(void)
                min_bus = (reg >> 16) & 0xff;
                max_bus = (reg >> 24) & 0xff;
                node = (reg >> 4) & 0x07;
-                set_mp_bus_range_to_node(min_bus, max_bus, node);
                link = (reg >> 8) & 0x03;
                info = alloc_pci_root_info(min_bus, max_bus, node, link);
@@ -380,10 +370,13 @@ static int __init pci_io_ecs_init(void)
        if (early_pci_allowed())
                pci_enable_pci_io_ecs();
-        register_cpu_notifier(&amd_cpu_notifier);
+        cpu_notifier_register_begin();
        for_each_online_cpu(cpu)
                amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
                               (void *)(long)cpu);
+        __register_cpu_notifier(&amd_cpu_notifier);
+        cpu_notifier_register_done();
        pci_probe |= PCI_HAS_IO_ECS;
        return 0;
diff --git a/arch/x86/pci/bus_numa.c b/arch/x86/pci/bus_numa.c
index c2735feb2508..f3a2cfc14125 100644
--- a/arch/x86/pci/bus_numa.c
+++ b/arch/x86/pci/bus_numa.c
@@ -10,9 +10,6 @@ static struct pci_root_info *x86_find_pci_root_info(int bus)
 {
        struct pci_root_info *info;
-        if (list_empty(&pci_root_infos))
-                return NULL;
        list_for_each_entry(info, &pci_root_infos, list)
                if (info->busn.start == bus)
                        return info;
@@ -20,6 +17,16 @@ static struct pci_root_info *x86_find_pci_root_info(int bus)
        return NULL;
 }
+int x86_pci_root_bus_node(int bus)
+{
+        struct pci_root_info *info = x86_find_pci_root_info(bus);
+        if (!info)
+                return NUMA_NO_NODE;
+        return info->node;
+}
 void x86_pci_root_bus_resources(int bus, struct list_head *resources)
 {
        struct pci_root_info *info = x86_find_pci_root_info(bus);
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 981c2dbd72cc..059a76c29739 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -456,19 +456,25 @@ void __init dmi_check_pciprobe(void)
        dmi_check_system(pciprobe_dmi_table);
 }
-struct pci_bus *pcibios_scan_root(int busnum)
+void pcibios_scan_root(int busnum)
 {
-        struct pci_bus *bus = NULL;
+        struct pci_bus *bus;
+        struct pci_sysdata *sd;
+        LIST_HEAD(resources);
-        while ((bus = pci_find_next_bus(bus)) != NULL) {
+        sd = kzalloc(sizeof(*sd), GFP_KERNEL);
-                if (bus->number == busnum) {
+        if (!sd) {
-                        /* Already scanned */
+                printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busnum);
-                        return bus;
+                return;
-                }
+        }
+        sd->node = x86_pci_root_bus_node(busnum);
+        x86_pci_root_bus_resources(busnum, &resources);
+        printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
+        bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
+        if (!bus) {
+                pci_free_resource_list(&resources);
+                kfree(sd);
        }
-        return pci_scan_bus_on_node(busnum, &pci_root_ops,
-                                        get_mp_bus_to_node(busnum));
 }
 void __init pcibios_set_cache_line_size(void)
@@ -561,7 +567,6 @@ char * __init pcibios_setup(char *str)
                pci_probe |= PCI_PROBE_NOEARLY;
                return NULL;
        }
-#ifndef CONFIG_X86_VISWS
        else if (!strcmp(str, "usepirqmask")) {
                pci_probe |= PCI_USE_PIRQ_MASK;
                return NULL;
@@ -571,9 +576,7 @@ char * __init pcibios_setup(char *str)
        } else if (!strncmp(str, "lastbus=", 8)) {
                pcibios_last_bus = simple_strtol(str+8, NULL, 0);
                return NULL;
-        }
+        } else if (!strcmp(str, "rom")) {
-#endif
-        else if (!strcmp(str, "rom")) {
                pci_probe |= PCI_ASSIGN_ROMS;
                return NULL;
        } else if (!strcmp(str, "norom")) {
@@ -677,105 +680,3 @@ int pci_ext_cfg_avail(void)
        else
                return 0;
 }
-struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node)
-{
-        LIST_HEAD(resources);
-        struct pci_bus *bus = NULL;
-        struct pci_sysdata *sd;
-        /*
-         * Allocate per-root-bus (not per bus) arch-specific data.
-         * TODO: leak; this memory is never freed.
-         * It's arguable whether it's worth the trouble to care.
-         */
-        sd = kzalloc(sizeof(*sd), GFP_KERNEL);
-        if (!sd) {
-                printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busno);
-                return NULL;
-        }
-        sd->node = node;
-        x86_pci_root_bus_resources(busno, &resources);
-        printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busno);
-        bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources);
-        if (!bus) {
-                pci_free_resource_list(&resources);
-                kfree(sd);
-        }
-        return bus;
-}
-struct pci_bus *pci_scan_bus_with_sysdata(int busno)
-{
-        return pci_scan_bus_on_node(busno, &pci_root_ops, -1);
-}
-/*
- * NUMA info for PCI busses
- *
- * Early arch code is responsible for filling in reasonable values here.
- * A node id of "-1" means "use current node".  In other words, if a bus
- * has a -1 node id, it's not tightly coupled to any particular chunk
- * of memory (as is the case on some Nehalem systems).
- */
-#ifdef CONFIG_NUMA
-#define BUS_NR 256
-#ifdef CONFIG_X86_64
-static int mp_bus_to_node[BUS_NR] = {
-        [0 ... BUS_NR - 1] = -1
-};
-void set_mp_bus_to_node(int busnum, int node)
-{
-        if (busnum >= 0 &&  busnum < BUS_NR)
-                mp_bus_to_node[busnum] = node;
-}
-int get_mp_bus_to_node(int busnum)
-{
-        int node = -1;
-        if (busnum < 0 || busnum > (BUS_NR - 1))
-                return node;
-        node = mp_bus_to_node[busnum];
-        /*
-         * let numa_node_id to decide it later in dma_alloc_pages
-         * if there is no ram on that node
-         */
-        if (node != -1 && !node_online(node))
-                node = -1;
-        return node;
-}
-#else /* CONFIG_X86_32 */
-static int mp_bus_to_node[BUS_NR] = {
-        [0 ... BUS_NR - 1] = -1
-};
-void set_mp_bus_to_node(int busnum, int node)
-{
-        if (busnum >= 0 &&  busnum < BUS_NR)
-        mp_bus_to_node[busnum] = (unsigned char) node;
-}
-int get_mp_bus_to_node(int busnum)
-{
-        int node;
-        if (busnum < 0 || busnum > (BUS_NR - 1))
-                return 0;
-        node = mp_bus_to_node[busnum];
-        return node;
-}
-#endif /* CONFIG_X86_32 */
-#endif /* CONFIG_NUMA */
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index bca9e85daaa5..94ae9ae9574f 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -25,9 +25,9 @@ static void pci_fixup_i450nx(struct pci_dev *d)
                dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
                        suba, subb);
                if (busno)
-                        pci_scan_bus_with_sysdata(busno);       /* Bus A */
+                        pcibios_scan_root(busno);       /* Bus A */
                if (suba < subb)
-                        pci_scan_bus_with_sysdata(suba+1);      /* Bus B */
+                        pcibios_scan_root(suba+1);      /* Bus B */
        }
        pcibios_last_bus = -1;
 }
@@ -42,7 +42,7 @@ static void pci_fixup_i450gx(struct pci_dev *d)
        u8 busno;
        pci_read_config_byte(d, 0x4a, &busno);
        dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
-        pci_scan_bus_with_sysdata(busno);
+        pcibios_scan_root(busno);
        pcibios_last_bus = -1;
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
@@ -313,9 +313,10 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC1,	pcie_r
 * IORESOURCE_ROM_SHADOW is used to associate the boot video
 * card with this copy. On laptops this copy has to be used since
 * the main ROM may be compressed or combined with another image.
- * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
+ * See pci_map_rom() for use of this flag. Before marking the device
- * is marked here since the boot video device will be the only enabled
+ * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
- * video device at this point.
+ * by either arch cde or vga-arbitration, if so only apply the fixup to this
+ * already determined primary video card.
 */
 static void pci_fixup_video(struct pci_dev *pdev)
@@ -346,12 +347,13 @@ static void pci_fixup_video(struct pci_dev *pdev)
                }
                bus = bus->parent;
        }
-        pci_read_config_word(pdev, PCI_COMMAND, &config);
+        if (!vga_default_device() || pdev == vga_default_device()) {
-        if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
+                pci_read_config_word(pdev, PCI_COMMAND, &config);
-                pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
+                if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
-                dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
+                        pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
-                if (!vga_default_device())
+                        dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
                        vga_set_default_device(pdev);
+                }
        }
 }
 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 372e9b8989b3..84112f55dd7a 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -136,13 +136,9 @@ static void __init pirq_peer_trick(void)
                busmap[e->bus] = 1;
        }
        for (i = 1; i < 256; i++) {
-                int node;
                if (!busmap[i] || pci_find_bus(0, i))
                        continue;
-                node = get_mp_bus_to_node(i);
+                pcibios_scan_root(i);
-                if (pci_scan_bus_on_node(i, &pci_root_ops, node))
-                        printk(KERN_INFO "PCI: Discovered primary peer "
-                               "bus %02x [IRQ]\n", i);
        }
        pcibios_last_bus = -1;
 }
diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c
index 4db96fb1c232..5b662c0faf8c 100644
--- a/arch/x86/pci/legacy.c
+++ b/arch/x86/pci/legacy.c
@@ -37,19 +37,17 @@ int __init pci_legacy_init(void)
 void pcibios_scan_specific_bus(int busn)
 {
        int devfn;
-        long node;
        u32 l;
        if (pci_find_bus(0, busn))
                return;
-        node = get_mp_bus_to_node(busn);
        for (devfn = 0; devfn < 256; devfn += 8) {
                if (!raw_pci_read(0, busn, devfn, PCI_VENDOR_ID, 2, &l) &&
                    l != 0x0000 && l != 0xffff) {
                        DBG("Found device at %02x:%02x [%04x]\n", busn, devfn, l);
                        printk(KERN_INFO "PCI: Discovered peer bus %02x\n", busn);
-                        pci_scan_bus_on_node(busn, &pci_root_ops, node);
+                        pcibios_scan_root(busn);
                        return;
                }
        }
diff --git a/arch/x86/pci/numaq_32.c b/arch/x86/pci/numaq_32.c
deleted file mode 100644
index 72c229f9ebcf..000000000000
--- a/arch/x86/pci/numaq_32.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * numaq_32.c - Low-level PCI access for NUMA-Q machines
- */
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/nodemask.h>
-#include <asm/apic.h>
-#include <asm/mpspec.h>
-#include <asm/pci_x86.h>
-#include <asm/numaq.h>
-#define BUS2QUAD(global) (mp_bus_id_to_node[global])
-#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
-#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
-#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
-        (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
-static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
-{
-        unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
-        if (xquad_portio)
-                writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
-        else
-                outl(val, 0xCF8);
-}
-static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
-                             unsigned int devfn, int reg, int len, u32 *value)
-{
-        unsigned long flags;
-        void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
-        WARN_ON(seg);
-        if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
-                return -EINVAL;
-        raw_spin_lock_irqsave(&pci_config_lock, flags);
-        write_cf8(bus, devfn, reg);
-        switch (len) {
-        case 1:
-                if (xquad_portio)
-                        *value = readb(adr + (reg & 3));
-                else
-                        *value = inb(0xCFC + (reg & 3));
-                break;
-        case 2:
-                if (xquad_portio)
-                        *value = readw(adr + (reg & 2));
-                else
-                        *value = inw(0xCFC + (reg & 2));
-                break;
-        case 4:
-                if (xquad_portio)
-                        *value = readl(adr);
-                else
-                        *value = inl(0xCFC);
-                break;
-        }
-        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
-        return 0;
-}
-static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
-                              unsigned int devfn, int reg, int len, u32 value)
-{
-        unsigned long flags;
-        void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
-        WARN_ON(seg);
-        if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) 
-                return -EINVAL;
-        raw_spin_lock_irqsave(&pci_config_lock, flags);
-        write_cf8(bus, devfn, reg);
-        switch (len) {
-        case 1:
-                if (xquad_portio)
-                        writeb(value, adr + (reg & 3));
-                else
-                        outb((u8)value, 0xCFC + (reg & 3));
-                break;
-        case 2:
-                if (xquad_portio)
-                        writew(value, adr + (reg & 2));
-                else
-                        outw((u16)value, 0xCFC + (reg & 2));
-                break;
-        case 4:
-                if (xquad_portio)
-                        writel(value, adr + reg);
-                else
-                        outl((u32)value, 0xCFC);
-                break;
-        }
-        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
-        return 0;
-}
-#undef PCI_CONF1_MQ_ADDRESS
-static const struct pci_raw_ops pci_direct_conf1_mq = {
-        .read   = pci_conf1_mq_read,
-        .write  = pci_conf1_mq_write
-};
-static void pci_fixup_i450nx(struct pci_dev *d)
-{
-        /*
-         * i450NX -- Find and scan all secondary buses on all PXB's.
-         */
-        int pxb, reg;
-        u8 busno, suba, subb;
-        int quad = BUS2QUAD(d->bus->number);
-        dev_info(&d->dev, "searching for i450NX host bridges\n");
-        reg = 0xd0;
-        for(pxb=0; pxb<2; pxb++) {
-                pci_read_config_byte(d, reg++, &busno);
-                pci_read_config_byte(d, reg++, &suba);
-                pci_read_config_byte(d, reg++, &subb);
-                dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
-                        pxb, busno, suba, subb);
-                if (busno) {
-                        /* Bus A */
-                        pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
-                }
-                if (suba < subb) {
-                        /* Bus B */
-                        pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, suba+1));
-                }
-        }
-        pcibios_last_bus = -1;
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
-int __init pci_numaq_init(void)
-{
-        int quad;
-        raw_pci_ops = &pci_direct_conf1_mq;
-        pcibios_scan_root(0);
-        if (num_online_nodes() > 1)
-                for_each_online_node(quad) {
-                        if (quad == 0)
-                                continue;
-                        printk("Scanning PCI bus %d for quad %d\n", 
-                                QUADLOCAL2BUS(quad,0), quad);
-                        pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, 0));
-                }
-        return 0;
-}
diff --git a/arch/x86/pci/visws.c b/arch/x86/pci/visws.c
deleted file mode 100644
index 3e6d2a6db866..000000000000
--- a/arch/x86/pci/visws.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- *      Low-Level PCI Support for SGI Visual Workstation
- *
- *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <asm/setup.h>
-#include <asm/pci_x86.h>
-#include <asm/visws/cobalt.h>
-#include <asm/visws/lithium.h>
-static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
-static void pci_visws_disable_irq(struct pci_dev *dev) { }
-/* int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq; */
-/* void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq; */
-/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */
-unsigned int pci_bus0, pci_bus1;
-static int __init visws_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        int irq, bus = dev->bus->number;
-        pin--;
-        /* Nothing useful at PIIX4 pin 1 */
-        if (bus == pci_bus0 && slot == 4 && pin == 0)
-                return -1;
-        /* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
-        if (bus == pci_bus0 && slot == 4 && pin == 3) {
-                irq = CO_IRQ(CO_APIC_PIIX4_USB);
-                goto out;
-        }
-        /* First pin spread down 1 APIC entry per slot */
-        if (pin == 0) {
-                irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
-                                                CO_APIC_PCIA_BASE0) + slot);
-                goto out;
-        }
-        /* lines 1,2,3 from any slot is shared in this twirly pattern */
-        if (bus == pci_bus1) {
-                /* lines 1-3 from devices 0 1 rotate over 2 apic entries */
-                irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
-        } else { /* bus == pci_bus0 */
-                /* lines 1-3 from devices 0-3 rotate over 3 apic entries */
-                if (slot == 0)
-                        slot = 3; /* same pattern */
-                irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
-        }
-out:
-        printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
-        return irq;
-}
-int __init pci_visws_init(void)
-{
-        pcibios_enable_irq = &pci_visws_enable_irq;
-        pcibios_disable_irq = &pci_visws_disable_irq;
-        /* The VISWS supports configuration access type 1 only */
-        pci_probe = (pci_probe | PCI_PROBE_CONF1) &
-                    ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
-        pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
-        pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
-        printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
-                "bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
-        raw_pci_ops = &pci_direct_conf1;
-        pci_scan_bus_with_sysdata(pci_bus0);
-        pci_scan_bus_with_sysdata(pci_bus1);
-        pci_fixup_irqs(pci_common_swizzle, visws_map_irq);
-        pcibios_resource_survey();
-        /* Request bus scan */
-        return 1;
-}
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index 103e702ec5a7..905956f16465 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -178,6 +178,7 @@ static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
        i = 0;
        list_for_each_entry(msidesc, &dev->msi_list, list) {
                irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
+                                               (type == PCI_CAP_ID_MSI) ? nvec : 1,
                                               (type == PCI_CAP_ID_MSIX) ?
                                               "pcifront-msi-x" :
                                               "pcifront-msi",
@@ -245,6 +246,7 @@ static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                                "xen: msi already bound to pirq=%d\n", pirq);
                }
                irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
+                                               (type == PCI_CAP_ID_MSI) ? nvec : 1,
                                               (type == PCI_CAP_ID_MSIX) ?
                                               "msi-x" : "msi",
                                               DOMID_SELF);
@@ -269,9 +271,6 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
        int ret = 0;
        struct msi_desc *msidesc;
-        if (type == PCI_CAP_ID_MSI && nvec > 1)
-                return 1;
        list_for_each_entry(msidesc, &dev->msi_list, list) {
                struct physdev_map_pirq map_irq;
                domid_t domid;
@@ -291,7 +290,10 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                              (pci_domain_nr(dev->bus) << 16);
                map_irq.devfn = dev->devfn;
-                if (type == PCI_CAP_ID_MSIX) {
+                if (type == PCI_CAP_ID_MSI && nvec > 1) {
+                        map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
+                        map_irq.entry_nr = nvec;
+                } else if (type == PCI_CAP_ID_MSIX) {
                        int pos;
                        u32 table_offset, bir;
@@ -308,6 +310,16 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                if (pci_seg_supported)
                        ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
                                                    &map_irq);
+                if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
+                        /*
+                         * If MAP_PIRQ_TYPE_MULTI_MSI is not available
+                         * there's nothing else we can do in this case.
+                         * Just set ret > 0 so driver can retry with
+                         * single MSI.
+                         */
+                        ret = 1;
+                        goto out;
+                }
                if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
                        map_irq.type = MAP_PIRQ_TYPE_MSI;
                        map_irq.index = -1;
@@ -324,11 +336,10 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                        goto out;
                }
-                ret = xen_bind_pirq_msi_to_irq(dev, msidesc,
+                ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
-                                               map_irq.pirq,
+                                               (type == PCI_CAP_ID_MSI) ? nvec : 1,
-                                               (type == PCI_CAP_ID_MSIX) ?
+                                               (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
-                                               "msi-x" : "msi",
+                                               domid);
-                                                domid);
                if (ret < 0)
                        goto out;
        }
diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile
index 20342d4c82ce..85afde1fa3e5 100644
--- a/arch/x86/platform/Makefile
+++ b/arch/x86/platform/Makefile
@@ -9,5 +9,4 @@ obj-y	+= olpc/
 obj-y   += scx200/
 obj-y   += sfi/
 obj-y   += ts5500/
-obj-y   += visws/
 obj-y   += uv/
diff --git a/arch/x86/platform/visws/Makefile b/arch/x86/platform/visws/Makefile
deleted file mode 100644
index 91bc17ab2fd5..000000000000
--- a/arch/x86/platform/visws/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-$(CONFIG_X86_VISWS) += visws_quirks.o
diff --git a/arch/x86/platform/visws/visws_quirks.c b/arch/x86/platform/visws/visws_quirks.c
deleted file mode 100644
index 94d8a39332ec..000000000000
--- a/arch/x86/platform/visws/visws_quirks.c
+++ /dev/null
@@ -1,608 +0,0 @@
-/*
- *  SGI Visual Workstation support and quirks, unmaintained.
- *
- *  Split out from setup.c by davej@suse.de
- *
- *      Copyright (C) 1999 Bent Hagemark, Ingo Molnar
- *
- *  SGI Visual Workstation interrupt controller
- *
- *  The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
- *  which serves as the main interrupt controller in the system.  Non-legacy
- *  hardware in the system uses this controller directly.  Legacy devices
- *  are connected to the PIIX4 which in turn has its 8259(s) connected to
- *  a of the Cobalt APIC entry.
- *
- *  09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
- *
- *  25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
- */
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <asm/visws/cobalt.h>
-#include <asm/visws/piix4.h>
-#include <asm/io_apic.h>
-#include <asm/fixmap.h>
-#include <asm/reboot.h>
-#include <asm/setup.h>
-#include <asm/apic.h>
-#include <asm/e820.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <linux/kernel_stat.h>
-#include <asm/i8259.h>
-#include <asm/irq_vectors.h>
-#include <asm/visws/lithium.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/pci_ids.h>
-extern int no_broadcast;
-char visws_board_type   = -1;
-char visws_board_rev    = -1;
-static void __init visws_time_init(void)
-{
-        printk(KERN_INFO "Starting Cobalt Timer system clock\n");
-        /* Set the countdown value */
-        co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
-        /* Start the timer */
-        co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
-        /* Enable (unmask) the timer interrupt */
-        co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
-        setup_default_timer_irq();
-}
-/* Replaces the default init_ISA_irqs in the generic setup */
-static void __init visws_pre_intr_init(void);
-/* Quirk for machine specific memory setup. */
-#define MB (1024 * 1024)
-unsigned long sgivwfb_mem_phys;
-unsigned long sgivwfb_mem_size;
-EXPORT_SYMBOL(sgivwfb_mem_phys);
-EXPORT_SYMBOL(sgivwfb_mem_size);
-long long mem_size __initdata = 0;
-static char * __init visws_memory_setup(void)
-{
-        long long gfx_mem_size = 8 * MB;
-        mem_size = boot_params.alt_mem_k;
-        if (!mem_size) {
-                printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
-                mem_size = 128 * MB;
-        }
-        /*
-         * this hardcodes the graphics memory to 8 MB
-         * it really should be sized dynamically (or at least
-         * set as a boot param)
-         */
-        if (!sgivwfb_mem_size) {
-                printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
-                sgivwfb_mem_size = 8 * MB;
-        }
-        /*
-         * Trim to nearest MB
-         */
-        sgivwfb_mem_size &= ~((1 << 20) - 1);
-        sgivwfb_mem_phys = mem_size - gfx_mem_size;
-        e820_add_region(0, LOWMEMSIZE(), E820_RAM);
-        e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
-        e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
-        return "PROM";
-}
-static void visws_machine_emergency_restart(void)
-{
-        /*
-         * Visual Workstations restart after this
-         * register is poked on the PIIX4
-         */
-        outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
-}
-static void visws_machine_power_off(void)
-{
-        unsigned short pm_status;
-/*      extern unsigned int pci_bus0; */
-        while ((pm_status = inw(PMSTS_PORT)) & 0x100)
-                outw(pm_status, PMSTS_PORT);
-        outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
-        mdelay(10);
-#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
-        (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
-/*      outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
-        outl(PIIX_SPECIAL_STOP, 0xCFC);
-}
-static void __init visws_get_smp_config(unsigned int early)
-{
-}
-/*
- * The Visual Workstation is Intel MP compliant in the hardware
- * sense, but it doesn't have a BIOS(-configuration table).
- * No problem for Linux.
- */
-static void __init MP_processor_info(struct mpc_cpu *m)
-{
-        int ver, logical_apicid;
-        physid_mask_t apic_cpus;
-        if (!(m->cpuflag & CPU_ENABLED))
-                return;
-        logical_apicid = m->apicid;
-        printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
-               m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
-               m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
-               (m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver);
-        if (m->cpuflag & CPU_BOOTPROCESSOR)
-                boot_cpu_physical_apicid = m->apicid;
-        ver = m->apicver;
-        if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) {
-                printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
-                        m->apicid, MAX_LOCAL_APIC);
-                return;
-        }
-        apic->apicid_to_cpu_present(m->apicid, &apic_cpus);
-        physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
-        /*
-         * Validate version
-         */
-        if (ver == 0x0) {
-                printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
-                        "fixing up to 0x10. (tell your hw vendor)\n",
-                        m->apicid);
-                ver = 0x10;
-        }
-        apic_version[m->apicid] = ver;
-}
-static void __init visws_find_smp_config(void)
-{
-        struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS);
-        unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
-        if (ncpus > CO_CPU_MAX) {
-                printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
-                        ncpus, mp);
-                ncpus = CO_CPU_MAX;
-        }
-        if (ncpus > setup_max_cpus)
-                ncpus = setup_max_cpus;
-#ifdef CONFIG_X86_LOCAL_APIC
-        smp_found_config = 1;
-#endif
-        while (ncpus--)
-                MP_processor_info(mp++);
-        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
-}
-static void visws_trap_init(void);
-void __init visws_early_detect(void)
-{
-        int raw;
-        visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
-                                                         >> PIIX_GPI_BD_SHIFT;
-        if (visws_board_type < 0)
-                return;
-        /*
-         * Override the default platform setup functions
-         */
-        x86_init.resources.memory_setup = visws_memory_setup;
-        x86_init.mpparse.get_smp_config = visws_get_smp_config;
-        x86_init.mpparse.find_smp_config = visws_find_smp_config;
-        x86_init.irqs.pre_vector_init = visws_pre_intr_init;
-        x86_init.irqs.trap_init = visws_trap_init;
-        x86_init.timers.timer_init = visws_time_init;
-        x86_init.pci.init = pci_visws_init;
-        x86_init.pci.init_irq = x86_init_noop;
-        /*
-         * Install reboot quirks:
-         */
-        pm_power_off                    = visws_machine_power_off;
-        machine_ops.emergency_restart   = visws_machine_emergency_restart;
-        /*
-         * Do not use broadcast IPIs:
-         */
-        no_broadcast = 0;
-#ifdef CONFIG_X86_IO_APIC
-        /*
-         * Turn off IO-APIC detection and initialization:
-         */
-        skip_ioapic_setup               = 1;
-#endif
-        /*
-         * Get Board rev.
-         * First, we have to initialize the 307 part to allow us access
-         * to the GPIO registers.  Let's map them at 0x0fc0 which is right
-         * after the PIIX4 PM section.
-         */
-        outb_p(SIO_DEV_SEL, SIO_INDEX);
-        outb_p(SIO_GP_DEV, SIO_DATA);   /* Talk to GPIO regs. */
-        outb_p(SIO_DEV_MSB, SIO_INDEX);
-        outb_p(SIO_GP_MSB, SIO_DATA);   /* MSB of GPIO base address */
-        outb_p(SIO_DEV_LSB, SIO_INDEX);
-        outb_p(SIO_GP_LSB, SIO_DATA);   /* LSB of GPIO base address */
-        outb_p(SIO_DEV_ENB, SIO_INDEX);
-        outb_p(1, SIO_DATA);            /* Enable GPIO registers. */
-        /*
-         * Now, we have to map the power management section to write
-         * a bit which enables access to the GPIO registers.
-         * What lunatic came up with this shit?
-         */
-        outb_p(SIO_DEV_SEL, SIO_INDEX);
-        outb_p(SIO_PM_DEV, SIO_DATA);   /* Talk to GPIO regs. */
-        outb_p(SIO_DEV_MSB, SIO_INDEX);
-        outb_p(SIO_PM_MSB, SIO_DATA);   /* MSB of PM base address */
-        outb_p(SIO_DEV_LSB, SIO_INDEX);
-        outb_p(SIO_PM_LSB, SIO_DATA);   /* LSB of PM base address */
-        outb_p(SIO_DEV_ENB, SIO_INDEX);
-        outb_p(1, SIO_DATA);            /* Enable PM registers. */
-        /*
-         * Now, write the PM register which enables the GPIO registers.
-         */
-        outb_p(SIO_PM_FER2, SIO_PM_INDEX);
-        outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
-        /*
-         * Now, initialize the GPIO registers.
-         * We want them all to be inputs which is the
-         * power on default, so let's leave them alone.
-         * So, let's just read the board rev!
-         */
-        raw = inb_p(SIO_GP_DATA1);
-        raw &= 0x7f;    /* 7 bits of valid board revision ID. */
-        if (visws_board_type == VISWS_320) {
-                if (raw < 0x6) {
-                        visws_board_rev = 4;
-                } else if (raw < 0xc) {
-                        visws_board_rev = 5;
-                } else {
-                        visws_board_rev = 6;
-                }
-        } else if (visws_board_type == VISWS_540) {
-                        visws_board_rev = 2;
-                } else {
-                        visws_board_rev = raw;
-                }
-        printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
-               (visws_board_type == VISWS_320 ? "320" :
-               (visws_board_type == VISWS_540 ? "540" :
-                "unknown")), visws_board_rev);
-}
-#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
-#define BCD (LI_INTB | LI_INTC | LI_INTD)
-#define ALLDEVS (A01234 | BCD)
-static __init void lithium_init(void)
-{
-        set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
-        set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
-        if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
-            (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
-                printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
-/*              panic("This machine is not SGI Visual Workstation 320/540"); */
-        }
-        if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
-            (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
-                printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
-/*              panic("This machine is not SGI Visual Workstation 320/540"); */
-        }
-        li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
-        li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
-}
-static __init void cobalt_init(void)
-{
-        /*
-         * On normal SMP PC this is used only with SMP, but we have to
-         * use it and set it up here to start the Cobalt clock
-         */
-        set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
-        setup_local_APIC();
-        printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
-                (unsigned int)apic_read(APIC_LVR),
-                (unsigned int)apic_read(APIC_ID));
-        set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
-        set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
-        printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
-                co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
-        /* Enable Cobalt APIC being careful to NOT change the ID! */
-        co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
-        printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
-                co_apic_read(CO_APIC_ID));
-}
-static void __init visws_trap_init(void)
-{
-        lithium_init();
-        cobalt_init();
-}
-/*
- * IRQ controller / APIC support:
- */
-static DEFINE_SPINLOCK(cobalt_lock);
-/*
- * Set the given Cobalt APIC Redirection Table entry to point
- * to the given IDT vector/index.
- */
-static inline void co_apic_set(int entry, int irq)
-{
-        co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
-        co_apic_write(CO_APIC_HI(entry), 0);
-}
-/*
- * Cobalt (IO)-APIC functions to handle PCI devices.
- */
-static inline int co_apic_ide0_hack(void)
-{
-        extern char visws_board_type;
-        extern char visws_board_rev;
-        if (visws_board_type == VISWS_320 && visws_board_rev == 5)
-                return 5;
-        return CO_APIC_IDE0;
-}
-static int is_co_apic(unsigned int irq)
-{
-        if (IS_CO_APIC(irq))
-                return CO_APIC(irq);
-        switch (irq) {
-                case 0: return CO_APIC_CPU;
-                case CO_IRQ_IDE0: return co_apic_ide0_hack();
-                case CO_IRQ_IDE1: return CO_APIC_IDE1;
-                default: return -1;
-        }
-}
-/*
- * This is the SGI Cobalt (IO-)APIC:
- */
-static void enable_cobalt_irq(struct irq_data *data)
-{
-        co_apic_set(is_co_apic(data->irq), data->irq);
-}
-static void disable_cobalt_irq(struct irq_data *data)
-{
-        int entry = is_co_apic(data->irq);
-        co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
-        co_apic_read(CO_APIC_LO(entry));
-}
-static void ack_cobalt_irq(struct irq_data *data)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&cobalt_lock, flags);
-        disable_cobalt_irq(data);
-        apic_write(APIC_EOI, APIC_EOI_ACK);
-        spin_unlock_irqrestore(&cobalt_lock, flags);
-}
-static struct irq_chip cobalt_irq_type = {
-        .name           = "Cobalt-APIC",
-        .irq_enable     = enable_cobalt_irq,
-        .irq_disable    = disable_cobalt_irq,
-        .irq_ack        = ack_cobalt_irq,
-};
-/*
- * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
- * -- not the manner expected by the code in i8259.c.
- *
- * there is a 'master' physical interrupt source that gets sent to
- * the CPU. But in the chipset there are various 'virtual' interrupts
- * waiting to be handled. We represent this to Linux through a 'master'
- * interrupt controller type, and through a special virtual interrupt-
- * controller. Device drivers only see the virtual interrupt sources.
- */
-static unsigned int startup_piix4_master_irq(struct irq_data *data)
-{
-        legacy_pic->init(0);
-        enable_cobalt_irq(data);
-        return 0;
-}
-static struct irq_chip piix4_master_irq_type = {
-        .name           = "PIIX4-master",
-        .irq_startup    = startup_piix4_master_irq,
-        .irq_ack        = ack_cobalt_irq,
-};
-static void pii4_mask(struct irq_data *data) { }
-static struct irq_chip piix4_virtual_irq_type = {
-        .name           = "PIIX4-virtual",
-        .irq_mask       = pii4_mask,
-};
-/*
- * PIIX4-8259 master/virtual functions to handle interrupt requests
- * from legacy devices: floppy, parallel, serial, rtc.
- *
- * None of these get Cobalt APIC entries, neither do they have IDT
- * entries. These interrupts are purely virtual and distributed from
- * the 'master' interrupt source: CO_IRQ_8259.
- *
- * When the 8259 interrupts its handler figures out which of these
- * devices is interrupting and dispatches to its handler.
- *
- * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
- * enable_irq gets the right irq. This 'master' irq is never directly
- * manipulated by any driver.
- */
-static irqreturn_t piix4_master_intr(int irq, void *dev_id)
-{
-        unsigned long flags;
-        int realirq;
-        raw_spin_lock_irqsave(&i8259A_lock, flags);
-        /* Find out what's interrupting in the PIIX4 master 8259 */
-        outb(0x0c, 0x20);               /* OCW3 Poll command */
-        realirq = inb(0x20);
-        /*
-         * Bit 7 == 0 means invalid/spurious
-         */
-        if (unlikely(!(realirq & 0x80)))
-                goto out_unlock;
-        realirq &= 7;
-        if (unlikely(realirq == 2)) {
-                outb(0x0c, 0xa0);
-                realirq = inb(0xa0);
-                if (unlikely(!(realirq & 0x80)))
-                        goto out_unlock;
-                realirq = (realirq & 7) + 8;
-        }
-        /* mask and ack interrupt */
-        cached_irq_mask |= 1 << realirq;
-        if (unlikely(realirq > 7)) {
-                inb(0xa1);
-                outb(cached_slave_mask, 0xa1);
-                outb(0x60 + (realirq & 7), 0xa0);
-                outb(0x60 + 2, 0x20);
-        } else {
-                inb(0x21);
-                outb(cached_master_mask, 0x21);
-                outb(0x60 + realirq, 0x20);
-        }
-        raw_spin_unlock_irqrestore(&i8259A_lock, flags);
-        /*
-         * handle this 'virtual interrupt' as a Cobalt one now.
-         */
-        generic_handle_irq(realirq);
-        return IRQ_HANDLED;
-out_unlock:
-        raw_spin_unlock_irqrestore(&i8259A_lock, flags);
-        return IRQ_NONE;
-}
-static struct irqaction master_action = {
-        .handler =      piix4_master_intr,
-        .name =         "PIIX4-8259",
-        .flags =        IRQF_NO_THREAD,
-};
-static struct irqaction cascade_action = {
-        .handler =      no_action,
-        .name =         "cascade",
-        .flags =        IRQF_NO_THREAD,
-};
-static inline void set_piix4_virtual_irq_type(void)
-{
-        piix4_virtual_irq_type.irq_enable = i8259A_chip.irq_unmask;
-        piix4_virtual_irq_type.irq_disable = i8259A_chip.irq_mask;
-        piix4_virtual_irq_type.irq_unmask = i8259A_chip.irq_unmask;
-}
-static void __init visws_pre_intr_init(void)
-{
-        int i;
-        set_piix4_virtual_irq_type();
-        for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
-                struct irq_chip *chip = NULL;
-                if (i == 0)
-                        chip = &cobalt_irq_type;
-                else if (i == CO_IRQ_IDE0)
-                        chip = &cobalt_irq_type;
-                else if (i == CO_IRQ_IDE1)
-                        chip = &cobalt_irq_type;
-                else if (i == CO_IRQ_8259)
-                        chip = &piix4_master_irq_type;
-                else if (i < CO_IRQ_APIC0)
-                        chip = &piix4_virtual_irq_type;
-                else if (IS_CO_APIC(i))
-                        chip = &cobalt_irq_type;
-                if (chip)
-                        irq_set_chip(i, chip);
-        }
-        setup_irq(CO_IRQ_8259, &master_action);
-        setup_irq(2, &cascade_action);
-}
diff --git a/arch/x86/syscalls/syscall_64.tbl b/arch/x86/syscalls/syscall_64.tbl
index a12bddc7ccea..04376ac3d9ef 100644
--- a/arch/x86/syscalls/syscall_64.tbl
+++ b/arch/x86/syscalls/syscall_64.tbl
@@ -322,6 +322,7 @@
 313     common  finit_module            sys_finit_module
 314     common  sched_setattr           sys_sched_setattr
 315     common  sched_getattr           sys_sched_getattr
+316     common  renameat2               sys_renameat2
 #
 # x32-specific system call numbers start at 512 to avoid cache impact
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index cfbdbdb4e173..bbb1d2259ecf 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -69,8 +69,8 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
        "__per_cpu_load|"
        "init_per_cpu__.*|"
        "__end_rodata_hpage_align|"
-        "__vvar_page|"
 #endif
+        "__vvar_page|"
        "_end)$"
 };
diff --git a/arch/x86/vdso/Makefile b/arch/x86/vdso/Makefile
index 9206ac7961a5..c580d1210ffe 100644
--- a/arch/x86/vdso/Makefile
+++ b/arch/x86/vdso/Makefile
@@ -23,7 +23,8 @@ vobjs-$(VDSOX32-y) += $(vobjx32s-compat)
 vobj64s := $(filter-out $(vobjx32s-compat),$(vobjs-y))
 # files to link into kernel
-obj-$(VDSO64-y)                 += vma.o vdso.o
+obj-y                           += vma.o
+obj-$(VDSO64-y)                 += vdso.o
 obj-$(VDSOX32-y)                += vdsox32.o
 obj-$(VDSO32-y)                 += vdso32.o vdso32-setup.o
@@ -138,7 +139,7 @@ override obj-dirs = $(dir $(obj)) $(obj)/vdso32/
 targets += vdso32/vdso32.lds
 targets += $(vdso32-images) $(vdso32-images:=.dbg)
-targets += vdso32/note.o $(vdso32.so-y:%=vdso32/%.o)
+targets += vdso32/note.o vdso32/vclock_gettime.o $(vdso32.so-y:%=vdso32/%.o)
 extra-y += $(vdso32-images)
@@ -148,8 +149,19 @@ KBUILD_AFLAGS_32 := $(filter-out -m64,$(KBUILD_AFLAGS))
 $(vdso32-images:%=$(obj)/%.dbg): KBUILD_AFLAGS = $(KBUILD_AFLAGS_32)
 $(vdso32-images:%=$(obj)/%.dbg): asflags-$(CONFIG_X86_64) += -m32
+KBUILD_CFLAGS_32 := $(filter-out -m64,$(KBUILD_CFLAGS))
+KBUILD_CFLAGS_32 := $(filter-out -mcmodel=kernel,$(KBUILD_CFLAGS_32))
+KBUILD_CFLAGS_32 := $(filter-out -fno-pic,$(KBUILD_CFLAGS_32))
+KBUILD_CFLAGS_32 := $(filter-out -mfentry,$(KBUILD_CFLAGS_32))
+KBUILD_CFLAGS_32 += -m32 -msoft-float -mregparm=0 -fpic
+KBUILD_CFLAGS_32 += $(call cc-option, -fno-stack-protector)
+KBUILD_CFLAGS_32 += $(call cc-option, -foptimize-sibling-calls)
+KBUILD_CFLAGS_32 += -fno-omit-frame-pointer
+$(vdso32-images:%=$(obj)/%.dbg): KBUILD_CFLAGS = $(KBUILD_CFLAGS_32)
 $(vdso32-images:%=$(obj)/%.dbg): $(obj)/vdso32-%.so.dbg: FORCE \
                                 $(obj)/vdso32/vdso32.lds \
+                                 $(obj)/vdso32/vclock_gettime.o \
                                 $(obj)/vdso32/note.o \
                                 $(obj)/vdso32/%.o
        $(call if_changed,vdso)
diff --git a/arch/x86/vdso/vclock_gettime.c b/arch/x86/vdso/vclock_gettime.c
index eb5d7a56f8d4..16d686171e9a 100644
--- a/arch/x86/vdso/vclock_gettime.c
+++ b/arch/x86/vdso/vclock_gettime.c
@@ -4,6 +4,9 @@
 *
 * Fast user context implementation of clock_gettime, gettimeofday, and time.
 *
+ * 32 Bit compat layer by Stefani Seibold <stefani@seibold.net>
+ *  sponsored by Rohde & Schwarz GmbH & Co. KG Munich/Germany
+ *
 * The code should have no internal unresolved relocations.
 * Check with readelf after changing.
 */
@@ -11,56 +14,55 @@
 /* Disable profiling for userspace code: */
 #define DISABLE_BRANCH_PROFILING
-#include <linux/kernel.h>
+#include <uapi/linux/time.h>
-#include <linux/posix-timers.h>
-#include <linux/time.h>
-#include <linux/string.h>
-#include <asm/vsyscall.h>
-#include <asm/fixmap.h>
 #include <asm/vgtod.h>
-#include <asm/timex.h>
 #include <asm/hpet.h>
+#include <asm/vvar.h>
 #include <asm/unistd.h>
-#include <asm/io.h>
+#include <asm/msr.h>
-#include <asm/pvclock.h>
+#include <linux/math64.h>
+#include <linux/time.h>
 #define gtod (&VVAR(vsyscall_gtod_data))
-notrace static cycle_t vread_tsc(void)
+extern int __vdso_clock_gettime(clockid_t clock, struct timespec *ts);
+extern int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz);
+extern time_t __vdso_time(time_t *t);
+#ifdef CONFIG_HPET_TIMER
+static inline u32 read_hpet_counter(const volatile void *addr)
 {
-        cycle_t ret;
+        return *(const volatile u32 *) (addr + HPET_COUNTER);
-        u64 last;
+}
+#endif
-        /*
+#ifndef BUILD_VDSO32
-         * Empirically, a fence (of type that depends on the CPU)
-         * before rdtsc is enough to ensure that rdtsc is ordered
-         * with respect to loads.  The various CPU manuals are unclear
-         * as to whether rdtsc can be reordered with later loads,
-         * but no one has ever seen it happen.
-         */
-        rdtsc_barrier();
-        ret = (cycle_t)vget_cycles();
-        last = VVAR(vsyscall_gtod_data).clock.cycle_last;
+#include <linux/kernel.h>
+#include <asm/vsyscall.h>
+#include <asm/fixmap.h>
+#include <asm/pvclock.h>
-        if (likely(ret >= last))
+static notrace cycle_t vread_hpet(void)
-                return ret;
+{
+        return read_hpet_counter((const void *)fix_to_virt(VSYSCALL_HPET));
+}
-        /*
+notrace static long vdso_fallback_gettime(long clock, struct timespec *ts)
-         * GCC likes to generate cmov here, but this branch is extremely
+{
-         * predictable (it's just a funciton of time and the likely is
+        long ret;
-         * very likely) and there's a data dependence, so force GCC
+        asm("syscall" : "=a" (ret) :
-         * to generate a branch instead.  I don't barrier() because
+            "0" (__NR_clock_gettime), "D" (clock), "S" (ts) : "memory");
-         * we don't actually need a barrier, and if this function
+        return ret;
-         * ever gets inlined it will generate worse code.
-         */
-        asm volatile ("");
-        return last;
 }
-static notrace cycle_t vread_hpet(void)
+notrace static long vdso_fallback_gtod(struct timeval *tv, struct timezone *tz)
 {
-        return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + HPET_COUNTER);
+        long ret;
+        asm("syscall" : "=a" (ret) :
+            "0" (__NR_gettimeofday), "D" (tv), "S" (tz) : "memory");
+        return ret;
 }
 #ifdef CONFIG_PARAVIRT_CLOCK
@@ -124,7 +126,7 @@ static notrace cycle_t vread_pvclock(int *mode)
                *mode = VCLOCK_NONE;
        /* refer to tsc.c read_tsc() comment for rationale */
-        last = VVAR(vsyscall_gtod_data).clock.cycle_last;
+        last = gtod->cycle_last;
        if (likely(ret >= last))
                return ret;
@@ -133,11 +135,30 @@ static notrace cycle_t vread_pvclock(int *mode)
 }
 #endif
+#else
+extern u8 hpet_page
+        __attribute__((visibility("hidden")));
+#ifdef CONFIG_HPET_TIMER
+static notrace cycle_t vread_hpet(void)
+{
+        return read_hpet_counter((const void *)(&hpet_page));
+}
+#endif
 notrace static long vdso_fallback_gettime(long clock, struct timespec *ts)
 {
        long ret;
-        asm("syscall" : "=a" (ret) :
-            "0" (__NR_clock_gettime),"D" (clock), "S" (ts) : "memory");
+        asm(
+                "mov %%ebx, %%edx \n"
+                "mov %2, %%ebx \n"
+                "call VDSO32_vsyscall \n"
+                "mov %%edx, %%ebx \n"
+                : "=a" (ret)
+                : "0" (__NR_clock_gettime), "g" (clock), "c" (ts)
+                : "memory", "edx");
        return ret;
 }
@@ -145,28 +166,79 @@ notrace static long vdso_fallback_gtod(struct timeval *tv, struct timezone *tz)
 {
        long ret;
-        asm("syscall" : "=a" (ret) :
+        asm(
-            "0" (__NR_gettimeofday), "D" (tv), "S" (tz) : "memory");
+                "mov %%ebx, %%edx \n"
+                "mov %2, %%ebx \n"
+                "call VDSO32_vsyscall \n"
+                "mov %%edx, %%ebx \n"
+                : "=a" (ret)
+                : "0" (__NR_gettimeofday), "g" (tv), "c" (tz)
+                : "memory", "edx");
        return ret;
 }
+#ifdef CONFIG_PARAVIRT_CLOCK
+static notrace cycle_t vread_pvclock(int *mode)
+{
+        *mode = VCLOCK_NONE;
+        return 0;
+}
+#endif
+#endif
+notrace static cycle_t vread_tsc(void)
+{
+        cycle_t ret;
+        u64 last;
+        /*
+         * Empirically, a fence (of type that depends on the CPU)
+         * before rdtsc is enough to ensure that rdtsc is ordered
+         * with respect to loads.  The various CPU manuals are unclear
+         * as to whether rdtsc can be reordered with later loads,
+         * but no one has ever seen it happen.
+         */
+        rdtsc_barrier();
+        ret = (cycle_t)__native_read_tsc();
+        last = gtod->cycle_last;
+        if (likely(ret >= last))
+                return ret;
+        /*
+         * GCC likes to generate cmov here, but this branch is extremely
+         * predictable (it's just a funciton of time and the likely is
+         * very likely) and there's a data dependence, so force GCC
+         * to generate a branch instead.  I don't barrier() because
+         * we don't actually need a barrier, and if this function
+         * ever gets inlined it will generate worse code.
+         */
+        asm volatile ("");
+        return last;
+}
 notrace static inline u64 vgetsns(int *mode)
 {
-        long v;
+        u64 v;
        cycles_t cycles;
-        if (gtod->clock.vclock_mode == VCLOCK_TSC)
+        if (gtod->vclock_mode == VCLOCK_TSC)
                cycles = vread_tsc();
-        else if (gtod->clock.vclock_mode == VCLOCK_HPET)
+#ifdef CONFIG_HPET_TIMER
+        else if (gtod->vclock_mode == VCLOCK_HPET)
                cycles = vread_hpet();
+#endif
 #ifdef CONFIG_PARAVIRT_CLOCK
-        else if (gtod->clock.vclock_mode == VCLOCK_PVCLOCK)
+        else if (gtod->vclock_mode == VCLOCK_PVCLOCK)
                cycles = vread_pvclock(mode);
 #endif
        else
                return 0;
-        v = (cycles - gtod->clock.cycle_last) & gtod->clock.mask;
+        v = (cycles - gtod->cycle_last) & gtod->mask;
-        return v * gtod->clock.mult;
+        return v * gtod->mult;
 }
 /* Code size doesn't matter (vdso is 4k anyway) and this is faster. */
@@ -176,106 +248,102 @@ notrace static int __always_inline do_realtime(struct timespec *ts)
        u64 ns;
        int mode;
-        ts->tv_nsec = 0;
        do {
-                seq = raw_read_seqcount_begin(&gtod->seq);
+                seq = gtod_read_begin(gtod);
-                mode = gtod->clock.vclock_mode;
+                mode = gtod->vclock_mode;
                ts->tv_sec = gtod->wall_time_sec;
                ns = gtod->wall_time_snsec;
                ns += vgetsns(&mode);
-                ns >>= gtod->clock.shift;
+                ns >>= gtod->shift;
-        } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
+        } while (unlikely(gtod_read_retry(gtod, seq)));
+        ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
+        ts->tv_nsec = ns;
-        timespec_add_ns(ts, ns);
        return mode;
 }
-notrace static int do_monotonic(struct timespec *ts)
+notrace static int __always_inline do_monotonic(struct timespec *ts)
 {
        unsigned long seq;
        u64 ns;
        int mode;
-        ts->tv_nsec = 0;
        do {
-                seq = raw_read_seqcount_begin(&gtod->seq);
+                seq = gtod_read_begin(gtod);
-                mode = gtod->clock.vclock_mode;
+                mode = gtod->vclock_mode;
                ts->tv_sec = gtod->monotonic_time_sec;
                ns = gtod->monotonic_time_snsec;
                ns += vgetsns(&mode);
-                ns >>= gtod->clock.shift;
+                ns >>= gtod->shift;
-        } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
+        } while (unlikely(gtod_read_retry(gtod, seq)));
-        timespec_add_ns(ts, ns);
+        ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
+        ts->tv_nsec = ns;
        return mode;
 }
-notrace static int do_realtime_coarse(struct timespec *ts)
+notrace static void do_realtime_coarse(struct timespec *ts)
 {
        unsigned long seq;
        do {
-                seq = raw_read_seqcount_begin(&gtod->seq);
+                seq = gtod_read_begin(gtod);
-                ts->tv_sec = gtod->wall_time_coarse.tv_sec;
+                ts->tv_sec = gtod->wall_time_coarse_sec;
-                ts->tv_nsec = gtod->wall_time_coarse.tv_nsec;
+                ts->tv_nsec = gtod->wall_time_coarse_nsec;
-        } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
+        } while (unlikely(gtod_read_retry(gtod, seq)));
-        return 0;
 }
-notrace static int do_monotonic_coarse(struct timespec *ts)
+notrace static void do_monotonic_coarse(struct timespec *ts)
 {
        unsigned long seq;
        do {
-                seq = raw_read_seqcount_begin(&gtod->seq);
+                seq = gtod_read_begin(gtod);
-                ts->tv_sec = gtod->monotonic_time_coarse.tv_sec;
+                ts->tv_sec = gtod->monotonic_time_coarse_sec;
-                ts->tv_nsec = gtod->monotonic_time_coarse.tv_nsec;
+                ts->tv_nsec = gtod->monotonic_time_coarse_nsec;
-        } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
+        } while (unlikely(gtod_read_retry(gtod, seq)));
-        return 0;
 }
 notrace int __vdso_clock_gettime(clockid_t clock, struct timespec *ts)
 {
-        int ret = VCLOCK_NONE;
        switch (clock) {
        case CLOCK_REALTIME:
-                ret = do_realtime(ts);
+                if (do_realtime(ts) == VCLOCK_NONE)
+                        goto fallback;
                break;
        case CLOCK_MONOTONIC:
-                ret = do_monotonic(ts);
+                if (do_monotonic(ts) == VCLOCK_NONE)
+                        goto fallback;
                break;
        case CLOCK_REALTIME_COARSE:
-                return do_realtime_coarse(ts);
+                do_realtime_coarse(ts);
+                break;
        case CLOCK_MONOTONIC_COARSE:
-                return do_monotonic_coarse(ts);
+                do_monotonic_coarse(ts);
+                break;
+        default:
+                goto fallback;
        }
-        if (ret == VCLOCK_NONE)
-                return vdso_fallback_gettime(clock, ts);
        return 0;
+fallback:
+        return vdso_fallback_gettime(clock, ts);
 }
 int clock_gettime(clockid_t, struct timespec *)
        __attribute__((weak, alias("__vdso_clock_gettime")));
 notrace int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
 {
-        long ret = VCLOCK_NONE;
        if (likely(tv != NULL)) {
-                BUILD_BUG_ON(offsetof(struct timeval, tv_usec) !=
+                if (unlikely(do_realtime((struct timespec *)tv) == VCLOCK_NONE))
-                             offsetof(struct timespec, tv_nsec) ||
+                        return vdso_fallback_gtod(tv, tz);
-                             sizeof(*tv) != sizeof(struct timespec));
-                ret = do_realtime((struct timespec *)tv);
                tv->tv_usec /= 1000;
        }
        if (unlikely(tz != NULL)) {
-                /* Avoid memcpy. Some old compilers fail to inline it */
+                tz->tz_minuteswest = gtod->tz_minuteswest;
-                tz->tz_minuteswest = gtod->sys_tz.tz_minuteswest;
+                tz->tz_dsttime = gtod->tz_dsttime;
-                tz->tz_dsttime = gtod->sys_tz.tz_dsttime;
        }
-        if (ret == VCLOCK_NONE)
-                return vdso_fallback_gtod(tv, tz);
        return 0;
 }
 int gettimeofday(struct timeval *, struct timezone *)
@@ -287,8 +355,8 @@ int gettimeofday(struct timeval *, struct timezone *)
 */
 notrace time_t __vdso_time(time_t *t)
 {
-        /* This is atomic on x86_64 so we don't need any locks. */
+        /* This is atomic on x86 so we don't need any locks. */
-        time_t result = ACCESS_ONCE(VVAR(vsyscall_gtod_data).wall_time_sec);
+        time_t result = ACCESS_ONCE(gtod->wall_time_sec);
        if (t)
                *t = result;
diff --git a/arch/x86/vdso/vdso-layout.lds.S b/arch/x86/vdso/vdso-layout.lds.S
index 634a2cf62046..2e263f367b13 100644
--- a/arch/x86/vdso/vdso-layout.lds.S
+++ b/arch/x86/vdso/vdso-layout.lds.S
@@ -6,7 +6,25 @@
 SECTIONS
 {
-        . = VDSO_PRELINK + SIZEOF_HEADERS;
+#ifdef BUILD_VDSO32
+#include <asm/vdso32.h>
+        .hpet_sect : {
+                hpet_page = . - VDSO_OFFSET(VDSO_HPET_PAGE);
+        } :text :hpet_sect
+        .vvar_sect : {
+                vvar = . - VDSO_OFFSET(VDSO_VVAR_PAGE);
+        /* Place all vvars at the offsets in asm/vvar.h. */
+#define EMIT_VVAR(name, offset) vvar_ ## name = vvar + offset;
+#define __VVAR_KERNEL_LDS
+#include <asm/vvar.h>
+#undef __VVAR_KERNEL_LDS
+#undef EMIT_VVAR
+        } :text :vvar_sect
+#endif
+        . = SIZEOF_HEADERS;
        .hash           : { *(.hash) }                  :text
        .gnu.hash       : { *(.gnu.hash) }
@@ -44,6 +62,11 @@ SECTIONS
        . = ALIGN(0x100);
        .text           : { *(.text*) }                 :text   =0x90909090
+        /DISCARD/ : {
+                *(.discard)
+                *(.discard.*)
+        }
 }
 /*
@@ -61,4 +84,8 @@ PHDRS
        dynamic         PT_DYNAMIC      FLAGS(4);               /* PF_R */
        note            PT_NOTE         FLAGS(4);               /* PF_R */
        eh_frame_hdr    PT_GNU_EH_FRAME;
+#ifdef BUILD_VDSO32
+        vvar_sect       PT_NULL         FLAGS(4);               /* PF_R */
+        hpet_sect       PT_NULL         FLAGS(4);               /* PF_R */
+#endif
 }
diff --git a/arch/x86/vdso/vdso.S b/arch/x86/vdso/vdso.S
index 1e13eb8c9656..be3f23b09af5 100644
--- a/arch/x86/vdso/vdso.S
+++ b/arch/x86/vdso/vdso.S
@@ -1,21 +1,3 @@
-#include <asm/page_types.h>
+#include <asm/vdso.h>
-#include <linux/linkage.h>
-__PAGE_ALIGNED_DATA
+DEFINE_VDSO_IMAGE(vdso, "arch/x86/vdso/vdso.so")
-        .globl vdso_start, vdso_end
-        .align PAGE_SIZE
-vdso_start:
-        .incbin "arch/x86/vdso/vdso.so"
-vdso_end:
-        .align PAGE_SIZE /* extra data here leaks to userspace. */
-.previous
-        .globl vdso_pages
-        .bss
-        .align 8
-        .type vdso_pages, @object
-vdso_pages:
-        .zero (vdso_end - vdso_start + PAGE_SIZE - 1) / PAGE_SIZE * 8
-        .size vdso_pages, .-vdso_pages
diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c
index d6bfb876cfb0..00348980a3a6 100644
--- a/arch/x86/vdso/vdso32-setup.c
+++ b/arch/x86/vdso/vdso32-setup.c
@@ -16,6 +16,7 @@
 #include <linux/mm.h>
 #include <linux/err.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <asm/cpufeature.h>
 #include <asm/msr.h>
@@ -25,17 +26,14 @@
 #include <asm/tlbflush.h>
 #include <asm/vdso.h>
 #include <asm/proto.h>
+#include <asm/fixmap.h>
-enum {
+#include <asm/hpet.h>
-        VDSO_DISABLED = 0,
+#include <asm/vvar.h>
-        VDSO_ENABLED = 1,
-        VDSO_COMPAT = 2,
-};
 #ifdef CONFIG_COMPAT_VDSO
-#define VDSO_DEFAULT    VDSO_COMPAT
+#define VDSO_DEFAULT    0
 #else
-#define VDSO_DEFAULT    VDSO_ENABLED
+#define VDSO_DEFAULT    1
 #endif
 #ifdef CONFIG_X86_64
@@ -44,13 +42,6 @@ enum {
 #endif
 /*
- * This is the difference between the prelinked addresses in the vDSO images
- * and the VDSO_HIGH_BASE address where CONFIG_COMPAT_VDSO places the vDSO
- * in the user address space.
- */
-#define VDSO_ADDR_ADJUST        (VDSO_HIGH_BASE - (unsigned long)VDSO32_PRELINK)
-/*
 * Should the kernel map a VDSO page into processes and pass its
 * address down to glibc upon exec()?
 */
@@ -60,6 +51,9 @@ static int __init vdso_setup(char *s)
 {
        vdso_enabled = simple_strtoul(s, NULL, 0);
+        if (vdso_enabled > 1)
+                pr_warn("vdso32 values other than 0 and 1 are no longer allowed; vdso disabled\n");
        return 1;
 }
@@ -76,124 +70,8 @@ __setup_param("vdso=", vdso32_setup, vdso_setup, 0);
 EXPORT_SYMBOL_GPL(vdso_enabled);
 #endif
-static __init void reloc_symtab(Elf32_Ehdr *ehdr,
+static struct page **vdso32_pages;
-                                unsigned offset, unsigned size)
+static unsigned vdso32_size;
-{
-        Elf32_Sym *sym = (void *)ehdr + offset;
-        unsigned nsym = size / sizeof(*sym);
-        unsigned i;
-        for(i = 0; i < nsym; i++, sym++) {
-                if (sym->st_shndx == SHN_UNDEF ||
-                    sym->st_shndx == SHN_ABS)
-                        continue;  /* skip */
-                if (sym->st_shndx > SHN_LORESERVE) {
-                        printk(KERN_INFO "VDSO: unexpected st_shndx %x\n",
-                               sym->st_shndx);
-                        continue;
-                }
-                switch(ELF_ST_TYPE(sym->st_info)) {
-                case STT_OBJECT:
-                case STT_FUNC:
-                case STT_SECTION:
-                case STT_FILE:
-                        sym->st_value += VDSO_ADDR_ADJUST;
-                }
-        }
-}
-static __init void reloc_dyn(Elf32_Ehdr *ehdr, unsigned offset)
-{
-        Elf32_Dyn *dyn = (void *)ehdr + offset;
-        for(; dyn->d_tag != DT_NULL; dyn++)
-                switch(dyn->d_tag) {
-                case DT_PLTGOT:
-                case DT_HASH:
-                case DT_STRTAB:
-                case DT_SYMTAB:
-                case DT_RELA:
-                case DT_INIT:
-                case DT_FINI:
-                case DT_REL:
-                case DT_DEBUG:
-                case DT_JMPREL:
-                case DT_VERSYM:
-                case DT_VERDEF:
-                case DT_VERNEED:
-                case DT_ADDRRNGLO ... DT_ADDRRNGHI:
-                        /* definitely pointers needing relocation */
-                        dyn->d_un.d_ptr += VDSO_ADDR_ADJUST;
-                        break;
-                case DT_ENCODING ... OLD_DT_LOOS-1:
-                case DT_LOOS ... DT_HIOS-1:
-                        /* Tags above DT_ENCODING are pointers if
-                           they're even */
-                        if (dyn->d_tag >= DT_ENCODING &&
-                            (dyn->d_tag & 1) == 0)
-                                dyn->d_un.d_ptr += VDSO_ADDR_ADJUST;
-                        break;
-                case DT_VERDEFNUM:
-                case DT_VERNEEDNUM:
-                case DT_FLAGS_1:
-                case DT_RELACOUNT:
-                case DT_RELCOUNT:
-                case DT_VALRNGLO ... DT_VALRNGHI:
-                        /* definitely not pointers */
-                        break;
-                case OLD_DT_LOOS ... DT_LOOS-1:
-                case DT_HIOS ... DT_VALRNGLO-1:
-                default:
-                        if (dyn->d_tag > DT_ENCODING)
-                                printk(KERN_INFO "VDSO: unexpected DT_tag %x\n",
-                                       dyn->d_tag);
-                        break;
-                }
-}
-static __init void relocate_vdso(Elf32_Ehdr *ehdr)
-{
-        Elf32_Phdr *phdr;
-        Elf32_Shdr *shdr;
-        int i;
-        BUG_ON(memcmp(ehdr->e_ident, ELFMAG, SELFMAG) != 0 ||
-               !elf_check_arch_ia32(ehdr) ||
-               ehdr->e_type != ET_DYN);
-        ehdr->e_entry += VDSO_ADDR_ADJUST;
-        /* rebase phdrs */
-        phdr = (void *)ehdr + ehdr->e_phoff;
-        for (i = 0; i < ehdr->e_phnum; i++) {
-                phdr[i].p_vaddr += VDSO_ADDR_ADJUST;
-                /* relocate dynamic stuff */
-                if (phdr[i].p_type == PT_DYNAMIC)
-                        reloc_dyn(ehdr, phdr[i].p_offset);
-        }
-        /* rebase sections */
-        shdr = (void *)ehdr + ehdr->e_shoff;
-        for(i = 0; i < ehdr->e_shnum; i++) {
-                if (!(shdr[i].sh_flags & SHF_ALLOC))
-                        continue;
-                shdr[i].sh_addr += VDSO_ADDR_ADJUST;
-                if (shdr[i].sh_type == SHT_SYMTAB ||
-                    shdr[i].sh_type == SHT_DYNSYM)
-                        reloc_symtab(ehdr, shdr[i].sh_offset,
-                                     shdr[i].sh_size);
-        }
-}
-static struct page *vdso32_pages[1];
 #ifdef CONFIG_X86_64
@@ -212,12 +90,6 @@ void syscall32_cpu_init(void)
        wrmsrl(MSR_CSTAR, ia32_cstar_target);
 }
-#define compat_uses_vma         1
-static inline void map_compat_vdso(int map)
-{
-}
 #else  /* CONFIG_X86_32 */
 #define vdso32_sysenter()       (boot_cpu_has(X86_FEATURE_SEP))
@@ -241,64 +113,36 @@ void enable_sep_cpu(void)
        put_cpu();      
 }
-static struct vm_area_struct gate_vma;
-static int __init gate_vma_init(void)
-{
-        gate_vma.vm_mm = NULL;
-        gate_vma.vm_start = FIXADDR_USER_START;
-        gate_vma.vm_end = FIXADDR_USER_END;
-        gate_vma.vm_flags = VM_READ | VM_MAYREAD | VM_EXEC | VM_MAYEXEC;
-        gate_vma.vm_page_prot = __P101;
-        return 0;
-}
-#define compat_uses_vma         0
-static void map_compat_vdso(int map)
-{
-        static int vdso_mapped;
-        if (map == vdso_mapped)
-                return;
-        vdso_mapped = map;
-        __set_fixmap(FIX_VDSO, page_to_pfn(vdso32_pages[0]) << PAGE_SHIFT,
-                     map ? PAGE_READONLY_EXEC : PAGE_NONE);
-        /* flush stray tlbs */
-        flush_tlb_all();
-}
 #endif  /* CONFIG_X86_64 */
 int __init sysenter_setup(void)
 {
-        void *syscall_page = (void *)get_zeroed_page(GFP_ATOMIC);
+        char *vdso32_start, *vdso32_end;
-        const void *vsyscall;
+        int npages, i;
-        size_t vsyscall_len;
-        vdso32_pages[0] = virt_to_page(syscall_page);
-#ifdef CONFIG_X86_32
-        gate_vma_init();
-#endif
+#ifdef CONFIG_COMPAT
        if (vdso32_syscall()) {
-                vsyscall = &vdso32_syscall_start;
+                vdso32_start = vdso32_syscall_start;
-                vsyscall_len = &vdso32_syscall_end - &vdso32_syscall_start;
+                vdso32_end = vdso32_syscall_end;
-        } else if (vdso32_sysenter()){
+                vdso32_pages = vdso32_syscall_pages;
-                vsyscall = &vdso32_sysenter_start;
+        } else
-                vsyscall_len = &vdso32_sysenter_end - &vdso32_sysenter_start;
+#endif
+        if (vdso32_sysenter()) {
+                vdso32_start = vdso32_sysenter_start;
+                vdso32_end = vdso32_sysenter_end;
+                vdso32_pages = vdso32_sysenter_pages;
        } else {
-                vsyscall = &vdso32_int80_start;
+                vdso32_start = vdso32_int80_start;
-                vsyscall_len = &vdso32_int80_end - &vdso32_int80_start;
+                vdso32_end = vdso32_int80_end;
+                vdso32_pages = vdso32_int80_pages;
        }
-        memcpy(syscall_page, vsyscall, vsyscall_len);
+        npages = ((vdso32_end - vdso32_start) + PAGE_SIZE - 1) / PAGE_SIZE;
-        relocate_vdso(syscall_page);
+        vdso32_size = npages << PAGE_SHIFT;
+        for (i = 0; i < npages; i++)
+                vdso32_pages[i] = virt_to_page(vdso32_start + i*PAGE_SIZE);
+        patch_vdso32(vdso32_start, vdso32_size);
        return 0;
 }
@@ -309,48 +153,73 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
        struct mm_struct *mm = current->mm;
        unsigned long addr;
        int ret = 0;
-        bool compat;
+        struct vm_area_struct *vma;
 #ifdef CONFIG_X86_X32_ABI
        if (test_thread_flag(TIF_X32))
                return x32_setup_additional_pages(bprm, uses_interp);
 #endif
-        if (vdso_enabled == VDSO_DISABLED)
+        if (vdso_enabled != 1)  /* Other values all mean "disabled" */
                return 0;
        down_write(&mm->mmap_sem);
-        /* Test compat mode once here, in case someone
+        addr = get_unmapped_area(NULL, 0, vdso32_size + VDSO_OFFSET(VDSO_PREV_PAGES), 0, 0);
-           changes it via sysctl */
+        if (IS_ERR_VALUE(addr)) {
-        compat = (vdso_enabled == VDSO_COMPAT);
+                ret = addr;
+                goto up_fail;
+        }
+        addr += VDSO_OFFSET(VDSO_PREV_PAGES);
-        map_compat_vdso(compat);
+        current->mm->context.vdso = (void *)addr;
-        if (compat)
+        /*
-                addr = VDSO_HIGH_BASE;
+         * MAYWRITE to allow gdb to COW and set breakpoints
-        else {
+         */
-                addr = get_unmapped_area(NULL, 0, PAGE_SIZE, 0, 0);
+        ret = install_special_mapping(mm,
-                if (IS_ERR_VALUE(addr)) {
+                        addr,
-                        ret = addr;
+                        vdso32_size,
-                        goto up_fail;
+                        VM_READ|VM_EXEC|
-                }
+                        VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
+                        vdso32_pages);
+        if (ret)
+                goto up_fail;
+        vma = _install_special_mapping(mm,
+                        addr -  VDSO_OFFSET(VDSO_PREV_PAGES),
+                        VDSO_OFFSET(VDSO_PREV_PAGES),
+                        VM_READ,
+                        NULL);
+        if (IS_ERR(vma)) {
+                ret = PTR_ERR(vma);
+                goto up_fail;
        }
-        current->mm->context.vdso = (void *)addr;
+        ret = remap_pfn_range(vma,
+                addr - VDSO_OFFSET(VDSO_VVAR_PAGE),
+                __pa_symbol(&__vvar_page) >> PAGE_SHIFT,
+                PAGE_SIZE,
+                PAGE_READONLY);
+        if (ret)
+                goto up_fail;
-        if (compat_uses_vma || !compat) {
+#ifdef CONFIG_HPET_TIMER
-                /*
+        if (hpet_address) {
-                 * MAYWRITE to allow gdb to COW and set breakpoints
+                ret = io_remap_pfn_range(vma,
-                 */
+                        addr - VDSO_OFFSET(VDSO_HPET_PAGE),
-                ret = install_special_mapping(mm, addr, PAGE_SIZE,
+                        hpet_address >> PAGE_SHIFT,
-                                              VM_READ|VM_EXEC|
+                        PAGE_SIZE,
-                                              VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
+                        pgprot_noncached(PAGE_READONLY));
-                                              vdso32_pages);
                if (ret)
                        goto up_fail;
        }
+#endif
        current_thread_info()->sysenter_return =
                VDSO32_SYMBOL(addr, SYSENTER_RETURN);
@@ -411,20 +280,12 @@ const char *arch_vma_name(struct vm_area_struct *vma)
 struct vm_area_struct *get_gate_vma(struct mm_struct *mm)
 {
-        /*
-         * Check to see if the corresponding task was created in compat vdso
-         * mode.
-         */
-        if (mm && mm->context.vdso == (void *)VDSO_HIGH_BASE)
-                return &gate_vma;
        return NULL;
 }
 int in_gate_area(struct mm_struct *mm, unsigned long addr)
 {
-        const struct vm_area_struct *vma = get_gate_vma(mm);
+        return 0;
-        return vma && addr >= vma->vm_start && addr < vma->vm_end;
 }
 int in_gate_area_no_mm(unsigned long addr)
diff --git a/arch/x86/vdso/vdso32.S b/arch/x86/vdso/vdso32.S
index 2ce5f82c333b..018bcd9f97b4 100644
--- a/arch/x86/vdso/vdso32.S
+++ b/arch/x86/vdso/vdso32.S
@@ -1,22 +1,9 @@
-#include <linux/init.h>
+#include <asm/vdso.h>
-__INITDATA
+DEFINE_VDSO_IMAGE(vdso32_int80, "arch/x86/vdso/vdso32-int80.so")
-        .globl vdso32_int80_start, vdso32_int80_end
-vdso32_int80_start:
-        .incbin "arch/x86/vdso/vdso32-int80.so"
-vdso32_int80_end:
-        .globl vdso32_syscall_start, vdso32_syscall_end
-vdso32_syscall_start:
 #ifdef CONFIG_COMPAT
-        .incbin "arch/x86/vdso/vdso32-syscall.so"
+DEFINE_VDSO_IMAGE(vdso32_syscall, "arch/x86/vdso/vdso32-syscall.so")
 #endif
-vdso32_syscall_end:
-        .globl vdso32_sysenter_start, vdso32_sysenter_end
-vdso32_sysenter_start:
-        .incbin "arch/x86/vdso/vdso32-sysenter.so"
-vdso32_sysenter_end:
-__FINIT
+DEFINE_VDSO_IMAGE(vdso32_sysenter, "arch/x86/vdso/vdso32-sysenter.so")
diff --git a/arch/x86/vdso/vdso32/vclock_gettime.c b/arch/x86/vdso/vdso32/vclock_gettime.c
new file mode 100644
index 000000000000..175cc72c0f68
--- /dev/null
+++ b/arch/x86/vdso/vdso32/vclock_gettime.c
@@ -0,0 +1,30 @@
+#define BUILD_VDSO32
+#ifndef CONFIG_CC_OPTIMIZE_FOR_SIZE
+#undef CONFIG_OPTIMIZE_INLINING
+#endif
+#undef CONFIG_X86_PPRO_FENCE
+#ifdef CONFIG_X86_64
+/*
+ * in case of a 32 bit VDSO for a 64 bit kernel fake a 32 bit kernel
+ * configuration
+ */
+#undef CONFIG_64BIT
+#undef CONFIG_X86_64
+#undef CONFIG_ILLEGAL_POINTER_VALUE
+#undef CONFIG_SPARSEMEM_VMEMMAP
+#undef CONFIG_NR_CPUS
+#define CONFIG_X86_32 1
+#define CONFIG_PAGE_OFFSET 0
+#define CONFIG_ILLEGAL_POINTER_VALUE 0
+#define CONFIG_NR_CPUS 1
+#define BUILD_VDSO32_64
+#endif
+#include "../vclock_gettime.c"
diff --git a/arch/x86/vdso/vdso32/vdso32.lds.S b/arch/x86/vdso/vdso32/vdso32.lds.S
index 976124bb5f92..aadb8b9994cd 100644
--- a/arch/x86/vdso/vdso32/vdso32.lds.S
+++ b/arch/x86/vdso/vdso32/vdso32.lds.S
@@ -8,7 +8,11 @@
 * values visible using the asm-x86/vdso.h macros from the kernel proper.
 */
+#include <asm/page.h>
+#define BUILD_VDSO32
 #define VDSO_PRELINK 0
 #include "../vdso-layout.lds.S"
 /* The ELF entry point can be used to set the AT_SYSINFO value.  */
@@ -19,6 +23,13 @@ ENTRY(__kernel_vsyscall);
 */
 VERSION
 {
+        LINUX_2.6 {
+        global:
+                __vdso_clock_gettime;
+                __vdso_gettimeofday;
+                __vdso_time;
+        };
        LINUX_2.5 {
        global:
                __kernel_vsyscall;
@@ -31,7 +42,9 @@ VERSION
 /*
 * Symbols we define here called VDSO* get their values into vdso32-syms.h.
 */
-VDSO32_PRELINK          = VDSO_PRELINK;
 VDSO32_vsyscall         = __kernel_vsyscall;
 VDSO32_sigreturn        = __kernel_sigreturn;
 VDSO32_rt_sigreturn     = __kernel_rt_sigreturn;
+VDSO32_clock_gettime    = clock_gettime;
+VDSO32_gettimeofday     = gettimeofday;
+VDSO32_time             = time;
diff --git a/arch/x86/vdso/vdsox32.S b/arch/x86/vdso/vdsox32.S
index 295f1c7543d8..f4aa34e7f370 100644
--- a/arch/x86/vdso/vdsox32.S
+++ b/arch/x86/vdso/vdsox32.S
@@ -1,21 +1,3 @@
-#include <asm/page_types.h>
+#include <asm/vdso.h>
-#include <linux/linkage.h>
-__PAGE_ALIGNED_DATA
+DEFINE_VDSO_IMAGE(vdsox32, "arch/x86/vdso/vdsox32.so")
-        .globl vdsox32_start, vdsox32_end
-        .align PAGE_SIZE
-vdsox32_start:
-        .incbin "arch/x86/vdso/vdsox32.so"
-vdsox32_end:
-        .align PAGE_SIZE /* extra data here leaks to userspace. */
-.previous
-        .globl vdsox32_pages
-        .bss
-        .align 8
-        .type vdsox32_pages, @object
-vdsox32_pages:
-        .zero (vdsox32_end - vdsox32_start + PAGE_SIZE - 1) / PAGE_SIZE * 8
-        .size vdsox32_pages, .-vdsox32_pages
diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c
index 431e87544411..1ad102613127 100644
--- a/arch/x86/vdso/vma.c
+++ b/arch/x86/vdso/vma.c
@@ -16,20 +16,22 @@
 #include <asm/vdso.h>
 #include <asm/page.h>
+#if defined(CONFIG_X86_64)
 unsigned int __read_mostly vdso_enabled = 1;
-extern char vdso_start[], vdso_end[];
+DECLARE_VDSO_IMAGE(vdso);
 extern unsigned short vdso_sync_cpuid;
-extern struct page *vdso_pages[];
 static unsigned vdso_size;
 #ifdef CONFIG_X86_X32_ABI
-extern char vdsox32_start[], vdsox32_end[];
+DECLARE_VDSO_IMAGE(vdsox32);
-extern struct page *vdsox32_pages[];
 static unsigned vdsox32_size;
+#endif
+#endif
-static void __init patch_vdsox32(void *vdso, size_t len)
+#if defined(CONFIG_X86_32) || defined(CONFIG_X86_X32_ABI) || \
+        defined(CONFIG_COMPAT)
+void __init patch_vdso32(void *vdso, size_t len)
 {
        Elf32_Ehdr *hdr = vdso;
        Elf32_Shdr *sechdrs, *alt_sec = 0;
@@ -52,7 +54,7 @@ static void __init patch_vdsox32(void *vdso, size_t len)
        }
        /* If we get here, it's probably a bug. */
-        pr_warning("patch_vdsox32: .altinstructions not found\n");
+        pr_warning("patch_vdso32: .altinstructions not found\n");
        return;  /* nothing to patch */
 found:
@@ -61,6 +63,7 @@ found:
 }
 #endif
+#if defined(CONFIG_X86_64)
 static void __init patch_vdso64(void *vdso, size_t len)
 {
        Elf64_Ehdr *hdr = vdso;
@@ -104,7 +107,7 @@ static int __init init_vdso(void)
                vdso_pages[i] = virt_to_page(vdso_start + i*PAGE_SIZE);
 #ifdef CONFIG_X86_X32_ABI
-        patch_vdsox32(vdsox32_start, vdsox32_end - vdsox32_start);
+        patch_vdso32(vdsox32_start, vdsox32_end - vdsox32_start);
        npages = (vdsox32_end - vdsox32_start + PAGE_SIZE - 1) / PAGE_SIZE;
        vdsox32_size = npages << PAGE_SHIFT;
        for (i = 0; i < npages; i++)
@@ -204,3 +207,4 @@ static __init int vdso_setup(char *s)
        return 0;
 }
 __setup("vdso=", vdso_setup);
+#endif
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 01b90261fa38..e88fda867a33 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -7,7 +7,7 @@ config XEN
        depends on PARAVIRT
        select PARAVIRT_CLOCK
        select XEN_HAVE_PVMMU
-        depends on X86_64 || (X86_32 && X86_PAE && !X86_VISWS)
+        depends on X86_64 || (X86_32 && X86_PAE)
        depends on X86_TSC
        help
          This is the Linux Xen port.  Enabling this will allow the
@@ -19,11 +19,6 @@ config XEN_DOM0
        depends on XEN && PCI_XEN && SWIOTLB_XEN
        depends on X86_LOCAL_APIC && X86_IO_APIC && ACPI && PCI
-# Dummy symbol since people have come to rely on the PRIVILEGED_GUEST
-# name in tools.
-config XEN_PRIVILEGED_GUEST
-        def_bool XEN_DOM0
 config XEN_PVHVM
        def_bool y
        depends on XEN && PCI && X86_LOCAL_APIC
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 2423ef04ffea..86e02eabb640 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -2058,7 +2058,6 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
        case FIX_RO_IDT:
 #ifdef CONFIG_X86_32
        case FIX_WP_TEST:
-        case FIX_VDSO:
 # ifdef CONFIG_HIGHMEM
        case FIX_KMAP_BEGIN ... FIX_KMAP_END:
 # endif
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c
index 696c694986d0..85e5d78c9874 100644
--- a/arch/x86/xen/p2m.c
+++ b/arch/x86/xen/p2m.c
@@ -881,6 +881,65 @@ static unsigned long mfn_hash(unsigned long mfn)
        return hash_long(mfn, M2P_OVERRIDE_HASH_SHIFT);
 }
+int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops,
+                            struct gnttab_map_grant_ref *kmap_ops,
+                            struct page **pages, unsigned int count)
+{
+        int i, ret = 0;
+        bool lazy = false;
+        pte_t *pte;
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return 0;
+        if (kmap_ops &&
+            !in_interrupt() &&
+            paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE) {
+                arch_enter_lazy_mmu_mode();
+                lazy = true;
+        }
+        for (i = 0; i < count; i++) {
+                unsigned long mfn, pfn;
+                /* Do not add to override if the map failed. */
+                if (map_ops[i].status)
+                        continue;
+                if (map_ops[i].flags & GNTMAP_contains_pte) {
+                        pte = (pte_t *) (mfn_to_virt(PFN_DOWN(map_ops[i].host_addr)) +
+                                (map_ops[i].host_addr & ~PAGE_MASK));
+                        mfn = pte_mfn(*pte);
+                } else {
+                        mfn = PFN_DOWN(map_ops[i].dev_bus_addr);
+                }
+                pfn = page_to_pfn(pages[i]);
+                WARN_ON(PagePrivate(pages[i]));
+                SetPagePrivate(pages[i]);
+                set_page_private(pages[i], mfn);
+                pages[i]->index = pfn_to_mfn(pfn);
+                if (unlikely(!set_phys_to_machine(pfn, FOREIGN_FRAME(mfn)))) {
+                        ret = -ENOMEM;
+                        goto out;
+                }
+                if (kmap_ops) {
+                        ret = m2p_add_override(mfn, pages[i], &kmap_ops[i]);
+                        if (ret)
+                                goto out;
+                }
+        }
+out:
+        if (lazy)
+                arch_leave_lazy_mmu_mode();
+        return ret;
+}
+EXPORT_SYMBOL_GPL(set_foreign_p2m_mapping);
 /* Add an MFN override for a particular page */
 int m2p_add_override(unsigned long mfn, struct page *page,
                struct gnttab_map_grant_ref *kmap_op)
@@ -899,13 +958,6 @@ int m2p_add_override(unsigned long mfn, struct page *page,
                                        "m2p_add_override: pfn %lx not mapped", pfn))
                        return -EINVAL;
        }
-        WARN_ON(PagePrivate(page));
-        SetPagePrivate(page);
-        set_page_private(page, mfn);
-        page->index = pfn_to_mfn(pfn);
-        if (unlikely(!set_phys_to_machine(pfn, FOREIGN_FRAME(mfn))))
-                return -ENOMEM;
        if (kmap_op != NULL) {
                if (!PageHighMem(page)) {
@@ -943,20 +995,62 @@ int m2p_add_override(unsigned long mfn, struct page *page,
        return 0;
 }
 EXPORT_SYMBOL_GPL(m2p_add_override);
+int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops,
+                              struct gnttab_map_grant_ref *kmap_ops,
+                              struct page **pages, unsigned int count)
+{
+        int i, ret = 0;
+        bool lazy = false;
+        if (xen_feature(XENFEAT_auto_translated_physmap))
+                return 0;
+        if (kmap_ops &&
+            !in_interrupt() &&
+            paravirt_get_lazy_mode() == PARAVIRT_LAZY_NONE) {
+                arch_enter_lazy_mmu_mode();
+                lazy = true;
+        }
+        for (i = 0; i < count; i++) {
+                unsigned long mfn = get_phys_to_machine(page_to_pfn(pages[i]));
+                unsigned long pfn = page_to_pfn(pages[i]);
+                if (mfn == INVALID_P2M_ENTRY || !(mfn & FOREIGN_FRAME_BIT)) {
+                        ret = -EINVAL;
+                        goto out;
+                }
+                set_page_private(pages[i], INVALID_P2M_ENTRY);
+                WARN_ON(!PagePrivate(pages[i]));
+                ClearPagePrivate(pages[i]);
+                set_phys_to_machine(pfn, pages[i]->index);
+                if (kmap_ops)
+                        ret = m2p_remove_override(pages[i], &kmap_ops[i], mfn);
+                if (ret)
+                        goto out;
+        }
+out:
+        if (lazy)
+                arch_leave_lazy_mmu_mode();
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clear_foreign_p2m_mapping);
 int m2p_remove_override(struct page *page,
-                struct gnttab_map_grant_ref *kmap_op)
+                        struct gnttab_map_grant_ref *kmap_op,
+                        unsigned long mfn)
 {
        unsigned long flags;
-        unsigned long mfn;
        unsigned long pfn;
        unsigned long uninitialized_var(address);
        unsigned level;
        pte_t *ptep = NULL;
        pfn = page_to_pfn(page);
-        mfn = get_phys_to_machine(pfn);
-        if (mfn == INVALID_P2M_ENTRY || !(mfn & FOREIGN_FRAME_BIT))
-                return -EINVAL;
        if (!PageHighMem(page)) {
                address = (unsigned long)__va(pfn << PAGE_SHIFT);
@@ -970,10 +1064,7 @@ int m2p_remove_override(struct page *page,
        spin_lock_irqsave(&m2p_override_lock, flags);
        list_del(&page->lru);
        spin_unlock_irqrestore(&m2p_override_lock, flags);
-        WARN_ON(!PagePrivate(page));
-        ClearPagePrivate(page);
-        set_phys_to_machine(pfn, page->index);
        if (kmap_op != NULL) {
                if (!PageHighMem(page)) {
                        struct multicall_space mcs;
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index c87ae7c6e5f9..02d6d29a63c1 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -41,7 +41,7 @@ config ARCH_HAS_ILOG2_U32
 config ARCH_HAS_ILOG2_U64
        def_bool n
-config NO_IOPORT
+config NO_IOPORT_MAP
        def_bool n
 config HZ
@@ -239,7 +239,7 @@ config XTENSA_PLATFORM_XT2000
 config XTENSA_PLATFORM_S6105
        bool "S6105"
        select SERIAL_CONSOLE
-        select NO_IOPORT
+        select NO_IOPORT_MAP
 config XTENSA_PLATFORM_XTFPGA
        bool "XTFPGA"
diff --git a/arch/xtensa/configs/iss_defconfig b/arch/xtensa/configs/iss_defconfig
index 4f233204faf9..1493c68352d1 100644
--- a/arch/xtensa/configs/iss_defconfig
+++ b/arch/xtensa/configs/iss_defconfig
@@ -11,7 +11,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_NO_IOPORT=y
+CONFIG_NO_IOPORT_MAP=y
 CONFIG_HZ=100
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 CONFIG_CONSTRUCTORS=y
@@ -627,7 +627,6 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
diff --git a/arch/xtensa/configs/s6105_defconfig b/arch/xtensa/configs/s6105_defconfig
index d929f77a0360..12a492ab6d17 100644
--- a/arch/xtensa/configs/s6105_defconfig
+++ b/arch/xtensa/configs/s6105_defconfig
@@ -11,7 +11,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_NO_IOPORT=y
+CONFIG_NO_IOPORT_MAP=y
 CONFIG_HZ=100
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -569,7 +569,6 @@ CONFIG_DEBUG_SPINLOCK_SLEEP=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
 CONFIG_DEBUG_NOMMU_REGIONS=y
-# CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
author	Ingo Molnar <mingo@kernel.org>	2014-04-14 10:44:42 -0400
committer	Ingo Molnar <mingo@kernel.org>	2014-04-14 10:44:42 -0400
commit	740c699a8d316c8bf8593f19e2ca47795e690622 (patch)
tree	a78886955770a477945c5d84e06b2e7678733b54 /arch
parent	e69af4657e7764d03ad555f0b583d9c4217bcefa (diff)
parent	c9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff)