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Diffstat (limited to 'arch/arm/boot/dts/sun7i-a20.dtsi')
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi302
1 files changed, 265 insertions, 37 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index cadcf2f9881d..32efc105df83 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -17,7 +17,15 @@
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 aliases { 19 aliases {
20 ethernet0 = &emac; 20 ethernet0 = &gmac;
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
27 serial6 = &uart6;
28 serial7 = &uart7;
21 }; 29 };
22 30
23 cpus { 31 cpus {
@@ -41,16 +49,25 @@
41 reg = <0x40000000 0x80000000>; 49 reg = <0x40000000 0x80000000>;
42 }; 50 };
43 51
52 timer {
53 compatible = "arm,armv7-timer";
54 interrupts = <1 13 0xf08>,
55 <1 14 0xf08>,
56 <1 11 0xf08>,
57 <1 10 0xf08>;
58 };
59
44 clocks { 60 clocks {
45 #address-cells = <1>; 61 #address-cells = <1>;
46 #size-cells = <1>; 62 #size-cells = <1>;
47 ranges; 63 ranges;
48 64
49 osc24M: osc24M@01c20050 { 65 osc24M: clk@01c20050 {
50 #clock-cells = <0>; 66 #clock-cells = <0>;
51 compatible = "allwinner,sun4i-osc-clk"; 67 compatible = "allwinner,sun4i-a10-osc-clk";
52 reg = <0x01c20050 0x4>; 68 reg = <0x01c20050 0x4>;
53 clock-frequency = <24000000>; 69 clock-frequency = <24000000>;
70 clock-output-names = "osc24M";
54 }; 71 };
55 72
56 osc32k: clk@0 { 73 osc32k: clk@0 {
@@ -60,31 +77,33 @@
60 clock-output-names = "osc32k"; 77 clock-output-names = "osc32k";
61 }; 78 };
62 79
63 pll1: pll1@01c20000 { 80 pll1: clk@01c20000 {
64 #clock-cells = <0>; 81 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk"; 82 compatible = "allwinner,sun4i-a10-pll1-clk";
66 reg = <0x01c20000 0x4>; 83 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 84 clocks = <&osc24M>;
85 clock-output-names = "pll1";
68 }; 86 };
69 87
70 pll4: pll4@01c20018 { 88 pll4: clk@01c20018 {
71 #clock-cells = <0>; 89 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 90 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20018 0x4>; 91 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>; 92 clocks = <&osc24M>;
93 clock-output-names = "pll4";
75 }; 94 };
76 95
77 pll5: pll5@01c20020 { 96 pll5: clk@01c20020 {
78 #clock-cells = <1>; 97 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk"; 98 compatible = "allwinner,sun4i-a10-pll5-clk";
80 reg = <0x01c20020 0x4>; 99 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>; 100 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other"; 101 clock-output-names = "pll5_ddr", "pll5_other";
83 }; 102 };
84 103
85 pll6: pll6@01c20028 { 104 pll6: clk@01c20028 {
86 #clock-cells = <1>; 105 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk"; 106 compatible = "allwinner,sun4i-a10-pll6-clk";
88 reg = <0x01c20028 0x4>; 107 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>; 108 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 109 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -92,26 +111,29 @@
92 111
93 cpu: cpu@01c20054 { 112 cpu: cpu@01c20054 {
94 #clock-cells = <0>; 113 #clock-cells = <0>;
95 compatible = "allwinner,sun4i-cpu-clk"; 114 compatible = "allwinner,sun4i-a10-cpu-clk";
96 reg = <0x01c20054 0x4>; 115 reg = <0x01c20054 0x4>;
97 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; 116 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
117 clock-output-names = "cpu";
98 }; 118 };
99 119
100 axi: axi@01c20054 { 120 axi: axi@01c20054 {
101 #clock-cells = <0>; 121 #clock-cells = <0>;
102 compatible = "allwinner,sun4i-axi-clk"; 122 compatible = "allwinner,sun4i-a10-axi-clk";
103 reg = <0x01c20054 0x4>; 123 reg = <0x01c20054 0x4>;
104 clocks = <&cpu>; 124 clocks = <&cpu>;
125 clock-output-names = "axi";
105 }; 126 };
106 127
107 ahb: ahb@01c20054 { 128 ahb: ahb@01c20054 {
108 #clock-cells = <0>; 129 #clock-cells = <0>;
109 compatible = "allwinner,sun4i-ahb-clk"; 130 compatible = "allwinner,sun4i-a10-ahb-clk";
110 reg = <0x01c20054 0x4>; 131 reg = <0x01c20054 0x4>;
111 clocks = <&axi>; 132 clocks = <&axi>;
133 clock-output-names = "ahb";
112 }; 134 };
113 135
114 ahb_gates: ahb_gates@01c20060 { 136 ahb_gates: clk@01c20060 {
115 #clock-cells = <1>; 137 #clock-cells = <1>;
116 compatible = "allwinner,sun7i-a20-ahb-gates-clk"; 138 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
117 reg = <0x01c20060 0x8>; 139 reg = <0x01c20060 0x8>;
@@ -133,12 +155,13 @@
133 155
134 apb0: apb0@01c20054 { 156 apb0: apb0@01c20054 {
135 #clock-cells = <0>; 157 #clock-cells = <0>;
136 compatible = "allwinner,sun4i-apb0-clk"; 158 compatible = "allwinner,sun4i-a10-apb0-clk";
137 reg = <0x01c20054 0x4>; 159 reg = <0x01c20054 0x4>;
138 clocks = <&ahb>; 160 clocks = <&ahb>;
161 clock-output-names = "apb0";
139 }; 162 };
140 163
141 apb0_gates: apb0_gates@01c20068 { 164 apb0_gates: clk@01c20068 {
142 #clock-cells = <1>; 165 #clock-cells = <1>;
143 compatible = "allwinner,sun7i-a20-apb0-gates-clk"; 166 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
144 reg = <0x01c20068 0x4>; 167 reg = <0x01c20068 0x4>;
@@ -151,19 +174,21 @@
151 174
152 apb1_mux: apb1_mux@01c20058 { 175 apb1_mux: apb1_mux@01c20058 {
153 #clock-cells = <0>; 176 #clock-cells = <0>;
154 compatible = "allwinner,sun4i-apb1-mux-clk"; 177 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
155 reg = <0x01c20058 0x4>; 178 reg = <0x01c20058 0x4>;
156 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 179 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
180 clock-output-names = "apb1_mux";
157 }; 181 };
158 182
159 apb1: apb1@01c20058 { 183 apb1: apb1@01c20058 {
160 #clock-cells = <0>; 184 #clock-cells = <0>;
161 compatible = "allwinner,sun4i-apb1-clk"; 185 compatible = "allwinner,sun4i-a10-apb1-clk";
162 reg = <0x01c20058 0x4>; 186 reg = <0x01c20058 0x4>;
163 clocks = <&apb1_mux>; 187 clocks = <&apb1_mux>;
188 clock-output-names = "apb1";
164 }; 189 };
165 190
166 apb1_gates: apb1_gates@01c2006c { 191 apb1_gates: clk@01c2006c {
167 #clock-cells = <1>; 192 #clock-cells = <1>;
168 compatible = "allwinner,sun7i-a20-apb1-gates-clk"; 193 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
169 reg = <0x01c2006c 0x4>; 194 reg = <0x01c2006c 0x4>;
@@ -178,7 +203,7 @@
178 203
179 nand_clk: clk@01c20080 { 204 nand_clk: clk@01c20080 {
180 #clock-cells = <0>; 205 #clock-cells = <0>;
181 compatible = "allwinner,sun4i-mod0-clk"; 206 compatible = "allwinner,sun4i-a10-mod0-clk";
182 reg = <0x01c20080 0x4>; 207 reg = <0x01c20080 0x4>;
183 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
184 clock-output-names = "nand"; 209 clock-output-names = "nand";
@@ -186,7 +211,7 @@
186 211
187 ms_clk: clk@01c20084 { 212 ms_clk: clk@01c20084 {
188 #clock-cells = <0>; 213 #clock-cells = <0>;
189 compatible = "allwinner,sun4i-mod0-clk"; 214 compatible = "allwinner,sun4i-a10-mod0-clk";
190 reg = <0x01c20084 0x4>; 215 reg = <0x01c20084 0x4>;
191 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
192 clock-output-names = "ms"; 217 clock-output-names = "ms";
@@ -194,7 +219,7 @@
194 219
195 mmc0_clk: clk@01c20088 { 220 mmc0_clk: clk@01c20088 {
196 #clock-cells = <0>; 221 #clock-cells = <0>;
197 compatible = "allwinner,sun4i-mod0-clk"; 222 compatible = "allwinner,sun4i-a10-mod0-clk";
198 reg = <0x01c20088 0x4>; 223 reg = <0x01c20088 0x4>;
199 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
200 clock-output-names = "mmc0"; 225 clock-output-names = "mmc0";
@@ -202,7 +227,7 @@
202 227
203 mmc1_clk: clk@01c2008c { 228 mmc1_clk: clk@01c2008c {
204 #clock-cells = <0>; 229 #clock-cells = <0>;
205 compatible = "allwinner,sun4i-mod0-clk"; 230 compatible = "allwinner,sun4i-a10-mod0-clk";
206 reg = <0x01c2008c 0x4>; 231 reg = <0x01c2008c 0x4>;
207 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
208 clock-output-names = "mmc1"; 233 clock-output-names = "mmc1";
@@ -210,7 +235,7 @@
210 235
211 mmc2_clk: clk@01c20090 { 236 mmc2_clk: clk@01c20090 {
212 #clock-cells = <0>; 237 #clock-cells = <0>;
213 compatible = "allwinner,sun4i-mod0-clk"; 238 compatible = "allwinner,sun4i-a10-mod0-clk";
214 reg = <0x01c20090 0x4>; 239 reg = <0x01c20090 0x4>;
215 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
216 clock-output-names = "mmc2"; 241 clock-output-names = "mmc2";
@@ -218,7 +243,7 @@
218 243
219 mmc3_clk: clk@01c20094 { 244 mmc3_clk: clk@01c20094 {
220 #clock-cells = <0>; 245 #clock-cells = <0>;
221 compatible = "allwinner,sun4i-mod0-clk"; 246 compatible = "allwinner,sun4i-a10-mod0-clk";
222 reg = <0x01c20094 0x4>; 247 reg = <0x01c20094 0x4>;
223 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
224 clock-output-names = "mmc3"; 249 clock-output-names = "mmc3";
@@ -226,7 +251,7 @@
226 251
227 ts_clk: clk@01c20098 { 252 ts_clk: clk@01c20098 {
228 #clock-cells = <0>; 253 #clock-cells = <0>;
229 compatible = "allwinner,sun4i-mod0-clk"; 254 compatible = "allwinner,sun4i-a10-mod0-clk";
230 reg = <0x01c20098 0x4>; 255 reg = <0x01c20098 0x4>;
231 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
232 clock-output-names = "ts"; 257 clock-output-names = "ts";
@@ -234,7 +259,7 @@
234 259
235 ss_clk: clk@01c2009c { 260 ss_clk: clk@01c2009c {
236 #clock-cells = <0>; 261 #clock-cells = <0>;
237 compatible = "allwinner,sun4i-mod0-clk"; 262 compatible = "allwinner,sun4i-a10-mod0-clk";
238 reg = <0x01c2009c 0x4>; 263 reg = <0x01c2009c 0x4>;
239 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
240 clock-output-names = "ss"; 265 clock-output-names = "ss";
@@ -242,7 +267,7 @@
242 267
243 spi0_clk: clk@01c200a0 { 268 spi0_clk: clk@01c200a0 {
244 #clock-cells = <0>; 269 #clock-cells = <0>;
245 compatible = "allwinner,sun4i-mod0-clk"; 270 compatible = "allwinner,sun4i-a10-mod0-clk";
246 reg = <0x01c200a0 0x4>; 271 reg = <0x01c200a0 0x4>;
247 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
248 clock-output-names = "spi0"; 273 clock-output-names = "spi0";
@@ -250,7 +275,7 @@
250 275
251 spi1_clk: clk@01c200a4 { 276 spi1_clk: clk@01c200a4 {
252 #clock-cells = <0>; 277 #clock-cells = <0>;
253 compatible = "allwinner,sun4i-mod0-clk"; 278 compatible = "allwinner,sun4i-a10-mod0-clk";
254 reg = <0x01c200a4 0x4>; 279 reg = <0x01c200a4 0x4>;
255 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
256 clock-output-names = "spi1"; 281 clock-output-names = "spi1";
@@ -258,7 +283,7 @@
258 283
259 spi2_clk: clk@01c200a8 { 284 spi2_clk: clk@01c200a8 {
260 #clock-cells = <0>; 285 #clock-cells = <0>;
261 compatible = "allwinner,sun4i-mod0-clk"; 286 compatible = "allwinner,sun4i-a10-mod0-clk";
262 reg = <0x01c200a8 0x4>; 287 reg = <0x01c200a8 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264 clock-output-names = "spi2"; 289 clock-output-names = "spi2";
@@ -266,7 +291,7 @@
266 291
267 pata_clk: clk@01c200ac { 292 pata_clk: clk@01c200ac {
268 #clock-cells = <0>; 293 #clock-cells = <0>;
269 compatible = "allwinner,sun4i-mod0-clk"; 294 compatible = "allwinner,sun4i-a10-mod0-clk";
270 reg = <0x01c200ac 0x4>; 295 reg = <0x01c200ac 0x4>;
271 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
272 clock-output-names = "pata"; 297 clock-output-names = "pata";
@@ -274,7 +299,7 @@
274 299
275 ir0_clk: clk@01c200b0 { 300 ir0_clk: clk@01c200b0 {
276 #clock-cells = <0>; 301 #clock-cells = <0>;
277 compatible = "allwinner,sun4i-mod0-clk"; 302 compatible = "allwinner,sun4i-a10-mod0-clk";
278 reg = <0x01c200b0 0x4>; 303 reg = <0x01c200b0 0x4>;
279 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
280 clock-output-names = "ir0"; 305 clock-output-names = "ir0";
@@ -282,15 +307,24 @@
282 307
283 ir1_clk: clk@01c200b4 { 308 ir1_clk: clk@01c200b4 {
284 #clock-cells = <0>; 309 #clock-cells = <0>;
285 compatible = "allwinner,sun4i-mod0-clk"; 310 compatible = "allwinner,sun4i-a10-mod0-clk";
286 reg = <0x01c200b4 0x4>; 311 reg = <0x01c200b4 0x4>;
287 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
288 clock-output-names = "ir1"; 313 clock-output-names = "ir1";
289 }; 314 };
290 315
316 usb_clk: clk@01c200cc {
317 #clock-cells = <1>;
318 #reset-cells = <1>;
319 compatible = "allwinner,sun4i-a10-usb-clk";
320 reg = <0x01c200cc 0x4>;
321 clocks = <&pll6 1>;
322 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
323 };
324
291 spi3_clk: clk@01c200d4 { 325 spi3_clk: clk@01c200d4 {
292 #clock-cells = <0>; 326 #clock-cells = <0>;
293 compatible = "allwinner,sun4i-mod0-clk"; 327 compatible = "allwinner,sun4i-a10-mod0-clk";
294 reg = <0x01c200d4 0x4>; 328 reg = <0x01c200d4 0x4>;
295 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
296 clock-output-names = "spi3"; 330 clock-output-names = "spi3";
@@ -298,13 +332,41 @@
298 332
299 mbus_clk: clk@01c2015c { 333 mbus_clk: clk@01c2015c {
300 #clock-cells = <0>; 334 #clock-cells = <0>;
301 compatible = "allwinner,sun4i-mod0-clk"; 335 compatible = "allwinner,sun4i-a10-mod0-clk";
302 reg = <0x01c2015c 0x4>; 336 reg = <0x01c2015c 0x4>;
303 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; 337 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
304 clock-output-names = "mbus"; 338 clock-output-names = "mbus";
305 }; 339 };
306 340
307 /* 341 /*
342 * The following two are dummy clocks, placeholders used in the gmac_tx
343 * clock. The gmac driver will choose one parent depending on the PHY
344 * interface mode, using clk_set_rate auto-reparenting.
345 * The actual TX clock rate is not controlled by the gmac_tx clock.
346 */
347 mii_phy_tx_clk: clk@2 {
348 #clock-cells = <0>;
349 compatible = "fixed-clock";
350 clock-frequency = <25000000>;
351 clock-output-names = "mii_phy_tx";
352 };
353
354 gmac_int_tx_clk: clk@3 {
355 #clock-cells = <0>;
356 compatible = "fixed-clock";
357 clock-frequency = <125000000>;
358 clock-output-names = "gmac_int_tx";
359 };
360
361 gmac_tx_clk: clk@01c20164 {
362 #clock-cells = <0>;
363 compatible = "allwinner,sun7i-a20-gmac-clk";
364 reg = <0x01c20164 0x4>;
365 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
366 clock-output-names = "gmac_tx";
367 };
368
369 /*
308 * Dummy clock used by output clocks 370 * Dummy clock used by output clocks
309 */ 371 */
310 osc24M_32k: clk@1 { 372 osc24M_32k: clk@1 {
@@ -347,6 +409,28 @@
347 interrupts = <0 0 4>; 409 interrupts = <0 0 4>;
348 }; 410 };
349 411
412 spi0: spi@01c05000 {
413 compatible = "allwinner,sun4i-a10-spi";
414 reg = <0x01c05000 0x1000>;
415 interrupts = <0 10 4>;
416 clocks = <&ahb_gates 20>, <&spi0_clk>;
417 clock-names = "ahb", "mod";
418 status = "disabled";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 };
422
423 spi1: spi@01c06000 {
424 compatible = "allwinner,sun4i-a10-spi";
425 reg = <0x01c06000 0x1000>;
426 interrupts = <0 11 4>;
427 clocks = <&ahb_gates 21>, <&spi1_clk>;
428 clock-names = "ahb", "mod";
429 status = "disabled";
430 #address-cells = <1>;
431 #size-cells = <0>;
432 };
433
350 emac: ethernet@01c0b000 { 434 emac: ethernet@01c0b000 {
351 compatible = "allwinner,sun4i-a10-emac"; 435 compatible = "allwinner,sun4i-a10-emac";
352 reg = <0x01c0b000 0x1000>; 436 reg = <0x01c0b000 0x1000>;
@@ -363,6 +447,88 @@
363 #size-cells = <0>; 447 #size-cells = <0>;
364 }; 448 };
365 449
450 usbphy: phy@01c13400 {
451 #phy-cells = <1>;
452 compatible = "allwinner,sun7i-a20-usb-phy";
453 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
454 reg-names = "phy_ctrl", "pmu1", "pmu2";
455 clocks = <&usb_clk 8>;
456 clock-names = "usb_phy";
457 resets = <&usb_clk 1>, <&usb_clk 2>;
458 reset-names = "usb1_reset", "usb2_reset";
459 status = "disabled";
460 };
461
462 ehci0: usb@01c14000 {
463 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
464 reg = <0x01c14000 0x100>;
465 interrupts = <0 39 4>;
466 clocks = <&ahb_gates 1>;
467 phys = <&usbphy 1>;
468 phy-names = "usb";
469 status = "disabled";
470 };
471
472 ohci0: usb@01c14400 {
473 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
474 reg = <0x01c14400 0x100>;
475 interrupts = <0 64 4>;
476 clocks = <&usb_clk 6>, <&ahb_gates 2>;
477 phys = <&usbphy 1>;
478 phy-names = "usb";
479 status = "disabled";
480 };
481
482 spi2: spi@01c17000 {
483 compatible = "allwinner,sun4i-a10-spi";
484 reg = <0x01c17000 0x1000>;
485 interrupts = <0 12 4>;
486 clocks = <&ahb_gates 22>, <&spi2_clk>;
487 clock-names = "ahb", "mod";
488 status = "disabled";
489 #address-cells = <1>;
490 #size-cells = <0>;
491 };
492
493 ahci: sata@01c18000 {
494 compatible = "allwinner,sun4i-a10-ahci";
495 reg = <0x01c18000 0x1000>;
496 interrupts = <0 56 4>;
497 clocks = <&pll6 0>, <&ahb_gates 25>;
498 status = "disabled";
499 };
500
501 ehci1: usb@01c1c000 {
502 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
503 reg = <0x01c1c000 0x100>;
504 interrupts = <0 40 4>;
505 clocks = <&ahb_gates 3>;
506 phys = <&usbphy 2>;
507 phy-names = "usb";
508 status = "disabled";
509 };
510
511 ohci1: usb@01c1c400 {
512 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
513 reg = <0x01c1c400 0x100>;
514 interrupts = <0 65 4>;
515 clocks = <&usb_clk 7>, <&ahb_gates 4>;
516 phys = <&usbphy 2>;
517 phy-names = "usb";
518 status = "disabled";
519 };
520
521 spi3: spi@01c1f000 {
522 compatible = "allwinner,sun4i-a10-spi";
523 reg = <0x01c1f000 0x1000>;
524 interrupts = <0 50 4>;
525 clocks = <&ahb_gates 23>, <&spi3_clk>;
526 clock-names = "ahb", "mod";
527 status = "disabled";
528 #address-cells = <1>;
529 #size-cells = <0>;
530 };
531
366 pio: pinctrl@01c20800 { 532 pio: pinctrl@01c20800 {
367 compatible = "allwinner,sun7i-a20-pinctrl"; 533 compatible = "allwinner,sun7i-a20-pinctrl";
368 reg = <0x01c20800 0x400>; 534 reg = <0x01c20800 0x400>;
@@ -381,6 +547,13 @@
381 allwinner,pull = <0>; 547 allwinner,pull = <0>;
382 }; 548 };
383 549
550 uart2_pins_a: uart2@0 {
551 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
552 allwinner,function = "uart2";
553 allwinner,drive = <0>;
554 allwinner,pull = <0>;
555 };
556
384 uart6_pins_a: uart6@0 { 557 uart6_pins_a: uart6@0 {
385 allwinner,pins = "PI12", "PI13"; 558 allwinner,pins = "PI12", "PI13";
386 allwinner,function = "uart6"; 559 allwinner,function = "uart6";
@@ -440,6 +613,46 @@
440 allwinner,drive = <0>; 613 allwinner,drive = <0>;
441 allwinner,pull = <0>; 614 allwinner,pull = <0>;
442 }; 615 };
616
617 gmac_pins_mii_a: gmac_mii@0 {
618 allwinner,pins = "PA0", "PA1", "PA2",
619 "PA3", "PA4", "PA5", "PA6",
620 "PA7", "PA8", "PA9", "PA10",
621 "PA11", "PA12", "PA13", "PA14",
622 "PA15", "PA16";
623 allwinner,function = "gmac";
624 allwinner,drive = <0>;
625 allwinner,pull = <0>;
626 };
627
628 gmac_pins_rgmii_a: gmac_rgmii@0 {
629 allwinner,pins = "PA0", "PA1", "PA2",
630 "PA3", "PA4", "PA5", "PA6",
631 "PA7", "PA8", "PA10",
632 "PA11", "PA12", "PA13",
633 "PA15", "PA16";
634 allwinner,function = "gmac";
635 /*
636 * data lines in RGMII mode use DDR mode
637 * and need a higher signal drive strength
638 */
639 allwinner,drive = <3>;
640 allwinner,pull = <0>;
641 };
642
643 spi1_pins_a: spi1@0 {
644 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
645 allwinner,function = "spi1";
646 allwinner,drive = <0>;
647 allwinner,pull = <0>;
648 };
649
650 spi2_pins_a: spi2@0 {
651 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
652 allwinner,function = "spi2";
653 allwinner,drive = <0>;
654 allwinner,pull = <0>;
655 };
443 }; 656 };
444 657
445 timer@01c20c00 { 658 timer@01c20c00 {
@@ -455,7 +668,7 @@
455 }; 668 };
456 669
457 wdt: watchdog@01c20c90 { 670 wdt: watchdog@01c20c90 {
458 compatible = "allwinner,sun4i-wdt"; 671 compatible = "allwinner,sun4i-a10-wdt";
459 reg = <0x01c20c90 0x10>; 672 reg = <0x01c20c90 0x10>;
460 }; 673 };
461 674
@@ -601,6 +814,21 @@
601 status = "disabled"; 814 status = "disabled";
602 }; 815 };
603 816
817 gmac: ethernet@01c50000 {
818 compatible = "allwinner,sun7i-a20-gmac";
819 reg = <0x01c50000 0x10000>;
820 interrupts = <0 85 4>;
821 interrupt-names = "macirq";
822 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
823 clock-names = "stmmaceth", "allwinner_gmac_tx";
824 snps,pbl = <2>;
825 snps,fixed-burst;
826 snps,force_sf_dma_mode;
827 status = "disabled";
828 #address-cells = <1>;
829 #size-cells = <0>;
830 };
831
604 hstimer@01c60000 { 832 hstimer@01c60000 {
605 compatible = "allwinner,sun7i-a20-hstimer"; 833 compatible = "allwinner,sun7i-a20-hstimer";
606 reg = <0x01c60000 0x1000>; 834 reg = <0x01c60000 0x1000>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 08:23:11 -0400