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-rw-r--r--arch/arm/boot/dts/Makefile144
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts60
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts56
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi17
-rw-r--r--arch/arm/boot/dts/am3517-craneboard.dts174
-rw-r--r--arch/arm/boot/dts/am4372.dtsi46
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts127
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts183
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts56
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts7
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts6
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi8
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi33
-rw-r--r--arch/arm/boot/dts/armada-375-db.dts130
-rw-r--r--arch/arm/boot/dts/armada-375.dtsi464
-rw-r--r--arch/arm/boot/dts/armada-380.dtsi117
-rw-r--r--arch/arm/boot/dts/armada-385-db.dts122
-rw-r--r--arch/arm/boot/dts/armada-385-rd.dts94
-rw-r--r--arch/arm/boot/dts/armada-385.dtsi149
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi376
-rw-r--r--arch/arm/boot/dts/armada-xp-axpwifiap.dts6
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts13
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts22
-rw-r--r--arch/arm/boot/dts/armada-xp-matrix.dts7
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts12
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi6
-rw-r--r--arch/arm/boot/dts/at91-ariag25.dts1
-rw-r--r--arch/arm/boot/dts/at91-cosino.dtsi1
-rw-r--r--arch/arm/boot/dts/at91-cosino_mega2560.dts1
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi11
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi735
-rw-r--r--arch/arm/boot/dts/at91sam9261ek.dts211
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi12
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi802
-rw-r--r--arch/arm/boot/dts/at91sam9rlek.dts157
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi14
-rw-r--r--arch/arm/boot/dts/atlas6.dtsi22
-rw-r--r--arch/arm/boot/dts/bcm11351.dtsi192
-rw-r--r--arch/arm/boot/dts/bcm21664-garnet.dts (renamed from arch/arm/boot/dts/bcm11351-brt.dts)12
-rw-r--r--arch/arm/boot/dts/bcm21664.dtsi292
-rw-r--r--arch/arm/boot/dts/bcm28155-ap.dts51
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi92
-rw-r--r--arch/arm/boot/dts/bcm4708-netgear-r6250.dts35
-rw-r--r--arch/arm/boot/dts/bcm4708.dtsi34
-rw-r--r--arch/arm/boot/dts/bcm5301x.dtsi95
-rw-r--r--arch/arm/boot/dts/bcm59056.dtsi74
-rw-r--r--arch/arm/boot/dts/dove.dtsi22
-rw-r--r--arch/arm/boot/dts/dra7.dtsi168
-rw-r--r--arch/arm/boot/dts/efm32gg-dk3750.dts2
-rw-r--r--arch/arm/boot/dts/efm32gg.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi92
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts63
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts66
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi11
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi15
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx.dts4
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts6
-rw-r--r--arch/arm/boot/dts/exynos4412-smdk4412.dts2
-rw-r--r--arch/arm/boot/dts/exynos4412-tiny4412.dts2
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts93
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi16
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi60
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi7
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts28
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts169
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts6
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi148
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts315
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts255
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi172
-rw-r--r--arch/arm/boot/dts/exynos5440-sd5v1.dts2
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts2
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi35
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts8
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts5
-rw-r--r--arch/arm/boot/dts/imx23-stmp378x_devb.dts5
-rw-r--r--arch/arm/boot/dts/imx23.dtsi8
-rw-r--r--arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi73
-rw-r--r--arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts174
-rw-r--r--arch/arm/boot/dts/imx25-pinfunc.h494
-rw-r--r--arch/arm/boot/dts/imx25.dtsi18
-rw-r--r--arch/arm/boot/dts/imx27-apf27.dts38
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts149
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts77
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts44
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi103
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts178
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi (renamed from arch/arm/boot/dts/imx27-phytec-phycore-som.dts)133
-rw-r--r--arch/arm/boot/dts/imx27-pinfunc.h526
-rw-r--r--arch/arm/boot/dts/imx27.dtsi207
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts29
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts5
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts2
-rw-r--r--arch/arm/boot/dts/imx28-cfa10037.dts7
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts31
-rw-r--r--arch/arm/boot/dts/imx28-cfa10057.dts7
-rw-r--r--arch/arm/boot/dts/imx28-cfa10058.dts7
-rw-r--r--arch/arm/boot/dts/imx28-duckbill.dts121
-rw-r--r--arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts71
-rw-r--r--arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts50
-rw-r--r--arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi326
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts24
-rw-r--r--arch/arm/boot/dts/imx28-m28cu3.dts17
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts20
-rw-r--r--arch/arm/boot/dts/imx28-sps1.dts7
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts24
-rw-r--r--arch/arm/boot/dts/imx28.dtsi65
-rw-r--r--arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi81
-rw-r--r--arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts143
-rw-r--r--arch/arm/boot/dts/imx35.dtsi359
-rw-r--r--arch/arm/boot/dts/imx50-evk.dts119
-rw-r--r--arch/arm/boot/dts/imx50-pinfunc.h923
-rw-r--r--arch/arm/boot/dts/imx50.dtsi478
-rw-r--r--arch/arm/boot/dts/imx51-apf51.dts40
-rw-r--r--arch/arm/boot/dts/imx51-apf51dev.dts113
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts281
-rw-r--r--arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi93
-rw-r--r--arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts175
-rw-r--r--arch/arm/boot/dts/imx51.dtsi481
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts33
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts126
-rw-r--r--arch/arm/boot/dts/imx53-m53evk.dts245
-rw-r--r--arch/arm/boot/dts/imx53-mba53.dts52
-rw-r--r--arch/arm/boot/dts/imx53-qsb-common.dtsi345
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts210
-rw-r--r--arch/arm/boot/dts/imx53-qsrb.dts158
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts119
-rw-r--r--arch/arm/boot/dts/imx53-tqma53.dtsi175
-rw-r--r--arch/arm/boot/dts/imx53-tx53-x03x.dts315
-rw-r--r--arch/arm/boot/dts/imx53-tx53-x13x.dts243
-rw-r--r--arch/arm/boot/dts/imx53-tx53.dtsi510
-rw-r--r--arch/arm/boot/dts/imx53-voipac-bsb.dts159
-rw-r--r--arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi277
-rw-r--r--arch/arm/boot/dts/imx53.dtsi727
-rw-r--r--arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts23
-rw-r--r--arch/arm/boot/dts/imx6dl-gw51xx.dts19
-rw-r--r--arch/arm/boot/dts/imx6dl-gw52xx.dts19
-rw-r--r--arch/arm/boot/dts/imx6dl-gw53xx.dts19
-rw-r--r--arch/arm/boot/dts/imx6dl-gw54xx.dts19
-rw-r--r--arch/arm/boot/dts/imx6dl-nitrogen6x.dts21
-rw-r--r--arch/arm/boot/dts/imx6dl-pinfunc.h2
-rw-r--r--arch/arm/boot/dts/imx6dl-sabrelite.dts20
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi46
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts140
-rw-r--r--arch/arm/boot/dts/imx6q-cm-fx6.dts107
-rw-r--r--arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts23
-rw-r--r--arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts372
-rw-r--r--arch/arm/boot/dts/imx6q-gk802.dts171
-rw-r--r--arch/arm/boot/dts/imx6q-gw51xx.dts19
-rw-r--r--arch/arm/boot/dts/imx6q-gw52xx.dts23
-rw-r--r--arch/arm/boot/dts/imx6q-gw53xx.dts23
-rw-r--r--arch/arm/boot/dts/imx6q-gw5400-a.dts546
-rw-r--r--arch/arm/boot/dts/imx6q-gw54xx.dts23
-rw-r--r--arch/arm/boot/dts/imx6q-nitrogen6x.dts25
-rw-r--r--arch/arm/boot/dts/imx6q-phytec-pbab01.dts16
-rw-r--r--arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi167
-rw-r--r--arch/arm/boot/dts/imx6q-pinfunc.h2
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts178
-rw-r--r--arch/arm/boot/dts/imx6q-sbc6x.dts58
-rw-r--r--arch/arm/boot/dts/imx6q-udoo.dts54
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi146
-rw-r--r--arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi199
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw51xx.dtsi374
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi490
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi553
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw54xx.dtsi580
-rw-r--r--arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi422
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi378
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabrelite.dtsi423
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi277
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard.dtsi131
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi1053
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts427
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi385
-rw-r--r--arch/arm/boot/dts/integratorap.dts35
-rw-r--r--arch/arm/boot/dts/integratorcp.dts102
-rw-r--r--arch/arm/boot/dts/k2e-clocks.dtsi78
-rw-r--r--arch/arm/boot/dts/k2e-evm.dts60
-rw-r--r--arch/arm/boot/dts/k2e.dtsi80
-rw-r--r--arch/arm/boot/dts/k2hk-clocks.dtsi426
-rw-r--r--arch/arm/boot/dts/k2hk-evm.dts83
-rw-r--r--arch/arm/boot/dts/k2hk.dtsi46
-rw-r--r--arch/arm/boot/dts/k2l-clocks.dtsi267
-rw-r--r--arch/arm/boot/dts/k2l-evm.dts37
-rw-r--r--arch/arm/boot/dts/k2l.dtsi55
-rw-r--r--arch/arm/boot/dts/keystone-clocks.dtsi427
-rw-r--r--arch/arm/boot/dts/keystone.dtsi102
-rw-r--r--arch/arm/boot/dts/kirkwood-b3.dts204
-rw-r--r--arch/arm/boot/dts/kirkwood-ds109.dts41
-rw-r--r--arch/arm/boot/dts/kirkwood-ds110jv10.dts41
-rw-r--r--arch/arm/boot/dts/kirkwood-ds111.dts44
-rw-r--r--arch/arm/boot/dts/kirkwood-ds112.dts48
-rw-r--r--arch/arm/boot/dts/kirkwood-ds209.dts44
-rw-r--r--arch/arm/boot/dts/kirkwood-ds210.dts46
-rw-r--r--arch/arm/boot/dts/kirkwood-ds212.dts47
-rw-r--r--arch/arm/boot/dts/kirkwood-ds212j.dts41
-rw-r--r--arch/arm/boot/dts/kirkwood-ds409.dts48
-rw-r--r--arch/arm/boot/dts/kirkwood-ds409slim.dts40
-rw-r--r--arch/arm/boot/dts/kirkwood-ds411.dts52
-rw-r--r--arch/arm/boot/dts/kirkwood-ds411j.dts48
-rw-r--r--arch/arm/boot/dts/kirkwood-ds411slim.dts48
-rw-r--r--arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts62
-rw-r--r--arch/arm/boot/dts/kirkwood-rd88f6192.dts112
-rw-r--r--arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts26
-rw-r--r--arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts31
-rw-r--r--arch/arm/boot/dts/kirkwood-rd88f6281.dtsi152
-rw-r--r--arch/arm/boot/dts/kirkwood-rs212.dts48
-rw-r--r--arch/arm/boot/dts/kirkwood-rs409.dts44
-rw-r--r--arch/arm/boot/dts/kirkwood-rs411.dts44
-rw-r--r--arch/arm/boot/dts/kirkwood-synology.dtsi871
-rw-r--r--arch/arm/boot/dts/kirkwood-t5325.dts208
-rw-r--r--arch/arm/boot/dts/kirkwood-ts419-6281.dts20
-rw-r--r--arch/arm/boot/dts/kirkwood-ts419-6282.dts32
-rw-r--r--arch/arm/boot/dts/kirkwood-ts419.dtsi75
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi24
-rw-r--r--arch/arm/boot/dts/marco.dtsi3
-rw-r--r--arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi58
-rw-r--r--arch/arm/boot/dts/omap2.dtsi31
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi2
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi22
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts142
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts139
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3517.dts136
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3530.dts48
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3730.dts57
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x.dtsi110
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x30.dtsi74
-rw-r--r--arch/arm/boot/dts/omap3-devkit8000.dts16
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dts51
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts58
-rw-r--r--arch/arm/boot/dts/omap3-ldp.dts23
-rw-r--r--arch/arm/boot/dts/omap3-lilly-a83x.dtsi459
-rw-r--r--arch/arm/boot/dts/omap3-lilly-dbb056.dts170
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts167
-rw-r--r--arch/arm/boot/dts/omap3-overo-alto35-common.dtsi77
-rw-r--r--arch/arm/boot/dts/omap3-overo-alto35.dts22
-rw-r--r--arch/arm/boot/dts/omap3-overo-base.dtsi221
-rw-r--r--arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi69
-rw-r--r--arch/arm/boot/dts/omap3-overo-chestnut43.dts38
-rw-r--r--arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi94
-rw-r--r--arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi57
-rw-r--r--arch/arm/boot/dts/omap3-overo-gallop43.dts38
-rw-r--r--arch/arm/boot/dts/omap3-overo-palo43-common.dtsi53
-rw-r--r--arch/arm/boot/dts/omap3-overo-palo43.dts38
-rw-r--r--arch/arm/boot/dts/omap3-overo-storm-alto35.dts21
-rw-r--r--arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts38
-rw-r--r--arch/arm/boot/dts/omap3-overo-storm-gallop43.dts38
-rw-r--r--arch/arm/boot/dts/omap3-overo-storm-palo43.dts38
-rw-r--r--arch/arm/boot/dts/omap3-overo-storm-summit.dts30
-rw-r--r--arch/arm/boot/dts/omap3-overo-storm-tobi.dts2
-rw-r--r--arch/arm/boot/dts/omap3-overo-storm.dtsi35
-rw-r--r--arch/arm/boot/dts/omap3-overo-summit-common.dtsi31
-rw-r--r--arch/arm/boot/dts/omap3-overo-summit.dts30
-rw-r--r--arch/arm/boot/dts/omap3-overo-tobi-common.dtsi51
-rw-r--r--arch/arm/boot/dts/omap3-overo-tobi.dts2
-rw-r--r--arch/arm/boot/dts/omap3-overo.dtsi98
-rw-r--r--arch/arm/boot/dts/omap3-sb-t35.dtsi29
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3517.dts43
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3530.dts36
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3730.dts23
-rw-r--r--arch/arm/boot/dts/omap3.dtsi98
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts7
-rw-r--r--arch/arm/boot/dts/omap3430es1-clocks.dtsi16
-rw-r--r--arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi6
-rw-r--r--arch/arm/boot/dts/omap36xx-clocks.dtsi20
-rw-r--r--arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi10
-rw-r--r--arch/arm/boot/dts/omap36xx.dtsi28
-rw-r--r--arch/arm/boot/dts/omap3xxx-clocks.dtsi8
-rw-r--r--arch/arm/boot/dts/omap4-duovero-parlor.dts146
-rw-r--r--arch/arm/boot/dts/omap4-duovero.dtsi252
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi146
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts146
-rw-r--r--arch/arm/boot/dts/omap4.dtsi168
-rw-r--r--arch/arm/boot/dts/omap443x.dtsi26
-rw-r--r--arch/arm/boot/dts/omap4460.dtsi37
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts8
-rw-r--r--arch/arm/boot/dts/omap5.dtsi68
-rw-r--r--arch/arm/boot/dts/prima2.dtsi25
-rw-r--r--arch/arm/boot/dts/qcom-msm8660-surf.dts59
-rw-r--r--arch/arm/boot/dts/qcom-msm8660.dtsi87
-rw-r--r--arch/arm/boot/dts/qcom-msm8960-cdp.dts66
-rw-r--r--arch/arm/boot/dts/qcom-msm8960.dtsi135
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi81
-rw-r--r--arch/arm/boot/dts/r7s72100-genmai-reference.dts13
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi147
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw-reference.dts4
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi40
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts153
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi192
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch-reference.dts115
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts274
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi325
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi13
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi13
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi10
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi28
-rw-r--r--arch/arm/boot/dts/sama5d3xdm.dtsi6
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi41
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi11
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts21
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dtsi11
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts14
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts17
-rw-r--r--arch/arm/boot/dts/socfpga_vt.dts16
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi12
-rw-r--r--arch/arm/boot/dts/ste-href-ab8500.dtsi428
-rw-r--r--arch/arm/boot/dts/ste-href-ab8505.dtsi240
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60.dtsi1
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus.dtsi1
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts1
-rw-r--r--arch/arm/boot/dts/ste-u300.dts2
-rw-r--r--arch/arm/boot/dts/stih415-clock.dtsi14
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi204
-rw-r--r--arch/arm/boot/dts/stih415.dtsi70
-rw-r--r--arch/arm/boot/dts/stih416-clock.dtsi14
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi210
-rw-r--r--arch/arm/boot/dts/stih416.dtsi79
-rw-r--r--arch/arm/boot/dts/stih41x-b2000.dtsi22
-rw-r--r--arch/arm/boot/dts/stih41x-b2020.dtsi14
-rw-r--r--arch/arm/boot/dts/stih41x-b2020x.dtsi28
-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts55
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts40
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts56
-rw-r--r--arch/arm/boot/dts/sun4i-a10-inet97fv2.dts69
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts31
-rw-r--r--arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts111
-rw-r--r--arch/arm/boot/dts/sun4i-a10-pcduino.dts79
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi215
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts27
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi160
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts27
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts27
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi161
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts18
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi188
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts53
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubietruck.dts61
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts68
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi302
-rw-r--r--arch/arm/boot/dts/sunxi-common-regulators.dtsi75
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts9
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi8
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts312
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi339
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts46
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts55
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts39
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi4
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi7
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi6
-rw-r--r--arch/arm/boot/dts/tps65910.dtsi5
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi7
-rw-r--r--arch/arm/boot/dts/vf610-cosmic.dts29
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts158
-rw-r--r--arch/arm/boot/dts/vf610.dtsi273
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi43
360 files changed, 34832 insertions, 5191 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 032030361bef..35c146f31e46 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -12,6 +12,8 @@ dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
12dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb 12dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
13dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb 13dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
14dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb 14dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
15# sam9261
16dtb-$(CONFIG_ARCH_AT91) += at91sam9261ek.dtb
15# sam9263 17# sam9263
16dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb 18dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
17dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb 19dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
@@ -29,6 +31,8 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
29dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb 31dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
30# sam9n12 32# sam9n12
31dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb 33dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
34# sam9rl
35dtb-$(CONFIG_ARCH_AT91) += at91sam9rlek.dtb
32# sam9x5 36# sam9x5
33dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb 37dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
34dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb 38dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb
@@ -47,19 +51,15 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
47 51
48dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 52dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
49dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 53dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
50dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ 54dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
51 bcm28155-ap.dtb 55 bcm21664-garnet.dtb
52dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 56dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
57dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
53dtb-$(CONFIG_ARCH_BERLIN) += \ 58dtb-$(CONFIG_ARCH_BERLIN) += \
54 berlin2-sony-nsz-gs7.dtb \ 59 berlin2-sony-nsz-gs7.dtb \
55 berlin2cd-google-chromecast.dtb 60 berlin2cd-google-chromecast.dtb
56dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ 61dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
57 da850-evm.dtb 62 da850-evm.dtb
58dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
59 dove-cubox.dtb \
60 dove-d2plug.dtb \
61 dove-d3plug.dtb \
62 dove-dove-db.dtb
63dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb 63dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
64dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 64dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
65 exynos4210-smdkv310.dtb \ 65 exynos4210-smdkv310.dtb \
@@ -82,14 +82,30 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
82 ecx-2000.dtb 82 ecx-2000.dtb
83dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 83dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
84 integratorcp.dtb 84 integratorcp.dtb
85dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb 85dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
86dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ 86 k2l-evm.dtb \
87 k2e-evm.dtb
88kirkwood := \
89 kirkwood-b3.dtb \
90 kirkwood-cloudbox.dtb \
87 kirkwood-db-88f6281.dtb \ 91 kirkwood-db-88f6281.dtb \
88 kirkwood-db-88f6282.dtb \ 92 kirkwood-db-88f6282.dtb \
89 kirkwood-dns320.dtb \ 93 kirkwood-dns320.dtb \
90 kirkwood-dns325.dtb \ 94 kirkwood-dns325.dtb \
91 kirkwood-dockstar.dtb \ 95 kirkwood-dockstar.dtb \
92 kirkwood-dreamplug.dtb \ 96 kirkwood-dreamplug.dtb \
97 kirkwood-ds109.dtb \
98 kirkwood-ds110jv10.dtb \
99 kirkwood-ds111.dtb \
100 kirkwood-ds209.dtb \
101 kirkwood-ds210.dtb \
102 kirkwood-ds212.dtb \
103 kirkwood-ds212j.dtb \
104 kirkwood-ds409.dtb \
105 kirkwood-ds409slim.dtb \
106 kirkwood-ds411.dtb \
107 kirkwood-ds411j.dtb \
108 kirkwood-ds411slim.dtb \
93 kirkwood-goflexnet.dtb \ 109 kirkwood-goflexnet.dtb \
94 kirkwood-guruplug-server-plus.dtb \ 110 kirkwood-guruplug-server-plus.dtb \
95 kirkwood-ib62x0.dtb \ 111 kirkwood-ib62x0.dtb \
@@ -112,54 +128,74 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
112 kirkwood-nsa310a.dtb \ 128 kirkwood-nsa310a.dtb \
113 kirkwood-openblocks_a6.dtb \ 129 kirkwood-openblocks_a6.dtb \
114 kirkwood-openblocks_a7.dtb \ 130 kirkwood-openblocks_a7.dtb \
131 kirkwood-rd88f6192.dtb \
132 kirkwood-rd88f6281-a0.dtb \
133 kirkwood-rd88f6281-a1.dtb \
134 kirkwood-rs212.dtb \
135 kirkwood-rs409.dtb \
136 kirkwood-rs411.dtb \
115 kirkwood-sheevaplug.dtb \ 137 kirkwood-sheevaplug.dtb \
116 kirkwood-sheevaplug-esata.dtb \ 138 kirkwood-sheevaplug-esata.dtb \
139 kirkwood-t5325.dtb \
117 kirkwood-topkick.dtb \ 140 kirkwood-topkick.dtb \
118 kirkwood-ts219-6281.dtb \ 141 kirkwood-ts219-6281.dtb \
119 kirkwood-ts219-6282.dtb 142 kirkwood-ts219-6282.dtb \
143 kirkwood-ts419-6281.dtb \
144 kirkwood-ts419-6282.dtb
145dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood)
146dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood)
147dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
120dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 148dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
121dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb 149dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
122dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
123 qcom-msm8960-cdp.dtb \
124 qcom-apq8074-dragonboard.dtb
125dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
126 armada-370-mirabox.dtb \
127 armada-370-netgear-rn102.dtb \
128 armada-370-netgear-rn104.dtb \
129 armada-370-rd.dtb \
130 armada-xp-axpwifiap.dtb \
131 armada-xp-db.dtb \
132 armada-xp-gp.dtb \
133 armada-xp-netgear-rn2120.dtb \
134 armada-xp-matrix.dtb \
135 armada-xp-openblocks-ax3-4.dtb
136dtb-$(CONFIG_ARCH_MXC) += \ 150dtb-$(CONFIG_ARCH_MXC) += \
151 imx25-eukrea-mbimxsd25-baseboard.dtb \
137 imx25-karo-tx25.dtb \ 152 imx25-karo-tx25.dtb \
138 imx25-pdk.dtb \ 153 imx25-pdk.dtb \
139 imx27-apf27.dtb \ 154 imx27-apf27.dtb \
140 imx27-apf27dev.dtb \ 155 imx27-apf27dev.dtb \
141 imx27-pdk.dtb \ 156 imx27-pdk.dtb \
142 imx27-phytec-phycore-som.dtb \
143 imx27-phytec-phycore-rdk.dtb \ 157 imx27-phytec-phycore-rdk.dtb \
144 imx27-phytec-phycard-s-som.dtb \
145 imx27-phytec-phycard-s-rdk.dtb \ 158 imx27-phytec-phycard-s-rdk.dtb \
146 imx31-bug.dtb \ 159 imx31-bug.dtb \
160 imx35-eukrea-mbimxsd35-baseboard.dtb \
161 imx50-evk.dtb \
147 imx51-apf51.dtb \ 162 imx51-apf51.dtb \
148 imx51-apf51dev.dtb \ 163 imx51-apf51dev.dtb \
149 imx51-babbage.dtb \ 164 imx51-babbage.dtb \
165 imx51-eukrea-mbimxsd51-baseboard.dtb \
150 imx53-ard.dtb \ 166 imx53-ard.dtb \
151 imx53-evk.dtb \
152 imx53-m53evk.dtb \ 167 imx53-m53evk.dtb \
153 imx53-mba53.dtb \ 168 imx53-mba53.dtb \
154 imx53-qsb.dtb \ 169 imx53-qsb.dtb \
170 imx53-qsrb.dtb \
155 imx53-smd.dtb \ 171 imx53-smd.dtb \
172 imx53-tx53-x03x.dtb \
173 imx53-tx53-x13x.dtb \
174 imx53-voipac-bsb.dtb \
156 imx6dl-cubox-i.dtb \ 175 imx6dl-cubox-i.dtb \
176 imx6dl-dfi-fs700-m60.dtb \
177 imx6dl-gw51xx.dtb \
178 imx6dl-gw52xx.dtb \
179 imx6dl-gw53xx.dtb \
180 imx6dl-gw54xx.dtb \
157 imx6dl-hummingboard.dtb \ 181 imx6dl-hummingboard.dtb \
182 imx6dl-nitrogen6x.dtb \
158 imx6dl-sabreauto.dtb \ 183 imx6dl-sabreauto.dtb \
184 imx6dl-sabrelite.dtb \
159 imx6dl-sabresd.dtb \ 185 imx6dl-sabresd.dtb \
160 imx6dl-wandboard.dtb \ 186 imx6dl-wandboard.dtb \
161 imx6q-arm2.dtb \ 187 imx6q-arm2.dtb \
188 imx6q-cm-fx6.dtb \
162 imx6q-cubox-i.dtb \ 189 imx6q-cubox-i.dtb \
190 imx6q-dfi-fs700-m60.dtb \
191 imx6q-dmo-edmqmx6.dtb \
192 imx6q-gk802.dtb \
193 imx6q-gw51xx.dtb \
194 imx6q-gw52xx.dtb \
195 imx6q-gw53xx.dtb \
196 imx6q-gw5400-a.dtb \
197 imx6q-gw54xx.dtb \
198 imx6q-nitrogen6x.dtb \
163 imx6q-phytec-pbab01.dtb \ 199 imx6q-phytec-pbab01.dtb \
164 imx6q-sabreauto.dtb \ 200 imx6q-sabreauto.dtb \
165 imx6q-sabrelite.dtb \ 201 imx6q-sabrelite.dtb \
@@ -183,6 +219,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
183 imx28-cfa10056.dtb \ 219 imx28-cfa10056.dtb \
184 imx28-cfa10057.dtb \ 220 imx28-cfa10057.dtb \
185 imx28-cfa10058.dtb \ 221 imx28-cfa10058.dtb \
222 imx28-duckbill.dtb \
223 imx28-eukrea-mbmx283lc.dtb \
224 imx28-eukrea-mbmx287lc.dtb \
186 imx28-evk.dtb \ 225 imx28-evk.dtb \
187 imx28-m28cu3.dtb \ 226 imx28-m28cu3.dtb \
188 imx28-m28evk.dtb \ 227 imx28-m28evk.dtb \
@@ -199,6 +238,10 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
199 omap2420-n810-wimax.dtb \ 238 omap2420-n810-wimax.dtb \
200 omap3430-sdp.dtb \ 239 omap3430-sdp.dtb \
201 omap3-beagle.dtb \ 240 omap3-beagle.dtb \
241 omap3-cm-t3517.dtb \
242 omap3-sbc-t3517.dtb \
243 omap3-cm-t3530.dtb \
244 omap3-sbc-t3530.dtb \
202 omap3-cm-t3730.dtb \ 245 omap3-cm-t3730.dtb \
203 omap3-sbc-t3730.dtb \ 246 omap3-sbc-t3730.dtb \
204 omap3-devkit8000.dtb \ 247 omap3-devkit8000.dtb \
@@ -209,12 +252,24 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
209 omap3-n900.dtb \ 252 omap3-n900.dtb \
210 omap3-n9.dtb \ 253 omap3-n9.dtb \
211 omap3-n950.dtb \ 254 omap3-n950.dtb \
255 omap3-overo-alto35.dtb \
256 omap3-overo-storm-alto35.dtb \
257 omap3-overo-chestnut43.dtb \
258 omap3-overo-storm-chestnut43.dtb \
259 omap3-overo-gallop43.dtb \
260 omap3-overo-storm-gallop43.dtb \
261 omap3-overo-palo43.dtb \
262 omap3-overo-storm-palo43.dtb \
263 omap3-overo-summit.dtb \
264 omap3-overo-storm-summit.dtb \
212 omap3-overo-tobi.dtb \ 265 omap3-overo-tobi.dtb \
213 omap3-overo-storm-tobi.dtb \ 266 omap3-overo-storm-tobi.dtb \
214 omap3-gta04.dtb \ 267 omap3-gta04.dtb \
215 omap3-igep0020.dtb \ 268 omap3-igep0020.dtb \
216 omap3-igep0030.dtb \ 269 omap3-igep0030.dtb \
270 omap3-lilly-dbb056.dtb \
217 omap3-zoom3.dtb \ 271 omap3-zoom3.dtb \
272 omap4-duovero-parlor.dtb \
218 omap4-panda.dtb \ 273 omap4-panda.dtb \
219 omap4-panda-a4.dtb \ 274 omap4-panda-a4.dtb \
220 omap4-panda-es.dtb \ 275 omap4-panda-es.dtb \
@@ -228,12 +283,17 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
228 am335x-boneblack.dtb \ 283 am335x-boneblack.dtb \
229 am335x-nano.dtb \ 284 am335x-nano.dtb \
230 am335x-base0033.dtb \ 285 am335x-base0033.dtb \
286 am3517-craneboard.dtb \
231 am3517-evm.dtb \ 287 am3517-evm.dtb \
232 am3517_mt_ventoux.dtb \ 288 am3517_mt_ventoux.dtb \
233 am43x-epos-evm.dtb \ 289 am43x-epos-evm.dtb \
290 am437x-gp-evm.dtb \
234 dra7-evm.dtb 291 dra7-evm.dtb
235dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb 292dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
236dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 293dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
294dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
295 qcom-msm8960-cdp.dtb \
296 qcom-apq8074-dragonboard.dtb
237dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ 297dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
238 ste-hrefprev60-stuib.dtb \ 298 ste-hrefprev60-stuib.dtb \
239 ste-hrefprev60-tvk.dtb \ 299 ste-hrefprev60-tvk.dtb \
@@ -284,6 +344,9 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
284 sun4i-a10-cubieboard.dtb \ 344 sun4i-a10-cubieboard.dtb \
285 sun4i-a10-mini-xplus.dtb \ 345 sun4i-a10-mini-xplus.dtb \
286 sun4i-a10-hackberry.dtb \ 346 sun4i-a10-hackberry.dtb \
347 sun4i-a10-inet97fv2.dtb \
348 sun4i-a10-olinuxino-lime.dtb \
349 sun4i-a10-pcduino.dtb \
287 sun5i-a10s-olinuxino-micro.dtb \ 350 sun5i-a10s-olinuxino-micro.dtb \
288 sun5i-a13-olinuxino.dtb \ 351 sun5i-a13-olinuxino.dtb \
289 sun5i-a13-olinuxino-micro.dtb \ 352 sun5i-a13-olinuxino-micro.dtb \
@@ -322,8 +385,31 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
322dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ 385dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
323 zynq-zc706.dtb \ 386 zynq-zc706.dtb \
324 zynq-zed.dtb 387 zynq-zed.dtb
388dtb-$(CONFIG_MACH_ARMADA_370) += \
389 armada-370-db.dtb \
390 armada-370-mirabox.dtb \
391 armada-370-netgear-rn102.dtb \
392 armada-370-netgear-rn104.dtb \
393 armada-370-rd.dtb
394dtb-$(CONFIG_MACH_ARMADA_375) += \
395 armada-375-db.dtb
396dtb-$(CONFIG_MACH_ARMADA_38X) += \
397 armada-385-db.dtb \
398 armada-385-rd.dtb
399dtb-$(CONFIG_MACH_ARMADA_XP) += \
400 armada-xp-axpwifiap.dtb \
401 armada-xp-db.dtb \
402 armada-xp-gp.dtb \
403 armada-xp-netgear-rn2120.dtb \
404 armada-xp-matrix.dtb \
405 armada-xp-openblocks-ax3-4.dtb
406dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
407 dove-cubox.dtb \
408 dove-d2plug.dtb \
409 dove-d3plug.dtb \
410 dove-dove-db.dtb
325 411
326targets += dtbs 412targets += dtbs dtbs_install
327targets += $(dtb-y) 413targets += $(dtb-y)
328endif 414endif
329 415
@@ -333,3 +419,5 @@ dtbs: $(addprefix $(obj)/, $(dtb-y))
333 $(Q)rm -f $(obj)/../*.dtb 419 $(Q)rm -f $(obj)/../*.dtb
334 420
335clean-files := *.dtb 421clean-files := *.dtb
422
423dtbs_install: $(addsuffix _dtbinst_, $(dtb-y))
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 7e6c64ed966d..28ae040e7c3d 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -260,6 +260,12 @@
260 >; 260 >;
261 }; 261 };
262 262
263 mmc1_pins: pinmux_mmc1_pins {
264 pinctrl-single,pins = <
265 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
266 >;
267 };
268
263 lcd_pins_s0: lcd_pins_s0 { 269 lcd_pins_s0: lcd_pins_s0 {
264 pinctrl-single,pins = < 270 pinctrl-single,pins = <
265 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ 271 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
@@ -434,9 +440,9 @@
434 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 440 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
435 nand@0,0 { 441 nand@0,0 {
436 reg = <0 0 0>; /* CS0, offset 0 */ 442 reg = <0 0 0>; /* CS0, offset 0 */
437 nand-bus-width = <8>;
438 ti,nand-ecc-opt = "bch8"; 443 ti,nand-ecc-opt = "bch8";
439 gpmc,device-nand = "true"; 444 ti,elm-id = <&elm>;
445 nand-bus-width = <8>;
440 gpmc,device-width = <1>; 446 gpmc,device-width = <1>;
441 gpmc,sync-clk-ps = <0>; 447 gpmc,sync-clk-ps = <0>;
442 gpmc,cs-on-ns = <0>; 448 gpmc,cs-on-ns = <0>;
@@ -460,50 +466,51 @@
460 gpmc,wait-monitoring-ns = <0>; 466 gpmc,wait-monitoring-ns = <0>;
461 gpmc,wr-access-ns = <40>; 467 gpmc,wr-access-ns = <40>;
462 gpmc,wr-data-mux-bus-ns = <0>; 468 gpmc,wr-data-mux-bus-ns = <0>;
463 469 /* MTD partition table */
470 /* All SPL-* partitions are sized to minimal length
471 * which can be independently programmable. For
472 * NAND flash this is equal to size of erase-block */
464 #address-cells = <1>; 473 #address-cells = <1>;
465 #size-cells = <1>; 474 #size-cells = <1>;
466 elm_id = <&elm>;
467
468 /* MTD partition table */
469 partition@0 { 475 partition@0 {
470 label = "SPL1"; 476 label = "NAND.SPL";
471 reg = <0x00000000 0x000020000>; 477 reg = <0x00000000 0x000020000>;
472 }; 478 };
473
474 partition@1 { 479 partition@1 {
475 label = "SPL2"; 480 label = "NAND.SPL.backup1";
476 reg = <0x00020000 0x00020000>; 481 reg = <0x00020000 0x00020000>;
477 }; 482 };
478
479 partition@2 { 483 partition@2 {
480 label = "SPL3"; 484 label = "NAND.SPL.backup2";
481 reg = <0x00040000 0x00020000>; 485 reg = <0x00040000 0x00020000>;
482 }; 486 };
483
484 partition@3 { 487 partition@3 {
485 label = "SPL4"; 488 label = "NAND.SPL.backup3";
486 reg = <0x00060000 0x00020000>; 489 reg = <0x00060000 0x00020000>;
487 }; 490 };
488
489 partition@4 { 491 partition@4 {
490 label = "U-boot"; 492 label = "NAND.u-boot-spl";
491 reg = <0x00080000 0x001e0000>; 493 reg = <0x00080000 0x00040000>;
492 }; 494 };
493
494 partition@5 { 495 partition@5 {
495 label = "environment"; 496 label = "NAND.u-boot";
496 reg = <0x00260000 0x00020000>; 497 reg = <0x000C0000 0x00100000>;
497 }; 498 };
498
499 partition@6 { 499 partition@6 {
500 label = "Kernel"; 500 label = "NAND.u-boot-env";
501 reg = <0x00280000 0x00500000>; 501 reg = <0x001C0000 0x00020000>;
502 }; 502 };
503
504 partition@7 { 503 partition@7 {
505 label = "File-System"; 504 label = "NAND.u-boot-env.backup1";
506 reg = <0x00780000 0x0F880000>; 505 reg = <0x001E0000 0x00020000>;
506 };
507 partition@8 {
508 label = "NAND.kernel";
509 reg = <0x00200000 0x00800000>;
510 };
511 partition@9 {
512 label = "NAND.file-system";
513 reg = <0x00A00000 0x0F600000>;
507 }; 514 };
508 }; 515 };
509}; 516};
@@ -643,6 +650,9 @@
643 status = "okay"; 650 status = "okay";
644 vmmc-supply = <&vmmc_reg>; 651 vmmc-supply = <&vmmc_reg>;
645 bus-width = <4>; 652 bus-width = <4>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&mmc1_pins>;
655 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
646}; 656};
647 657
648&sham { 658&sham {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 486880b74831..ec08f6f677c3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -45,6 +45,18 @@
45 regulator-boot-on; 45 regulator-boot-on;
46 }; 46 };
47 47
48 wl12xx_vmmc: fixedregulator@2 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&wl12xx_gpio>;
51 compatible = "regulator-fixed";
52 regulator-name = "vwl1271";
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <1800000>;
55 gpio = <&gpio1 29 0>;
56 startup-delay-us = <70000>;
57 enable-active-high;
58 };
59
48 leds { 60 leds {
49 pinctrl-names = "default"; 61 pinctrl-names = "default";
50 pinctrl-0 = <&user_leds_s0>; 62 pinctrl-0 = <&user_leds_s0>;
@@ -270,6 +282,24 @@
270 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 282 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
271 >; 283 >;
272 }; 284 };
285
286 mmc2_pins: pinmux_mmc2_pins {
287 pinctrl-single,pins = <
288 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
289 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
290 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
291 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
292 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
293 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
294 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
295 >;
296 };
297
298 wl12xx_gpio: pinmux_wl12xx_gpio {
299 pinctrl-single,pins = <
300 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
301 >;
302 };
273}; 303};
274 304
275&uart0 { 305&uart0 {
@@ -342,9 +372,22 @@
342 status = "okay"; 372 status = "okay";
343 }; 373 };
344 374
375 usb-phy@47401b00 {
376 status = "okay";
377 };
378
345 usb@47401000 { 379 usb@47401000 {
346 status = "okay"; 380 status = "okay";
347 }; 381 };
382
383 usb@47401800 {
384 status = "okay";
385 dr_mode = "host";
386 };
387
388 dma-controller@07402000 {
389 status = "okay";
390 };
348}; 391};
349 392
350&epwmss2 { 393&epwmss2 {
@@ -440,6 +483,7 @@
440 pinctrl-names = "default", "sleep"; 483 pinctrl-names = "default", "sleep";
441 pinctrl-0 = <&cpsw_default>; 484 pinctrl-0 = <&cpsw_default>;
442 pinctrl-1 = <&cpsw_sleep>; 485 pinctrl-1 = <&cpsw_sleep>;
486 dual_emac = <1>;
443}; 487};
444 488
445&davinci_mdio { 489&davinci_mdio {
@@ -451,11 +495,13 @@
451&cpsw_emac0 { 495&cpsw_emac0 {
452 phy_id = <&davinci_mdio>, <0>; 496 phy_id = <&davinci_mdio>, <0>;
453 phy-mode = "rgmii-txid"; 497 phy-mode = "rgmii-txid";
498 dual_emac_res_vlan = <1>;
454}; 499};
455 500
456&cpsw_emac1 { 501&cpsw_emac1 {
457 phy_id = <&davinci_mdio>, <1>; 502 phy_id = <&davinci_mdio>, <1>;
458 phy-mode = "rgmii-txid"; 503 phy-mode = "rgmii-txid";
504 dual_emac_res_vlan = <2>;
459}; 505};
460 506
461&mmc1 { 507&mmc1 {
@@ -479,6 +525,16 @@
479 ti,no-reset-on-init; 525 ti,no-reset-on-init;
480}; 526};
481 527
528&mmc2 {
529 status = "okay";
530 vmmc-supply = <&wl12xx_vmmc>;
531 ti,non-removable;
532 bus-width = <4>;
533 cap-power-off-card;
534 pinctrl-names = "default";
535 pinctrl-0 = <&mmc2_pins>;
536};
537
482&mcasp1 { 538&mcasp1 {
483 pinctrl-names = "default"; 539 pinctrl-names = "default";
484 pinctrl-0 = <&mcasp1_pins>; 540 pinctrl-0 = <&mcasp1_pins>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 6d95d3df33c7..9770e35f2536 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -58,6 +58,10 @@
58 275000 1125000 58 275000 1125000
59 >; 59 >;
60 voltage-tolerance = <2>; /* 2 percentage */ 60 voltage-tolerance = <2>; /* 2 percentage */
61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
61 clock-latency = <300000>; /* From omap-cpufreq driver */ 65 clock-latency = <300000>; /* From omap-cpufreq driver */
62 }; 66 };
63 }; 67 };
@@ -318,6 +322,7 @@
318 compatible = "ti,omap4-hwspinlock"; 322 compatible = "ti,omap4-hwspinlock";
319 reg = <0x480ca000 0x1000>; 323 reg = <0x480ca000 0x1000>;
320 ti,hwmods = "spinlock"; 324 ti,hwmods = "spinlock";
325 #hwlock-cells = <1>;
321 }; 326 };
322 327
323 wdt2: wdt@44e35000 { 328 wdt2: wdt@44e35000 {
@@ -399,7 +404,7 @@
399 ti,timer-pwm; 404 ti,timer-pwm;
400 }; 405 };
401 406
402 rtc@44e3e000 { 407 rtc: rtc@44e3e000 {
403 compatible = "ti,da830-rtc"; 408 compatible = "ti,da830-rtc";
404 reg = <0x44e3e000 0x1000>; 409 reg = <0x44e3e000 0x1000>;
405 interrupts = <75 410 interrupts = <75
@@ -448,7 +453,7 @@
448 ti,hwmods = "usb_otg_hs"; 453 ti,hwmods = "usb_otg_hs";
449 status = "disabled"; 454 status = "disabled";
450 455
451 usb_ctrl_mod: control@44e10000 { 456 usb_ctrl_mod: control@44e10620 {
452 compatible = "ti,am335x-usb-ctrl-module"; 457 compatible = "ti,am335x-usb-ctrl-module";
453 reg = <0x44e10620 0x10 458 reg = <0x44e10620 0x10
454 0x44e10648 0x4>; 459 0x44e10648 0x4>;
@@ -551,7 +556,7 @@
551 "tx14", "tx15"; 556 "tx14", "tx15";
552 }; 557 };
553 558
554 cppi41dma: dma-controller@07402000 { 559 cppi41dma: dma-controller@47402000 {
555 compatible = "ti,am3359-cppi41"; 560 compatible = "ti,am3359-cppi41";
556 reg = <0x47400000 0x1000 561 reg = <0x47400000 0x1000
557 0x47402000 0x1000 562 0x47402000 0x1000
@@ -582,6 +587,8 @@
582 compatible = "ti,am33xx-ecap"; 587 compatible = "ti,am33xx-ecap";
583 #pwm-cells = <3>; 588 #pwm-cells = <3>;
584 reg = <0x48300100 0x80>; 589 reg = <0x48300100 0x80>;
590 interrupts = <31>;
591 interrupt-names = "ecap0";
585 ti,hwmods = "ecap0"; 592 ti,hwmods = "ecap0";
586 status = "disabled"; 593 status = "disabled";
587 }; 594 };
@@ -610,6 +617,8 @@
610 compatible = "ti,am33xx-ecap"; 617 compatible = "ti,am33xx-ecap";
611 #pwm-cells = <3>; 618 #pwm-cells = <3>;
612 reg = <0x48302100 0x80>; 619 reg = <0x48302100 0x80>;
620 interrupts = <47>;
621 interrupt-names = "ecap1";
613 ti,hwmods = "ecap1"; 622 ti,hwmods = "ecap1";
614 status = "disabled"; 623 status = "disabled";
615 }; 624 };
@@ -638,6 +647,8 @@
638 compatible = "ti,am33xx-ecap"; 647 compatible = "ti,am33xx-ecap";
639 #pwm-cells = <3>; 648 #pwm-cells = <3>;
640 reg = <0x48304100 0x80>; 649 reg = <0x48304100 0x80>;
650 interrupts = <61>;
651 interrupt-names = "ecap2";
641 ti,hwmods = "ecap2"; 652 ti,hwmods = "ecap2";
642 status = "disabled"; 653 status = "disabled";
643 }; 654 };
diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts
new file mode 100644
index 000000000000..2d40b3f241cd
--- /dev/null
+++ b/arch/arm/boot/dts/am3517-craneboard.dts
@@ -0,0 +1,174 @@
1/*
2 * See craneboard.org for more details
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10/dts-v1/;
11
12#include "am3517.dtsi"
13
14/ {
15 model = "TI AM3517 CraneBoard (TMDSEVM3517)";
16 compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3";
17
18 memory {
19 device_type = "memory";
20 reg = <0x80000000 0x10000000>; /* 256 MB */
21 };
22
23 vbat: fixedregulator@0 {
24 compatible = "regulator-fixed";
25 regulator-name = "vbat";
26 regulator-min-microvolt = <5000000>;
27 regulator-max-microvolt = <5000000>;
28 regulator-boot-on;
29 };
30};
31
32&davinci_emac {
33 status = "okay";
34};
35
36&davinci_mdio {
37 status = "okay";
38};
39
40&i2c1 {
41 clock-frequency = <2600000>;
42
43 tps: tps@2d {
44 reg = <0x2d>;
45 };
46};
47
48&i2c2 {
49 clock-frequency = <400000>;
50 /* goes to expansion connector */
51 status = "disabled";
52};
53
54&i2c3 {
55 clock-frequency = <400000>;
56 /* goes to expansion connector */
57 status = "disabled";
58};
59
60&mmc1 {
61 vmmc-supply = <&vdd2_reg>;
62 bus-width = <8>;
63};
64
65&mmc2 {
66 /* goes to expansion connector */
67 status = "disabled";
68};
69
70&mmc3 {
71 /* goes to expansion connector */
72 status = "disabled";
73};
74
75#include "tps65910.dtsi"
76
77&omap3_pmx_core {
78 tps_pins: pinmux_tps_pins {
79 pinctrl-single,pins = <
80 0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */
81 >;
82 };
83};
84
85&tps {
86 pinctrl-names = "default";
87 pinctrl-0 = <&tps_pins>;
88
89 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
90 interrupt-parent = <&intc>;
91
92 ti,en-ck32k-xtal;
93
94 vcc1-supply = <&vbat>;
95 vcc2-supply = <&vbat>;
96 vcc3-supply = <&vbat>;
97 vcc4-supply = <&vbat>;
98 vcc5-supply = <&vbat>;
99 vcc6-supply = <&vbat>;
100 vcc7-supply = <&vbat>;
101 vccio-supply = <&vbat>;
102
103 regulators {
104 vrtc_reg: regulator@0 {
105 regulator-always-on;
106 };
107
108 vio_reg: regulator@1 {
109 regulator-always-on;
110 };
111
112 /*
113 * Unused:
114 * VDIG1=2.7V,300mA max
115 * VDIG2=1.8V,300mA max
116 */
117
118 vpll_reg: regulator@7 {
119 /* VDDS_DPLL_1V8 */
120 regulator-min-microvolt = <1800000>;
121 regulator-max-microvolt = <1800000>;
122 regulator-always-on;
123 };
124
125 vaux1_reg: regulator@9 {
126 /* VDDS_SRAM_1V8 */
127 regulator-min-microvolt = <1800000>;
128 regulator-max-microvolt = <1800000>;
129 regulator-always-on;
130 };
131
132 vaux2_reg: regulator@10 {
133 /* VDDA1P8V_USBPHY */
134 regulator-min-microvolt = <1800000>;
135 regulator-max-microvolt = <1800000>;
136 regulator-always-on;
137 };
138
139 /* VAUX33 unused */
140
141 vdac_reg: regulator@8 {
142 /* VDDA_DAC_1V8 */
143 regulator-min-microvolt = <1800000>;
144 regulator-max-microvolt = <1800000>;
145 regulator-always-on;
146 };
147
148 vmmc_reg: regulator@12 {
149 /* VDDA3P3V_USBPHY */
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 regulator-always-on;
153 };
154
155 vdd1_reg: regulator@2 {
156 /* VDD_CORE */
157 regulator-name = "vdd_core";
158 regulator-min-microvolt = <1200000>;
159 regulator-max-microvolt = <1200000>;
160 regulator-boot-on;
161 regulator-always-on;
162 };
163
164 vdd2_reg: regulator@3 {
165 /* VDDSHV_3V3 */
166 regulator-name = "vdd_shv";
167 regulator-min-microvolt = <3300000>;
168 regulator-max-microvolt = <3300000>;
169 regulator-always-on;
170 };
171
172 /* VDD3 unused */
173 };
174};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index c6bd4d986c29..36d523a26831 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -8,6 +8,7 @@
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
12 13
13#include "skeleton.dtsi" 14#include "skeleton.dtsi"
@@ -33,6 +34,11 @@
33 compatible = "arm,cortex-a9"; 34 compatible = "arm,cortex-a9";
34 device_type = "cpu"; 35 device_type = "cpu";
35 reg = <0>; 36 reg = <0>;
37
38 clocks = <&dpll_mpu_ck>;
39 clock-names = "cpu";
40
41 clock-latency = <300000>; /* From omap-cpufreq driver */
36 }; 42 };
37 }; 43 };
38 44
@@ -351,6 +357,13 @@
351 status = "disabled"; 357 status = "disabled";
352 }; 358 };
353 359
360 hwspinlock: spinlock@480ca000 {
361 compatible = "ti,omap4-hwspinlock";
362 reg = <0x480ca000 0x1000>;
363 ti,hwmods = "spinlock";
364 #hwlock-cells = <1>;
365 };
366
354 i2c0: i2c@44e0b000 { 367 i2c0: i2c@44e0b000 {
355 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 368 compatible = "ti,am4372-i2c","ti,omap4-i2c";
356 reg = <0x44e0b000 0x1000>; 369 reg = <0x44e0b000 0x1000>;
@@ -521,6 +534,7 @@
521 534
522 ecap0: ecap@48300100 { 535 ecap0: ecap@48300100 {
523 compatible = "ti,am4372-ecap","ti,am33xx-ecap"; 536 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
537 #pwm-cells = <3>;
524 reg = <0x48300100 0x80>; 538 reg = <0x48300100 0x80>;
525 ti,hwmods = "ecap0"; 539 ti,hwmods = "ecap0";
526 status = "disabled"; 540 status = "disabled";
@@ -528,6 +542,7 @@
528 542
529 ehrpwm0: ehrpwm@48300200 { 543 ehrpwm0: ehrpwm@48300200 {
530 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 544 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
545 #pwm-cells = <3>;
531 reg = <0x48300200 0x80>; 546 reg = <0x48300200 0x80>;
532 ti,hwmods = "ehrpwm0"; 547 ti,hwmods = "ehrpwm0";
533 status = "disabled"; 548 status = "disabled";
@@ -545,6 +560,7 @@
545 560
546 ecap1: ecap@48302100 { 561 ecap1: ecap@48302100 {
547 compatible = "ti,am4372-ecap","ti,am33xx-ecap"; 562 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
563 #pwm-cells = <3>;
548 reg = <0x48302100 0x80>; 564 reg = <0x48302100 0x80>;
549 ti,hwmods = "ecap1"; 565 ti,hwmods = "ecap1";
550 status = "disabled"; 566 status = "disabled";
@@ -552,6 +568,7 @@
552 568
553 ehrpwm1: ehrpwm@48302200 { 569 ehrpwm1: ehrpwm@48302200 {
554 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 570 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
571 #pwm-cells = <3>;
555 reg = <0x48302200 0x80>; 572 reg = <0x48302200 0x80>;
556 ti,hwmods = "ehrpwm1"; 573 ti,hwmods = "ehrpwm1";
557 status = "disabled"; 574 status = "disabled";
@@ -569,6 +586,7 @@
569 586
570 ecap2: ecap@48304100 { 587 ecap2: ecap@48304100 {
571 compatible = "ti,am4372-ecap","ti,am33xx-ecap"; 588 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
589 #pwm-cells = <3>;
572 reg = <0x48304100 0x80>; 590 reg = <0x48304100 0x80>;
573 ti,hwmods = "ecap2"; 591 ti,hwmods = "ecap2";
574 status = "disabled"; 592 status = "disabled";
@@ -576,6 +594,7 @@
576 594
577 ehrpwm2: ehrpwm@48304200 { 595 ehrpwm2: ehrpwm@48304200 {
578 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 596 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
597 #pwm-cells = <3>;
579 reg = <0x48304200 0x80>; 598 reg = <0x48304200 0x80>;
580 ti,hwmods = "ehrpwm2"; 599 ti,hwmods = "ehrpwm2";
581 status = "disabled"; 600 status = "disabled";
@@ -593,6 +612,7 @@
593 612
594 ehrpwm3: ehrpwm@48306200 { 613 ehrpwm3: ehrpwm@48306200 {
595 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 614 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
615 #pwm-cells = <3>;
596 reg = <0x48306200 0x80>; 616 reg = <0x48306200 0x80>;
597 ti,hwmods = "ehrpwm3"; 617 ti,hwmods = "ehrpwm3";
598 status = "disabled"; 618 status = "disabled";
@@ -610,6 +630,7 @@
610 630
611 ehrpwm4: ehrpwm@48308200 { 631 ehrpwm4: ehrpwm@48308200 {
612 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 632 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
633 #pwm-cells = <3>;
613 reg = <0x48308200 0x80>; 634 reg = <0x48308200 0x80>;
614 ti,hwmods = "ehrpwm4"; 635 ti,hwmods = "ehrpwm4";
615 status = "disabled"; 636 status = "disabled";
@@ -627,6 +648,7 @@
627 648
628 ehrpwm5: ehrpwm@4830a200 { 649 ehrpwm5: ehrpwm@4830a200 {
629 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 650 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
651 #pwm-cells = <3>;
630 reg = <0x4830a200 0x80>; 652 reg = <0x4830a200 0x80>;
631 ti,hwmods = "ehrpwm5"; 653 ti,hwmods = "ehrpwm5";
632 status = "disabled"; 654 status = "disabled";
@@ -689,6 +711,30 @@
689 <&edma 11>; 711 <&edma 11>;
690 dma-names = "tx", "rx"; 712 dma-names = "tx", "rx";
691 }; 713 };
714
715 elm: elm@48080000 {
716 compatible = "ti,am3352-elm";
717 reg = <0x48080000 0x2000>;
718 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
719 ti,hwmods = "elm";
720 clocks = <&l4ls_gclk>;
721 clock-names = "fck";
722 status = "disabled";
723 };
724
725 gpmc: gpmc@50000000 {
726 compatible = "ti,am3352-gpmc";
727 ti,hwmods = "gpmc";
728 clocks = <&l3s_gclk>;
729 clock-names = "fck";
730 reg = <0x50000000 0x2000>;
731 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
732 gpmc,num-cs = <7>;
733 gpmc,num-waitpins = <2>;
734 #address-cells = <2>;
735 #size-cells = <1>;
736 status = "disabled";
737 };
692 }; 738 };
693}; 739};
694 740
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
new file mode 100644
index 000000000000..df8798e8bd25
--- /dev/null
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -0,0 +1,127 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x GP EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/pwm/pwm.h>
16#include <dt-bindings/gpio/gpio.h>
17
18/ {
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
21
22 vmmcsd_fixed: fixedregulator-sd {
23 compatible = "regulator-fixed";
24 regulator-name = "vmmcsd_fixed";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 enable-active-high;
28 };
29
30 backlight {
31 compatible = "pwm-backlight";
32 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
33 brightness-levels = <0 51 53 56 62 75 101 152 255>;
34 default-brightness-level = <8>;
35 };
36
37 matrix_keypad: matrix_keypad@0 {
38 compatible = "gpio-matrix-keypad";
39 debounce-delay-ms = <5>;
40 col-scan-delay-us = <2>;
41
42 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
43 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
44 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
45
46 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
47 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
48
49 linux,keymap = <0x00000201 /* P1 */
50 0x00010202 /* P2 */
51 0x01000067 /* UP */
52 0x0101006a /* RIGHT */
53 0x02000069 /* LEFT */
54 0x0201006c>; /* DOWN */
55 };
56};
57
58&am43xx_pinmux {
59 i2c0_pins: i2c0_pins {
60 pinctrl-single,pins = <
61 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
62 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
63 >;
64 };
65
66 i2c1_pins: i2c1_pins {
67 pinctrl-single,pins = <
68 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
69 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
70 >;
71 };
72
73 mmc1_pins: pinmux_mmc1_pins {
74 pinctrl-single,pins = <
75 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
76 >;
77 };
78
79 ecap0_pins: backlight_pins {
80 pinctrl-single,pins = <
81 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
82 >;
83 };
84};
85
86&i2c0 {
87 status = "okay";
88 pinctrl-names = "default";
89 pinctrl-0 = <&i2c0_pins>;
90};
91
92&i2c1 {
93 status = "okay";
94 pinctrl-names = "default";
95 pinctrl-0 = <&i2c1_pins>;
96};
97
98&epwmss0 {
99 status = "okay";
100};
101
102&ecap0 {
103 status = "okay";
104 pinctrl-names = "default";
105 pinctrl-0 = <&ecap0_pins>;
106};
107
108&gpio0 {
109 status = "okay";
110};
111
112&gpio3 {
113 status = "okay";
114};
115
116&gpio4 {
117 status = "okay";
118};
119
120&mmc1 {
121 status = "okay";
122 vmmc-supply = <&vmmcsd_fixed>;
123 bus-width = <4>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&mmc1_pins>;
126 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
127};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c7a94f..167dbc8494de 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -13,6 +13,7 @@
13#include "am4372.dtsi" 13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h> 14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pwm/pwm.h>
16 17
17/ { 18/ {
18 model = "TI AM43x EPOS EVM"; 19 model = "TI AM43x EPOS EVM";
@@ -79,6 +80,64 @@
79 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 80 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
80 >; 81 >;
81 }; 82 };
83
84 nand_flash_x8: nand_flash_x8 {
85 pinctrl-single,pins = <
86 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
87 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
88 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
89 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
90 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
91 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
92 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
93 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
94 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
95 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
96 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
97 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
98 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
99 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
100 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
101 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
102 >;
103 };
104
105 ecap0_pins: backlight_pins {
106 pinctrl-single,pins = <
107 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
108 >;
109 };
110
111 i2c2_pins: pinmux_i2c2_pins {
112 pinctrl-single,pins = <
113 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
114 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
115 >;
116 };
117
118 spi0_pins: pinmux_spi0_pins {
119 pinctrl-single,pins = <
120 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
121 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
122 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
123 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
124 >;
125 };
126
127 spi1_pins: pinmux_spi1_pins {
128 pinctrl-single,pins = <
129 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
130 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
131 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
132 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
133 >;
134 };
135
136 mmc1_pins: pinmux_mmc1_pins {
137 pinctrl-single,pins = <
138 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
139 >;
140 };
82 }; 141 };
83 142
84 matrix_keypad: matrix_keypad@0 { 143 matrix_keypad: matrix_keypad@0 {
@@ -113,12 +172,22 @@
113 0x0203006c /* DOWN */ 172 0x0203006c /* DOWN */
114 0x03030069>; /* LEFT */ 173 0x03030069>; /* LEFT */
115 }; 174 };
175
176 backlight {
177 compatible = "pwm-backlight";
178 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
179 brightness-levels = <0 51 53 56 62 75 101 152 255>;
180 default-brightness-level = <8>;
181 };
116}; 182};
117 183
118&mmc1 { 184&mmc1 {
119 status = "okay"; 185 status = "okay";
120 vmmc-supply = <&vmmcsd_fixed>; 186 vmmc-supply = <&vmmcsd_fixed>;
121 bus-width = <4>; 187 bus-width = <4>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&mmc1_pins>;
190 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
122}; 191};
123 192
124&mac { 193&mac {
@@ -169,6 +238,12 @@
169 }; 238 };
170}; 239};
171 240
241&i2c2 {
242 pinctrl-names = "default";
243 pinctrl-0 = <&i2c2_pins>;
244 status = "okay";
245};
246
172&gpio0 { 247&gpio0 {
173 status = "okay"; 248 status = "okay";
174}; 249};
@@ -184,3 +259,111 @@
184&gpio3 { 259&gpio3 {
185 status = "okay"; 260 status = "okay";
186}; 261};
262
263&elm {
264 status = "okay";
265};
266
267&gpmc {
268 status = "okay";
269 pinctrl-names = "default";
270 pinctrl-0 = <&nand_flash_x8>;
271 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
272 nand@0,0 {
273 reg = <0 0 0>; /* CS0, offset 0 */
274 ti,nand-ecc-opt = "bch8";
275 ti,elm-id = <&elm>;
276 nand-bus-width = <8>;
277 gpmc,device-width = <1>;
278 gpmc,sync-clk-ps = <0>;
279 gpmc,cs-on-ns = <0>;
280 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
281 gpmc,cs-wr-off-ns = <40>;
282 gpmc,adv-on-ns = <0>; /* cs-on-ns */
283 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
284 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
285 gpmc,we-on-ns = <0>; /* cs-on-ns */
286 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
287 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
288 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
289 gpmc,access-ns = <30>; /* tCEA + 4*/
290 gpmc,rd-cycle-ns = <40>;
291 gpmc,wr-cycle-ns = <40>;
292 gpmc,wait-on-read = "true";
293 gpmc,wait-on-write = "true";
294 gpmc,bus-turnaround-ns = <0>;
295 gpmc,cycle2cycle-delay-ns = <0>;
296 gpmc,clk-activation-ns = <0>;
297 gpmc,wait-monitoring-ns = <0>;
298 gpmc,wr-access-ns = <40>;
299 gpmc,wr-data-mux-bus-ns = <0>;
300 /* MTD partition table */
301 /* All SPL-* partitions are sized to minimal length
302 * which can be independently programmable. For
303 * NAND flash this is equal to size of erase-block */
304 #address-cells = <1>;
305 #size-cells = <1>;
306 partition@0 {
307 label = "NAND.SPL";
308 reg = <0x00000000 0x00040000>;
309 };
310 partition@1 {
311 label = "NAND.SPL.backup1";
312 reg = <0x00040000 0x00040000>;
313 };
314 partition@2 {
315 label = "NAND.SPL.backup2";
316 reg = <0x00080000 0x00040000>;
317 };
318 partition@3 {
319 label = "NAND.SPL.backup3";
320 reg = <0x000C0000 0x00040000>;
321 };
322 partition@4 {
323 label = "NAND.u-boot-spl-os";
324 reg = <0x00100000 0x00080000>;
325 };
326 partition@5 {
327 label = "NAND.u-boot";
328 reg = <0x00180000 0x00100000>;
329 };
330 partition@6 {
331 label = "NAND.u-boot-env";
332 reg = <0x00280000 0x00040000>;
333 };
334 partition@7 {
335 label = "NAND.u-boot-env.backup1";
336 reg = <0x002C0000 0x00040000>;
337 };
338 partition@8 {
339 label = "NAND.kernel";
340 reg = <0x00300000 0x00700000>;
341 };
342 partition@9 {
343 label = "NAND.file-system";
344 reg = <0x00800000 0x1F600000>;
345 };
346 };
347};
348
349&epwmss0 {
350 status = "okay";
351};
352
353&ecap0 {
354 status = "okay";
355 pinctrl-names = "default";
356 pinctrl-0 = <&ecap0_pins>;
357};
358
359&spi0 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&spi0_pins>;
362 status = "okay";
363};
364
365&spi1 {
366 pinctrl-names = "default";
367 pinctrl-0 = <&spi1_pins>;
368 status = "okay";
369};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 08a56bcfc724..82f238a9063f 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -64,6 +64,22 @@
64 phy-mode = "rgmii-id"; 64 phy-mode = "rgmii-id";
65 }; 65 };
66 66
67 i2c@11000 {
68 pinctrl-0 = <&i2c0_pins>;
69 pinctrl-names = "default";
70 status = "okay";
71 audio_codec: audio-codec@4a {
72 compatible = "cirrus,cs42l51";
73 reg = <0x4a>;
74 };
75 };
76
77 audio-controller@30000 {
78 pinctrl-0 = <&i2s_pins2>;
79 pinctrl-names = "default";
80 status = "okay";
81 };
82
67 mvsdio@d4000 { 83 mvsdio@d4000 {
68 pinctrl-0 = <&sdio_pins1>; 84 pinctrl-0 = <&sdio_pins1>;
69 pinctrl-names = "default"; 85 pinctrl-names = "default";
@@ -80,6 +96,30 @@
80 broken-cd; 96 broken-cd;
81 }; 97 };
82 98
99 pinctrl {
100 /*
101 * These pins might be muxed as I2S by
102 * the bootloader, but it conflicts
103 * with the real I2S pins that are
104 * muxed using i2s_pins. We must mux
105 * those pins to a function other than
106 * I2S.
107 */
108 pinctrl-0 = <&hog_pins1 &hog_pins2>;
109 pinctrl-names = "default";
110
111 hog_pins1: hog-pins1 {
112 marvell,pins = "mpp6", "mpp8", "mpp10",
113 "mpp12", "mpp13";
114 marvell,function = "gpio";
115 };
116
117 hog_pins2: hog-pins2 {
118 marvell,pins = "mpp5", "mpp7", "mpp9";
119 marvell,function = "gpo";
120 };
121 };
122
83 usb@50000 { 123 usb@50000 {
84 status = "okay"; 124 status = "okay";
85 }; 125 };
@@ -112,10 +152,26 @@
112 /* Port 0, Lane 0 */ 152 /* Port 0, Lane 0 */
113 status = "okay"; 153 status = "okay";
114 }; 154 };
155
115 pcie@2,0 { 156 pcie@2,0 {
116 /* Port 1, Lane 0 */ 157 /* Port 1, Lane 0 */
117 status = "okay"; 158 status = "okay";
118 }; 159 };
119 }; 160 };
120 }; 161 };
162
163 sound {
164 compatible = "marvell,a370db-audio";
165 marvell,audio-controller = <&audio_controller>;
166 marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>;
167 status = "okay";
168 };
169
170 spdif_out: spdif-out {
171 compatible = "linux,spdif-dit";
172 };
173
174 spdif_in: spdif-in {
175 compatible = "linux,spdif-dir";
176 };
121}; 177};
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 944e8785b308..2354fe023ee0 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -9,6 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12#include <dt-bindings/gpio/gpio.h>
12#include "armada-370.dtsi" 13#include "armada-370.dtsi"
13 14
14/ { 15/ {
@@ -73,19 +74,19 @@
73 74
74 green_pwr_led { 75 green_pwr_led {
75 label = "mirabox:green:pwr"; 76 label = "mirabox:green:pwr";
76 gpios = <&gpio1 31 1>; 77 gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
77 default-state = "keep"; 78 default-state = "keep";
78 }; 79 };
79 80
80 blue_stat_led { 81 blue_stat_led {
81 label = "mirabox:blue:stat"; 82 label = "mirabox:blue:stat";
82 gpios = <&gpio2 0 1>; 83 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
83 default-state = "off"; 84 default-state = "off";
84 }; 85 };
85 86
86 green_stat_led { 87 green_stat_led {
87 label = "mirabox:green:stat"; 88 label = "mirabox:green:stat";
88 gpios = <&gpio2 1 1>; 89 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
89 default-state = "off"; 90 default-state = "off";
90 }; 91 };
91 }; 92 };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index abbb807459d2..3e2c857d6000 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -12,6 +12,8 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15#include <dt-bindings/input/input.h>
16#include <dt-bindings/gpio/gpio.h>
15#include "armada-370.dtsi" 17#include "armada-370.dtsi"
16 18
17/ { 19/ {
@@ -100,8 +102,8 @@
100 #size-cells = <0>; 102 #size-cells = <0>;
101 button@1 { 103 button@1 {
102 label = "Software Button"; 104 label = "Software Button";
103 linux,code = <116>; 105 linux,code = <KEY_POWER>;
104 gpios = <&gpio0 6 1>; 106 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
105 }; 107 };
106 }; 108 };
107 109
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 74b5964430ac..bbb40f62037d 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -44,8 +44,8 @@
44 #size-cells = <1>; 44 #size-cells = <1>;
45 controller = <&mbusc>; 45 controller = <&mbusc>;
46 interrupt-parent = <&mpic>; 46 interrupt-parent = <&mpic>;
47 pcie-mem-aperture = <0xe0000000 0x8000000>; 47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xe8000000 0x100000>; 48 pcie-io-aperture = <0xffe00000 0x100000>;
49 49
50 devbus-bootcs { 50 devbus-bootcs {
51 compatible = "marvell,mvebu-devbus"; 51 compatible = "marvell,mvebu-devbus";
@@ -199,6 +199,10 @@
199 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 199 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
200 }; 200 };
201 201
202 watchdog@20300 {
203 reg = <0x20300 0x34>, <0x20704 0x4>;
204 };
205
202 usb@50000 { 206 usb@50000 {
203 compatible = "marvell,orion-ehci"; 207 compatible = "marvell,orion-ehci";
204 reg = <0x50000 0x500>; 208 reg = <0x50000 0x500>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 0d8530c98cf5..af1f11e9e5a0 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -132,6 +132,25 @@
132 "mpp51", "mpp52", "mpp53"; 132 "mpp51", "mpp52", "mpp53";
133 marvell,function = "sd0"; 133 marvell,function = "sd0";
134 }; 134 };
135
136 i2c0_pins: i2c0-pins {
137 marvell,pins = "mpp2", "mpp3";
138 marvell,function = "i2c0";
139 };
140
141 i2s_pins1: i2s-pins1 {
142 marvell,pins = "mpp5", "mpp6", "mpp7",
143 "mpp8", "mpp9", "mpp10",
144 "mpp12", "mpp13";
145 marvell,function = "audio";
146 };
147
148 i2s_pins2: i2s-pins2 {
149 marvell,pins = "mpp49", "mpp47", "mpp50",
150 "mpp59", "mpp57", "mpp61",
151 "mpp62", "mpp60", "mpp58";
152 marvell,function = "audio";
153 };
135 }; 154 };
136 155
137 gpio0: gpio@18100 { 156 gpio0: gpio@18100 {
@@ -196,6 +215,20 @@
196 clocks = <&coreclk 2>; 215 clocks = <&coreclk 2>;
197 }; 216 };
198 217
218 watchdog@20300 {
219 compatible = "marvell,armada-370-wdt";
220 clocks = <&coreclk 2>;
221 };
222
223 audio_controller: audio-controller@30000 {
224 compatible = "marvell,armada370-audio";
225 reg = <0x30000 0x4000>;
226 interrupts = <93>;
227 clocks = <&gateclk 0>;
228 clock-names = "internal";
229 status = "disabled";
230 };
231
199 usb@50000 { 232 usb@50000 {
200 clocks = <&coreclk 0>; 233 clocks = <&coreclk 0>;
201 }; 234 };
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
new file mode 100644
index 000000000000..9378d3136b41
--- /dev/null
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -0,0 +1,130 @@
1/*
2 * Device Tree file for Marvell Armada 375 evaluation board
3 * (DB-88F6720)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16#include <dt-bindings/gpio/gpio.h>
17#include "armada-375.dtsi"
18
19/ {
20 model = "Marvell Armada 375 Development Board";
21 compatible = "marvell,a375-db", "marvell,armada375";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x40000000>; /* 1 GB */
30 };
31
32 soc {
33 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
34 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
35
36 internal-regs {
37 spi@10600 {
38 pinctrl-0 = <&spi0_pins>;
39 pinctrl-names = "default";
40 /*
41 * SPI conflicts with NAND, so we disable it
42 * here, and select NAND as the enabled device
43 * by default.
44 */
45 status = "disabled";
46
47 spi-flash@0 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "n25q128a13";
51 reg = <0>; /* Chip select 0 */
52 spi-max-frequency = <108000000>;
53 };
54 };
55
56 i2c@11000 {
57 status = "okay";
58 clock-frequency = <100000>;
59 pinctrl-0 = <&i2c0_pins>;
60 pinctrl-names = "default";
61 };
62
63 i2c@11100 {
64 status = "okay";
65 clock-frequency = <100000>;
66 pinctrl-0 = <&i2c1_pins>;
67 pinctrl-names = "default";
68 };
69
70 serial@12000 {
71 clock-frequency = <200000000>;
72 status = "okay";
73 };
74
75 pinctrl {
76 sdio_st_pins: sdio-st-pins {
77 marvell,pins = "mpp44", "mpp45";
78 marvell,function = "gpio";
79 };
80 };
81
82 nand: nand@d0000 {
83 pinctrl-0 = <&nand_pins>;
84 pinctrl-names = "default";
85 status = "okay";
86 num-cs = <1>;
87 marvell,nand-keep-config;
88 marvell,nand-enable-arbiter;
89 nand-on-flash-bbt;
90
91 partition@0 {
92 label = "U-Boot";
93 reg = <0 0x800000>;
94 };
95 partition@800000 {
96 label = "Linux";
97 reg = <0x800000 0x800000>;
98 };
99 partition@1000000 {
100 label = "Filesystem";
101 reg = <0x1000000 0x3f000000>;
102 };
103 };
104
105 mvsdio@d4000 {
106 pinctrl-0 = <&sdio_pins &sdio_st_pins>;
107 pinctrl-names = "default";
108 status = "okay";
109 cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
110 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
111 };
112 };
113
114 pcie-controller {
115 status = "okay";
116 /*
117 * The two PCIe units are accessible through
118 * standard PCIe slots on the board.
119 */
120 pcie@1,0 {
121 /* Port 0, Lane 0 */
122 status = "okay";
123 };
124 pcie@2,0 {
125 /* Port 1, Lane 0 */
126 status = "okay";
127 };
128 };
129 };
130};
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
new file mode 100644
index 000000000000..3877693fb2d8
--- /dev/null
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -0,0 +1,464 @@
1/*
2 * Device Tree Include file for Marvell Armada 375 family SoC
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include "skeleton.dtsi"
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/interrupt-controller/irq.h>
17
18#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
19
20/ {
21 model = "Marvell Armada 375 family SoC";
22 compatible = "marvell,armada375";
23
24 aliases {
25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 gpio2 = &gpio2;
28 };
29
30 clocks {
31 /* 2 GHz fixed main PLL */
32 mainpll: mainpll {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <2000000000>;
36 };
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42 cpu@0 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 reg = <0>;
46 };
47 cpu@1 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 reg = <1>;
51 };
52 };
53
54 soc {
55 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
56 #address-cells = <2>;
57 #size-cells = <1>;
58 controller = <&mbusc>;
59 interrupt-parent = <&gic>;
60 pcie-mem-aperture = <0xe0000000 0x8000000>;
61 pcie-io-aperture = <0xe8000000 0x100000>;
62
63 bootrom {
64 compatible = "marvell,bootrom";
65 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
66 };
67
68 devbus-bootcs {
69 compatible = "marvell,mvebu-devbus";
70 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
71 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
72 #address-cells = <1>;
73 #size-cells = <1>;
74 clocks = <&coreclk 0>;
75 status = "disabled";
76 };
77
78 devbus-cs0 {
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
82 #address-cells = <1>;
83 #size-cells = <1>;
84 clocks = <&coreclk 0>;
85 status = "disabled";
86 };
87
88 devbus-cs1 {
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 clocks = <&coreclk 0>;
95 status = "disabled";
96 };
97
98 devbus-cs2 {
99 compatible = "marvell,mvebu-devbus";
100 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
101 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104 clocks = <&coreclk 0>;
105 status = "disabled";
106 };
107
108 devbus-cs3 {
109 compatible = "marvell,mvebu-devbus";
110 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
111 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
112 #address-cells = <1>;
113 #size-cells = <1>;
114 clocks = <&coreclk 0>;
115 status = "disabled";
116 };
117
118 internal-regs {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
123
124 L2: cache-controller@8000 {
125 compatible = "arm,pl310-cache";
126 reg = <0x8000 0x1000>;
127 cache-unified;
128 cache-level = <2>;
129 };
130
131 timer@c600 {
132 compatible = "arm,cortex-a9-twd-timer";
133 reg = <0xc600 0x20>;
134 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
135 clocks = <&coreclk 2>;
136 };
137
138 gic: interrupt-controller@d000 {
139 compatible = "arm,cortex-a9-gic";
140 #interrupt-cells = <3>;
141 #size-cells = <0>;
142 interrupt-controller;
143 reg = <0xd000 0x1000>,
144 <0xc100 0x100>;
145 };
146
147 spi0: spi@10600 {
148 compatible = "marvell,orion-spi";
149 reg = <0x10600 0x50>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 cell-index = <0>;
153 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&coreclk 0>;
155 status = "disabled";
156 };
157
158 spi1: spi@10680 {
159 compatible = "marvell,orion-spi";
160 reg = <0x10680 0x50>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 cell-index = <1>;
164 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&coreclk 0>;
166 status = "disabled";
167 };
168
169 i2c0: i2c@11000 {
170 compatible = "marvell,mv64xxx-i2c";
171 reg = <0x11000 0x20>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
175 timeout-ms = <1000>;
176 clocks = <&coreclk 0>;
177 status = "disabled";
178 };
179
180 i2c1: i2c@11100 {
181 compatible = "marvell,mv64xxx-i2c";
182 reg = <0x11100 0x20>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
186 timeout-ms = <1000>;
187 clocks = <&coreclk 0>;
188 status = "disabled";
189 };
190
191 serial@12000 {
192 compatible = "snps,dw-apb-uart";
193 reg = <0x12000 0x100>;
194 reg-shift = <2>;
195 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
196 reg-io-width = <1>;
197 status = "disabled";
198 };
199
200 serial@12100 {
201 compatible = "snps,dw-apb-uart";
202 reg = <0x12100 0x100>;
203 reg-shift = <2>;
204 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
205 reg-io-width = <1>;
206 status = "disabled";
207 };
208
209 pinctrl {
210 compatible = "marvell,mv88f6720-pinctrl";
211 reg = <0x18000 0x24>;
212
213 i2c0_pins: i2c0-pins {
214 marvell,pins = "mpp14", "mpp15";
215 marvell,function = "i2c0";
216 };
217
218 i2c1_pins: i2c1-pins {
219 marvell,pins = "mpp61", "mpp62";
220 marvell,function = "i2c1";
221 };
222
223 nand_pins: nand-pins {
224 marvell,pins = "mpp0", "mpp1", "mpp2",
225 "mpp3", "mpp4", "mpp5",
226 "mpp6", "mpp7", "mpp8",
227 "mpp9", "mpp10", "mpp11",
228 "mpp12", "mpp13";
229 marvell,function = "nand";
230 };
231
232 sdio_pins: sdio-pins {
233 marvell,pins = "mpp24", "mpp25", "mpp26",
234 "mpp27", "mpp28", "mpp29";
235 marvell,function = "sd";
236 };
237
238 spi0_pins: spi0-pins {
239 marvell,pins = "mpp0", "mpp1", "mpp4",
240 "mpp5", "mpp8", "mpp9";
241 marvell,function = "spi0";
242 };
243 };
244
245 gpio0: gpio@18100 {
246 compatible = "marvell,orion-gpio";
247 reg = <0x18100 0x40>;
248 ngpios = <32>;
249 gpio-controller;
250 #gpio-cells = <2>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
257 };
258
259 gpio1: gpio@18140 {
260 compatible = "marvell,orion-gpio";
261 reg = <0x18140 0x40>;
262 ngpios = <32>;
263 gpio-controller;
264 #gpio-cells = <2>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
267 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
271 };
272
273 gpio2: gpio@18180 {
274 compatible = "marvell,orion-gpio";
275 reg = <0x18180 0x40>;
276 ngpios = <3>;
277 gpio-controller;
278 #gpio-cells = <2>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
282 };
283
284 system-controller@18200 {
285 compatible = "marvell,armada-375-system-controller";
286 reg = <0x18200 0x100>;
287 };
288
289 gateclk: clock-gating-control@18220 {
290 compatible = "marvell,armada-375-gating-clock";
291 reg = <0x18220 0x4>;
292 clocks = <&coreclk 0>;
293 #clock-cells = <1>;
294 };
295
296 mbusc: mbus-controller@20000 {
297 compatible = "marvell,mbus-controller";
298 reg = <0x20000 0x100>, <0x20180 0x20>;
299 };
300
301 mpic: interrupt-controller@20000 {
302 compatible = "marvell,mpic";
303 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
304 #interrupt-cells = <1>;
305 #size-cells = <1>;
306 interrupt-controller;
307 msi-controller;
308 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
309 };
310
311 timer@20300 {
312 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
313 reg = <0x20300 0x30>, <0x21040 0x30>;
314 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
315 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
316 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
317 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
318 <&mpic 5>,
319 <&mpic 6>;
320 clocks = <&coreclk 0>;
321 };
322
323 xor@60800 {
324 compatible = "marvell,orion-xor";
325 reg = <0x60800 0x100
326 0x60A00 0x100>;
327 clocks = <&gateclk 22>;
328 status = "okay";
329
330 xor00 {
331 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
332 dmacap,memcpy;
333 dmacap,xor;
334 };
335 xor01 {
336 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
337 dmacap,memcpy;
338 dmacap,xor;
339 dmacap,memset;
340 };
341 };
342
343 xor@60900 {
344 compatible = "marvell,orion-xor";
345 reg = <0x60900 0x100
346 0x60b00 0x100>;
347 clocks = <&gateclk 23>;
348 status = "okay";
349
350 xor10 {
351 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
352 dmacap,memcpy;
353 dmacap,xor;
354 };
355 xor11 {
356 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
357 dmacap,memcpy;
358 dmacap,xor;
359 dmacap,memset;
360 };
361 };
362
363 sata@a0000 {
364 compatible = "marvell,orion-sata";
365 reg = <0xa0000 0x5000>;
366 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&gateclk 14>, <&gateclk 20>;
368 clock-names = "0", "1";
369 status = "disabled";
370 };
371
372 nand@d0000 {
373 compatible = "marvell,armada370-nand";
374 reg = <0xd0000 0x54>;
375 #address-cells = <1>;
376 #size-cells = <1>;
377 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&gateclk 11>;
379 status = "disabled";
380 };
381
382 mvsdio@d4000 {
383 compatible = "marvell,orion-sdio";
384 reg = <0xd4000 0x200>;
385 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&gateclk 17>;
387 bus-width = <4>;
388 cap-sdio-irq;
389 cap-sd-highspeed;
390 cap-mmc-highspeed;
391 status = "disabled";
392 };
393
394 coreclk: mvebu-sar@e8204 {
395 compatible = "marvell,armada-375-core-clock";
396 reg = <0xe8204 0x04>;
397 #clock-cells = <1>;
398 };
399
400 coredivclk: corediv-clock@e8250 {
401 compatible = "marvell,armada-375-corediv-clock";
402 reg = <0xe8250 0xc>;
403 #clock-cells = <1>;
404 clocks = <&mainpll>;
405 clock-output-names = "nand";
406 };
407 };
408
409 pcie-controller {
410 compatible = "marvell,armada-370-pcie";
411 status = "disabled";
412 device_type = "pci";
413
414 #address-cells = <3>;
415 #size-cells = <2>;
416
417 msi-parent = <&mpic>;
418 bus-range = <0x00 0xff>;
419
420 ranges =
421 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
422 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
423 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
424 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
425 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
426 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
427
428 pcie@1,0 {
429 device_type = "pci";
430 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
431 reg = <0x0800 0 0 0 0>;
432 #address-cells = <3>;
433 #size-cells = <2>;
434 #interrupt-cells = <1>;
435 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
436 0x81000000 0 0 0x81000000 0x1 0 1 0>;
437 interrupt-map-mask = <0 0 0 0>;
438 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
439 marvell,pcie-port = <0>;
440 marvell,pcie-lane = <0>;
441 clocks = <&gateclk 5>;
442 status = "disabled";
443 };
444
445 pcie@2,0 {
446 device_type = "pci";
447 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
448 reg = <0x1000 0 0 0 0>;
449 #address-cells = <3>;
450 #size-cells = <2>;
451 #interrupt-cells = <1>;
452 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
453 0x81000000 0 0 0x81000000 0x2 0 1 0>;
454 interrupt-map-mask = <0 0 0 0>;
455 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
456 marvell,pcie-port = <0>;
457 marvell,pcie-lane = <1>;
458 clocks = <&gateclk 6>;
459 status = "disabled";
460 };
461
462 };
463 };
464};
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
new file mode 100644
index 000000000000..068031f0f263
--- /dev/null
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -0,0 +1,117 @@
1/*
2 * Device Tree Include file for Marvell Armada 380 SoC.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "armada-38x.dtsi"
16
17/ {
18 model = "Marvell Armada 380 family SoC";
19 compatible = "marvell,armada380", "marvell,armada38x";
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 reg = <0>;
28 };
29 };
30
31 soc {
32 internal-regs {
33 pinctrl {
34 compatible = "marvell,mv88f6810-pinctrl";
35 reg = <0x18000 0x20>;
36 };
37 };
38
39 pcie-controller {
40 compatible = "marvell,armada-370-pcie";
41 status = "disabled";
42 device_type = "pci";
43
44 #address-cells = <3>;
45 #size-cells = <2>;
46
47 msi-parent = <&mpic>;
48 bus-range = <0x00 0xff>;
49
50 ranges =
51 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
53 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
54 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
55 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
56 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
57 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
58 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
59 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
60 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
61
62 /* x1 port */
63 pcie@1,0 {
64 device_type = "pci";
65 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
66 reg = <0x0800 0 0 0 0>;
67 #address-cells = <3>;
68 #size-cells = <2>;
69 #interrupt-cells = <1>;
70 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
71 0x81000000 0 0 0x81000000 0x1 0 1 0>;
72 interrupt-map-mask = <0 0 0 0>;
73 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
74 marvell,pcie-port = <0>;
75 marvell,pcie-lane = <0>;
76 clocks = <&gateclk 8>;
77 status = "disabled";
78 };
79
80 /* x1 port */
81 pcie@2,0 {
82 device_type = "pci";
83 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
84 reg = <0x1000 0 0 0 0>;
85 #address-cells = <3>;
86 #size-cells = <2>;
87 #interrupt-cells = <1>;
88 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
89 0x81000000 0 0 0x81000000 0x2 0 1 0>;
90 interrupt-map-mask = <0 0 0 0>;
91 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
92 marvell,pcie-port = <1>;
93 marvell,pcie-lane = <0>;
94 clocks = <&gateclk 5>;
95 status = "disabled";
96 };
97
98 /* x1 port */
99 pcie@3,0 {
100 device_type = "pci";
101 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
102 reg = <0x1000 0 0 0 0>;
103 #address-cells = <3>;
104 #size-cells = <2>;
105 #interrupt-cells = <1>;
106 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
107 0x81000000 0 0 0x81000000 0x3 0 1 0>;
108 interrupt-map-mask = <0 0 0 0>;
109 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
110 marvell,pcie-port = <2>;
111 marvell,pcie-lane = <0>;
112 clocks = <&gateclk 6>;
113 status = "disabled";
114 };
115 };
116 };
117};
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
new file mode 100644
index 000000000000..6828d77696a6
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -0,0 +1,122 @@
1/*
2 * Device Tree file for Marvell Armada 385 evaluation board
3 * (DB-88F6820)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14/dts-v1/;
15#include "armada-385.dtsi"
16
17/ {
18 model = "Marvell Armada 385 Development Board";
19 compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
20
21 chosen {
22 bootargs = "console=ttyS0,115200 earlyprintk";
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x00000000 0x10000000>; /* 256 MB */
28 };
29
30 soc {
31 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
32 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
33
34 internal-regs {
35 spi@10600 {
36 status = "okay";
37
38 spi-flash@0 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 compatible = "w25q32";
42 reg = <0>; /* Chip select 0 */
43 spi-max-frequency = <108000000>;
44 };
45 };
46
47 i2c@11000 {
48 status = "okay";
49 clock-frequency = <100000>;
50 };
51
52 i2c@11100 {
53 status = "okay";
54 clock-frequency = <100000>;
55 };
56
57 serial@12000 {
58 clock-frequency = <200000000>;
59 status = "okay";
60 };
61
62 ethernet@30000 {
63 status = "okay";
64 phy = <&phy1>;
65 phy-mode = "rgmii-id";
66 };
67
68 ethernet@70000 {
69 status = "okay";
70 phy = <&phy0>;
71 phy-mode = "rgmii-id";
72 };
73
74 mdio {
75 phy0: ethernet-phy@0 {
76 reg = <0>;
77 };
78
79 phy1: ethernet-phy@1 {
80 reg = <1>;
81 };
82 };
83
84 flash@d0000 {
85 status = "okay";
86 num-cs = <1>;
87 marvell,nand-keep-config;
88 marvell,nand-enable-arbiter;
89 nand-on-flash-bbt;
90
91 partition@0 {
92 label = "U-Boot";
93 reg = <0 0x800000>;
94 };
95 partition@800000 {
96 label = "Linux";
97 reg = <0x800000 0x800000>;
98 };
99 partition@1000000 {
100 label = "Filesystem";
101 reg = <0x1000000 0x3f000000>;
102 };
103 };
104 };
105
106 pcie-controller {
107 status = "okay";
108 /*
109 * The two PCIe units are accessible through
110 * standard PCIe slots on the board.
111 */
112 pcie@1,0 {
113 /* Port 0, Lane 0 */
114 status = "okay";
115 };
116 pcie@2,0 {
117 /* Port 1, Lane 0 */
118 status = "okay";
119 };
120 };
121 };
122};
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts
new file mode 100644
index 000000000000..45250c88814b
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-rd.dts
@@ -0,0 +1,94 @@
1/*
2 * Device Tree file for Marvell Armada 385 Reference Design board
3 * (RD-88F6820-AP)
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16#include "armada-385.dtsi"
17
18/ {
19 model = "Marvell Armada 385 Reference Design";
20 compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
21
22 chosen {
23 bootargs = "console=ttyS0,115200 earlyprintk";
24 };
25
26 memory {
27 device_type = "memory";
28 reg = <0x00000000 0x10000000>; /* 256 MB */
29 };
30
31 soc {
32 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
33 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
34
35 internal-regs {
36 spi@10600 {
37 status = "okay";
38
39 spi-flash@0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "st,m25p128";
43 reg = <0>; /* Chip select 0 */
44 spi-max-frequency = <108000000>;
45 };
46 };
47
48 i2c@11000 {
49 status = "okay";
50 clock-frequency = <100000>;
51 };
52
53 serial@12000 {
54 clock-frequency = <200000000>;
55 status = "okay";
56 };
57
58 ethernet@30000 {
59 status = "okay";
60 phy = <&phy0>;
61 phy-mode = "rgmii-id";
62 };
63
64 ethernet@70000 {
65 status = "okay";
66 phy = <&phy1>;
67 phy-mode = "rgmii-id";
68 };
69
70
71 mdio {
72 phy0: ethernet-phy@0 {
73 reg = <0>;
74 };
75
76 phy1: ethernet-phy@1 {
77 reg = <1>;
78 };
79 };
80 };
81
82 pcie-controller {
83 status = "okay";
84 /*
85 * One PCIe units is accessible through
86 * standard PCIe slot on the board.
87 */
88 pcie@1,0 {
89 /* Port 0, Lane 0 */
90 status = "okay";
91 };
92 };
93 };
94};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
new file mode 100644
index 000000000000..e2919f02e1d4
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -0,0 +1,149 @@
1/*
2 * Device Tree Include file for Marvell Armada 385 SoC.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "armada-38x.dtsi"
16
17/ {
18 model = "Marvell Armada 385 family SoC";
19 compatible = "marvell,armada385", "marvell,armada38x";
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 reg = <0>;
28 };
29 cpu@1 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 reg = <1>;
33 };
34 };
35
36 soc {
37 internal-regs {
38 pinctrl {
39 compatible = "marvell,mv88f6820-pinctrl";
40 reg = <0x18000 0x20>;
41 };
42 };
43
44 pcie-controller {
45 compatible = "marvell,armada-370-pcie";
46 status = "disabled";
47 device_type = "pci";
48
49 #address-cells = <3>;
50 #size-cells = <2>;
51
52 msi-parent = <&mpic>;
53 bus-range = <0x00 0xff>;
54
55 ranges =
56 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
57 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
58 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
59 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
60 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
61 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
62 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
63 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
64 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
65 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
66 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
67 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
68
69 /*
70 * This port can be either x4 or x1. When
71 * configured in x4 by the bootloader, then
72 * pcie@4,0 is not available.
73 */
74 pcie@1,0 {
75 device_type = "pci";
76 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
77 reg = <0x0800 0 0 0 0>;
78 #address-cells = <3>;
79 #size-cells = <2>;
80 #interrupt-cells = <1>;
81 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
82 0x81000000 0 0 0x81000000 0x1 0 1 0>;
83 interrupt-map-mask = <0 0 0 0>;
84 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
85 marvell,pcie-port = <0>;
86 marvell,pcie-lane = <0>;
87 clocks = <&gateclk 8>;
88 status = "disabled";
89 };
90
91 /* x1 port */
92 pcie@2,0 {
93 device_type = "pci";
94 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
95 reg = <0x1000 0 0 0 0>;
96 #address-cells = <3>;
97 #size-cells = <2>;
98 #interrupt-cells = <1>;
99 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
100 0x81000000 0 0 0x81000000 0x2 0 1 0>;
101 interrupt-map-mask = <0 0 0 0>;
102 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
103 marvell,pcie-port = <1>;
104 marvell,pcie-lane = <0>;
105 clocks = <&gateclk 5>;
106 status = "disabled";
107 };
108
109 /* x1 port */
110 pcie@3,0 {
111 device_type = "pci";
112 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
113 reg = <0x1000 0 0 0 0>;
114 #address-cells = <3>;
115 #size-cells = <2>;
116 #interrupt-cells = <1>;
117 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
118 0x81000000 0 0 0x81000000 0x3 0 1 0>;
119 interrupt-map-mask = <0 0 0 0>;
120 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
121 marvell,pcie-port = <2>;
122 marvell,pcie-lane = <0>;
123 clocks = <&gateclk 6>;
124 status = "disabled";
125 };
126
127 /*
128 * x1 port only available when pcie@1,0 is
129 * configured as a x1 port
130 */
131 pcie@4,0 {
132 device_type = "pci";
133 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
134 reg = <0x1000 0 0 0 0>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
139 0x81000000 0 0 0x81000000 0x4 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
142 marvell,pcie-port = <3>;
143 marvell,pcie-lane = <0>;
144 clocks = <&gateclk 7>;
145 status = "disabled";
146 };
147 };
148 };
149};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
new file mode 100644
index 000000000000..a064f59da02d
--- /dev/null
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -0,0 +1,376 @@
1/*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "skeleton.dtsi"
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
20
21/ {
22 model = "Marvell Armada 38x family SoC";
23 compatible = "marvell,armada38x";
24
25 aliases {
26 gpio0 = &gpio0;
27 gpio1 = &gpio1;
28 eth0 = &eth0;
29 eth1 = &eth1;
30 eth2 = &eth2;
31 };
32
33 soc {
34 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
35 "simple-bus";
36 #address-cells = <2>;
37 #size-cells = <1>;
38 controller = <&mbusc>;
39 interrupt-parent = <&gic>;
40 pcie-mem-aperture = <0xe0000000 0x8000000>;
41 pcie-io-aperture = <0xe8000000 0x100000>;
42
43 bootrom {
44 compatible = "marvell,bootrom";
45 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
46 };
47
48 devbus-bootcs {
49 compatible = "marvell,mvebu-devbus";
50 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
51 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
52 #address-cells = <1>;
53 #size-cells = <1>;
54 clocks = <&coreclk 0>;
55 status = "disabled";
56 };
57
58 devbus-cs0 {
59 compatible = "marvell,mvebu-devbus";
60 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
61 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 clocks = <&coreclk 0>;
65 status = "disabled";
66 };
67
68 devbus-cs1 {
69 compatible = "marvell,mvebu-devbus";
70 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
71 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
72 #address-cells = <1>;
73 #size-cells = <1>;
74 clocks = <&coreclk 0>;
75 status = "disabled";
76 };
77
78 devbus-cs2 {
79 compatible = "marvell,mvebu-devbus";
80 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
81 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
82 #address-cells = <1>;
83 #size-cells = <1>;
84 clocks = <&coreclk 0>;
85 status = "disabled";
86 };
87
88 devbus-cs3 {
89 compatible = "marvell,mvebu-devbus";
90 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
91 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 clocks = <&coreclk 0>;
95 status = "disabled";
96 };
97
98 internal-regs {
99 compatible = "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
103
104 L2: cache-controller@8000 {
105 compatible = "arm,pl310-cache";
106 reg = <0x8000 0x1000>;
107 cache-unified;
108 cache-level = <2>;
109 };
110
111 timer@c600 {
112 compatible = "arm,cortex-a9-twd-timer";
113 reg = <0xc600 0x20>;
114 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
115 clocks = <&coreclk 2>;
116 };
117
118 gic: interrupt-controller@d000 {
119 compatible = "arm,cortex-a9-gic";
120 #interrupt-cells = <3>;
121 #size-cells = <0>;
122 interrupt-controller;
123 reg = <0xd000 0x1000>,
124 <0xc100 0x100>;
125 };
126
127 spi0: spi@10600 {
128 compatible = "marvell,orion-spi";
129 reg = <0x10600 0x50>;
130 #address-cells = <1>;
131 #size-cells = <0>;
132 cell-index = <0>;
133 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&coreclk 0>;
135 status = "disabled";
136 };
137
138 spi1: spi@10680 {
139 compatible = "marvell,orion-spi";
140 reg = <0x10680 0x50>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143 cell-index = <1>;
144 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&coreclk 0>;
146 status = "disabled";
147 };
148
149 i2c0: i2c@11000 {
150 compatible = "marvell,mv64xxx-i2c";
151 reg = <0x11000 0x20>;
152 #address-cells = <1>;
153 #size-cells = <0>;
154 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
155 timeout-ms = <1000>;
156 clocks = <&coreclk 0>;
157 status = "disabled";
158 };
159
160 i2c1: i2c@11100 {
161 compatible = "marvell,mv64xxx-i2c";
162 reg = <0x11100 0x20>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
166 timeout-ms = <1000>;
167 clocks = <&coreclk 0>;
168 status = "disabled";
169 };
170
171 serial@12000 {
172 compatible = "snps,dw-apb-uart";
173 reg = <0x12000 0x100>;
174 reg-shift = <2>;
175 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
176 reg-io-width = <1>;
177 status = "disabled";
178 };
179
180 serial@12100 {
181 compatible = "snps,dw-apb-uart";
182 reg = <0x12100 0x100>;
183 reg-shift = <2>;
184 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
185 reg-io-width = <1>;
186 status = "disabled";
187 };
188
189 pinctrl {
190 compatible = "marvell,mv88f6820-pinctrl";
191 reg = <0x18000 0x20>;
192 };
193
194 gpio0: gpio@18100 {
195 compatible = "marvell,orion-gpio";
196 reg = <0x18100 0x40>;
197 ngpios = <32>;
198 gpio-controller;
199 #gpio-cells = <2>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
202 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
206 };
207
208 gpio1: gpio@18140 {
209 compatible = "marvell,orion-gpio";
210 reg = <0x18140 0x40>;
211 ngpios = <28>;
212 gpio-controller;
213 #gpio-cells = <2>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
216 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
220 };
221
222 system-controller@18200 {
223 compatible = "marvell,armada-380-system-controller",
224 "marvell,armada-370-xp-system-controller";
225 reg = <0x18200 0x100>;
226 };
227
228 gateclk: clock-gating-control@18220 {
229 compatible = "marvell,armada-380-gating-clock";
230 reg = <0x18220 0x4>;
231 clocks = <&coreclk 0>;
232 #clock-cells = <1>;
233 };
234
235 coreclk: mvebu-sar@18600 {
236 compatible = "marvell,armada-380-core-clock";
237 reg = <0x18600 0x04>;
238 #clock-cells = <1>;
239 };
240
241 mbusc: mbus-controller@20000 {
242 compatible = "marvell,mbus-controller";
243 reg = <0x20000 0x100>, <0x20180 0x20>;
244 };
245
246 mpic: interrupt-controller@20000 {
247 compatible = "marvell,mpic";
248 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
249 #interrupt-cells = <1>;
250 #size-cells = <1>;
251 interrupt-controller;
252 msi-controller;
253 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
254 };
255
256 timer@20300 {
257 compatible = "marvell,armada-380-timer",
258 "marvell,armada-xp-timer";
259 reg = <0x20300 0x30>, <0x21040 0x30>;
260 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
261 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
262 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
263 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
264 <&mpic 5>,
265 <&mpic 6>;
266 clocks = <&coreclk 2>, <&refclk>;
267 clock-names = "nbclk", "fixed";
268 };
269
270 eth1: ethernet@30000 {
271 compatible = "marvell,armada-370-neta";
272 reg = <0x30000 0x4000>;
273 interrupts-extended = <&mpic 10>;
274 clocks = <&gateclk 3>;
275 status = "disabled";
276 };
277
278 eth2: ethernet@34000 {
279 compatible = "marvell,armada-370-neta";
280 reg = <0x34000 0x4000>;
281 interrupts-extended = <&mpic 12>;
282 clocks = <&gateclk 2>;
283 status = "disabled";
284 };
285
286 xor@60800 {
287 compatible = "marvell,orion-xor";
288 reg = <0x60800 0x100
289 0x60a00 0x100>;
290 clocks = <&gateclk 22>;
291 status = "okay";
292
293 xor00 {
294 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
295 dmacap,memcpy;
296 dmacap,xor;
297 };
298 xor01 {
299 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
300 dmacap,memcpy;
301 dmacap,xor;
302 dmacap,memset;
303 };
304 };
305
306 xor@60900 {
307 compatible = "marvell,orion-xor";
308 reg = <0x60900 0x100
309 0x60b00 0x100>;
310 clocks = <&gateclk 28>;
311 status = "okay";
312
313 xor10 {
314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
315 dmacap,memcpy;
316 dmacap,xor;
317 };
318 xor11 {
319 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
320 dmacap,memcpy;
321 dmacap,xor;
322 dmacap,memset;
323 };
324 };
325
326 eth0: ethernet@70000 {
327 compatible = "marvell,armada-370-neta";
328 reg = <0x70000 0x4000>;
329 interrupts-extended = <&mpic 8>;
330 clocks = <&gateclk 4>;
331 status = "disabled";
332 };
333
334 mdio {
335 #address-cells = <1>;
336 #size-cells = <0>;
337 compatible = "marvell,orion-mdio";
338 reg = <0x72004 0x4>;
339 };
340
341 coredivclk: clock@e4250 {
342 compatible = "marvell,armada-380-corediv-clock";
343 reg = <0xe4250 0xc>;
344 #clock-cells = <1>;
345 clocks = <&mainpll>;
346 clock-output-names = "nand";
347 };
348
349 flash@d0000 {
350 compatible = "marvell,armada370-nand";
351 reg = <0xd0000 0x54>;
352 #address-cells = <1>;
353 #size-cells = <1>;
354 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&coredivclk 0>;
356 status = "disabled";
357 };
358 };
359 };
360
361 clocks {
362 /* 2 GHz fixed main PLL */
363 mainpll: mainpll {
364 compatible = "fixed-clock";
365 #clock-cells = <0>;
366 clock-frequency = <2000000000>;
367 };
368
369 /* 25 MHz reference crystal */
370 refclk: oscillator {
371 compatible = "fixed-clock";
372 #clock-cells = <0>;
373 clock-frequency = <25000000>;
374 };
375 };
376};
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index c5fe57269f5a..d83d7d69ac01 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -16,6 +16,8 @@
16 */ 16 */
17 17
18/dts-v1/; 18/dts-v1/;
19#include <dt-bindings/gpio/gpio.h>
20#include <dt-bindings/input/input.h>
19#include "armada-xp-mv78230.dtsi" 21#include "armada-xp-mv78230.dtsi"
20 22
21/ { 23/ {
@@ -157,8 +159,8 @@
157 159
158 button@1 { 160 button@1 {
159 label = "Factory Reset Button"; 161 label = "Factory Reset Button";
160 linux,code = <141>; /* KEY_SETUP */ 162 linux,code = <KEY_SETUP>;
161 gpios = <&gpio1 1 1>; 163 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
162 }; 164 };
163 }; 165 };
164}; 166};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index bcf6d79a57ec..448373c4b0e5 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -2,7 +2,7 @@
2 * Device Tree file for Marvell Armada XP evaluation board 2 * Device Tree file for Marvell Armada XP evaluation board
3 * (DB-78460-BP) 3 * (DB-78460-BP)
4 * 4 *
5 * Copyright (C) 2012 Marvell 5 * Copyright (C) 2012-2014 Marvell
6 * 6 *
7 * Lior Amsalem <alior@marvell.com> 7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
@@ -11,6 +11,15 @@
11 * This file is licensed under the terms of the GNU General Public 11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any 12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 *
15 * Note: this Device Tree assumes that the bootloader has remapped the
16 * internal registers to 0xf1000000 (instead of the default
17 * 0xd0000000). The 0xf1000000 is the default used by the recent,
18 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 * boards were delivered with an older version of the bootloader that
20 * left internal registers mapped at 0xd0000000. If you are in this
21 * situation, you should either update your bootloader (preferred
22 * solution) or the below Device Tree should be adjusted.
14 */ 23 */
15 24
16/dts-v1/; 25/dts-v1/;
@@ -30,7 +39,7 @@
30 }; 39 };
31 40
32 soc { 41 soc {
33 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 42 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
34 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 43 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
35 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; 44 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
36 45
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 274e2ad5f51c..61bda687f782 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -2,7 +2,7 @@
2 * Device Tree file for Marvell Armada XP development board 2 * Device Tree file for Marvell Armada XP development board
3 * (DB-MV784MP-GP) 3 * (DB-MV784MP-GP)
4 * 4 *
5 * Copyright (C) 2013 Marvell 5 * Copyright (C) 2013-2014 Marvell
6 * 6 *
7 * Lior Amsalem <alior@marvell.com> 7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
@@ -11,6 +11,15 @@
11 * This file is licensed under the terms of the GNU General Public 11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any 12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 *
15 * Note: this Device Tree assumes that the bootloader has remapped the
16 * internal registers to 0xf1000000 (instead of the default
17 * 0xd0000000). The 0xf1000000 is the default used by the recent,
18 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 * boards were delivered with an older version of the bootloader that
20 * left internal registers mapped at 0xd0000000. If you are in this
21 * situation, you should either update your bootloader (preferred
22 * solution) or the below Device Tree should be adjusted.
14 */ 23 */
15 24
16/dts-v1/; 25/dts-v1/;
@@ -30,16 +39,17 @@
30 * 8 GB of plug-in RAM modules by default.The amount 39 * 8 GB of plug-in RAM modules by default.The amount
31 * of memory available can be changed by the 40 * of memory available can be changed by the
32 * bootloader according the size of the module 41 * bootloader according the size of the module
33 * actually plugged. Only 7GB are usable because 42 * actually plugged. However, memory between
34 * addresses from 0xC0000000 to 0xffffffff are used by 43 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
35 * the internal registers of the SoC. 44 * the address range used for I/O (internal registers,
45 * MBus windows).
36 */ 46 */
37 reg = <0x00000000 0x00000000 0x00000000 0xC0000000>, 47 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
38 <0x00000001 0x00000000 0x00000001 0x00000000>; 48 <0x00000001 0x00000000 0x00000001 0x00000000>;
39 }; 49 };
40 50
41 soc { 51 soc {
42 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 52 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
43 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 53 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
44 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; 54 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
45 55
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index e47c49ecd55c..c2242745b9b8 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -23,7 +23,12 @@
23 23
24 memory { 24 memory {
25 device_type = "memory"; 25 device_type = "memory";
26 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ 26 /*
27 * This board has 4 GB of RAM, but the last 256 MB of
28 * RAM are not usable due to the overlap with the MBus
29 * Window address range
30 */
31 reg = <0 0x00000000 0 0xf0000000>;
27 }; 32 };
28 33
29 soc { 34 soc {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 99bcf76e6953..985948ce67b3 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -11,6 +11,8 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/input/input.h>
14#include "armada-xp-mv78260.dtsi" 16#include "armada-xp-mv78260.dtsi"
15 17
16/ { 18/ {
@@ -90,19 +92,19 @@
90 92
91 red_led { 93 red_led {
92 label = "red_led"; 94 label = "red_led";
93 gpios = <&gpio1 17 1>; 95 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
94 default-state = "off"; 96 default-state = "off";
95 }; 97 };
96 98
97 yellow_led { 99 yellow_led {
98 label = "yellow_led"; 100 label = "yellow_led";
99 gpios = <&gpio1 19 1>; 101 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
100 default-state = "off"; 102 default-state = "off";
101 }; 103 };
102 104
103 green_led { 105 green_led {
104 label = "green_led"; 106 label = "green_led";
105 gpios = <&gpio1 21 1>; 107 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
106 default-state = "keep"; 108 default-state = "keep";
107 }; 109 };
108 }; 110 };
@@ -114,8 +116,8 @@
114 116
115 button@1 { 117 button@1 {
116 label = "Init Button"; 118 label = "Init Button";
117 linux,code = <116>; 119 linux,code = <KEY_POWER>;
118 gpios = <&gpio1 28 0>; 120 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
119 }; 121 };
120 }; 122 };
121 123
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index b8b84a22f0f3..abb9f9dcc525 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -111,6 +111,12 @@
111 clock-names = "nbclk", "fixed"; 111 clock-names = "nbclk", "fixed";
112 }; 112 };
113 113
114 watchdog@20300 {
115 compatible = "marvell,armada-xp-wdt";
116 clocks = <&coreclk 2>, <&refclk>;
117 clock-names = "nbclk", "fixed";
118 };
119
114 armada-370-xp-pmsu@22000 { 120 armada-370-xp-pmsu@22000 {
115 compatible = "marvell,armada-370-xp-pmsu"; 121 compatible = "marvell,armada-370-xp-pmsu";
116 reg = <0x22100 0x400>, <0x20800 0x20>; 122 reg = <0x22100 0x400>, <0x20800 0x20>;
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index cce45f5177f9..55ab6180e350 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -129,7 +129,6 @@
129 adc0: adc@f804c000 { 129 adc0: adc@f804c000 {
130 status = "okay"; 130 status = "okay";
131 atmel,adc-channels-used = <0xf>; 131 atmel,adc-channels-used = <0xf>;
132 atmel,adc-num-channels = <4>;
133 }; 132 };
134 133
135 dbgu: serial@fffff200 { 134 dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi
index 2093c4d7cd6a..df4b78695695 100644
--- a/arch/arm/boot/dts/at91-cosino.dtsi
+++ b/arch/arm/boot/dts/at91-cosino.dtsi
@@ -64,7 +64,6 @@
64 }; 64 };
65 65
66 adc0: adc@f804c000 { 66 adc0: adc@f804c000 {
67 atmel,adc-clock-rate = <1000000>;
68 atmel,adc-ts-wires = <4>; 67 atmel,adc-ts-wires = <4>;
69 atmel,adc-ts-pressure-threshold = <10000>; 68 atmel,adc-ts-pressure-threshold = <10000>;
70 status = "okay"; 69 status = "okay";
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts
index f9415dd11f17..a542d5837a17 100644
--- a/arch/arm/boot/dts/at91-cosino_mega2560.dts
+++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts
@@ -27,7 +27,6 @@
27 }; 27 };
28 28
29 adc0: adc@f804c000 { 29 adc0: adc@f804c000 {
30 atmel,adc-clock-rate = <1000000>;
31 atmel,adc-ts-wires = <4>; 30 atmel,adc-ts-wires = <4>;
32 atmel,adc-ts-pressure-threshold = <10000>; 31 atmel,adc-ts-pressure-threshold = <10000>;
33 status = "okay"; 32 status = "okay";
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 997901f7ed73..366fc2cbcd64 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -608,37 +608,38 @@
608 }; 608 };
609 609
610 adc0: adc@fffe0000 { 610 adc0: adc@fffe0000 {
611 #address-cells = <1>;
612 #size-cells = <0>;
611 compatible = "atmel,at91sam9260-adc"; 613 compatible = "atmel,at91sam9260-adc";
612 reg = <0xfffe0000 0x100>; 614 reg = <0xfffe0000 0x100>;
613 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; 615 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
614 atmel,adc-use-external-triggers; 616 atmel,adc-use-external-triggers;
615 atmel,adc-channels-used = <0xf>; 617 atmel,adc-channels-used = <0xf>;
616 atmel,adc-vref = <3300>; 618 atmel,adc-vref = <3300>;
617 atmel,adc-num-channels = <4>;
618 atmel,adc-startup-time = <15>; 619 atmel,adc-startup-time = <15>;
619 atmel,adc-channel-base = <0x30>;
620 atmel,adc-drdy-mask = <0x10000>;
621 atmel,adc-status-register = <0x1c>;
622 atmel,adc-trigger-register = <0x04>;
623 atmel,adc-res = <8 10>; 620 atmel,adc-res = <8 10>;
624 atmel,adc-res-names = "lowres", "highres"; 621 atmel,adc-res-names = "lowres", "highres";
625 atmel,adc-use-res = "highres"; 622 atmel,adc-use-res = "highres";
626 623
627 trigger@0 { 624 trigger@0 {
625 reg = <0>;
628 trigger-name = "timer-counter-0"; 626 trigger-name = "timer-counter-0";
629 trigger-value = <0x1>; 627 trigger-value = <0x1>;
630 }; 628 };
631 trigger@1 { 629 trigger@1 {
630 reg = <1>;
632 trigger-name = "timer-counter-1"; 631 trigger-name = "timer-counter-1";
633 trigger-value = <0x3>; 632 trigger-value = <0x3>;
634 }; 633 };
635 634
636 trigger@2 { 635 trigger@2 {
636 reg = <2>;
637 trigger-name = "timer-counter-2"; 637 trigger-name = "timer-counter-2";
638 trigger-value = <0x5>; 638 trigger-value = <0x5>;
639 }; 639 };
640 640
641 trigger@3 { 641 trigger@3 {
642 reg = <3>;
642 trigger-name = "external"; 643 trigger-name = "external";
643 trigger-value = <0x13>; 644 trigger-value = <0x13>;
644 trigger-external; 645 trigger-external;
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
new file mode 100644
index 000000000000..e21dda0e8986
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -0,0 +1,735 @@
1/*
2 * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
3 *
4 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
9#include "skeleton.dtsi"
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/clk/at91.h>
14
15/ {
16 model = "Atmel AT91SAM9261 family SoC";
17 compatible = "atmel,at91sam9261";
18 interrupt-parent = <&aic>;
19
20 aliases {
21 serial0 = &dbgu;
22 serial1 = &usart0;
23 serial2 = &usart1;
24 serial3 = &usart2;
25 gpio0 = &pioA;
26 gpio1 = &pioB;
27 gpio2 = &pioC;
28 tcb0 = &tcb0;
29 i2c0 = &i2c0;
30 ssc0 = &ssc0;
31 ssc1 = &ssc1;
32 };
33
34 cpus {
35 #address-cells = <0>;
36 #size-cells = <0>;
37
38 cpu {
39 compatible = "arm,arm926ej-s";
40 device_type = "cpu";
41 };
42 };
43
44 memory {
45 reg = <0x20000000 0x08000000>;
46 };
47
48 ahb {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 usb0: ohci@00500000 {
55 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
56 reg = <0x00500000 0x100000>;
57 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
58 clocks = <&usb>, <&ohci_clk>, <&hclk0>, <&uhpck>;
59 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
60 status = "disabled";
61 };
62
63 fb0: fb@0x00600000 {
64 compatible = "atmel,at91sam9261-lcdc";
65 reg = <0x00600000 0x1000>;
66 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_fb>;
69 clocks = <&lcd_clk>, <&hclk1>;
70 clock-names = "lcdc_clk", "hclk";
71 status = "disabled";
72 };
73
74 nand0: nand@40000000 {
75 compatible = "atmel,at91rm9200-nand";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 reg = <0x40000000 0x10000000>;
79 atmel,nand-addr-offset = <22>;
80 atmel,nand-cmd-offset = <21>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_nand>;
83
84 gpios = <&pioC 15 GPIO_ACTIVE_HIGH>,
85 <&pioC 14 GPIO_ACTIVE_HIGH>,
86 <0>;
87 status = "disabled";
88 };
89
90 apb {
91 compatible = "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95
96 tcb0: timer@fffa0000 {
97 compatible = "atmel,at91rm9200-tcb";
98 reg = <0xfffa0000 0x100>;
99 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
100 <18 IRQ_TYPE_LEVEL_HIGH 0>,
101 <19 IRQ_TYPE_LEVEL_HIGH 0>;
102 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
103 clock-names = "t0_clk", "t1_clk", "t2_clk";
104 };
105
106 usb1: gadget@fffa4000 {
107 compatible = "atmel,at91rm9200-udc";
108 reg = <0xfffa4000 0x4000>;
109 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
110 clocks = <&usb>, <&udc_clk>, <&udpck>;
111 clock-names = "usb_clk", "udc_clk", "udpck";
112 status = "disabled";
113 };
114
115 mmc0: mmc@fffa8000 {
116 compatible = "atmel,hsmci";
117 reg = <0xfffa8000 0x600>;
118 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
121 #address-cells = <1>;
122 #size-cells = <0>;
123 clocks = <&mci0_clk>;
124 clock-names = "mci_clk";
125 status = "disabled";
126 };
127
128 i2c0: i2c@fffac000 {
129 compatible = "atmel,at91sam9261-i2c";
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_i2c_twi>;
132 reg = <0xfffac000 0x100>;
133 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 clocks = <&twi0_clk>;
137 status = "disabled";
138 };
139
140 usart0: serial@fffb0000 {
141 compatible = "atmel,at91sam9260-usart";
142 reg = <0xfffb0000 0x200>;
143 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
144 atmel,use-dma-rx;
145 atmel,use-dma-tx;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_usart0>;
148 clocks = <&usart0_clk>;
149 clock-names = "usart";
150 status = "disabled";
151 };
152
153 usart1: serial@fffb4000 {
154 compatible = "atmel,at91sam9260-usart";
155 reg = <0xfffb4000 0x200>;
156 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
157 atmel,use-dma-rx;
158 atmel,use-dma-tx;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_usart1>;
161 clocks = <&usart1_clk>;
162 clock-names = "usart";
163 status = "disabled";
164 };
165
166 usart2: serial@fffb8000{
167 compatible = "atmel,at91sam9260-usart";
168 reg = <0xfffb8000 0x200>;
169 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
170 atmel,use-dma-rx;
171 atmel,use-dma-tx;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_usart2>;
174 clocks = <&usart2_clk>;
175 clock-names = "usart";
176 status = "disabled";
177 };
178
179 ssc0: ssc@fffbc000 {
180 compatible = "atmel,at91rm9200-ssc";
181 reg = <0xfffbc000 0x4000>;
182 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
185 status = "disabled";
186 };
187
188 ssc1: ssc@fffc0000 {
189 compatible = "atmel,at91rm9200-ssc";
190 reg = <0xfffc0000 0x4000>;
191 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
194 status = "disabled";
195 };
196
197 spi0: spi@fffc8000 {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 compatible = "atmel,at91rm9200-spi";
201 reg = <0xfffc8000 0x200>;
202 cs-gpios = <0>, <0>, <0>, <0>;
203 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_spi0>;
206 clocks = <&spi0_clk>;
207 clock-names = "spi_clk";
208 status = "disabled";
209 };
210
211 spi1: spi@fffcc000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "atmel,at91rm9200-spi";
215 reg = <0xfffcc000 0x200>;
216 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_spi1>;
219 clocks = <&spi1_clk>;
220 clock-names = "spi_clk";
221 status = "disabled";
222 };
223
224 ramc: ramc@ffffea00 {
225 compatible = "atmel,at91sam9260-sdramc";
226 reg = <0xffffea00 0x200>;
227 };
228
229 matrix: matrix@ffffee00 {
230 compatible = "atmel,at91sam9260-bus-matrix";
231 reg = <0xffffee00 0x200>;
232 };
233
234 aic: interrupt-controller@fffff000 {
235 #interrupt-cells = <3>;
236 compatible = "atmel,at91rm9200-aic";
237 interrupt-controller;
238 reg = <0xfffff000 0x200>;
239 atmel,external-irqs = <29 30 31>;
240 };
241
242 dbgu: serial@fffff200 {
243 compatible = "atmel,at91sam9260-usart";
244 reg = <0xfffff200 0x200>;
245 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_dbgu>;
248 clocks = <&mck>;
249 clock-names = "usart";
250 status = "disabled";
251 };
252
253 pinctrl@fffff400 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
257 ranges = <0xfffff400 0xfffff400 0x600>;
258
259 atmel,mux-mask =
260 /* A B */
261 <0xffffffff 0xfffffff7>, /* pioA */
262 <0xffffffff 0xfffffff4>, /* pioB */
263 <0xffffffff 0xffffff07>; /* pioC */
264
265 /* shared pinctrl settings */
266 dbgu {
267 pinctrl_dbgu: dbgu-0 {
268 atmel,pins =
269 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
270 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
271 };
272 };
273
274 usart0 {
275 pinctrl_usart0: usart0-0 {
276 atmel,pins =
277 <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
278 <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
279 };
280
281 pinctrl_usart0_rts: usart0_rts-0 {
282 atmel,pins =
283 <AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
284 };
285
286 pinctrl_usart0_cts: usart0_cts-0 {
287 atmel,pins =
288 <AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
289 };
290 };
291
292 usart1 {
293 pinctrl_usart1: usart1-0 {
294 atmel,pins =
295 <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
296 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
297 };
298
299 pinctrl_usart1_rts: usart1_rts-0 {
300 atmel,pins =
301 <AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
302 };
303
304 pinctrl_usart1_cts: usart1_cts-0 {
305 atmel,pins =
306 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
307 };
308 };
309
310 usart2 {
311 pinctrl_usart2: usart2-0 {
312 atmel,pins =
313 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
314 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
315 };
316
317 pinctrl_usart2_rts: usart2_rts-0 {
318 atmel,pins =
319 <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
320 };
321
322 pinctrl_usart2_cts: usart2_cts-0 {
323 atmel,pins =
324 <AT91_PIOA 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
325 };
326 };
327
328 nand {
329 pinctrl_nand: nand-0 {
330 atmel,pins =
331 <AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
332 <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
333 };
334 };
335
336 mmc0 {
337 pinctrl_mmc0_clk: mmc0_clk-0 {
338 atmel,pins =
339 <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
340 };
341
342 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
343 atmel,pins =
344 <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
345 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
346 };
347
348 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
349 atmel,pins =
350 <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
351 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
352 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
353 };
354 };
355
356 ssc0 {
357 pinctrl_ssc0_tx: ssc0_tx-0 {
358 atmel,pins =
359 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
360 <AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>,
361 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
362 };
363
364 pinctrl_ssc0_rx: ssc0_rx-0 {
365 atmel,pins =
366 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,
367 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
368 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
369 };
370 };
371
372 ssc1 {
373 pinctrl_ssc1_tx: ssc1_tx-0 {
374 atmel,pins =
375 <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
376 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
377 <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
378 };
379
380 pinctrl_ssc1_rx: ssc1_rx-0 {
381 atmel,pins =
382 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
383 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
384 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
385 };
386 };
387
388 spi0 {
389 pinctrl_spi0: spi0-0 {
390 atmel,pins =
391 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
392 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
393 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
394 };
395 };
396
397 spi1 {
398 pinctrl_spi1: spi1-0 {
399 atmel,pins =
400 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>,
401 <AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>,
402 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
403 };
404 };
405
406 tcb0 {
407 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
408 atmel,pins = <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
409 };
410
411 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
412 atmel,pins = <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
413 };
414
415 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
416 atmel,pins = <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
417 };
418
419 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
420 atmel,pins = <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
421 };
422
423 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
424 atmel,pins = <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
425 };
426
427 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
428 atmel,pins = <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;
429 };
430
431 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
432 atmel,pins = <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
433 };
434
435 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
436 atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
437 };
438
439 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
440 atmel,pins = <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;
441 };
442 };
443
444 i2c0 {
445 pinctrl_i2c_bitbang: i2c-0-bitbang {
446 atmel,pins =
447 <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>,
448 <AT91_PIOA 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
449 };
450 pinctrl_i2c_twi: i2c-0-twi {
451 atmel,pins =
452 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
453 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
454 };
455 };
456
457 fb {
458 pinctrl_fb: fb-0 {
459 atmel,pins =
460 <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
461 <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
462 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
463 <AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
464 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
465 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
466 <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>,
467 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
468 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
469 <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
470 <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
471 <AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
472 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
473 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
474 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE>,
475 <AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
476 <AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
477 <AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
478 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
479 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>,
480 <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
481 };
482 };
483
484 pioA: gpio@fffff400 {
485 compatible = "atmel,at91rm9200-gpio";
486 reg = <0xfffff400 0x200>;
487 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
488 #gpio-cells = <2>;
489 gpio-controller;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 clocks = <&pioA_clk>;
493 };
494
495 pioB: gpio@fffff600 {
496 compatible = "atmel,at91rm9200-gpio";
497 reg = <0xfffff600 0x200>;
498 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
499 #gpio-cells = <2>;
500 gpio-controller;
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 clocks = <&pioB_clk>;
504 };
505
506 pioC: gpio@fffff800 {
507 compatible = "atmel,at91rm9200-gpio";
508 reg = <0xfffff800 0x200>;
509 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
510 #gpio-cells = <2>;
511 gpio-controller;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 clocks = <&pioC_clk>;
515 };
516 };
517
518 pmc: pmc@fffffc00 {
519 compatible = "atmel,at91rm9200-pmc";
520 reg = <0xfffffc00 0x100>;
521 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
522 interrupt-controller;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 #interrupt-cells = <1>;
526
527 clk32k: slck {
528 compatible = "fixed-clock";
529 #clock-cells = <0>;
530 clock-frequency = <32768>;
531 };
532
533 main: mainck {
534 compatible = "atmel,at91rm9200-clk-main";
535 #clock-cells = <0>;
536 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
537 clocks = <&clk32k>;
538 };
539
540 plla: pllack {
541 compatible = "atmel,at91rm9200-clk-pll";
542 #clock-cells = <0>;
543 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
544 clocks = <&main>;
545 reg = <0>;
546 atmel,clk-input-range = <1000000 32000000>;
547 #atmel,pll-clk-output-range-cells = <4>;
548 atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
549 };
550
551 pllb: pllbck {
552 compatible = "atmel,at91rm9200-clk-pll";
553 #clock-cells = <0>;
554 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
555 clocks = <&main>;
556 reg = <1>;
557 atmel,clk-input-range = <1000000 32000000>;
558 #atmel,pll-clk-output-range-cells = <4>;
559 atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
560 };
561
562 mck: masterck {
563 compatible = "atmel,at91rm9200-clk-master";
564 #clock-cells = <0>;
565 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
566 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
567 atmel,clk-output-range = <0 94000000>;
568 atmel,clk-divisors = <1 2 4 3>;
569 };
570
571 usb: usbck {
572 compatible = "atmel,at91rm9200-clk-usb";
573 #clock-cells = <0>;
574 atmel,clk-divisors = <1 2 4 3>;
575 clocks = <&pllb>;
576 };
577
578 systemck {
579 compatible = "atmel,at91rm9200-clk-system";
580 #address-cells = <1>;
581 #size-cells = <0>;
582
583 uhpck: uhpck {
584 #clock-cells = <0>;
585 reg = <6>;
586 clocks = <&usb>;
587 };
588
589 udpck: udpck {
590 #clock-cells = <0>;
591 reg = <7>;
592 clocks = <&usb>;
593 };
594
595 hclk0: hclk0 {
596 #clock-cells = <0>;
597 reg = <16>;
598 clocks = <&mck>;
599 };
600
601 hclk1: hclk1 {
602 #clock-cells = <0>;
603 reg = <17>;
604 clocks = <&mck>;
605 };
606 };
607
608 periphck {
609 compatible = "atmel,at91rm9200-clk-peripheral";
610 #address-cells = <1>;
611 #size-cells = <0>;
612 clocks = <&mck>;
613
614 pioA_clk: pioA_clk {
615 #clock-cells = <0>;
616 reg = <2>;
617 };
618
619 pioB_clk: pioB_clk {
620 #clock-cells = <0>;
621 reg = <3>;
622 };
623
624 pioC_clk: pioC_clk {
625 #clock-cells = <0>;
626 reg = <4>;
627 };
628
629 usart0_clk: usart0_clk {
630 #clock-cells = <0>;
631 reg = <6>;
632 };
633
634 usart1_clk: usart1_clk {
635 #clock-cells = <0>;
636 reg = <7>;
637 };
638
639 usart2_clk: usart2_clk {
640 #clock-cells = <0>;
641 reg = <8>;
642 };
643
644 mci0_clk: mci0_clk {
645 #clock-cells = <0>;
646 reg = <9>;
647 };
648
649 udc_clk: udc_clk {
650 #clock-cells = <0>;
651 reg = <10>;
652 };
653
654 twi0_clk: twi0_clk {
655 reg = <11>;
656 #clock-cells = <0>;
657 };
658
659 spi0_clk: spi0_clk {
660 #clock-cells = <0>;
661 reg = <12>;
662 };
663
664 spi1_clk: spi1_clk {
665 #clock-cells = <0>;
666 reg = <13>;
667 };
668
669 tc0_clk: tc0_clk {
670 #clock-cells = <0>;
671 reg = <17>;
672 };
673
674 tc1_clk: tc1_clk {
675 #clock-cells = <0>;
676 reg = <18>;
677 };
678
679 tc2_clk: tc2_clk {
680 #clock-cells = <0>;
681 reg = <19>;
682 };
683
684 ohci_clk: ohci_clk {
685 #clock-cells = <0>;
686 reg = <20>;
687 };
688
689 lcd_clk: lcd_clk {
690 #clock-cells = <0>;
691 reg = <21>;
692 };
693 };
694 };
695
696 rstc@fffffd00 {
697 compatible = "atmel,at91sam9260-rstc";
698 reg = <0xfffffd00 0x10>;
699 };
700
701 shdwc@fffffd10 {
702 compatible = "atmel,at91sam9260-shdwc";
703 reg = <0xfffffd10 0x10>;
704 };
705
706 pit: timer@fffffd30 {
707 compatible = "atmel,at91sam9260-pit";
708 reg = <0xfffffd30 0xf>;
709 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
710 clocks = <&mck>;
711 };
712
713 watchdog@fffffd40 {
714 compatible = "atmel,at91sam9260-wdt";
715 reg = <0xfffffd40 0x10>;
716 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
717 status = "disabled";
718 };
719 };
720 };
721
722 i2c@0 {
723 compatible = "i2c-gpio";
724 pinctrl-names = "default";
725 pinctrl-0 = <&pinctrl_i2c_bitbang>;
726 gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */
727 <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */
728 i2c-gpio,sda-open-drain;
729 i2c-gpio,scl-open-drain;
730 i2c-gpio,delay-us = <2>; /* ~100 kHz */
731 #address-cells = <1>;
732 #size-cells = <0>;
733 status = "disabled";
734 };
735};
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
new file mode 100644
index 000000000000..2ce527e70c7a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -0,0 +1,211 @@
1/*
2 * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board
3 *
4 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8/dts-v1/;
9#include "at91sam9261.dtsi"
10
11/ {
12 model = "Atmel at91sam9261ek";
13 compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw";
17 };
18
19 memory {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock@0 {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <18432000>;
31 };
32 };
33
34 ahb {
35 usb0: ohci@00500000 {
36 status = "okay";
37 };
38
39 fb0: fb@0x00600000 {
40 display = <&display0>;
41 atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
42 status = "okay";
43
44 display0: display {
45 bits-per-pixel = <16>;
46 atmel,lcdcon-backlight;
47 atmel,dmacon = <0x1>;
48 atmel,lcdcon2 = <0x80008002>;
49 atmel,guard-time = <1>;
50 atmel,lcd-wiring-mode = "BRG";
51
52 display-timings {
53 native-mode = <&timing0>;
54 timing0: timing0 {
55 clock-frequency = <4965000>;
56 hactive = <240>;
57 vactive = <320>;
58 hback-porch = <1>;
59 hfront-porch = <33>;
60 vback-porch = <1>;
61 vfront-porch = <0>;
62 hsync-len = <5>;
63 vsync-len = <1>;
64 hsync-active = <1>;
65 vsync-active = <1>;
66 };
67 };
68 };
69 };
70
71 nand0: nand@40000000 {
72 nand-bus-width = <8>;
73 nand-ecc-mode = "soft";
74 nand-on-flash-bbt;
75 status = "okay";
76
77 at91bootstrap@0 {
78 label = "at91bootstrap";
79 reg = <0x0 0x40000>;
80 };
81
82 bootloader@40000 {
83 label = "bootloader";
84 reg = <0x40000 0x80000>;
85 };
86
87 bootloaderenv@c0000 {
88 label = "bootloader env";
89 reg = <0xc0000 0xc0000>;
90 };
91
92 dtb@180000 {
93 label = "device tree";
94 reg = <0x180000 0x80000>;
95 };
96
97 kernel@200000 {
98 label = "kernel";
99 reg = <0x200000 0x600000>;
100 };
101
102 rootfs@800000 {
103 label = "rootfs";
104 reg = <0x800000 0x0f800000>;
105 };
106 };
107
108 apb {
109 usb1: gadget@fffa4000 {
110 atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>;
111 status = "okay";
112 };
113
114 spi0: spi@fffc8000 {
115 cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>;
116 status = "okay";
117
118 mtd_dataflash@0 {
119 compatible = "atmel,at45", "atmel,dataflash";
120 reg = <0>;
121 spi-max-frequency = <15000000>;
122 };
123
124 tsc2046@0 {
125 reg = <2>;
126 compatible = "ti,ads7843";
127 interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>;
128 spi-max-frequency = <3000000>;
129 pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>;
130
131 ti,x-min = /bits/ 16 <150>;
132 ti,x-max = /bits/ 16 <3830>;
133 ti,y-min = /bits/ 16 <190>;
134 ti,y-max = /bits/ 16 <3830>;
135 ti,vref-delay-usecs = /bits/ 16 <450>;
136 ti,x-plate-ohms = /bits/ 16 <450>;
137 ti,y-plate-ohms = /bits/ 16 <250>;
138 ti,pressure-max = /bits/ 16 <15000>;
139 ti,debounce-rep = /bits/ 16 <0>;
140 ti,debounce-tol = /bits/ 16 <65535>;
141 ti,debounce-max = /bits/ 16 <1>;
142
143 linux,wakeup;
144 };
145 };
146
147 dbgu: serial@fffff200 {
148 status = "okay";
149 };
150
151 watchdog@fffffd40 {
152 status = "okay";
153 };
154
155 };
156 };
157
158 leds {
159 compatible = "gpio-leds";
160
161 ds8 {
162 label = "ds8";
163 gpios = <&pioA 13 GPIO_ACTIVE_LOW>;
164 linux,default-trigger = "none";
165 };
166
167 ds7 {
168 label = "ds7";
169 gpios = <&pioA 14 GPIO_ACTIVE_LOW>;
170 linux,default-trigger = "nand-disk";
171 };
172
173 ds1 {
174 label = "ds1";
175 gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
176 linux,default-trigger = "heartbeat";
177 };
178 };
179
180 gpio_keys {
181 compatible = "gpio-keys";
182
183 button_0 {
184 label = "button_0";
185 gpios = <&pioA 27 GPIO_ACTIVE_LOW>;
186 linux,code = <256>;
187 gpio-key,wakeup;
188 };
189
190 button_1 {
191 label = "button_1";
192 gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
193 linux,code = <257>;
194 gpio-key,wakeup;
195 };
196
197 button_2 {
198 label = "button_2";
199 gpios = <&pioA 25 GPIO_ACTIVE_LOW>;
200 linux,code = <258>;
201 gpio-key,wakeup;
202 };
203
204 button_3 {
205 label = "button_3";
206 gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
207 linux,code = <259>;
208 gpio-key,wakeup;
209 };
210 };
211};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index cbcc058b26b4..9cdaecff13b3 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -632,40 +632,41 @@
632 }; 632 };
633 633
634 adc0: adc@fffb0000 { 634 adc0: adc@fffb0000 {
635 #address-cells = <1>;
636 #size-cells = <0>;
635 compatible = "atmel,at91sam9260-adc"; 637 compatible = "atmel,at91sam9260-adc";
636 reg = <0xfffb0000 0x100>; 638 reg = <0xfffb0000 0x100>;
637 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 639 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
638 atmel,adc-use-external-triggers; 640 atmel,adc-use-external-triggers;
639 atmel,adc-channels-used = <0xff>; 641 atmel,adc-channels-used = <0xff>;
640 atmel,adc-vref = <3300>; 642 atmel,adc-vref = <3300>;
641 atmel,adc-num-channels = <8>;
642 atmel,adc-startup-time = <40>; 643 atmel,adc-startup-time = <40>;
643 atmel,adc-channel-base = <0x30>;
644 atmel,adc-drdy-mask = <0x10000>;
645 atmel,adc-status-register = <0x1c>;
646 atmel,adc-trigger-register = <0x08>;
647 atmel,adc-res = <8 10>; 644 atmel,adc-res = <8 10>;
648 atmel,adc-res-names = "lowres", "highres"; 645 atmel,adc-res-names = "lowres", "highres";
649 atmel,adc-use-res = "highres"; 646 atmel,adc-use-res = "highres";
650 647
651 trigger@0 { 648 trigger@0 {
649 reg = <0>;
652 trigger-name = "external-rising"; 650 trigger-name = "external-rising";
653 trigger-value = <0x1>; 651 trigger-value = <0x1>;
654 trigger-external; 652 trigger-external;
655 }; 653 };
656 trigger@1 { 654 trigger@1 {
655 reg = <1>;
657 trigger-name = "external-falling"; 656 trigger-name = "external-falling";
658 trigger-value = <0x2>; 657 trigger-value = <0x2>;
659 trigger-external; 658 trigger-external;
660 }; 659 };
661 660
662 trigger@2 { 661 trigger@2 {
662 reg = <2>;
663 trigger-name = "external-any"; 663 trigger-name = "external-any";
664 trigger-value = <0x3>; 664 trigger-value = <0x3>;
665 trigger-external; 665 trigger-external;
666 }; 666 };
667 667
668 trigger@3 { 668 trigger@3 {
669 reg = <3>;
669 trigger-name = "continuous"; 670 trigger-name = "continuous";
670 trigger-value = <0x6>; 671 trigger-value = <0x6>;
671 }; 672 };
@@ -817,6 +818,7 @@
817 >; 818 >;
818 atmel,nand-addr-offset = <21>; 819 atmel,nand-addr-offset = <21>;
819 atmel,nand-cmd-offset = <22>; 820 atmel,nand-cmd-offset = <22>;
821 atmel,nand-has-dma;
820 pinctrl-names = "default"; 822 pinctrl-names = "default";
821 pinctrl-0 = <&pinctrl_nand>; 823 pinctrl-0 = <&pinctrl_nand>;
822 gpios = <&pioC 8 GPIO_ACTIVE_HIGH 824 gpios = <&pioC 8 GPIO_ACTIVE_HIGH
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 394e6ce2afb7..9f04808fc697 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -570,6 +570,7 @@
570 atmel,pmecc-lookup-table-offset = <0x0 0x8000>; 570 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
571 atmel,nand-addr-offset = <21>; 571 atmel,nand-addr-offset = <21>;
572 atmel,nand-cmd-offset = <22>; 572 atmel,nand-cmd-offset = <22>;
573 atmel,nand-has-dma;
573 pinctrl-names = "default"; 574 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_nand>; 575 pinctrl-0 = <&pinctrl_nand>;
575 gpios = <&pioD 5 GPIO_ACTIVE_HIGH 576 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
new file mode 100644
index 000000000000..63e1784d272c
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -0,0 +1,802 @@
1/*
2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
3 *
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include "skeleton.dtsi"
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/clk/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Atmel AT91SAM9RL family SoC";
17 compatible = "atmel,at91sam9rl", "atmel,at91sam9";
18 interrupt-parent = <&aic>;
19
20 aliases {
21 serial0 = &dbgu;
22 serial1 = &usart0;
23 serial2 = &usart1;
24 serial3 = &usart2;
25 serial4 = &usart3;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 gpio3 = &pioD;
30 tcb0 = &tcb0;
31 i2c0 = &i2c0;
32 i2c1 = &i2c1;
33 ssc0 = &ssc0;
34 ssc1 = &ssc1;
35 };
36
37 cpus {
38 #address-cells = <0>;
39 #size-cells = <0>;
40
41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
44 };
45 };
46
47 memory {
48 reg = <0x20000000 0x04000000>;
49 };
50
51 ahb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 nand0: nand@40000000 {
58 compatible = "atmel,at91rm9200-nand";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x40000000 0x10000000>,
62 <0xffffe800 0x200>;
63 atmel,nand-addr-offset = <21>;
64 atmel,nand-cmd-offset = <22>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_nand>;
67 gpios = <&pioD 17 GPIO_ACTIVE_HIGH>,
68 <&pioB 6 GPIO_ACTIVE_HIGH>,
69 <0>;
70 status = "disabled";
71 };
72
73 apb {
74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78
79 tcb0: timer@fffa0000 {
80 compatible = "atmel,at91rm9200-tcb";
81 reg = <0xfffa0000 0x100>;
82 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
83 <17 IRQ_TYPE_LEVEL_HIGH 0>,
84 <18 IRQ_TYPE_LEVEL_HIGH 0>;
85 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
86 clock-names = "t0_clk", "t1_clk", "t2_clk";
87 };
88
89 mmc0: mmc@fffa4000 {
90 compatible = "atmel,hsmci";
91 reg = <0xfffa4000 0x600>;
92 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
93 #address-cells = <1>;
94 #size-cells = <0>;
95 pinctrl-names = "default";
96 clocks = <&mci0_clk>;
97 clock-names = "mci_clk";
98 status = "disabled";
99 };
100
101 i2c0: i2c@fffa8000 {
102 compatible = "atmel,at91sam9260-i2c";
103 reg = <0xfffa8000 0x100>;
104 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 clocks = <&twi0_clk>;
108 status = "disabled";
109 };
110
111 i2c1: i2c@fffac000 {
112 compatible = "atmel,at91sam9260-i2c";
113 reg = <0xfffac000 0x100>;
114 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 status = "disabled";
118 };
119
120 usart0: serial@fffb0000 {
121 compatible = "atmel,at91sam9260-usart";
122 reg = <0xfffb0000 0x200>;
123 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
124 atmel,use-dma-rx;
125 atmel,use-dma-tx;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_usart0>;
128 clocks = <&usart0_clk>;
129 clock-names = "usart";
130 status = "disabled";
131 };
132
133 usart1: serial@fffb4000 {
134 compatible = "atmel,at91sam9260-usart";
135 reg = <0xfffb4000 0x200>;
136 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
137 atmel,use-dma-rx;
138 atmel,use-dma-tx;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_usart1>;
141 clocks = <&usart1_clk>;
142 clock-names = "usart";
143 status = "disabled";
144 };
145
146 usart2: serial@fffb8000 {
147 compatible = "atmel,at91sam9260-usart";
148 reg = <0xfffb8000 0x200>;
149 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
150 atmel,use-dma-rx;
151 atmel,use-dma-tx;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_usart2>;
154 clocks = <&usart2_clk>;
155 clock-names = "usart";
156 status = "disabled";
157 };
158
159 usart3: serial@fffbc000 {
160 compatible = "atmel,at91sam9260-usart";
161 reg = <0xfffbc000 0x200>;
162 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
163 atmel,use-dma-rx;
164 atmel,use-dma-tx;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usart3>;
167 clocks = <&usart3_clk>;
168 clock-names = "usart";
169 status = "disabled";
170 };
171
172 ssc0: ssc@fffc0000 {
173 compatible = "atmel,at91rm9200-ssc";
174 reg = <0xfffc0000 0x4000>;
175 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
178 status = "disabled";
179 };
180
181 ssc1: ssc@fffc4000 {
182 compatible = "atmel,at91rm9200-ssc";
183 reg = <0xfffc4000 0x4000>;
184 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
187 status = "disabled";
188 };
189
190 spi0: spi@fffcc000 {
191 #address-cells = <1>;
192 #size-cells = <0>;
193 compatible = "atmel,at91rm9200-spi";
194 reg = <0xfffcc000 0x200>;
195 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_spi0>;
198 clocks = <&spi0_clk>;
199 clock-names = "spi_clk";
200 status = "disabled";
201 };
202
203 ramc0: ramc@ffffea00 {
204 compatible = "atmel,at91sam9260-sdramc";
205 reg = <0xffffea00 0x200>;
206 };
207
208 aic: interrupt-controller@fffff000 {
209 #interrupt-cells = <3>;
210 compatible = "atmel,at91rm9200-aic";
211 interrupt-controller;
212 reg = <0xfffff000 0x200>;
213 atmel,external-irqs = <31>;
214 };
215
216 dbgu: serial@fffff200 {
217 compatible = "atmel,at91sam9260-usart";
218 reg = <0xfffff200 0x200>;
219 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_dbgu>;
222 clocks = <&mck>;
223 clock-names = "usart";
224 status = "disabled";
225 };
226
227 pinctrl@fffff400 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
231 ranges = <0xfffff400 0xfffff400 0x800>;
232
233 atmel,mux-mask =
234 /* A B */
235 <0xffffffff 0xe05c6738>, /* pioA */
236 <0xffffffff 0x0000c780>, /* pioB */
237 <0xffffffff 0xe3ffff0e>, /* pioC */
238 <0x003fffff 0x0001ff3c>; /* pioD */
239
240 /* shared pinctrl settings */
241 dbgu {
242 pinctrl_dbgu: dbgu-0 {
243 atmel,pins =
244 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
245 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
246 };
247 };
248
249 i2c_gpio0 {
250 pinctrl_i2c_gpio0: i2c_gpio0-0 {
251 atmel,pins =
252 <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
253 <AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
254 };
255 };
256
257 i2c_gpio1 {
258 pinctrl_i2c_gpio1: i2c_gpio1-0 {
259 atmel,pins =
260 <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
261 <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
262 };
263 };
264
265 mmc0 {
266 pinctrl_mmc0_clk: mmc0_clk-0 {
267 atmel,pins =
268 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
269 };
270
271 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
272 atmel,pins =
273 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
274 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
275 };
276
277 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
278 atmel,pins =
279 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
280 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
281 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
282 };
283 };
284
285 nand {
286 pinctrl_nand: nand-0 {
287 atmel,pins =
288 <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
289 <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
290 };
291
292 pinctrl_nand0_ale_cle: nand_ale_cle-0 {
293 atmel,pins =
294 <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
295 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
296 };
297
298 pinctrl_nand0_oe_we: nand_oe_we-0 {
299 atmel,pins =
300 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE>,
301 <AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;
302 };
303
304 pinctrl_nand0_cs: nand_cs-0 {
305 atmel,pins =
306 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
307 };
308 };
309
310 ssc0 {
311 pinctrl_ssc0_tx: ssc0_tx-0 {
312 atmel,pins =
313 <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
314 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
315 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
316 };
317
318 pinctrl_ssc0_rx: ssc0_rx-0 {
319 atmel,pins =
320 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
321 <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
322 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
323 };
324 };
325
326 ssc1 {
327 pinctrl_ssc1_tx: ssc1_tx-0 {
328 atmel,pins =
329 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
330 <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
331 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
332 };
333
334 pinctrl_ssc1_rx: ssc1_rx-0 {
335 atmel,pins =
336 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE>,
337 <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
338 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
339 };
340 };
341
342 spi0 {
343 pinctrl_spi0: spi0-0 {
344 atmel,pins =
345 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
346 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
347 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
348 };
349 };
350
351 tcb0 {
352 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
353 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
354 };
355
356 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
357 atmel,pins = <AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
358 };
359
360 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
361 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
362 };
363
364 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
365 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
366 };
367
368 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
369 atmel,pins = <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
370 };
371
372 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
373 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
374 };
375
376 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
377 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
378 };
379
380 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
381 atmel,pins = <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
382 };
383
384 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
385 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
386 };
387 };
388
389 usart0 {
390 pinctrl_usart0: usart0-0 {
391 atmel,pins =
392 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
393 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
394 };
395
396 pinctrl_usart0_rts: usart0_rts-0 {
397 atmel,pins =
398 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
399 };
400
401 pinctrl_usart0_cts: usart0_cts-0 {
402 atmel,pins =
403 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
404 };
405
406 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
407 atmel,pins =
408 <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
409 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
410 };
411
412 pinctrl_usart0_dcd: usart0_dcd-0 {
413 atmel,pins =
414 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
415 };
416
417 pinctrl_usart0_ri: usart0_ri-0 {
418 atmel,pins =
419 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
420 };
421
422 pinctrl_usart0_sck: usart0_sck-0 {
423 atmel,pins =
424 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
425 };
426 };
427
428 usart1 {
429 pinctrl_usart1: usart1-0 {
430 atmel,pins =
431 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
432 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
433 };
434
435 pinctrl_usart1_rts: usart1_rts-0 {
436 atmel,pins =
437 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
438 };
439
440 pinctrl_usart1_cts: usart1_cts-0 {
441 atmel,pins =
442 <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
443 };
444
445 pinctrl_usart1_sck: usart1_sck-0 {
446 atmel,pins =
447 <AT91_PIOD 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
448 };
449 };
450
451 usart2 {
452 pinctrl_usart2: usart2-0 {
453 atmel,pins =
454 <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
455 <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
456 };
457
458 pinctrl_usart2_rts: usart2_rts-0 {
459 atmel,pins =
460 <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
461 };
462
463 pinctrl_usart2_cts: usart2_cts-0 {
464 atmel,pins =
465 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
466 };
467
468 pinctrl_usart2_sck: usart2_sck-0 {
469 atmel,pins =
470 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
471 };
472 };
473
474 usart3 {
475 pinctrl_usart3: usart3-0 {
476 atmel,pins =
477 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
478 <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
479 };
480
481 pinctrl_usart3_rts: usart3_rts-0 {
482 atmel,pins =
483 <AT91_PIOD 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
484 };
485
486 pinctrl_usart3_cts: usart3_cts-0 {
487 atmel,pins =
488 <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
489 };
490
491 pinctrl_usart3_sck: usart3_sck-0 {
492 atmel,pins =
493 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
494 };
495 };
496
497 pioA: gpio@fffff400 {
498 compatible = "atmel,at91rm9200-gpio";
499 reg = <0xfffff400 0x200>;
500 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
501 #gpio-cells = <2>;
502 gpio-controller;
503 interrupt-controller;
504 #interrupt-cells = <2>;
505 clocks = <&pioA_clk>;
506 };
507
508 pioB: gpio@fffff600 {
509 compatible = "atmel,at91rm9200-gpio";
510 reg = <0xfffff600 0x200>;
511 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
512 #gpio-cells = <2>;
513 gpio-controller;
514 interrupt-controller;
515 #interrupt-cells = <2>;
516 clocks = <&pioB_clk>;
517 };
518
519 pioC: gpio@fffff800 {
520 compatible = "atmel,at91rm9200-gpio";
521 reg = <0xfffff800 0x200>;
522 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
523 #gpio-cells = <2>;
524 gpio-controller;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 clocks = <&pioC_clk>;
528 };
529
530 pioD: gpio@fffffa00 {
531 compatible = "atmel,at91rm9200-gpio";
532 reg = <0xfffffa00 0x200>;
533 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
534 #gpio-cells = <2>;
535 gpio-controller;
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 clocks = <&pioD_clk>;
539 };
540 };
541
542 pmc: pmc@fffffc00 {
543 compatible = "atmel,at91sam9g45-pmc";
544 reg = <0xfffffc00 0x100>;
545 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
546 interrupt-controller;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #interrupt-cells = <1>;
550
551 clk32k: slck {
552 compatible = "fixed-clock";
553 #clock-cells = <0>;
554 clock-frequency = <32768>;
555 };
556
557 main: mainck {
558 compatible = "atmel,at91rm9200-clk-main";
559 #clock-cells = <0>;
560 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
561 clocks = <&clk32k>;
562 };
563
564 plla: pllack {
565 compatible = "atmel,at91rm9200-clk-pll";
566 #clock-cells = <0>;
567 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
568 clocks = <&main>;
569 reg = <0>;
570 atmel,clk-input-range = <1000000 32000000>;
571 #atmel,pll-clk-output-range-cells = <4>;
572 atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
573 };
574
575 utmi: utmick {
576 compatible = "atmel,at91sam9x5-clk-utmi";
577 #clock-cells = <0>;
578 interrupt-parent = <&pmc>;
579 interrupts = <AT91_PMC_LOCKU>;
580 clocks = <&main>;
581 };
582
583 mck: masterck {
584 compatible = "atmel,at91rm9200-clk-master";
585 #clock-cells = <0>;
586 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
587 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
588 atmel,clk-output-range = <0 94000000>;
589 atmel,clk-divisors = <1 2 4 3>;
590 };
591
592 prog: progck {
593 compatible = "atmel,at91rm9200-clk-programmable";
594 #address-cells = <1>;
595 #size-cells = <0>;
596 interrupt-parent = <&pmc>;
597 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
598
599 prog0: prog0 {
600 #clock-cells = <0>;
601 reg = <0>;
602 interrupts = <AT91_PMC_PCKRDY(0)>;
603 };
604
605 prog1: prog1 {
606 #clock-cells = <0>;
607 reg = <1>;
608 interrupts = <AT91_PMC_PCKRDY(1)>;
609 };
610 };
611
612 systemck {
613 compatible = "atmel,at91rm9200-clk-system";
614 #address-cells = <1>;
615 #size-cells = <0>;
616
617 pck0: pck0 {
618 #clock-cells = <0>;
619 reg = <8>;
620 clocks = <&prog0>;
621 };
622
623 pck1: pck1 {
624 #clock-cells = <0>;
625 reg = <9>;
626 clocks = <&prog1>;
627 };
628
629 };
630
631 periphck {
632 compatible = "atmel,at91rm9200-clk-peripheral";
633 #address-cells = <1>;
634 #size-cells = <0>;
635 clocks = <&mck>;
636
637 pioA_clk: pioA_clk {
638 #clock-cells = <0>;
639 reg = <2>;
640 };
641
642 pioB_clk: pioB_clk {
643 #clock-cells = <0>;
644 reg = <3>;
645 };
646
647 pioC_clk: pioC_clk {
648 #clock-cells = <0>;
649 reg = <4>;
650 };
651
652 pioD_clk: pioD_clk {
653 #clock-cells = <0>;
654 reg = <5>;
655 };
656
657 usart0_clk: usart0_clk {
658 #clock-cells = <0>;
659 reg = <6>;
660 };
661
662 usart1_clk: usart1_clk {
663 #clock-cells = <0>;
664 reg = <7>;
665 };
666
667 usart2_clk: usart2_clk {
668 #clock-cells = <0>;
669 reg = <8>;
670 };
671
672 usart3_clk: usart3_clk {
673 #clock-cells = <0>;
674 reg = <9>;
675 };
676
677 mci0_clk: mci0_clk {
678 #clock-cells = <0>;
679 reg = <10>;
680 };
681
682 twi0_clk: twi0_clk {
683 #clock-cells = <0>;
684 reg = <11>;
685 };
686
687 twi1_clk: twi1_clk {
688 #clock-cells = <0>;
689 reg = <12>;
690 };
691
692 spi0_clk: spi0_clk {
693 #clock-cells = <0>;
694 reg = <13>;
695 };
696
697 ssc0_clk: ssc0_clk {
698 #clock-cells = <0>;
699 reg = <14>;
700 };
701
702 ssc1_clk: ssc1_clk {
703 #clock-cells = <0>;
704 reg = <15>;
705 };
706
707 tc0_clk: tc0_clk {
708 #clock-cells = <0>;
709 reg = <16>;
710 };
711
712 tc1_clk: tc1_clk {
713 #clock-cells = <0>;
714 reg = <17>;
715 };
716
717 tc2_clk: tc2_clk {
718 #clock-cells = <0>;
719 reg = <18>;
720 };
721
722 pwm_clk: pwm_clk {
723 #clock-cells = <0>;
724 reg = <19>;
725 };
726
727 adc_clk: adc_clk {
728 #clock-cells = <0>;
729 reg = <20>;
730 };
731
732 dma0_clk: dma0_clk {
733 #clock-cells = <0>;
734 reg = <21>;
735 };
736
737 udphs_clk: udphs_clk {
738 #clock-cells = <0>;
739 reg = <22>;
740 };
741
742 lcd_clk: lcd_clk {
743 #clock-cells = <0>;
744 reg = <23>;
745 };
746 };
747 };
748
749 rstc@fffffd00 {
750 compatible = "atmel,at91sam9260-rstc";
751 reg = <0xfffffd00 0x10>;
752 };
753
754 shdwc@fffffd10 {
755 compatible = "atmel,at91sam9260-shdwc";
756 reg = <0xfffffd10 0x10>;
757 };
758
759 pit: timer@fffffd30 {
760 compatible = "atmel,at91sam9260-pit";
761 reg = <0xfffffd30 0xf>;
762 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
763 clocks = <&mck>;
764 };
765
766 watchdog@fffffd40 {
767 compatible = "atmel,at91sam9260-wdt";
768 reg = <0xfffffd40 0x10>;
769 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
770 status = "disabled";
771 };
772 };
773 };
774
775 i2c@0 {
776 compatible = "i2c-gpio";
777 gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */
778 <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */
779 i2c-gpio,sda-open-drain;
780 i2c-gpio,scl-open-drain;
781 i2c-gpio,delay-us = <2>; /* ~100 kHz */
782 #address-cells = <1>;
783 #size-cells = <0>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&pinctrl_i2c_gpio0>;
786 status = "disabled";
787 };
788
789 i2c@1 {
790 compatible = "i2c-gpio";
791 gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */
792 <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */
793 i2c-gpio,sda-open-drain;
794 i2c-gpio,scl-open-drain;
795 i2c-gpio,delay-us = <2>; /* ~100 kHz */
796 #address-cells = <1>;
797 #size-cells = <0>;
798 pinctrl-names = "default";
799 pinctrl-0 = <&pinctrl_i2c_gpio1>;
800 status = "disabled";
801 };
802};
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
new file mode 100644
index 000000000000..cddb37825fad
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -0,0 +1,157 @@
1/*
2 * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board
3 *
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 *
6 * Licensed under GPLv2 only
7 */
8/dts-v1/;
9#include "at91sam9rl.dtsi"
10
11/ {
12 model = "Atmel at91sam9rlek";
13 compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "console=ttyS0,115200 rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw";
17 };
18
19 memory {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 main_clock: clock {
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>;
31 };
32 };
33
34 ahb {
35 nand0: nand@40000000 {
36 nand-bus-width = <8>;
37 nand-ecc-mode = "soft";
38 nand-on-flash-bbt = <1>;
39 status = "okay";
40
41 at91bootstrap@0 {
42 label = "at91bootstrap";
43 reg = <0x0 0x40000>;
44 };
45
46 bootloader@40000 {
47 label = "bootloader";
48 reg = <0x40000 0x80000>;
49 };
50
51 bootloaderenv@c0000 {
52 label = "bootloader env";
53 reg = <0xc0000 0xc0000>;
54 };
55
56 dtb@180000 {
57 label = "device tree";
58 reg = <0x180000 0x80000>;
59 };
60
61 kernel@200000 {
62 label = "kernel";
63 reg = <0x200000 0x600000>;
64 };
65
66 rootfs@800000 {
67 label = "rootfs";
68 reg = <0x800000 0x0f800000>;
69 };
70 };
71
72 apb {
73 mmc0: mmc@fffa4000 {
74 pinctrl-0 = <
75 &pinctrl_board_mmc0
76 &pinctrl_mmc0_clk
77 &pinctrl_mmc0_slot0_cmd_dat0
78 &pinctrl_mmc0_slot0_dat1_3>;
79 status = "okay";
80 slot@0 {
81 reg = <0>;
82 bus-width = <4>;
83 cd-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
84 };
85 };
86
87 usart0: serial@fffb0000 {
88 pinctrl-0 = <
89 &pinctrl_usart0
90 &pinctrl_usart0_rts
91 &pinctrl_usart0_cts>;
92 status = "okay";
93 };
94
95 dbgu: serial@fffff200 {
96 status = "okay";
97 };
98
99 pinctrl@fffff400 {
100 mmc0 {
101 pinctrl_board_mmc0: mmc0-board {
102 atmel,pins =
103 <AT91_PIOA 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
104 };
105 };
106 };
107
108 pmc: pmc@fffffc00 {
109 main: mainck {
110 clock-frequency = <12000000>;
111 };
112 };
113
114 watchdog@fffffd40 {
115 status = "okay";
116 };
117 };
118 };
119
120 leds {
121 compatible = "gpio-leds";
122
123 ds1 {
124 label = "ds1";
125 gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
126 };
127
128 ds2 {
129 label = "ds2";
130 gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
131 };
132
133 ds3 {
134 label = "ds3";
135 gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
136 linux,default-trigger = "heartbeat";
137 };
138 };
139
140 gpio_keys {
141 compatible = "gpio-keys";
142
143 right_click {
144 label = "right_click";
145 gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
146 linux,code = <273>;
147 gpio-key,wakeup;
148 };
149
150 left_click {
151 label = "left_click";
152 gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
153 linux,code = <272>;
154 gpio-key,wakeup;
155 };
156 };
157};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 174219de92fa..fc13c9240da8 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -621,41 +621,42 @@
621 }; 621 };
622 622
623 adc0: adc@f804c000 { 623 adc0: adc@f804c000 {
624 #address-cells = <1>;
625 #size-cells = <0>;
624 compatible = "atmel,at91sam9260-adc"; 626 compatible = "atmel,at91sam9260-adc";
625 reg = <0xf804c000 0x100>; 627 reg = <0xf804c000 0x100>;
626 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; 628 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
627 atmel,adc-use-external; 629 atmel,adc-use-external-triggers;
628 atmel,adc-channels-used = <0xffff>; 630 atmel,adc-channels-used = <0xffff>;
629 atmel,adc-vref = <3300>; 631 atmel,adc-vref = <3300>;
630 atmel,adc-num-channels = <12>;
631 atmel,adc-startup-time = <40>; 632 atmel,adc-startup-time = <40>;
632 atmel,adc-channel-base = <0x50>;
633 atmel,adc-drdy-mask = <0x1000000>;
634 atmel,adc-status-register = <0x30>;
635 atmel,adc-trigger-register = <0xc0>;
636 atmel,adc-res = <8 10>; 633 atmel,adc-res = <8 10>;
637 atmel,adc-res-names = "lowres", "highres"; 634 atmel,adc-res-names = "lowres", "highres";
638 atmel,adc-use-res = "highres"; 635 atmel,adc-use-res = "highres";
639 636
640 trigger@0 { 637 trigger@0 {
638 reg = <0>;
641 trigger-name = "external-rising"; 639 trigger-name = "external-rising";
642 trigger-value = <0x1>; 640 trigger-value = <0x1>;
643 trigger-external; 641 trigger-external;
644 }; 642 };
645 643
646 trigger@1 { 644 trigger@1 {
645 reg = <1>;
647 trigger-name = "external-falling"; 646 trigger-name = "external-falling";
648 trigger-value = <0x2>; 647 trigger-value = <0x2>;
649 trigger-external; 648 trigger-external;
650 }; 649 };
651 650
652 trigger@2 { 651 trigger@2 {
652 reg = <2>;
653 trigger-name = "external-any"; 653 trigger-name = "external-any";
654 trigger-value = <0x3>; 654 trigger-value = <0x3>;
655 trigger-external; 655 trigger-external;
656 }; 656 };
657 657
658 trigger@3 { 658 trigger@3 {
659 reg = <3>;
659 trigger-name = "continuous"; 660 trigger-name = "continuous";
660 trigger-value = <0x6>; 661 trigger-value = <0x6>;
661 }; 662 };
@@ -790,6 +791,7 @@
790 atmel,pmecc-lookup-table-offset = <0x0 0x8000>; 791 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
791 atmel,nand-addr-offset = <21>; 792 atmel,nand-addr-offset = <21>;
792 atmel,nand-cmd-offset = <22>; 793 atmel,nand-cmd-offset = <22>;
794 atmel,nand-has-dma;
793 pinctrl-names = "default"; 795 pinctrl-names = "default";
794 pinctrl-0 = <&pinctrl_nand>; 796 pinctrl-0 = <&pinctrl_nand>;
795 gpios = <&pioD 5 GPIO_ACTIVE_HIGH 797 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index f8674bcc4489..9d72674049d6 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -65,9 +65,10 @@
65 #clock-cells = <1>; 65 #clock-cells = <1>;
66 }; 66 };
67 67
68 reset-controller@88010000 { 68 rstc: reset-controller@88010000 {
69 compatible = "sirf,prima2-rstc"; 69 compatible = "sirf,prima2-rstc";
70 reg = <0x88010000 0x1000>; 70 reg = <0x88010000 0x1000>;
71 #reset-cells = <1>;
71 }; 72 };
72 73
73 rsc-controller@88020000 { 74 rsc-controller@88020000 {
@@ -217,8 +218,8 @@
217 interrupts = <17>; 218 interrupts = <17>;
218 fifosize = <128>; 219 fifosize = <128>;
219 clocks = <&clks 13>; 220 clocks = <&clks 13>;
220 sirf,uart-dma-rx-channel = <21>; 221 dmas = <&dmac1 5>, <&dmac0 2>;
221 sirf,uart-dma-tx-channel = <2>; 222 dma-names = "rx", "tx";
222 }; 223 };
223 224
224 uart1: uart@b0060000 { 225 uart1: uart@b0060000 {
@@ -228,6 +229,7 @@
228 interrupts = <18>; 229 interrupts = <18>;
229 fifosize = <32>; 230 fifosize = <32>;
230 clocks = <&clks 14>; 231 clocks = <&clks 14>;
232 dma-names = "no-rx", "no-tx";
231 }; 233 };
232 234
233 uart2: uart@b0070000 { 235 uart2: uart@b0070000 {
@@ -237,8 +239,8 @@
237 interrupts = <19>; 239 interrupts = <19>;
238 fifosize = <128>; 240 fifosize = <128>;
239 clocks = <&clks 15>; 241 clocks = <&clks 15>;
240 sirf,uart-dma-rx-channel = <6>; 242 dmas = <&dmac0 6>, <&dmac0 7>;
241 sirf,uart-dma-tx-channel = <7>; 243 dma-names = "rx", "tx";
242 }; 244 };
243 245
244 usp0: usp@b0080000 { 246 usp0: usp@b0080000 {
@@ -248,8 +250,8 @@
248 interrupts = <20>; 250 interrupts = <20>;
249 fifosize = <128>; 251 fifosize = <128>;
250 clocks = <&clks 28>; 252 clocks = <&clks 28>;
251 sirf,usp-dma-rx-channel = <17>; 253 dmas = <&dmac1 1>, <&dmac1 2>;
252 sirf,usp-dma-tx-channel = <18>; 254 dma-names = "rx", "tx";
253 }; 255 };
254 256
255 usp1: usp@b0090000 { 257 usp1: usp@b0090000 {
@@ -259,8 +261,8 @@
259 interrupts = <21>; 261 interrupts = <21>;
260 fifosize = <128>; 262 fifosize = <128>;
261 clocks = <&clks 29>; 263 clocks = <&clks 29>;
262 sirf,usp-dma-rx-channel = <14>; 264 dmas = <&dmac0 14>, <&dmac0 15>;
263 sirf,usp-dma-tx-channel = <15>; 265 dma-names = "rx", "tx";
264 }; 266 };
265 267
266 dmac0: dma-controller@b00b0000 { 268 dmac0: dma-controller@b00b0000 {
@@ -269,6 +271,7 @@
269 reg = <0xb00b0000 0x10000>; 271 reg = <0xb00b0000 0x10000>;
270 interrupts = <12>; 272 interrupts = <12>;
271 clocks = <&clks 24>; 273 clocks = <&clks 24>;
274 #dma-cells = <1>;
272 }; 275 };
273 276
274 dmac1: dma-controller@b0160000 { 277 dmac1: dma-controller@b0160000 {
@@ -277,6 +280,7 @@
277 reg = <0xb0160000 0x10000>; 280 reg = <0xb0160000 0x10000>;
278 interrupts = <13>; 281 interrupts = <13>;
279 clocks = <&clks 25>; 282 clocks = <&clks 25>;
283 #dma-cells = <1>;
280 }; 284 };
281 285
282 vip@b00C0000 { 286 vip@b00C0000 {
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 792fde1b7f75..64d069bcc409 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -14,6 +14,8 @@
14#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
16 16
17#include "dt-bindings/clock/bcm281xx.h"
18
17#include "skeleton.dtsi" 19#include "skeleton.dtsi"
18 20
19/ { 21/ {
@@ -43,7 +45,7 @@
43 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 45 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
44 status = "disabled"; 46 status = "disabled";
45 reg = <0x3e000000 0x1000>; 47 reg = <0x3e000000 0x1000>;
46 clocks = <&uartb_clk>; 48 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
47 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 49 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
48 reg-shift = <2>; 50 reg-shift = <2>;
49 reg-io-width = <4>; 51 reg-io-width = <4>;
@@ -53,7 +55,7 @@
53 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 55 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
54 status = "disabled"; 56 status = "disabled";
55 reg = <0x3e001000 0x1000>; 57 reg = <0x3e001000 0x1000>;
56 clocks = <&uartb2_clk>; 58 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
57 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 59 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
58 reg-shift = <2>; 60 reg-shift = <2>;
59 reg-io-width = <4>; 61 reg-io-width = <4>;
@@ -63,7 +65,7 @@
63 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 65 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
64 status = "disabled"; 66 status = "disabled";
65 reg = <0x3e002000 0x1000>; 67 reg = <0x3e002000 0x1000>;
66 clocks = <&uartb3_clk>; 68 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
67 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 69 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
68 reg-shift = <2>; 70 reg-shift = <2>;
69 reg-io-width = <4>; 71 reg-io-width = <4>;
@@ -73,7 +75,7 @@
73 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 75 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
74 status = "disabled"; 76 status = "disabled";
75 reg = <0x3e003000 0x1000>; 77 reg = <0x3e003000 0x1000>;
76 clocks = <&uartb4_clk>; 78 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
77 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 79 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
78 reg-shift = <2>; 80 reg-shift = <2>;
79 reg-io-width = <4>; 81 reg-io-width = <4>;
@@ -95,7 +97,7 @@
95 compatible = "brcm,kona-timer"; 97 compatible = "brcm,kona-timer";
96 reg = <0x35006000 0x1000>; 98 reg = <0x35006000 0x1000>;
97 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 99 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&hub_timer_clk>; 100 clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
99 }; 101 };
100 102
101 gpio: gpio@35003000 { 103 gpio: gpio@35003000 {
@@ -118,7 +120,7 @@
118 compatible = "brcm,kona-sdhci"; 120 compatible = "brcm,kona-sdhci";
119 reg = <0x3f180000 0x10000>; 121 reg = <0x3f180000 0x10000>;
120 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 122 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&sdio1_clk>; 123 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
122 status = "disabled"; 124 status = "disabled";
123 }; 125 };
124 126
@@ -126,7 +128,7 @@
126 compatible = "brcm,kona-sdhci"; 128 compatible = "brcm,kona-sdhci";
127 reg = <0x3f190000 0x10000>; 129 reg = <0x3f190000 0x10000>;
128 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&sdio2_clk>; 131 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
130 status = "disabled"; 132 status = "disabled";
131 }; 133 };
132 134
@@ -134,7 +136,7 @@
134 compatible = "brcm,kona-sdhci"; 136 compatible = "brcm,kona-sdhci";
135 reg = <0x3f1a0000 0x10000>; 137 reg = <0x3f1a0000 0x10000>;
136 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 138 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&sdio3_clk>; 139 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
138 status = "disabled"; 140 status = "disabled";
139 }; 141 };
140 142
@@ -142,7 +144,7 @@
142 compatible = "brcm,kona-sdhci"; 144 compatible = "brcm,kona-sdhci";
143 reg = <0x3f1b0000 0x10000>; 145 reg = <0x3f1b0000 0x10000>;
144 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 146 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&sdio4_clk>; 147 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
146 status = "disabled"; 148 status = "disabled";
147 }; 149 };
148 150
@@ -157,7 +159,7 @@
157 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 159 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
158 #address-cells = <1>; 160 #address-cells = <1>;
159 #size-cells = <0>; 161 #size-cells = <0>;
160 clocks = <&bsc1_clk>; 162 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
161 status = "disabled"; 163 status = "disabled";
162 }; 164 };
163 165
@@ -167,7 +169,7 @@
167 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 169 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
168 #address-cells = <1>; 170 #address-cells = <1>;
169 #size-cells = <0>; 171 #size-cells = <0>;
170 clocks = <&bsc2_clk>; 172 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>;
171 status = "disabled"; 173 status = "disabled";
172 }; 174 };
173 175
@@ -177,7 +179,7 @@
177 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 179 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
178 #address-cells = <1>; 180 #address-cells = <1>;
179 #size-cells = <0>; 181 #size-cells = <0>;
180 clocks = <&bsc3_clk>; 182 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>;
181 status = "disabled"; 183 status = "disabled";
182 }; 184 };
183 185
@@ -187,105 +189,191 @@
187 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 189 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
188 #address-cells = <1>; 190 #address-cells = <1>;
189 #size-cells = <0>; 191 #size-cells = <0>;
190 clocks = <&pmu_bsc_clk>; 192 clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>;
191 status = "disabled"; 193 status = "disabled";
192 }; 194 };
193 195
194 clocks { 196 clocks {
195 bsc1_clk: bsc1 { 197 #address-cells = <1>;
196 compatible = "fixed-clock"; 198 #size-cells = <1>;
197 clock-frequency = <13000000>; 199 ranges;
200
201 root_ccu: root_ccu {
202 compatible = "brcm,bcm11351-root-ccu";
203 reg = <0x35001000 0x0f00>;
204 #clock-cells = <1>;
205 clock-output-names = "frac_1m";
206 };
207
208 hub_ccu: hub_ccu {
209 compatible = "brcm,bcm11351-hub-ccu";
210 reg = <0x34000000 0x0f00>;
211 #clock-cells = <1>;
212 clock-output-names = "tmon_1m";
213 };
214
215 aon_ccu: aon_ccu {
216 compatible = "brcm,bcm11351-aon-ccu";
217 reg = <0x35002000 0x0f00>;
218 #clock-cells = <1>;
219 clock-output-names = "hub_timer",
220 "pmu_bsc",
221 "pmu_bsc_var";
222 };
223
224 master_ccu: master_ccu {
225 compatible = "brcm,bcm11351-master-ccu";
226 reg = <0x3f001000 0x0f00>;
227 #clock-cells = <1>;
228 clock-output-names = "sdio1",
229 "sdio2",
230 "sdio3",
231 "sdio4",
232 "usb_ic",
233 "hsic2_48m",
234 "hsic2_12m";
235 };
236
237 slave_ccu: slave_ccu {
238 compatible = "brcm,bcm11351-slave-ccu";
239 reg = <0x3e011000 0x0f00>;
240 #clock-cells = <1>;
241 clock-output-names = "uartb",
242 "uartb2",
243 "uartb3",
244 "uartb4",
245 "ssp0",
246 "ssp2",
247 "bsc1",
248 "bsc2",
249 "bsc3",
250 "pwm";
251 };
252
253 ref_1m_clk: ref_1m {
198 #clock-cells = <0>; 254 #clock-cells = <0>;
255 compatible = "fixed-clock";
256 clock-frequency = <1000000>;
199 }; 257 };
200 258
201 bsc2_clk: bsc2 { 259 ref_32k_clk: ref_32k {
260 #clock-cells = <0>;
202 compatible = "fixed-clock"; 261 compatible = "fixed-clock";
203 clock-frequency = <13000000>; 262 clock-frequency = <32768>;
263 };
264
265 bbl_32k_clk: bbl_32k {
204 #clock-cells = <0>; 266 #clock-cells = <0>;
267 compatible = "fixed-clock";
268 clock-frequency = <32768>;
205 }; 269 };
206 270
207 bsc3_clk: bsc3 { 271 ref_13m_clk: ref_13m {
272 #clock-cells = <0>;
208 compatible = "fixed-clock"; 273 compatible = "fixed-clock";
209 clock-frequency = <13000000>; 274 clock-frequency = <13000000>;
210 #clock-cells = <0>;
211 }; 275 };
212 276
213 pmu_bsc_clk: pmu_bsc { 277 var_13m_clk: var_13m {
278 #clock-cells = <0>;
214 compatible = "fixed-clock"; 279 compatible = "fixed-clock";
215 clock-frequency = <13000000>; 280 clock-frequency = <13000000>;
216 #clock-cells = <0>;
217 }; 281 };
218 282
219 hub_timer_clk: hub_timer { 283 dft_19_5m_clk: dft_19_5m {
220 compatible = "fixed-clock";
221 clock-frequency = <32768>;
222 #clock-cells = <0>; 284 #clock-cells = <0>;
285 compatible = "fixed-clock";
286 clock-frequency = <19500000>;
223 }; 287 };
224 288
225 pwm_clk: pwm { 289 ref_crystal_clk: ref_crystal {
290 #clock-cells = <0>;
226 compatible = "fixed-clock"; 291 compatible = "fixed-clock";
227 clock-frequency = <26000000>; 292 clock-frequency = <26000000>;
228 #clock-cells = <0>;
229 }; 293 };
230 294
231 sdio1_clk: sdio1 { 295 ref_cx40_clk: ref_cx40 {
232 compatible = "fixed-clock";
233 clock-frequency = <48000000>;
234 #clock-cells = <0>; 296 #clock-cells = <0>;
297 compatible = "fixed-clock";
298 clock-frequency = <40000000>;
235 }; 299 };
236 300
237 sdio2_clk: sdio2 { 301 ref_52m_clk: ref_52m {
238 compatible = "fixed-clock";
239 clock-frequency = <48000000>;
240 #clock-cells = <0>; 302 #clock-cells = <0>;
303 compatible = "fixed-clock";
304 clock-frequency = <52000000>;
241 }; 305 };
242 306
243 sdio3_clk: sdio3 { 307 var_52m_clk: var_52m {
244 compatible = "fixed-clock";
245 clock-frequency = <48000000>;
246 #clock-cells = <0>; 308 #clock-cells = <0>;
309 compatible = "fixed-clock";
310 clock-frequency = <52000000>;
247 }; 311 };
248 312
249 sdio4_clk: sdio4 { 313 usb_otg_ahb_clk: usb_otg_ahb {
250 compatible = "fixed-clock"; 314 compatible = "fixed-clock";
251 clock-frequency = <48000000>; 315 clock-frequency = <52000000>;
252 #clock-cells = <0>; 316 #clock-cells = <0>;
253 }; 317 };
254 318
255 tmon_1m_clk: tmon_1m { 319 ref_96m_clk: ref_96m {
256 compatible = "fixed-clock";
257 clock-frequency = <1000000>;
258 #clock-cells = <0>; 320 #clock-cells = <0>;
321 compatible = "fixed-clock";
322 clock-frequency = <96000000>;
259 }; 323 };
260 324
261 uartb_clk: uartb { 325 var_96m_clk: var_96m {
262 compatible = "fixed-clock";
263 clock-frequency = <13000000>;
264 #clock-cells = <0>; 326 #clock-cells = <0>;
327 compatible = "fixed-clock";
328 clock-frequency = <96000000>;
265 }; 329 };
266 330
267 uartb2_clk: uartb2 { 331 ref_104m_clk: ref_104m {
332 #clock-cells = <0>;
268 compatible = "fixed-clock"; 333 compatible = "fixed-clock";
269 clock-frequency = <13000000>; 334 clock-frequency = <104000000>;
335 };
336
337 var_104m_clk: var_104m {
270 #clock-cells = <0>; 338 #clock-cells = <0>;
339 compatible = "fixed-clock";
340 clock-frequency = <104000000>;
271 }; 341 };
272 342
273 uartb3_clk: uartb3 { 343 ref_156m_clk: ref_156m {
344 #clock-cells = <0>;
274 compatible = "fixed-clock"; 345 compatible = "fixed-clock";
275 clock-frequency = <13000000>; 346 clock-frequency = <156000000>;
347 };
348
349 var_156m_clk: var_156m {
276 #clock-cells = <0>; 350 #clock-cells = <0>;
351 compatible = "fixed-clock";
352 clock-frequency = <156000000>;
277 }; 353 };
278 354
279 uartb4_clk: uartb4 { 355 ref_208m_clk: ref_208m {
356 #clock-cells = <0>;
280 compatible = "fixed-clock"; 357 compatible = "fixed-clock";
281 clock-frequency = <13000000>; 358 clock-frequency = <208000000>;
359 };
360
361 var_208m_clk: var_208m {
282 #clock-cells = <0>; 362 #clock-cells = <0>;
363 compatible = "fixed-clock";
364 clock-frequency = <208000000>;
283 }; 365 };
284 366
285 usb_otg_ahb_clk: usb_otg_ahb { 367 ref_312m_clk: ref_312m {
368 #clock-cells = <0>;
286 compatible = "fixed-clock"; 369 compatible = "fixed-clock";
287 clock-frequency = <52000000>; 370 clock-frequency = <312000000>;
371 };
372
373 var_312m_clk: var_312m {
288 #clock-cells = <0>; 374 #clock-cells = <0>;
375 compatible = "fixed-clock";
376 clock-frequency = <312000000>;
289 }; 377 };
290 }; 378 };
291 379
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm21664-garnet.dts
index 396b70459cdc..e87cb26ddf84 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm21664-garnet.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2012 Broadcom Corporation 2 * Copyright (C) 2014 Broadcom Corporation
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as 5 * modify it under the terms of the GNU General Public License as
@@ -13,11 +13,13 @@
13 13
14/dts-v1/; 14/dts-v1/;
15 15
16#include "bcm11351.dtsi" 16#include <dt-bindings/gpio/gpio.h>
17
18#include "bcm21664.dtsi"
17 19
18/ { 20/ {
19 model = "BCM11351 BRT board"; 21 model = "BCM21664 Garnet board";
20 compatible = "brcm,bcm11351-brt", "brcm,bcm11351"; 22 compatible = "brcm,bcm21664-garnet", "brcm,bcm21664";
21 23
22 memory { 24 memory {
23 reg = <0x80000000 0x40000000>; /* 1 GB */ 25 reg = <0x80000000 0x40000000>; /* 1 GB */
@@ -40,7 +42,7 @@
40 42
41 sdio4: sdio@3f1b0000 { 43 sdio4: sdio@3f1b0000 {
42 max-frequency = <48000000>; 44 max-frequency = <48000000>;
43 cd-gpios = <&gpio 14 0>; 45 cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>;
44 status = "okay"; 46 status = "okay";
45 }; 47 };
46 48
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
new file mode 100644
index 000000000000..08a44d41b672
--- /dev/null
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -0,0 +1,292 @@
1/*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
17#include "skeleton.dtsi"
18
19/ {
20 model = "BCM21664 SoC";
21 compatible = "brcm,bcm21664";
22 interrupt-parent = <&gic>;
23
24 chosen {
25 bootargs = "console=ttyS0,115200n8";
26 };
27
28 gic: interrupt-controller@3ff00100 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
31 #address-cells = <0>;
32 interrupt-controller;
33 reg = <0x3ff01000 0x1000>,
34 <0x3ff00100 0x100>;
35 };
36
37 smc@0x3404e000 {
38 compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
39 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
40 };
41
42 uart@3e000000 {
43 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
44 status = "disabled";
45 reg = <0x3e000000 0x118>;
46 clocks = <&uartb_clk>;
47 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
48 reg-shift = <2>;
49 reg-io-width = <4>;
50 };
51
52 uart@3e001000 {
53 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
54 status = "disabled";
55 reg = <0x3e001000 0x118>;
56 clocks = <&uartb2_clk>;
57 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
58 reg-shift = <2>;
59 reg-io-width = <4>;
60 };
61
62 uart@3e002000 {
63 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
64 status = "disabled";
65 reg = <0x3e002000 0x118>;
66 clocks = <&uartb3_clk>;
67 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
68 reg-shift = <2>;
69 reg-io-width = <4>;
70 };
71
72 L2: l2-cache {
73 compatible = "arm,pl310-cache";
74 reg = <0x3ff20000 0x1000>;
75 cache-unified;
76 cache-level = <2>;
77 };
78
79 brcm,resetmgr@35001f00 {
80 compatible = "brcm,bcm21664-resetmgr";
81 reg = <0x35001f00 0x24>;
82 };
83
84 timer@35006000 {
85 compatible = "brcm,kona-timer";
86 reg = <0x35006000 0x1c>;
87 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
88 clocks = <&hub_timer_clk>;
89 };
90
91 gpio: gpio@35003000 {
92 compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
93 reg = <0x35003000 0x524>;
94 interrupts =
95 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
99 #gpio-cells = <2>;
100 #interrupt-cells = <2>;
101 gpio-controller;
102 interrupt-controller;
103 };
104
105 sdio1: sdio@3f180000 {
106 compatible = "brcm,kona-sdhci";
107 reg = <0x3f180000 0x801c>;
108 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&sdio1_clk>;
110 status = "disabled";
111 };
112
113 sdio2: sdio@3f190000 {
114 compatible = "brcm,kona-sdhci";
115 reg = <0x3f190000 0x801c>;
116 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&sdio2_clk>;
118 status = "disabled";
119 };
120
121 sdio3: sdio@3f1a0000 {
122 compatible = "brcm,kona-sdhci";
123 reg = <0x3f1a0000 0x801c>;
124 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&sdio3_clk>;
126 status = "disabled";
127 };
128
129 sdio4: sdio@3f1b0000 {
130 compatible = "brcm,kona-sdhci";
131 reg = <0x3f1b0000 0x801c>;
132 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&sdio4_clk>;
134 status = "disabled";
135 };
136
137 i2c@3e016000 {
138 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
139 reg = <0x3e016000 0x70>;
140 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143 clocks = <&bsc1_clk>;
144 status = "disabled";
145 };
146
147 i2c@3e017000 {
148 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
149 reg = <0x3e017000 0x70>;
150 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 clocks = <&bsc2_clk>;
154 status = "disabled";
155 };
156
157 i2c@3e018000 {
158 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
159 reg = <0x3e018000 0x70>;
160 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 clocks = <&bsc3_clk>;
164 status = "disabled";
165 };
166
167 i2c@3e01c000 {
168 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
169 reg = <0x3e01c000 0x70>;
170 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 clocks = <&bsc4_clk>;
174 status = "disabled";
175 };
176
177 clocks {
178 bsc1_clk: bsc1 {
179 compatible = "fixed-clock";
180 clock-frequency = <13000000>;
181 #clock-cells = <0>;
182 };
183
184 bsc2_clk: bsc2 {
185 compatible = "fixed-clock";
186 clock-frequency = <13000000>;
187 #clock-cells = <0>;
188 };
189
190 bsc3_clk: bsc3 {
191 compatible = "fixed-clock";
192 clock-frequency = <13000000>;
193 #clock-cells = <0>;
194 };
195
196 bsc4_clk: bsc4 {
197 compatible = "fixed-clock";
198 clock-frequency = <13000000>;
199 #clock-cells = <0>;
200 };
201
202 pmu_bsc_clk: pmu_bsc {
203 compatible = "fixed-clock";
204 clock-frequency = <13000000>;
205 #clock-cells = <0>;
206 };
207
208 hub_timer_clk: hub_timer {
209 compatible = "fixed-clock";
210 clock-frequency = <32768>;
211 #clock-cells = <0>;
212 };
213
214 pwm_clk: pwm {
215 compatible = "fixed-clock";
216 clock-frequency = <26000000>;
217 #clock-cells = <0>;
218 };
219
220 sdio1_clk: sdio1 {
221 compatible = "fixed-clock";
222 clock-frequency = <48000000>;
223 #clock-cells = <0>;
224 };
225
226 sdio2_clk: sdio2 {
227 compatible = "fixed-clock";
228 clock-frequency = <48000000>;
229 #clock-cells = <0>;
230 };
231
232 sdio3_clk: sdio3 {
233 compatible = "fixed-clock";
234 clock-frequency = <48000000>;
235 #clock-cells = <0>;
236 };
237
238 sdio4_clk: sdio4 {
239 compatible = "fixed-clock";
240 clock-frequency = <48000000>;
241 #clock-cells = <0>;
242 };
243
244 tmon_1m_clk: tmon_1m {
245 compatible = "fixed-clock";
246 clock-frequency = <1000000>;
247 #clock-cells = <0>;
248 };
249
250 uartb_clk: uartb {
251 compatible = "fixed-clock";
252 clock-frequency = <13000000>;
253 #clock-cells = <0>;
254 };
255
256 uartb2_clk: uartb2 {
257 compatible = "fixed-clock";
258 clock-frequency = <13000000>;
259 #clock-cells = <0>;
260 };
261
262 uartb3_clk: uartb3 {
263 compatible = "fixed-clock";
264 clock-frequency = <13000000>;
265 #clock-cells = <0>;
266 };
267
268 usb_otg_ahb_clk: usb_otg_ahb {
269 compatible = "fixed-clock";
270 clock-frequency = <52000000>;
271 #clock-cells = <0>;
272 };
273 };
274
275 usbotg: usb@3f120000 {
276 compatible = "snps,dwc2";
277 reg = <0x3f120000 0x10000>;
278 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&usb_otg_ahb_clk>;
280 clock-names = "otg";
281 phys = <&usbphy>;
282 phy-names = "usb2-phy";
283 status = "disabled";
284 };
285
286 usbphy: usb-phy@3f130000 {
287 compatible = "brcm,kona-usb2-phy";
288 reg = <0x3f130000 0x28>;
289 #phy-cells = <0>;
290 status = "disabled";
291 };
292};
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index 5ff2382a49e4..af3da55eef49 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -46,27 +46,32 @@
46 46
47 i2c@3500d000 { 47 i2c@3500d000 {
48 status="okay"; 48 status="okay";
49 clock-frequency = <400000>; 49 clock-frequency = <100000>;
50 };
51 50
52 sdio1: sdio@3f180000 { 51 pmu: pmu@8 {
53 max-frequency = <48000000>; 52 reg = <0x08>;
54 status = "okay"; 53 };
55 }; 54 };
56 55
57 sdio2: sdio@3f190000 { 56 sdio2: sdio@3f190000 {
58 non-removable; 57 non-removable;
59 max-frequency = <48000000>; 58 max-frequency = <48000000>;
59 vmmc-supply = <&camldo1_reg>;
60 vqmmc-supply = <&iosr1_reg>;
60 status = "okay"; 61 status = "okay";
61 }; 62 };
62 63
63 sdio4: sdio@3f1b0000 { 64 sdio4: sdio@3f1b0000 {
64 max-frequency = <48000000>; 65 max-frequency = <48000000>;
65 cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; 66 cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
67 vmmc-supply = <&sdldo_reg>;
68 vqmmc-supply = <&sdxldo_reg>;
66 status = "okay"; 69 status = "okay";
67 }; 70 };
68 71
69 usbotg: usb@3f120000 { 72 usbotg: usb@3f120000 {
73 vusb_d-supply = <&usbldo_reg>;
74 vusb_a-supply = <&iosr1_reg>;
70 status = "okay"; 75 status = "okay";
71 }; 76 };
72 77
@@ -74,3 +79,39 @@
74 status = "okay"; 79 status = "okay";
75 }; 80 };
76}; 81};
82
83#include "bcm59056.dtsi"
84
85&pmu {
86 compatible = "brcm,bcm59056";
87 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
88 regulators {
89 camldo1_reg: camldo1 {
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-always-on;
93 };
94
95 sdldo_reg: sdldo {
96 regulator-min-microvolt = <3000000>;
97 regulator-max-microvolt = <3000000>;
98 };
99
100 sdxldo_reg: sdxldo {
101 regulator-min-microvolt = <2700000>;
102 regulator-max-microvolt = <3300000>;
103 };
104
105 usbldo_reg: usbldo {
106 regulator-min-microvolt = <3300000>;
107 regulator-max-microvolt = <3300000>;
108 regulator-always-on;
109 };
110
111 iosr1_reg: iosr1 {
112 regulator-min-microvolt = <1800000>;
113 regulator-max-microvolt = <1800000>;
114 regulator-always-on;
115 };
116 };
117};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index b021c96d3ba1..b8473c43e888 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -15,39 +15,52 @@
15 #size-cells = <1>; 15 #size-cells = <1>;
16 ranges = <0x7e000000 0x20000000 0x02000000>; 16 ranges = <0x7e000000 0x20000000 0x02000000>;
17 17
18 timer { 18 timer@7e003000 {
19 compatible = "brcm,bcm2835-system-timer"; 19 compatible = "brcm,bcm2835-system-timer";
20 reg = <0x7e003000 0x1000>; 20 reg = <0x7e003000 0x1000>;
21 interrupts = <1 0>, <1 1>, <1 2>, <1 3>; 21 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
22 clock-frequency = <1000000>; 22 clock-frequency = <1000000>;
23 }; 23 };
24 24
25 intc: interrupt-controller { 25 dma: dma@7e007000 {
26 compatible = "brcm,bcm2835-dma";
27 reg = <0x7e007000 0xf00>;
28 interrupts = <1 16>,
29 <1 17>,
30 <1 18>,
31 <1 19>,
32 <1 20>,
33 <1 21>,
34 <1 22>,
35 <1 23>,
36 <1 24>,
37 <1 25>,
38 <1 26>,
39 <1 27>,
40 <1 28>;
41
42 #dma-cells = <1>;
43 brcm,dma-channel-mask = <0x7f35>;
44 };
45
46 intc: interrupt-controller@7e00b200 {
26 compatible = "brcm,bcm2835-armctrl-ic"; 47 compatible = "brcm,bcm2835-armctrl-ic";
27 reg = <0x7e00b200 0x200>; 48 reg = <0x7e00b200 0x200>;
28 interrupt-controller; 49 interrupt-controller;
29 #interrupt-cells = <2>; 50 #interrupt-cells = <2>;
30 }; 51 };
31 52
32 watchdog { 53 watchdog@7e100000 {
33 compatible = "brcm,bcm2835-pm-wdt"; 54 compatible = "brcm,bcm2835-pm-wdt";
34 reg = <0x7e100000 0x28>; 55 reg = <0x7e100000 0x28>;
35 }; 56 };
36 57
37 rng { 58 rng@7e104000 {
38 compatible = "brcm,bcm2835-rng"; 59 compatible = "brcm,bcm2835-rng";
39 reg = <0x7e104000 0x10>; 60 reg = <0x7e104000 0x10>;
40 }; 61 };
41 62
42 uart@20201000 { 63 gpio: gpio@7e200000 {
43 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
44 reg = <0x7e201000 0x1000>;
45 interrupts = <2 25>;
46 clock-frequency = <3000000>;
47 arm,primecell-periphid = <0x00241011>;
48 };
49
50 gpio: gpio {
51 compatible = "brcm,bcm2835-gpio"; 64 compatible = "brcm,bcm2835-gpio";
52 reg = <0x7e200000 0xb4>; 65 reg = <0x7e200000 0xb4>;
53 /* 66 /*
@@ -70,7 +83,25 @@
70 #interrupt-cells = <2>; 83 #interrupt-cells = <2>;
71 }; 84 };
72 85
73 spi: spi@20204000 { 86 uart@7e201000 {
87 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
88 reg = <0x7e201000 0x1000>;
89 interrupts = <2 25>;
90 clock-frequency = <3000000>;
91 arm,primecell-periphid = <0x00241011>;
92 };
93
94 i2s: i2s@7e203000 {
95 compatible = "brcm,bcm2835-i2s";
96 reg = <0x7e203000 0x20>,
97 <0x7e101098 0x02>;
98
99 dmas = <&dma 2>,
100 <&dma 3>;
101 dma-names = "tx", "rx";
102 };
103
104 spi: spi@7e204000 {
74 compatible = "brcm,bcm2835-spi"; 105 compatible = "brcm,bcm2835-spi";
75 reg = <0x7e204000 0x1000>; 106 reg = <0x7e204000 0x1000>;
76 interrupts = <2 22>; 107 interrupts = <2 22>;
@@ -90,7 +121,15 @@
90 status = "disabled"; 121 status = "disabled";
91 }; 122 };
92 123
93 i2c1: i2c@20804000 { 124 sdhci: sdhci@7e300000 {
125 compatible = "brcm,bcm2835-sdhci";
126 reg = <0x7e300000 0x100>;
127 interrupts = <2 30>;
128 clocks = <&clk_mmc>;
129 status = "disabled";
130 };
131
132 i2c1: i2c@7e804000 {
94 compatible = "brcm,bcm2835-i2c"; 133 compatible = "brcm,bcm2835-i2c";
95 reg = <0x7e804000 0x1000>; 134 reg = <0x7e804000 0x1000>;
96 interrupts = <2 21>; 135 interrupts = <2 21>;
@@ -100,19 +139,15 @@
100 status = "disabled"; 139 status = "disabled";
101 }; 140 };
102 141
103 sdhci: sdhci { 142 usb@7e980000 {
104 compatible = "brcm,bcm2835-sdhci";
105 reg = <0x7e300000 0x100>;
106 interrupts = <2 30>;
107 clocks = <&clk_mmc>;
108 status = "disabled";
109 };
110
111 usb {
112 compatible = "brcm,bcm2835-usb"; 143 compatible = "brcm,bcm2835-usb";
113 reg = <0x7e980000 0x10000>; 144 reg = <0x7e980000 0x10000>;
114 interrupts = <1 9>; 145 interrupts = <1 9>;
115 }; 146 };
147
148 arm-pmu {
149 compatible = "arm,arm1176-pmu";
150 };
116 }; 151 };
117 152
118 clocks { 153 clocks {
@@ -120,24 +155,27 @@
120 #address-cells = <1>; 155 #address-cells = <1>;
121 #size-cells = <0>; 156 #size-cells = <0>;
122 157
123 clk_mmc: mmc { 158 clk_mmc: clock@0 {
124 compatible = "fixed-clock"; 159 compatible = "fixed-clock";
125 reg = <0>; 160 reg = <0>;
126 #clock-cells = <0>; 161 #clock-cells = <0>;
162 clock-output-names = "mmc";
127 clock-frequency = <100000000>; 163 clock-frequency = <100000000>;
128 }; 164 };
129 165
130 clk_i2c: i2c { 166 clk_i2c: clock@1 {
131 compatible = "fixed-clock"; 167 compatible = "fixed-clock";
132 reg = <1>; 168 reg = <1>;
133 #clock-cells = <0>; 169 #clock-cells = <0>;
170 clock-output-names = "i2c";
134 clock-frequency = <250000000>; 171 clock-frequency = <250000000>;
135 }; 172 };
136 173
137 clk_spi: spi { 174 clk_spi: clock@2 {
138 compatible = "fixed-clock"; 175 compatible = "fixed-clock";
139 reg = <2>; 176 reg = <2>;
140 #clock-cells = <0>; 177 #clock-cells = <0>;
178 clock-output-names = "spi";
141 clock-frequency = <250000000>; 179 clock-frequency = <250000000>;
142 }; 180 };
143 }; 181 };
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
new file mode 100644
index 000000000000..3b5259de5a38
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -0,0 +1,35 @@
1/*
2 * Broadcom BCM470X / BCM5301X arm platform code.
3 * DTS for Netgear R6250 V1
4 *
5 * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10/dts-v1/;
11
12#include "bcm4708.dtsi"
13
14/ {
15 compatible = "netgear,r6250v1", "brcm,bcm4708";
16 model = "Netgear R6250 V1 (BCM4708)";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 memory {
23 reg = <0x00000000 0x08000000>;
24 };
25
26 chipcommonA {
27 uart0: serial@0300 {
28 status = "okay";
29 };
30
31 uart1: serial@0400 {
32 status = "okay";
33 };
34 };
35};
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
new file mode 100644
index 000000000000..31141e83fedd
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -0,0 +1,34 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for BCM4708 SoC.
4 *
5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10#include "bcm5301x.dtsi"
11
12/ {
13 compatible = "brcm,bcm4708";
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
23 reg = <0x0>;
24 };
25
26 cpu@1 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
30 reg = <0x1>;
31 };
32 };
33
34};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
new file mode 100644
index 000000000000..53c624f766b4
--- /dev/null
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -0,0 +1,95 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
5 *
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "skeleton.dtsi"
14
15/ {
16 interrupt-parent = <&gic>;
17
18 chipcommonA {
19 compatible = "simple-bus";
20 ranges = <0x00000000 0x18000000 0x00001000>;
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 uart0: serial@0300 {
25 compatible = "ns16550";
26 reg = <0x0300 0x100>;
27 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
28 clock-frequency = <100000000>;
29 status = "disabled";
30 };
31
32 uart1: serial@0400 {
33 compatible = "ns16550";
34 reg = <0x0400 0x100>;
35 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
36 clock-frequency = <100000000>;
37 status = "disabled";
38 };
39 };
40
41 mpcore {
42 compatible = "simple-bus";
43 ranges = <0x00000000 0x19020000 0x00003000>;
44 #address-cells = <1>;
45 #size-cells = <1>;
46
47 scu@0000 {
48 compatible = "arm,cortex-a9-scu";
49 reg = <0x0000 0x100>;
50 };
51
52 timer@0200 {
53 compatible = "arm,cortex-a9-global-timer";
54 reg = <0x0200 0x100>;
55 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&clk_periph>;
57 };
58
59 local-timer@0600 {
60 compatible = "arm,cortex-a9-twd-timer";
61 reg = <0x0600 0x100>;
62 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&clk_periph>;
64 };
65
66 gic: interrupt-controller@1000 {
67 compatible = "arm,cortex-a9-gic";
68 #interrupt-cells = <3>;
69 #address-cells = <0>;
70 interrupt-controller;
71 reg = <0x1000 0x1000>,
72 <0x0100 0x100>;
73 };
74
75 L2: cache-controller@2000 {
76 compatible = "arm,pl310-cache";
77 reg = <0x2000 0x1000>;
78 cache-unified;
79 cache-level = <2>;
80 };
81 };
82
83 clocks {
84 #address-cells = <1>;
85 #size-cells = <0>;
86
87 /* As long as we do not have a real clock driver us this
88 * fixed clock */
89 clk_periph: periph {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <400000000>;
93 };
94 };
95};
diff --git a/arch/arm/boot/dts/bcm59056.dtsi b/arch/arm/boot/dts/bcm59056.dtsi
new file mode 100644
index 000000000000..dfadaaa89b05
--- /dev/null
+++ b/arch/arm/boot/dts/bcm59056.dtsi
@@ -0,0 +1,74 @@
1/*
2* Copyright 2014 Linaro Limited
3* Author: Matt Porter <mporter@linaro.org>
4*
5* This program is free software; you can redistribute it and/or modify it
6* under the terms of the GNU General Public License as published by the
7* Free Software Foundation; either version 2 of the License, or (at your
8* option) any later version.
9*/
10
11&pmu {
12 compatible = "brcm,bcm59056";
13 regulators {
14 rfldo_reg: rfldo {
15 };
16
17 camldo1_reg: camldo1 {
18 };
19
20 camldo2_reg: camldo2 {
21 };
22
23 simldo1_reg: simldo1 {
24 };
25
26 simldo2_reg: simldo2 {
27 };
28
29 sdldo_reg: sdldo {
30 };
31
32 sdxldo_reg: sdxldo {
33 };
34
35 mmcldo1_reg: mmcldo1 {
36 };
37
38 mmcldo2_reg: mmcldo2 {
39 };
40
41 audldo_reg: audldo {
42 };
43
44 micldo_reg: micldo {
45 };
46
47 usbldo_reg: usbldo {
48 };
49
50 vibldo_reg: vibldo {
51 };
52
53 csr_reg: csr {
54 };
55
56 iosr1_reg: iosr1 {
57 };
58
59 iosr2_reg: iosr2 {
60 };
61
62 msr_reg: msr {
63 };
64
65 sdsr1_reg: sdsr1 {
66 };
67
68 sdsr2_reg: sdsr2 {
69 };
70
71 vsr_reg: vsr {
72 };
73 };
74};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 187fd46b7b5e..3b891dd20993 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -186,6 +186,11 @@
186 reg = <0x20000 0x80>, <0x800100 0x8>; 186 reg = <0x20000 0x80>, <0x800100 0x8>;
187 }; 187 };
188 188
189 sysc: system-ctrl@20000 {
190 compatible = "marvell,orion-system-controller";
191 reg = <0x20000 0x110>;
192 };
193
189 bridge_intc: bridge-interrupt-ctrl@20110 { 194 bridge_intc: bridge-interrupt-ctrl@20110 {
190 compatible = "marvell,orion-bridge-intc"; 195 compatible = "marvell,orion-bridge-intc";
191 interrupt-controller; 196 interrupt-controller;
@@ -210,6 +215,14 @@
210 clocks = <&core_clk 0>; 215 clocks = <&core_clk 0>;
211 }; 216 };
212 217
218 watchdog@20300 {
219 compatible = "marvell,orion-wdt";
220 reg = <0x20300 0x28>, <0x20108 0x4>;
221 interrupt-parent = <&bridge_intc>;
222 interrupts = <3>;
223 clocks = <&core_clk 0>;
224 };
225
213 crypto: crypto-engine@30000 { 226 crypto: crypto-engine@30000 {
214 compatible = "marvell,orion-crypto"; 227 compatible = "marvell,orion-crypto";
215 reg = <0x30000 0x10000>, 228 reg = <0x30000 0x10000>,
@@ -381,7 +394,8 @@
381 394
382 pinctrl: pin-ctrl@d0200 { 395 pinctrl: pin-ctrl@d0200 {
383 compatible = "marvell,dove-pinctrl"; 396 compatible = "marvell,dove-pinctrl";
384 reg = <0xd0200 0x10>; 397 reg = <0xd0200 0x14>,
398 <0xd0440 0x04>;
385 clocks = <&gate_clk 22>; 399 clocks = <&gate_clk 22>;
386 400
387 pmx_gpio_0: pmx-gpio-0 { 401 pmx_gpio_0: pmx-gpio-0 {
@@ -603,6 +617,12 @@
603 reg = <0xd8500 0x20>; 617 reg = <0xd8500 0x20>;
604 }; 618 };
605 619
620 gconf: global-config@e802c {
621 compatible = "marvell,dove-global-config",
622 "syscon";
623 reg = <0xe802c 0x14>;
624 };
625
606 gpio2: gpio-ctrl@e8400 { 626 gpio2: gpio-ctrl@e8400 {
607 compatible = "marvell,orion-gpio"; 627 compatible = "marvell,orion-gpio";
608 #gpio-cells = <2>; 628 #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1fd75aa4639d..1c0f8e1893ae 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -47,6 +47,11 @@
47 1000000 1060000 47 1000000 1060000
48 1176000 1160000 48 1176000 1160000
49 >; 49 >;
50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
50 }; 55 };
51 cpu@1 { 56 cpu@1 {
52 device_type = "cpu"; 57 device_type = "cpu";
@@ -149,6 +154,22 @@
149 ti,hwmods = "counter_32k"; 154 ti,hwmods = "counter_32k";
150 }; 155 };
151 156
157 dra7_ctrl_general: tisyscon@4a002e00 {
158 compatible = "syscon";
159 reg = <0x4a002e00 0x7c>;
160 };
161
162 pbias_regulator: pbias_regulator {
163 compatible = "ti,pbias-omap";
164 reg = <0 0x4>;
165 syscon = <&dra7_ctrl_general>;
166 pbias_mmc_reg: pbias_mmc_omap5 {
167 regulator-name = "pbias_mmc_omap5";
168 regulator-min-microvolt = <1800000>;
169 regulator-max-microvolt = <3000000>;
170 };
171 };
172
152 dra7_pmx_core: pinmux@4a003400 { 173 dra7_pmx_core: pinmux@4a003400 {
153 compatible = "pinctrl-single"; 174 compatible = "pinctrl-single";
154 reg = <0x4a003400 0x0464>; 175 reg = <0x4a003400 0x0464>;
@@ -464,6 +485,20 @@
464 ti,hwmods = "wd_timer2"; 485 ti,hwmods = "wd_timer2";
465 }; 486 };
466 487
488 hwspinlock: spinlock@4a0f6000 {
489 compatible = "ti,omap4-hwspinlock";
490 reg = <0x4a0f6000 0x1000>;
491 ti,hwmods = "spinlock";
492 #hwlock-cells = <1>;
493 };
494
495 dmm@4e000000 {
496 compatible = "ti,omap5-dmm";
497 reg = <0x4e000000 0x800>;
498 interrupts = <0 113 0x4>;
499 ti,hwmods = "dmm";
500 };
501
467 i2c1: i2c@48070000 { 502 i2c1: i2c@48070000 {
468 compatible = "ti,omap4-i2c"; 503 compatible = "ti,omap4-i2c";
469 reg = <0x48070000 0x100>; 504 reg = <0x48070000 0x100>;
@@ -524,6 +559,7 @@
524 dmas = <&sdma 61>, <&sdma 62>; 559 dmas = <&sdma 61>, <&sdma 62>;
525 dma-names = "tx", "rx"; 560 dma-names = "tx", "rx";
526 status = "disabled"; 561 status = "disabled";
562 pbias-supply = <&pbias_mmc_reg>;
527 }; 563 };
528 564
529 mmc2: mmc@480b4000 { 565 mmc2: mmc@480b4000 {
@@ -559,6 +595,138 @@
559 status = "disabled"; 595 status = "disabled";
560 }; 596 };
561 597
598 abb_mpu: regulator-abb-mpu {
599 compatible = "ti,abb-v3";
600 regulator-name = "abb_mpu";
601 #address-cells = <0>;
602 #size-cells = <0>;
603 clocks = <&sys_clkin1>;
604 ti,settling-time = <50>;
605 ti,clock-cycles = <16>;
606
607 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
608 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
609 <0x4ae0c158 0x4>;
610 reg-names = "setup-address", "control-address",
611 "int-address", "efuse-address",
612 "ldo-address";
613 ti,tranxdone-status-mask = <0x80>;
614 /* LDOVBBMPU_FBB_MUX_CTRL */
615 ti,ldovbb-override-mask = <0x400>;
616 /* LDOVBBMPU_FBB_VSET_OUT */
617 ti,ldovbb-vset-mask = <0x1F>;
618
619 /*
620 * NOTE: only FBB mode used but actual vset will
621 * determine final biasing
622 */
623 ti,abb_info = <
624 /*uV ABB efuse rbb_m fbb_m vset_m*/
625 1060000 0 0x0 0 0x02000000 0x01F00000
626 1160000 0 0x4 0 0x02000000 0x01F00000
627 1210000 0 0x8 0 0x02000000 0x01F00000
628 >;
629 };
630
631 abb_ivahd: regulator-abb-ivahd {
632 compatible = "ti,abb-v3";
633 regulator-name = "abb_ivahd";
634 #address-cells = <0>;
635 #size-cells = <0>;
636 clocks = <&sys_clkin1>;
637 ti,settling-time = <50>;
638 ti,clock-cycles = <16>;
639
640 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
641 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
642 <0x4a002470 0x4>;
643 reg-names = "setup-address", "control-address",
644 "int-address", "efuse-address",
645 "ldo-address";
646 ti,tranxdone-status-mask = <0x40000000>;
647 /* LDOVBBIVA_FBB_MUX_CTRL */
648 ti,ldovbb-override-mask = <0x400>;
649 /* LDOVBBIVA_FBB_VSET_OUT */
650 ti,ldovbb-vset-mask = <0x1F>;
651
652 /*
653 * NOTE: only FBB mode used but actual vset will
654 * determine final biasing
655 */
656 ti,abb_info = <
657 /*uV ABB efuse rbb_m fbb_m vset_m*/
658 1055000 0 0x0 0 0x02000000 0x01F00000
659 1150000 0 0x4 0 0x02000000 0x01F00000
660 1250000 0 0x8 0 0x02000000 0x01F00000
661 >;
662 };
663
664 abb_dspeve: regulator-abb-dspeve {
665 compatible = "ti,abb-v3";
666 regulator-name = "abb_dspeve";
667 #address-cells = <0>;
668 #size-cells = <0>;
669 clocks = <&sys_clkin1>;
670 ti,settling-time = <50>;
671 ti,clock-cycles = <16>;
672
673 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
674 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
675 <0x4a00246c 0x4>;
676 reg-names = "setup-address", "control-address",
677 "int-address", "efuse-address",
678 "ldo-address";
679 ti,tranxdone-status-mask = <0x20000000>;
680 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
681 ti,ldovbb-override-mask = <0x400>;
682 /* LDOVBBDSPEVE_FBB_VSET_OUT */
683 ti,ldovbb-vset-mask = <0x1F>;
684
685 /*
686 * NOTE: only FBB mode used but actual vset will
687 * determine final biasing
688 */
689 ti,abb_info = <
690 /*uV ABB efuse rbb_m fbb_m vset_m*/
691 1055000 0 0x0 0 0x02000000 0x01F00000
692 1150000 0 0x4 0 0x02000000 0x01F00000
693 1250000 0 0x8 0 0x02000000 0x01F00000
694 >;
695 };
696
697 abb_gpu: regulator-abb-gpu {
698 compatible = "ti,abb-v3";
699 regulator-name = "abb_gpu";
700 #address-cells = <0>;
701 #size-cells = <0>;
702 clocks = <&sys_clkin1>;
703 ti,settling-time = <50>;
704 ti,clock-cycles = <16>;
705
706 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
707 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
708 <0x4ae0c154 0x4>;
709 reg-names = "setup-address", "control-address",
710 "int-address", "efuse-address",
711 "ldo-address";
712 ti,tranxdone-status-mask = <0x10000000>;
713 /* LDOVBBGPU_FBB_MUX_CTRL */
714 ti,ldovbb-override-mask = <0x400>;
715 /* LDOVBBGPU_FBB_VSET_OUT */
716 ti,ldovbb-vset-mask = <0x1F>;
717
718 /*
719 * NOTE: only FBB mode used but actual vset will
720 * determine final biasing
721 */
722 ti,abb_info = <
723 /*uV ABB efuse rbb_m fbb_m vset_m*/
724 1090000 0 0x0 0 0x02000000 0x01F00000
725 1210000 0 0x4 0 0x02000000 0x01F00000
726 1280000 0 0x8 0 0x02000000 0x01F00000
727 >;
728 };
729
562 mcspi1: spi@48098000 { 730 mcspi1: spi@48098000 {
563 compatible = "ti,omap4-mcspi"; 731 compatible = "ti,omap4-mcspi";
564 reg = <0x48098000 0x200>; 732 reg = <0x48098000 0x200>;
diff --git a/arch/arm/boot/dts/efm32gg-dk3750.dts b/arch/arm/boot/dts/efm32gg-dk3750.dts
index aa5c0f6363d6..b4031fa4a567 100644
--- a/arch/arm/boot/dts/efm32gg-dk3750.dts
+++ b/arch/arm/boot/dts/efm32gg-dk3750.dts
@@ -26,7 +26,7 @@
26 }; 26 };
27 27
28 i2c@4000a000 { 28 i2c@4000a000 {
29 location = <3>; 29 efm32,location = <3>;
30 status = "ok"; 30 status = "ok";
31 31
32 temp@48 { 32 temp@48 {
diff --git a/arch/arm/boot/dts/efm32gg.dtsi b/arch/arm/boot/dts/efm32gg.dtsi
index a342ab0e6e4f..106d505c5d3d 100644
--- a/arch/arm/boot/dts/efm32gg.dtsi
+++ b/arch/arm/boot/dts/efm32gg.dtsi
@@ -84,7 +84,7 @@
84 status = "disabled"; 84 status = "disabled";
85 }; 85 };
86 86
87 spi2: spi@40x4000c800 { /* USART2 */ 87 spi2: spi@4000c800 { /* USART2 */
88 #address-cells = <1>; 88 #address-cells = <1>;
89 #size-cells = <0>; 89 #size-cells = <0>;
90 compatible = "efm32,spi"; 90 compatible = "efm32,spi";
@@ -110,7 +110,7 @@
110 status = "disabled"; 110 status = "disabled";
111 }; 111 };
112 112
113 uart2: uart@40x4000c800 { /* USART2 */ 113 uart2: uart@4000c800 { /* USART2 */
114 compatible = "efm32,uart"; 114 compatible = "efm32,uart";
115 reg = <0x4000c800 0x400>; 115 reg = <0x4000c800 0x400>;
116 interrupts = <18 19>; 116 interrupts = <18 19>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 08452e183b57..2f8bcd068d17 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,6 +19,7 @@
19 * published by the Free Software Foundation. 19 * published by the Free Software Foundation.
20 */ 20 */
21 21
22#include <dt-bindings/clock/exynos4.h>
22#include "skeleton.dtsi" 23#include "skeleton.dtsi"
23 24
24/ { 25/ {
@@ -85,6 +86,11 @@
85 reg = <0x10023CE0 0x20>; 86 reg = <0x10023CE0 0x20>;
86 }; 87 };
87 88
89 pd_gps_alive: gps-alive-power-domain@10023D00 {
90 compatible = "samsung,exynos4210-pd";
91 reg = <0x10023D00 0x20>;
92 };
93
88 gic: interrupt-controller@10490000 { 94 gic: interrupt-controller@10490000 {
89 compatible = "arm,cortex-a9-gic"; 95 compatible = "arm,cortex-a9-gic";
90 #interrupt-cells = <3>; 96 #interrupt-cells = <3>;
@@ -104,6 +110,20 @@
104 reg = <0x10010000 0x400>; 110 reg = <0x10010000 0x400>;
105 }; 111 };
106 112
113 dsi_0: dsi@11C80000 {
114 compatible = "samsung,exynos4210-mipi-dsi";
115 reg = <0x11C80000 0x10000>;
116 interrupts = <0 79 0>;
117 samsung,power-domain = <&pd_lcd0>;
118 phys = <&mipi_phy 1>;
119 phy-names = "dsim";
120 clocks = <&clock 286>, <&clock 143>;
121 clock-names = "bus_clk", "pll_clk";
122 status = "disabled";
123 #address-cells = <1>;
124 #size-cells = <0>;
125 };
126
107 camera { 127 camera {
108 compatible = "samsung,fimc", "simple-bus"; 128 compatible = "samsung,fimc", "simple-bus";
109 status = "disabled"; 129 status = "disabled";
@@ -119,7 +139,7 @@
119 compatible = "samsung,exynos4210-fimc"; 139 compatible = "samsung,exynos4210-fimc";
120 reg = <0x11800000 0x1000>; 140 reg = <0x11800000 0x1000>;
121 interrupts = <0 84 0>; 141 interrupts = <0 84 0>;
122 clocks = <&clock 256>, <&clock 128>; 142 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
123 clock-names = "fimc", "sclk_fimc"; 143 clock-names = "fimc", "sclk_fimc";
124 samsung,power-domain = <&pd_cam>; 144 samsung,power-domain = <&pd_cam>;
125 samsung,sysreg = <&sys_reg>; 145 samsung,sysreg = <&sys_reg>;
@@ -130,7 +150,7 @@
130 compatible = "samsung,exynos4210-fimc"; 150 compatible = "samsung,exynos4210-fimc";
131 reg = <0x11810000 0x1000>; 151 reg = <0x11810000 0x1000>;
132 interrupts = <0 85 0>; 152 interrupts = <0 85 0>;
133 clocks = <&clock 257>, <&clock 129>; 153 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
134 clock-names = "fimc", "sclk_fimc"; 154 clock-names = "fimc", "sclk_fimc";
135 samsung,power-domain = <&pd_cam>; 155 samsung,power-domain = <&pd_cam>;
136 samsung,sysreg = <&sys_reg>; 156 samsung,sysreg = <&sys_reg>;
@@ -141,7 +161,7 @@
141 compatible = "samsung,exynos4210-fimc"; 161 compatible = "samsung,exynos4210-fimc";
142 reg = <0x11820000 0x1000>; 162 reg = <0x11820000 0x1000>;
143 interrupts = <0 86 0>; 163 interrupts = <0 86 0>;
144 clocks = <&clock 258>, <&clock 130>; 164 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
145 clock-names = "fimc", "sclk_fimc"; 165 clock-names = "fimc", "sclk_fimc";
146 samsung,power-domain = <&pd_cam>; 166 samsung,power-domain = <&pd_cam>;
147 samsung,sysreg = <&sys_reg>; 167 samsung,sysreg = <&sys_reg>;
@@ -152,7 +172,7 @@
152 compatible = "samsung,exynos4210-fimc"; 172 compatible = "samsung,exynos4210-fimc";
153 reg = <0x11830000 0x1000>; 173 reg = <0x11830000 0x1000>;
154 interrupts = <0 87 0>; 174 interrupts = <0 87 0>;
155 clocks = <&clock 259>, <&clock 131>; 175 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
156 clock-names = "fimc", "sclk_fimc"; 176 clock-names = "fimc", "sclk_fimc";
157 samsung,power-domain = <&pd_cam>; 177 samsung,power-domain = <&pd_cam>;
158 samsung,sysreg = <&sys_reg>; 178 samsung,sysreg = <&sys_reg>;
@@ -163,7 +183,7 @@
163 compatible = "samsung,exynos4210-csis"; 183 compatible = "samsung,exynos4210-csis";
164 reg = <0x11880000 0x4000>; 184 reg = <0x11880000 0x4000>;
165 interrupts = <0 78 0>; 185 interrupts = <0 78 0>;
166 clocks = <&clock 260>, <&clock 134>; 186 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
167 clock-names = "csis", "sclk_csis"; 187 clock-names = "csis", "sclk_csis";
168 bus-width = <4>; 188 bus-width = <4>;
169 samsung,power-domain = <&pd_cam>; 189 samsung,power-domain = <&pd_cam>;
@@ -178,7 +198,7 @@
178 compatible = "samsung,exynos4210-csis"; 198 compatible = "samsung,exynos4210-csis";
179 reg = <0x11890000 0x4000>; 199 reg = <0x11890000 0x4000>;
180 interrupts = <0 80 0>; 200 interrupts = <0 80 0>;
181 clocks = <&clock 261>, <&clock 135>; 201 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
182 clock-names = "csis", "sclk_csis"; 202 clock-names = "csis", "sclk_csis";
183 bus-width = <2>; 203 bus-width = <2>;
184 samsung,power-domain = <&pd_cam>; 204 samsung,power-domain = <&pd_cam>;
@@ -194,7 +214,7 @@
194 compatible = "samsung,s3c2410-wdt"; 214 compatible = "samsung,s3c2410-wdt";
195 reg = <0x10060000 0x100>; 215 reg = <0x10060000 0x100>;
196 interrupts = <0 43 0>; 216 interrupts = <0 43 0>;
197 clocks = <&clock 345>; 217 clocks = <&clock CLK_WDT>;
198 clock-names = "watchdog"; 218 clock-names = "watchdog";
199 status = "disabled"; 219 status = "disabled";
200 }; 220 };
@@ -203,7 +223,7 @@
203 compatible = "samsung,s3c6410-rtc"; 223 compatible = "samsung,s3c6410-rtc";
204 reg = <0x10070000 0x100>; 224 reg = <0x10070000 0x100>;
205 interrupts = <0 44 0>, <0 45 0>; 225 interrupts = <0 44 0>, <0 45 0>;
206 clocks = <&clock 346>; 226 clocks = <&clock CLK_RTC>;
207 clock-names = "rtc"; 227 clock-names = "rtc";
208 status = "disabled"; 228 status = "disabled";
209 }; 229 };
@@ -212,7 +232,7 @@
212 compatible = "samsung,s5pv210-keypad"; 232 compatible = "samsung,s5pv210-keypad";
213 reg = <0x100A0000 0x100>; 233 reg = <0x100A0000 0x100>;
214 interrupts = <0 109 0>; 234 interrupts = <0 109 0>;
215 clocks = <&clock 347>; 235 clocks = <&clock CLK_KEYIF>;
216 clock-names = "keypad"; 236 clock-names = "keypad";
217 status = "disabled"; 237 status = "disabled";
218 }; 238 };
@@ -221,7 +241,7 @@
221 compatible = "samsung,exynos4210-sdhci"; 241 compatible = "samsung,exynos4210-sdhci";
222 reg = <0x12510000 0x100>; 242 reg = <0x12510000 0x100>;
223 interrupts = <0 73 0>; 243 interrupts = <0 73 0>;
224 clocks = <&clock 297>, <&clock 145>; 244 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
225 clock-names = "hsmmc", "mmc_busclk.2"; 245 clock-names = "hsmmc", "mmc_busclk.2";
226 status = "disabled"; 246 status = "disabled";
227 }; 247 };
@@ -230,7 +250,7 @@
230 compatible = "samsung,exynos4210-sdhci"; 250 compatible = "samsung,exynos4210-sdhci";
231 reg = <0x12520000 0x100>; 251 reg = <0x12520000 0x100>;
232 interrupts = <0 74 0>; 252 interrupts = <0 74 0>;
233 clocks = <&clock 298>, <&clock 146>; 253 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
234 clock-names = "hsmmc", "mmc_busclk.2"; 254 clock-names = "hsmmc", "mmc_busclk.2";
235 status = "disabled"; 255 status = "disabled";
236 }; 256 };
@@ -239,7 +259,7 @@
239 compatible = "samsung,exynos4210-sdhci"; 259 compatible = "samsung,exynos4210-sdhci";
240 reg = <0x12530000 0x100>; 260 reg = <0x12530000 0x100>;
241 interrupts = <0 75 0>; 261 interrupts = <0 75 0>;
242 clocks = <&clock 299>, <&clock 147>; 262 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
243 clock-names = "hsmmc", "mmc_busclk.2"; 263 clock-names = "hsmmc", "mmc_busclk.2";
244 status = "disabled"; 264 status = "disabled";
245 }; 265 };
@@ -248,7 +268,7 @@
248 compatible = "samsung,exynos4210-sdhci"; 268 compatible = "samsung,exynos4210-sdhci";
249 reg = <0x12540000 0x100>; 269 reg = <0x12540000 0x100>;
250 interrupts = <0 76 0>; 270 interrupts = <0 76 0>;
251 clocks = <&clock 300>, <&clock 148>; 271 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
252 clock-names = "hsmmc", "mmc_busclk.2"; 272 clock-names = "hsmmc", "mmc_busclk.2";
253 status = "disabled"; 273 status = "disabled";
254 }; 274 };
@@ -257,7 +277,7 @@
257 compatible = "samsung,exynos4210-ehci"; 277 compatible = "samsung,exynos4210-ehci";
258 reg = <0x12580000 0x100>; 278 reg = <0x12580000 0x100>;
259 interrupts = <0 70 0>; 279 interrupts = <0 70 0>;
260 clocks = <&clock 304>; 280 clocks = <&clock CLK_USB_HOST>;
261 clock-names = "usbhost"; 281 clock-names = "usbhost";
262 status = "disabled"; 282 status = "disabled";
263 }; 283 };
@@ -266,7 +286,7 @@
266 compatible = "samsung,exynos4210-ohci"; 286 compatible = "samsung,exynos4210-ohci";
267 reg = <0x12590000 0x100>; 287 reg = <0x12590000 0x100>;
268 interrupts = <0 70 0>; 288 interrupts = <0 70 0>;
269 clocks = <&clock 304>; 289 clocks = <&clock CLK_USB_HOST>;
270 clock-names = "usbhost"; 290 clock-names = "usbhost";
271 status = "disabled"; 291 status = "disabled";
272 }; 292 };
@@ -276,7 +296,7 @@
276 reg = <0x13400000 0x10000>; 296 reg = <0x13400000 0x10000>;
277 interrupts = <0 94 0>; 297 interrupts = <0 94 0>;
278 samsung,power-domain = <&pd_mfc>; 298 samsung,power-domain = <&pd_mfc>;
279 clocks = <&clock 273>; 299 clocks = <&clock CLK_MFC>;
280 clock-names = "mfc"; 300 clock-names = "mfc";
281 status = "disabled"; 301 status = "disabled";
282 }; 302 };
@@ -285,7 +305,7 @@
285 compatible = "samsung,exynos4210-uart"; 305 compatible = "samsung,exynos4210-uart";
286 reg = <0x13800000 0x100>; 306 reg = <0x13800000 0x100>;
287 interrupts = <0 52 0>; 307 interrupts = <0 52 0>;
288 clocks = <&clock 312>, <&clock 151>; 308 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
289 clock-names = "uart", "clk_uart_baud0"; 309 clock-names = "uart", "clk_uart_baud0";
290 status = "disabled"; 310 status = "disabled";
291 }; 311 };
@@ -294,7 +314,7 @@
294 compatible = "samsung,exynos4210-uart"; 314 compatible = "samsung,exynos4210-uart";
295 reg = <0x13810000 0x100>; 315 reg = <0x13810000 0x100>;
296 interrupts = <0 53 0>; 316 interrupts = <0 53 0>;
297 clocks = <&clock 313>, <&clock 152>; 317 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
298 clock-names = "uart", "clk_uart_baud0"; 318 clock-names = "uart", "clk_uart_baud0";
299 status = "disabled"; 319 status = "disabled";
300 }; 320 };
@@ -303,7 +323,7 @@
303 compatible = "samsung,exynos4210-uart"; 323 compatible = "samsung,exynos4210-uart";
304 reg = <0x13820000 0x100>; 324 reg = <0x13820000 0x100>;
305 interrupts = <0 54 0>; 325 interrupts = <0 54 0>;
306 clocks = <&clock 314>, <&clock 153>; 326 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
307 clock-names = "uart", "clk_uart_baud0"; 327 clock-names = "uart", "clk_uart_baud0";
308 status = "disabled"; 328 status = "disabled";
309 }; 329 };
@@ -312,7 +332,7 @@
312 compatible = "samsung,exynos4210-uart"; 332 compatible = "samsung,exynos4210-uart";
313 reg = <0x13830000 0x100>; 333 reg = <0x13830000 0x100>;
314 interrupts = <0 55 0>; 334 interrupts = <0 55 0>;
315 clocks = <&clock 315>, <&clock 154>; 335 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
316 clock-names = "uart", "clk_uart_baud0"; 336 clock-names = "uart", "clk_uart_baud0";
317 status = "disabled"; 337 status = "disabled";
318 }; 338 };
@@ -323,7 +343,7 @@
323 compatible = "samsung,s3c2440-i2c"; 343 compatible = "samsung,s3c2440-i2c";
324 reg = <0x13860000 0x100>; 344 reg = <0x13860000 0x100>;
325 interrupts = <0 58 0>; 345 interrupts = <0 58 0>;
326 clocks = <&clock 317>; 346 clocks = <&clock CLK_I2C0>;
327 clock-names = "i2c"; 347 clock-names = "i2c";
328 pinctrl-names = "default"; 348 pinctrl-names = "default";
329 pinctrl-0 = <&i2c0_bus>; 349 pinctrl-0 = <&i2c0_bus>;
@@ -336,7 +356,7 @@
336 compatible = "samsung,s3c2440-i2c"; 356 compatible = "samsung,s3c2440-i2c";
337 reg = <0x13870000 0x100>; 357 reg = <0x13870000 0x100>;
338 interrupts = <0 59 0>; 358 interrupts = <0 59 0>;
339 clocks = <&clock 318>; 359 clocks = <&clock CLK_I2C1>;
340 clock-names = "i2c"; 360 clock-names = "i2c";
341 pinctrl-names = "default"; 361 pinctrl-names = "default";
342 pinctrl-0 = <&i2c1_bus>; 362 pinctrl-0 = <&i2c1_bus>;
@@ -349,7 +369,7 @@
349 compatible = "samsung,s3c2440-i2c"; 369 compatible = "samsung,s3c2440-i2c";
350 reg = <0x13880000 0x100>; 370 reg = <0x13880000 0x100>;
351 interrupts = <0 60 0>; 371 interrupts = <0 60 0>;
352 clocks = <&clock 319>; 372 clocks = <&clock CLK_I2C2>;
353 clock-names = "i2c"; 373 clock-names = "i2c";
354 status = "disabled"; 374 status = "disabled";
355 }; 375 };
@@ -360,7 +380,7 @@
360 compatible = "samsung,s3c2440-i2c"; 380 compatible = "samsung,s3c2440-i2c";
361 reg = <0x13890000 0x100>; 381 reg = <0x13890000 0x100>;
362 interrupts = <0 61 0>; 382 interrupts = <0 61 0>;
363 clocks = <&clock 320>; 383 clocks = <&clock CLK_I2C3>;
364 clock-names = "i2c"; 384 clock-names = "i2c";
365 status = "disabled"; 385 status = "disabled";
366 }; 386 };
@@ -371,7 +391,7 @@
371 compatible = "samsung,s3c2440-i2c"; 391 compatible = "samsung,s3c2440-i2c";
372 reg = <0x138A0000 0x100>; 392 reg = <0x138A0000 0x100>;
373 interrupts = <0 62 0>; 393 interrupts = <0 62 0>;
374 clocks = <&clock 321>; 394 clocks = <&clock CLK_I2C4>;
375 clock-names = "i2c"; 395 clock-names = "i2c";
376 status = "disabled"; 396 status = "disabled";
377 }; 397 };
@@ -382,7 +402,7 @@
382 compatible = "samsung,s3c2440-i2c"; 402 compatible = "samsung,s3c2440-i2c";
383 reg = <0x138B0000 0x100>; 403 reg = <0x138B0000 0x100>;
384 interrupts = <0 63 0>; 404 interrupts = <0 63 0>;
385 clocks = <&clock 322>; 405 clocks = <&clock CLK_I2C5>;
386 clock-names = "i2c"; 406 clock-names = "i2c";
387 status = "disabled"; 407 status = "disabled";
388 }; 408 };
@@ -393,7 +413,7 @@
393 compatible = "samsung,s3c2440-i2c"; 413 compatible = "samsung,s3c2440-i2c";
394 reg = <0x138C0000 0x100>; 414 reg = <0x138C0000 0x100>;
395 interrupts = <0 64 0>; 415 interrupts = <0 64 0>;
396 clocks = <&clock 323>; 416 clocks = <&clock CLK_I2C6>;
397 clock-names = "i2c"; 417 clock-names = "i2c";
398 status = "disabled"; 418 status = "disabled";
399 }; 419 };
@@ -404,7 +424,7 @@
404 compatible = "samsung,s3c2440-i2c"; 424 compatible = "samsung,s3c2440-i2c";
405 reg = <0x138D0000 0x100>; 425 reg = <0x138D0000 0x100>;
406 interrupts = <0 65 0>; 426 interrupts = <0 65 0>;
407 clocks = <&clock 324>; 427 clocks = <&clock CLK_I2C7>;
408 clock-names = "i2c"; 428 clock-names = "i2c";
409 status = "disabled"; 429 status = "disabled";
410 }; 430 };
@@ -417,7 +437,7 @@
417 dma-names = "tx", "rx"; 437 dma-names = "tx", "rx";
418 #address-cells = <1>; 438 #address-cells = <1>;
419 #size-cells = <0>; 439 #size-cells = <0>;
420 clocks = <&clock 327>, <&clock 159>; 440 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
421 clock-names = "spi", "spi_busclk0"; 441 clock-names = "spi", "spi_busclk0";
422 pinctrl-names = "default"; 442 pinctrl-names = "default";
423 pinctrl-0 = <&spi0_bus>; 443 pinctrl-0 = <&spi0_bus>;
@@ -432,7 +452,7 @@
432 dma-names = "tx", "rx"; 452 dma-names = "tx", "rx";
433 #address-cells = <1>; 453 #address-cells = <1>;
434 #size-cells = <0>; 454 #size-cells = <0>;
435 clocks = <&clock 328>, <&clock 160>; 455 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
436 clock-names = "spi", "spi_busclk0"; 456 clock-names = "spi", "spi_busclk0";
437 pinctrl-names = "default"; 457 pinctrl-names = "default";
438 pinctrl-0 = <&spi1_bus>; 458 pinctrl-0 = <&spi1_bus>;
@@ -447,7 +467,7 @@
447 dma-names = "tx", "rx"; 467 dma-names = "tx", "rx";
448 #address-cells = <1>; 468 #address-cells = <1>;
449 #size-cells = <0>; 469 #size-cells = <0>;
450 clocks = <&clock 329>, <&clock 161>; 470 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
451 clock-names = "spi", "spi_busclk0"; 471 clock-names = "spi", "spi_busclk0";
452 pinctrl-names = "default"; 472 pinctrl-names = "default";
453 pinctrl-0 = <&spi2_bus>; 473 pinctrl-0 = <&spi2_bus>;
@@ -458,7 +478,7 @@
458 compatible = "samsung,exynos4210-pwm"; 478 compatible = "samsung,exynos4210-pwm";
459 reg = <0x139D0000 0x1000>; 479 reg = <0x139D0000 0x1000>;
460 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; 480 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
461 clocks = <&clock 336>; 481 clocks = <&clock CLK_PWM>;
462 clock-names = "timers"; 482 clock-names = "timers";
463 #pwm-cells = <2>; 483 #pwm-cells = <2>;
464 status = "disabled"; 484 status = "disabled";
@@ -475,7 +495,7 @@
475 compatible = "arm,pl330", "arm,primecell"; 495 compatible = "arm,pl330", "arm,primecell";
476 reg = <0x12680000 0x1000>; 496 reg = <0x12680000 0x1000>;
477 interrupts = <0 35 0>; 497 interrupts = <0 35 0>;
478 clocks = <&clock 292>; 498 clocks = <&clock CLK_PDMA0>;
479 clock-names = "apb_pclk"; 499 clock-names = "apb_pclk";
480 #dma-cells = <1>; 500 #dma-cells = <1>;
481 #dma-channels = <8>; 501 #dma-channels = <8>;
@@ -486,7 +506,7 @@
486 compatible = "arm,pl330", "arm,primecell"; 506 compatible = "arm,pl330", "arm,primecell";
487 reg = <0x12690000 0x1000>; 507 reg = <0x12690000 0x1000>;
488 interrupts = <0 36 0>; 508 interrupts = <0 36 0>;
489 clocks = <&clock 293>; 509 clocks = <&clock CLK_PDMA1>;
490 clock-names = "apb_pclk"; 510 clock-names = "apb_pclk";
491 #dma-cells = <1>; 511 #dma-cells = <1>;
492 #dma-channels = <8>; 512 #dma-channels = <8>;
@@ -497,7 +517,7 @@
497 compatible = "arm,pl330", "arm,primecell"; 517 compatible = "arm,pl330", "arm,primecell";
498 reg = <0x12850000 0x1000>; 518 reg = <0x12850000 0x1000>;
499 interrupts = <0 34 0>; 519 interrupts = <0 34 0>;
500 clocks = <&clock 279>; 520 clocks = <&clock CLK_MDMA>;
501 clock-names = "apb_pclk"; 521 clock-names = "apb_pclk";
502 #dma-cells = <1>; 522 #dma-cells = <1>;
503 #dma-channels = <8>; 523 #dma-channels = <8>;
@@ -511,7 +531,7 @@
511 reg = <0x11c00000 0x20000>; 531 reg = <0x11c00000 0x20000>;
512 interrupt-names = "fifo", "vsync", "lcd_sys"; 532 interrupt-names = "fifo", "vsync", "lcd_sys";
513 interrupts = <11 0>, <11 1>, <11 2>; 533 interrupts = <11 0>, <11 1>, <11 2>;
514 clocks = <&clock 140>, <&clock 283>; 534 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
515 clock-names = "sclk_fimd", "fimd"; 535 clock-names = "sclk_fimd", "fimd";
516 samsung,power-domain = <&pd_lcd0>; 536 samsung,power-domain = <&pd_lcd0>;
517 status = "disabled"; 537 status = "disabled";
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 2aa13cb3bbed..72fb11f7ea21 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -19,7 +19,7 @@
19 19
20/ { 20/ {
21 model = "Insignal Origen evaluation board based on Exynos4210"; 21 model = "Insignal Origen evaluation board based on Exynos4210";
22 compatible = "insignal,origen", "samsung,exynos4210"; 22 compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4";
23 23
24 memory { 24 memory {
25 reg = <0x40000000 0x10000000 25 reg = <0x40000000 0x10000000
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 9c01b718d29d..636d16684750 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -19,7 +19,7 @@
19 19
20/ { 20/ {
21 model = "Samsung smdkv310 evaluation board based on Exynos4210"; 21 model = "Samsung smdkv310 evaluation board based on Exynos4210";
22 compatible = "samsung,smdkv310", "samsung,exynos4210"; 22 compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4";
23 23
24 memory { 24 memory {
25 reg = <0x40000000 0x80000000>; 25 reg = <0x40000000 0x80000000>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 63cc571ca307..63aa2bb24a4b 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -17,7 +17,7 @@
17 17
18/ { 18/ {
19 model = "Samsung Trats based on Exynos4210"; 19 model = "Samsung Trats based on Exynos4210";
20 compatible = "samsung,trats", "samsung,exynos4210"; 20 compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4";
21 21
22 memory { 22 memory {
23 reg = <0x40000000 0x10000000 23 reg = <0x40000000 0x10000000
@@ -353,6 +353,67 @@
353 }; 353 };
354 }; 354 };
355 355
356 dsi_0: dsi@11C80000 {
357 vddcore-supply = <&vusb_reg>;
358 vddio-supply = <&vmipi_reg>;
359 samsung,pll-clock-frequency = <24000000>;
360 status = "okay";
361
362 ports {
363 #address-cells = <1>;
364 #size-cells = <0>;
365
366 port@1 {
367 reg = <1>;
368
369 dsi_out: endpoint {
370 remote-endpoint = <&dsi_in>;
371 samsung,burst-clock-frequency = <500000000>;
372 samsung,esc-clock-frequency = <20000000>;
373 };
374 };
375 };
376
377 panel@0 {
378 reg = <0>;
379 compatible = "samsung,s6e8aa0";
380 vdd3-supply = <&vcclcd_reg>;
381 vci-supply = <&vlcd_reg>;
382 reset-gpios = <&gpy4 5 0>;
383 power-on-delay= <50>;
384 reset-delay = <100>;
385 init-delay = <100>;
386 flip-horizontal;
387 flip-vertical;
388 panel-width-mm = <58>;
389 panel-height-mm = <103>;
390
391 display-timings {
392 timing-0 {
393 clock-frequency = <57153600>;
394 hactive = <720>;
395 vactive = <1280>;
396 hfront-porch = <5>;
397 hback-porch = <5>;
398 hsync-len = <5>;
399 vfront-porch = <13>;
400 vback-porch = <1>;
401 vsync-len = <2>;
402 };
403 };
404
405 port {
406 dsi_in: endpoint {
407 remote-endpoint = <&dsi_out>;
408 };
409 };
410 };
411 };
412
413 fimd@11c00000 {
414 status = "okay";
415 };
416
356 camera { 417 camera {
357 pinctrl-names = "default"; 418 pinctrl-names = "default";
358 pinctrl-0 = <>; 419 pinctrl-0 = <>;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d2e3f5f5916d..63e34b24b04f 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -17,7 +17,7 @@
17 17
18/ { 18/ {
19 model = "Samsung Universal C210 based on Exynos4210 rev0"; 19 model = "Samsung Universal C210 based on Exynos4210 rev0";
20 compatible = "samsung,universal_c210", "samsung,exynos4210"; 20 compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4";
21 21
22 memory { 22 memory {
23 reg = <0x40000000 0x10000000 23 reg = <0x40000000 0x10000000
@@ -345,6 +345,70 @@
345 }; 345 };
346 }; 346 };
347 347
348 spi-lcd {
349 compatible = "spi-gpio";
350 #address-cells = <1>;
351 #size-cells = <0>;
352
353 gpio-sck = <&gpy3 1 0>;
354 gpio-mosi = <&gpy3 3 0>;
355 num-chipselects = <1>;
356 cs-gpios = <&gpy4 3 0>;
357
358 lcd@0 {
359 compatible = "samsung,ld9040";
360 reg = <0>;
361 vdd3-supply = <&ldo7_reg>;
362 vci-supply = <&ldo17_reg>;
363 reset-gpios = <&gpy4 5 0>;
364 spi-max-frequency = <1200000>;
365 spi-cpol;
366 spi-cpha;
367 power-on-delay = <10>;
368 reset-delay = <10>;
369 panel-width-mm = <90>;
370 panel-height-mm = <154>;
371 display-timings {
372 timing {
373 clock-frequency = <23492370>;
374 hactive = <480>;
375 vactive = <800>;
376 hback-porch = <16>;
377 hfront-porch = <16>;
378 vback-porch = <2>;
379 vfront-porch = <28>;
380 hsync-len = <2>;
381 vsync-len = <1>;
382 hsync-active = <0>;
383 vsync-active = <0>;
384 de-active = <0>;
385 pixelclk-active = <0>;
386 };
387 };
388 port {
389 lcd_ep: endpoint {
390 remote-endpoint = <&fimd_dpi_ep>;
391 };
392 };
393 };
394 };
395
396 fimd: fimd@11c00000 {
397 pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
398 pinctrl-names = "default";
399 status = "okay";
400 samsung,invert-vden;
401 samsung,invert-vclk;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 port@3 {
405 reg = <3>;
406 fimd_dpi_ep: endpoint {
407 remote-endpoint = <&lcd_ep>;
408 };
409 };
410 };
411
348 pwm@139D0000 { 412 pwm@139D0000 {
349 compatible = "samsung,s5p6440-pwm"; 413 compatible = "samsung,s5p6440-pwm";
350 status = "okay"; 414 status = "okay";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 48ecd7a755ab..cacf6140dd2f 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -23,7 +23,7 @@
23#include "exynos4210-pinctrl.dtsi" 23#include "exynos4210-pinctrl.dtsi"
24 24
25/ { 25/ {
26 compatible = "samsung,exynos4210"; 26 compatible = "samsung,exynos4210", "samsung,exynos4";
27 27
28 aliases { 28 aliases {
29 pinctrl0 = &pinctrl_0; 29 pinctrl0 = &pinctrl_0;
@@ -53,7 +53,7 @@
53 reg = <0x10050000 0x800>; 53 reg = <0x10050000 0x800>;
54 interrupt-parent = <&mct_map>; 54 interrupt-parent = <&mct_map>;
55 interrupts = <0>, <1>, <2>, <3>, <4>, <5>; 55 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
56 clocks = <&clock 3>, <&clock 344>; 56 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
57 clock-names = "fin_pll", "mct"; 57 clock-names = "fin_pll", "mct";
58 58
59 mct_map: mct-map { 59 mct_map: mct-map {
@@ -109,7 +109,7 @@
109 interrupt-parent = <&combiner>; 109 interrupt-parent = <&combiner>;
110 reg = <0x100C0000 0x100>; 110 reg = <0x100C0000 0x100>;
111 interrupts = <2 4>; 111 interrupts = <2 4>;
112 clocks = <&clock 383>; 112 clocks = <&clock CLK_TMU_APBIF>;
113 clock-names = "tmu_apbif"; 113 clock-names = "tmu_apbif";
114 status = "disabled"; 114 status = "disabled";
115 }; 115 };
@@ -118,13 +118,14 @@
118 compatible = "samsung,s5pv210-g2d"; 118 compatible = "samsung,s5pv210-g2d";
119 reg = <0x12800000 0x1000>; 119 reg = <0x12800000 0x1000>;
120 interrupts = <0 89 0>; 120 interrupts = <0 89 0>;
121 clocks = <&clock 177>, <&clock 277>; 121 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
122 clock-names = "sclk_fimg2d", "fimg2d"; 122 clock-names = "sclk_fimg2d", "fimg2d";
123 status = "disabled"; 123 status = "disabled";
124 }; 124 };
125 125
126 camera { 126 camera {
127 clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; 127 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
128 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
128 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 129 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
129 130
130 fimc_0: fimc@11800000 { 131 fimc_0: fimc@11800000 {
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 94a43f9a05e2..3c00e6ec9302 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -20,18 +20,13 @@
20#include "exynos4x12.dtsi" 20#include "exynos4x12.dtsi"
21 21
22/ { 22/ {
23 compatible = "samsung,exynos4212"; 23 compatible = "samsung,exynos4212", "samsung,exynos4";
24 24
25 gic: interrupt-controller@10490000 { 25 combiner: interrupt-controller@10440000 {
26 cpu-offset = <0x8000>; 26 samsung,combiner-nr = <18>;
27 }; 27 };
28 28
29 interrupt-controller@10440000 { 29 gic: interrupt-controller@10490000 {
30 samsung,combiner-nr = <18>; 30 cpu-offset = <0x8000>;
31 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
32 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
33 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
34 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
35 <0 107 0>, <0 108 0>;
36 }; 31 };
37}; 32};
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 9804fcb71f8c..31db28a4bb33 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -16,7 +16,7 @@
16 16
17/ { 17/ {
18 model = "Hardkernel ODROID-X board based on Exynos4412"; 18 model = "Hardkernel ODROID-X board based on Exynos4412";
19 compatible = "hardkernel,odroid-x", "samsung,exynos4412"; 19 compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4";
20 20
21 memory { 21 memory {
22 reg = <0x40000000 0x40000000>; 22 reg = <0x40000000 0x40000000>;
@@ -251,7 +251,7 @@
251 buck2_reg: BUCK2 { 251 buck2_reg: BUCK2 {
252 regulator-name = "vdd_arm"; 252 regulator-name = "vdd_arm";
253 regulator-min-microvolt = <900000>; 253 regulator-min-microvolt = <900000>;
254 regulator-max-microvolt = <1300000>; 254 regulator-max-microvolt = <1350000>;
255 regulator-always-on; 255 regulator-always-on;
256 regulator-boot-on; 256 regulator-boot-on;
257 }; 257 };
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 6bc053924e9e..e2c0dcab4d81 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -17,7 +17,7 @@
17 17
18/ { 18/ {
19 model = "Insignal Origen evaluation board based on Exynos4412"; 19 model = "Insignal Origen evaluation board based on Exynos4412";
20 compatible = "insignal,origen4412", "samsung,exynos4412"; 20 compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4";
21 21
22 memory { 22 memory {
23 reg = <0x40000000 0x40000000>; 23 reg = <0x40000000 0x40000000>;
@@ -459,8 +459,8 @@
459 459
460 buck2_reg: BUCK2 { 460 buck2_reg: BUCK2 {
461 regulator-name = "vdd_arm"; 461 regulator-name = "vdd_arm";
462 regulator-min-microvolt = <925000>; 462 regulator-min-microvolt = <900000>;
463 regulator-max-microvolt = <1300000>; 463 regulator-max-microvolt = <1350000>;
464 regulator-always-on; 464 regulator-always-on;
465 regulator-boot-on; 465 regulator-boot-on;
466 op_mode = <1>; /* Normal Mode */ 466 op_mode = <1>; /* Normal Mode */
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index ad316a1ee9e0..ded0b70f7644 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -17,7 +17,7 @@
17 17
18/ { 18/ {
19 model = "Samsung SMDK evaluation board based on Exynos4412"; 19 model = "Samsung SMDK evaluation board based on Exynos4412";
20 compatible = "samsung,smdk4412", "samsung,exynos4412"; 20 compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4";
21 21
22 memory { 22 memory {
23 reg = <0x40000000 0x40000000>; 23 reg = <0x40000000 0x40000000>;
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
index 0a9831256b33..ea6929d9c621 100644
--- a/arch/arm/boot/dts/exynos4412-tiny4412.dts
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -16,7 +16,7 @@
16 16
17/ { 17/ {
18 model = "FriendlyARM TINY4412 board based on Exynos4412"; 18 model = "FriendlyARM TINY4412 board based on Exynos4412";
19 compatible = "friendlyarm,tiny4412", "samsung,exynos4412"; 19 compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4";
20 20
21 memory { 21 memory {
22 reg = <0x40000000 0x40000000>; 22 reg = <0x40000000 0x40000000>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 4f851ccf40eb..9583563dd0ef 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -17,7 +17,7 @@
17 17
18/ { 18/ {
19 model = "Samsung Trats 2 based on Exynos4412"; 19 model = "Samsung Trats 2 based on Exynos4412";
20 compatible = "samsung,trats2", "samsung,exynos4412"; 20 compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
21 21
22 aliases { 22 aliases {
23 i2c8 = &i2c_ak8975; 23 i2c8 = &i2c_ak8975;
@@ -71,6 +71,15 @@
71 enable-active-high; 71 enable-active-high;
72 }; 72 };
73 73
74 lcd_vdd3_reg: voltage-regulator-2 {
75 compatible = "regulator-fixed";
76 regulator-name = "LCD_VDD_2.2V";
77 regulator-min-microvolt = <2200000>;
78 regulator-max-microvolt = <2200000>;
79 gpio = <&gpc0 1 0>;
80 enable-active-high;
81 };
82
74 /* More to come */ 83 /* More to come */
75 }; 84 };
76 85
@@ -106,6 +115,11 @@
106 }; 115 };
107 }; 116 };
108 117
118 adc: adc@126C0000 {
119 vdd-supply = <&ldo3_reg>;
120 status = "okay";
121 };
122
109 i2c@13890000 { 123 i2c@13890000 {
110 samsung,i2c-sda-delay = <100>; 124 samsung,i2c-sda-delay = <100>;
111 samsung,i2c-slave-addr = <0x10>; 125 samsung,i2c-slave-addr = <0x10>;
@@ -511,6 +525,67 @@
511 }; 525 };
512 }; 526 };
513 527
528 dsi_0: dsi@11C80000 {
529 vddcore-supply = <&ldo8_reg>;
530 vddio-supply = <&ldo10_reg>;
531 samsung,pll-clock-frequency = <24000000>;
532 status = "okay";
533
534 ports {
535 #address-cells = <1>;
536 #size-cells = <0>;
537
538 port@1 {
539 reg = <1>;
540
541 dsi_out: endpoint {
542 remote-endpoint = <&dsi_in>;
543 samsung,burst-clock-frequency = <500000000>;
544 samsung,esc-clock-frequency = <20000000>;
545 };
546 };
547 };
548
549 panel@0 {
550 compatible = "samsung,s6e8aa0";
551 reg = <0>;
552 vdd3-supply = <&lcd_vdd3_reg>;
553 vci-supply = <&ldo25_reg>;
554 reset-gpios = <&gpy4 5 0>;
555 power-on-delay= <50>;
556 reset-delay = <100>;
557 init-delay = <100>;
558 flip-horizontal;
559 flip-vertical;
560 panel-width-mm = <58>;
561 panel-height-mm = <103>;
562
563 display-timings {
564 timing-0 {
565 clock-frequency = <0>;
566 hactive = <720>;
567 vactive = <1280>;
568 hfront-porch = <5>;
569 hback-porch = <5>;
570 hsync-len = <5>;
571 vfront-porch = <13>;
572 vback-porch = <1>;
573 vsync-len = <2>;
574 };
575 };
576
577 port {
578 dsi_in: endpoint {
579 remote-endpoint = <&dsi_out>;
580 };
581 };
582 };
583 };
584
585 fimd@11c00000 {
586 status = "okay";
587 };
588
514 camera { 589 camera {
515 pinctrl-0 = <&cam_port_b_clk_active>; 590 pinctrl-0 = <&cam_port_b_clk_active>;
516 pinctrl-names = "default"; 591 pinctrl-names = "default";
@@ -589,4 +664,20 @@
589 }; 664 };
590 }; 665 };
591 }; 666 };
667
668 thermistor-ap@0 {
669 compatible = "ntc,ncp15wb473";
670 pullup-uv = <1800000>; /* VCC_1.8V_AP */
671 pullup-ohm = <100000>; /* 100K */
672 pulldown-ohm = <100000>; /* 100K */
673 io-channels = <&adc 1>; /* AP temperature */
674 };
675
676 thermistor-battery@1 {
677 compatible = "ntc,ncp15wb473";
678 pullup-uv = <1800000>; /* VCC_1.8V_AP */
679 pullup-ohm = <100000>; /* 100K */
680 pulldown-ohm = <100000>; /* 100K */
681 io-channels = <&adc 2>; /* Battery temperature */
682 };
592}; 683};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 87b339c739de..15d3c0ac2f5f 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -20,19 +20,13 @@
20#include "exynos4x12.dtsi" 20#include "exynos4x12.dtsi"
21 21
22/ { 22/ {
23 compatible = "samsung,exynos4412"; 23 compatible = "samsung,exynos4412", "samsung,exynos4";
24 24
25 gic: interrupt-controller@10490000 { 25 combiner: interrupt-controller@10440000 {
26 cpu-offset = <0x4000>;
27 };
28
29 interrupt-controller@10440000 {
30 samsung,combiner-nr = <20>; 26 samsung,combiner-nr = <20>;
31 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
32 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
33 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
34 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
35 <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
36 }; 27 };
37 28
29 gic: interrupt-controller@10490000 {
30 cpu-offset = <0x4000>;
31 };
38}; 32};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 5c412aa14738..c4a9306f8529 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -31,6 +31,12 @@
31 mshc0 = &mshc_0; 31 mshc0 = &mshc_0;
32 }; 32 };
33 33
34 pmu {
35 compatible = "arm,cortex-a9-pmu";
36 interrupt-parent = <&combiner>;
37 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
38 };
39
34 pd_isp: isp-power-domain@10023CA0 { 40 pd_isp: isp-power-domain@10023CA0 {
35 compatible = "samsung,exynos4210-pd"; 41 compatible = "samsung,exynos4210-pd";
36 reg = <0x10023CA0 0x20>; 42 reg = <0x10023CA0 0x20>;
@@ -47,7 +53,7 @@
47 reg = <0x10050000 0x800>; 53 reg = <0x10050000 0x800>;
48 interrupt-parent = <&mct_map>; 54 interrupt-parent = <&mct_map>;
49 interrupts = <0>, <1>, <2>, <3>, <4>; 55 interrupts = <0>, <1>, <2>, <3>, <4>;
50 clocks = <&clock 3>, <&clock 344>; 56 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
51 clock-names = "fin_pll", "mct"; 57 clock-names = "fin_pll", "mct";
52 58
53 mct_map: mct-map { 59 mct_map: mct-map {
@@ -62,6 +68,14 @@
62 }; 68 };
63 }; 69 };
64 70
71 combiner: interrupt-controller@10440000 {
72 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
73 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
74 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
75 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
76 <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
77 };
78
65 pinctrl_0: pinctrl@11400000 { 79 pinctrl_0: pinctrl@11400000 {
66 compatible = "samsung,exynos4x12-pinctrl"; 80 compatible = "samsung,exynos4x12-pinctrl";
67 reg = <0x11400000 0x1000>; 81 reg = <0x11400000 0x1000>;
@@ -80,6 +94,18 @@
80 }; 94 };
81 }; 95 };
82 96
97 adc: adc@126C0000 {
98 compatible = "samsung,exynos-adc-v1";
99 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
100 interrupt-parent = <&combiner>;
101 interrupts = <10 3>;
102 clocks = <&clock CLK_TSADC>;
103 clock-names = "adc";
104 #io-channel-cells = <1>;
105 io-channel-ranges;
106 status = "disabled";
107 };
108
83 pinctrl_2: pinctrl@03860000 { 109 pinctrl_2: pinctrl@03860000 {
84 compatible = "samsung,exynos4x12-pinctrl"; 110 compatible = "samsung,exynos4x12-pinctrl";
85 reg = <0x03860000 0x1000>; 111 reg = <0x03860000 0x1000>;
@@ -97,13 +123,14 @@
97 compatible = "samsung,exynos4212-g2d"; 123 compatible = "samsung,exynos4212-g2d";
98 reg = <0x10800000 0x1000>; 124 reg = <0x10800000 0x1000>;
99 interrupts = <0 89 0>; 125 interrupts = <0 89 0>;
100 clocks = <&clock 177>, <&clock 277>; 126 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
101 clock-names = "sclk_fimg2d", "fimg2d"; 127 clock-names = "sclk_fimg2d", "fimg2d";
102 status = "disabled"; 128 status = "disabled";
103 }; 129 };
104 130
105 camera { 131 camera {
106 clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>; 132 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
133 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
107 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 134 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
108 135
109 fimc_0: fimc@11800000 { 136 fimc_0: fimc@11800000 {
@@ -145,7 +172,7 @@
145 reg = <0x12390000 0x1000>; 172 reg = <0x12390000 0x1000>;
146 interrupts = <0 105 0>; 173 interrupts = <0 105 0>;
147 samsung,power-domain = <&pd_isp>; 174 samsung,power-domain = <&pd_isp>;
148 clocks = <&clock 353>; 175 clocks = <&clock CLK_FIMC_LITE0>;
149 clock-names = "flite"; 176 clock-names = "flite";
150 status = "disabled"; 177 status = "disabled";
151 }; 178 };
@@ -155,7 +182,7 @@
155 reg = <0x123A0000 0x1000>; 182 reg = <0x123A0000 0x1000>;
156 interrupts = <0 106 0>; 183 interrupts = <0 106 0>;
157 samsung,power-domain = <&pd_isp>; 184 samsung,power-domain = <&pd_isp>;
158 clocks = <&clock 354>; 185 clocks = <&clock CLK_FIMC_LITE1>;
159 clock-names = "flite"; 186 clock-names = "flite";
160 status = "disabled"; 187 status = "disabled";
161 }; 188 };
@@ -165,12 +192,19 @@
165 reg = <0x12000000 0x260000>; 192 reg = <0x12000000 0x260000>;
166 interrupts = <0 90 0>, <0 95 0>; 193 interrupts = <0 90 0>, <0 95 0>;
167 samsung,power-domain = <&pd_isp>; 194 samsung,power-domain = <&pd_isp>;
168 clocks = <&clock 353>, <&clock 354>, <&clock 355>, 195 clocks = <&clock CLK_FIMC_LITE0>,
169 <&clock 356>, <&clock 17>, <&clock 357>, 196 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
170 <&clock 358>, <&clock 359>, <&clock 360>, 197 <&clock CLK_PPMUISPMX>,
171 <&clock 450>,<&clock 451>, <&clock 452>, 198 <&clock CLK_MOUT_MPLL_USER_T>,
172 <&clock 453>, <&clock 176>, <&clock 13>, 199 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
173 <&clock 454>, <&clock 395>, <&clock 455>; 200 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
201 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
202 <&clock CLK_DIV_MCUISP0>,
203 <&clock CLK_DIV_MCUISP1>,
204 <&clock CLK_SCLK_UART_ISP>,
205 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
206 <&clock CLK_ACLK400_MCUISP>,
207 <&clock CLK_DIV_ACLK400_MCUISP>;
174 clock-names = "lite0", "lite1", "ppmuispx", 208 clock-names = "lite0", "lite1", "ppmuispx",
175 "ppmuispmx", "mpll", "isp", 209 "ppmuispmx", "mpll", "isp",
176 "drc", "fd", "mcuisp", 210 "drc", "fd", "mcuisp",
@@ -190,7 +224,7 @@
190 i2c1_isp: i2c-isp@12140000 { 224 i2c1_isp: i2c-isp@12140000 {
191 compatible = "samsung,exynos4212-i2c-isp"; 225 compatible = "samsung,exynos4212-i2c-isp";
192 reg = <0x12140000 0x100>; 226 reg = <0x12140000 0x100>;
193 clocks = <&clock 370>; 227 clocks = <&clock CLK_I2C1_ISP>;
194 clock-names = "i2c_isp"; 228 clock-names = "i2c_isp";
195 #address-cells = <1>; 229 #address-cells = <1>;
196 #size-cells = <0>; 230 #size-cells = <0>;
@@ -205,7 +239,7 @@
205 #address-cells = <1>; 239 #address-cells = <1>;
206 #size-cells = <0>; 240 #size-cells = <0>;
207 fifo-depth = <0x80>; 241 fifo-depth = <0x80>;
208 clocks = <&clock 301>, <&clock 149>; 242 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
209 clock-names = "biu", "ciu"; 243 clock-names = "biu", "ciu";
210 status = "disabled"; 244 status = "disabled";
211 }; 245 };
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 258dca441f36..79d0608d6dcc 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -81,13 +81,6 @@
81 status = "disabled"; 81 status = "disabled";
82 }; 82 };
83 83
84 watchdog {
85 compatible = "samsung,s3c2410-wdt";
86 reg = <0x101D0000 0x100>;
87 interrupts = <0 42 0>;
88 status = "disabled";
89 };
90
91 fimd@14400000 { 84 fimd@14400000 {
92 compatible = "samsung,exynos5250-fimd"; 85 compatible = "samsung,exynos5250-fimd";
93 interrupt-parent = <&combiner>; 86 interrupt-parent = <&combiner>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index b42e658876e5..090f9830b129 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -15,7 +15,7 @@
15 15
16/ { 16/ {
17 model = "Insignal Arndale evaluation board based on EXYNOS5250"; 17 model = "Insignal Arndale evaluation board based on EXYNOS5250";
18 compatible = "insignal,arndale", "samsung,exynos5250"; 18 compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";
19 19
20 memory { 20 memory {
21 reg = <0x40000000 0x80000000>; 21 reg = <0x40000000 0x80000000>;
@@ -25,6 +25,10 @@
25 bootargs = "console=ttySAC2,115200"; 25 bootargs = "console=ttySAC2,115200";
26 }; 26 };
27 27
28 rtc@101E0000 {
29 status = "okay";
30 };
31
28 codec@11000000 { 32 codec@11000000 {
29 samsung,mfc-r = <0x43000000 0x800000>; 33 samsung,mfc-r = <0x43000000 0x800000>;
30 samsung,mfc-l = <0x51000000 0x800000>; 34 samsung,mfc-l = <0x51000000 0x800000>;
@@ -287,6 +291,7 @@
287 regulator-name = "vdd_g3d"; 291 regulator-name = "vdd_g3d";
288 regulator-min-microvolt = <1000000>; 292 regulator-min-microvolt = <1000000>;
289 regulator-max-microvolt = <1000000>; 293 regulator-max-microvolt = <1000000>;
294 regulator-always-on;
290 regulator-boot-on; 295 regulator-boot-on;
291 op_mode = <1>; 296 op_mode = <1>;
292 }; 297 };
@@ -370,6 +375,27 @@
370 }; 375 };
371 }; 376 };
372 377
378 i2c@121D0000 {
379 status = "okay";
380 samsung,i2c-sda-delay = <100>;
381 samsung,i2c-max-bus-freq = <40000>;
382 samsung,i2c-slave-addr = <0x38>;
383
384 sata_phy_i2c:sata-phy@38 {
385 compatible = "samsung,exynos-sataphy-i2c";
386 reg = <0x38>;
387 };
388 };
389
390 sata@122F0000 {
391 status = "okay";
392 };
393
394 sata-phy@12170000 {
395 status = "okay";
396 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
397 };
398
373 mmc_0: mmc@12200000 { 399 mmc_0: mmc@12200000 {
374 status = "okay"; 400 status = "okay";
375 num-slots = <1>; 401 num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e69837c435c..a794a705d404 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -14,7 +14,7 @@
14 14
15/ { 15/ {
16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; 16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
17 compatible = "samsung,smdk5250", "samsung,exynos5250"; 17 compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
18 18
19 aliases { 19 aliases {
20 }; 20 };
@@ -27,6 +27,10 @@
27 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; 27 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
28 }; 28 };
29 29
30 rtc@101E0000 {
31 status = "okay";
32 };
33
30 i2c@12C60000 { 34 i2c@12C60000 {
31 samsung,i2c-sda-delay = <100>; 35 samsung,i2c-sda-delay = <100>;
32 samsung,i2c-max-bus-freq = <20000>; 36 samsung,i2c-max-bus-freq = <20000>;
@@ -36,6 +40,148 @@
36 compatible = "samsung,s524ad0xd1"; 40 compatible = "samsung,s524ad0xd1";
37 reg = <0x50>; 41 reg = <0x50>;
38 }; 42 };
43
44 max77686@09 {
45 compatible = "maxim,max77686";
46 reg = <0x09>;
47
48 voltage-regulators {
49 ldo1_reg: LDO1 {
50 regulator-name = "P1.0V_LDO_OUT1";
51 regulator-min-microvolt = <1000000>;
52 regulator-max-microvolt = <1000000>;
53 regulator-always-on;
54 };
55
56 ldo2_reg: LDO2 {
57 regulator-name = "P1.2V_LDO_OUT2";
58 regulator-min-microvolt = <1200000>;
59 regulator-max-microvolt = <1200000>;
60 regulator-always-on;
61 };
62
63 ldo3_reg: LDO3 {
64 regulator-name = "P1.8V_LDO_OUT3";
65 regulator-min-microvolt = <1800000>;
66 regulator-max-microvolt = <1800000>;
67 regulator-always-on;
68 };
69
70 ldo4_reg: LDO4 {
71 regulator-name = "P2.8V_LDO_OUT4";
72 regulator-min-microvolt = <2800000>;
73 regulator-max-microvolt = <2800000>;
74 };
75
76 ldo5_reg: LDO5 {
77 regulator-name = "P1.8V_LDO_OUT5";
78 regulator-min-microvolt = <1800000>;
79 regulator-max-microvolt = <1800000>;
80 };
81
82 ldo6_reg: LDO6 {
83 regulator-name = "P1.1V_LDO_OUT6";
84 regulator-min-microvolt = <1100000>;
85 regulator-max-microvolt = <1100000>;
86 regulator-always-on;
87 };
88
89 ldo7_reg: LDO7 {
90 regulator-name = "P1.1V_LDO_OUT7";
91 regulator-min-microvolt = <1100000>;
92 regulator-max-microvolt = <1100000>;
93 regulator-always-on;
94 };
95
96 ldo8_reg: LDO8 {
97 regulator-name = "P1.0V_LDO_OUT8";
98 regulator-min-microvolt = <1000000>;
99 regulator-max-microvolt = <1000000>;
100 };
101
102 ldo10_reg: LDO10 {
103 regulator-name = "P1.8V_LDO_OUT10";
104 regulator-min-microvolt = <1800000>;
105 regulator-max-microvolt = <1800000>;
106 };
107
108 ldo11_reg: LDO11 {
109 regulator-name = "P1.8V_LDO_OUT11";
110 regulator-min-microvolt = <1800000>;
111 regulator-max-microvolt = <1800000>;
112 };
113
114 ldo12_reg: LDO12 {
115 regulator-name = "P3.0V_LDO_OUT12";
116 regulator-min-microvolt = <3000000>;
117 regulator-max-microvolt = <3000000>;
118 };
119
120 ldo13_reg: LDO13 {
121 regulator-name = "P1.8V_LDO_OUT13";
122 regulator-min-microvolt = <1800000>;
123 regulator-max-microvolt = <1800000>;
124 };
125
126 ldo14_reg: LDO14 {
127 regulator-name = "P1.8V_LDO_OUT14";
128 regulator-min-microvolt = <1800000>;
129 regulator-max-microvolt = <1800000>;
130 };
131
132 ldo15_reg: LDO15 {
133 regulator-name = "P1.0V_LDO_OUT15";
134 regulator-min-microvolt = <1000000>;
135 regulator-max-microvolt = <1000000>;
136 };
137
138 ldo16_reg: LDO16 {
139 regulator-name = "P1.8V_LDO_OUT16";
140 regulator-min-microvolt = <1800000>;
141 regulator-max-microvolt = <1800000>;
142 };
143
144 buck1_reg: BUCK1 {
145 regulator-name = "vdd_mif";
146 regulator-min-microvolt = <950000>;
147 regulator-max-microvolt = <1300000>;
148 regulator-always-on;
149 regulator-boot-on;
150 };
151
152 buck2_reg: BUCK2 {
153 regulator-name = "vdd_arm";
154 regulator-min-microvolt = <850000>;
155 regulator-max-microvolt = <1350000>;
156 regulator-always-on;
157 regulator-boot-on;
158 };
159
160 buck3_reg: BUCK3 {
161 regulator-name = "vdd_int";
162 regulator-min-microvolt = <900000>;
163 regulator-max-microvolt = <1200000>;
164 regulator-always-on;
165 regulator-boot-on;
166 };
167
168 buck4_reg: BUCK4 {
169 regulator-name = "vdd_g3d";
170 regulator-min-microvolt = <850000>;
171 regulator-max-microvolt = <1300000>;
172 regulator-always-on;
173 regulator-boot-on;
174 };
175
176 buck5_reg: BUCK5 {
177 regulator-name = "P1.8V_BUCK_OUT5";
178 regulator-min-microvolt = <1800000>;
179 regulator-max-microvolt = <1800000>;
180 regulator-always-on;
181 regulator-boot-on;
182 };
183 };
184 };
39 }; 185 };
40 186
41 vdd: fixed-regulator@0 { 187 vdd: fixed-regulator@0 {
@@ -96,16 +242,12 @@
96 samsung,i2c-slave-addr = <0x38>; 242 samsung,i2c-slave-addr = <0x38>;
97 status = "okay"; 243 status = "okay";
98 244
99 sata-phy { 245 sata_phy_i2c:sata-phy@38 {
100 compatible = "samsung,sata-phy"; 246 compatible = "samsung,exynos-sataphy-i2c";
101 reg = <0x38>; 247 reg = <0x38>;
102 }; 248 };
103 }; 249 };
104 250
105 sata@122F0000 {
106 samsung,sata-freq = <66>;
107 };
108
109 i2c@12C80000 { 251 i2c@12C80000 {
110 samsung,i2c-sda-delay = <100>; 252 samsung,i2c-sda-delay = <100>;
111 samsung,i2c-max-bus-freq = <66000>; 253 samsung,i2c-max-bus-freq = <66000>;
@@ -128,6 +270,15 @@
128 }; 270 };
129 }; 271 };
130 272
273 sata@122F0000 {
274 status = "okay";
275 };
276
277 sata-phy@12170000 {
278 status = "okay";
279 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
280 };
281
131 mmc@12200000 { 282 mmc@12200000 {
132 status = "okay"; 283 status = "okay";
133 num-slots = <1>; 284 num-slots = <1>;
@@ -164,10 +315,6 @@
164 }; 315 };
165 }; 316 };
166 317
167 spi_0: spi@12d20000 {
168 status = "disabled";
169 };
170
171 spi_1: spi@12d30000 { 318 spi_1: spi@12d30000 {
172 status = "okay"; 319 status = "okay";
173 320
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 7e45eea2d78f..1ce1088a00fb 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -14,12 +14,16 @@
14 14
15/ { 15/ {
16 model = "Google Snow"; 16 model = "Google Snow";
17 compatible = "google,snow", "samsung,exynos5250"; 17 compatible = "google,snow", "samsung,exynos5250", "samsung,exynos5";
18 18
19 aliases { 19 aliases {
20 i2c104 = &i2c_104; 20 i2c104 = &i2c_104;
21 }; 21 };
22 22
23 rtc@101E0000 {
24 status = "okay";
25 };
26
23 pinctrl@11400000 { 27 pinctrl@11400000 {
24 sd3_clk: sd3-clk { 28 sd3_clk: sd3-clk {
25 samsung,pin-drv = <0>; 29 samsung,pin-drv = <0>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b7dec41e32af..37423314a028 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,13 +17,14 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20#include <dt-bindings/clock/exynos5250.h>
20#include "exynos5.dtsi" 21#include "exynos5.dtsi"
21#include "exynos5250-pinctrl.dtsi" 22#include "exynos5250-pinctrl.dtsi"
22 23
23#include <dt-bindings/clk/exynos-audss-clk.h> 24#include <dt-bindings/clock/exynos-audss-clk.h>
24 25
25/ { 26/ {
26 compatible = "samsung,exynos5250"; 27 compatible = "samsung,exynos5250", "samsung,exynos5";
27 28
28 aliases { 29 aliases {
29 spi0 = &spi_0; 30 spi0 = &spi_0;
@@ -46,6 +47,7 @@
46 i2c6 = &i2c_6; 47 i2c6 = &i2c_6;
47 i2c7 = &i2c_7; 48 i2c7 = &i2c_7;
48 i2c8 = &i2c_8; 49 i2c8 = &i2c_8;
50 i2c9 = &i2c_9;
49 pinctrl0 = &pinctrl_0; 51 pinctrl0 = &pinctrl_0;
50 pinctrl1 = &pinctrl_1; 52 pinctrl1 = &pinctrl_1;
51 pinctrl2 = &pinctrl_2; 53 pinctrl2 = &pinctrl_2;
@@ -90,7 +92,8 @@
90 compatible = "samsung,exynos5250-audss-clock"; 92 compatible = "samsung,exynos5250-audss-clock";
91 reg = <0x03810000 0x0C>; 93 reg = <0x03810000 0x0C>;
92 #clock-cells = <1>; 94 #clock-cells = <1>;
93 clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>; 95 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
96 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
94 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 97 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
95 }; 98 };
96 99
@@ -115,7 +118,7 @@
115 interrupt-parent = <&mct_map>; 118 interrupt-parent = <&mct_map>;
116 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 119 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
117 <4 0>, <5 0>; 120 <4 0>, <5 0>;
118 clocks = <&clock 1>, <&clock 335>; 121 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
119 clock-names = "fin_pll", "mct"; 122 clock-names = "fin_pll", "mct";
120 123
121 mct_map: mct-map { 124 mct_map: mct-map {
@@ -167,16 +170,25 @@
167 interrupts = <0 47 0>; 170 interrupts = <0 47 0>;
168 }; 171 };
169 172
170 watchdog { 173 pmu_system_controller: system-controller@10040000 {
171 clocks = <&clock 336>; 174 compatible = "samsung,exynos5250-pmu", "syscon";
175 reg = <0x10040000 0x5000>;
176 };
177
178 watchdog@101D0000 {
179 compatible = "samsung,exynos5250-wdt";
180 reg = <0x101D0000 0x100>;
181 interrupts = <0 42 0>;
182 clocks = <&clock CLK_WDT>;
172 clock-names = "watchdog"; 183 clock-names = "watchdog";
184 samsung,syscon-phandle = <&pmu_system_controller>;
173 }; 185 };
174 186
175 g2d@10850000 { 187 g2d@10850000 {
176 compatible = "samsung,exynos5250-g2d"; 188 compatible = "samsung,exynos5250-g2d";
177 reg = <0x10850000 0x1000>; 189 reg = <0x10850000 0x1000>;
178 interrupts = <0 91 0>; 190 interrupts = <0 91 0>;
179 clocks = <&clock 345>; 191 clocks = <&clock CLK_G2D>;
180 clock-names = "fimg2d"; 192 clock-names = "fimg2d";
181 }; 193 };
182 194
@@ -185,55 +197,64 @@
185 reg = <0x11000000 0x10000>; 197 reg = <0x11000000 0x10000>;
186 interrupts = <0 96 0>; 198 interrupts = <0 96 0>;
187 samsung,power-domain = <&pd_mfc>; 199 samsung,power-domain = <&pd_mfc>;
188 clocks = <&clock 266>; 200 clocks = <&clock CLK_MFC>;
189 clock-names = "mfc"; 201 clock-names = "mfc";
190 }; 202 };
191 203
192 rtc@101E0000 { 204 rtc@101E0000 {
193 clocks = <&clock 337>; 205 clocks = <&clock CLK_RTC>;
194 clock-names = "rtc"; 206 clock-names = "rtc";
195 status = "okay"; 207 status = "disabled";
196 }; 208 };
197 209
198 tmu@10060000 { 210 tmu@10060000 {
199 compatible = "samsung,exynos5250-tmu"; 211 compatible = "samsung,exynos5250-tmu";
200 reg = <0x10060000 0x100>; 212 reg = <0x10060000 0x100>;
201 interrupts = <0 65 0>; 213 interrupts = <0 65 0>;
202 clocks = <&clock 338>; 214 clocks = <&clock CLK_TMU>;
203 clock-names = "tmu_apbif"; 215 clock-names = "tmu_apbif";
204 }; 216 };
205 217
206 serial@12C00000 { 218 serial@12C00000 {
207 clocks = <&clock 289>, <&clock 146>; 219 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
208 clock-names = "uart", "clk_uart_baud0"; 220 clock-names = "uart", "clk_uart_baud0";
209 }; 221 };
210 222
211 serial@12C10000 { 223 serial@12C10000 {
212 clocks = <&clock 290>, <&clock 147>; 224 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
213 clock-names = "uart", "clk_uart_baud0"; 225 clock-names = "uart", "clk_uart_baud0";
214 }; 226 };
215 227
216 serial@12C20000 { 228 serial@12C20000 {
217 clocks = <&clock 291>, <&clock 148>; 229 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
218 clock-names = "uart", "clk_uart_baud0"; 230 clock-names = "uart", "clk_uart_baud0";
219 }; 231 };
220 232
221 serial@12C30000 { 233 serial@12C30000 {
222 clocks = <&clock 292>, <&clock 149>; 234 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
223 clock-names = "uart", "clk_uart_baud0"; 235 clock-names = "uart", "clk_uart_baud0";
224 }; 236 };
225 237
226 sata@122F0000 { 238 sata@122F0000 {
227 compatible = "samsung,exynos5-sata-ahci"; 239 compatible = "snps,dwc-ahci";
240 samsung,sata-freq = <66>;
228 reg = <0x122F0000 0x1ff>; 241 reg = <0x122F0000 0x1ff>;
229 interrupts = <0 115 0>; 242 interrupts = <0 115 0>;
230 clocks = <&clock 277>, <&clock 143>; 243 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
231 clock-names = "sata", "sclk_sata"; 244 clock-names = "sata", "sclk_sata";
245 phys = <&sata_phy>;
246 phy-names = "sata-phy";
247 status = "disabled";
232 }; 248 };
233 249
234 sata-phy@12170000 { 250 sata_phy: sata-phy@12170000 {
235 compatible = "samsung,exynos5-sata-phy"; 251 compatible = "samsung,exynos5250-sata-phy";
236 reg = <0x12170000 0x1ff>; 252 reg = <0x12170000 0x1ff>;
253 clocks = <&clock 287>;
254 clock-names = "sata_phyctrl";
255 #phy-cells = <0>;
256 samsung,syscon-phandle = <&pmu_system_controller>;
257 status = "disabled";
237 }; 258 };
238 259
239 i2c_0: i2c@12C60000 { 260 i2c_0: i2c@12C60000 {
@@ -242,7 +263,7 @@
242 interrupts = <0 56 0>; 263 interrupts = <0 56 0>;
243 #address-cells = <1>; 264 #address-cells = <1>;
244 #size-cells = <0>; 265 #size-cells = <0>;
245 clocks = <&clock 294>; 266 clocks = <&clock CLK_I2C0>;
246 clock-names = "i2c"; 267 clock-names = "i2c";
247 pinctrl-names = "default"; 268 pinctrl-names = "default";
248 pinctrl-0 = <&i2c0_bus>; 269 pinctrl-0 = <&i2c0_bus>;
@@ -255,7 +276,7 @@
255 interrupts = <0 57 0>; 276 interrupts = <0 57 0>;
256 #address-cells = <1>; 277 #address-cells = <1>;
257 #size-cells = <0>; 278 #size-cells = <0>;
258 clocks = <&clock 295>; 279 clocks = <&clock CLK_I2C1>;
259 clock-names = "i2c"; 280 clock-names = "i2c";
260 pinctrl-names = "default"; 281 pinctrl-names = "default";
261 pinctrl-0 = <&i2c1_bus>; 282 pinctrl-0 = <&i2c1_bus>;
@@ -268,7 +289,7 @@
268 interrupts = <0 58 0>; 289 interrupts = <0 58 0>;
269 #address-cells = <1>; 290 #address-cells = <1>;
270 #size-cells = <0>; 291 #size-cells = <0>;
271 clocks = <&clock 296>; 292 clocks = <&clock CLK_I2C2>;
272 clock-names = "i2c"; 293 clock-names = "i2c";
273 pinctrl-names = "default"; 294 pinctrl-names = "default";
274 pinctrl-0 = <&i2c2_bus>; 295 pinctrl-0 = <&i2c2_bus>;
@@ -281,7 +302,7 @@
281 interrupts = <0 59 0>; 302 interrupts = <0 59 0>;
282 #address-cells = <1>; 303 #address-cells = <1>;
283 #size-cells = <0>; 304 #size-cells = <0>;
284 clocks = <&clock 297>; 305 clocks = <&clock CLK_I2C3>;
285 clock-names = "i2c"; 306 clock-names = "i2c";
286 pinctrl-names = "default"; 307 pinctrl-names = "default";
287 pinctrl-0 = <&i2c3_bus>; 308 pinctrl-0 = <&i2c3_bus>;
@@ -294,7 +315,7 @@
294 interrupts = <0 60 0>; 315 interrupts = <0 60 0>;
295 #address-cells = <1>; 316 #address-cells = <1>;
296 #size-cells = <0>; 317 #size-cells = <0>;
297 clocks = <&clock 298>; 318 clocks = <&clock CLK_I2C4>;
298 clock-names = "i2c"; 319 clock-names = "i2c";
299 pinctrl-names = "default"; 320 pinctrl-names = "default";
300 pinctrl-0 = <&i2c4_bus>; 321 pinctrl-0 = <&i2c4_bus>;
@@ -307,7 +328,7 @@
307 interrupts = <0 61 0>; 328 interrupts = <0 61 0>;
308 #address-cells = <1>; 329 #address-cells = <1>;
309 #size-cells = <0>; 330 #size-cells = <0>;
310 clocks = <&clock 299>; 331 clocks = <&clock CLK_I2C5>;
311 clock-names = "i2c"; 332 clock-names = "i2c";
312 pinctrl-names = "default"; 333 pinctrl-names = "default";
313 pinctrl-0 = <&i2c5_bus>; 334 pinctrl-0 = <&i2c5_bus>;
@@ -320,7 +341,7 @@
320 interrupts = <0 62 0>; 341 interrupts = <0 62 0>;
321 #address-cells = <1>; 342 #address-cells = <1>;
322 #size-cells = <0>; 343 #size-cells = <0>;
323 clocks = <&clock 300>; 344 clocks = <&clock CLK_I2C6>;
324 clock-names = "i2c"; 345 clock-names = "i2c";
325 pinctrl-names = "default"; 346 pinctrl-names = "default";
326 pinctrl-0 = <&i2c6_bus>; 347 pinctrl-0 = <&i2c6_bus>;
@@ -333,7 +354,7 @@
333 interrupts = <0 63 0>; 354 interrupts = <0 63 0>;
334 #address-cells = <1>; 355 #address-cells = <1>;
335 #size-cells = <0>; 356 #size-cells = <0>;
336 clocks = <&clock 301>; 357 clocks = <&clock CLK_I2C7>;
337 clock-names = "i2c"; 358 clock-names = "i2c";
338 pinctrl-names = "default"; 359 pinctrl-names = "default";
339 pinctrl-0 = <&i2c7_bus>; 360 pinctrl-0 = <&i2c7_bus>;
@@ -346,17 +367,17 @@
346 interrupts = <0 64 0>; 367 interrupts = <0 64 0>;
347 #address-cells = <1>; 368 #address-cells = <1>;
348 #size-cells = <0>; 369 #size-cells = <0>;
349 clocks = <&clock 302>; 370 clocks = <&clock CLK_I2C_HDMI>;
350 clock-names = "i2c"; 371 clock-names = "i2c";
351 status = "disabled"; 372 status = "disabled";
352 }; 373 };
353 374
354 i2c@121D0000 { 375 i2c_9: i2c@121D0000 {
355 compatible = "samsung,exynos5-sata-phy-i2c"; 376 compatible = "samsung,exynos5-sata-phy-i2c";
356 reg = <0x121D0000 0x100>; 377 reg = <0x121D0000 0x100>;
357 #address-cells = <1>; 378 #address-cells = <1>;
358 #size-cells = <0>; 379 #size-cells = <0>;
359 clocks = <&clock 288>; 380 clocks = <&clock CLK_SATA_PHYI2C>;
360 clock-names = "i2c"; 381 clock-names = "i2c";
361 status = "disabled"; 382 status = "disabled";
362 }; 383 };
@@ -371,7 +392,7 @@
371 dma-names = "tx", "rx"; 392 dma-names = "tx", "rx";
372 #address-cells = <1>; 393 #address-cells = <1>;
373 #size-cells = <0>; 394 #size-cells = <0>;
374 clocks = <&clock 304>, <&clock 154>; 395 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
375 clock-names = "spi", "spi_busclk0"; 396 clock-names = "spi", "spi_busclk0";
376 pinctrl-names = "default"; 397 pinctrl-names = "default";
377 pinctrl-0 = <&spi0_bus>; 398 pinctrl-0 = <&spi0_bus>;
@@ -387,7 +408,7 @@
387 dma-names = "tx", "rx"; 408 dma-names = "tx", "rx";
388 #address-cells = <1>; 409 #address-cells = <1>;
389 #size-cells = <0>; 410 #size-cells = <0>;
390 clocks = <&clock 305>, <&clock 155>; 411 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
391 clock-names = "spi", "spi_busclk0"; 412 clock-names = "spi", "spi_busclk0";
392 pinctrl-names = "default"; 413 pinctrl-names = "default";
393 pinctrl-0 = <&spi1_bus>; 414 pinctrl-0 = <&spi1_bus>;
@@ -403,7 +424,7 @@
403 dma-names = "tx", "rx"; 424 dma-names = "tx", "rx";
404 #address-cells = <1>; 425 #address-cells = <1>;
405 #size-cells = <0>; 426 #size-cells = <0>;
406 clocks = <&clock 306>, <&clock 156>; 427 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
407 clock-names = "spi", "spi_busclk0"; 428 clock-names = "spi", "spi_busclk0";
408 pinctrl-names = "default"; 429 pinctrl-names = "default";
409 pinctrl-0 = <&spi2_bus>; 430 pinctrl-0 = <&spi2_bus>;
@@ -415,7 +436,7 @@
415 #address-cells = <1>; 436 #address-cells = <1>;
416 #size-cells = <0>; 437 #size-cells = <0>;
417 reg = <0x12200000 0x1000>; 438 reg = <0x12200000 0x1000>;
418 clocks = <&clock 280>, <&clock 139>; 439 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
419 clock-names = "biu", "ciu"; 440 clock-names = "biu", "ciu";
420 fifo-depth = <0x80>; 441 fifo-depth = <0x80>;
421 status = "disabled"; 442 status = "disabled";
@@ -427,7 +448,7 @@
427 #address-cells = <1>; 448 #address-cells = <1>;
428 #size-cells = <0>; 449 #size-cells = <0>;
429 reg = <0x12210000 0x1000>; 450 reg = <0x12210000 0x1000>;
430 clocks = <&clock 281>, <&clock 140>; 451 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
431 clock-names = "biu", "ciu"; 452 clock-names = "biu", "ciu";
432 fifo-depth = <0x80>; 453 fifo-depth = <0x80>;
433 status = "disabled"; 454 status = "disabled";
@@ -439,7 +460,7 @@
439 #address-cells = <1>; 460 #address-cells = <1>;
440 #size-cells = <0>; 461 #size-cells = <0>;
441 reg = <0x12220000 0x1000>; 462 reg = <0x12220000 0x1000>;
442 clocks = <&clock 282>, <&clock 141>; 463 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
443 clock-names = "biu", "ciu"; 464 clock-names = "biu", "ciu";
444 fifo-depth = <0x80>; 465 fifo-depth = <0x80>;
445 status = "disabled"; 466 status = "disabled";
@@ -451,7 +472,7 @@
451 interrupts = <0 78 0>; 472 interrupts = <0 78 0>;
452 #address-cells = <1>; 473 #address-cells = <1>;
453 #size-cells = <0>; 474 #size-cells = <0>;
454 clocks = <&clock 283>, <&clock 142>; 475 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
455 clock-names = "biu", "ciu"; 476 clock-names = "biu", "ciu";
456 fifo-depth = <0x80>; 477 fifo-depth = <0x80>;
457 status = "disabled"; 478 status = "disabled";
@@ -481,7 +502,7 @@
481 dmas = <&pdma1 12 502 dmas = <&pdma1 12
482 &pdma1 11>; 503 &pdma1 11>;
483 dma-names = "tx", "rx"; 504 dma-names = "tx", "rx";
484 clocks = <&clock 307>, <&clock 157>; 505 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
485 clock-names = "iis", "i2s_opclk0"; 506 clock-names = "iis", "i2s_opclk0";
486 pinctrl-names = "default"; 507 pinctrl-names = "default";
487 pinctrl-0 = <&i2s1_bus>; 508 pinctrl-0 = <&i2s1_bus>;
@@ -494,7 +515,7 @@
494 dmas = <&pdma0 12 515 dmas = <&pdma0 12
495 &pdma0 11>; 516 &pdma0 11>;
496 dma-names = "tx", "rx"; 517 dma-names = "tx", "rx";
497 clocks = <&clock 308>, <&clock 158>; 518 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
498 clock-names = "iis", "i2s_opclk0"; 519 clock-names = "iis", "i2s_opclk0";
499 pinctrl-names = "default"; 520 pinctrl-names = "default";
500 pinctrl-0 = <&i2s2_bus>; 521 pinctrl-0 = <&i2s2_bus>;
@@ -502,7 +523,7 @@
502 523
503 usb@12000000 { 524 usb@12000000 {
504 compatible = "samsung,exynos5250-dwusb3"; 525 compatible = "samsung,exynos5250-dwusb3";
505 clocks = <&clock 286>; 526 clocks = <&clock CLK_USB3>;
506 clock-names = "usbdrd30"; 527 clock-names = "usbdrd30";
507 #address-cells = <1>; 528 #address-cells = <1>;
508 #size-cells = <1>; 529 #size-cells = <1>;
@@ -519,7 +540,7 @@
519 usb3_phy: usbphy@12100000 { 540 usb3_phy: usbphy@12100000 {
520 compatible = "samsung,exynos5250-usb3phy"; 541 compatible = "samsung,exynos5250-usb3phy";
521 reg = <0x12100000 0x100>; 542 reg = <0x12100000 0x100>;
522 clocks = <&clock 1>, <&clock 286>; 543 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>;
523 clock-names = "ext_xtal", "usbdrd30"; 544 clock-names = "ext_xtal", "usbdrd30";
524 #address-cells = <1>; 545 #address-cells = <1>;
525 #size-cells = <1>; 546 #size-cells = <1>;
@@ -535,7 +556,7 @@
535 reg = <0x12110000 0x100>; 556 reg = <0x12110000 0x100>;
536 interrupts = <0 71 0>; 557 interrupts = <0 71 0>;
537 558
538 clocks = <&clock 285>; 559 clocks = <&clock CLK_USB2>;
539 clock-names = "usbhost"; 560 clock-names = "usbhost";
540 }; 561 };
541 562
@@ -544,14 +565,14 @@
544 reg = <0x12120000 0x100>; 565 reg = <0x12120000 0x100>;
545 interrupts = <0 71 0>; 566 interrupts = <0 71 0>;
546 567
547 clocks = <&clock 285>; 568 clocks = <&clock CLK_USB2>;
548 clock-names = "usbhost"; 569 clock-names = "usbhost";
549 }; 570 };
550 571
551 usb2_phy: usbphy@12130000 { 572 usb2_phy: usbphy@12130000 {
552 compatible = "samsung,exynos5250-usb2phy"; 573 compatible = "samsung,exynos5250-usb2phy";
553 reg = <0x12130000 0x100>; 574 reg = <0x12130000 0x100>;
554 clocks = <&clock 1>, <&clock 285>; 575 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
555 clock-names = "ext_xtal", "usbhost"; 576 clock-names = "ext_xtal", "usbhost";
556 #address-cells = <1>; 577 #address-cells = <1>;
557 #size-cells = <1>; 578 #size-cells = <1>;
@@ -568,7 +589,7 @@
568 reg = <0x12dd0000 0x100>; 589 reg = <0x12dd0000 0x100>;
569 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 590 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
570 #pwm-cells = <3>; 591 #pwm-cells = <3>;
571 clocks = <&clock 311>; 592 clocks = <&clock CLK_PWM>;
572 clock-names = "timers"; 593 clock-names = "timers";
573 }; 594 };
574 595
@@ -583,7 +604,7 @@
583 compatible = "arm,pl330", "arm,primecell"; 604 compatible = "arm,pl330", "arm,primecell";
584 reg = <0x121A0000 0x1000>; 605 reg = <0x121A0000 0x1000>;
585 interrupts = <0 34 0>; 606 interrupts = <0 34 0>;
586 clocks = <&clock 275>; 607 clocks = <&clock CLK_PDMA0>;
587 clock-names = "apb_pclk"; 608 clock-names = "apb_pclk";
588 #dma-cells = <1>; 609 #dma-cells = <1>;
589 #dma-channels = <8>; 610 #dma-channels = <8>;
@@ -594,7 +615,7 @@
594 compatible = "arm,pl330", "arm,primecell"; 615 compatible = "arm,pl330", "arm,primecell";
595 reg = <0x121B0000 0x1000>; 616 reg = <0x121B0000 0x1000>;
596 interrupts = <0 35 0>; 617 interrupts = <0 35 0>;
597 clocks = <&clock 276>; 618 clocks = <&clock CLK_PDMA1>;
598 clock-names = "apb_pclk"; 619 clock-names = "apb_pclk";
599 #dma-cells = <1>; 620 #dma-cells = <1>;
600 #dma-channels = <8>; 621 #dma-channels = <8>;
@@ -605,7 +626,7 @@
605 compatible = "arm,pl330", "arm,primecell"; 626 compatible = "arm,pl330", "arm,primecell";
606 reg = <0x10800000 0x1000>; 627 reg = <0x10800000 0x1000>;
607 interrupts = <0 33 0>; 628 interrupts = <0 33 0>;
608 clocks = <&clock 346>; 629 clocks = <&clock CLK_MDMA0>;
609 clock-names = "apb_pclk"; 630 clock-names = "apb_pclk";
610 #dma-cells = <1>; 631 #dma-cells = <1>;
611 #dma-channels = <8>; 632 #dma-channels = <8>;
@@ -616,7 +637,7 @@
616 compatible = "arm,pl330", "arm,primecell"; 637 compatible = "arm,pl330", "arm,primecell";
617 reg = <0x11C10000 0x1000>; 638 reg = <0x11C10000 0x1000>;
618 interrupts = <0 124 0>; 639 interrupts = <0 124 0>;
619 clocks = <&clock 271>; 640 clocks = <&clock CLK_MDMA1>;
620 clock-names = "apb_pclk"; 641 clock-names = "apb_pclk";
621 #dma-cells = <1>; 642 #dma-cells = <1>;
622 #dma-channels = <8>; 643 #dma-channels = <8>;
@@ -629,7 +650,7 @@
629 reg = <0x13e00000 0x1000>; 650 reg = <0x13e00000 0x1000>;
630 interrupts = <0 85 0>; 651 interrupts = <0 85 0>;
631 samsung,power-domain = <&pd_gsc>; 652 samsung,power-domain = <&pd_gsc>;
632 clocks = <&clock 256>; 653 clocks = <&clock CLK_GSCL0>;
633 clock-names = "gscl"; 654 clock-names = "gscl";
634 }; 655 };
635 656
@@ -638,7 +659,7 @@
638 reg = <0x13e10000 0x1000>; 659 reg = <0x13e10000 0x1000>;
639 interrupts = <0 86 0>; 660 interrupts = <0 86 0>;
640 samsung,power-domain = <&pd_gsc>; 661 samsung,power-domain = <&pd_gsc>;
641 clocks = <&clock 257>; 662 clocks = <&clock CLK_GSCL1>;
642 clock-names = "gscl"; 663 clock-names = "gscl";
643 }; 664 };
644 665
@@ -647,7 +668,7 @@
647 reg = <0x13e20000 0x1000>; 668 reg = <0x13e20000 0x1000>;
648 interrupts = <0 87 0>; 669 interrupts = <0 87 0>;
649 samsung,power-domain = <&pd_gsc>; 670 samsung,power-domain = <&pd_gsc>;
650 clocks = <&clock 258>; 671 clocks = <&clock CLK_GSCL2>;
651 clock-names = "gscl"; 672 clock-names = "gscl";
652 }; 673 };
653 674
@@ -656,7 +677,7 @@
656 reg = <0x13e30000 0x1000>; 677 reg = <0x13e30000 0x1000>;
657 interrupts = <0 88 0>; 678 interrupts = <0 88 0>;
658 samsung,power-domain = <&pd_gsc>; 679 samsung,power-domain = <&pd_gsc>;
659 clocks = <&clock 259>; 680 clocks = <&clock CLK_GSCL3>;
660 clock-names = "gscl"; 681 clock-names = "gscl";
661 }; 682 };
662 683
@@ -664,8 +685,9 @@
664 compatible = "samsung,exynos4212-hdmi"; 685 compatible = "samsung,exynos4212-hdmi";
665 reg = <0x14530000 0x70000>; 686 reg = <0x14530000 0x70000>;
666 interrupts = <0 95 0>; 687 interrupts = <0 95 0>;
667 clocks = <&clock 344>, <&clock 136>, <&clock 137>, 688 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
668 <&clock 159>, <&clock 1024>; 689 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
690 <&clock CLK_MOUT_HDMI>;
669 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 691 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
670 "sclk_hdmiphy", "mout_hdmi"; 692 "sclk_hdmiphy", "mout_hdmi";
671 }; 693 };
@@ -674,7 +696,7 @@
674 compatible = "samsung,exynos5250-mixer"; 696 compatible = "samsung,exynos5250-mixer";
675 reg = <0x14450000 0x10000>; 697 reg = <0x14450000 0x10000>;
676 interrupts = <0 94 0>; 698 interrupts = <0 94 0>;
677 clocks = <&clock 343>, <&clock 136>; 699 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
678 clock-names = "mixer", "sclk_hdmi"; 700 clock-names = "mixer", "sclk_hdmi";
679 }; 701 };
680 702
@@ -685,14 +707,14 @@
685 }; 707 };
686 708
687 dp-controller@145B0000 { 709 dp-controller@145B0000 {
688 clocks = <&clock 342>; 710 clocks = <&clock CLK_DP>;
689 clock-names = "dp"; 711 clock-names = "dp";
690 phys = <&dp_phy>; 712 phys = <&dp_phy>;
691 phy-names = "dp"; 713 phy-names = "dp";
692 }; 714 };
693 715
694 fimd@14400000 { 716 fimd@14400000 {
695 clocks = <&clock 133>, <&clock 339>; 717 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
696 clock-names = "sclk_fimd", "fimd"; 718 clock-names = "sclk_fimd", "fimd";
697 }; 719 };
698 720
@@ -700,10 +722,18 @@
700 compatible = "samsung,exynos-adc-v1"; 722 compatible = "samsung,exynos-adc-v1";
701 reg = <0x12D10000 0x100>, <0x10040718 0x4>; 723 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
702 interrupts = <0 106 0>; 724 interrupts = <0 106 0>;
703 clocks = <&clock 303>; 725 clocks = <&clock CLK_ADC>;
704 clock-names = "adc"; 726 clock-names = "adc";
705 #io-channel-cells = <1>; 727 #io-channel-cells = <1>;
706 io-channel-ranges; 728 io-channel-ranges;
707 status = "disabled"; 729 status = "disabled";
708 }; 730 };
731
732 sss@10830000 {
733 compatible = "samsung,exynos4210-secss";
734 reg = <0x10830000 0x10000>;
735 interrupts = <0 112 0>;
736 clocks = <&clock 348>;
737 clock-names = "secss";
738 };
709}; 739};
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 7340745ff979..80a3bf4c5986 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -11,10 +11,12 @@
11 11
12/dts-v1/; 12/dts-v1/;
13#include "exynos5420.dtsi" 13#include "exynos5420.dtsi"
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/input/input.h>
14 16
15/ { 17/ {
16 model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; 18 model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
17 compatible = "insignal,arndale-octa", "samsung,exynos5420"; 19 compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
18 20
19 memory { 21 memory {
20 reg = <0x20000000 0x80000000>; 22 reg = <0x20000000 0x80000000>;
@@ -31,6 +33,10 @@
31 }; 33 };
32 }; 34 };
33 35
36 rtc@101E0000 {
37 status = "okay";
38 };
39
34 mmc@12200000 { 40 mmc@12200000 {
35 status = "okay"; 41 status = "okay";
36 broken-cd; 42 broken-cd;
@@ -41,6 +47,7 @@
41 samsung,dw-mshc-ddr-timing = <0 2>; 47 samsung,dw-mshc-ddr-timing = <0 2>;
42 pinctrl-names = "default"; 48 pinctrl-names = "default";
43 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; 49 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
50 vmmc-supply = <&ldo10_reg>;
44 51
45 slot@0 { 52 slot@0 {
46 reg = <0>; 53 reg = <0>;
@@ -57,10 +64,316 @@
57 samsung,dw-mshc-ddr-timing = <1 2>; 64 samsung,dw-mshc-ddr-timing = <1 2>;
58 pinctrl-names = "default"; 65 pinctrl-names = "default";
59 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 66 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
67 vmmc-supply = <&ldo10_reg>;
60 68
61 slot@0 { 69 slot@0 {
62 reg = <0>; 70 reg = <0>;
63 bus-width = <4>; 71 bus-width = <4>;
64 }; 72 };
65 }; 73 };
74
75 hsi2c_4: i2c@12CA0000 {
76 status = "okay";
77
78 s2mps11_pmic@66 {
79 compatible = "samsung,s2mps11-pmic";
80 reg = <0x66>;
81 s2mps11,buck2-ramp-delay = <12>;
82 s2mps11,buck34-ramp-delay = <12>;
83 s2mps11,buck16-ramp-delay = <12>;
84 s2mps11,buck6-ramp-enable = <1>;
85 s2mps11,buck2-ramp-enable = <1>;
86 s2mps11,buck3-ramp-enable = <1>;
87 s2mps11,buck4-ramp-enable = <1>;
88
89 interrupt-parent = <&gpx3>;
90 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
91
92 s2mps11_osc: clocks {
93 #clock-cells = <1>;
94 clock-output-names = "s2mps11_ap",
95 "s2mps11_cp", "s2mps11_bt";
96 };
97
98 regulators {
99 ldo1_reg: LDO1 {
100 regulator-name = "PVDD_ALIVE_1V0";
101 regulator-min-microvolt = <1000000>;
102 regulator-max-microvolt = <1000000>;
103 regulator-always-on;
104 };
105
106 ldo2_reg: LDO2 {
107 regulator-name = "PVDD_APIO_1V8";
108 regulator-min-microvolt = <1800000>;
109 regulator-max-microvolt = <1800000>;
110 };
111
112 ldo3_reg: LDO3 {
113 regulator-name = "PVDD_APIO_MMCON_1V8";
114 regulator-min-microvolt = <1800000>;
115 regulator-max-microvolt = <1800000>;
116 regulator-always-on;
117 };
118
119 ldo4_reg: LDO4 {
120 regulator-name = "PVDD_ADC_1V8";
121 regulator-min-microvolt = <1800000>;
122 regulator-max-microvolt = <1800000>;
123 };
124
125 ldo5_reg: LDO5 {
126 regulator-name = "PVDD_PLL_1V8";
127 regulator-min-microvolt = <1800000>;
128 regulator-max-microvolt = <1800000>;
129 regulator-always-on;
130 };
131
132 ldo6_reg: LDO6 {
133 regulator-name = "PVDD_ANAIP_1V0";
134 regulator-min-microvolt = <1000000>;
135 regulator-max-microvolt = <1000000>;
136 };
137
138 ldo7_reg: LDO7 {
139 regulator-name = "PVDD_ANAIP_1V8";
140 regulator-min-microvolt = <1800000>;
141 regulator-max-microvolt = <1800000>;
142 };
143
144 ldo8_reg: LDO8 {
145 regulator-name = "PVDD_ABB_1V8";
146 regulator-min-microvolt = <1800000>;
147 regulator-max-microvolt = <1800000>;
148 };
149
150 ldo9_reg: LDO9 {
151 regulator-name = "PVDD_USB_3V3";
152 regulator-min-microvolt = <3000000>;
153 regulator-max-microvolt = <3000000>;
154 regulator-always-on;
155 };
156
157 ldo10_reg: LDO10 {
158 regulator-name = "PVDD_PRE_1V8";
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <1800000>;
161 regulator-always-on;
162 };
163
164 ldo11_reg: LDO11 {
165 regulator-name = "PVDD_USB_1V0";
166 regulator-min-microvolt = <1000000>;
167 regulator-max-microvolt = <1000000>;
168 regulator-always-on;
169 };
170
171 ldo12_reg: LDO12 {
172 regulator-name = "PVDD_HSIC_1V8";
173 regulator-min-microvolt = <1800000>;
174 regulator-max-microvolt = <1800000>;
175 };
176
177 ldo13_reg: LDO13 {
178 regulator-name = "PVDD_APIO_MMCOFF_2V8";
179 regulator-min-microvolt = <2800000>;
180 regulator-max-microvolt = <2800000>;
181 };
182
183 ldo15_reg: LDO15 {
184 regulator-name = "PVDD_PERI_2V8";
185 regulator-min-microvolt = <3300000>;
186 regulator-max-microvolt = <3300000>;
187 };
188
189 ldo16_reg: LDO16 {
190 regulator-name = "PVDD_PERI_3V3";
191 regulator-min-microvolt = <2200000>;
192 regulator-max-microvolt = <2200000>;
193 };
194
195 ldo18_reg: LDO18 {
196 regulator-name = "PVDD_EMMC_1V8";
197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <1800000>;
199 };
200
201 ldo19_reg: LDO19 {
202 regulator-name = "PVDD_TFLASH_2V8";
203 regulator-min-microvolt = <2800000>;
204 regulator-max-microvolt = <2800000>;
205 };
206
207 ldo20_reg: LDO20 {
208 regulator-name = "PVDD_BTWIFI_1V8";
209 regulator-min-microvolt = <1800000>;
210 regulator-max-microvolt = <1800000>;
211 };
212
213 ldo21_reg: LDO21 {
214 regulator-name = "PVDD_CAM1IO_1V8";
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <1800000>;
217 };
218
219 ldo23_reg: LDO23 {
220 regulator-name = "PVDD_MIFS_1V1";
221 regulator-min-microvolt = <1200000>;
222 regulator-max-microvolt = <1200000>;
223 regulator-always-on;
224 };
225
226 ldo24_reg: LDO24 {
227 regulator-name = "PVDD_CAM1_AVDD_2V8";
228 regulator-min-microvolt = <2800000>;
229 regulator-max-microvolt = <2800000>;
230 };
231
232 ldo26_reg: LDO26 {
233 regulator-name = "PVDD_CAM0_AF_2V8";
234 regulator-min-microvolt = <3000000>;
235 regulator-max-microvolt = <3000000>;
236 };
237
238 ldo27_reg: LDO27 {
239 regulator-name = "PVDD_G3DS_1V0";
240 regulator-min-microvolt = <1200000>;
241 regulator-max-microvolt = <1200000>;
242 };
243
244 ldo28_reg: LDO28 {
245 regulator-name = "PVDD_TSP_3V3";
246 regulator-min-microvolt = <3300000>;
247 regulator-max-microvolt = <3300000>;
248 };
249
250 ldo29_reg: LDO29 {
251 regulator-name = "PVDD_AUDIO_1V8";
252 regulator-min-microvolt = <1800000>;
253 regulator-max-microvolt = <1800000>;
254 };
255
256 ldo31_reg: LDO31 {
257 regulator-name = "PVDD_PERI_1V8";
258 regulator-min-microvolt = <1800000>;
259 regulator-max-microvolt = <1800000>;
260 };
261
262 ldo32_reg: LDO32 {
263 regulator-name = "PVDD_LCD_1V8";
264 regulator-min-microvolt = <1800000>;
265 regulator-max-microvolt = <1800000>;
266 };
267
268 ldo33_reg: LDO33 {
269 regulator-name = "PVDD_CAM0IO_1V8";
270 regulator-min-microvolt = <1800000>;
271 regulator-max-microvolt = <1800000>;
272 };
273
274 ldo35_reg: LDO35 {
275 regulator-name = "PVDD_CAM0_DVDD_1V2";
276 regulator-min-microvolt = <1200000>;
277 regulator-max-microvolt = <1200000>;
278 };
279
280 ldo38_reg: LDO38 {
281 regulator-name = "PVDD_CAM0_AVDD_2V8";
282 regulator-min-microvolt = <2800000>;
283 regulator-max-microvolt = <2800000>;
284 };
285
286 buck1_reg: BUCK1 {
287 regulator-name = "PVDD_MIF_1V1";
288 regulator-min-microvolt = <800000>;
289 regulator-max-microvolt = <1100000>;
290 regulator-always-on;
291 };
292
293 buck2_reg: BUCK2 {
294 regulator-name = "vdd_arm";
295 regulator-min-microvolt = <800000>;
296 regulator-max-microvolt = <1000000>;
297 regulator-always-on;
298 };
299
300 buck3_reg: BUCK3 {
301 regulator-name = "PVDD_INT_1V0";
302 regulator-min-microvolt = <800000>;
303 regulator-max-microvolt = <1000000>;
304 regulator-always-on;
305 };
306
307 buck4_reg: BUCK4 {
308 regulator-name = "PVDD_G3D_1V0";
309 regulator-min-microvolt = <800000>;
310 regulator-max-microvolt = <1000000>;
311 };
312
313 buck5_reg: BUCK5 {
314 regulator-name = "PVDD_LPDDR3_1V2";
315 regulator-min-microvolt = <800000>;
316 regulator-max-microvolt = <1200000>;
317 regulator-always-on;
318 };
319
320 buck6_reg: BUCK6 {
321 regulator-name = "PVDD_KFC_1V0";
322 regulator-min-microvolt = <800000>;
323 regulator-max-microvolt = <1000000>;
324 regulator-always-on;
325 };
326
327 buck7_reg: BUCK7 {
328 regulator-name = "VIN_LLDO_1V4";
329 regulator-min-microvolt = <800000>;
330 regulator-max-microvolt = <1400000>;
331 regulator-always-on;
332 };
333
334 buck8_reg: BUCK8 {
335 regulator-name = "VIN_MLDO_2V0";
336 regulator-min-microvolt = <800000>;
337 regulator-max-microvolt = <2000000>;
338 regulator-always-on;
339 };
340
341 buck9_reg: BUCK9 {
342 regulator-name = "VIN_HLDO_3V5";
343 regulator-min-microvolt = <3000000>;
344 regulator-max-microvolt = <3500000>;
345 regulator-always-on;
346 };
347
348 buck10_reg: BUCK10 {
349 regulator-name = "PVDD_EMMCF_2V8";
350 regulator-min-microvolt = <2800000>;
351 regulator-max-microvolt = <2800000>;
352 };
353 };
354 };
355 };
356
357 gpio_keys {
358 compatible = "gpio-keys";
359
360 wakeup {
361 label = "SW-TACT1";
362 gpios = <&gpx2 7 1>;
363 linux,code = <KEY_WAKEUP>;
364 gpio-key,wakeup;
365 };
366 };
367
368 amba {
369 mdma1: mdma@11C10000 {
370 /*
371 * MDMA1 can support both secure and non-secure
372 * AXI transactions. When this is enabled in the kernel
373 * for boards that run in secure mode, we are getting
374 * imprecise external aborts causing the kernel to oops.
375 */
376 status = "disabled";
377 };
378 };
66}; 379};
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index fb5a1e25c632..69104850eb5e 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -14,7 +14,7 @@
14 14
15/ { 15/ {
16 model = "Samsung SMDK5420 board based on EXYNOS5420"; 16 model = "Samsung SMDK5420 board based on EXYNOS5420";
17 compatible = "samsung,smdk5420", "samsung,exynos5420"; 17 compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5";
18 18
19 memory { 19 memory {
20 reg = <0x20000000 0x80000000>; 20 reg = <0x20000000 0x80000000>;
@@ -31,6 +31,43 @@
31 }; 31 };
32 }; 32 };
33 33
34 regulators {
35 compatible = "simple-bus";
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 vdd: fixed-regulator@0 {
40 compatible = "regulator-fixed";
41 reg = <0>;
42 regulator-name = "vdd-supply";
43 regulator-min-microvolt = <1800000>;
44 regulator-max-microvolt = <1800000>;
45 regulator-always-on;
46 };
47
48 dbvdd: fixed-regulator@1 {
49 compatible = "regulator-fixed";
50 reg = <1>;
51 regulator-name = "dbvdd-supply";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
54 regulator-always-on;
55 };
56
57 spkvdd: fixed-regulator@2 {
58 compatible = "regulator-fixed";
59 reg = <2>;
60 regulator-name = "spkvdd-supply";
61 regulator-min-microvolt = <5000000>;
62 regulator-max-microvolt = <5000000>;
63 regulator-always-on;
64 };
65 };
66
67 rtc@101E0000 {
68 status = "okay";
69 };
70
34 mmc@12200000 { 71 mmc@12200000 {
35 status = "okay"; 72 status = "okay";
36 broken-cd; 73 broken-cd;
@@ -120,4 +157,220 @@
120 reg = <0x50>; 157 reg = <0x50>;
121 }; 158 };
122 }; 159 };
160
161 hsi2c_4: i2c@12CA0000 {
162 status = "okay";
163
164 s2mps11_pmic@66 {
165 compatible = "samsung,s2mps11-pmic";
166 reg = <0x66>;
167 s2mps11,buck2-ramp-delay = <12>;
168 s2mps11,buck34-ramp-delay = <12>;
169 s2mps11,buck16-ramp-delay = <12>;
170 s2mps11,buck6-ramp-enable = <1>;
171 s2mps11,buck2-ramp-enable = <1>;
172 s2mps11,buck3-ramp-enable = <1>;
173 s2mps11,buck4-ramp-enable = <1>;
174
175 s2mps11_osc: clocks {
176 #clock-cells = <1>;
177 clock-output-names = "s2mps11_ap",
178 "s2mps11_cp", "s2mps11_bt";
179 };
180
181 regulators {
182 ldo1_reg: LDO1 {
183 regulator-name = "vdd_ldo1";
184 regulator-min-microvolt = <1000000>;
185 regulator-max-microvolt = <1000000>;
186 regulator-always-on;
187 };
188
189 ldo3_reg: LDO3 {
190 regulator-name = "vdd_ldo3";
191 regulator-min-microvolt = <1800000>;
192 regulator-max-microvolt = <1800000>;
193 regulator-always-on;
194 };
195
196 ldo5_reg: LDO5 {
197 regulator-name = "vdd_ldo5";
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <1800000>;
200 regulator-always-on;
201 };
202
203 ldo6_reg: LDO6 {
204 regulator-name = "vdd_ldo6";
205 regulator-min-microvolt = <1000000>;
206 regulator-max-microvolt = <1000000>;
207 regulator-always-on;
208 };
209
210 ldo7_reg: LDO7 {
211 regulator-name = "vdd_ldo7";
212 regulator-min-microvolt = <1800000>;
213 regulator-max-microvolt = <1800000>;
214 regulator-always-on;
215 };
216
217 ldo8_reg: LDO8 {
218 regulator-name = "vdd_ldo8";
219 regulator-min-microvolt = <1800000>;
220 regulator-max-microvolt = <1800000>;
221 regulator-always-on;
222 };
223
224 ldo9_reg: LDO9 {
225 regulator-name = "vdd_ldo9";
226 regulator-min-microvolt = <3000000>;
227 regulator-max-microvolt = <3000000>;
228 regulator-always-on;
229 };
230
231 ldo10_reg: LDO10 {
232 regulator-name = "vdd_ldo10";
233 regulator-min-microvolt = <1800000>;
234 regulator-max-microvolt = <1800000>;
235 regulator-always-on;
236 };
237
238 ldo11_reg: LDO11 {
239 regulator-name = "vdd_ldo11";
240 regulator-min-microvolt = <1000000>;
241 regulator-max-microvolt = <1000000>;
242 regulator-always-on;
243 };
244
245 ldo12_reg: LDO12 {
246 regulator-name = "vdd_ldo12";
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <1800000>;
249 regulator-always-on;
250 };
251
252 ldo13_reg: LDO13 {
253 regulator-name = "vdd_ldo13";
254 regulator-min-microvolt = <2800000>;
255 regulator-max-microvolt = <2800000>;
256 regulator-always-on;
257 };
258
259 ldo15_reg: LDO15 {
260 regulator-name = "vdd_ldo15";
261 regulator-min-microvolt = <3100000>;
262 regulator-max-microvolt = <3100000>;
263 regulator-always-on;
264 };
265
266 ldo16_reg: LDO16 {
267 regulator-name = "vdd_ldo16";
268 regulator-min-microvolt = <2200000>;
269 regulator-max-microvolt = <2200000>;
270 regulator-always-on;
271 };
272
273 ldo17_reg: LDO17 {
274 regulator-name = "tsp_avdd";
275 regulator-min-microvolt = <3300000>;
276 regulator-max-microvolt = <3300000>;
277 regulator-always-on;
278 };
279
280 ldo19_reg: LDO19 {
281 regulator-name = "vdd_sd";
282 regulator-min-microvolt = <2800000>;
283 regulator-max-microvolt = <2800000>;
284 regulator-always-on;
285 };
286
287 ldo24_reg: LDO24 {
288 regulator-name = "tsp_io";
289 regulator-min-microvolt = <2800000>;
290 regulator-max-microvolt = <2800000>;
291 regulator-always-on;
292 };
293
294 buck1_reg: BUCK1 {
295 regulator-name = "vdd_mif";
296 regulator-min-microvolt = <800000>;
297 regulator-max-microvolt = <1300000>;
298 regulator-always-on;
299 regulator-boot-on;
300 };
301
302 buck2_reg: BUCK2 {
303 regulator-name = "vdd_arm";
304 regulator-min-microvolt = <800000>;
305 regulator-max-microvolt = <1500000>;
306 regulator-always-on;
307 regulator-boot-on;
308 };
309
310 buck3_reg: BUCK3 {
311 regulator-name = "vdd_int";
312 regulator-min-microvolt = <800000>;
313 regulator-max-microvolt = <1400000>;
314 regulator-always-on;
315 regulator-boot-on;
316 };
317
318 buck4_reg: BUCK4 {
319 regulator-name = "vdd_g3d";
320 regulator-min-microvolt = <800000>;
321 regulator-max-microvolt = <1400000>;
322 regulator-always-on;
323 regulator-boot-on;
324 };
325
326 buck5_reg: BUCK5 {
327 regulator-name = "vdd_mem";
328 regulator-min-microvolt = <800000>;
329 regulator-max-microvolt = <1400000>;
330 regulator-always-on;
331 regulator-boot-on;
332 };
333
334 buck6_reg: BUCK6 {
335 regulator-name = "vdd_kfc";
336 regulator-min-microvolt = <800000>;
337 regulator-max-microvolt = <1500000>;
338 regulator-always-on;
339 regulator-boot-on;
340 };
341
342 buck7_reg: BUCK7 {
343 regulator-name = "vdd_1.0v_ldo";
344 regulator-min-microvolt = <800000>;
345 regulator-max-microvolt = <1500000>;
346 regulator-always-on;
347 regulator-boot-on;
348 };
349
350 buck8_reg: BUCK8 {
351 regulator-name = "vdd_1.8v_ldo";
352 regulator-min-microvolt = <800000>;
353 regulator-max-microvolt = <1500000>;
354 regulator-always-on;
355 regulator-boot-on;
356 };
357
358 buck9_reg: BUCK9 {
359 regulator-name = "vdd_2.8v_ldo";
360 regulator-min-microvolt = <3000000>;
361 regulator-max-microvolt = <3750000>;
362 regulator-always-on;
363 regulator-boot-on;
364 };
365
366 buck10_reg: BUCK10 {
367 regulator-name = "vdd_vmem";
368 regulator-min-microvolt = <2850000>;
369 regulator-max-microvolt = <2850000>;
370 regulator-always-on;
371 regulator-boot-on;
372 };
373 };
374 };
375 };
123}; 376};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8db792b26f79..c3a9a66c5767 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -13,13 +13,14 @@
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 */ 14 */
15 15
16#include <dt-bindings/clock/exynos5420.h>
16#include "exynos5.dtsi" 17#include "exynos5.dtsi"
17#include "exynos5420-pinctrl.dtsi" 18#include "exynos5420-pinctrl.dtsi"
18 19
19#include <dt-bindings/clk/exynos-audss-clk.h> 20#include <dt-bindings/clock/exynos-audss-clk.h>
20 21
21/ { 22/ {
22 compatible = "samsung,exynos5420"; 23 compatible = "samsung,exynos5420", "samsung,exynos5";
23 24
24 aliases { 25 aliases {
25 mshc0 = &mmc_0; 26 mshc0 = &mmc_0;
@@ -119,7 +120,8 @@
119 compatible = "samsung,exynos5420-audss-clock"; 120 compatible = "samsung,exynos5420-audss-clock";
120 reg = <0x03810000 0x0C>; 121 reg = <0x03810000 0x0C>;
121 #clock-cells = <1>; 122 #clock-cells = <1>;
122 clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>; 123 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
124 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
123 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 125 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
124 }; 126 };
125 127
@@ -127,7 +129,7 @@
127 compatible = "samsung,mfc-v7"; 129 compatible = "samsung,mfc-v7";
128 reg = <0x11000000 0x10000>; 130 reg = <0x11000000 0x10000>;
129 interrupts = <0 96 0>; 131 interrupts = <0 96 0>;
130 clocks = <&clock 401>; 132 clocks = <&clock CLK_MFC>;
131 clock-names = "mfc"; 133 clock-names = "mfc";
132 }; 134 };
133 135
@@ -137,7 +139,7 @@
137 #address-cells = <1>; 139 #address-cells = <1>;
138 #size-cells = <0>; 140 #size-cells = <0>;
139 reg = <0x12200000 0x2000>; 141 reg = <0x12200000 0x2000>;
140 clocks = <&clock 351>, <&clock 132>; 142 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
141 clock-names = "biu", "ciu"; 143 clock-names = "biu", "ciu";
142 fifo-depth = <0x40>; 144 fifo-depth = <0x40>;
143 status = "disabled"; 145 status = "disabled";
@@ -149,7 +151,7 @@
149 #address-cells = <1>; 151 #address-cells = <1>;
150 #size-cells = <0>; 152 #size-cells = <0>;
151 reg = <0x12210000 0x2000>; 153 reg = <0x12210000 0x2000>;
152 clocks = <&clock 352>, <&clock 133>; 154 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
153 clock-names = "biu", "ciu"; 155 clock-names = "biu", "ciu";
154 fifo-depth = <0x40>; 156 fifo-depth = <0x40>;
155 status = "disabled"; 157 status = "disabled";
@@ -161,7 +163,7 @@
161 #address-cells = <1>; 163 #address-cells = <1>;
162 #size-cells = <0>; 164 #size-cells = <0>;
163 reg = <0x12220000 0x1000>; 165 reg = <0x12220000 0x1000>;
164 clocks = <&clock 353>, <&clock 134>; 166 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
165 clock-names = "biu", "ciu"; 167 clock-names = "biu", "ciu";
166 fifo-depth = <0x40>; 168 fifo-depth = <0x40>;
167 status = "disabled"; 169 status = "disabled";
@@ -175,7 +177,7 @@
175 interrupt-parent = <&mct_map>; 177 interrupt-parent = <&mct_map>;
176 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, 178 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
177 <8>, <9>, <10>, <11>; 179 <8>, <9>, <10>, <11>;
178 clocks = <&clock 1>, <&clock 315>; 180 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
179 clock-names = "fin_pll", "mct"; 181 clock-names = "fin_pll", "mct";
180 182
181 mct_map: mct-map { 183 mct_map: mct-map {
@@ -269,9 +271,9 @@
269 }; 271 };
270 272
271 rtc@101E0000 { 273 rtc@101E0000 {
272 clocks = <&clock 317>; 274 clocks = <&clock CLK_RTC>;
273 clock-names = "rtc"; 275 clock-names = "rtc";
274 status = "okay"; 276 status = "disabled";
275 }; 277 };
276 278
277 amba { 279 amba {
@@ -281,11 +283,22 @@
281 interrupt-parent = <&gic>; 283 interrupt-parent = <&gic>;
282 ranges; 284 ranges;
283 285
286 adma: adma@03880000 {
287 compatible = "arm,pl330", "arm,primecell";
288 reg = <0x03880000 0x1000>;
289 interrupts = <0 110 0>;
290 clocks = <&clock_audss EXYNOS_ADMA>;
291 clock-names = "apb_pclk";
292 #dma-cells = <1>;
293 #dma-channels = <6>;
294 #dma-requests = <16>;
295 };
296
284 pdma0: pdma@121A0000 { 297 pdma0: pdma@121A0000 {
285 compatible = "arm,pl330", "arm,primecell"; 298 compatible = "arm,pl330", "arm,primecell";
286 reg = <0x121A0000 0x1000>; 299 reg = <0x121A0000 0x1000>;
287 interrupts = <0 34 0>; 300 interrupts = <0 34 0>;
288 clocks = <&clock 362>; 301 clocks = <&clock CLK_PDMA0>;
289 clock-names = "apb_pclk"; 302 clock-names = "apb_pclk";
290 #dma-cells = <1>; 303 #dma-cells = <1>;
291 #dma-channels = <8>; 304 #dma-channels = <8>;
@@ -296,7 +309,7 @@
296 compatible = "arm,pl330", "arm,primecell"; 309 compatible = "arm,pl330", "arm,primecell";
297 reg = <0x121B0000 0x1000>; 310 reg = <0x121B0000 0x1000>;
298 interrupts = <0 35 0>; 311 interrupts = <0 35 0>;
299 clocks = <&clock 363>; 312 clocks = <&clock CLK_PDMA1>;
300 clock-names = "apb_pclk"; 313 clock-names = "apb_pclk";
301 #dma-cells = <1>; 314 #dma-cells = <1>;
302 #dma-channels = <8>; 315 #dma-channels = <8>;
@@ -307,7 +320,7 @@
307 compatible = "arm,pl330", "arm,primecell"; 320 compatible = "arm,pl330", "arm,primecell";
308 reg = <0x10800000 0x1000>; 321 reg = <0x10800000 0x1000>;
309 interrupts = <0 33 0>; 322 interrupts = <0 33 0>;
310 clocks = <&clock 473>; 323 clocks = <&clock CLK_MDMA0>;
311 clock-names = "apb_pclk"; 324 clock-names = "apb_pclk";
312 #dma-cells = <1>; 325 #dma-cells = <1>;
313 #dma-channels = <8>; 326 #dma-channels = <8>;
@@ -318,7 +331,7 @@
318 compatible = "arm,pl330", "arm,primecell"; 331 compatible = "arm,pl330", "arm,primecell";
319 reg = <0x11C10000 0x1000>; 332 reg = <0x11C10000 0x1000>;
320 interrupts = <0 124 0>; 333 interrupts = <0 124 0>;
321 clocks = <&clock 442>; 334 clocks = <&clock CLK_MDMA1>;
322 clock-names = "apb_pclk"; 335 clock-names = "apb_pclk";
323 #dma-cells = <1>; 336 #dma-cells = <1>;
324 #dma-channels = <8>; 337 #dma-channels = <8>;
@@ -326,6 +339,49 @@
326 }; 339 };
327 }; 340 };
328 341
342 i2s0: i2s@03830000 {
343 compatible = "samsung,exynos5420-i2s";
344 reg = <0x03830000 0x100>;
345 dmas = <&adma 0
346 &adma 2
347 &adma 1>;
348 dma-names = "tx", "rx", "tx-sec";
349 clocks = <&clock_audss EXYNOS_I2S_BUS>,
350 <&clock_audss EXYNOS_I2S_BUS>,
351 <&clock_audss EXYNOS_SCLK_I2S>;
352 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
353 samsung,idma-addr = <0x03000000>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2s0_bus>;
356 status = "disabled";
357 };
358
359 i2s1: i2s@12D60000 {
360 compatible = "samsung,exynos5420-i2s";
361 reg = <0x12D60000 0x100>;
362 dmas = <&pdma1 12
363 &pdma1 11>;
364 dma-names = "tx", "rx";
365 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
366 clock-names = "iis", "i2s_opclk0";
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2s1_bus>;
369 status = "disabled";
370 };
371
372 i2s2: i2s@12D70000 {
373 compatible = "samsung,exynos5420-i2s";
374 reg = <0x12D70000 0x100>;
375 dmas = <&pdma0 12
376 &pdma0 11>;
377 dma-names = "tx", "rx";
378 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
379 clock-names = "iis", "i2s_opclk0";
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2s2_bus>;
382 status = "disabled";
383 };
384
329 spi_0: spi@12d20000 { 385 spi_0: spi@12d20000 {
330 compatible = "samsung,exynos4210-spi"; 386 compatible = "samsung,exynos4210-spi";
331 reg = <0x12d20000 0x100>; 387 reg = <0x12d20000 0x100>;
@@ -337,7 +393,7 @@
337 #size-cells = <0>; 393 #size-cells = <0>;
338 pinctrl-names = "default"; 394 pinctrl-names = "default";
339 pinctrl-0 = <&spi0_bus>; 395 pinctrl-0 = <&spi0_bus>;
340 clocks = <&clock 271>, <&clock 135>; 396 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
341 clock-names = "spi", "spi_busclk0"; 397 clock-names = "spi", "spi_busclk0";
342 status = "disabled"; 398 status = "disabled";
343 }; 399 };
@@ -353,7 +409,7 @@
353 #size-cells = <0>; 409 #size-cells = <0>;
354 pinctrl-names = "default"; 410 pinctrl-names = "default";
355 pinctrl-0 = <&spi1_bus>; 411 pinctrl-0 = <&spi1_bus>;
356 clocks = <&clock 272>, <&clock 136>; 412 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
357 clock-names = "spi", "spi_busclk0"; 413 clock-names = "spi", "spi_busclk0";
358 status = "disabled"; 414 status = "disabled";
359 }; 415 };
@@ -369,28 +425,28 @@
369 #size-cells = <0>; 425 #size-cells = <0>;
370 pinctrl-names = "default"; 426 pinctrl-names = "default";
371 pinctrl-0 = <&spi2_bus>; 427 pinctrl-0 = <&spi2_bus>;
372 clocks = <&clock 273>, <&clock 137>; 428 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
373 clock-names = "spi", "spi_busclk0"; 429 clock-names = "spi", "spi_busclk0";
374 status = "disabled"; 430 status = "disabled";
375 }; 431 };
376 432
377 serial@12C00000 { 433 serial@12C00000 {
378 clocks = <&clock 257>, <&clock 128>; 434 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
379 clock-names = "uart", "clk_uart_baud0"; 435 clock-names = "uart", "clk_uart_baud0";
380 }; 436 };
381 437
382 serial@12C10000 { 438 serial@12C10000 {
383 clocks = <&clock 258>, <&clock 129>; 439 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
384 clock-names = "uart", "clk_uart_baud0"; 440 clock-names = "uart", "clk_uart_baud0";
385 }; 441 };
386 442
387 serial@12C20000 { 443 serial@12C20000 {
388 clocks = <&clock 259>, <&clock 130>; 444 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
389 clock-names = "uart", "clk_uart_baud0"; 445 clock-names = "uart", "clk_uart_baud0";
390 }; 446 };
391 447
392 serial@12C30000 { 448 serial@12C30000 {
393 clocks = <&clock 260>, <&clock 131>; 449 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
394 clock-names = "uart", "clk_uart_baud0"; 450 clock-names = "uart", "clk_uart_baud0";
395 }; 451 };
396 452
@@ -399,7 +455,7 @@
399 reg = <0x12dd0000 0x100>; 455 reg = <0x12dd0000 0x100>;
400 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 456 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
401 #pwm-cells = <3>; 457 #pwm-cells = <3>;
402 clocks = <&clock 279>; 458 clocks = <&clock CLK_PWM>;
403 clock-names = "timers"; 459 clock-names = "timers";
404 }; 460 };
405 461
@@ -410,7 +466,7 @@
410 }; 466 };
411 467
412 dp-controller@145B0000 { 468 dp-controller@145B0000 {
413 clocks = <&clock 412>; 469 clocks = <&clock CLK_DP1>;
414 clock-names = "dp"; 470 clock-names = "dp";
415 phys = <&dp_phy>; 471 phys = <&dp_phy>;
416 phy-names = "dp"; 472 phy-names = "dp";
@@ -418,7 +474,7 @@
418 474
419 fimd@14400000 { 475 fimd@14400000 {
420 samsung,power-domain = <&disp_pd>; 476 samsung,power-domain = <&disp_pd>;
421 clocks = <&clock 147>, <&clock 421>; 477 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
422 clock-names = "sclk_fimd", "fimd"; 478 clock-names = "sclk_fimd", "fimd";
423 }; 479 };
424 480
@@ -426,7 +482,7 @@
426 compatible = "samsung,exynos-adc-v2"; 482 compatible = "samsung,exynos-adc-v2";
427 reg = <0x12D10000 0x100>, <0x10040720 0x4>; 483 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
428 interrupts = <0 106 0>; 484 interrupts = <0 106 0>;
429 clocks = <&clock 270>; 485 clocks = <&clock CLK_TSADC>;
430 clock-names = "adc"; 486 clock-names = "adc";
431 #io-channel-cells = <1>; 487 #io-channel-cells = <1>;
432 io-channel-ranges; 488 io-channel-ranges;
@@ -439,7 +495,7 @@
439 interrupts = <0 56 0>; 495 interrupts = <0 56 0>;
440 #address-cells = <1>; 496 #address-cells = <1>;
441 #size-cells = <0>; 497 #size-cells = <0>;
442 clocks = <&clock 261>; 498 clocks = <&clock CLK_I2C0>;
443 clock-names = "i2c"; 499 clock-names = "i2c";
444 pinctrl-names = "default"; 500 pinctrl-names = "default";
445 pinctrl-0 = <&i2c0_bus>; 501 pinctrl-0 = <&i2c0_bus>;
@@ -452,7 +508,7 @@
452 interrupts = <0 57 0>; 508 interrupts = <0 57 0>;
453 #address-cells = <1>; 509 #address-cells = <1>;
454 #size-cells = <0>; 510 #size-cells = <0>;
455 clocks = <&clock 262>; 511 clocks = <&clock CLK_I2C1>;
456 clock-names = "i2c"; 512 clock-names = "i2c";
457 pinctrl-names = "default"; 513 pinctrl-names = "default";
458 pinctrl-0 = <&i2c1_bus>; 514 pinctrl-0 = <&i2c1_bus>;
@@ -465,7 +521,7 @@
465 interrupts = <0 58 0>; 521 interrupts = <0 58 0>;
466 #address-cells = <1>; 522 #address-cells = <1>;
467 #size-cells = <0>; 523 #size-cells = <0>;
468 clocks = <&clock 263>; 524 clocks = <&clock CLK_I2C2>;
469 clock-names = "i2c"; 525 clock-names = "i2c";
470 pinctrl-names = "default"; 526 pinctrl-names = "default";
471 pinctrl-0 = <&i2c2_bus>; 527 pinctrl-0 = <&i2c2_bus>;
@@ -478,7 +534,7 @@
478 interrupts = <0 59 0>; 534 interrupts = <0 59 0>;
479 #address-cells = <1>; 535 #address-cells = <1>;
480 #size-cells = <0>; 536 #size-cells = <0>;
481 clocks = <&clock 264>; 537 clocks = <&clock CLK_I2C3>;
482 clock-names = "i2c"; 538 clock-names = "i2c";
483 pinctrl-names = "default"; 539 pinctrl-names = "default";
484 pinctrl-0 = <&i2c3_bus>; 540 pinctrl-0 = <&i2c3_bus>;
@@ -493,7 +549,7 @@
493 #size-cells = <0>; 549 #size-cells = <0>;
494 pinctrl-names = "default"; 550 pinctrl-names = "default";
495 pinctrl-0 = <&i2c4_hs_bus>; 551 pinctrl-0 = <&i2c4_hs_bus>;
496 clocks = <&clock 265>; 552 clocks = <&clock CLK_I2C4>;
497 clock-names = "hsi2c"; 553 clock-names = "hsi2c";
498 status = "disabled"; 554 status = "disabled";
499 }; 555 };
@@ -506,7 +562,7 @@
506 #size-cells = <0>; 562 #size-cells = <0>;
507 pinctrl-names = "default"; 563 pinctrl-names = "default";
508 pinctrl-0 = <&i2c5_hs_bus>; 564 pinctrl-0 = <&i2c5_hs_bus>;
509 clocks = <&clock 266>; 565 clocks = <&clock CLK_I2C5>;
510 clock-names = "hsi2c"; 566 clock-names = "hsi2c";
511 status = "disabled"; 567 status = "disabled";
512 }; 568 };
@@ -519,7 +575,7 @@
519 #size-cells = <0>; 575 #size-cells = <0>;
520 pinctrl-names = "default"; 576 pinctrl-names = "default";
521 pinctrl-0 = <&i2c6_hs_bus>; 577 pinctrl-0 = <&i2c6_hs_bus>;
522 clocks = <&clock 267>; 578 clocks = <&clock CLK_I2C6>;
523 clock-names = "hsi2c"; 579 clock-names = "hsi2c";
524 status = "disabled"; 580 status = "disabled";
525 }; 581 };
@@ -532,7 +588,7 @@
532 #size-cells = <0>; 588 #size-cells = <0>;
533 pinctrl-names = "default"; 589 pinctrl-names = "default";
534 pinctrl-0 = <&i2c7_hs_bus>; 590 pinctrl-0 = <&i2c7_hs_bus>;
535 clocks = <&clock 268>; 591 clocks = <&clock CLK_I2C7>;
536 clock-names = "hsi2c"; 592 clock-names = "hsi2c";
537 status = "disabled"; 593 status = "disabled";
538 }; 594 };
@@ -545,7 +601,7 @@
545 #size-cells = <0>; 601 #size-cells = <0>;
546 pinctrl-names = "default"; 602 pinctrl-names = "default";
547 pinctrl-0 = <&i2c8_hs_bus>; 603 pinctrl-0 = <&i2c8_hs_bus>;
548 clocks = <&clock 281>; 604 clocks = <&clock CLK_I2C8>;
549 clock-names = "hsi2c"; 605 clock-names = "hsi2c";
550 status = "disabled"; 606 status = "disabled";
551 }; 607 };
@@ -558,7 +614,7 @@
558 #size-cells = <0>; 614 #size-cells = <0>;
559 pinctrl-names = "default"; 615 pinctrl-names = "default";
560 pinctrl-0 = <&i2c9_hs_bus>; 616 pinctrl-0 = <&i2c9_hs_bus>;
561 clocks = <&clock 282>; 617 clocks = <&clock CLK_I2C9>;
562 clock-names = "hsi2c"; 618 clock-names = "hsi2c";
563 status = "disabled"; 619 status = "disabled";
564 }; 620 };
@@ -571,7 +627,7 @@
571 #size-cells = <0>; 627 #size-cells = <0>;
572 pinctrl-names = "default"; 628 pinctrl-names = "default";
573 pinctrl-0 = <&i2c10_hs_bus>; 629 pinctrl-0 = <&i2c10_hs_bus>;
574 clocks = <&clock 283>; 630 clocks = <&clock CLK_I2C10>;
575 clock-names = "hsi2c"; 631 clock-names = "hsi2c";
576 status = "disabled"; 632 status = "disabled";
577 }; 633 };
@@ -580,8 +636,9 @@
580 compatible = "samsung,exynos4212-hdmi"; 636 compatible = "samsung,exynos4212-hdmi";
581 reg = <0x14530000 0x70000>; 637 reg = <0x14530000 0x70000>;
582 interrupts = <0 95 0>; 638 interrupts = <0 95 0>;
583 clocks = <&clock 413>, <&clock 143>, <&clock 768>, 639 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
584 <&clock 158>, <&clock 640>; 640 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
641 <&clock CLK_MOUT_HDMI>;
585 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 642 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
586 "sclk_hdmiphy", "mout_hdmi"; 643 "sclk_hdmiphy", "mout_hdmi";
587 status = "disabled"; 644 status = "disabled";
@@ -591,7 +648,7 @@
591 compatible = "samsung,exynos5420-mixer"; 648 compatible = "samsung,exynos5420-mixer";
592 reg = <0x14450000 0x10000>; 649 reg = <0x14450000 0x10000>;
593 interrupts = <0 94 0>; 650 interrupts = <0 94 0>;
594 clocks = <&clock 431>, <&clock 143>; 651 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
595 clock-names = "mixer", "sclk_hdmi"; 652 clock-names = "mixer", "sclk_hdmi";
596 }; 653 };
597 654
@@ -599,7 +656,7 @@
599 compatible = "samsung,exynos5-gsc"; 656 compatible = "samsung,exynos5-gsc";
600 reg = <0x13e00000 0x1000>; 657 reg = <0x13e00000 0x1000>;
601 interrupts = <0 85 0>; 658 interrupts = <0 85 0>;
602 clocks = <&clock 465>; 659 clocks = <&clock CLK_GSCL0>;
603 clock-names = "gscl"; 660 clock-names = "gscl";
604 samsung,power-domain = <&gsc_pd>; 661 samsung,power-domain = <&gsc_pd>;
605 }; 662 };
@@ -608,16 +665,21 @@
608 compatible = "samsung,exynos5-gsc"; 665 compatible = "samsung,exynos5-gsc";
609 reg = <0x13e10000 0x1000>; 666 reg = <0x13e10000 0x1000>;
610 interrupts = <0 86 0>; 667 interrupts = <0 86 0>;
611 clocks = <&clock 466>; 668 clocks = <&clock CLK_GSCL1>;
612 clock-names = "gscl"; 669 clock-names = "gscl";
613 samsung,power-domain = <&gsc_pd>; 670 samsung,power-domain = <&gsc_pd>;
614 }; 671 };
615 672
673 pmu_system_controller: system-controller@10040000 {
674 compatible = "samsung,exynos5420-pmu", "syscon";
675 reg = <0x10040000 0x5000>;
676 };
677
616 tmu_cpu0: tmu@10060000 { 678 tmu_cpu0: tmu@10060000 {
617 compatible = "samsung,exynos5420-tmu"; 679 compatible = "samsung,exynos5420-tmu";
618 reg = <0x10060000 0x100>; 680 reg = <0x10060000 0x100>;
619 interrupts = <0 65 0>; 681 interrupts = <0 65 0>;
620 clocks = <&clock 318>; 682 clocks = <&clock CLK_TMU>;
621 clock-names = "tmu_apbif"; 683 clock-names = "tmu_apbif";
622 }; 684 };
623 685
@@ -625,7 +687,7 @@
625 compatible = "samsung,exynos5420-tmu"; 687 compatible = "samsung,exynos5420-tmu";
626 reg = <0x10064000 0x100>; 688 reg = <0x10064000 0x100>;
627 interrupts = <0 183 0>; 689 interrupts = <0 183 0>;
628 clocks = <&clock 318>; 690 clocks = <&clock CLK_TMU>;
629 clock-names = "tmu_apbif"; 691 clock-names = "tmu_apbif";
630 }; 692 };
631 693
@@ -633,7 +695,7 @@
633 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 695 compatible = "samsung,exynos5420-tmu-ext-triminfo";
634 reg = <0x10068000 0x100>, <0x1006c000 0x4>; 696 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
635 interrupts = <0 184 0>; 697 interrupts = <0 184 0>;
636 clocks = <&clock 318>, <&clock 318>; 698 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
637 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 699 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
638 }; 700 };
639 701
@@ -641,7 +703,7 @@
641 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 703 compatible = "samsung,exynos5420-tmu-ext-triminfo";
642 reg = <0x1006c000 0x100>, <0x100a0000 0x4>; 704 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
643 interrupts = <0 185 0>; 705 interrupts = <0 185 0>;
644 clocks = <&clock 318>, <&clock 319>; 706 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
645 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 707 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
646 }; 708 };
647 709
@@ -649,7 +711,25 @@
649 compatible = "samsung,exynos5420-tmu-ext-triminfo"; 711 compatible = "samsung,exynos5420-tmu-ext-triminfo";
650 reg = <0x100a0000 0x100>, <0x10068000 0x4>; 712 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
651 interrupts = <0 215 0>; 713 interrupts = <0 215 0>;
652 clocks = <&clock 319>, <&clock 318>; 714 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
653 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 715 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
654 }; 716 };
717
718 watchdog@101D0000 {
719 compatible = "samsung,exynos5420-wdt";
720 reg = <0x101D0000 0x100>;
721 interrupts = <0 42 0>;
722 clocks = <&clock CLK_WDT>;
723 clock-names = "watchdog";
724 samsung,syscon-phandle = <&pmu_system_controller>;
725 };
726
727 sss@10830000 {
728 compatible = "samsung,exynos4210-secss";
729 reg = <0x10830000 0x10000>;
730 interrupts = <0 112 0>;
731 clocks = <&clock 471>;
732 clock-names = "secss";
733 samsung,power-domain = <&g2d_pd>;
734 };
655}; 735};
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index 777fb1c2c70f..268609a42b2c 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -14,7 +14,7 @@
14 14
15/ { 15/ {
16 model = "SAMSUNG SD5v1 board based on EXYNOS5440"; 16 model = "SAMSUNG SD5v1 board based on EXYNOS5440";
17 compatible = "samsung,sd5v1", "samsung,exynos5440"; 17 compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5";
18 18
19 chosen { 19 chosen {
20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; 20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d58cb787061a..ff55dac6e219 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -14,7 +14,7 @@
14 14
15/ { 15/ {
16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; 16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
17 compatible = "samsung,ssdk5440", "samsung,exynos5440"; 17 compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5";
18 18
19 chosen { 19 chosen {
20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; 20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 02a0a1226cef..84f77c2fe4d4 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,10 +9,11 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12#include <dt-bindings/clock/exynos5440.h>
12#include "skeleton.dtsi" 13#include "skeleton.dtsi"
13 14
14/ { 15/ {
15 compatible = "samsung,exynos5440"; 16 compatible = "samsung,exynos5440", "samsung,exynos5";
16 17
17 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
18 19
@@ -105,7 +106,7 @@
105 compatible = "samsung,exynos4210-uart"; 106 compatible = "samsung,exynos4210-uart";
106 reg = <0xB0000 0x1000>; 107 reg = <0xB0000 0x1000>;
107 interrupts = <0 2 0>; 108 interrupts = <0 2 0>;
108 clocks = <&clock 21>, <&clock 21>; 109 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
109 clock-names = "uart", "clk_uart_baud0"; 110 clock-names = "uart", "clk_uart_baud0";
110 }; 111 };
111 112
@@ -113,7 +114,7 @@
113 compatible = "samsung,exynos4210-uart"; 114 compatible = "samsung,exynos4210-uart";
114 reg = <0xC0000 0x1000>; 115 reg = <0xC0000 0x1000>;
115 interrupts = <0 3 0>; 116 interrupts = <0 3 0>;
116 clocks = <&clock 21>, <&clock 21>; 117 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
117 clock-names = "uart", "clk_uart_baud0"; 118 clock-names = "uart", "clk_uart_baud0";
118 }; 119 };
119 120
@@ -125,7 +126,7 @@
125 #size-cells = <0>; 126 #size-cells = <0>;
126 samsung,spi-src-clk = <0>; 127 samsung,spi-src-clk = <0>;
127 num-cs = <1>; 128 num-cs = <1>;
128 clocks = <&clock 21>, <&clock 16>; 129 clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
129 clock-names = "spi", "spi_busclk0"; 130 clock-names = "spi", "spi_busclk0";
130 }; 131 };
131 132
@@ -161,7 +162,7 @@
161 interrupts = <0 5 0>; 162 interrupts = <0 5 0>;
162 #address-cells = <1>; 163 #address-cells = <1>;
163 #size-cells = <0>; 164 #size-cells = <0>;
164 clocks = <&clock 21>; 165 clocks = <&clock CLK_B_125>;
165 clock-names = "i2c"; 166 clock-names = "i2c";
166 }; 167 };
167 168
@@ -171,7 +172,7 @@
171 interrupts = <0 6 0>; 172 interrupts = <0 6 0>;
172 #address-cells = <1>; 173 #address-cells = <1>;
173 #size-cells = <0>; 174 #size-cells = <0>;
174 clocks = <&clock 21>; 175 clocks = <&clock CLK_B_125>;
175 clock-names = "i2c"; 176 clock-names = "i2c";
176 }; 177 };
177 178
@@ -179,7 +180,7 @@
179 compatible = "samsung,s3c2410-wdt"; 180 compatible = "samsung,s3c2410-wdt";
180 reg = <0x110000 0x1000>; 181 reg = <0x110000 0x1000>;
181 interrupts = <0 1 0>; 182 interrupts = <0 1 0>;
182 clocks = <&clock 21>; 183 clocks = <&clock CLK_B_125>;
183 clock-names = "watchdog"; 184 clock-names = "watchdog";
184 }; 185 };
185 186
@@ -190,7 +191,7 @@
190 interrupts = <0 31 4>; 191 interrupts = <0 31 4>;
191 interrupt-names = "macirq"; 192 interrupt-names = "macirq";
192 phy-mode = "sgmii"; 193 phy-mode = "sgmii";
193 clocks = <&clock 25>; 194 clocks = <&clock CLK_GMAC0>;
194 clock-names = "stmmaceth"; 195 clock-names = "stmmaceth";
195 }; 196 };
196 197
@@ -206,7 +207,7 @@
206 compatible = "samsung,s3c6410-rtc"; 207 compatible = "samsung,s3c6410-rtc";
207 reg = <0x130000 0x1000>; 208 reg = <0x130000 0x1000>;
208 interrupts = <0 17 0>, <0 16 0>; 209 interrupts = <0 17 0>, <0 16 0>;
209 clocks = <&clock 21>; 210 clocks = <&clock CLK_B_125>;
210 clock-names = "rtc"; 211 clock-names = "rtc";
211 }; 212 };
212 213
@@ -214,7 +215,7 @@
214 compatible = "samsung,exynos5440-tmu"; 215 compatible = "samsung,exynos5440-tmu";
215 reg = <0x160118 0x230>, <0x160368 0x10>; 216 reg = <0x160118 0x230>, <0x160368 0x10>;
216 interrupts = <0 58 0>; 217 interrupts = <0 58 0>;
217 clocks = <&clock 21>; 218 clocks = <&clock CLK_B_125>;
218 clock-names = "tmu_apbif"; 219 clock-names = "tmu_apbif";
219 }; 220 };
220 221
@@ -222,7 +223,7 @@
222 compatible = "samsung,exynos5440-tmu"; 223 compatible = "samsung,exynos5440-tmu";
223 reg = <0x16011C 0x230>, <0x160368 0x10>; 224 reg = <0x16011C 0x230>, <0x160368 0x10>;
224 interrupts = <0 58 0>; 225 interrupts = <0 58 0>;
225 clocks = <&clock 21>; 226 clocks = <&clock CLK_B_125>;
226 clock-names = "tmu_apbif"; 227 clock-names = "tmu_apbif";
227 }; 228 };
228 229
@@ -230,7 +231,7 @@
230 compatible = "samsung,exynos5440-tmu"; 231 compatible = "samsung,exynos5440-tmu";
231 reg = <0x160120 0x230>, <0x160368 0x10>; 232 reg = <0x160120 0x230>, <0x160368 0x10>;
232 interrupts = <0 58 0>; 233 interrupts = <0 58 0>;
233 clocks = <&clock 21>; 234 clocks = <&clock CLK_B_125>;
234 clock-names = "tmu_apbif"; 235 clock-names = "tmu_apbif";
235 }; 236 };
236 237
@@ -238,7 +239,7 @@
238 compatible = "snps,exynos5440-ahci"; 239 compatible = "snps,exynos5440-ahci";
239 reg = <0x210000 0x10000>; 240 reg = <0x210000 0x10000>;
240 interrupts = <0 30 0>; 241 interrupts = <0 30 0>;
241 clocks = <&clock 23>; 242 clocks = <&clock CLK_SATA>;
242 clock-names = "sata"; 243 clock-names = "sata";
243 }; 244 };
244 245
@@ -246,7 +247,7 @@
246 compatible = "samsung,exynos5440-ohci"; 247 compatible = "samsung,exynos5440-ohci";
247 reg = <0x220000 0x1000>; 248 reg = <0x220000 0x1000>;
248 interrupts = <0 29 0>; 249 interrupts = <0 29 0>;
249 clocks = <&clock 24>; 250 clocks = <&clock CLK_USB>;
250 clock-names = "usbhost"; 251 clock-names = "usbhost";
251 }; 252 };
252 253
@@ -254,7 +255,7 @@
254 compatible = "samsung,exynos5440-ehci"; 255 compatible = "samsung,exynos5440-ehci";
255 reg = <0x221000 0x1000>; 256 reg = <0x221000 0x1000>;
256 interrupts = <0 29 0>; 257 interrupts = <0 29 0>;
257 clocks = <&clock 24>; 258 clocks = <&clock CLK_USB>;
258 clock-names = "usbhost"; 259 clock-names = "usbhost";
259 }; 260 };
260 261
@@ -264,7 +265,7 @@
264 0x270000 0x1000 265 0x270000 0x1000
265 0x271000 0x40>; 266 0x271000 0x40>;
266 interrupts = <0 20 0>, <0 21 0>, <0 22 0>; 267 interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
267 clocks = <&clock 28>, <&clock 27>; 268 clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
268 clock-names = "pcie", "pcie_bus"; 269 clock-names = "pcie", "pcie_bus";
269 #address-cells = <3>; 270 #address-cells = <3>;
270 #size-cells = <2>; 271 #size-cells = <2>;
@@ -285,7 +286,7 @@
285 0x272000 0x1000 286 0x272000 0x1000
286 0x271040 0x40>; 287 0x271040 0x40>;
287 interrupts = <0 23 0>, <0 24 0>, <0 25 0>; 288 interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
288 clocks = <&clock 29>, <&clock 27>; 289 clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
289 clock-names = "pcie", "pcie_bus"; 290 clock-names = "pcie", "pcie_bus";
290 #address-cells = <3>; 291 #address-cells = <3>;
291 #size-cells = <2>; 292 #size-cells = <2>;
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 1f026adefd45..a33f66c11b73 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -127,17 +127,21 @@
127 127
128 regulators { 128 regulators {
129 compatible = "simple-bus"; 129 compatible = "simple-bus";
130 #address-cells = <1>;
131 #size-cells = <0>;
130 132
131 reg_vddio_sd0: vddio-sd0 { 133 reg_vddio_sd0: regulator@0 {
132 compatible = "regulator-fixed"; 134 compatible = "regulator-fixed";
135 reg = <0>;
133 regulator-name = "vddio-sd0"; 136 regulator-name = "vddio-sd0";
134 regulator-min-microvolt = <3300000>; 137 regulator-min-microvolt = <3300000>;
135 regulator-max-microvolt = <3300000>; 138 regulator-max-microvolt = <3300000>;
136 gpio = <&gpio1 29 0>; 139 gpio = <&gpio1 29 0>;
137 }; 140 };
138 141
139 reg_lcd_3v3: lcd-3v3 { 142 reg_lcd_3v3: regulator@1 {
140 compatible = "regulator-fixed"; 143 compatible = "regulator-fixed";
144 reg = <1>;
141 regulator-name = "lcd-3v3"; 145 regulator-name = "lcd-3v3";
142 regulator-min-microvolt = <3300000>; 146 regulator-min-microvolt = <3300000>;
143 regulator-max-microvolt = <3300000>; 147 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 526bfdbd87f9..7e6eef2488e8 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -100,9 +100,12 @@
100 100
101 regulators { 101 regulators {
102 compatible = "simple-bus"; 102 compatible = "simple-bus";
103 #address-cells = <1>;
104 #size-cells = <0>;
103 105
104 reg_usb0_vbus: usb0_vbus { 106 reg_usb0_vbus: regulator@0 {
105 compatible = "regulator-fixed"; 107 compatible = "regulator-fixed";
108 reg = <0>;
106 regulator-name = "usb0_vbus"; 109 regulator-name = "usb0_vbus";
107 regulator-min-microvolt = <5000000>; 110 regulator-min-microvolt = <5000000>;
108 regulator-max-microvolt = <5000000>; 111 regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index cb64e2b191ea..455169e99d49 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -66,9 +66,12 @@
66 66
67 regulators { 67 regulators {
68 compatible = "simple-bus"; 68 compatible = "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <0>;
69 71
70 reg_vddio_sd0: vddio-sd0 { 72 reg_vddio_sd0: regulator@0 {
71 compatible = "regulator-fixed"; 73 compatible = "regulator-fixed";
74 reg = <0>;
72 regulator-name = "vddio-sd0"; 75 regulator-name = "vddio-sd0";
73 regulator-min-microvolt = <3300000>; 76 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 581b75433be6..bbcfb5a19c77 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,6 +23,7 @@
23 serial1 = &auart1; 23 serial1 = &auart1;
24 spi0 = &ssp0; 24 spi0 = &ssp0;
25 spi1 = &ssp1; 25 spi1 = &ssp1;
26 usbphy0 = &usbphy0;
26 }; 27 };
27 28
28 cpus { 29 cpus {
@@ -428,7 +429,7 @@
428 status = "disabled"; 429 status = "disabled";
429 }; 430 };
430 431
431 lradc@80050000 { 432 lradc: lradc@80050000 {
432 compatible = "fsl,imx23-lradc"; 433 compatible = "fsl,imx23-lradc";
433 reg = <0x80050000 0x2000>; 434 reg = <0x80050000 0x2000>;
434 interrupts = <36 37 38 39 40 41 42 43 44>; 435 interrupts = <36 37 38 39 40 41 42 43 44>;
@@ -526,4 +527,9 @@
526 status = "disabled"; 527 status = "disabled";
527 }; 528 };
528 }; 529 };
530
531 iio_hwmon {
532 compatible = "iio-hwmon";
533 io-channels = <&lradc 8>;
534 };
529}; 535};
diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
new file mode 100644
index 000000000000..d6f27641c0ef
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
@@ -0,0 +1,73 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "imx25.dtsi"
15
16/ {
17 model = "Eukrea CPUIMX25";
18 compatible = "eukrea,cpuimx25", "fsl,imx25";
19
20 memory {
21 reg = <0x80000000 0x4000000>; /* 64M */
22 };
23};
24
25&fec {
26 phy-mode = "rmii";
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_fec>;
29 status = "okay";
30};
31
32&i2c1 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_i2c1>;
35 status = "okay";
36
37 pcf8563@51 {
38 compatible = "nxp,pcf8563";
39 reg = <0x51>;
40 };
41};
42
43&iomuxc {
44 imx25-eukrea-cpuimx25 {
45 pinctrl_fec: fecgrp {
46 fsl,pins = <
47 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
48 MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
49 MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
50 MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
51 MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
52 MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
53 MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
54 MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
55 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
56 >;
57 };
58
59 pinctrl_i2c1: i2c1grp {
60 fsl,pins = <
61 MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
62 MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
63 >;
64 };
65 };
66};
67
68&nfc {
69 nand-bus-width = <8>;
70 nand-ecc-mode = "hw";
71 nand-on-flash-bbt;
72 status = "okay";
73};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
new file mode 100644
index 000000000000..62fb3da50bdb
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -0,0 +1,174 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include "imx25-eukrea-cpuimx25.dtsi"
19
20/ {
21 model = "Eukrea MBIMXSD25";
22 compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
23
24 gpio_keys {
25 compatible = "gpio-keys";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpiokeys>;
28
29 bp1 {
30 label = "BP1";
31 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
32 linux,code = <BTN_MISC>;
33 gpio-key,wakeup;
34 };
35 };
36
37 leds {
38 compatible = "gpio-leds";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpioled>;
41
42 led1 {
43 label = "led1";
44 gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
45 linux,default-trigger = "heartbeat";
46 };
47 };
48
49 sound {
50 compatible = "eukrea,asoc-tlv320";
51 eukrea,model = "imx25-eukrea-tlv320aic23";
52 ssi-controller = <&ssi1>;
53 fsl,mux-int-port = <1>;
54 fsl,mux-ext-port = <5>;
55 };
56};
57
58&audmux {
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_audmux>;
61 status = "okay";
62};
63
64&esdhc1 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_esdhc1>;
67 cd-gpios = <&gpio1 20>;
68 status = "okay";
69};
70
71&i2c1 {
72 tlv320aic23: codec@1a {
73 compatible = "ti,tlv320aic23";
74 reg = <0x1a>;
75 };
76};
77
78&iomuxc {
79 imx25-eukrea-mbimxsd25-baseboard {
80 pinctrl_audmux: audmuxgrp {
81 fsl,pins = <
82 MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0
83 MX25_PAD_KPP_COL2__AUD5_TXC 0xe0
84 MX25_PAD_KPP_COL1__AUD5_RXD 0xe0
85 MX25_PAD_KPP_COL0__AUD5_TXD 0xe0
86 >;
87 };
88
89 pinctrl_esdhc1: esdhc1grp {
90 fsl,pins = <
91 MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0
92 MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0
93 MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0
94 MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0
95 MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0
96 MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0
97 >;
98 };
99
100 pinctrl_gpiokeys: gpiokeysgrp {
101 fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
102 };
103
104 pinctrl_gpioled: gpioledgrp {
105 fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
106 };
107
108 pinctrl_lcdc: lcdcgrp {
109 fsl,pins = <
110 MX25_PAD_LD0__LD0 0x1
111 MX25_PAD_LD1__LD1 0x1
112 MX25_PAD_LD2__LD2 0x1
113 MX25_PAD_LD3__LD3 0x1
114 MX25_PAD_LD4__LD4 0x1
115 MX25_PAD_LD5__LD5 0x1
116 MX25_PAD_LD6__LD6 0x1
117 MX25_PAD_LD7__LD7 0x1
118 MX25_PAD_LD8__LD8 0x1
119 MX25_PAD_LD9__LD9 0x1
120 MX25_PAD_LD10__LD10 0x1
121 MX25_PAD_LD11__LD11 0x1
122 MX25_PAD_LD12__LD12 0x1
123 MX25_PAD_LD13__LD13 0x1
124 MX25_PAD_LD14__LD14 0x1
125 MX25_PAD_LD15__LD15 0x1
126 MX25_PAD_GPIO_E__LD16 0x1
127 MX25_PAD_GPIO_F__LD17 0x1
128 MX25_PAD_HSYNC__HSYNC 0x80000000
129 MX25_PAD_VSYNC__VSYNC 0x80000000
130 MX25_PAD_LSCLK__LSCLK 0x80000000
131 MX25_PAD_OE_ACD__OE_ACD 0x80000000
132 MX25_PAD_CONTRAST__CONTRAST 0x80000000
133 >;
134 };
135
136 pinctrl_uart1: uart1grp {
137 fsl,pins = <
138 MX25_PAD_UART1_RTS__UART1_RTS 0xe0
139 MX25_PAD_UART1_CTS__UART1_CTS 0xe0
140 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
141 MX25_PAD_UART1_RXD__UART1_RXD 0xc0
142 >;
143 };
144
145 pinctrl_uart2: uart2grp {
146 fsl,pins = <
147 MX25_PAD_UART2_RXD__UART2_RXD 0x80000000
148 MX25_PAD_UART2_TXD__UART2_TXD 0x80000000
149 MX25_PAD_UART2_RTS__UART2_RTS 0x80000000
150 MX25_PAD_UART2_CTS__UART2_CTS 0x80000000
151 >;
152 };
153 };
154};
155
156&ssi1 {
157 codec-handle = <&tlv320aic23>;
158 fsl,mode = "i2s-slave";
159 status = "okay";
160};
161
162&uart1 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_uart1>;
165 fsl,uart-has-rtscts;
166 status = "okay";
167};
168
169&uart2 {
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_uart2>;
172 fsl,uart-has-rtscts;
173 status = "okay";
174};
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
new file mode 100644
index 000000000000..9238a95d8e62
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -0,0 +1,494 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 * Based on imx35-pinfunc.h in the same directory Which is:
4 * Copyright 2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef __DTS_IMX25_PINFUNC_H
13#define __DTS_IMX25_PINFUNC_H
14
15/*
16 * The pin function ID is a tuple of
17 * <mux_reg conf_reg input_reg mux_mode input_val>
18 */
19
20#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
21#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
22
23#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
24#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
25
26#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
27#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
28
29#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
30#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
31
32#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
33#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
34
35#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
36#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
37
38#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
39#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
40#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
41
42#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
43#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000
44#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
45
46#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
47#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
48#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
49
50#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
51#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
52#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
53
54#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
55#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
56
57#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
58#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
59
60#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
61#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
62#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
63
64#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
65#define MX25_PAD_A25__GPIO_2_11 0x03c 0x254 0x000 0x15 0x000
66#define MX25_PAD_A25__FEC_CRS 0x03c 0x254 0x508 0x17 0x000
67
68#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x10 0x000
69#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x14 0x000
70#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x15 0x000
71
72#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x10 0x000
73#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x14 0x000
74#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x15 0x000
75
76#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x10 0x000
77#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x14 0x000
78#define MX25_PAD_OE__GPIO_2_14 0x048 0x260 0x000 0x15 0x000
79
80#define MX25_PAD_CS0__CS0 0x04c 0x000 0x000 0x00 0x000
81#define MX25_PAD_CS0__GPIO_4_2 0x04c 0x000 0x000 0x05 0x000
82
83#define MX25_PAD_CS1__CS1 0x050 0x000 0x000 0x00 0x000
84#define MX25_PAD_CS1__NF_CE3 0x050 0x000 0x000 0x01 0x000
85#define MX25_PAD_CS1__GPIO_4_3 0x050 0x000 0x000 0x05 0x000
86
87#define MX25_PAD_CS4__CS4 0x054 0x264 0x000 0x10 0x000
88#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000
89#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000
90#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000
91
92#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x10 0x000
93#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
94#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x13 0x000
95#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x15 0x000
96
97#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000
98#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000
99
100#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000
101#define MX25_PAD_ECB__UART5_TXD_MUX 0x060 0x270 0x000 0x13 0x000
102#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000
103
104#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000
105#define MX25_PAD_LBA__UART5_RXD_MUX 0x064 0x274 0x578 0x13 0x000
106#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000
107
108#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000
109#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000
110
111#define MX25_PAD_RW__RW 0x06c 0x278 0x000 0x10 0x000
112#define MX25_PAD_RW__AUD4_TXFS 0x06c 0x278 0x474 0x14 0x000
113#define MX25_PAD_RW__GPIO_3_25 0x06c 0x278 0x000 0x15 0x000
114
115#define MX25_PAD_NFWE_B__NFWE_B 0x070 0x000 0x000 0x10 0x000
116#define MX25_PAD_NFWE_B__GPIO_3_26 0x070 0x000 0x000 0x15 0x000
117
118#define MX25_PAD_NFRE_B__NFRE_B 0x074 0x000 0x000 0x10 0x000
119#define MX25_PAD_NFRE_B__GPIO_3_27 0x074 0x000 0x000 0x15 0x000
120
121#define MX25_PAD_NFALE__NFALE 0x078 0x000 0x000 0x10 0x000
122#define MX25_PAD_NFALE__GPIO_3_28 0x078 0x000 0x000 0x15 0x000
123
124#define MX25_PAD_NFCLE__NFCLE 0x07c 0x000 0x000 0x10 0x000
125#define MX25_PAD_NFCLE__GPIO_3_29 0x07c 0x000 0x000 0x15 0x000
126
127#define MX25_PAD_NFWP_B__NFWP_B 0x080 0x000 0x000 0x10 0x000
128#define MX25_PAD_NFWP_B__GPIO_3_30 0x080 0x000 0x000 0x15 0x000
129
130#define MX25_PAD_NFRB__NFRB 0x084 0x27c 0x000 0x10 0x000
131#define MX25_PAD_NFRB__GPIO_3_31 0x084 0x27c 0x000 0x15 0x000
132
133#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
134#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
135#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
136
137#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
138#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
139#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
140
141#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
142#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
143#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
144
145#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
146#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
147
148#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
149#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
150
151#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
152#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
153#define MX25_PAD_D10__USBOTG_OC 0x09c 0x294 0x57c 0x06 0x000
154
155#define MX25_PAD_D9__D9 0x0a0 0x298 0x000 0x00 0x000
156#define MX25_PAD_D9__GPIO_4_11 0x0a0 0x298 0x000 0x05 0x000
157#define MX25_PAD_D9__USBH2_PWR 0x0a0 0x298 0x000 0x06 0x000
158
159#define MX25_PAD_D8__D8 0x0a4 0x29c 0x000 0x00 0x000
160#define MX25_PAD_D8__GPIO_4_12 0x0a4 0x29c 0x000 0x05 0x000
161#define MX25_PAD_D8__USBH2_OC 0x0a4 0x29c 0x580 0x06 0x000
162
163#define MX25_PAD_D7__D7 0x0a8 0x2a0 0x000 0x00 0x000
164#define MX25_PAD_D7__GPIO_4_13 0x0a8 0x2a0 0x000 0x05 0x000
165
166#define MX25_PAD_D6__D6 0x0ac 0x2a4 0x000 0x00 0x000
167#define MX25_PAD_D6__GPIO_4_14 0x0ac 0x2a4 0x000 0x05 0x000
168
169#define MX25_PAD_D5__D5 0x0b0 0x2a8 0x000 0x00 0x000
170#define MX25_PAD_D5__GPIO_4_15 0x0b0 0x2a8 0x000 0x05 0x000
171
172#define MX25_PAD_D4__D4 0x0b4 0x2ac 0x000 0x00 0x000
173#define MX25_PAD_D4__GPIO_4_16 0x0b4 0x2ac 0x000 0x05 0x000
174
175#define MX25_PAD_D3__D3 0x0b8 0x2b0 0x000 0x00 0x000
176#define MX25_PAD_D3__GPIO_4_17 0x0b8 0x2b0 0x000 0x05 0x000
177
178#define MX25_PAD_D2__D2 0x0bc 0x2b4 0x000 0x00 0x000
179#define MX25_PAD_D2__GPIO_4_18 0x0bc 0x2b4 0x000 0x05 0x000
180
181#define MX25_PAD_D1__D1 0x0c0 0x2b8 0x000 0x00 0x000
182#define MX25_PAD_D1__GPIO_4_19 0x0c0 0x2b8 0x000 0x05 0x000
183
184#define MX25_PAD_D0__D0 0x0c4 0x2bc 0x000 0x00 0x000
185#define MX25_PAD_D0__GPIO_4_20 0x0c4 0x2bc 0x000 0x05 0x000
186
187#define MX25_PAD_LD0__LD0 0x0c8 0x2c0 0x000 0x10 0x000
188#define MX25_PAD_LD0__CSI_D0 0x0c8 0x2c0 0x488 0x12 0x000
189#define MX25_PAD_LD0__GPIO_2_15 0x0c8 0x2c0 0x000 0x15 0x000
190
191#define MX25_PAD_LD1__LD1 0x0cc 0x2c4 0x000 0x10 0x000
192#define MX25_PAD_LD1__CSI_D1 0x0cc 0x2c4 0x48c 0x12 0x000
193#define MX25_PAD_LD1__GPIO_2_16 0x0cc 0x2c4 0x000 0x15 0x000
194
195#define MX25_PAD_LD2__LD2 0x0d0 0x2c8 0x000 0x10 0x000
196#define MX25_PAD_LD2__GPIO_2_17 0x0d0 0x2c8 0x000 0x15 0x000
197
198#define MX25_PAD_LD3__LD3 0x0d4 0x2cc 0x000 0x10 0x000
199#define MX25_PAD_LD3__GPIO_2_18 0x0d4 0x2cc 0x000 0x15 0x000
200
201#define MX25_PAD_LD4__LD4 0x0d8 0x2d0 0x000 0x10 0x000
202#define MX25_PAD_LD4__GPIO_2_19 0x0d8 0x2d0 0x000 0x15 0x000
203
204#define MX25_PAD_LD5__LD5 0x0dc 0x2d4 0x000 0x10 0x000
205#define MX25_PAD_LD5__GPIO_1_19 0x0dc 0x2d4 0x000 0x15 0x000
206
207#define MX25_PAD_LD6__LD6 0x0e0 0x2d8 0x000 0x10 0x000
208#define MX25_PAD_LD6__GPIO_1_20 0x0e0 0x2d8 0x000 0x15 0x000
209
210#define MX25_PAD_LD7__LD7 0x0e4 0x2dc 0x000 0x10 0x000
211#define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000
212
213#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
214#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
215
216#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
217#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
218
219#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
220#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001
221
222#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
223#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
224
225#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
226#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
227
228#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
229#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
230
231#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
232#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
233
234#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
235#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
236
237#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
238#define MX25_PAD_HSYNC__GPIO_1_22 0x108 0x300 0x000 0x15 0x000
239
240#define MX25_PAD_VSYNC__VSYNC 0x10c 0x304 0x000 0x10 0x000
241#define MX25_PAD_VSYNC__GPIO_1_23 0x10c 0x304 0x000 0x15 0x000
242
243#define MX25_PAD_LSCLK__LSCLK 0x110 0x308 0x000 0x10 0x000
244#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
245
246#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
247#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
248
249#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
250#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000
251#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001
252
253#define MX25_PAD_PWM__PWM 0x11c 0x314 0x000 0x10 0x000
254#define MX25_PAD_PWM__GPIO_1_26 0x11c 0x314 0x000 0x15 0x000
255#define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001
256
257#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
258#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
259#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
260#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
261
262#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
263#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
264#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
265
266#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
267#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
268#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
269#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
270
271#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
272#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
273#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
274
275#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
276#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
277
278#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
279#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
280
281#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
282#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
283
284#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
285#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
286
287#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
288#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
289
290#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
291#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
292
293#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
294#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
295
296#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
297#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
298
299#define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000
300#define MX25_PAD_I2C1_CLK__GPIO_1_12 0x150 0x348 0x000 0x15 0x000
301
302#define MX25_PAD_I2C1_DAT__I2C1_DAT 0x154 0x34c 0x000 0x10 0x000
303#define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000
304
305#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000
306#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000
307
308#define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000
309#define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000
310
311#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000
312#define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000
313
314#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000
315#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000
316
317#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000
318#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000
319
320#define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000
321#define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000
322
323#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x10 0x000
324#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x15 0x000
325
326#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x10 0x000
327#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x15 0x000
328
329#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000
330#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001
331#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000
332
333#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000
334#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x11 0x001
335#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x15 0x000
336
337#define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000
338#define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000
339
340#define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000
341#define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000
342
343#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000
344#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002
345#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
346
347#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
348#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
349#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
350
351#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
352#define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002
353#define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000
354
355#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000
356#define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002
357#define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000
358
359#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000
360#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000
361
362#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000
363#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x13 0x000
364#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
365
366#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
367#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002
368#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
369
370#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
371#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002
372#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
373
374#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
375#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x15 0x000
376
377#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x10 0x000
378#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x15 0x000
379
380#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x10 0x000
381#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x13 0x002
382#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
383
384#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
385#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002
386#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
387
388#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
389#define MX25_PAD_KPP_COL0__UART4_RXD_MUX 0x1b8 0x3b0 0x570 0x11 0x001
390#define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000
391#define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000
392
393#define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000
394#define MX25_PAD_KPP_COL1__UART4_TXD_MUX 0x1bc 0x3b4 0x000 0x11 0x000
395#define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000
396#define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000
397
398#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x10 0x000
399#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x000 0x11 0x000
400#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x12 0x000
401#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x15 0x000
402
403#define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000
404#define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000
405#define MX25_PAD_KPP_COL3__AUD5_TXFS 0x1c4 0x3bc 0x000 0x12 0x000
406#define MX25_PAD_KPP_COL3__GPIO_3_4 0x1c4 0x3bc 0x000 0x15 0x000
407
408#define MX25_PAD_FEC_MDC__FEC_MDC 0x1c8 0x3c0 0x000 0x10 0x000
409#define MX25_PAD_FEC_MDC__AUD4_TXD 0x1c8 0x3c0 0x464 0x12 0x001
410#define MX25_PAD_FEC_MDC__GPIO_3_5 0x1c8 0x3c0 0x000 0x15 0x000
411
412#define MX25_PAD_FEC_MDIO__FEC_MDIO 0x1cc 0x3c4 0x000 0x10 0x000
413#define MX25_PAD_FEC_MDIO__AUD4_RXD 0x1cc 0x3c4 0x460 0x12 0x001
414#define MX25_PAD_FEC_MDIO__GPIO_3_6 0x1cc 0x3c4 0x000 0x15 0x000
415
416#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x1d0 0x3c8 0x000 0x10 0x000
417#define MX25_PAD_FEC_TDATA0__GPIO_3_7 0x1d0 0x3c8 0x000 0x15 0x000
418
419#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x1d4 0x3cc 0x000 0x10 0x000
420#define MX25_PAD_FEC_TDATA1__AUD4_TXFS 0x1d4 0x3cc 0x474 0x12 0x001
421#define MX25_PAD_FEC_TDATA1__GPIO_3_8 0x1d4 0x3cc 0x000 0x15 0x000
422
423#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x10 0x000
424#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x15 0x000
425
426#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x10 0x000
427#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
428
429#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
430#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
431
432#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
433#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
434#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
435
436#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1e8 0x3e0 0x000 0x10 0x000
437#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 0x1e8 0x3e0 0x000 0x15 0x000
438
439#define MX25_PAD_RTCK__RTCK 0x1ec 0x3e4 0x000 0x10 0x000
440#define MX25_PAD_RTCK__OWIRE 0x1ec 0x3e4 0x000 0x11 0x000
441#define MX25_PAD_RTCK__GPIO_3_14 0x1ec 0x3e4 0x000 0x15 0x000
442
443#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
444#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
445
446#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
447
448#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
449#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
450#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
451
452#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
453#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
454#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
455
456#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
457#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
458
459#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
460#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
461#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
462
463#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
464#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000
465#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
466
467#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
468#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
469
470#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
471#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
472
473#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000
474#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000
475
476#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
477#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
478#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
479#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
480#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
481
482#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000
483#define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001
484#define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000
485
486#define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000
487#define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000
488
489#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
490#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
491#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
492#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
493
494#endif /* __DTS_IMX25_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 737ed5da8f71..32f760e24898 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include "skeleton.dtsi" 12#include "skeleton.dtsi"
13#include "imx25-pinfunc.h"
13 14
14/ { 15/ {
15 aliases { 16 aliases {
@@ -173,12 +174,12 @@
173 status = "disabled"; 174 status = "disabled";
174 }; 175 };
175 176
176 iomuxc@43fac000{ 177 iomuxc: iomuxc@43fac000 {
177 compatible = "fsl,imx25-iomuxc"; 178 compatible = "fsl,imx25-iomuxc";
178 reg = <0x43fac000 0x4000>; 179 reg = <0x43fac000 0x4000>;
179 }; 180 };
180 181
181 audmux@43fb0000 { 182 audmux: audmux@43fb0000 {
182 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux"; 183 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
183 reg = <0x43fb0000 0x4000>; 184 reg = <0x43fb0000 0x4000>;
184 status = "disabled"; 185 status = "disabled";
@@ -236,6 +237,11 @@
236 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; 237 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
237 reg = <0x50014000 0x4000>; 238 reg = <0x50014000 0x4000>;
238 interrupts = <11>; 239 interrupts = <11>;
240 clocks = <&clks 118>;
241 clock-names = "ipg";
242 dmas = <&sdma 24 1 0>,
243 <&sdma 25 1 0>;
244 dma-names = "rx", "tx";
239 status = "disabled"; 245 status = "disabled";
240 }; 246 };
241 247
@@ -266,6 +272,11 @@
266 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; 272 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
267 reg = <0x50034000 0x4000>; 273 reg = <0x50034000 0x4000>;
268 interrupts = <12>; 274 interrupts = <12>;
275 clocks = <&clks 117>;
276 clock-names = "ipg";
277 dmas = <&sdma 28 1 0>,
278 <&sdma 29 1 0>;
279 dma-names = "rx", "tx";
269 status = "disabled"; 280 status = "disabled";
270 }; 281 };
271 282
@@ -436,13 +447,14 @@
436 #interrupt-cells = <2>; 447 #interrupt-cells = <2>;
437 }; 448 };
438 449
439 sdma@53fd4000 { 450 sdma: sdma@53fd4000 {
440 compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; 451 compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
441 reg = <0x53fd4000 0x4000>; 452 reg = <0x53fd4000 0x4000>;
442 clocks = <&clks 112>, <&clks 68>; 453 clocks = <&clks 112>, <&clks 68>;
443 clock-names = "ipg", "ahb"; 454 clock-names = "ipg", "ahb";
444 #dma-cells = <3>; 455 #dma-cells = <3>;
445 interrupts = <34>; 456 interrupts = <34>;
457 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
446 }; 458 };
447 459
448 wdog@53fdc000 { 460 wdog@53fdc000 {
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index ba4c6df08ece..09f57b39e3ef 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -34,11 +34,49 @@
34 }; 34 };
35}; 35};
36 36
37&iomuxc {
38 imx27-apf27 {
39 pinctrl_fec1: fec1grp {
40 fsl,pins = <
41 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
42 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
43 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
44 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
45 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
46 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
47 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
48 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
49 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
50 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
51 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
52 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
53 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
54 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
55 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
56 MX27_PAD_ATA_DATA13__FEC_COL 0x0
57 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
58 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
59 >;
60 };
61
62 pinctrl_uart1: uart1grp {
63 fsl,pins = <
64 MX27_PAD_UART1_TXD__UART1_TXD 0x0
65 MX27_PAD_UART1_RXD__UART1_RXD 0x0
66 >;
67 };
68 };
69};
70
37&uart1 { 71&uart1 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_uart1>;
38 status = "okay"; 74 status = "okay";
39}; 75};
40 76
41&fec { 77&fec {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_fec1>;
42 status = "okay"; 80 status = "okay";
43}; 81};
44 82
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 47c8c26012e4..2b6d489dae69 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -22,10 +22,10 @@
22 bits-per-pixel = <16>; /* non-standard but required */ 22 bits-per-pixel = <16>; /* non-standard but required */
23 fsl,pcr = <0xfae80083>; /* non-standard but required */ 23 fsl,pcr = <0xfae80083>; /* non-standard but required */
24 display-timings { 24 display-timings {
25 timing0: 640x480 { 25 timing0: 800x480 {
26 clock-frequency = <33000033>; 26 clock-frequency = <33000033>;
27 hactive = <800>; 27 hactive = <800>;
28 vactive = <640>; 28 vactive = <480>;
29 hback-porch = <96>; 29 hback-porch = <96>;
30 hfront-porch = <96>; 30 hfront-porch = <96>;
31 vback-porch = <20>; 31 vback-porch = <20>;
@@ -38,20 +38,24 @@
38 38
39 gpio-keys { 39 gpio-keys {
40 compatible = "gpio-keys"; 40 compatible = "gpio-keys";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_gpio_keys>;
41 43
42 user-key { 44 user-key {
43 label = "user"; 45 label = "user";
44 gpios = <&gpio6 13 0>; 46 gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
45 linux,code = <276>; /* BTN_EXTRA */ 47 linux,code = <276>; /* BTN_EXTRA */
46 }; 48 };
47 }; 49 };
48 50
49 leds { 51 leds {
50 compatible = "gpio-leds"; 52 compatible = "gpio-leds";
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_gpio_leds>;
51 55
52 user { 56 user {
53 label = "Heartbeat"; 57 label = "Heartbeat";
54 gpios = <&gpio6 14 0>; 58 gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
55 linux,default-trigger = "heartbeat"; 59 linux,default-trigger = "heartbeat";
56 }; 60 };
57 }; 61 };
@@ -59,25 +63,34 @@
59 63
60&cspi1 { 64&cspi1 {
61 fsl,spi-num-chipselects = <1>; 65 fsl,spi-num-chipselects = <1>;
62 cs-gpios = <&gpio4 28 1>; 66 cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
63 status = "okay"; 69 status = "okay";
64}; 70};
65 71
66&cspi2 { 72&cspi2 {
67 fsl,spi-num-chipselects = <3>; 73 fsl,spi-num-chipselects = <3>;
68 cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>, 74 cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>,
69 <&gpio2 17 1>; 75 <&gpio4 27 GPIO_ACTIVE_LOW>,
76 <&gpio2 17 GPIO_ACTIVE_LOW>;
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>;
70 status = "okay"; 79 status = "okay";
71}; 80};
72 81
73&fb { 82&fb {
74 display = <&display>; 83 display = <&display>;
75 fsl,dmacr = <0x00020010>; 84 fsl,dmacr = <0x00020010>;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_imxfb1>;
76 status = "okay"; 87 status = "okay";
77}; 88};
78 89
79&i2c1 { 90&i2c1 {
80 clock-frequency = <400000>; 91 clock-frequency = <400000>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_i2c1>;
81 status = "okay"; 94 status = "okay";
82 95
83 rtc@68 { 96 rtc@68 {
@@ -87,5 +100,127 @@
87}; 100};
88 101
89&i2c2 { 102&i2c2 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_i2c2>;
90 status = "okay"; 105 status = "okay";
91}; 106};
107
108&iomuxc {
109 imx27-apf27dev {
110 pinctrl_cspi1: cspi1grp {
111 fsl,pins = <
112 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
113 MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
114 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
115 >;
116 };
117
118 pinctrl_cspi1_cs: cspi1csgrp {
119 fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
120 };
121
122 pinctrl_cspi2: cspi2grp {
123 fsl,pins = <
124 MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
125 MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
126 MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
127 >;
128 };
129
130 pinctrl_cspi2_cs: cspi2csgrp {
131 fsl,pins = <
132 MX27_PAD_CSI_D5__GPIO2_17 0x0
133 MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
134 MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
135 >;
136 };
137
138 pinctrl_gpio_leds: gpioledsgrp {
139 fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
140 };
141
142 pinctrl_gpio_keys: gpiokeysgrp {
143 fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
144 };
145
146 pinctrl_imxfb1: imxfbgrp {
147 fsl,pins = <
148 MX27_PAD_CLS__CLS 0x0
149 MX27_PAD_CONTRAST__CONTRAST 0x0
150 MX27_PAD_LD0__LD0 0x0
151 MX27_PAD_LD1__LD1 0x0
152 MX27_PAD_LD2__LD2 0x0
153 MX27_PAD_LD3__LD3 0x0
154 MX27_PAD_LD4__LD4 0x0
155 MX27_PAD_LD5__LD5 0x0
156 MX27_PAD_LD6__LD6 0x0
157 MX27_PAD_LD7__LD7 0x0
158 MX27_PAD_LD8__LD8 0x0
159 MX27_PAD_LD9__LD9 0x0
160 MX27_PAD_LD10__LD10 0x0
161 MX27_PAD_LD11__LD11 0x0
162 MX27_PAD_LD12__LD12 0x0
163 MX27_PAD_LD13__LD13 0x0
164 MX27_PAD_LD14__LD14 0x0
165 MX27_PAD_LD15__LD15 0x0
166 MX27_PAD_LD16__LD16 0x0
167 MX27_PAD_LD17__LD17 0x0
168 MX27_PAD_LSCLK__LSCLK 0x0
169 MX27_PAD_OE_ACD__OE_ACD 0x0
170 MX27_PAD_PS__PS 0x0
171 MX27_PAD_REV__REV 0x0
172 MX27_PAD_SPL_SPR__SPL_SPR 0x0
173 MX27_PAD_HSYNC__HSYNC 0x0
174 MX27_PAD_VSYNC__VSYNC 0x0
175 >;
176 };
177
178 pinctrl_i2c1: i2c1grp {
179 fsl,pins = <
180 MX27_PAD_I2C_DATA__I2C_DATA 0x0
181 MX27_PAD_I2C_CLK__I2C_CLK 0x0
182 >;
183 };
184
185 pinctrl_i2c2: i2c2grp {
186 fsl,pins = <
187 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
188 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
189 >;
190 };
191
192 pinctrl_pwm: pwmgrp {
193 fsl,pins = <
194 MX27_PAD_PWMO__PWMO 0x0
195 >;
196 };
197
198 pinctrl_sdhc2: sdhc2grp {
199 fsl,pins = <
200 MX27_PAD_SD2_CLK__SD2_CLK 0x0
201 MX27_PAD_SD2_CMD__SD2_CMD 0x0
202 MX27_PAD_SD2_D0__SD2_D0 0x0
203 MX27_PAD_SD2_D1__SD2_D1 0x0
204 MX27_PAD_SD2_D2__SD2_D2 0x0
205 MX27_PAD_SD2_D3__SD2_D3 0x0
206 >;
207 };
208
209 pinctrl_sdhc2_cd: sdhc2cdgrp {
210 fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
211 };
212 };
213};
214
215&sdhci2 {
216 bus-width = <4>;
217 cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>;
220 status = "okay";
221};
222
223&pwm {
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_pwm>;
226};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 5a31c776513f..3c3964a99637 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -9,7 +9,7 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include "imx27-phytec-phycard-s-som.dts" 12#include "imx27-phytec-phycard-s-som.dtsi"
13 13
14/ { 14/ {
15 model = "Phytec pca100 rapid development kit"; 15 model = "Phytec pca100 rapid development kit";
@@ -37,9 +37,12 @@
37 37
38 regulators { 38 regulators {
39 compatible = "simple-bus"; 39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <0>;
40 42
41 reg_3v3: 3v3 { 43 reg_3v3: regulator@0 {
42 compatible = "regulator-fixed"; 44 compatible = "regulator-fixed";
45 reg = <0>;
43 regulator-name = "3V3"; 46 regulator-name = "3V3";
44 regulator-min-microvolt = <3300000>; 47 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>; 48 regulator-max-microvolt = <3300000>;
@@ -54,6 +57,8 @@
54}; 57};
55 58
56&i2c1 { 59&i2c1 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_i2c1>;
57 status = "okay"; 62 status = "okay";
58 63
59 rtc@51 { 64 rtc@51 {
@@ -68,26 +73,92 @@
68 }; 73 };
69}; 74};
70 75
76&iomuxc {
77 imx27-phycard-s-rdk {
78 pinctrl_i2c1: i2c1grp {
79 fsl,pins = <
80 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
81 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
82 >;
83 };
84
85 pinctrl_owire1: owire1grp {
86 fsl,pins = <
87 MX27_PAD_RTCK__OWIRE 0x0
88 >;
89 };
90
91 pinctrl_sdhc2: sdhc2grp {
92 fsl,pins = <
93 MX27_PAD_SD2_CLK__SD2_CLK 0x0
94 MX27_PAD_SD2_CMD__SD2_CMD 0x0
95 MX27_PAD_SD2_D0__SD2_D0 0x0
96 MX27_PAD_SD2_D1__SD2_D1 0x0
97 MX27_PAD_SD2_D2__SD2_D2 0x0
98 MX27_PAD_SD2_D3__SD2_D3 0x0
99 MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
100 >;
101 };
102
103 pinctrl_uart1: uart1grp {
104 fsl,pins = <
105 MX27_PAD_UART1_TXD__UART1_TXD 0x0
106 MX27_PAD_UART1_RXD__UART1_RXD 0x0
107 MX27_PAD_UART1_CTS__UART1_CTS 0x0
108 MX27_PAD_UART1_RTS__UART1_RTS 0x0
109 >;
110 };
111
112 pinctrl_uart2: uart2grp {
113 fsl,pins = <
114 MX27_PAD_UART2_TXD__UART2_TXD 0x0
115 MX27_PAD_UART2_RXD__UART2_RXD 0x0
116 MX27_PAD_UART2_CTS__UART2_CTS 0x0
117 MX27_PAD_UART2_RTS__UART2_RTS 0x0
118 >;
119 };
120
121 pinctrl_uart3: uart3grp {
122 fsl,pins = <
123 MX27_PAD_UART3_TXD__UART3_TXD 0x0
124 MX27_PAD_UART3_RXD__UART3_RXD 0x0
125 MX27_PAD_UART3_CTS__UART3_CTS 0x0
126 MX27_PAD_UART3_RTS__UART3_RTS 0x0
127 >;
128 };
129 };
130};
131
71&owire { 132&owire {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_owire1>;
72 status = "okay"; 135 status = "okay";
73}; 136};
74 137
75&sdhci2 { 138&sdhci2 {
76 cd-gpios = <&gpio3 29 0>; 139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_sdhc2>;
141 cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
77 status = "okay"; 142 status = "okay";
78}; 143};
79 144
80&uart1 { 145&uart1 {
81 fsl,uart-has-rtscts; 146 fsl,uart-has-rtscts;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_uart1>;
82 status = "okay"; 149 status = "okay";
83}; 150};
84 151
85&uart2 { 152&uart2 {
86 fsl,uart-has-rtscts; 153 fsl,uart-has-rtscts;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_uart2>;
87 status = "okay"; 156 status = "okay";
88}; 157};
89 158
90&uart3 { 159&uart3 {
91 fsl,uart-has-rtscts; 160 fsl,uart-has-rtscts;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_uart3>;
92 status = "okay"; 163 status = "okay";
93}; 164};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
deleted file mode 100644
index c8d57d1d0743..000000000000
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
3 * and Markus Pargmann, Pengutronix
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14#include "imx27.dtsi"
15
16/ {
17 model = "Phytec pca100";
18 compatible = "phytec,imx27-pca100", "fsl,imx27";
19
20 memory {
21 reg = <0xa0000000 0x08000000>; /* 128MB */
22 };
23};
24
25&cspi1 {
26 fsl,spi-num-chipselects = <2>;
27 cs-gpios = <&gpio4 28 0>,
28 <&gpio4 27 0>;
29 status = "okay";
30};
31
32&fec {
33 status = "okay";
34};
35
36&i2c2 {
37 status = "okay";
38
39 at24@52 {
40 compatible = "at,24c32";
41 pagesize = <32>;
42 reg = <0x52>;
43 };
44};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
new file mode 100644
index 000000000000..1b6248079682
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -0,0 +1,103 @@
1/*
2 * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
3 * and Markus Pargmann, Pengutronix
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14#include "imx27.dtsi"
15
16/ {
17 model = "Phytec pca100";
18 compatible = "phytec,imx27-pca100", "fsl,imx27";
19
20 memory {
21 reg = <0xa0000000 0x08000000>; /* 128MB */
22 };
23};
24
25&cspi1 {
26 fsl,spi-num-chipselects = <2>;
27 cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
28 <&gpio4 27 GPIO_ACTIVE_HIGH>;
29 status = "okay";
30};
31
32&fec {
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_fec1>;
35 status = "okay";
36};
37
38&i2c2 {
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_i2c2>;
41 status = "okay";
42
43 at24@52 {
44 compatible = "at,24c32";
45 pagesize = <32>;
46 reg = <0x52>;
47 };
48};
49
50&iomuxc {
51 imx27-phycard-s-som {
52 pinctrl_fec1: fec1grp {
53 fsl,pins = <
54 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
55 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
56 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
57 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
58 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
59 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
60 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
61 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
62 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
63 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
64 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
65 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
66 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
67 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
68 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
69 MX27_PAD_ATA_DATA13__FEC_COL 0x0
70 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
71 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
72 >;
73 };
74
75 pinctrl_i2c2: i2c2grp {
76 fsl,pins = <
77 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
78 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
79 >;
80 };
81
82 pinctrl_nfc: nfcgrp {
83 fsl,pins = <
84 MX27_PAD_NFRB__NFRB 0x0
85 MX27_PAD_NFCLE__NFCLE 0x0
86 MX27_PAD_NFWP_B__NFWP_B 0x0
87 MX27_PAD_NFCE_B__NFCE_B 0x0
88 MX27_PAD_NFALE__NFALE 0x0
89 MX27_PAD_NFRE_B__NFRE_B 0x0
90 MX27_PAD_NFWE_B__NFWE_B 0x0
91 >;
92 };
93 };
94};
95
96&nfc {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_nfc>;
99 nand-bus-width = <8>;
100 nand-ecc-mode = "hw";
101 nand-on-flash-bbt;
102 status = "okay";
103};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index 0fc6551786c6..df3b2e731835 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -7,7 +7,7 @@
7 * http://www.gnu.org/copyleft/gpl.html 7 * http://www.gnu.org/copyleft/gpl.html
8 */ 8 */
9 9
10#include "imx27-phytec-phycore-som.dts" 10#include "imx27-phytec-phycore-som.dtsi"
11 11
12/ { 12/ {
13 model = "Phytec pcm970"; 13 model = "Phytec pcm970";
@@ -16,32 +16,200 @@
16 16
17&cspi1 { 17&cspi1 {
18 fsl,spi-num-chipselects = <2>; 18 fsl,spi-num-chipselects = <2>;
19 cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>; 19 cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
20 <&gpio4 27 GPIO_ACTIVE_LOW>;
21};
22
23&i2c1 {
24 clock-frequency = <400000>;
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_i2c1>;
27 status = "okay";
28
29 camgpio: pca9536@41 {
30 compatible = "nxp,pca9536";
31 reg = <0x41>;
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35};
36
37&iomuxc {
38 imx27_phycore_rdk {
39 pinctrl_i2c1: i2c1grp {
40 /* Add pullup to DATA line */
41 fsl,pins = <
42 MX27_PAD_I2C_DATA__I2C_DATA 0x1
43 MX27_PAD_I2C_CLK__I2C_CLK 0x0
44 >;
45 };
46
47 pinctrl_owire1: owire1grp {
48 fsl,pins = <
49 MX27_PAD_RTCK__OWIRE 0x0
50 >;
51 };
52
53 pinctrl_sdhc2: sdhc2grp {
54 fsl,pins = <
55 MX27_PAD_SD2_CLK__SD2_CLK 0x0
56 MX27_PAD_SD2_CMD__SD2_CMD 0x0
57 MX27_PAD_SD2_D0__SD2_D0 0x0
58 MX27_PAD_SD2_D1__SD2_D1 0x0
59 MX27_PAD_SD2_D2__SD2_D2 0x0
60 MX27_PAD_SD2_D3__SD2_D3 0x0
61 MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */
62 MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
63 >;
64 };
65
66 pinctrl_uart1: uart1grp {
67 fsl,pins = <
68 MX27_PAD_UART1_TXD__UART1_TXD 0x0
69 MX27_PAD_UART1_RXD__UART1_RXD 0x0
70 MX27_PAD_UART1_CTS__UART1_CTS 0x0
71 MX27_PAD_UART1_RTS__UART1_RTS 0x0
72 >;
73 };
74
75 pinctrl_uart2: uart2grp {
76 fsl,pins = <
77 MX27_PAD_UART2_TXD__UART2_TXD 0x0
78 MX27_PAD_UART2_RXD__UART2_RXD 0x0
79 MX27_PAD_UART2_CTS__UART2_CTS 0x0
80 MX27_PAD_UART2_RTS__UART2_RTS 0x0
81 >;
82 };
83
84 pinctrl_usbh2: usbh2grp {
85 fsl,pins = <
86 MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
87 MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
88 MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
89 MX27_PAD_USBH2_STP__USBH2_STP 0x0
90 MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
91 MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
92 MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
93 MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
94 MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
95 MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
96 MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
97 MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
98 >;
99 };
100
101 pinctrl_weim: weimgrp {
102 fsl,pins = <
103 MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */
104 MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */
105 >;
106 };
107 };
108};
109
110&owire {
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_owire1>;
113 status = "okay";
114};
115
116&pmicleds {
117 ledr1: led@3 {
118 reg = <3>;
119 label = "system:red1:user";
120 };
121
122 ledg1: led@4 {
123 reg = <4>;
124 label = "system:green1:user";
125 };
126
127 ledb1: led@5 {
128 reg = <5>;
129 label = "system:blue1:user";
130 };
131
132 ledr2: led@6 {
133 reg = <6>;
134 label = "system:red2:user";
135 };
136
137 ledg2: led@7 {
138 reg = <7>;
139 label = "system:green2:user";
140 };
141
142 ledb2: led@8 {
143 reg = <8>;
144 label = "system:blue2:user";
145 };
146
147 ledr3: led@9 {
148 reg = <9>;
149 label = "system:red3:nand";
150 linux,default-trigger = "nand-disk";
151 };
152
153 ledg3: led@10 {
154 reg = <10>;
155 label = "system:green3:live";
156 linux,default-trigger = "heartbeat";
157 };
158
159 ledb3: led@11 {
160 reg = <11>;
161 label = "system:blue3:cpu";
162 linux,default-trigger = "cpu0";
163 };
20}; 164};
21 165
22&sdhci2 { 166&sdhci2 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_sdhc2>;
23 bus-width = <4>; 169 bus-width = <4>;
24 cd-gpios = <&gpio3 29 0>; 170 cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
25 wp-gpios = <&gpio3 28 0>; 171 wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
26 vmmc-supply = <&vmmc1_reg>; 172 vmmc-supply = <&vmmc1_reg>;
27 status = "okay"; 173 status = "okay";
28}; 174};
29 175
30&uart1 { 176&uart1 {
31 fsl,uart-has-rtscts; 177 fsl,uart-has-rtscts;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_uart1>;
180 status = "okay";
32}; 181};
33 182
34&uart2 { 183&uart2 {
35 fsl,uart-has-rtscts; 184 fsl,uart-has-rtscts;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart2>;
187 status = "okay";
188};
189
190&usbh2 {
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_usbh2>;
193 dr_mode = "host";
194 phy_type = "ulpi";
195 vbus-supply = <&reg_5v0>;
196 disable-over-current;
36 status = "okay"; 197 status = "okay";
37}; 198};
38 199
200&usbphy2 {
201 vcc-supply = <&reg_5v0>;
202};
203
39&weim { 204&weim {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_weim>;
207
40 can@d4000000 { 208 can@d4000000 {
41 compatible = "nxp,sja1000"; 209 compatible = "nxp,sja1000";
42 reg = <4 0x00000000 0x00000100>; 210 reg = <4 0x00000000 0x00000100>;
43 interrupt-parent = <&gpio5>; 211 interrupt-parent = <&gpio5>;
44 interrupts = <19 0x2>; 212 interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
45 nxp,external-clock-frequency = <16000000>; 213 nxp,external-clock-frequency = <16000000>;
46 nxp,tx-output-config = <0x16>; 214 nxp,tx-output-config = <0x16>;
47 nxp,no-comparator-bypass; 215 nxp,no-comparator-bypass;
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index 4ec402c38945..cefaa6994623 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -19,6 +19,28 @@
19 memory { 19 memory {
20 reg = <0xa0000000 0x08000000>; 20 reg = <0xa0000000 0x08000000>;
21 }; 21 };
22
23 regulators {
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 reg_3v3: regulator@0 {
29 compatible = "regulator-fixed";
30 reg = <0>;
31 regulator-name = "3V3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 };
35
36 reg_5v0: regulator@1 {
37 compatible = "regulator-fixed";
38 reg = <1>;
39 regulator-name = "5V0";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
42 };
43 };
22}; 44};
23 45
24&audmux { 46&audmux {
@@ -37,21 +59,30 @@
37}; 59};
38 60
39&cspi1 { 61&cspi1 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_cspi1>;
40 fsl,spi-num-chipselects = <1>; 64 fsl,spi-num-chipselects = <1>;
41 cs-gpios = <&gpio4 28 0>; 65 cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
42 status = "okay"; 66 status = "okay";
43 67
44 pmic: mc13783@0 { 68 pmic: mc13783@0 {
45 #address-cells = <1>; 69 #address-cells = <1>;
46 #size-cells = <0>; 70 #size-cells = <0>;
47 compatible = "fsl,mc13783"; 71 compatible = "fsl,mc13783";
48 spi-max-frequency = <20000000>;
49 reg = <0>; 72 reg = <0>;
73 spi-cs-high;
74 spi-max-frequency = <20000000>;
50 interrupt-parent = <&gpio2>; 75 interrupt-parent = <&gpio2>;
51 interrupts = <23 0x4>; 76 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
52 fsl,mc13xxx-uses-adc; 77 fsl,mc13xxx-uses-adc;
53 fsl,mc13xxx-uses-rtc; 78 fsl,mc13xxx-uses-rtc;
54 79
80 pmicleds: leds {
81 #address-cells = <1>;
82 #size-cells = <0>;
83 led-control = <0x001 0x000 0x000 0x000 0x000 0x000>;
84 };
85
55 regulators { 86 regulators {
56 /* SW1A and SW1B joined operation */ 87 /* SW1A and SW1B joined operation */
57 sw1_reg: sw1a { 88 sw1_reg: sw1a {
@@ -134,12 +165,18 @@
134}; 165};
135 166
136&fec { 167&fec {
137 phy-reset-gpios = <&gpio3 30 0>; 168 phy-mode = "mii";
169 phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
170 phy-supply = <&reg_3v3>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_fec1>;
138 status = "okay"; 173 status = "okay";
139}; 174};
140 175
141&i2c2 { 176&i2c2 {
142 clock-frequency = <400000>; 177 clock-frequency = <400000>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c2>;
143 status = "okay"; 180 status = "okay";
144 181
145 at24@52 { 182 at24@52 {
@@ -159,16 +196,102 @@
159 }; 196 };
160}; 197};
161 198
199&iomuxc {
200 imx27_phycore_som {
201 pinctrl_cspi1: cspi1grp {
202 fsl,pins = <
203 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
204 MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
205 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
206 MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */
207 MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */
208 >;
209 };
210
211 pinctrl_fec1: fec1grp {
212 fsl,pins = <
213 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
214 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
215 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
216 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
217 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
218 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
219 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
220 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
221 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
222 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
223 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
224 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
225 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
226 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
227 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
228 MX27_PAD_ATA_DATA13__FEC_COL 0x0
229 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
230 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
231 MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
232 >;
233 };
234
235 pinctrl_i2c2: i2c2grp {
236 fsl,pins = <
237 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
238 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
239 >;
240 };
241
242 pinctrl_nfc: nfcgrp {
243 fsl,pins = <
244 MX27_PAD_NFRB__NFRB 0x0
245 MX27_PAD_NFCLE__NFCLE 0x0
246 MX27_PAD_NFWP_B__NFWP_B 0x0
247 MX27_PAD_NFCE_B__NFCE_B 0x0
248 MX27_PAD_NFALE__NFALE 0x0
249 MX27_PAD_NFRE_B__NFRE_B 0x0
250 MX27_PAD_NFWE_B__NFWE_B 0x0
251 >;
252 };
253
254 pinctrl_usbotg: usbotggrp {
255 fsl,pins = <
256 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
257 MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
258 MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
259 MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
260 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
261 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
262 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
263 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
264 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
265 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
266 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
267 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
268 >;
269 };
270 };
271};
272
162&nfc { 273&nfc {
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_nfc>;
163 nand-bus-width = <8>; 276 nand-bus-width = <8>;
164 nand-ecc-mode = "hw"; 277 nand-ecc-mode = "hw";
278 nand-on-flash-bbt;
165 status = "okay"; 279 status = "okay";
166}; 280};
167 281
168&uart1 { 282&usbotg {
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_usbotg>;
285 dr_mode = "otg";
286 phy_type = "ulpi";
287 vbus-supply = <&sw3_reg>;
169 status = "okay"; 288 status = "okay";
170}; 289};
171 290
291&usbphy0 {
292 vcc-supply = <&sw3_reg>;
293};
294
172&weim { 295&weim {
173 status = "okay"; 296 status = "okay";
174 297
diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/imx27-pinfunc.h
new file mode 100644
index 000000000000..f5387b4de577
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-pinfunc.h
@@ -0,0 +1,526 @@
1/*
2 * Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __DTS_IMX27_PINFUNC_H
13#define __DTS_IMX27_PINFUNC_H
14
15/*
16 * The pin function ID is a tuple of
17 * <pin mux_id>
18 * mux_id consists of
19 * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
20 *
21 * function: 0 - Primary function
22 * 1 - Alternate function
23 * 2 - GPIO
24 * direction: 0 - Input
25 * 1 - Output
26 * gpio_oconf: 0 - A_IN
27 * 1 - B_IN
28 * 2 - C_IN
29 * 3 - Data Register
30 * gpio_iconfa/b: 0 - GPIO_IN
31 * 1 - Interrupt Status Register
32 * 2 - 0
33 * 3 - 1
34 *
35 * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
36 * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
37 * number on the specific port (between 0 and 31).
38 */
39
40#define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
41#define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032
42#define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
43#define MX27_PAD_USBH2_DIR__GPIO1_1 0x01 0x032
44#define MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x02 0x004
45#define MX27_PAD_USBH2_DATA7__GPIO1_2 0x02 0x032
46#define MX27_PAD_USBH2_NXT__USBH2_NXT 0x03 0x000
47#define MX27_PAD_USBH2_NXT__GPIO1_3 0x03 0x032
48#define MX27_PAD_USBH2_STP__USBH2_STP 0x04 0x004
49#define MX27_PAD_USBH2_STP__GPIO1_4 0x04 0x032
50#define MX27_PAD_LSCLK__LSCLK 0x05 0x004
51#define MX27_PAD_LSCLK__GPIO1_5 0x05 0x032
52#define MX27_PAD_LD0__LD0 0x06 0x004
53#define MX27_PAD_LD0__GPIO1_6 0x06 0x032
54#define MX27_PAD_LD1__LD1 0x07 0x004
55#define MX27_PAD_LD1__GPIO1_7 0x07 0x032
56#define MX27_PAD_LD2__LD2 0x08 0x004
57#define MX27_PAD_LD2__GPIO1_8 0x08 0x032
58#define MX27_PAD_LD3__LD3 0x09 0x004
59#define MX27_PAD_LD3__GPIO1_9 0x09 0x032
60#define MX27_PAD_LD4__LD4 0x0a 0x004
61#define MX27_PAD_LD4__GPIO1_10 0x0a 0x032
62#define MX27_PAD_LD5__LD5 0x0b 0x004
63#define MX27_PAD_LD5__GPIO1_11 0x0b 0x032
64#define MX27_PAD_LD6__LD6 0x0c 0x004
65#define MX27_PAD_LD6__GPIO1_12 0x0c 0x032
66#define MX27_PAD_LD7__LD7 0x0d 0x004
67#define MX27_PAD_LD7__GPIO1_13 0x0d 0x032
68#define MX27_PAD_LD8__LD8 0x0e 0x004
69#define MX27_PAD_LD8__GPIO1_14 0x0e 0x032
70#define MX27_PAD_LD9__LD9 0x0f 0x004
71#define MX27_PAD_LD9__GPIO1_15 0x0f 0x032
72#define MX27_PAD_LD10__LD10 0x10 0x004
73#define MX27_PAD_LD10__GPIO1_16 0x10 0x032
74#define MX27_PAD_LD11__LD11 0x11 0x004
75#define MX27_PAD_LD11__GPIO1_17 0x11 0x032
76#define MX27_PAD_LD12__LD12 0x12 0x004
77#define MX27_PAD_LD12__GPIO1_18 0x12 0x032
78#define MX27_PAD_LD13__LD13 0x13 0x004
79#define MX27_PAD_LD13__GPIO1_19 0x13 0x032
80#define MX27_PAD_LD14__LD14 0x14 0x004
81#define MX27_PAD_LD14__GPIO1_20 0x14 0x032
82#define MX27_PAD_LD15__LD15 0x15 0x004
83#define MX27_PAD_LD15__GPIO1_21 0x15 0x032
84#define MX27_PAD_LD16__LD16 0x16 0x004
85#define MX27_PAD_LD16__GPIO1_22 0x16 0x032
86#define MX27_PAD_LD17__LD17 0x17 0x004
87#define MX27_PAD_LD17__GPIO1_23 0x17 0x032
88#define MX27_PAD_REV__REV 0x18 0x004
89#define MX27_PAD_REV__GPIO1_24 0x18 0x032
90#define MX27_PAD_CLS__CLS 0x19 0x004
91#define MX27_PAD_CLS__GPIO1_25 0x19 0x032
92#define MX27_PAD_PS__PS 0x1a 0x004
93#define MX27_PAD_PS__GPIO1_26 0x1a 0x032
94#define MX27_PAD_SPL_SPR__SPL_SPR 0x1b 0x004
95#define MX27_PAD_SPL_SPR__GPIO1_27 0x1b 0x032
96#define MX27_PAD_HSYNC__HSYNC 0x1c 0x004
97#define MX27_PAD_HSYNC__GPIO1_28 0x1c 0x032
98#define MX27_PAD_VSYNC__VSYNC 0x1d 0x004
99#define MX27_PAD_VSYNC__GPIO1_29 0x1d 0x032
100#define MX27_PAD_CONTRAST__CONTRAST 0x1e 0x004
101#define MX27_PAD_CONTRAST__GPIO1_30 0x1e 0x032
102#define MX27_PAD_OE_ACD__OE_ACD 0x1f 0x004
103#define MX27_PAD_OE_ACD__GPIO1_31 0x1f 0x032
104#define MX27_PAD_UNUSED0__UNUSED0 0x20 0x004
105#define MX27_PAD_UNUSED0__GPIO2_0 0x20 0x032
106#define MX27_PAD_UNUSED1__UNUSED1 0x21 0x004
107#define MX27_PAD_UNUSED1__GPIO2_1 0x21 0x032
108#define MX27_PAD_UNUSED2__UNUSED2 0x22 0x004
109#define MX27_PAD_UNUSED2__GPIO2_2 0x22 0x032
110#define MX27_PAD_UNUSED3__UNUSED3 0x23 0x004
111#define MX27_PAD_UNUSED3__GPIO2_3 0x23 0x032
112#define MX27_PAD_SD2_D0__SD2_D0 0x24 0x004
113#define MX27_PAD_SD2_D0__MSHC_DATA0 0x24 0x005
114#define MX27_PAD_SD2_D0__GPIO2_4 0x24 0x032
115#define MX27_PAD_SD2_D1__SD2_D1 0x25 0x004
116#define MX27_PAD_SD2_D1__MSHC_DATA1 0x25 0x005
117#define MX27_PAD_SD2_D1__GPIO2_5 0x25 0x032
118#define MX27_PAD_SD2_D2__SD2_D2 0x26 0x004
119#define MX27_PAD_SD2_D2__MSHC_DATA2 0x26 0x005
120#define MX27_PAD_SD2_D2__GPIO2_6 0x26 0x032
121#define MX27_PAD_SD2_D3__SD2_D3 0x27 0x004
122#define MX27_PAD_SD2_D3__MSHC_DATA3 0x27 0x005
123#define MX27_PAD_SD2_D3__GPIO2_7 0x27 0x032
124#define MX27_PAD_SD2_CMD__SD2_CMD 0x28 0x004
125#define MX27_PAD_SD2_CMD__MSHC_BS 0x28 0x005
126#define MX27_PAD_SD2_CMD__GPIO2_8 0x28 0x032
127#define MX27_PAD_SD2_CLK__SD2_CLK 0x29 0x004
128#define MX27_PAD_SD2_CLK__MSHC_SCLK 0x29 0x005
129#define MX27_PAD_SD2_CLK__GPIO2_9 0x29 0x032
130#define MX27_PAD_CSI_D0__CSI_D0 0x2a 0x000
131#define MX27_PAD_CSI_D0__UART6_TXD 0x2a 0x005
132#define MX27_PAD_CSI_D0__GPIO2_10 0x2a 0x032
133#define MX27_PAD_CSI_D1__CSI_D1 0x2b 0x000
134#define MX27_PAD_CSI_D1__UART6_RXD 0x2b 0x001
135#define MX27_PAD_CSI_D1__GPIO2_11 0x2b 0x032
136#define MX27_PAD_CSI_D2__CSI_D2 0x2c 0x000
137#define MX27_PAD_CSI_D2__UART6_CTS 0x2c 0x005
138#define MX27_PAD_CSI_D2__GPIO2_12 0x2c 0x032
139#define MX27_PAD_CSI_D3__CSI_D3 0x2d 0x000
140#define MX27_PAD_CSI_D3__UART6_RTS 0x2d 0x001
141#define MX27_PAD_CSI_D3__GPIO2_13 0x2d 0x032
142#define MX27_PAD_CSI_D4__CSI_D4 0x2e 0x000
143#define MX27_PAD_CSI_D4__GPIO2_14 0x2e 0x032
144#define MX27_PAD_CSI_MCLK__CSI_MCLK 0x2f 0x004
145#define MX27_PAD_CSI_MCLK__GPIO2_15 0x2f 0x032
146#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK 0x30 0x000
147#define MX27_PAD_CSI_PIXCLK__GPIO2_16 0x30 0x032
148#define MX27_PAD_CSI_D5__CSI_D5 0x31 0x000
149#define MX27_PAD_CSI_D5__GPIO2_17 0x31 0x032
150#define MX27_PAD_CSI_D6__CSI_D6 0x32 0x000
151#define MX27_PAD_CSI_D6__UART5_TXD 0x32 0x005
152#define MX27_PAD_CSI_D6__GPIO2_18 0x32 0x032
153#define MX27_PAD_CSI_D7__CSI_D7 0x33 0x000
154#define MX27_PAD_CSI_D7__UART5_RXD 0x33 0x001
155#define MX27_PAD_CSI_D7__GPIO2_19 0x33 0x032
156#define MX27_PAD_CSI_VSYNC__CSI_VSYNC 0x34 0x000
157#define MX27_PAD_CSI_VSYNC__UART5_CTS 0x34 0x005
158#define MX27_PAD_CSI_VSYNC__GPIO2_20 0x34 0x032
159#define MX27_PAD_CSI_HSYNC__CSI_HSYNC 0x35 0x000
160#define MX27_PAD_CSI_HSYNC__UART5_RTS 0x35 0x001
161#define MX27_PAD_CSI_HSYNC__GPIO2_21 0x35 0x032
162#define MX27_PAD_USBH1_SUSP__USBH1_SUSP 0x36 0x004
163#define MX27_PAD_USBH1_SUSP__GPIO2_22 0x36 0x032
164#define MX27_PAD_USB_PWR__USB_PWR 0x37 0x004
165#define MX27_PAD_USB_PWR__GPIO2_23 0x37 0x032
166#define MX27_PAD_USB_OC_B__USB_OC_B 0x38 0x000
167#define MX27_PAD_USB_OC_B__GPIO2_24 0x38 0x032
168#define MX27_PAD_USBH1_RCV__USBH1_RCV 0x39 0x004
169#define MX27_PAD_USBH1_RCV__GPIO2_25 0x39 0x032
170#define MX27_PAD_USBH1_FS__USBH1_FS 0x3a 0x004
171#define MX27_PAD_USBH1_FS__UART4_RTS 0x3a 0x001
172#define MX27_PAD_USBH1_FS__GPIO2_26 0x3a 0x032
173#define MX27_PAD_USBH1_OE_B__USBH1_OE_B 0x3b 0x004
174#define MX27_PAD_USBH1_OE_B__GPIO2_27 0x3b 0x032
175#define MX27_PAD_USBH1_TXDM__USBH1_TXDM 0x3c 0x004
176#define MX27_PAD_USBH1_TXDM__UART4_TXD 0x3c 0x005
177#define MX27_PAD_USBH1_TXDM__GPIO2_28 0x3c 0x032
178#define MX27_PAD_USBH1_TXDP__USBH1_TXDP 0x3d 0x004
179#define MX27_PAD_USBH1_TXDP__UART4_CTS 0x3d 0x005
180#define MX27_PAD_USBH1_TXDP__GPIO2_29 0x3d 0x032
181#define MX27_PAD_USBH1_RXDM__USBH1_RXDM 0x3e 0x004
182#define MX27_PAD_USBH1_RXDM__GPIO2_30 0x3e 0x032
183#define MX27_PAD_USBH1_RXDP__USBH1_RXDP 0x3f 0x004
184#define MX27_PAD_USBH1_RXDP__UART4_RXD 0x3f 0x001
185#define MX27_PAD_USBH1_RXDP__GPIO2_31 0x3f 0x032
186#define MX27_PAD_UNUSED4__UNUSED4 0x40 0x004
187#define MX27_PAD_UNUSED4__GPIO3_0 0x40 0x032
188#define MX27_PAD_UNUSED5__UNUSED5 0x41 0x004
189#define MX27_PAD_UNUSED5__GPIO3_1 0x41 0x032
190#define MX27_PAD_UNUSED6__UNUSED6 0x42 0x004
191#define MX27_PAD_UNUSED6__GPIO3_2 0x42 0x032
192#define MX27_PAD_UNUSED7__UNUSED7 0x43 0x004
193#define MX27_PAD_UNUSED7__GPIO3_3 0x43 0x032
194#define MX27_PAD_UNUSED8__UNUSED8 0x44 0x004
195#define MX27_PAD_UNUSED8__GPIO3_4 0x44 0x032
196#define MX27_PAD_I2C2_SDA__I2C2_SDA 0x45 0x004
197#define MX27_PAD_I2C2_SDA__GPIO3_5 0x45 0x032
198#define MX27_PAD_I2C2_SCL__I2C2_SCL 0x46 0x004
199#define MX27_PAD_I2C2_SCL__GPIO3_6 0x46 0x032
200#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x47 0x004
201#define MX27_PAD_USBOTG_DATA5__GPIO3_7 0x47 0x032
202#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x48 0x004
203#define MX27_PAD_USBOTG_DATA6__GPIO3_8 0x48 0x032
204#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x49 0x004
205#define MX27_PAD_USBOTG_DATA0__GPIO3_9 0x49 0x032
206#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x4a 0x004
207#define MX27_PAD_USBOTG_DATA2__GPIO3_10 0x4a 0x032
208#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x4b 0x004
209#define MX27_PAD_USBOTG_DATA1__GPIO3_11 0x4b 0x032
210#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x4c 0x004
211#define MX27_PAD_USBOTG_DATA4__GPIO3_12 0x4c 0x032
212#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x4d 0x004
213#define MX27_PAD_USBOTG_DATA3__GPIO3_13 0x4d 0x032
214#define MX27_PAD_TOUT__TOUT 0x4e 0x004
215#define MX27_PAD_TOUT__GPIO3_14 0x4e 0x032
216#define MX27_PAD_TIN__TIN 0x4f 0x000
217#define MX27_PAD_TIN__GPIO3_15 0x4f 0x032
218#define MX27_PAD_SSI4_FS__SSI4_FS 0x50 0x004
219#define MX27_PAD_SSI4_FS__GPIO3_16 0x50 0x032
220#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x51 0x004
221#define MX27_PAD_SSI4_RXDAT__GPIO3_17 0x51 0x032
222#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x52 0x004
223#define MX27_PAD_SSI4_TXDAT__GPIO3_18 0x52 0x032
224#define MX27_PAD_SSI4_CLK__SSI4_CLK 0x53 0x004
225#define MX27_PAD_SSI4_CLK__GPIO3_19 0x53 0x032
226#define MX27_PAD_SSI1_FS__SSI1_FS 0x54 0x004
227#define MX27_PAD_SSI1_FS__GPIO3_20 0x54 0x032
228#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x55 0x004
229#define MX27_PAD_SSI1_RXDAT__GPIO3_21 0x55 0x032
230#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x56 0x004
231#define MX27_PAD_SSI1_TXDAT__GPIO3_22 0x56 0x032
232#define MX27_PAD_SSI1_CLK__SSI1_CLK 0x57 0x004
233#define MX27_PAD_SSI1_CLK__GPIO3_23 0x57 0x032
234#define MX27_PAD_SSI2_FS__SSI2_FS 0x58 0x004
235#define MX27_PAD_SSI2_FS__GPT5_TOUT 0x58 0x005
236#define MX27_PAD_SSI2_FS__GPIO3_24 0x58 0x032
237#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT 0x59 0x004
238#define MX27_PAD_SSI2_RXDAT__GPTS_TIN 0x59 0x001
239#define MX27_PAD_SSI2_RXDAT__GPIO3_25 0x59 0x032
240#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT 0x5a 0x004
241#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT 0x5a 0x005
242#define MX27_PAD_SSI2_TXDAT__GPIO3_26 0x5a 0x032
243#define MX27_PAD_SSI2_CLK__SSI2_CLK 0x5b 0x004
244#define MX27_PAD_SSI2_CLK__GPT4_TIN 0x5b 0x001
245#define MX27_PAD_SSI2_CLK__GPIO3_27 0x5b 0x032
246#define MX27_PAD_SSI3_FS__SSI3_FS 0x5c 0x004
247#define MX27_PAD_SSI3_FS__SLCDC2_D0 0x5c 0x001
248#define MX27_PAD_SSI3_FS__GPIO3_28 0x5c 0x032
249#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT 0x5d 0x004
250#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS 0x5d 0x001
251#define MX27_PAD_SSI3_RXDAT__GPIO3_29 0x5d 0x032
252#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT 0x5e 0x004
253#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS 0x5e 0x001
254#define MX27_PAD_SSI3_TXDAT__GPIO3_30 0x5e 0x032
255#define MX27_PAD_SSI3_CLK__SSI3_CLK 0x5f 0x004
256#define MX27_PAD_SSI3_CLK__SLCDC2_CLK 0x5f 0x001
257#define MX27_PAD_SSI3_CLK__GPIO3_31 0x5f 0x032
258#define MX27_PAD_SD3_CMD__SD3_CMD 0x60 0x004
259#define MX27_PAD_SD3_CMD__FEC_TXD0 0x60 0x006
260#define MX27_PAD_SD3_CMD__GPIO4_0 0x60 0x032
261#define MX27_PAD_SD3_CLK__SD3_CLK 0x61 0x004
262#define MX27_PAD_SD3_CLK__ETMTRACEPKT15 0x61 0x005
263#define MX27_PAD_SD3_CLK__FEC_TXD1 0x61 0x006
264#define MX27_PAD_SD3_CLK__GPIO4_1 0x61 0x032
265#define MX27_PAD_ATA_DATA0__ATA_DATA0 0x62 0x004
266#define MX27_PAD_ATA_DATA0__SD3_D0 0x62 0x005
267#define MX27_PAD_ATA_DATA0__FEC_TXD2 0x62 0x006
268#define MX27_PAD_ATA_DATA0__GPIO4_2 0x62 0x032
269#define MX27_PAD_ATA_DATA1__ATA_DATA1 0x63 0x004
270#define MX27_PAD_ATA_DATA1__SD3_D1 0x63 0x005
271#define MX27_PAD_ATA_DATA1__FEC_TXD3 0x63 0x006
272#define MX27_PAD_ATA_DATA1__GPIO4_3 0x63 0x032
273#define MX27_PAD_ATA_DATA2__ATA_DATA2 0x64 0x004
274#define MX27_PAD_ATA_DATA2__SD3_D2 0x64 0x005
275#define MX27_PAD_ATA_DATA2__FEC_RX_ER 0x64 0x002
276#define MX27_PAD_ATA_DATA2__GPIO4_4 0x64 0x032
277#define MX27_PAD_ATA_DATA3__ATA_DATA3 0x65 0x004
278#define MX27_PAD_ATA_DATA3__SD3_D3 0x65 0x005
279#define MX27_PAD_ATA_DATA3__FEC_RXD1 0x65 0x002
280#define MX27_PAD_ATA_DATA3__GPIO4_5 0x65 0x032
281#define MX27_PAD_ATA_DATA4__ATA_DATA4 0x66 0x004
282#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14 0x66 0x005
283#define MX27_PAD_ATA_DATA4__FEC_RXD2 0x66 0x002
284#define MX27_PAD_ATA_DATA4__GPIO4_6 0x66 0x032
285#define MX27_PAD_ATA_DATA5__ATA_DATA5 0x67 0x004
286#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13 0x67 0x005
287#define MX27_PAD_ATA_DATA5__FEC_RXD3 0x67 0x002
288#define MX27_PAD_ATA_DATA5__GPIO4_7 0x67 0x032
289#define MX27_PAD_ATA_DATA6__ATA_DATA6 0x68 0x004
290#define MX27_PAD_ATA_DATA6__FEC_MDIO 0x68 0x005
291#define MX27_PAD_ATA_DATA6__GPIO4_8 0x68 0x032
292#define MX27_PAD_ATA_DATA7__ATA_DATA7 0x69 0x004
293#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12 0x69 0x005
294#define MX27_PAD_ATA_DATA7__FEC_MDC 0x69 0x006
295#define MX27_PAD_ATA_DATA7__GPIO4_9 0x69 0x032
296#define MX27_PAD_ATA_DATA8__ATA_DATA8 0x6a 0x004
297#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11 0x6a 0x005
298#define MX27_PAD_ATA_DATA8__FEC_CRS 0x6a 0x002
299#define MX27_PAD_ATA_DATA8__GPIO4_10 0x6a 0x032
300#define MX27_PAD_ATA_DATA9__ATA_DATA9 0x6b 0x004
301#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10 0x6b 0x005
302#define MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x6b 0x002
303#define MX27_PAD_ATA_DATA9__GPIO4_11 0x6b 0x032
304#define MX27_PAD_ATA_DATA10__ATA_DATA10 0x6c 0x004
305#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9 0x6c 0x005
306#define MX27_PAD_ATA_DATA10__FEC_RXD0 0x6c 0x002
307#define MX27_PAD_ATA_DATA10__GPIO4_12 0x6c 0x032
308#define MX27_PAD_ATA_DATA11__ATA_DATA11 0x6d 0x004
309#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8 0x6d 0x005
310#define MX27_PAD_ATA_DATA11__FEC_RX_DV 0x6d 0x002
311#define MX27_PAD_ATA_DATA11__GPIO4_13 0x6d 0x032
312#define MX27_PAD_ATA_DATA12__ATA_DATA12 0x6e 0x004
313#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7 0x6e 0x005
314#define MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x6e 0x002
315#define MX27_PAD_ATA_DATA12__GPIO4_14 0x6e 0x032
316#define MX27_PAD_ATA_DATA13__ATA_DATA13 0x6f 0x004
317#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6 0x6f 0x005
318#define MX27_PAD_ATA_DATA13__FEC_COL 0x6f 0x002
319#define MX27_PAD_ATA_DATA13__GPIO4_15 0x6f 0x032
320#define MX27_PAD_ATA_DATA14__ATA_DATA14 0x70 0x004
321#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5 0x70 0x005
322#define MX27_PAD_ATA_DATA14__FEC_TX_ER 0x70 0x006
323#define MX27_PAD_ATA_DATA14__GPIO4_16 0x70 0x032
324#define MX27_PAD_I2C_DATA__I2C_DATA 0x71 0x004
325#define MX27_PAD_I2C_DATA__GPIO4_17 0x71 0x032
326#define MX27_PAD_I2C_CLK__I2C_CLK 0x72 0x004
327#define MX27_PAD_I2C_CLK__GPIO4_18 0x72 0x032
328#define MX27_PAD_CSPI2_SS2__CSPI2_SS2 0x73 0x004
329#define MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x73 0x005
330#define MX27_PAD_CSPI2_SS2__GPIO4_19 0x73 0x032
331#define MX27_PAD_CSPI2_SS1__CSPI2_SS1 0x74 0x004
332#define MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x74 0x005
333#define MX27_PAD_CSPI2_SS1__GPIO4_20 0x74 0x032
334#define MX27_PAD_CSPI2_SS0__CSPI2_SS0 0x75 0x004
335#define MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x75 0x005
336#define MX27_PAD_CSPI2_SS0__GPIO4_21 0x75 0x032
337#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x76 0x004
338#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x76 0x005
339#define MX27_PAD_CSPI2_SCLK__GPIO4_22 0x76 0x032
340#define MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x77 0x004
341#define MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x77 0x005
342#define MX27_PAD_CSPI2_MISO__GPIO4_23 0x77 0x032
343#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x78 0x004
344#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x78 0x005
345#define MX27_PAD_CSPI2_MOSI__GPIO4_24 0x78 0x032
346#define MX27_PAD_CSPI1_RDY__CSPI1_RDY 0x79 0x000
347#define MX27_PAD_CSPI1_RDY__GPIO4_25 0x79 0x032
348#define MX27_PAD_CSPI1_SS2__CSPI1_SS2 0x7a 0x004
349#define MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x7a 0x005
350#define MX27_PAD_CSPI1_SS2__GPIO4_26 0x7a 0x032
351#define MX27_PAD_CSPI1_SS1__CSPI1_SS1 0x7b 0x004
352#define MX27_PAD_CSPI1_SS1__GPIO4_27 0x7b 0x032
353#define MX27_PAD_CSPI1_SS0__CSPI1_SS0 0x7c 0x004
354#define MX27_PAD_CSPI1_SS0__GPIO4_28 0x7c 0x032
355#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x7d 0x004
356#define MX27_PAD_CSPI1_SCLK__GPIO4_29 0x7d 0x032
357#define MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x7e 0x004
358#define MX27_PAD_CSPI1_MISO__GPIO4_30 0x7e 0x032
359#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x7f 0x004
360#define MX27_PAD_CSPI1_MOSI__GPIO4_31 0x7f 0x032
361#define MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x80 0x000
362#define MX27_PAD_USBOTG_NXT__KP_COL6A 0x80 0x005
363#define MX27_PAD_USBOTG_NXT__GPIO5_0 0x80 0x032
364#define MX27_PAD_USBOTG_STP__USBOTG_STP 0x81 0x004
365#define MX27_PAD_USBOTG_STP__KP_ROW6A 0x81 0x005
366#define MX27_PAD_USBOTG_STP__GPIO5_1 0x81 0x032
367#define MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x82 0x000
368#define MX27_PAD_USBOTG_DIR__KP_ROW7A 0x82 0x005
369#define MX27_PAD_USBOTG_DIR__GPIO5_2 0x82 0x032
370#define MX27_PAD_UART2_CTS__UART2_CTS 0x83 0x004
371#define MX27_PAD_UART2_CTS__KP_COL7 0x83 0x005
372#define MX27_PAD_UART2_CTS__GPIO5_3 0x83 0x032
373#define MX27_PAD_UART2_RTS__UART2_RTS 0x84 0x000
374#define MX27_PAD_UART2_RTS__KP_ROW7 0x84 0x005
375#define MX27_PAD_UART2_RTS__GPIO5_4 0x84 0x032
376#define MX27_PAD_PWMO__PWMO 0x85 0x004
377#define MX27_PAD_PWMO__GPIO5_5 0x85 0x032
378#define MX27_PAD_UART2_TXD__UART2_TXD 0x86 0x004
379#define MX27_PAD_UART2_TXD__KP_COL6 0x86 0x005
380#define MX27_PAD_UART2_TXD__GPIO5_6 0x86 0x032
381#define MX27_PAD_UART2_RXD__UART2_RXD 0x87 0x000
382#define MX27_PAD_UART2_RXD__KP_ROW6 0x87 0x005
383#define MX27_PAD_UART2_RXD__GPIO5_7 0x87 0x032
384#define MX27_PAD_UART3_TXD__UART3_TXD 0x88 0x004
385#define MX27_PAD_UART3_TXD__GPIO5_8 0x88 0x032
386#define MX27_PAD_UART3_RXD__UART3_RXD 0x89 0x000
387#define MX27_PAD_UART3_RXD__GPIO5_9 0x89 0x032
388#define MX27_PAD_UART3_CTS__UART3_CTS 0x8a 0x004
389#define MX27_PAD_UART3_CTS__GPIO5_10 0x8a 0x032
390#define MX27_PAD_UART3_RTS__UART3_RTS 0x8b 0x000
391#define MX27_PAD_UART3_RTS__GPIO5_11 0x8b 0x032
392#define MX27_PAD_UART1_TXD__UART1_TXD 0x8c 0x004
393#define MX27_PAD_UART1_TXD__GPIO5_12 0x8c 0x032
394#define MX27_PAD_UART1_RXD__UART1_RXD 0x8d 0x000
395#define MX27_PAD_UART1_RXD__GPIO5_13 0x8d 0x032
396#define MX27_PAD_UART1_CTS__UART1_CTS 0x8e 0x004
397#define MX27_PAD_UART1_CTS__GPIO5_14 0x8e 0x032
398#define MX27_PAD_UART1_RTS__UART1_RTS 0x8f 0x000
399#define MX27_PAD_UART1_RTS__GPIO5_15 0x8f 0x032
400#define MX27_PAD_RTCK__RTCK 0x90 0x004
401#define MX27_PAD_RTCK__OWIRE 0x90 0x005
402#define MX27_PAD_RTCK__GPIO5_16 0x90 0x032
403#define MX27_PAD_RESET_OUT_B__RESET_OUT_B 0x91 0x004
404#define MX27_PAD_RESET_OUT_B__GPIO5_17 0x91 0x032
405#define MX27_PAD_SD1_D0__SD1_D0 0x92 0x004
406#define MX27_PAD_SD1_D0__CSPI3_MISO 0x92 0x001
407#define MX27_PAD_SD1_D0__GPIO5_18 0x92 0x032
408#define MX27_PAD_SD1_D1__SD1_D1 0x93 0x004
409#define MX27_PAD_SD1_D1__GPIO5_19 0x93 0x032
410#define MX27_PAD_SD1_D2__SD1_D2 0x94 0x004
411#define MX27_PAD_SD1_D2__GPIO5_20 0x94 0x032
412#define MX27_PAD_SD1_D3__SD1_D3 0x95 0x004
413#define MX27_PAD_SD1_D3__CSPI3_SS 0x95 0x005
414#define MX27_PAD_SD1_D3__GPIO5_21 0x95 0x032
415#define MX27_PAD_SD1_CMD__SD1_CMD 0x96 0x004
416#define MX27_PAD_SD1_CMD__CSPI3_MOSI 0x96 0x005
417#define MX27_PAD_SD1_CMD__GPIO5_22 0x96 0x032
418#define MX27_PAD_SD1_CLK__SD1_CLK 0x97 0x004
419#define MX27_PAD_SD1_CLK__CSPI3_SCLK 0x97 0x005
420#define MX27_PAD_SD1_CLK__GPIO5_23 0x97 0x032
421#define MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x98 0x000
422#define MX27_PAD_USBOTG_CLK__GPIO5_24 0x98 0x032
423#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x99 0x004
424#define MX27_PAD_USBOTG_DATA7__GPIO5_25 0x99 0x032
425#define MX27_PAD_UNUSED9__UNUSED9 0x9a 0x004
426#define MX27_PAD_UNUSED9__GPIO5_26 0x9a 0x032
427#define MX27_PAD_UNUSED10__UNUSED10 0x9b 0x004
428#define MX27_PAD_UNUSED10__GPIO5_27 0x9b 0x032
429#define MX27_PAD_UNUSED11__UNUSED11 0x9c 0x004
430#define MX27_PAD_UNUSED11__GPIO5_28 0x9c 0x032
431#define MX27_PAD_UNUSED12__UNUSED12 0x9d 0x004
432#define MX27_PAD_UNUSED12__GPIO5_29 0x9d 0x032
433#define MX27_PAD_UNUSED13__UNUSED13 0x9e 0x004
434#define MX27_PAD_UNUSED13__GPIO5_30 0x9e 0x032
435#define MX27_PAD_UNUSED14__UNUSED14 0x9f 0x004
436#define MX27_PAD_UNUSED14__GPIO5_31 0x9f 0x032
437#define MX27_PAD_NFRB__NFRB 0xa0 0x000
438#define MX27_PAD_NFRB__ETMTRACEPKT3 0xa0 0x005
439#define MX27_PAD_NFRB__GPIO6_0 0xa0 0x032
440#define MX27_PAD_NFCLE__NFCLE 0xa1 0x004
441#define MX27_PAD_NFCLE__ETMTRACEPKT0 0xa1 0x005
442#define MX27_PAD_NFCLE__GPIO6_1 0xa1 0x032
443#define MX27_PAD_NFWP_B__NFWP_B 0xa2 0x004
444#define MX27_PAD_NFWP_B__ETMTRACEPKT1 0xa2 0x005
445#define MX27_PAD_NFWP_B__GPIO6_2 0xa2 0x032
446#define MX27_PAD_NFCE_B__NFCE_B 0xa3 0x004
447#define MX27_PAD_NFCE_B__ETMTRACEPKT2 0xa3 0x005
448#define MX27_PAD_NFCE_B__GPIO6_3 0xa3 0x032
449#define MX27_PAD_NFALE__NFALE 0xa4 0x004
450#define MX27_PAD_NFALE__ETMPIPESTAT0 0xa4 0x005
451#define MX27_PAD_NFALE__GPIO6_4 0xa4 0x032
452#define MX27_PAD_NFRE_B__NFRE_B 0xa5 0x004
453#define MX27_PAD_NFRE_B__ETMPIPESTAT1 0xa5 0x005
454#define MX27_PAD_NFRE_B__GPIO6_5 0xa5 0x032
455#define MX27_PAD_NFWE_B__NFWE_B 0xa6 0x004
456#define MX27_PAD_NFWE_B__ETMPIPESTAT2 0xa6 0x005
457#define MX27_PAD_NFWE_B__GPIO6_6 0xa6 0x032
458#define MX27_PAD_PC_POE__PC_POE 0xa7 0x004
459#define MX27_PAD_PC_POE__ATA_BUFFER_EN 0xa7 0x005
460#define MX27_PAD_PC_POE__GPIO6_7 0xa7 0x032
461#define MX27_PAD_PC_RW_B__PC_RW_B 0xa8 0x004
462#define MX27_PAD_PC_RW_B__ATA_IORDY 0xa8 0x001
463#define MX27_PAD_PC_RW_B__GPIO6_8 0xa8 0x032
464#define MX27_PAD_IOIS16__IOIS16 0xa9 0x000
465#define MX27_PAD_IOIS16__ATA_INTRQ 0xa9 0x001
466#define MX27_PAD_IOIS16__GPIO6_9 0xa9 0x032
467#define MX27_PAD_PC_RST__PC_RST 0xaa 0x004
468#define MX27_PAD_PC_RST__ATA_RESET_B 0xaa 0x005
469#define MX27_PAD_PC_RST__GPIO6_10 0xaa 0x032
470#define MX27_PAD_PC_BVD2__PC_BVD2 0xab 0x000
471#define MX27_PAD_PC_BVD2__ATA_DMACK 0xab 0x005
472#define MX27_PAD_PC_BVD2__GPIO6_11 0xab 0x032
473#define MX27_PAD_PC_BVD1__PC_BVD1 0xac 0x000
474#define MX27_PAD_PC_BVD1__ATA_DMARQ 0xac 0x001
475#define MX27_PAD_PC_BVD1__GPIO6_12 0xac 0x032
476#define MX27_PAD_PC_VS2__PC_VS2 0xad 0x000
477#define MX27_PAD_PC_VS2__ATA_DA0 0xad 0x005
478#define MX27_PAD_PC_VS2__GPIO6_13 0xad 0x032
479#define MX27_PAD_PC_VS1__PC_VS1 0xae 0x000
480#define MX27_PAD_PC_VS1__ATA_DA1 0xae 0x005
481#define MX27_PAD_PC_VS1__GPIO6_14 0xae 0x032
482#define MX27_PAD_CLKO__CLKO 0xaf 0x004
483#define MX27_PAD_CLKO__GPIO6_15 0xaf 0x032
484#define MX27_PAD_PC_PWRON__PC_PWRON 0xb0 0x000
485#define MX27_PAD_PC_PWRON__ATA_DA2 0xb0 0x005
486#define MX27_PAD_PC_PWRON__GPIO6_16 0xb0 0x032
487#define MX27_PAD_PC_READY__PC_READY 0xb1 0x000
488#define MX27_PAD_PC_READY__ATA_CS0 0xb1 0x005
489#define MX27_PAD_PC_READY__GPIO6_17 0xb1 0x032
490#define MX27_PAD_PC_WAIT_B__PC_WAIT_B 0xb2 0x000
491#define MX27_PAD_PC_WAIT_B__ATA_CS1 0xb2 0x005
492#define MX27_PAD_PC_WAIT_B__GPIO6_18 0xb2 0x032
493#define MX27_PAD_PC_CD2_B__PC_CD2_B 0xb3 0x000
494#define MX27_PAD_PC_CD2_B__ATA_DIOW 0xb3 0x005
495#define MX27_PAD_PC_CD2_B__GPIO6_19 0xb3 0x032
496#define MX27_PAD_PC_CD1_B__PC_CD1_B 0xb4 0x000
497#define MX27_PAD_PC_CD1_B__ATA_DIOR 0xb4 0x005
498#define MX27_PAD_PC_CD1_B__GPIO6_20 0xb4 0x032
499#define MX27_PAD_CS4_B__CS4_B 0xb5 0x004
500#define MX27_PAD_CS4_B__ETMTRACESYNC 0xb5 0x005
501#define MX27_PAD_CS4_B__GPIO6_21 0xb5 0x032
502#define MX27_PAD_CS5_B__CS5_B 0xb6 0x004
503#define MX27_PAD_CS5_B__ETMTRACECLK 0xb6 0x005
504#define MX27_PAD_CS5_B__GPIO6_22 0xb6 0x032
505#define MX27_PAD_ATA_DATA15__ATA_DATA15 0xb7 0x004
506#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4 0xb7 0x005
507#define MX27_PAD_ATA_DATA15__FEC_TX_EN 0xb7 0x006
508#define MX27_PAD_ATA_DATA15__GPIO6_23 0xb7 0x032
509#define MX27_PAD_UNUSED15__UNUSED15 0xb8 0x004
510#define MX27_PAD_UNUSED15__GPIO6_24 0xb8 0x032
511#define MX27_PAD_UNUSED16__UNUSED16 0xb9 0x004
512#define MX27_PAD_UNUSED16__GPIO6_25 0xb9 0x032
513#define MX27_PAD_UNUSED17__UNUSED17 0xba 0x004
514#define MX27_PAD_UNUSED17__GPIO6_26 0xba 0x032
515#define MX27_PAD_UNUSED18__UNUSED18 0xbb 0x004
516#define MX27_PAD_UNUSED18__GPIO6_27 0xbb 0x032
517#define MX27_PAD_UNUSED19__UNUSED19 0xbc 0x004
518#define MX27_PAD_UNUSED19__GPIO6_28 0xbc 0x032
519#define MX27_PAD_UNUSED20__UNUSED20 0xbd 0x004
520#define MX27_PAD_UNUSED20__GPIO6_29 0xbd 0x032
521#define MX27_PAD_UNUSED21__UNUSED21 0xbe 0x004
522#define MX27_PAD_UNUSED21__GPIO6_30 0xbe 0x032
523#define MX27_PAD_UNUSED22__UNUSED22 0xbf 0x004
524#define MX27_PAD_UNUSED22__GPIO6_31 0xbf 0x032
525
526#endif /* __DTS_IMX27_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 826231eb4446..6279e0b4f768 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -10,6 +10,9 @@
10 */ 10 */
11 11
12#include "skeleton.dtsi" 12#include "skeleton.dtsi"
13#include "imx27-pinfunc.h"
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/gpio/gpio.h>
13 16
14/ { 17/ {
15 aliases { 18 aliases {
@@ -67,6 +70,26 @@
67 }; 70 };
68 }; 71 };
69 72
73 usbphy {
74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 usbphy0: usbphy@0 {
79 compatible = "usb-nop-xceiv";
80 reg = <0>;
81 clocks = <&clks 75>;
82 clock-names = "main_clk";
83 };
84
85 usbphy2: usbphy@2 {
86 compatible = "usb-nop-xceiv";
87 reg = <2>;
88 clocks = <&clks 75>;
89 clock-names = "main_clk";
90 };
91 };
92
70 soc { 93 soc {
71 #address-cells = <1>; 94 #address-cells = <1>;
72 #size-cells = <1>; 95 #size-cells = <1>;
@@ -204,6 +227,30 @@
204 status = "disabled"; 227 status = "disabled";
205 }; 228 };
206 229
230 ssi1: ssi@10010000 {
231 #sound-dai-cells = <0>;
232 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
233 reg = <0x10010000 0x1000>;
234 interrupts = <14>;
235 clocks = <&clks 26>;
236 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
237 dma-names = "rx0", "tx0", "rx1", "tx1";
238 fsl,fifo-depth = <8>;
239 status = "disabled";
240 };
241
242 ssi2: ssi@10011000 {
243 #sound-dai-cells = <0>;
244 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
245 reg = <0x10011000 0x1000>;
246 interrupts = <13>;
247 clocks = <&clks 25>;
248 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
249 dma-names = "rx0", "tx0", "rx1", "tx1";
250 fsl,fifo-depth = <8>;
251 status = "disabled";
252 };
253
207 i2c1: i2c@10012000 { 254 i2c1: i2c@10012000 {
208 #address-cells = <1>; 255 #address-cells = <1>;
209 #size-cells = <0>; 256 #size-cells = <0>;
@@ -236,64 +283,72 @@
236 status = "disabled"; 283 status = "disabled";
237 }; 284 };
238 285
239 gpio1: gpio@10015000 { 286 iomuxc: iomuxc@10015000 {
240 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 287 compatible = "fsl,imx27-iomuxc";
241 reg = <0x10015000 0x100>; 288 reg = <0x10015000 0x600>;
242 interrupts = <8>; 289 #address-cells = <1>;
243 gpio-controller; 290 #size-cells = <1>;
244 #gpio-cells = <2>; 291 ranges;
245 interrupt-controller; 292
246 #interrupt-cells = <2>; 293 gpio1: gpio@10015000 {
247 }; 294 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
248 295 reg = <0x10015000 0x100>;
249 gpio2: gpio@10015100 { 296 interrupts = <8>;
250 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 297 gpio-controller;
251 reg = <0x10015100 0x100>; 298 #gpio-cells = <2>;
252 interrupts = <8>; 299 interrupt-controller;
253 gpio-controller; 300 #interrupt-cells = <2>;
254 #gpio-cells = <2>; 301 };
255 interrupt-controller; 302
256 #interrupt-cells = <2>; 303 gpio2: gpio@10015100 {
257 }; 304 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
258 305 reg = <0x10015100 0x100>;
259 gpio3: gpio@10015200 { 306 interrupts = <8>;
260 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 307 gpio-controller;
261 reg = <0x10015200 0x100>; 308 #gpio-cells = <2>;
262 interrupts = <8>; 309 interrupt-controller;
263 gpio-controller; 310 #interrupt-cells = <2>;
264 #gpio-cells = <2>; 311 };
265 interrupt-controller; 312
266 #interrupt-cells = <2>; 313 gpio3: gpio@10015200 {
267 }; 314 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
268 315 reg = <0x10015200 0x100>;
269 gpio4: gpio@10015300 { 316 interrupts = <8>;
270 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 317 gpio-controller;
271 reg = <0x10015300 0x100>; 318 #gpio-cells = <2>;
272 interrupts = <8>; 319 interrupt-controller;
273 gpio-controller; 320 #interrupt-cells = <2>;
274 #gpio-cells = <2>; 321 };
275 interrupt-controller; 322
276 #interrupt-cells = <2>; 323 gpio4: gpio@10015300 {
277 }; 324 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
278 325 reg = <0x10015300 0x100>;
279 gpio5: gpio@10015400 { 326 interrupts = <8>;
280 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 327 gpio-controller;
281 reg = <0x10015400 0x100>; 328 #gpio-cells = <2>;
282 interrupts = <8>; 329 interrupt-controller;
283 gpio-controller; 330 #interrupt-cells = <2>;
284 #gpio-cells = <2>; 331 };
285 interrupt-controller; 332
286 #interrupt-cells = <2>; 333 gpio5: gpio@10015400 {
287 }; 334 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
288 335 reg = <0x10015400 0x100>;
289 gpio6: gpio@10015500 { 336 interrupts = <8>;
290 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 337 gpio-controller;
291 reg = <0x10015500 0x100>; 338 #gpio-cells = <2>;
292 interrupts = <8>; 339 interrupt-controller;
293 gpio-controller; 340 #interrupt-cells = <2>;
294 #gpio-cells = <2>; 341 };
295 interrupt-controller; 342
296 #interrupt-cells = <2>; 343 gpio6: gpio@10015500 {
344 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
345 reg = <0x10015500 0x100>;
346 interrupts = <8>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 };
297 }; 352 };
298 353
299 audmux: audmux@10016000 { 354 audmux: audmux@10016000 {
@@ -404,6 +459,42 @@
404 iram = <&iram>; 459 iram = <&iram>;
405 }; 460 };
406 461
462 usbotg: usb@10024000 {
463 compatible = "fsl,imx27-usb";
464 reg = <0x10024000 0x200>;
465 interrupts = <56>;
466 clocks = <&clks 15>;
467 fsl,usbmisc = <&usbmisc 0>;
468 fsl,usbphy = <&usbphy0>;
469 status = "disabled";
470 };
471
472 usbh1: usb@10024200 {
473 compatible = "fsl,imx27-usb";
474 reg = <0x10024200 0x200>;
475 interrupts = <54>;
476 clocks = <&clks 15>;
477 fsl,usbmisc = <&usbmisc 1>;
478 status = "disabled";
479 };
480
481 usbh2: usb@10024400 {
482 compatible = "fsl,imx27-usb";
483 reg = <0x10024400 0x200>;
484 interrupts = <55>;
485 clocks = <&clks 15>;
486 fsl,usbmisc = <&usbmisc 2>;
487 fsl,usbphy = <&usbphy2>;
488 status = "disabled";
489 };
490
491 usbmisc: usbmisc@10024600 {
492 #index-cells = <1>;
493 compatible = "fsl,imx27-usbmisc";
494 reg = <0x10024600 0x200>;
495 clocks = <&clks 62>;
496 };
497
407 sahara2: sahara@10025000 { 498 sahara2: sahara@10025000 {
408 compatible = "fsl,imx27-sahara"; 499 compatible = "fsl,imx27-sahara";
409 reg = <0x10025000 0x1000>; 500 reg = <0x10025000 0x1000>;
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index e2efd8d89c4f..221cac4fb2cd 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -48,6 +48,7 @@
48 MX28_PAD_LCD_D20__GPIO_1_20 48 MX28_PAD_LCD_D20__GPIO_1_20
49 MX28_PAD_LCD_D21__GPIO_1_21 49 MX28_PAD_LCD_D21__GPIO_1_21
50 MX28_PAD_LCD_D22__GPIO_1_22 50 MX28_PAD_LCD_D22__GPIO_1_22
51 MX28_PAD_GPMI_CE1N__GPIO_0_17
51 >; 52 >;
52 fsl,drive-strength = <MXS_DRIVE_4mA>; 53 fsl,drive-strength = <MXS_DRIVE_4mA>;
53 fsl,voltage = <MXS_VOLTAGE_HIGH>; 54 fsl,voltage = <MXS_VOLTAGE_HIGH>;
@@ -66,6 +67,16 @@
66 fsl,voltage = <MXS_VOLTAGE_HIGH>; 67 fsl,voltage = <MXS_VOLTAGE_HIGH>;
67 fsl,pull-up = <MXS_PULL_DISABLE>; 68 fsl,pull-up = <MXS_PULL_DISABLE>;
68 }; 69 };
70
71 usb0_otg_apf28dev: otg-apf28dev@0 {
72 reg = <0>;
73 fsl,pinmux-ids = <
74 MX28_PAD_LCD_D23__GPIO_1_23
75 >;
76 fsl,drive-strength = <MXS_DRIVE_4mA>;
77 fsl,voltage = <MXS_VOLTAGE_HIGH>;
78 fsl,pull-up = <MXS_PULL_DISABLE>;
79 };
69 }; 80 };
70 81
71 lcdif@80030000 { 82 lcdif@80030000 {
@@ -131,6 +142,8 @@
131 142
132 ahb@80080000 { 143 ahb@80080000 {
133 usb0: usb@80080000 { 144 usb0: usb@80080000 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&usb0_otg_apf28dev>;
134 vbus-supply = <&reg_usb0_vbus>; 147 vbus-supply = <&reg_usb0_vbus>;
135 status = "okay"; 148 status = "okay";
136 }; 149 };
@@ -150,13 +163,17 @@
150 163
151 regulators { 164 regulators {
152 compatible = "simple-bus"; 165 compatible = "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <0>;
153 168
154 reg_usb0_vbus: usb0_vbus { 169 reg_usb0_vbus: regulator@0 {
155 compatible = "regulator-fixed"; 170 compatible = "regulator-fixed";
171 reg = <0>;
156 regulator-name = "usb0_vbus"; 172 regulator-name = "usb0_vbus";
157 regulator-min-microvolt = <5000000>; 173 regulator-min-microvolt = <5000000>;
158 regulator-max-microvolt = <5000000>; 174 regulator-max-microvolt = <5000000>;
159 gpio = <&gpio1 23 1>; 175 gpio = <&gpio1 23 1>;
176 enable-active-high;
160 }; 177 };
161 }; 178 };
162 179
@@ -177,4 +194,14 @@
177 brightness-levels = <0 4 8 16 32 64 128 255>; 194 brightness-levels = <0 4 8 16 32 64 128 255>;
178 default-brightness-level = <6>; 195 default-brightness-level = <6>;
179 }; 196 };
197
198 gpio-keys {
199 compatible = "gpio-keys";
200
201 user-button {
202 label = "User button";
203 gpios = <&gpio0 17 0>;
204 linux,code = <0x100>;
205 };
206 };
180}; 207};
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index 6f254ca816cb..e1ce9179db63 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -193,9 +193,12 @@
193 193
194 regulators { 194 regulators {
195 compatible = "simple-bus"; 195 compatible = "simple-bus";
196 #address-cells = <1>;
197 #size-cells = <0>;
196 198
197 reg_3p3v: 3p3v { 199 reg_3p3v: regulator@0 {
198 compatible = "regulator-fixed"; 200 compatible = "regulator-fixed";
201 reg = <0>;
199 regulator-name = "3P3V"; 202 regulator-name = "3P3V";
200 regulator-min-microvolt = <3300000>; 203 regulator-min-microvolt = <3300000>;
201 regulator-max-microvolt = <3300000>; 204 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index cabb6171a19d..ae7c3390e65a 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -100,6 +100,8 @@
100 usb0: usb@80080000 { 100 usb0: usb@80080000 {
101 pinctrl-names = "default"; 101 pinctrl-names = "default";
102 pinctrl-0 = <&usb0_otg_cfa10036>; 102 pinctrl-0 = <&usb0_otg_cfa10036>;
103 dr_mode = "peripheral";
104 phy_type = "utmi";
103 status = "okay"; 105 status = "okay";
104 }; 106 };
105 }; 107 };
diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts
index f93e9a700e52..e5beaa58bb40 100644
--- a/arch/arm/boot/dts/imx28-cfa10037.dts
+++ b/arch/arm/boot/dts/imx28-cfa10037.dts
@@ -54,7 +54,7 @@
54 ahb@80080000 { 54 ahb@80080000 {
55 usb1: usb@80090000 { 55 usb1: usb@80090000 {
56 vbus-supply = <&reg_usb1_vbus>; 56 vbus-supply = <&reg_usb1_vbus>;
57 pinctrl-0 = <&usbphy1_pins_a>; 57 pinctrl-0 = <&usb1_pins_a>;
58 pinctrl-names = "default"; 58 pinctrl-names = "default";
59 status = "okay"; 59 status = "okay";
60 }; 60 };
@@ -72,9 +72,12 @@
72 72
73 regulators { 73 regulators {
74 compatible = "simple-bus"; 74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <0>;
75 77
76 reg_usb1_vbus: usb1_vbus { 78 reg_usb1_vbus: regulator@0 {
77 compatible = "regulator-fixed"; 79 compatible = "regulator-fixed";
80 reg = <0>;
78 pinctrl-names = "default"; 81 pinctrl-names = "default";
79 pinctrl-0 = <&usb_pins_cfa10037>; 82 pinctrl-0 = <&usb_pins_cfa10037>;
80 regulator-name = "usb1_vbus"; 83 regulator-name = "usb1_vbus";
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 7087b4bf6a8f..7d51459de5e8 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -229,15 +229,39 @@
229 i2c-parent = <&i2c1>; 229 i2c-parent = <&i2c1>;
230 230
231 i2c@0 { 231 i2c@0 {
232 #address-cells = <1>;
233 #size-cells = <0>;
232 reg = <0>; 234 reg = <0>;
235
236 adc0: nau7802@2a {
237 compatible = "nuvoton,nau7802";
238 reg = <0x2a>;
239 nuvoton,vldo = <3000>;
240 };
233 }; 241 };
234 242
235 i2c@1 { 243 i2c@1 {
244 #address-cells = <1>;
245 #size-cells = <0>;
236 reg = <1>; 246 reg = <1>;
247
248 adc1: nau7802@2a {
249 compatible = "nuvoton,nau7802";
250 reg = <0x2a>;
251 nuvoton,vldo = <3000>;
252 };
237 }; 253 };
238 254
239 i2c@2 { 255 i2c@2 {
256 #address-cells = <1>;
257 #size-cells = <0>;
240 reg = <2>; 258 reg = <2>;
259
260 adc2: nau7802@2a {
261 compatible = "nuvoton,nau7802";
262 reg = <0x2a>;
263 nuvoton,vldo = <3000>;
264 };
241 }; 265 };
242 266
243 i2c@3 { 267 i2c@3 {
@@ -274,7 +298,7 @@
274 ahb@80080000 { 298 ahb@80080000 {
275 usb1: usb@80090000 { 299 usb1: usb@80090000 {
276 vbus-supply = <&reg_usb1_vbus>; 300 vbus-supply = <&reg_usb1_vbus>;
277 pinctrl-0 = <&usbphy1_pins_a>; 301 pinctrl-0 = <&usb1_pins_a>;
278 pinctrl-names = "default"; 302 pinctrl-names = "default";
279 status = "okay"; 303 status = "okay";
280 }; 304 };
@@ -282,9 +306,12 @@
282 306
283 regulators { 307 regulators {
284 compatible = "simple-bus"; 308 compatible = "simple-bus";
309 #address-cells = <1>;
310 #size-cells = <0>;
285 311
286 reg_usb1_vbus: usb1_vbus { 312 reg_usb1_vbus: regulator@0 {
287 compatible = "regulator-fixed"; 313 compatible = "regulator-fixed";
314 reg = <0>;
288 pinctrl-names = "default"; 315 pinctrl-names = "default";
289 pinctrl-0 = <&usb_pins_cfa10049>; 316 pinctrl-0 = <&usb_pins_cfa10049>;
290 regulator-name = "usb1_vbus"; 317 regulator-name = "usb1_vbus";
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
index 3c1312885ae0..c4e00ce4b6da 100644
--- a/arch/arm/boot/dts/imx28-cfa10057.dts
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -134,7 +134,7 @@
134 ahb@80080000 { 134 ahb@80080000 {
135 usb1: usb@80090000 { 135 usb1: usb@80090000 {
136 vbus-supply = <&reg_usb1_vbus>; 136 vbus-supply = <&reg_usb1_vbus>;
137 pinctrl-0 = <&usbphy1_pins_a>; 137 pinctrl-0 = <&usb1_pins_a>;
138 pinctrl-names = "default"; 138 pinctrl-names = "default";
139 status = "okay"; 139 status = "okay";
140 }; 140 };
@@ -142,9 +142,12 @@
142 142
143 regulators { 143 regulators {
144 compatible = "simple-bus"; 144 compatible = "simple-bus";
145 #address-cells = <1>;
146 #size-cells = <0>;
145 147
146 reg_usb1_vbus: usb1_vbus { 148 reg_usb1_vbus: regulator@0 {
147 compatible = "regulator-fixed"; 149 compatible = "regulator-fixed";
150 reg = <0>;
148 pinctrl-names = "default"; 151 pinctrl-names = "default";
149 pinctrl-0 = <&usb_pins_cfa10057>; 152 pinctrl-0 = <&usb_pins_cfa10057>;
150 regulator-name = "usb1_vbus"; 153 regulator-name = "usb1_vbus";
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts
index 2469d34df0ae..7c9cc783f0d1 100644
--- a/arch/arm/boot/dts/imx28-cfa10058.dts
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -101,7 +101,7 @@
101 ahb@80080000 { 101 ahb@80080000 {
102 usb1: usb@80090000 { 102 usb1: usb@80090000 {
103 vbus-supply = <&reg_usb1_vbus>; 103 vbus-supply = <&reg_usb1_vbus>;
104 pinctrl-0 = <&usbphy1_pins_a>; 104 pinctrl-0 = <&usb1_pins_a>;
105 pinctrl-names = "default"; 105 pinctrl-names = "default";
106 status = "okay"; 106 status = "okay";
107 }; 107 };
@@ -109,11 +109,14 @@
109 109
110 regulators { 110 regulators {
111 compatible = "simple-bus"; 111 compatible = "simple-bus";
112 #address-cells = <1>;
113 #size-cells = <0>;
112 114
113 reg_usb1_vbus: usb1_vbus { 115 reg_usb1_vbus: regulator@0 {
114 pinctrl-names = "default"; 116 pinctrl-names = "default";
115 pinctrl-0 = <&usb_pins_cfa10058>; 117 pinctrl-0 = <&usb_pins_cfa10058>;
116 compatible = "regulator-fixed"; 118 compatible = "regulator-fixed";
119 reg = <0>;
117 regulator-name = "usb1_vbus"; 120 regulator-name = "usb1_vbus";
118 regulator-min-microvolt = <5000000>; 121 regulator-min-microvolt = <5000000>;
119 regulator-max-microvolt = <5000000>; 122 regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
new file mode 100644
index 000000000000..5f326c1c1850
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -0,0 +1,121 @@
1/*
2 * Copyright (C) 2013 Michael Heimpold <mhei@heimpold.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx28.dtsi"
14
15/ {
16 model = "I2SE Duckbill";
17 compatible = "i2se,duckbill", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 ssp0: ssp@80010000 {
26 compatible = "fsl,imx28-mmc";
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_8bit_pins_a
29 &mmc0_cd_cfg &mmc0_sck_cfg>;
30 bus-width = <8>;
31 vmmc-supply = <&reg_3p3v>;
32 status = "okay";
33 };
34
35 pinctrl@80018000 {
36 pinctrl-names = "default";
37 pinctrl-0 = <&hog_pins_a>;
38
39 hog_pins_a: hog@0 {
40 reg = <0>;
41 fsl,pinmux-ids = <
42 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */
43 >;
44 fsl,drive-strength = <MXS_DRIVE_4mA>;
45 fsl,voltage = <MXS_VOLTAGE_HIGH>;
46 fsl,pull-up = <MXS_PULL_DISABLE>;
47 };
48
49 led_pins_a: led_gpio@0 {
50 reg = <0>;
51 fsl,pinmux-ids = <
52 MX28_PAD_AUART1_RX__GPIO_3_4
53 MX28_PAD_AUART1_TX__GPIO_3_5
54 >;
55 fsl,drive-strength = <MXS_DRIVE_4mA>;
56 fsl,voltage = <MXS_VOLTAGE_HIGH>;
57 fsl,pull-up = <MXS_PULL_DISABLE>;
58 };
59 };
60 };
61
62 apbx@80040000 {
63 duart: serial@80074000 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&duart_pins_a>;
66 status = "okay";
67 };
68
69 usbphy0: usbphy@8007c000 {
70 status = "okay";
71 };
72 };
73 };
74
75 ahb@80080000 {
76 usb0: usb@80080000 {
77 status = "okay";
78 };
79
80 mac0: ethernet@800f0000 {
81 phy-mode = "rmii";
82 pinctrl-names = "default";
83 pinctrl-0 = <&mac0_pins_a>;
84 phy-supply = <&reg_3p3v>;
85 phy-reset-gpios = <&gpio4 13 0>;
86 phy-reset-duration = <100>;
87 status = "okay";
88 };
89 };
90
91 regulators {
92 compatible = "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <0>;
95
96 reg_3p3v: regulator@0 {
97 compatible = "regulator-fixed";
98 reg = <0>;
99 regulator-name = "3P3V";
100 regulator-min-microvolt = <3300000>;
101 regulator-max-microvolt = <3300000>;
102 regulator-always-on;
103 };
104 };
105
106 leds {
107 compatible = "gpio-leds";
108 pinctrl-names = "default";
109 pinctrl-0 = <&led_pins_a>;
110
111 status {
112 label = "duckbill:green:status";
113 gpios = <&gpio3 5 0>;
114 };
115
116 failure {
117 label = "duckbill:red:status";
118 gpios = <&gpio3 4 0>;
119 };
120 };
121};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
new file mode 100644
index 000000000000..7c1572c5a4fb
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
@@ -0,0 +1,71 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <eric@eukrea.com>
3 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/*
16 * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC
17 */
18
19/dts-v1/;
20#include "imx28-eukrea-mbmx28lc.dtsi"
21
22/ {
23 model = "Eukrea Electromatique MBMX283LC";
24 compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
25
26 memory {
27 reg = <0x40000000 0x04000000>;
28 };
29};
30
31&gpmi {
32 pinctrl-names = "default";
33 pinctrl-0 = <&gpmi_pins_a>;
34 status = "okay";
35};
36
37&i2c0 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&i2c0_pins_a>;
40 status = "okay";
41
42 pcf8563: rtc@51 {
43 compatible = "nxp,pcf8563";
44 reg = <0x51>;
45 };
46};
47
48
49&mac0 {
50 phy-mode = "rmii";
51 pinctrl-names = "default";
52 pinctrl-0 = <&mac0_pins_a>;
53 phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
54 status = "okay";
55};
56
57&pinctrl{
58 pinctrl-names = "default";
59 pinctrl-0 = <&hog_pins_cpuimx283>;
60
61 hog_pins_cpuimx283: hog-cpuimx283@0 {
62 reg = <0>;
63 fsl,pinmux-ids = <
64 MX28_PAD_ENET0_RX_CLK__GPIO_4_13
65 MX28_PAD_ENET0_TX_CLK__GPIO_4_5
66 >;
67 fsl,drive-strength = <MXS_DRIVE_4mA>;
68 fsl,voltage = <MXS_VOLTAGE_HIGH>;
69 fsl,pull-up = <MXS_PULL_ENABLE>;
70 };
71};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
new file mode 100644
index 000000000000..e773144e1e03
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
@@ -0,0 +1,50 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <eric@eukrea.com>
3 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/*
16 * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC
17 */
18
19#include "imx28-eukrea-mbmx283lc.dts"
20
21/ {
22 model = "Eukrea Electromatique MBMX287LC";
23 compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
24
25 memory {
26 reg = <0x40000000 0x08000000>;
27 };
28};
29
30&mac1 {
31 phy-mode = "rmii";
32 pinctrl-names = "default";
33 pinctrl-0 = <&mac1_pins_a>;
34 phy-reset-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
35 status = "okay";
36};
37
38&pinctrl {
39 pinctrl-names = "default";
40 pinctrl-0 = <&hog_pins_cpuimx283 &hog_pins_cpuimx287>;
41 hog_pins_cpuimx287: hog-cpuimx287@0 {
42 reg = <0>;
43 fsl,pinmux-ids = <
44 MX28_PAD_SPDIF__GPIO_3_27
45 >;
46 fsl,drive-strength = <MXS_DRIVE_4mA>;
47 fsl,voltage = <MXS_VOLTAGE_HIGH>;
48 fsl,pull-up = <MXS_PULL_ENABLE>;
49 };
50};
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
new file mode 100644
index 000000000000..927b391d2058
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
@@ -0,0 +1,326 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <eric@eukrea.com>
3 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/input/input.h>
16#include <dt-bindings/gpio/gpio.h>
17#include "imx28.dtsi"
18
19/ {
20 model = "Eukrea Electromatique MBMX28LC";
21 compatible = "eukrea,mbmx28lc", "fsl,imx28";
22
23 backlight {
24 compatible = "pwm-backlight";
25 pwms = <&pwm 4 1000000>;
26 brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>;
27 default-brightness-level = <10>;
28 };
29
30 button-sw3 {
31 compatible = "gpio-keys";
32 pinctrl-names = "default";
33 pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>;
34
35 sw3 {
36 label = "SW3";
37 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
38 linux,code = <BTN_MISC>;
39 gpio-key,wakeup;
40 };
41 };
42
43 button-sw4 {
44 compatible = "gpio-keys";
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>;
47
48 sw4 {
49 label = "SW4";
50 gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
51 linux,code = <BTN_MISC>;
52 gpio-key,wakeup;
53 };
54 };
55
56 led-d6 {
57 compatible = "gpio-leds";
58 pinctrl-names = "default";
59 pinctrl-0 = <&led_d6_pins_mbmx28lc>;
60
61 led1 {
62 label = "d6";
63 gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
67
68 led-d7 {
69 compatible = "gpio-leds";
70 pinctrl-names = "default";
71 pinctrl-0 = <&led_d7_pins_mbmx28lc>;
72
73 led1 {
74 label = "d7";
75 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
76 linux,default-trigger = "default-on";
77 };
78 };
79
80 regulators {
81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 reg_3p3v: regulator@0 {
86 compatible = "regulator-fixed";
87 regulator-name = "3P3V";
88 regulator-min-microvolt = <3300000>;
89 regulator-max-microvolt = <3300000>;
90 regulator-always-on;
91 };
92
93 reg_lcd_3v3: regulator@1 {
94 compatible = "regulator-fixed";
95 pinctrl-names = "default";
96 pinctrl-0 = <&reg_lcd_3v3_pins_mbmx28lc>;
97 regulator-name = "lcd-3v3";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
101 enable-active-high;
102 };
103
104 reg_usb0_vbus: regulator@2 {
105 compatible = "regulator-fixed";
106 pinctrl-names = "default";
107 pinctrl-0 = <&reg_usb0_vbus_pins_mbmx28lc>;
108 regulator-name = "usb0_vbus";
109 regulator-min-microvolt = <5000000>;
110 regulator-max-microvolt = <5000000>;
111 gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
112 enable-active-high;
113 };
114
115 reg_usb1_vbus: regulator@3 {
116 compatible = "regulator-fixed";
117 pinctrl-names = "default";
118 pinctrl-0 = <&reg_usb1_vbus_pins_mbmx28lc>;
119 regulator-name = "usb1_vbus";
120 regulator-min-microvolt = <5000000>;
121 regulator-max-microvolt = <5000000>;
122 gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
123 enable-active-high;
124 };
125 };
126
127 sound {
128 compatible = "fsl,imx28-mbmx28lc-sgtl5000",
129 "fsl,mxs-audio-sgtl5000";
130 model = "imx28-mbmx28lc-sgtl5000";
131 saif-controllers = <&saif0 &saif1>;
132 audio-codec = <&sgtl5000>;
133 };
134};
135
136&duart {
137 pinctrl-names = "default";
138 pinctrl-0 = <&duart_4pins_a>;
139 status = "okay";
140};
141
142&i2c0 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&i2c0_pins_a>;
145 status = "okay";
146
147 sgtl5000: codec@0a {
148 compatible = "fsl,sgtl5000";
149 reg = <0x0a>;
150 VDDA-supply = <&reg_3p3v>;
151 VDDIO-supply = <&reg_3p3v>;
152 clocks = <&saif0>;
153 };
154};
155
156&lcdif {
157 pinctrl-names = "default";
158 pinctrl-0 = <&lcdif_18bit_pins_a &lcdif_pins_mbmx28lc>;
159 lcd-supply = <&reg_lcd_3v3>;
160 display = <&display0>;
161 status = "okay";
162
163 display0: display0 {
164 model = "43WVF1G-0";
165 bits-per-pixel = <16>;
166 bus-width = <18>;
167
168 display-timings {
169 native-mode = <&timing0>;
170 timing0: timing0 {
171 clock-frequency = <9072000>;
172 hactive = <480>;
173 vactive = <272>;
174 hback-porch = <10>;
175 hfront-porch = <5>;
176 vback-porch = <8>;
177 vfront-porch = <8>;
178 hsync-len = <40>;
179 vsync-len = <10>;
180 hsync-active = <0>;
181 vsync-active = <0>;
182 de-active = <1>;
183 pixelclk-active = <1>;
184 };
185 };
186 };
187};
188
189&lradc {
190 fsl,lradc-touchscreen-wires = <4>;
191 status = "okay";
192};
193
194&pinctrl {
195 gpio_button_sw3_pins_mbmx28lc: gpio-button-sw3-mbmx28lc@0 {
196 reg = <0>;
197 fsl,pinmux-ids = <
198 MX28_PAD_LCD_D21__GPIO_1_21
199 >;
200 fsl,drive-strength = <MXS_DRIVE_4mA>;
201 fsl,voltage = <MXS_VOLTAGE_HIGH>;
202 fsl,pull-up = <MXS_PULL_DISABLE>;
203 };
204
205 gpio_button_sw4_pins_mbmx28lc: gpio-button-sw4-mbmx28lc@0 {
206 reg = <0>;
207 fsl,pinmux-ids = <
208 MX28_PAD_LCD_D20__GPIO_1_20
209 >;
210 fsl,drive-strength = <MXS_DRIVE_4mA>;
211 fsl,voltage = <MXS_VOLTAGE_HIGH>;
212 fsl,pull-up = <MXS_PULL_DISABLE>;
213 };
214
215 lcdif_pins_mbmx28lc: lcdif-mbmx28lc@0 {
216 reg = <0>;
217 fsl,pinmux-ids = <
218 MX28_PAD_LCD_VSYNC__LCD_VSYNC
219 MX28_PAD_LCD_HSYNC__LCD_HSYNC
220 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
221 MX28_PAD_LCD_ENABLE__LCD_ENABLE
222 >;
223 fsl,drive-strength = <MXS_DRIVE_4mA>;
224 fsl,voltage = <MXS_VOLTAGE_HIGH>;
225 fsl,pull-up = <MXS_PULL_DISABLE>;
226 };
227
228 led_d6_pins_mbmx28lc: led-d6-mbmx28lc@0 {
229 reg = <0>;
230 fsl,pinmux-ids = <
231 MX28_PAD_LCD_D23__GPIO_1_23
232 >;
233 fsl,drive-strength = <MXS_DRIVE_4mA>;
234 fsl,voltage = <MXS_VOLTAGE_HIGH>;
235 fsl,pull-up = <MXS_PULL_DISABLE>;
236 };
237
238 led_d7_pins_mbmx28lc: led-d7-mbmx28lc@0 {
239 reg = <0>;
240 fsl,pinmux-ids = <
241 MX28_PAD_LCD_D22__GPIO_1_22
242 >;
243 fsl,drive-strength = <MXS_DRIVE_4mA>;
244 fsl,voltage = <MXS_VOLTAGE_HIGH>;
245 fsl,pull-up = <MXS_PULL_DISABLE>;
246 };
247
248 reg_lcd_3v3_pins_mbmx28lc: lcd-3v3-mbmx28lc@0 {
249 reg = <0>;
250 fsl,pinmux-ids = <
251 MX28_PAD_LCD_RESET__GPIO_3_30
252 >;
253 fsl,drive-strength = <MXS_DRIVE_4mA>;
254 fsl,voltage = <MXS_VOLTAGE_HIGH>;
255 fsl,pull-up = <MXS_PULL_DISABLE>;
256 };
257
258 reg_usb0_vbus_pins_mbmx28lc: reg-usb0-vbus-mbmx28lc@0 {
259 reg = <0>;
260 fsl,pinmux-ids = <
261 MX28_PAD_LCD_D18__GPIO_1_18
262 >;
263 fsl,drive-strength = <MXS_DRIVE_4mA>;
264 fsl,voltage = <MXS_VOLTAGE_HIGH>;
265 fsl,pull-up = <MXS_PULL_DISABLE>;
266 };
267
268 reg_usb1_vbus_pins_mbmx28lc: reg-usb1-vbus-mbmx28lc@0 {
269 reg = <0>;
270 fsl,pinmux-ids = <
271 MX28_PAD_LCD_D19__GPIO_1_19
272 >;
273 fsl,drive-strength = <MXS_DRIVE_4mA>;
274 fsl,voltage = <MXS_VOLTAGE_HIGH>;
275 fsl,pull-up = <MXS_PULL_DISABLE>;
276 };
277};
278
279&pwm {
280 pinctrl-names = "default";
281 pinctrl-0 = <&pwm4_pins_a>;
282 status = "okay";
283};
284
285&saif0 {
286 pinctrl-names = "default";
287 pinctrl-0 = <&saif0_pins_a>;
288 status = "okay";
289};
290
291&saif1 {
292 pinctrl-names = "default";
293 pinctrl-0 = <&saif1_pins_a>;
294 fsl,saif-master = <&saif0>;
295 status = "okay";
296};
297
298&ssp0 {
299 compatible = "fsl,imx28-mmc";
300 pinctrl-names = "default";
301 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>;
302 bus-width = <4>;
303 cd-inverted;
304 status = "okay";
305};
306
307&usb0 {
308 disable-over-current;
309 vbus-supply = <&reg_usb0_vbus>;
310 status = "okay";
311 pinctrl-names = "default";
312 pinctrl-0 = <&usb0_id_pins_b>;
313};
314
315&usb1 {
316 vbus-supply = <&reg_usb1_vbus>;
317 status = "okay";
318};
319
320&usbphy0 {
321 status = "okay";
322};
323
324&usbphy1 {
325 status = "okay";
326};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 4267c2b05d60..e4cc44c98585 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -193,6 +193,7 @@
193 i2c0: i2c@80058000 { 193 i2c0: i2c@80058000 {
194 pinctrl-names = "default"; 194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c0_pins_a>; 195 pinctrl-0 = <&i2c0_pins_a>;
196 clock-frequency = <400000>;
196 status = "okay"; 197 status = "okay";
197 198
198 sgtl5000: codec@0a { 199 sgtl5000: codec@0a {
@@ -278,33 +279,39 @@
278 279
279 regulators { 280 regulators {
280 compatible = "simple-bus"; 281 compatible = "simple-bus";
282 #address-cells = <1>;
283 #size-cells = <0>;
281 284
282 reg_3p3v: 3p3v { 285 reg_3p3v: regulator@0 {
283 compatible = "regulator-fixed"; 286 compatible = "regulator-fixed";
287 reg = <0>;
284 regulator-name = "3P3V"; 288 regulator-name = "3P3V";
285 regulator-min-microvolt = <3300000>; 289 regulator-min-microvolt = <3300000>;
286 regulator-max-microvolt = <3300000>; 290 regulator-max-microvolt = <3300000>;
287 regulator-always-on; 291 regulator-always-on;
288 }; 292 };
289 293
290 reg_vddio_sd0: vddio-sd0 { 294 reg_vddio_sd0: regulator@1 {
291 compatible = "regulator-fixed"; 295 compatible = "regulator-fixed";
296 reg = <1>;
292 regulator-name = "vddio-sd0"; 297 regulator-name = "vddio-sd0";
293 regulator-min-microvolt = <3300000>; 298 regulator-min-microvolt = <3300000>;
294 regulator-max-microvolt = <3300000>; 299 regulator-max-microvolt = <3300000>;
295 gpio = <&gpio3 28 0>; 300 gpio = <&gpio3 28 0>;
296 }; 301 };
297 302
298 reg_fec_3v3: fec-3v3 { 303 reg_fec_3v3: regulator@2 {
299 compatible = "regulator-fixed"; 304 compatible = "regulator-fixed";
305 reg = <2>;
300 regulator-name = "fec-3v3"; 306 regulator-name = "fec-3v3";
301 regulator-min-microvolt = <3300000>; 307 regulator-min-microvolt = <3300000>;
302 regulator-max-microvolt = <3300000>; 308 regulator-max-microvolt = <3300000>;
303 gpio = <&gpio2 15 0>; 309 gpio = <&gpio2 15 0>;
304 }; 310 };
305 311
306 reg_usb0_vbus: usb0_vbus { 312 reg_usb0_vbus: regulator@3 {
307 compatible = "regulator-fixed"; 313 compatible = "regulator-fixed";
314 reg = <3>;
308 regulator-name = "usb0_vbus"; 315 regulator-name = "usb0_vbus";
309 regulator-min-microvolt = <5000000>; 316 regulator-min-microvolt = <5000000>;
310 regulator-max-microvolt = <5000000>; 317 regulator-max-microvolt = <5000000>;
@@ -312,8 +319,9 @@
312 enable-active-high; 319 enable-active-high;
313 }; 320 };
314 321
315 reg_usb1_vbus: usb1_vbus { 322 reg_usb1_vbus: regulator@4 {
316 compatible = "regulator-fixed"; 323 compatible = "regulator-fixed";
324 reg = <4>;
317 regulator-name = "usb1_vbus"; 325 regulator-name = "usb1_vbus";
318 regulator-min-microvolt = <5000000>; 326 regulator-min-microvolt = <5000000>;
319 regulator-max-microvolt = <5000000>; 327 regulator-max-microvolt = <5000000>;
@@ -321,8 +329,9 @@
321 enable-active-high; 329 enable-active-high;
322 }; 330 };
323 331
324 reg_lcd_3v3: lcd-3v3 { 332 reg_lcd_3v3: regulator@5 {
325 compatible = "regulator-fixed"; 333 compatible = "regulator-fixed";
334 reg = <5>;
326 regulator-name = "lcd-3v3"; 335 regulator-name = "lcd-3v3";
327 regulator-min-microvolt = <3300000>; 336 regulator-min-microvolt = <3300000>;
328 regulator-max-microvolt = <3300000>; 337 regulator-max-microvolt = <3300000>;
@@ -330,8 +339,9 @@
330 enable-active-high; 339 enable-active-high;
331 }; 340 };
332 341
333 reg_can_3v3: can-3v3 { 342 reg_can_3v3: regulator@6 {
334 compatible = "regulator-fixed"; 343 compatible = "regulator-fixed";
344 reg = <6>;
335 regulator-name = "can-3v3"; 345 regulator-name = "can-3v3";
336 regulator-min-microvolt = <3300000>; 346 regulator-min-microvolt = <3300000>;
337 regulator-max-microvolt = <3300000>; 347 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index d3958da60bd7..9348ce59dda4 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -116,7 +116,6 @@
116 pinctrl-0 = <&lcdif_24bit_pins_a 116 pinctrl-0 = <&lcdif_24bit_pins_a
117 &lcdif_pins_m28>; 117 &lcdif_pins_m28>;
118 display = <&display>; 118 display = <&display>;
119 reset-active-high;
120 status = "okay"; 119 status = "okay";
121 120
122 display: display0 { 121 display: display0 {
@@ -180,7 +179,7 @@
180 usb1: usb@80090000 { 179 usb1: usb@80090000 {
181 vbus-supply = <&reg_usb1_vbus>; 180 vbus-supply = <&reg_usb1_vbus>;
182 pinctrl-names = "default"; 181 pinctrl-names = "default";
183 pinctrl-0 = <&usbphy1_pins_a>; 182 pinctrl-0 = <&usb1_pins_a>;
184 disable-over-current; 183 disable-over-current;
185 status = "okay"; 184 status = "okay";
186 }; 185 };
@@ -229,33 +228,39 @@
229 228
230 regulators { 229 regulators {
231 compatible = "simple-bus"; 230 compatible = "simple-bus";
231 #address-cells = <1>;
232 #size-cells = <0>;
232 233
233 reg_3p3v: 3p3v { 234 reg_3p3v: regulator@0 {
234 compatible = "regulator-fixed"; 235 compatible = "regulator-fixed";
236 reg = <0>;
235 regulator-name = "3P3V"; 237 regulator-name = "3P3V";
236 regulator-min-microvolt = <3300000>; 238 regulator-min-microvolt = <3300000>;
237 regulator-max-microvolt = <3300000>; 239 regulator-max-microvolt = <3300000>;
238 regulator-always-on; 240 regulator-always-on;
239 }; 241 };
240 242
241 reg_vddio_sd0: vddio-sd0 { 243 reg_vddio_sd0: regulator@1 {
242 compatible = "regulator-fixed"; 244 compatible = "regulator-fixed";
245 reg = <1>;
243 regulator-name = "vddio-sd0"; 246 regulator-name = "vddio-sd0";
244 regulator-min-microvolt = <3300000>; 247 regulator-min-microvolt = <3300000>;
245 regulator-max-microvolt = <3300000>; 248 regulator-max-microvolt = <3300000>;
246 gpio = <&gpio3 29 0>; 249 gpio = <&gpio3 29 0>;
247 }; 250 };
248 251
249 reg_vddio_sd1: vddio-sd1 { 252 reg_vddio_sd1: regulator@2 {
250 compatible = "regulator-fixed"; 253 compatible = "regulator-fixed";
254 reg = <2>;
251 regulator-name = "vddio-sd1"; 255 regulator-name = "vddio-sd1";
252 regulator-min-microvolt = <3300000>; 256 regulator-min-microvolt = <3300000>;
253 regulator-max-microvolt = <3300000>; 257 regulator-max-microvolt = <3300000>;
254 gpio = <&gpio2 19 0>; 258 gpio = <&gpio2 19 0>;
255 }; 259 };
256 260
257 reg_usb1_vbus: usb1_vbus { 261 reg_usb1_vbus: regulator@3 {
258 compatible = "regulator-fixed"; 262 compatible = "regulator-fixed";
263 reg = <3>;
259 regulator-name = "usb1_vbus"; 264 regulator-name = "usb1_vbus";
260 regulator-min-microvolt = <5000000>; 265 regulator-min-microvolt = <5000000>;
261 regulator-max-microvolt = <5000000>; 266 regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 8e2477fbe1d7..f0ad7b9b9d9a 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -194,7 +194,7 @@
194 }; 194 };
195 195
196 rtc: rtc@68 { 196 rtc: rtc@68 {
197 compatible = "stm,mt41t62"; 197 compatible = "stm,m41t62";
198 reg = <0x68>; 198 reg = <0x68>;
199 }; 199 };
200 }; 200 };
@@ -248,14 +248,14 @@
248 usb0: usb@80080000 { 248 usb0: usb@80080000 {
249 vbus-supply = <&reg_usb0_vbus>; 249 vbus-supply = <&reg_usb0_vbus>;
250 pinctrl-names = "default"; 250 pinctrl-names = "default";
251 pinctrl-0 = <&usbphy0_pins_a>; 251 pinctrl-0 = <&usb0_pins_a>;
252 status = "okay"; 252 status = "okay";
253 }; 253 };
254 254
255 usb1: usb@80090000 { 255 usb1: usb@80090000 {
256 vbus-supply = <&reg_usb1_vbus>; 256 vbus-supply = <&reg_usb1_vbus>;
257 pinctrl-names = "default"; 257 pinctrl-names = "default";
258 pinctrl-0 = <&usbphy1_pins_a>; 258 pinctrl-0 = <&usb1_pins_a>;
259 status = "okay"; 259 status = "okay";
260 }; 260 };
261 261
@@ -285,33 +285,39 @@
285 285
286 regulators { 286 regulators {
287 compatible = "simple-bus"; 287 compatible = "simple-bus";
288 #address-cells = <1>;
289 #size-cells = <0>;
288 290
289 reg_3p3v: 3p3v { 291 reg_3p3v: regulator@0 {
290 compatible = "regulator-fixed"; 292 compatible = "regulator-fixed";
293 reg = <0>;
291 regulator-name = "3P3V"; 294 regulator-name = "3P3V";
292 regulator-min-microvolt = <3300000>; 295 regulator-min-microvolt = <3300000>;
293 regulator-max-microvolt = <3300000>; 296 regulator-max-microvolt = <3300000>;
294 regulator-always-on; 297 regulator-always-on;
295 }; 298 };
296 299
297 reg_vddio_sd0: vddio-sd0 { 300 reg_vddio_sd0: regulator@1 {
298 compatible = "regulator-fixed"; 301 compatible = "regulator-fixed";
302 reg = <1>;
299 regulator-name = "vddio-sd0"; 303 regulator-name = "vddio-sd0";
300 regulator-min-microvolt = <3300000>; 304 regulator-min-microvolt = <3300000>;
301 regulator-max-microvolt = <3300000>; 305 regulator-max-microvolt = <3300000>;
302 gpio = <&gpio3 28 0>; 306 gpio = <&gpio3 28 0>;
303 }; 307 };
304 308
305 reg_usb0_vbus: usb0_vbus { 309 reg_usb0_vbus: regulator@2 {
306 compatible = "regulator-fixed"; 310 compatible = "regulator-fixed";
311 reg = <2>;
307 regulator-name = "usb0_vbus"; 312 regulator-name = "usb0_vbus";
308 regulator-min-microvolt = <5000000>; 313 regulator-min-microvolt = <5000000>;
309 regulator-max-microvolt = <5000000>; 314 regulator-max-microvolt = <5000000>;
310 gpio = <&gpio3 12 0>; 315 gpio = <&gpio3 12 0>;
311 }; 316 };
312 317
313 reg_usb1_vbus: usb1_vbus { 318 reg_usb1_vbus: regulator@3 {
314 compatible = "regulator-fixed"; 319 compatible = "regulator-fixed";
320 reg = <3>;
315 regulator-name = "usb1_vbus"; 321 regulator-name = "usb1_vbus";
316 regulator-min-microvolt = <5000000>; 322 regulator-min-microvolt = <5000000>;
317 regulator-max-microvolt = <5000000>; 323 regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 4870f07bf56a..0ce3cb8e7914 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -106,7 +106,7 @@
106 usb0: usb@80080000 { 106 usb0: usb@80080000 {
107 vbus-supply = <&reg_usb0_vbus>; 107 vbus-supply = <&reg_usb0_vbus>;
108 pinctrl-names = "default"; 108 pinctrl-names = "default";
109 pinctrl-0 = <&usbphy0_pins_b>; 109 pinctrl-0 = <&usb0_pins_b>;
110 status = "okay"; 110 status = "okay";
111 }; 111 };
112 112
@@ -127,9 +127,12 @@
127 127
128 regulators { 128 regulators {
129 compatible = "simple-bus"; 129 compatible = "simple-bus";
130 #address-cells = <1>;
131 #size-cells = <0>;
130 132
131 reg_usb0_vbus: usb0_vbus { 133 reg_usb0_vbus: regulator@0 {
132 compatible = "regulator-fixed"; 134 compatible = "regulator-fixed";
135 reg = <0>;
133 regulator-name = "usb0_vbus"; 136 regulator-name = "usb0_vbus";
134 regulator-min-microvolt = <5000000>; 137 regulator-min-microvolt = <5000000>;
135 regulator-max-microvolt = <5000000>; 138 regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index be5a0550d58c..e14bd86f3e99 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -43,9 +43,12 @@
43 43
44 regulators { 44 regulators {
45 compatible = "simple-bus"; 45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <0>;
46 48
47 reg_usb0_vbus: usb0_vbus { 49 reg_usb0_vbus: regulator@0 {
48 compatible = "regulator-fixed"; 50 compatible = "regulator-fixed";
51 reg = <0>;
49 regulator-name = "usb0_vbus"; 52 regulator-name = "usb0_vbus";
50 regulator-min-microvolt = <5000000>; 53 regulator-min-microvolt = <5000000>;
51 regulator-max-microvolt = <5000000>; 54 regulator-max-microvolt = <5000000>;
@@ -53,8 +56,9 @@
53 enable-active-high; 56 enable-active-high;
54 }; 57 };
55 58
56 reg_usb1_vbus: usb1_vbus { 59 reg_usb1_vbus: regulator@1 {
57 compatible = "regulator-fixed"; 60 compatible = "regulator-fixed";
61 reg = <1>;
58 regulator-name = "usb1_vbus"; 62 regulator-name = "usb1_vbus";
59 regulator-min-microvolt = <5000000>; 63 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>; 64 regulator-max-microvolt = <5000000>;
@@ -62,35 +66,38 @@
62 enable-active-high; 66 enable-active-high;
63 }; 67 };
64 68
65 reg_2p5v: 2p5v { 69 reg_2p5v: regulator@2 {
66 compatible = "regulator-fixed"; 70 compatible = "regulator-fixed";
71 reg = <2>;
67 regulator-name = "2P5V"; 72 regulator-name = "2P5V";
68 regulator-min-microvolt = <2500000>; 73 regulator-min-microvolt = <2500000>;
69 regulator-max-microvolt = <2500000>; 74 regulator-max-microvolt = <2500000>;
70 regulator-always-on; 75 regulator-always-on;
71 }; 76 };
72 77
73 reg_3p3v: 3p3v { 78 reg_3p3v: regulator@3 {
74 compatible = "regulator-fixed"; 79 compatible = "regulator-fixed";
80 reg = <3>;
75 regulator-name = "3P3V"; 81 regulator-name = "3P3V";
76 regulator-min-microvolt = <3300000>; 82 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>;
78 regulator-always-on; 84 regulator-always-on;
79 }; 85 };
80 86
81 reg_can_xcvr: can-xcvr { 87 reg_can_xcvr: regulator@4 {
82 compatible = "regulator-fixed"; 88 compatible = "regulator-fixed";
89 reg = <4>;
83 regulator-name = "CAN XCVR"; 90 regulator-name = "CAN XCVR";
84 regulator-min-microvolt = <3300000>; 91 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>; 92 regulator-max-microvolt = <3300000>;
86 gpio = <&gpio1 0 0>; 93 gpio = <&gpio1 0 0>;
87 enable-active-low;
88 pinctrl-names = "default"; 94 pinctrl-names = "default";
89 pinctrl-0 = <&tx28_flexcan_xcvr_pins>; 95 pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
90 }; 96 };
91 97
92 reg_lcd: lcd-power { 98 reg_lcd: regulator@5 {
93 compatible = "regulator-fixed"; 99 compatible = "regulator-fixed";
100 reg = <5>;
94 regulator-name = "LCD POWER"; 101 regulator-name = "LCD POWER";
95 regulator-min-microvolt = <3300000>; 102 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>;
@@ -98,8 +105,9 @@
98 enable-active-high; 105 enable-active-high;
99 }; 106 };
100 107
101 reg_lcd_reset: lcd-reset { 108 reg_lcd_reset: regulator@6 {
102 compatible = "regulator-fixed"; 109 compatible = "regulator-fixed";
110 reg = <6>;
103 regulator-name = "LCD RESET"; 111 regulator-name = "LCD RESET";
104 regulator-min-microvolt = <3300000>; 112 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <3300000>; 113 regulator-max-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index f8e9b20f6982..90a579532b8b 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,6 +32,8 @@
32 serial4 = &auart4; 32 serial4 = &auart4;
33 spi0 = &ssp1; 33 spi0 = &ssp1;
34 spi1 = &ssp2; 34 spi1 = &ssp2;
35 usbphy0 = &usbphy0;
36 usbphy1 = &usbphy1;
35 }; 37 };
36 38
37 cpus { 39 cpus {
@@ -343,6 +345,19 @@
343 fsl,pull-up = <MXS_PULL_DISABLE>; 345 fsl,pull-up = <MXS_PULL_DISABLE>;
344 }; 346 };
345 347
348 auart2_pins_a: auart2-pins@0 {
349 reg = <0>;
350 fsl,pinmux-ids = <
351 MX28_PAD_AUART2_RX__AUART2_RX
352 MX28_PAD_AUART2_TX__AUART2_TX
353 MX28_PAD_AUART2_CTS__AUART2_CTS
354 MX28_PAD_AUART2_RTS__AUART2_RTS
355 >;
356 fsl,drive-strength = <MXS_DRIVE_4mA>;
357 fsl,voltage = <MXS_VOLTAGE_HIGH>;
358 fsl,pull-up = <MXS_PULL_DISABLE>;
359 };
360
346 auart3_pins_a: auart3@0 { 361 auart3_pins_a: auart3@0 {
347 reg = <0>; 362 reg = <0>;
348 fsl,pinmux-ids = < 363 fsl,pinmux-ids = <
@@ -655,6 +670,33 @@
655 fsl,pull-up = <MXS_PULL_DISABLE>; 670 fsl,pull-up = <MXS_PULL_DISABLE>;
656 }; 671 };
657 672
673 lcdif_18bit_pins_a: lcdif-18bit@0 {
674 reg = <0>;
675 fsl,pinmux-ids = <
676 MX28_PAD_LCD_D00__LCD_D0
677 MX28_PAD_LCD_D01__LCD_D1
678 MX28_PAD_LCD_D02__LCD_D2
679 MX28_PAD_LCD_D03__LCD_D3
680 MX28_PAD_LCD_D04__LCD_D4
681 MX28_PAD_LCD_D05__LCD_D5
682 MX28_PAD_LCD_D06__LCD_D6
683 MX28_PAD_LCD_D07__LCD_D7
684 MX28_PAD_LCD_D08__LCD_D8
685 MX28_PAD_LCD_D09__LCD_D9
686 MX28_PAD_LCD_D10__LCD_D10
687 MX28_PAD_LCD_D11__LCD_D11
688 MX28_PAD_LCD_D12__LCD_D12
689 MX28_PAD_LCD_D13__LCD_D13
690 MX28_PAD_LCD_D14__LCD_D14
691 MX28_PAD_LCD_D15__LCD_D15
692 MX28_PAD_LCD_D16__LCD_D16
693 MX28_PAD_LCD_D17__LCD_D17
694 >;
695 fsl,drive-strength = <MXS_DRIVE_4mA>;
696 fsl,voltage = <MXS_VOLTAGE_HIGH>;
697 fsl,pull-up = <MXS_PULL_DISABLE>;
698 };
699
658 lcdif_16bit_pins_a: lcdif-16bit@0 { 700 lcdif_16bit_pins_a: lcdif-16bit@0 {
659 reg = <0>; 701 reg = <0>;
660 fsl,pinmux-ids = < 702 fsl,pinmux-ids = <
@@ -743,7 +785,7 @@
743 fsl,pull-up = <MXS_PULL_DISABLE>; 785 fsl,pull-up = <MXS_PULL_DISABLE>;
744 }; 786 };
745 787
746 usbphy0_pins_a: usbphy0@0 { 788 usb0_pins_a: usb0@0 {
747 reg = <0>; 789 reg = <0>;
748 fsl,pinmux-ids = < 790 fsl,pinmux-ids = <
749 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 791 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
@@ -753,7 +795,7 @@
753 fsl,pull-up = <MXS_PULL_DISABLE>; 795 fsl,pull-up = <MXS_PULL_DISABLE>;
754 }; 796 };
755 797
756 usbphy0_pins_b: usbphy0@1 { 798 usb0_pins_b: usb0@1 {
757 reg = <1>; 799 reg = <1>;
758 fsl,pinmux-ids = < 800 fsl,pinmux-ids = <
759 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 801 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
@@ -763,7 +805,7 @@
763 fsl,pull-up = <MXS_PULL_DISABLE>; 805 fsl,pull-up = <MXS_PULL_DISABLE>;
764 }; 806 };
765 807
766 usbphy1_pins_a: usbphy1@0 { 808 usb1_pins_a: usb1@0 {
767 reg = <0>; 809 reg = <0>;
768 fsl,pinmux-ids = < 810 fsl,pinmux-ids = <
769 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 811 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
@@ -782,6 +824,17 @@
782 fsl,voltage = <MXS_VOLTAGE_HIGH>; 824 fsl,voltage = <MXS_VOLTAGE_HIGH>;
783 fsl,pull-up = <MXS_PULL_ENABLE>; 825 fsl,pull-up = <MXS_PULL_ENABLE>;
784 }; 826 };
827
828 usb0_id_pins_b: usb0id1@0 {
829 reg = <0>;
830 fsl,pinmux-ids = <
831 MX28_PAD_PWM2__USB0_ID
832 >;
833 fsl,drive-strength = <MXS_DRIVE_12mA>;
834 fsl,voltage = <MXS_VOLTAGE_HIGH>;
835 fsl,pull-up = <MXS_PULL_ENABLE>;
836 };
837
785 }; 838 };
786 839
787 digctl: digctl@8001c000 { 840 digctl: digctl@8001c000 {
@@ -946,6 +999,7 @@
946 20 21 22 23 24 25>; 999 20 21 22 23 24 25>;
947 status = "disabled"; 1000 status = "disabled";
948 clocks = <&clks 41>; 1001 clocks = <&clks 41>;
1002 #io-channel-cells = <1>;
949 }; 1003 };
950 1004
951 spdif: spdif@80054000 { 1005 spdif: spdif@80054000 {
@@ -1130,4 +1184,9 @@
1130 status = "disabled"; 1184 status = "disabled";
1131 }; 1185 };
1132 }; 1186 };
1187
1188 iio_hwmon {
1189 compatible = "iio-hwmon";
1190 io-channels = <&lradc 8>;
1191 };
1133}; 1192};
diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
new file mode 100644
index 000000000000..906ae937b013
--- /dev/null
+++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
@@ -0,0 +1,81 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "imx35.dtsi"
15
16/ {
17 model = "Eukrea CPUIMX35";
18 compatible = "eukrea,cpuimx35", "fsl,imx35";
19
20 memory {
21 reg = <0x80000000 0x8000000>; /* 128M */
22 };
23};
24
25&fec {
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_fec>;
28 status = "okay";
29};
30
31&i2c1 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_i2c1>;
34 status = "okay";
35
36 pcf8563@51 {
37 compatible = "nxp,pcf8563";
38 reg = <0x51>;
39 };
40};
41
42&iomuxc {
43 imx35-eukrea {
44 pinctrl_fec: fecgrp {
45 fsl,pins = <
46 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
47 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000
48 MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
49 MX35_PAD_FEC_COL__FEC_COL 0x80000000
50 MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000
51 MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000
52 MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
53 MX35_PAD_FEC_MDC__FEC_MDC 0x80000000
54 MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000
55 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000
56 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000
57 MX35_PAD_FEC_CRS__FEC_CRS 0x80000000
58 MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000
59 MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000
60 MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000
61 MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000
62 MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000
63 MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000
64 >;
65 };
66
67 pinctrl_i2c1: i2c1grp {
68 fsl,pins = <
69 MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000
70 MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000
71 >;
72 };
73 };
74};
75
76&nfc {
77 nand-bus-width = <8>;
78 nand-ecc-mode = "hw";
79 nand-on-flash-bbt;
80 status = "okay";
81};
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
new file mode 100644
index 000000000000..1bdec21f4533
--- /dev/null
+++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -0,0 +1,143 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include "imx35-eukrea-cpuimx35.dtsi"
19
20/ {
21 model = "Eukrea CPUIMX35";
22 compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35";
23
24 gpio_keys {
25 compatible = "gpio-keys";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_bp1>;
28
29 bp1 {
30 label = "BP1";
31 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
32 linux,code = <BTN_MISC>;
33 gpio-key,wakeup;
34 linux,input-type = <1>;
35 };
36 };
37
38 leds {
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_led1>;
42
43 led1 {
44 label = "led1";
45 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
46 linux,default-trigger = "heartbeat";
47 };
48 };
49};
50
51&audmux {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_audmux>;
54 status = "okay";
55};
56
57&esdhc1 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_esdhc1>;
60 cd-gpios = <&gpio3 24>;
61 status = "okay";
62};
63
64&i2c1 {
65 tlv320aic23: codec@1a {
66 compatible = "ti,tlv320aic23";
67 reg = <0x1a>;
68 };
69};
70
71&iomuxc {
72 imx35-eukrea {
73 pinctrl_audmux: audmuxgrp {
74 fsl,pins = <
75 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000
76 MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000
77 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000
78 MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000
79 >;
80 };
81
82 pinctrl_bp1: bp1grp {
83 fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>;
84 };
85
86 pinctrl_esdhc1: esdhc1grp {
87 fsl,pins = <
88 MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
89 MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
90 MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
91 MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
92 MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
93 MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
94 MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */
95 >;
96 };
97
98 pinctrl_led1: led1grp {
99 fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>;
100 };
101
102 pinctrl_reg_lcd_3v3: reg-lcd-3v3 {
103 fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>;
104 };
105
106 pinctrl_uart1: uart1grp {
107 fsl,pins = <
108 MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
109 MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
110 MX35_PAD_CTS1__UART1_CTS 0x1c5
111 MX35_PAD_RTS1__UART1_RTS 0x1c5
112 >;
113 };
114
115 pinctrl_uart2: uart2grp {
116 fsl,pins = <
117 MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5
118 MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5
119 MX35_PAD_RTS2__UART2_RTS 0x1c5
120 MX35_PAD_CTS2__UART2_CTS 0x1c5
121 >;
122 };
123 };
124};
125
126&ssi1 {
127 fsl,mode = "i2s-slave";
128 status = "okay";
129};
130
131&uart1 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_uart1>;
134 fsl,uart-has-rtscts;
135 status = "okay";
136};
137
138&uart2 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_uart2>;
141 fsl,uart-has-rtscts;
142 status = "okay";
143};
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
new file mode 100644
index 000000000000..88b218f8f810
--- /dev/null
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -0,0 +1,359 @@
1/*
2 * Copyright 2012 Steffen Trumtrar, Pengutronix
3 *
4 * based on imx27.dtsi
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation.
9 */
10
11#include "skeleton.dtsi"
12#include "imx35-pinfunc.h"
13
14/ {
15 aliases {
16 gpio0 = &gpio1;
17 gpio1 = &gpio2;
18 gpio2 = &gpio3;
19 serial0 = &uart1;
20 serial1 = &uart2;
21 serial2 = &uart3;
22 spi0 = &spi1;
23 spi1 = &spi2;
24 };
25
26 cpus {
27 #address-cells = <0>;
28 #size-cells = <0>;
29
30 cpu {
31 compatible = "arm,arm1136";
32 device_type = "cpu";
33 };
34 };
35
36 avic: avic-interrupt-controller@68000000 {
37 compatible = "fsl,imx35-avic", "fsl,avic";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 reg = <0x68000000 0x10000000>;
41 };
42
43 soc {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "simple-bus";
47 interrupt-parent = <&avic>;
48 ranges;
49
50 L2: l2-cache@30000000 {
51 compatible = "arm,l210-cache";
52 reg = <0x30000000 0x1000>;
53 cache-unified;
54 cache-level = <2>;
55 };
56
57 aips1: aips@43f00000 {
58 compatible = "fsl,aips", "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x43f00000 0x100000>;
62 ranges;
63
64 i2c1: i2c@43f80000 {
65 #address-cells = <1>;
66 #size-cells = <0>;
67 compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
68 reg = <0x43f80000 0x4000>;
69 clocks = <&clks 51>;
70 clock-names = "ipg_per";
71 interrupts = <10>;
72 status = "disabled";
73 };
74
75 i2c3: i2c@43f84000 {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
79 reg = <0x43f84000 0x4000>;
80 clocks = <&clks 53>;
81 clock-names = "ipg_per";
82 interrupts = <3>;
83 status = "disabled";
84 };
85
86 uart1: serial@43f90000 {
87 compatible = "fsl,imx35-uart", "fsl,imx21-uart";
88 reg = <0x43f90000 0x4000>;
89 clocks = <&clks 9>, <&clks 70>;
90 clock-names = "ipg", "per";
91 interrupts = <45>;
92 status = "disabled";
93 };
94
95 uart2: serial@43f94000 {
96 compatible = "fsl,imx35-uart", "fsl,imx21-uart";
97 reg = <0x43f94000 0x4000>;
98 clocks = <&clks 9>, <&clks 71>;
99 clock-names = "ipg", "per";
100 interrupts = <32>;
101 status = "disabled";
102 };
103
104 i2c2: i2c@43f98000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 compatible = "fsl,imx35-i2c", "fsl,imx1-i2c";
108 reg = <0x43f98000 0x4000>;
109 clocks = <&clks 52>;
110 clock-names = "ipg_per";
111 interrupts = <4>;
112 status = "disabled";
113 };
114
115 ssi1: ssi@43fa0000 {
116 compatible = "fsl,imx35-ssi", "fsl,imx21-ssi";
117 reg = <0x43fa0000 0x4000>;
118 interrupts = <11>;
119 clocks = <&clks 68>;
120 dmas = <&sdma 28 0 0>,
121 <&sdma 29 0 0>;
122 dma-names = "rx", "tx";
123 fsl,fifo-depth = <15>;
124 status = "disabled";
125 };
126
127 spi1: cspi@43fa4000 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 compatible = "fsl,imx35-cspi";
131 reg = <0x43fa4000 0x4000>;
132 clocks = <&clks 35 &clks 35>;
133 clock-names = "ipg", "per";
134 interrupts = <14>;
135 status = "disabled";
136 };
137
138 iomuxc: iomuxc@43fac000 {
139 compatible = "fsl,imx35-iomuxc";
140 reg = <0x43fac000 0x4000>;
141 };
142 };
143
144 spba: spba-bus@50000000 {
145 compatible = "fsl,spba-bus", "simple-bus";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 reg = <0x50000000 0x100000>;
149 ranges;
150
151 uart3: serial@5000c000 {
152 compatible = "fsl,imx35-uart", "fsl,imx21-uart";
153 reg = <0x5000c000 0x4000>;
154 clocks = <&clks 9>, <&clks 72>;
155 clock-names = "ipg", "per";
156 interrupts = <18>;
157 status = "disabled";
158 };
159
160 spi2: cspi@50010000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx35-cspi";
164 reg = <0x50010000 0x4000>;
165 interrupts = <13>;
166 clocks = <&clks 36 &clks 36>;
167 clock-names = "ipg", "per";
168 status = "disabled";
169 };
170
171 fec: fec@50038000 {
172 compatible = "fsl,imx35-fec", "fsl,imx27-fec";
173 reg = <0x50038000 0x4000>;
174 clocks = <&clks 46>, <&clks 8>;
175 clock-names = "ipg", "ahb";
176 interrupts = <57>;
177 status = "disabled";
178 };
179 };
180
181 aips2: aips@53f00000 {
182 compatible = "fsl,aips", "simple-bus";
183 #address-cells = <1>;
184 #size-cells = <1>;
185 reg = <0x53f00000 0x100000>;
186 ranges;
187
188 clks: ccm@53f80000 {
189 compatible = "fsl,imx35-ccm";
190 reg = <0x53f80000 0x4000>;
191 interrupts = <31>;
192 #clock-cells = <1>;
193 };
194
195 gpio3: gpio@53fa4000 {
196 compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
197 reg = <0x53fa4000 0x4000>;
198 interrupts = <56>;
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 };
204
205 esdhc1: esdhc@53fb4000 {
206 compatible = "fsl,imx35-esdhc";
207 reg = <0x53fb4000 0x4000>;
208 interrupts = <7>;
209 clocks = <&clks 9>, <&clks 8>, <&clks 43>;
210 clock-names = "ipg", "ahb", "per";
211 status = "disabled";
212 };
213
214 esdhc2: esdhc@53fb8000 {
215 compatible = "fsl,imx35-esdhc";
216 reg = <0x53fb8000 0x4000>;
217 interrupts = <8>;
218 clocks = <&clks 9>, <&clks 8>, <&clks 44>;
219 clock-names = "ipg", "ahb", "per";
220 status = "disabled";
221 };
222
223 esdhc3: esdhc@53fbc000 {
224 compatible = "fsl,imx35-esdhc";
225 reg = <0x53fbc000 0x4000>;
226 interrupts = <9>;
227 clocks = <&clks 9>, <&clks 8>, <&clks 45>;
228 clock-names = "ipg", "ahb", "per";
229 status = "disabled";
230 };
231
232 audmux: audmux@53fc4000 {
233 compatible = "fsl,imx35-audmux", "fsl,imx31-audmux";
234 reg = <0x53fc4000 0x4000>;
235 status = "disabled";
236 };
237
238 gpio1: gpio@53fcc000 {
239 compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
240 reg = <0x53fcc000 0x4000>;
241 interrupts = <52>;
242 gpio-controller;
243 #gpio-cells = <2>;
244 interrupt-controller;
245 #interrupt-cells = <2>;
246 };
247
248 gpio2: gpio@53fd0000 {
249 compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
250 reg = <0x53fd0000 0x4000>;
251 interrupts = <51>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
256 };
257
258 sdma: sdma@53fd4000 {
259 compatible = "fsl,imx35-sdma";
260 reg = <0x53fd4000 0x4000>;
261 clocks = <&clks 9>, <&clks 65>;
262 clock-names = "ipg", "ahb";
263 #dma-cells = <3>;
264 interrupts = <34>;
265 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin";
266 };
267
268 wdog: wdog@53fdc000 {
269 compatible = "fsl,imx35-wdt", "fsl,imx21-wdt";
270 reg = <0x53fdc000 0x4000>;
271 clocks = <&clks 74>;
272 clock-names = "";
273 interrupts = <55>;
274 };
275
276 can1: can@53fe4000 {
277 compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
278 reg = <0x53fe4000 0x1000>;
279 clocks = <&clks 33>;
280 clock-names = "ipg";
281 interrupts = <43>;
282 status = "disabled";
283 };
284
285 can2: can@53fe8000 {
286 compatible = "fsl,imx35-flexcan", "fsl,p1010-flexcan";
287 reg = <0x53fe8000 0x1000>;
288 clocks = <&clks 34>;
289 clock-names = "ipg";
290 interrupts = <44>;
291 status = "disabled";
292 };
293
294 usbotg: usb@53ff4000 {
295 compatible = "fsl,imx35-usb", "fsl,imx27-usb";
296 reg = <0x53ff4000 0x0200>;
297 interrupts = <37>;
298 clocks = <&clks 9>, <&clks 73>, <&clks 28>;
299 clock-names = "ipg", "ahb", "per";
300 fsl,usbmisc = <&usbmisc 0>;
301 status = "disabled";
302 };
303
304 usbhost1: usb@53ff4400 {
305 compatible = "fsl,imx35-usb", "fsl,imx27-usb";
306 reg = <0x53ff4400 0x0200>;
307 interrupts = <35>;
308 clocks = <&clks 9>, <&clks 73>, <&clks 28>;
309 clock-names = "ipg", "ahb", "per";
310 fsl,usbmisc = <&usbmisc 1>;
311 status = "disabled";
312 };
313
314 usbmisc: usbmisc@53ff4600 {
315 #index-cells = <1>;
316 compatible = "fsl,imx35-usbmisc";
317 clocks = <&clks 9>, <&clks 73>, <&clks 28>;
318 clock-names = "ipg", "ahb", "per";
319 reg = <0x53ff4600 0x00f>;
320 };
321 };
322
323 emi@80000000 { /* External Memory Interface */
324 compatible = "fsl,emi", "simple-bus";
325 #address-cells = <1>;
326 #size-cells = <1>;
327 reg = <0x80000000 0x40000000>;
328 ranges;
329
330 nfc: nand@bb000000 {
331 #address-cells = <1>;
332 #size-cells = <1>;
333 compatible = "fsl,imx35-nand", "fsl,imx25-nand";
334 reg = <0xbb000000 0x2000>;
335 clocks = <&clks 29>;
336 clock-names = "";
337 interrupts = <33>;
338 status = "disabled";
339 };
340
341 weim: weim@b8002000 {
342 #address-cells = <2>;
343 #size-cells = <1>;
344 clocks = <&clks 0>;
345 compatible = "fsl,imx35-weim", "fsl,imx27-weim";
346 reg = <0xb8002000 0x1000>;
347 ranges = <
348 0 0 0xa0000000 0x8000000
349 1 0 0xa8000000 0x8000000
350 2 0 0xb0000000 0x2000000
351 3 0 0xb2000000 0x2000000
352 4 0 0xb4000000 0x2000000
353 5 0 0xb6000000 0x2000000
354 >;
355 status = "disabled";
356 };
357 };
358 };
359};
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
new file mode 100644
index 000000000000..1b22512c91bd
--- /dev/null
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -0,0 +1,119 @@
1/*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15#include "imx50.dtsi"
16
17/ {
18 model = "Freescale i.MX50 Evaluation Kit";
19 compatible = "fsl,imx50-evk", "fsl,imx50";
20
21 memory {
22 reg = <0x70000000 0x80000000>;
23 };
24};
25
26&cspi {
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_cspi>;
29 fsl,spi-num-chipselects = <2>;
30 cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
31 status = "okay";
32
33 flash: m25p32@1 {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "m25p32", "m25p80";
37 spi-max-frequency = <25000000>;
38 reg = <1>;
39
40 partition@0 {
41 label = "bootloader";
42 reg = <0x0 0x100000>;
43 read-only;
44 };
45
46 partition@100000 {
47 label = "kernel";
48 reg = <0x100000 0x300000>;
49 };
50 };
51};
52
53&fec {
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_fec>;
56 phy-mode = "rmii";
57 phy-reset-gpios = <&gpio4 12 0>;
58 status = "okay";
59};
60
61&iomuxc {
62 imx50-evk {
63 pinctrl_cspi: cspigrp {
64 fsl,pins = <
65 MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
66 MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
67 MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
68 MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
69 MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4
70 >;
71 };
72
73 pinctrl_fec: fecgrp {
74 fsl,pins = <
75 MX50_PAD_SSI_RXFS__FEC_MDC 0x80
76 MX50_PAD_SSI_RXC__FEC_MDIO 0x80
77 MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
78 MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
79 MX50_PAD_DISP_D2__FEC_RX_DV 0x80
80 MX50_PAD_DISP_D3__FEC_RDATA_1 0x80
81 MX50_PAD_DISP_D4__FEC_RDATA_0 0x80
82 MX50_PAD_DISP_D5__FEC_TX_EN 0x80
83 MX50_PAD_DISP_D6__FEC_TDATA_1 0x80
84 MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
85 >;
86 };
87
88 pinctrl_uart1: uart1grp {
89 fsl,pins = <
90 MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4
91 MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4
92 MX50_PAD_UART1_RTS__UART1_RTS 0x1e4
93 MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
94 >;
95 };
96 };
97};
98
99&uart1 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_uart1>;
102 status = "okay";
103};
104
105&usbh1 {
106 status = "okay";
107};
108
109&usbh2 {
110 status = "okay";
111};
112
113&usbh3 {
114 status = "okay";
115};
116
117&usbotg {
118 status = "okay";
119};
diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/imx50-pinfunc.h
new file mode 100644
index 000000000000..97e6e7f4ebdd
--- /dev/null
+++ b/arch/arm/boot/dts/imx50-pinfunc.h
@@ -0,0 +1,923 @@
1/*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_IMX50_PINFUNC_H
11#define __DTS_IMX50_PINFUNC_H
12
13/*
14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */
17#define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
18#define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
19#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
20#define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
21#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
22#define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
23#define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
24#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
25#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
26#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
27#define MX50_PAD_KEY_COL1__KPP_COL_1 0x028 0x2d4 0x000 0x0 0x0
28#define MX50_PAD_KEY_COL1__GPIO4_2 0x028 0x2d4 0x000 0x1 0x0
29#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0
30#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6 0x028 0x2d4 0x000 0x6 0x0
31#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE 0x028 0x2d4 0x000 0x7 0x0
32#define MX50_PAD_KEY_ROW1__KPP_ROW_1 0x02c 0x2d8 0x000 0x0 0x0
33#define MX50_PAD_KEY_ROW1__GPIO4_3 0x02c 0x2d8 0x000 0x1 0x0
34#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0
35#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0
36#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0
37#define MX50_PAD_KEY_COL2__KPP_COL_1 0x030 0x2dc 0x000 0x0 0x0
38#define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0
39#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0
40#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0
41#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK 0x030 0x2dc 0x000 0x7 0x0
42#define MX50_PAD_KEY_ROW2__KPP_ROW_2 0x034 0x2e0 0x000 0x0 0x0
43#define MX50_PAD_KEY_ROW2__GPIO4_5 0x034 0x2e0 0x000 0x1 0x0
44#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0
45#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0
46#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0
47#define MX50_PAD_KEY_COL3__KPP_COL_2 0x038 0x2e4 0x000 0x0 0x0
48#define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0
49#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0
50#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0
51#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1 0x038 0x2e4 0x000 0x7 0x0
52#define MX50_PAD_KEY_ROW3__KPP_ROW_3 0x03c 0x2e8 0x000 0x0 0x0
53#define MX50_PAD_KEY_ROW3__GPIO4_7 0x03c 0x2e8 0x000 0x1 0x0
54#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0
55#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1 0x03c 0x2e8 0x7bc 0x6 0x0
56#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID 0x03c 0x2e8 0x000 0x7 0x0
57#define MX50_PAD_I2C1_SCL__I2C1_SCL 0x040 0x2ec 0x000 0x0 0x0
58#define MX50_PAD_I2C1_SCL__GPIO6_18 0x040 0x2ec 0x000 0x1 0x0
59#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0
60#define MX50_PAD_I2C1_SDA__I2C1_SDA 0x044 0x2f0 0x000 0x0 0x0
61#define MX50_PAD_I2C1_SDA__GPIO6_19 0x044 0x2f0 0x000 0x1 0x0
62#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2 0x1
63#define MX50_PAD_I2C2_SCL__I2C2_SCL 0x048 0x2f4 0x000 0x0 0x0
64#define MX50_PAD_I2C2_SCL__GPIO6_20 0x048 0x2f4 0x000 0x1 0x0
65#define MX50_PAD_I2C2_SCL__UART2_CTS 0x048 0x2f4 0x000 0x2 0x0
66#define MX50_PAD_I2C2_SDA__I2C2_SDA 0x04c 0x2f8 0x000 0x0 0x0
67#define MX50_PAD_I2C2_SDA__GPIO6_21 0x04c 0x2f8 0x000 0x1 0x0
68#define MX50_PAD_I2C2_SDA__UART2_RTS 0x04c 0x2f8 0x7c8 0x2 0x1
69#define MX50_PAD_I2C3_SCL__I2C3_SCL 0x050 0x2fc 0x000 0x0 0x0
70#define MX50_PAD_I2C3_SCL__GPIO6_22 0x050 0x2fc 0x000 0x1 0x0
71#define MX50_PAD_I2C3_SCL__FEC_MDC 0x050 0x2fc 0x000 0x2 0x0
72#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY 0x050 0x2fc 0x000 0x3 0x0
73#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 0x050 0x2fc 0x000 0x5 0x0
74#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0 0x050 0x2fc 0x000 0x6 0x0
75#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC 0x050 0x2fc 0x7e8 0x7 0x0
76#define MX50_PAD_I2C3_SDA__I2C3_SDA 0x054 0x300 0x000 0x0 0x0
77#define MX50_PAD_I2C3_SDA__GPIO6_23 0x054 0x300 0x000 0x1 0x0
78#define MX50_PAD_I2C3_SDA__FEC_MDIO 0x054 0x300 0x774 0x2 0x0
79#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT 0x054 0x300 0x000 0x3 0x0
80#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB 0x054 0x300 0x000 0x4 0x0
81#define MX50_PAD_I2C3_SDA__GPT_CAPIN2 0x054 0x300 0x000 0x5 0x0
82#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1 0x054 0x300 0x000 0x6 0x0
83#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR 0x054 0x300 0x000 0x7 0x0
84#define MX50_PAD_PWM1__PWM1_PWMO 0x058 0x304 0x000 0x0 0x0
85#define MX50_PAD_PWM1__GPIO6_24 0x058 0x304 0x000 0x1 0x0
86#define MX50_PAD_PWM1__USBOH1_USBOTG_OC 0x058 0x304 0x7e8 0x2 0x1
87#define MX50_PAD_PWM1__GPT_CMPOUT1 0x058 0x304 0x000 0x5 0x0
88#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2 0x058 0x304 0x000 0x6 0x0
89#define MX50_PAD_PWM1__SJC_FAIL 0x058 0x304 0x000 0x7 0x0
90#define MX50_PAD_PWM2__PWM2_PWMO 0x05c 0x308 0x000 0x0 0x0
91#define MX50_PAD_PWM2__GPIO6_25 0x05c 0x308 0x000 0x1 0x0
92#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR 0x05c 0x308 0x000 0x2 0x0
93#define MX50_PAD_PWM2__GPT_CMPOUT2 0x05c 0x308 0x000 0x5 0x0
94#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3 0x05c 0x308 0x000 0x6 0x0
95#define MX50_PAD_PWM2__SRC_ANY_PU_RST 0x05c 0x308 0x000 0x7 0x0
96#define MX50_PAD_OWIRE__OWIRE_LINE 0x060 0x30c 0x000 0x0 0x0
97#define MX50_PAD_OWIRE__GPIO6_26 0x060 0x30c 0x000 0x1 0x0
98#define MX50_PAD_OWIRE__USBOH1_USBH1_OC 0x060 0x30c 0x000 0x2 0x0
99#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK 0x060 0x30c 0x000 0x3 0x0
100#define MX50_PAD_OWIRE__EPDC_PWRIRQ 0x060 0x30c 0x000 0x4 0x0
101#define MX50_PAD_OWIRE__GPT_CMPOUT3 0x060 0x30c 0x000 0x5 0x0
102#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4 0x060 0x30c 0x000 0x6 0x0
103#define MX50_PAD_OWIRE__SJC_JTAG_ACT 0x060 0x30c 0x000 0x7 0x0
104#define MX50_PAD_EPITO__EPIT1_EPITO 0x064 0x310 0x000 0x0 0x0
105#define MX50_PAD_EPITO__GPIO6_27 0x064 0x310 0x000 0x1 0x0
106#define MX50_PAD_EPITO__USBOH1_USBH1_PWR 0x064 0x310 0x000 0x2 0x0
107#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK 0x064 0x310 0x000 0x3 0x0
108#define MX50_PAD_EPITO__DPLLIP1_TOG_EN 0x064 0x310 0x000 0x4 0x0
109#define MX50_PAD_EPITO__GPT_CLK_IN 0x064 0x310 0x000 0x5 0x0
110#define MX50_PAD_EPITO__PMU_IRQ_B 0x064 0x310 0x000 0x6 0x0
111#define MX50_PAD_EPITO__SJC_DE_B 0x064 0x310 0x000 0x7 0x0
112#define MX50_PAD_WDOG__WDOG1_WDOG_B 0x068 0x314 0x000 0x0 0x0
113#define MX50_PAD_WDOG__GPIO6_28 0x068 0x314 0x000 0x1 0x0
114#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB 0x068 0x314 0x000 0x2 0x0
115#define MX50_PAD_WDOG__CCM_XTAL32K 0x068 0x314 0x000 0x6 0x0
116#define MX50_PAD_WDOG__SJC_DONE 0x068 0x314 0x000 0x7 0x0
117#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS 0x06c 0x318 0x000 0x0 0x0
118#define MX50_PAD_SSI_TXFS__GPIO6_0 0x06c 0x318 0x000 0x1 0x0
119#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1 0x06c 0x318 0x000 0x6 0x0
120#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8 0x06c 0x318 0x000 0x7 0x0
121#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC 0x070 0x31c 0x000 0x0 0x0
122#define MX50_PAD_SSI_TXC__GPIO6_1 0x070 0x31c 0x000 0x1 0x0
123#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0 0x070 0x31c 0x000 0x6 0x0
124#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9 0x070 0x31c 0x000 0x7 0x0
125#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD 0x074 0x320 0x000 0x0 0x0
126#define MX50_PAD_SSI_TXD__GPIO6_2 0x074 0x320 0x000 0x1 0x0
127#define MX50_PAD_SSI_TXD__CSPI_RDY 0x074 0x320 0x6e8 0x4 0x0
128#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10 0x074 0x320 0x000 0x7 0x0
129#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD 0x078 0x324 0x000 0x0 0x0
130#define MX50_PAD_SSI_RXD__GPIO6_3 0x078 0x324 0x000 0x1 0x0
131#define MX50_PAD_SSI_RXD__CSPI_SS3 0x078 0x324 0x6f4 0x4 0x0
132#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11 0x078 0x324 0x000 0x7 0x0
133#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS 0x07c 0x328 0x000 0x0 0x0
134#define MX50_PAD_SSI_RXFS__GPIO6_4 0x07c 0x328 0x000 0x1 0x0
135#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX 0x07c 0x328 0x7e4 0x2 0x0
136#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6 0x07c 0x328 0x804 0x3 0x0
137#define MX50_PAD_SSI_RXFS__CSPI_SS2 0x07c 0x328 0x6f0 0x4 0x0
138#define MX50_PAD_SSI_RXFS__FEC_COL 0x07c 0x328 0x770 0x5 0x0
139#define MX50_PAD_SSI_RXFS__FEC_MDC 0x07c 0x328 0x000 0x6 0x0
140#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12 0x07c 0x328 0x000 0x7 0x0
141#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC 0x080 0x32c 0x000 0x0 0x0
142#define MX50_PAD_SSI_RXC__GPIO6_5 0x080 0x32c 0x000 0x1 0x0
143#define MX50_PAD_SSI_RXC__UART5_RXD_MUX 0x080 0x32c 0x7e4 0x2 0x1
144#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7 0x080 0x32c 0x808 0x3 0x0
145#define MX50_PAD_SSI_RXC__CSPI_SS1 0x080 0x32c 0x6ec 0x4 0x0
146#define MX50_PAD_SSI_RXC__FEC_RX_CLK 0x080 0x32c 0x780 0x5 0x0
147#define MX50_PAD_SSI_RXC__FEC_MDIO 0x080 0x32c 0x774 0x6 0x1
148#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13 0x080 0x32c 0x000 0x7 0x0
149#define MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x084 0x330 0x7c4 0x0 0x0
150#define MX50_PAD_UART1_TXD__GPIO6_6 0x084 0x330 0x000 0x1 0x0
151#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14 0x084 0x330 0x000 0x7 0x0
152#define MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x088 0x334 0x7c4 0x0 0x1
153#define MX50_PAD_UART1_RXD__GPIO6_7 0x088 0x334 0x000 0x1 0x0
154#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15 0x088 0x334 0x000 0x7 0x0
155#define MX50_PAD_UART1_CTS__UART1_CTS 0x08c 0x338 0x000 0x0 0x0
156#define MX50_PAD_UART1_CTS__GPIO6_8 0x08c 0x338 0x000 0x1 0x0
157#define MX50_PAD_UART1_CTS__UART5_TXD_MUX 0x08c 0x338 0x7e4 0x2 0x2
158#define MX50_PAD_UART1_CTS__ESDHC4_DAT4 0x08c 0x338 0x760 0x4 0x0
159#define MX50_PAD_UART1_CTS__ESDHC4_CMD 0x08c 0x338 0x74c 0x5 0x0
160#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8 0x08c 0x338 0x000 0x7 0x0
161#define MX50_PAD_UART1_RTS__UART1_RTS 0x090 0x33c 0x7c0 0x0 0x3
162#define MX50_PAD_UART1_RTS__GPIO6_9 0x090 0x33c 0x000 0x1 0x0
163#define MX50_PAD_UART1_RTS__UART5_RXD_MUX 0x090 0x33c 0x7e4 0x2 0x3
164#define MX50_PAD_UART1_RTS__ESDHC4_DAT5 0x090 0x33c 0x764 0x4 0x0
165#define MX50_PAD_UART1_RTS__ESDHC4_CLK 0x090 0x33c 0x748 0x5 0x0
166#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9 0x090 0x33c 0x000 0x7 0x0
167#define MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x094 0x340 0x7cc 0x0 0x2
168#define MX50_PAD_UART2_TXD__GPIO6_10 0x094 0x340 0x000 0x1 0x0
169#define MX50_PAD_UART2_TXD__ESDHC4_DAT6 0x094 0x340 0x768 0x4 0x0
170#define MX50_PAD_UART2_TXD__ESDHC4_DAT4 0x094 0x340 0x760 0x5 0x1
171#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10 0x094 0x340 0x000 0x7 0x0
172#define MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x098 0x344 0x7cc 0x0 0x3
173#define MX50_PAD_UART2_RXD__GPIO6_11 0x098 0x344 0x000 0x1 0x0
174#define MX50_PAD_UART2_RXD__ESDHC4_DAT7 0x098 0x344 0x76c 0x4 0x0
175#define MX50_PAD_UART2_RXD__ESDHC4_DAT5 0x098 0x344 0x764 0x5 0x1
176#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11 0x098 0x344 0x000 0x7 0x0
177#define MX50_PAD_UART2_CTS__UART2_CTS 0x09c 0x348 0x000 0x0 0x0
178#define MX50_PAD_UART2_CTS__GPIO6_12 0x09c 0x348 0x000 0x1 0x0
179#define MX50_PAD_UART2_CTS__ESDHC4_CMD 0x09c 0x348 0x74c 0x4 0x1
180#define MX50_PAD_UART2_CTS__ESDHC4_DAT6 0x09c 0x348 0x768 0x5 0x1
181#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12 0x09c 0x348 0x000 0x7 0x0
182#define MX50_PAD_UART2_RTS__UART2_RTS 0x0a0 0x34c 0x7c8 0x0 0x2
183#define MX50_PAD_UART2_RTS__GPIO6_13 0x0a0 0x34c 0x000 0x1 0x0
184#define MX50_PAD_UART2_RTS__ESDHC4_CLK 0x0a0 0x34c 0x748 0x4 0x1
185#define MX50_PAD_UART2_RTS__ESDHC4_DAT7 0x0a0 0x34c 0x76c 0x5 0x1
186#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13 0x0a0 0x34c 0x000 0x7 0x0
187#define MX50_PAD_UART3_TXD__UART3_TXD_MUX 0x0a4 0x350 0x7d4 0x0 0x0
188#define MX50_PAD_UART3_TXD__GPIO6_14 0x0a4 0x350 0x000 0x1 0x0
189#define MX50_PAD_UART3_TXD__ESDHC1_DAT4 0x0a4 0x350 0x000 0x3 0x0
190#define MX50_PAD_UART3_TXD__ESDHC4_DAT0 0x0a4 0x350 0x000 0x4 0x0
191#define MX50_PAD_UART3_TXD__ESDHC2_WP 0x0a4 0x350 0x744 0x5 0x0
192#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12 0x0a4 0x350 0x81c 0x6 0x0
193#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14 0x0a4 0x350 0x000 0x7 0x0
194#define MX50_PAD_UART3_RXD__UART3_RXD_MUX 0x0a8 0x354 0x7d4 0x0 0x1
195#define MX50_PAD_UART3_RXD__GPIO6_15 0x0a8 0x354 0x000 0x1 0x0
196#define MX50_PAD_UART3_RXD__ESDHC1_DAT5 0x0a8 0x354 0x000 0x3 0x0
197#define MX50_PAD_UART3_RXD__ESDHC4_DAT1 0x0a8 0x354 0x754 0x4 0x0
198#define MX50_PAD_UART3_RXD__ESDHC2_CD 0x0a8 0x354 0x740 0x5 0x0
199#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0
200#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15 0x0a8 0x354 0x000 0x7 0x0
201#define MX50_PAD_UART4_TXD__UART4_TXD_MUX 0x0ac 0x358 0x7dc 0x0 0x0
202#define MX50_PAD_UART4_TXD__GPIO6_16 0x0ac 0x358 0x000 0x1 0x0
203#define MX50_PAD_UART4_TXD__UART3_CTS 0x0ac 0x358 0x7d0 0x2 0x0
204#define MX50_PAD_UART4_TXD__ESDHC1_DAT6 0x0ac 0x358 0x000 0x3 0x0
205#define MX50_PAD_UART4_TXD__ESDHC4_DAT2 0x0ac 0x358 0x758 0x4 0x0
206#define MX50_PAD_UART4_TXD__ESDHC2_LCTL 0x0ac 0x358 0x000 0x5 0x0
207#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14 0x0ac 0x358 0x824 0x6 0x0
208#define MX50_PAD_UART4_RXD__UART4_RXD_MUX 0x0b0 0x35c 0x7dc 0x0 0x1
209#define MX50_PAD_UART4_RXD__GPIO6_17 0x0b0 0x35c 0x000 0x1 0x0
210#define MX50_PAD_UART4_RXD__UART3_RTS 0x0b0 0x35c 0x7d0 0x2 0x1
211#define MX50_PAD_UART4_RXD__ESDHC1_DAT7 0x0b0 0x35c 0x000 0x3 0x0
212#define MX50_PAD_UART4_RXD__ESDHC4_DAT3 0x0b0 0x35c 0x75c 0x4 0x0
213#define MX50_PAD_UART4_RXD__ESDHC1_LCTL 0x0b0 0x35c 0x000 0x5 0x0
214#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15 0x0b0 0x35c 0x828 0x6 0x0
215#define MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x0b4 0x360 0x000 0x0 0x0
216#define MX50_PAD_CSPI_SCLK__GPIO4_8 0x0b4 0x360 0x000 0x1 0x0
217#define MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x0b8 0x364 0x000 0x0 0x0
218#define MX50_PAD_CSPI_MOSI__GPIO4_9 0x0b8 0x364 0x000 0x1 0x0
219#define MX50_PAD_CSPI_MISO__CSPI_MISO 0x0bc 0x368 0x000 0x0 0x0
220#define MX50_PAD_CSPI_MISO__GPIO4_10 0x0bc 0x368 0x000 0x1 0x0
221#define MX50_PAD_CSPI_SS0__CSPI_SS0 0x0c0 0x36c 0x000 0x0 0x0
222#define MX50_PAD_CSPI_SS0__GPIO4_11 0x0c0 0x36c 0x000 0x1 0x0
223#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0c4 0x370 0x000 0x0 0x0
224#define MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0c4 0x370 0x000 0x1 0x0
225#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY 0x0c4 0x370 0x6e8 0x2 0x1
226#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY 0x0c4 0x370 0x000 0x3 0x0
227#define MX50_PAD_ECSPI1_SCLK__UART3_RTS 0x0c4 0x370 0x7d0 0x4 0x2
228#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6 0x0c4 0x370 0x000 0x5 0x0
229#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8 0x0c4 0x370 0x80c 0x7 0x0
230#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x0c8 0x374 0x000 0x0 0x0
231#define MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x0c8 0x374 0x000 0x1 0x0
232#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0x0c8 0x374 0x6ec 0x2 0x1
233#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 0x0c8 0x374 0x000 0x3 0x0
234#define MX50_PAD_ECSPI1_MOSI__UART3_CTS 0x0c8 0x374 0x000 0x4 0x0
235#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7 0x0c8 0x374 0x000 0x5 0x0
236#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9 0x0c8 0x374 0x810 0x7 0x0
237#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0cc 0x378 0x000 0x0 0x0
238#define MX50_PAD_ECSPI1_MISO__GPIO4_14 0x0cc 0x378 0x000 0x1 0x0
239#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 0x0cc 0x378 0x6f0 0x2 0x1
240#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 0x0cc 0x378 0x000 0x3 0x0
241#define MX50_PAD_ECSPI1_MISO__UART4_RTS 0x0cc 0x378 0x7d8 0x4 0x0
242#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8 0x0cc 0x378 0x000 0x5 0x0
243#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10 0x0cc 0x378 0x814 0x7 0x0
244#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0d0 0x37c 0x000 0x0 0x0
245#define MX50_PAD_ECSPI1_SS0__GPIO4_15 0x0d0 0x37c 0x000 0x1 0x0
246#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 0x0d0 0x37c 0x6f4 0x2 0x1
247#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 0x0d0 0x37c 0x000 0x3 0x0
248#define MX50_PAD_ECSPI1_SS0__UART4_CTS 0x0d0 0x37c 0x000 0x4 0x0
249#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9 0x0d0 0x37c 0x000 0x5 0x0
250#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11 0x0d0 0x37c 0x818 0x7 0x0
251#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0d4 0x380 0x000 0x0 0x0
252#define MX50_PAD_ECSPI2_SCLK__GPIO4_16 0x0d4 0x380 0x000 0x1 0x0
253#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN 0x0d4 0x380 0x000 0x2 0x0
254#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY 0x0d4 0x380 0x000 0x3 0x0
255#define MX50_PAD_ECSPI2_SCLK__UART5_RTS 0x0d4 0x380 0x7e0 0x4 0x0
256#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK 0x0d4 0x380 0x000 0x5 0x0
257#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4 0x0d4 0x380 0x000 0x6 0x0
258#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8 0x0d4 0x380 0x80c 0x7 0x1
259#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x0d8 0x384 0x000 0x0 0x0
260#define MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0d8 0x384 0x000 0x1 0x0
261#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E 0x0d8 0x384 0x000 0x2 0x0
262#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 0x0d8 0x384 0x000 0x3 0x0
263#define MX50_PAD_ECSPI2_MOSI__UART5_CTS 0x0d8 0x384 0x7e0 0x4 0x1
264#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE 0x0d8 0x384 0x000 0x5 0x0
265#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5 0x0d8 0x384 0x000 0x6 0x0
266#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9 0x0d8 0x384 0x810 0x7 0x1
267#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0dc 0x388 0x000 0x0 0x0
268#define MX50_PAD_ECSPI2_MISO__GPIO4_18 0x0dc 0x388 0x000 0x1 0x0
269#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS 0x0dc 0x388 0x000 0x2 0x0
270#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 0x0dc 0x388 0x000 0x3 0x0
271#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX 0x0dc 0x388 0x7e4 0x4 0x4
272#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC 0x0dc 0x388 0x73c 0x5 0x0
273#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6 0x0dc 0x388 0x000 0x6 0x0
274#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10 0x0dc 0x388 0x814 0x7 0x1
275#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0e0 0x38c 0x000 0x0 0x0
276#define MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0e0 0x38c 0x000 0x1 0x0
277#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS 0x0e0 0x38c 0x000 0x2 0x0
278#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3 0x0e0 0x38c 0x000 0x3 0x0
279#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX 0x0e0 0x38c 0x7e4 0x4 0x5
280#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC 0x0e0 0x38c 0x6f8 0x5 0x0
281#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7 0x0e0 0x38c 0x000 0x6 0x0
282#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11 0x0e0 0x38c 0x818 0x7 0x1
283#define MX50_PAD_SD1_CLK__ESDHC1_CLK 0x0e4 0x390 0x000 0x0 0x0
284#define MX50_PAD_SD1_CLK__GPIO5_0 0x0e4 0x390 0x000 0x1 0x0
285#define MX50_PAD_SD1_CLK__CCM_CLKO 0x0e4 0x390 0x000 0x7 0x0
286#define MX50_PAD_SD1_CMD__ESDHC1_CMD 0x0e8 0x394 0x000 0x0 0x0
287#define MX50_PAD_SD1_CMD__GPIO5_1 0x0e8 0x394 0x000 0x1 0x0
288#define MX50_PAD_SD1_CMD__CCM_CLKO2 0x0e8 0x394 0x000 0x7 0x0
289#define MX50_PAD_SD1_D0__ESDHC1_DAT0 0x0ec 0x398 0x000 0x0 0x0
290#define MX50_PAD_SD1_D0__GPIO5_2 0x0ec 0x398 0x000 0x1 0x0
291#define MX50_PAD_SD1_D0__CCM_PLL1_BYP 0x0ec 0x398 0x6dc 0x7 0x0
292#define MX50_PAD_SD1_D1__ESDHC1_DAT1 0x0f0 0x39c 0x000 0x0 0x0
293#define MX50_PAD_SD1_D1__GPIO5_3 0x0f0 0x39c 0x000 0x1 0x0
294#define MX50_PAD_SD1_D1__CCM_PLL2_BYP 0x0f0 0x39c 0x000 0x7 0x0
295#define MX50_PAD_SD1_D2__ESDHC1_DAT2 0x0f4 0x3a0 0x000 0x0 0x0
296#define MX50_PAD_SD1_D2__GPIO5_4 0x0f4 0x3a0 0x000 0x1 0x0
297#define MX50_PAD_SD1_D2__CCM_PLL3_BYP 0x0f4 0x3a0 0x6e4 0x7 0x0
298#define MX50_PAD_SD1_D3__ESDHC1_DAT3 0x0f8 0x3a4 0x000 0x0 0x0
299#define MX50_PAD_SD1_D3__GPIO5_5 0x0f8 0x3a4 0x000 0x1 0x0
300#define MX50_PAD_SD2_CLK__ESDHC2_CLK 0x0fc 0x3a8 0x000 0x0 0x0
301#define MX50_PAD_SD2_CLK__GPIO5_6 0x0fc 0x3a8 0x000 0x1 0x0
302#define MX50_PAD_SD2_CLK__MSHC_SCLK 0x0fc 0x3a8 0x000 0x2 0x0
303#define MX50_PAD_SD2_CMD__ESDHC2_CMD 0x100 0x3ac 0x000 0x0 0x0
304#define MX50_PAD_SD2_CMD__GPIO5_7 0x100 0x3ac 0x000 0x1 0x0
305#define MX50_PAD_SD2_CMD__MSHC_BS 0x100 0x3ac 0x000 0x2 0x0
306#define MX50_PAD_SD2_D0__ESDHC2_DAT0 0x104 0x3b0 0x000 0x0 0x0
307#define MX50_PAD_SD2_D0__GPIO5_8 0x104 0x3b0 0x000 0x1 0x0
308#define MX50_PAD_SD2_D0__MSHC_DATA_0 0x104 0x3b0 0x000 0x2 0x0
309#define MX50_PAD_SD2_D0__KPP_COL_4 0x104 0x3b0 0x790 0x3 0x0
310#define MX50_PAD_SD2_D1__ESDHC2_DAT1 0x108 0x3b4 0x000 0x0 0x0
311#define MX50_PAD_SD2_D1__GPIO5_9 0x108 0x3b4 0x000 0x1 0x0
312#define MX50_PAD_SD2_D1__MSHC_DATA_1 0x108 0x3b4 0x000 0x2 0x0
313#define MX50_PAD_SD2_D1__KPP_ROW_4 0x108 0x3b4 0x7a0 0x3 0x0
314#define MX50_PAD_SD2_D2__ESDHC2_DAT2 0x10c 0x3b8 0x000 0x0 0x0
315#define MX50_PAD_SD2_D2__GPIO5_10 0x10c 0x3b8 0x000 0x1 0x0
316#define MX50_PAD_SD2_D2__MSHC_DATA_2 0x10c 0x3b8 0x000 0x2 0x0
317#define MX50_PAD_SD2_D2__KPP_COL_5 0x10c 0x3b8 0x794 0x3 0x0
318#define MX50_PAD_SD2_D3__ESDHC2_DAT3 0x110 0x3bc 0x000 0x0 0x0
319#define MX50_PAD_SD2_D3__GPIO5_11 0x110 0x3bc 0x000 0x1 0x0
320#define MX50_PAD_SD2_D3__MSHC_DATA_3 0x110 0x3bc 0x000 0x2 0x0
321#define MX50_PAD_SD2_D3__KPP_ROW_5 0x110 0x3bc 0x7a4 0x3 0x0
322#define MX50_PAD_SD2_D4__ESDHC2_DAT4 0x114 0x3c0 0x000 0x0 0x0
323#define MX50_PAD_SD2_D4__GPIO5_12 0x114 0x3c0 0x000 0x1 0x0
324#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS 0x114 0x3c0 0x6d0 0x2 0x0
325#define MX50_PAD_SD2_D4__KPP_COL_6 0x114 0x3c0 0x798 0x3 0x0
326#define MX50_PAD_SD2_D4__EIM_WEIM_D_0 0x114 0x3c0 0x7ec 0x4 0x0
327#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0 0x114 0x3c0 0x000 0x7 0x0
328#define MX50_PAD_SD2_D5__ESDHC2_DAT5 0x118 0x3c4 0x000 0x0 0x0
329#define MX50_PAD_SD2_D5__GPIO5_13 0x118 0x3c4 0x000 0x1 0x0
330#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC 0x118 0x3c4 0x6cc 0x2 0x0
331#define MX50_PAD_SD2_D5__KPP_ROW_6 0x118 0x3c4 0x7a8 0x3 0x0
332#define MX50_PAD_SD2_D5__EIM_WEIM_D_1 0x118 0x3c4 0x7f0 0x4 0x0
333#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1 0x118 0x3c4 0x000 0x7 0x0
334#define MX50_PAD_SD2_D6__ESDHC2_DAT6 0x11c 0x3c8 0x000 0x0 0x0
335#define MX50_PAD_SD2_D6__GPIO5_14 0x11c 0x3c8 0x000 0x1 0x0
336#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD 0x11c 0x3c8 0x6c4 0x2 0x0
337#define MX50_PAD_SD2_D6__KPP_COL_7 0x11c 0x3c8 0x79c 0x3 0x0
338#define MX50_PAD_SD2_D6__EIM_WEIM_D_2 0x11c 0x3c8 0x7f4 0x4 0x0
339#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2 0x11c 0x3c8 0x000 0x7 0x0
340#define MX50_PAD_SD2_D7__ESDHC2_DAT7 0x120 0x3cc 0x000 0x0 0x0
341#define MX50_PAD_SD2_D7__GPIO5_15 0x120 0x3cc 0x000 0x1 0x0
342#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS 0x120 0x3cc 0x6d8 0x2 0x0
343#define MX50_PAD_SD2_D7__KPP_ROW_7 0x120 0x3cc 0x7ac 0x3 0x0
344#define MX50_PAD_SD2_D7__EIM_WEIM_D_3 0x120 0x3cc 0x7f8 0x4 0x0
345#define MX50_PAD_SD2_D7__CCM_STOP 0x120 0x3cc 0x000 0x7 0x0
346#define MX50_PAD_SD2_WP__ESDHC2_WP 0x124 0x3d0 0x744 0x0 0x1
347#define MX50_PAD_SD2_WP__GPIO5_16 0x124 0x3d0 0x000 0x1 0x0
348#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD 0x124 0x3d0 0x6c8 0x2 0x0
349#define MX50_PAD_SD2_WP__EIM_WEIM_D_4 0x124 0x3d0 0x7fc 0x4 0x0
350#define MX50_PAD_SD2_WP__CCM_WAIT 0x124 0x3d0 0x000 0x7 0x0
351#define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1
352#define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0
353#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0
354#define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0
355#define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0
356#define MX50_PAD_DISP_D0__ELCDIF_DAT_0 0x12c 0x40c 0x6fc 0x0 0x0
357#define MX50_PAD_DISP_D0__GPIO2_0 0x12c 0x40c 0x000 0x1 0x0
358#define MX50_PAD_DISP_D0__FEC_TX_CLK 0x12c 0x40c 0x78c 0x2 0x0
359#define MX50_PAD_DISP_D0__EIM_WEIM_A_16 0x12c 0x40c 0x000 0x3 0x0
360#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0 0x12c 0x40c 0x000 0x6 0x0
361#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0 0x12c 0x40c 0x000 0x7 0x0
362#define MX50_PAD_DISP_D1__ELCDIF_DAT_1 0x130 0x410 0x700 0x0 0x0
363#define MX50_PAD_DISP_D1__GPIO2_1 0x130 0x410 0x000 0x1 0x0
364#define MX50_PAD_DISP_D1__FEC_RX_ERR 0x130 0x410 0x788 0x2 0x0
365#define MX50_PAD_DISP_D1__EIM_WEIM_A_17 0x130 0x410 0x000 0x3 0x0
366#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1 0x130 0x410 0x000 0x6 0x0
367#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1 0x130 0x410 0x000 0x7 0x0
368#define MX50_PAD_DISP_D2__ELCDIF_DAT_2 0x134 0x414 0x704 0x0 0x0
369#define MX50_PAD_DISP_D2__GPIO2_2 0x134 0x414 0x000 0x1 0x0
370#define MX50_PAD_DISP_D2__FEC_RX_DV 0x134 0x414 0x784 0x2 0x0
371#define MX50_PAD_DISP_D2__EIM_WEIM_A_18 0x134 0x414 0x000 0x3 0x0
372#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2 0x134 0x414 0x000 0x6 0x0
373#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2 0x134 0x414 0x000 0x7 0x0
374#define MX50_PAD_DISP_D3__ELCDIF_DAT_3 0x138 0x418 0x708 0x0 0x0
375#define MX50_PAD_DISP_D3__GPIO2_3 0x138 0x418 0x000 0x1 0x0
376#define MX50_PAD_DISP_D3__FEC_RDATA_1 0x138 0x418 0x77c 0x2 0x0
377#define MX50_PAD_DISP_D3__EIM_WEIM_A_19 0x138 0x418 0x000 0x3 0x0
378#define MX50_PAD_DISP_D3__FEC_COL 0x138 0x418 0x770 0x4 0x1
379#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3 0x138 0x418 0x000 0x6 0x0
380#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3 0x138 0x418 0x000 0x7 0x0
381#define MX50_PAD_DISP_D4__ELCDIF_DAT_4 0x13c 0x41c 0x70c 0x0 0x0
382#define MX50_PAD_DISP_D4__GPIO2_4 0x13c 0x41c 0x000 0x1 0x0
383#define MX50_PAD_DISP_D4__FEC_RDATA_0 0x13c 0x41c 0x778 0x2 0x0
384#define MX50_PAD_DISP_D4__EIM_WEIM_A_20 0x13c 0x41c 0x000 0x3 0x0
385#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4 0x13c 0x41c 0x000 0x6 0x0
386#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4 0x13c 0x41c 0x000 0x7 0x0
387#define MX50_PAD_DISP_D5__ELCDIF_DAT_5 0x140 0x420 0x710 0x0 0x0
388#define MX50_PAD_DISP_D5__GPIO2_5 0x140 0x420 0x000 0x1 0x0
389#define MX50_PAD_DISP_D5__FEC_TX_EN 0x140 0x420 0x000 0x2 0x0
390#define MX50_PAD_DISP_D5__EIM_WEIM_A_21 0x140 0x420 0x000 0x3 0x0
391#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5 0x140 0x420 0x000 0x6 0x0
392#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5 0x140 0x420 0x000 0x7 0x0
393#define MX50_PAD_DISP_D6__ELCDIF_DAT_6 0x144 0x424 0x714 0x0 0x0
394#define MX50_PAD_DISP_D6__GPIO2_6 0x144 0x424 0x000 0x1 0x0
395#define MX50_PAD_DISP_D6__FEC_TDATA_1 0x144 0x424 0x000 0x2 0x0
396#define MX50_PAD_DISP_D6__EIM_WEIM_A_22 0x144 0x424 0x000 0x3 0x0
397#define MX50_PAD_DISP_D6__FEC_RX_CLK 0x144 0x424 0x780 0x4 0x1
398#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6 0x144 0x424 0x000 0x6 0x0
399#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6 0x144 0x424 0x000 0x7 0x0
400#define MX50_PAD_DISP_D7__ELCDIF_DAT_7 0x148 0x428 0x718 0x0 0x0
401#define MX50_PAD_DISP_D7__GPIO2_7 0x148 0x428 0x000 0x1 0x0
402#define MX50_PAD_DISP_D7__FEC_TDATA_0 0x148 0x428 0x000 0x2 0x0
403#define MX50_PAD_DISP_D7__EIM_WEIM_A_23 0x148 0x428 0x000 0x3 0x0
404#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7 0x148 0x428 0x000 0x6 0x0
405#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7 0x148 0x428 0x000 0x7 0x0
406#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN 0x14c 0x42c 0x000 0x0 0x0
407#define MX50_PAD_DISP_WR__GPIO2_16 0x14c 0x42c 0x000 0x1 0x0
408#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK 0x14c 0x42c 0x000 0x2 0x0
409#define MX50_PAD_DISP_WR__EIM_WEIM_A_24 0x14c 0x42c 0x000 0x3 0x0
410#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8 0x14c 0x42c 0x000 0x6 0x0
411#define MX50_PAD_DISP_WR__USBPHY1_AVALID 0x14c 0x42c 0x000 0x7 0x0
412#define MX50_PAD_DISP_RD__ELCDIF_RD_E 0x150 0x430 0x000 0x0 0x0
413#define MX50_PAD_DISP_RD__GPIO2_19 0x150 0x430 0x000 0x1 0x0
414#define MX50_PAD_DISP_RD__ELCDIF_ENABLE 0x150 0x430 0x000 0x2 0x0
415#define MX50_PAD_DISP_RD__EIM_WEIM_A_25 0x150 0x430 0x000 0x3 0x0
416#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9 0x150 0x430 0x000 0x6 0x0
417#define MX50_PAD_DISP_RD__USBPHY1_BVALID 0x150 0x430 0x000 0x7 0x0
418#define MX50_PAD_DISP_RS__ELCDIF_RS 0x154 0x434 0x000 0x0 0x0
419#define MX50_PAD_DISP_RS__GPIO2_17 0x154 0x434 0x000 0x1 0x0
420#define MX50_PAD_DISP_RS__ELCDIF_VSYNC 0x154 0x434 0x73c 0x2 0x1
421#define MX50_PAD_DISP_RS__EIM_WEIM_A_26 0x154 0x434 0x000 0x3 0x0
422#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10 0x154 0x434 0x000 0x6 0x0
423#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION 0x154 0x434 0x000 0x7 0x0
424#define MX50_PAD_DISP_CS__ELCDIF_CS 0x158 0x438 0x000 0x0 0x0
425#define MX50_PAD_DISP_CS__GPIO2_21 0x158 0x438 0x000 0x1 0x0
426#define MX50_PAD_DISP_CS__ELCDIF_HSYNC 0x158 0x438 0x6f8 0x2 0x1
427#define MX50_PAD_DISP_CS__EIM_WEIM_A_27 0x158 0x438 0x000 0x3 0x0
428#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3 0x158 0x438 0x000 0x4 0x0
429#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11 0x158 0x438 0x000 0x6 0x0
430#define MX50_PAD_DISP_CS__USBPHY1_IDDIG 0x158 0x438 0x000 0x7 0x0
431#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY 0x15c 0x43c 0x6f8 0x0 0x2
432#define MX50_PAD_DISP_BUSY__GPIO2_18 0x15c 0x43c 0x000 0x1 0x0
433#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3 0x15c 0x43c 0x000 0x4 0x0
434#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12 0x15c 0x43c 0x000 0x6 0x0
435#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT 0x15c 0x43c 0x000 0x7 0x0
436#define MX50_PAD_DISP_RESET__ELCDIF_RESET 0x160 0x440 0x000 0x0 0x0
437#define MX50_PAD_DISP_RESET__GPIO2_20 0x160 0x440 0x000 0x1 0x0
438#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3 0x160 0x440 0x000 0x4 0x0
439#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13 0x160 0x440 0x000 0x6 0x0
440#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK 0x160 0x440 0x000 0x7 0x0
441#define MX50_PAD_SD3_CMD__ESDHC3_CMD 0x164 0x444 0x000 0x0 0x0
442#define MX50_PAD_SD3_CMD__GPIO5_18 0x164 0x444 0x000 0x1 0x0
443#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN 0x164 0x444 0x000 0x2 0x0
444#define MX50_PAD_SD3_CMD__SSP_CMD 0x164 0x444 0x000 0x3 0x0
445#define MX50_PAD_SD3_CLK__ESDHC3_CLK 0x168 0x448 0x000 0x0 0x0
446#define MX50_PAD_SD3_CLK__GPIO5_19 0x168 0x448 0x000 0x1 0x0
447#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN 0x168 0x448 0x000 0x2 0x0
448#define MX50_PAD_SD3_CLK__SSP_CLK 0x168 0x448 0x000 0x3 0x0
449#define MX50_PAD_SD3_D0__ESDHC3_DAT0 0x16c 0x44c 0x000 0x0 0x0
450#define MX50_PAD_SD3_D0__GPIO5_20 0x16c 0x44c 0x000 0x1 0x0
451#define MX50_PAD_SD3_D0__EIM_NANDF_D_4 0x16c 0x44c 0x000 0x2 0x0
452#define MX50_PAD_SD3_D0__SSP_D0 0x16c 0x44c 0x000 0x3 0x0
453#define MX50_PAD_SD3_D0__CCM_PLL1_BYP 0x16c 0x44c 0x6dc 0x7 0x1
454#define MX50_PAD_SD3_D1__ESDHC3_DAT1 0x170 0x450 0x000 0x0 0x0
455#define MX50_PAD_SD3_D1__GPIO5_21 0x170 0x450 0x000 0x1 0x0
456#define MX50_PAD_SD3_D1__EIM_NANDF_D_5 0x170 0x450 0x000 0x2 0x0
457#define MX50_PAD_SD3_D1__SSP_D1 0x170 0x450 0x000 0x3 0x0
458#define MX50_PAD_SD3_D1__CCM_PLL2_BYP 0x170 0x450 0x000 0x7 0x0
459#define MX50_PAD_SD3_D2__ESDHC3_DAT2 0x174 0x454 0x000 0x0 0x0
460#define MX50_PAD_SD3_D2__GPIO5_22 0x174 0x454 0x000 0x1 0x0
461#define MX50_PAD_SD3_D2__EIM_NANDF_D_6 0x174 0x454 0x000 0x2 0x0
462#define MX50_PAD_SD3_D2__SSP_D2 0x174 0x454 0x000 0x3 0x0
463#define MX50_PAD_SD3_D2__CCM_PLL3_BYP 0x174 0x454 0x6e4 0x7 0x1
464#define MX50_PAD_SD3_D3__ESDHC3_DAT3 0x178 0x458 0x000 0x0 0x0
465#define MX50_PAD_SD3_D3__GPIO5_23 0x178 0x458 0x000 0x1 0x0
466#define MX50_PAD_SD3_D3__EIM_NANDF_D_7 0x178 0x458 0x000 0x2 0x0
467#define MX50_PAD_SD3_D3__SSP_D3 0x178 0x458 0x000 0x3 0x0
468#define MX50_PAD_SD3_D4__ESDHC3_DAT4 0x17c 0x45c 0x000 0x0 0x0
469#define MX50_PAD_SD3_D4__GPIO5_24 0x17c 0x45c 0x000 0x1 0x0
470#define MX50_PAD_SD3_D4__EIM_NANDF_D_0 0x17c 0x45c 0x000 0x2 0x0
471#define MX50_PAD_SD3_D4__SSP_D4 0x17c 0x45c 0x000 0x3 0x0
472#define MX50_PAD_SD3_D5__ESDHC3_DAT5 0x180 0x460 0x000 0x0 0x0
473#define MX50_PAD_SD3_D5__GPIO5_25 0x180 0x460 0x000 0x1 0x0
474#define MX50_PAD_SD3_D5__EIM_NANDF_D_1 0x180 0x460 0x000 0x2 0x0
475#define MX50_PAD_SD3_D5__SSP_D5 0x180 0x460 0x000 0x3 0x0
476#define MX50_PAD_SD3_D6__ESDHC3_DAT6 0x184 0x464 0x000 0x0 0x0
477#define MX50_PAD_SD3_D6__GPIO5_26 0x184 0x464 0x000 0x1 0x0
478#define MX50_PAD_SD3_D6__EIM_NANDF_D_2 0x184 0x464 0x000 0x2 0x0
479#define MX50_PAD_SD3_D6__SSP_D6 0x184 0x464 0x000 0x3 0x0
480#define MX50_PAD_SD3_D7__ESDHC3_DAT7 0x188 0x468 0x000 0x0 0x0
481#define MX50_PAD_SD3_D7__GPIO5_27 0x188 0x468 0x000 0x1 0x0
482#define MX50_PAD_SD3_D7__EIM_NANDF_D_3 0x188 0x468 0x000 0x2 0x0
483#define MX50_PAD_SD3_D7__SSP_D7 0x188 0x468 0x000 0x3 0x0
484#define MX50_PAD_SD3_WP__ESDHC3_WP 0x18c 0x46C 0x000 0x0 0x0
485#define MX50_PAD_SD3_WP__GPIO5_28 0x18c 0x46C 0x000 0x1 0x0
486#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN 0x18c 0x46C 0x000 0x2 0x0
487#define MX50_PAD_SD3_WP__SSP_CD 0x18c 0x46C 0x000 0x3 0x0
488#define MX50_PAD_SD3_WP__ESDHC4_LCTL 0x18c 0x46C 0x000 0x4 0x0
489#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3 0x18c 0x46C 0x000 0x5 0x0
490#define MX50_PAD_DISP_D8__ELCDIF_DAT_8 0x190 0x470 0x71c 0x0 0x0
491#define MX50_PAD_DISP_D8__GPIO2_8 0x190 0x470 0x000 0x1 0x0
492#define MX50_PAD_DISP_D8__EIM_NANDF_CLE 0x190 0x470 0x000 0x2 0x0
493#define MX50_PAD_DISP_D8__ESDHC1_LCTL 0x190 0x470 0x000 0x3 0x0
494#define MX50_PAD_DISP_D8__ESDHC4_CMD 0x190 0x470 0x74c 0x4 0x2
495#define MX50_PAD_DISP_D8__KPP_COL_4 0x190 0x470 0x790 0x5 0x1
496#define MX50_PAD_DISP_D8__FEC_TX_CLK 0x190 0x470 0x78c 0x6 0x1
497#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0 0x190 0x470 0x000 0x7 0x0
498#define MX50_PAD_DISP_D9__ELCDIF_DAT_9 0x194 0x474 0x720 0x0 0x0
499#define MX50_PAD_DISP_D9__GPIO2_9 0x194 0x474 0x000 0x1 0x0
500#define MX50_PAD_DISP_D9__EIM_NANDF_ALE 0x194 0x474 0x000 0x2 0x0
501#define MX50_PAD_DISP_D9__ESDHC2_LCTL 0x194 0x474 0x000 0x3 0x0
502#define MX50_PAD_DISP_D9__ESDHC4_CLK 0x194 0x474 0x748 0x4 0x2
503#define MX50_PAD_DISP_D9__KPP_ROW_4 0x194 0x474 0x7a0 0x5 0x1
504#define MX50_PAD_DISP_D9__FEC_RX_ER 0x194 0x474 0x788 0x6 0x1
505#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1 0x194 0x474 0x000 0x7 0x0
506#define MX50_PAD_DISP_D10__ELCDIF_DAT_10 0x198 0x478 0x724 0x0 0x0
507#define MX50_PAD_DISP_D10__GPIO2_10 0x198 0x478 0x000 0x1 0x0
508#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0 0x198 0x478 0x000 0x2 0x0
509#define MX50_PAD_DISP_D10__ESDHC3_LCTL 0x198 0x478 0x000 0x3 0x0
510#define MX50_PAD_DISP_D10__ESDHC4_DAT0 0x198 0x478 0x000 0x4 0x0
511#define MX50_PAD_DISP_D10__KPP_COL_5 0x198 0x478 0x794 0x5 0x1
512#define MX50_PAD_DISP_D10__FEC_RX_DV 0x198 0x478 0x784 0x6 0x1
513#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2 0x198 0x478 0x000 0x7 0x0
514#define MX50_PAD_DISP_D11__ELCDIF_DAT_11 0x19c 0x47c 0x728 0x0 0x0
515#define MX50_PAD_DISP_D11__GPIO2_11 0x19c 0x47c 0x000 0x1 0x0
516#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1 0x19c 0x47c 0x000 0x2 0x0
517#define MX50_PAD_DISP_D11__ESDHC4_DAT1 0x19c 0x47c 0x754 0x4 0x1
518#define MX50_PAD_DISP_D11__KPP_ROW_5 0x19c 0x47c 0x7a4 0x5 0x1
519#define MX50_PAD_DISP_D11__FEC_RDATA_1 0x19c 0x47c 0x77c 0x6 0x1
520#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3 0x19c 0x47c 0x000 0x7 0x0
521#define MX50_PAD_DISP_D12__ELCDIF_DAT_12 0x1a0 0x480 0x72c 0x0 0x0
522#define MX50_PAD_DISP_D12__GPIO2_12 0x1a0 0x480 0x000 0x1 0x0
523#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2 0x1a0 0x480 0x000 0x2 0x0
524#define MX50_PAD_DISP_D12__ESDHC1_CD 0x1a0 0x480 0x000 0x3 0x0
525#define MX50_PAD_DISP_D12__ESDHC4_DAT2 0x1a0 0x480 0x758 0x4 0x1
526#define MX50_PAD_DISP_D12__KPP_COL_6 0x1a0 0x480 0x798 0x5 0x1
527#define MX50_PAD_DISP_D12__FEC_RDATA_0 0x1a0 0x480 0x778 0x6 0x1
528#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4 0x1a0 0x480 0x000 0x7 0x0
529#define MX50_PAD_DISP_D13__ELCDIF_DAT_13 0x1a4 0x484 0x730 0x0 0x0
530#define MX50_PAD_DISP_D13__GPIO2_13 0x1a4 0x484 0x000 0x1 0x0
531#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3 0x1a4 0x484 0x000 0x2 0x0
532#define MX50_PAD_DISP_D13__ESDHC3_CD 0x1a4 0x484 0x000 0x3 0x0
533#define MX50_PAD_DISP_D13__ESDHC4_DAT3 0x1a4 0x484 0x75c 0x4 0x1
534#define MX50_PAD_DISP_D13__KPP_ROW_6 0x1a4 0x484 0x7a8 0x5 0x1
535#define MX50_PAD_DISP_D13__FEC_TX_EN 0x1a4 0x484 0x000 0x6 0x0
536#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5 0x1a4 0x484 0x000 0x7 0x0
537#define MX50_PAD_DISP_D14__ELCDIF_DAT_14 0x1a8 0x488 0x734 0x0 0x0
538#define MX50_PAD_DISP_D14__GPIO2_14 0x1a8 0x488 0x000 0x1 0x0
539#define MX50_PAD_DISP_D14__EIM_NANDF_READY0 0x1a8 0x488 0x7b4 0x2 0x1
540#define MX50_PAD_DISP_D14__ESDHC1_WP 0x1a8 0x488 0x000 0x3 0x0
541#define MX50_PAD_DISP_D14__ESDHC4_WP 0x1a8 0x488 0x000 0x4 0x0
542#define MX50_PAD_DISP_D14__KPP_COL_7 0x1a8 0x488 0x79c 0x5 0x1
543#define MX50_PAD_DISP_D14__FEC_TDATA_1 0x1a8 0x488 0x000 0x6 0x0
544#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6 0x1a8 0x488 0x000 0x7 0x0
545#define MX50_PAD_DISP_D15__ELCDIF_DAT_15 0x1ac 0x48c 0x738 0x0 0x0
546#define MX50_PAD_DISP_D15__GPIO2_15 0x1ac 0x48c 0x000 0x1 0x0
547#define MX50_PAD_DISP_D15__EIM_NANDF_DQS 0x1ac 0x48c 0x7b0 0x2 0x1
548#define MX50_PAD_DISP_D15__ESDHC3_RST 0x1ac 0x48c 0x000 0x3 0x0
549#define MX50_PAD_DISP_D15__ESDHC4_CD 0x1ac 0x48c 0x000 0x4 0x0
550#define MX50_PAD_DISP_D15__KPP_ROW_7 0x1ac 0x48c 0x7ac 0x5 0x1
551#define MX50_PAD_DISP_D15__FEC_TDATA_0 0x1ac 0x48c 0x000 0x6 0x0
552#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7 0x1ac 0x48c 0x000 0x7 0x0
553#define MX50_PAD_EPDC_D0__EPDC_SDDO_0 0x1b0 0x54c 0x000 0x0 0x0
554#define MX50_PAD_EPDC_D0__GPIO3_0 0x1b0 0x54c 0x000 0x1 0x0
555#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0 0x1b0 0x54c 0x7ec 0x2 0x1
556#define MX50_PAD_EPDC_D0__ELCDIF_RS 0x1b0 0x54c 0x000 0x3 0x0
557#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK 0x1b0 0x54c 0x000 0x4 0x0
558#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0 0x1b0 0x54c 0x000 0x6 0x0
559#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0 0x1b0 0x54c 0x000 0x7 0x0
560#define MX50_PAD_EPDC_D1__EPDC_SDDO_1 0x1b4 0x550 0x000 0x0 0x0
561#define MX50_PAD_EPDC_D1__GPIO3_1 0x1b4 0x550 0x000 0x1 0x0
562#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1 0x1b4 0x550 0x7f0 0x2 0x1
563#define MX50_PAD_EPDC_D1__ELCDIF_CS 0x1b4 0x550 0x000 0x3 0x0
564#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE 0x1b4 0x550 0x000 0x4 0x0
565#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1 0x1b4 0x550 0x000 0x6 0x0
566#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1 0x1b4 0x550 0x000 0x7 0x0
567#define MX50_PAD_EPDC_D2__EPDC_SDDO_2 0x1b8 0x554 0x000 0x0 0x0
568#define MX50_PAD_EPDC_D2__GPIO3_2 0x1b8 0x554 0x000 0x1 0x0
569#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2 0x1b8 0x554 0x7f4 0x2 0x1
570#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN 0x1b8 0x554 0x000 0x3 0x0
571#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC 0x1b8 0x554 0x73c 0x4 0x2
572#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2 0x1b8 0x554 0x000 0x6 0x0
573#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2 0x1b8 0x554 0x000 0x7 0x0
574#define MX50_PAD_EPDC_D3__EPDC_SDDO_3 0x1bc 0x558 0x000 0x0 0x0
575#define MX50_PAD_EPDC_D3__GPIO3_3 0x1bc 0x558 0x000 0x1 0x0
576#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3 0x1bc 0x558 0x7f8 0x2 0x1
577#define MX50_PAD_EPDC_D3__ELCDIF_RD_E 0x1bc 0x558 0x000 0x3 0x0
578#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC 0x1bc 0x558 0x6f8 0x4 0x3
579#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3 0x1bc 0x558 0x000 0x6 0x0
580#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3 0x1bc 0x558 0x000 0x7 0x0
581#define MX50_PAD_EPDC_D4__EPDC_SDDO_4 0x1c0 0x55c 0x000 0x0 0x0
582#define MX50_PAD_EPDC_D4__GPIO3_4 0x1c0 0x55c 0x000 0x1 0x0
583#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4 0x1c0 0x55c 0x7fc 0x2 0x1
584#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4 0x1c0 0x55c 0x000 0x6 0x0
585#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4 0x1c0 0x55c 0x000 0x7 0x0
586#define MX50_PAD_EPDC_D5__EPDC_SDDO_5 0x1c4 0x560 0x000 0x0 0x0
587#define MX50_PAD_EPDC_D5__GPIO3_5 0x1c4 0x560 0x000 0x1 0x0
588#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5 0x1c4 0x560 0x800 0x2 0x1
589#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5 0x1c4 0x560 0x000 0x6 0x0
590#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5 0x1c4 0x560 0x000 0x7 0x0
591#define MX50_PAD_EPDC_D6__EPDC_SDDO_6 0x1c8 0x564 0x000 0x0 0x0
592#define MX50_PAD_EPDC_D6__GPIO3_6 0x1c8 0x564 0x000 0x1 0x0
593#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6 0x1c8 0x564 0x804 0x2 0x1
594#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6 0x1c8 0x564 0x000 0x6 0x0
595#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6 0x1c8 0x564 0x000 0x7 0x0
596#define MX50_PAD_EPDC_D7__EPDC_SDDO_7 0x1cc 0x568 0x000 0x0 0x0
597#define MX50_PAD_EPDC_D7__GPIO3_7 0x1cc 0x568 0x000 0x1 0x0
598#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7 0x1cc 0x568 0x808 0x2 0x1
599#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7 0x1cc 0x568 0x000 0x6 0x0
600#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7 0x1cc 0x568 0x000 0x7 0x0
601#define MX50_PAD_EPDC_D8__EPDC_SDDO_8 0x1d0 0x56c 0x000 0x0 0x0
602#define MX50_PAD_EPDC_D8__GPIO3_8 0x1d0 0x56c 0x000 0x1 0x0
603#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8 0x1d0 0x56c 0x80c 0x2 0x2
604#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24 0x1d0 0x56c 0x000 0x3 0x0
605#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS 0x1d0 0x56c 0x000 0x6 0x0
606#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0 0x1d0 0x56c 0x000 0x7 0x0
607#define MX50_PAD_EPDC_D9__EPDC_SDDO_9 0x1d4 0x570 0x000 0x0 0x0
608#define MX50_PAD_EPDC_D9__GPIO3_9 0x1d4 0x570 0x000 0x1 0x0
609#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9 0x1d4 0x570 0x810 0x2 0x2
610#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25 0x1d4 0x570 0x000 0x3 0x0
611#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x1d4 0x570 0x000 0x6 0x0
612#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1 0x1d4 0x570 0x000 0x7 0x0
613#define MX50_PAD_EPDC_D10__EPDC_SDDO_10 0x1d8 0x574 0x000 0x0 0x0
614#define MX50_PAD_EPDC_D10__GPIO3_10 0x1d8 0x574 0x000 0x1 0x0
615#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10 0x1d8 0x574 0x814 0x2 0x2
616#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26 0x1d8 0x574 0x000 0x3 0x0
617#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0 0x1d8 0x574 0x000 0x6 0x0
618#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2 0x1d8 0x574 0x000 0x7 0x0
619#define MX50_PAD_EPDC_D11__EPDC_SDDO_11 0x1dc 0x578 0x000 0x0 0x0
620#define MX50_PAD_EPDC_D11__GPIO3_11 0x1dc 0x578 0x000 0x1 0x0
621#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11 0x1dc 0x578 0x818 0x2 0x2
622#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27 0x1dc 0x578 0x000 0x3 0x0
623#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1 0x1dc 0x578 0x000 0x6 0x0
624#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3 0x1dc 0x578 0x000 0x7 0x0
625#define MX50_PAD_EPDC_D12__EPDC_SDDO_12 0x1e0 0x57c 0x000 0x0 0x0
626#define MX50_PAD_EPDC_D12__GPIO3_12 0x1e0 0x57c 0x000 0x1 0x0
627#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12 0x1e0 0x57c 0x81c 0x2 0x1
628#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28 0x1e0 0x57c 0x000 0x3 0x0
629#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2 0x1e0 0x57c 0x000 0x6 0x0
630#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4 0x1e0 0x57c 0x000 0x7 0x0
631#define MX50_PAD_EPDC_D13__EPDC_SDDO_13 0x1e4 0x580 0x000 0x0 0x0
632#define MX50_PAD_EPDC_D13__GPIO3_13 0x1e4 0x580 0x000 0x1 0x0
633#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1
634#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29 0x1e4 0x580 0x000 0x3 0x0
635#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3 0x1e4 0x580 0x000 0x6 0x0
636#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5 0x1e4 0x580 0x000 0x7 0x0
637#define MX50_PAD_EPDC_D14__EPDC_SDDO_14 0x1e8 0x584 0x000 0x0 0x0
638#define MX50_PAD_EPDC_D14__GPIO3_14 0x1e8 0x584 0x000 0x1 0x0
639#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14 0x1e8 0x584 0x824 0x2 0x1
640#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30 0x1e8 0x584 0x000 0x3 0x0
641#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD 0x1e8 0x584 0x000 0x4 0x0
642#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4 0x1e8 0x584 0x000 0x6 0x0
643#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6 0x1e8 0x584 0x000 0x7 0x0
644#define MX50_PAD_EPDC_D15__EPDC_SDDO_15 0x1ec 0x588 0x000 0x0 0x0
645#define MX50_PAD_EPDC_D15__GPIO3_15 0x1ec 0x588 0x000 0x1 0x0
646#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15 0x1ec 0x588 0x828 0x2 0x1
647#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31 0x1ec 0x588 0x000 0x3 0x0
648#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC 0x1ec 0x588 0x000 0x4 0x0
649#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5 0x1ec 0x588 0x000 0x6 0x0
650#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7 0x1ec 0x588 0x000 0x7 0x0
651#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK 0x1f0 0x58c 0x000 0x0 0x0
652#define MX50_PAD_EPDC_GDCLK__GPIO3_16 0x1f0 0x58c 0x000 0x1 0x0
653#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16 0x1f0 0x58c 0x000 0x2 0x0
654#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16 0x1f0 0x58c 0x000 0x3 0x0
655#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS 0x1f0 0x58c 0x000 0x4 0x0
656#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0 0x1f0 0x58c 0x000 0x6 0x0
657#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK 0x1f0 0x58c 0x000 0x7 0x0
658#define MX50_PAD_EPDC_GDSP__EPCD_GDSP 0x1f4 0x590 0x000 0x0 0x0
659#define MX50_PAD_EPDC_GDSP__GPIO3_17 0x1f4 0x590 0x000 0x1 0x0
660#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17 0x1f4 0x590 0x000 0x2 0x0
661#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17 0x1f4 0x590 0x000 0x3 0x0
662#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD 0x1f4 0x590 0x000 0x4 0x0
663#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1 0x1f4 0x590 0x000 0x6 0x0
664#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID 0x1f4 0x590 0x000 0x7 0x0
665#define MX50_PAD_EPDC_GDOE__EPCD_GDOE 0x1f8 0x594 0x000 0x0 0x0
666#define MX50_PAD_EPDC_GDOE__GPIO3_18 0x1f8 0x594 0x000 0x1 0x0
667#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18 0x1f8 0x594 0x000 0x2 0x0
668#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18 0x1f8 0x594 0x000 0x3 0x0
669#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC 0x1f8 0x594 0x000 0x4 0x0
670#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2 0x1f8 0x594 0x000 0x6 0x0
671#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION 0x1f8 0x594 0x000 0x7 0x0
672#define MX50_PAD_EPDC_GDRL__EPCD_GDRL 0x1fc 0x598 0x000 0x0 0x0
673#define MX50_PAD_EPDC_GDRL__GPIO3_19 0x1fc 0x598 0x000 0x1 0x0
674#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19 0x1f8 0x598 0x000 0x2 0x0
675#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19 0x1fc 0x598 0x000 0x3 0x0
676#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS 0x1fc 0x598 0x000 0x4 0x0
677#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3 0x1fc 0x598 0x000 0x6 0x0
678#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG 0x1fc 0x598 0x000 0x7 0x0
679#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK 0x200 0x59c 0x000 0x0 0x0
680#define MX50_PAD_EPDC_SDCLK__GPIO3_20 0x200 0x59c 0x000 0x1 0x0
681#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20 0x200 0x59c 0x000 0x2 0x0
682#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20 0x200 0x59c 0x000 0x3 0x0
683#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD 0x200 0x59c 0x000 0x4 0x0
684#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0 0x200 0x59c 0x000 0x6 0x0
685#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT 0x200 0x59c 0x000 0x7 0x0
686#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ 0x204 0x5a0 0x000 0x0 0x0
687#define MX50_PAD_EPDC_SDOEZ__GPIO3_21 0x204 0x5a0 0x000 0x1 0x0
688#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21 0x204 0x5a0 0x000 0x2 0x0
689#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21 0x204 0x5a0 0x000 0x3 0x0
690#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC 0x204 0x5a0 0x000 0x4 0x0
691#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1 0x204 0x5a0 0x000 0x6 0x0
692#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY 0x204 0x5a0 0x000 0x7 0x0
693#define MX50_PAD_EPDC_SDOED__EPCD_SDOED 0x208 0x5a4 0x000 0x0 0x0
694#define MX50_PAD_EPDC_SDOED__GPIO3_22 0x208 0x5a4 0x000 0x1 0x0
695#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22 0x208 0x5a4 0x000 0x2 0x0
696#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22 0x208 0x5a4 0x000 0x3 0x0
697#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS 0x208 0x5a4 0x000 0x4 0x0
698#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2 0x208 0x5a4 0x000 0x6 0x0
699#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID 0x208 0x5a4 0x000 0x7 0x0
700#define MX50_PAD_EPDC_SDOE__EPCD_SDOE 0x20c 0x5a8 0x000 0x0 0x0
701#define MX50_PAD_EPDC_SDOE__GPIO3_23 0x20c 0x5a8 0x000 0x1 0x0
702#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23 0x20c 0x5a8 0x000 0x2 0x0
703#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23 0x20c 0x5a8 0x000 0x3 0x0
704#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD 0x20c 0x5a8 0x000 0x4 0x0
705#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3 0x20c 0x5a8 0x000 0x6 0x0
706#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE 0x20c 0x5a8 0x000 0x7 0x0
707#define MX50_PAD_EPDC_SDLE__EPCD_SDLE 0x210 0x5ac 0x000 0x0 0x0
708#define MX50_PAD_EPDC_SDLE__GPIO3_24 0x210 0x5ac 0x000 0x1 0x0
709#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24 0x210 0x5ac 0x000 0x2 0x0
710#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8 0x210 0x5ac 0x71c 0x3 0x1
711#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC 0x210 0x5ac 0x000 0x4 0x0
712#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4 0x210 0x5ac 0x000 0x6 0x0
713#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR 0x210 0x5ac 0x000 0x7 0x0
714#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN 0x214 0x5b0 0x000 0x0 0x0
715#define MX50_PAD_EPDC_SDCLKN__GPIO3_25 0x214 0x5b0 0x000 0x1 0x0
716#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25 0x214 0x5b0 0x000 0x2 0x0
717#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9 0x214 0x5b0 0x720 0x3 0x1
718#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS 0x214 0x5b0 0x000 0x4 0x0
719#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR 0x214 0x5b0 0x000 0x6 0x0
720#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK 0x214 0x5b0 0x000 0x7 0x0
721#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR 0x218 0x5b4 0x000 0x0 0x0
722#define MX50_PAD_EPDC_SDSHR__GPIO3_26 0x218 0x5b4 0x000 0x1 0x0
723#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26 0x218 0x5b4 0x000 0x2 0x0
724#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10 0x218 0x5b4 0x724 0x3 0x1
725#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD 0x218 0x5b4 0x6c8 0x4 0x1
726#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB 0x218 0x5b4 0x000 0x6 0x0
727#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0 0x218 0x5b4 0x000 0x7 0x0
728#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM 0x21c 0x5b8 0x000 0x0 0x0
729#define MX50_PAD_EPDC_PWRCOM__GPIO3_27 0x21c 0x5b8 0x000 0x1 0x0
730#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27 0x21c 0x5b8 0x000 0x2 0x0
731#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11 0x21c 0x5b8 0x728 0x3 0x1
732#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC 0x21c 0x5b8 0x6d4 0x4 0x1
733#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN 0x21c 0x5b8 0x000 0x6 0x0
734#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1 0x21c 0x5b8 0x000 0x7 0x0
735#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT 0x220 0x5bc 0x000 0x0 0x0
736#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0x220 0x5bc 0x000 0x1 0x0
737#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28 0x220 0x5bc 0x000 0x2 0x0
738#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12 0x220 0x5bc 0x72c 0x3 0x1
739#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS 0x220 0x5bc 0x6d8 0x4 0x1
740#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE 0x220 0x5bc 0x000 0x6 0x0
741#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID 0x220 0x5bc 0x000 0x7 0x0
742#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0 0x224 0x5c0 0x000 0x0 0x0
743#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x224 0x5c0 0x000 0x1 0x0
744#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29 0x224 0x5c0 0x000 0x2 0x0
745#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13 0x224 0x5c0 0x730 0x3 0x1
746#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD 0x224 0x5c0 0x6c4 0x4 0x1
747#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE 0x224 0x5c0 0x000 0x6 0x0
748#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID 0x224 0x5c0 0x000 0x7 0x0
749#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1 0x228 0x5c4 0x000 0x0 0x0
750#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x228 0x5c4 0x000 0x1 0x0
751#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30 0x228 0x5c4 0x000 0x2 0x0
752#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14 0x228 0x5c4 0x734 0x3 0x1
753#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC 0x228 0x5c4 0x6cc 0x4 0x1
754#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD 0x228 0x5c4 0x000 0x6 0x0
755#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST 0x228 0x5c4 0x000 0x7 0x0
756#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2 0x22c 0x5c8 0x000 0x0 0x0
757#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31 0x22c 0x5c8 0x000 0x1 0x0
758#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31 0x22c 0x5c8 0x000 0x2 0x0
759#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15 0x22c 0x5c8 0x738 0x3 0x1
760#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS 0x22c 0x5c8 0x6d0 0x4 0x1
761#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0 0x22c 0x5c8 0x7b8 0x6 0x1
762#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST 0x22c 0x5c8 0x000 0x7 0x0
763#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3 0x230 0x5cc 0x000 0x0 0x0
764#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20 0x230 0x5cc 0x000 0x1 0x0
765#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2 0x230 0x5cc 0x000 0x2 0x0
766#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1 0x230 0x5cc 0x7bc 0x6 0x1
767#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK 0x230 0x5cc 0x000 0x7 0x0
768#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0 0x234 0x5d0 0x000 0x0 0x0
769#define MX50_PAD_EPDC_VCOM0__GPIO4_21 0x234 0x5d0 0x000 0x1 0x0
770#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3 0x234 0x5d0 0x000 0x2 0x0
771#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK 0x234 0x5d0 0x000 0x7 0x0
772#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1 0x238 0x5d4 0x000 0x0 0x0
773#define MX50_PAD_EPDC_VCOM1__GPIO4_22 0x238 0x5d4 0x000 0x1 0x0
774#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3 0x238 0x5d4 0x000 0x2 0x0
775#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0 0x23c 0x5d8 0x000 0x0 0x0
776#define MX50_PAD_EPDC_BDR0__GPIO4_23 0x23c 0x5d8 0x000 0x1 0x0
777#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7 0x23c 0x5d8 0x718 0x3 0x1
778#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1 0x240 0x5dc 0x000 0x0 0x0
779#define MX50_PAD_EPDC_BDR1__GPIO4_24 0x240 0x5dc 0x000 0x1 0x0
780#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6 0x240 0x5dc 0x714 0x3 0x1
781#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0 0x244 0x5e0 0x000 0x0 0x0
782#define MX50_PAD_EPDC_SDCE0__GPIO4_25 0x244 0x5e0 0x000 0x1 0x0
783#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5 0x244 0x5e0 0x710 0x3 0x1
784#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1 0x248 0x5e4 0x000 0x0 0x0
785#define MX50_PAD_EPDC_SDCE1__GPIO4_26 0x248 0x5e4 0x000 0x1 0x0
786#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4 0x248 0x5e4 0x70c 0x3 0x0
787#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2 0x24c 0x5e8 0x000 0x0 0x0
788#define MX50_PAD_EPDC_SDCE2__GPIO4_27 0x24c 0x5e8 0x000 0x1 0x0
789#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3 0x24c 0x5e8 0x708 0x3 0x1
790#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3 0x250 0x5ec 0x000 0x0 0x0
791#define MX50_PAD_EPDC_SDCE3__GPIO4_28 0x250 0x5ec 0x000 0x1 0x0
792#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2 0x250 0x5ec 0x704 0x3 0x1
793#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4 0x254 0x5f0 0x000 0x0 0x0
794#define MX50_PAD_EPDC_SDCE4__GPIO4_29 0x254 0x5f0 0x000 0x1 0x0
795#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1 0x254 0x5f0 0x700 0x3 0x1
796#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5 0x258 0x5f4 0x000 0x0 0x0
797#define MX50_PAD_EPDC_SDCE5__GPIO4_30 0x258 0x5f4 0x000 0x1 0x0
798#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0 0x258 0x5f4 0x6fc 0x3 0x1
799#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0 0x25c 0x5f8 0x000 0x0 0x0
800#define MX50_PAD_EIM_DA0__GPIO1_0 0x25c 0x5f8 0x000 0x1 0x0
801#define MX50_PAD_EIM_DA0__KPP_COL_4 0x25c 0x5f8 0x790 0x3 0x2
802#define MX50_PAD_EIM_DA0__TPIU_TRACE_0 0x25c 0x5f8 0x000 0x6 0x0
803#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0 0x25c 0x5f8 0x000 0x7 0x0
804#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1 0x260 0x5fc 0x000 0x0 0x0
805#define MX50_PAD_EIM_DA1__GPIO1_1 0x260 0x5fc 0x000 0x1 0x0
806#define MX50_PAD_EIM_DA1__KPP_ROW_4 0x260 0x5fc 0x7a0 0x3 0x2
807#define MX50_PAD_EIM_DA1__TPIU_TRACE_1 0x260 0x5fc 0x000 0x6 0x0
808#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1 0x260 0x5fc 0x000 0x7 0x0
809#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2 0x264 0x600 0x000 0x0 0x0
810#define MX50_PAD_EIM_DA2__GPIO1_2 0x264 0x600 0x000 0x1 0x0
811#define MX50_PAD_EIM_DA2__KPP_COL_5 0x264 0x600 0x794 0x3 0x2
812#define MX50_PAD_EIM_DA2__TPIU_TRACE_2 0x264 0x600 0x000 0x6 0x0
813#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2 0x264 0x600 0x000 0x7 0x0
814#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3 0x268 0x604 0x000 0x0 0x0
815#define MX50_PAD_EIM_DA3__GPIO1_3 0x268 0x604 0x000 0x1 0x0
816#define MX50_PAD_EIM_DA3__KPP_ROW_5 0x268 0x604 0x7a4 0x3 0x2
817#define MX50_PAD_EIM_DA3__TPIU_TRACE_3 0x268 0x604 0x000 0x6 0x0
818#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3 0x268 0x604 0x000 0x7 0x0
819#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4 0x26c 0x608 0x000 0x0 0x0
820#define MX50_PAD_EIM_DA4__GPIO1_4 0x26c 0x608 0x000 0x1 0x0
821#define MX50_PAD_EIM_DA4__KPP_COL_6 0x26c 0x608 0x798 0x3 0x2
822#define MX50_PAD_EIM_DA4__TPIU_TRACE_4 0x26c 0x608 0x000 0x6 0x0
823#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4 0x26c 0x608 0x000 0x7 0x0
824#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5 0x270 0x60c 0x000 0x0 0x0
825#define MX50_PAD_EIM_DA5__GPIO1_5 0x270 0x60c 0x000 0x1 0x0
826#define MX50_PAD_EIM_DA5__KPP_ROW_6 0x270 0x60c 0x7a8 0x3 0x2
827#define MX50_PAD_EIM_DA5__TPIU_TRACE_5 0x270 0x60c 0x000 0x6 0x0
828#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5 0x270 0x60c 0x000 0x7 0x0
829#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6 0x274 0x610 0x000 0x0 0x0
830#define MX50_PAD_EIM_DA6__GPIO1_6 0x274 0x610 0x000 0x1 0x0
831#define MX50_PAD_EIM_DA6__KPP_COL_7 0x274 0x610 0x79c 0x3 0x2
832#define MX50_PAD_EIM_DA6__TPIU_TRACE_6 0x274 0x610 0x000 0x6 0x0
833#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6 0x274 0x610 0x000 0x7 0x0
834#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7 0x278 0x614 0x000 0x0 0x0
835#define MX50_PAD_EIM_DA7__GPIO1_7 0x278 0x614 0x000 0x1 0x0
836#define MX50_PAD_EIM_DA7__KPP_ROW_7 0x278 0x614 0x7ac 0x3 0x2
837#define MX50_PAD_EIM_DA7__TPIU_TRACE_7 0x278 0x614 0x000 0x6 0x0
838#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7 0x278 0x614 0x000 0x7 0x0
839#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8 0x27c 0x618 0x000 0x0 0x0
840#define MX50_PAD_EIM_DA8__GPIO1_8 0x27c 0x618 0x000 0x1 0x0
841#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE 0x27c 0x618 0x000 0x2 0x0
842#define MX50_PAD_EIM_DA8__TPIU_TRACE_8 0x27c 0x618 0x000 0x6 0x0
843#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0 0x27c 0x618 0x000 0x7 0x0
844#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9 0x280 0x61c 0x000 0x0 0x0
845#define MX50_PAD_EIM_DA9__GPIO1_9 0x280 0x61c 0x000 0x1 0x0
846#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE 0x280 0x61c 0x000 0x2 0x0
847#define MX50_PAD_EIM_DA9__TPIU_TRACE_9 0x280 0x61c 0x000 0x6 0x0
848#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1 0x280 0x61c 0x000 0x7 0x0
849#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10 0x284 0x620 0x000 0x0 0x0
850#define MX50_PAD_EIM_DA10__GPIO1_10 0x284 0x620 0x000 0x1 0x0
851#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0 0x284 0x620 0x000 0x2 0x0
852#define MX50_PAD_EIM_DA10__TPIU_TRACE_10 0x284 0x620 0x000 0x6 0x0
853#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2 0x284 0x620 0x000 0x7 0x0
854#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11 0x288 0x624 0x000 0x0 0x0
855#define MX50_PAD_EIM_DA11__GPIO1_11 0x288 0x624 0x000 0x1 0x0
856#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1 0x288 0x624 0x000 0x2 0x0
857#define MX50_PAD_EIM_DA11__TPIU_TRACE_11 0x288 0x624 0x000 0x6 0x0
858#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3 0x288 0x624 0x000 0x7 0x0
859#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12 0x28c 0x628 0x000 0x0 0x0
860#define MX50_PAD_EIM_DA12__GPIO1_12 0x28c 0x628 0x000 0x1 0x0
861#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2 0x28c 0x628 0x000 0x2 0x0
862#define MX50_PAD_EIM_DA12__EPDC_SDCE_6 0x28c 0x628 0x000 0x3 0x0
863#define MX50_PAD_EIM_DA12__TPIU_TRACE_12 0x28c 0x628 0x000 0x6 0x0
864#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4 0x28c 0x628 0x000 0x7 0x0
865#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13 0x290 0x62c 0x000 0x0 0x0
866#define MX50_PAD_EIM_DA13__GPIO1_13 0x290 0x62c 0x000 0x1 0x0
867#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3 0x290 0x62c 0x000 0x2 0x0
868#define MX50_PAD_EIM_DA13__EPDC_SDCE_7 0x290 0x62c 0x000 0x3 0x0
869#define MX50_PAD_EIM_DA13__TPIU_TRACE_13 0x290 0x62c 0x000 0x6 0x0
870#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5 0x290 0x62c 0x000 0x7 0x0
871#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14 0x294 0x630 0x000 0x0 0x0
872#define MX50_PAD_EIM_DA14__GPIO1_14 0x294 0x630 0x000 0x1 0x0
873#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0 0x294 0x630 0x7b4 0x2 0x2
874#define MX50_PAD_EIM_DA14__EPDC_SDCE_8 0x294 0x630 0x000 0x3 0x0
875#define MX50_PAD_EIM_DA14__TPIU_TRACE_14 0x294 0x630 0x000 0x6 0x0
876#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6 0x294 0x630 0x000 0x7 0x0
877#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15 0x298 0x634 0x000 0x0 0x0
878#define MX50_PAD_EIM_DA15__GPIO1_15 0x298 0x634 0x000 0x1 0x0
879#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS 0x298 0x634 0x7b0 0x2 0x2
880#define MX50_PAD_EIM_DA15__EPDC_SDCE_9 0x298 0x634 0x000 0x3 0x0
881#define MX50_PAD_EIM_DA15__TPIU_TRACE_15 0x298 0x634 0x000 0x6 0x0
882#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7 0x298 0x634 0x000 0x7 0x0
883#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2 0x29c 0x638 0x000 0x0 0x0
884#define MX50_PAD_EIM_CS2__GPIO1_16 0x29c 0x638 0x000 0x1 0x0
885#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27 0x29c 0x638 0x000 0x2 0x0
886#define MX50_PAD_EIM_CS2__TPIU_TRCLK 0x29c 0x638 0x000 0x6 0x0
887#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0 0x29c 0x638 0x000 0x7 0x0
888#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1 0x2a0 0x63c 0x000 0x0 0x0
889#define MX50_PAD_EIM_CS1__GPIO1_17 0x2a0 0x63c 0x000 0x1 0x0
890#define MX50_PAD_EIM_CS1__TPIU_TRCTL 0x2a0 0x63c 0x000 0x6 0x0
891#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1 0x2a0 0x63c 0x000 0x7 0x0
892#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0 0x2a4 0x640 0x000 0x0 0x0
893#define MX50_PAD_EIM_CS0__GPIO1_18 0x2a4 0x640 0x000 0x1 0x0
894#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2 0x2a4 0x640 0x000 0x7 0x0
895#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0 0x2a8 0x644 0x000 0x0 0x0
896#define MX50_PAD_EIM_EB0__GPIO1_19 0x2a8 0x644 0x000 0x1 0x0
897#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3 0x2a8 0x644 0x000 0x7 0x0
898#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1 0x2ac 0x648 0x000 0x0 0x0
899#define MX50_PAD_EIM_EB1__GPIO1_20 0x2ac 0x648 0x000 0x1 0x0
900#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4 0x2ac 0x648 0x000 0x7 0x0
901#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT 0x2b0 0x64c 0x000 0x0 0x0
902#define MX50_PAD_EIM_WAIT__GPIO1_21 0x2b0 0x64c 0x000 0x1 0x0
903#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B 0x2b0 0x64c 0x000 0x2 0x0
904#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5 0x2b0 0x64c 0x000 0x7 0x0
905#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK 0x2b4 0x650 0x000 0x0 0x0
906#define MX50_PAD_EIM_BCLK__GPIO1_22 0x2b4 0x650 0x000 0x1 0x0
907#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6 0x2b4 0x650 0x000 0x7 0x0
908#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY 0x2b8 0x654 0x000 0x0 0x0
909#define MX50_PAD_EIM_RDY__GPIO1_23 0x2b8 0x654 0x000 0x1 0x0
910#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7 0x2b8 0x654 0x000 0x7 0x0
911#define MX50_PAD_EIM_OE__EIM_WEIM_OE 0x2bc 0x658 0x000 0x0 0x0
912#define MX50_PAD_EIM_OE__GPIO1_24 0x2bc 0x658 0x000 0x1 0x0
913#define MX50_PAD_EIM_OE__INT_BOOT 0x2bc 0x658 0x000 0x7 0x0
914#define MX50_PAD_EIM_RW__EIM_WEIM_RW 0x2c0 0x65c 0x000 0x0 0x0
915#define MX50_PAD_EIM_RW__GPIO1_25 0x2c0 0x65c 0x000 0x1 0x0
916#define MX50_PAD_EIM_RW__SYSTEM_RST 0x2c0 0x65c 0x000 0x7 0x0
917#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA 0x2c4 0x660 0x000 0x0 0x0
918#define MX50_PAD_EIM_LBA__GPIO1_26 0x2c4 0x660 0x000 0x1 0x0
919#define MX50_PAD_EIM_LBA__TESTER_ACK 0x2c4 0x660 0x000 0x7 0x0
920#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE 0x2c8 0x664 0x000 0x0 0x0
921#define MX50_PAD_EIM_CRE__GPIO1_27 0x2c8 0x664 0x000 0x1 0x0
922
923#endif /* __DTS_IMX50_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
new file mode 100644
index 000000000000..0c75fe3deb35
--- /dev/null
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -0,0 +1,478 @@
1/*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include "skeleton.dtsi"
15#include "imx50-pinfunc.h"
16#include <dt-bindings/clock/imx5-clock.h>
17
18/ {
19 aliases {
20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
24 gpio4 = &gpio5;
25 gpio5 = &gpio6;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
30 serial4 = &uart5;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a8";
39 reg = <0x0>;
40 };
41 };
42
43 tzic: tz-interrupt-controller@0fffc000 {
44 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 reg = <0x0fffc000 0x4000>;
48 };
49
50 clocks {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 ckil {
55 compatible = "fsl,imx-ckil", "fixed-clock";
56 clock-frequency = <32768>;
57 };
58
59 ckih1 {
60 compatible = "fsl,imx-ckih1", "fixed-clock";
61 clock-frequency = <22579200>;
62 };
63
64 ckih2 {
65 compatible = "fsl,imx-ckih2", "fixed-clock";
66 clock-frequency = <0>;
67 };
68
69 osc {
70 compatible = "fsl,imx-osc", "fixed-clock";
71 clock-frequency = <24000000>;
72 };
73 };
74
75 soc {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "simple-bus";
79 interrupt-parent = <&tzic>;
80 ranges;
81
82 aips@50000000 { /* AIPS1 */
83 compatible = "fsl,aips-bus", "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 reg = <0x50000000 0x10000000>;
87 ranges;
88
89 spba@50000000 {
90 compatible = "fsl,spba-bus", "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 reg = <0x50000000 0x40000>;
94 ranges;
95
96 esdhc1: esdhc@50004000 {
97 compatible = "fsl,imx50-esdhc";
98 reg = <0x50004000 0x4000>;
99 interrupts = <1>;
100 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
101 <&clks IMX5_CLK_DUMMY>,
102 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
103 clock-names = "ipg", "ahb", "per";
104 bus-width = <4>;
105 status = "disabled";
106 };
107
108 esdhc2: esdhc@50008000 {
109 compatible = "fsl,imx50-esdhc";
110 reg = <0x50008000 0x4000>;
111 interrupts = <2>;
112 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
113 <&clks IMX5_CLK_DUMMY>,
114 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
115 clock-names = "ipg", "ahb", "per";
116 bus-width = <4>;
117 status = "disabled";
118 };
119
120 uart3: serial@5000c000 {
121 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
122 reg = <0x5000c000 0x4000>;
123 interrupts = <33>;
124 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
125 <&clks IMX5_CLK_UART3_PER_GATE>;
126 clock-names = "ipg", "per";
127 status = "disabled";
128 };
129
130 ecspi1: ecspi@50010000 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
134 reg = <0x50010000 0x4000>;
135 interrupts = <36>;
136 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
137 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
138 clock-names = "ipg", "per";
139 status = "disabled";
140 };
141
142 ssi2: ssi@50014000 {
143 compatible = "fsl,imx50-ssi",
144 "fsl,imx51-ssi",
145 "fsl,imx21-ssi";
146 reg = <0x50014000 0x4000>;
147 interrupts = <30>;
148 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
149 fsl,fifo-depth = <15>;
150 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
151 status = "disabled";
152 };
153
154 esdhc3: esdhc@50020000 {
155 compatible = "fsl,imx50-esdhc";
156 reg = <0x50020000 0x4000>;
157 interrupts = <3>;
158 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
159 <&clks IMX5_CLK_DUMMY>,
160 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
161 clock-names = "ipg", "ahb", "per";
162 bus-width = <4>;
163 status = "disabled";
164 };
165
166 esdhc4: esdhc@50024000 {
167 compatible = "fsl,imx50-esdhc";
168 reg = <0x50024000 0x4000>;
169 interrupts = <4>;
170 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
171 <&clks IMX5_CLK_DUMMY>,
172 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
173 clock-names = "ipg", "ahb", "per";
174 bus-width = <4>;
175 status = "disabled";
176 };
177 };
178
179 usbotg: usb@53f80000 {
180 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
181 reg = <0x53f80000 0x0200>;
182 interrupts = <18>;
183 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
184 status = "disabled";
185 };
186
187 usbh1: usb@53f80200 {
188 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
189 reg = <0x53f80200 0x0200>;
190 interrupts = <14>;
191 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
192 status = "disabled";
193 };
194
195 usbh2: usb@53f80400 {
196 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
197 reg = <0x53f80400 0x0200>;
198 interrupts = <16>;
199 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
200 status = "disabled";
201 };
202
203 usbh3: usb@53f80600 {
204 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
205 reg = <0x53f80600 0x0200>;
206 interrupts = <17>;
207 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
208 status = "disabled";
209 };
210
211 gpio1: gpio@53f84000 {
212 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
213 reg = <0x53f84000 0x4000>;
214 interrupts = <50 51>;
215 gpio-controller;
216 #gpio-cells = <2>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 };
220
221 gpio2: gpio@53f88000 {
222 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
223 reg = <0x53f88000 0x4000>;
224 interrupts = <52 53>;
225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
229 };
230
231 gpio3: gpio@53f8c000 {
232 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
233 reg = <0x53f8c000 0x4000>;
234 interrupts = <54 55>;
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 };
240
241 gpio4: gpio@53f90000 {
242 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
243 reg = <0x53f90000 0x4000>;
244 interrupts = <56 57>;
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 };
250
251 wdog1: wdog@53f98000 {
252 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
253 reg = <0x53f98000 0x4000>;
254 interrupts = <58>;
255 clocks = <&clks IMX5_CLK_DUMMY>;
256 };
257
258 gpt: timer@53fa0000 {
259 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
260 reg = <0x53fa0000 0x4000>;
261 interrupts = <39>;
262 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
263 <&clks IMX5_CLK_GPT_HF_GATE>;
264 clock-names = "ipg", "per";
265 };
266
267 iomuxc: iomuxc@53fa8000 {
268 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
269 reg = <0x53fa8000 0x4000>;
270 };
271
272 gpr: iomuxc-gpr@53fa8000 {
273 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
274 reg = <0x53fa8000 0xc>;
275 };
276
277 pwm1: pwm@53fb4000 {
278 #pwm-cells = <2>;
279 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
280 reg = <0x53fb4000 0x4000>;
281 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
282 <&clks IMX5_CLK_PWM1_HF_GATE>;
283 clock-names = "ipg", "per";
284 interrupts = <61>;
285 };
286
287 pwm2: pwm@53fb8000 {
288 #pwm-cells = <2>;
289 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
290 reg = <0x53fb8000 0x4000>;
291 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
292 <&clks IMX5_CLK_PWM2_HF_GATE>;
293 clock-names = "ipg", "per";
294 interrupts = <94>;
295 };
296
297 uart1: serial@53fbc000 {
298 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
299 reg = <0x53fbc000 0x4000>;
300 interrupts = <31>;
301 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
302 <&clks IMX5_CLK_UART1_PER_GATE>;
303 clock-names = "ipg", "per";
304 status = "disabled";
305 };
306
307 uart2: serial@53fc0000 {
308 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
309 reg = <0x53fc0000 0x4000>;
310 interrupts = <32>;
311 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
312 <&clks IMX5_CLK_UART2_PER_GATE>;
313 clock-names = "ipg", "per";
314 status = "disabled";
315 };
316
317 src: src@53fd0000 {
318 compatible = "fsl,imx50-src", "fsl,imx51-src";
319 reg = <0x53fd0000 0x4000>;
320 #reset-cells = <1>;
321 };
322
323 clks: ccm@53fd4000{
324 compatible = "fsl,imx50-ccm";
325 reg = <0x53fd4000 0x4000>;
326 interrupts = <0 71 0x04 0 72 0x04>;
327 #clock-cells = <1>;
328 };
329
330 gpio5: gpio@53fdc000 {
331 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
332 reg = <0x53fdc000 0x4000>;
333 interrupts = <103 104>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 };
339
340 gpio6: gpio@53fe0000 {
341 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
342 reg = <0x53fe0000 0x4000>;
343 interrupts = <105 106>;
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 };
349
350 i2c3: i2c@53fec000 {
351 #address-cells = <1>;
352 #size-cells = <0>;
353 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
354 reg = <0x53fec000 0x4000>;
355 interrupts = <64>;
356 clocks = <&clks IMX5_CLK_I2C3_GATE>;
357 status = "disabled";
358 };
359
360 uart4: serial@53ff0000 {
361 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
362 reg = <0x53ff0000 0x4000>;
363 interrupts = <13>;
364 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
365 <&clks IMX5_CLK_UART4_PER_GATE>;
366 clock-names = "ipg", "per";
367 status = "disabled";
368 };
369 };
370
371 aips@60000000 { /* AIPS2 */
372 compatible = "fsl,aips-bus", "simple-bus";
373 #address-cells = <1>;
374 #size-cells = <1>;
375 reg = <0x60000000 0x10000000>;
376 ranges;
377
378 uart5: serial@63f90000 {
379 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
380 reg = <0x63f90000 0x4000>;
381 interrupts = <86>;
382 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
383 <&clks IMX5_CLK_UART5_PER_GATE>;
384 clock-names = "ipg", "per";
385 status = "disabled";
386 };
387
388 owire: owire@63fa4000 {
389 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
390 reg = <0x63fa4000 0x4000>;
391 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
392 status = "disabled";
393 };
394
395 ecspi2: ecspi@63fac000 {
396 #address-cells = <1>;
397 #size-cells = <0>;
398 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
399 reg = <0x63fac000 0x4000>;
400 interrupts = <37>;
401 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
402 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
403 clock-names = "ipg", "per";
404 status = "disabled";
405 };
406
407 sdma: sdma@63fb0000 {
408 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
409 reg = <0x63fb0000 0x4000>;
410 interrupts = <6>;
411 clocks = <&clks IMX5_CLK_SDMA_GATE>,
412 <&clks IMX5_CLK_SDMA_GATE>;
413 clock-names = "ipg", "ahb";
414 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
415 };
416
417 cspi: cspi@63fc0000 {
418 #address-cells = <1>;
419 #size-cells = <0>;
420 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
421 reg = <0x63fc0000 0x4000>;
422 interrupts = <38>;
423 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
424 <&clks IMX5_CLK_CSPI_IPG_GATE>;
425 clock-names = "ipg", "per";
426 status = "disabled";
427 };
428
429 i2c2: i2c@63fc4000 {
430 #address-cells = <1>;
431 #size-cells = <0>;
432 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
433 reg = <0x63fc4000 0x4000>;
434 interrupts = <63>;
435 clocks = <&clks IMX5_CLK_I2C2_GATE>;
436 status = "disabled";
437 };
438
439 i2c1: i2c@63fc8000 {
440 #address-cells = <1>;
441 #size-cells = <0>;
442 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
443 reg = <0x63fc8000 0x4000>;
444 interrupts = <62>;
445 clocks = <&clks IMX5_CLK_I2C1_GATE>;
446 status = "disabled";
447 };
448
449 ssi1: ssi@63fcc000 {
450 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
451 "fsl,imx21-ssi";
452 reg = <0x63fcc000 0x4000>;
453 interrupts = <29>;
454 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
455 fsl,fifo-depth = <15>;
456 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
457 status = "disabled";
458 };
459
460 audmux: audmux@63fd0000 {
461 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
462 reg = <0x63fd0000 0x4000>;
463 status = "disabled";
464 };
465
466 fec: ethernet@63fec000 {
467 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
468 reg = <0x63fec000 0x4000>;
469 interrupts = <87>;
470 clocks = <&clks IMX5_CLK_FEC_GATE>,
471 <&clks IMX5_CLK_FEC_GATE>,
472 <&clks IMX5_CLK_FEC_GATE>;
473 clock-names = "ipg", "ahb", "ptp";
474 status = "disabled";
475 };
476 };
477 };
478};
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index b3606993f2e8..e88b2a6be079 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -34,13 +34,47 @@
34 34
35&fec { 35&fec {
36 pinctrl-names = "default"; 36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_fec_2>; 37 pinctrl-0 = <&pinctrl_fec>;
38 phy-mode = "mii"; 38 phy-mode = "mii";
39 phy-reset-gpios = <&gpio3 0 0>; 39 phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
40 phy-reset-duration = <1>; 40 phy-reset-duration = <1>;
41 status = "okay"; 41 status = "okay";
42}; 42};
43 43
44&iomuxc {
45 imx51-apf51 {
46 pinctrl_fec: fecgrp {
47 fsl,pins = <
48 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
49 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
50 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
51 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
52 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
53 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
54 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
55 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
56 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
57 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
58 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
59 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
60 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
61 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
62 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
63 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
64 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
65 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
66 >;
67 };
68
69 pinctrl_uart3: uart3grp {
70 fsl,pins = <
71 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
72 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
73 >;
74 };
75 };
76};
77
44&nfc { 78&nfc {
45 nand-bus-width = <8>; 79 nand-bus-width = <8>;
46 nand-ecc-mode = "hw"; 80 nand-ecc-mode = "hw";
@@ -50,6 +84,6 @@
50 84
51&uart3 { 85&uart3 {
52 pinctrl-names = "default"; 86 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_uart3_2>; 87 pinctrl-0 = <&pinctrl_uart3>;
54 status = "okay"; 88 status = "okay";
55}; 89};
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index 5a7f552786a1..c5a9a24c280a 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -18,10 +18,9 @@
18 18
19 display@di1 { 19 display@di1 {
20 compatible = "fsl,imx-parallel-display"; 20 compatible = "fsl,imx-parallel-display";
21 crtcs = <&ipu 0>;
22 interface-pix-fmt = "bgr666"; 21 interface-pix-fmt = "bgr666";
23 pinctrl-names = "default"; 22 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_ipu_disp1_1>; 23 pinctrl-0 = <&pinctrl_ipu_disp1>;
25 24
26 display-timings { 25 display-timings {
27 lw700 { 26 lw700 {
@@ -41,6 +40,12 @@
41 pixelclk-active = <0>; 40 pixelclk-active = <0>;
42 }; 41 };
43 }; 42 };
43
44 port {
45 display_in: endpoint {
46 remote-endpoint = <&ipu_di0_disp0>;
47 };
48 };
44 }; 49 };
45 50
46 gpio-keys { 51 gpio-keys {
@@ -48,7 +53,7 @@
48 53
49 user-key { 54 user-key {
50 label = "user"; 55 label = "user";
51 gpios = <&gpio1 3 0>; 56 gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
52 linux,code = <256>; /* BTN_0 */ 57 linux,code = <256>; /* BTN_0 */
53 }; 58 };
54 }; 59 };
@@ -58,7 +63,7 @@
58 63
59 user { 64 user {
60 label = "Heartbeat"; 65 label = "Heartbeat";
61 gpios = <&gpio1 2 0>; 66 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
62 linux,default-trigger = "heartbeat"; 67 linux,default-trigger = "heartbeat";
63 }; 68 };
64 }; 69 };
@@ -66,31 +71,33 @@
66 71
67&ecspi1 { 72&ecspi1 {
68 pinctrl-names = "default"; 73 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_ecspi1_1>; 74 pinctrl-0 = <&pinctrl_ecspi1>;
70 fsl,spi-num-chipselects = <2>; 75 fsl,spi-num-chipselects = <2>;
71 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; 76 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
77 <&gpio4 25 GPIO_ACTIVE_HIGH>;
72 status = "okay"; 78 status = "okay";
73}; 79};
74 80
75&ecspi2 { 81&ecspi2 {
76 pinctrl-names = "default"; 82 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_ecspi2_1>; 83 pinctrl-0 = <&pinctrl_ecspi2>;
78 fsl,spi-num-chipselects = <2>; 84 fsl,spi-num-chipselects = <2>;
79 cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>; 85 cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
86 <&gpio3 27 GPIO_ACTIVE_LOW>;
80 status = "okay"; 87 status = "okay";
81}; 88};
82 89
83&esdhc1 { 90&esdhc1 {
84 pinctrl-names = "default"; 91 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_esdhc1_1>; 92 pinctrl-0 = <&pinctrl_esdhc1>;
86 cd-gpios = <&gpio2 29 0>; 93 cd-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
87 bus-width = <4>; 94 bus-width = <4>;
88 status = "okay"; 95 status = "okay";
89}; 96};
90 97
91&esdhc2 { 98&esdhc2 {
92 pinctrl-names = "default"; 99 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_esdhc2_1>; 100 pinctrl-0 = <&pinctrl_esdhc2>;
94 bus-width = <4>; 101 bus-width = <4>;
95 non-removable; 102 non-removable;
96 status = "okay"; 103 status = "okay";
@@ -98,7 +105,7 @@
98 105
99&i2c2 { 106&i2c2 {
100 pinctrl-names = "default"; 107 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c2_2>; 108 pinctrl-0 = <&pinctrl_i2c2>;
102 status = "okay"; 109 status = "okay";
103}; 110};
104 111
@@ -106,7 +113,7 @@
106 pinctrl-names = "default"; 113 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_hog>; 114 pinctrl-0 = <&pinctrl_hog>;
108 115
109 hog { 116 imx51-apf51dev {
110 pinctrl_hog: hoggrp { 117 pinctrl_hog: hoggrp {
111 fsl,pins = < 118 fsl,pins = <
112 MX51_PAD_EIM_EB2__GPIO2_22 0x0C5 119 MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
@@ -120,5 +127,85 @@
120 MX51_PAD_GPIO1_3__GPIO1_3 0x0C5 127 MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
121 >; 128 >;
122 }; 129 };
130
131 pinctrl_ecspi1: ecspi1grp {
132 fsl,pins = <
133 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
134 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
135 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
136 >;
137 };
138
139 pinctrl_ecspi2: ecspi2grp {
140 fsl,pins = <
141 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
142 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
143 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
144 >;
145 };
146
147 pinctrl_esdhc1: esdhc1grp {
148 fsl,pins = <
149 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
150 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
151 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
152 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
153 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
154 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
155 >;
156 };
157
158 pinctrl_esdhc2: esdhc2grp {
159 fsl,pins = <
160 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
161 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
162 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
163 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
164 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
165 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
166 >;
167 };
168
169 pinctrl_i2c2: i2c2grp {
170 fsl,pins = <
171 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
172 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
173 >;
174 };
175
176 pinctrl_ipu_disp1: ipudisp1grp {
177 fsl,pins = <
178 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
179 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
180 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
181 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
182 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
183 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
184 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
185 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
186 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
187 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
188 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
189 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
190 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
191 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
192 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
193 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
194 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
195 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
196 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
197 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
198 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
199 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
200 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
201 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
202 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
203 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
204 >;
205 };
123 }; 206 };
124}; 207};
208
209&ipu_di0_disp0 {
210 remote-endpoint = <&display_in>;
211};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index be1407cf5abd..9e9deb244b76 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -21,12 +21,11 @@
21 reg = <0x90000000 0x20000000>; 21 reg = <0x90000000 0x20000000>;
22 }; 22 };
23 23
24 display@di0 { 24 display0: display@di0 {
25 compatible = "fsl,imx-parallel-display"; 25 compatible = "fsl,imx-parallel-display";
26 crtcs = <&ipu 0>;
27 interface-pix-fmt = "rgb24"; 26 interface-pix-fmt = "rgb24";
28 pinctrl-names = "default"; 27 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp1_1>; 28 pinctrl-0 = <&pinctrl_ipu_disp1>;
30 display-timings { 29 display-timings {
31 native-mode = <&timing0>; 30 native-mode = <&timing0>;
32 timing0: dvi { 31 timing0: dvi {
@@ -41,14 +40,19 @@
41 vsync-len = <10>; 40 vsync-len = <10>;
42 }; 41 };
43 }; 42 };
43
44 port {
45 display0_in: endpoint {
46 remote-endpoint = <&ipu_di0_disp0>;
47 };
48 };
44 }; 49 };
45 50
46 display@di1 { 51 display1: display@di1 {
47 compatible = "fsl,imx-parallel-display"; 52 compatible = "fsl,imx-parallel-display";
48 crtcs = <&ipu 1>;
49 interface-pix-fmt = "rgb565"; 53 interface-pix-fmt = "rgb565";
50 pinctrl-names = "default"; 54 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_ipu_disp2_1>; 55 pinctrl-0 = <&pinctrl_ipu_disp2>;
52 status = "disabled"; 56 status = "disabled";
53 display-timings { 57 display-timings {
54 native-mode = <&timing1>; 58 native-mode = <&timing1>;
@@ -68,6 +72,12 @@
68 pixelclk-active = <0>; 72 pixelclk-active = <0>;
69 }; 73 };
70 }; 74 };
75
76 port {
77 display1_in: endpoint {
78 remote-endpoint = <&ipu_di1_disp1>;
79 };
80 };
71 }; 81 };
72 82
73 gpio-keys { 83 gpio-keys {
@@ -75,12 +85,23 @@
75 85
76 power { 86 power {
77 label = "Power Button"; 87 label = "Power Button";
78 gpios = <&gpio2 21 0>; 88 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
79 linux,code = <116>; /* KEY_POWER */ 89 linux,code = <116>; /* KEY_POWER */
80 gpio-key,wakeup; 90 gpio-key,wakeup;
81 }; 91 };
82 }; 92 };
83 93
94 leds {
95 compatible = "gpio-leds";
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_gpio_leds>;
98
99 led-diagnostic {
100 label = "diagnostic";
101 gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
102 };
103 };
104
84 sound { 105 sound {
85 compatible = "fsl,imx51-babbage-sgtl5000", 106 compatible = "fsl,imx51-babbage-sgtl5000",
86 "fsl,imx-audio-sgtl5000"; 107 "fsl,imx-audio-sgtl5000";
@@ -105,14 +126,14 @@
105 reg=<0>; 126 reg=<0>;
106 #clock-cells = <0>; 127 #clock-cells = <0>;
107 clock-frequency = <26000000>; 128 clock-frequency = <26000000>;
108 gpios = <&gpio4 26 1>; 129 gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
109 }; 130 };
110 }; 131 };
111}; 132};
112 133
113&esdhc1 { 134&esdhc1 {
114 pinctrl-names = "default"; 135 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_esdhc1_1>; 136 pinctrl-0 = <&pinctrl_esdhc1>;
116 fsl,cd-controller; 137 fsl,cd-controller;
117 fsl,wp-controller; 138 fsl,wp-controller;
118 status = "okay"; 139 status = "okay";
@@ -120,24 +141,25 @@
120 141
121&esdhc2 { 142&esdhc2 {
122 pinctrl-names = "default"; 143 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_esdhc2_1>; 144 pinctrl-0 = <&pinctrl_esdhc2>;
124 cd-gpios = <&gpio1 6 0>; 145 cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
125 wp-gpios = <&gpio1 5 0>; 146 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
126 status = "okay"; 147 status = "okay";
127}; 148};
128 149
129&uart3 { 150&uart3 {
130 pinctrl-names = "default"; 151 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>; 152 pinctrl-0 = <&pinctrl_uart3>;
132 fsl,uart-has-rtscts; 153 fsl,uart-has-rtscts;
133 status = "okay"; 154 status = "okay";
134}; 155};
135 156
136&ecspi1 { 157&ecspi1 {
137 pinctrl-names = "default"; 158 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_ecspi1_1>; 159 pinctrl-0 = <&pinctrl_ecspi1>;
139 fsl,spi-num-chipselects = <2>; 160 fsl,spi-num-chipselects = <2>;
140 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; 161 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
162 <&gpio4 25 GPIO_ACTIVE_LOW>;
141 status = "okay"; 163 status = "okay";
142 164
143 pmic: mc13892@0 { 165 pmic: mc13892@0 {
@@ -148,7 +170,7 @@
148 spi-cs-high; 170 spi-cs-high;
149 reg = <0>; 171 reg = <0>;
150 interrupt-parent = <&gpio1>; 172 interrupt-parent = <&gpio1>;
151 interrupts = <8 0x4>; 173 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
152 174
153 regulators { 175 regulators {
154 sw1_reg: sw1 { 176 sw1_reg: sw1 {
@@ -258,6 +280,14 @@
258 }; 280 };
259}; 281};
260 282
283&ipu_di0_disp0 {
284 remote-endpoint = <&display0_in>;
285};
286
287&ipu_di1_disp1 {
288 remote-endpoint = <&display1_in>;
289};
290
261&ssi2 { 291&ssi2 {
262 fsl,mode = "i2s-slave"; 292 fsl,mode = "i2s-slave";
263 status = "okay"; 293 status = "okay";
@@ -267,7 +297,7 @@
267 pinctrl-names = "default"; 297 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_hog>; 298 pinctrl-0 = <&pinctrl_hog>;
269 299
270 hog { 300 imx51-babbage {
271 pinctrl_hog: hoggrp { 301 pinctrl_hog: hoggrp {
272 fsl,pins = < 302 fsl,pins = <
273 MX51_PAD_GPIO1_0__SD1_CD 0x20d5 303 MX51_PAD_GPIO1_0__SD1_CD 0x20d5
@@ -280,25 +310,194 @@
280 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 310 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
281 >; 311 >;
282 }; 312 };
313
314 pinctrl_audmux: audmuxgrp {
315 fsl,pins = <
316 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
317 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
318 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
319 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
320 >;
321 };
322
323 pinctrl_ecspi1: ecspi1grp {
324 fsl,pins = <
325 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
326 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
327 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
328 >;
329 };
330
331 pinctrl_esdhc1: esdhc1grp {
332 fsl,pins = <
333 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
334 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
335 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
336 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
337 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
338 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
339 >;
340 };
341
342 pinctrl_esdhc2: esdhc2grp {
343 fsl,pins = <
344 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
345 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
346 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
347 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
348 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
349 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
350 >;
351 };
352
353 pinctrl_fec: fecgrp {
354 fsl,pins = <
355 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
356 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
357 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
358 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
359 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
360 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
361 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
362 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
363 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
364 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
365 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
366 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
367 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
368 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
369 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
370 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
371 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
372 MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
373 >;
374 };
375
376 pinctrl_gpio_leds: gpioledsgrp {
377 fsl,pins = <
378 MX51_PAD_EIM_D22__GPIO2_6 0x80000000
379 >;
380 };
381
382 pinctrl_i2c2: i2c2grp {
383 fsl,pins = <
384 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
385 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
386 >;
387 };
388
389 pinctrl_ipu_disp1: ipudisp1grp {
390 fsl,pins = <
391 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
392 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
393 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
394 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
395 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
396 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
397 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
398 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
399 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
400 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
401 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
402 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
403 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
404 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
405 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
406 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
407 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
408 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
409 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
410 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
411 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
412 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
413 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
414 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
415 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
416 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
417 >;
418 };
419
420 pinctrl_ipu_disp2: ipudisp2grp {
421 fsl,pins = <
422 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
423 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
424 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
425 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
426 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
427 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
428 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
429 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
430 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
431 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
432 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
433 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
434 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
435 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
436 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
437 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
438 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
439 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
440 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
441 MX51_PAD_DI_GP4__DI2_PIN15 0x5
442 >;
443 };
444
445 pinctrl_kpp: kppgrp {
446 fsl,pins = <
447 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
448 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
449 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
450 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
451 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
452 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
453 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
454 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
455 >;
456 };
457
458 pinctrl_uart1: uart1grp {
459 fsl,pins = <
460 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
461 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
462 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
463 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
464 >;
465 };
466
467 pinctrl_uart2: uart2grp {
468 fsl,pins = <
469 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
470 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
471 >;
472 };
473
474 pinctrl_uart3: uart3grp {
475 fsl,pins = <
476 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
477 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
478 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
479 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
480 >;
481 };
283 }; 482 };
284}; 483};
285 484
286&uart1 { 485&uart1 {
287 pinctrl-names = "default"; 486 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>; 487 pinctrl-0 = <&pinctrl_uart1>;
289 fsl,uart-has-rtscts; 488 fsl,uart-has-rtscts;
290 status = "okay"; 489 status = "okay";
291}; 490};
292 491
293&uart2 { 492&uart2 {
294 pinctrl-names = "default"; 493 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_uart2_1>; 494 pinctrl-0 = <&pinctrl_uart2>;
296 status = "okay"; 495 status = "okay";
297}; 496};
298 497
299&i2c2 { 498&i2c2 {
300 pinctrl-names = "default"; 499 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_i2c2_1>; 500 pinctrl-0 = <&pinctrl_i2c2>;
302 status = "okay"; 501 status = "okay";
303 502
304 sgtl5000: codec@0a { 503 sgtl5000: codec@0a {
@@ -312,35 +511,39 @@
312 511
313&audmux { 512&audmux {
314 pinctrl-names = "default"; 513 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_audmux_1>; 514 pinctrl-0 = <&pinctrl_audmux>;
316 status = "okay"; 515 status = "okay";
317}; 516};
318 517
319&fec { 518&fec {
320 pinctrl-names = "default"; 519 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_fec_1>; 520 pinctrl-0 = <&pinctrl_fec>;
322 phy-mode = "mii"; 521 phy-mode = "mii";
522 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
523 phy-reset-duration = <1>;
323 status = "okay"; 524 status = "okay";
324}; 525};
325 526
326&kpp { 527&kpp {
327 pinctrl-names = "default"; 528 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_kpp_1>; 529 pinctrl-0 = <&pinctrl_kpp>;
329 linux,keymap = <0x00000067 /* KEY_UP */ 530 linux,keymap = <
330 0x0001006c /* KEY_DOWN */ 531 MATRIX_KEY(0, 0, KEY_UP)
331 0x00020072 /* KEY_VOLUMEDOWN */ 532 MATRIX_KEY(0, 1, KEY_DOWN)
332 0x00030066 /* KEY_HOME */ 533 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
333 0x0100006a /* KEY_RIGHT */ 534 MATRIX_KEY(0, 3, KEY_HOME)
334 0x01010069 /* KEY_LEFT */ 535 MATRIX_KEY(1, 0, KEY_RIGHT)
335 0x0102001c /* KEY_ENTER */ 536 MATRIX_KEY(1, 1, KEY_LEFT)
336 0x01030073 /* KEY_VOLUMEUP */ 537 MATRIX_KEY(1, 2, KEY_ENTER)
337 0x02000040 /* KEY_F6 */ 538 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
338 0x02010042 /* KEY_F8 */ 539 MATRIX_KEY(2, 0, KEY_F6)
339 0x02020043 /* KEY_F9 */ 540 MATRIX_KEY(2, 1, KEY_F8)
340 0x02030044 /* KEY_F10 */ 541 MATRIX_KEY(2, 2, KEY_F9)
341 0x0300003b /* KEY_F1 */ 542 MATRIX_KEY(2, 3, KEY_F10)
342 0x0301003c /* KEY_F2 */ 543 MATRIX_KEY(3, 0, KEY_F1)
343 0x0302003d /* KEY_F3 */ 544 MATRIX_KEY(3, 1, KEY_F2)
344 0x03030074>; /* KEY_POWER */ 545 MATRIX_KEY(3, 2, KEY_F3)
546 MATRIX_KEY(3, 3, KEY_POWER)
547 >;
345 status = "okay"; 548 status = "okay";
346}; 549};
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
new file mode 100644
index 000000000000..9b3acf6e4282
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
@@ -0,0 +1,93 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include "imx51.dtsi"
20
21/ {
22 model = "Eukrea CPUIMX51";
23 compatible = "eukrea,cpuimx51", "fsl,imx51";
24
25 memory {
26 reg = <0x90000000 0x10000000>; /* 256M */
27 };
28};
29
30&fec {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_fec>;
33 status = "okay";
34};
35
36&i2c1 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_i2c1>;
39 status = "okay";
40
41 pcf8563@51 {
42 compatible = "nxp,pcf8563";
43 reg = <0x51>;
44 };
45};
46
47&iomuxc {
48 imx51-eukrea {
49 pinctrl_tsc2007_1: tsc2007grp-1 {
50 fsl,pins = <
51 MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
52 MX51_PAD_NANDF_D8__GPIO4_0 0x1f5
53 >;
54 };
55
56 pinctrl_fec: fecgrp {
57 fsl,pins = <
58 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
59 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
60 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
61 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
62 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
63 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
64 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
65 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
66 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
67 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
68 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
69 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
70 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
71 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
72 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
73 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
74 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
75 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
76 >;
77 };
78
79 pinctrl_i2c1: i2c1grp {
80 fsl,pins = <
81 MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed
82 MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed
83 >;
84 };
85 };
86};
87
88&nfc {
89 nand-bus-width = <8>;
90 nand-ecc-mode = "hw";
91 nand-on-flash-bbt;
92 status = "okay";
93};
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
new file mode 100644
index 000000000000..5cec4f322096
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -0,0 +1,175 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19/dts-v1/;
20#include "imx51-eukrea-cpuimx51.dtsi"
21#include <dt-bindings/gpio/gpio.h>
22
23/ {
24 model = "Eukrea CPUIMX51";
25 compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51";
26
27 gpio_keys {
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpiokeys_1>;
31
32 button-1 {
33 label = "BP1";
34 gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
35 linux,code = <256>;
36 gpio-key,wakeup;
37 linux,input-type = <1>;
38 };
39 };
40
41 leds {
42 compatible = "gpio-leds";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_gpioled>;
45
46 led1 {
47 label = "led1";
48 gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
49 linux,default-trigger = "heartbeat";
50 };
51 };
52
53 sound {
54 compatible = "eukrea,asoc-tlv320";
55 eukrea,model = "imx51-eukrea-tlv320aic23";
56 ssi-controller = <&ssi2>;
57 fsl,mux-int-port = <2>;
58 fsl,mux-ext-port = <3>;
59 };
60};
61
62&audmux {
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_audmux>;
65 status = "okay";
66};
67
68&esdhc1 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>;
71 fsl,cd-controller;
72 status = "okay";
73};
74
75&i2c1 {
76 tlv320aic23: codec@1a {
77 compatible = "ti,tlv320aic23";
78 reg = <0x1a>;
79 };
80};
81
82&iomuxc {
83 imx51-eukrea {
84 pinctrl_audmux: audmuxgrp {
85 fsl,pins = <
86 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
87 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
88 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
89 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
90 >;
91 };
92
93 pinctrl_esdhc1: esdhc1grp {
94 fsl,pins = <
95 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
96 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
97 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
98 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
99 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
100 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
101 >;
102 };
103
104 pinctrl_uart1: uart1grp {
105 fsl,pins = <
106 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
107 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
108 >;
109 };
110
111 pinctrl_uart3: uart3grp {
112 fsl,pins = <
113 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
114 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
115 >;
116 };
117
118 pinctrl_uart3_rtscts: uart3rtsctsgrp {
119 fsl,pins = <
120 MX51_PAD_KEY_COL4__UART3_RTS 0x1c5
121 MX51_PAD_KEY_COL5__UART3_CTS 0x1c5
122 >;
123 };
124
125 pinctrl_backlight_1: backlightgrp-1 {
126 fsl,pins = <
127 MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5
128 >;
129 };
130
131 pinctrl_esdhc1_cd: esdhc1_cd {
132 fsl,pins = <
133 MX51_PAD_GPIO1_0__SD1_CD 0x20d5
134 >;
135 };
136
137 pinctrl_gpiokeys_1: gpiokeysgrp-1 {
138 fsl,pins = <
139 MX51_PAD_NANDF_D9__GPIO3_31 0x1f5
140 >;
141 };
142
143 pinctrl_gpioled: gpioledgrp-1 {
144 fsl,pins = <
145 MX51_PAD_NANDF_D10__GPIO3_30 0x80000000
146 >;
147 };
148
149 pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
150 fsl,pins = <
151 MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
152 >;
153 };
154 };
155};
156
157&ssi2 {
158 codec-handle = <&tlv320aic23>;
159 fsl,mode = "i2s-slave";
160 status = "okay";
161};
162
163&uart1 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_uart1>;
166 fsl,uart-has-rtscts;
167 status = "okay";
168};
169
170&uart3 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
173 fsl,uart-has-rtscts;
174 status = "okay";
175};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 4bcdd3ad15e5..5f8216d08f6b 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -12,6 +12,10 @@
12 12
13#include "skeleton.dtsi" 13#include "skeleton.dtsi"
14#include "imx51-pinfunc.h" 14#include "imx51-pinfunc.h"
15#include <dt-bindings/clock/imx5-clock.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include <dt-bindings/interrupt-controller/irq.h>
15 19
16/ { 20/ {
17 aliases { 21 aliases {
@@ -21,6 +25,10 @@
21 gpio3 = &gpio4; 25 gpio3 = &gpio4;
22 i2c0 = &i2c1; 26 i2c0 = &i2c1;
23 i2c1 = &i2c2; 27 i2c1 = &i2c2;
28 mmc0 = &esdhc1;
29 mmc1 = &esdhc2;
30 mmc2 = &esdhc3;
31 mmc3 = &esdhc4;
24 serial0 = &uart1; 32 serial0 = &uart1;
25 serial1 = &uart2; 33 serial1 = &uart2;
26 serial2 = &uart3; 34 serial2 = &uart3;
@@ -64,21 +72,40 @@
64 cpus { 72 cpus {
65 #address-cells = <1>; 73 #address-cells = <1>;
66 #size-cells = <0>; 74 #size-cells = <0>;
67 cpu@0 { 75 cpu: cpu@0 {
68 device_type = "cpu"; 76 device_type = "cpu";
69 compatible = "arm,cortex-a8"; 77 compatible = "arm,cortex-a8";
70 reg = <0>; 78 reg = <0>;
71 clock-latency = <61036>; /* two CLK32 periods */ 79 clock-latency = <62500>;
72 clocks = <&clks 24>; 80 clocks = <&clks IMX5_CLK_CPU_PODF>;
73 clock-names = "cpu"; 81 clock-names = "cpu";
74 operating-points = < 82 operating-points = <
75 /* kHz uV (No regulator support) */ 83 166000 1000000
76 160000 0 84 600000 1050000
77 800000 0 85 800000 1100000
78 >; 86 >;
87 voltage-tolerance = <5>;
79 }; 88 };
80 }; 89 };
81 90
91 usbphy {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 compatible = "simple-bus";
95
96 usbphy0: usbphy@0 {
97 compatible = "usb-nop-xceiv";
98 reg = <0>;
99 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
100 clock-names = "main_clk";
101 };
102 };
103
104 display-subsystem {
105 compatible = "fsl,imx-display-subsystem";
106 ports = <&ipu_di0>, <&ipu_di1>;
107 };
108
82 soc { 109 soc {
83 #address-cells = <1>; 110 #address-cells = <1>;
84 #size-cells = <1>; 111 #size-cells = <1>;
@@ -92,13 +119,30 @@
92 }; 119 };
93 120
94 ipu: ipu@40000000 { 121 ipu: ipu@40000000 {
95 #crtc-cells = <1>; 122 #address-cells = <1>;
123 #size-cells = <0>;
96 compatible = "fsl,imx51-ipu"; 124 compatible = "fsl,imx51-ipu";
97 reg = <0x40000000 0x20000000>; 125 reg = <0x40000000 0x20000000>;
98 interrupts = <11 10>; 126 interrupts = <11 10>;
99 clocks = <&clks 59>, <&clks 110>, <&clks 61>; 127 clocks = <&clks IMX5_CLK_IPU_GATE>,
128 <&clks IMX5_CLK_IPU_DI0_GATE>,
129 <&clks IMX5_CLK_IPU_DI1_GATE>;
100 clock-names = "bus", "di0", "di1"; 130 clock-names = "bus", "di0", "di1";
101 resets = <&src 2>; 131 resets = <&src 2>;
132
133 ipu_di0: port@2 {
134 reg = <2>;
135
136 ipu_di0_disp0: endpoint {
137 };
138 };
139
140 ipu_di1: port@3 {
141 reg = <3>;
142
143 ipu_di1_disp1: endpoint {
144 };
145 };
102 }; 146 };
103 147
104 aips@70000000 { /* AIPS1 */ 148 aips@70000000 { /* AIPS1 */
@@ -119,7 +163,9 @@
119 compatible = "fsl,imx51-esdhc"; 163 compatible = "fsl,imx51-esdhc";
120 reg = <0x70004000 0x4000>; 164 reg = <0x70004000 0x4000>;
121 interrupts = <1>; 165 interrupts = <1>;
122 clocks = <&clks 44>, <&clks 0>, <&clks 71>; 166 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
167 <&clks IMX5_CLK_DUMMY>,
168 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
123 clock-names = "ipg", "ahb", "per"; 169 clock-names = "ipg", "ahb", "per";
124 status = "disabled"; 170 status = "disabled";
125 }; 171 };
@@ -128,7 +174,9 @@
128 compatible = "fsl,imx51-esdhc"; 174 compatible = "fsl,imx51-esdhc";
129 reg = <0x70008000 0x4000>; 175 reg = <0x70008000 0x4000>;
130 interrupts = <2>; 176 interrupts = <2>;
131 clocks = <&clks 45>, <&clks 0>, <&clks 72>; 177 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
178 <&clks IMX5_CLK_DUMMY>,
179 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
132 clock-names = "ipg", "ahb", "per"; 180 clock-names = "ipg", "ahb", "per";
133 bus-width = <4>; 181 bus-width = <4>;
134 status = "disabled"; 182 status = "disabled";
@@ -138,7 +186,8 @@
138 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 186 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
139 reg = <0x7000c000 0x4000>; 187 reg = <0x7000c000 0x4000>;
140 interrupts = <33>; 188 interrupts = <33>;
141 clocks = <&clks 32>, <&clks 33>; 189 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
190 <&clks IMX5_CLK_UART3_PER_GATE>;
142 clock-names = "ipg", "per"; 191 clock-names = "ipg", "per";
143 status = "disabled"; 192 status = "disabled";
144 }; 193 };
@@ -149,7 +198,8 @@
149 compatible = "fsl,imx51-ecspi"; 198 compatible = "fsl,imx51-ecspi";
150 reg = <0x70010000 0x4000>; 199 reg = <0x70010000 0x4000>;
151 interrupts = <36>; 200 interrupts = <36>;
152 clocks = <&clks 51>, <&clks 52>; 201 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
202 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
153 clock-names = "ipg", "per"; 203 clock-names = "ipg", "per";
154 status = "disabled"; 204 status = "disabled";
155 }; 205 };
@@ -158,7 +208,7 @@
158 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 208 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
159 reg = <0x70014000 0x4000>; 209 reg = <0x70014000 0x4000>;
160 interrupts = <30>; 210 interrupts = <30>;
161 clocks = <&clks 49>; 211 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
162 dmas = <&sdma 24 1 0>, 212 dmas = <&sdma 24 1 0>,
163 <&sdma 25 1 0>; 213 <&sdma 25 1 0>;
164 dma-names = "rx", "tx"; 214 dma-names = "rx", "tx";
@@ -171,7 +221,9 @@
171 compatible = "fsl,imx51-esdhc"; 221 compatible = "fsl,imx51-esdhc";
172 reg = <0x70020000 0x4000>; 222 reg = <0x70020000 0x4000>;
173 interrupts = <3>; 223 interrupts = <3>;
174 clocks = <&clks 46>, <&clks 0>, <&clks 73>; 224 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
225 <&clks IMX5_CLK_DUMMY>,
226 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
175 clock-names = "ipg", "ahb", "per"; 227 clock-names = "ipg", "ahb", "per";
176 bus-width = <4>; 228 bus-width = <4>;
177 status = "disabled"; 229 status = "disabled";
@@ -181,25 +233,20 @@
181 compatible = "fsl,imx51-esdhc"; 233 compatible = "fsl,imx51-esdhc";
182 reg = <0x70024000 0x4000>; 234 reg = <0x70024000 0x4000>;
183 interrupts = <4>; 235 interrupts = <4>;
184 clocks = <&clks 47>, <&clks 0>, <&clks 74>; 236 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
237 <&clks IMX5_CLK_DUMMY>,
238 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
185 clock-names = "ipg", "ahb", "per"; 239 clock-names = "ipg", "ahb", "per";
186 bus-width = <4>; 240 bus-width = <4>;
187 status = "disabled"; 241 status = "disabled";
188 }; 242 };
189 }; 243 };
190 244
191 usbphy0: usbphy@0 {
192 compatible = "usb-nop-xceiv";
193 clocks = <&clks 75>;
194 clock-names = "main_clk";
195 status = "okay";
196 };
197
198 usbotg: usb@73f80000 { 245 usbotg: usb@73f80000 {
199 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 246 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
200 reg = <0x73f80000 0x0200>; 247 reg = <0x73f80000 0x0200>;
201 interrupts = <18>; 248 interrupts = <18>;
202 clocks = <&clks 108>; 249 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
203 fsl,usbmisc = <&usbmisc 0>; 250 fsl,usbmisc = <&usbmisc 0>;
204 fsl,usbphy = <&usbphy0>; 251 fsl,usbphy = <&usbphy0>;
205 status = "disabled"; 252 status = "disabled";
@@ -209,7 +256,7 @@
209 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 256 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
210 reg = <0x73f80200 0x0200>; 257 reg = <0x73f80200 0x0200>;
211 interrupts = <14>; 258 interrupts = <14>;
212 clocks = <&clks 108>; 259 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
213 fsl,usbmisc = <&usbmisc 1>; 260 fsl,usbmisc = <&usbmisc 1>;
214 status = "disabled"; 261 status = "disabled";
215 }; 262 };
@@ -218,7 +265,7 @@
218 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 265 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
219 reg = <0x73f80400 0x0200>; 266 reg = <0x73f80400 0x0200>;
220 interrupts = <16>; 267 interrupts = <16>;
221 clocks = <&clks 108>; 268 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
222 fsl,usbmisc = <&usbmisc 2>; 269 fsl,usbmisc = <&usbmisc 2>;
223 status = "disabled"; 270 status = "disabled";
224 }; 271 };
@@ -227,7 +274,7 @@
227 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 274 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
228 reg = <0x73f80600 0x0200>; 275 reg = <0x73f80600 0x0200>;
229 interrupts = <17>; 276 interrupts = <17>;
230 clocks = <&clks 108>; 277 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
231 fsl,usbmisc = <&usbmisc 3>; 278 fsl,usbmisc = <&usbmisc 3>;
232 status = "disabled"; 279 status = "disabled";
233 }; 280 };
@@ -236,7 +283,7 @@
236 #index-cells = <1>; 283 #index-cells = <1>;
237 compatible = "fsl,imx51-usbmisc"; 284 compatible = "fsl,imx51-usbmisc";
238 reg = <0x73f80800 0x200>; 285 reg = <0x73f80800 0x200>;
239 clocks = <&clks 108>; 286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
240 }; 287 };
241 288
242 gpio1: gpio@73f84000 { 289 gpio1: gpio@73f84000 {
@@ -283,7 +330,7 @@
283 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; 330 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
284 reg = <0x73f94000 0x4000>; 331 reg = <0x73f94000 0x4000>;
285 interrupts = <60>; 332 interrupts = <60>;
286 clocks = <&clks 0>; 333 clocks = <&clks IMX5_CLK_DUMMY>;
287 status = "disabled"; 334 status = "disabled";
288 }; 335 };
289 336
@@ -291,14 +338,14 @@
291 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 338 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
292 reg = <0x73f98000 0x4000>; 339 reg = <0x73f98000 0x4000>;
293 interrupts = <58>; 340 interrupts = <58>;
294 clocks = <&clks 0>; 341 clocks = <&clks IMX5_CLK_DUMMY>;
295 }; 342 };
296 343
297 wdog2: wdog@73f9c000 { 344 wdog2: wdog@73f9c000 {
298 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 345 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
299 reg = <0x73f9c000 0x4000>; 346 reg = <0x73f9c000 0x4000>;
300 interrupts = <59>; 347 interrupts = <59>;
301 clocks = <&clks 0>; 348 clocks = <&clks IMX5_CLK_DUMMY>;
302 status = "disabled"; 349 status = "disabled";
303 }; 350 };
304 351
@@ -306,7 +353,8 @@
306 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; 353 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
307 reg = <0x73fa0000 0x4000>; 354 reg = <0x73fa0000 0x4000>;
308 interrupts = <39>; 355 interrupts = <39>;
309 clocks = <&clks 36>, <&clks 41>; 356 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
357 <&clks IMX5_CLK_GPT_HF_GATE>;
310 clock-names = "ipg", "per"; 358 clock-names = "ipg", "per";
311 }; 359 };
312 360
@@ -319,7 +367,8 @@
319 #pwm-cells = <2>; 367 #pwm-cells = <2>;
320 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 368 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
321 reg = <0x73fb4000 0x4000>; 369 reg = <0x73fb4000 0x4000>;
322 clocks = <&clks 37>, <&clks 38>; 370 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
371 <&clks IMX5_CLK_PWM1_HF_GATE>;
323 clock-names = "ipg", "per"; 372 clock-names = "ipg", "per";
324 interrupts = <61>; 373 interrupts = <61>;
325 }; 374 };
@@ -328,7 +377,8 @@
328 #pwm-cells = <2>; 377 #pwm-cells = <2>;
329 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 378 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
330 reg = <0x73fb8000 0x4000>; 379 reg = <0x73fb8000 0x4000>;
331 clocks = <&clks 39>, <&clks 40>; 380 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
381 <&clks IMX5_CLK_PWM2_HF_GATE>;
332 clock-names = "ipg", "per"; 382 clock-names = "ipg", "per";
333 interrupts = <94>; 383 interrupts = <94>;
334 }; 384 };
@@ -337,7 +387,8 @@
337 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 387 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
338 reg = <0x73fbc000 0x4000>; 388 reg = <0x73fbc000 0x4000>;
339 interrupts = <31>; 389 interrupts = <31>;
340 clocks = <&clks 28>, <&clks 29>; 390 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
391 <&clks IMX5_CLK_UART1_PER_GATE>;
341 clock-names = "ipg", "per"; 392 clock-names = "ipg", "per";
342 status = "disabled"; 393 status = "disabled";
343 }; 394 };
@@ -346,7 +397,8 @@
346 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 397 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
347 reg = <0x73fc0000 0x4000>; 398 reg = <0x73fc0000 0x4000>;
348 interrupts = <32>; 399 interrupts = <32>;
349 clocks = <&clks 30>, <&clks 31>; 400 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
401 <&clks IMX5_CLK_UART2_PER_GATE>;
350 clock-names = "ipg", "per"; 402 clock-names = "ipg", "per";
351 status = "disabled"; 403 status = "disabled";
352 }; 404 };
@@ -376,14 +428,14 @@
376 compatible = "fsl,imx51-iim", "fsl,imx27-iim"; 428 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
377 reg = <0x83f98000 0x4000>; 429 reg = <0x83f98000 0x4000>;
378 interrupts = <69>; 430 interrupts = <69>;
379 clocks = <&clks 107>; 431 clocks = <&clks IMX5_CLK_IIM_GATE>;
380 }; 432 };
381 433
382 owire: owire@83fa4000 { 434 owire: owire@83fa4000 {
383 compatible = "fsl,imx51-owire", "fsl,imx21-owire"; 435 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
384 reg = <0x83fa4000 0x4000>; 436 reg = <0x83fa4000 0x4000>;
385 interrupts = <88>; 437 interrupts = <88>;
386 clocks = <&clks 159>; 438 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
387 status = "disabled"; 439 status = "disabled";
388 }; 440 };
389 441
@@ -393,7 +445,8 @@
393 compatible = "fsl,imx51-ecspi"; 445 compatible = "fsl,imx51-ecspi";
394 reg = <0x83fac000 0x4000>; 446 reg = <0x83fac000 0x4000>;
395 interrupts = <37>; 447 interrupts = <37>;
396 clocks = <&clks 53>, <&clks 54>; 448 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
449 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
397 clock-names = "ipg", "per"; 450 clock-names = "ipg", "per";
398 status = "disabled"; 451 status = "disabled";
399 }; 452 };
@@ -402,7 +455,8 @@
402 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 455 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
403 reg = <0x83fb0000 0x4000>; 456 reg = <0x83fb0000 0x4000>;
404 interrupts = <6>; 457 interrupts = <6>;
405 clocks = <&clks 56>, <&clks 56>; 458 clocks = <&clks IMX5_CLK_SDMA_GATE>,
459 <&clks IMX5_CLK_SDMA_GATE>;
406 clock-names = "ipg", "ahb"; 460 clock-names = "ipg", "ahb";
407 #dma-cells = <3>; 461 #dma-cells = <3>;
408 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 462 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
@@ -414,7 +468,8 @@
414 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 468 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
415 reg = <0x83fc0000 0x4000>; 469 reg = <0x83fc0000 0x4000>;
416 interrupts = <38>; 470 interrupts = <38>;
417 clocks = <&clks 55>, <&clks 55>; 471 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
472 <&clks IMX5_CLK_CSPI_IPG_GATE>;
418 clock-names = "ipg", "per"; 473 clock-names = "ipg", "per";
419 status = "disabled"; 474 status = "disabled";
420 }; 475 };
@@ -425,7 +480,7 @@
425 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 480 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
426 reg = <0x83fc4000 0x4000>; 481 reg = <0x83fc4000 0x4000>;
427 interrupts = <63>; 482 interrupts = <63>;
428 clocks = <&clks 35>; 483 clocks = <&clks IMX5_CLK_I2C2_GATE>;
429 status = "disabled"; 484 status = "disabled";
430 }; 485 };
431 486
@@ -435,7 +490,7 @@
435 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 490 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
436 reg = <0x83fc8000 0x4000>; 491 reg = <0x83fc8000 0x4000>;
437 interrupts = <62>; 492 interrupts = <62>;
438 clocks = <&clks 34>; 493 clocks = <&clks IMX5_CLK_I2C1_GATE>;
439 status = "disabled"; 494 status = "disabled";
440 }; 495 };
441 496
@@ -443,7 +498,7 @@
443 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 498 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
444 reg = <0x83fcc000 0x4000>; 499 reg = <0x83fcc000 0x4000>;
445 interrupts = <29>; 500 interrupts = <29>;
446 clocks = <&clks 48>; 501 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
447 dmas = <&sdma 28 0 0>, 502 dmas = <&sdma 28 0 0>,
448 <&sdma 29 0 0>; 503 <&sdma 29 0 0>;
449 dma-names = "rx", "tx"; 504 dma-names = "rx", "tx";
@@ -455,6 +510,8 @@
455 audmux: audmux@83fd0000 { 510 audmux: audmux@83fd0000 {
456 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; 511 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
457 reg = <0x83fd0000 0x4000>; 512 reg = <0x83fd0000 0x4000>;
513 clocks = <&clks IMX5_CLK_DUMMY>;
514 clock-names = "audmux";
458 status = "disabled"; 515 status = "disabled";
459 }; 516 };
460 517
@@ -463,7 +520,7 @@
463 #size-cells = <1>; 520 #size-cells = <1>;
464 compatible = "fsl,imx51-weim"; 521 compatible = "fsl,imx51-weim";
465 reg = <0x83fda000 0x1000>; 522 reg = <0x83fda000 0x1000>;
466 clocks = <&clks 57>; 523 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
467 ranges = < 524 ranges = <
468 0 0 0xb0000000 0x08000000 525 0 0 0xb0000000 0x08000000
469 1 0 0xb8000000 0x08000000 526 1 0 0xb8000000 0x08000000
@@ -479,7 +536,7 @@
479 compatible = "fsl,imx51-nand"; 536 compatible = "fsl,imx51-nand";
480 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 537 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
481 interrupts = <8>; 538 interrupts = <8>;
482 clocks = <&clks 60>; 539 clocks = <&clks IMX5_CLK_NFC_GATE>;
483 status = "disabled"; 540 status = "disabled";
484 }; 541 };
485 542
@@ -487,7 +544,7 @@
487 compatible = "fsl,imx51-pata", "fsl,imx27-pata"; 544 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
488 reg = <0x83fe0000 0x4000>; 545 reg = <0x83fe0000 0x4000>;
489 interrupts = <70>; 546 interrupts = <70>;
490 clocks = <&clks 172>; 547 clocks = <&clks IMX5_CLK_PATA_GATE>;
491 status = "disabled"; 548 status = "disabled";
492 }; 549 };
493 550
@@ -495,7 +552,7 @@
495 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 552 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
496 reg = <0x83fe8000 0x4000>; 553 reg = <0x83fe8000 0x4000>;
497 interrupts = <96>; 554 interrupts = <96>;
498 clocks = <&clks 50>; 555 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
499 dmas = <&sdma 46 0 0>, 556 dmas = <&sdma 46 0 0>,
500 <&sdma 47 0 0>; 557 <&sdma 47 0 0>;
501 dma-names = "rx", "tx"; 558 dma-names = "rx", "tx";
@@ -508,336 +565,12 @@
508 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 565 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
509 reg = <0x83fec000 0x4000>; 566 reg = <0x83fec000 0x4000>;
510 interrupts = <87>; 567 interrupts = <87>;
511 clocks = <&clks 42>, <&clks 42>, <&clks 42>; 568 clocks = <&clks IMX5_CLK_FEC_GATE>,
569 <&clks IMX5_CLK_FEC_GATE>,
570 <&clks IMX5_CLK_FEC_GATE>;
512 clock-names = "ipg", "ahb", "ptp"; 571 clock-names = "ipg", "ahb", "ptp";
513 status = "disabled"; 572 status = "disabled";
514 }; 573 };
515 }; 574 };
516 }; 575 };
517}; 576};
518
519&iomuxc {
520 audmux {
521 pinctrl_audmux_1: audmuxgrp-1 {
522 fsl,pins = <
523 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
524 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
525 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
526 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
527 >;
528 };
529 };
530
531 fec {
532 pinctrl_fec_1: fecgrp-1 {
533 fsl,pins = <
534 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
535 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
536 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
537 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
538 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
539 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
540 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
541 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
542 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
543 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
544 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
545 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
546 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
547 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
548 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
549 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
550 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
551 >;
552 };
553
554 pinctrl_fec_2: fecgrp-2 {
555 fsl,pins = <
556 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
557 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
558 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
559 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
560 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
561 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
562 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
563 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
564 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
565 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
566 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
567 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
568 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
569 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
570 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
571 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
572 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
573 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
574 >;
575 };
576 };
577
578 ecspi1 {
579 pinctrl_ecspi1_1: ecspi1grp-1 {
580 fsl,pins = <
581 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
582 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
583 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
584 >;
585 };
586 };
587
588 ecspi2 {
589 pinctrl_ecspi2_1: ecspi2grp-1 {
590 fsl,pins = <
591 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
592 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
593 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
594 >;
595 };
596 };
597
598 esdhc1 {
599 pinctrl_esdhc1_1: esdhc1grp-1 {
600 fsl,pins = <
601 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
602 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
603 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
604 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
605 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
606 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
607 >;
608 };
609 };
610
611 esdhc2 {
612 pinctrl_esdhc2_1: esdhc2grp-1 {
613 fsl,pins = <
614 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
615 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
616 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
617 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
618 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
619 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
620 >;
621 };
622 };
623
624 i2c2 {
625 pinctrl_i2c2_1: i2c2grp-1 {
626 fsl,pins = <
627 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
628 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
629 >;
630 };
631
632 pinctrl_i2c2_2: i2c2grp-2 {
633 fsl,pins = <
634 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
635 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
636 >;
637 };
638
639 pinctrl_i2c2_3: i2c2grp-3 {
640 fsl,pins = <
641 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
642 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
643 >;
644 };
645 };
646
647 ipu_disp1 {
648 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
649 fsl,pins = <
650 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
651 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
652 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
653 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
654 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
655 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
656 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
657 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
658 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
659 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
660 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
661 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
662 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
663 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
664 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
665 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
666 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
667 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
668 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
669 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
670 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
671 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
672 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
673 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
674 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
675 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
676 >;
677 };
678 };
679
680 ipu_disp2 {
681 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
682 fsl,pins = <
683 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
684 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
685 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
686 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
687 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
688 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
689 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
690 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
691 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
692 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
693 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
694 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
695 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
696 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
697 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
698 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
699 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
700 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
701 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
702 MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
703 >;
704 };
705 };
706
707 kpp {
708 pinctrl_kpp_1: kppgrp-1 {
709 fsl,pins = <
710 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
711 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
712 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
713 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
714 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
715 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
716 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
717 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
718 >;
719 };
720 };
721
722 pata {
723 pinctrl_pata_1: patagrp-1 {
724 fsl,pins = <
725 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
726 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
727 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
728 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
729 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
730 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
731 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
732 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
733 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
734 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
735 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
736 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
737 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
738 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
739 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
740 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
741 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
742 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
743 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
744 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
745 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
746 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
747 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
748 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
749 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
750 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
751 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
752 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
753 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
754 >;
755 };
756 };
757
758 uart1 {
759 pinctrl_uart1_1: uart1grp-1 {
760 fsl,pins = <
761 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
762 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
763 >;
764 };
765
766 pinctrl_uart1_rtscts_1: uart1rtscts-1 {
767 fsl,pins = <
768 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
769 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
770 >;
771 };
772 };
773
774 uart2 {
775 pinctrl_uart2_1: uart2grp-1 {
776 fsl,pins = <
777 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
778 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
779 >;
780 };
781 };
782
783 uart3 {
784 pinctrl_uart3_1: uart3grp-1 {
785 fsl,pins = <
786 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
787 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
788 >;
789 };
790
791 pinctrl_uart3_rtscts_1: uart3rtscts-1 {
792 fsl,pins = <
793 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
794 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
795 >;
796 };
797
798 pinctrl_uart3_2: uart3grp-2 {
799 fsl,pins = <
800 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
801 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
802 >;
803 };
804 };
805
806 usbh1 {
807 pinctrl_usbh1_1: usbh1grp-1 {
808 fsl,pins = <
809 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
810 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
811 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
812 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
813 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
814 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
815 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
816 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
817 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
818 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
819 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
820 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
821 >;
822 };
823 };
824
825 usbh2 {
826 pinctrl_usbh2_1: usbh2grp-1 {
827 fsl,pins = <
828 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
829 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
830 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
831 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
832 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
833 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
834 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
835 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
836 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
837 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
838 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
839 MX51_PAD_EIM_A26__USBH2_STP 0x1e5
840 >;
841 };
842 };
843};
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 174f86938c89..e9337ad52f59 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -49,9 +49,12 @@
49 49
50 regulators { 50 regulators {
51 compatible = "simple-bus"; 51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <0>;
52 54
53 reg_3p3v: 3p3v { 55 reg_3p3v: regulator@0 {
54 compatible = "regulator-fixed"; 56 compatible = "regulator-fixed";
57 reg = <0>;
55 regulator-name = "3P3V"; 58 regulator-name = "3P3V";
56 regulator-min-microvolt = <3300000>; 59 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>;
@@ -99,7 +102,7 @@
99 102
100&esdhc1 { 103&esdhc1 {
101 pinctrl-names = "default"; 104 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_esdhc1_2>; 105 pinctrl-0 = <&pinctrl_esdhc1>;
103 cd-gpios = <&gpio1 1 0>; 106 cd-gpios = <&gpio1 1 0>;
104 wp-gpios = <&gpio1 9 0>; 107 wp-gpios = <&gpio1 9 0>;
105 status = "okay"; 108 status = "okay";
@@ -109,7 +112,7 @@
109 pinctrl-names = "default"; 112 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_hog>; 113 pinctrl-0 = <&pinctrl_hog>;
111 114
112 hog { 115 imx53-ard {
113 pinctrl_hog: hoggrp { 116 pinctrl_hog: hoggrp {
114 fsl,pins = < 117 fsl,pins = <
115 MX53_PAD_GPIO_1__GPIO1_1 0x80000000 118 MX53_PAD_GPIO_1__GPIO1_1 0x80000000
@@ -148,11 +151,33 @@
148 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 151 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
149 >; 152 >;
150 }; 153 };
154
155 pinctrl_esdhc1: esdhc1grp {
156 fsl,pins = <
157 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
158 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
159 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
160 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
161 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
162 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
163 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
164 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
165 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
166 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
167 >;
168 };
169
170 pinctrl_uart1: uart1grp {
171 fsl,pins = <
172 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
173 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
174 >;
175 };
151 }; 176 };
152}; 177};
153 178
154&uart1 { 179&uart1 {
155 pinctrl-names = "default"; 180 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_uart1_2>; 181 pinctrl-0 = <&pinctrl_uart1>;
157 status = "okay"; 182 status = "okay";
158}; 183};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
deleted file mode 100644
index 801fda728ed6..000000000000
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14#include "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Evaluation Kit";
18 compatible = "fsl,imx53-evk", "fsl,imx53";
19
20 memory {
21 reg = <0x70000000 0x80000000>;
22 };
23
24 leds {
25 compatible = "gpio-leds";
26
27 green {
28 label = "Heartbeat";
29 gpios = <&gpio7 7 0>;
30 linux,default-trigger = "heartbeat";
31 };
32 };
33};
34
35&esdhc1 {
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc1_1>;
38 cd-gpios = <&gpio3 13 0>;
39 wp-gpios = <&gpio3 14 0>;
40 status = "okay";
41};
42
43&ecspi1 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_ecspi1_1>;
46 fsl,spi-num-chipselects = <2>;
47 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
48 status = "okay";
49
50 flash: at45db321d@1 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
54 spi-max-frequency = <25000000>;
55 reg = <1>;
56
57 partition@0 {
58 label = "U-Boot";
59 reg = <0x0 0x40000>;
60 read-only;
61 };
62
63 partition@40000 {
64 label = "Kernel";
65 reg = <0x40000 0x3c0000>;
66 };
67 };
68};
69
70&esdhc3 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_esdhc3_1>;
73 cd-gpios = <&gpio3 11 0>;
74 wp-gpios = <&gpio3 12 0>;
75 status = "okay";
76};
77
78&iomuxc {
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_hog>;
81
82 hog {
83 pinctrl_hog: hoggrp {
84 fsl,pins = <
85 MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
86 MX53_PAD_EIM_D19__GPIO3_19 0x80000000
87 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
88 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
89 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
90 MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
91 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
92 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
93 >;
94 };
95 };
96};
97
98&uart1 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_uart1_1>;
101 status = "okay";
102};
103
104&i2c2 {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_i2c2_1>;
107 status = "okay";
108
109 pmic: mc13892@08 {
110 compatible = "fsl,mc13892", "fsl,mc13xxx";
111 reg = <0x08>;
112 };
113
114 codec: sgtl5000@0a {
115 compatible = "fsl,sgtl5000";
116 reg = <0x0a>;
117 };
118};
119
120&fec {
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_fec_1>;
123 phy-mode = "rmii";
124 phy-reset-gpios = <&gpio7 6 0>;
125 status = "okay";
126};
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index 7d304d02ed38..f6d3ac3e5587 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -21,12 +21,11 @@
21 }; 21 };
22 22
23 soc { 23 soc {
24 display@di1 { 24 display1: display@di1 {
25 compatible = "fsl,imx-parallel-display"; 25 compatible = "fsl,imx-parallel-display";
26 crtcs = <&ipu 1>;
27 interface-pix-fmt = "bgr666"; 26 interface-pix-fmt = "bgr666";
28 pinctrl-names = "default"; 27 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp2_1>; 28 pinctrl-0 = <&pinctrl_ipu_disp1>;
30 29
31 display-timings { 30 display-timings {
32 800x480p60 { 31 800x480p60 {
@@ -44,6 +43,12 @@
44 }; 43 };
45 }; 44 };
46 }; 45 };
46
47 port {
48 display1_in: endpoint {
49 remote-endpoint = <&ipu_di1_disp1>;
50 };
51 };
47 }; 52 };
48 53
49 backlight { 54 backlight {
@@ -51,6 +56,7 @@
51 pwms = <&pwm1 0 3000>; 56 pwms = <&pwm1 0 3000>;
52 brightness-levels = <0 4 8 16 32 64 128 255>; 57 brightness-levels = <0 4 8 16 32 64 128 255>;
53 default-brightness-level = <6>; 58 default-brightness-level = <6>;
59 power-supply = <&reg_backlight>;
54 }; 60 };
55 61
56 leds { 62 leds {
@@ -73,14 +79,36 @@
73 79
74 regulators { 80 regulators {
75 compatible = "simple-bus"; 81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <0>;
76 84
77 reg_3p2v: 3p2v { 85 reg_3p2v: regulator@0 {
78 compatible = "regulator-fixed"; 86 compatible = "regulator-fixed";
87 reg = <0>;
79 regulator-name = "3P2V"; 88 regulator-name = "3P2V";
80 regulator-min-microvolt = <3200000>; 89 regulator-min-microvolt = <3200000>;
81 regulator-max-microvolt = <3200000>; 90 regulator-max-microvolt = <3200000>;
82 regulator-always-on; 91 regulator-always-on;
83 }; 92 };
93
94
95 reg_backlight: regulator@1 {
96 compatible = "regulator-fixed";
97 reg = <1>;
98 regulator-name = "lcd-supply";
99 regulator-min-microvolt = <3200000>;
100 regulator-max-microvolt = <3200000>;
101 regulator-always-on;
102 };
103
104 reg_usbh1_vbus: regulator@3 {
105 compatible = "regulator-fixed";
106 reg = <3>;
107 regulator-name = "vbus";
108 regulator-min-microvolt = <5000000>;
109 regulator-max-microvolt = <5000000>;
110 gpio = <&gpio1 2 0>;
111 };
84 }; 112 };
85 113
86 sound { 114 sound {
@@ -102,25 +130,25 @@
102 130
103&audmux { 131&audmux {
104 pinctrl-names = "default"; 132 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_audmux_2>; 133 pinctrl-0 = <&pinctrl_audmux>;
106 status = "okay"; 134 status = "okay";
107}; 135};
108 136
109&can1 { 137&can1 {
110 pinctrl-names = "default"; 138 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_can1_3>; 139 pinctrl-0 = <&pinctrl_can1>;
112 status = "okay"; 140 status = "okay";
113}; 141};
114 142
115&can2 { 143&can2 {
116 pinctrl-names = "default"; 144 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_can2_1>; 145 pinctrl-0 = <&pinctrl_can2>;
118 status = "okay"; 146 status = "okay";
119}; 147};
120 148
121&esdhc1 { 149&esdhc1 {
122 pinctrl-names = "default"; 150 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_esdhc1_1>; 151 pinctrl-0 = <&pinctrl_esdhc1>;
124 cd-gpios = <&gpio1 1 0>; 152 cd-gpios = <&gpio1 1 0>;
125 wp-gpios = <&gpio1 9 0>; 153 wp-gpios = <&gpio1 9 0>;
126 status = "okay"; 154 status = "okay";
@@ -128,14 +156,14 @@
128 156
129&fec { 157&fec {
130 pinctrl-names = "default"; 158 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_fec_1>; 159 pinctrl-0 = <&pinctrl_fec>;
132 phy-mode = "rmii"; 160 phy-mode = "rmii";
133 status = "okay"; 161 status = "okay";
134}; 162};
135 163
136&i2c1 { 164&i2c1 {
137 pinctrl-names = "default"; 165 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c1_2>; 166 pinctrl-0 = <&pinctrl_i2c1>;
139 status = "okay"; 167 status = "okay";
140 168
141 sgtl5000: codec@0a { 169 sgtl5000: codec@0a {
@@ -143,13 +171,13 @@
143 reg = <0x0a>; 171 reg = <0x0a>;
144 VDDA-supply = <&reg_3p2v>; 172 VDDA-supply = <&reg_3p2v>;
145 VDDIO-supply = <&reg_3p2v>; 173 VDDIO-supply = <&reg_3p2v>;
146 clocks = <&clks 150>; 174 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
147 }; 175 };
148}; 176};
149 177
150&i2c2 { 178&i2c2 {
151 pinctrl-names = "default"; 179 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_i2c2_2>; 180 pinctrl-0 = <&pinctrl_i2c2>;
153 clock-frequency = <400000>; 181 clock-frequency = <400000>;
154 status = "okay"; 182 status = "okay";
155 183
@@ -193,7 +221,7 @@
193 221
194&i2c3 { 222&i2c3 {
195 pinctrl-names = "default"; 223 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_i2c3_1>; 224 pinctrl-0 = <&pinctrl_i2c3>;
197 status = "okay"; 225 status = "okay";
198}; 226};
199 227
@@ -201,14 +229,14 @@
201 pinctrl-names = "default"; 229 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_hog>; 230 pinctrl-0 = <&pinctrl_hog>;
203 231
204 hog { 232 imx53-m53evk {
205 pinctrl_hog: hoggrp { 233 pinctrl_hog: hoggrp {
206 fsl,pins = < 234 fsl,pins = <
207 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 235 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
208 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 236 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
209 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 237 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
210 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 238 MX53_PAD_GPIO_2__GPIO1_2 0x80000000
211 239 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
212 >; 240 >;
213 }; 241 };
214 242
@@ -218,12 +246,172 @@
218 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 246 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
219 >; 247 >;
220 }; 248 };
249
250 pinctrl_audmux: audmuxgrp {
251 fsl,pins = <
252 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
253 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
254 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
255 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
256 >;
257 };
258
259 pinctrl_can1: can1grp {
260 fsl,pins = <
261 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
262 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
263 >;
264 };
265
266 pinctrl_can2: can2grp {
267 fsl,pins = <
268 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
269 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
270 >;
271 };
272
273 pinctrl_esdhc1: esdhc1grp {
274 fsl,pins = <
275 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
276 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
277 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
278 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
279 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
280 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
281 >;
282 };
283
284 pinctrl_fec: fecgrp {
285 fsl,pins = <
286 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
287 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
288 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
289 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
290 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
291 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
292 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
293 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
294 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
295 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
296 >;
297 };
298
299 pinctrl_i2c1: i2c1grp {
300 fsl,pins = <
301 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
302 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
303 >;
304 };
305
306 pinctrl_i2c2: i2c2grp {
307 fsl,pins = <
308 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
309 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
310 >;
311 };
312
313 pinctrl_i2c3: i2c3grp {
314 fsl,pins = <
315 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
316 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
317 >;
318 };
319
320 pinctrl_ipu_disp1: ipudisp1grp {
321 fsl,pins = <
322 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
323 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
324 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
325 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
326 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
327 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
328 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
329 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
330 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
331 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
332 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
333 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
334 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
335 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
336 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
337 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
338 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
339 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
340 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
341 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
342 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
343 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
344 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
345 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
346 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
347 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
348 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
349 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
350 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
351 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
352 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
353 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
354 >;
355 };
356
357 pinctrl_nand: nandgrp {
358 fsl,pins = <
359 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
360 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
361 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
362 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
363 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
364 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
365 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
366 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
367 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
368 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
369 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
370 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
371 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
372 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
373 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
374 >;
375 };
376
377 pinctrl_pwm1: pwm1grp {
378 fsl,pins = <
379 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
380 >;
381 };
382
383 pinctrl_uart1: uart1grp {
384 fsl,pins = <
385 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
386 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
387 >;
388 };
389
390 pinctrl_uart2: uart2grp {
391 fsl,pins = <
392 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
393 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
394 >;
395 };
396
397 pinctrl_uart3: uart3grp {
398 fsl,pins = <
399 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
400 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
401 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
402 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
403 >;
404 };
221 }; 405 };
222}; 406};
223 407
408&ipu_di1_disp1 {
409 remote-endpoint = <&display1_in>;
410};
411
224&nfc { 412&nfc {
225 pinctrl-names = "default"; 413 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_nand_1>; 414 pinctrl-0 = <&pinctrl_nand>;
227 nand-bus-width = <8>; 415 nand-bus-width = <8>;
228 nand-ecc-mode = "hw"; 416 nand-ecc-mode = "hw";
229 status = "okay"; 417 status = "okay";
@@ -231,7 +419,11 @@
231 419
232&pwm1 { 420&pwm1 {
233 pinctrl-names = "default"; 421 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_pwm1_1>; 422 pinctrl-0 = <&pinctrl_pwm1>;
423 status = "okay";
424};
425
426&sata {
235 status = "okay"; 427 status = "okay";
236}; 428};
237 429
@@ -242,18 +434,29 @@
242 434
243&uart1 { 435&uart1 {
244 pinctrl-names = "default"; 436 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_uart1_2>; 437 pinctrl-0 = <&pinctrl_uart1>;
246 status = "okay"; 438 status = "okay";
247}; 439};
248 440
249&uart2 { 441&uart2 {
250 pinctrl-names = "default"; 442 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_uart2_1>; 443 pinctrl-0 = <&pinctrl_uart2>;
252 status = "okay"; 444 status = "okay";
253}; 445};
254 446
255&uart3 { 447&uart3 {
256 pinctrl-names = "default"; 448 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_uart3_1>; 449 pinctrl-0 = <&pinctrl_uart3>;
450 status = "okay";
451};
452
453&usbh1 {
454 vbus-supply = <&reg_usbh1_vbus>;
455 phy_type = "utmi";
456 status = "okay";
457};
458
459&usbotg {
460 dr_mode = "peripheral";
258 status = "okay"; 461 status = "okay";
259}; 462};
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index a63090267941..7c8c12969892 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -17,14 +17,6 @@
17 model = "TQ MBa53 starter kit"; 17 model = "TQ MBa53 starter kit";
18 compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; 18 compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
19 19
20 reg_backlight: fixed@0 {
21 compatible = "regulator-fixed";
22 regulator-name = "lcd-supply";
23 gpio = <&gpio2 5 0>;
24 startup-delay-us = <5000>;
25 enable-active-low;
26 };
27
28 backlight { 20 backlight {
29 compatible = "pwm-backlight"; 21 compatible = "pwm-backlight";
30 pwms = <&pwm2 0 50000>; 22 pwms = <&pwm2 0 50000>;
@@ -38,17 +30,37 @@
38 compatible = "fsl,imx-parallel-display"; 30 compatible = "fsl,imx-parallel-display";
39 pinctrl-names = "default"; 31 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_disp1_1>; 32 pinctrl-0 = <&pinctrl_disp1_1>;
41 crtcs = <&ipu 1>;
42 interface-pix-fmt = "rgb24"; 33 interface-pix-fmt = "rgb24";
43 status = "disabled"; 34 status = "disabled";
35
36 port {
37 display1_in: endpoint {
38 remote-endpoint = <&ipu_di1_disp1>;
39 };
40 };
44 }; 41 };
45 42
46 reg_3p2v: 3p2v { 43 regulators {
47 compatible = "regulator-fixed"; 44 compatible = "simple-bus";
48 regulator-name = "3P2V"; 45 #address-cells = <1>;
49 regulator-min-microvolt = <3200000>; 46 #size-cells = <0>;
50 regulator-max-microvolt = <3200000>; 47
51 regulator-always-on; 48 reg_backlight: regulator@0 {
49 compatible = "regulator-fixed";
50 reg = <0>;
51 regulator-name = "lcd-supply";
52 gpio = <&gpio2 5 0>;
53 startup-delay-us = <5000>;
54 };
55
56 reg_3p2v: regulator@1 {
57 compatible = "regulator-fixed";
58 reg = <1>;
59 regulator-name = "3P2V";
60 regulator-min-microvolt = <3200000>;
61 regulator-max-microvolt = <3200000>;
62 regulator-always-on;
63 };
52 }; 64 };
53 65
54 sound { 66 sound {
@@ -141,6 +153,10 @@
141 }; 153 };
142}; 154};
143 155
156&ipu_di1_disp1 {
157 remote-endpoint = <&display1_in>;
158};
159
144&cspi { 160&cspi {
145 status = "okay"; 161 status = "okay";
146}; 162};
@@ -148,14 +164,14 @@
148&audmux { 164&audmux {
149 status = "okay"; 165 status = "okay";
150 pinctrl-names = "default"; 166 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_audmux_1>; 167 pinctrl-0 = <&pinctrl_audmux>;
152}; 168};
153 169
154&i2c2 { 170&i2c2 {
155 codec: sgtl5000@a { 171 codec: sgtl5000@a {
156 compatible = "fsl,sgtl5000"; 172 compatible = "fsl,sgtl5000";
157 reg = <0x0a>; 173 reg = <0x0a>;
158 clocks = <&clks 150>; 174 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
159 VDDA-supply = <&reg_3p2v>; 175 VDDA-supply = <&reg_3p2v>;
160 VDDIO-supply = <&reg_3p2v>; 176 VDDIO-supply = <&reg_3p2v>;
161 }; 177 };
@@ -228,7 +244,7 @@
228&tve { 244&tve {
229 pinctrl-names = "default"; 245 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_vga_sync_1>; 246 pinctrl-0 = <&pinctrl_vga_sync_1>;
231 ddc = <&i2c3>; 247 i2c-ddc-bus = <&i2c3>;
232 fsl,tve-mode = "vga"; 248 fsl,tve-mode = "vga";
233 fsl,hsync-pin = <4>; 249 fsl,hsync-pin = <4>;
234 fsl,vsync-pin = <6>; 250 fsl,vsync-pin = <6>;
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
new file mode 100644
index 000000000000..3f825a6813da
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -0,0 +1,345 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include "imx53.dtsi"
14
15/ {
16 memory {
17 reg = <0x70000000 0x40000000>;
18 };
19
20 display0: display@di0 {
21 compatible = "fsl,imx-parallel-display";
22 interface-pix-fmt = "rgb565";
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_ipu_disp0>;
25 status = "disabled";
26 display-timings {
27 claawvga {
28 native-mode;
29 clock-frequency = <27000000>;
30 hactive = <800>;
31 vactive = <480>;
32 hback-porch = <40>;
33 hfront-porch = <60>;
34 vback-porch = <10>;
35 vfront-porch = <10>;
36 hsync-len = <20>;
37 vsync-len = <10>;
38 hsync-active = <0>;
39 vsync-active = <0>;
40 de-active = <1>;
41 pixelclk-active = <0>;
42 };
43 };
44
45 port {
46 display0_in: endpoint {
47 remote-endpoint = <&ipu_di0_disp0>;
48 };
49 };
50 };
51
52 gpio-keys {
53 compatible = "gpio-keys";
54
55 power {
56 label = "Power Button";
57 gpios = <&gpio1 8 0>;
58 linux,code = <116>; /* KEY_POWER */
59 };
60
61 volume-up {
62 label = "Volume Up";
63 gpios = <&gpio2 14 0>;
64 linux,code = <115>; /* KEY_VOLUMEUP */
65 gpio-key,wakeup;
66 };
67
68 volume-down {
69 label = "Volume Down";
70 gpios = <&gpio2 15 0>;
71 linux,code = <114>; /* KEY_VOLUMEDOWN */
72 gpio-key,wakeup;
73 };
74 };
75
76 leds {
77 compatible = "gpio-leds";
78 pinctrl-names = "default";
79 pinctrl-0 = <&led_pin_gpio7_7>;
80
81 user {
82 label = "Heartbeat";
83 gpios = <&gpio7 7 0>;
84 linux,default-trigger = "heartbeat";
85 };
86 };
87
88 regulators {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <0>;
92
93 reg_3p2v: regulator@0 {
94 compatible = "regulator-fixed";
95 reg = <0>;
96 regulator-name = "3P2V";
97 regulator-min-microvolt = <3200000>;
98 regulator-max-microvolt = <3200000>;
99 regulator-always-on;
100 };
101
102 reg_usb_vbus: regulator@1 {
103 compatible = "regulator-fixed";
104 reg = <1>;
105 regulator-name = "usb_vbus";
106 regulator-min-microvolt = <5000000>;
107 regulator-max-microvolt = <5000000>;
108 gpio = <&gpio7 8 0>;
109 enable-active-high;
110 };
111 };
112
113 sound {
114 compatible = "fsl,imx53-qsb-sgtl5000",
115 "fsl,imx-audio-sgtl5000";
116 model = "imx53-qsb-sgtl5000";
117 ssi-controller = <&ssi2>;
118 audio-codec = <&sgtl5000>;
119 audio-routing =
120 "MIC_IN", "Mic Jack",
121 "Mic Jack", "Mic Bias",
122 "Headphone Jack", "HP_OUT";
123 mux-int-port = <2>;
124 mux-ext-port = <5>;
125 };
126};
127
128&esdhc1 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_esdhc1>;
131 status = "okay";
132};
133
134&ipu_di0_disp0 {
135 remote-endpoint = <&display0_in>;
136};
137
138&ssi2 {
139 fsl,mode = "i2s-slave";
140 status = "okay";
141};
142
143&esdhc3 {
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_esdhc3>;
146 cd-gpios = <&gpio3 11 0>;
147 wp-gpios = <&gpio3 12 0>;
148 bus-width = <8>;
149 status = "okay";
150};
151
152&iomuxc {
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_hog>;
155
156 imx53-qsb {
157 pinctrl_hog: hoggrp {
158 fsl,pins = <
159 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
160 MX53_PAD_GPIO_8__GPIO1_8 0x80000000
161 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
162 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
163 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
164 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
165 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
166 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
167 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
168 >;
169 };
170
171 led_pin_gpio7_7: led_gpio7_7@0 {
172 fsl,pins = <
173 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
174 >;
175 };
176
177 pinctrl_audmux: audmuxgrp {
178 fsl,pins = <
179 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
180 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
181 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
182 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
183 >;
184 };
185
186 pinctrl_esdhc1: esdhc1grp {
187 fsl,pins = <
188 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
189 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
190 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
191 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
192 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
193 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
194 >;
195 };
196
197 pinctrl_esdhc3: esdhc3grp {
198 fsl,pins = <
199 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
200 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
201 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
202 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
203 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
204 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
205 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
206 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
207 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
208 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
209 >;
210 };
211
212 pinctrl_fec: fecgrp {
213 fsl,pins = <
214 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
215 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
216 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
217 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
218 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
219 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
220 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
221 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
222 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
223 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
224 >;
225 };
226
227 pinctrl_i2c1: i2c1grp {
228 fsl,pins = <
229 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
230 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
231 >;
232 };
233
234 pinctrl_i2c2: i2c2grp {
235 fsl,pins = <
236 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
237 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
238 >;
239 };
240
241 pinctrl_ipu_disp0: ipudisp0grp {
242 fsl,pins = <
243 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
244 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
245 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
246 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
247 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
248 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
249 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
250 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
251 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
252 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
253 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
254 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
255 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
256 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
257 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
258 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
259 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
260 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
261 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
262 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
263 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
264 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
265 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
266 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
267 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
268 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
269 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
270 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
271 >;
272 };
273
274 pinctrl_uart1: uart1grp {
275 fsl,pins = <
276 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
277 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
278 >;
279 };
280 };
281};
282
283&uart1 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_uart1>;
286 status = "okay";
287};
288
289&i2c2 {
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_i2c2>;
292 status = "okay";
293
294 sgtl5000: codec@0a {
295 compatible = "fsl,sgtl5000";
296 reg = <0x0a>;
297 VDDA-supply = <&reg_3p2v>;
298 VDDIO-supply = <&reg_3p2v>;
299 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
300 };
301};
302
303&i2c1 {
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_i2c1>;
306 status = "okay";
307
308 accelerometer: mma8450@1c {
309 compatible = "fsl,mma8450";
310 reg = <0x1c>;
311 };
312};
313
314&audmux {
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_audmux>;
317 status = "okay";
318};
319
320&fec {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_fec>;
323 phy-mode = "rmii";
324 phy-reset-gpios = <&gpio7 6 0>;
325 status = "okay";
326};
327
328&sata {
329 status = "okay";
330};
331
332&vpu {
333 status = "okay";
334};
335
336&usbh1 {
337 vbus-supply = <&reg_usb_vbus>;
338 phy_type = "utmi";
339 status = "okay";
340};
341
342&usbotg {
343 dr_mode = "peripheral";
344 status = "okay";
345};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 91a5935a4aac..dec4b073ceb1 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -11,193 +11,14 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14#include "imx53.dtsi" 14#include "imx53-qsb-common.dtsi"
15 15
16/ { 16/ {
17 model = "Freescale i.MX53 Quick Start Board"; 17 model = "Freescale i.MX53 Quick Start Board";
18 compatible = "fsl,imx53-qsb", "fsl,imx53"; 18 compatible = "fsl,imx53-qsb", "fsl,imx53";
19
20 memory {
21 reg = <0x70000000 0x40000000>;
22 };
23
24 display@di0 {
25 compatible = "fsl,imx-parallel-display";
26 crtcs = <&ipu 0>;
27 interface-pix-fmt = "rgb565";
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp0_1>;
30 status = "disabled";
31 display-timings {
32 claawvga {
33 native-mode;
34 clock-frequency = <27000000>;
35 hactive = <800>;
36 vactive = <480>;
37 hback-porch = <40>;
38 hfront-porch = <60>;
39 vback-porch = <10>;
40 vfront-porch = <10>;
41 hsync-len = <20>;
42 vsync-len = <10>;
43 hsync-active = <0>;
44 vsync-active = <0>;
45 de-active = <1>;
46 pixelclk-active = <0>;
47 };
48 };
49 };
50
51 gpio-keys {
52 compatible = "gpio-keys";
53
54 power {
55 label = "Power Button";
56 gpios = <&gpio1 8 0>;
57 linux,code = <116>; /* KEY_POWER */
58 };
59
60 volume-up {
61 label = "Volume Up";
62 gpios = <&gpio2 14 0>;
63 linux,code = <115>; /* KEY_VOLUMEUP */
64 gpio-key,wakeup;
65 };
66
67 volume-down {
68 label = "Volume Down";
69 gpios = <&gpio2 15 0>;
70 linux,code = <114>; /* KEY_VOLUMEDOWN */
71 gpio-key,wakeup;
72 };
73 };
74
75 leds {
76 compatible = "gpio-leds";
77 pinctrl-names = "default";
78 pinctrl-0 = <&led_pin_gpio7_7>;
79
80 user {
81 label = "Heartbeat";
82 gpios = <&gpio7 7 0>;
83 linux,default-trigger = "heartbeat";
84 };
85 };
86
87 regulators {
88 compatible = "simple-bus";
89
90 reg_3p2v: 3p2v {
91 compatible = "regulator-fixed";
92 regulator-name = "3P2V";
93 regulator-min-microvolt = <3200000>;
94 regulator-max-microvolt = <3200000>;
95 regulator-always-on;
96 };
97
98 reg_usb_vbus: usb_vbus {
99 compatible = "regulator-fixed";
100 regulator-name = "usb_vbus";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 gpio = <&gpio7 8 0>;
104 enable-active-high;
105 };
106 };
107
108 sound {
109 compatible = "fsl,imx53-qsb-sgtl5000",
110 "fsl,imx-audio-sgtl5000";
111 model = "imx53-qsb-sgtl5000";
112 ssi-controller = <&ssi2>;
113 audio-codec = <&sgtl5000>;
114 audio-routing =
115 "MIC_IN", "Mic Jack",
116 "Mic Jack", "Mic Bias",
117 "Headphone Jack", "HP_OUT";
118 mux-int-port = <2>;
119 mux-ext-port = <5>;
120 };
121};
122
123&esdhc1 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_esdhc1_1>;
126 status = "okay";
127};
128
129&ssi2 {
130 fsl,mode = "i2s-slave";
131 status = "okay";
132};
133
134&esdhc3 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_esdhc3_1>;
137 cd-gpios = <&gpio3 11 0>;
138 wp-gpios = <&gpio3 12 0>;
139 bus-width = <8>;
140 status = "okay";
141};
142
143&iomuxc {
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_hog>;
146
147 hog {
148 pinctrl_hog: hoggrp {
149 fsl,pins = <
150 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
151 MX53_PAD_GPIO_8__GPIO1_8 0x80000000
152 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
153 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
154 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
155 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
156 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
157 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
158 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
159 >;
160 };
161
162 led_pin_gpio7_7: led_gpio7_7@0 {
163 fsl,pins = <
164 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
165 >;
166 };
167 };
168
169};
170
171&uart1 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_uart1_1>;
174 status = "okay";
175};
176
177&i2c2 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c2_1>;
180 status = "okay";
181
182 sgtl5000: codec@0a {
183 compatible = "fsl,sgtl5000";
184 reg = <0x0a>;
185 VDDA-supply = <&reg_3p2v>;
186 VDDIO-supply = <&reg_3p2v>;
187 clocks = <&clks 150>;
188 };
189}; 19};
190 20
191&i2c1 { 21&i2c1 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_i2c1_1>;
194 status = "okay";
195
196 accelerometer: mma8450@1c {
197 compatible = "fsl,mma8450";
198 reg = <0x1c>;
199 };
200
201 pmic: dialog@48 { 22 pmic: dialog@48 {
202 compatible = "dlg,da9053-aa", "dlg,da9052"; 23 compatible = "dlg,da9053-aa", "dlg,da9052";
203 reg = <0x48>; 24 reg = <0x48>;
@@ -292,32 +113,3 @@
292 }; 113 };
293 }; 114 };
294}; 115};
295
296&audmux {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_audmux_1>;
299 status = "okay";
300};
301
302&fec {
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_fec_1>;
305 phy-mode = "rmii";
306 phy-reset-gpios = <&gpio7 6 0>;
307 status = "okay";
308};
309
310&vpu {
311 status = "okay";
312};
313
314&usbh1 {
315 vbus-supply = <&reg_usb_vbus>;
316 phy_type = "utmi";
317 status = "okay";
318};
319
320&usbotg {
321 dr_mode = "peripheral";
322 status = "okay";
323};
diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts
new file mode 100644
index 000000000000..f1bbf9a32991
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@@ -0,0 +1,158 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14
15#include "imx53-qsb-common.dtsi"
16
17/ {
18 model = "Freescale i.MX53 Quick Start-R Board";
19 compatible = "fsl,imx53-qsrb", "fsl,imx53";
20};
21
22&iomuxc {
23 i2c1 {
24 /* open drain */
25 pinctrl_i2c1_qsrb: i2c1grp-1 {
26 fsl,pins = <
27 MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
28 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
29 >;
30 };
31 };
32};
33
34&i2c1 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_i2c1_qsrb>;
37 status = "okay";
38
39 pmic: mc34708@8 {
40 compatible = "fsl,mc34708";
41 reg = <0x08>;
42 interrupt-parent = <&gpio5>;
43 interrupts = <23 0x8>;
44 regulators {
45 sw1_reg: sw1a {
46 regulator-name = "SW1";
47 regulator-min-microvolt = <650000>;
48 regulator-max-microvolt = <1437500>;
49 regulator-boot-on;
50 regulator-always-on;
51 };
52
53 sw1b_reg: sw1b {
54 regulator-name = "SW1B";
55 regulator-min-microvolt = <650000>;
56 regulator-max-microvolt = <1437500>;
57 regulator-boot-on;
58 regulator-always-on;
59 };
60
61 sw2_reg: sw2 {
62 regulator-name = "SW2";
63 regulator-min-microvolt = <650000>;
64 regulator-max-microvolt = <1437500>;
65 regulator-boot-on;
66 regulator-always-on;
67 };
68
69 sw3_reg: sw3 {
70 regulator-name = "SW3";
71 regulator-min-microvolt = <650000>;
72 regulator-max-microvolt = <1425000>;
73 regulator-boot-on;
74 };
75
76 sw4a_reg: sw4a {
77 regulator-name = "SW4A";
78 regulator-min-microvolt = <1200000>;
79 regulator-max-microvolt = <3300000>;
80 regulator-boot-on;
81 regulator-always-on;
82 };
83
84 sw4b_reg: sw4b {
85 regulator-name = "SW4B";
86 regulator-min-microvolt = <1200000>;
87 regulator-max-microvolt = <3300000>;
88 regulator-boot-on;
89 regulator-always-on;
90 };
91
92 sw5_reg: sw5 {
93 regulator-name = "SW5";
94 regulator-min-microvolt = <1200000>;
95 regulator-max-microvolt = <1975000>;
96 regulator-boot-on;
97 regulator-always-on;
98 };
99
100 swbst_reg: swbst {
101 regulator-name = "SWBST";
102 regulator-boot-on;
103 regulator-always-on;
104 };
105
106 vpll_reg: vpll {
107 regulator-name = "VPLL";
108 regulator-min-microvolt = <1200000>;
109 regulator-max-microvolt = <1800000>;
110 regulator-boot-on;
111 };
112
113 vrefddr_reg: vrefddr {
114 regulator-name = "VREFDDR";
115 regulator-boot-on;
116 regulator-always-on;
117 };
118
119 vusb_reg: vusb {
120 regulator-name = "VUSB";
121 regulator-boot-on;
122 regulator-always-on;
123 };
124
125 vusb2_reg: vusb2 {
126 regulator-name = "VUSB2";
127 regulator-min-microvolt = <2500000>;
128 regulator-max-microvolt = <3000000>;
129 regulator-boot-on;
130 regulator-always-on;
131 };
132
133 vdac_reg: vdac {
134 regulator-name = "VDAC";
135 regulator-min-microvolt = <2500000>;
136 regulator-max-microvolt = <2775000>;
137 regulator-boot-on;
138 regulator-always-on;
139 };
140
141 vgen1_reg: vgen1 {
142 regulator-name = "VGEN1";
143 regulator-min-microvolt = <1200000>;
144 regulator-max-microvolt = <1550000>;
145 regulator-boot-on;
146 regulator-always-on;
147 };
148
149 vgen2_reg: vgen2 {
150 regulator-name = "VGEN2";
151 regulator-min-microvolt = <2500000>;
152 regulator-max-microvolt = <3300000>;
153 regulator-boot-on;
154 regulator-always-on;
155 };
156 };
157 };
158};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index a9b6e10de0a5..5ec1590ff7bc 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -40,7 +40,7 @@
40 40
41&esdhc1 { 41&esdhc1 {
42 pinctrl-names = "default"; 42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_esdhc1_1>; 43 pinctrl-0 = <&pinctrl_esdhc1>;
44 cd-gpios = <&gpio3 13 0>; 44 cd-gpios = <&gpio3 13 0>;
45 wp-gpios = <&gpio4 11 0>; 45 wp-gpios = <&gpio4 11 0>;
46 status = "okay"; 46 status = "okay";
@@ -48,21 +48,21 @@
48 48
49&esdhc2 { 49&esdhc2 {
50 pinctrl-names = "default"; 50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_esdhc2_1>; 51 pinctrl-0 = <&pinctrl_esdhc2>;
52 non-removable; 52 non-removable;
53 status = "okay"; 53 status = "okay";
54}; 54};
55 55
56&uart3 { 56&uart3 {
57 pinctrl-names = "default"; 57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_uart3_1>; 58 pinctrl-0 = <&pinctrl_uart3>;
59 fsl,uart-has-rtscts; 59 fsl,uart-has-rtscts;
60 status = "okay"; 60 status = "okay";
61}; 61};
62 62
63&ecspi1 { 63&ecspi1 {
64 pinctrl-names = "default"; 64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_ecspi1_1>; 65 pinctrl-0 = <&pinctrl_ecspi1>;
66 fsl,spi-num-chipselects = <2>; 66 fsl,spi-num-chipselects = <2>;
67 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; 67 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
68 status = "okay"; 68 status = "okay";
@@ -95,7 +95,7 @@
95 95
96&esdhc3 { 96&esdhc3 {
97 pinctrl-names = "default"; 97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_esdhc3_1>; 98 pinctrl-0 = <&pinctrl_esdhc3>;
99 non-removable; 99 non-removable;
100 status = "okay"; 100 status = "okay";
101}; 101};
@@ -104,7 +104,7 @@
104 pinctrl-names = "default"; 104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_hog>; 105 pinctrl-0 = <&pinctrl_hog>;
106 106
107 hog { 107 imx53-smd {
108 pinctrl_hog: hoggrp { 108 pinctrl_hog: hoggrp {
109 fsl,pins = < 109 fsl,pins = <
110 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 110 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
@@ -116,24 +116,121 @@
116 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 116 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
117 >; 117 >;
118 }; 118 };
119
120 pinctrl_ecspi1: ecspi1grp {
121 fsl,pins = <
122 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
123 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
124 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
125 >;
126 };
127
128 pinctrl_esdhc1: esdhc1grp {
129 fsl,pins = <
130 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
131 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
132 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
133 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
134 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
135 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
136 >;
137 };
138
139 pinctrl_esdhc2: esdhc2grp {
140 fsl,pins = <
141 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
142 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
143 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
144 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
145 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
146 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
147 >;
148 };
149
150 pinctrl_esdhc3: esdhc3grp {
151 fsl,pins = <
152 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
153 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
154 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
155 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
156 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
157 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
158 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
159 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
160 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
161 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
162 >;
163 };
164
165 pinctrl_fec: fecgrp {
166 fsl,pins = <
167 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
168 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
169 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
170 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
171 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
172 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
173 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
174 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
175 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
176 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
177 >;
178 };
179
180 pinctrl_i2c1: i2c1grp {
181 fsl,pins = <
182 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
183 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
184 >;
185 };
186
187 pinctrl_i2c2: i2c2grp {
188 fsl,pins = <
189 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
190 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
191 >;
192 };
193
194 pinctrl_uart1: uart1grp {
195 fsl,pins = <
196 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
197 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
198 >;
199 };
200
201 pinctrl_uart2: uart2grp {
202 fsl,pins = <
203 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
204 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
205 >;
206 };
207
208 pinctrl_uart3: uart3grp {
209 fsl,pins = <
210 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
211 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
212 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
213 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
214 >;
215 };
119 }; 216 };
120}; 217};
121 218
122&uart1 { 219&uart1 {
123 pinctrl-names = "default"; 220 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_uart1_1>; 221 pinctrl-0 = <&pinctrl_uart1>;
125 status = "okay"; 222 status = "okay";
126}; 223};
127 224
128&uart2 { 225&uart2 {
129 pinctrl-names = "default"; 226 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_uart2_1>; 227 pinctrl-0 = <&pinctrl_uart2>;
131 status = "okay"; 228 status = "okay";
132}; 229};
133 230
134&i2c2 { 231&i2c2 {
135 pinctrl-names = "default"; 232 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_i2c2_1>; 233 pinctrl-0 = <&pinctrl_i2c2>;
137 status = "okay"; 234 status = "okay";
138 235
139 codec: sgtl5000@0a { 236 codec: sgtl5000@0a {
@@ -154,7 +251,7 @@
154 251
155&i2c1 { 252&i2c1 {
156 pinctrl-names = "default"; 253 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_i2c1_1>; 254 pinctrl-0 = <&pinctrl_i2c1>;
158 status = "okay"; 255 status = "okay";
159 256
160 accelerometer: mma8450@1c { 257 accelerometer: mma8450@1c {
@@ -175,7 +272,7 @@
175 272
176&fec { 273&fec {
177 pinctrl-names = "default"; 274 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_fec_1>; 275 pinctrl-0 = <&pinctrl_fec>;
179 phy-mode = "rmii"; 276 phy-mode = "rmii";
180 phy-reset-gpios = <&gpio7 6 0>; 277 phy-reset-gpios = <&gpio7 6 0>;
181 status = "okay"; 278 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index abd72af545bf..4f1f0e2868bf 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -22,9 +22,12 @@
22 22
23 regulators { 23 regulators {
24 compatible = "simple-bus"; 24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <0>;
25 27
26 reg_3p3v: 3p3v { 28 reg_3p3v: regulator@0 {
27 compatible = "regulator-fixed"; 29 compatible = "regulator-fixed";
30 reg = <0>;
28 regulator-name = "3P3V"; 31 regulator-name = "3P3V";
29 regulator-min-microvolt = <3300000>; 32 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>; 33 regulator-max-microvolt = <3300000>;
@@ -35,8 +38,8 @@
35 38
36&esdhc2 { 39&esdhc2 {
37 pinctrl-names = "default"; 40 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_esdhc2_1>, 41 pinctrl-0 = <&pinctrl_esdhc2>,
39 <&pinctrl_tqma53_esdhc2_2>; 42 <&pinctrl_esdhc2_cdwp>;
40 vmmc-supply = <&reg_3p3v>; 43 vmmc-supply = <&reg_3p3v>;
41 wp-gpios = <&gpio1 2 0>; 44 wp-gpios = <&gpio1 2 0>;
42 cd-gpios = <&gpio1 4 0>; 45 cd-gpios = <&gpio1 4 0>;
@@ -45,13 +48,13 @@
45 48
46&uart3 { 49&uart3 {
47 pinctrl-names = "default"; 50 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart3_2>; 51 pinctrl-0 = <&pinctrl_uart3>;
49 status = "disabled"; 52 status = "disabled";
50}; 53};
51 54
52&ecspi1 { 55&ecspi1 {
53 pinctrl-names = "default"; 56 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_ecspi1_1>; 57 pinctrl-0 = <&pinctrl_ecspi1>;
55 fsl,spi-num-chipselects = <4>; 58 fsl,spi-num-chipselects = <4>;
56 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, 59 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
57 <&gpio3 24 0>, <&gpio3 25 0>; 60 <&gpio3 24 0>, <&gpio3 25 0>;
@@ -60,7 +63,7 @@
60 63
61&esdhc3 { /* EMMC */ 64&esdhc3 { /* EMMC */
62 pinctrl-names = "default"; 65 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_esdhc3_1>; 66 pinctrl-0 = <&pinctrl_esdhc3>;
64 vmmc-supply = <&reg_3p3v>; 67 vmmc-supply = <&reg_3p3v>;
65 non-removable; 68 non-removable;
66 bus-width = <8>; 69 bus-width = <8>;
@@ -71,27 +74,7 @@
71 pinctrl-names = "default"; 74 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_hog>; 75 pinctrl-0 = <&pinctrl_hog>;
73 76
74 esdhc2_2 { 77 imx53-tqma53 {
75 pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
76 fsl,pins = <
77 MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
78 MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
79 >;
80 };
81 };
82
83 i2s {
84 pinctrl_i2s_1: i2s-grp1 {
85 fsl,pins = <
86 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */
87 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */
88 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
89 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */
90 >;
91 };
92 };
93
94 hog {
95 pinctrl_hog: hoggrp { 78 pinctrl_hog: hoggrp {
96 fsl,pins = < 79 fsl,pins = <
97 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ 80 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
@@ -107,43 +90,165 @@
107 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ 90 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
108 >; 91 >;
109 }; 92 };
93
94 pinctrl_audmux: audmuxgrp {
95 fsl,pins = <
96 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
97 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
98 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
99 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
100 >;
101 };
102
103 pinctrl_can1: can1grp {
104 fsl,pins = <
105 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
106 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
107 >;
108 };
109
110 pinctrl_can2: can2grp {
111 fsl,pins = <
112 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
113 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
114 >;
115 };
116
117 pinctrl_cspi: cspigrp {
118 fsl,pins = <
119 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
120 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
121 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
122 >;
123 };
124
125 pinctrl_ecspi1: ecspi1grp {
126 fsl,pins = <
127 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
128 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
129 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
130 >;
131 };
132
133 pinctrl_esdhc2: esdhc2grp {
134 fsl,pins = <
135 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
136 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
137 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
138 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
139 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
140 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
141 >;
142 };
143
144 pinctrl_esdhc2_cdwp: esdhc2cdwp {
145 fsl,pins = <
146 MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
147 MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
148 >;
149 };
150
151 pinctrl_esdhc3: esdhc3grp {
152 fsl,pins = <
153 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
154 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
155 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
156 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
157 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
158 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
159 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
160 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
161 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
162 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
163 >;
164 };
165
166 pinctrl_fec: fecgrp {
167 fsl,pins = <
168 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
169 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
170 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
171 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
172 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
173 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
174 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
175 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
176 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
177 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
178 >;
179 };
180
181 pinctrl_i2c2: i2c2grp {
182 fsl,pins = <
183 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
184 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
185 >;
186 };
187
188 pinctrl_i2c3: i2c3grp {
189 fsl,pins = <
190 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
191 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
192 >;
193 };
194
195 pinctrl_uart1: uart1grp {
196 fsl,pins = <
197 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
198 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
199 >;
200 };
201
202 pinctrl_uart2: uart2grp {
203 fsl,pins = <
204 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
205 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
206 >;
207 };
208
209 pinctrl_uart3: uart3grp {
210 fsl,pins = <
211 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
212 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
213 >;
214 };
110 }; 215 };
111}; 216};
112 217
113&uart1 { 218&uart1 {
114 pinctrl-names = "default"; 219 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_uart1_2>; 220 pinctrl-0 = <&pinctrl_uart1>;
116 fsl,uart-has-rtscts; 221 fsl,uart-has-rtscts;
117 status = "disabled"; 222 status = "disabled";
118}; 223};
119 224
120&uart2 { 225&uart2 {
121 pinctrl-names = "default"; 226 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_uart2_1>; 227 pinctrl-0 = <&pinctrl_uart2>;
123 status = "disabled"; 228 status = "disabled";
124}; 229};
125 230
126&can1 { 231&can1 {
127 pinctrl-names = "default"; 232 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_can1_2>; 233 pinctrl-0 = <&pinctrl_can1>;
129 status = "disabled"; 234 status = "disabled";
130}; 235};
131 236
132&can2 { 237&can2 {
133 pinctrl-names = "default"; 238 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_can2_1>; 239 pinctrl-0 = <&pinctrl_can2>;
135 status = "disabled"; 240 status = "disabled";
136}; 241};
137 242
138&i2c3 { 243&i2c3 {
139 pinctrl-names = "default"; 244 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c3_1>; 245 pinctrl-0 = <&pinctrl_i2c3>;
141 status = "disabled"; 246 status = "disabled";
142}; 247};
143 248
144&cspi { 249&cspi {
145 pinctrl-names = "default"; 250 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_cspi_1>; 251 pinctrl-0 = <&pinctrl_cspi>;
147 fsl,spi-num-chipselects = <3>; 252 fsl,spi-num-chipselects = <3>;
148 cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>, 253 cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
149 <&gpio1 21 0>; 254 <&gpio1 21 0>;
@@ -152,7 +257,7 @@
152 257
153&i2c2 { 258&i2c2 {
154 pinctrl-names = "default"; 259 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c2_1>; 260 pinctrl-0 = <&pinctrl_i2c2>;
156 status = "okay"; 261 status = "okay";
157 262
158 pmic: mc34708@8 { 263 pmic: mc34708@8 {
@@ -177,7 +282,7 @@
177 282
178&fec { 283&fec {
179 pinctrl-names = "default"; 284 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_fec_1>; 285 pinctrl-0 = <&pinctrl_fec>;
181 phy-mode = "rmii"; 286 phy-mode = "rmii";
182 status = "disabled"; 287 status = "disabled";
183}; 288};
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
new file mode 100644
index 000000000000..0217dde3b36b
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -0,0 +1,315 @@
1/*
2 * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx53-tx53.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/pwm/pwm.h>
16
17/ {
18 model = "Ka-Ro electronics TX53 module (LCD)";
19 compatible = "karo,tx53", "fsl,imx53";
20
21 aliases {
22 display = &display;
23 };
24
25 soc {
26 display: display@di0 {
27 compatible = "fsl,imx-parallel-display";
28 crtcs = <&ipu 0>;
29 interface-pix-fmt = "rgb24";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_rgb24_vga1>;
32 status = "okay";
33
34 display-timings {
35 VGA {
36 clock-frequency = <25200000>;
37 hactive = <640>;
38 vactive = <480>;
39 hback-porch = <48>;
40 hsync-len = <96>;
41 hfront-porch = <16>;
42 vback-porch = <31>;
43 vsync-len = <2>;
44 vfront-porch = <12>;
45 hsync-active = <0>;
46 vsync-active = <0>;
47 de-active = <1>;
48 pixelclk-active = <0>;
49 };
50
51 ETV570 {
52 clock-frequency = <25200000>;
53 hactive = <640>;
54 vactive = <480>;
55 hback-porch = <114>;
56 hsync-len = <30>;
57 hfront-porch = <16>;
58 vback-porch = <32>;
59 vsync-len = <3>;
60 vfront-porch = <10>;
61 hsync-active = <0>;
62 vsync-active = <0>;
63 de-active = <1>;
64 pixelclk-active = <0>;
65 };
66
67 ET0350 {
68 clock-frequency = <6413760>;
69 hactive = <320>;
70 vactive = <240>;
71 hback-porch = <34>;
72 hsync-len = <34>;
73 hfront-porch = <20>;
74 vback-porch = <15>;
75 vsync-len = <3>;
76 vfront-porch = <4>;
77 hsync-active = <0>;
78 vsync-active = <0>;
79 de-active = <1>;
80 pixelclk-active = <0>;
81 };
82
83 ET0430 {
84 clock-frequency = <9009000>;
85 hactive = <480>;
86 vactive = <272>;
87 hback-porch = <2>;
88 hsync-len = <41>;
89 hfront-porch = <2>;
90 vback-porch = <2>;
91 vsync-len = <10>;
92 vfront-porch = <2>;
93 hsync-active = <0>;
94 vsync-active = <0>;
95 de-active = <1>;
96 pixelclk-active = <1>;
97 };
98
99 ET0500 {
100 clock-frequency = <33264000>;
101 hactive = <800>;
102 vactive = <480>;
103 hback-porch = <88>;
104 hsync-len = <128>;
105 hfront-porch = <40>;
106 vback-porch = <33>;
107 vsync-len = <2>;
108 vfront-porch = <10>;
109 hsync-active = <0>;
110 vsync-active = <0>;
111 de-active = <1>;
112 pixelclk-active = <0>;
113 };
114
115 ET0700 { /* same as ET0500 */
116 clock-frequency = <33264000>;
117 hactive = <800>;
118 vactive = <480>;
119 hback-porch = <88>;
120 hsync-len = <128>;
121 hfront-porch = <40>;
122 vback-porch = <33>;
123 vsync-len = <2>;
124 vfront-porch = <10>;
125 hsync-active = <0>;
126 vsync-active = <0>;
127 de-active = <1>;
128 pixelclk-active = <0>;
129 };
130
131 ETQ570 {
132 clock-frequency = <6596040>;
133 hactive = <320>;
134 vactive = <240>;
135 hback-porch = <38>;
136 hsync-len = <30>;
137 hfront-porch = <30>;
138 vback-porch = <16>;
139 vsync-len = <3>;
140 vfront-porch = <4>;
141 hsync-active = <0>;
142 vsync-active = <0>;
143 de-active = <1>;
144 pixelclk-active = <0>;
145 };
146 };
147 };
148 };
149
150 backlight: backlight {
151 compatible = "pwm-backlight";
152 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
153 power-supply = <&reg_3v3>;
154 brightness-levels = <
155 0 1 2 3 4 5 6 7 8 9
156 10 11 12 13 14 15 16 17 18 19
157 20 21 22 23 24 25 26 27 28 29
158 30 31 32 33 34 35 36 37 38 39
159 40 41 42 43 44 45 46 47 48 49
160 50 51 52 53 54 55 56 57 58 59
161 60 61 62 63 64 65 66 67 68 69
162 70 71 72 73 74 75 76 77 78 79
163 80 81 82 83 84 85 86 87 88 89
164 90 91 92 93 94 95 96 97 98 99
165 100
166 >;
167 default-brightness-level = <50>;
168 };
169
170 regulators {
171 reg_lcd_pwr: regulator@5 {
172 compatible = "regulator-fixed";
173 reg = <5>;
174 regulator-name = "LCD POWER";
175 regulator-min-microvolt = <3300000>;
176 regulator-max-microvolt = <3300000>;
177 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
178 enable-active-high;
179 regulator-boot-on;
180 };
181
182 reg_lcd_reset: regulator@6 {
183 compatible = "regulator-fixed";
184 reg = <6>;
185 regulator-name = "LCD RESET";
186 regulator-min-microvolt = <3300000>;
187 regulator-max-microvolt = <3300000>;
188 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
189 enable-active-high;
190 regulator-boot-on;
191 };
192 };
193};
194
195&i2c3 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c3>;
198 status = "okay";
199
200 sgtl5000: codec@0a {
201 compatible = "fsl,sgtl5000";
202 reg = <0x0a>;
203 VDDA-supply = <&reg_2v5>;
204 VDDIO-supply = <&reg_3v3>;
205 clocks = <&mclk>;
206 };
207
208 polytouch: edt-ft5x06@38 {
209 compatible = "edt,edt-ft5x06";
210 reg = <0x38>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
213 interrupt-parent = <&gpio6>;
214 interrupts = <15 0>;
215 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
216 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
217 };
218
219 touchscreen: tsc2007@48 {
220 compatible = "ti,tsc2007";
221 reg = <0x48>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_tsc2007>;
224 interrupt-parent = <&gpio3>;
225 interrupts = <26 0>;
226 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
227 ti,x-plate-ohms = <660>;
228 linux,wakeup;
229 };
230};
231
232&iomuxc {
233 imx53-tx53-x03x {
234 pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
235 fsl,pins = <
236 MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */
237 MX53_PAD_EIM_A16__GPIO2_22 0x04 /* Reset */
238 MX53_PAD_EIM_A17__GPIO2_21 0x04 /* Wake */
239 >;
240 };
241
242 pinctrl_kpp: kppgrp {
243 fsl,pins = <
244 MX53_PAD_GPIO_9__KPP_COL_6 0x1f4
245 MX53_PAD_GPIO_4__KPP_COL_7 0x1f4
246 MX53_PAD_KEY_COL2__KPP_COL_2 0x1f4
247 MX53_PAD_KEY_COL3__KPP_COL_3 0x1f4
248 MX53_PAD_GPIO_2__KPP_ROW_6 0x1f4
249 MX53_PAD_GPIO_5__KPP_ROW_7 0x1f4
250 MX53_PAD_KEY_ROW2__KPP_ROW_2 0x1f4
251 MX53_PAD_KEY_ROW3__KPP_ROW_3 0x1f4
252 >;
253 };
254
255 pinctrl_rgb24_vga1: rgb24-vgagrp1 {
256 fsl,pins = <
257 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
258 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
259 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
260 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
261 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
262 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
263 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
264 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
265 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
266 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
267 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
268 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
269 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
270 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
271 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
272 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
273 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
274 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
275 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
276 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
277 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
278 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
279 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
280 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
281 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
282 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
283 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
284 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
285 >;
286 };
287
288 pinctrl_tsc2007: tsc2007grp {
289 fsl,pins = <
290 MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */
291 >;
292 };
293 };
294};
295
296&kpp {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_kpp>;
299 /* sample keymap */
300 /* row/col 0,1 are mapped to KPP row/col 6,7 */
301 linux,keymap = <
302 MATRIX_KEY(6, 6, KEY_POWER)
303 MATRIX_KEY(6, 7, KEY_KP0)
304 MATRIX_KEY(6, 2, KEY_KP1)
305 MATRIX_KEY(6, 3, KEY_KP2)
306 MATRIX_KEY(7, 6, KEY_KP3)
307 MATRIX_KEY(7, 7, KEY_KP4)
308 MATRIX_KEY(7, 2, KEY_KP5)
309 MATRIX_KEY(7, 3, KEY_KP6)
310 MATRIX_KEY(2, 6, KEY_KP7)
311 MATRIX_KEY(2, 7, KEY_KP8)
312 MATRIX_KEY(2, 2, KEY_KP9)
313 >;
314 status = "okay";
315};
diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts
new file mode 100644
index 000000000000..64804719f0f4
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts
@@ -0,0 +1,243 @@
1/*
2 * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx53-tx53.dtsi"
14#include <dt-bindings/input/input.h>
15
16/ {
17 model = "Ka-Ro electronics TX53 module (LVDS)";
18 compatible = "karo,tx53", "fsl,imx53";
19
20 aliases {
21 display = &lvds0;
22 lvds0 = &lvds0;
23 lvds1 = &lvds1;
24 };
25
26 backlight0: backlight0 {
27 compatible = "pwm-backlight";
28 pwms = <&pwm2 0 500000 0>;
29 power-supply = <&reg_3v3>;
30 brightness-levels = <
31 0 1 2 3 4 5 6 7 8 9
32 10 11 12 13 14 15 16 17 18 19
33 20 21 22 23 24 25 26 27 28 29
34 30 31 32 33 34 35 36 37 38 39
35 40 41 42 43 44 45 46 47 48 49
36 50 51 52 53 54 55 56 57 58 59
37 60 61 62 63 64 65 66 67 68 69
38 70 71 72 73 74 75 76 77 78 79
39 80 81 82 83 84 85 86 87 88 89
40 90 91 92 93 94 95 96 97 98 99
41 100
42 >;
43 default-brightness-level = <50>;
44 };
45
46 backlight1: backlight1 {
47 compatible = "pwm-backlight";
48 pwms = <&pwm1 0 500000 0>;
49 power-supply = <&reg_3v3>;
50 brightness-levels = <
51 0 1 2 3 4 5 6 7 8 9
52 10 11 12 13 14 15 16 17 18 19
53 20 21 22 23 24 25 26 27 28 29
54 30 31 32 33 34 35 36 37 38 39
55 40 41 42 43 44 45 46 47 48 49
56 50 51 52 53 54 55 56 57 58 59
57 60 61 62 63 64 65 66 67 68 69
58 70 71 72 73 74 75 76 77 78 79
59 80 81 82 83 84 85 86 87 88 89
60 90 91 92 93 94 95 96 97 98 99
61 100
62 >;
63 default-brightness-level = <50>;
64 };
65
66 regulators {
67 reg_lcd_pwr0: regulator@5 {
68 compatible = "regulator-fixed";
69 reg = <5>;
70 regulator-name = "LVDS0 POWER";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
74 enable-active-high;
75 regulator-boot-on;
76 };
77
78 reg_lcd_pwr1: regulator@6 {
79 compatible = "regulator-fixed";
80 reg = <6>;
81 regulator-name = "LVDS1 POWER";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
85 enable-active-high;
86 regulator-boot-on;
87 };
88 };
89};
90
91&i2c2 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_i2c2>;
94 status = "okay";
95
96 touchscreen2: eeti@04 {
97 compatible = "eeti,egalax_ts";
98 reg = <0x04>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_eeti2>;
101 interrupt-parent = <&gpio3>;
102 interrupts = <23 0>;
103 wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
104 linux,wakeup;
105 };
106};
107
108&i2c3 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_i2c3>;
111 status = "okay";
112
113 sgtl5000: codec@0a {
114 compatible = "fsl,sgtl5000";
115 reg = <0x0a>;
116 VDDA-supply = <&reg_2v5>;
117 VDDIO-supply = <&reg_3v3>;
118 clocks = <&mclk>;
119 };
120
121 touchscreen1: eeti@04 {
122 compatible = "eeti,egalax_ts";
123 reg = <0x04>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_eeti1>;
126 interrupt-parent = <&gpio3>;
127 interrupts = <22 0>;
128 wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
129 linux,wakeup;
130 };
131};
132
133&iomuxc {
134 imx53-tx53-x13x {
135 pinctrl_i2c2: i2c2-grp1 {
136 fsl,pins = <
137 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
138 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
139 >;
140 };
141
142 pinctrl_lvds0: lvds0grp {
143 fsl,pins = <
144 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
145 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
146 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
147 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
148 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
149 >;
150 };
151
152 pinctrl_lvds1: lvds1grp {
153 fsl,pins = <
154 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
155 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
156 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
157 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
158 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
159 >;
160 };
161
162 pinctrl_pwm1: pwm1grp {
163 fsl,pins = <MX53_PAD_GPIO_9__PWM1_PWMO 0x04>;
164 };
165
166 pinctrl_eeti1: eeti1grp {
167 fsl,pins = <
168 MX53_PAD_EIM_D22__GPIO3_22 0x1f0 /* Interrupt */
169 >;
170 };
171
172 pinctrl_eeti2: eeti2grp {
173 fsl,pins = <
174 MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */
175 >;
176 };
177 };
178};
179
180&ldb {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_lvds0 &pinctrl_lvds1>;
183 status = "okay";
184
185 lvds0: lvds-channel@0 {
186 fsl,data-mapping = "jeida";
187 fsl,data-width = <24>;
188 status = "okay";
189
190 display-timings {
191 native-mode = <&lvds_timing0>;
192 lvds_timing0: hsd100pxn1 {
193 clock-frequency = <65000000>;
194 hactive = <1024>;
195 vactive = <768>;
196 hback-porch = <220>;
197 hsync-len = <60>;
198 hfront-porch = <40>;
199 vback-porch = <21>;
200 vsync-len = <10>;
201 vfront-porch = <7>;
202 hsync-active = <0>;
203 vsync-active = <0>;
204 de-active = <1>;
205 pixelclk-active = <0>;
206 };
207 };
208 };
209
210 lvds1: lvds-channel@1 {
211 fsl,data-mapping = "jeida";
212 fsl,data-width = <24>;
213 status = "okay";
214
215 display-timings {
216 native-mode = <&lvds_timing1>;
217 lvds_timing1: hsd100pxn1 {
218 clock-frequency = <65000000>;
219 hactive = <1024>;
220 vactive = <768>;
221 hback-porch = <220>;
222 hsync-len = <60>;
223 hfront-porch = <40>;
224 vback-porch = <21>;
225 vsync-len = <10>;
226 vfront-porch = <7>;
227 hsync-active = <0>;
228 vsync-active = <0>;
229 de-active = <1>;
230 pixelclk-active = <0>;
231 };
232 };
233 };
234};
235
236&pwm1 {
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_pwm1>;
239};
240
241&sata {
242 status = "okay";
243};
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index f494766700a3..e348796ba689 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -1,122 +1,550 @@
1/* 1/*
2 * Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> 2 * Copyright 2012 <LW@KARO-electronics.de>
3 * based on imx53-qsb.dts
4 * Copyright 2011 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
3 * 6 *
4 * The code contained herein is licensed under the GNU General Public 7 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 8 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations: 9 * Version 2 at the following locations:
7 * 10 *
8 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html 12 * http://www.gnu.org/copyleft/gpl.html
10 */ 13 */
11 14
12/include/ "imx53.dtsi" 15#include "imx53.dtsi"
16#include <dt-bindings/gpio/gpio.h>
13 17
14/ { 18/ {
15 model = "Ka-Ro TX53"; 19 model = "Ka-Ro electronics TX53 module";
16 compatible = "karo,tx53", "fsl,imx53"; 20 compatible = "karo,tx53", "fsl,imx53";
17 21
18 memory { 22 aliases {
19 reg = <0x70000000 0x40000000>; /* Up to 1GiB */ 23 can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
24 can1 = &can1;
25 ipu = &ipu;
26 reg_can_xcvr = &reg_can_xcvr;
27 usbh1 = &usbh1;
28 usbotg = &usbotg;
29 };
30
31 clocks {
32 ckih1 {
33 clock-frequency = <0>;
34 };
35
36 mclk: clock@0 {
37 compatible = "fixed-clock";
38 reg = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <27000000>;
41 };
42 };
43
44 gpio-keys {
45 compatible = "gpio-keys";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_gpio_key>;
48
49 power {
50 label = "Power Button";
51 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
52 linux,code = <116>; /* KEY_POWER */
53 gpio-key,wakeup;
54 };
55 };
56
57 leds {
58 compatible = "gpio-leds";
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_stk5led>;
61
62 user {
63 label = "Heartbeat";
64 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
66 };
20 }; 67 };
21 68
22 regulators { 69 regulators {
23 compatible = "simple-bus"; 70 compatible = "simple-bus";
71 #address-cells = <1>;
72 #size-cells = <0>;
24 73
25 reg_3p3v: 3p3v { 74 reg_2v5: regulator@0 {
26 compatible = "regulator-fixed"; 75 compatible = "regulator-fixed";
27 regulator-name = "3P3V"; 76 reg = <0>;
77 regulator-name = "2V5";
78 regulator-min-microvolt = <2500000>;
79 regulator-max-microvolt = <2500000>;
80 };
81
82 reg_3v3: regulator@1 {
83 compatible = "regulator-fixed";
84 reg = <1>;
85 regulator-name = "3V3";
28 regulator-min-microvolt = <3300000>; 86 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>;
30 regulator-always-on;
31 }; 88 };
89
90 reg_can_xcvr: regulator@2 {
91 compatible = "regulator-fixed";
92 reg = <2>;
93 regulator-name = "CAN XCVR";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_can_xcvr>;
98 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
99 };
100
101 reg_usbh1_vbus: regulator@3 {
102 compatible = "regulator-fixed";
103 reg = <3>;
104 regulator-name = "usbh1_vbus";
105 regulator-min-microvolt = <5000000>;
106 regulator-max-microvolt = <5000000>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_usbh1_vbus>;
109 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
110 enable-active-high;
111 };
112
113 reg_usbotg_vbus: regulator@4 {
114 compatible = "regulator-fixed";
115 reg = <4>;
116 regulator-name = "usbotg_vbus";
117 regulator-min-microvolt = <5000000>;
118 regulator-max-microvolt = <5000000>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_usbotg_vbus>;
121 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
122 enable-active-high;
123 };
124 };
125
126 sound {
127 compatible = "karo,tx53-audio-sgtl5000", "fsl,imx-audio-sgtl5000";
128 model = "tx53-audio-sgtl5000";
129 ssi-controller = <&ssi1>;
130 audio-codec = <&sgtl5000>;
131 audio-routing =
132 "MIC_IN", "Mic Jack",
133 "Mic Jack", "Mic Bias",
134 "Headphone Jack", "HP_OUT";
135 /* '1' based port numbers according to datasheet names */
136 mux-int-port = <1>;
137 mux-ext-port = <5>;
32 }; 138 };
33}; 139};
34 140
141&audmux {
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_ssi1>;
144 status = "okay";
145};
146
35&can1 { 147&can1 {
36 pinctrl-names = "default"; 148 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_can1_2>; 149 pinctrl-0 = <&pinctrl_can1>;
38 status = "disabled"; 150 xceiver-supply = <&reg_can_xcvr>;
151 status = "okay";
39}; 152};
40 153
41&can2 { 154&can2 {
42 pinctrl-names = "default"; 155 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_can2_1>; 156 pinctrl-0 = <&pinctrl_can2>;
44 status = "disabled"; 157 xceiver-supply = <&reg_can_xcvr>;
158 status = "okay";
45}; 159};
46 160
47&ecspi1 { 161&ecspi1 {
48 pinctrl-names = "default"; 162 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_ecspi1_2>; 163 pinctrl-0 = <&pinctrl_ecspi1>;
50 status = "disabled"; 164 fsl,spi-num-chipselects = <2>;
165 status = "okay";
166
167 cs-gpios = <
168 &gpio2 30 GPIO_ACTIVE_HIGH
169 &gpio3 19 GPIO_ACTIVE_HIGH
170 >;
171
172 spidev0: spi@0 {
173 compatible = "spidev";
174 reg = <0>;
175 spi-max-frequency = <54000000>;
176 };
177
178 spidev1: spi@1 {
179 compatible = "spidev";
180 reg = <1>;
181 spi-max-frequency = <54000000>;
182 };
51}; 183};
52 184
53&esdhc1 { 185&esdhc1 {
186 cd-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
187 fsl,wp-controller;
54 pinctrl-names = "default"; 188 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_esdhc1_2>; 189 pinctrl-0 = <&pinctrl_esdhc1>;
56 status = "disabled"; 190 status = "okay";
57}; 191};
58 192
59&esdhc2 { 193&esdhc2 {
194 cd-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
195 fsl,wp-controller;
60 pinctrl-names = "default"; 196 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_esdhc2_1>; 197 pinctrl-0 = <&pinctrl_esdhc2>;
62 status = "disabled"; 198 status = "okay";
63}; 199};
64 200
65&fec { 201&fec {
66 pinctrl-names = "default"; 202 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_fec_1>; 203 pinctrl-0 = <&pinctrl_fec>;
68 phy-mode = "rmii"; 204 phy-mode = "rmii";
69 status = "disabled"; 205 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
206 phy-handle = <&phy0>;
207 mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
208 status = "okay";
209
210 phy0: ethernet-phy@0 {
211 interrupt-parent = <&gpio2>;
212 interrupts = <4>;
213 device_type = "ethernet-phy";
214 };
70}; 215};
71 216
72&i2c3 { 217&i2c1 {
73 pinctrl-names = "default"; 218 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_i2c3_2>; 219 pinctrl-0 = <&pinctrl_i2c1>;
75 status = "disabled"; 220 clock-frequency = <400000>;
221 status = "okay";
222
223 rtc1: ds1339@68 {
224 compatible = "dallas,ds1339";
225 reg = <0x68>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_ds1339>;
228 interrupt-parent = <&gpio4>;
229 interrupts = <20 0>;
230 };
76}; 231};
77 232
78&owire { 233&iomuxc {
79 pinctrl-names = "default"; 234 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_owire_1>; 235 pinctrl-0 = <&pinctrl_hog>;
81 status = "disabled"; 236
237 imx53-tx53 {
238 pinctrl_hog: hoggrp {
239 /* pins not in use by any device on the Starterkit board series */
240 fsl,pins = <
241 /* CMOS Sensor Interface */
242 MX53_PAD_CSI0_DAT12__GPIO5_30 0x1f4
243 MX53_PAD_CSI0_DAT13__GPIO5_31 0x1f4
244 MX53_PAD_CSI0_DAT14__GPIO6_0 0x1f4
245 MX53_PAD_CSI0_DAT15__GPIO6_1 0x1f4
246 MX53_PAD_CSI0_DAT16__GPIO6_2 0x1f4
247 MX53_PAD_CSI0_DAT17__GPIO6_3 0x1f4
248 MX53_PAD_CSI0_DAT18__GPIO6_4 0x1f4
249 MX53_PAD_CSI0_DAT19__GPIO6_5 0x1f4
250 MX53_PAD_CSI0_MCLK__GPIO5_19 0x1f4
251 MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1f4
252 MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1f4
253 MX53_PAD_GPIO_0__GPIO1_0 0x1f4
254 /* Module Specific Signal */
255 /* MX53_PAD_NANDF_CS2__GPIO6_15 0x1f4 maybe used by EDT-FT5x06 */
256 /* MX53_PAD_EIM_A16__GPIO2_22 0x1f4 maybe used by EDT-FT5x06 */
257 MX53_PAD_EIM_D29__GPIO3_29 0x1f4
258 MX53_PAD_EIM_EB3__GPIO2_31 0x1f4
259 /* MX53_PAD_EIM_A17__GPIO2_21 0x1f4 maybe used by EDT-FT5x06 */
260 /* MX53_PAD_EIM_A18__GPIO2_20 0x1f4 used by LED */
261 MX53_PAD_EIM_A19__GPIO2_19 0x1f4
262 MX53_PAD_EIM_A20__GPIO2_18 0x1f4
263 MX53_PAD_EIM_A21__GPIO2_17 0x1f4
264 MX53_PAD_EIM_A22__GPIO2_16 0x1f4
265 MX53_PAD_EIM_A23__GPIO6_6 0x1f4
266 MX53_PAD_EIM_A24__GPIO5_4 0x1f4
267 MX53_PAD_CSI0_DAT8__GPIO5_26 0x1f4
268 MX53_PAD_CSI0_DAT9__GPIO5_27 0x1f4
269 MX53_PAD_CSI0_DAT10__GPIO5_28 0x1f4
270 MX53_PAD_CSI0_DAT11__GPIO5_29 0x1f4
271 /* MX53_PAD_EIM_D22__GPIO3_22 0x1f4 maybe used by EETI touchpanel driver */
272 /* MX53_PAD_EIM_D23__GPIO3_23 0x1f4 maybe used by EETI touchpanel driver */
273 MX53_PAD_GPIO_13__GPIO4_3 0x1f4
274 MX53_PAD_EIM_CS0__GPIO2_23 0x1f4
275 MX53_PAD_EIM_CS1__GPIO2_24 0x1f4
276 MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1f4
277 MX53_PAD_EIM_WAIT__GPIO5_0 0x1f4
278 MX53_PAD_EIM_EB0__GPIO2_28 0x1f4
279 MX53_PAD_EIM_EB1__GPIO2_29 0x1f4
280 MX53_PAD_EIM_OE__GPIO2_25 0x1f4
281 MX53_PAD_EIM_LBA__GPIO2_27 0x1f4
282 MX53_PAD_EIM_RW__GPIO2_26 0x1f4
283 MX53_PAD_EIM_DA8__GPIO3_8 0x1f4
284 MX53_PAD_EIM_DA9__GPIO3_9 0x1f4
285 MX53_PAD_EIM_DA10__GPIO3_10 0x1f4
286 MX53_PAD_EIM_DA11__GPIO3_11 0x1f4
287 MX53_PAD_EIM_DA12__GPIO3_12 0x1f4
288 MX53_PAD_EIM_DA13__GPIO3_13 0x1f4
289 MX53_PAD_EIM_DA14__GPIO3_14 0x1f4
290 MX53_PAD_EIM_DA15__GPIO3_15 0x1f4
291 >;
292 };
293
294 pinctrl_can1: can1grp {
295 fsl,pins = <
296 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
297 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
298 >;
299 };
300
301 pinctrl_can2: can2grp {
302 fsl,pins = <
303 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
304 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
305 >;
306 };
307
308 pinctrl_can_xcvr: can-xcvrgrp {
309 fsl,pins = <MX53_PAD_DISP0_DAT0__GPIO4_21 0xe0>; /* Flexcan XCVR enable */
310 };
311
312 pinctrl_ds1339: ds1339grp {
313 fsl,pins = <MX53_PAD_DI0_PIN4__GPIO4_20 0xe0>;
314 };
315
316 pinctrl_ecspi1: ecspi1grp {
317 fsl,pins = <
318 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
319 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
320 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
321 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
322 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
323 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
324 >;
325 };
326
327 pinctrl_esdhc1: esdhc1grp {
328 fsl,pins = <
329 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
330 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
331 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
332 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
333 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
334 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
335 MX53_PAD_EIM_D24__GPIO3_24 0x1f0
336 >;
337 };
338
339 pinctrl_esdhc2: esdhc2grp {
340 fsl,pins = <
341 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
342 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
343 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
344 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
345 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
346 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
347 MX53_PAD_EIM_D25__GPIO3_25 0x1f0
348 >;
349 };
350
351 pinctrl_fec: fecgrp {
352 fsl,pins = <
353 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
354 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
355 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
356 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
357 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
358 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
359 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
360 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
361 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
362 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
363 >;
364 };
365
366 pinctrl_gpio_key: gpio-keygrp {
367 fsl,pins = <MX53_PAD_EIM_A25__GPIO5_2 0x1f4>;
368 };
369
370 pinctrl_i2c1: i2c1grp {
371 fsl,pins = <
372 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
373 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
374 >;
375 };
376
377 pinctrl_i2c3: i2c3grp {
378 fsl,pins = <
379 MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000
380 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
381 >;
382 };
383
384 pinctrl_nand: nandgrp {
385 fsl,pins = <
386 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
387 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
388 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
389 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
390 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
391 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
392 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
393 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
394 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
395 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
396 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
397 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
398 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
399 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
400 MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
401 >;
402 };
403
404 pinctrl_pwm2: pwm2grp {
405 fsl,pins = <
406 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
407 >;
408 };
409
410 pinctrl_ssi1: ssi1grp {
411 fsl,pins = <
412 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
413 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
414 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
415 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
416 >;
417 };
418
419 pinctrl_ssi2: ssi2grp {
420 fsl,pins = <
421 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
422 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
423 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
424 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
425 MX53_PAD_EIM_D27__GPIO3_27 0x1f0
426 >;
427 };
428
429 pinctrl_stk5led: stk5ledgrp {
430 fsl,pins = <MX53_PAD_EIM_A18__GPIO2_20 0xc0>;
431 };
432
433 pinctrl_uart1: uart1grp {
434 fsl,pins = <
435 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
436 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
437 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
438 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
439 >;
440 };
441
442 pinctrl_uart2: uart2grp {
443 fsl,pins = <
444 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
445 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
446 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
447 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
448 >;
449 };
450
451 pinctrl_uart3: uart3grp {
452 fsl,pins = <
453 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
454 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
455 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
456 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
457 >;
458 };
459
460 pinctrl_usbh1: usbh1grp {
461 fsl,pins = <
462 MX53_PAD_EIM_D30__GPIO3_30 0x100 /* OC */
463 >;
464 };
465
466 pinctrl_usbh1_vbus: usbh1-vbusgrp {
467 fsl,pins = <
468 MX53_PAD_EIM_D31__GPIO3_31 0xe0 /* VBUS ENABLE */
469 >;
470 };
471
472 pinctrl_usbotg_vbus: usbotg-vbusgrp {
473 fsl,pins = <
474 MX53_PAD_GPIO_7__GPIO1_7 0xe0 /* VBUS ENABLE */
475 MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */
476 >;
477 };
478 };
479};
480
481&ipu {
482 status = "okay";
483};
484
485&nfc {
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_nand>;
488 nand-bus-width = <8>;
489 nand-ecc-mode = "hw";
490 nand-on-flash-bbt;
491 status = "okay";
82}; 492};
83 493
84&pwm2 { 494&pwm2 {
85 pinctrl-names = "default"; 495 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_pwm2_1>; 496 pinctrl-0 = <&pinctrl_pwm2>;
87 status = "disabled"; 497 #pwm-cells = <3>;
498};
499
500&sdma {
501 fsl,sdma-ram-script-name = "sdma-imx53.bin";
88}; 502};
89 503
90&ssi1 { 504&ssi1 {
91 pinctrl-names = "default"; 505 fsl,mode = "i2s-slave";
92 pinctrl-0 = <&pinctrl_audmux_1>; 506 codec-handle = <&sgtl5000>;
93 status = "disabled"; 507 status = "okay";
94}; 508};
95 509
96&ssi2 { 510&ssi2 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_audmux_2>;
99 status = "disabled"; 511 status = "disabled";
100}; 512};
101 513
102&uart1 { 514&uart1 {
103 pinctrl-names = "default"; 515 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_uart1_2>, 516 pinctrl-0 = <&pinctrl_uart1>;
105 <&pinctrl_uart1_3>;
106 fsl,uart-has-rtscts; 517 fsl,uart-has-rtscts;
107 status = "disabled"; 518 status = "okay";
108}; 519};
109 520
110&uart2 { 521&uart2 {
111 pinctrl-names = "default"; 522 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_uart2_2>; 523 pinctrl-0 = <&pinctrl_uart2>;
113 fsl,uart-has-rtscts; 524 fsl,uart-has-rtscts;
114 status = "disabled"; 525 status = "okay";
115}; 526};
116 527
117&uart3 { 528&uart3 {
118 pinctrl-names = "default"; 529 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_uart3_1>; 530 pinctrl-0 = <&pinctrl_uart3>;
120 fsl,uart-has-rtscts; 531 fsl,uart-has-rtscts;
121 status = "disabled"; 532 status = "okay";
533};
534
535&usbh1 {
536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_usbh1>;
538 phy_type = "utmi";
539 disable-over-current;
540 vbus-supply = <&reg_usbh1_vbus>;
541 status = "okay";
542};
543
544&usbotg {
545 phy_type = "utmi";
546 dr_mode = "peripheral";
547 disable-over-current;
548 vbus-supply = <&reg_usbotg_vbus>;
549 status = "okay";
122}; 550};
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts
new file mode 100644
index 000000000000..7f6711a48615
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -0,0 +1,159 @@
1/*
2 * Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx53-voipac-dmm-668.dtsi"
14
15/ {
16 sound {
17 compatible = "fsl,imx53-voipac-sgtl5000",
18 "fsl,imx-audio-sgtl5000";
19 model = "imx53-voipac-sgtl5000";
20 ssi-controller = <&ssi2>;
21 audio-codec = <&sgtl5000>;
22 audio-routing =
23 "Headphone Jack", "HP_OUT";
24 mux-int-port = <2>;
25 mux-ext-port = <5>;
26 };
27
28 leds {
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pin_gpio>;
32
33 led1 {
34 label = "led-red";
35 gpios = <&gpio3 29 0>;
36 default-state = "off";
37 };
38
39 led2 {
40 label = "led-orange";
41 gpios = <&gpio2 31 0>;
42 default-state = "off";
43 };
44 };
45};
46
47&iomuxc {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_hog>;
50
51 imx53-voipac {
52 pinctrl_hog: hoggrp {
53 fsl,pins = <
54 /* SD2_CD */
55 MX53_PAD_EIM_D25__GPIO3_25 0x80000000
56 /* SD2_WP */
57 MX53_PAD_EIM_A19__GPIO2_19 0x80000000
58 >;
59 };
60
61 led_pin_gpio: led_gpio {
62 fsl,pins = <
63 MX53_PAD_EIM_D29__GPIO3_29 0x80000000
64 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
65 >;
66 };
67
68 /* Keyboard controller */
69 pinctrl_kpp_1: kppgrp-1 {
70 fsl,pins = <
71 MX53_PAD_GPIO_9__KPP_COL_6 0xe8
72 MX53_PAD_GPIO_4__KPP_COL_7 0xe8
73 MX53_PAD_KEY_COL2__KPP_COL_2 0xe8
74 MX53_PAD_KEY_COL3__KPP_COL_3 0xe8
75 MX53_PAD_KEY_COL4__KPP_COL_4 0xe8
76 MX53_PAD_GPIO_2__KPP_ROW_6 0xe0
77 MX53_PAD_GPIO_5__KPP_ROW_7 0xe0
78 MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0
79 MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0
80 MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0
81 >;
82 };
83
84 pinctrl_audmux: audmuxgrp {
85 fsl,pins = <
86 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
87 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
88 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
89 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
90 >;
91 };
92
93 pinctrl_esdhc2: esdhc2grp {
94 fsl,pins = <
95 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
96 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
97 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
98 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
99 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
100 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
101 >;
102 };
103
104 pinctrl_i2c3: i2c3grp {
105 fsl,pins = <
106 MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000
107 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
108 >;
109 };
110 };
111};
112
113&audmux {
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_audmux>; /* SSI1 */
116 status = "okay";
117};
118
119&esdhc2 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_esdhc2>;
122 cd-gpios = <&gpio3 25 0>;
123 wp-gpios = <&gpio2 19 0>;
124 vmmc-supply = <&reg_3p3v>;
125 status = "okay";
126};
127
128&i2c3 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_i2c3>;
131 status = "okay";
132
133 sgtl5000: codec@0a {
134 compatible = "fsl,sgtl5000";
135 reg = <0x0a>;
136 VDDA-supply = <&reg_3p3v>;
137 VDDIO-supply = <&reg_3p3v>;
138 clocks = <&clks 150>;
139 };
140};
141
142&kpp {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_kpp_1>;
145 linux,keymap = <
146 0x0203003b /* KEY_F1 */
147 0x0603003c /* KEY_F2 */
148 0x0207003d /* KEY_F3 */
149 0x0607003e /* KEY_F4 */
150 >;
151 keypad,num-rows = <8>;
152 keypad,num-columns = <1>;
153 status = "okay";
154};
155
156&ssi2 {
157 fsl,mode = "i2s-slave";
158 status = "okay";
159};
diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
new file mode 100644
index 000000000000..ba689fbd0e41
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
@@ -0,0 +1,277 @@
1/*
2 * Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "imx53.dtsi"
13
14/ {
15 model = "Voipac i.MX53 X53-DMM-668";
16 compatible = "voipac,imx53-dmm-668", "fsl,imx53";
17
18 memory@70000000 {
19 device_type = "memory";
20 reg = <0x70000000 0x20000000>;
21 };
22
23 memory@b0000000 {
24 device_type = "memory";
25 reg = <0xb0000000 0x20000000>;
26 };
27
28 regulators {
29 compatible = "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 reg_3p3v: regulator@0 {
34 compatible = "regulator-fixed";
35 reg = <0>;
36 regulator-name = "3P3V";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-always-on;
40 };
41
42 reg_usb_vbus: regulator@1 {
43 compatible = "regulator-fixed";
44 reg = <1>;
45 regulator-name = "usb_vbus";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 gpio = <&gpio3 31 0>; /* PEN */
49 enable-active-high;
50 };
51 };
52};
53
54&iomuxc {
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_hog>;
57
58 imx53-voipac {
59 pinctrl_hog: hoggrp {
60 fsl,pins = <
61 /* Make DA9053 regulator functional */
62 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
63 /* FEC Power enable */
64 MX53_PAD_GPIO_11__GPIO4_1 0x80000000
65 /* FEC RST */
66 MX53_PAD_GPIO_12__GPIO4_2 0x80000000
67 >;
68 };
69
70 pinctrl_ecspi1: ecspi1grp {
71 fsl,pins = <
72 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
73 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
74 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
75 >;
76 };
77
78 pinctrl_fec: fecgrp {
79 fsl,pins = <
80 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
81 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
82 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
83 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
84 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
85 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
86 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
87 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
88 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
89 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
90 >;
91 };
92
93 pinctrl_i2c1: i2c1grp {
94 fsl,pins = <
95 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
96 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
97 >;
98 };
99
100 pinctrl_uart1: uart1grp {
101 fsl,pins = <
102 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
103 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
104 >;
105 };
106
107 pinctrl_nand: nandgrp {
108 fsl,pins = <
109 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
110 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
111 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
112 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
113 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
114 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
115 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
116 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
117 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
118 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
119 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
120 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
121 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
122 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
123 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
124 >;
125 };
126 };
127};
128
129&ecspi1 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_ecspi1>;
132 fsl,spi-num-chipselects = <4>;
133 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>;
134 status = "okay";
135};
136
137&fec {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_fec>;
140 phy-mode = "rmii";
141 phy-reset-gpios = <&gpio4 2 0>;
142 status = "okay";
143};
144
145&i2c1 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_i2c1>;
148 status = "okay";
149
150 pmic: dialog@48 {
151 compatible = "dlg,da9053-aa", "dlg,da9052";
152 reg = <0x48>;
153 interrupt-parent = <&gpio7>;
154 interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
155
156 regulators {
157 buck1_reg: buck1 {
158 regulator-name = "BUCKCORE";
159 regulator-min-microvolt = <1200000>;
160 regulator-max-microvolt = <1400000>;
161 regulator-always-on;
162 };
163
164 buck2_reg: buck2 {
165 regulator-name = "BUCKPRO";
166 regulator-min-microvolt = <900000>;
167 regulator-max-microvolt = <1350000>;
168 regulator-always-on;
169 };
170
171 buck3_reg: buck3 {
172 regulator-name = "BUCKMEM";
173 regulator-min-microvolt = <1420000>;
174 regulator-max-microvolt = <1580000>;
175 regulator-always-on;
176 };
177
178 buck4_reg: buck4 {
179 regulator-name = "BUCKPERI";
180 regulator-min-microvolt = <2370000>;
181 regulator-max-microvolt = <2630000>;
182 regulator-always-on;
183 };
184
185 ldo1_reg: ldo1 {
186 regulator-name = "ldo1_1v3";
187 regulator-min-microvolt = <1250000>;
188 regulator-max-microvolt = <1350000>;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192
193 ldo2_reg: ldo2 {
194 regulator-name = "ldo2_1v3";
195 regulator-min-microvolt = <1250000>;
196 regulator-max-microvolt = <1350000>;
197 regulator-always-on;
198 };
199
200 ldo3_reg: ldo3 {
201 regulator-name = "ldo3_3v3";
202 regulator-min-microvolt = <3250000>;
203 regulator-max-microvolt = <3350000>;
204 regulator-always-on;
205 };
206
207 ldo4_reg: ldo4 {
208 regulator-name = "ldo4_2v775";
209 regulator-min-microvolt = <2770000>;
210 regulator-max-microvolt = <2780000>;
211 regulator-always-on;
212 };
213
214 ldo5_reg: ldo5 {
215 regulator-name = "ldo5_3v3";
216 regulator-min-microvolt = <3250000>;
217 regulator-max-microvolt = <3350000>;
218 regulator-always-on;
219 };
220
221 ldo6_reg: ldo6 {
222 regulator-name = "ldo6_1v3";
223 regulator-min-microvolt = <1250000>;
224 regulator-max-microvolt = <1350000>;
225 regulator-always-on;
226 };
227
228 ldo7_reg: ldo7 {
229 regulator-name = "ldo7_2v75";
230 regulator-min-microvolt = <2700000>;
231 regulator-max-microvolt = <2800000>;
232 regulator-always-on;
233 };
234
235 ldo8_reg: ldo8 {
236 regulator-name = "ldo8_1v8";
237 regulator-min-microvolt = <1750000>;
238 regulator-max-microvolt = <1850000>;
239 regulator-always-on;
240 };
241
242 ldo9_reg: ldo9 {
243 regulator-name = "ldo9_1v5";
244 regulator-min-microvolt = <1450000>;
245 regulator-max-microvolt = <1550000>;
246 regulator-always-on;
247 };
248
249 ldo10_reg: ldo10 {
250 regulator-name = "ldo10_1v3";
251 regulator-min-microvolt = <1250000>;
252 regulator-max-microvolt = <1350000>;
253 regulator-always-on;
254 };
255 };
256 };
257};
258
259&nfc {
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_nand>;
262 nand-bus-width = <8>;
263 nand-ecc-mode = "hw";
264 status = "okay";
265};
266
267&uart1 {
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_uart1>;
270 status = "okay";
271};
272
273&usbh1 {
274 vbus-supply = <&reg_usb_vbus>;
275 phy_type = "utmi";
276 status = "okay";
277};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 4307e80b2d2e..b57ab57740f6 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -12,6 +12,9 @@
12 12
13#include "skeleton.dtsi" 13#include "skeleton.dtsi"
14#include "imx53-pinfunc.h" 14#include "imx53-pinfunc.h"
15#include <dt-bindings/clock/imx5-clock.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
15 18
16/ { 19/ {
17 aliases { 20 aliases {
@@ -25,6 +28,10 @@
25 i2c0 = &i2c1; 28 i2c0 = &i2c1;
26 i2c1 = &i2c2; 29 i2c1 = &i2c2;
27 i2c2 = &i2c3; 30 i2c2 = &i2c3;
31 mmc0 = &esdhc1;
32 mmc1 = &esdhc2;
33 mmc2 = &esdhc3;
34 mmc3 = &esdhc4;
28 serial0 = &uart1; 35 serial0 = &uart1;
29 serial1 = &uart2; 36 serial1 = &uart2;
30 serial2 = &uart3; 37 serial2 = &uart3;
@@ -45,6 +52,11 @@
45 }; 52 };
46 }; 53 };
47 54
55 display-subsystem {
56 compatible = "fsl,imx-display-subsystem";
57 ports = <&ipu_di0>, <&ipu_di1>;
58 };
59
48 tzic: tz-interrupt-controller@0fffc000 { 60 tzic: tz-interrupt-controller@0fffc000 {
49 compatible = "fsl,imx53-tzic", "fsl,tzic"; 61 compatible = "fsl,imx53-tzic", "fsl,tzic";
50 interrupt-controller; 62 interrupt-controller;
@@ -84,14 +96,63 @@
84 interrupt-parent = <&tzic>; 96 interrupt-parent = <&tzic>;
85 ranges; 97 ranges;
86 98
99 sata: sata@10000000 {
100 compatible = "fsl,imx53-ahci";
101 reg = <0x10000000 0x1000>;
102 interrupts = <28>;
103 clocks = <&clks IMX5_CLK_SATA_GATE>,
104 <&clks IMX5_CLK_SATA_REF>,
105 <&clks IMX5_CLK_AHB>;
106 clock-names = "sata_gate", "sata_ref", "ahb";
107 status = "disabled";
108 };
109
87 ipu: ipu@18000000 { 110 ipu: ipu@18000000 {
88 #crtc-cells = <1>; 111 #address-cells = <1>;
112 #size-cells = <0>;
89 compatible = "fsl,imx53-ipu"; 113 compatible = "fsl,imx53-ipu";
90 reg = <0x18000000 0x080000000>; 114 reg = <0x18000000 0x080000000>;
91 interrupts = <11 10>; 115 interrupts = <11 10>;
92 clocks = <&clks 59>, <&clks 110>, <&clks 61>; 116 clocks = <&clks IMX5_CLK_IPU_GATE>,
117 <&clks IMX5_CLK_IPU_DI0_GATE>,
118 <&clks IMX5_CLK_IPU_DI1_GATE>;
93 clock-names = "bus", "di0", "di1"; 119 clock-names = "bus", "di0", "di1";
94 resets = <&src 2>; 120 resets = <&src 2>;
121
122 ipu_di0: port@2 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <2>;
126
127 ipu_di0_disp0: endpoint@0 {
128 reg = <0>;
129 };
130
131 ipu_di0_lvds0: endpoint@1 {
132 reg = <1>;
133 remote-endpoint = <&lvds0_in>;
134 };
135 };
136
137 ipu_di1: port@3 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 reg = <3>;
141
142 ipu_di1_disp1: endpoint@0 {
143 reg = <0>;
144 };
145
146 ipu_di1_lvds1: endpoint@1 {
147 reg = <1>;
148 remote-endpoint = <&lvds1_in>;
149 };
150
151 ipu_di1_tve: endpoint@2 {
152 reg = <2>;
153 remote-endpoint = <&tve_in>;
154 };
155 };
95 }; 156 };
96 157
97 aips@50000000 { /* AIPS1 */ 158 aips@50000000 { /* AIPS1 */
@@ -112,7 +173,9 @@
112 compatible = "fsl,imx53-esdhc"; 173 compatible = "fsl,imx53-esdhc";
113 reg = <0x50004000 0x4000>; 174 reg = <0x50004000 0x4000>;
114 interrupts = <1>; 175 interrupts = <1>;
115 clocks = <&clks 44>, <&clks 0>, <&clks 71>; 176 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
177 <&clks IMX5_CLK_DUMMY>,
178 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
116 clock-names = "ipg", "ahb", "per"; 179 clock-names = "ipg", "ahb", "per";
117 bus-width = <4>; 180 bus-width = <4>;
118 status = "disabled"; 181 status = "disabled";
@@ -122,7 +185,9 @@
122 compatible = "fsl,imx53-esdhc"; 185 compatible = "fsl,imx53-esdhc";
123 reg = <0x50008000 0x4000>; 186 reg = <0x50008000 0x4000>;
124 interrupts = <2>; 187 interrupts = <2>;
125 clocks = <&clks 45>, <&clks 0>, <&clks 72>; 188 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
189 <&clks IMX5_CLK_DUMMY>,
190 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
126 clock-names = "ipg", "ahb", "per"; 191 clock-names = "ipg", "ahb", "per";
127 bus-width = <4>; 192 bus-width = <4>;
128 status = "disabled"; 193 status = "disabled";
@@ -132,7 +197,8 @@
132 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 197 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
133 reg = <0x5000c000 0x4000>; 198 reg = <0x5000c000 0x4000>;
134 interrupts = <33>; 199 interrupts = <33>;
135 clocks = <&clks 32>, <&clks 33>; 200 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
201 <&clks IMX5_CLK_UART3_PER_GATE>;
136 clock-names = "ipg", "per"; 202 clock-names = "ipg", "per";
137 status = "disabled"; 203 status = "disabled";
138 }; 204 };
@@ -143,16 +209,19 @@
143 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 209 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
144 reg = <0x50010000 0x4000>; 210 reg = <0x50010000 0x4000>;
145 interrupts = <36>; 211 interrupts = <36>;
146 clocks = <&clks 51>, <&clks 52>; 212 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
213 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
147 clock-names = "ipg", "per"; 214 clock-names = "ipg", "per";
148 status = "disabled"; 215 status = "disabled";
149 }; 216 };
150 217
151 ssi2: ssi@50014000 { 218 ssi2: ssi@50014000 {
152 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 219 compatible = "fsl,imx53-ssi",
220 "fsl,imx51-ssi",
221 "fsl,imx21-ssi";
153 reg = <0x50014000 0x4000>; 222 reg = <0x50014000 0x4000>;
154 interrupts = <30>; 223 interrupts = <30>;
155 clocks = <&clks 49>; 224 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
156 dmas = <&sdma 24 1 0>, 225 dmas = <&sdma 24 1 0>,
157 <&sdma 25 1 0>; 226 <&sdma 25 1 0>;
158 dma-names = "rx", "tx"; 227 dma-names = "rx", "tx";
@@ -165,7 +234,9 @@
165 compatible = "fsl,imx53-esdhc"; 234 compatible = "fsl,imx53-esdhc";
166 reg = <0x50020000 0x4000>; 235 reg = <0x50020000 0x4000>;
167 interrupts = <3>; 236 interrupts = <3>;
168 clocks = <&clks 46>, <&clks 0>, <&clks 73>; 237 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
238 <&clks IMX5_CLK_DUMMY>,
239 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
169 clock-names = "ipg", "ahb", "per"; 240 clock-names = "ipg", "ahb", "per";
170 bus-width = <4>; 241 bus-width = <4>;
171 status = "disabled"; 242 status = "disabled";
@@ -175,7 +246,9 @@
175 compatible = "fsl,imx53-esdhc"; 246 compatible = "fsl,imx53-esdhc";
176 reg = <0x50024000 0x4000>; 247 reg = <0x50024000 0x4000>;
177 interrupts = <4>; 248 interrupts = <4>;
178 clocks = <&clks 47>, <&clks 0>, <&clks 74>; 249 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
250 <&clks IMX5_CLK_DUMMY>,
251 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
179 clock-names = "ipg", "ahb", "per"; 252 clock-names = "ipg", "ahb", "per";
180 bus-width = <4>; 253 bus-width = <4>;
181 status = "disabled"; 254 status = "disabled";
@@ -184,14 +257,14 @@
184 257
185 usbphy0: usbphy@0 { 258 usbphy0: usbphy@0 {
186 compatible = "usb-nop-xceiv"; 259 compatible = "usb-nop-xceiv";
187 clocks = <&clks 124>; 260 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
188 clock-names = "main_clk"; 261 clock-names = "main_clk";
189 status = "okay"; 262 status = "okay";
190 }; 263 };
191 264
192 usbphy1: usbphy@1 { 265 usbphy1: usbphy@1 {
193 compatible = "usb-nop-xceiv"; 266 compatible = "usb-nop-xceiv";
194 clocks = <&clks 125>; 267 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
195 clock-names = "main_clk"; 268 clock-names = "main_clk";
196 status = "okay"; 269 status = "okay";
197 }; 270 };
@@ -200,7 +273,7 @@
200 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 273 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
201 reg = <0x53f80000 0x0200>; 274 reg = <0x53f80000 0x0200>;
202 interrupts = <18>; 275 interrupts = <18>;
203 clocks = <&clks 108>; 276 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
204 fsl,usbmisc = <&usbmisc 0>; 277 fsl,usbmisc = <&usbmisc 0>;
205 fsl,usbphy = <&usbphy0>; 278 fsl,usbphy = <&usbphy0>;
206 status = "disabled"; 279 status = "disabled";
@@ -210,7 +283,7 @@
210 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 283 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
211 reg = <0x53f80200 0x0200>; 284 reg = <0x53f80200 0x0200>;
212 interrupts = <14>; 285 interrupts = <14>;
213 clocks = <&clks 108>; 286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
214 fsl,usbmisc = <&usbmisc 1>; 287 fsl,usbmisc = <&usbmisc 1>;
215 fsl,usbphy = <&usbphy1>; 288 fsl,usbphy = <&usbphy1>;
216 status = "disabled"; 289 status = "disabled";
@@ -220,7 +293,7 @@
220 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 293 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
221 reg = <0x53f80400 0x0200>; 294 reg = <0x53f80400 0x0200>;
222 interrupts = <16>; 295 interrupts = <16>;
223 clocks = <&clks 108>; 296 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
224 fsl,usbmisc = <&usbmisc 2>; 297 fsl,usbmisc = <&usbmisc 2>;
225 status = "disabled"; 298 status = "disabled";
226 }; 299 };
@@ -229,7 +302,7 @@
229 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 302 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
230 reg = <0x53f80600 0x0200>; 303 reg = <0x53f80600 0x0200>;
231 interrupts = <17>; 304 interrupts = <17>;
232 clocks = <&clks 108>; 305 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
233 fsl,usbmisc = <&usbmisc 3>; 306 fsl,usbmisc = <&usbmisc 3>;
234 status = "disabled"; 307 status = "disabled";
235 }; 308 };
@@ -238,7 +311,7 @@
238 #index-cells = <1>; 311 #index-cells = <1>;
239 compatible = "fsl,imx53-usbmisc"; 312 compatible = "fsl,imx53-usbmisc";
240 reg = <0x53f80800 0x200>; 313 reg = <0x53f80800 0x200>;
241 clocks = <&clks 108>; 314 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
242 }; 315 };
243 316
244 gpio1: gpio@53f84000 { 317 gpio1: gpio@53f84000 {
@@ -281,18 +354,26 @@
281 #interrupt-cells = <2>; 354 #interrupt-cells = <2>;
282 }; 355 };
283 356
357 kpp: kpp@53f94000 {
358 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
359 reg = <0x53f94000 0x4000>;
360 interrupts = <60>;
361 clocks = <&clks IMX5_CLK_DUMMY>;
362 status = "disabled";
363 };
364
284 wdog1: wdog@53f98000 { 365 wdog1: wdog@53f98000 {
285 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 366 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
286 reg = <0x53f98000 0x4000>; 367 reg = <0x53f98000 0x4000>;
287 interrupts = <58>; 368 interrupts = <58>;
288 clocks = <&clks 0>; 369 clocks = <&clks IMX5_CLK_DUMMY>;
289 }; 370 };
290 371
291 wdog2: wdog@53f9c000 { 372 wdog2: wdog@53f9c000 {
292 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 373 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
293 reg = <0x53f9c000 0x4000>; 374 reg = <0x53f9c000 0x4000>;
294 interrupts = <59>; 375 interrupts = <59>;
295 clocks = <&clks 0>; 376 clocks = <&clks IMX5_CLK_DUMMY>;
296 status = "disabled"; 377 status = "disabled";
297 }; 378 };
298 379
@@ -300,521 +381,14 @@
300 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; 381 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
301 reg = <0x53fa0000 0x4000>; 382 reg = <0x53fa0000 0x4000>;
302 interrupts = <39>; 383 interrupts = <39>;
303 clocks = <&clks 36>, <&clks 41>; 384 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
385 <&clks IMX5_CLK_GPT_HF_GATE>;
304 clock-names = "ipg", "per"; 386 clock-names = "ipg", "per";
305 }; 387 };
306 388
307 iomuxc: iomuxc@53fa8000 { 389 iomuxc: iomuxc@53fa8000 {
308 compatible = "fsl,imx53-iomuxc"; 390 compatible = "fsl,imx53-iomuxc";
309 reg = <0x53fa8000 0x4000>; 391 reg = <0x53fa8000 0x4000>;
310
311 audmux {
312 pinctrl_audmux_1: audmuxgrp-1 {
313 fsl,pins = <
314 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
315 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
316 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
317 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
318 >;
319 };
320
321 pinctrl_audmux_2: audmuxgrp-2 {
322 fsl,pins = <
323 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
324 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
325 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
326 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
327 >;
328 };
329
330 pinctrl_audmux_3: audmuxgrp-3 {
331 fsl,pins = <
332 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
333 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
334 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
335 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
336 >;
337 };
338 };
339
340 fec {
341 pinctrl_fec_1: fecgrp-1 {
342 fsl,pins = <
343 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
344 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
345 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
346 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
347 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
348 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
349 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
350 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
351 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
352 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
353 >;
354 };
355
356 pinctrl_fec_2: fecgrp-2 {
357 fsl,pins = <
358 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
359 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
360 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
361 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
362 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
363 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
364 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
365 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
366 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
367 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
368 MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
369 MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
370 MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
371 MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
372 MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
373 MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
374 MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
375 MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
376 >;
377 };
378 };
379
380 csi {
381 pinctrl_csi_1: csigrp-1 {
382 fsl,pins = <
383 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
384 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
385 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
386 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
387 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
388 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
389 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
390 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
391 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
392 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
393 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
394 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
395 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
396 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
397 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
398 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
399 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
400 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
401 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
402 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
403 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
404 >;
405 };
406
407 pinctrl_csi_2: csigrp-2 {
408 fsl,pins = <
409 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
410 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
411 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
412 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
413 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
414 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
415 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
416 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
417 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
418 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
419 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
420 >;
421 };
422 };
423
424 cspi {
425 pinctrl_cspi_1: cspigrp-1 {
426 fsl,pins = <
427 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
428 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
429 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
430 >;
431 };
432
433 pinctrl_cspi_2: cspigrp-2 {
434 fsl,pins = <
435 MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
436 MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
437 MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
438 >;
439 };
440 };
441
442 ecspi1 {
443 pinctrl_ecspi1_1: ecspi1grp-1 {
444 fsl,pins = <
445 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
446 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
447 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
448 >;
449 };
450
451 pinctrl_ecspi1_2: ecspi1grp-2 {
452 fsl,pins = <
453 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
454 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
455 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
456 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
457 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
458 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
459 >;
460 };
461 };
462
463 ecspi2 {
464 pinctrl_ecspi2_1: ecspi2grp-1 {
465 fsl,pins = <
466 MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
467 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
468 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
469 >;
470 };
471 };
472
473 esdhc1 {
474 pinctrl_esdhc1_1: esdhc1grp-1 {
475 fsl,pins = <
476 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
477 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
478 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
479 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
480 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
481 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
482 >;
483 };
484
485 pinctrl_esdhc1_2: esdhc1grp-2 {
486 fsl,pins = <
487 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
488 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
489 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
490 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
491 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
492 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
493 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
494 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
495 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
496 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
497 >;
498 };
499 };
500
501 esdhc2 {
502 pinctrl_esdhc2_1: esdhc2grp-1 {
503 fsl,pins = <
504 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
505 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
506 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
507 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
508 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
509 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
510 >;
511 };
512 };
513
514 esdhc3 {
515 pinctrl_esdhc3_1: esdhc3grp-1 {
516 fsl,pins = <
517 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
518 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
519 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
520 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
521 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
522 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
523 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
524 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
525 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
526 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
527 >;
528 };
529 };
530
531 can1 {
532 pinctrl_can1_1: can1grp-1 {
533 fsl,pins = <
534 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
535 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
536 >;
537 };
538
539 pinctrl_can1_2: can1grp-2 {
540 fsl,pins = <
541 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
542 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
543 >;
544 };
545
546 pinctrl_can1_3: can1grp-3 {
547 fsl,pins = <
548 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
549 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
550 >;
551 };
552 };
553
554 can2 {
555 pinctrl_can2_1: can2grp-1 {
556 fsl,pins = <
557 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
558 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
559 >;
560 };
561 };
562
563 i2c1 {
564 pinctrl_i2c1_1: i2c1grp-1 {
565 fsl,pins = <
566 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
567 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
568 >;
569 };
570
571 pinctrl_i2c1_2: i2c1grp-2 {
572 fsl,pins = <
573 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
574 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
575 >;
576 };
577 };
578
579 i2c2 {
580 pinctrl_i2c2_1: i2c2grp-1 {
581 fsl,pins = <
582 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
583 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
584 >;
585 };
586
587 pinctrl_i2c2_2: i2c2grp-2 {
588 fsl,pins = <
589 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
590 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
591 >;
592 };
593 };
594
595 i2c3 {
596 pinctrl_i2c3_1: i2c3grp-1 {
597 fsl,pins = <
598 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
599 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
600 >;
601 };
602 };
603
604 ipu_disp0 {
605 pinctrl_ipu_disp0_1: ipudisp0grp-1 {
606 fsl,pins = <
607 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
608 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
609 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
610 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
611 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
612 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
613 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
614 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
615 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
616 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
617 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
618 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
619 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
620 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
621 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
622 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
623 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
624 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
625 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
626 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
627 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
628 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
629 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
630 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
631 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
632 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
633 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
634 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
635 >;
636 };
637 };
638
639 ipu_disp1 {
640 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
641 fsl,pins = <
642 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
643 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
644 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
645 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
646 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
647 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
648 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
649 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
650 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
651 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
652 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
653 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
654 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
655 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
656 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
657 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
658 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
659 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
660 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
661 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
662 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
663 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
664 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
665 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
666 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
667 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
668 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
669 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
670 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
671 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
672 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
673 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
674 >;
675 };
676 };
677
678 ipu_disp2 {
679 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
680 fsl,pins = <
681 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
682 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
683 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
684 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
685 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
686 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
687 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
688 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
689 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
690 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
691 >;
692 };
693 };
694
695 nand {
696 pinctrl_nand_1: nandgrp-1 {
697 fsl,pins = <
698 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
699 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
700 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
701 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
702 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
703 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
704 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
705 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
706 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
707 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
708 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
709 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
710 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
711 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
712 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
713 >;
714 };
715 };
716
717 owire {
718 pinctrl_owire_1: owiregrp-1 {
719 fsl,pins = <
720 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
721 >;
722 };
723 };
724
725 pwm1 {
726 pinctrl_pwm1_1: pwm1grp-1 {
727 fsl,pins = <
728 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
729 >;
730 };
731 };
732
733 pwm2 {
734 pinctrl_pwm2_1: pwm2grp-1 {
735 fsl,pins = <
736 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
737 >;
738 };
739 };
740
741 uart1 {
742 pinctrl_uart1_1: uart1grp-1 {
743 fsl,pins = <
744 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
745 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
746 >;
747 };
748
749 pinctrl_uart1_2: uart1grp-2 {
750 fsl,pins = <
751 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
752 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
753 >;
754 };
755
756 pinctrl_uart1_3: uart1grp-3 {
757 fsl,pins = <
758 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
759 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
760 >;
761 };
762 };
763
764 uart2 {
765 pinctrl_uart2_1: uart2grp-1 {
766 fsl,pins = <
767 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
768 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
769 >;
770 };
771
772 pinctrl_uart2_2: uart2grp-2 {
773 fsl,pins = <
774 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
775 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
776 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
777 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
778 >;
779 };
780 };
781
782 uart3 {
783 pinctrl_uart3_1: uart3grp-1 {
784 fsl,pins = <
785 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
786 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
787 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
788 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
789 >;
790 };
791
792 pinctrl_uart3_2: uart3grp-2 {
793 fsl,pins = <
794 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
795 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
796 >;
797 };
798
799 };
800
801 uart4 {
802 pinctrl_uart4_1: uart4grp-1 {
803 fsl,pins = <
804 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
805 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
806 >;
807 };
808 };
809
810 uart5 {
811 pinctrl_uart5_1: uart5grp-1 {
812 fsl,pins = <
813 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
814 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
815 >;
816 };
817 };
818 }; 392 };
819 393
820 gpr: iomuxc-gpr@53fa8000 { 394 gpr: iomuxc-gpr@53fa8000 {
@@ -828,9 +402,12 @@
828 compatible = "fsl,imx53-ldb"; 402 compatible = "fsl,imx53-ldb";
829 reg = <0x53fa8008 0x4>; 403 reg = <0x53fa8008 0x4>;
830 gpr = <&gpr>; 404 gpr = <&gpr>;
831 clocks = <&clks 122>, <&clks 120>, 405 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
832 <&clks 115>, <&clks 116>, 406 <&clks IMX5_CLK_LDB_DI1_SEL>,
833 <&clks 123>, <&clks 85>; 407 <&clks IMX5_CLK_IPU_DI0_SEL>,
408 <&clks IMX5_CLK_IPU_DI1_SEL>,
409 <&clks IMX5_CLK_LDB_DI0_GATE>,
410 <&clks IMX5_CLK_LDB_DI1_GATE>;
834 clock-names = "di0_pll", "di1_pll", 411 clock-names = "di0_pll", "di1_pll",
835 "di0_sel", "di1_sel", 412 "di0_sel", "di1_sel",
836 "di0", "di1"; 413 "di0", "di1";
@@ -838,14 +415,24 @@
838 415
839 lvds-channel@0 { 416 lvds-channel@0 {
840 reg = <0>; 417 reg = <0>;
841 crtcs = <&ipu 0>;
842 status = "disabled"; 418 status = "disabled";
419
420 port {
421 lvds0_in: endpoint {
422 remote-endpoint = <&ipu_di0_lvds0>;
423 };
424 };
843 }; 425 };
844 426
845 lvds-channel@1 { 427 lvds-channel@1 {
846 reg = <1>; 428 reg = <1>;
847 crtcs = <&ipu 1>;
848 status = "disabled"; 429 status = "disabled";
430
431 port {
432 lvds1_in: endpoint {
433 remote-endpoint = <&ipu_di0_lvds0>;
434 };
435 };
849 }; 436 };
850 }; 437 };
851 438
@@ -853,7 +440,8 @@
853 #pwm-cells = <2>; 440 #pwm-cells = <2>;
854 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 441 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
855 reg = <0x53fb4000 0x4000>; 442 reg = <0x53fb4000 0x4000>;
856 clocks = <&clks 37>, <&clks 38>; 443 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
444 <&clks IMX5_CLK_PWM1_HF_GATE>;
857 clock-names = "ipg", "per"; 445 clock-names = "ipg", "per";
858 interrupts = <61>; 446 interrupts = <61>;
859 }; 447 };
@@ -862,7 +450,8 @@
862 #pwm-cells = <2>; 450 #pwm-cells = <2>;
863 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 451 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
864 reg = <0x53fb8000 0x4000>; 452 reg = <0x53fb8000 0x4000>;
865 clocks = <&clks 39>, <&clks 40>; 453 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
454 <&clks IMX5_CLK_PWM2_HF_GATE>;
866 clock-names = "ipg", "per"; 455 clock-names = "ipg", "per";
867 interrupts = <94>; 456 interrupts = <94>;
868 }; 457 };
@@ -871,7 +460,8 @@
871 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 460 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
872 reg = <0x53fbc000 0x4000>; 461 reg = <0x53fbc000 0x4000>;
873 interrupts = <31>; 462 interrupts = <31>;
874 clocks = <&clks 28>, <&clks 29>; 463 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
464 <&clks IMX5_CLK_UART1_PER_GATE>;
875 clock-names = "ipg", "per"; 465 clock-names = "ipg", "per";
876 status = "disabled"; 466 status = "disabled";
877 }; 467 };
@@ -880,7 +470,8 @@
880 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 470 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
881 reg = <0x53fc0000 0x4000>; 471 reg = <0x53fc0000 0x4000>;
882 interrupts = <32>; 472 interrupts = <32>;
883 clocks = <&clks 30>, <&clks 31>; 473 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
474 <&clks IMX5_CLK_UART2_PER_GATE>;
884 clock-names = "ipg", "per"; 475 clock-names = "ipg", "per";
885 status = "disabled"; 476 status = "disabled";
886 }; 477 };
@@ -889,7 +480,8 @@
889 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 480 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
890 reg = <0x53fc8000 0x4000>; 481 reg = <0x53fc8000 0x4000>;
891 interrupts = <82>; 482 interrupts = <82>;
892 clocks = <&clks 158>, <&clks 157>; 483 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
484 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
893 clock-names = "ipg", "per"; 485 clock-names = "ipg", "per";
894 status = "disabled"; 486 status = "disabled";
895 }; 487 };
@@ -898,7 +490,8 @@
898 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 490 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
899 reg = <0x53fcc000 0x4000>; 491 reg = <0x53fcc000 0x4000>;
900 interrupts = <83>; 492 interrupts = <83>;
901 clocks = <&clks 87>, <&clks 86>; 493 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
494 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
902 clock-names = "ipg", "per"; 495 clock-names = "ipg", "per";
903 status = "disabled"; 496 status = "disabled";
904 }; 497 };
@@ -952,7 +545,7 @@
952 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 545 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
953 reg = <0x53fec000 0x4000>; 546 reg = <0x53fec000 0x4000>;
954 interrupts = <64>; 547 interrupts = <64>;
955 clocks = <&clks 88>; 548 clocks = <&clks IMX5_CLK_I2C3_GATE>;
956 status = "disabled"; 549 status = "disabled";
957 }; 550 };
958 551
@@ -960,7 +553,8 @@
960 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 553 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
961 reg = <0x53ff0000 0x4000>; 554 reg = <0x53ff0000 0x4000>;
962 interrupts = <13>; 555 interrupts = <13>;
963 clocks = <&clks 65>, <&clks 66>; 556 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
557 <&clks IMX5_CLK_UART4_PER_GATE>;
964 clock-names = "ipg", "per"; 558 clock-names = "ipg", "per";
965 status = "disabled"; 559 status = "disabled";
966 }; 560 };
@@ -977,14 +571,15 @@
977 compatible = "fsl,imx53-iim", "fsl,imx27-iim"; 571 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
978 reg = <0x63f98000 0x4000>; 572 reg = <0x63f98000 0x4000>;
979 interrupts = <69>; 573 interrupts = <69>;
980 clocks = <&clks 107>; 574 clocks = <&clks IMX5_CLK_IIM_GATE>;
981 }; 575 };
982 576
983 uart5: serial@63f90000 { 577 uart5: serial@63f90000 {
984 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 578 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
985 reg = <0x63f90000 0x4000>; 579 reg = <0x63f90000 0x4000>;
986 interrupts = <86>; 580 interrupts = <86>;
987 clocks = <&clks 67>, <&clks 68>; 581 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
582 <&clks IMX5_CLK_UART5_PER_GATE>;
988 clock-names = "ipg", "per"; 583 clock-names = "ipg", "per";
989 status = "disabled"; 584 status = "disabled";
990 }; 585 };
@@ -992,7 +587,7 @@
992 owire: owire@63fa4000 { 587 owire: owire@63fa4000 {
993 compatible = "fsl,imx53-owire", "fsl,imx21-owire"; 588 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
994 reg = <0x63fa4000 0x4000>; 589 reg = <0x63fa4000 0x4000>;
995 clocks = <&clks 159>; 590 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
996 status = "disabled"; 591 status = "disabled";
997 }; 592 };
998 593
@@ -1002,7 +597,8 @@
1002 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 597 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
1003 reg = <0x63fac000 0x4000>; 598 reg = <0x63fac000 0x4000>;
1004 interrupts = <37>; 599 interrupts = <37>;
1005 clocks = <&clks 53>, <&clks 54>; 600 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
601 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
1006 clock-names = "ipg", "per"; 602 clock-names = "ipg", "per";
1007 status = "disabled"; 603 status = "disabled";
1008 }; 604 };
@@ -1011,7 +607,8 @@
1011 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 607 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
1012 reg = <0x63fb0000 0x4000>; 608 reg = <0x63fb0000 0x4000>;
1013 interrupts = <6>; 609 interrupts = <6>;
1014 clocks = <&clks 56>, <&clks 56>; 610 clocks = <&clks IMX5_CLK_SDMA_GATE>,
611 <&clks IMX5_CLK_SDMA_GATE>;
1015 clock-names = "ipg", "ahb"; 612 clock-names = "ipg", "ahb";
1016 #dma-cells = <3>; 613 #dma-cells = <3>;
1017 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 614 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
@@ -1023,7 +620,8 @@
1023 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 620 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
1024 reg = <0x63fc0000 0x4000>; 621 reg = <0x63fc0000 0x4000>;
1025 interrupts = <38>; 622 interrupts = <38>;
1026 clocks = <&clks 55>, <&clks 55>; 623 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
624 <&clks IMX5_CLK_CSPI_IPG_GATE>;
1027 clock-names = "ipg", "per"; 625 clock-names = "ipg", "per";
1028 status = "disabled"; 626 status = "disabled";
1029 }; 627 };
@@ -1034,7 +632,7 @@
1034 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 632 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1035 reg = <0x63fc4000 0x4000>; 633 reg = <0x63fc4000 0x4000>;
1036 interrupts = <63>; 634 interrupts = <63>;
1037 clocks = <&clks 35>; 635 clocks = <&clks IMX5_CLK_I2C2_GATE>;
1038 status = "disabled"; 636 status = "disabled";
1039 }; 637 };
1040 638
@@ -1044,15 +642,16 @@
1044 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 642 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1045 reg = <0x63fc8000 0x4000>; 643 reg = <0x63fc8000 0x4000>;
1046 interrupts = <62>; 644 interrupts = <62>;
1047 clocks = <&clks 34>; 645 clocks = <&clks IMX5_CLK_I2C1_GATE>;
1048 status = "disabled"; 646 status = "disabled";
1049 }; 647 };
1050 648
1051 ssi1: ssi@63fcc000 { 649 ssi1: ssi@63fcc000 {
1052 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 650 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
651 "fsl,imx21-ssi";
1053 reg = <0x63fcc000 0x4000>; 652 reg = <0x63fcc000 0x4000>;
1054 interrupts = <29>; 653 interrupts = <29>;
1055 clocks = <&clks 48>; 654 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
1056 dmas = <&sdma 28 0 0>, 655 dmas = <&sdma 28 0 0>,
1057 <&sdma 29 0 0>; 656 <&sdma 29 0 0>;
1058 dma-names = "rx", "tx"; 657 dma-names = "rx", "tx";
@@ -1071,15 +670,16 @@
1071 compatible = "fsl,imx53-nand"; 670 compatible = "fsl,imx53-nand";
1072 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; 671 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1073 interrupts = <8>; 672 interrupts = <8>;
1074 clocks = <&clks 60>; 673 clocks = <&clks IMX5_CLK_NFC_GATE>;
1075 status = "disabled"; 674 status = "disabled";
1076 }; 675 };
1077 676
1078 ssi3: ssi@63fe8000 { 677 ssi3: ssi@63fe8000 {
1079 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 678 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
679 "fsl,imx21-ssi";
1080 reg = <0x63fe8000 0x4000>; 680 reg = <0x63fe8000 0x4000>;
1081 interrupts = <96>; 681 interrupts = <96>;
1082 clocks = <&clks 50>; 682 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
1083 dmas = <&sdma 46 0 0>, 683 dmas = <&sdma 46 0 0>,
1084 <&sdma 47 0 0>; 684 <&sdma 47 0 0>;
1085 dma-names = "rx", "tx"; 685 dma-names = "rx", "tx";
@@ -1092,7 +692,9 @@
1092 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 692 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1093 reg = <0x63fec000 0x4000>; 693 reg = <0x63fec000 0x4000>;
1094 interrupts = <87>; 694 interrupts = <87>;
1095 clocks = <&clks 42>, <&clks 42>, <&clks 42>; 695 clocks = <&clks IMX5_CLK_FEC_GATE>,
696 <&clks IMX5_CLK_FEC_GATE>,
697 <&clks IMX5_CLK_FEC_GATE>;
1096 clock-names = "ipg", "ahb", "ptp"; 698 clock-names = "ipg", "ahb", "ptp";
1097 status = "disabled"; 699 status = "disabled";
1098 }; 700 };
@@ -1101,17 +703,24 @@
1101 compatible = "fsl,imx53-tve"; 703 compatible = "fsl,imx53-tve";
1102 reg = <0x63ff0000 0x1000>; 704 reg = <0x63ff0000 0x1000>;
1103 interrupts = <92>; 705 interrupts = <92>;
1104 clocks = <&clks 69>, <&clks 116>; 706 clocks = <&clks IMX5_CLK_TVE_GATE>,
707 <&clks IMX5_CLK_IPU_DI1_SEL>;
1105 clock-names = "tve", "di_sel"; 708 clock-names = "tve", "di_sel";
1106 crtcs = <&ipu 1>;
1107 status = "disabled"; 709 status = "disabled";
710
711 port {
712 tve_in: endpoint {
713 remote-endpoint = <&ipu_di1_tve>;
714 };
715 };
1108 }; 716 };
1109 717
1110 vpu: vpu@63ff4000 { 718 vpu: vpu@63ff4000 {
1111 compatible = "fsl,imx53-vpu"; 719 compatible = "fsl,imx53-vpu";
1112 reg = <0x63ff4000 0x1000>; 720 reg = <0x63ff4000 0x1000>;
1113 interrupts = <9>; 721 interrupts = <9>;
1114 clocks = <&clks 63>, <&clks 63>; 722 clocks = <&clks IMX5_CLK_VPU_GATE>,
723 <&clks IMX5_CLK_VPU_GATE>;
1115 clock-names = "per", "ahb"; 724 clock-names = "per", "ahb";
1116 iram = <&ocram>; 725 iram = <&ocram>;
1117 status = "disabled"; 726 status = "disabled";
@@ -1121,7 +730,7 @@
1121 ocram: sram@f8000000 { 730 ocram: sram@f8000000 {
1122 compatible = "mmio-sram"; 731 compatible = "mmio-sram";
1123 reg = <0xf8000000 0x20000>; 732 reg = <0xf8000000 0x20000>;
1124 clocks = <&clks 186>; 733 clocks = <&clks IMX5_CLK_OCRAM>;
1125 }; 734 };
1126 }; 735 };
1127}; 736};
diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
new file mode 100644
index 000000000000..994f96a3fb54
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2013 Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __DTS_V1__
13#define __DTS_V1__
14/dts-v1/;
15#endif
16
17#include "imx6dl.dtsi"
18#include "imx6qdl-dfi-fs700-m60.dtsi"
19
20/ {
21 model = "DFI FS700-M60-6DL i.MX6dl Q7 Board";
22 compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl";
23};
diff --git a/arch/arm/boot/dts/imx6dl-gw51xx.dts b/arch/arm/boot/dts/imx6dl-gw51xx.dts
new file mode 100644
index 000000000000..4bd055f4c930
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw51xx.dts
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6dl.dtsi"
14#include "imx6qdl-gw51xx.dtsi"
15
16/ {
17 model = "Gateworks Ventana i.MX6 DualLite GW51XX";
18 compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl";
19};
diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/imx6dl-gw52xx.dts
new file mode 100644
index 000000000000..c9136058f15e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw52xx.dts
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6dl.dtsi"
14#include "imx6qdl-gw52xx.dtsi"
15
16/ {
17 model = "Gateworks Ventana i.MX6 DualLite GW52XX";
18 compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
19};
diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/imx6dl-gw53xx.dts
new file mode 100644
index 000000000000..61818a14fde6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw53xx.dts
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6dl.dtsi"
14#include "imx6qdl-gw53xx.dtsi"
15
16/ {
17 model = "Gateworks Ventana i.MX6 DualLite GW53XX";
18 compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
19};
diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/imx6dl-gw54xx.dts
new file mode 100644
index 000000000000..ab38b6770a06
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw54xx.dts
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6dl.dtsi"
14#include "imx6qdl-gw54xx.dtsi"
15
16/ {
17 model = "Gateworks Ventana i.MX6 DualLite GW54XX";
18 compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
19};
diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts
new file mode 100644
index 000000000000..5f4d33ccc4b3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright 2013 Boundary Devices, Inc.
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15#include "imx6dl.dtsi"
16#include "imx6qdl-nitrogen6x.dtsi"
17
18/ {
19 model = "Freescale i.MX6 DualLite Nitrogen6x Board";
20 compatible = "fsl,imx6dl-nitrogen6x", "fsl,imx6dl";
21};
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
index b81a7a4ebab6..0ead323fdbd2 100644
--- a/arch/arm/boot/dts/imx6dl-pinfunc.h
+++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
@@ -755,6 +755,7 @@
755#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 755#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
756#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 756#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0
757#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 757#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
758#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609
758#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 759#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
759#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 760#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
760#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 761#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
@@ -950,6 +951,7 @@
950#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 951#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0
951#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 952#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0
952#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 953#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1
954#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0
953#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 955#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0
954#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 956#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0
955#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 957#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0
diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/imx6dl-sabrelite.dts
new file mode 100644
index 000000000000..2de04479dc35
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-sabrelite.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14#include "imx6dl.dtsi"
15#include "imx6qdl-sabrelite.dtsi"
16
17/ {
18 model = "Freescale i.MX6 DualLite SABRE Lite Board";
19 compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl";
20};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 9e8ae118fdd4..5c5f574330f9 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -8,6 +8,7 @@
8 * 8 *
9 */ 9 */
10 10
11#include <dt-bindings/interrupt-controller/irq.h>
11#include "imx6dl-pinfunc.h" 12#include "imx6dl-pinfunc.h"
12#include "imx6qdl.dtsi" 13#include "imx6qdl.dtsi"
13 14
@@ -21,6 +22,26 @@
21 device_type = "cpu"; 22 device_type = "cpu";
22 reg = <0>; 23 reg = <0>;
23 next-level-cache = <&L2>; 24 next-level-cache = <&L2>;
25 operating-points = <
26 /* kHz uV */
27 996000 1275000
28 792000 1175000
29 396000 1075000
30 >;
31 fsl,soc-operating-points = <
32 /* ARM kHz SOC-PU uV */
33 996000 1175000
34 792000 1175000
35 396000 1175000
36 >;
37 clock-latency = <61036>; /* two CLK32 periods */
38 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
39 <&clks 17>, <&clks 170>;
40 clock-names = "arm", "pll2_pfd2_396m", "step",
41 "pll1_sw", "pll1_sys";
42 arm-supply = <&reg_arm>;
43 pu-supply = <&reg_pu>;
44 soc-supply = <&reg_soc>;
24 }; 45 };
25 46
26 cpu@1 { 47 cpu@1 {
@@ -45,17 +66,17 @@
45 66
46 pxp: pxp@020f0000 { 67 pxp: pxp@020f0000 {
47 reg = <0x020f0000 0x4000>; 68 reg = <0x020f0000 0x4000>;
48 interrupts = <0 98 0x04>; 69 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
49 }; 70 };
50 71
51 epdc: epdc@020f4000 { 72 epdc: epdc@020f4000 {
52 reg = <0x020f4000 0x4000>; 73 reg = <0x020f4000 0x4000>;
53 interrupts = <0 97 0x04>; 74 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
54 }; 75 };
55 76
56 lcdif: lcdif@020f8000 { 77 lcdif: lcdif@020f8000 {
57 reg = <0x020f8000 0x4000>; 78 reg = <0x020f8000 0x4000>;
58 interrupts = <0 39 0x04>; 79 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
59 }; 80 };
60 }; 81 };
61 82
@@ -65,11 +86,20 @@
65 #size-cells = <0>; 86 #size-cells = <0>;
66 compatible = "fsl,imx1-i2c"; 87 compatible = "fsl,imx1-i2c";
67 reg = <0x021f8000 0x4000>; 88 reg = <0x021f8000 0x4000>;
68 interrupts = <0 35 0x04>; 89 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
69 status = "disabled"; 90 status = "disabled";
70 }; 91 };
71 }; 92 };
72 }; 93 };
94
95 display-subsystem {
96 compatible = "fsl,imx-display-subsystem";
97 ports = <&ipu1_di0>, <&ipu1_di1>;
98 };
99};
100
101&hdmi {
102 compatible = "fsl,imx6dl-hdmi";
73}; 103};
74 104
75&ldb { 105&ldb {
@@ -79,12 +109,4 @@
79 clock-names = "di0_pll", "di1_pll", 109 clock-names = "di0_pll", "di1_pll",
80 "di0_sel", "di1_sel", 110 "di0_sel", "di1_sel",
81 "di0", "di1"; 111 "di0", "di1";
82
83 lvds-channel@0 {
84 crtcs = <&ipu1 0>, <&ipu1 1>;
85 };
86
87 lvds-channel@1 {
88 crtcs = <&ipu1 0>, <&ipu1 1>;
89 };
90}; 112};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index edf1bd967164..78df05e9d1ce 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -23,14 +23,27 @@
23 23
24 regulators { 24 regulators {
25 compatible = "simple-bus"; 25 compatible = "simple-bus";
26 #address-cells = <1>;
27 #size-cells = <0>;
26 28
27 reg_3p3v: 3p3v { 29 reg_3p3v: regulator@0 {
28 compatible = "regulator-fixed"; 30 compatible = "regulator-fixed";
31 reg = <0>;
29 regulator-name = "3P3V"; 32 regulator-name = "3P3V";
30 regulator-min-microvolt = <3300000>; 33 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>; 34 regulator-max-microvolt = <3300000>;
32 regulator-always-on; 35 regulator-always-on;
33 }; 36 };
37
38 reg_usb_otg_vbus: regulator@1 {
39 compatible = "regulator-fixed";
40 reg = <1>;
41 regulator-name = "usb_otg_vbus";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
44 gpio = <&gpio3 22 0>;
45 enable-active-high;
46 };
34 }; 47 };
35 48
36 leds { 49 leds {
@@ -46,7 +59,7 @@
46 59
47&gpmi { 60&gpmi {
48 pinctrl-names = "default"; 61 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_gpmi_nand_1>; 62 pinctrl-0 = <&pinctrl_gpmi_nand>;
50 status = "disabled"; /* gpmi nand conflicts with SD */ 63 status = "disabled"; /* gpmi nand conflicts with SD */
51}; 64};
52 65
@@ -54,28 +67,131 @@
54 pinctrl-names = "default"; 67 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_hog>; 68 pinctrl-0 = <&pinctrl_hog>;
56 69
57 hog { 70 imx6q-arm2 {
58 pinctrl_hog: hoggrp { 71 pinctrl_hog: hoggrp {
59 fsl,pins = < 72 fsl,pins = <
60 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 73 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
61 >; 74 >;
62 }; 75 };
63 };
64 76
65 arm2 { 77 pinctrl_enet: enetgrp {
66 pinctrl_usdhc3_arm2: usdhc3grp-arm2 { 78 fsl,pins = <
79 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
80 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
81 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
82 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
83 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
84 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
85 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
86 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
87 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
88 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
89 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
90 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
91 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
92 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
93 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
94 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
95 >;
96 };
97
98 pinctrl_gpmi_nand: gpminandgrp {
99 fsl,pins = <
100 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
101 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
102 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
103 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
104 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
105 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
106 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
107 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
108 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
109 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
110 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
111 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
112 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
113 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
114 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
115 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
116 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
117 >;
118 };
119
120 pinctrl_uart2: uart2grp {
121 fsl,pins = <
122 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
123 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
124 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
125 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
126 >;
127 };
128
129 pinctrl_uart4: uart4grp {
130 fsl,pins = <
131 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
132 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
133 >;
134 };
135
136 pinctrl_usbotg: usbotggrp {
137 fsl,pins = <
138 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
139 >;
140 };
141
142 pinctrl_usdhc3: usdhc3grp {
143 fsl,pins = <
144 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
145 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
146 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
147 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
148 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
149 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
150 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
151 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
152 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
153 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
154 >;
155 };
156
157 pinctrl_usdhc3_cdwp: usdhc3cdwp {
67 fsl,pins = < 158 fsl,pins = <
68 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 159 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
69 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 160 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
70 >; 161 >;
71 }; 162 };
163
164 pinctrl_usdhc4: usdhc4grp {
165 fsl,pins = <
166 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
167 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
168 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
169 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
170 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
171 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
172 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
173 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
174 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
175 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
176 >;
177 };
72 }; 178 };
73}; 179};
74 180
75&fec { 181&fec {
76 pinctrl-names = "default"; 182 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_enet_2>; 183 pinctrl-0 = <&pinctrl_enet>;
78 phy-mode = "rgmii"; 184 phy-mode = "rgmii";
185 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
186 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
187 status = "okay";
188};
189
190&usbotg {
191 vbus-supply = <&reg_usb_otg_vbus>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_usbotg>;
194 disable-over-current;
79 status = "okay"; 195 status = "okay";
80}; 196};
81 197
@@ -84,8 +200,8 @@
84 wp-gpios = <&gpio6 14 0>; 200 wp-gpios = <&gpio6 14 0>;
85 vmmc-supply = <&reg_3p3v>; 201 vmmc-supply = <&reg_3p3v>;
86 pinctrl-names = "default"; 202 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_usdhc3_1 203 pinctrl-0 = <&pinctrl_usdhc3
88 &pinctrl_usdhc3_arm2>; 204 &pinctrl_usdhc3_cdwp>;
89 status = "okay"; 205 status = "okay";
90}; 206};
91 207
@@ -93,13 +209,13 @@
93 non-removable; 209 non-removable;
94 vmmc-supply = <&reg_3p3v>; 210 vmmc-supply = <&reg_3p3v>;
95 pinctrl-names = "default"; 211 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_usdhc4_1>; 212 pinctrl-0 = <&pinctrl_usdhc4>;
97 status = "okay"; 213 status = "okay";
98}; 214};
99 215
100&uart2 { 216&uart2 {
101 pinctrl-names = "default"; 217 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart2_2>; 218 pinctrl-0 = <&pinctrl_uart2>;
103 fsl,dte-mode; 219 fsl,dte-mode;
104 fsl,uart-has-rtscts; 220 fsl,uart-has-rtscts;
105 status = "okay"; 221 status = "okay";
@@ -107,6 +223,6 @@
107 223
108&uart4 { 224&uart4 {
109 pinctrl-names = "default"; 225 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_uart4_1>; 226 pinctrl-0 = <&pinctrl_uart4>;
111 status = "okay"; 227 status = "okay";
112}; 228};
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
new file mode 100644
index 000000000000..99b46f8030ad
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -0,0 +1,107 @@
1/*
2 * Copyright 2013 CompuLab Ltd.
3 *
4 * Author: Valentin Raevsky <valentin@compulab.co.il>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15#include "imx6q.dtsi"
16
17/ {
18 model = "CompuLab CM-FX6";
19 compatible = "compulab,cm-fx6", "fsl,imx6q";
20
21 memory {
22 reg = <0x10000000 0x80000000>;
23 };
24
25 leds {
26 compatible = "gpio-leds";
27
28 heartbeat-led {
29 label = "Heartbeat";
30 gpios = <&gpio2 31 0>;
31 linux,default-trigger = "heartbeat";
32 };
33 };
34};
35
36&fec {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_enet>;
39 phy-mode = "rgmii";
40 status = "okay";
41};
42
43&gpmi {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_gpmi_nand>;
46 status = "okay";
47};
48
49&iomuxc {
50 imx6q-cm-fx6 {
51 pinctrl_enet: enetgrp {
52 fsl,pins = <
53 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
54 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
55 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
56 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
57 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
58 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
59 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
60 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
61 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
62 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
63 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
64 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
65 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
66 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
67 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
68 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
69 >;
70 };
71
72 pinctrl_gpmi_nand: gpminandgrp {
73 fsl,pins = <
74 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
75 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
76 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
77 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
78 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
79 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
80 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
81 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
82 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
83 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
84 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
85 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
86 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
87 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
88 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
89 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
90 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
91 >;
92 };
93
94 pinctrl_uart4: uart4grp {
95 fsl,pins = <
96 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
97 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
98 >;
99 };
100 };
101};
102
103&uart4 {
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_uart4>;
106 status = "okay";
107};
diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
new file mode 100644
index 000000000000..fd0ad9a8866c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2013 Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __DTS_V1__
13#define __DTS_V1__
14/dts-v1/;
15#endif
16
17#include "imx6q.dtsi"
18#include "imx6qdl-dfi-fs700-m60.dtsi"
19
20/ {
21 model = "DFI FS700-M60-6QD i.MX6qd Q7 Board";
22 compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q";
23};
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
new file mode 100644
index 000000000000..a63bbb3d46bb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -0,0 +1,372 @@
1/*
2 * Copyright 2013 Data Modul AG
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13
14#include <dt-bindings/gpio/gpio.h>
15#include "imx6q.dtsi"
16
17/ {
18 model = "Data Modul eDM-QMX6 Board";
19 compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
20
21 aliases {
22 gpio7 = &stmpe_gpio;
23 };
24
25 memory {
26 reg = <0x10000000 0x80000000>;
27 };
28
29 regulators {
30 compatible = "simple-bus";
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 reg_3p3v: regulator@0 {
35 compatible = "regulator-fixed";
36 reg = <0>;
37 regulator-name = "3P3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 };
42
43 reg_usb_otg_vbus: regulator@1 {
44 compatible = "regulator-fixed";
45 reg = <1>;
46 regulator-name = "usb_otg_vbus";
47 regulator-min-microvolt = <5000000>;
48 regulator-max-microvolt = <5000000>;
49 gpio = <&gpio7 12 0>;
50 };
51
52 reg_usb_host1: regulator@2 {
53 compatible = "regulator-fixed";
54 reg = <2>;
55 regulator-name = "usb_host1_en";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 gpio = <&gpio3 31 0>;
59 enable-active-high;
60 };
61 };
62
63 gpio-leds {
64 compatible = "gpio-leds";
65
66 led-blue {
67 label = "blue";
68 gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>;
69 linux,default-trigger = "heartbeat";
70 };
71
72 led-green {
73 label = "green";
74 gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>;
75 };
76
77 led-pink {
78 label = "pink";
79 gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>;
80 };
81
82 led-red {
83 label = "red";
84 gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>;
85 };
86 };
87};
88
89&fec {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet>;
92 phy-mode = "rgmii";
93 phy-reset-gpios = <&gpio3 23 0>;
94 phy-supply = <&vgen2_1v2_eth>;
95 status = "okay";
96};
97
98&i2c2 {
99 clock-frequency = <100000>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c2
102 &pinctrl_stmpe>;
103 status = "okay";
104
105 pmic: pfuze100@08 {
106 compatible = "fsl,pfuze100";
107 reg = <0x08>;
108 interrupt-parent = <&gpio3>;
109 interrupts = <20 8>;
110
111 regulators {
112 sw1a_reg: sw1ab {
113 regulator-min-microvolt = <300000>;
114 regulator-max-microvolt = <1875000>;
115 regulator-boot-on;
116 regulator-always-on;
117 };
118
119 sw1c_reg: sw1c {
120 regulator-min-microvolt = <300000>;
121 regulator-max-microvolt = <1875000>;
122 regulator-boot-on;
123 regulator-always-on;
124 };
125
126 sw2_reg: sw2 {
127 regulator-min-microvolt = <800000>;
128 regulator-max-microvolt = <3300000>;
129 regulator-boot-on;
130 regulator-always-on;
131 };
132
133 sw3a_reg: sw3a {
134 regulator-min-microvolt = <400000>;
135 regulator-max-microvolt = <1975000>;
136 regulator-boot-on;
137 regulator-always-on;
138 };
139
140 sw3b_reg: sw3b {
141 regulator-min-microvolt = <400000>;
142 regulator-max-microvolt = <1975000>;
143 regulator-boot-on;
144 regulator-always-on;
145 };
146
147 sw4_reg: sw4 {
148 regulator-min-microvolt = <400000>;
149 regulator-max-microvolt = <1975000>;
150 regulator-always-on;
151 };
152
153 swbst_reg: swbst {
154 regulator-min-microvolt = <5000000>;
155 regulator-max-microvolt = <5150000>;
156 regulator-always-on;
157 };
158
159 snvs_reg: vsnvs {
160 regulator-min-microvolt = <1000000>;
161 regulator-max-microvolt = <3000000>;
162 regulator-boot-on;
163 regulator-always-on;
164 };
165
166 vref_reg: vrefddr {
167 regulator-boot-on;
168 regulator-always-on;
169 };
170
171 vgen1_reg: vgen1 {
172 regulator-min-microvolt = <800000>;
173 regulator-max-microvolt = <1550000>;
174 };
175
176 vgen2_1v2_eth: vgen2 {
177 regulator-min-microvolt = <800000>;
178 regulator-max-microvolt = <1550000>;
179 };
180
181 vdd_high_in: vgen3 {
182 regulator-min-microvolt = <1800000>;
183 regulator-max-microvolt = <3300000>;
184 regulator-boot-on;
185 regulator-always-on;
186 };
187
188 vgen4_reg: vgen4 {
189 regulator-min-microvolt = <1800000>;
190 regulator-max-microvolt = <3300000>;
191 regulator-always-on;
192 };
193
194 vgen5_reg: vgen5 {
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3300000>;
197 regulator-always-on;
198 };
199
200 vgen6_reg: vgen6 {
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <3300000>;
203 regulator-always-on;
204 };
205 };
206 };
207
208 stmpe: stmpe1601@40 {
209 compatible = "st,stmpe1601";
210 reg = <0x40>;
211 interrupts = <30 0>;
212 interrupt-parent = <&gpio3>;
213
214 stmpe_gpio: stmpe_gpio {
215 #gpio-cells = <2>;
216 compatible = "st,stmpe-gpio";
217 };
218 };
219
220 temp1: ad7414@4c {
221 compatible = "ad,ad7414";
222 reg = <0x4c>;
223 };
224
225 temp2: ad7414@4d {
226 compatible = "ad,ad7414";
227 reg = <0x4d>;
228 };
229
230 rtc: m41t62@68 {
231 compatible = "stm,m41t62";
232 reg = <0x68>;
233 };
234};
235
236&iomuxc {
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_hog>;
239
240 imx6q-dmo-edmqmx6 {
241 pinctrl_hog: hoggrp {
242 fsl,pins = <
243 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
244 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
245 >;
246 };
247
248 pinctrl_enet: enetgrp {
249 fsl,pins = <
250 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
251 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
252 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
253 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
254 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
255 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
256 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
257 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
258 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
259 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
260 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
261 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
262 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
263 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
264 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
265 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
266 >;
267 };
268
269 pinctrl_i2c2: i2c2grp {
270 fsl,pins = <
271 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
272 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
273 >;
274 };
275
276 pinctrl_stmpe: stmpegrp {
277 fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
278 };
279
280 pinctrl_uart1: uart1grp {
281 fsl,pins = <
282 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
283 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
284 >;
285 };
286
287 pinctrl_uart2: uart2grp {
288 fsl,pins = <
289 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
290 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
291 >;
292 };
293
294 pinctrl_usbotg: usbotggrp {
295 fsl,pins = <
296 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
297 >;
298 };
299
300 pinctrl_usdhc3: usdhc3grp {
301 fsl,pins = <
302 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
303 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
304 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
305 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
306 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
307 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
308 >;
309 };
310
311 pinctrl_usdhc4: usdhc4grp {
312 fsl,pins = <
313 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
314 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
315 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
316 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
317 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
318 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
319 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
320 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
321 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
322 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
323 >;
324 };
325 };
326};
327
328&sata {
329 status = "okay";
330};
331
332&uart1 {
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_uart1>;
335 status = "okay";
336};
337
338&uart2 {
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_uart2>;
341 status = "okay";
342};
343
344&usbh1 {
345 vbus-supply = <&reg_usb_host1>;
346 disable-over-current;
347 status = "okay";
348};
349
350&usbotg {
351 vbus-supply = <&reg_usb_otg_vbus>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_usbotg>;
354 disable-over-current;
355 status = "okay";
356};
357
358&usdhc3 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_usdhc3>;
361 vmmc-supply = <&reg_3p3v>;
362 status = "okay";
363};
364
365&usdhc4 {
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_usdhc4>;
368 vmmc-supply = <&reg_3p3v>;
369 non-removable;
370 bus-width = <8>;
371 status = "okay";
372};
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts
new file mode 100644
index 000000000000..4a9b4dc9afc0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -0,0 +1,171 @@
1/*
2 * Copyright (C) 2013 Philipp Zabel
3 *
4 * This file is licensed under the terms of the GNU General Public License
5 * version 2. This program is licensed "as is" without any warranty of any
6 * kind, whether express or implied.
7 */
8
9/dts-v1/;
10#include "imx6q.dtsi"
11
12/ {
13 model = "Zealz GK802";
14 compatible = "zealz,imx6q-gk802", "fsl,imx6q";
15
16 chosen {
17 linux,stdout-path = &uart4;
18 };
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 regulators {
25 compatible = "simple-bus";
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 reg_3p3v: regulator@0 {
30 compatible = "regulator-fixed";
31 reg = <0>;
32 regulator-name = "3P3V";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-always-on;
36 };
37 };
38
39 gpio-keys {
40 compatible = "gpio-keys";
41
42 recovery-button {
43 label = "recovery";
44 gpios = <&gpio3 16 1>;
45 linux,code = <0x198>; /* KEY_RESTART */
46 gpio-key,wakeup;
47 };
48 };
49};
50
51/* Internal I2C */
52&i2c2 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_i2c2>;
55 clock-frequency = <100000>;
56 status = "okay";
57
58 /* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */
59 eeprom: dm2016@51 {
60 compatible = "sdmc,dm2016";
61 reg = <0x51>;
62 };
63};
64
65/* External I2C via HDMI */
66&i2c3 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_i2c3>;
69 clock-frequency = <100000>;
70 status = "okay";
71};
72
73&iomuxc {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_hog>;
76
77 imx6q-gk802 {
78 pinctrl_hog: hoggrp {
79 fsl,pins = <
80 /* Recovery button, active-low */
81 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1
82 /* RTL8192CU enable GPIO, active-low */
83 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
84 >;
85 };
86
87 pinctrl_i2c2: i2c2grp {
88 fsl,pins = <
89 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
90 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
91 >;
92 };
93
94 pinctrl_i2c3: i2c3grp {
95 fsl,pins = <
96 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
97 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
98 >;
99 };
100
101 pinctrl_uart4: uart4grp {
102 fsl,pins = <
103 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
104 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
105 >;
106 };
107
108 pinctrl_usdhc3: usdhc3grp {
109 fsl,pins = <
110 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
111 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
112 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
113 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
114 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
115 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
116 >;
117 };
118
119 pinctrl_usdhc4: usdhc4grp {
120 fsl,pins = <
121 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
122 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
123 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
124 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
125 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
126 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
127 >;
128 };
129 };
130};
131
132&uart2 {
133 status = "okay";
134};
135
136&uart4 {
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_uart4>;
139 status = "okay";
140};
141
142/* External USB-A port (USBOTG) */
143&usbotg {
144 disable-over-current;
145 status = "okay";
146};
147
148/* Internal USB port (USBH1), connected to RTL8192CU */
149&usbh1 {
150 disable-over-current;
151 status = "okay";
152};
153
154/* External microSD */
155&usdhc3 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_usdhc3>;
158 bus-width = <4>;
159 cd-gpios = <&gpio6 11 0>;
160 vmmc-supply = <&reg_3p3v>;
161 status = "okay";
162};
163
164/* Internal microSD */
165&usdhc4 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_usdhc4>;
168 bus-width = <4>;
169 vmmc-supply = <&reg_3p3v>;
170 status = "okay";
171};
diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/imx6q-gw51xx.dts
new file mode 100644
index 000000000000..af4929aee075
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw51xx.dts
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14#include "imx6qdl-gw54xx.dtsi"
15
16/ {
17 model = "Gateworks Ventana i.MX6 Quad GW51XX";
18 compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q";
19};
diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/imx6q-gw52xx.dts
new file mode 100644
index 000000000000..5f71ddbc7f05
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw52xx.dts
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14#include "imx6qdl-gw52xx.dtsi"
15
16/ {
17 model = "Gateworks Ventana i.MX6 Quad GW52XX";
18 compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
19};
20
21&sata {
22 status = "okay";
23};
diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/imx6q-gw53xx.dts
new file mode 100644
index 000000000000..360c316b4740
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw53xx.dts
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14#include "imx6qdl-gw53xx.dtsi"
15
16/ {
17 model = "Gateworks Ventana i.MX6 Quad GW53XX";
18 compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
19};
20
21&sata {
22 status = "okay";
23};
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
new file mode 100644
index 000000000000..902f98310481
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -0,0 +1,546 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14
15/ {
16 model = "Gateworks Ventana GW5400-A";
17 compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q";
18
19 /* these are used by bootloader for disabling nodes */
20 aliases {
21 ethernet0 = &fec;
22 ethernet1 = &eth1;
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 led0 = &led0;
27 led1 = &led1;
28 led2 = &led2;
29 sky2 = &eth1;
30 ssi0 = &ssi1;
31 spi0 = &ecspi1;
32 usb0 = &usbh1;
33 usb1 = &usbotg;
34 usdhc2 = &usdhc3;
35 };
36
37 chosen {
38 bootargs = "console=ttymxc1,115200";
39 };
40
41 leds {
42 compatible = "gpio-leds";
43
44 led0: user1 {
45 label = "user1";
46 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
47 default-state = "on";
48 linux,default-trigger = "heartbeat";
49 };
50
51 led1: user2 {
52 label = "user2";
53 gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */
54 default-state = "off";
55 };
56
57 led2: user3 {
58 label = "user3";
59 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
60 default-state = "off";
61 };
62 };
63
64 memory {
65 reg = <0x10000000 0x40000000>;
66 };
67
68 pps {
69 compatible = "pps-gpio";
70 gpios = <&gpio1 5 0>;
71 status = "okay";
72 };
73
74 regulators {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 reg_1p0v: regulator@0 {
80 compatible = "regulator-fixed";
81 reg = <0>;
82 regulator-name = "1P0V";
83 regulator-min-microvolt = <1000000>;
84 regulator-max-microvolt = <1000000>;
85 regulator-always-on;
86 };
87
88 reg_3p3v: regulator@1 {
89 compatible = "regulator-fixed";
90 reg = <1>;
91 regulator-name = "3P3V";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 regulator-always-on;
95 };
96
97 reg_usb_h1_vbus: regulator@2 {
98 compatible = "regulator-fixed";
99 reg = <2>;
100 regulator-name = "usb_h1_vbus";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 regulator-always-on;
104 };
105
106 reg_usb_otg_vbus: regulator@3 {
107 compatible = "regulator-fixed";
108 reg = <3>;
109 regulator-name = "usb_otg_vbus";
110 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>;
112 gpio = <&gpio3 22 0>;
113 enable-active-high;
114 };
115 };
116
117 sound {
118 compatible = "fsl,imx6q-sabrelite-sgtl5000",
119 "fsl,imx-audio-sgtl5000";
120 model = "imx6q-sabrelite-sgtl5000";
121 ssi-controller = <&ssi1>;
122 audio-codec = <&codec>;
123 audio-routing =
124 "MIC_IN", "Mic Jack",
125 "Mic Jack", "Mic Bias",
126 "Headphone Jack", "HP_OUT";
127 mux-int-port = <1>;
128 mux-ext-port = <4>;
129 };
130};
131
132&audmux {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_audmux>;
135 status = "okay";
136};
137
138&ecspi1 {
139 fsl,spi-num-chipselects = <1>;
140 cs-gpios = <&gpio3 19 0>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_ecspi1>;
143 status = "okay";
144
145 flash: m25p80@0 {
146 compatible = "sst,w25q256";
147 spi-max-frequency = <30000000>;
148 reg = <0>;
149 };
150};
151
152&fec {
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_enet>;
155 phy-mode = "rgmii";
156 phy-reset-gpios = <&gpio1 30 0>;
157 status = "okay";
158};
159
160&i2c1 {
161 clock-frequency = <100000>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_i2c1>;
164 status = "okay";
165
166 eeprom1: eeprom@50 {
167 compatible = "atmel,24c02";
168 reg = <0x50>;
169 pagesize = <16>;
170 };
171
172 eeprom2: eeprom@51 {
173 compatible = "atmel,24c02";
174 reg = <0x51>;
175 pagesize = <16>;
176 };
177
178 eeprom3: eeprom@52 {
179 compatible = "atmel,24c02";
180 reg = <0x52>;
181 pagesize = <16>;
182 };
183
184 eeprom4: eeprom@53 {
185 compatible = "atmel,24c02";
186 reg = <0x53>;
187 pagesize = <16>;
188 };
189
190 gpio: pca9555@23 {
191 compatible = "nxp,pca9555";
192 reg = <0x23>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 };
196
197 hwmon: gsc@29 {
198 compatible = "gw,gsp";
199 reg = <0x29>;
200 };
201
202 rtc: ds1672@68 {
203 compatible = "dallas,ds1672";
204 reg = <0x68>;
205 };
206};
207
208&i2c2 {
209 clock-frequency = <100000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c2>;
212 status = "okay";
213
214 pmic: pfuze100@08 {
215 compatible = "fsl,pfuze100";
216 reg = <0x08>;
217
218 regulators {
219 sw1a_reg: sw1ab {
220 regulator-min-microvolt = <300000>;
221 regulator-max-microvolt = <1875000>;
222 regulator-boot-on;
223 regulator-always-on;
224 regulator-ramp-delay = <6250>;
225 };
226
227 sw1c_reg: sw1c {
228 regulator-min-microvolt = <300000>;
229 regulator-max-microvolt = <1875000>;
230 regulator-boot-on;
231 regulator-always-on;
232 regulator-ramp-delay = <6250>;
233 };
234
235 sw2_reg: sw2 {
236 regulator-min-microvolt = <800000>;
237 regulator-max-microvolt = <3950000>;
238 regulator-boot-on;
239 regulator-always-on;
240 };
241
242 sw3a_reg: sw3a {
243 regulator-min-microvolt = <400000>;
244 regulator-max-microvolt = <1975000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248
249 sw3b_reg: sw3b {
250 regulator-min-microvolt = <400000>;
251 regulator-max-microvolt = <1975000>;
252 regulator-boot-on;
253 regulator-always-on;
254 };
255
256 sw4_reg: sw4 {
257 regulator-min-microvolt = <800000>;
258 regulator-max-microvolt = <3300000>;
259 };
260
261 swbst_reg: swbst {
262 regulator-min-microvolt = <5000000>;
263 regulator-max-microvolt = <5150000>;
264 };
265
266 snvs_reg: vsnvs {
267 regulator-min-microvolt = <1000000>;
268 regulator-max-microvolt = <3000000>;
269 regulator-boot-on;
270 regulator-always-on;
271 };
272
273 vref_reg: vrefddr {
274 regulator-boot-on;
275 regulator-always-on;
276 };
277
278 vgen1_reg: vgen1 {
279 regulator-min-microvolt = <800000>;
280 regulator-max-microvolt = <1550000>;
281 };
282
283 vgen2_reg: vgen2 {
284 regulator-min-microvolt = <800000>;
285 regulator-max-microvolt = <1550000>;
286 };
287
288 vgen3_reg: vgen3 {
289 regulator-min-microvolt = <1800000>;
290 regulator-max-microvolt = <3300000>;
291 };
292
293 vgen4_reg: vgen4 {
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <3300000>;
296 regulator-always-on;
297 };
298
299 vgen5_reg: vgen5 {
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <3300000>;
302 regulator-always-on;
303 };
304
305 vgen6_reg: vgen6 {
306 regulator-min-microvolt = <1800000>;
307 regulator-max-microvolt = <3300000>;
308 regulator-always-on;
309 };
310 };
311 };
312
313 pciswitch: pex8609@3f {
314 compatible = "plx,pex8609";
315 reg = <0x3f>;
316 };
317
318 pciclkgen: si52147@6b {
319 compatible = "sil,si52147";
320 reg = <0x6b>;
321 };
322};
323
324&i2c3 {
325 clock-frequency = <100000>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_i2c3>;
328 status = "okay";
329
330 accelerometer: mma8450@1c {
331 compatible = "fsl,mma8450";
332 reg = <0x1c>;
333 };
334
335 codec: sgtl5000@0a {
336 compatible = "fsl,sgtl5000";
337 reg = <0x0a>;
338 clocks = <&clks 201>;
339 VDDA-supply = <&sw4_reg>;
340 VDDIO-supply = <&reg_3p3v>;
341 };
342
343 hdmiin: adv7611@4c {
344 compatible = "adi,adv7611";
345 reg = <0x4c>;
346 };
347
348 touchscreen: egalax_ts@04 {
349 compatible = "eeti,egalax_ts";
350 reg = <0x04>;
351 interrupt-parent = <&gpio7>;
352 interrupts = <12 2>; /* gpio7_12 active low */
353 wakeup-gpios = <&gpio7 12 0>;
354 };
355
356 videoout: adv7393@2a {
357 compatible = "adi,adv7393";
358 reg = <0x2a>;
359 };
360
361 videoin: adv7180@20 {
362 compatible = "adi,adv7180";
363 reg = <0x20>;
364 };
365};
366
367&iomuxc {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_hog>;
370
371 imx6q-gw5400-a {
372 pinctrl_hog: hoggrp {
373 fsl,pins = <
374 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
375 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */
376 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
377 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */
378 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
379 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */
380 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */
381 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
382 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */
383 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
384 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */
385 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */
386 >;
387 };
388
389 pinctrl_audmux: audmuxgrp {
390 fsl,pins = <
391 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
392 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
393 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
394 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
395 >;
396 };
397
398 pinctrl_ecspi1: ecspi1grp {
399 fsl,pins = <
400 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
401 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
402 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
403 >;
404 };
405
406 pinctrl_enet: enetgrp {
407 fsl,pins = <
408 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
409 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
410 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
411 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
412 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
413 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
414 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
415 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
416 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
417 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
418 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
419 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
420 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
421 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
422 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
423 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
424 >;
425 };
426
427 pinctrl_i2c1: i2c1grp {
428 fsl,pins = <
429 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
430 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
431 >;
432 };
433
434 pinctrl_i2c2: i2c2grp {
435 fsl,pins = <
436 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
437 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
438 >;
439 };
440
441 pinctrl_i2c3: i2c3grp {
442 fsl,pins = <
443 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
444 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
445 >;
446 };
447
448 pinctrl_uart1: uart1grp {
449 fsl,pins = <
450 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
451 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
452 >;
453 };
454
455 pinctrl_uart2: uart2grp {
456 fsl,pins = <
457 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
458 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
459 >;
460 };
461
462 pinctrl_uart5: uart5grp {
463 fsl,pins = <
464 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
465 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
466 >;
467 };
468
469 pinctrl_usbotg: usbotggrp {
470 fsl,pins = <
471 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
472 >;
473 };
474
475 pinctrl_usdhc3: usdhc3grp {
476 fsl,pins = <
477 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
478 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
479 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
480 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
481 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
482 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
483 >;
484 };
485 };
486};
487
488&ldb {
489 status = "okay";
490 lvds-channel@0 {
491 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
492 };
493};
494
495&pcie {
496 reset-gpio = <&gpio1 29 0>;
497 status = "okay";
498
499 eth1: sky2@8 { /* MAC/PHY on bus 8 */
500 compatible = "marvell,sky2";
501 };
502};
503
504&ssi1 {
505 fsl,mode = "i2s-slave";
506 status = "okay";
507};
508
509&uart1 {
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_uart1>;
512 status = "okay";
513};
514
515&uart2 {
516 pinctrl-names = "default";
517 pinctrl-0 = <&pinctrl_uart2>;
518 status = "okay";
519};
520
521&uart5 {
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_uart5>;
524 status = "okay";
525};
526
527&usbotg {
528 vbus-supply = <&reg_usb_otg_vbus>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_usbotg>;
531 disable-over-current;
532 status = "okay";
533};
534
535&usbh1 {
536 vbus-supply = <&reg_usb_h1_vbus>;
537 status = "okay";
538};
539
540&usdhc3 {
541 pinctrl-names = "default";
542 pinctrl-0 = <&pinctrl_usdhc3>;
543 cd-gpios = <&gpio7 0 0>;
544 vmmc-supply = <&reg_3p3v>;
545 status = "okay";
546};
diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts
new file mode 100644
index 000000000000..ab518d66a75e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw54xx.dts
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14#include "imx6qdl-gw54xx.dtsi"
15
16/ {
17 model = "Gateworks Ventana i.MX6 Quad GW54XX";
18 compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
19};
20
21&sata {
22 status = "okay";
23};
diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/imx6q-nitrogen6x.dts
new file mode 100644
index 000000000000..a57866b2e97e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-nitrogen6x.dts
@@ -0,0 +1,25 @@
1/*
2 * Copyright 2013 Boundary Devices, Inc.
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15#include "imx6q.dtsi"
16#include "imx6qdl-nitrogen6x.dtsi"
17
18/ {
19 model = "Freescale i.MX6 Quad Nitrogen6x Board";
20 compatible = "fsl,imx6q-nitrogen6x", "fsl,imx6q";
21};
22
23&sata {
24 status = "okay";
25};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
index 7d37ec60d58d..5607c331fca8 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
@@ -21,10 +21,26 @@
21 status = "okay"; 21 status = "okay";
22}; 22};
23 23
24&gpmi {
25 status = "okay";
26};
27
28&sata {
29 status = "okay";
30};
31
24&uart4 { 32&uart4 {
25 status = "okay"; 33 status = "okay";
26}; 34};
27 35
36&usbh1 {
37 status = "okay";
38};
39
40&usbotg {
41 status = "okay";
42};
43
28&usdhc2 { 44&usdhc2 {
29 status = "okay"; 45 status = "okay";
30}; 46};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index 1a3b50d4d8fa..324f1550976b 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -18,11 +18,35 @@
18 memory { 18 memory {
19 reg = <0x10000000 0x80000000>; 19 reg = <0x10000000 0x80000000>;
20 }; 20 };
21
22 regulators {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 reg_usb_otg_vbus: regulator@0 {
28 compatible = "regulator-fixed";
29 reg = <0>;
30 regulator-name = "usb_otg_vbus";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
33 gpio = <&gpio4 15 0>;
34 };
35
36 reg_usb_h1_vbus: regulator@1 {
37 compatible = "regulator-fixed";
38 reg = <1>;
39 regulator-name = "usb_h1_vbus";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
42 gpio = <&gpio1 0 0>;
43 };
44 };
21}; 45};
22 46
23&ecspi3 { 47&ecspi3 {
24 pinctrl-names = "default"; 48 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_ecspi3_1>; 49 pinctrl-0 = <&pinctrl_ecspi3>;
26 status = "okay"; 50 status = "okay";
27 fsl,spi-num-chipselects = <1>; 51 fsl,spi-num-chipselects = <1>;
28 cs-gpios = <&gpio4 24 0>; 52 cs-gpios = <&gpio4 24 0>;
@@ -36,7 +60,7 @@
36 60
37&i2c1 { 61&i2c1 {
38 pinctrl-names = "default"; 62 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_i2c1_1>; 63 pinctrl-0 = <&pinctrl_i2c1>;
40 status = "okay"; 64 status = "okay";
41 65
42 eeprom@50 { 66 eeprom@50 {
@@ -128,7 +152,7 @@
128 pinctrl-names = "default"; 152 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_hog>; 153 pinctrl-0 = <&pinctrl_hog>;
130 154
131 hog { 155 imx6q-phytec-pfla02 {
132 pinctrl_hog: hoggrp { 156 pinctrl_hog: hoggrp {
133 fsl,pins = < 157 fsl,pins = <
134 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 158 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
@@ -136,10 +160,109 @@
136 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ 160 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
137 >; 161 >;
138 }; 162 };
139 };
140 163
141 pfla02 { 164 pinctrl_ecspi3: ecspi3grp {
142 pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { 165 fsl,pins = <
166 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
167 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
168 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
169 >;
170 };
171
172 pinctrl_enet: enetgrp {
173 fsl,pins = <
174 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
175 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
176 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
177 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
178 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
179 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
180 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
181 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
182 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
183 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
184 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
185 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
186 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
187 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
188 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
189 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
190 >;
191 };
192
193 pinctrl_gpmi_nand: gpminandgrp {
194 fsl,pins = <
195 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
196 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
197 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
198 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
199 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
200 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
201 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
202 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
203 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
204 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
205 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
206 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
207 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
208 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
209 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
210 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
211 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
212 >;
213 };
214
215 pinctrl_i2c1: i2c1grp {
216 fsl,pins = <
217 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
218 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
219 >;
220 };
221
222 pinctrl_uart4: uart4grp {
223 fsl,pins = <
224 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
225 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
226 >;
227 };
228
229 pinctrl_usbh1: usbh1grp {
230 fsl,pins = <
231 MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
232 >;
233 };
234
235 pinctrl_usbotg: usbotggrp {
236 fsl,pins = <
237 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
238 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
239 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
240 >;
241 };
242
243 pinctrl_usdhc2: usdhc2grp {
244 fsl,pins = <
245 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
246 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
247 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
248 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
249 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
250 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
251 >;
252 };
253
254 pinctrl_usdhc3: usdhc3grp {
255 fsl,pins = <
256 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
257 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
258 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
259 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
260 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
261 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
262 >;
263 };
264
265 pinctrl_usdhc3_cdwp: usdhc3cdwp {
143 fsl,pins = < 266 fsl,pins = <
144 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 267 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
145 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 268 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
@@ -150,21 +273,43 @@
150 273
151&fec { 274&fec {
152 pinctrl-names = "default"; 275 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_enet_3>; 276 pinctrl-0 = <&pinctrl_enet>;
154 phy-mode = "rgmii"; 277 phy-mode = "rgmii";
155 phy-reset-gpios = <&gpio3 23 0>; 278 phy-reset-gpios = <&gpio3 23 0>;
156 status = "disabled"; 279 status = "disabled";
157}; 280};
158 281
282&gpmi {
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_gpmi_nand>;
285 nand-on-flash-bbt;
286 status = "disabled";
287};
288
159&uart4 { 289&uart4 {
160 pinctrl-names = "default"; 290 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_uart4_1>; 291 pinctrl-0 = <&pinctrl_uart4>;
292 status = "disabled";
293};
294
295&usbh1 {
296 vbus-supply = <&reg_usb_h1_vbus>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_usbh1>;
299 status = "disabled";
300};
301
302&usbotg {
303 vbus-supply = <&reg_usb_otg_vbus>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_usbotg>;
306 disable-over-current;
162 status = "disabled"; 307 status = "disabled";
163}; 308};
164 309
165&usdhc2 { 310&usdhc2 {
166 pinctrl-names = "default"; 311 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_usdhc2_2>; 312 pinctrl-0 = <&pinctrl_usdhc2>;
168 cd-gpios = <&gpio1 4 0>; 313 cd-gpios = <&gpio1 4 0>;
169 wp-gpios = <&gpio1 2 0>; 314 wp-gpios = <&gpio1 2 0>;
170 status = "disabled"; 315 status = "disabled";
@@ -172,8 +317,8 @@
172 317
173&usdhc3 { 318&usdhc3 {
174 pinctrl-names = "default"; 319 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_usdhc3_2 320 pinctrl-0 = <&pinctrl_usdhc3
176 &pinctrl_usdhc3_pfla02>; 321 &pinctrl_usdhc3_cdwp>;
177 cd-gpios = <&gpio1 27 0>; 322 cd-gpios = <&gpio1 27 0>;
178 wp-gpios = <&gpio1 29 0>; 323 wp-gpios = <&gpio1 29 0>;
179 status = "disabled"; 324 status = "disabled";
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
index 97ed0816a6e0..9fc6120a1853 100644
--- a/arch/arm/boot/dts/imx6q-pinfunc.h
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -673,6 +673,7 @@
673#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 673#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
674#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 674#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
675#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 675#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
676#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609
676#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 677#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
677#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 678#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
678#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 679#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
@@ -1024,6 +1025,7 @@
1024#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 1025#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
1025#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 1026#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
1026#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 1027#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
1028#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0
1027#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 1029#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
1028#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 1030#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
1029#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 1031#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index f004913f7d80..96e4688be77c 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -12,189 +12,13 @@
12 12
13/dts-v1/; 13/dts-v1/;
14#include "imx6q.dtsi" 14#include "imx6q.dtsi"
15#include "imx6qdl-sabrelite.dtsi"
15 16
16/ { 17/ {
17 model = "Freescale i.MX6 Quad SABRE Lite Board"; 18 model = "Freescale i.MX6 Quad SABRE Lite Board";
18 compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; 19 compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 regulators {
25 compatible = "simple-bus";
26
27 reg_2p5v: 2p5v {
28 compatible = "regulator-fixed";
29 regulator-name = "2P5V";
30 regulator-min-microvolt = <2500000>;
31 regulator-max-microvolt = <2500000>;
32 regulator-always-on;
33 };
34
35 reg_3p3v: 3p3v {
36 compatible = "regulator-fixed";
37 regulator-name = "3P3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 };
42
43 reg_usb_otg_vbus: usb_otg_vbus {
44 compatible = "regulator-fixed";
45 regulator-name = "usb_otg_vbus";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 gpio = <&gpio3 22 0>;
49 enable-active-high;
50 };
51 };
52
53 sound {
54 compatible = "fsl,imx6q-sabrelite-sgtl5000",
55 "fsl,imx-audio-sgtl5000";
56 model = "imx6q-sabrelite-sgtl5000";
57 ssi-controller = <&ssi1>;
58 audio-codec = <&codec>;
59 audio-routing =
60 "MIC_IN", "Mic Jack",
61 "Mic Jack", "Mic Bias",
62 "Headphone Jack", "HP_OUT";
63 mux-int-port = <1>;
64 mux-ext-port = <4>;
65 };
66};
67
68&audmux {
69 status = "okay";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_audmux_1>;
72};
73
74&ecspi1 {
75 fsl,spi-num-chipselects = <1>;
76 cs-gpios = <&gpio3 19 0>;
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_ecspi1_1>;
79 status = "okay";
80
81 flash: m25p80@0 {
82 compatible = "sst,sst25vf016b";
83 spi-max-frequency = <20000000>;
84 reg = <0>;
85 };
86};
87
88&fec {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_enet_1>;
91 phy-mode = "rgmii";
92 phy-reset-gpios = <&gpio3 23 0>;
93 status = "okay";
94};
95
96&i2c1 {
97 status = "okay";
98 clock-frequency = <100000>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_i2c1_1>;
101
102 codec: sgtl5000@0a {
103 compatible = "fsl,sgtl5000";
104 reg = <0x0a>;
105 clocks = <&clks 201>;
106 VDDA-supply = <&reg_2p5v>;
107 VDDIO-supply = <&reg_3p3v>;
108 };
109};
110
111&iomuxc {
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_hog>;
114
115 hog {
116 pinctrl_hog: hoggrp {
117 fsl,pins = <
118 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
119 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
120 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
121 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
122 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
123 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
124 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
125 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
126 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
127 >;
128 };
129 };
130};
131
132&ldb {
133 status = "okay";
134
135 lvds-channel@0 {
136 fsl,data-mapping = "spwg";
137 fsl,data-width = <18>;
138 status = "okay";
139
140 display-timings {
141 native-mode = <&timing0>;
142 timing0: hsd100pxn1 {
143 clock-frequency = <65000000>;
144 hactive = <1024>;
145 vactive = <768>;
146 hback-porch = <220>;
147 hfront-porch = <40>;
148 vback-porch = <21>;
149 vfront-porch = <7>;
150 hsync-len = <60>;
151 vsync-len = <10>;
152 };
153 };
154 };
155}; 20};
156 21
157&sata { 22&sata {
158 status = "okay"; 23 status = "okay";
159}; 24};
160
161&ssi1 {
162 fsl,mode = "i2s-slave";
163 status = "okay";
164};
165
166&uart2 {
167 status = "okay";
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2_1>;
170};
171
172&usbh1 {
173 status = "okay";
174};
175
176&usbotg {
177 vbus-supply = <&reg_usb_otg_vbus>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_usbotg_1>;
180 disable-over-current;
181 status = "okay";
182};
183
184&usdhc3 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_usdhc3_2>;
187 cd-gpios = <&gpio7 0 0>;
188 wp-gpios = <&gpio7 1 0>;
189 vmmc-supply = <&reg_3p3v>;
190 status = "okay";
191};
192
193&usdhc4 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_usdhc4_2>;
196 cd-gpios = <&gpio2 6 0>;
197 wp-gpios = <&gpio2 7 0>;
198 vmmc-supply = <&reg_3p3v>;
199 status = "okay";
200};
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
index ee6addf149af..86cf09364664 100644
--- a/arch/arm/boot/dts/imx6q-sbc6x.dts
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -17,28 +17,78 @@
17 }; 17 };
18}; 18};
19 19
20
20&fec { 21&fec {
21 pinctrl-names = "default"; 22 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_enet_1>; 23 pinctrl-0 = <&pinctrl_enet>;
23 phy-mode = "rgmii"; 24 phy-mode = "rgmii";
24 status = "okay"; 25 status = "okay";
25}; 26};
26 27
28&iomuxc {
29 imx6q-sbc6x {
30 pinctrl_enet: enetgrp {
31 fsl,pins = <
32 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
33 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
34 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
35 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
36 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
37 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
38 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
39 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
40 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
41 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
42 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
43 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
44 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
45 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
46 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
47 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
48 >;
49 };
50
51 pinctrl_uart1: uart1grp {
52 fsl,pins = <
53 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
54 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
55 >;
56 };
57
58 pinctrl_usbotg: usbotggrp {
59 fsl,pins = <
60 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
61 >;
62 };
63
64 pinctrl_usdhc3: usdhc3grp {
65 fsl,pins = <
66 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
67 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
68 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
69 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
70 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
71 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
72 >;
73 };
74 };
75};
76
27&uart1 { 77&uart1 {
28 pinctrl-names = "default"; 78 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_uart1_1>; 79 pinctrl-0 = <&pinctrl_uart1>;
30 status = "okay"; 80 status = "okay";
31}; 81};
32 82
33&usbotg { 83&usbotg {
34 pinctrl-names = "default"; 84 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_usbotg_1>; 85 pinctrl-0 = <&pinctrl_usbotg>;
36 disable-over-current; 86 disable-over-current;
37 status = "okay"; 87 status = "okay";
38}; 88};
39 89
40&usdhc3 { 90&usdhc3 {
41 pinctrl-names = "default"; 91 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_usdhc3_2>; 92 pinctrl-0 = <&pinctrl_usdhc3>;
43 status = "okay"; 93 status = "okay";
44}; 94};
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
index 6e1ccdc019a7..ed397d149ab6 100644
--- a/arch/arm/boot/dts/imx6q-udoo.dts
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -21,19 +21,69 @@
21 }; 21 };
22}; 22};
23 23
24&fec {
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_enet>;
27 phy-mode = "rgmii";
28 status = "okay";
29};
30
31&iomuxc {
32 imx6q-udoo {
33 pinctrl_enet: enetgrp {
34 fsl,pins = <
35 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
36 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
37 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
38 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
39 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
40 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
41 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
42 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
43 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
44 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
45 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
46 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
47 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
48 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
49 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
50 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
51 >;
52 };
53
54 pinctrl_uart2: uart2grp {
55 fsl,pins = <
56 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
57 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
58 >;
59 };
60
61 pinctrl_usdhc3: usdhc3grp {
62 fsl,pins = <
63 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
64 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
65 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
66 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
67 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
68 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
69 >;
70 };
71 };
72};
73
24&sata { 74&sata {
25 status = "okay"; 75 status = "okay";
26}; 76};
27 77
28&uart2 { 78&uart2 {
29 pinctrl-names = "default"; 79 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_uart2_1>; 80 pinctrl-0 = <&pinctrl_uart2>;
31 status = "okay"; 81 status = "okay";
32}; 82};
33 83
34&usdhc3 { 84&usdhc3 {
35 pinctrl-names = "default"; 85 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_usdhc3_2>; 86 pinctrl-0 = <&pinctrl_usdhc3>;
37 non-removable; 87 non-removable;
38 status = "okay"; 88 status = "okay";
39}; 89};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index f024ef28b34b..addd3f881ce2 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -8,10 +8,15 @@
8 * 8 *
9 */ 9 */
10 10
11#include <dt-bindings/interrupt-controller/irq.h>
11#include "imx6q-pinfunc.h" 12#include "imx6q-pinfunc.h"
12#include "imx6qdl.dtsi" 13#include "imx6qdl.dtsi"
13 14
14/ { 15/ {
16 aliases {
17 spi4 = &ecspi5;
18 };
19
15 cpus { 20 cpus {
16 #address-cells = <1>; 21 #address-cells = <1>;
17 #size-cells = <0>; 22 #size-cells = <0>;
@@ -25,8 +30,17 @@
25 /* kHz uV */ 30 /* kHz uV */
26 1200000 1275000 31 1200000 1275000
27 996000 1250000 32 996000 1250000
33 852000 1250000
28 792000 1150000 34 792000 1150000
29 396000 950000 35 396000 975000
36 >;
37 fsl,soc-operating-points = <
38 /* ARM kHz SOC-PU uV */
39 1200000 1275000
40 996000 1250000
41 852000 1250000
42 792000 1175000
43 396000 1175000
30 >; 44 >;
31 clock-latency = <61036>; /* two CLK32 periods */ 45 clock-latency = <61036>; /* two CLK32 periods */
32 clocks = <&clks 104>, <&clks 6>, <&clks 16>, 46 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
@@ -74,7 +88,7 @@
74 #size-cells = <0>; 88 #size-cells = <0>;
75 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 89 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
76 reg = <0x02018000 0x4000>; 90 reg = <0x02018000 0x4000>;
77 interrupts = <0 35 0x04>; 91 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&clks 116>, <&clks 116>; 92 clocks = <&clks 116>, <&clks 116>;
79 clock-names = "ipg", "per"; 93 clock-names = "ipg", "per";
80 status = "disabled"; 94 status = "disabled";
@@ -125,20 +139,92 @@
125 sata: sata@02200000 { 139 sata: sata@02200000 {
126 compatible = "fsl,imx6q-ahci"; 140 compatible = "fsl,imx6q-ahci";
127 reg = <0x02200000 0x4000>; 141 reg = <0x02200000 0x4000>;
128 interrupts = <0 39 0x04>; 142 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&clks 154>, <&clks 187>, <&clks 105>; 143 clocks = <&clks 154>, <&clks 187>, <&clks 105>;
130 clock-names = "sata", "sata_ref", "ahb"; 144 clock-names = "sata", "sata_ref", "ahb";
131 status = "disabled"; 145 status = "disabled";
132 }; 146 };
133 147
134 ipu2: ipu@02800000 { 148 ipu2: ipu@02800000 {
135 #crtc-cells = <1>; 149 #address-cells = <1>;
150 #size-cells = <0>;
136 compatible = "fsl,imx6q-ipu"; 151 compatible = "fsl,imx6q-ipu";
137 reg = <0x02800000 0x400000>; 152 reg = <0x02800000 0x400000>;
138 interrupts = <0 8 0x4 0 7 0x4>; 153 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
154 <0 7 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&clks 133>, <&clks 134>, <&clks 137>; 155 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
140 clock-names = "bus", "di0", "di1"; 156 clock-names = "bus", "di0", "di1";
141 resets = <&src 4>; 157 resets = <&src 4>;
158
159 ipu2_di0: port@2 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 reg = <2>;
163
164 ipu2_di0_disp0: endpoint@0 {
165 };
166
167 ipu2_di0_hdmi: endpoint@1 {
168 remote-endpoint = <&hdmi_mux_2>;
169 };
170
171 ipu2_di0_mipi: endpoint@2 {
172 };
173
174 ipu2_di0_lvds0: endpoint@3 {
175 remote-endpoint = <&lvds0_mux_2>;
176 };
177
178 ipu2_di0_lvds1: endpoint@4 {
179 remote-endpoint = <&lvds1_mux_2>;
180 };
181 };
182
183 ipu2_di1: port@3 {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 reg = <3>;
187
188 ipu2_di1_hdmi: endpoint@1 {
189 remote-endpoint = <&hdmi_mux_3>;
190 };
191
192 ipu2_di1_mipi: endpoint@2 {
193 };
194
195 ipu2_di1_lvds0: endpoint@3 {
196 remote-endpoint = <&lvds0_mux_3>;
197 };
198
199 ipu2_di1_lvds1: endpoint@4 {
200 remote-endpoint = <&lvds1_mux_3>;
201 };
202 };
203 };
204 };
205
206 display-subsystem {
207 compatible = "fsl,imx-display-subsystem";
208 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
209 };
210};
211
212&hdmi {
213 compatible = "fsl,imx6q-hdmi";
214
215 port@2 {
216 reg = <2>;
217
218 hdmi_mux_2: endpoint {
219 remote-endpoint = <&ipu2_di0_hdmi>;
220 };
221 };
222
223 port@3 {
224 reg = <3>;
225
226 hdmi_mux_3: endpoint {
227 remote-endpoint = <&ipu2_di1_hdmi>;
142 }; 228 };
143 }; 229 };
144}; 230};
@@ -152,10 +238,56 @@
152 "di0", "di1"; 238 "di0", "di1";
153 239
154 lvds-channel@0 { 240 lvds-channel@0 {
155 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; 241 port@2 {
242 reg = <2>;
243
244 lvds0_mux_2: endpoint {
245 remote-endpoint = <&ipu2_di0_lvds0>;
246 };
247 };
248
249 port@3 {
250 reg = <3>;
251
252 lvds0_mux_3: endpoint {
253 remote-endpoint = <&ipu2_di1_lvds0>;
254 };
255 };
156 }; 256 };
157 257
158 lvds-channel@1 { 258 lvds-channel@1 {
159 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; 259 port@2 {
260 reg = <2>;
261
262 lvds1_mux_2: endpoint {
263 remote-endpoint = <&ipu2_di0_lvds1>;
264 };
265 };
266
267 port@3 {
268 reg = <3>;
269
270 lvds1_mux_3: endpoint {
271 remote-endpoint = <&ipu2_di1_lvds1>;
272 };
273 };
274 };
275};
276
277&mipi_dsi {
278 port@2 {
279 reg = <2>;
280
281 mipi_mux_2: endpoint {
282 remote-endpoint = <&ipu2_di0_mipi>;
283 };
284 };
285
286 port@3 {
287 reg = <3>;
288
289 mipi_mux_3: endpoint {
290 remote-endpoint = <&ipu2_di1_mipi>;
291 };
160 }; 292 };
161}; 293};
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
new file mode 100644
index 000000000000..25cf035dd36e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -0,0 +1,199 @@
1/ {
2 regulators {
3 compatible = "simple-bus";
4 #address-cells = <1>;
5 #size-cells = <0>;
6
7 dummy_reg: regulator@0 {
8 compatible = "regulator-fixed";
9 reg = <0>;
10 regulator-name = "dummy-supply";
11 };
12
13 reg_usb_otg_vbus: regulator@1 {
14 compatible = "regulator-fixed";
15 reg = <1>;
16 regulator-name = "usb_otg_vbus";
17 regulator-min-microvolt = <5000000>;
18 regulator-max-microvolt = <5000000>;
19 gpio = <&gpio3 22 0>;
20 enable-active-high;
21 };
22 };
23
24 chosen {
25 linux,stdout-path = &uart1;
26 };
27};
28
29&ecspi3 {
30 fsl,spi-num-chipselects = <1>;
31 cs-gpios = <&gpio4 24 0>;
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_ecspi3>;
34 status = "okay";
35
36 flash: m25p80@0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "sst,sst25vf040b", "m25p80";
40 spi-max-frequency = <20000000>;
41 reg = <0>;
42 };
43};
44
45&fec {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_enet>;
48 status = "okay";
49 phy-mode = "rgmii";
50};
51
52&iomuxc {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_hog>;
55
56 imx6qdl-dfi-fs700-m60 {
57 pinctrl_hog: hoggrp {
58 fsl,pins = <
59 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
60 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */
61 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */
62 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */
63 >;
64 };
65
66 pinctrl_enet: enetgrp {
67 fsl,pins = <
68 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
69 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
70 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
71 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
72 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
73 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
74 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
75 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
76 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
77 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
78 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
79 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
80 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
81 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
82 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
83 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
84 >;
85 };
86
87 pinctrl_i2c2: i2c2grp {
88 fsl,pins = <
89 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
90 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
91 >;
92 };
93
94 pinctrl_uart1: uart1grp {
95 fsl,pins = <
96 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
97 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
98 >;
99 };
100
101 pinctrl_usbotg: usbotggrp {
102 fsl,pins = <
103 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
104 >;
105 };
106
107 pinctrl_usdhc2: usdhc2grp {
108 fsl,pins = <
109 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
110 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
111 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
112 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
113 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
114 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
115 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */
116 >;
117 };
118
119 pinctrl_usdhc3: usdhc3grp {
120 fsl,pins = <
121 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
122 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
123 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
124 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
125 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
126 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
127 >;
128 };
129
130 pinctrl_usdhc4: usdhc4grp {
131 fsl,pins = <
132 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
133 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
134 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
135 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
136 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
137 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
138 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
139 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
140 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
141 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
142 >;
143 };
144
145 pinctrl_ecspi3: ecspi3grp {
146 fsl,pins = <
147 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
148 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
149 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
150 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
151 >;
152 };
153 };
154};
155
156&i2c2 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_i2c2>;
159 status = "okay";
160};
161
162&uart1 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_uart1>;
165 status = "okay";
166};
167
168&usbh1 {
169 status = "okay";
170};
171
172&usbotg {
173 vbus-supply = <&reg_usb_otg_vbus>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_usbotg>;
176 disable-over-current;
177 dr_mode = "host";
178 status = "okay";
179};
180
181&usdhc2 { /* module slot */
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_usdhc2>;
184 cd-gpios = <&gpio2 2 0>;
185 status = "okay";
186};
187
188&usdhc3 { /* baseboard slot */
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_usdhc3>;
191};
192
193&usdhc4 { /* eMMC */
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_usdhc4>;
196 bus-width = <8>;
197 non-removable;
198 status = "okay";
199};
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
new file mode 100644
index 000000000000..98a422153ce7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -0,0 +1,374 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 /* these are used by bootloader for disabling nodes */
14 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 led0 = &led0;
18 led1 = &led1;
19 nand = &gpmi;
20 usb0 = &usbh1;
21 usb1 = &usbotg;
22 };
23
24 chosen {
25 bootargs = "console=ttymxc1,115200";
26 };
27
28 leds {
29 compatible = "gpio-leds";
30
31 led0: user1 {
32 label = "user1";
33 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
34 default-state = "on";
35 linux,default-trigger = "heartbeat";
36 };
37
38 led1: user2 {
39 label = "user2";
40 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
41 default-state = "off";
42 };
43 };
44
45 memory {
46 reg = <0x10000000 0x20000000>;
47 };
48
49 pps {
50 compatible = "pps-gpio";
51 gpios = <&gpio1 26 0>;
52 status = "okay";
53 };
54
55 regulators {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 reg_3p3v: regulator@0 {
61 compatible = "regulator-fixed";
62 reg = <0>;
63 regulator-name = "3P3V";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 regulator-always-on;
67 };
68
69 reg_5p0v: regulator@1 {
70 compatible = "regulator-fixed";
71 reg = <1>;
72 regulator-name = "5P0V";
73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <5000000>;
75 regulator-always-on;
76 };
77
78 reg_usb_otg_vbus: regulator@2 {
79 compatible = "regulator-fixed";
80 reg = <2>;
81 regulator-name = "usb_otg_vbus";
82 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>;
84 gpio = <&gpio3 22 0>;
85 enable-active-high;
86 };
87 };
88};
89
90&fec {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_enet>;
93 phy-mode = "rgmii";
94 phy-reset-gpios = <&gpio1 30 0>;
95 status = "okay";
96};
97
98&gpmi {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_gpmi_nand>;
101 status = "okay";
102};
103
104&i2c1 {
105 clock-frequency = <100000>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_i2c1>;
108 status = "okay";
109
110 eeprom1: eeprom@50 {
111 compatible = "atmel,24c02";
112 reg = <0x50>;
113 pagesize = <16>;
114 };
115
116 eeprom2: eeprom@51 {
117 compatible = "atmel,24c02";
118 reg = <0x51>;
119 pagesize = <16>;
120 };
121
122 eeprom3: eeprom@52 {
123 compatible = "atmel,24c02";
124 reg = <0x52>;
125 pagesize = <16>;
126 };
127
128 eeprom4: eeprom@53 {
129 compatible = "atmel,24c02";
130 reg = <0x53>;
131 pagesize = <16>;
132 };
133
134 gpio: pca9555@23 {
135 compatible = "nxp,pca9555";
136 reg = <0x23>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 hwmon: gsc@29 {
142 compatible = "gw,gsp";
143 reg = <0x29>;
144 };
145
146 rtc: ds1672@68 {
147 compatible = "dallas,ds1672";
148 reg = <0x68>;
149 };
150};
151
152&i2c2 {
153 clock-frequency = <100000>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c2>;
156 status = "okay";
157
158 pmic: ltc3676@3c {
159 compatible = "ltc,ltc3676";
160 reg = <0x3c>;
161
162 regulators {
163 sw1_reg: ltc3676__sw1 {
164 regulator-min-microvolt = <1175000>;
165 regulator-max-microvolt = <1175000>;
166 regulator-boot-on;
167 regulator-always-on;
168 };
169
170 sw2_reg: ltc3676__sw2 {
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <1800000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 sw3_reg: ltc3676__sw3 {
178 regulator-min-microvolt = <1175000>;
179 regulator-max-microvolt = <1175000>;
180 regulator-boot-on;
181 regulator-always-on;
182 };
183
184 sw4_reg: ltc3676__sw4 {
185 regulator-min-microvolt = <1500000>;
186 regulator-max-microvolt = <1500000>;
187 regulator-boot-on;
188 regulator-always-on;
189 };
190
191 ldo2_reg: ltc3676__ldo2 {
192 regulator-min-microvolt = <2500000>;
193 regulator-max-microvolt = <2500000>;
194 regulator-boot-on;
195 regulator-always-on;
196 };
197
198 ldo4_reg: ltc3676__ldo4 {
199 regulator-min-microvolt = <3000000>;
200 regulator-max-microvolt = <3000000>;
201 };
202 };
203 };
204};
205
206&i2c3 {
207 clock-frequency = <100000>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_i2c3>;
210 status = "okay";
211
212 videoin: adv7180@20 {
213 compatible = "adi,adv7180";
214 reg = <0x20>;
215 };
216};
217
218&iomuxc {
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_hog>;
221
222 imx6qdl-gw51xx {
223 pinctrl_hog: hoggrp {
224 fsl,pins = <
225 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */
226 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */
227 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
228 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
229 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
230 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */
231 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
232 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
233 >;
234 };
235
236 pinctrl_enet: enetgrp {
237 fsl,pins = <
238 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
239 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
240 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
241 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
242 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
243 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
244 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
245 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
246 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
247 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
248 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
249 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
250 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
251 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
252 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
253 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
254 >;
255 };
256
257 pinctrl_gpmi_nand: gpminandgrp {
258 fsl,pins = <
259 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
260 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
261 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
262 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
263 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
264 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
265 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
266 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
267 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
268 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
269 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
270 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
271 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
272 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
273 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
274 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
275 >;
276 };
277
278 pinctrl_i2c1: i2c1grp {
279 fsl,pins = <
280 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
281 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
282 >;
283 };
284
285 pinctrl_i2c2: i2c2grp {
286 fsl,pins = <
287 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
288 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
289 >;
290 };
291
292 pinctrl_i2c3: i2c3grp {
293 fsl,pins = <
294 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
295 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
296 >;
297 };
298
299 pinctrl_uart1: uart1grp {
300 fsl,pins = <
301 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
302 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
303 >;
304 };
305
306 pinctrl_uart2: uart2grp {
307 fsl,pins = <
308 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
309 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
310 >;
311 };
312
313 pinctrl_uart3: uart3grp {
314 fsl,pins = <
315 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
316 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
317 >;
318 };
319
320 pinctrl_uart5: uart5grp {
321 fsl,pins = <
322 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
323 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
324 >;
325 };
326
327 pinctrl_usbotg: usbotggrp {
328 fsl,pins = <
329 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
330 >;
331 };
332 };
333};
334
335&pcie {
336 reset-gpio = <&gpio1 0 0>;
337 status = "okay";
338};
339
340&uart1 {
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_uart1>;
343 status = "okay";
344};
345
346&uart2 {
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_uart2>;
349 status = "okay";
350};
351
352&uart3 {
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_uart3>;
355 status = "okay";
356};
357
358&uart5 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_uart5>;
361 status = "okay";
362};
363
364&usbotg {
365 vbus-supply = <&reg_usb_otg_vbus>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_usbotg>;
368 disable-over-current;
369 status = "okay";
370};
371
372&usbh1 {
373 status = "okay";
374};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
new file mode 100644
index 000000000000..8e99c9a9bc76
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -0,0 +1,490 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 /* these are used by bootloader for disabling nodes */
14 aliases {
15 ethernet0 = &fec;
16 led0 = &led0;
17 led1 = &led1;
18 led2 = &led2;
19 nand = &gpmi;
20 ssi0 = &ssi1;
21 usb0 = &usbh1;
22 usb1 = &usbotg;
23 usdhc2 = &usdhc3;
24 };
25
26 chosen {
27 bootargs = "console=ttymxc1,115200";
28 };
29
30 leds {
31 compatible = "gpio-leds";
32
33 led0: user1 {
34 label = "user1";
35 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
36 default-state = "on";
37 linux,default-trigger = "heartbeat";
38 };
39
40 led1: user2 {
41 label = "user2";
42 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
43 default-state = "off";
44 };
45
46 led2: user3 {
47 label = "user3";
48 gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */
49 default-state = "off";
50 };
51 };
52
53 memory {
54 reg = <0x10000000 0x20000000>;
55 };
56
57 pps {
58 compatible = "pps-gpio";
59 gpios = <&gpio1 26 0>;
60 status = "okay";
61 };
62
63 regulators {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 reg_1p0v: regulator@0 {
69 compatible = "regulator-fixed";
70 reg = <0>;
71 regulator-name = "1P0V";
72 regulator-min-microvolt = <1000000>;
73 regulator-max-microvolt = <1000000>;
74 regulator-always-on;
75 };
76
77 /* remove this fixed regulator once ltc3676__sw2 driver available */
78 reg_1p8v: regulator@1 {
79 compatible = "regulator-fixed";
80 reg = <1>;
81 regulator-name = "1P8V";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
84 regulator-always-on;
85 };
86
87 reg_3p3v: regulator@2 {
88 compatible = "regulator-fixed";
89 reg = <2>;
90 regulator-name = "3P3V";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
93 regulator-always-on;
94 };
95
96 reg_5p0v: regulator@3 {
97 compatible = "regulator-fixed";
98 reg = <3>;
99 regulator-name = "5P0V";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-always-on;
103 };
104
105 reg_usb_otg_vbus: regulator@4 {
106 compatible = "regulator-fixed";
107 reg = <4>;
108 regulator-name = "usb_otg_vbus";
109 regulator-min-microvolt = <5000000>;
110 regulator-max-microvolt = <5000000>;
111 gpio = <&gpio3 22 0>;
112 enable-active-high;
113 };
114 };
115
116 sound {
117 compatible = "fsl,imx6q-sabrelite-sgtl5000",
118 "fsl,imx-audio-sgtl5000";
119 model = "imx6q-sabrelite-sgtl5000";
120 ssi-controller = <&ssi1>;
121 audio-codec = <&codec>;
122 audio-routing =
123 "MIC_IN", "Mic Jack",
124 "Mic Jack", "Mic Bias",
125 "Headphone Jack", "HP_OUT";
126 mux-int-port = <1>;
127 mux-ext-port = <4>;
128 };
129};
130
131&audmux {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_audmux>;
134 status = "okay";
135};
136
137&fec {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_enet>;
140 phy-mode = "rgmii";
141 phy-reset-gpios = <&gpio1 30 0>;
142 status = "okay";
143};
144
145&gpmi {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_gpmi_nand>;
148 status = "okay";
149};
150
151&i2c1 {
152 clock-frequency = <100000>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c1>;
155 status = "okay";
156
157 eeprom1: eeprom@50 {
158 compatible = "atmel,24c02";
159 reg = <0x50>;
160 pagesize = <16>;
161 };
162
163 eeprom2: eeprom@51 {
164 compatible = "atmel,24c02";
165 reg = <0x51>;
166 pagesize = <16>;
167 };
168
169 eeprom3: eeprom@52 {
170 compatible = "atmel,24c02";
171 reg = <0x52>;
172 pagesize = <16>;
173 };
174
175 eeprom4: eeprom@53 {
176 compatible = "atmel,24c02";
177 reg = <0x53>;
178 pagesize = <16>;
179 };
180
181 gpio: pca9555@23 {
182 compatible = "nxp,pca9555";
183 reg = <0x23>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 };
187
188 hwmon: gsc@29 {
189 compatible = "gw,gsp";
190 reg = <0x29>;
191 };
192
193 rtc: ds1672@68 {
194 compatible = "dallas,ds1672";
195 reg = <0x68>;
196 };
197};
198
199&i2c2 {
200 clock-frequency = <100000>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_i2c2>;
203 status = "okay";
204
205 pciswitch: pex8609@3f {
206 compatible = "plx,pex8609";
207 reg = <0x3f>;
208 };
209
210 pmic: ltc3676@3c {
211 compatible = "ltc,ltc3676";
212 reg = <0x3c>;
213
214 regulators {
215 sw1_reg: ltc3676__sw1 {
216 regulator-min-microvolt = <1175000>;
217 regulator-max-microvolt = <1175000>;
218 regulator-boot-on;
219 regulator-always-on;
220 };
221
222 sw2_reg: ltc3676__sw2 {
223 regulator-min-microvolt = <1800000>;
224 regulator-max-microvolt = <1800000>;
225 regulator-boot-on;
226 regulator-always-on;
227 };
228
229 sw3_reg: ltc3676__sw3 {
230 regulator-min-microvolt = <1175000>;
231 regulator-max-microvolt = <1175000>;
232 regulator-boot-on;
233 regulator-always-on;
234 };
235
236 sw4_reg: ltc3676__sw4 {
237 regulator-min-microvolt = <1500000>;
238 regulator-max-microvolt = <1500000>;
239 regulator-boot-on;
240 regulator-always-on;
241 };
242
243 ldo2_reg: ltc3676__ldo2 {
244 regulator-min-microvolt = <2500000>;
245 regulator-max-microvolt = <2500000>;
246 regulator-boot-on;
247 regulator-always-on;
248 };
249
250 ldo3_reg: ltc3676__ldo3 {
251 regulator-min-microvolt = <1800000>;
252 regulator-max-microvolt = <1800000>;
253 regulator-boot-on;
254 regulator-always-on;
255 };
256
257 ldo4_reg: ltc3676__ldo4 {
258 regulator-min-microvolt = <3000000>;
259 regulator-max-microvolt = <3000000>;
260 };
261 };
262 };
263};
264
265&i2c3 {
266 clock-frequency = <100000>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_i2c3>;
269 status = "okay";
270
271 accelerometer: fxos8700@1e {
272 compatible = "fsl,fxos8700";
273 reg = <0x13>;
274 };
275
276 codec: sgtl5000@0a {
277 compatible = "fsl,sgtl5000";
278 reg = <0x0a>;
279 clocks = <&clks 169>;
280 VDDA-supply = <&reg_1p8v>;
281 VDDIO-supply = <&reg_3p3v>;
282 };
283
284 touchscreen: egalax_ts@04 {
285 compatible = "eeti,egalax_ts";
286 reg = <0x04>;
287 interrupt-parent = <&gpio7>;
288 interrupts = <12 2>; /* gpio7_12 active low */
289 wakeup-gpios = <&gpio7 12 0>;
290 };
291
292 videoin: adv7180@20 {
293 compatible = "adi,adv7180";
294 reg = <0x20>;
295 };
296};
297
298&iomuxc {
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_hog>;
301
302 imx6qdl-gw52xx {
303 pinctrl_hog: hoggrp {
304 fsl,pins = <
305 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */
306 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */
307 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
308 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */
309 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
310 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */
311 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */
312 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
313 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
314 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */
315 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */
316 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
317 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
318 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
319 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */
320 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */
321 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */
322 >;
323 };
324
325 pinctrl_audmux: audmuxgrp {
326 fsl,pins = <
327 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
328 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
329 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
330 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
331 >;
332 };
333
334 pinctrl_enet: enetgrp {
335 fsl,pins = <
336 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
337 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
338 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
339 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
340 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
341 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
342 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
343 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
344 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
345 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
346 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
347 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
348 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
349 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
350 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
351 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
352 >;
353 };
354
355 pinctrl_gpmi_nand: gpminandgrp {
356 fsl,pins = <
357 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
358 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
359 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
360 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
361 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
362 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
363 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
364 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
365 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
366 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
367 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
368 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
369 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
370 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
371 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
372 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
373 >;
374 };
375
376 pinctrl_i2c1: i2c1grp {
377 fsl,pins = <
378 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
379 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
380 >;
381 };
382
383 pinctrl_i2c2: i2c2grp {
384 fsl,pins = <
385 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
386 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
387 >;
388 };
389
390 pinctrl_i2c3: i2c3grp {
391 fsl,pins = <
392 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
393 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
394 >;
395 };
396
397 pinctrl_uart1: uart1grp {
398 fsl,pins = <
399 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
400 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
401 >;
402 };
403
404 pinctrl_uart2: uart2grp {
405 fsl,pins = <
406 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
407 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
408 >;
409 };
410
411 pinctrl_uart5: uart5grp {
412 fsl,pins = <
413 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
414 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
415 >;
416 };
417
418 pinctrl_usbotg: usbotggrp {
419 fsl,pins = <
420 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
421 >;
422 };
423
424 pinctrl_usdhc3: usdhc3grp {
425 fsl,pins = <
426 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
427 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
428 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
429 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
430 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
431 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
432 >;
433 };
434 };
435};
436
437&ldb {
438 status = "okay";
439 lvds-channel@0 {
440 crtcs = <&ipu1 0>, <&ipu1 1>;
441 };
442};
443
444&pcie {
445 reset-gpio = <&gpio1 29 0>;
446 status = "okay";
447};
448
449&ssi1 {
450 fsl,mode = "i2s-slave";
451 status = "okay";
452};
453
454&uart1 {
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_uart1>;
457 status = "okay";
458};
459
460&uart2 {
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_uart2>;
463 status = "okay";
464};
465
466&uart5 {
467 pinctrl-names = "default";
468 pinctrl-0 = <&pinctrl_uart5>;
469 status = "okay";
470};
471
472&usbotg {
473 vbus-supply = <&reg_usb_otg_vbus>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_usbotg>;
476 disable-over-current;
477 status = "okay";
478};
479
480&usbh1 {
481 status = "okay";
482};
483
484&usdhc3 {
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_usdhc3>;
487 cd-gpios = <&gpio7 0 0>;
488 vmmc-supply = <&reg_3p3v>;
489 status = "okay";
490};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
new file mode 100644
index 000000000000..c8e5ae06deaf
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -0,0 +1,553 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 /* these are used by bootloader for disabling nodes */
14 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 ethernet1 = &eth1;
18 led0 = &led0;
19 led1 = &led1;
20 led2 = &led2;
21 nand = &gpmi;
22 sky2 = &eth1;
23 ssi0 = &ssi1;
24 usb0 = &usbh1;
25 usb1 = &usbotg;
26 usdhc2 = &usdhc3;
27 };
28
29 chosen {
30 bootargs = "console=ttymxc1,115200";
31 };
32
33 leds {
34 compatible = "gpio-leds";
35
36 led0: user1 {
37 label = "user1";
38 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
39 default-state = "on";
40 linux,default-trigger = "heartbeat";
41 };
42
43 led1: user2 {
44 label = "user2";
45 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
46 default-state = "off";
47 };
48
49 led2: user3 {
50 label = "user3";
51 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
52 default-state = "off";
53 };
54 };
55
56 memory {
57 reg = <0x10000000 0x40000000>;
58 };
59
60 pps {
61 compatible = "pps-gpio";
62 gpios = <&gpio1 26 0>;
63 status = "okay";
64 };
65
66 regulators {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 reg_1p0v: regulator@0 {
72 compatible = "regulator-fixed";
73 reg = <0>;
74 regulator-name = "1P0V";
75 regulator-min-microvolt = <1000000>;
76 regulator-max-microvolt = <1000000>;
77 regulator-always-on;
78 };
79
80 /* remove when pmic 1p8 regulator available */
81 reg_1p8v: regulator@1 {
82 compatible = "regulator-fixed";
83 reg = <1>;
84 regulator-name = "1P8V";
85 regulator-min-microvolt = <1800000>;
86 regulator-max-microvolt = <1800000>;
87 regulator-always-on;
88 };
89
90 reg_3p3v: regulator@2 {
91 compatible = "regulator-fixed";
92 reg = <2>;
93 regulator-name = "3P3V";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
96 regulator-always-on;
97 };
98
99 reg_usb_h1_vbus: regulator@3 {
100 compatible = "regulator-fixed";
101 reg = <3>;
102 regulator-name = "usb_h1_vbus";
103 regulator-min-microvolt = <5000000>;
104 regulator-max-microvolt = <5000000>;
105 regulator-always-on;
106 };
107
108 reg_usb_otg_vbus: regulator@4 {
109 compatible = "regulator-fixed";
110 reg = <4>;
111 regulator-name = "usb_otg_vbus";
112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <5000000>;
114 gpio = <&gpio3 22 0>;
115 enable-active-high;
116 };
117 };
118
119 sound {
120 compatible = "fsl,imx6q-sabrelite-sgtl5000",
121 "fsl,imx-audio-sgtl5000";
122 model = "imx6q-sabrelite-sgtl5000";
123 ssi-controller = <&ssi1>;
124 audio-codec = <&codec>;
125 audio-routing =
126 "MIC_IN", "Mic Jack",
127 "Mic Jack", "Mic Bias",
128 "Headphone Jack", "HP_OUT";
129 mux-int-port = <1>;
130 mux-ext-port = <4>;
131 };
132};
133
134&audmux {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_audmux>;
137 status = "okay";
138};
139
140&can1 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_flexcan1>;
143 status = "okay";
144};
145
146&fec {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_enet>;
149 phy-mode = "rgmii";
150 phy-reset-gpios = <&gpio1 30 0>;
151 status = "okay";
152};
153
154&gpmi {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_gpmi_nand>;
157 status = "okay";
158};
159
160&i2c1 {
161 clock-frequency = <100000>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_i2c1>;
164 status = "okay";
165
166 eeprom1: eeprom@50 {
167 compatible = "atmel,24c02";
168 reg = <0x50>;
169 pagesize = <16>;
170 };
171
172 eeprom2: eeprom@51 {
173 compatible = "atmel,24c02";
174 reg = <0x51>;
175 pagesize = <16>;
176 };
177
178 eeprom3: eeprom@52 {
179 compatible = "atmel,24c02";
180 reg = <0x52>;
181 pagesize = <16>;
182 };
183
184 eeprom4: eeprom@53 {
185 compatible = "atmel,24c02";
186 reg = <0x53>;
187 pagesize = <16>;
188 };
189
190 gpio: pca9555@23 {
191 compatible = "nxp,pca9555";
192 reg = <0x23>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 };
196
197 hwmon: gsc@29 {
198 compatible = "gw,gsp";
199 reg = <0x29>;
200 };
201
202 rtc: ds1672@68 {
203 compatible = "dallas,ds1672";
204 reg = <0x68>;
205 };
206};
207
208&i2c2 {
209 clock-frequency = <100000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c2>;
212 status = "okay";
213
214 pciclkgen: si53156@6b {
215 compatible = "sil,si53156";
216 reg = <0x6b>;
217 };
218
219 pciswitch: pex8606@3f {
220 compatible = "plx,pex8606";
221 reg = <0x3f>;
222 };
223
224 pmic: ltc3676@3c {
225 compatible = "ltc,ltc3676";
226 reg = <0x3c>;
227
228 regulators {
229 /* VDD_SOC */
230 sw1_reg: ltc3676__sw1 {
231 regulator-min-microvolt = <1175000>;
232 regulator-max-microvolt = <1175000>;
233 regulator-boot-on;
234 regulator-always-on;
235 };
236
237 /* VDD_1P8 */
238 sw2_reg: ltc3676__sw2 {
239 regulator-min-microvolt = <1800000>;
240 regulator-max-microvolt = <1800000>;
241 regulator-boot-on;
242 regulator-always-on;
243 };
244
245 /* VDD_ARM */
246 sw3_reg: ltc3676__sw3 {
247 regulator-min-microvolt = <1175000>;
248 regulator-max-microvolt = <1175000>;
249 regulator-boot-on;
250 regulator-always-on;
251 };
252
253 /* VDD_DDR */
254 sw4_reg: ltc3676__sw4 {
255 regulator-min-microvolt = <1500000>;
256 regulator-max-microvolt = <1500000>;
257 regulator-boot-on;
258 regulator-always-on;
259 };
260
261 /* VDD_2P5 */
262 ldo2_reg: ltc3676__ldo2 {
263 regulator-min-microvolt = <2500000>;
264 regulator-max-microvolt = <2500000>;
265 regulator-boot-on;
266 regulator-always-on;
267 };
268
269 /* VDD_1P8 */
270 ldo3_reg: ltc3676__ldo3 {
271 regulator-min-microvolt = <1800000>;
272 regulator-max-microvolt = <1800000>;
273 regulator-boot-on;
274 regulator-always-on;
275 };
276
277 /* VDD_HIGH */
278 ldo4_reg: ltc3676__ldo4 {
279 regulator-min-microvolt = <3000000>;
280 regulator-max-microvolt = <3000000>;
281 };
282 };
283 };
284};
285
286&i2c3 {
287 clock-frequency = <100000>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_i2c3>;
290 status = "okay";
291
292 accelerometer: fxos8700@1e {
293 compatible = "fsl,fxos8700";
294 reg = <0x1e>;
295 };
296
297 codec: sgtl5000@0a {
298 compatible = "fsl,sgtl5000";
299 reg = <0x0a>;
300 clocks = <&clks 201>;
301 VDDA-supply = <&reg_1p8v>;
302 VDDIO-supply = <&reg_3p3v>;
303 };
304
305 hdmiin: adv7611@4c {
306 compatible = "adi,adv7611";
307 reg = <0x4c>;
308 };
309
310 touchscreen: egalax_ts@04 {
311 compatible = "eeti,egalax_ts";
312 reg = <0x04>;
313 interrupt-parent = <&gpio1>;
314 interrupts = <11 2>; /* gpio1_11 active low */
315 wakeup-gpios = <&gpio1 11 0>;
316 };
317
318 videoout: adv7393@2a {
319 compatible = "adi,adv7393";
320 reg = <0x2a>;
321 };
322
323 videoin: adv7180@20 {
324 compatible = "adi,adv7180";
325 reg = <0x20>;
326 };
327};
328
329&iomuxc {
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_hog>;
332
333 imx6qdl-gw53xx {
334 pinctrl_hog: hoggrp {
335 fsl,pins = <
336 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */
337 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */
338 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
339 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */
340 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
341 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
342 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */
343 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
344 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */
345 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */
346 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */
347 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */
348 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */
349 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
350 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */
351 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
352 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
353 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */
354 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */
355 >;
356 };
357
358 pinctrl_audmux: audmuxgrp {
359 fsl,pins = <
360 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
361 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
362 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
363 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
364 >;
365 };
366
367 pinctrl_enet: enetgrp {
368 fsl,pins = <
369 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
370 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
371 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
372 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
373 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
374 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
375 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
376 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
377 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
378 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
379 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
380 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
381 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
382 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
383 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
384 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
385 >;
386 };
387
388 pinctrl_flexcan1: flexcan1grp {
389 fsl,pins = <
390 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
391 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
392 >;
393 };
394
395 pinctrl_gpmi_nand: gpminandgrp {
396 fsl,pins = <
397 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
398 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
399 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
400 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
401 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
402 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
403 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
404 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
405 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
406 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
407 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
408 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
409 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
410 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
411 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
412 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
413 >;
414 };
415
416 pinctrl_i2c1: i2c1grp {
417 fsl,pins = <
418 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
419 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
420 >;
421 };
422
423 pinctrl_i2c2: i2c2grp {
424 fsl,pins = <
425 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
426 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
427 >;
428 };
429
430 pinctrl_i2c3: i2c3grp {
431 fsl,pins = <
432 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
433 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
434 >;
435 };
436
437 pinctrl_uart1: uart1grp {
438 fsl,pins = <
439 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
440 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
441 >;
442 };
443
444 pinctrl_uart2: uart2grp {
445 fsl,pins = <
446 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
447 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
448 >;
449 };
450
451 pinctrl_uart5: uart5grp {
452 fsl,pins = <
453 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
454 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
455 >;
456 };
457
458 pinctrl_usbotg: usbotggrp {
459 fsl,pins = <
460 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
461 >;
462 };
463
464 pinctrl_usdhc3: usdhc3grp {
465 fsl,pins = <
466 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
467 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
468 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
469 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
470 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
471 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
472 >;
473 };
474 };
475};
476
477&ldb {
478 status = "okay";
479
480 lvds-channel@1 {
481 fsl,data-mapping = "spwg";
482 fsl,data-width = <18>;
483 status = "okay";
484
485 display-timings {
486 native-mode = <&timing0>;
487 timing0: hsd100pxn1 {
488 clock-frequency = <65000000>;
489 hactive = <1024>;
490 vactive = <768>;
491 hback-porch = <220>;
492 hfront-porch = <40>;
493 vback-porch = <21>;
494 vfront-porch = <7>;
495 hsync-len = <60>;
496 vsync-len = <10>;
497 };
498 };
499 };
500};
501
502&pcie {
503 reset-gpio = <&gpio1 29 0>;
504 status = "okay";
505
506 eth1: sky2@8 { /* MAC/PHY on bus 8 */
507 compatible = "marvell,sky2";
508 };
509};
510
511&ssi1 {
512 fsl,mode = "i2s-slave";
513 status = "okay";
514};
515
516&uart1 {
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_uart1>;
519 status = "okay";
520};
521
522&uart2 {
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_uart2>;
525 status = "okay";
526};
527
528&uart5 {
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_uart5>;
531 status = "okay";
532};
533
534&usbotg {
535 vbus-supply = <&reg_usb_otg_vbus>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_usbotg>;
538 disable-over-current;
539 status = "okay";
540};
541
542&usbh1 {
543 vbus-supply = <&reg_usb_h1_vbus>;
544 status = "okay";
545};
546
547&usdhc3 {
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_usdhc3>;
550 cd-gpios = <&gpio7 0 0>;
551 vmmc-supply = <&reg_3p3v>;
552 status = "okay";
553};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
new file mode 100644
index 000000000000..2795dfc8c926
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -0,0 +1,580 @@
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 /* these are used by bootloader for disabling nodes */
14 aliases {
15 can0 = &can1;
16 ethernet0 = &fec;
17 ethernet1 = &eth1;
18 led0 = &led0;
19 led1 = &led1;
20 led2 = &led2;
21 nand = &gpmi;
22 sky2 = &eth1;
23 ssi0 = &ssi1;
24 usb0 = &usbh1;
25 usb1 = &usbotg;
26 usdhc2 = &usdhc3;
27 };
28
29 chosen {
30 bootargs = "console=ttymxc1,115200";
31 };
32
33 leds {
34 compatible = "gpio-leds";
35
36 led0: user1 {
37 label = "user1";
38 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
39 default-state = "on";
40 linux,default-trigger = "heartbeat";
41 };
42
43 led1: user2 {
44 label = "user2";
45 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
46 default-state = "off";
47 };
48
49 led2: user3 {
50 label = "user3";
51 gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
52 default-state = "off";
53 };
54 };
55
56 memory {
57 reg = <0x10000000 0x40000000>;
58 };
59
60 pps {
61 compatible = "pps-gpio";
62 gpios = <&gpio1 26 0>;
63 status = "okay";
64 };
65
66 regulators {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 reg_1p0v: regulator@0 {
72 compatible = "regulator-fixed";
73 reg = <0>;
74 regulator-name = "1P0V";
75 regulator-min-microvolt = <1000000>;
76 regulator-max-microvolt = <1000000>;
77 regulator-always-on;
78 };
79
80 reg_3p3v: regulator@1 {
81 compatible = "regulator-fixed";
82 reg = <1>;
83 regulator-name = "3P3V";
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 regulator-always-on;
87 };
88
89 reg_usb_h1_vbus: regulator@2 {
90 compatible = "regulator-fixed";
91 reg = <2>;
92 regulator-name = "usb_h1_vbus";
93 regulator-min-microvolt = <5000000>;
94 regulator-max-microvolt = <5000000>;
95 regulator-always-on;
96 };
97
98 reg_usb_otg_vbus: regulator@3 {
99 compatible = "regulator-fixed";
100 reg = <3>;
101 regulator-name = "usb_otg_vbus";
102 regulator-min-microvolt = <5000000>;
103 regulator-max-microvolt = <5000000>;
104 gpio = <&gpio3 22 0>;
105 enable-active-high;
106 };
107 };
108
109 sound {
110 compatible = "fsl,imx6q-sabrelite-sgtl5000",
111 "fsl,imx-audio-sgtl5000";
112 model = "imx6q-sabrelite-sgtl5000";
113 ssi-controller = <&ssi1>;
114 audio-codec = <&codec>;
115 audio-routing =
116 "MIC_IN", "Mic Jack",
117 "Mic Jack", "Mic Bias",
118 "Headphone Jack", "HP_OUT";
119 mux-int-port = <1>;
120 mux-ext-port = <4>;
121 };
122};
123
124&audmux {
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
127 status = "okay";
128};
129
130&can1 {
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_flexcan1>;
133 status = "okay";
134};
135
136&fec {
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_enet>;
139 phy-mode = "rgmii";
140 phy-reset-gpios = <&gpio1 30 0>;
141 status = "okay";
142};
143
144&gpmi {
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_gpmi_nand>;
147 status = "okay";
148};
149
150&i2c1 {
151 clock-frequency = <100000>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c1>;
154 status = "okay";
155
156 eeprom1: eeprom@50 {
157 compatible = "atmel,24c02";
158 reg = <0x50>;
159 pagesize = <16>;
160 };
161
162 eeprom2: eeprom@51 {
163 compatible = "atmel,24c02";
164 reg = <0x51>;
165 pagesize = <16>;
166 };
167
168 eeprom3: eeprom@52 {
169 compatible = "atmel,24c02";
170 reg = <0x52>;
171 pagesize = <16>;
172 };
173
174 eeprom4: eeprom@53 {
175 compatible = "atmel,24c02";
176 reg = <0x53>;
177 pagesize = <16>;
178 };
179
180 gpio: pca9555@23 {
181 compatible = "nxp,pca9555";
182 reg = <0x23>;
183 gpio-controller;
184 #gpio-cells = <2>;
185 };
186
187 hwmon: gsc@29 {
188 compatible = "gw,gsp";
189 reg = <0x29>;
190 };
191
192 rtc: ds1672@68 {
193 compatible = "dallas,ds1672";
194 reg = <0x68>;
195 };
196};
197
198&i2c2 {
199 clock-frequency = <100000>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c2>;
202 status = "okay";
203
204 pmic: pfuze100@08 {
205 compatible = "fsl,pfuze100";
206 reg = <0x08>;
207
208 regulators {
209 sw1a_reg: sw1ab {
210 regulator-min-microvolt = <300000>;
211 regulator-max-microvolt = <1875000>;
212 regulator-boot-on;
213 regulator-always-on;
214 regulator-ramp-delay = <6250>;
215 };
216
217 sw1c_reg: sw1c {
218 regulator-min-microvolt = <300000>;
219 regulator-max-microvolt = <1875000>;
220 regulator-boot-on;
221 regulator-always-on;
222 regulator-ramp-delay = <6250>;
223 };
224
225 sw2_reg: sw2 {
226 regulator-min-microvolt = <800000>;
227 regulator-max-microvolt = <3950000>;
228 regulator-boot-on;
229 regulator-always-on;
230 };
231
232 sw3a_reg: sw3a {
233 regulator-min-microvolt = <400000>;
234 regulator-max-microvolt = <1975000>;
235 regulator-boot-on;
236 regulator-always-on;
237 };
238
239 sw3b_reg: sw3b {
240 regulator-min-microvolt = <400000>;
241 regulator-max-microvolt = <1975000>;
242 regulator-boot-on;
243 regulator-always-on;
244 };
245
246 sw4_reg: sw4 {
247 regulator-min-microvolt = <800000>;
248 regulator-max-microvolt = <3300000>;
249 };
250
251 swbst_reg: swbst {
252 regulator-min-microvolt = <5000000>;
253 regulator-max-microvolt = <5150000>;
254 };
255
256 snvs_reg: vsnvs {
257 regulator-min-microvolt = <1000000>;
258 regulator-max-microvolt = <3000000>;
259 regulator-boot-on;
260 regulator-always-on;
261 };
262
263 vref_reg: vrefddr {
264 regulator-boot-on;
265 regulator-always-on;
266 };
267
268 vgen1_reg: vgen1 {
269 regulator-min-microvolt = <800000>;
270 regulator-max-microvolt = <1550000>;
271 };
272
273 vgen2_reg: vgen2 {
274 regulator-min-microvolt = <800000>;
275 regulator-max-microvolt = <1550000>;
276 };
277
278 vgen3_reg: vgen3 {
279 regulator-min-microvolt = <1800000>;
280 regulator-max-microvolt = <3300000>;
281 };
282
283 vgen4_reg: vgen4 {
284 regulator-min-microvolt = <1800000>;
285 regulator-max-microvolt = <3300000>;
286 regulator-always-on;
287 };
288
289 vgen5_reg: vgen5 {
290 regulator-min-microvolt = <1800000>;
291 regulator-max-microvolt = <3300000>;
292 regulator-always-on;
293 };
294
295 vgen6_reg: vgen6 {
296 regulator-min-microvolt = <1800000>;
297 regulator-max-microvolt = <3300000>;
298 regulator-always-on;
299 };
300 };
301 };
302
303 pciswitch: pex8609@3f {
304 compatible = "plx,pex8609";
305 reg = <0x3f>;
306 };
307
308 pciclkgen: si52147@6b {
309 compatible = "sil,si52147";
310 reg = <0x6b>;
311 };
312};
313
314&i2c3 {
315 clock-frequency = <100000>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_i2c3>;
318 status = "okay";
319
320 accelerometer: fxos8700@1e {
321 compatible = "fsl,fxos8700";
322 reg = <0x1e>;
323 };
324
325 codec: sgtl5000@0a {
326 compatible = "fsl,sgtl5000";
327 reg = <0x0a>;
328 clocks = <&clks 201>;
329 VDDA-supply = <&sw4_reg>;
330 VDDIO-supply = <&reg_3p3v>;
331 };
332
333 hdmiin: adv7611@4c {
334 compatible = "adi,adv7611";
335 reg = <0x4c>;
336 };
337
338 touchscreen: egalax_ts@04 {
339 compatible = "eeti,egalax_ts";
340 reg = <0x04>;
341 interrupt-parent = <&gpio7>;
342 interrupts = <12 2>; /* gpio7_12 active low */
343 wakeup-gpios = <&gpio7 12 0>;
344 };
345
346 videoout: adv7393@2a {
347 compatible = "adi,adv7393";
348 reg = <0x2a>;
349 };
350
351 videoin: adv7180@20 {
352 compatible = "adi,adv7180";
353 reg = <0x20>;
354 };
355};
356
357&iomuxc {
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_hog>;
360
361 imx6qdl-gw54xx {
362 pinctrl_hog: hoggrp {
363 fsl,pins = <
364 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
365 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */
366 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
367 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
368 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */
369 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
370 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */
371 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */
372 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
373 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
374 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
375 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */
376 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */
377 >;
378 };
379
380 pinctrl_audmux: audmuxgrp {
381 fsl,pins = <
382 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
383 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
384 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
385 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
386 >;
387 };
388
389 pinctrl_enet: enetgrp {
390 fsl,pins = <
391 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
392 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
393 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
394 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
395 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
396 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
397 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
398 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
399 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
400 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
401 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
402 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
403 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
404 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
405 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
406 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
407 >;
408 };
409
410 pinctrl_flexcan1: flexcan1grp {
411 fsl,pins = <
412 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
413 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
414 >;
415 };
416
417 pinctrl_gpmi_nand: gpminandgrp {
418 fsl,pins = <
419 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
420 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
421 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
422 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
423 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
424 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
425 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
426 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
427 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
428 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
429 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
430 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
431 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
432 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
433 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
434 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
435 >;
436 };
437
438 pinctrl_i2c1: i2c1grp {
439 fsl,pins = <
440 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
441 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
442 >;
443 };
444
445 pinctrl_i2c2: i2c2grp {
446 fsl,pins = <
447 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
448 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
449 >;
450 };
451
452 pinctrl_i2c3: i2c3grp {
453 fsl,pins = <
454 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
455 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
456 >;
457 };
458
459 pinctrl_uart1: uart1grp {
460 fsl,pins = <
461 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
462 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
463 >;
464 };
465
466 pinctrl_uart2: uart2grp {
467 fsl,pins = <
468 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
469 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
470 >;
471 };
472
473 pinctrl_uart5: uart5grp {
474 fsl,pins = <
475 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
476 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
477 >;
478 };
479
480 pinctrl_usbotg: usbotggrp {
481 fsl,pins = <
482 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
483 >;
484 };
485
486 pinctrl_usdhc3: usdhc3grp {
487 fsl,pins = <
488 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
489 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
490 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
491 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
492 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
493 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
494 >;
495 };
496 };
497};
498
499&ldb {
500 status = "okay";
501
502 lvds-channel@1 {
503 fsl,data-mapping = "spwg";
504 fsl,data-width = <18>;
505 status = "okay";
506
507 display-timings {
508 native-mode = <&timing0>;
509 timing0: hsd100pxn1 {
510 clock-frequency = <65000000>;
511 hactive = <1024>;
512 vactive = <768>;
513 hback-porch = <220>;
514 hfront-porch = <40>;
515 vback-porch = <21>;
516 vfront-porch = <7>;
517 hsync-len = <60>;
518 vsync-len = <10>;
519 };
520 };
521 };
522};
523
524&pcie {
525 reset-gpio = <&gpio1 29 0>;
526 status = "okay";
527
528 eth1: sky2@8 { /* MAC/PHY on bus 8 */
529 compatible = "marvell,sky2";
530 };
531};
532
533&ssi1 {
534 fsl,mode = "i2s-slave";
535 status = "okay";
536};
537
538&ssi2 {
539 fsl,mode = "i2s-slave";
540 status = "okay";
541};
542
543&uart1 {
544 pinctrl-names = "default";
545 pinctrl-0 = <&pinctrl_uart1>;
546 status = "okay";
547};
548
549&uart2 {
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_uart2>;
552 status = "okay";
553};
554
555&uart5 {
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_uart5>;
558 status = "okay";
559};
560
561&usbotg {
562 vbus-supply = <&reg_usb_otg_vbus>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&pinctrl_usbotg>;
565 disable-over-current;
566 status = "okay";
567};
568
569&usbh1 {
570 vbus-supply = <&reg_usb_h1_vbus>;
571 status = "okay";
572};
573
574&usdhc3 {
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_usdhc3>;
577 cd-gpios = <&gpio7 0 0>;
578 vmmc-supply = <&reg_3p3v>;
579 status = "okay";
580};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
new file mode 100644
index 000000000000..99be301b5232
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -0,0 +1,422 @@
1/*
2 * Copyright 2013 Boundary Devices, Inc.
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15
16/ {
17 memory {
18 reg = <0x10000000 0x40000000>;
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 reg_2p5v: regulator@0 {
27 compatible = "regulator-fixed";
28 reg = <0>;
29 regulator-name = "2P5V";
30 regulator-min-microvolt = <2500000>;
31 regulator-max-microvolt = <2500000>;
32 regulator-always-on;
33 };
34
35 reg_3p3v: regulator@1 {
36 compatible = "regulator-fixed";
37 reg = <1>;
38 regulator-name = "3P3V";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 regulator-always-on;
42 };
43
44 reg_usb_otg_vbus: regulator@2 {
45 compatible = "regulator-fixed";
46 reg = <2>;
47 regulator-name = "usb_otg_vbus";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 gpio = <&gpio3 22 0>;
51 enable-active-high;
52 };
53 };
54
55 gpio-keys {
56 compatible = "gpio-keys";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_gpio_keys>;
59
60 power {
61 label = "Power Button";
62 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
63 linux,code = <KEY_POWER>;
64 gpio-key,wakeup;
65 };
66
67 menu {
68 label = "Menu";
69 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
70 linux,code = <KEY_MENU>;
71 };
72
73 home {
74 label = "Home";
75 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
76 linux,code = <KEY_HOME>;
77 };
78
79 back {
80 label = "Back";
81 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_BACK>;
83 };
84
85 volume-up {
86 label = "Volume Up";
87 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
88 linux,code = <KEY_VOLUMEUP>;
89 };
90
91 volume-down {
92 label = "Volume Down";
93 gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
94 linux,code = <KEY_VOLUMEDOWN>;
95 };
96 };
97
98 sound {
99 compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
100 "fsl,imx-audio-sgtl5000";
101 model = "imx6q-nitrogen6x-sgtl5000";
102 ssi-controller = <&ssi1>;
103 audio-codec = <&codec>;
104 audio-routing =
105 "MIC_IN", "Mic Jack",
106 "Mic Jack", "Mic Bias",
107 "Headphone Jack", "HP_OUT";
108 mux-int-port = <1>;
109 mux-ext-port = <3>;
110 };
111
112 backlight_lcd {
113 compatible = "pwm-backlight";
114 pwms = <&pwm1 0 5000000>;
115 brightness-levels = <0 4 8 16 32 64 128 255>;
116 default-brightness-level = <7>;
117 power-supply = <&reg_3p3v>;
118 status = "okay";
119 };
120
121 backlight_lvds {
122 compatible = "pwm-backlight";
123 pwms = <&pwm4 0 5000000>;
124 brightness-levels = <0 4 8 16 32 64 128 255>;
125 default-brightness-level = <7>;
126 power-supply = <&reg_3p3v>;
127 status = "okay";
128 };
129};
130
131&audmux {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_audmux>;
134 status = "okay";
135};
136
137&ecspi1 {
138 fsl,spi-num-chipselects = <1>;
139 cs-gpios = <&gpio3 19 0>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_ecspi1>;
142 status = "okay";
143
144 flash: m25p80@0 {
145 compatible = "sst,sst25vf016b";
146 spi-max-frequency = <20000000>;
147 reg = <0>;
148 };
149};
150
151&fec {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_enet>;
154 phy-mode = "rgmii";
155 phy-reset-gpios = <&gpio1 27 0>;
156 txen-skew-ps = <0>;
157 txc-skew-ps = <3000>;
158 rxdv-skew-ps = <0>;
159 rxc-skew-ps = <3000>;
160 rxd0-skew-ps = <0>;
161 rxd1-skew-ps = <0>;
162 rxd2-skew-ps = <0>;
163 rxd3-skew-ps = <0>;
164 txd0-skew-ps = <0>;
165 txd1-skew-ps = <0>;
166 txd2-skew-ps = <0>;
167 txd3-skew-ps = <0>;
168 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
169 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
170 status = "okay";
171};
172
173&i2c1 {
174 clock-frequency = <100000>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_i2c1>;
177 status = "okay";
178
179 codec: sgtl5000@0a {
180 compatible = "fsl,sgtl5000";
181 reg = <0x0a>;
182 clocks = <&clks 201>;
183 VDDA-supply = <&reg_2p5v>;
184 VDDIO-supply = <&reg_3p3v>;
185 };
186};
187
188&iomuxc {
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_hog>;
191
192 imx6q-nitrogen6x {
193 pinctrl_hog: hoggrp {
194 fsl,pins = <
195 /* SGTL5000 sys_mclk */
196 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
197 >;
198 };
199
200 pinctrl_audmux: audmuxgrp {
201 fsl,pins = <
202 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
203 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
204 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
205 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
206 >;
207 };
208
209 pinctrl_ecspi1: ecspi1grp {
210 fsl,pins = <
211 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
212 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
213 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
214 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
215 >;
216 };
217
218 pinctrl_enet: enetgrp {
219 fsl,pins = <
220 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
221 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
222 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
223 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
224 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
225 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
226 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
227 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
228 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
229 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
230 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
231 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
232 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
233 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
234 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
235 /* Phy reset */
236 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
237 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
238 >;
239 };
240
241 pinctrl_gpio_keys: gpio_keysgrp {
242 fsl,pins = <
243 /* Power Button */
244 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
245 /* Menu Button */
246 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
247 /* Home Button */
248 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
249 /* Back Button */
250 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
251 /* Volume Up Button */
252 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
253 /* Volume Down Button */
254 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
255 >;
256 };
257
258 pinctrl_i2c1: i2c1grp {
259 fsl,pins = <
260 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
261 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
262 >;
263 };
264
265 pinctrl_pwm1: pwm1grp {
266 fsl,pins = <
267 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
268 >;
269 };
270
271 pinctrl_pwm3: pwm3grp {
272 fsl,pins = <
273 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
274 >;
275 };
276
277 pinctrl_pwm4: pwm4grp {
278 fsl,pins = <
279 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
280 >;
281 };
282
283 pinctrl_uart1: uart1grp {
284 fsl,pins = <
285 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
286 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
287 >;
288 };
289
290 pinctrl_uart2: uart2grp {
291 fsl,pins = <
292 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
293 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
294 >;
295 };
296
297 pinctrl_usbotg: usbotggrp {
298 fsl,pins = <
299 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
300 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
301 /* power enable, high active */
302 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
303 >;
304 };
305
306 pinctrl_usdhc3: usdhc3grp {
307 fsl,pins = <
308 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
309 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
310 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
311 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
312 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
313 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
314 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
315 >;
316 };
317
318 pinctrl_usdhc4: usdhc4grp {
319 fsl,pins = <
320 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
321 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
322 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
323 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
324 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
325 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
326 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
327 >;
328 };
329 };
330};
331
332&ldb {
333 status = "okay";
334
335 lvds-channel@0 {
336 fsl,data-mapping = "spwg";
337 fsl,data-width = <18>;
338 status = "okay";
339
340 display-timings {
341 native-mode = <&timing0>;
342 timing0: hsd100pxn1 {
343 clock-frequency = <65000000>;
344 hactive = <1024>;
345 vactive = <768>;
346 hback-porch = <220>;
347 hfront-porch = <40>;
348 vback-porch = <21>;
349 vfront-porch = <7>;
350 hsync-len = <60>;
351 vsync-len = <10>;
352 };
353 };
354 };
355};
356
357&pcie {
358 status = "okay";
359};
360
361&pwm1 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_pwm1>;
364 status = "okay";
365};
366
367&pwm3 {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_pwm3>;
370 status = "okay";
371};
372
373&pwm4 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_pwm4>;
376 status = "okay";
377};
378
379&ssi1 {
380 fsl,mode = "i2s-slave";
381 status = "okay";
382};
383
384&uart1 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_uart1>;
387 status = "okay";
388};
389
390&uart2 {
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_uart2>;
393 status = "okay";
394};
395
396&usbh1 {
397 status = "okay";
398};
399
400&usbotg {
401 vbus-supply = <&reg_usb_otg_vbus>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_usbotg>;
404 disable-over-current;
405 status = "okay";
406};
407
408&usdhc3 {
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_usdhc3>;
411 cd-gpios = <&gpio7 0 0>;
412 vmmc-supply = <&reg_3p3v>;
413 status = "okay";
414};
415
416&usdhc4 {
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_usdhc4>;
419 cd-gpios = <&gpio2 6 0>;
420 vmmc-supply = <&reg_3p3v>;
421 status = "okay";
422};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index ff6f1e8f2dd9..009abd69385d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -10,17 +10,46 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13#include <dt-bindings/gpio/gpio.h>
14
13/ { 15/ {
14 memory { 16 memory {
15 reg = <0x10000000 0x80000000>; 17 reg = <0x10000000 0x80000000>;
16 }; 18 };
19
20 leds {
21 compatible = "gpio-leds";
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_gpio_leds>;
24
25 user {
26 label = "debug";
27 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
28 };
29 };
30
31 sound-spdif {
32 compatible = "fsl,imx-audio-spdif",
33 "fsl,imx-sabreauto-spdif";
34 model = "imx-spdif";
35 spdif-controller = <&spdif>;
36 spdif-in;
37 };
38
39 backlight {
40 compatible = "pwm-backlight";
41 pwms = <&pwm3 0 5000000>;
42 brightness-levels = <0 4 8 16 32 64 128 255>;
43 default-brightness-level = <7>;
44 status = "okay";
45 };
17}; 46};
18 47
19&ecspi1 { 48&ecspi1 {
20 fsl,spi-num-chipselects = <1>; 49 fsl,spi-num-chipselects = <1>;
21 cs-gpios = <&gpio3 19 0>; 50 cs-gpios = <&gpio3 19 0>;
22 pinctrl-names = "default"; 51 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>; 52 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
24 status = "disabled"; /* pin conflict with WEIM NOR */ 53 status = "disabled"; /* pin conflict with WEIM NOR */
25 54
26 flash: m25p80@0 { 55 flash: m25p80@0 {
@@ -34,22 +63,130 @@
34 63
35&fec { 64&fec {
36 pinctrl-names = "default"; 65 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_enet_2>; 66 pinctrl-0 = <&pinctrl_enet>;
38 phy-mode = "rgmii"; 67 phy-mode = "rgmii";
68 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
69 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
39 status = "okay"; 70 status = "okay";
40}; 71};
41 72
42&gpmi { 73&gpmi {
43 pinctrl-names = "default"; 74 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_gpmi_nand_1>; 75 pinctrl-0 = <&pinctrl_gpmi_nand>;
76 status = "okay";
77};
78
79&i2c2 {
80 clock-frequency = <100000>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_i2c2>;
45 status = "okay"; 83 status = "okay";
84
85 pmic: pfuze100@08 {
86 compatible = "fsl,pfuze100";
87 reg = <0x08>;
88
89 regulators {
90 sw1a_reg: sw1ab {
91 regulator-min-microvolt = <300000>;
92 regulator-max-microvolt = <1875000>;
93 regulator-boot-on;
94 regulator-always-on;
95 regulator-ramp-delay = <6250>;
96 };
97
98 sw1c_reg: sw1c {
99 regulator-min-microvolt = <300000>;
100 regulator-max-microvolt = <1875000>;
101 regulator-boot-on;
102 regulator-always-on;
103 regulator-ramp-delay = <6250>;
104 };
105
106 sw2_reg: sw2 {
107 regulator-min-microvolt = <800000>;
108 regulator-max-microvolt = <3300000>;
109 regulator-boot-on;
110 regulator-always-on;
111 };
112
113 sw3a_reg: sw3a {
114 regulator-min-microvolt = <400000>;
115 regulator-max-microvolt = <1975000>;
116 regulator-boot-on;
117 regulator-always-on;
118 };
119
120 sw3b_reg: sw3b {
121 regulator-min-microvolt = <400000>;
122 regulator-max-microvolt = <1975000>;
123 regulator-boot-on;
124 regulator-always-on;
125 };
126
127 sw4_reg: sw4 {
128 regulator-min-microvolt = <800000>;
129 regulator-max-microvolt = <3300000>;
130 };
131
132 swbst_reg: swbst {
133 regulator-min-microvolt = <5000000>;
134 regulator-max-microvolt = <5150000>;
135 };
136
137 snvs_reg: vsnvs {
138 regulator-min-microvolt = <1000000>;
139 regulator-max-microvolt = <3000000>;
140 regulator-boot-on;
141 regulator-always-on;
142 };
143
144 vref_reg: vrefddr {
145 regulator-boot-on;
146 regulator-always-on;
147 };
148
149 vgen1_reg: vgen1 {
150 regulator-min-microvolt = <800000>;
151 regulator-max-microvolt = <1550000>;
152 };
153
154 vgen2_reg: vgen2 {
155 regulator-min-microvolt = <800000>;
156 regulator-max-microvolt = <1550000>;
157 };
158
159 vgen3_reg: vgen3 {
160 regulator-min-microvolt = <1800000>;
161 regulator-max-microvolt = <3300000>;
162 };
163
164 vgen4_reg: vgen4 {
165 regulator-min-microvolt = <1800000>;
166 regulator-max-microvolt = <3300000>;
167 regulator-always-on;
168 };
169
170 vgen5_reg: vgen5 {
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <3300000>;
173 regulator-always-on;
174 };
175
176 vgen6_reg: vgen6 {
177 regulator-min-microvolt = <1800000>;
178 regulator-max-microvolt = <3300000>;
179 regulator-always-on;
180 };
181 };
182 };
46}; 183};
47 184
48&iomuxc { 185&iomuxc {
49 pinctrl-names = "default"; 186 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_hog>; 187 pinctrl-0 = <&pinctrl_hog>;
51 188
52 hog { 189 imx6qdl-sabreauto {
53 pinctrl_hog: hoggrp { 190 pinctrl_hog: hoggrp {
54 fsl,pins = < 191 fsl,pins = <
55 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 192 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
@@ -57,28 +194,245 @@
57 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 194 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
58 >; 195 >;
59 }; 196 };
60 };
61 197
62 ecspi1 { 198 pinctrl_ecspi1: ecspi1grp {
63 pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { 199 fsl,pins = <
200 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
201 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
202 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
203 >;
204 };
205
206 pinctrl_ecspi1_cs: ecspi1cs {
64 fsl,pins = < 207 fsl,pins = <
65 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 208 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
66 >; 209 >;
67 }; 210 };
211
212 pinctrl_enet: enetgrp {
213 fsl,pins = <
214 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
215 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
216 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
217 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
218 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
219 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
220 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
221 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
222 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
223 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
224 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
225 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
226 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
227 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
228 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
229 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
230 >;
231 };
232
233 pinctrl_gpio_leds: gpioledsgrp {
234 fsl,pins = <
235 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
236 >;
237 };
238
239 pinctrl_gpmi_nand: gpminandgrp {
240 fsl,pins = <
241 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
242 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
243 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
244 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
245 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
246 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
247 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
248 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
249 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
250 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
251 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
252 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
253 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
254 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
255 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
256 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
257 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
258 >;
259 };
260
261 pinctrl_i2c2: i2c2grp {
262 fsl,pins = <
263 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
264 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
265 >;
266 };
267
268 pinctrl_pwm3: pwm1grp {
269 fsl,pins = <
270 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
271 >;
272 };
273
274 pinctrl_spdif: spdifgrp {
275 fsl,pins = <
276 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
277 >;
278 };
279
280 pinctrl_uart4: uart4grp {
281 fsl,pins = <
282 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
283 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
284 >;
285 };
286
287 pinctrl_usdhc3: usdhc3grp {
288 fsl,pins = <
289 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
290 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
291 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
292 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
293 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
294 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
295 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
296 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
297 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
298 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
299 >;
300 };
301
302 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
303 fsl,pins = <
304 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
305 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
306 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
307 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
308 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
309 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
310 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
311 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
312 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
313 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
314 >;
315 };
316
317 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
318 fsl,pins = <
319 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
320 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
321 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
322 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
323 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
324 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
325 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
326 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
327 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
328 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
329 >;
330 };
331
332 pinctrl_weim_cs0: weimcs0grp {
333 fsl,pins = <
334 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
335 >;
336 };
337
338 pinctrl_weim_nor: weimnorgrp {
339 fsl,pins = <
340 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
341 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
342 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
343 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
344 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
345 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
346 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
347 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
348 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
349 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
350 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
351 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
352 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
353 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
354 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
355 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
356 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
357 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
358 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
359 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
360 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
361 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
362 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
363 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
364 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
365 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
366 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
367 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
368 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
369 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
370 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
371 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
372 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
373 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
374 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
375 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
376 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
377 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
378 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
379 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
380 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
381 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
382 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
383 >;
384 };
385 };
386};
387
388&ldb {
389 status = "okay";
390
391 lvds-channel@0 {
392 fsl,data-mapping = "spwg";
393 fsl,data-width = <18>;
394 status = "okay";
395
396 display-timings {
397 native-mode = <&timing0>;
398 timing0: hsd100pxn1 {
399 clock-frequency = <65000000>;
400 hactive = <1024>;
401 vactive = <768>;
402 hback-porch = <220>;
403 hfront-porch = <40>;
404 vback-porch = <21>;
405 vfront-porch = <7>;
406 hsync-len = <60>;
407 vsync-len = <10>;
408 };
409 };
68 }; 410 };
69}; 411};
70 412
413&pwm3 {
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_pwm3>;
416 status = "okay";
417};
418
419&spdif {
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_spdif>;
422 status = "okay";
423};
424
71&uart4 { 425&uart4 {
72 pinctrl-names = "default"; 426 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_uart4_1>; 427 pinctrl-0 = <&pinctrl_uart4>;
74 status = "okay"; 428 status = "okay";
75}; 429};
76 430
77&usdhc3 { 431&usdhc3 {
78 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 432 pinctrl-names = "default", "state_100mhz", "state_200mhz";
79 pinctrl-0 = <&pinctrl_usdhc3_1>; 433 pinctrl-0 = <&pinctrl_usdhc3>;
80 pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; 434 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
81 pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; 435 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
82 cd-gpios = <&gpio6 15 0>; 436 cd-gpios = <&gpio6 15 0>;
83 wp-gpios = <&gpio1 13 0>; 437 wp-gpios = <&gpio1 13 0>;
84 status = "okay"; 438 status = "okay";
@@ -86,7 +440,7 @@
86 440
87&weim { 441&weim {
88 pinctrl-names = "default"; 442 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; 443 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
90 #address-cells = <2>; 444 #address-cells = <2>;
91 #size-cells = <1>; 445 #size-cells = <1>;
92 ranges = <0 0 0x08000000 0x08000000>; 446 ranges = <0 0 0x08000000 0x08000000>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
new file mode 100644
index 000000000000..3bec128c7971
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -0,0 +1,423 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14
15/ {
16 memory {
17 reg = <0x10000000 0x40000000>;
18 };
19
20 regulators {
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 reg_2p5v: regulator@0 {
26 compatible = "regulator-fixed";
27 reg = <0>;
28 regulator-name = "2P5V";
29 regulator-min-microvolt = <2500000>;
30 regulator-max-microvolt = <2500000>;
31 regulator-always-on;
32 };
33
34 reg_3p3v: regulator@1 {
35 compatible = "regulator-fixed";
36 reg = <1>;
37 regulator-name = "3P3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 };
42
43 reg_usb_otg_vbus: regulator@2 {
44 compatible = "regulator-fixed";
45 reg = <2>;
46 regulator-name = "usb_otg_vbus";
47 regulator-min-microvolt = <5000000>;
48 regulator-max-microvolt = <5000000>;
49 gpio = <&gpio3 22 0>;
50 enable-active-high;
51 };
52 };
53
54 gpio-keys {
55 compatible = "gpio-keys";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_gpio_keys>;
58
59 power {
60 label = "Power Button";
61 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
62 linux,code = <KEY_POWER>;
63 gpio-key,wakeup;
64 };
65
66 menu {
67 label = "Menu";
68 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
69 linux,code = <KEY_MENU>;
70 };
71
72 home {
73 label = "Home";
74 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_HOME>;
76 };
77
78 back {
79 label = "Back";
80 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
81 linux,code = <KEY_BACK>;
82 };
83
84 volume-up {
85 label = "Volume Up";
86 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
87 linux,code = <KEY_VOLUMEUP>;
88 };
89
90 volume-down {
91 label = "Volume Down";
92 gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
93 linux,code = <KEY_VOLUMEDOWN>;
94 };
95 };
96
97 sound {
98 compatible = "fsl,imx6q-sabrelite-sgtl5000",
99 "fsl,imx-audio-sgtl5000";
100 model = "imx6q-sabrelite-sgtl5000";
101 ssi-controller = <&ssi1>;
102 audio-codec = <&codec>;
103 audio-routing =
104 "MIC_IN", "Mic Jack",
105 "Mic Jack", "Mic Bias",
106 "Headphone Jack", "HP_OUT";
107 mux-int-port = <1>;
108 mux-ext-port = <4>;
109 };
110
111 backlight_lcd {
112 compatible = "pwm-backlight";
113 pwms = <&pwm1 0 5000000>;
114 brightness-levels = <0 4 8 16 32 64 128 255>;
115 default-brightness-level = <7>;
116 power-supply = <&reg_3p3v>;
117 status = "okay";
118 };
119
120 backlight_lvds {
121 compatible = "pwm-backlight";
122 pwms = <&pwm4 0 5000000>;
123 brightness-levels = <0 4 8 16 32 64 128 255>;
124 default-brightness-level = <7>;
125 power-supply = <&reg_3p3v>;
126 status = "okay";
127 };
128};
129
130&audmux {
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_audmux>;
133 status = "okay";
134};
135
136&ecspi1 {
137 fsl,spi-num-chipselects = <1>;
138 cs-gpios = <&gpio3 19 0>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_ecspi1>;
141 status = "okay";
142
143 flash: m25p80@0 {
144 compatible = "sst,sst25vf016b";
145 spi-max-frequency = <20000000>;
146 reg = <0>;
147 };
148};
149
150&fec {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_enet>;
153 phy-mode = "rgmii";
154 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
155 txen-skew-ps = <0>;
156 txc-skew-ps = <3000>;
157 rxdv-skew-ps = <0>;
158 rxc-skew-ps = <3000>;
159 rxd0-skew-ps = <0>;
160 rxd1-skew-ps = <0>;
161 rxd2-skew-ps = <0>;
162 rxd3-skew-ps = <0>;
163 txd0-skew-ps = <0>;
164 txd1-skew-ps = <0>;
165 txd2-skew-ps = <0>;
166 txd3-skew-ps = <0>;
167 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
168 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
169 status = "okay";
170};
171
172&i2c1 {
173 clock-frequency = <100000>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c1>;
176 status = "okay";
177
178 codec: sgtl5000@0a {
179 compatible = "fsl,sgtl5000";
180 reg = <0x0a>;
181 clocks = <&clks 201>;
182 VDDA-supply = <&reg_2p5v>;
183 VDDIO-supply = <&reg_3p3v>;
184 };
185};
186
187&iomuxc {
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_hog>;
190
191 imx6q-sabrelite {
192 pinctrl_hog: hoggrp {
193 fsl,pins = <
194 /* SGTL5000 sys_mclk */
195 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
196 >;
197 };
198
199 pinctrl_audmux: audmuxgrp {
200 fsl,pins = <
201 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
202 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
203 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
204 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
205 >;
206 };
207
208 pinctrl_ecspi1: ecspi1grp {
209 fsl,pins = <
210 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
211 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
212 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
213 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
214 >;
215 };
216
217 pinctrl_enet: enetgrp {
218 fsl,pins = <
219 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
220 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
221 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
222 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
223 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
224 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
225 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
226 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
227 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
228 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
229 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
230 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
231 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
232 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
233 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
234 /* Phy reset */
235 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
236 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
237 >;
238 };
239
240 pinctrl_gpio_keys: gpio_keysgrp {
241 fsl,pins = <
242 /* Power Button */
243 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
244 /* Menu Button */
245 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
246 /* Home Button */
247 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
248 /* Back Button */
249 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
250 /* Volume Up Button */
251 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
252 /* Volume Down Button */
253 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
254 >;
255 };
256
257 pinctrl_i2c1: i2c1grp {
258 fsl,pins = <
259 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
260 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
261 >;
262 };
263
264 pinctrl_pwm1: pwm1grp {
265 fsl,pins = <
266 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
267 >;
268 };
269
270 pinctrl_pwm3: pwm3grp {
271 fsl,pins = <
272 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
273 >;
274 };
275
276 pinctrl_pwm4: pwm4grp {
277 fsl,pins = <
278 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
279 >;
280 };
281
282 pinctrl_uart1: uart1grp {
283 fsl,pins = <
284 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
285 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
286 >;
287 };
288
289 pinctrl_uart2: uart2grp {
290 fsl,pins = <
291 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
292 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
293 >;
294 };
295
296 pinctrl_usbotg: usbotggrp {
297 fsl,pins = <
298 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
299 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
300 /* power enable, high active */
301 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
302 >;
303 };
304
305 pinctrl_usdhc3: usdhc3grp {
306 fsl,pins = <
307 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
308 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
309 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
310 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
311 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
312 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
313 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
314 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
315 >;
316 };
317
318 pinctrl_usdhc4: usdhc4grp {
319 fsl,pins = <
320 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
321 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
322 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
323 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
324 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
325 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
326 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
327 >;
328 };
329 };
330};
331
332&ldb {
333 status = "okay";
334
335 lvds-channel@0 {
336 fsl,data-mapping = "spwg";
337 fsl,data-width = <18>;
338 status = "okay";
339
340 display-timings {
341 native-mode = <&timing0>;
342 timing0: hsd100pxn1 {
343 clock-frequency = <65000000>;
344 hactive = <1024>;
345 vactive = <768>;
346 hback-porch = <220>;
347 hfront-porch = <40>;
348 vback-porch = <21>;
349 vfront-porch = <7>;
350 hsync-len = <60>;
351 vsync-len = <10>;
352 };
353 };
354 };
355};
356
357&pcie {
358 status = "okay";
359};
360
361&pwm1 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_pwm1>;
364 status = "okay";
365};
366
367&pwm3 {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_pwm3>;
370 status = "okay";
371};
372
373&pwm4 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_pwm4>;
376 status = "okay";
377};
378
379&ssi1 {
380 fsl,mode = "i2s-slave";
381 status = "okay";
382};
383
384&uart1 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_uart1>;
387 status = "okay";
388};
389
390&uart2 {
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_uart2>;
393 status = "okay";
394};
395
396&usbh1 {
397 status = "okay";
398};
399
400&usbotg {
401 vbus-supply = <&reg_usb_otg_vbus>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_usbotg>;
404 disable-over-current;
405 status = "okay";
406};
407
408&usdhc3 {
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_usdhc3>;
411 cd-gpios = <&gpio7 0 0>;
412 wp-gpios = <&gpio7 1 0>;
413 vmmc-supply = <&reg_3p3v>;
414 status = "okay";
415};
416
417&usdhc4 {
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_usdhc4>;
420 cd-gpios = <&gpio2 6 0>;
421 vmmc-supply = <&reg_3p3v>;
422 status = "okay";
423};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index e75e11b36dff..0d816d3be4b6 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -10,6 +10,9 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15
13/ { 16/ {
14 memory { 17 memory {
15 reg = <0x10000000 0x40000000>; 18 reg = <0x10000000 0x40000000>;
@@ -17,9 +20,12 @@
17 20
18 regulators { 21 regulators {
19 compatible = "simple-bus"; 22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
20 25
21 reg_usb_otg_vbus: usb_otg_vbus { 26 reg_usb_otg_vbus: regulator@0 {
22 compatible = "regulator-fixed"; 27 compatible = "regulator-fixed";
28 reg = <0>;
23 regulator-name = "usb_otg_vbus"; 29 regulator-name = "usb_otg_vbus";
24 regulator-min-microvolt = <5000000>; 30 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>; 31 regulator-max-microvolt = <5000000>;
@@ -27,8 +33,9 @@
27 enable-active-high; 33 enable-active-high;
28 }; 34 };
29 35
30 reg_usb_h1_vbus: usb_h1_vbus { 36 reg_usb_h1_vbus: regulator@1 {
31 compatible = "regulator-fixed"; 37 compatible = "regulator-fixed";
38 reg = <1>;
32 regulator-name = "usb_h1_vbus"; 39 regulator-name = "usb_h1_vbus";
33 regulator-min-microvolt = <5000000>; 40 regulator-min-microvolt = <5000000>;
34 regulator-max-microvolt = <5000000>; 41 regulator-max-microvolt = <5000000>;
@@ -36,8 +43,9 @@
36 enable-active-high; 43 enable-active-high;
37 }; 44 };
38 45
39 reg_audio: wm8962_supply { 46 reg_audio: regulator@2 {
40 compatible = "regulator-fixed"; 47 compatible = "regulator-fixed";
48 reg = <2>;
41 regulator-name = "wm8962-supply"; 49 regulator-name = "wm8962-supply";
42 gpio = <&gpio4 10 0>; 50 gpio = <&gpio4 10 0>;
43 enable-active-high; 51 enable-active-high;
@@ -46,19 +54,28 @@
46 54
47 gpio-keys { 55 gpio-keys {
48 compatible = "gpio-keys"; 56 compatible = "gpio-keys";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_gpio_keys>;
59
60 power {
61 label = "Power Button";
62 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
63 gpio-key,wakeup;
64 linux,code = <KEY_POWER>;
65 };
49 66
50 volume-up { 67 volume-up {
51 label = "Volume Up"; 68 label = "Volume Up";
52 gpios = <&gpio1 4 0>; 69 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
53 gpio-key,wakeup; 70 gpio-key,wakeup;
54 linux,code = <115>; /* KEY_VOLUMEUP */ 71 linux,code = <KEY_VOLUMEUP>;
55 }; 72 };
56 73
57 volume-down { 74 volume-down {
58 label = "Volume Down"; 75 label = "Volume Down";
59 gpios = <&gpio1 5 0>; 76 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
60 gpio-key,wakeup; 77 gpio-key,wakeup;
61 linux,code = <114>; /* KEY_VOLUMEDOWN */ 78 linux,code = <KEY_VOLUMEDOWN>;
62 }; 79 };
63 }; 80 };
64 81
@@ -92,7 +109,7 @@
92 109
93&audmux { 110&audmux {
94 pinctrl-names = "default"; 111 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_audmux_2>; 112 pinctrl-0 = <&pinctrl_audmux>;
96 status = "okay"; 113 status = "okay";
97}; 114};
98 115
@@ -100,7 +117,7 @@
100 fsl,spi-num-chipselects = <1>; 117 fsl,spi-num-chipselects = <1>;
101 cs-gpios = <&gpio4 9 0>; 118 cs-gpios = <&gpio4 9 0>;
102 pinctrl-names = "default"; 119 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_ecspi1_2>; 120 pinctrl-0 = <&pinctrl_ecspi1>;
104 status = "okay"; 121 status = "okay";
105 122
106 flash: m25p80@0 { 123 flash: m25p80@0 {
@@ -114,7 +131,7 @@
114 131
115&fec { 132&fec {
116 pinctrl-names = "default"; 133 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_enet_1>; 134 pinctrl-0 = <&pinctrl_enet>;
118 phy-mode = "rgmii"; 135 phy-mode = "rgmii";
119 phy-reset-gpios = <&gpio1 25 0>; 136 phy-reset-gpios = <&gpio1 25 0>;
120 status = "okay"; 137 status = "okay";
@@ -123,7 +140,7 @@
123&i2c1 { 140&i2c1 {
124 clock-frequency = <100000>; 141 clock-frequency = <100000>;
125 pinctrl-names = "default"; 142 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_i2c1_2>; 143 pinctrl-0 = <&pinctrl_i2c1>;
127 status = "okay"; 144 status = "okay";
128 145
129 codec: wm8962@1a { 146 codec: wm8962@1a {
@@ -149,10 +166,116 @@
149 }; 166 };
150}; 167};
151 168
169&i2c2 {
170 clock-frequency = <100000>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_i2c2>;
173 status = "okay";
174
175 pmic: pfuze100@08 {
176 compatible = "fsl,pfuze100";
177 reg = <0x08>;
178
179 regulators {
180 sw1a_reg: sw1ab {
181 regulator-min-microvolt = <300000>;
182 regulator-max-microvolt = <1875000>;
183 regulator-boot-on;
184 regulator-always-on;
185 regulator-ramp-delay = <6250>;
186 };
187
188 sw1c_reg: sw1c {
189 regulator-min-microvolt = <300000>;
190 regulator-max-microvolt = <1875000>;
191 regulator-boot-on;
192 regulator-always-on;
193 regulator-ramp-delay = <6250>;
194 };
195
196 sw2_reg: sw2 {
197 regulator-min-microvolt = <800000>;
198 regulator-max-microvolt = <3300000>;
199 regulator-boot-on;
200 regulator-always-on;
201 };
202
203 sw3a_reg: sw3a {
204 regulator-min-microvolt = <400000>;
205 regulator-max-microvolt = <1975000>;
206 regulator-boot-on;
207 regulator-always-on;
208 };
209
210 sw3b_reg: sw3b {
211 regulator-min-microvolt = <400000>;
212 regulator-max-microvolt = <1975000>;
213 regulator-boot-on;
214 regulator-always-on;
215 };
216
217 sw4_reg: sw4 {
218 regulator-min-microvolt = <800000>;
219 regulator-max-microvolt = <3300000>;
220 };
221
222 swbst_reg: swbst {
223 regulator-min-microvolt = <5000000>;
224 regulator-max-microvolt = <5150000>;
225 };
226
227 snvs_reg: vsnvs {
228 regulator-min-microvolt = <1000000>;
229 regulator-max-microvolt = <3000000>;
230 regulator-boot-on;
231 regulator-always-on;
232 };
233
234 vref_reg: vrefddr {
235 regulator-boot-on;
236 regulator-always-on;
237 };
238
239 vgen1_reg: vgen1 {
240 regulator-min-microvolt = <800000>;
241 regulator-max-microvolt = <1550000>;
242 };
243
244 vgen2_reg: vgen2 {
245 regulator-min-microvolt = <800000>;
246 regulator-max-microvolt = <1550000>;
247 };
248
249 vgen3_reg: vgen3 {
250 regulator-min-microvolt = <1800000>;
251 regulator-max-microvolt = <3300000>;
252 };
253
254 vgen4_reg: vgen4 {
255 regulator-min-microvolt = <1800000>;
256 regulator-max-microvolt = <3300000>;
257 regulator-always-on;
258 };
259
260 vgen5_reg: vgen5 {
261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <3300000>;
263 regulator-always-on;
264 };
265
266 vgen6_reg: vgen6 {
267 regulator-min-microvolt = <1800000>;
268 regulator-max-microvolt = <3300000>;
269 regulator-always-on;
270 };
271 };
272 };
273};
274
152&i2c3 { 275&i2c3 {
153 clock-frequency = <100000>; 276 clock-frequency = <100000>;
154 pinctrl-names = "default"; 277 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c3_2>; 278 pinctrl-0 = <&pinctrl_i2c3>;
156 status = "okay"; 279 status = "okay";
157 280
158 egalax_ts@04 { 281 egalax_ts@04 {
@@ -168,11 +291,9 @@
168 pinctrl-names = "default"; 291 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_hog>; 292 pinctrl-0 = <&pinctrl_hog>;
170 293
171 hog { 294 imx6qdl-sabresd {
172 pinctrl_hog: hoggrp { 295 pinctrl_hog: hoggrp {
173 fsl,pins = < 296 fsl,pins = <
174 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
175 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
176 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 297 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
177 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 298 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
178 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 299 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
@@ -184,6 +305,122 @@
184 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 305 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
185 >; 306 >;
186 }; 307 };
308
309 pinctrl_audmux: audmuxgrp {
310 fsl,pins = <
311 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
312 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
313 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
314 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
315 >;
316 };
317
318 pinctrl_ecspi1: ecspi1grp {
319 fsl,pins = <
320 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
321 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
322 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
323 >;
324 };
325
326 pinctrl_enet: enetgrp {
327 fsl,pins = <
328 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
329 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
330 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
331 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
332 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
333 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
334 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
335 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
336 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
337 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
338 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
339 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
340 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
341 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
342 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
343 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
344 >;
345 };
346
347 pinctrl_gpio_keys: gpio_keysgrp {
348 fsl,pins = <
349 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
350 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
351 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
352 >;
353 };
354
355 pinctrl_i2c1: i2c1grp {
356 fsl,pins = <
357 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
358 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
359 >;
360 };
361
362 pinctrl_i2c2: i2c2grp {
363 fsl,pins = <
364 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
365 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
366 >;
367 };
368
369 pinctrl_i2c3: i2c3grp {
370 fsl,pins = <
371 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
372 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
373 >;
374 };
375
376 pinctrl_pwm1: pwm1grp {
377 fsl,pins = <
378 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
379 >;
380 };
381
382 pinctrl_uart1: uart1grp {
383 fsl,pins = <
384 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
385 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
386 >;
387 };
388
389 pinctrl_usbotg: usbotggrp {
390 fsl,pins = <
391 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
392 >;
393 };
394
395 pinctrl_usdhc2: usdhc2grp {
396 fsl,pins = <
397 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
398 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
399 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
400 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
401 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
402 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
403 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
404 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
405 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
406 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
407 >;
408 };
409
410 pinctrl_usdhc3: usdhc3grp {
411 fsl,pins = <
412 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
413 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
414 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
415 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
416 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
417 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
418 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
419 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
420 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
421 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
422 >;
423 };
187 }; 424 };
188}; 425};
189 426
@@ -214,7 +451,7 @@
214 451
215&pwm1 { 452&pwm1 {
216 pinctrl-names = "default"; 453 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_pwm0_1>; 454 pinctrl-0 = <&pinctrl_pwm1>;
218 status = "okay"; 455 status = "okay";
219}; 456};
220 457
@@ -225,7 +462,7 @@
225 462
226&uart1 { 463&uart1 {
227 pinctrl-names = "default"; 464 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_uart1_1>; 465 pinctrl-0 = <&pinctrl_uart1>;
229 status = "okay"; 466 status = "okay";
230}; 467};
231 468
@@ -237,14 +474,14 @@
237&usbotg { 474&usbotg {
238 vbus-supply = <&reg_usb_otg_vbus>; 475 vbus-supply = <&reg_usb_otg_vbus>;
239 pinctrl-names = "default"; 476 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_usbotg_2>; 477 pinctrl-0 = <&pinctrl_usbotg>;
241 disable-over-current; 478 disable-over-current;
242 status = "okay"; 479 status = "okay";
243}; 480};
244 481
245&usdhc2 { 482&usdhc2 {
246 pinctrl-names = "default"; 483 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_usdhc2_1>; 484 pinctrl-0 = <&pinctrl_usdhc2>;
248 bus-width = <8>; 485 bus-width = <8>;
249 cd-gpios = <&gpio2 2 0>; 486 cd-gpios = <&gpio2 2 0>;
250 wp-gpios = <&gpio2 3 0>; 487 wp-gpios = <&gpio2 3 0>;
@@ -253,7 +490,7 @@
253 490
254&usdhc3 { 491&usdhc3 {
255 pinctrl-names = "default"; 492 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_usdhc3_1>; 493 pinctrl-0 = <&pinctrl_usdhc3>;
257 bus-width = <8>; 494 bus-width = <8>;
258 cd-gpios = <&gpio2 0 0>; 495 cd-gpios = <&gpio2 0 0>;
259 wp-gpios = <&gpio2 1 0>; 496 wp-gpios = <&gpio2 1 0>;
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 35f547929167..bdfdf89d405f 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -12,17 +12,21 @@
12/ { 12/ {
13 regulators { 13 regulators {
14 compatible = "simple-bus"; 14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <0>;
15 17
16 reg_2p5v: 2p5v { 18 reg_2p5v: regulator@0 {
17 compatible = "regulator-fixed"; 19 compatible = "regulator-fixed";
20 reg = <0>;
18 regulator-name = "2P5V"; 21 regulator-name = "2P5V";
19 regulator-min-microvolt = <2500000>; 22 regulator-min-microvolt = <2500000>;
20 regulator-max-microvolt = <2500000>; 23 regulator-max-microvolt = <2500000>;
21 regulator-always-on; 24 regulator-always-on;
22 }; 25 };
23 26
24 reg_3p3v: 3p3v { 27 reg_3p3v: regulator@1 {
25 compatible = "regulator-fixed"; 28 compatible = "regulator-fixed";
29 reg = <1>;
26 regulator-name = "3P3V"; 30 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>; 31 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>;
@@ -54,14 +58,14 @@
54 58
55&audmux { 59&audmux {
56 pinctrl-names = "default"; 60 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_audmux_2>; 61 pinctrl-0 = <&pinctrl_audmux>;
58 status = "okay"; 62 status = "okay";
59}; 63};
60 64
61&i2c2 { 65&i2c2 {
62 clock-frequency = <100000>; 66 clock-frequency = <100000>;
63 pinctrl-names = "default"; 67 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_i2c2_2>; 68 pinctrl-0 = <&pinctrl_i2c2>;
65 status = "okay"; 69 status = "okay";
66 70
67 codec: sgtl5000@0a { 71 codec: sgtl5000@0a {
@@ -77,7 +81,7 @@
77 pinctrl-names = "default"; 81 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_hog>; 82 pinctrl-0 = <&pinctrl_hog>;
79 83
80 hog { 84 imx6qdl-wandboard {
81 pinctrl_hog: hoggrp { 85 pinctrl_hog: hoggrp {
82 fsl,pins = < 86 fsl,pins = <
83 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 87 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
@@ -91,20 +95,121 @@
91 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 95 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
92 >; 96 >;
93 }; 97 };
98
99 pinctrl_audmux: audmuxgrp {
100 fsl,pins = <
101 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
102 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
103 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
104 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
105 >;
106 };
107
108 pinctrl_enet: enetgrp {
109 fsl,pins = <
110 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
111 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
112 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
113 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
114 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
115 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
116 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
117 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
118 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
119 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
120 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
121 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
122 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
123 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
124 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
125 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
126 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
127 >;
128 };
129
130 pinctrl_i2c2: i2c2grp {
131 fsl,pins = <
132 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
133 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
134 >;
135 };
136
137 pinctrl_spdif: spdifgrp {
138 fsl,pins = <
139 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
140 >;
141 };
142
143 pinctrl_uart1: uart1grp {
144 fsl,pins = <
145 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
146 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
147 >;
148 };
149
150 pinctrl_uart3: uart3grp {
151 fsl,pins = <
152 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
153 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
154 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
155 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
156 >;
157 };
158
159 pinctrl_usbotg: usbotggrp {
160 fsl,pins = <
161 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
162 >;
163 };
164
165 pinctrl_usdhc1: usdhc1grp {
166 fsl,pins = <
167 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
168 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
169 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
170 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
171 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
172 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
173 >;
174 };
175
176 pinctrl_usdhc2: usdhc2grp {
177 fsl,pins = <
178 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
179 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
180 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
181 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
182 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
183 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
184 >;
185 };
186
187 pinctrl_usdhc3: usdhc3grp {
188 fsl,pins = <
189 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
190 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
191 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
192 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
193 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
194 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
195 >;
196 };
94 }; 197 };
95}; 198};
96 199
97&fec { 200&fec {
98 pinctrl-names = "default"; 201 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_enet_1>; 202 pinctrl-0 = <&pinctrl_enet>;
100 phy-mode = "rgmii"; 203 phy-mode = "rgmii";
101 phy-reset-gpios = <&gpio3 29 0>; 204 phy-reset-gpios = <&gpio3 29 0>;
205 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
206 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
102 status = "okay"; 207 status = "okay";
103}; 208};
104 209
105&spdif { 210&spdif {
106 pinctrl-names = "default"; 211 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_spdif_3>; 212 pinctrl-0 = <&pinctrl_spdif>;
108 status = "okay"; 213 status = "okay";
109}; 214};
110 215
@@ -115,13 +220,13 @@
115 220
116&uart1 { 221&uart1 {
117 pinctrl-names = "default"; 222 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_uart1_1>; 223 pinctrl-0 = <&pinctrl_uart1>;
119 status = "okay"; 224 status = "okay";
120}; 225};
121 226
122&uart3 { 227&uart3 {
123 pinctrl-names = "default"; 228 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_uart3_2>; 229 pinctrl-0 = <&pinctrl_uart3>;
125 fsl,uart-has-rtscts; 230 fsl,uart-has-rtscts;
126 status = "okay"; 231 status = "okay";
127}; 232};
@@ -132,7 +237,7 @@
132 237
133&usbotg { 238&usbotg {
134 pinctrl-names = "default"; 239 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_usbotg_1>; 240 pinctrl-0 = <&pinctrl_usbotg>;
136 disable-over-current; 241 disable-over-current;
137 dr_mode = "peripheral"; 242 dr_mode = "peripheral";
138 status = "okay"; 243 status = "okay";
@@ -140,21 +245,21 @@
140 245
141&usdhc1 { 246&usdhc1 {
142 pinctrl-names = "default"; 247 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_usdhc1_2>; 248 pinctrl-0 = <&pinctrl_usdhc1>;
144 cd-gpios = <&gpio1 2 0>; 249 cd-gpios = <&gpio1 2 0>;
145 status = "okay"; 250 status = "okay";
146}; 251};
147 252
148&usdhc2 { 253&usdhc2 {
149 pinctrl-names = "default"; 254 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_usdhc2_2>; 255 pinctrl-0 = <&pinctrl_usdhc2>;
151 non-removable; 256 non-removable;
152 status = "okay"; 257 status = "okay";
153}; 258};
154 259
155&usdhc3 { 260&usdhc3 {
156 pinctrl-names = "default"; 261 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_usdhc3_2>; 262 pinctrl-0 = <&pinctrl_usdhc3>;
158 cd-gpios = <&gpio3 9 0>; 263 cd-gpios = <&gpio3 9 0>;
159 status = "okay"; 264 status = "okay";
160}; 265};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index fb28b2ecb1db..55cb926fa3f7 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -14,6 +14,8 @@
14 14
15/ { 15/ {
16 aliases { 16 aliases {
17 can0 = &can1;
18 can1 = &can2;
17 gpio0 = &gpio1; 19 gpio0 = &gpio1;
18 gpio1 = &gpio2; 20 gpio1 = &gpio2;
19 gpio2 = &gpio3; 21 gpio2 = &gpio3;
@@ -24,6 +26,10 @@
24 i2c0 = &i2c1; 26 i2c0 = &i2c1;
25 i2c1 = &i2c2; 27 i2c1 = &i2c2;
26 i2c2 = &i2c3; 28 i2c2 = &i2c3;
29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 mmc2 = &usdhc3;
32 mmc3 = &usdhc4;
27 serial0 = &uart1; 33 serial0 = &uart1;
28 serial1 = &uart2; 34 serial1 = &uart2;
29 serial2 = &uart3; 35 serial2 = &uart3;
@@ -33,6 +39,8 @@
33 spi1 = &ecspi2; 39 spi1 = &ecspi2;
34 spi2 = &ecspi3; 40 spi2 = &ecspi3;
35 spi3 = &ecspi4; 41 spi3 = &ecspi4;
42 usbphy0 = &usbphy1;
43 usbphy1 = &usbphy2;
36 }; 44 };
37 45
38 intc: interrupt-controller@00a01000 { 46 intc: interrupt-controller@00a01000 {
@@ -75,7 +83,10 @@
75 dma_apbh: dma-apbh@00110000 { 83 dma_apbh: dma-apbh@00110000 {
76 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 84 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
77 reg = <0x00110000 0x2000>; 85 reg = <0x00110000 0x2000>;
78 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>; 86 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
87 <0 13 IRQ_TYPE_LEVEL_HIGH>,
88 <0 13 IRQ_TYPE_LEVEL_HIGH>,
89 <0 13 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 90 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
80 #dma-cells = <1>; 91 #dma-cells = <1>;
81 dma-channels = <4>; 92 dma-channels = <4>;
@@ -88,7 +99,7 @@
88 #size-cells = <1>; 99 #size-cells = <1>;
89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 100 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
90 reg-names = "gpmi-nand", "bch"; 101 reg-names = "gpmi-nand", "bch";
91 interrupts = <0 15 0x04>; 102 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
92 interrupt-names = "bch"; 103 interrupt-names = "bch";
93 clocks = <&clks 152>, <&clks 153>, <&clks 151>, 104 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
94 <&clks 150>, <&clks 149>; 105 <&clks 150>, <&clks 149>;
@@ -109,7 +120,7 @@
109 L2: l2-cache@00a02000 { 120 L2: l2-cache@00a02000 {
110 compatible = "arm,pl310-cache"; 121 compatible = "arm,pl310-cache";
111 reg = <0x00a02000 0x1000>; 122 reg = <0x00a02000 0x1000>;
112 interrupts = <0 92 0x04>; 123 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
113 cache-unified; 124 cache-unified;
114 cache-level = <2>; 125 cache-level = <2>;
115 arm,tag-latency = <4 2 3>; 126 arm,tag-latency = <4 2 3>;
@@ -126,7 +137,7 @@
126 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 137 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
127 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 138 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
128 num-lanes = <1>; 139 num-lanes = <1>;
129 interrupts = <0 123 0x04>; 140 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; 141 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
131 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; 142 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
132 status = "disabled"; 143 status = "disabled";
@@ -134,7 +145,7 @@
134 145
135 pmu { 146 pmu {
136 compatible = "arm,cortex-a9-pmu"; 147 compatible = "arm,cortex-a9-pmu";
137 interrupts = <0 94 0x04>; 148 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
138 }; 149 };
139 150
140 aips-bus@02000000 { /* AIPS1 */ 151 aips-bus@02000000 { /* AIPS1 */
@@ -154,7 +165,7 @@
154 spdif: spdif@02004000 { 165 spdif: spdif@02004000 {
155 compatible = "fsl,imx35-spdif"; 166 compatible = "fsl,imx35-spdif";
156 reg = <0x02004000 0x4000>; 167 reg = <0x02004000 0x4000>;
157 interrupts = <0 52 0x04>; 168 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
158 dmas = <&sdma 14 18 0>, 169 dmas = <&sdma 14 18 0>,
159 <&sdma 15 18 0>; 170 <&sdma 15 18 0>;
160 dma-names = "rx", "tx"; 171 dma-names = "rx", "tx";
@@ -176,9 +187,11 @@
176 #size-cells = <0>; 187 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02008000 0x4000>; 189 reg = <0x02008000 0x4000>;
179 interrupts = <0 31 0x04>; 190 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&clks 112>, <&clks 112>; 191 clocks = <&clks 112>, <&clks 112>;
181 clock-names = "ipg", "per"; 192 clock-names = "ipg", "per";
193 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
194 dma-names = "rx", "tx";
182 status = "disabled"; 195 status = "disabled";
183 }; 196 };
184 197
@@ -187,9 +200,11 @@
187 #size-cells = <0>; 200 #size-cells = <0>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 201 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
189 reg = <0x0200c000 0x4000>; 202 reg = <0x0200c000 0x4000>;
190 interrupts = <0 32 0x04>; 203 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&clks 113>, <&clks 113>; 204 clocks = <&clks 113>, <&clks 113>;
192 clock-names = "ipg", "per"; 205 clock-names = "ipg", "per";
206 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
207 dma-names = "rx", "tx";
193 status = "disabled"; 208 status = "disabled";
194 }; 209 };
195 210
@@ -198,9 +213,11 @@
198 #size-cells = <0>; 213 #size-cells = <0>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 214 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02010000 0x4000>; 215 reg = <0x02010000 0x4000>;
201 interrupts = <0 33 0x04>; 216 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clks 114>, <&clks 114>; 217 clocks = <&clks 114>, <&clks 114>;
203 clock-names = "ipg", "per"; 218 clock-names = "ipg", "per";
219 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
220 dma-names = "rx", "tx";
204 status = "disabled"; 221 status = "disabled";
205 }; 222 };
206 223
@@ -209,16 +226,18 @@
209 #size-cells = <0>; 226 #size-cells = <0>;
210 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 227 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
211 reg = <0x02014000 0x4000>; 228 reg = <0x02014000 0x4000>;
212 interrupts = <0 34 0x04>; 229 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&clks 115>, <&clks 115>; 230 clocks = <&clks 115>, <&clks 115>;
214 clock-names = "ipg", "per"; 231 clock-names = "ipg", "per";
232 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
233 dma-names = "rx", "tx";
215 status = "disabled"; 234 status = "disabled";
216 }; 235 };
217 236
218 uart1: serial@02020000 { 237 uart1: serial@02020000 {
219 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 238 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
220 reg = <0x02020000 0x4000>; 239 reg = <0x02020000 0x4000>;
221 interrupts = <0 26 0x04>; 240 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&clks 160>, <&clks 161>; 241 clocks = <&clks 160>, <&clks 161>;
223 clock-names = "ipg", "per"; 242 clock-names = "ipg", "per";
224 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 243 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
@@ -228,13 +247,15 @@
228 247
229 esai: esai@02024000 { 248 esai: esai@02024000 {
230 reg = <0x02024000 0x4000>; 249 reg = <0x02024000 0x4000>;
231 interrupts = <0 51 0x04>; 250 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
232 }; 251 };
233 252
234 ssi1: ssi@02028000 { 253 ssi1: ssi@02028000 {
235 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 254 compatible = "fsl,imx6q-ssi",
255 "fsl,imx51-ssi",
256 "fsl,imx21-ssi";
236 reg = <0x02028000 0x4000>; 257 reg = <0x02028000 0x4000>;
237 interrupts = <0 46 0x04>; 258 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks 178>; 259 clocks = <&clks 178>;
239 dmas = <&sdma 37 1 0>, 260 dmas = <&sdma 37 1 0>,
240 <&sdma 38 1 0>; 261 <&sdma 38 1 0>;
@@ -245,9 +266,11 @@
245 }; 266 };
246 267
247 ssi2: ssi@0202c000 { 268 ssi2: ssi@0202c000 {
248 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 269 compatible = "fsl,imx6q-ssi",
270 "fsl,imx51-ssi",
271 "fsl,imx21-ssi";
249 reg = <0x0202c000 0x4000>; 272 reg = <0x0202c000 0x4000>;
250 interrupts = <0 47 0x04>; 273 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clks 179>; 274 clocks = <&clks 179>;
252 dmas = <&sdma 41 1 0>, 275 dmas = <&sdma 41 1 0>,
253 <&sdma 42 1 0>; 276 <&sdma 42 1 0>;
@@ -258,9 +281,11 @@
258 }; 281 };
259 282
260 ssi3: ssi@02030000 { 283 ssi3: ssi@02030000 {
261 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 284 compatible = "fsl,imx6q-ssi",
285 "fsl,imx51-ssi",
286 "fsl,imx21-ssi";
262 reg = <0x02030000 0x4000>; 287 reg = <0x02030000 0x4000>;
263 interrupts = <0 48 0x04>; 288 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clks 180>; 289 clocks = <&clks 180>;
265 dmas = <&sdma 45 1 0>, 290 dmas = <&sdma 45 1 0>,
266 <&sdma 46 1 0>; 291 <&sdma 46 1 0>;
@@ -272,7 +297,7 @@
272 297
273 asrc: asrc@02034000 { 298 asrc: asrc@02034000 {
274 reg = <0x02034000 0x4000>; 299 reg = <0x02034000 0x4000>;
275 interrupts = <0 50 0x04>; 300 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
276 }; 301 };
277 302
278 spba@0203c000 { 303 spba@0203c000 {
@@ -282,7 +307,8 @@
282 307
283 vpu: vpu@02040000 { 308 vpu: vpu@02040000 {
284 reg = <0x02040000 0x3c000>; 309 reg = <0x02040000 0x3c000>;
285 interrupts = <0 3 0x04 0 12 0x04>; 310 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
311 <0 12 IRQ_TYPE_LEVEL_HIGH>;
286 }; 312 };
287 313
288 aipstz@0207c000 { /* AIPSTZ1 */ 314 aipstz@0207c000 { /* AIPSTZ1 */
@@ -293,7 +319,7 @@
293 #pwm-cells = <2>; 319 #pwm-cells = <2>;
294 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 320 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
295 reg = <0x02080000 0x4000>; 321 reg = <0x02080000 0x4000>;
296 interrupts = <0 83 0x04>; 322 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&clks 62>, <&clks 145>; 323 clocks = <&clks 62>, <&clks 145>;
298 clock-names = "ipg", "per"; 324 clock-names = "ipg", "per";
299 }; 325 };
@@ -302,7 +328,7 @@
302 #pwm-cells = <2>; 328 #pwm-cells = <2>;
303 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 329 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
304 reg = <0x02084000 0x4000>; 330 reg = <0x02084000 0x4000>;
305 interrupts = <0 84 0x04>; 331 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clks 62>, <&clks 146>; 332 clocks = <&clks 62>, <&clks 146>;
307 clock-names = "ipg", "per"; 333 clock-names = "ipg", "per";
308 }; 334 };
@@ -311,7 +337,7 @@
311 #pwm-cells = <2>; 337 #pwm-cells = <2>;
312 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 338 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
313 reg = <0x02088000 0x4000>; 339 reg = <0x02088000 0x4000>;
314 interrupts = <0 85 0x04>; 340 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks 62>, <&clks 147>; 341 clocks = <&clks 62>, <&clks 147>;
316 clock-names = "ipg", "per"; 342 clock-names = "ipg", "per";
317 }; 343 };
@@ -320,7 +346,7 @@
320 #pwm-cells = <2>; 346 #pwm-cells = <2>;
321 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 347 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
322 reg = <0x0208c000 0x4000>; 348 reg = <0x0208c000 0x4000>;
323 interrupts = <0 86 0x04>; 349 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clks 62>, <&clks 148>; 350 clocks = <&clks 62>, <&clks 148>;
325 clock-names = "ipg", "per"; 351 clock-names = "ipg", "per";
326 }; 352 };
@@ -328,23 +354,25 @@
328 can1: flexcan@02090000 { 354 can1: flexcan@02090000 {
329 compatible = "fsl,imx6q-flexcan"; 355 compatible = "fsl,imx6q-flexcan";
330 reg = <0x02090000 0x4000>; 356 reg = <0x02090000 0x4000>;
331 interrupts = <0 110 0x04>; 357 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clks 108>, <&clks 109>; 358 clocks = <&clks 108>, <&clks 109>;
333 clock-names = "ipg", "per"; 359 clock-names = "ipg", "per";
360 status = "disabled";
334 }; 361 };
335 362
336 can2: flexcan@02094000 { 363 can2: flexcan@02094000 {
337 compatible = "fsl,imx6q-flexcan"; 364 compatible = "fsl,imx6q-flexcan";
338 reg = <0x02094000 0x4000>; 365 reg = <0x02094000 0x4000>;
339 interrupts = <0 111 0x04>; 366 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&clks 110>, <&clks 111>; 367 clocks = <&clks 110>, <&clks 111>;
341 clock-names = "ipg", "per"; 368 clock-names = "ipg", "per";
369 status = "disabled";
342 }; 370 };
343 371
344 gpt: gpt@02098000 { 372 gpt: gpt@02098000 {
345 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; 373 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
346 reg = <0x02098000 0x4000>; 374 reg = <0x02098000 0x4000>;
347 interrupts = <0 55 0x04>; 375 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&clks 119>, <&clks 120>; 376 clocks = <&clks 119>, <&clks 120>;
349 clock-names = "ipg", "per"; 377 clock-names = "ipg", "per";
350 }; 378 };
@@ -352,7 +380,8 @@
352 gpio1: gpio@0209c000 { 380 gpio1: gpio@0209c000 {
353 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 381 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
354 reg = <0x0209c000 0x4000>; 382 reg = <0x0209c000 0x4000>;
355 interrupts = <0 66 0x04 0 67 0x04>; 383 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
384 <0 67 IRQ_TYPE_LEVEL_HIGH>;
356 gpio-controller; 385 gpio-controller;
357 #gpio-cells = <2>; 386 #gpio-cells = <2>;
358 interrupt-controller; 387 interrupt-controller;
@@ -362,7 +391,8 @@
362 gpio2: gpio@020a0000 { 391 gpio2: gpio@020a0000 {
363 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 392 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
364 reg = <0x020a0000 0x4000>; 393 reg = <0x020a0000 0x4000>;
365 interrupts = <0 68 0x04 0 69 0x04>; 394 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
395 <0 69 IRQ_TYPE_LEVEL_HIGH>;
366 gpio-controller; 396 gpio-controller;
367 #gpio-cells = <2>; 397 #gpio-cells = <2>;
368 interrupt-controller; 398 interrupt-controller;
@@ -372,7 +402,8 @@
372 gpio3: gpio@020a4000 { 402 gpio3: gpio@020a4000 {
373 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 403 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
374 reg = <0x020a4000 0x4000>; 404 reg = <0x020a4000 0x4000>;
375 interrupts = <0 70 0x04 0 71 0x04>; 405 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
406 <0 71 IRQ_TYPE_LEVEL_HIGH>;
376 gpio-controller; 407 gpio-controller;
377 #gpio-cells = <2>; 408 #gpio-cells = <2>;
378 interrupt-controller; 409 interrupt-controller;
@@ -382,7 +413,8 @@
382 gpio4: gpio@020a8000 { 413 gpio4: gpio@020a8000 {
383 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 414 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
384 reg = <0x020a8000 0x4000>; 415 reg = <0x020a8000 0x4000>;
385 interrupts = <0 72 0x04 0 73 0x04>; 416 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
417 <0 73 IRQ_TYPE_LEVEL_HIGH>;
386 gpio-controller; 418 gpio-controller;
387 #gpio-cells = <2>; 419 #gpio-cells = <2>;
388 interrupt-controller; 420 interrupt-controller;
@@ -392,7 +424,8 @@
392 gpio5: gpio@020ac000 { 424 gpio5: gpio@020ac000 {
393 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 425 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
394 reg = <0x020ac000 0x4000>; 426 reg = <0x020ac000 0x4000>;
395 interrupts = <0 74 0x04 0 75 0x04>; 427 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
428 <0 75 IRQ_TYPE_LEVEL_HIGH>;
396 gpio-controller; 429 gpio-controller;
397 #gpio-cells = <2>; 430 #gpio-cells = <2>;
398 interrupt-controller; 431 interrupt-controller;
@@ -402,7 +435,8 @@
402 gpio6: gpio@020b0000 { 435 gpio6: gpio@020b0000 {
403 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 436 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
404 reg = <0x020b0000 0x4000>; 437 reg = <0x020b0000 0x4000>;
405 interrupts = <0 76 0x04 0 77 0x04>; 438 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
439 <0 77 IRQ_TYPE_LEVEL_HIGH>;
406 gpio-controller; 440 gpio-controller;
407 #gpio-cells = <2>; 441 #gpio-cells = <2>;
408 interrupt-controller; 442 interrupt-controller;
@@ -412,7 +446,8 @@
412 gpio7: gpio@020b4000 { 446 gpio7: gpio@020b4000 {
413 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 447 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
414 reg = <0x020b4000 0x4000>; 448 reg = <0x020b4000 0x4000>;
415 interrupts = <0 78 0x04 0 79 0x04>; 449 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
450 <0 79 IRQ_TYPE_LEVEL_HIGH>;
416 gpio-controller; 451 gpio-controller;
417 #gpio-cells = <2>; 452 #gpio-cells = <2>;
418 interrupt-controller; 453 interrupt-controller;
@@ -421,20 +456,20 @@
421 456
422 kpp: kpp@020b8000 { 457 kpp: kpp@020b8000 {
423 reg = <0x020b8000 0x4000>; 458 reg = <0x020b8000 0x4000>;
424 interrupts = <0 82 0x04>; 459 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
425 }; 460 };
426 461
427 wdog1: wdog@020bc000 { 462 wdog1: wdog@020bc000 {
428 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 463 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
429 reg = <0x020bc000 0x4000>; 464 reg = <0x020bc000 0x4000>;
430 interrupts = <0 80 0x04>; 465 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clks 0>; 466 clocks = <&clks 0>;
432 }; 467 };
433 468
434 wdog2: wdog@020c0000 { 469 wdog2: wdog@020c0000 {
435 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 470 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
436 reg = <0x020c0000 0x4000>; 471 reg = <0x020c0000 0x4000>;
437 interrupts = <0 81 0x04>; 472 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clks 0>; 473 clocks = <&clks 0>;
439 status = "disabled"; 474 status = "disabled";
440 }; 475 };
@@ -442,14 +477,17 @@
442 clks: ccm@020c4000 { 477 clks: ccm@020c4000 {
443 compatible = "fsl,imx6q-ccm"; 478 compatible = "fsl,imx6q-ccm";
444 reg = <0x020c4000 0x4000>; 479 reg = <0x020c4000 0x4000>;
445 interrupts = <0 87 0x04 0 88 0x04>; 480 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
481 <0 88 IRQ_TYPE_LEVEL_HIGH>;
446 #clock-cells = <1>; 482 #clock-cells = <1>;
447 }; 483 };
448 484
449 anatop: anatop@020c8000 { 485 anatop: anatop@020c8000 {
450 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; 486 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
451 reg = <0x020c8000 0x1000>; 487 reg = <0x020c8000 0x1000>;
452 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; 488 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
489 <0 54 IRQ_TYPE_LEVEL_HIGH>,
490 <0 127 IRQ_TYPE_LEVEL_HIGH>;
453 491
454 regulator-1p1@110 { 492 regulator-1p1@110 {
455 compatible = "fsl,anatop-regulator"; 493 compatible = "fsl,anatop-regulator";
@@ -495,7 +533,7 @@
495 533
496 reg_arm: regulator-vddcore@140 { 534 reg_arm: regulator-vddcore@140 {
497 compatible = "fsl,anatop-regulator"; 535 compatible = "fsl,anatop-regulator";
498 regulator-name = "cpu"; 536 regulator-name = "vddarm";
499 regulator-min-microvolt = <725000>; 537 regulator-min-microvolt = <725000>;
500 regulator-max-microvolt = <1450000>; 538 regulator-max-microvolt = <1450000>;
501 regulator-always-on; 539 regulator-always-on;
@@ -547,23 +585,26 @@
547 585
548 tempmon: tempmon { 586 tempmon: tempmon {
549 compatible = "fsl,imx6q-tempmon"; 587 compatible = "fsl,imx6q-tempmon";
550 interrupts = <0 49 0x04>; 588 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
551 fsl,tempmon = <&anatop>; 589 fsl,tempmon = <&anatop>;
552 fsl,tempmon-data = <&ocotp>; 590 fsl,tempmon-data = <&ocotp>;
591 clocks = <&clks 172>;
553 }; 592 };
554 593
555 usbphy1: usbphy@020c9000 { 594 usbphy1: usbphy@020c9000 {
556 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 595 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
557 reg = <0x020c9000 0x1000>; 596 reg = <0x020c9000 0x1000>;
558 interrupts = <0 44 0x04>; 597 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clks 182>; 598 clocks = <&clks 182>;
599 fsl,anatop = <&anatop>;
560 }; 600 };
561 601
562 usbphy2: usbphy@020ca000 { 602 usbphy2: usbphy@020ca000 {
563 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 603 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
564 reg = <0x020ca000 0x1000>; 604 reg = <0x020ca000 0x1000>;
565 interrupts = <0 45 0x04>; 605 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&clks 183>; 606 clocks = <&clks 183>;
607 fsl,anatop = <&anatop>;
567 }; 608 };
568 609
569 snvs@020cc000 { 610 snvs@020cc000 {
@@ -575,31 +616,34 @@
575 snvs-rtc-lp@34 { 616 snvs-rtc-lp@34 {
576 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 617 compatible = "fsl,sec-v4.0-mon-rtc-lp";
577 reg = <0x34 0x58>; 618 reg = <0x34 0x58>;
578 interrupts = <0 19 0x04 0 20 0x04>; 619 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
620 <0 20 IRQ_TYPE_LEVEL_HIGH>;
579 }; 621 };
580 }; 622 };
581 623
582 epit1: epit@020d0000 { /* EPIT1 */ 624 epit1: epit@020d0000 { /* EPIT1 */
583 reg = <0x020d0000 0x4000>; 625 reg = <0x020d0000 0x4000>;
584 interrupts = <0 56 0x04>; 626 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
585 }; 627 };
586 628
587 epit2: epit@020d4000 { /* EPIT2 */ 629 epit2: epit@020d4000 { /* EPIT2 */
588 reg = <0x020d4000 0x4000>; 630 reg = <0x020d4000 0x4000>;
589 interrupts = <0 57 0x04>; 631 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
590 }; 632 };
591 633
592 src: src@020d8000 { 634 src: src@020d8000 {
593 compatible = "fsl,imx6q-src", "fsl,imx51-src"; 635 compatible = "fsl,imx6q-src", "fsl,imx51-src";
594 reg = <0x020d8000 0x4000>; 636 reg = <0x020d8000 0x4000>;
595 interrupts = <0 91 0x04 0 96 0x04>; 637 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
638 <0 96 IRQ_TYPE_LEVEL_HIGH>;
596 #reset-cells = <1>; 639 #reset-cells = <1>;
597 }; 640 };
598 641
599 gpc: gpc@020dc000 { 642 gpc: gpc@020dc000 {
600 compatible = "fsl,imx6q-gpc"; 643 compatible = "fsl,imx6q-gpc";
601 reg = <0x020dc000 0x4000>; 644 reg = <0x020dc000 0x4000>;
602 interrupts = <0 89 0x04 0 90 0x04>; 645 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
646 <0 90 IRQ_TYPE_LEVEL_HIGH>;
603 }; 647 };
604 648
605 gpr: iomuxc-gpr@020e0000 { 649 gpr: iomuxc-gpr@020e0000 {
@@ -610,778 +654,103 @@
610 iomuxc: iomuxc@020e0000 { 654 iomuxc: iomuxc@020e0000 {
611 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 655 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
612 reg = <0x020e0000 0x4000>; 656 reg = <0x020e0000 0x4000>;
657 };
613 658
614 audmux { 659 ldb: ldb@020e0008 {
615 pinctrl_audmux_1: audmux-1 { 660 #address-cells = <1>;
616 fsl,pins = < 661 #size-cells = <0>;
617 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000 662 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
618 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000 663 gpr = <&gpr>;
619 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000 664 status = "disabled";
620 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
621 >;
622 };
623
624 pinctrl_audmux_2: audmux-2 {
625 fsl,pins = <
626 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
627 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
628 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
629 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
630 >;
631 };
632
633 pinctrl_audmux_3: audmux-3 {
634 fsl,pins = <
635 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
636 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
637 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
638 >;
639 };
640 };
641
642 ecspi1 {
643 pinctrl_ecspi1_1: ecspi1grp-1 {
644 fsl,pins = <
645 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
646 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
647 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
648 >;
649 };
650
651 pinctrl_ecspi1_2: ecspi1grp-2 {
652 fsl,pins = <
653 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
654 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
655 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
656 >;
657 };
658 };
659
660 ecspi3 {
661 pinctrl_ecspi3_1: ecspi3grp-1 {
662 fsl,pins = <
663 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
664 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
665 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
666 >;
667 };
668 };
669
670 enet {
671 pinctrl_enet_1: enetgrp-1 {
672 fsl,pins = <
673 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
674 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
675 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
676 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
677 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
678 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
679 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
680 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
681 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
682 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
683 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
684 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
685 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
686 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
687 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
688 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
689 >;
690 };
691
692 pinctrl_enet_2: enetgrp-2 {
693 fsl,pins = <
694 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
695 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
696 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
697 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
698 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
699 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
700 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
701 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
702 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
703 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
704 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
705 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
706 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
707 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
708 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
709 >;
710 };
711
712 pinctrl_enet_3: enetgrp-3 {
713 fsl,pins = <
714 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
715 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
716 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
717 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
718 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
719 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
720 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
721 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
722 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
723 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
724 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
725 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
726 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
727 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
728 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
729 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
730 >;
731 };
732 };
733
734 esai {
735 pinctrl_esai_1: esaigrp-1 {
736 fsl,pins = <
737 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
738 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
739 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
740 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
741 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
742 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
743 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
744 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
745 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
746 >;
747 };
748
749 pinctrl_esai_2: esaigrp-2 {
750 fsl,pins = <
751 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
752 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
753 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
754 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
755 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
756 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
757 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
758 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
759 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
760 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
761 >;
762 };
763 };
764
765 flexcan1 {
766 pinctrl_flexcan1_1: flexcan1grp-1 {
767 fsl,pins = <
768 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
769 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
770 >;
771 };
772
773 pinctrl_flexcan1_2: flexcan1grp-2 {
774 fsl,pins = <
775 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
776 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
777 >;
778 };
779 };
780
781 flexcan2 {
782 pinctrl_flexcan2_1: flexcan2grp-1 {
783 fsl,pins = <
784 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
785 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
786 >;
787 };
788 };
789
790 gpmi-nand {
791 pinctrl_gpmi_nand_1: gpmi-nand-1 {
792 fsl,pins = <
793 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
794 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
795 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
796 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
797 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
798 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
799 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
800 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
801 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
802 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
803 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
804 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
805 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
806 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
807 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
808 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
809 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
810 >;
811 };
812 };
813
814 hdmi_hdcp {
815 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
816 fsl,pins = <
817 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
818 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
819 >;
820 };
821
822 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
823 fsl,pins = <
824 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
825 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
826 >;
827 };
828
829 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
830 fsl,pins = <
831 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
832 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
833 >;
834 };
835 };
836
837 hdmi_cec {
838 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
839 fsl,pins = <
840 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
841 >;
842 };
843
844 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
845 fsl,pins = <
846 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
847 >;
848 };
849 };
850
851 i2c1 {
852 pinctrl_i2c1_1: i2c1grp-1 {
853 fsl,pins = <
854 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
855 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
856 >;
857 };
858
859 pinctrl_i2c1_2: i2c1grp-2 {
860 fsl,pins = <
861 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
862 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
863 >;
864 };
865 };
866
867 i2c2 {
868 pinctrl_i2c2_1: i2c2grp-1 {
869 fsl,pins = <
870 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
871 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
872 >;
873 };
874
875 pinctrl_i2c2_2: i2c2grp-2 {
876 fsl,pins = <
877 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
878 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
879 >;
880 };
881
882 pinctrl_i2c2_3: i2c2grp-3 {
883 fsl,pins = <
884 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
885 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
886 >;
887 };
888 };
889
890 i2c3 {
891 pinctrl_i2c3_1: i2c3grp-1 {
892 fsl,pins = <
893 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
894 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
895 >;
896 };
897
898 pinctrl_i2c3_2: i2c3grp-2 {
899 fsl,pins = <
900 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
901 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
902 >;
903 };
904
905 pinctrl_i2c3_3: i2c3grp-3 {
906 fsl,pins = <
907 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
908 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
909 >;
910 };
911
912 pinctrl_i2c3_4: i2c3grp-4 {
913 fsl,pins = <
914 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
915 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
916 >;
917 };
918 };
919
920 ipu1 {
921 pinctrl_ipu1_1: ipu1grp-1 {
922 fsl,pins = <
923 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
924 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
925 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
926 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
927 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
928 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
929 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
930 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
931 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
932 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
933 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
934 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
935 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
936 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
937 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
938 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
939 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
940 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
941 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
942 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
943 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
944 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
945 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
946 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
947 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
948 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
949 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
950 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
951 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
952 >;
953 };
954
955 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
956 fsl,pins = <
957 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
958 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
959 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
960 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
961 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
962 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
963 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
964 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
965 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
966 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
967 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
968 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
969 >;
970 };
971
972 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
973 fsl,pins = <
974 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
975 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
976 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
977 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
978 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
979 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
980 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
981 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
982 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
983 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
984 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
985 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
986 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
987 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
988 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
989 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
990 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
991 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
992 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
993 >;
994 };
995 };
996
997 mlb {
998 pinctrl_mlb_1: mlbgrp-1 {
999 fsl,pins = <
1000 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
1001 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
1002 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
1003 >;
1004 };
1005
1006 pinctrl_mlb_2: mlbgrp-2 {
1007 fsl,pins = <
1008 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
1009 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
1010 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
1011 >;
1012 };
1013 };
1014
1015 pwm0 {
1016 pinctrl_pwm0_1: pwm0grp-1 {
1017 fsl,pins = <
1018 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
1019 >;
1020 };
1021 };
1022
1023 pwm3 {
1024 pinctrl_pwm3_1: pwm3grp-1 {
1025 fsl,pins = <
1026 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1027 >;
1028 };
1029 };
1030
1031 spdif {
1032 pinctrl_spdif_1: spdifgrp-1 {
1033 fsl,pins = <
1034 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1035 >;
1036 };
1037
1038 pinctrl_spdif_2: spdifgrp-2 {
1039 fsl,pins = <
1040 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1041 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1042 >;
1043 };
1044
1045 pinctrl_spdif_3: spdifgrp-3 {
1046 fsl,pins = <
1047 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
1048 >;
1049 };
1050 };
1051
1052 uart1 {
1053 pinctrl_uart1_1: uart1grp-1 {
1054 fsl,pins = <
1055 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1056 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1057 >;
1058 };
1059 };
1060
1061 uart2 {
1062 pinctrl_uart2_1: uart2grp-1 {
1063 fsl,pins = <
1064 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1065 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1066 >;
1067 };
1068
1069 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1070 fsl,pins = <
1071 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1072 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1073 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1074 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1075 >;
1076 };
1077 };
1078
1079 uart3 {
1080 pinctrl_uart3_1: uart3grp-1 {
1081 fsl,pins = <
1082 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1083 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1084 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1085 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1086 >;
1087 };
1088
1089 pinctrl_uart3_2: uart3grp-2 {
1090 fsl,pins = <
1091 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1092 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1093 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1094 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1095 >;
1096 };
1097 };
1098
1099 uart4 {
1100 pinctrl_uart4_1: uart4grp-1 {
1101 fsl,pins = <
1102 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1103 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1104 >;
1105 };
1106 };
1107
1108 usbotg {
1109 pinctrl_usbotg_1: usbotggrp-1 {
1110 fsl,pins = <
1111 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1112 >;
1113 };
1114
1115 pinctrl_usbotg_2: usbotggrp-2 {
1116 fsl,pins = <
1117 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1118 >;
1119 };
1120 };
1121
1122 usbh2 {
1123 pinctrl_usbh2_1: usbh2grp-1 {
1124 fsl,pins = <
1125 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1126 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1127 >;
1128 };
1129
1130 pinctrl_usbh2_2: usbh2grp-2 {
1131 fsl,pins = <
1132 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1133 >;
1134 };
1135 };
1136
1137 usbh3 {
1138 pinctrl_usbh3_1: usbh3grp-1 {
1139 fsl,pins = <
1140 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1141 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1142 >;
1143 };
1144 665
1145 pinctrl_usbh3_2: usbh3grp-2 { 666 lvds-channel@0 {
1146 fsl,pins = < 667 #address-cells = <1>;
1147 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 668 #size-cells = <0>;
1148 >; 669 reg = <0>;
1149 }; 670 status = "disabled";
1150 };
1151 671
1152 usdhc1 { 672 port@0 {
1153 pinctrl_usdhc1_1: usdhc1grp-1 { 673 reg = <0>;
1154 fsl,pins = <
1155 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1156 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1157 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1158 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1159 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1160 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1161 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1162 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1163 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1164 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1165 >;
1166 };
1167 674
1168 pinctrl_usdhc1_2: usdhc1grp-2 { 675 lvds0_mux_0: endpoint {
1169 fsl,pins = < 676 remote-endpoint = <&ipu1_di0_lvds0>;
1170 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 677 };
1171 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1172 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1173 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1174 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1175 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1176 >;
1177 }; 678 };
1178 };
1179 679
1180 usdhc2 { 680 port@1 {
1181 pinctrl_usdhc2_1: usdhc2grp-1 { 681 reg = <1>;
1182 fsl,pins = <
1183 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1184 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1185 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1186 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1187 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1188 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1189 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1190 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1191 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1192 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1193 >;
1194 };
1195 682
1196 pinctrl_usdhc2_2: usdhc2grp-2 { 683 lvds0_mux_1: endpoint {
1197 fsl,pins = < 684 remote-endpoint = <&ipu1_di1_lvds0>;
1198 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 685 };
1199 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1200 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1201 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1202 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1203 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1204 >;
1205 }; 686 };
1206 }; 687 };
1207 688
1208 usdhc3 { 689 lvds-channel@1 {
1209 pinctrl_usdhc3_1: usdhc3grp-1 { 690 #address-cells = <1>;
1210 fsl,pins = < 691 #size-cells = <0>;
1211 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 692 reg = <1>;
1212 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 693 status = "disabled";
1213 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1214 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1215 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1216 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1217 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1218 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1219 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1220 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1221 >;
1222 };
1223
1224 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
1225 fsl,pins = <
1226 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
1227 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
1228 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
1229 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
1230 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
1231 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
1232 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
1233 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
1234 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
1235 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
1236 >;
1237 };
1238 694
1239 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ 695 port@0 {
1240 fsl,pins = < 696 reg = <0>;
1241 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
1242 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
1243 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
1244 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
1245 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
1246 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
1247 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
1248 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
1249 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
1250 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
1251 >;
1252 };
1253 697
1254 pinctrl_usdhc3_2: usdhc3grp-2 { 698 lvds1_mux_0: endpoint {
1255 fsl,pins = < 699 remote-endpoint = <&ipu1_di0_lvds1>;
1256 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 700 };
1257 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1258 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1259 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1260 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1261 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1262 >;
1263 }; 701 };
1264 };
1265 702
1266 usdhc4 { 703 port@1 {
1267 pinctrl_usdhc4_1: usdhc4grp-1 { 704 reg = <1>;
1268 fsl,pins = <
1269 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1270 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1271 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1272 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1273 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1274 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1275 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1276 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1277 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1278 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1279 >;
1280 };
1281 705
1282 pinctrl_usdhc4_2: usdhc4grp-2 { 706 lvds1_mux_1: endpoint {
1283 fsl,pins = < 707 remote-endpoint = <&ipu1_di1_lvds1>;
1284 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 708 };
1285 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1286 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1287 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1288 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1289 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1290 >;
1291 };
1292 };
1293
1294 weim {
1295 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1296 fsl,pins = <
1297 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1298 >;
1299 };
1300
1301 pinctrl_weim_nor_1: weim_norgrp-1 {
1302 fsl,pins = <
1303 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1304 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1305 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1306 /* data */
1307 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1308 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1309 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1310 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1311 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1312 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1313 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1314 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1315 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1316 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1317 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1318 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1319 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1320 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1321 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1322 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1323 /* address */
1324 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1325 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1326 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1327 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1328 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1329 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1330 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1331 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1332 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1333 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1334 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1335 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1336 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1337 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1338 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1339 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1340 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1341 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1342 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1343 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1344 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1345 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1346 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1347 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1348 >;
1349 }; 709 };
1350 }; 710 };
1351 }; 711 };
1352 712
1353 ldb: ldb@020e0008 { 713 hdmi: hdmi@0120000 {
1354 #address-cells = <1>; 714 #address-cells = <1>;
1355 #size-cells = <0>; 715 #size-cells = <0>;
1356 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; 716 reg = <0x00120000 0x9000>;
717 interrupts = <0 115 0x04>;
1357 gpr = <&gpr>; 718 gpr = <&gpr>;
719 clocks = <&clks 123>, <&clks 124>;
720 clock-names = "iahb", "isfr";
1358 status = "disabled"; 721 status = "disabled";
1359 722
1360 lvds-channel@0 { 723 port@0 {
1361 reg = <0>; 724 reg = <0>;
1362 status = "disabled"; 725
726 hdmi_mux_0: endpoint {
727 remote-endpoint = <&ipu1_di0_hdmi>;
728 };
1363 }; 729 };
1364 730
1365 lvds-channel@1 { 731 port@1 {
1366 reg = <1>; 732 reg = <1>;
1367 status = "disabled"; 733
734 hdmi_mux_1: endpoint {
735 remote-endpoint = <&ipu1_di1_hdmi>;
736 };
1368 }; 737 };
1369 }; 738 };
1370 739
1371 dcic1: dcic@020e4000 { 740 dcic1: dcic@020e4000 {
1372 reg = <0x020e4000 0x4000>; 741 reg = <0x020e4000 0x4000>;
1373 interrupts = <0 124 0x04>; 742 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
1374 }; 743 };
1375 744
1376 dcic2: dcic@020e8000 { 745 dcic2: dcic@020e8000 {
1377 reg = <0x020e8000 0x4000>; 746 reg = <0x020e8000 0x4000>;
1378 interrupts = <0 125 0x04>; 747 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
1379 }; 748 };
1380 749
1381 sdma: sdma@020ec000 { 750 sdma: sdma@020ec000 {
1382 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 751 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1383 reg = <0x020ec000 0x4000>; 752 reg = <0x020ec000 0x4000>;
1384 interrupts = <0 2 0x04>; 753 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
1385 clocks = <&clks 155>, <&clks 155>; 754 clocks = <&clks 155>, <&clks 155>;
1386 clock-names = "ipg", "ahb"; 755 clock-names = "ipg", "ahb";
1387 #dma-cells = <3>; 756 #dma-cells = <3>;
@@ -1398,7 +767,8 @@
1398 767
1399 caam@02100000 { 768 caam@02100000 {
1400 reg = <0x02100000 0x40000>; 769 reg = <0x02100000 0x40000>;
1401 interrupts = <0 105 0x04 0 106 0x04>; 770 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
771 <0 106 IRQ_TYPE_LEVEL_HIGH>;
1402 }; 772 };
1403 773
1404 aipstz@0217c000 { /* AIPSTZ2 */ 774 aipstz@0217c000 { /* AIPSTZ2 */
@@ -1408,7 +778,7 @@
1408 usbotg: usb@02184000 { 778 usbotg: usb@02184000 {
1409 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 779 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1410 reg = <0x02184000 0x200>; 780 reg = <0x02184000 0x200>;
1411 interrupts = <0 43 0x04>; 781 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
1412 clocks = <&clks 162>; 782 clocks = <&clks 162>;
1413 fsl,usbphy = <&usbphy1>; 783 fsl,usbphy = <&usbphy1>;
1414 fsl,usbmisc = <&usbmisc 0>; 784 fsl,usbmisc = <&usbmisc 0>;
@@ -1418,7 +788,7 @@
1418 usbh1: usb@02184200 { 788 usbh1: usb@02184200 {
1419 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 789 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1420 reg = <0x02184200 0x200>; 790 reg = <0x02184200 0x200>;
1421 interrupts = <0 40 0x04>; 791 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
1422 clocks = <&clks 162>; 792 clocks = <&clks 162>;
1423 fsl,usbphy = <&usbphy2>; 793 fsl,usbphy = <&usbphy2>;
1424 fsl,usbmisc = <&usbmisc 1>; 794 fsl,usbmisc = <&usbmisc 1>;
@@ -1428,7 +798,7 @@
1428 usbh2: usb@02184400 { 798 usbh2: usb@02184400 {
1429 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 799 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1430 reg = <0x02184400 0x200>; 800 reg = <0x02184400 0x200>;
1431 interrupts = <0 41 0x04>; 801 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1432 clocks = <&clks 162>; 802 clocks = <&clks 162>;
1433 fsl,usbmisc = <&usbmisc 2>; 803 fsl,usbmisc = <&usbmisc 2>;
1434 status = "disabled"; 804 status = "disabled";
@@ -1437,7 +807,7 @@
1437 usbh3: usb@02184600 { 807 usbh3: usb@02184600 {
1438 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 808 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1439 reg = <0x02184600 0x200>; 809 reg = <0x02184600 0x200>;
1440 interrupts = <0 42 0x04>; 810 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1441 clocks = <&clks 162>; 811 clocks = <&clks 162>;
1442 fsl,usbmisc = <&usbmisc 3>; 812 fsl,usbmisc = <&usbmisc 3>;
1443 status = "disabled"; 813 status = "disabled";
@@ -1453,7 +823,9 @@
1453 fec: ethernet@02188000 { 823 fec: ethernet@02188000 {
1454 compatible = "fsl,imx6q-fec"; 824 compatible = "fsl,imx6q-fec";
1455 reg = <0x02188000 0x4000>; 825 reg = <0x02188000 0x4000>;
1456 interrupts = <0 118 0x04 0 119 0x04>; 826 interrupts-extended =
827 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
828 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&clks 117>, <&clks 117>, <&clks 190>; 829 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
1458 clock-names = "ipg", "ahb", "ptp"; 830 clock-names = "ipg", "ahb", "ptp";
1459 status = "disabled"; 831 status = "disabled";
@@ -1461,13 +833,15 @@
1461 833
1462 mlb@0218c000 { 834 mlb@0218c000 {
1463 reg = <0x0218c000 0x4000>; 835 reg = <0x0218c000 0x4000>;
1464 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; 836 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
837 <0 117 IRQ_TYPE_LEVEL_HIGH>,
838 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1465 }; 839 };
1466 840
1467 usdhc1: usdhc@02190000 { 841 usdhc1: usdhc@02190000 {
1468 compatible = "fsl,imx6q-usdhc"; 842 compatible = "fsl,imx6q-usdhc";
1469 reg = <0x02190000 0x4000>; 843 reg = <0x02190000 0x4000>;
1470 interrupts = <0 22 0x04>; 844 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&clks 163>, <&clks 163>, <&clks 163>; 845 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1472 clock-names = "ipg", "ahb", "per"; 846 clock-names = "ipg", "ahb", "per";
1473 bus-width = <4>; 847 bus-width = <4>;
@@ -1477,7 +851,7 @@
1477 usdhc2: usdhc@02194000 { 851 usdhc2: usdhc@02194000 {
1478 compatible = "fsl,imx6q-usdhc"; 852 compatible = "fsl,imx6q-usdhc";
1479 reg = <0x02194000 0x4000>; 853 reg = <0x02194000 0x4000>;
1480 interrupts = <0 23 0x04>; 854 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1481 clocks = <&clks 164>, <&clks 164>, <&clks 164>; 855 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1482 clock-names = "ipg", "ahb", "per"; 856 clock-names = "ipg", "ahb", "per";
1483 bus-width = <4>; 857 bus-width = <4>;
@@ -1487,7 +861,7 @@
1487 usdhc3: usdhc@02198000 { 861 usdhc3: usdhc@02198000 {
1488 compatible = "fsl,imx6q-usdhc"; 862 compatible = "fsl,imx6q-usdhc";
1489 reg = <0x02198000 0x4000>; 863 reg = <0x02198000 0x4000>;
1490 interrupts = <0 24 0x04>; 864 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1491 clocks = <&clks 165>, <&clks 165>, <&clks 165>; 865 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1492 clock-names = "ipg", "ahb", "per"; 866 clock-names = "ipg", "ahb", "per";
1493 bus-width = <4>; 867 bus-width = <4>;
@@ -1497,7 +871,7 @@
1497 usdhc4: usdhc@0219c000 { 871 usdhc4: usdhc@0219c000 {
1498 compatible = "fsl,imx6q-usdhc"; 872 compatible = "fsl,imx6q-usdhc";
1499 reg = <0x0219c000 0x4000>; 873 reg = <0x0219c000 0x4000>;
1500 interrupts = <0 25 0x04>; 874 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1501 clocks = <&clks 166>, <&clks 166>, <&clks 166>; 875 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1502 clock-names = "ipg", "ahb", "per"; 876 clock-names = "ipg", "ahb", "per";
1503 bus-width = <4>; 877 bus-width = <4>;
@@ -1509,7 +883,7 @@
1509 #size-cells = <0>; 883 #size-cells = <0>;
1510 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 884 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1511 reg = <0x021a0000 0x4000>; 885 reg = <0x021a0000 0x4000>;
1512 interrupts = <0 36 0x04>; 886 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1513 clocks = <&clks 125>; 887 clocks = <&clks 125>;
1514 status = "disabled"; 888 status = "disabled";
1515 }; 889 };
@@ -1519,7 +893,7 @@
1519 #size-cells = <0>; 893 #size-cells = <0>;
1520 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 894 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1521 reg = <0x021a4000 0x4000>; 895 reg = <0x021a4000 0x4000>;
1522 interrupts = <0 37 0x04>; 896 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1523 clocks = <&clks 126>; 897 clocks = <&clks 126>;
1524 status = "disabled"; 898 status = "disabled";
1525 }; 899 };
@@ -1529,7 +903,7 @@
1529 #size-cells = <0>; 903 #size-cells = <0>;
1530 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 904 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1531 reg = <0x021a8000 0x4000>; 905 reg = <0x021a8000 0x4000>;
1532 interrupts = <0 38 0x04>; 906 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1533 clocks = <&clks 127>; 907 clocks = <&clks 127>;
1534 status = "disabled"; 908 status = "disabled";
1535 }; 909 };
@@ -1550,7 +924,7 @@
1550 weim: weim@021b8000 { 924 weim: weim@021b8000 {
1551 compatible = "fsl,imx6q-weim"; 925 compatible = "fsl,imx6q-weim";
1552 reg = <0x021b8000 0x4000>; 926 reg = <0x021b8000 0x4000>;
1553 interrupts = <0 14 0x04>; 927 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1554 clocks = <&clks 196>; 928 clocks = <&clks 196>;
1555 }; 929 };
1556 930
@@ -1561,12 +935,12 @@
1561 935
1562 tzasc@021d0000 { /* TZASC1 */ 936 tzasc@021d0000 { /* TZASC1 */
1563 reg = <0x021d0000 0x4000>; 937 reg = <0x021d0000 0x4000>;
1564 interrupts = <0 108 0x04>; 938 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1565 }; 939 };
1566 940
1567 tzasc@021d4000 { /* TZASC2 */ 941 tzasc@021d4000 { /* TZASC2 */
1568 reg = <0x021d4000 0x4000>; 942 reg = <0x021d4000 0x4000>;
1569 interrupts = <0 109 0x04>; 943 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1570 }; 944 };
1571 945
1572 audmux: audmux@021d8000 { 946 audmux: audmux@021d8000 {
@@ -1575,23 +949,42 @@
1575 status = "disabled"; 949 status = "disabled";
1576 }; 950 };
1577 951
1578 mipi@021dc000 { /* MIPI-CSI */ 952 mipi_csi: mipi@021dc000 {
1579 reg = <0x021dc000 0x4000>; 953 reg = <0x021dc000 0x4000>;
1580 }; 954 };
1581 955
1582 mipi@021e0000 { /* MIPI-DSI */ 956 mipi_dsi: mipi@021e0000 {
957 #address-cells = <1>;
958 #size-cells = <0>;
1583 reg = <0x021e0000 0x4000>; 959 reg = <0x021e0000 0x4000>;
960 status = "disabled";
961
962 port@0 {
963 reg = <0>;
964
965 mipi_mux_0: endpoint {
966 remote-endpoint = <&ipu1_di0_mipi>;
967 };
968 };
969
970 port@1 {
971 reg = <1>;
972
973 mipi_mux_1: endpoint {
974 remote-endpoint = <&ipu1_di1_mipi>;
975 };
976 };
1584 }; 977 };
1585 978
1586 vdoa@021e4000 { 979 vdoa@021e4000 {
1587 reg = <0x021e4000 0x4000>; 980 reg = <0x021e4000 0x4000>;
1588 interrupts = <0 18 0x04>; 981 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1589 }; 982 };
1590 983
1591 uart2: serial@021e8000 { 984 uart2: serial@021e8000 {
1592 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 985 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1593 reg = <0x021e8000 0x4000>; 986 reg = <0x021e8000 0x4000>;
1594 interrupts = <0 27 0x04>; 987 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1595 clocks = <&clks 160>, <&clks 161>; 988 clocks = <&clks 160>, <&clks 161>;
1596 clock-names = "ipg", "per"; 989 clock-names = "ipg", "per";
1597 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 990 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
@@ -1602,7 +995,7 @@
1602 uart3: serial@021ec000 { 995 uart3: serial@021ec000 {
1603 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 996 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1604 reg = <0x021ec000 0x4000>; 997 reg = <0x021ec000 0x4000>;
1605 interrupts = <0 28 0x04>; 998 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1606 clocks = <&clks 160>, <&clks 161>; 999 clocks = <&clks 160>, <&clks 161>;
1607 clock-names = "ipg", "per"; 1000 clock-names = "ipg", "per";
1608 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1001 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
@@ -1613,7 +1006,7 @@
1613 uart4: serial@021f0000 { 1006 uart4: serial@021f0000 {
1614 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1007 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1615 reg = <0x021f0000 0x4000>; 1008 reg = <0x021f0000 0x4000>;
1616 interrupts = <0 29 0x04>; 1009 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1617 clocks = <&clks 160>, <&clks 161>; 1010 clocks = <&clks 160>, <&clks 161>;
1618 clock-names = "ipg", "per"; 1011 clock-names = "ipg", "per";
1619 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1012 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
@@ -1624,7 +1017,7 @@
1624 uart5: serial@021f4000 { 1017 uart5: serial@021f4000 {
1625 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1018 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1626 reg = <0x021f4000 0x4000>; 1019 reg = <0x021f4000 0x4000>;
1627 interrupts = <0 30 0x04>; 1020 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1628 clocks = <&clks 160>, <&clks 161>; 1021 clocks = <&clks 160>, <&clks 161>;
1629 clock-names = "ipg", "per"; 1022 clock-names = "ipg", "per";
1630 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1023 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
@@ -1634,13 +1027,65 @@
1634 }; 1027 };
1635 1028
1636 ipu1: ipu@02400000 { 1029 ipu1: ipu@02400000 {
1637 #crtc-cells = <1>; 1030 #address-cells = <1>;
1031 #size-cells = <0>;
1638 compatible = "fsl,imx6q-ipu"; 1032 compatible = "fsl,imx6q-ipu";
1639 reg = <0x02400000 0x400000>; 1033 reg = <0x02400000 0x400000>;
1640 interrupts = <0 6 0x4 0 5 0x4>; 1034 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1035 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1641 clocks = <&clks 130>, <&clks 131>, <&clks 132>; 1036 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1642 clock-names = "bus", "di0", "di1"; 1037 clock-names = "bus", "di0", "di1";
1643 resets = <&src 2>; 1038 resets = <&src 2>;
1039
1040 ipu1_di0: port@2 {
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 reg = <2>;
1044
1045 ipu1_di0_disp0: endpoint@0 {
1046 };
1047
1048 ipu1_di0_hdmi: endpoint@1 {
1049 remote-endpoint = <&hdmi_mux_0>;
1050 };
1051
1052 ipu1_di0_mipi: endpoint@2 {
1053 remote-endpoint = <&mipi_mux_0>;
1054 };
1055
1056 ipu1_di0_lvds0: endpoint@3 {
1057 remote-endpoint = <&lvds0_mux_0>;
1058 };
1059
1060 ipu1_di0_lvds1: endpoint@4 {
1061 remote-endpoint = <&lvds1_mux_0>;
1062 };
1063 };
1064
1065 ipu1_di1: port@3 {
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1068 reg = <3>;
1069
1070 ipu1_di0_disp1: endpoint@0 {
1071 };
1072
1073 ipu1_di1_hdmi: endpoint@1 {
1074 remote-endpoint = <&hdmi_mux_1>;
1075 };
1076
1077 ipu1_di1_mipi: endpoint@2 {
1078 remote-endpoint = <&mipi_mux_1>;
1079 };
1080
1081 ipu1_di1_lvds0: endpoint@3 {
1082 remote-endpoint = <&lvds0_mux_1>;
1083 };
1084
1085 ipu1_di1_lvds1: endpoint@4 {
1086 remote-endpoint = <&lvds1_mux_1>;
1087 };
1088 };
1644 }; 1089 };
1645 }; 1090 };
1646}; 1091};
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index cc68e19c5163..864d8dfb51ca 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -8,6 +8,8 @@
8 8
9/dts-v1/; 9/dts-v1/;
10 10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
11#include "imx6sl.dtsi" 13#include "imx6sl.dtsi"
12 14
13/ { 15/ {
@@ -18,11 +20,26 @@
18 reg = <0x80000000 0x40000000>; 20 reg = <0x80000000 0x40000000>;
19 }; 21 };
20 22
23 leds {
24 compatible = "gpio-leds";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_led>;
27
28 user {
29 label = "debug";
30 gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
31 linux,default-trigger = "heartbeat";
32 };
33 };
34
21 regulators { 35 regulators {
22 compatible = "simple-bus"; 36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <0>;
23 39
24 reg_usb_otg1_vbus: usb_otg1_vbus { 40 reg_usb_otg1_vbus: regulator@0 {
25 compatible = "regulator-fixed"; 41 compatible = "regulator-fixed";
42 reg = <0>;
26 regulator-name = "usb_otg1_vbus"; 43 regulator-name = "usb_otg1_vbus";
27 regulator-min-microvolt = <5000000>; 44 regulator-min-microvolt = <5000000>;
28 regulator-max-microvolt = <5000000>; 45 regulator-max-microvolt = <5000000>;
@@ -30,22 +47,63 @@
30 enable-active-high; 47 enable-active-high;
31 }; 48 };
32 49
33 reg_usb_otg2_vbus: usb_otg2_vbus { 50 reg_usb_otg2_vbus: regulator@1 {
34 compatible = "regulator-fixed"; 51 compatible = "regulator-fixed";
52 reg = <1>;
35 regulator-name = "usb_otg2_vbus"; 53 regulator-name = "usb_otg2_vbus";
36 regulator-min-microvolt = <5000000>; 54 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>; 55 regulator-max-microvolt = <5000000>;
38 gpio = <&gpio4 2 0>; 56 gpio = <&gpio4 2 0>;
39 enable-active-high; 57 enable-active-high;
40 }; 58 };
59
60 reg_aud3v: regulator@2 {
61 compatible = "regulator-fixed";
62 reg = <2>;
63 regulator-name = "wm8962-supply-3v15";
64 regulator-min-microvolt = <3150000>;
65 regulator-max-microvolt = <3150000>;
66 regulator-boot-on;
67 };
68
69 reg_aud4v: regulator@3 {
70 compatible = "regulator-fixed";
71 reg = <3>;
72 regulator-name = "wm8962-supply-4v2";
73 regulator-min-microvolt = <4325000>;
74 regulator-max-microvolt = <4325000>;
75 regulator-boot-on;
76 };
77 };
78
79 sound {
80 compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
81 model = "wm8962-audio";
82 ssi-controller = <&ssi2>;
83 audio-codec = <&codec>;
84 audio-routing =
85 "Headphone Jack", "HPOUTL",
86 "Headphone Jack", "HPOUTR",
87 "Ext Spk", "SPKOUTL",
88 "Ext Spk", "SPKOUTR",
89 "AMIC", "MICBIAS",
90 "IN3R", "AMIC";
91 mux-int-port = <2>;
92 mux-ext-port = <3>;
41 }; 93 };
42}; 94};
43 95
96&audmux {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_audmux3>;
99 status = "okay";
100};
101
44&ecspi1 { 102&ecspi1 {
45 fsl,spi-num-chipselects = <1>; 103 fsl,spi-num-chipselects = <1>;
46 cs-gpios = <&gpio4 11 0>; 104 cs-gpios = <&gpio4 11 0>;
47 pinctrl-names = "default"; 105 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_ecspi1_1>; 106 pinctrl-0 = <&pinctrl_ecspi1>;
49 status = "okay"; 107 status = "okay";
50 108
51 flash: m25p80@0 { 109 flash: m25p80@0 {
@@ -59,16 +117,144 @@
59 117
60&fec { 118&fec {
61 pinctrl-names = "default"; 119 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_fec_1>; 120 pinctrl-0 = <&pinctrl_fec>;
63 phy-mode = "rmii"; 121 phy-mode = "rmii";
64 status = "okay"; 122 status = "okay";
65}; 123};
66 124
125&i2c1 {
126 clock-frequency = <100000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c1>;
129 status = "okay";
130
131 pmic: pfuze100@08 {
132 compatible = "fsl,pfuze100";
133 reg = <0x08>;
134
135 regulators {
136 sw1a_reg: sw1ab {
137 regulator-min-microvolt = <300000>;
138 regulator-max-microvolt = <1875000>;
139 regulator-boot-on;
140 regulator-always-on;
141 regulator-ramp-delay = <6250>;
142 };
143
144 sw1c_reg: sw1c {
145 regulator-min-microvolt = <300000>;
146 regulator-max-microvolt = <1875000>;
147 regulator-boot-on;
148 regulator-always-on;
149 regulator-ramp-delay = <6250>;
150 };
151
152 sw2_reg: sw2 {
153 regulator-min-microvolt = <800000>;
154 regulator-max-microvolt = <3300000>;
155 regulator-boot-on;
156 regulator-always-on;
157 };
158
159 sw3a_reg: sw3a {
160 regulator-min-microvolt = <400000>;
161 regulator-max-microvolt = <1975000>;
162 regulator-boot-on;
163 regulator-always-on;
164 };
165
166 sw3b_reg: sw3b {
167 regulator-min-microvolt = <400000>;
168 regulator-max-microvolt = <1975000>;
169 regulator-boot-on;
170 regulator-always-on;
171 };
172
173 sw4_reg: sw4 {
174 regulator-min-microvolt = <800000>;
175 regulator-max-microvolt = <3300000>;
176 };
177
178 swbst_reg: swbst {
179 regulator-min-microvolt = <5000000>;
180 regulator-max-microvolt = <5150000>;
181 };
182
183 snvs_reg: vsnvs {
184 regulator-min-microvolt = <1000000>;
185 regulator-max-microvolt = <3000000>;
186 regulator-boot-on;
187 regulator-always-on;
188 };
189
190 vref_reg: vrefddr {
191 regulator-boot-on;
192 regulator-always-on;
193 };
194
195 vgen1_reg: vgen1 {
196 regulator-min-microvolt = <800000>;
197 regulator-max-microvolt = <1550000>;
198 regulator-always-on;
199 };
200
201 vgen2_reg: vgen2 {
202 regulator-min-microvolt = <800000>;
203 regulator-max-microvolt = <1550000>;
204 };
205
206 vgen3_reg: vgen3 {
207 regulator-min-microvolt = <1800000>;
208 regulator-max-microvolt = <3300000>;
209 };
210
211 vgen4_reg: vgen4 {
212 regulator-min-microvolt = <1800000>;
213 regulator-max-microvolt = <3300000>;
214 regulator-always-on;
215 };
216
217 vgen5_reg: vgen5 {
218 regulator-min-microvolt = <1800000>;
219 regulator-max-microvolt = <3300000>;
220 regulator-always-on;
221 };
222
223 vgen6_reg: vgen6 {
224 regulator-min-microvolt = <1800000>;
225 regulator-max-microvolt = <3300000>;
226 regulator-always-on;
227 };
228 };
229 };
230};
231
232&i2c2 {
233 clock-frequency = <100000>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_i2c2>;
236 status = "okay";
237
238 codec: wm8962@1a {
239 compatible = "wlf,wm8962";
240 reg = <0x1a>;
241 clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
242 DCVDD-supply = <&vgen3_reg>;
243 DBVDD-supply = <&reg_aud3v>;
244 AVDD-supply = <&vgen3_reg>;
245 CPVDD-supply = <&vgen3_reg>;
246 MICVDD-supply = <&reg_aud3v>;
247 PLLVDD-supply = <&vgen3_reg>;
248 SPKVDD1-supply = <&reg_aud4v>;
249 SPKVDD2-supply = <&reg_aud4v>;
250 };
251};
252
67&iomuxc { 253&iomuxc {
68 pinctrl-names = "default"; 254 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_hog>; 255 pinctrl-0 = <&pinctrl_hog>;
70 256
71 hog { 257 imx6sl-evk {
72 pinctrl_hog: hoggrp { 258 pinctrl_hog: hoggrp {
73 fsl,pins = < 259 fsl,pins = <
74 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 260 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
@@ -78,21 +264,230 @@
78 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 264 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
79 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 265 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
80 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 266 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
267 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
268 >;
269 };
270
271 pinctrl_audmux3: audmux3grp {
272 fsl,pins = <
273 MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
274 MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
275 MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
276 MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
277 >;
278 };
279
280 pinctrl_ecspi1: ecspi1grp {
281 fsl,pins = <
282 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
283 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
284 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
285 >;
286 };
287
288 pinctrl_fec: fecgrp {
289 fsl,pins = <
290 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
291 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
292 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
293 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
294 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
295 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
296 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
297 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
298 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
299 >;
300 };
301
302 pinctrl_i2c1: i2c1grp {
303 fsl,pins = <
304 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
305 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
306 >;
307 };
308
309
310 pinctrl_i2c2: i2c2grp {
311 fsl,pins = <
312 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
313 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
314 >;
315 };
316
317 pinctrl_led: ledgrp {
318 fsl,pins = <
319 MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
320 >;
321 };
322
323 pinctrl_kpp: kppgrp {
324 fsl,pins = <
325 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
326 MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
327 MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
328 MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
329 MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
330 MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
331 >;
332 };
333
334 pinctrl_uart1: uart1grp {
335 fsl,pins = <
336 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
337 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
338 >;
339 };
340
341 pinctrl_usbotg1: usbotg1grp {
342 fsl,pins = <
343 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
344 >;
345 };
346
347 pinctrl_usdhc1: usdhc1grp {
348 fsl,pins = <
349 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
350 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
351 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
352 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
353 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
354 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
355 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
356 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
357 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
358 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
359 >;
360 };
361
362 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
363 fsl,pins = <
364 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
365 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
366 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
367 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
368 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
369 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
370 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
371 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
372 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
373 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
374 >;
375 };
376
377 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
378 fsl,pins = <
379 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
380 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
381 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
382 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
383 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
384 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
385 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
386 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
387 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
388 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
389 >;
390 };
391
392 pinctrl_usdhc2: usdhc2grp {
393 fsl,pins = <
394 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
395 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
396 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
397 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
398 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
399 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
400 >;
401 };
402
403 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
404 fsl,pins = <
405 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
406 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
407 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
408 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
409 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
410 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
411 >;
412 };
413
414 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
415 fsl,pins = <
416 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
417 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
418 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
419 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
420 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
421 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
422 >;
423 };
424
425 pinctrl_usdhc3: usdhc3grp {
426 fsl,pins = <
427 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
428 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
429 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
430 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
431 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
432 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
433 >;
434 };
435
436 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
437 fsl,pins = <
438 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
439 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
440 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
441 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
442 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
443 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
444 >;
445 };
446
447 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
448 fsl,pins = <
449 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
450 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
451 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
452 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
453 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
454 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
81 >; 455 >;
82 }; 456 };
83 }; 457 };
84}; 458};
85 459
460&kpp {
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_kpp>;
463 linux,keymap = <
464 MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */
465 MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */
466 MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */
467 MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */
468 MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */
469 MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */
470 MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
471 MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
472 >;
473 status = "okay";
474};
475
476&ssi2 {
477 fsl,mode = "i2s-slave";
478 status = "okay";
479};
480
86&uart1 { 481&uart1 {
87 pinctrl-names = "default"; 482 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_uart1_1>; 483 pinctrl-0 = <&pinctrl_uart1>;
89 status = "okay"; 484 status = "okay";
90}; 485};
91 486
92&usbotg1 { 487&usbotg1 {
93 vbus-supply = <&reg_usb_otg1_vbus>; 488 vbus-supply = <&reg_usb_otg1_vbus>;
94 pinctrl-names = "default"; 489 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_usbotg1_1>; 490 pinctrl-0 = <&pinctrl_usbotg1>;
96 disable-over-current; 491 disable-over-current;
97 status = "okay"; 492 status = "okay";
98}; 493};
@@ -106,9 +501,9 @@
106 501
107&usdhc1 { 502&usdhc1 {
108 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 503 pinctrl-names = "default", "state_100mhz", "state_200mhz";
109 pinctrl-0 = <&pinctrl_usdhc1_1>; 504 pinctrl-0 = <&pinctrl_usdhc1>;
110 pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>; 505 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
111 pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>; 506 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
112 bus-width = <8>; 507 bus-width = <8>;
113 cd-gpios = <&gpio4 7 0>; 508 cd-gpios = <&gpio4 7 0>;
114 wp-gpios = <&gpio4 6 0>; 509 wp-gpios = <&gpio4 6 0>;
@@ -117,9 +512,9 @@
117 512
118&usdhc2 { 513&usdhc2 {
119 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 514 pinctrl-names = "default", "state_100mhz", "state_200mhz";
120 pinctrl-0 = <&pinctrl_usdhc2_1>; 515 pinctrl-0 = <&pinctrl_usdhc2>;
121 pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; 516 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
122 pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; 517 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
123 cd-gpios = <&gpio5 0 0>; 518 cd-gpios = <&gpio5 0 0>;
124 wp-gpios = <&gpio4 29 0>; 519 wp-gpios = <&gpio4 29 0>;
125 status = "okay"; 520 status = "okay";
@@ -127,9 +522,9 @@
127 522
128&usdhc3 { 523&usdhc3 {
129 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 524 pinctrl-names = "default", "state_100mhz", "state_200mhz";
130 pinctrl-0 = <&pinctrl_usdhc3_1>; 525 pinctrl-0 = <&pinctrl_usdhc3>;
131 pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; 526 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
132 pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; 527 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
133 cd-gpios = <&gpio3 22 0>; 528 cd-gpios = <&gpio3 22 0>;
134 status = "okay"; 529 status = "okay";
135}; 530};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 28558f1aaf2d..3cb4941afeef 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -7,6 +7,7 @@
7 * 7 *
8 */ 8 */
9 9
10#include <dt-bindings/interrupt-controller/irq.h>
10#include "skeleton.dtsi" 11#include "skeleton.dtsi"
11#include "imx6sl-pinfunc.h" 12#include "imx6sl-pinfunc.h"
12#include <dt-bindings/clock/imx6sl-clock.h> 13#include <dt-bindings/clock/imx6sl-clock.h>
@@ -27,6 +28,8 @@
27 spi1 = &ecspi2; 28 spi1 = &ecspi2;
28 spi2 = &ecspi3; 29 spi2 = &ecspi3;
29 spi3 = &ecspi4; 30 spi3 = &ecspi4;
31 usbphy0 = &usbphy1;
32 usbphy1 = &usbphy2;
30 }; 33 };
31 34
32 cpus { 35 cpus {
@@ -38,6 +41,27 @@
38 device_type = "cpu"; 41 device_type = "cpu";
39 reg = <0x0>; 42 reg = <0x0>;
40 next-level-cache = <&L2>; 43 next-level-cache = <&L2>;
44 operating-points = <
45 /* kHz uV */
46 996000 1275000
47 792000 1175000
48 396000 975000
49 >;
50 fsl,soc-operating-points = <
51 /* ARM kHz SOC-PU uV */
52 996000 1225000
53 792000 1175000
54 396000 1175000
55 >;
56 clock-latency = <61036>; /* two CLK32 periods */
57 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
58 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
59 <&clks IMX6SL_CLK_PLL1_SYS>;
60 clock-names = "arm", "pll2_pfd2_396m", "step",
61 "pll1_sw", "pll1_sys";
62 arm-supply = <&reg_arm>;
63 pu-supply = <&reg_pu>;
64 soc-supply = <&reg_soc>;
41 }; 65 };
42 }; 66 };
43 67
@@ -73,10 +97,16 @@
73 interrupt-parent = <&intc>; 97 interrupt-parent = <&intc>;
74 ranges; 98 ranges;
75 99
100 ocram: sram@00900000 {
101 compatible = "mmio-sram";
102 reg = <0x00900000 0x20000>;
103 clocks = <&clks IMX6SL_CLK_OCRAM>;
104 };
105
76 L2: l2-cache@00a02000 { 106 L2: l2-cache@00a02000 {
77 compatible = "arm,pl310-cache"; 107 compatible = "arm,pl310-cache";
78 reg = <0x00a02000 0x1000>; 108 reg = <0x00a02000 0x1000>;
79 interrupts = <0 92 0x04>; 109 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
80 cache-unified; 110 cache-unified;
81 cache-level = <2>; 111 cache-level = <2>;
82 arm,tag-latency = <4 2 3>; 112 arm,tag-latency = <4 2 3>;
@@ -85,7 +115,7 @@
85 115
86 pmu { 116 pmu {
87 compatible = "arm,cortex-a9-pmu"; 117 compatible = "arm,cortex-a9-pmu";
88 interrupts = <0 94 0x04>; 118 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
89 }; 119 };
90 120
91 aips1: aips-bus@02000000 { 121 aips1: aips-bus@02000000 {
@@ -104,7 +134,7 @@
104 134
105 spdif: spdif@02004000 { 135 spdif: spdif@02004000 {
106 reg = <0x02004000 0x4000>; 136 reg = <0x02004000 0x4000>;
107 interrupts = <0 52 0x04>; 137 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
108 }; 138 };
109 139
110 ecspi1: ecspi@02008000 { 140 ecspi1: ecspi@02008000 {
@@ -112,7 +142,7 @@
112 #size-cells = <0>; 142 #size-cells = <0>;
113 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 143 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
114 reg = <0x02008000 0x4000>; 144 reg = <0x02008000 0x4000>;
115 interrupts = <0 31 0x04>; 145 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&clks IMX6SL_CLK_ECSPI1>, 146 clocks = <&clks IMX6SL_CLK_ECSPI1>,
117 <&clks IMX6SL_CLK_ECSPI1>; 147 <&clks IMX6SL_CLK_ECSPI1>;
118 clock-names = "ipg", "per"; 148 clock-names = "ipg", "per";
@@ -124,7 +154,7 @@
124 #size-cells = <0>; 154 #size-cells = <0>;
125 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 155 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
126 reg = <0x0200c000 0x4000>; 156 reg = <0x0200c000 0x4000>;
127 interrupts = <0 32 0x04>; 157 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&clks IMX6SL_CLK_ECSPI2>, 158 clocks = <&clks IMX6SL_CLK_ECSPI2>,
129 <&clks IMX6SL_CLK_ECSPI2>; 159 <&clks IMX6SL_CLK_ECSPI2>;
130 clock-names = "ipg", "per"; 160 clock-names = "ipg", "per";
@@ -136,7 +166,7 @@
136 #size-cells = <0>; 166 #size-cells = <0>;
137 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 167 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
138 reg = <0x02010000 0x4000>; 168 reg = <0x02010000 0x4000>;
139 interrupts = <0 33 0x04>; 169 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&clks IMX6SL_CLK_ECSPI3>, 170 clocks = <&clks IMX6SL_CLK_ECSPI3>,
141 <&clks IMX6SL_CLK_ECSPI3>; 171 <&clks IMX6SL_CLK_ECSPI3>;
142 clock-names = "ipg", "per"; 172 clock-names = "ipg", "per";
@@ -148,7 +178,7 @@
148 #size-cells = <0>; 178 #size-cells = <0>;
149 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 179 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
150 reg = <0x02014000 0x4000>; 180 reg = <0x02014000 0x4000>;
151 interrupts = <0 34 0x04>; 181 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&clks IMX6SL_CLK_ECSPI4>, 182 clocks = <&clks IMX6SL_CLK_ECSPI4>,
153 <&clks IMX6SL_CLK_ECSPI4>; 183 <&clks IMX6SL_CLK_ECSPI4>;
154 clock-names = "ipg", "per"; 184 clock-names = "ipg", "per";
@@ -159,7 +189,7 @@
159 compatible = "fsl,imx6sl-uart", 189 compatible = "fsl,imx6sl-uart",
160 "fsl,imx6q-uart", "fsl,imx21-uart"; 190 "fsl,imx6q-uart", "fsl,imx21-uart";
161 reg = <0x02018000 0x4000>; 191 reg = <0x02018000 0x4000>;
162 interrupts = <0 30 0x04>; 192 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&clks IMX6SL_CLK_UART>, 193 clocks = <&clks IMX6SL_CLK_UART>,
164 <&clks IMX6SL_CLK_UART_SERIAL>; 194 <&clks IMX6SL_CLK_UART_SERIAL>;
165 clock-names = "ipg", "per"; 195 clock-names = "ipg", "per";
@@ -172,7 +202,7 @@
172 compatible = "fsl,imx6sl-uart", 202 compatible = "fsl,imx6sl-uart",
173 "fsl,imx6q-uart", "fsl,imx21-uart"; 203 "fsl,imx6q-uart", "fsl,imx21-uart";
174 reg = <0x02020000 0x4000>; 204 reg = <0x02020000 0x4000>;
175 interrupts = <0 26 0x04>; 205 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6SL_CLK_UART>, 206 clocks = <&clks IMX6SL_CLK_UART>,
177 <&clks IMX6SL_CLK_UART_SERIAL>; 207 <&clks IMX6SL_CLK_UART_SERIAL>;
178 clock-names = "ipg", "per"; 208 clock-names = "ipg", "per";
@@ -185,7 +215,7 @@
185 compatible = "fsl,imx6sl-uart", 215 compatible = "fsl,imx6sl-uart",
186 "fsl,imx6q-uart", "fsl,imx21-uart"; 216 "fsl,imx6q-uart", "fsl,imx21-uart";
187 reg = <0x02024000 0x4000>; 217 reg = <0x02024000 0x4000>;
188 interrupts = <0 27 0x04>; 218 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&clks IMX6SL_CLK_UART>, 219 clocks = <&clks IMX6SL_CLK_UART>,
190 <&clks IMX6SL_CLK_UART_SERIAL>; 220 <&clks IMX6SL_CLK_UART_SERIAL>;
191 clock-names = "ipg", "per"; 221 clock-names = "ipg", "per";
@@ -195,9 +225,11 @@
195 }; 225 };
196 226
197 ssi1: ssi@02028000 { 227 ssi1: ssi@02028000 {
198 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; 228 compatible = "fsl,imx6sl-ssi",
229 "fsl,imx51-ssi",
230 "fsl,imx21-ssi";
199 reg = <0x02028000 0x4000>; 231 reg = <0x02028000 0x4000>;
200 interrupts = <0 46 0x04>; 232 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&clks IMX6SL_CLK_SSI1>; 233 clocks = <&clks IMX6SL_CLK_SSI1>;
202 dmas = <&sdma 37 1 0>, 234 dmas = <&sdma 37 1 0>,
203 <&sdma 38 1 0>; 235 <&sdma 38 1 0>;
@@ -207,9 +239,11 @@
207 }; 239 };
208 240
209 ssi2: ssi@0202c000 { 241 ssi2: ssi@0202c000 {
210 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; 242 compatible = "fsl,imx6sl-ssi",
243 "fsl,imx51-ssi",
244 "fsl,imx21-ssi";
211 reg = <0x0202c000 0x4000>; 245 reg = <0x0202c000 0x4000>;
212 interrupts = <0 47 0x04>; 246 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&clks IMX6SL_CLK_SSI2>; 247 clocks = <&clks IMX6SL_CLK_SSI2>;
214 dmas = <&sdma 41 1 0>, 248 dmas = <&sdma 41 1 0>,
215 <&sdma 42 1 0>; 249 <&sdma 42 1 0>;
@@ -219,9 +253,11 @@
219 }; 253 };
220 254
221 ssi3: ssi@02030000 { 255 ssi3: ssi@02030000 {
222 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; 256 compatible = "fsl,imx6sl-ssi",
257 "fsl,imx51-ssi",
258 "fsl,imx21-ssi";
223 reg = <0x02030000 0x4000>; 259 reg = <0x02030000 0x4000>;
224 interrupts = <0 48 0x04>; 260 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&clks IMX6SL_CLK_SSI3>; 261 clocks = <&clks IMX6SL_CLK_SSI3>;
226 dmas = <&sdma 45 1 0>, 262 dmas = <&sdma 45 1 0>,
227 <&sdma 46 1 0>; 263 <&sdma 46 1 0>;
@@ -234,7 +270,7 @@
234 compatible = "fsl,imx6sl-uart", 270 compatible = "fsl,imx6sl-uart",
235 "fsl,imx6q-uart", "fsl,imx21-uart"; 271 "fsl,imx6q-uart", "fsl,imx21-uart";
236 reg = <0x02034000 0x4000>; 272 reg = <0x02034000 0x4000>;
237 interrupts = <0 28 0x04>; 273 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks IMX6SL_CLK_UART>, 274 clocks = <&clks IMX6SL_CLK_UART>,
239 <&clks IMX6SL_CLK_UART_SERIAL>; 275 <&clks IMX6SL_CLK_UART_SERIAL>;
240 clock-names = "ipg", "per"; 276 clock-names = "ipg", "per";
@@ -247,7 +283,7 @@
247 compatible = "fsl,imx6sl-uart", 283 compatible = "fsl,imx6sl-uart",
248 "fsl,imx6q-uart", "fsl,imx21-uart"; 284 "fsl,imx6q-uart", "fsl,imx21-uart";
249 reg = <0x02038000 0x4000>; 285 reg = <0x02038000 0x4000>;
250 interrupts = <0 29 0x04>; 286 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clks IMX6SL_CLK_UART>, 287 clocks = <&clks IMX6SL_CLK_UART>,
252 <&clks IMX6SL_CLK_UART_SERIAL>; 288 <&clks IMX6SL_CLK_UART_SERIAL>;
253 clock-names = "ipg", "per"; 289 clock-names = "ipg", "per";
@@ -261,7 +297,7 @@
261 #pwm-cells = <2>; 297 #pwm-cells = <2>;
262 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 298 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
263 reg = <0x02080000 0x4000>; 299 reg = <0x02080000 0x4000>;
264 interrupts = <0 83 0x04>; 300 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&clks IMX6SL_CLK_PWM1>, 301 clocks = <&clks IMX6SL_CLK_PWM1>,
266 <&clks IMX6SL_CLK_PWM1>; 302 <&clks IMX6SL_CLK_PWM1>;
267 clock-names = "ipg", "per"; 303 clock-names = "ipg", "per";
@@ -271,7 +307,7 @@
271 #pwm-cells = <2>; 307 #pwm-cells = <2>;
272 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 308 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
273 reg = <0x02084000 0x4000>; 309 reg = <0x02084000 0x4000>;
274 interrupts = <0 84 0x04>; 310 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&clks IMX6SL_CLK_PWM2>, 311 clocks = <&clks IMX6SL_CLK_PWM2>,
276 <&clks IMX6SL_CLK_PWM2>; 312 <&clks IMX6SL_CLK_PWM2>;
277 clock-names = "ipg", "per"; 313 clock-names = "ipg", "per";
@@ -281,7 +317,7 @@
281 #pwm-cells = <2>; 317 #pwm-cells = <2>;
282 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 318 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
283 reg = <0x02088000 0x4000>; 319 reg = <0x02088000 0x4000>;
284 interrupts = <0 85 0x04>; 320 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6SL_CLK_PWM3>, 321 clocks = <&clks IMX6SL_CLK_PWM3>,
286 <&clks IMX6SL_CLK_PWM3>; 322 <&clks IMX6SL_CLK_PWM3>;
287 clock-names = "ipg", "per"; 323 clock-names = "ipg", "per";
@@ -291,7 +327,7 @@
291 #pwm-cells = <2>; 327 #pwm-cells = <2>;
292 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 328 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
293 reg = <0x0208c000 0x4000>; 329 reg = <0x0208c000 0x4000>;
294 interrupts = <0 86 0x04>; 330 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks IMX6SL_CLK_PWM4>, 331 clocks = <&clks IMX6SL_CLK_PWM4>,
296 <&clks IMX6SL_CLK_PWM4>; 332 <&clks IMX6SL_CLK_PWM4>;
297 clock-names = "ipg", "per"; 333 clock-names = "ipg", "per";
@@ -300,7 +336,7 @@
300 gpt: gpt@02098000 { 336 gpt: gpt@02098000 {
301 compatible = "fsl,imx6sl-gpt"; 337 compatible = "fsl,imx6sl-gpt";
302 reg = <0x02098000 0x4000>; 338 reg = <0x02098000 0x4000>;
303 interrupts = <0 55 0x04>; 339 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SL_CLK_GPT>, 340 clocks = <&clks IMX6SL_CLK_GPT>,
305 <&clks IMX6SL_CLK_GPT_SERIAL>; 341 <&clks IMX6SL_CLK_GPT_SERIAL>;
306 clock-names = "ipg", "per"; 342 clock-names = "ipg", "per";
@@ -309,7 +345,8 @@
309 gpio1: gpio@0209c000 { 345 gpio1: gpio@0209c000 {
310 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 346 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
311 reg = <0x0209c000 0x4000>; 347 reg = <0x0209c000 0x4000>;
312 interrupts = <0 66 0x04 0 67 0x04>; 348 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
349 <0 67 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller; 350 gpio-controller;
314 #gpio-cells = <2>; 351 #gpio-cells = <2>;
315 interrupt-controller; 352 interrupt-controller;
@@ -319,7 +356,8 @@
319 gpio2: gpio@020a0000 { 356 gpio2: gpio@020a0000 {
320 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 357 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
321 reg = <0x020a0000 0x4000>; 358 reg = <0x020a0000 0x4000>;
322 interrupts = <0 68 0x04 0 69 0x04>; 359 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
360 <0 69 IRQ_TYPE_LEVEL_HIGH>;
323 gpio-controller; 361 gpio-controller;
324 #gpio-cells = <2>; 362 #gpio-cells = <2>;
325 interrupt-controller; 363 interrupt-controller;
@@ -329,7 +367,8 @@
329 gpio3: gpio@020a4000 { 367 gpio3: gpio@020a4000 {
330 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 368 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
331 reg = <0x020a4000 0x4000>; 369 reg = <0x020a4000 0x4000>;
332 interrupts = <0 70 0x04 0 71 0x04>; 370 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
371 <0 71 IRQ_TYPE_LEVEL_HIGH>;
333 gpio-controller; 372 gpio-controller;
334 #gpio-cells = <2>; 373 #gpio-cells = <2>;
335 interrupt-controller; 374 interrupt-controller;
@@ -339,7 +378,8 @@
339 gpio4: gpio@020a8000 { 378 gpio4: gpio@020a8000 {
340 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 379 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
341 reg = <0x020a8000 0x4000>; 380 reg = <0x020a8000 0x4000>;
342 interrupts = <0 72 0x04 0 73 0x04>; 381 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
382 <0 73 IRQ_TYPE_LEVEL_HIGH>;
343 gpio-controller; 383 gpio-controller;
344 #gpio-cells = <2>; 384 #gpio-cells = <2>;
345 interrupt-controller; 385 interrupt-controller;
@@ -349,7 +389,8 @@
349 gpio5: gpio@020ac000 { 389 gpio5: gpio@020ac000 {
350 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 390 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
351 reg = <0x020ac000 0x4000>; 391 reg = <0x020ac000 0x4000>;
352 interrupts = <0 74 0x04 0 75 0x04>; 392 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
393 <0 75 IRQ_TYPE_LEVEL_HIGH>;
353 gpio-controller; 394 gpio-controller;
354 #gpio-cells = <2>; 395 #gpio-cells = <2>;
355 interrupt-controller; 396 interrupt-controller;
@@ -357,21 +398,23 @@
357 }; 398 };
358 399
359 kpp: kpp@020b8000 { 400 kpp: kpp@020b8000 {
401 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
360 reg = <0x020b8000 0x4000>; 402 reg = <0x020b8000 0x4000>;
361 interrupts = <0 82 0x04>; 403 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clks IMX6SL_CLK_DUMMY>;
362 }; 405 };
363 406
364 wdog1: wdog@020bc000 { 407 wdog1: wdog@020bc000 {
365 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 408 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
366 reg = <0x020bc000 0x4000>; 409 reg = <0x020bc000 0x4000>;
367 interrupts = <0 80 0x04>; 410 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clks IMX6SL_CLK_DUMMY>; 411 clocks = <&clks IMX6SL_CLK_DUMMY>;
369 }; 412 };
370 413
371 wdog2: wdog@020c0000 { 414 wdog2: wdog@020c0000 {
372 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 415 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
373 reg = <0x020c0000 0x4000>; 416 reg = <0x020c0000 0x4000>;
374 interrupts = <0 81 0x04>; 417 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&clks IMX6SL_CLK_DUMMY>; 418 clocks = <&clks IMX6SL_CLK_DUMMY>;
376 status = "disabled"; 419 status = "disabled";
377 }; 420 };
@@ -379,7 +422,8 @@
379 clks: ccm@020c4000 { 422 clks: ccm@020c4000 {
380 compatible = "fsl,imx6sl-ccm"; 423 compatible = "fsl,imx6sl-ccm";
381 reg = <0x020c4000 0x4000>; 424 reg = <0x020c4000 0x4000>;
382 interrupts = <0 87 0x04 0 88 0x04>; 425 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
426 <0 88 IRQ_TYPE_LEVEL_HIGH>;
383 #clock-cells = <1>; 427 #clock-cells = <1>;
384 }; 428 };
385 429
@@ -388,7 +432,9 @@
388 "fsl,imx6q-anatop", 432 "fsl,imx6q-anatop",
389 "syscon", "simple-bus"; 433 "syscon", "simple-bus";
390 reg = <0x020c8000 0x1000>; 434 reg = <0x020c8000 0x1000>;
391 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; 435 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
436 <0 54 IRQ_TYPE_LEVEL_HIGH>,
437 <0 127 IRQ_TYPE_LEVEL_HIGH>;
392 438
393 regulator-1p1@110 { 439 regulator-1p1@110 {
394 compatible = "fsl,anatop-regulator"; 440 compatible = "fsl,anatop-regulator";
@@ -434,7 +480,7 @@
434 480
435 reg_arm: regulator-vddcore@140 { 481 reg_arm: regulator-vddcore@140 {
436 compatible = "fsl,anatop-regulator"; 482 compatible = "fsl,anatop-regulator";
437 regulator-name = "cpu"; 483 regulator-name = "vddarm";
438 regulator-min-microvolt = <725000>; 484 regulator-min-microvolt = <725000>;
439 regulator-max-microvolt = <1450000>; 485 regulator-max-microvolt = <1450000>;
440 regulator-always-on; 486 regulator-always-on;
@@ -487,15 +533,17 @@
487 usbphy1: usbphy@020c9000 { 533 usbphy1: usbphy@020c9000 {
488 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 534 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
489 reg = <0x020c9000 0x1000>; 535 reg = <0x020c9000 0x1000>;
490 interrupts = <0 44 0x04>; 536 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clks IMX6SL_CLK_USBPHY1>; 537 clocks = <&clks IMX6SL_CLK_USBPHY1>;
538 fsl,anatop = <&anatop>;
492 }; 539 };
493 540
494 usbphy2: usbphy@020ca000 { 541 usbphy2: usbphy@020ca000 {
495 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 542 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
496 reg = <0x020ca000 0x1000>; 543 reg = <0x020ca000 0x1000>;
497 interrupts = <0 45 0x04>; 544 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&clks IMX6SL_CLK_USBPHY2>; 545 clocks = <&clks IMX6SL_CLK_USBPHY2>;
546 fsl,anatop = <&anatop>;
499 }; 547 };
500 548
501 snvs@020cc000 { 549 snvs@020cc000 {
@@ -507,31 +555,33 @@
507 snvs-rtc-lp@34 { 555 snvs-rtc-lp@34 {
508 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 556 compatible = "fsl,sec-v4.0-mon-rtc-lp";
509 reg = <0x34 0x58>; 557 reg = <0x34 0x58>;
510 interrupts = <0 19 0x04 0 20 0x04>; 558 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
559 <0 20 IRQ_TYPE_LEVEL_HIGH>;
511 }; 560 };
512 }; 561 };
513 562
514 epit1: epit@020d0000 { 563 epit1: epit@020d0000 {
515 reg = <0x020d0000 0x4000>; 564 reg = <0x020d0000 0x4000>;
516 interrupts = <0 56 0x04>; 565 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
517 }; 566 };
518 567
519 epit2: epit@020d4000 { 568 epit2: epit@020d4000 {
520 reg = <0x020d4000 0x4000>; 569 reg = <0x020d4000 0x4000>;
521 interrupts = <0 57 0x04>; 570 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
522 }; 571 };
523 572
524 src: src@020d8000 { 573 src: src@020d8000 {
525 compatible = "fsl,imx6sl-src", "fsl,imx51-src"; 574 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
526 reg = <0x020d8000 0x4000>; 575 reg = <0x020d8000 0x4000>;
527 interrupts = <0 91 0x04 0 96 0x04>; 576 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
577 <0 96 IRQ_TYPE_LEVEL_HIGH>;
528 #reset-cells = <1>; 578 #reset-cells = <1>;
529 }; 579 };
530 580
531 gpc: gpc@020dc000 { 581 gpc: gpc@020dc000 {
532 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; 582 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
533 reg = <0x020dc000 0x4000>; 583 reg = <0x020dc000 0x4000>;
534 interrupts = <0 89 0x04>; 584 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
535 }; 585 };
536 586
537 gpr: iomuxc-gpr@020e0000 { 587 gpr: iomuxc-gpr@020e0000 {
@@ -543,235 +593,22 @@
543 iomuxc: iomuxc@020e0000 { 593 iomuxc: iomuxc@020e0000 {
544 compatible = "fsl,imx6sl-iomuxc"; 594 compatible = "fsl,imx6sl-iomuxc";
545 reg = <0x020e0000 0x4000>; 595 reg = <0x020e0000 0x4000>;
546
547 ecspi1 {
548 pinctrl_ecspi1_1: ecspi1grp-1 {
549 fsl,pins = <
550 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
551 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
552 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
553 >;
554 };
555 };
556
557 fec {
558 pinctrl_fec_1: fecgrp-1 {
559 fsl,pins = <
560 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
561 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
562 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
563 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
564 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
565 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
566 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
567 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
568 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
569 >;
570 };
571 };
572
573 uart1 {
574 pinctrl_uart1_1: uart1grp-1 {
575 fsl,pins = <
576 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
577 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
578 >;
579 };
580 };
581
582 usbotg1 {
583 pinctrl_usbotg1_1: usbotg1grp-1 {
584 fsl,pins = <
585 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
586 >;
587 };
588
589 pinctrl_usbotg1_2: usbotg1grp-2 {
590 fsl,pins = <
591 MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
592 >;
593 };
594
595 pinctrl_usbotg1_3: usbotg1grp-3 {
596 fsl,pins = <
597 MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
598 >;
599 };
600
601 pinctrl_usbotg1_4: usbotg1grp-4 {
602 fsl,pins = <
603 MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
604 >;
605 };
606
607 pinctrl_usbotg1_5: usbotg1grp-5 {
608 fsl,pins = <
609 MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
610 >;
611 };
612 };
613
614 usbotg2 {
615 pinctrl_usbotg2_1: usbotg2grp-1 {
616 fsl,pins = <
617 MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
618 >;
619 };
620
621 pinctrl_usbotg2_2: usbotg2grp-2 {
622 fsl,pins = <
623 MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
624 >;
625 };
626
627 pinctrl_usbotg2_3: usbotg2grp-3 {
628 fsl,pins = <
629 MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
630 >;
631 };
632
633 pinctrl_usbotg2_4: usbotg2grp-4 {
634 fsl,pins = <
635 MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
636 >;
637 };
638 };
639
640 usdhc1 {
641 pinctrl_usdhc1_1: usdhc1grp-1 {
642 fsl,pins = <
643 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
644 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
645 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
646 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
647 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
648 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
649 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
650 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
651 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
652 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
653 >;
654 };
655
656 pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
657 fsl,pins = <
658 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
659 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
660 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
661 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
662 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
663 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
664 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
665 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
666 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
667 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
668 >;
669 };
670
671 pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
672 fsl,pins = <
673 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
674 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
675 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
676 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
677 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
678 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
679 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
680 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
681 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
682 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
683 >;
684 };
685
686
687 };
688
689 usdhc2 {
690 pinctrl_usdhc2_1: usdhc2grp-1 {
691 fsl,pins = <
692 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
693 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
694 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
695 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
696 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
697 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
698 >;
699 };
700
701 pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
702 fsl,pins = <
703 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
704 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
705 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
706 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
707 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
708 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
709 >;
710 };
711
712 pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
713 fsl,pins = <
714 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
715 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
716 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
717 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
718 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
719 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
720 >;
721 };
722
723 };
724
725 usdhc3 {
726 pinctrl_usdhc3_1: usdhc3grp-1 {
727 fsl,pins = <
728 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
729 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
730 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
731 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
732 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
733 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
734 >;
735 };
736
737 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
738 fsl,pins = <
739 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
740 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
741 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
742 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
743 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
744 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
745 >;
746 };
747
748 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
749 fsl,pins = <
750 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
751 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
752 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
753 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
754 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
755 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
756 >;
757 };
758 };
759 }; 596 };
760 597
761 csi: csi@020e4000 { 598 csi: csi@020e4000 {
762 reg = <0x020e4000 0x4000>; 599 reg = <0x020e4000 0x4000>;
763 interrupts = <0 7 0x04>; 600 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
764 }; 601 };
765 602
766 spdc: spdc@020e8000 { 603 spdc: spdc@020e8000 {
767 reg = <0x020e8000 0x4000>; 604 reg = <0x020e8000 0x4000>;
768 interrupts = <0 6 0x04>; 605 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
769 }; 606 };
770 607
771 sdma: sdma@020ec000 { 608 sdma: sdma@020ec000 {
772 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma"; 609 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
773 reg = <0x020ec000 0x4000>; 610 reg = <0x020ec000 0x4000>;
774 interrupts = <0 2 0x04>; 611 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clks IMX6SL_CLK_SDMA>, 612 clocks = <&clks IMX6SL_CLK_SDMA>,
776 <&clks IMX6SL_CLK_SDMA>; 613 <&clks IMX6SL_CLK_SDMA>;
777 clock-names = "ipg", "ahb"; 614 clock-names = "ipg", "ahb";
@@ -782,22 +619,22 @@
782 619
783 pxp: pxp@020f0000 { 620 pxp: pxp@020f0000 {
784 reg = <0x020f0000 0x4000>; 621 reg = <0x020f0000 0x4000>;
785 interrupts = <0 98 0x04>; 622 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
786 }; 623 };
787 624
788 epdc: epdc@020f4000 { 625 epdc: epdc@020f4000 {
789 reg = <0x020f4000 0x4000>; 626 reg = <0x020f4000 0x4000>;
790 interrupts = <0 97 0x04>; 627 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
791 }; 628 };
792 629
793 lcdif: lcdif@020f8000 { 630 lcdif: lcdif@020f8000 {
794 reg = <0x020f8000 0x4000>; 631 reg = <0x020f8000 0x4000>;
795 interrupts = <0 39 0x04>; 632 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
796 }; 633 };
797 634
798 dcp: dcp@020fc000 { 635 dcp: dcp@020fc000 {
799 reg = <0x020fc000 0x4000>; 636 reg = <0x020fc000 0x4000>;
800 interrupts = <0 99 0x04>; 637 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
801 }; 638 };
802 }; 639 };
803 640
@@ -811,7 +648,7 @@
811 usbotg1: usb@02184000 { 648 usbotg1: usb@02184000 {
812 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 649 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
813 reg = <0x02184000 0x200>; 650 reg = <0x02184000 0x200>;
814 interrupts = <0 43 0x04>; 651 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX6SL_CLK_USBOH3>; 652 clocks = <&clks IMX6SL_CLK_USBOH3>;
816 fsl,usbphy = <&usbphy1>; 653 fsl,usbphy = <&usbphy1>;
817 fsl,usbmisc = <&usbmisc 0>; 654 fsl,usbmisc = <&usbmisc 0>;
@@ -821,7 +658,7 @@
821 usbotg2: usb@02184200 { 658 usbotg2: usb@02184200 {
822 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 659 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
823 reg = <0x02184200 0x200>; 660 reg = <0x02184200 0x200>;
824 interrupts = <0 42 0x04>; 661 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clks IMX6SL_CLK_USBOH3>; 662 clocks = <&clks IMX6SL_CLK_USBOH3>;
826 fsl,usbphy = <&usbphy2>; 663 fsl,usbphy = <&usbphy2>;
827 fsl,usbmisc = <&usbmisc 1>; 664 fsl,usbmisc = <&usbmisc 1>;
@@ -831,7 +668,7 @@
831 usbh: usb@02184400 { 668 usbh: usb@02184400 {
832 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 669 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
833 reg = <0x02184400 0x200>; 670 reg = <0x02184400 0x200>;
834 interrupts = <0 40 0x04>; 671 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clks IMX6SL_CLK_USBOH3>; 672 clocks = <&clks IMX6SL_CLK_USBOH3>;
836 fsl,usbmisc = <&usbmisc 2>; 673 fsl,usbmisc = <&usbmisc 2>;
837 status = "disabled"; 674 status = "disabled";
@@ -847,7 +684,7 @@
847 fec: ethernet@02188000 { 684 fec: ethernet@02188000 {
848 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; 685 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
849 reg = <0x02188000 0x4000>; 686 reg = <0x02188000 0x4000>;
850 interrupts = <0 114 0x04>; 687 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX6SL_CLK_ENET_REF>, 688 clocks = <&clks IMX6SL_CLK_ENET_REF>,
852 <&clks IMX6SL_CLK_ENET_REF>; 689 <&clks IMX6SL_CLK_ENET_REF>;
853 clock-names = "ipg", "ahb"; 690 clock-names = "ipg", "ahb";
@@ -857,7 +694,7 @@
857 usdhc1: usdhc@02190000 { 694 usdhc1: usdhc@02190000 {
858 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 695 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
859 reg = <0x02190000 0x4000>; 696 reg = <0x02190000 0x4000>;
860 interrupts = <0 22 0x04>; 697 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks IMX6SL_CLK_USDHC1>, 698 clocks = <&clks IMX6SL_CLK_USDHC1>,
862 <&clks IMX6SL_CLK_USDHC1>, 699 <&clks IMX6SL_CLK_USDHC1>,
863 <&clks IMX6SL_CLK_USDHC1>; 700 <&clks IMX6SL_CLK_USDHC1>;
@@ -869,7 +706,7 @@
869 usdhc2: usdhc@02194000 { 706 usdhc2: usdhc@02194000 {
870 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 707 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
871 reg = <0x02194000 0x4000>; 708 reg = <0x02194000 0x4000>;
872 interrupts = <0 23 0x04>; 709 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&clks IMX6SL_CLK_USDHC2>, 710 clocks = <&clks IMX6SL_CLK_USDHC2>,
874 <&clks IMX6SL_CLK_USDHC2>, 711 <&clks IMX6SL_CLK_USDHC2>,
875 <&clks IMX6SL_CLK_USDHC2>; 712 <&clks IMX6SL_CLK_USDHC2>;
@@ -881,7 +718,7 @@
881 usdhc3: usdhc@02198000 { 718 usdhc3: usdhc@02198000 {
882 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 719 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
883 reg = <0x02198000 0x4000>; 720 reg = <0x02198000 0x4000>;
884 interrupts = <0 24 0x04>; 721 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6SL_CLK_USDHC3>, 722 clocks = <&clks IMX6SL_CLK_USDHC3>,
886 <&clks IMX6SL_CLK_USDHC3>, 723 <&clks IMX6SL_CLK_USDHC3>,
887 <&clks IMX6SL_CLK_USDHC3>; 724 <&clks IMX6SL_CLK_USDHC3>;
@@ -893,7 +730,7 @@
893 usdhc4: usdhc@0219c000 { 730 usdhc4: usdhc@0219c000 {
894 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 731 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
895 reg = <0x0219c000 0x4000>; 732 reg = <0x0219c000 0x4000>;
896 interrupts = <0 25 0x04>; 733 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&clks IMX6SL_CLK_USDHC4>, 734 clocks = <&clks IMX6SL_CLK_USDHC4>,
898 <&clks IMX6SL_CLK_USDHC4>, 735 <&clks IMX6SL_CLK_USDHC4>,
899 <&clks IMX6SL_CLK_USDHC4>; 736 <&clks IMX6SL_CLK_USDHC4>;
@@ -907,7 +744,7 @@
907 #size-cells = <0>; 744 #size-cells = <0>;
908 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 745 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
909 reg = <0x021a0000 0x4000>; 746 reg = <0x021a0000 0x4000>;
910 interrupts = <0 36 0x04>; 747 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clks IMX6SL_CLK_I2C1>; 748 clocks = <&clks IMX6SL_CLK_I2C1>;
912 status = "disabled"; 749 status = "disabled";
913 }; 750 };
@@ -917,7 +754,7 @@
917 #size-cells = <0>; 754 #size-cells = <0>;
918 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 755 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
919 reg = <0x021a4000 0x4000>; 756 reg = <0x021a4000 0x4000>;
920 interrupts = <0 37 0x04>; 757 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clks IMX6SL_CLK_I2C2>; 758 clocks = <&clks IMX6SL_CLK_I2C2>;
922 status = "disabled"; 759 status = "disabled";
923 }; 760 };
@@ -927,7 +764,7 @@
927 #size-cells = <0>; 764 #size-cells = <0>;
928 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 765 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
929 reg = <0x021a8000 0x4000>; 766 reg = <0x021a8000 0x4000>;
930 interrupts = <0 38 0x04>; 767 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clks IMX6SL_CLK_I2C3>; 768 clocks = <&clks IMX6SL_CLK_I2C3>;
932 status = "disabled"; 769 status = "disabled";
933 }; 770 };
@@ -939,12 +776,12 @@
939 776
940 rngb: rngb@021b4000 { 777 rngb: rngb@021b4000 {
941 reg = <0x021b4000 0x4000>; 778 reg = <0x021b4000 0x4000>;
942 interrupts = <0 5 0x04>; 779 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
943 }; 780 };
944 781
945 weim: weim@021b8000 { 782 weim: weim@021b8000 {
946 reg = <0x021b8000 0x4000>; 783 reg = <0x021b8000 0x4000>;
947 interrupts = <0 14 0x04>; 784 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
948 }; 785 };
949 786
950 ocotp: ocotp@021bc000 { 787 ocotp: ocotp@021bc000 {
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index e6be9315ff0a..b10e6351da53 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -18,6 +18,28 @@
18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; 18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
19 }; 19 };
20 20
21 /* 24 MHz chrystal on the core module */
22 xtal24mhz: xtal24mhz@24M {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
26 };
27
28 pclk: pclk@0 {
29 #clock-cells = <0>;
30 compatible = "fixed-factor-clock";
31 clock-div = <1>;
32 clock-mult = <1>;
33 clocks = <&xtal24mhz>;
34 };
35
36 /* The UART clock is 14.74 MHz divided by an ICS525 */
37 uartclk: uartclk@14.74M {
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
40 clock-frequency = <14745600>;
41 };
42
21 syscon { 43 syscon {
22 compatible = "arm,integrator-ap-syscon"; 44 compatible = "arm,integrator-ap-syscon";
23 reg = <0x11000000 0x100>; 45 reg = <0x11000000 0x100>;
@@ -28,14 +50,17 @@
28 50
29 timer0: timer@13000000 { 51 timer0: timer@13000000 {
30 compatible = "arm,integrator-timer"; 52 compatible = "arm,integrator-timer";
53 clocks = <&xtal24mhz>;
31 }; 54 };
32 55
33 timer1: timer@13000100 { 56 timer1: timer@13000100 {
34 compatible = "arm,integrator-timer"; 57 compatible = "arm,integrator-timer";
58 clocks = <&xtal24mhz>;
35 }; 59 };
36 60
37 timer2: timer@13000200 { 61 timer2: timer@13000200 {
38 compatible = "arm,integrator-timer"; 62 compatible = "arm,integrator-timer";
63 clocks = <&xtal24mhz>;
39 }; 64 };
40 65
41 pic: pic@14000000 { 66 pic: pic@14000000 {
@@ -92,26 +117,36 @@
92 rtc: rtc@15000000 { 117 rtc: rtc@15000000 {
93 compatible = "arm,pl030", "arm,primecell"; 118 compatible = "arm,pl030", "arm,primecell";
94 arm,primecell-periphid = <0x00041030>; 119 arm,primecell-periphid = <0x00041030>;
120 clocks = <&pclk>;
121 clock-names = "apb_pclk";
95 }; 122 };
96 123
97 uart0: uart@16000000 { 124 uart0: uart@16000000 {
98 compatible = "arm,pl010", "arm,primecell"; 125 compatible = "arm,pl010", "arm,primecell";
99 arm,primecell-periphid = <0x00041010>; 126 arm,primecell-periphid = <0x00041010>;
127 clocks = <&uartclk>, <&pclk>;
128 clock-names = "uartclk", "apb_pclk";
100 }; 129 };
101 130
102 uart1: uart@17000000 { 131 uart1: uart@17000000 {
103 compatible = "arm,pl010", "arm,primecell"; 132 compatible = "arm,pl010", "arm,primecell";
104 arm,primecell-periphid = <0x00041010>; 133 arm,primecell-periphid = <0x00041010>;
134 clocks = <&uartclk>, <&pclk>;
135 clock-names = "uartclk", "apb_pclk";
105 }; 136 };
106 137
107 kmi0: kmi@18000000 { 138 kmi0: kmi@18000000 {
108 compatible = "arm,pl050", "arm,primecell"; 139 compatible = "arm,pl050", "arm,primecell";
109 arm,primecell-periphid = <0x00041050>; 140 arm,primecell-periphid = <0x00041050>;
141 clocks = <&xtal24mhz>, <&pclk>;
142 clock-names = "KMIREFCLK", "apb_pclk";
110 }; 143 };
111 144
112 kmi1: kmi@19000000 { 145 kmi1: kmi@19000000 {
113 compatible = "arm,pl050", "arm,primecell"; 146 compatible = "arm,pl050", "arm,primecell";
114 arm,primecell-periphid = <0x00041050>; 147 arm,primecell-periphid = <0x00041050>;
148 clocks = <&xtal24mhz>, <&pclk>;
149 clock-names = "KMIREFCLK", "apb_pclk";
115 }; 150 };
116 }; 151 };
117}; 152};
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index a21c17de9a5e..d43f15b4f79a 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -13,25 +13,107 @@
13 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; 13 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
14 }; 14 };
15 15
16 /*
17 * The Integrator/CP overall clocking architecture can be found in
18 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
19 * appear to illustrate the layout used in most configurations.
20 */
21
22 /* The codec chrystal operates at 24.576 MHz */
23 xtal_codec: xtal24.576@24.576M {
24 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <24576000>;
27 };
28
29 /* The chrystal is divided by 2 by the codec for the AACI bit clock */
30 aaci_bitclk: aaci_bitclk@12.288M {
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
33 clock-div = <2>;
34 clock-mult = <1>;
35 clocks = <&xtal_codec>;
36 };
37
38 /* This is a 25MHz chrystal on the base board */
39 xtal25mhz: xtal25mhz@25M {
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <25000000>;
43 };
44
45 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
46 uartclk: uartclk@14.74M {
47 #clock-cells = <0>;
48 compatible = "fixed-clock";
49 clock-frequency = <14745600>;
50 };
51
52 /* Actually sysclk I think */
53 pclk: pclk@0 {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <0>;
57 };
58
59 core-module@10000000 {
60 /* 24 MHz chrystal on the core module */
61 xtal24mhz: xtal24mhz@24M {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <24000000>;
65 };
66
67 /*
68 * External oscillator on the core module, usually used
69 * to drive video circuitry. Driven from the 24MHz clock.
70 */
71 auxosc: cm_aux_osc@25M {
72 #clock-cells = <0>;
73 compatible = "arm,integrator-cm-auxosc";
74 clocks = <&xtal24mhz>;
75 };
76
77 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
78 kmiclk: kmiclk@1M {
79 #clock-cells = <0>;
80 compatible = "fixed-factor-clock";
81 clock-div = <3>;
82 clock-mult = <1>;
83 clocks = <&xtal24mhz>;
84 };
85
86 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
87 timclk: timclk@1M {
88 #clock-cells = <0>;
89 compatible = "fixed-factor-clock";
90 clock-div = <24>;
91 clock-mult = <1>;
92 clocks = <&xtal24mhz>;
93 };
94 };
95
16 syscon { 96 syscon {
17 compatible = "arm,integrator-cp-syscon"; 97 compatible = "arm,integrator-cp-syscon";
18 reg = <0xcb000000 0x100>; 98 reg = <0xcb000000 0x100>;
19 }; 99 };
20 100
21 timer0: timer@13000000 { 101 timer0: timer@13000000 {
22 /* TIMER0 runs @ 25MHz */ 102 /* TIMER0 runs directly on the 25MHz chrystal */
23 compatible = "arm,integrator-cp-timer"; 103 compatible = "arm,integrator-cp-timer";
24 status = "disabled"; 104 clocks = <&xtal25mhz>;
25 }; 105 };
26 106
27 timer1: timer@13000100 { 107 timer1: timer@13000100 {
28 /* TIMER1 runs @ 1MHz */ 108 /* TIMER1 runs @ 1MHz */
29 compatible = "arm,integrator-cp-timer"; 109 compatible = "arm,integrator-cp-timer";
110 clocks = <&timclk>;
30 }; 111 };
31 112
32 timer2: timer@13000200 { 113 timer2: timer@13000200 {
33 /* TIMER2 runs @ 1MHz */ 114 /* TIMER2 runs @ 1MHz */
34 compatible = "arm,integrator-cp-timer"; 115 compatible = "arm,integrator-cp-timer";
116 clocks = <&timclk>;
35 }; 117 };
36 118
37 pic: pic@14000000 { 119 pic: pic@14000000 {
@@ -74,22 +156,32 @@
74 */ 156 */
75 rtc@15000000 { 157 rtc@15000000 {
76 compatible = "arm,pl031", "arm,primecell"; 158 compatible = "arm,pl031", "arm,primecell";
159 clocks = <&pclk>;
160 clock-names = "apb_pclk";
77 }; 161 };
78 162
79 uart@16000000 { 163 uart@16000000 {
80 compatible = "arm,pl011", "arm,primecell"; 164 compatible = "arm,pl011", "arm,primecell";
165 clocks = <&uartclk>, <&pclk>;
166 clock-names = "uartclk", "apb_pclk";
81 }; 167 };
82 168
83 uart@17000000 { 169 uart@17000000 {
84 compatible = "arm,pl011", "arm,primecell"; 170 compatible = "arm,pl011", "arm,primecell";
171 clocks = <&uartclk>, <&pclk>;
172 clock-names = "uartclk", "apb_pclk";
85 }; 173 };
86 174
87 kmi@18000000 { 175 kmi@18000000 {
88 compatible = "arm,pl050", "arm,primecell"; 176 compatible = "arm,pl050", "arm,primecell";
177 clocks = <&kmiclk>, <&pclk>;
178 clock-names = "KMIREFCLK", "apb_pclk";
89 }; 179 };
90 180
91 kmi@19000000 { 181 kmi@19000000 {
92 compatible = "arm,pl050", "arm,primecell"; 182 compatible = "arm,pl050", "arm,primecell";
183 clocks = <&kmiclk>, <&pclk>;
184 clock-names = "KMIREFCLK", "apb_pclk";
93 }; 185 };
94 186
95 /* 187 /*
@@ -100,18 +192,24 @@
100 reg = <0x1c000000 0x1000>; 192 reg = <0x1c000000 0x1000>;
101 interrupts = <23 24>; 193 interrupts = <23 24>;
102 max-frequency = <515633>; 194 max-frequency = <515633>;
195 clocks = <&uartclk>, <&pclk>;
196 clock-names = "mclk", "apb_pclk";
103 }; 197 };
104 198
105 aaci@1d000000 { 199 aaci@1d000000 {
106 compatible = "arm,pl041", "arm,primecell"; 200 compatible = "arm,pl041", "arm,primecell";
107 reg = <0x1d000000 0x1000>; 201 reg = <0x1d000000 0x1000>;
108 interrupts = <25>; 202 interrupts = <25>;
203 clocks = <&pclk>;
204 clock-names = "apb_pclk";
109 }; 205 };
110 206
111 clcd@c0000000 { 207 clcd@c0000000 {
112 compatible = "arm,pl110", "arm,primecell"; 208 compatible = "arm,pl110", "arm,primecell";
113 reg = <0xC0000000 0x1000>; 209 reg = <0xC0000000 0x1000>;
114 interrupts = <22>; 210 interrupts = <22>;
211 clocks = <&auxosc>, <&pclk>;
212 clock-names = "clcd", "apb_pclk";
115 }; 213 };
116 }; 214 };
117}; 215};
diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi
new file mode 100644
index 000000000000..90774d604bc1
--- /dev/null
+++ b/arch/arm/boot/dts/k2e-clocks.dtsi
@@ -0,0 +1,78 @@
1/*
2 * Copyright 2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Edison SoC specific device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11clocks {
12 mainpllclk: mainpllclk@2310110 {
13 #clock-cells = <0>;
14 compatible = "ti,keystone,main-pll-clock";
15 clocks = <&refclksys>;
16 reg = <0x02620350 4>, <0x02310110 4>;
17 reg-names = "control", "multiplier";
18 fixed-postdiv = <2>;
19 };
20
21 papllclk: papllclk@2620358 {
22 #clock-cells = <0>;
23 compatible = "ti,keystone,pll-clock";
24 clocks = <&refclkpass>;
25 clock-output-names = "pa-pll-clk";
26 reg = <0x02620358 4>;
27 reg-names = "control";
28 };
29
30 ddr3apllclk: ddr3apllclk@2620360 {
31 #clock-cells = <0>;
32 compatible = "ti,keystone,pll-clock";
33 clocks = <&refclkddr3a>;
34 clock-output-names = "ddr-3a-pll-clk";
35 reg = <0x02620360 4>;
36 reg-names = "control";
37 };
38
39 clkusb1: clkusb1 {
40 #clock-cells = <0>;
41 compatible = "ti,keystone,psc-clock";
42 clocks = <&chipclk16>;
43 clock-output-names = "usb";
44 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
45 reg-names = "control", "domain";
46 domain-id = <0>;
47 };
48
49 clkhyperlink0: clkhyperlink0 {
50 #clock-cells = <0>;
51 compatible = "ti,keystone,psc-clock";
52 clocks = <&chipclk12>;
53 clock-output-names = "hyperlink-0";
54 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
55 reg-names = "control", "domain";
56 domain-id = <5>;
57 };
58
59 clkpcie1: clkpcie1 {
60 #clock-cells = <0>;
61 compatible = "ti,keystone,psc-clock";
62 clocks = <&chipclk12>;
63 clock-output-names = "pcie";
64 reg = <0x0235006c 0xb00>, <0x02350000 0x400>;
65 reg-names = "control", "domain";
66 domain-id = <18>;
67 };
68
69 clkxge: clkxge {
70 #clock-cells = <0>;
71 compatible = "ti,keystone,psc-clock";
72 clocks = <&chipclk13>;
73 clock-output-names = "xge";
74 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
75 reg-names = "control", "domain";
76 domain-id = <29>;
77 };
78};
diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts
new file mode 100644
index 000000000000..74b3b63e94cf
--- /dev/null
+++ b/arch/arm/boot/dts/k2e-evm.dts
@@ -0,0 +1,60 @@
1/*
2 * Copyright 2013-2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Edison EVM device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10/dts-v1/;
11
12#include "keystone.dtsi"
13#include "k2e.dtsi"
14
15/ {
16 compatible = "ti,k2e-evm","ti,keystone";
17 model = "Texas Instruments Keystone 2 Edison EVM";
18
19 soc {
20
21 clocks {
22 refclksys: refclksys {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <100000000>;
26 clock-output-names = "refclk-sys";
27 };
28
29 refclkpass: refclkpass {
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
32 clock-frequency = <100000000>;
33 clock-output-names = "refclk-pass";
34 };
35
36 refclkddr3a: refclkddr3a {
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <100000000>;
40 clock-output-names = "refclk-ddr3a";
41 };
42 };
43 };
44};
45
46&usb_phy {
47 status = "okay";
48};
49
50&usb {
51 status = "okay";
52};
53
54&usb1_phy {
55 status = "okay";
56};
57
58&usb1 {
59 status = "okay";
60};
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
new file mode 100644
index 000000000000..03d01909525b
--- /dev/null
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -0,0 +1,80 @@
1/*
2 * Copyright 2013-2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Edison soc device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/ {
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 interrupt-parent = <&gic>;
17
18 cpu@0 {
19 compatible = "arm,cortex-a15";
20 device_type = "cpu";
21 reg = <0>;
22 };
23
24 cpu@1 {
25 compatible = "arm,cortex-a15";
26 device_type = "cpu";
27 reg = <1>;
28 };
29
30 cpu@2 {
31 compatible = "arm,cortex-a15";
32 device_type = "cpu";
33 reg = <2>;
34 };
35
36 cpu@3 {
37 compatible = "arm,cortex-a15";
38 device_type = "cpu";
39 reg = <3>;
40 };
41 };
42
43 soc {
44 /include/ "k2e-clocks.dtsi"
45
46 usb: usb@2680000 {
47 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
48 dwc3@2690000 {
49 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
50 };
51 };
52
53 usb1_phy: usb_phy@2620750 {
54 compatible = "ti,keystone-usbphy";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0x2620750 24>;
58 status = "disabled";
59 };
60
61 usb1: usb@25000000 {
62 compatible = "ti,keystone-dwc3";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x25000000 0x10000>;
66 clocks = <&clkusb1>;
67 clock-names = "usb";
68 interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
69 ranges;
70 status = "disabled";
71
72 dwc3@25010000 {
73 compatible = "synopsys,dwc3";
74 reg = <0x25010000 0x70000>;
75 interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
76 usb-phy = <&usb1_phy>, <&usb1_phy>;
77 };
78 };
79 };
80};
diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi
new file mode 100644
index 000000000000..96e65365afe3
--- /dev/null
+++ b/arch/arm/boot/dts/k2hk-clocks.dtsi
@@ -0,0 +1,426 @@
1/*
2 * Copyright 2013-2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Kepler/Hawking SoC clock nodes
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11clocks {
12 armpllclk: armpllclk@2620370 {
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
15 clocks = <&refclkarm>;
16 clock-output-names = "arm-pll-clk";
17 reg = <0x02620370 4>;
18 reg-names = "control";
19 };
20
21 mainpllclk: mainpllclk@2310110 {
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
24 clocks = <&refclksys>;
25 reg = <0x02620350 4>, <0x02310110 4>;
26 reg-names = "control", "multiplier";
27 fixed-postdiv = <2>;
28 };
29
30 papllclk: papllclk@2620358 {
31 #clock-cells = <0>;
32 compatible = "ti,keystone,pll-clock";
33 clocks = <&refclkpass>;
34 clock-output-names = "pa-pll-clk";
35 reg = <0x02620358 4>;
36 reg-names = "control";
37 };
38
39 ddr3apllclk: ddr3apllclk@2620360 {
40 #clock-cells = <0>;
41 compatible = "ti,keystone,pll-clock";
42 clocks = <&refclkddr3a>;
43 clock-output-names = "ddr-3a-pll-clk";
44 reg = <0x02620360 4>;
45 reg-names = "control";
46 };
47
48 ddr3bpllclk: ddr3bpllclk@2620368 {
49 #clock-cells = <0>;
50 compatible = "ti,keystone,pll-clock";
51 clocks = <&refclkddr3b>;
52 clock-output-names = "ddr-3b-pll-clk";
53 reg = <0x02620368 4>;
54 reg-names = "control";
55 };
56
57 clktsip: clktsip {
58 #clock-cells = <0>;
59 compatible = "ti,keystone,psc-clock";
60 clocks = <&chipclk16>;
61 clock-output-names = "tsip";
62 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
63 reg-names = "control", "domain";
64 domain-id = <0>;
65 };
66
67 clksrio: clksrio {
68 #clock-cells = <0>;
69 compatible = "ti,keystone,psc-clock";
70 clocks = <&chipclk1rstiso13>;
71 clock-output-names = "srio";
72 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
73 reg-names = "control", "domain";
74 domain-id = <4>;
75 };
76
77 clkhyperlink0: clkhyperlink0 {
78 #clock-cells = <0>;
79 compatible = "ti,keystone,psc-clock";
80 clocks = <&chipclk12>;
81 clock-output-names = "hyperlink-0";
82 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
83 reg-names = "control", "domain";
84 domain-id = <5>;
85 };
86
87 clkgem1: clkgem1 {
88 #clock-cells = <0>;
89 compatible = "ti,keystone,psc-clock";
90 clocks = <&chipclk1>;
91 clock-output-names = "gem1";
92 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
93 reg-names = "control", "domain";
94 domain-id = <9>;
95 };
96
97 clkgem2: clkgem2 {
98 #clock-cells = <0>;
99 compatible = "ti,keystone,psc-clock";
100 clocks = <&chipclk1>;
101 clock-output-names = "gem2";
102 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
103 reg-names = "control", "domain";
104 domain-id = <10>;
105 };
106
107 clkgem3: clkgem3 {
108 #clock-cells = <0>;
109 compatible = "ti,keystone,psc-clock";
110 clocks = <&chipclk1>;
111 clock-output-names = "gem3";
112 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
113 reg-names = "control", "domain";
114 domain-id = <11>;
115 };
116
117 clkgem4: clkgem4 {
118 #clock-cells = <0>;
119 compatible = "ti,keystone,psc-clock";
120 clocks = <&chipclk1>;
121 clock-output-names = "gem4";
122 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
123 reg-names = "control", "domain";
124 domain-id = <12>;
125 };
126
127 clkgem5: clkgem5 {
128 #clock-cells = <0>;
129 compatible = "ti,keystone,psc-clock";
130 clocks = <&chipclk1>;
131 clock-output-names = "gem5";
132 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
133 reg-names = "control", "domain";
134 domain-id = <13>;
135 };
136
137 clkgem6: clkgem6 {
138 #clock-cells = <0>;
139 compatible = "ti,keystone,psc-clock";
140 clocks = <&chipclk1>;
141 clock-output-names = "gem6";
142 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
143 reg-names = "control", "domain";
144 domain-id = <14>;
145 };
146
147 clkgem7: clkgem7 {
148 #clock-cells = <0>;
149 compatible = "ti,keystone,psc-clock";
150 clocks = <&chipclk1>;
151 clock-output-names = "gem7";
152 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
153 reg-names = "control", "domain";
154 domain-id = <15>;
155 };
156
157 clkddr31: clkddr31 {
158 #clock-cells = <0>;
159 compatible = "ti,keystone,psc-clock";
160 clocks = <&chipclk13>;
161 clock-output-names = "ddr3-1";
162 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
163 reg-names = "control", "domain";
164 domain-id = <16>;
165 };
166
167 clktac: clktac {
168 #clock-cells = <0>;
169 compatible = "ti,keystone,psc-clock";
170 clocks = <&chipclk13>;
171 clock-output-names = "tac";
172 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
173 reg-names = "control", "domain";
174 domain-id = <17>;
175 };
176
177 clkrac01: clkrac01 {
178 #clock-cells = <0>;
179 compatible = "ti,keystone,psc-clock";
180 clocks = <&chipclk13>;
181 clock-output-names = "rac-01";
182 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
183 reg-names = "control", "domain";
184 domain-id = <17>;
185 };
186
187 clkrac23: clkrac23 {
188 #clock-cells = <0>;
189 compatible = "ti,keystone,psc-clock";
190 clocks = <&chipclk13>;
191 clock-output-names = "rac-23";
192 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
193 reg-names = "control", "domain";
194 domain-id = <18>;
195 };
196
197 clkfftc0: clkfftc0 {
198 #clock-cells = <0>;
199 compatible = "ti,keystone,psc-clock";
200 clocks = <&chipclk13>;
201 clock-output-names = "fftc-0";
202 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
203 reg-names = "control", "domain";
204 domain-id = <19>;
205 };
206
207 clkfftc1: clkfftc1 {
208 #clock-cells = <0>;
209 compatible = "ti,keystone,psc-clock";
210 clocks = <&chipclk13>;
211 clock-output-names = "fftc-1";
212 reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
213 reg-names = "control", "domain";
214 domain-id = <19>;
215 };
216
217 clkfftc2: clkfftc2 {
218 #clock-cells = <0>;
219 compatible = "ti,keystone,psc-clock";
220 clocks = <&chipclk13>;
221 clock-output-names = "fftc-2";
222 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
223 reg-names = "control", "domain";
224 domain-id = <20>;
225 };
226
227 clkfftc3: clkfftc3 {
228 #clock-cells = <0>;
229 compatible = "ti,keystone,psc-clock";
230 clocks = <&chipclk13>;
231 clock-output-names = "fftc-3";
232 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
233 reg-names = "control", "domain";
234 domain-id = <20>;
235 };
236
237 clkfftc4: clkfftc4 {
238 #clock-cells = <0>;
239 compatible = "ti,keystone,psc-clock";
240 clocks = <&chipclk13>;
241 clock-output-names = "fftc-4";
242 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
243 reg-names = "control", "domain";
244 domain-id = <20>;
245 };
246
247 clkfftc5: clkfftc5 {
248 #clock-cells = <0>;
249 compatible = "ti,keystone,psc-clock";
250 clocks = <&chipclk13>;
251 clock-output-names = "fftc-5";
252 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
253 reg-names = "control", "domain";
254 domain-id = <20>;
255 };
256
257 clkaif: clkaif {
258 #clock-cells = <0>;
259 compatible = "ti,keystone,psc-clock";
260 clocks = <&chipclk13>;
261 clock-output-names = "aif";
262 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
263 reg-names = "control", "domain";
264 domain-id = <21>;
265 };
266
267 clktcp3d0: clktcp3d0 {
268 #clock-cells = <0>;
269 compatible = "ti,keystone,psc-clock";
270 clocks = <&chipclk13>;
271 clock-output-names = "tcp3d-0";
272 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
273 reg-names = "control", "domain";
274 domain-id = <22>;
275 };
276
277 clktcp3d1: clktcp3d1 {
278 #clock-cells = <0>;
279 compatible = "ti,keystone,psc-clock";
280 clocks = <&chipclk13>;
281 clock-output-names = "tcp3d-1";
282 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
283 reg-names = "control", "domain";
284 domain-id = <22>;
285 };
286
287 clktcp3d2: clktcp3d2 {
288 #clock-cells = <0>;
289 compatible = "ti,keystone,psc-clock";
290 clocks = <&chipclk13>;
291 clock-output-names = "tcp3d-2";
292 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
293 reg-names = "control", "domain";
294 domain-id = <23>;
295 };
296
297 clktcp3d3: clktcp3d3 {
298 #clock-cells = <0>;
299 compatible = "ti,keystone,psc-clock";
300 clocks = <&chipclk13>;
301 clock-output-names = "tcp3d-3";
302 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
303 reg-names = "control", "domain";
304 domain-id = <23>;
305 };
306
307 clkvcp0: clkvcp0 {
308 #clock-cells = <0>;
309 compatible = "ti,keystone,psc-clock";
310 clocks = <&chipclk13>;
311 clock-output-names = "vcp-0";
312 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
313 reg-names = "control", "domain";
314 domain-id = <24>;
315 };
316
317 clkvcp1: clkvcp1 {
318 #clock-cells = <0>;
319 compatible = "ti,keystone,psc-clock";
320 clocks = <&chipclk13>;
321 clock-output-names = "vcp-1";
322 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
323 reg-names = "control", "domain";
324 domain-id = <24>;
325 };
326
327 clkvcp2: clkvcp2 {
328 #clock-cells = <0>;
329 compatible = "ti,keystone,psc-clock";
330 clocks = <&chipclk13>;
331 clock-output-names = "vcp-2";
332 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
333 reg-names = "control", "domain";
334 domain-id = <24>;
335 };
336
337 clkvcp3: clkvcp3 {
338 #clock-cells = <0>;
339 compatible = "ti,keystone,psc-clock";
340 clocks = <&chipclk13>;
341 clock-output-names = "vcp-3";
342 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
343 reg-names = "control", "domain";
344 domain-id = <24>;
345 };
346
347 clkvcp4: clkvcp4 {
348 #clock-cells = <0>;
349 compatible = "ti,keystone,psc-clock";
350 clocks = <&chipclk13>;
351 clock-output-names = "vcp-4";
352 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
353 reg-names = "control", "domain";
354 domain-id = <25>;
355 };
356
357 clkvcp5: clkvcp5 {
358 #clock-cells = <0>;
359 compatible = "ti,keystone,psc-clock";
360 clocks = <&chipclk13>;
361 clock-output-names = "vcp-5";
362 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
363 reg-names = "control", "domain";
364 domain-id = <25>;
365 };
366
367 clkvcp6: clkvcp6 {
368 #clock-cells = <0>;
369 compatible = "ti,keystone,psc-clock";
370 clocks = <&chipclk13>;
371 clock-output-names = "vcp-6";
372 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
373 reg-names = "control", "domain";
374 domain-id = <25>;
375 };
376
377 clkvcp7: clkvcp7 {
378 #clock-cells = <0>;
379 compatible = "ti,keystone,psc-clock";
380 clocks = <&chipclk13>;
381 clock-output-names = "vcp-7";
382 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
383 reg-names = "control", "domain";
384 domain-id = <25>;
385 };
386
387 clkbcp: clkbcp {
388 #clock-cells = <0>;
389 compatible = "ti,keystone,psc-clock";
390 clocks = <&chipclk13>;
391 clock-output-names = "bcp";
392 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
393 reg-names = "control", "domain";
394 domain-id = <26>;
395 };
396
397 clkdxb: clkdxb {
398 #clock-cells = <0>;
399 compatible = "ti,keystone,psc-clock";
400 clocks = <&chipclk13>;
401 clock-output-names = "dxb";
402 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
403 reg-names = "control", "domain";
404 domain-id = <27>;
405 };
406
407 clkhyperlink1: clkhyperlink1 {
408 #clock-cells = <0>;
409 compatible = "ti,keystone,psc-clock";
410 clocks = <&chipclk12>;
411 clock-output-names = "hyperlink-1";
412 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
413 reg-names = "control", "domain";
414 domain-id = <28>;
415 };
416
417 clkxge: clkxge {
418 #clock-cells = <0>;
419 compatible = "ti,keystone,psc-clock";
420 clocks = <&chipclk13>;
421 clock-output-names = "xge";
422 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
423 reg-names = "control", "domain";
424 domain-id = <29>;
425 };
426};
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
index eaefdfef65c3..c93d06f9f2a8 100644
--- a/arch/arm/boot/dts/k2hk-evm.dts
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2013 Texas Instruments, Inc. 2 * Copyright 2013-2014 Texas Instruments, Inc.
3 * 3 *
4 * Keystone 2 Kepler/Hawking EVM device tree 4 * Keystone 2 Kepler/Hawking EVM device tree
5 * 5 *
@@ -10,12 +10,14 @@
10/dts-v1/; 10/dts-v1/;
11 11
12#include "keystone.dtsi" 12#include "keystone.dtsi"
13#include "k2hk.dtsi"
13 14
14/ { 15/ {
15 compatible = "ti,keystone-evm"; 16 compatible = "ti,k2hk-evm","ti,keystone";
17 model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
16 18
17 soc { 19 soc {
18 clock { 20 clocks {
19 refclksys: refclksys { 21 refclksys: refclksys {
20 #clock-cells = <0>; 22 #clock-cells = <0>;
21 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
@@ -52,6 +54,29 @@
52 }; 54 };
53 }; 55 };
54 }; 56 };
57
58 leds {
59 compatible = "gpio-leds";
60 debug1_1 {
61 label = "keystone:green:debug1";
62 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
63 };
64
65 debug1_2 {
66 label = "keystone:red:debug1";
67 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
68 };
69
70 debug2 {
71 label = "keystone:blue:debug2";
72 gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
73 };
74
75 debug3 {
76 label = "keystone:blue:debug3";
77 gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
78 };
79 };
55}; 80};
56 81
57&usb_phy { 82&usb_phy {
@@ -61,3 +86,55 @@
61&usb { 86&usb {
62 status = "okay"; 87 status = "okay";
63}; 88};
89
90&aemif {
91 cs0 {
92 #address-cells = <2>;
93 #size-cells = <1>;
94 clock-ranges;
95 ranges;
96
97 ti,cs-chipselect = <0>;
98 /* all timings in nanoseconds */
99 ti,cs-min-turnaround-ns = <12>;
100 ti,cs-read-hold-ns = <6>;
101 ti,cs-read-strobe-ns = <23>;
102 ti,cs-read-setup-ns = <9>;
103 ti,cs-write-hold-ns = <8>;
104 ti,cs-write-strobe-ns = <23>;
105 ti,cs-write-setup-ns = <8>;
106
107 nand@0,0 {
108 compatible = "ti,keystone-nand","ti,davinci-nand";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 reg = <0 0 0x4000000
112 1 0 0x0000100>;
113
114 ti,davinci-chipselect = <0>;
115 ti,davinci-mask-ale = <0x2000>;
116 ti,davinci-mask-cle = <0x4000>;
117 ti,davinci-mask-chipsel = <0>;
118 nand-ecc-mode = "hw";
119 ti,davinci-ecc-bits = <4>;
120 nand-on-flash-bbt;
121
122 partition@0 {
123 label = "u-boot";
124 reg = <0x0 0x100000>;
125 read-only;
126 };
127
128 partition@100000 {
129 label = "params";
130 reg = <0x100000 0x80000>;
131 read-only;
132 };
133
134 partition@180000 {
135 label = "ubifs";
136 reg = <0x180000 0x1fe80000>;
137 };
138 };
139 };
140};
diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi
new file mode 100644
index 000000000000..c73899c73118
--- /dev/null
+++ b/arch/arm/boot/dts/k2hk.dtsi
@@ -0,0 +1,46 @@
1/*
2 * Copyright 2013-2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Kepler/Hawking soc specific device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/ {
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 interrupt-parent = <&gic>;
17
18 cpu@0 {
19 compatible = "arm,cortex-a15";
20 device_type = "cpu";
21 reg = <0>;
22 };
23
24 cpu@1 {
25 compatible = "arm,cortex-a15";
26 device_type = "cpu";
27 reg = <1>;
28 };
29
30 cpu@2 {
31 compatible = "arm,cortex-a15";
32 device_type = "cpu";
33 reg = <2>;
34 };
35
36 cpu@3 {
37 compatible = "arm,cortex-a15";
38 device_type = "cpu";
39 reg = <3>;
40 };
41 };
42
43 soc {
44 /include/ "k2hk-clocks.dtsi"
45 };
46};
diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi
new file mode 100644
index 000000000000..f584b80200f8
--- /dev/null
+++ b/arch/arm/boot/dts/k2l-clocks.dtsi
@@ -0,0 +1,267 @@
1/*
2 * Copyright 2013-2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 lamarr SoC clock nodes
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11clocks {
12 armpllclk: armpllclk@2620370 {
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
15 clocks = <&refclksys>;
16 clock-output-names = "arm-pll-clk";
17 reg = <0x02620370 4>;
18 reg-names = "control";
19 };
20
21 mainpllclk: mainpllclk@2310110 {
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
24 clocks = <&refclksys>;
25 reg = <0x02620350 4>, <0x02310110 4>;
26 reg-names = "control", "multiplier";
27 fixed-postdiv = <2>;
28 };
29
30 papllclk: papllclk@2620358 {
31 #clock-cells = <0>;
32 compatible = "ti,keystone,pll-clock";
33 clocks = <&refclksys>;
34 clock-output-names = "pa-pll-clk";
35 reg = <0x02620358 4>;
36 reg-names = "control";
37 };
38
39 ddr3apllclk: ddr3apllclk@2620360 {
40 #clock-cells = <0>;
41 compatible = "ti,keystone,pll-clock";
42 clocks = <&refclksys>;
43 clock-output-names = "ddr-3a-pll-clk";
44 reg = <0x02620360 4>;
45 reg-names = "control";
46 };
47
48 clkdfeiqnsys: clkdfeiqnsys {
49 #clock-cells = <0>;
50 compatible = "ti,keystone,psc-clock";
51 clocks = <&chipclk12>;
52 clock-output-names = "dfe";
53 reg-names = "control", "domain";
54 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
55 domain-id = <0>;
56 };
57
58 clkpcie1: clkpcie1 {
59 #clock-cells = <0>;
60 compatible = "ti,keystone,psc-clock";
61 clocks = <&chipclk12>;
62 clock-output-names = "pcie";
63 reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
64 reg-names = "control", "domain";
65 domain-id = <4>;
66 };
67
68 clkgem1: clkgem1 {
69 #clock-cells = <0>;
70 compatible = "ti,keystone,psc-clock";
71 clocks = <&chipclk1>;
72 clock-output-names = "gem1";
73 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
74 reg-names = "control", "domain";
75 domain-id = <9>;
76 };
77
78 clkgem2: clkgem2 {
79 #clock-cells = <0>;
80 compatible = "ti,keystone,psc-clock";
81 clocks = <&chipclk1>;
82 clock-output-names = "gem2";
83 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
84 reg-names = "control", "domain";
85 domain-id = <10>;
86 };
87
88 clkgem3: clkgem3 {
89 #clock-cells = <0>;
90 compatible = "ti,keystone,psc-clock";
91 clocks = <&chipclk1>;
92 clock-output-names = "gem3";
93 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
94 reg-names = "control", "domain";
95 domain-id = <11>;
96 };
97
98 clktac: clktac {
99 #clock-cells = <0>;
100 compatible = "ti,keystone,psc-clock";
101 clocks = <&chipclk13>;
102 clock-output-names = "tac";
103 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
104 reg-names = "control", "domain";
105 domain-id = <17>;
106 };
107
108 clkrac: clkrac {
109 #clock-cells = <0>;
110 compatible = "ti,keystone,psc-clock";
111 clocks = <&chipclk13>;
112 clock-output-names = "rac";
113 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
114 reg-names = "control", "domain";
115 domain-id = <17>;
116 };
117
118 clkdfepd0: clkdfepd0 {
119 #clock-cells = <0>;
120 compatible = "ti,keystone,psc-clock";
121 clocks = <&chipclk13>;
122 clock-output-names = "dfe-pd0";
123 reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
124 reg-names = "control", "domain";
125 domain-id = <18>;
126 };
127
128 clkfftc0: clkfftc0 {
129 #clock-cells = <0>;
130 compatible = "ti,keystone,psc-clock";
131 clocks = <&chipclk13>;
132 clock-output-names = "fftc-0";
133 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
134 reg-names = "control", "domain";
135 domain-id = <19>;
136 };
137
138 clkosr: clkosr {
139 #clock-cells = <0>;
140 compatible = "ti,keystone,psc-clock";
141 clocks = <&chipclk13>;
142 clock-output-names = "osr";
143 reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
144 reg-names = "control", "domain";
145 domain-id = <21>;
146 };
147
148 clktcp3d0: clktcp3d0 {
149 #clock-cells = <0>;
150 compatible = "ti,keystone,psc-clock";
151 clocks = <&chipclk13>;
152 clock-output-names = "tcp3d-0";
153 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
154 reg-names = "control", "domain";
155 domain-id = <22>;
156 };
157
158 clktcp3d1: clktcp3d1 {
159 #clock-cells = <0>;
160 compatible = "ti,keystone,psc-clock";
161 clocks = <&chipclk13>;
162 clock-output-names = "tcp3d-1";
163 reg = <0x02350094 0xb00>, <0x02350058 0x400>;
164 reg-names = "control", "domain";
165 domain-id = <23>;
166 };
167
168 clkvcp0: clkvcp0 {
169 #clock-cells = <0>;
170 compatible = "ti,keystone,psc-clock";
171 clocks = <&chipclk13>;
172 clock-output-names = "vcp-0";
173 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
174 reg-names = "control", "domain";
175 domain-id = <24>;
176 };
177
178 clkvcp1: clkvcp1 {
179 #clock-cells = <0>;
180 compatible = "ti,keystone,psc-clock";
181 clocks = <&chipclk13>;
182 clock-output-names = "vcp-1";
183 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
184 reg-names = "control", "domain";
185 domain-id = <24>;
186 };
187
188 clkvcp2: clkvcp2 {
189 #clock-cells = <0>;
190 compatible = "ti,keystone,psc-clock";
191 clocks = <&chipclk13>;
192 clock-output-names = "vcp-2";
193 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
194 reg-names = "control", "domain";
195 domain-id = <24>;
196 };
197
198 clkvcp3: clkvcp3 {
199 #clock-cells = <0>;
200 compatible = "ti,keystone,psc-clock";
201 clocks = <&chipclk13>;
202 clock-output-names = "vcp-3";
203 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
204 reg-names = "control", "domain";
205 domain-id = <24>;
206 };
207
208 clkbcp: clkbcp {
209 #clock-cells = <0>;
210 compatible = "ti,keystone,psc-clock";
211 clocks = <&chipclk13>;
212 clock-output-names = "bcp";
213 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
214 reg-names = "control", "domain";
215 domain-id = <26>;
216 };
217
218 clkdfepd1: clkdfepd1 {
219 #clock-cells = <0>;
220 compatible = "ti,keystone,psc-clock";
221 clocks = <&chipclk13>;
222 clock-output-names = "dfe-pd1";
223 reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
224 reg-names = "control", "domain";
225 domain-id = <27>;
226 };
227
228 clkfftc1: clkfftc1 {
229 #clock-cells = <0>;
230 compatible = "ti,keystone,psc-clock";
231 clocks = <&chipclk13>;
232 clock-output-names = "fftc-1";
233 reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
234 reg-names = "control", "domain";
235 domain-id = <28>;
236 };
237
238 clkiqnail: clkiqnail {
239 #clock-cells = <0>;
240 compatible = "ti,keystone,psc-clock";
241 clocks = <&chipclk13>;
242 clock-output-names = "iqn-ail";
243 reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
244 reg-names = "control", "domain";
245 domain-id = <29>;
246 };
247
248 clkuart2: clkuart2 {
249 #clock-cells = <0>;
250 compatible = "ti,keystone,psc-clock";
251 clocks = <&clkmodrst0>;
252 clock-output-names = "uart2";
253 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
254 reg-names = "control", "domain";
255 domain-id = <0>;
256 };
257
258 clkuart3: clkuart3 {
259 #clock-cells = <0>;
260 compatible = "ti,keystone,psc-clock";
261 clocks = <&clkmodrst0>;
262 clock-output-names = "uart3";
263 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
264 reg-names = "control", "domain";
265 domain-id = <0>;
266 };
267};
diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts
new file mode 100644
index 000000000000..50a70132ac9e
--- /dev/null
+++ b/arch/arm/boot/dts/k2l-evm.dts
@@ -0,0 +1,37 @@
1/*
2 * Copyright 2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Lamarr EVM device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10/dts-v1/;
11
12#include "keystone.dtsi"
13#include "k2l.dtsi"
14
15/ {
16 compatible = "ti,k2l-evm","ti,keystone";
17 model = "Texas Instruments Keystone 2 Lamarr EVM";
18
19 soc {
20 clocks {
21 refclksys: refclksys {
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
24 clock-frequency = <122880000>;
25 clock-output-names = "refclk-sys";
26 };
27 };
28 };
29};
30
31&usb_phy {
32 status = "okay";
33};
34
35&usb {
36 status = "okay";
37};
diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi
new file mode 100644
index 000000000000..1f7f479589e1
--- /dev/null
+++ b/arch/arm/boot/dts/k2l.dtsi
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Lamarr SoC specific device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/ {
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 interrupt-parent = <&gic>;
17
18 cpu@0 {
19 compatible = "arm,cortex-a15";
20 device_type = "cpu";
21 reg = <0>;
22 };
23
24 cpu@1 {
25 compatible = "arm,cortex-a15";
26 device_type = "cpu";
27 reg = <1>;
28 };
29 };
30
31 soc {
32
33 /include/ "k2l-clocks.dtsi"
34
35 uart2: serial@02348400 {
36 compatible = "ns16550a";
37 current-speed = <115200>;
38 reg-shift = <2>;
39 reg-io-width = <4>;
40 reg = <0x02348400 0x100>;
41 clocks = <&clkuart2>;
42 interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
43 };
44
45 uart3: serial@02348800 {
46 compatible = "ns16550a";
47 current-speed = <115200>;
48 reg-shift = <2>;
49 reg-io-width = <4>;
50 reg = <0x02348800 0x100>;
51 clocks = <&clkuart3>;
52 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
53 };
54 };
55};
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index ef58d1c24313..93f82c7010ab 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -13,51 +13,6 @@ clocks {
13 #size-cells = <1>; 13 #size-cells = <1>;
14 ranges; 14 ranges;
15 15
16 mainpllclk: mainpllclk@2310110 {
17 #clock-cells = <0>;
18 compatible = "ti,keystone,main-pll-clock";
19 clocks = <&refclksys>;
20 reg = <0x02620350 4>, <0x02310110 4>;
21 reg-names = "control", "multiplier";
22 fixed-postdiv = <2>;
23 };
24
25 papllclk: papllclk@2620358 {
26 #clock-cells = <0>;
27 compatible = "ti,keystone,pll-clock";
28 clocks = <&refclkpass>;
29 clock-output-names = "pa-pll-clk";
30 reg = <0x02620358 4>;
31 reg-names = "control";
32 };
33
34 ddr3apllclk: ddr3apllclk@2620360 {
35 #clock-cells = <0>;
36 compatible = "ti,keystone,pll-clock";
37 clocks = <&refclkddr3a>;
38 clock-output-names = "ddr-3a-pll-clk";
39 reg = <0x02620360 4>;
40 reg-names = "control";
41 };
42
43 ddr3bpllclk: ddr3bpllclk@2620368 {
44 #clock-cells = <0>;
45 compatible = "ti,keystone,pll-clock";
46 clocks = <&refclkddr3b>;
47 clock-output-names = "ddr-3b-pll-clk";
48 reg = <0x02620368 4>;
49 reg-names = "control";
50 };
51
52 armpllclk: armpllclk@2620370 {
53 #clock-cells = <0>;
54 compatible = "ti,keystone,pll-clock";
55 clocks = <&refclkarm>;
56 clock-output-names = "arm-pll-clk";
57 reg = <0x02620370 4>;
58 reg-names = "control";
59 };
60
61 mainmuxclk: mainmuxclk@2310108 { 16 mainmuxclk: mainmuxclk@2310108 {
62 #clock-cells = <0>; 17 #clock-cells = <0>;
63 compatible = "ti,keystone,pll-mux-clock"; 18 compatible = "ti,keystone,pll-mux-clock";
@@ -244,7 +199,7 @@ clocks {
244 clock-output-names = "debugss-trc"; 199 clock-output-names = "debugss-trc";
245 reg = <0x02350014 0xb00>, <0x02350000 0x400>; 200 reg = <0x02350014 0xb00>, <0x02350000 0x400>;
246 reg-names = "control", "domain"; 201 reg-names = "control", "domain";
247 domain-id = <0>; 202 domain-id = <1>;
248 }; 203 };
249 204
250 clktetbtrc: clktetbtrc { 205 clktetbtrc: clktetbtrc {
@@ -297,26 +252,6 @@ clocks {
297 domain-id = <3>; 252 domain-id = <3>;
298 }; 253 };
299 254
300 clksrio: clksrio {
301 #clock-cells = <0>;
302 compatible = "ti,keystone,psc-clock";
303 clocks = <&chipclk1rstiso13>;
304 clock-output-names = "srio";
305 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
306 reg-names = "control", "domain";
307 domain-id = <4>;
308 };
309
310 clkhyperlink0: clkhyperlink0 {
311 #clock-cells = <0>;
312 compatible = "ti,keystone,psc-clock";
313 clocks = <&chipclk12>;
314 clock-output-names = "hyperlink-0";
315 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
316 reg-names = "control", "domain";
317 domain-id = <5>;
318 };
319
320 clksr: clksr { 255 clksr: clksr {
321 #clock-cells = <0>; 256 #clock-cells = <0>;
322 compatible = "ti,keystone,psc-clock"; 257 compatible = "ti,keystone,psc-clock";
@@ -327,16 +262,6 @@ clocks {
327 domain-id = <6>; 262 domain-id = <6>;
328 }; 263 };
329 264
330 clkmsmcsram: clkmsmcsram {
331 #clock-cells = <0>;
332 compatible = "ti,keystone,psc-clock";
333 clocks = <&chipclk1>;
334 clock-output-names = "msmcsram";
335 reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
336 reg-names = "control", "domain";
337 domain-id = <7>;
338 };
339
340 clkgem0: clkgem0 { 265 clkgem0: clkgem0 {
341 #clock-cells = <0>; 266 #clock-cells = <0>;
342 compatible = "ti,keystone,psc-clock"; 267 compatible = "ti,keystone,psc-clock";
@@ -347,76 +272,6 @@ clocks {
347 domain-id = <8>; 272 domain-id = <8>;
348 }; 273 };
349 274
350 clkgem1: clkgem1 {
351 #clock-cells = <0>;
352 compatible = "ti,keystone,psc-clock";
353 clocks = <&chipclk1>;
354 clock-output-names = "gem1";
355 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
356 reg-names = "control", "domain";
357 domain-id = <9>;
358 };
359
360 clkgem2: clkgem2 {
361 #clock-cells = <0>;
362 compatible = "ti,keystone,psc-clock";
363 clocks = <&chipclk1>;
364 clock-output-names = "gem2";
365 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
366 reg-names = "control", "domain";
367 domain-id = <10>;
368 };
369
370 clkgem3: clkgem3 {
371 #clock-cells = <0>;
372 compatible = "ti,keystone,psc-clock";
373 clocks = <&chipclk1>;
374 clock-output-names = "gem3";
375 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
376 reg-names = "control", "domain";
377 domain-id = <11>;
378 };
379
380 clkgem4: clkgem4 {
381 #clock-cells = <0>;
382 compatible = "ti,keystone,psc-clock";
383 clocks = <&chipclk1>;
384 clock-output-names = "gem4";
385 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
386 reg-names = "control", "domain";
387 domain-id = <12>;
388 };
389
390 clkgem5: clkgem5 {
391 #clock-cells = <0>;
392 compatible = "ti,keystone,psc-clock";
393 clocks = <&chipclk1>;
394 clock-output-names = "gem5";
395 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
396 reg-names = "control", "domain";
397 domain-id = <13>;
398 };
399
400 clkgem6: clkgem6 {
401 #clock-cells = <0>;
402 compatible = "ti,keystone,psc-clock";
403 clocks = <&chipclk1>;
404 clock-output-names = "gem6";
405 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
406 reg-names = "control", "domain";
407 domain-id = <14>;
408 };
409
410 clkgem7: clkgem7 {
411 #clock-cells = <0>;
412 compatible = "ti,keystone,psc-clock";
413 clocks = <&chipclk1>;
414 clock-output-names = "gem7";
415 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
416 reg-names = "control", "domain";
417 domain-id = <15>;
418 };
419
420 clkddr30: clkddr30 { 275 clkddr30: clkddr30 {
421 #clock-cells = <0>; 276 #clock-cells = <0>;
422 compatible = "ti,keystone,psc-clock"; 277 compatible = "ti,keystone,psc-clock";
@@ -427,276 +282,6 @@ clocks {
427 domain-id = <16>; 282 domain-id = <16>;
428 }; 283 };
429 284
430 clkddr31: clkddr31 {
431 #clock-cells = <0>;
432 compatible = "ti,keystone,psc-clock";
433 clocks = <&chipclk13>;
434 clock-output-names = "ddr3-1";
435 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
436 reg-names = "control", "domain";
437 domain-id = <16>;
438 };
439
440 clktac: clktac {
441 #clock-cells = <0>;
442 compatible = "ti,keystone,psc-clock";
443 clocks = <&chipclk13>;
444 clock-output-names = "tac";
445 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
446 reg-names = "control", "domain";
447 domain-id = <17>;
448 };
449
450 clkrac01: clktac01 {
451 #clock-cells = <0>;
452 compatible = "ti,keystone,psc-clock";
453 clocks = <&chipclk13>;
454 clock-output-names = "rac-01";
455 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
456 reg-names = "control", "domain";
457 domain-id = <17>;
458 };
459
460 clkrac23: clktac23 {
461 #clock-cells = <0>;
462 compatible = "ti,keystone,psc-clock";
463 clocks = <&chipclk13>;
464 clock-output-names = "rac-23";
465 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
466 reg-names = "control", "domain";
467 domain-id = <18>;
468 };
469
470 clkfftc0: clkfftc0 {
471 #clock-cells = <0>;
472 compatible = "ti,keystone,psc-clock";
473 clocks = <&chipclk13>;
474 clock-output-names = "fftc-0";
475 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
476 reg-names = "control", "domain";
477 domain-id = <19>;
478 };
479
480 clkfftc1: clkfftc1 {
481 #clock-cells = <0>;
482 compatible = "ti,keystone,psc-clock";
483 clocks = <&chipclk13>;
484 clock-output-names = "fftc-1";
485 reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
486 reg-names = "control", "domain";
487 domain-id = <19>;
488 };
489
490 clkfftc2: clkfftc2 {
491 #clock-cells = <0>;
492 compatible = "ti,keystone,psc-clock";
493 clocks = <&chipclk13>;
494 clock-output-names = "fftc-2";
495 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
496 reg-names = "control", "domain";
497 domain-id = <20>;
498 };
499
500 clkfftc3: clkfftc3 {
501 #clock-cells = <0>;
502 compatible = "ti,keystone,psc-clock";
503 clocks = <&chipclk13>;
504 clock-output-names = "fftc-3";
505 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
506 reg-names = "control", "domain";
507 domain-id = <20>;
508 };
509
510 clkfftc4: clkfftc4 {
511 #clock-cells = <0>;
512 compatible = "ti,keystone,psc-clock";
513 clocks = <&chipclk13>;
514 clock-output-names = "fftc-4";
515 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
516 reg-names = "control", "domain";
517 domain-id = <20>;
518 };
519
520 clkfftc5: clkfftc5 {
521 #clock-cells = <0>;
522 compatible = "ti,keystone,psc-clock";
523 clocks = <&chipclk13>;
524 clock-output-names = "fftc-5";
525 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
526 reg-names = "control", "domain";
527 domain-id = <20>;
528 };
529
530 clkaif: clkaif {
531 #clock-cells = <0>;
532 compatible = "ti,keystone,psc-clock";
533 clocks = <&chipclk13>;
534 clock-output-names = "aif";
535 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
536 reg-names = "control", "domain";
537 domain-id = <21>;
538 };
539
540 clktcp3d0: clktcp3d0 {
541 #clock-cells = <0>;
542 compatible = "ti,keystone,psc-clock";
543 clocks = <&chipclk13>;
544 clock-output-names = "tcp3d-0";
545 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
546 reg-names = "control", "domain";
547 domain-id = <22>;
548 };
549
550 clktcp3d1: clktcp3d1 {
551 #clock-cells = <0>;
552 compatible = "ti,keystone,psc-clock";
553 clocks = <&chipclk13>;
554 clock-output-names = "tcp3d-1";
555 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
556 reg-names = "control", "domain";
557 domain-id = <22>;
558 };
559
560 clktcp3d2: clktcp3d2 {
561 #clock-cells = <0>;
562 compatible = "ti,keystone,psc-clock";
563 clocks = <&chipclk13>;
564 clock-output-names = "tcp3d-2";
565 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
566 reg-names = "control", "domain";
567 domain-id = <23>;
568 };
569
570 clktcp3d3: clktcp3d3 {
571 #clock-cells = <0>;
572 compatible = "ti,keystone,psc-clock";
573 clocks = <&chipclk13>;
574 clock-output-names = "tcp3d-3";
575 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
576 reg-names = "control", "domain";
577 domain-id = <23>;
578 };
579
580 clkvcp0: clkvcp0 {
581 #clock-cells = <0>;
582 compatible = "ti,keystone,psc-clock";
583 clocks = <&chipclk13>;
584 clock-output-names = "vcp-0";
585 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
586 reg-names = "control", "domain";
587 domain-id = <24>;
588 };
589
590 clkvcp1: clkvcp1 {
591 #clock-cells = <0>;
592 compatible = "ti,keystone,psc-clock";
593 clocks = <&chipclk13>;
594 clock-output-names = "vcp-1";
595 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
596 reg-names = "control", "domain";
597 domain-id = <24>;
598 };
599
600 clkvcp2: clkvcp2 {
601 #clock-cells = <0>;
602 compatible = "ti,keystone,psc-clock";
603 clocks = <&chipclk13>;
604 clock-output-names = "vcp-2";
605 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
606 reg-names = "control", "domain";
607 domain-id = <24>;
608 };
609
610 clkvcp3: clkvcp3 {
611 #clock-cells = <0>;
612 compatible = "ti,keystone,psc-clock";
613 clocks = <&chipclk13>;
614 clock-output-names = "vcp-3";
615 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
616 reg-names = "control", "domain";
617 domain-id = <24>;
618 };
619
620 clkvcp4: clkvcp4 {
621 #clock-cells = <0>;
622 compatible = "ti,keystone,psc-clock";
623 clocks = <&chipclk13>;
624 clock-output-names = "vcp-4";
625 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
626 reg-names = "control", "domain";
627 domain-id = <25>;
628 };
629
630 clkvcp5: clkvcp5 {
631 #clock-cells = <0>;
632 compatible = "ti,keystone,psc-clock";
633 clocks = <&chipclk13>;
634 clock-output-names = "vcp-5";
635 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
636 reg-names = "control", "domain";
637 domain-id = <25>;
638 };
639
640 clkvcp6: clkvcp6 {
641 #clock-cells = <0>;
642 compatible = "ti,keystone,psc-clock";
643 clocks = <&chipclk13>;
644 clock-output-names = "vcp-6";
645 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
646 reg-names = "control", "domain";
647 domain-id = <25>;
648 };
649
650 clkvcp7: clkvcp7 {
651 #clock-cells = <0>;
652 compatible = "ti,keystone,psc-clock";
653 clocks = <&chipclk13>;
654 clock-output-names = "vcp-7";
655 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
656 reg-names = "control", "domain";
657 domain-id = <25>;
658 };
659
660 clkbcp: clkbcp {
661 #clock-cells = <0>;
662 compatible = "ti,keystone,psc-clock";
663 clocks = <&chipclk13>;
664 clock-output-names = "bcp";
665 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
666 reg-names = "control", "domain";
667 domain-id = <26>;
668 };
669
670 clkdxb: clkdxb {
671 #clock-cells = <0>;
672 compatible = "ti,keystone,psc-clock";
673 clocks = <&chipclk13>;
674 clock-output-names = "dxb";
675 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
676 reg-names = "control", "domain";
677 domain-id = <27>;
678 };
679
680 clkhyperlink1: clkhyperlink1 {
681 #clock-cells = <0>;
682 compatible = "ti,keystone,psc-clock";
683 clocks = <&chipclk12>;
684 clock-output-names = "hyperlink-1";
685 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
686 reg-names = "control", "domain";
687 domain-id = <28>;
688 };
689
690 clkxge: clkxge {
691 #clock-cells = <0>;
692 compatible = "ti,keystone,psc-clock";
693 clocks = <&chipclk13>;
694 clock-output-names = "xge";
695 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
696 reg-names = "control", "domain";
697 domain-id = <29>;
698 };
699
700 clkwdtimer0: clkwdtimer0 { 285 clkwdtimer0: clkwdtimer0 {
701 #clock-cells = <0>; 286 #clock-cells = <0>;
702 compatible = "ti,keystone,psc-clock"; 287 compatible = "ti,keystone,psc-clock";
@@ -737,6 +322,16 @@ clocks {
737 domain-id = <0>; 322 domain-id = <0>;
738 }; 323 };
739 324
325 clktimer15: clktimer15 {
326 #clock-cells = <0>;
327 compatible = "ti,keystone,psc-clock";
328 clocks = <&clkmodrst0>;
329 clock-output-names = "timer15";
330 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
331 reg-names = "control", "domain";
332 domain-id = <0>;
333 };
334
740 clkuart0: clkuart0 { 335 clkuart0: clkuart0 {
741 #clock-cells = <0>; 336 #clock-cells = <0>;
742 compatible = "ti,keystone,psc-clock"; 337 compatible = "ti,keystone,psc-clock";
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index b4202907a27b..90823eb90c1b 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -7,6 +7,7 @@
7 */ 7 */
8 8
9#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/gpio/gpio.h>
10 11
11#include "skeleton.dtsi" 12#include "skeleton.dtsi"
12 13
@@ -24,37 +25,6 @@
24 reg = <0x00000000 0x80000000 0x00000000 0x40000000>; 25 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
25 }; 26 };
26 27
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 interrupt-parent = <&gic>;
32
33 cpu@0 {
34 compatible = "arm,cortex-a15";
35 device_type = "cpu";
36 reg = <0>;
37 };
38
39 cpu@1 {
40 compatible = "arm,cortex-a15";
41 device_type = "cpu";
42 reg = <1>;
43 };
44
45 cpu@2 {
46 compatible = "arm,cortex-a15";
47 device_type = "cpu";
48 reg = <2>;
49 };
50
51 cpu@3 {
52 compatible = "arm,cortex-a15";
53 device_type = "cpu";
54 reg = <3>;
55 };
56 };
57
58 gic: interrupt-controller { 28 gic: interrupt-controller {
59 compatible = "arm,cortex-a15-gic"; 29 compatible = "arm,cortex-a15-gic";
60 #interrupt-cells = <3>; 30 #interrupt-cells = <3>;
@@ -208,5 +178,75 @@
208 usb-phy = <&usb_phy>, <&usb_phy>; 178 usb-phy = <&usb_phy>, <&usb_phy>;
209 }; 179 };
210 }; 180 };
181
182 wdt: wdt@022f0080 {
183 compatible = "ti,keystone-wdt","ti,davinci-wdt";
184 reg = <0x022f0080 0x80>;
185 clocks = <&clkwdtimer0>;
186 };
187
188 clock_event: timer@22f0000 {
189 compatible = "ti,keystone-timer";
190 reg = <0x022f0000 0x80>;
191 interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
192 clocks = <&clktimer15>;
193 };
194
195 gpio0: gpio@260bf00 {
196 compatible = "ti,keystone-gpio";
197 reg = <0x0260bf00 0x100>;
198 gpio-controller;
199 #gpio-cells = <2>;
200 /* HW Interrupts mapped to GPIO pins */
201 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
202 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
203 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
204 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
205 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
206 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
207 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
208 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
209 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
210 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
211 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
212 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
213 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
214 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
215 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
216 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
217 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
218 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
219 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
220 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
221 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
222 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
223 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
224 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
225 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
226 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
227 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
228 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
229 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
230 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
231 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
232 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
233 clocks = <&clkgpio>;
234 clock-names = "gpio";
235 ti,ngpio = <32>;
236 ti,davinci-gpio-unbanked = <32>;
237 };
238
239 aemif: aemif@21000A00 {
240 compatible = "ti,keystone-aemif", "ti,davinci-aemif";
241 #address-cells = <2>;
242 #size-cells = <1>;
243 clocks = <&clkaemif>;
244 clock-names = "aemif";
245 clock-ranges;
246
247 reg = <0x21000A00 0x00000100>;
248 ranges = <0 0 0x30000000 0x10000000
249 1 0 0x21000A00 0x00000100>;
250 };
211 }; 251 };
212}; 252};
diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts
new file mode 100644
index 000000000000..40791053106b
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-b3.dts
@@ -0,0 +1,204 @@
1/*
2 * Device Tree file for Excito Bubba B3
3 *
4 * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Note: This requires a new'ish version of u-boot, which disables the
12 * L2 cache. If your B3 silently fails to boot, u-boot is probably too
13 * old. Either upgrade, or consider the following email:
14 *
15 * http://lists.debian.org/debian-arm/2012/08/msg00128.html
16 */
17
18/dts-v1/;
19
20#include "kirkwood.dtsi"
21#include "kirkwood-6281.dtsi"
22
23/ {
24 model = "Excito B3";
25 compatible = "excito,b3", "marvell,kirkwood-88f6281", "marvell,kirkwood";
26 memory { /* 512 MB */
27 device_type = "memory";
28 reg = <0x00000000 0x20000000>;
29 };
30
31 chosen {
32 bootargs = "console=ttyS0,115200n8 earlyprintk";
33 };
34
35 mbus {
36 pcie-controller {
37 status = "okay";
38
39 /* Wifi model has Atheros chipset on pcie port */
40 pcie@1,0 {
41 status = "okay";
42 };
43 };
44 };
45
46 ocp@f1000000 {
47 pinctrl: pinctrl@10000 {
48 pmx_button_power: pmx-button-power {
49 marvell,pins = "mpp39";
50 marvell,function = "gpio";
51 };
52 pmx_led_green: pmx-led-green {
53 marvell,pins = "mpp38";
54 marvell,function = "gpio";
55 };
56 pmx_led_red: pmx-led-red {
57 marvell,pins = "mpp41";
58 marvell,function = "gpio";
59 };
60 pmx_led_blue: pmx-led-blue {
61 marvell,pins = "mpp42";
62 marvell,function = "gpio";
63 };
64 pmx_beeper: pmx-beeper {
65 marvell,pins = "mpp40";
66 marvell,function = "gpio";
67 };
68 };
69
70 spi@10600 {
71 status = "okay";
72 pinctrl-0 = <&pmx_spi>;
73 pinctrl-names = "default";
74
75 m25p16@0 {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "m25p16";
79 reg = <0>;
80 spi-max-frequency = <40000000>;
81 mode = <0>;
82
83 partition@0 {
84 reg = <0x0 0xc0000>;
85 label = "u-boot";
86 };
87
88 partition@c0000 {
89 reg = <0xc0000 0x20000>;
90 label = "u-boot env";
91 };
92
93 partition@e0000 {
94 reg = <0xe0000 0x120000>;
95 label = "data";
96 };
97 };
98 };
99
100 i2c@11000 {
101 status = "okay";
102 /*
103 * There is something on the bus at address 0x64.
104 * Not yet identified what it is, maybe the eeprom
105 * for the Atheros WiFi chip?
106 */
107 };
108
109
110 serial@12000 {
111 /* Internal on test pins, 3.3v TTL
112 * UART0_RX = Testpoint 65
113 * UART0_TX = Testpoint 66
114 * See the Excito Wiki for more details.
115 */
116 pinctrl-0 = <&pmx_uart0>;
117 pinctrl-names = "default";
118 status = "okay";
119 };
120
121 sata@80000 {
122 /* One internal, the second as eSATA */
123 status = "okay";
124 nr-ports = <2>;
125 };
126 };
127
128 gpio-leds {
129 /*
130 * There is one LED "port" on the front and the colours
131 * mix together giving some interesting combinations.
132 */
133 compatible = "gpio-leds";
134 pinctrl-0 = < &pmx_led_green &pmx_led_red
135 &pmx_led_blue >;
136 pinctrl-names = "default";
137
138 programming_led {
139 label = "bubba3:green:programming";
140 gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
141 default-state = "off";
142 };
143
144 error_led {
145 label = "bubba3:red:error";
146 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
147 };
148
149 active_led {
150 label = "bubba3:blue:active";
151 gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
152 };
153 };
154
155 gpio-keys {
156 compatible = "gpio-keys";
157 pinctrl-0 = <&pmx_button_power>;
158 pinctrl-names = "default";
159
160 power-button {
161 /* On the back */
162 label = "Power Button";
163 linux,code = <KEY_POWER>;
164 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
165 };
166 };
167
168 beeper: beeper {
169 /* 4KHz Piezoelectric buzzer */
170 compatible = "gpio-beeper";
171 pinctrl-0 = <&pmx_beeper>;
172 pinctrl-names = "default";
173 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
174 };
175};
176
177&mdio {
178 status = "okay";
179
180 ethphy0: ethernet-phy@8 {
181 device_type = "ethernet-phy";
182 reg = <8>;
183 };
184
185 ethphy1: ethernet-phy@24 {
186 device_type = "ethernet-phy";
187 reg = <24>;
188 };
189};
190
191&eth0 {
192 status = "okay";
193 ethernet0-port@0 {
194 phy-handle = <&ethphy0>;
195 };
196};
197
198&eth1 {
199 status = "okay";
200 ethernet1-port@0 {
201 phy-handle = <&ethphy1>;
202 };
203};
204
diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts
new file mode 100644
index 000000000000..772092c94ca3
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds109.dts
@@ -0,0 +1,41 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6281.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS109, DS110, DS110jv20";
18 compatible = "synology,ds109", "synology,ds110jv20",
19 "synology,ds110", "marvell,kirkwood";
20
21 memory {
22 device_type = "memory";
23 reg = <0x00000000 0x8000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyS0,115200n8";
28 };
29
30 gpio-fan-150-32-35 {
31 status = "okay";
32 };
33
34 gpio-leds-hdd-21-1 {
35 status = "okay";
36 };
37};
38
39&rs5c372 {
40 status = "okay";
41};
diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
new file mode 100644
index 000000000000..aabafbe0da4c
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
@@ -0,0 +1,41 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6281.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS110j v10 and v30";
18 compatible = "synology,ds110jv10", "synology,ds110jv30",
19 "marvell,kirkwood";
20
21 memory {
22 device_type = "memory";
23 reg = <0x00000000 0x8000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyS0,115200n8";
28 };
29
30 gpio-fan-150-32-35 {
31 status = "okay";
32 };
33
34 gpio-leds-hdd-21-1 {
35 status = "okay";
36 };
37};
38
39&s35390a {
40 status = "okay";
41};
diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts
new file mode 100644
index 000000000000..16ec7fbab573
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds111.dts
@@ -0,0 +1,44 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6282.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS111";
18 compatible = "synology,ds111", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-100-15-35-1 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-21-1 {
34 status = "okay";
35 };
36};
37
38&s35390a {
39 status = "okay";
40};
41
42&pcie2 {
43 status = "okay";
44};
diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts
new file mode 100644
index 000000000000..cff1b2388765
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds112.dts
@@ -0,0 +1,48 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6282.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS111";
18 compatible = "synology,ds111", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-100-15-35-1 {
30 status = "okay";
31 };
32
33 gpio-leds-21-2 {
34 status = "okay";
35 };
36
37 regulators-hdd-30 {
38 status = "okay";
39 };
40};
41
42&s35390a {
43 status = "okay";
44};
45
46&pcie2 {
47 status = "okay";
48};
diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts
new file mode 100644
index 000000000000..330411993d38
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds209.dts
@@ -0,0 +1,44 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6281.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS209";
18 compatible = "synology,ds209", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-150-32-35 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-21-2 {
34 status = "okay";
35 };
36
37 regulators-hdd-31 {
38 status = "okay";
39 };
40};
41
42&rs5c372 {
43 status = "okay";
44};
diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts
new file mode 100644
index 000000000000..6052eaa37d4f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds210.dts
@@ -0,0 +1,46 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6281.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS210 v10, v20, v30, DS211j";
18 compatible = "synology,ds210jv10", "synology,ds210jv20",
19 "synology,ds210jv30", "synology,ds211j",
20 "marvell,kirkwood";
21
22 memory {
23 device_type = "memory";
24 reg = <0x00000000 0x8000000>;
25 };
26
27 chosen {
28 bootargs = "console=ttyS0,115200n8";
29 };
30
31 gpio-fan-150-32-35 {
32 status = "okay";
33 };
34
35 gpio-leds-hdd-21-2 {
36 status = "okay";
37 };
38
39 regulators-hdd-31 {
40 status = "okay";
41 };
42};
43
44&s35390a {
45 status = "okay";
46};
diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts
new file mode 100644
index 000000000000..7f76cd30e84e
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds212.dts
@@ -0,0 +1,47 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6282.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS212, DS212p v10, v20, DS213air v10, DS213 v10";
18 compatible = "synology,ds212", "synology,ds212pv10",
19 "synology,ds212pv10", "synology,ds212pv20",
20 "synology,ds213airv10", "synology,ds213v10",
21 "marvell,kirkwood";
22
23 memory {
24 device_type = "memory";
25 reg = <0x00000000 0x8000000>;
26 };
27
28 chosen {
29 bootargs = "console=ttyS0,115200n8";
30 };
31
32 gpio-fan-100-15-35-1 {
33 status = "okay";
34 };
35
36 gpio-leds-hdd-21-2 {
37 status = "okay";
38 };
39};
40
41&s35390a {
42 status = "okay";
43};
44
45&pcie2 {
46 status = "okay";
47};
diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts
new file mode 100644
index 000000000000..1f83a00f1f74
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds212j.dts
@@ -0,0 +1,41 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6281.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS212j v10, v20";
18 compatible = "synology,ds212jv10", "synology,ds212jv20",
19 "marvell,kirkwood";
20
21 memory {
22 device_type = "memory";
23 reg = <0x00000000 0x8000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyS0,115200n8";
28 };
29
30 gpio-fan-100-32-35 {
31 status = "okay";
32 };
33
34 gpio-leds-hdd-21-2 {
35 status = "okay";
36 };
37};
38
39&s35390a {
40 status = "okay";
41};
diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts
new file mode 100644
index 000000000000..0a573add44a2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds409.dts
@@ -0,0 +1,48 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6281.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS409, DS410j";
18 compatible = "synology,ds409", "synology,ds410j", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-150-15-18 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-36 {
34 status = "okay";
35 };
36
37 gpio-leds-alarm-12 {
38 status = "okay";
39 };
40};
41
42&eth1 {
43 status = "okay";
44};
45
46&rs5c372 {
47 status = "okay";
48};
diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts
new file mode 100644
index 000000000000..1848a6245fd3
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts
@@ -0,0 +1,40 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6281.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology 409slim";
18 compatible = "synology,ds409slim", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-150-32-35 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-20 {
34 status = "okay";
35 };
36};
37
38&rs5c372 {
39 status = "okay";
40};
diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts
new file mode 100644
index 000000000000..a1737b4311c6
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds411.dts
@@ -0,0 +1,52 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6282.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS411, DS413jv10";
18 compatible = "synology,ds411", "synology,ds413jv10", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-100-15-35-1 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-36 {
34 status = "okay";
35 };
36
37 regulators-hdd-34 {
38 status = "okay";
39 };
40};
41
42&eth1 {
43 status = "okay";
44};
45
46&s35390a {
47 status = "okay";
48};
49
50&pcie2 {
51 status = "okay";
52};
diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts
new file mode 100644
index 000000000000..0cde914eceae
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds411j.dts
@@ -0,0 +1,48 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6281.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS411j";
18 compatible = "synology,ds411j", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-150-15-18 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-36 {
34 status = "okay";
35 };
36
37 gpio-leds-alarm-12 {
38 status = "okay";
39 };
40};
41
42&eth1 {
43 status = "okay";
44};
45
46&s35390a {
47 status = "okay";
48};
diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts
new file mode 100644
index 000000000000..aef0cadc2c78
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts
@@ -0,0 +1,48 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6282.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology DS411slim";
18 compatible = "synology,ds411slim", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-100-15-35-1 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-36 {
34 status = "okay";
35 };
36};
37
38&eth1 {
39 status = "okay";
40};
41
42&s35390a {
43 status = "okay";
44};
45
46&pcie2 {
47 status = "okay";
48};
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index dc86429756d7..2cb0dc529165 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -122,4 +122,66 @@
122 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 122 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
123 }; 123 };
124 }; 124 };
125
126 dsa@0 {
127 compatible = "marvell,dsa";
128 #address-cells = <2>;
129 #size-cells = <0>;
130
131 dsa,ethernet = <&eth0>;
132 dsa,mii-bus = <&ethphy0>;
133
134 switch@0 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 reg = <0 0>; /* MDIO address 0, switch 0 in tree */
138
139 port@0 {
140 reg = <0>;
141 label = "lan1";
142 };
143
144 port@1 {
145 reg = <1>;
146 label = "lan2";
147 };
148
149 port@2 {
150 reg = <2>;
151 label = "lan3";
152 };
153
154 port@3 {
155 reg = <3>;
156 label = "lan4";
157 };
158
159 port@4 {
160 reg = <4>;
161 label = "wan";
162 };
163
164 port@5 {
165 reg = <5>;
166 label = "cpu";
167 };
168 };
169 };
170};
171
172&mdio {
173 status = "okay";
174
175 ethphy0: ethernet-phy@ff {
176 reg = <0xff>; /* No phy attached */
177 speed = <1000>;
178 duplex = <1>;
179 };
180};
181
182&eth0 {
183 status = "okay";
184 ethernet0-port@0 {
185 phy-handle = <&ethphy0>;
186 };
125}; 187};
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
new file mode 100644
index 000000000000..e9dd85049297
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
@@ -0,0 +1,112 @@
1/*
2 * Marvell RD88F6192 Board descrition
3 *
4 * Andrew Lunn <andrew@lunn.ch>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * This file contains the definitions that are common between the three
11 * variants of the Marvell Kirkwood Development Board.
12 */
13/dts-v1/;
14
15#include "kirkwood.dtsi"
16#include "kirkwood-6192.dtsi"
17
18/ {
19 model = "Marvell RD88F6192 reference design";
20 compatible = "marvell,rd88f6192", "marvell,kirkwood-88f6192", "marvell,kirkwood";
21
22 memory {
23 device_type = "memory";
24 reg = <0x00000000 0x20000000>;
25 };
26
27 chosen {
28 bootargs = "console=ttyS0,115200n8";
29 };
30
31 mbus {
32 pcie-controller {
33 status = "okay";
34
35 pcie@1,0 {
36 status = "okay";
37 };
38 };
39 };
40
41 ocp@f1000000 {
42 pinctrl: pinctrl@10000 {
43 pinctrl-0 = <&pmx_usb_power>;
44 pinctrl-names = "default";
45
46 pmx_usb_power: pmx-usb-power {
47 marvell,pins = "mpp10";
48 marvell,function = "gpo";
49 };
50 };
51
52 serial@12000 {
53 status = "okay";
54
55 };
56
57 spi@10600 {
58 status = "okay";
59 pinctrl-0 = <&pmx_spi>;
60 pinctrl-names = "default";
61
62 m25p128@0 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "st,m25p128";
66 reg = <0>;
67 spi-max-frequency = <20000000>;
68 mode = <0>;
69 };
70 };
71
72 sata@80000 {
73 status = "okay";
74 nr-ports = <2>;
75 };
76 };
77
78 regulators {
79 compatible = "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <0>;
82 pinctrl-0 = <&pmx_usb_power>;
83 pinctrl-names = "default";
84
85 usb_power: regulator@0 {
86 compatible = "regulator-fixed";
87 reg = <0>;
88 regulator-name = "USB VBUS";
89 regulator-min-microvolt = <5000000>;
90 regulator-max-microvolt = <5000000>;
91 enable-active-high;
92 regulator-always-on;
93 regulator-boot-on;
94 gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
95 };
96 };
97};
98
99&mdio {
100 status = "okay";
101
102 ethphy0: ethernet-phy@8 {
103 reg = <8>;
104 };
105};
106
107&eth0 {
108 status = "okay";
109 ethernet0-port@0 {
110 phy-handle = <&ethphy0>;
111 };
112}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts
new file mode 100644
index 000000000000..a803bbb70bc8
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts
@@ -0,0 +1,26 @@
1/*
2 * Marvell RD88F6181 A0 Board descrition
3 *
4 * Andrew Lunn <andrew@lunn.ch>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * This file contains the definitions for the board with the A0 variant of
11 * the SoC. The ethernet switch does not have a "wan" port.
12 */
13
14/dts-v1/;
15#include "kirkwood-rd88f6281.dtsi"
16
17/ {
18 model = "Marvell RD88f6281 Reference design, with A0 SoC";
19 compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
20
21 dsa@0 {
22 switch@0 {
23 reg = <10 0>; /* MDIO address 10, switch 0 in tree */
24 };
25 };
26}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts
new file mode 100644
index 000000000000..baeebbf1d8c7
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts
@@ -0,0 +1,31 @@
1/*
2 * Marvell RD88F6181 A1 Board descrition
3 *
4 * Andrew Lunn <andrew@lunn.ch>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * This file contains the definitions for the board with the A1 variant of
11 * the SoC. The ethernet switch has a "wan" port.
12 */
13
14/dts-v1/;
15
16#include "kirkwood-rd88f6281.dtsi"
17
18/ {
19 model = "Marvell RD88f6281 Reference design, with A1 SoC";
20 compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
21
22 dsa@0 {
23 switch@0 {
24 reg = <0 0>; /* MDIO address 0, switch 0 in tree */
25 port@4 {
26 reg = <4>;
27 label = "wan";
28 };
29 };
30 };
31}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
new file mode 100644
index 000000000000..d6368c39102e
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
@@ -0,0 +1,152 @@
1/*
2 * Marvell RD88F6181 Common Board descrition
3 *
4 * Andrew Lunn <andrew@lunn.ch>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * This file contains the definitions that are common between the two
11 * variants of the Marvell Kirkwood Development Board.
12 */
13
14#include "kirkwood.dtsi"
15#include "kirkwood-6281.dtsi"
16
17/ {
18 memory {
19 device_type = "memory";
20 reg = <0x00000000 0x20000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttyS0,115200n8";
25 };
26
27 mbus {
28 pcie-controller {
29 status = "okay";
30
31 pcie@1,0 {
32 status = "okay";
33 };
34 };
35 };
36
37 ocp@f1000000 {
38 pinctrl: pinctrl@10000 {
39 pinctrl-0 = <&pmx_sdio_cd>;
40 pinctrl-names = "default";
41
42 pmx_sdio_cd: pmx-sdio-cd {
43 marvell,pins = "mpp28";
44 marvell,function = "gpio";
45 };
46 };
47
48 serial@12000 {
49 status = "okay";
50
51 };
52
53 sata@80000 {
54 status = "okay";
55 nr-ports = <2>;
56 };
57 mvsdio@90000 {
58 pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
59 pinctrl-names = "default";
60 status = "okay";
61 cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
62 /* No WP GPIO */
63 };
64 };
65
66 dsa@0 {
67 compatible = "marvell,dsa";
68 #address-cells = <2>;
69 #size-cells = <0>;
70
71 dsa,ethernet = <&eth0>;
72 dsa,mii-bus = <&ethphy1>;
73
74 switch@0 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 port@0 {
79 reg = <0>;
80 label = "lan1";
81 };
82
83 port@1 {
84 reg = <1>;
85 label = "lan2";
86 };
87
88 port@2 {
89 reg = <2>;
90 label = "lan3";
91 };
92
93 port@3 {
94 reg = <3>;
95 label = "lan4";
96 };
97
98 port@5 {
99 reg = <5>;
100 label = "cpu";
101 };
102 };
103 };
104};
105
106&nand {
107 status = "okay";
108
109 partition@0 {
110 label = "u-boot";
111 reg = <0x0000000 0x100000>;
112 read-only;
113 };
114
115 partition@100000 {
116 label = "uImage";
117 reg = <0x0100000 0x200000>;
118 };
119
120 partition@300000 {
121 label = "data";
122 reg = <0x0300000 0x500000>;
123 };
124};
125
126&mdio {
127 status = "okay";
128
129 ethphy0: ethernet-phy@0 {
130 reg = <0>;
131 };
132
133 ethphy1: ethernet-phy@ff {
134 reg = <0xff>; /* No PHY attached */
135 speed = <1000>;
136 duple = <1>;
137 };
138};
139
140&eth0 {
141 status = "okay";
142 ethernet0-port@0 {
143 phy-handle = <&ethphy0>;
144 };
145};
146
147&eth1 {
148 status = "okay";
149 ethernet1-port@0 {
150 phy-handle = <&ethphy1>;
151 };
152};
diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts
new file mode 100644
index 000000000000..93ec3d00c6ab
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rs212.dts
@@ -0,0 +1,48 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6282.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology RS212";
18 compatible = "synology,rs212", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-100-15-35-3 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-38 {
34 status = "okay";
35 };
36
37 regulators-hdd-30-2 {
38 status = "okay";
39 };
40};
41
42&s35390a {
43 status = "okay";
44};
45
46&pcie2 {
47 status = "okay";
48};
diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts
new file mode 100644
index 000000000000..311df4e5aa28
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rs409.dts
@@ -0,0 +1,44 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6281.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology RS409";
18 compatible = "synology,rs409", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-150-15-18 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-36 {
34 status = "okay";
35 };
36};
37
38&eth1 {
39 status = "okay";
40};
41
42&rs5c372 {
43 status = "okay";
44};
diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts
new file mode 100644
index 000000000000..f90da850bb31
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-rs411.dts
@@ -0,0 +1,44 @@
1/*
2 * Andrew Lunn <andrew@lunn.ch>
3 * Ben Peddell <klightspeed@killerwolves.net>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10/dts-v1/;
11
12#include "kirkwood.dtsi"
13#include "kirkwood-6282.dtsi"
14#include "kirkwood-synology.dtsi"
15
16/ {
17 model = "Synology RS411 RS812";
18 compatible = "synology,rs411", "synology,rs812", "marvell,kirkwood";
19
20 memory {
21 device_type = "memory";
22 reg = <0x00000000 0x8000000>;
23 };
24
25 chosen {
26 bootargs = "console=ttyS0,115200n8";
27 };
28
29 gpio-fan-100-15-35-3 {
30 status = "okay";
31 };
32
33 gpio-leds-hdd-36 {
34 status = "okay";
35 };
36};
37
38&eth1 {
39 status = "okay";
40};
41
42&s35390a {
43 status = "okay";
44};
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi
new file mode 100644
index 000000000000..4227c974729d
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-synology.dtsi
@@ -0,0 +1,871 @@
1/*
2 * Nodes for Marvell 628x Synology devices
3 *
4 * Andrew Lunn <andrew@lunn.ch>
5 * Ben Peddell <klightspeed@killerwolves.net>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12/ {
13 mbus {
14 pcie-controller {
15 status = "okay";
16
17 pcie@1,0 {
18 status = "okay";
19 };
20
21 pcie2: pcie@2,0 {
22 status = "disabled";
23 };
24 };
25 };
26
27 ocp@f1000000 {
28 pinctrl: pinctrl@10000 {
29 pmx_alarmled_12: pmx-alarmled-12 {
30 marvell,pins = "mpp12";
31 marvell,function = "gpio";
32 };
33
34 pmx_fanctrl_15: pmx-fanctrl-15 {
35 marvell,pins = "mpp15";
36 marvell,function = "gpio";
37 };
38
39 pmx_fanctrl_16: pmx-fanctrl-16 {
40 marvell,pins = "mpp16";
41 marvell,function = "gpio";
42 };
43
44 pmx_fanctrl_17: pmx-fanctrl-17 {
45 marvell,pins = "mpp17";
46 marvell,function = "gpio";
47 };
48
49 pmx_fanalarm_18: pmx-fanalarm-18 {
50 marvell,pins = "mpp18";
51 marvell,function = "gpo";
52 };
53
54 pmx_hddled_20: pmx-hddled-20 {
55 marvell,pins = "mpp20";
56 marvell,function = "gpio";
57 };
58
59 pmx_hddled_21: pmx-hddled-21 {
60 marvell,pins = "mpp21";
61 marvell,function = "gpio";
62 };
63
64 pmx_hddled_22: pmx-hddled-22 {
65 marvell,pins = "mpp22";
66 marvell,function = "gpio";
67 };
68
69 pmx_hddled_23: pmx-hddled-23 {
70 marvell,pins = "mpp23";
71 marvell,function = "gpio";
72 };
73
74 pmx_hddled_24: pmx-hddled-24 {
75 marvell,pins = "mpp24";
76 marvell,function = "gpio";
77 };
78
79 pmx_hddled_25: pmx-hddled-25 {
80 marvell,pins = "mpp25";
81 marvell,function = "gpio";
82 };
83
84 pmx_hddled_26: pmx-hddled-26 {
85 marvell,pins = "mpp26";
86 marvell,function = "gpio";
87 };
88
89 pmx_hddled_27: pmx-hddled-27 {
90 marvell,pins = "mpp27";
91 marvell,function = "gpio";
92 };
93
94 pmx_hddled_28: pmx-hddled-28 {
95 marvell,pins = "mpp28";
96 marvell,function = "gpio";
97 };
98
99 pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 {
100 marvell,pins = "mpp29";
101 marvell,function = "gpio";
102 };
103
104 pmx_hdd1_pwr_30: pmx-hdd-pwr-30 {
105 marvell,pins = "mpp30";
106 marvell,function = "gpio";
107 };
108
109 pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 {
110 marvell,pins = "mpp31";
111 marvell,function = "gpio";
112 };
113
114 pmx_fanctrl_32: pmx-fanctrl-32 {
115 marvell,pins = "mpp32";
116 marvell,function = "gpio";
117 };
118
119 pmx_fanctrl_33: pmx-fanctrl-33 {
120 marvell,pins = "mpp33";
121 marvell,function = "gpo";
122 };
123
124 pmx_fanctrl_34: pmx-fanctrl-34 {
125 marvell,pins = "mpp34";
126 marvell,function = "gpio";
127 };
128
129 pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 {
130 marvell,pins = "mpp34";
131 marvell,function = "gpio";
132 };
133
134 pmx_fanalarm_35: pmx-fanalarm-35 {
135 marvell,pins = "mpp35";
136 marvell,function = "gpio";
137 };
138
139 pmx_hddled_36: pmx-hddled-36 {
140 marvell,pins = "mpp36";
141 marvell,function = "gpio";
142 };
143
144 pmx_hddled_37: pmx-hddled-37 {
145 marvell,pins = "mpp37";
146 marvell,function = "gpio";
147 };
148
149 pmx_hddled_38: pmx-hddled-38 {
150 marvell,pins = "mpp38";
151 marvell,function = "gpio";
152 };
153
154 pmx_hddled_39: pmx-hddled-39 {
155 marvell,pins = "mpp39";
156 marvell,function = "gpio";
157 };
158
159 pmx_hddled_40: pmx-hddled-40 {
160 marvell,pins = "mpp40";
161 marvell,function = "gpio";
162 };
163
164 pmx_hddled_41: pmx-hddled-41 {
165 marvell,pins = "mpp41";
166 marvell,function = "gpio";
167 };
168
169 pmx_hddled_42: pmx-hddled-42 {
170 marvell,pins = "mpp42";
171 marvell,function = "gpio";
172 };
173
174 pmx_hddled_43: pmx-hddled-43 {
175 marvell,pins = "mpp43";
176 marvell,function = "gpio";
177 };
178
179 pmx_hddled_44: pmx-hddled-44 {
180 marvell,pins = "mpp44";
181 marvell,function = "gpio";
182 };
183
184 pmx_hddled_45: pmx-hddled-45 {
185 marvell,pins = "mpp45";
186 marvell,function = "gpio";
187 };
188
189 pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 {
190 marvell,pins = "mpp44";
191 marvell,function = "gpio";
192 };
193
194 pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 {
195 marvell,pins = "mpp45";
196 marvell,function = "gpio";
197 };
198
199 pmx_fanalarm_44: pmx-fanalarm-44 {
200 marvell,pins = "mpp44";
201 marvell,function = "gpio";
202 };
203
204 pmx_fanalarm_45: pmx-fanalarm-45 {
205 marvell,pins = "mpp45";
206 marvell,function = "gpio";
207 };
208 };
209
210 rtc@10300 {
211 status = "disabled";
212 };
213
214 spi@10600 {
215 status = "okay";
216 pinctrl-0 = <&pmx_spi>;
217 pinctrl-names = "default";
218
219 m25p80@0 {
220 #address-cells = <1>;
221 #size-cells = <1>;
222 compatible = "st,m25p80";
223 reg = <0>;
224 spi-max-frequency = <20000000>;
225 mode = <0>;
226
227 partition@00000000 {
228 reg = <0x00000000 0x00080000>;
229 label = "RedBoot";
230 };
231
232 partition@00080000 {
233 reg = <0x00080000 0x00200000>;
234 label = "zImage";
235 };
236
237 partition@00280000 {
238 reg = <0x00280000 0x00140000>;
239 label = "rd.gz";
240 };
241
242 partition@003c0000 {
243 reg = <0x003c0000 0x00010000>;
244 label = "vendor";
245 };
246
247 partition@003d0000 {
248 reg = <0x003d0000 0x00020000>;
249 label = "RedBoot config";
250 };
251
252 partition@003f0000 {
253 reg = <0x003f0000 0x00010000>;
254 label = "FIS directory";
255 };
256 };
257 };
258
259 i2c@11000 {
260 status = "okay";
261 clock-frequency = <400000>;
262 pinctrl-0 = <&pmx_twsi0>;
263 pinctrl-names = "default";
264
265 rs5c372: rs5c372@32 {
266 status = "disabled";
267 compatible = "ricoh,rs5c372";
268 reg = <0x32>;
269 };
270
271 s35390a: s35390a@30 {
272 status = "disabled";
273 compatible = "ssi,s35390a";
274 reg = <0x30>;
275 };
276 };
277
278 serial@12000 {
279 status = "okay";
280 pinctrl-0 = <&pmx_uart0>;
281 pinctrl-names = "default";
282 };
283
284 serial@12100 {
285 status = "okay";
286 pinctrl-0 = <&pmx_uart1>;
287 pinctrl-names = "default";
288 };
289
290 poweroff@12100 {
291 compatible = "synology,power-off";
292 reg = <0x12100 0x100>;
293 clocks = <&gate_clk 7>;
294 };
295
296 sata@80000 {
297 pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
298 pinctrl-names = "default";
299 status = "okay";
300 nr-ports = <2>;
301 };
302 };
303
304 gpio-fan-150-32-35 {
305 status = "disabled";
306 compatible = "gpio-fan";
307 pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
308 &pmx_fanalarm_35>;
309 pinctrl-names = "default";
310 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
311 &gpio1 1 GPIO_ACTIVE_HIGH
312 &gpio1 2 GPIO_ACTIVE_HIGH>;
313 gpio-fan,speed-map = < 0 0
314 2200 1
315 2500 2
316 3000 4
317 3300 3
318 3700 5
319 3800 6
320 4200 7 >;
321 };
322
323 gpio-fan-150-15-18 {
324 status = "disabled";
325 compatible = "gpio-fan";
326 pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
327 &pmx_fanalarm_18>;
328 pinctrl-names = "default";
329 gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
330 &gpio0 16 GPIO_ACTIVE_HIGH
331 &gpio0 17 GPIO_ACTIVE_HIGH>;
332 alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
333 gpio-fan,speed-map = < 0 0
334 2200 1
335 2500 2
336 3000 4
337 3300 3
338 3700 5
339 3800 6
340 4200 7 >;
341 };
342
343 gpio-fan-100-32-35 {
344 status = "disabled";
345 compatible = "gpio-fan";
346 pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
347 &pmx_fanalarm_35>;
348 pinctrl-names = "default";
349 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
350 &gpio1 1 GPIO_ACTIVE_HIGH
351 &gpio1 2 GPIO_ACTIVE_HIGH>;
352 alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
353 gpio-fan,speed-map = < 0 0
354 2500 1
355 3100 2
356 3800 3
357 4600 4
358 4800 5
359 4900 6
360 5000 7 >;
361 };
362
363 gpio-fan-100-15-18 {
364 status = "disabled";
365 compatible = "gpio-fan";
366 pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
367 &pmx_fanalarm_18>;
368 pinctrl-names = "default";
369 gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
370 &gpio0 16 GPIO_ACTIVE_HIGH
371 &gpio0 17 GPIO_ACTIVE_HIGH>;
372 alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
373 gpio-fan,speed-map = < 0 0
374 2500 1
375 3100 2
376 3800 3
377 4600 4
378 4800 5
379 4900 6
380 5000 7 >;
381 };
382
383 gpio-fan-100-15-35-1 {
384 status = "disabled";
385 compatible = "gpio-fan";
386 pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
387 &pmx_fanalarm_35>;
388 pinctrl-names = "default";
389 gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
390 &gpio0 16 GPIO_ACTIVE_HIGH
391 &gpio0 17 GPIO_ACTIVE_HIGH>;
392 alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
393 gpio-fan,speed-map = < 0 0
394 2500 1
395 3100 2
396 3800 3
397 4600 4
398 4800 5
399 4900 6
400 5000 7 >;
401 };
402
403 gpio-fan-100-15-35-3 {
404 status = "disabled";
405 compatible = "gpio-fan";
406 pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
407 &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>;
408 pinctrl-names = "default";
409 gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
410 &gpio0 16 GPIO_ACTIVE_HIGH
411 &gpio0 17 GPIO_ACTIVE_HIGH>;
412 alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH
413 &gpio1 12 GPIO_ACTIVE_HIGH
414 &gpio1 13 GPIO_ACTIVE_HIGH>;
415 gpio-fan,speed-map = < 0 0
416 2500 1
417 3100 2
418 3800 3
419 4600 4
420 4800 5
421 4900 6
422 5000 7 >;
423 };
424
425 gpio-leds-alarm-12 {
426 status = "disabled";
427 compatible = "gpio-leds";
428 pinctrl-0 = <&pmx_alarmled_12>;
429 pinctrl-names = "default";
430
431 hdd1-green {
432 label = "synology:alarm";
433 gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
434 };
435 };
436
437 gpio-leds-hdd-20 {
438 status = "disabled";
439 compatible = "gpio-leds";
440 pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22
441 &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25
442 &pmx_hddled_26 &pmx_hddled_27>;
443 pinctrl-names = "default";
444
445 hdd1-green {
446 label = "synology:green:hdd1";
447 gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
448 };
449
450 hdd1-amber {
451 label = "synology:amber:hdd1";
452 gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
453 };
454
455 hdd2-green {
456 label = "synology:green:hdd2";
457 gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
458 };
459
460 hdd2-amber {
461 label = "synology:amber:hdd2";
462 gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
463 };
464
465 hdd3-green {
466 label = "synology:green:hdd3";
467 gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
468 };
469
470 hdd3-amber {
471 label = "synology:amber:hdd3";
472 gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
473 };
474
475 hdd4-green {
476 label = "synology:green:hdd4";
477 gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
478 };
479
480 hdd4-amber {
481 label = "synology:amber:hdd4";
482 gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
483 };
484 };
485
486 gpio-leds-hdd-21-1 {
487 status = "disabled";
488 compatible = "gpio-leds";
489 pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>;
490 pinctrl-names = "default";
491
492 hdd1-green {
493 label = "synology:green:hdd1";
494 gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
495 };
496
497 hdd1-amber {
498 label = "synology:amber:hdd1";
499 gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
500 };
501 };
502
503 gpio-leds-hdd-21-2 {
504 status = "disabled";
505 compatible = "gpio-leds";
506 pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>;
507 pinctrl-names = "default";
508
509 hdd1-green {
510 label = "synology:green:hdd1";
511 gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
512 };
513
514 hdd1-amber {
515 label = "synology:amber:hdd1";
516 gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
517 };
518
519 hdd2-green {
520 label = "synology:green:hdd2";
521 gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
522 };
523
524 hdd2-amber {
525 label = "synology:amber:hdd2";
526 gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
527 };
528 };
529
530 gpio-leds-hdd-36 {
531 status = "disabled";
532 compatible = "gpio-leds";
533 pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38
534 &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41
535 &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44
536 &pmx_hddled_45>;
537 pinctrl-names = "default";
538
539 hdd1-green {
540 label = "synology:green:hdd1";
541 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
542 };
543
544 hdd1-amber {
545 label = "synology:amber:hdd1";
546 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
547 };
548
549 hdd2-green {
550 label = "synology:green:hdd2";
551 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
552 };
553
554 hdd2-amber {
555 label = "synology:amber:hdd2";
556 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
557 };
558
559 hdd3-green {
560 label = "synology:green:hdd3";
561 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
562 };
563
564 hdd3-amber {
565 label = "synology:amber:hdd3";
566 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
567 };
568
569 hdd4-green {
570 label = "synology:green:hdd4";
571 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
572 };
573
574 hdd4-amber {
575 label = "synology:amber:hdd4";
576 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
577 };
578
579 hdd5-green {
580 label = "synology:green:hdd5";
581 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
582 };
583
584 hdd5-amber {
585 label = "synology:amber:hdd5";
586 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
587 };
588 };
589
590 gpio-leds-hdd-38 {
591 status = "disabled";
592 compatible = "gpio-leds";
593 pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>;
594 pinctrl-names = "default";
595
596 hdd1-green {
597 label = "synology:green:hdd1";
598 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
599 };
600
601 hdd1-amber {
602 label = "synology:amber:hdd1";
603 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
604 };
605
606 hdd2-green {
607 label = "synology:green:hdd2";
608 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
609 };
610
611 hdd2-amber {
612 label = "synology:amber:hdd2";
613 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
614 };
615 };
616
617 regulators-hdd-29 {
618 status = "disabled";
619 compatible = "simple-bus";
620 #address-cells = <1>;
621 #size-cells = <0>;
622 pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>;
623 pinctrl-names = "default";
624
625 regulator@1 {
626 compatible = "regulator-fixed";
627 reg = <1>;
628 regulator-name = "hdd1power";
629 regulator-min-microvolt = <5000000>;
630 regulator-max-microvolt = <5000000>;
631 enable-active-high;
632 regulator-always-on;
633 regulator-boot-on;
634 startup-delay-us = <5000000>;
635 gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
636 };
637
638 regulator@2 {
639 compatible = "regulator-fixed";
640 reg = <2>;
641 regulator-name = "hdd2power";
642 regulator-min-microvolt = <5000000>;
643 regulator-max-microvolt = <5000000>;
644 enable-active-high;
645 regulator-always-on;
646 regulator-boot-on;
647 startup-delay-us = <5000000>;
648 gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
649 };
650 };
651
652 regulators-hdd-30-1 {
653 status = "disabled";
654 compatible = "simple-bus";
655 #address-cells = <1>;
656 #size-cells = <0>;
657 pinctrl-0 = <&pmx_hdd1_pwr_30>;
658 pinctrl-names = "default";
659
660 regulator@1 {
661 compatible = "regulator-fixed";
662 reg = <1>;
663 regulator-name = "hdd1power";
664 regulator-min-microvolt = <5000000>;
665 regulator-max-microvolt = <5000000>;
666 enable-active-high;
667 regulator-always-on;
668 regulator-boot-on;
669 startup-delay-us = <5000000>;
670 gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
671 };
672 };
673
674 regulators-hdd-30-2 {
675 status = "disabled";
676 compatible = "simple-bus";
677 #address-cells = <1>;
678 #size-cells = <0>;
679 pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>;
680 pinctrl-names = "default";
681
682 regulator@1 {
683 compatible = "regulator-fixed";
684 reg = <1>;
685 regulator-name = "hdd1power";
686 regulator-min-microvolt = <5000000>;
687 regulator-max-microvolt = <5000000>;
688 enable-active-high;
689 regulator-always-on;
690 regulator-boot-on;
691 startup-delay-us = <5000000>;
692 gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
693 };
694
695 regulator@2 {
696 compatible = "regulator-fixed";
697 reg = <2>;
698 regulator-name = "hdd2power";
699 regulator-min-microvolt = <5000000>;
700 regulator-max-microvolt = <5000000>;
701 enable-active-high;
702 regulator-always-on;
703 regulator-boot-on;
704 startup-delay-us = <5000000>;
705 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
706 };
707 };
708
709 regulators-hdd-30-4 {
710 status = "disabled";
711 compatible = "simple-bus";
712 #address-cells = <1>;
713 #size-cells = <0>;
714 pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34
715 &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>;
716 pinctrl-names = "default";
717
718 regulator@1 {
719 compatible = "regulator-fixed";
720 reg = <1>;
721 regulator-name = "hdd1power";
722 regulator-min-microvolt = <5000000>;
723 regulator-max-microvolt = <5000000>;
724 enable-active-high;
725 regulator-always-on;
726 regulator-boot-on;
727 startup-delay-us = <5000000>;
728 gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
729 };
730
731 regulator@2 {
732 compatible = "regulator-fixed";
733 reg = <2>;
734 regulator-name = "hdd2power";
735 regulator-min-microvolt = <5000000>;
736 regulator-max-microvolt = <5000000>;
737 enable-active-high;
738 regulator-always-on;
739 regulator-boot-on;
740 startup-delay-us = <5000000>;
741 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
742 };
743
744 regulator@3 {
745 compatible = "regulator-fixed";
746 reg = <3>;
747 regulator-name = "hdd3power";
748 regulator-min-microvolt = <5000000>;
749 regulator-max-microvolt = <5000000>;
750 enable-active-high;
751 regulator-always-on;
752 regulator-boot-on;
753 startup-delay-us = <5000000>;
754 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
755 };
756
757 regulator@4 {
758 compatible = "regulator-fixed";
759 reg = <4>;
760 regulator-name = "hdd4power";
761 regulator-min-microvolt = <5000000>;
762 regulator-max-microvolt = <5000000>;
763 enable-active-high;
764 regulator-always-on;
765 regulator-boot-on;
766 startup-delay-us = <5000000>;
767 gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
768 };
769 };
770
771 regulators-hdd-31 {
772 status = "disabled";
773 compatible = "simple-bus";
774 #address-cells = <1>;
775 #size-cells = <0>;
776 pinctrl-0 = <&pmx_hdd2_pwr_31>;
777 pinctrl-names = "default";
778
779 regulator@1 {
780 compatible = "regulator-fixed";
781 reg = <1>;
782 regulator-name = "hdd2power";
783 regulator-min-microvolt = <5000000>;
784 regulator-max-microvolt = <5000000>;
785 enable-active-high;
786 regulator-always-on;
787 regulator-boot-on;
788 startup-delay-us = <5000000>;
789 gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
790 };
791 };
792
793 regulators-hdd-34 {
794 status = "disabled";
795 compatible = "simple-bus";
796 #address-cells = <1>;
797 #size-cells = <0>;
798 pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44
799 &pmx_hdd4_pwr_45>;
800 pinctrl-names = "default";
801
802 regulator@2 {
803 compatible = "regulator-fixed";
804 reg = <2>;
805 regulator-name = "hdd2power";
806 regulator-min-microvolt = <5000000>;
807 regulator-max-microvolt = <5000000>;
808 enable-active-high;
809 regulator-always-on;
810 regulator-boot-on;
811 startup-delay-us = <5000000>;
812 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
813 };
814
815 regulator@3 {
816 compatible = "regulator-fixed";
817 reg = <3>;
818 regulator-name = "hdd3power";
819 regulator-min-microvolt = <5000000>;
820 regulator-max-microvolt = <5000000>;
821 enable-active-high;
822 regulator-always-on;
823 regulator-boot-on;
824 startup-delay-us = <5000000>;
825 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
826 };
827
828 regulator@4 {
829 compatible = "regulator-fixed";
830 reg = <4>;
831 regulator-name = "hdd4power";
832 regulator-min-microvolt = <5000000>;
833 regulator-max-microvolt = <5000000>;
834 enable-active-high;
835 regulator-always-on;
836 regulator-boot-on;
837 startup-delay-us = <5000000>;
838 gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
839 };
840 };
841};
842
843&mdio {
844 status = "okay";
845
846 ethphy0: ethernet-phy@0 {
847 device_type = "ethernet-phy";
848 reg = <8>;
849 };
850
851 ethphy1: ethernet-phy@1 {
852 device_type = "ethernet-phy";
853 reg = <9>;
854 };
855};
856
857&eth0 {
858 status = "okay";
859
860 ethernet0-port@0 {
861 phy-handle = <&ethphy0>;
862 };
863};
864
865&eth1 {
866 status = "disabled";
867
868 ethernet1-port@0 {
869 phy-handle = <&ethphy1>;
870 };
871};
diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts
new file mode 100644
index 000000000000..7d1c7677a18f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-t5325.dts
@@ -0,0 +1,208 @@
1/*
2 * Device Tree file for HP t5325 Thin Client"
3 *
4 * Copyright (C) 2014
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12*/
13
14/dts-v1/;
15
16#include "kirkwood.dtsi"
17#include "kirkwood-6281.dtsi"
18
19/ {
20 model = "HP t5325 Thin Client";
21 compatible = "hp,t5325", "marvell,kirkwood-88f6281", "marvell,kirkwood";
22
23 memory {
24 device_type = "memory";
25 reg = <0x00000000 0x20000000>;
26 };
27
28 chosen {
29 bootargs = "console=ttyS0,115200n8";
30 };
31
32 mbus {
33 pcie-controller {
34 status = "okay";
35
36 pcie@1,0 {
37 status = "okay";
38 };
39 };
40 };
41
42 ocp@f1000000 {
43 pinctrl: pinctrl@10000 {
44 pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
45 pinctrl-names = "default";
46
47 pmx_button_power: pmx-button_power {
48 marvell,pins = "mpp45";
49 marvell,function = "gpio";
50 };
51
52 pmx_power_off: pmx-power-off {
53 marvell,pins = "mpp48";
54 marvell,function = "gpio";
55 };
56
57 pmx_led: pmx-led {
58 marvell,pins = "mpp21";
59 marvell,function = "gpio";
60 };
61
62 pmx_usb_sata_power_enable: pmx-usb-sata-power-enable {
63 marvell,pins = "mpp44";
64 marvell,function = "gpio";
65 };
66
67 /*
68 * Redefined from kirkwood-6281.dtsi, because
69 * we don't use SPI CS on MPP0, but on MPP7.
70 */
71 pmx_spi: pmx-spi {
72 marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7";
73 marvell,function = "spi";
74 };
75
76 pmx_sysrst: pmx-sysrst {
77 marvell,pins = "mpp6";
78 marvell,function = "sysrst";
79 };
80
81 pmx_i2s: pmx-i2s {
82 marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42",
83 "mpp43";
84 marvell,function = "audio";
85 };
86 };
87
88 spi@10600 {
89 pinctrl-0 = <&pmx_spi>;
90 pinctrl-names = "default";
91 status = "okay";
92
93 flash@0 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "st,m25p80";
97 spi-max-frequency = <86000000>;
98 reg = <0>;
99 mode = <0>;
100
101 partition@0 {
102 reg = <0x0 0x80000>;
103 label = "u-boot";
104 };
105
106 partition@1 {
107 reg = <0x80000 0x40000>;
108 label = "SSD firmware";
109 };
110
111 partition@2 {
112 reg = <0xc0000 0x10000>;
113 label = "u-boot env";
114 };
115
116 partition@3 {
117 reg = <0xd0000 0x10000>;
118 label = "permanent u-boot env";
119 };
120
121 partition@4 {
122 reg = <0xd0000 0x10000>;
123 label = "permanent u-boot env";
124 };
125 };
126 };
127
128 i2c@11000 {
129 status = "okay";
130
131 alc5621: alc5621@1a {
132 compatible = "realtek,alc5621";
133 reg = <0x1a>;
134 };
135 };
136
137 serial@12000 {
138 status = "okay";
139 };
140
141 sata@80000 {
142 status = "okay";
143 nr-ports = <2>;
144 };
145
146 audio: audio-controller@a0000 {
147 status = "okay";
148 };
149 };
150
151 regulators {
152 compatible = "simple-bus";
153 #address-cells = <1>;
154 #size-cells = <0>;
155 pinctrl-0 = <&pmx_usb_sata_power_enable>;
156 pinctrl-names = "default";
157
158 usb_power: regulator@1 {
159 compatible = "regulator-fixed";
160 reg = <1>;
161 regulator-name = "USB-SATA Power";
162 regulator-min-microvolt = <5000000>;
163 regulator-max-microvolt = <5000000>;
164 enable-active-high;
165 regulator-always-on;
166 regulator-boot-on;
167 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
168 };
169 };
170
171 gpio_keys {
172 compatible = "gpio-keys";
173 #address-cells = <1>;
174 #size-cells = <0>;
175 pinctrl-0 = <&pmx_button_power>;
176 pinctrl-names = "default";
177
178 button@1 {
179 label = "Power Button";
180 linux,code = <KEY_POWER>;
181 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
182 };
183 };
184
185 gpio_poweroff {
186 compatible = "gpio-poweroff";
187 pinctrl-0 = <&pmx_power_off>;
188 pinctrl-names = "default";
189 gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
190 };
191
192};
193
194&mdio {
195 status = "okay";
196
197 ethphy0: ethernet-phy {
198 device_type = "ethernet-phy";
199 reg = <8>;
200 };
201};
202
203&eth0 {
204 status = "okay";
205 ethernet0-port@0 {
206 phy-handle = <&ethphy0>;
207 };
208};
diff --git a/arch/arm/boot/dts/kirkwood-ts419-6281.dts b/arch/arm/boot/dts/kirkwood-ts419-6281.dts
new file mode 100644
index 000000000000..aa22aa862857
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ts419-6281.dts
@@ -0,0 +1,20 @@
1/*
2 * Device Tree file for QNAP TS41X with 6281 SoC
3 *
4 * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/dts-v1/;
13
14#include "kirkwood.dtsi"
15#include "kirkwood-6281.dtsi"
16#include "kirkwood-ts219.dtsi"
17#include "kirkwood-ts419.dtsi"
18
19&ethphy0 { reg = <8>; };
20&ethphy1 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts419-6282.dts b/arch/arm/boot/dts/kirkwood-ts419-6282.dts
new file mode 100644
index 000000000000..d7512d4cdced
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ts419-6282.dts
@@ -0,0 +1,32 @@
1/*
2 * Device Tree file for QNAP TS41X with 6282 SoC
3 *
4 * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/dts-v1/;
13
14#include "kirkwood.dtsi"
15#include "kirkwood-6282.dtsi"
16#include "kirkwood-ts219.dtsi"
17#include "kirkwood-ts419.dtsi"
18
19/ {
20 mbus {
21 pcie-controller {
22 status = "okay";
23
24 pcie@2,0 {
25 status = "okay";
26 };
27 };
28 };
29};
30
31&ethphy0 { reg = <0>; };
32&ethphy1 { reg = <1>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi
new file mode 100644
index 000000000000..1a9c624c7a92
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ts419.dtsi
@@ -0,0 +1,75 @@
1/*
2 * Device Tree include file for QNAP TS41X
3 *
4 * Copyright (C) 2013, Andrew Lunn <andrew@lunn.ch>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/ {
13 model = "QNAP TS419 family";
14 compatible = "qnap,ts419", "marvell,kirkwood";
15
16 ocp@f1000000 {
17 pinctrl: pinctrl@10000 {
18 pinctrl-names = "default";
19
20 pmx_USB_copy_button: pmx-USB-copy-button {
21 marvell,pins = "mpp43";
22 marvell,function = "gpio";
23 };
24 pmx_reset_button: pmx-reset-button {
25 marvell,pins = "mpp37";
26 marvell,function = "gpio";
27 };
28 /*
29 * JP1 indicates if an LCD module is installed
30 * on the serial port (0), or if the port is used
31 * as a console (1).
32 */
33 pmx_jumper_jp1: pmx-jumper_jp1 {
34 marvell,pins = "mpp45";
35 marvell,function = "gpio";
36 };
37
38 };
39 };
40
41 gpio_keys {
42 compatible = "gpio-keys";
43 #address-cells = <1>;
44 #size-cells = <0>;
45 pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
46 pinctrl-names = "default";
47
48 button@1 {
49 label = "USB Copy";
50 linux,code = <KEY_COPY>;
51 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
52 };
53 button@2 {
54 label = "Reset";
55 linux,code = <KEY_RESTART>;
56 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
57 };
58 };
59};
60
61&mdio {
62 status = "okay";
63
64 ethphy1: ethernet-phy@1 {
65 device_type = "ethernet-phy";
66 /* overwrite reg property in board file */
67 };
68};
69
70&eth1 {
71 status = "okay";
72 ethernet1-port@0 {
73 phy-handle = <&ethphy1>;
74 };
75};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 6abf44d257df..90384587c278 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -24,6 +24,7 @@
24 aliases { 24 aliases {
25 gpio0 = &gpio0; 25 gpio0 = &gpio0;
26 gpio1 = &gpio1; 26 gpio1 = &gpio1;
27 i2c0 = &i2c0;
27 }; 28 };
28 29
29 mbus { 30 mbus {
@@ -111,7 +112,7 @@
111 clocks = <&gate_clk 7>; 112 clocks = <&gate_clk 7>;
112 }; 113 };
113 114
114 i2c@11000 { 115 i2c0: i2c@11000 {
115 compatible = "marvell,mv64xxx-i2c"; 116 compatible = "marvell,mv64xxx-i2c";
116 reg = <0x11000 0x20>; 117 reg = <0x11000 0x20>;
117 #address-cells = <1>; 118 #address-cells = <1>;
@@ -145,6 +146,11 @@
145 reg = <0x20000 0x80>, <0x1500 0x20>; 146 reg = <0x20000 0x80>, <0x1500 0x20>;
146 }; 147 };
147 148
149 system-controller@20000 {
150 compatible = "marvell,orion-system-controller";
151 reg = <0x20000 0x120>;
152 };
153
148 bridge_intc: bridge-interrupt-ctrl@20110 { 154 bridge_intc: bridge-interrupt-ctrl@20110 {
149 compatible = "marvell,orion-bridge-intc"; 155 compatible = "marvell,orion-bridge-intc";
150 interrupt-controller; 156 interrupt-controller;
@@ -161,6 +167,11 @@
161 #clock-cells = <1>; 167 #clock-cells = <1>;
162 }; 168 };
163 169
170 l2: l2-cache@20128 {
171 compatible = "marvell,kirkwood-cache";
172 reg = <0x20128 0x4>;
173 };
174
164 intc: main-interrupt-ctrl@20200 { 175 intc: main-interrupt-ctrl@20200 {
165 compatible = "marvell,orion-intc"; 176 compatible = "marvell,orion-intc";
166 interrupt-controller; 177 interrupt-controller;
@@ -178,7 +189,7 @@
178 189
179 wdt: watchdog-timer@20300 { 190 wdt: watchdog-timer@20300 {
180 compatible = "marvell,orion-wdt"; 191 compatible = "marvell,orion-wdt";
181 reg = <0x20300 0x28>; 192 reg = <0x20300 0x28>, <0x20108 0x4>;
182 interrupt-parent = <&bridge_intc>; 193 interrupt-parent = <&bridge_intc>;
183 interrupts = <3>; 194 interrupts = <3>;
184 clocks = <&gate_clk 7>; 195 clocks = <&gate_clk 7>;
@@ -300,5 +311,14 @@
300 #phy-cells = <0>; 311 #phy-cells = <0>;
301 status = "ok"; 312 status = "ok";
302 }; 313 };
314
315 audio0: audio-controller@a0000 {
316 compatible = "marvell,kirkwood-audio";
317 reg = <0xa0000 0x2210>;
318 interrupts = <24>;
319 clocks = <&gate_clk 9>;
320 clock-names = "internal";
321 status = "disabled";
322 };
303 }; 323 };
304}; 324};
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
index 1579c3491ccd..0c9647d28765 100644
--- a/arch/arm/boot/dts/marco.dtsi
+++ b/arch/arm/boot/dts/marco.dtsi
@@ -58,9 +58,10 @@
58 #size-cells = <1>; 58 #size-cells = <1>;
59 ranges = <0xc2000000 0xc2000000 0x1000000>; 59 ranges = <0xc2000000 0xc2000000 0x1000000>;
60 60
61 reset-controller@c2000000 { 61 rstc: reset-controller@c2000000 {
62 compatible = "sirf,marco-rstc"; 62 compatible = "sirf,marco-rstc";
63 reg = <0xc2000000 0x10000>; 63 reg = <0xc2000000 0x10000>;
64 #reset-cells = <1>;
64 }; 65 };
65 }; 66 };
66 67
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
new file mode 100644
index 000000000000..73e272fadc20
--- /dev/null
+++ b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
@@ -0,0 +1,58 @@
1/*
2 * Common file for GPMC connected smsc9221 on omaps
3 *
4 * Compared to smsc911x, smsc9221 (and others like smsc9217
5 * or smsc 9218) has faster timings, leading to higher
6 * bandwidth.
7 *
8 * Note that the board specifc DTS file needs to specify
9 * ranges, pinctrl, reg, interrupt parent and interrupts.
10 */
11
12/ {
13 vddvario: regulator-vddvario {
14 compatible = "regulator-fixed";
15 regulator-name = "vddvario";
16 regulator-always-on;
17 };
18
19 vdd33a: regulator-vdd33a {
20 compatible = "regulator-fixed";
21 regulator-name = "vdd33a";
22 regulator-always-on;
23 };
24};
25
26&gpmc {
27 ethernet@gpmc {
28 compatible = "smsc,lan9221","smsc,lan9115";
29 bank-width = <2>;
30
31 gpmc,mux-add-data;
32 gpmc,cs-on-ns = <0>;
33 gpmc,cs-rd-off-ns = <42>;
34 gpmc,cs-wr-off-ns = <36>;
35 gpmc,adv-on-ns = <6>;
36 gpmc,adv-rd-off-ns = <12>;
37 gpmc,adv-wr-off-ns = <12>;
38 gpmc,oe-on-ns = <0>;
39 gpmc,oe-off-ns = <42>;
40 gpmc,we-on-ns = <0>;
41 gpmc,we-off-ns = <36>;
42 gpmc,rd-cycle-ns = <60>;
43 gpmc,wr-cycle-ns = <54>;
44 gpmc,access-ns = <36>;
45 gpmc,page-burst-access-ns = <0>;
46 gpmc,bus-turnaround-ns = <0>;
47 gpmc,cycle2cycle-delay-ns = <0>;
48 gpmc,wr-data-mux-bus-ns = <18>;
49 gpmc,wr-access-ns = <42>;
50 gpmc,cycle2cycle-samecsen;
51 gpmc,cycle2cycle-diffcsen;
52
53 vddvario-supply = <&vddvario>;
54 vdd33a-supply = <&vdd33a>;
55 reg-io-width = <4>;
56 smsc,save-mac-address;
57 };
58};
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 5377ddf83bf8..22f35ea142c1 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -271,5 +271,36 @@
271 ti,hwmods = "timer12"; 271 ti,hwmods = "timer12";
272 ti,timer-pwm; 272 ti,timer-pwm;
273 }; 273 };
274
275 dss: dss@48050000 {
276 compatible = "ti,omap2-dss";
277 reg = <0x48050000 0x400>;
278 status = "disabled";
279 ti,hwmods = "dss_core";
280 #address-cells = <1>;
281 #size-cells = <1>;
282 ranges;
283
284 dispc@48050400 {
285 compatible = "ti,omap2-dispc";
286 reg = <0x48050400 0x400>;
287 interrupts = <25>;
288 ti,hwmods = "dss_dispc";
289 };
290
291 rfbi: encoder@48050800 {
292 compatible = "ti,omap2-rfbi";
293 reg = <0x48050800 0x400>;
294 status = "disabled";
295 ti,hwmods = "dss_rfbi";
296 };
297
298 venc: encoder@48050c00 {
299 compatible = "ti,omap2-venc";
300 reg = <0x48050c00 0x400>;
301 status = "disabled";
302 ti,hwmods = "dss_venc";
303 };
304 };
274 }; 305 };
275}; 306};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 60c605de22dd..85b1fb014c43 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -99,6 +99,7 @@
99 dmas = <&sdma 31>, 99 dmas = <&sdma 31>,
100 <&sdma 32>; 100 <&sdma 32>;
101 dma-names = "tx", "rx"; 101 dma-names = "tx", "rx";
102 status = "disabled";
102 }; 103 };
103 104
104 mcbsp2: mcbsp@48076000 { 105 mcbsp2: mcbsp@48076000 {
@@ -112,6 +113,7 @@
112 dmas = <&sdma 33>, 113 dmas = <&sdma 33>,
113 <&sdma 34>; 114 <&sdma 34>;
114 dma-names = "tx", "rx"; 115 dma-names = "tx", "rx";
116 status = "disabled";
115 }; 117 };
116 118
117 msdi1: mmc@4809c000 { 119 msdi1: mmc@4809c000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d624345666f5..d09697dab55e 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -29,6 +29,22 @@
29 pinctrl-single,function-mask = <0x3f>; 29 pinctrl-single,function-mask = <0x3f>;
30 }; 30 };
31 31
32 omap2_scm_general: tisyscon@49002270 {
33 compatible = "syscon";
34 reg = <0x49002270 0x240>;
35 };
36
37 pbias_regulator: pbias_regulator {
38 compatible = "ti,pbias-omap";
39 reg = <0x230 0x4>;
40 syscon = <&omap2_scm_general>;
41 pbias_mmc_reg: pbias_mmc_omap2430 {
42 regulator-name = "pbias_mmc_omap2430";
43 regulator-min-microvolt = <1800000>;
44 regulator-max-microvolt = <3000000>;
45 };
46 };
47
32 gpio1: gpio@4900c000 { 48 gpio1: gpio@4900c000 {
33 compatible = "ti,omap2-gpio"; 49 compatible = "ti,omap2-gpio";
34 reg = <0x4900c000 0x200>; 50 reg = <0x4900c000 0x200>;
@@ -113,6 +129,7 @@
113 dmas = <&sdma 31>, 129 dmas = <&sdma 31>,
114 <&sdma 32>; 130 <&sdma 32>;
115 dma-names = "tx", "rx"; 131 dma-names = "tx", "rx";
132 status = "disabled";
116 }; 133 };
117 134
118 mcbsp2: mcbsp@48076000 { 135 mcbsp2: mcbsp@48076000 {
@@ -128,6 +145,7 @@
128 dmas = <&sdma 33>, 145 dmas = <&sdma 33>,
129 <&sdma 34>; 146 <&sdma 34>;
130 dma-names = "tx", "rx"; 147 dma-names = "tx", "rx";
148 status = "disabled";
131 }; 149 };
132 150
133 mcbsp3: mcbsp@4808c000 { 151 mcbsp3: mcbsp@4808c000 {
@@ -143,6 +161,7 @@
143 dmas = <&sdma 17>, 161 dmas = <&sdma 17>,
144 <&sdma 18>; 162 <&sdma 18>;
145 dma-names = "tx", "rx"; 163 dma-names = "tx", "rx";
164 status = "disabled";
146 }; 165 };
147 166
148 mcbsp4: mcbsp@4808e000 { 167 mcbsp4: mcbsp@4808e000 {
@@ -158,6 +177,7 @@
158 dmas = <&sdma 19>, 177 dmas = <&sdma 19>,
159 <&sdma 20>; 178 <&sdma 20>;
160 dma-names = "tx", "rx"; 179 dma-names = "tx", "rx";
180 status = "disabled";
161 }; 181 };
162 182
163 mcbsp5: mcbsp@48096000 { 183 mcbsp5: mcbsp@48096000 {
@@ -173,6 +193,7 @@
173 dmas = <&sdma 21>, 193 dmas = <&sdma 21>,
174 <&sdma 22>; 194 <&sdma 22>;
175 dma-names = "tx", "rx"; 195 dma-names = "tx", "rx";
196 status = "disabled";
176 }; 197 };
177 198
178 mmc1: mmc@4809c000 { 199 mmc1: mmc@4809c000 {
@@ -183,6 +204,7 @@
183 ti,dual-volt; 204 ti,dual-volt;
184 dmas = <&sdma 61>, <&sdma 62>; 205 dmas = <&sdma 61>, <&sdma 62>;
185 dma-names = "tx", "rx"; 206 dma-names = "tx", "rx";
207 pbias-supply = <&pbias_mmc_reg>;
186 }; 208 };
187 209
188 mmc2: mmc@480b4000 { 210 mmc2: mmc@480b4000 {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 447e714d435b..cf0be662297e 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -24,6 +24,11 @@
24 reg = <0x80000000 0x20000000>; /* 512 MB */ 24 reg = <0x80000000 0x20000000>; /* 512 MB */
25 }; 25 };
26 26
27 aliases {
28 display0 = &dvi0;
29 display1 = &tv0;
30 };
31
27 leds { 32 leds {
28 compatible = "gpio-leds"; 33 compatible = "gpio-leds";
29 34
@@ -86,6 +91,60 @@
86 reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ 91 reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
87 vcc-supply = <&hsusb2_power>; 92 vcc-supply = <&hsusb2_power>;
88 }; 93 };
94
95 tfp410: encoder@0 {
96 compatible = "ti,tfp410";
97 powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
98
99 /* XXX pinctrl from twl */
100
101 ports {
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 port@0 {
106 reg = <0>;
107
108 tfp410_in: endpoint@0 {
109 remote-endpoint = <&dpi_out>;
110 };
111 };
112
113 port@1 {
114 reg = <1>;
115
116 tfp410_out: endpoint@0 {
117 remote-endpoint = <&dvi_connector_in>;
118 };
119 };
120 };
121 };
122
123 dvi0: connector@0 {
124 compatible = "dvi-connector";
125 label = "dvi";
126
127 digital;
128
129 ddc-i2c-bus = <&i2c3>;
130
131 port {
132 dvi_connector_in: endpoint {
133 remote-endpoint = <&tfp410_out>;
134 };
135 };
136 };
137
138 tv0: connector@1 {
139 compatible = "svideo-connector";
140 label = "tv";
141
142 port {
143 tv_connector_in: endpoint {
144 remote-endpoint = <&venc_out>;
145 };
146 };
147 };
89}; 148};
90 149
91&omap3_pmx_wkup { 150&omap3_pmx_wkup {
@@ -94,6 +153,17 @@
94 0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ 153 0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
95 >; 154 >;
96 }; 155 };
156
157 dss_dpi_pins2: pinmux_dss_dpi_pins1 {
158 pinctrl-single,pins = <
159 0x0a (PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
160 0x0c (PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
161 0x10 (PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
162 0x12 (PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
163 0x14 (PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
164 0x16 (PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
165 >;
166 };
97}; 167};
98 168
99&omap3_pmx_core { 169&omap3_pmx_core {
@@ -119,6 +189,35 @@
119 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ 189 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
120 >; 190 >;
121 }; 191 };
192
193 dss_dpi_pins1: pinmux_dss_dpi_pins2 {
194 pinctrl-single,pins = <
195 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
196 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
197 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
198 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
199
200 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
201 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
202 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
203 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
204 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
205 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
206 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
207 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
208 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
209 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
210 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
211 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
212
213 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
214 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
215 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
216 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
217 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
218 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
219 >;
220 };
122}; 221};
123 222
124&omap3_pmx_core2 { 223&omap3_pmx_core2 {
@@ -164,15 +263,6 @@
164 263
165&i2c3 { 264&i2c3 {
166 clock-frequency = <100000>; 265 clock-frequency = <100000>;
167
168 /*
169 * Display monitor features are burnt in the EEPROM
170 * as EDID data.
171 */
172 eeprom@50 {
173 compatible = "ti,eeprom";
174 reg = <0x50>;
175 };
176}; 266};
177 267
178&mmc1 { 268&mmc1 {
@@ -234,3 +324,37 @@
234 regulator-max-microvolt = <1800000>; 324 regulator-max-microvolt = <1800000>;
235 regulator-always-on; 325 regulator-always-on;
236}; 326};
327
328&mcbsp2 {
329 status = "okay";
330};
331
332&dss {
333 status = "ok";
334
335 pinctrl-names = "default";
336 pinctrl-0 = <
337 &dss_dpi_pins1
338 &dss_dpi_pins2
339 >;
340
341 port {
342 dpi_out: endpoint {
343 remote-endpoint = <&tfp410_in>;
344 data-lines = <24>;
345 };
346 };
347};
348
349&venc {
350 status = "ok";
351
352 vdda-supply = <&vdac>;
353
354 port {
355 venc_out: endpoint {
356 remote-endpoint = <&tv_connector_in>;
357 ti,channels = <2>;
358 };
359 };
360};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 5053766d369b..3c3e6da1deac 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -24,6 +24,11 @@
24 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 }; 25 };
26 26
27 aliases {
28 display0 = &dvi0;
29 display1 = &tv0;
30 };
31
27 leds { 32 leds {
28 compatible = "gpio-leds"; 33 compatible = "gpio-leds";
29 pmu_stat { 34 pmu_stat {
@@ -80,6 +85,61 @@
80 }; 85 };
81 86
82 }; 87 };
88
89 tfp410: encoder@0 {
90 compatible = "ti,tfp410";
91 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
92
93 pinctrl-names = "default";
94 pinctrl-0 = <&tfp410_pins>;
95
96 ports {
97 #address-cells = <1>;
98 #size-cells = <0>;
99
100 port@0 {
101 reg = <0>;
102
103 tfp410_in: endpoint@0 {
104 remote-endpoint = <&dpi_out>;
105 };
106 };
107
108 port@1 {
109 reg = <1>;
110
111 tfp410_out: endpoint@0 {
112 remote-endpoint = <&dvi_connector_in>;
113 };
114 };
115 };
116 };
117
118 dvi0: connector@0 {
119 compatible = "dvi-connector";
120 label = "dvi";
121
122 digital;
123
124 ddc-i2c-bus = <&i2c3>;
125
126 port {
127 dvi_connector_in: endpoint {
128 remote-endpoint = <&tfp410_out>;
129 };
130 };
131 };
132
133 tv0: connector@1 {
134 compatible = "svideo-connector";
135 label = "tv";
136
137 port {
138 tv_connector_in: endpoint {
139 remote-endpoint = <&venc_out>;
140 };
141 };
142 };
83}; 143};
84 144
85&omap3_pmx_wkup { 145&omap3_pmx_wkup {
@@ -113,6 +173,45 @@
113 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 173 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
114 >; 174 >;
115 }; 175 };
176
177 tfp410_pins: pinmux_tfp410_pins {
178 pinctrl-single,pins = <
179 0x194 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
180 >;
181 };
182
183 dss_dpi_pins: pinmux_dss_dpi_pins {
184 pinctrl-single,pins = <
185 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
186 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
187 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
188 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
189 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
190 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
191 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
192 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
193 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
194 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
195 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
196 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
197 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
198 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
199 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
200 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
201 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
202 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
203 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
204 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
205 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
206 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
207 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
208 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
209 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
210 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
211 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
212 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
213 >;
214 };
116}; 215};
117 216
118&omap3_pmx_core2 { 217&omap3_pmx_core2 {
@@ -152,6 +251,10 @@
152#include "twl4030.dtsi" 251#include "twl4030.dtsi"
153#include "twl4030_omap3.dtsi" 252#include "twl4030_omap3.dtsi"
154 253
254&i2c3 {
255 clock-frequency = <100000>;
256};
257
155&mmc1 { 258&mmc1 {
156 vmmc-supply = <&vmmc1>; 259 vmmc-supply = <&vmmc1>;
157 vmmc_aux-supply = <&vsim>; 260 vmmc_aux-supply = <&vsim>;
@@ -211,3 +314,39 @@
211 regulator-max-microvolt = <1800000>; 314 regulator-max-microvolt = <1800000>;
212 regulator-always-on; 315 regulator-always-on;
213}; 316};
317
318&mcbsp2 {
319 status = "okay";
320};
321
322/* Needed to power the DPI pins */
323&vpll2 {
324 regulator-always-on;
325};
326
327&dss {
328 status = "ok";
329
330 pinctrl-names = "default";
331 pinctrl-0 = <&dss_dpi_pins>;
332
333 port {
334 dpi_out: endpoint {
335 remote-endpoint = <&tfp410_in>;
336 data-lines = <24>;
337 };
338 };
339};
340
341&venc {
342 status = "ok";
343
344 vdda-supply = <&vdac>;
345
346 port {
347 venc_out: endpoint {
348 remote-endpoint = <&tv_connector_in>;
349 ti,channels = <2>;
350 };
351 };
352};
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
new file mode 100644
index 000000000000..d00502f4fd9b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -0,0 +1,136 @@
1/*
2 * Support for CompuLab CM-T3517
3 */
4/dts-v1/;
5
6#include "am3517.dtsi"
7#include "omap3-cm-t3x.dtsi"
8
9/ {
10 model = "CompuLab CM-T3517";
11 compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
12
13 vmmc: regulator-vmmc {
14 compatible = "regulator-fixed";
15 regulator-name = "vmmc";
16 regulator-min-microvolt = <3300000>;
17 regulator-max-microvolt = <3300000>;
18 };
19
20 wl12xx_vmmc2: wl12xx_vmmc2 {
21 compatible = "regulator-fixed";
22 regulator-name = "vw1271";
23 pinctrl-names = "default";
24 pinctrl-0 = <
25 &wl12xx_wkup_pins
26 &wl12xx_core_pins
27 >;
28 regulator-min-microvolt = <1800000>;
29 regulator-max-microvolt = <1800000>;
30 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH >; /* gpio6 */
31 startup-delay-us = <20000>;
32 enable-active-high;
33 };
34
35 wl12xx_vaux2: wl12xx_vaux2 {
36 compatible = "regulator-fixed";
37 regulator-name = "vwl1271_vaux2";
38 regulator-min-microvolt = <1800000>;
39 regulator-max-microvolt = <1800000>;
40 };
41};
42
43&omap3_pmx_wkup {
44
45 wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
46 pinctrl-single,pins = <
47 OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
48 OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */
49 >;
50 };
51};
52
53&omap3_pmx_core {
54
55 phy1_reset_pins: pinmux_hsusb1_phy_reset_pins {
56 pinctrl-single,pins = <
57 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */
58 >;
59 };
60
61 phy2_reset_pins: pinmux_hsusb2_phy_reset_pins {
62 pinctrl-single,pins = <
63 OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */
64 >;
65 };
66
67 otg_drv_vbus: pinmux_otg_drv_vbus {
68 pinctrl-single,pins = <
69 OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50Mhz_clk.usb0_drvvbus */
70 >;
71 };
72
73 mmc2_pins: pinmux_mmc2_pins {
74 pinctrl-single,pins = <
75 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
76 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
77 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
78 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
79 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
80 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
81 >;
82 };
83
84 wl12xx_core_pins: pinmux_wl12xx_core_pins {
85 pinctrl-single,pins = <
86 OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */
87 OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */
88 >;
89 };
90
91 usb_hub_pins: pinmux_usb_hub_pins {
92 pinctrl-single,pins = <
93 OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */
94 >;
95 };
96};
97
98&hsusb1_phy {
99 pinctrl-names = "default";
100 pinctrl-0 = <&phy1_reset_pins>;
101 reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
102};
103
104&hsusb2_phy {
105 pinctrl-names = "default";
106 pinctrl-0 = <&phy2_reset_pins>;
107 reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>;
108};
109
110&davinci_emac {
111 status = "okay";
112};
113
114&davinci_mdio {
115 status = "okay";
116};
117
118&am35x_otg_hs {
119 status = "okay";
120 pinctrl-names = "default";
121 pinctrl-0 = <&otg_drv_vbus>;
122};
123
124&mmc1 {
125 vmmc-supply = <&vmmc>;
126};
127
128&mmc2 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&mmc2_pins>;
131 vmmc-supply = <&wl12xx_vmmc2>;
132 vmmc_aux-supply = <&wl12xx_vaux2>;
133 non-removable;
134 bus-width = <4>;
135 cap-power-off-card;
136};
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts
new file mode 100644
index 000000000000..d1458496520e
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cm-t3530.dts
@@ -0,0 +1,48 @@
1/*
2 * Support for CompuLab CM-T3530
3 */
4/dts-v1/;
5
6#include "omap34xx.dtsi"
7#include "omap3-cm-t3x30.dtsi"
8
9/ {
10 model = "CompuLab CM-T3530";
11 compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
12
13 /* Regulator to trigger the reset signal of the Wifi module */
14 mmc2_sdio_reset: regulator-mmc2-sdio-reset {
15 compatible = "regulator-fixed";
16 regulator-name = "regulator-mmc2-sdio-reset";
17 regulator-min-microvolt = <3300000>;
18 regulator-max-microvolt = <3300000>;
19 gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>;
20 enable-active-high;
21 };
22};
23
24&omap3_pmx_core {
25 mmc2_pins: pinmux_mmc2_pins {
26 pinctrl-single,pins = <
27 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
28 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
29 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
30 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
31 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
32 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
33 OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
34 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
35 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
36 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
37 >;
38 };
39};
40
41&mmc2 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&mmc2_pins>;
44 vmmc-supply = <&mmc2_sdio_reset>;
45 non-removable;
46 bus-width = <4>;
47 cap-power-off-card;
48};
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index 486f4d6c4219..b3f9a50b3bc8 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -32,57 +32,26 @@
32}; 32};
33 33
34&omap3_pmx_core { 34&omap3_pmx_core {
35 mmc1_pins: pinmux_mmc1_pins {
36 pinctrl-single,pins = <
37 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
38 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
39 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
40 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
41 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
42 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
43 >;
44 };
45 35
46 mmc2_pins: pinmux_mmc2_pins { 36 mmc2_pins: pinmux_mmc2_pins {
47 pinctrl-single,pins = < 37 pinctrl-single,pins = <
48 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 38 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
49 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 39 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
50 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 40 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
51 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 41 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
52 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 42 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
53 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 43 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
54 >;
55 };
56
57 smsc1_pins: pinmux_smsc1_pins {
58 pinctrl-single,pins = <
59 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */
60 0x16a (PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */
61 >;
62 };
63
64 uart3_pins: pinmux_uart3_pins {
65 pinctrl-single,pins = <
66 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
67 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
68 >; 44 >;
69 }; 45 };
70 46
71 wl12xx_gpio: pinmux_wl12xx_gpio { 47 wl12xx_gpio: pinmux_wl12xx_gpio {
72 pinctrl-single,pins = < 48 pinctrl-single,pins = <
73 0xb2 (PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ 49 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */
74 0x134 (PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ 50 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */
75 >; 51 >;
76 }; 52 };
77}; 53};
78 54
79&mmc1 {
80 vmmc-supply = <&vmmc1>;
81 bus-width = <4>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&mmc1_pins>;
84};
85
86&mmc2 { 55&mmc2 {
87 pinctrl-names = "default"; 56 pinctrl-names = "default";
88 pinctrl-0 = <&mmc2_pins>; 57 pinctrl-0 = <&mmc2_pins>;
@@ -92,13 +61,3 @@
92 bus-width = <4>; 61 bus-width = <4>;
93 cap-power-off-card; 62 cap-power-off-card;
94}; 63};
95
96&smsc1 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&smsc1_pins>;
99};
100
101&uart3 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&uart3_pins>;
104};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
new file mode 100644
index 000000000000..c671a2299ea8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -0,0 +1,110 @@
1/*
2 * Common support for CompuLab CM-T3x CoMs
3 */
4
5/ {
6
7 memory {
8 device_type = "memory";
9 reg = <0x80000000 0x10000000>; /* 256 MB */
10 };
11
12 leds {
13 compatible = "gpio-leds";
14 pinctrl-names = "default";
15 pinctrl-0 = <&green_led_pins>;
16 ledb {
17 label = "cm-t3x:green";
18 gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */
19 linux,default-trigger = "heartbeat";
20 };
21 };
22
23 /* HS USB Port 1 Power */
24 hsusb1_power: hsusb1_power_reg {
25 compatible = "regulator-fixed";
26 regulator-name = "hsusb1_vbus";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 startup-delay-us = <70000>;
30 };
31
32 /* HS USB Port 2 Power */
33 hsusb2_power: hsusb2_power_reg {
34 compatible = "regulator-fixed";
35 regulator-name = "hsusb2_vbus";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 startup-delay-us = <70000>;
39 };
40
41 /* HS USB Host PHY on PORT 1 */
42 hsusb1_phy: hsusb1_phy {
43 compatible = "usb-nop-xceiv";
44 vcc-supply = <&hsusb1_power>;
45 };
46
47 /* HS USB Host PHY on PORT 2 */
48 hsusb2_phy: hsusb2_phy {
49 compatible = "usb-nop-xceiv";
50 vcc-supply = <&hsusb2_power>;
51 };
52};
53
54&omap3_pmx_core {
55
56 uart3_pins: pinmux_uart3_pins {
57 pinctrl-single,pins = <
58 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
59 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
60 >;
61 };
62
63 mmc1_pins: pinmux_mmc1_pins {
64 pinctrl-single,pins = <
65 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
66 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
67 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
68 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
69 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
70 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
71 >;
72 };
73
74 green_led_pins: pinmux_green_led_pins {
75 pinctrl-single,pins = <
76 OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */
77 >;
78 };
79};
80
81&uart3 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&uart3_pins>;
84};
85
86&mmc1 {
87 pinctrl-names = "default";
88 pinctrl-0 = <&mmc1_pins>;
89 bus-width = <4>;
90};
91
92&mmc3 {
93 status = "disabled";
94};
95
96&i2c1 {
97 clock-frequency = <400000>;
98};
99
100&i2c3 {
101 clock-frequency = <400000>;
102};
103&usbhshost {
104 port1-mode = "ehci-phy";
105 port2-mode = "ehci-phy";
106};
107
108&usbhsehci {
109 phys = <&hsusb1_phy &hsusb2_phy>;
110};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index 3a9f004d8924..d00055809e31 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -1,28 +1,16 @@
1/* 1/*
2 * Common support for CompuLab CM-T3530 and CM-T3730 2 * Common support for CompuLab CM-T3x30 CoMs
3 */ 3 */
4 4
5/ { 5#include "omap3-cm-t3x.dtsi"
6 memory {
7 device_type = "memory";
8 reg = <0x80000000 0x10000000>; /* 256 MB */
9 };
10 6
7/ {
11 cpus { 8 cpus {
12 cpu@0 { 9 cpu@0 {
13 cpu0-supply = <&vcc>; 10 cpu0-supply = <&vcc>;
14 }; 11 };
15 }; 12 };
16 13
17 leds {
18 compatible = "gpio-leds";
19 ledb {
20 label = "cm-t35:green";
21 gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */
22 linux,default-trigger = "heartbeat";
23 };
24 };
25
26 vddvario: regulator-vddvario { 14 vddvario: regulator-vddvario {
27 compatible = "regulator-fixed"; 15 compatible = "regulator-fixed";
28 regulator-name = "vddvario"; 16 regulator-name = "vddvario";
@@ -36,11 +24,40 @@
36 }; 24 };
37}; 25};
38 26
27&omap3_pmx_core {
28
29 smsc1_pins: pinmux_smsc1_pins {
30 pinctrl-single,pins = <
31 OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */
32 OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */
33 >;
34 };
35
36 hsusb0_pins: pinmux_hsusb0_pins {
37 pinctrl-single,pins = <
38 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
39 OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
40 OMAP3_CORE1_IOPAD(0x21a4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
41 OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
42 OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */
43 OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
44 OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
45 OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */
46 OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */
47 OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */
48 OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */
49 OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
50 >;
51 };
52};
53
39&gpmc { 54&gpmc {
40 ranges = <5 0 0x2c000000 0x01000000>; 55 ranges = <5 0 0x2c000000 0x01000000>;
41 56
42 smsc1: ethernet@5,0 { 57 smsc1: ethernet@5,0 {
43 compatible = "smsc,lan9221", "smsc,lan9115"; 58 compatible = "smsc,lan9221", "smsc,lan9115";
59 pinctrl-names = "default";
60 pinctrl-0 = <&smsc1_pins>;
44 interrupt-parent = <&gpio6>; 61 interrupt-parent = <&gpio6>;
45 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 62 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
46 reg = <5 0 0xff>; 63 reg = <5 0 0xff>;
@@ -74,8 +91,6 @@
74}; 91};
75 92
76&i2c1 { 93&i2c1 {
77 clock-frequency = <400000>;
78
79 twl: twl@48 { 94 twl: twl@48 {
80 reg = <0x48>; 95 reg = <0x48>;
81 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 96 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
@@ -86,10 +101,31 @@
86#include "twl4030.dtsi" 101#include "twl4030.dtsi"
87#include "twl4030_omap3.dtsi" 102#include "twl4030_omap3.dtsi"
88 103
89&i2c3 { 104&mmc1 {
90 clock-frequency = <400000>; 105 vmmc-supply = <&vmmc1>;
91}; 106};
92 107
93&twl_gpio { 108&twl_gpio {
94 ti,use-leds; 109 ti,use-leds;
110 /* pullups: BIT(0) */
111 ti,pullups = <0x000001>;
112};
113
114&hsusb1_phy {
115 reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>;
116};
117
118&hsusb2_phy {
119 reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>;
120};
121
122&usb_otg_hs {
123 pinctrl-names = "default";
124 pinctrl-0 = <&hsusb0_pins>;
125 interface-type = <0>;
126 usb-phy = <&usb2_phy>;
127 phys = <&usb2_phy>;
128 phy-names = "usb2-phy";
129 mode = <3>;
130 power = <50>;
95}; 131};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 4665421bb7bc..bf5a515a3247 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -101,20 +101,8 @@
101 status = "disabled"; 101 status = "disabled";
102}; 102};
103 103
104&mcbsp1 { 104&mcbsp2 {
105 status = "disabled"; 105 status = "okay";
106};
107
108&mcbsp3 {
109 status = "disabled";
110};
111
112&mcbsp4 {
113 status = "disabled";
114};
115
116&mcbsp5 {
117 status = "disabled";
118}; 106};
119 107
120&gpmc { 108&gpmc {
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts
index d3b253bbc885..f8ad125fa46f 100644
--- a/arch/arm/boot/dts/omap3-gta04.dts
+++ b/arch/arm/boot/dts/omap3-gta04.dts
@@ -36,6 +36,14 @@
36 gpio-key,wakeup; 36 gpio-key,wakeup;
37 }; 37 };
38 }; 38 };
39
40 sound {
41 compatible = "ti,omap-twl4030";
42 ti,model = "gta04";
43
44 ti,mcbsp = <&mcbsp2>;
45 ti,codec = <&twl_audio>;
46 };
39}; 47};
40 48
41&omap3_pmx_core { 49&omap3_pmx_core {
@@ -80,6 +88,12 @@
80 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 88 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
81 interrupt-parent = <&intc>; 89 interrupt-parent = <&intc>;
82 }; 90 };
91
92 twl_audio: audio {
93 compatible = "ti,twl4030-audio";
94 codec {
95 };
96 };
83}; 97};
84 98
85#include "twl4030.dtsi" 99#include "twl4030.dtsi"
@@ -96,6 +110,14 @@
96 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 110 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
97 }; 111 };
98 112
113 /* accelerometer */
114 bma180@41 {
115 compatible = "bosch,bma180";
116 reg = <0x41>;
117 interrupt-parent = <&gpio3>;
118 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
119 };
120
99 /* leds */ 121 /* leds */
100 tca6507@45 { 122 tca6507@45 {
101 compatible = "ti,tca6507"; 123 compatible = "ti,tca6507";
@@ -124,6 +146,22 @@
124 reg = <0x4>; 146 reg = <0x4>;
125 }; 147 };
126 }; 148 };
149
150 /* compass aka magnetometer */
151 hmc5843@1e {
152 compatible = "honeywell,hmc5843";
153 reg = <0x1e>;
154 };
155
156 /* touchscreen */
157 tsc2007@48 {
158 compatible = "ti,tsc2007";
159 reg = <0x48>;
160 interrupt-parent = <&gpio6>;
161 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
162 gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;
163 ti,x-plate-ohms = <600>;
164 };
127}; 165};
128 166
129&i2c3 { 167&i2c3 {
@@ -148,7 +186,9 @@
148}; 186};
149 187
150&mmc2 { 188&mmc2 {
151 status = "disabled"; 189 vmmc-supply = <&vaux4>;
190 bus-width = <4>;
191 ti,non-removable;
152}; 192};
153 193
154&mmc3 { 194&mmc3 {
@@ -170,3 +210,12 @@
170 pinctrl-0 = <&uart3_pins>; 210 pinctrl-0 = <&uart3_pins>;
171}; 211};
172 212
213&charger {
214 bb_uvolt = <3200000>;
215 bb_uamp = <150>;
216};
217
218&vaux4 {
219 regulator-min-microvolt = <2800000>;
220 regulator-max-microvolt = <3150000>;
221};
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index c17009323520..b97736d98a64 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -170,6 +170,7 @@
170&mcbsp2 { 170&mcbsp2 {
171 pinctrl-names = "default"; 171 pinctrl-names = "default";
172 pinctrl-0 = <&mcbsp2_pins>; 172 pinctrl-0 = <&mcbsp2_pins>;
173 status = "okay";
173}; 174};
174 175
175&mmc1 { 176&mmc1 {
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index f2779ac75872..7abd64f6ae21 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -61,22 +61,63 @@
61 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ 61 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
62 vcc-supply = <&hsusb1_power>; 62 vcc-supply = <&hsusb1_power>;
63 }; 63 };
64
65 tfp410: encoder@0 {
66 compatible = "ti,tfp410";
67 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
68
69 ports {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 port@0 {
74 reg = <0>;
75
76 tfp410_in: endpoint@0 {
77 remote-endpoint = <&dpi_out>;
78 };
79 };
80
81 port@1 {
82 reg = <1>;
83
84 tfp410_out: endpoint@0 {
85 remote-endpoint = <&dvi_connector_in>;
86 };
87 };
88 };
89 };
90
91 dvi0: connector@0 {
92 compatible = "dvi-connector";
93 label = "dvi";
94
95 digital;
96
97 ddc-i2c-bus = <&i2c3>;
98
99 port {
100 dvi_connector_in: endpoint {
101 remote-endpoint = <&tfp410_out>;
102 };
103 };
104 };
64}; 105};
65 106
66&omap3_pmx_core { 107&omap3_pmx_core {
67 pinctrl-names = "default"; 108 pinctrl-names = "default";
68 pinctrl-0 = < 109 pinctrl-0 = <
69 &tfp410_pins 110 &tfp410_pins
70 &dss_pins 111 &dss_dpi_pins
71 >; 112 >;
72 113
73 tfp410_pins: tfp410_dvi_pins { 114 tfp410_pins: pinmux_tfp410_pins {
74 pinctrl-single,pins = < 115 pinctrl-single,pins = <
75 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 116 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
76 >; 117 >;
77 }; 118 };
78 119
79 dss_pins: pinmux_dss_dvi_pins { 120 dss_dpi_pins: pinmux_dss_dpi_pins {
80 pinctrl-single,pins = < 121 pinctrl-single,pins = <
81 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 122 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
82 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 123 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
@@ -226,3 +267,14 @@
226 /* Needed for DSS */ 267 /* Needed for DSS */
227 regulator-name = "vdds_dsi"; 268 regulator-name = "vdds_dsi";
228}; 269};
270
271&dss {
272 status = "ok";
273
274 port {
275 dpi_out: endpoint {
276 remote-endpoint = <&tfp410_in>;
277 data-lines = <24>;
278 };
279 };
280};
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index ddce0d807f70..0abe986a4ecc 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -174,8 +174,20 @@
174}; 174};
175 175
176&mmc1 { 176&mmc1 {
177 /* See 35xx errata 2.1.1.128 in SPRZ278F */
178 compatible = "ti,omap3-pre-es3-hsmmc";
177 vmmc-supply = <&vmmc1>; 179 vmmc-supply = <&vmmc1>;
178 bus-width = <4>; 180 bus-width = <4>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&mmc1_pins>;
183};
184
185&mmc2 {
186 status="disabled";
187};
188
189&mmc3 {
190 status="disabled";
179}; 191};
180 192
181&omap3_pmx_core { 193&omap3_pmx_core {
@@ -209,6 +221,17 @@
209 0x174 (PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ 221 0x174 (PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
210 >; 222 >;
211 }; 223 };
224
225 mmc1_pins: pinmux_mmc1_pins {
226 pinctrl-single,pins = <
227 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
228 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
229 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
230 OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
231 OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
232 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
233 >;
234 };
212}; 235};
213 236
214&usb_otg_hs { 237&usb_otg_hs {
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
new file mode 100644
index 000000000000..6369d9f43ca2
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -0,0 +1,459 @@
1/*
2 * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "omap36xx.dtsi"
11
12/ {
13 model = "INCOstartec LILLY-A83X module (DM3730)";
14 compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
15
16 chosen {
17 bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
18 };
19
20 memory {
21 device_type = "memory";
22 reg = <0x80000000 0x8000000>; /* 128 MB */
23 };
24
25 leds {
26 compatible = "gpio-leds";
27
28 led1 {
29 label = "lilly-a83x::led1";
30 gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
31 linux,default-trigger = "default-on";
32 };
33
34 };
35
36 sound {
37 compatible = "ti,omap-twl4030";
38 ti,model = "lilly-a83x";
39
40 ti,mcbsp = <&mcbsp2>;
41 ti,codec = <&twl_audio>;
42 };
43
44 reg_vcc3: vcc3 {
45 compatible = "regulator-fixed";
46 regulator-name = "VCC3";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
49 regulator-always-on;
50 };
51
52 hsusb1_phy: hsusb1_phy {
53 compatible = "usb-nop-xceiv";
54 vcc-supply = <&reg_vcc3>;
55 };
56};
57
58&omap3_pmx_wkup {
59 pinctrl-names = "default";
60
61 lan9221_pins: pinmux_lan9221_pins {
62 pinctrl-single,pins = <
63 OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */
64 >;
65 };
66
67 tsc2048_pins: pinmux_tsc2048_pins {
68 pinctrl-single,pins = <
69 OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */
70 >;
71 };
72
73 mmc1cd_pins: pinmux_mmc1cd_pins {
74 pinctrl-single,pins = <
75 OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */
76 >;
77 };
78};
79
80&omap3_pmx_core {
81 pinctrl-names = "default";
82
83 uart1_pins: pinmux_uart1_pins {
84 pinctrl-single,pins = <
85 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
86 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */
87 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */
88 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
89 >;
90 };
91
92 uart2_pins: pinmux_uart2_pins {
93 pinctrl-single,pins = <
94 OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */
95 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
96 >;
97 };
98
99 uart3_pins: pinmux_uart3_pins {
100 pinctrl-single,pins = <
101 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
102 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
103 >;
104 };
105
106 i2c1_pins: pinmux_i2c1_pins {
107 pinctrl-single,pins = <
108 OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
109 OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
110 >;
111 };
112
113 i2c2_pins: pinmux_i2c2_pins {
114 pinctrl-single,pins = <
115 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
116 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
117 >;
118 };
119
120 i2c3_pins: pinmux_i2c3_pins {
121 pinctrl-single,pins = <
122 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
123 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
124 >;
125 };
126
127 hsusb1_pins: pinmux_hsusb1_pins {
128 pinctrl-single,pins = <
129
130 /* GPIO 182 controls USB-Hub reset. But USB-Phy its
131 * reset can't be controlled. So we clamp this GPIO to
132 * high (PIN_OFF_OUTPUT_HIGH) to always enable USB-Hub.
133 */
134
135 OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcspi2_cs1.gpio_182 */
136 >;
137 };
138
139 hsusb_otg_pins: pinmux_hsusb_otg_pins {
140 pinctrl-single,pins = <
141 OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
142 OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
143 OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
144 OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
145 OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
146 OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
147 OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
148 OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
149 OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
150 OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
151 OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
152 OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
153 >;
154 };
155
156 mmc1_pins: pinmux_mmc1_pins {
157 pinctrl-single,pins = <
158 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
159 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
160 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
161 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
162 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
163 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
164 >;
165 };
166
167 spi2_pins: pinmux_spi2_pins {
168 pinctrl-single,pins = <
169 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */
170 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */
171 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_somi.mcspi2_somi */
172 OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */
173 >;
174 };
175};
176
177&omap3_pmx_core2 {
178 pinctrl-names = "default";
179 pinctrl-0 = <
180 &hsusb1_2_pins
181 >;
182
183 hsusb1_2_pins: pinmux_hsusb1_2_pins {
184 pinctrl-single,pins = <
185 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
186 OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
187 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */
188 OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */
189 OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */
190 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */
191 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */
192 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */
193 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */
194 OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */
195 OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */
196 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */
197 >;
198 };
199
200 gpio1_pins: pinmux_gpio1_pins {
201 pinctrl-single,pins = <
202 OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */
203 >;
204 };
205
206};
207
208&gpio1 {
209 pinctrl-names = "default";
210 pinctrl-0 = <&gpio1_pins>;
211};
212
213&gpio6 {
214 pinctrl-names = "default";
215 pinctrl-0 = <&hsusb1_pins>;
216};
217
218&i2c1 {
219 clock-frequency = <2600000>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&i2c1_pins>;
222
223 twl: twl@48 {
224 reg = <0x48>;
225 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
226 interrupt-parent = <&intc>;
227
228 twl_audio: audio {
229 compatible = "ti,twl4030-audio";
230 codec {
231 };
232 };
233 };
234};
235
236#include "twl4030.dtsi"
237#include "twl4030_omap3.dtsi"
238
239&twl {
240 vmmc1: regulator-vmmc1 {
241 regulator-always-on;
242 };
243
244 vdd1: regulator-vdd1 {
245 regulator-always-on;
246 };
247
248 vdd2: regulator-vdd2 {
249 regulator-always-on;
250 };
251};
252
253&i2c2 {
254 clock-frequency = <2600000>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&i2c2_pins>;
257};
258
259&i2c3 {
260 clock-frequency = <2600000>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&i2c3_pins>;
263 gpiom1: gpio@20 {
264 compatible = "mcp,mcp23017";
265 gpio-controller;
266 #gpio-cells = <2>;
267 reg = <0x20>;
268 };
269};
270
271&uart1 {
272 pinctrl-names = "default";
273 pinctrl-0 = <&uart1_pins>;
274};
275
276&uart2 {
277 pinctrl-names = "default";
278 pinctrl-0 = <&uart2_pins>;
279};
280
281&uart3 {
282 pinctrl-names = "default";
283 pinctrl-0 = <&uart3_pins>;
284};
285
286&uart4 {
287 status = "disabled";
288};
289
290&mmc1 {
291 cd-gpios = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
292 cd-inverted;
293 vmmc-supply = <&vmmc1>;
294 bus-width = <4>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&mmc1_pins &mmc1cd_pins>;
297 cap-sdio-irq;
298 cap-sd-highspeed;
299 cap-mmc-highspeed;
300};
301
302&mmc2 {
303 status = "disabled";
304};
305
306&mmc3 {
307 status = "disabled";
308};
309
310&mcspi2 {
311 status = "okay";
312 pinctrl-names = "default";
313 pinctrl-0 = <&spi2_pins>;
314
315 tsc2046@0 {
316 reg = <0>; /* CS0 */
317 compatible = "ti,tsc2046";
318 interrupt-parent = <&gpio1>;
319 interrupts = <8 0>; /* boot6 / gpio_8 */
320 spi-max-frequency = <1000000>;
321 pendown-gpio = <&gpio1 8 0>;
322 vcc-supply = <&reg_vcc3>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&tsc2048_pins>;
325
326 ti,x-min = <300>;
327 ti,x-max = <3000>;
328 ti,y-min = <600>;
329 ti,y-max = <3600>;
330 ti,x-plate-ohms = <80>;
331 ti,pressure-max = <255>;
332 ti,swap-xy;
333
334 linux,wakeup;
335 };
336};
337
338&usbhsehci {
339 phys = <&hsusb1_phy>;
340};
341
342&usbhshost {
343 pinctrl-names = "default";
344 pinctrl-0 = <&hsusb1_2_pins>;
345 num-ports = <2>;
346 port1-mode = "ehci-phy";
347};
348
349&usb_otg_hs {
350 pinctrl-names = "default";
351 pinctrl-0 = <&hsusb_otg_pins>;
352 interface-type = <0>;
353 usb-phy = <&usb2_phy>;
354 phys = <&usb2_phy>;
355 phy-names = "usb2-phy";
356 mode = <3>;
357 power = <50>;
358};
359
360&gpmc {
361 ranges = <0 0 0x30000000 0x1000000>,
362 <7 0 0x15000000 0x01000000>;
363
364 nand@0,0 {
365 reg = <0 0 0x1000000>;
366 nand-bus-width = <16>;
367 ti,nand-ecc-opt = "bch8";
368 /* no elm on omap3 */
369
370 gpmc,mux-add-data = <0>;
371 gpmc,device-nand;
372 gpmc,device-width = <2>;
373 gpmc,wait-pin = <0>;
374 gpmc,wait-monitoring-ns = <0>;
375 gpmc,burst-length= <4>;
376 gpmc,cs-on-ns = <0>;
377 gpmc,cs-rd-off-ns = <100>;
378 gpmc,cs-wr-off-ns = <100>;
379 gpmc,adv-on-ns = <0>;
380 gpmc,adv-rd-off-ns = <100>;
381 gpmc,adv-wr-off-ns = <100>;
382 gpmc,oe-on-ns = <5>;
383 gpmc,oe-off-ns = <75>;
384 gpmc,we-on-ns = <5>;
385 gpmc,we-off-ns = <75>;
386 gpmc,rd-cycle-ns = <100>;
387 gpmc,wr-cycle-ns = <100>;
388 gpmc,access-ns = <60>;
389 gpmc,page-burst-access-ns = <5>;
390 gpmc,bus-turnaround-ns = <0>;
391 gpmc,cycle2cycle-samecsen;
392 gpmc,cycle2cycle-delay-ns = <50>;
393 gpmc,wr-data-mux-bus-ns = <75>;
394 gpmc,wr-access-ns = <155>;
395
396 #address-cells = <1>;
397 #size-cells = <1>;
398
399 partition@0 {
400 label = "MLO";
401 reg = <0 0x80000>;
402 };
403
404 partition@0x80000 {
405 label = "u-boot";
406 reg = <0x80000 0x1e0000>;
407 };
408
409 partition@0x260000 {
410 label = "u-boot-environment";
411 reg = <0x260000 0x20000>;
412 };
413
414 partition@0x280000 {
415 label = "kernel";
416 reg = <0x280000 0x500000>;
417 };
418
419 partition@0x780000 {
420 label = "filesystem";
421 reg = <0x780000 0xf880000>;
422 };
423 };
424
425 ethernet@7,0 {
426 compatible = "smsc,lan9221", "smsc,lan9115";
427 bank-width = <2>;
428 gpmc,mux-add-data = <2>;
429 gpmc,cs-on-ns = <10>;
430 gpmc,cs-rd-off-ns = <60>;
431 gpmc,cs-wr-off-ns = <60>;
432 gpmc,adv-on-ns = <0>;
433 gpmc,adv-rd-off-ns = <10>;
434 gpmc,adv-wr-off-ns = <10>;
435 gpmc,oe-on-ns = <10>;
436 gpmc,oe-off-ns = <60>;
437 gpmc,we-on-ns = <10>;
438 gpmc,we-off-ns = <60>;
439 gpmc,rd-cycle-ns = <100>;
440 gpmc,wr-cycle-ns = <100>;
441 gpmc,access-ns = <50>;
442 gpmc,page-burst-access-ns = <5>;
443 gpmc,bus-turnaround-ns = <0>;
444 gpmc,cycle2cycle-delay-ns = <75>;
445 gpmc,wr-data-mux-bus-ns = <15>;
446 gpmc,wr-access-ns = <75>;
447 gpmc,cycle2cycle-samecsen;
448 gpmc,cycle2cycle-diffcsen;
449 vddvario-supply = <&reg_vcc3>;
450 vdd33a-supply = <&reg_vcc3>;
451 reg-io-width = <4>;
452 interrupt-parent = <&gpio5>;
453 interrupts = <1 0x2>;
454 reg = <7 0 0xff>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&lan9221_pins>;
457 phy-mode = "mii";
458 };
459};
diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
new file mode 100644
index 000000000000..834f7c65f62d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
@@ -0,0 +1,170 @@
1/*
2 * Copyright (C) 2014 Christoph Fritz <chf.fritzc@googlemail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9/dts-v1/;
10
11#include "omap3-lilly-a83x.dtsi"
12
13/ {
14 model = "INCOstartec LILLY-DBB056 (DM3730)";
15 compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
16};
17
18&twl {
19 vaux2: regulator-vaux2 {
20 compatible = "ti,twl4030-vaux2";
21 regulator-min-microvolt = <2800000>;
22 regulator-max-microvolt = <2800000>;
23 regulator-always-on;
24 };
25};
26
27&omap3_pmx_core {
28 pinctrl-names = "default";
29 pinctrl-0 = <&lcd_pins>;
30
31 lan9117_pins: pinmux_lan9117_pins {
32 pinctrl-single,pins = <
33 OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */
34 >;
35 };
36
37 gpio4_pins: pinmux_gpio4_pins {
38 pinctrl-single,pins = <
39 OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */
40 >;
41 };
42
43 gpio5_pins: pinmux_gpio5_pins {
44 pinctrl-single,pins = <
45 OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */
46 >;
47 };
48
49 lcd_pins: pinmux_lcd_pins {
50 pinctrl-single,pins = <
51 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
52 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
53 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
54 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
55 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
56 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
57 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
58 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
59 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
60 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
61 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
62 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
63 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
64 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
65 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
66 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
67 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
68 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
69 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
70 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
71 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
72 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
73 >;
74 };
75
76 mmc2_pins: pinmux_mmc2_pins {
77 pinctrl-single,pins = <
78 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
79 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
80 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
81 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
82 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
83 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
84 OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
85 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
86 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
87 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
88 OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 -> wp */
89 OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_164 -> cd */
90 >;
91 };
92
93 spi1_pins: pinmux_spi1_pins {
94 pinctrl-single,pins = <
95 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
96 OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
97 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
98 OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
99 >;
100 };
101};
102
103&gpio4 {
104 pinctrl-names = "default";
105 pinctrl-0 = <&gpio4_pins>;
106};
107
108&gpio5 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&gpio5_pins>;
111};
112
113&mmc2 {
114 status = "okay";
115 bus-width = <4>;
116 vmmc-supply = <&vmmc1>;
117 cd-gpios = <&gpio6 4 0>; /* gpio_164 */
118 wp-gpios = <&gpio6 3 0>; /* gpio_163 */
119 pinctrl-names = "default";
120 pinctrl-0 = <&mmc2_pins>;
121 ti,dual-volt;
122};
123
124&mcspi1 {
125 status = "okay";
126 pinctrl-names = "default";
127 pinctrl-0 = <&spi1_pins>;
128};
129
130&gpmc {
131 ranges = <0 0 0x30000000 0x1000000>, /* nand assigned by COM a83x */
132 <4 0 0x20000000 0x01000000>,
133 <7 0 0x15000000 0x01000000>; /* eth assigend by COM a83x */
134
135 ethernet@4,0 {
136 compatible = "smsc,lan9117", "smsc,lan9115";
137 bank-width = <2>;
138 gpmc,mux-add-data = <2>;
139 gpmc,cs-on-ns = <10>;
140 gpmc,cs-rd-off-ns = <65>;
141 gpmc,cs-wr-off-ns = <65>;
142 gpmc,adv-on-ns = <0>;
143 gpmc,adv-rd-off-ns = <10>;
144 gpmc,adv-wr-off-ns = <10>;
145 gpmc,oe-on-ns = <10>;
146 gpmc,oe-off-ns = <65>;
147 gpmc,we-on-ns = <10>;
148 gpmc,we-off-ns = <65>;
149 gpmc,rd-cycle-ns = <100>;
150 gpmc,wr-cycle-ns = <100>;
151 gpmc,access-ns = <60>;
152 gpmc,page-burst-access-ns = <5>;
153 gpmc,bus-turnaround-ns = <0>;
154 gpmc,cycle2cycle-delay-ns = <75>;
155 gpmc,wr-data-mux-bus-ns = <15>;
156 gpmc,wr-access-ns = <75>;
157 gpmc,cycle2cycle-samecsen;
158 gpmc,cycle2cycle-diffcsen;
159 vddvario-supply = <&reg_vcc3>;
160 vdd33a-supply = <&reg_vcc3>;
161 reg-io-width = <4>;
162 interrupt-parent = <&gpio4>;
163 interrupts = <2 0x2>;
164 reg = <4 0 0xff>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&lan9117_pins>;
167 phy-mode = "mii";
168 smsc,force-internal-phy;
169 };
170};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 0bf40c90faba..1a57b61f5e24 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -74,6 +74,22 @@
74 }; 74 };
75 }; 75 };
76 76
77 isp1704: isp1704 {
78 compatible = "nxp,isp1704";
79 nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
80 usb-phy = <&usb2_phy>;
81 };
82
83 tv: connector {
84 compatible = "composite-connector";
85 label = "tv";
86
87 port {
88 tv_connector_in: endpoint {
89 remote-endpoint = <&venc_out>;
90 };
91 };
92 };
77}; 93};
78 94
79&omap3_pmx_core { 95&omap3_pmx_core {
@@ -140,11 +156,23 @@
140 >; 156 >;
141 }; 157 };
142 158
143 display_pins: pinmux_display_pins { 159 acx565akm_pins: pinmux_acx565akm_pins {
144 pinctrl-single,pins = < 160 pinctrl-single,pins = <
145 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ 161 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
146 >; 162 >;
147 }; 163 };
164
165 dss_sdi_pins: pinmux_dss_sdi_pins {
166 pinctrl-single,pins = <
167 0x0c0 (PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
168 0x0c2 (PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
169 0x0c4 (PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
170 0x0c6 (PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
171
172 0x0d8 (PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
173 0x0da (PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
174 >;
175 };
148}; 176};
149 177
150&i2c1 { 178&i2c1 {
@@ -254,6 +282,61 @@
254 }; 282 };
255}; 283};
256 284
285&twl_keypad {
286 linux,keymap = < 0x00000010 /* KEY_Q */
287 0x00010018 /* KEY_O */
288 0x00020019 /* KEY_P */
289 0x00030033 /* KEY_COMMA */
290 0x0004000e /* KEY_BACKSPACE */
291 0x0006001e /* KEY_A */
292 0x0007001f /* KEY_S */
293
294 0x01000011 /* KEY_W */
295 0x01010020 /* KEY_D */
296 0x01020021 /* KEY_F */
297 0x01030022 /* KEY_G */
298 0x01040023 /* KEY_H */
299 0x01050024 /* KEY_J */
300 0x01060025 /* KEY_K */
301 0x01070026 /* KEY_L */
302
303 0x02000012 /* KEY_E */
304 0x02010034 /* KEY_DOT */
305 0x02020067 /* KEY_UP */
306 0x0203001c /* KEY_ENTER */
307 0x0205002c /* KEY_Z */
308 0x0206002d /* KEY_X */
309 0x0207002e /* KEY_C */
310 0x02080043 /* KEY_F9 */
311
312 0x03000013 /* KEY_R */
313 0x0301002f /* KEY_V */
314 0x03020030 /* KEY_B */
315 0x03030031 /* KEY_N */
316 0x03040032 /* KEY_M */
317 0x03050039 /* KEY_SPACE */
318 0x03060039 /* KEY_SPACE */
319 0x03070069 /* KEY_LEFT */
320
321 0x04000014 /* KEY_T */
322 0x0401006c /* KEY_DOWN */
323 0x0402006a /* KEY_RIGHT */
324 0x0404001d /* KEY_LEFTCTRL */
325 0x04050064 /* KEY_RIGHTALT */
326 0x0406002a /* KEY_LEFTSHIFT */
327 0x04080044 /* KEY_F10 */
328
329 0x05000015 /* KEY_Y */
330 0x05080057 /* KEY_F11 */
331
332 0x06000016 /* KEY_U */
333
334 0x07000017 /* KEY_I */
335 0x07010041 /* KEY_F7 */
336 0x07020042 /* KEY_F8 */
337 >;
338};
339
257&twl_gpio { 340&twl_gpio {
258 ti,pullups = <0x0>; 341 ti,pullups = <0x0>;
259 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ 342 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
@@ -291,6 +374,13 @@
291 DVDD-supply = <&vio>; 374 DVDD-supply = <&vio>;
292 }; 375 };
293 376
377 tsl2563: tsl2563@29 {
378 compatible = "amstaos,tsl2563";
379 reg = <0x29>;
380
381 amstaos,cover-comp-gain = <16>;
382 };
383
294 lp5523: lp5523@32 { 384 lp5523: lp5523@32 {
295 compatible = "national,lp5523"; 385 compatible = "national,lp5523";
296 reg = <0x32>; 386 reg = <0x32>;
@@ -356,6 +446,29 @@
356 compatible = "ti,bq27200"; 446 compatible = "ti,bq27200";
357 reg = <0x55>; 447 reg = <0x55>;
358 }; 448 };
449
450 tpa6130a2: tpa6130a2@60 {
451 compatible = "ti,tpa6130a2";
452 reg = <0x60>;
453
454 Vdd-supply = <&vmmc2>;
455
456 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
457 };
458
459 bq24150a: bq24150a@6b {
460 compatible = "ti,bq24150a";
461 reg = <0x6b>;
462
463 ti,current-limit = <100>;
464 ti,weak-battery-voltage = <3400>;
465 ti,battery-regulation-voltage = <4200>;
466 ti,charge-current = <650>;
467 ti,termination-current = <100>;
468 ti,resistor-sense = <68>;
469
470 ti,usb-charger-detection = <&isp1704>;
471 };
359}; 472};
360 473
361&i2c3 { 474&i2c3 {
@@ -471,13 +584,23 @@
471 spi-max-frequency = <6000000>; 584 spi-max-frequency = <6000000>;
472 reg = <0>; 585 reg = <0>;
473 }; 586 };
474 mipid@2 { 587
475 compatible = "acx565akm"; 588 acx565akm@2 {
589 compatible = "sony,acx565akm";
476 spi-max-frequency = <6000000>; 590 spi-max-frequency = <6000000>;
477 reg = <2>; 591 reg = <2>;
478 592
479 pinctrl-names = "default"; 593 pinctrl-names = "default";
480 pinctrl-0 = <&display_pins>; 594 pinctrl-0 = <&acx565akm_pins>;
595
596 label = "lcd";
597 reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
598
599 port {
600 lcd_in: endpoint {
601 remote-endpoint = <&sdi_out>;
602 };
603 };
481 }; 604 };
482}; 605};
483 606
@@ -503,3 +626,39 @@
503 pinctrl-names = "default"; 626 pinctrl-names = "default";
504 pinctrl-0 = <&uart3_pins>; 627 pinctrl-0 = <&uart3_pins>;
505}; 628};
629
630&dss {
631 status = "ok";
632
633 pinctrl-names = "default";
634 pinctrl-0 = <&dss_sdi_pins>;
635
636 vdds_sdi-supply = <&vaux1>;
637
638 ports {
639 #address-cells = <1>;
640 #size-cells = <0>;
641
642 port@1 {
643 reg = <1>;
644
645 sdi_out: endpoint {
646 remote-endpoint = <&lcd_in>;
647 datapairs = <2>;
648 };
649 };
650 };
651};
652
653&venc {
654 status = "ok";
655
656 vdda-supply = <&vdac>;
657
658 port {
659 venc_out: endpoint {
660 remote-endpoint = <&tv_connector_in>;
661 ti,channels = <1>;
662 };
663 };
664};
diff --git a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi
new file mode 100644
index 000000000000..19d64864a109
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi
@@ -0,0 +1,77 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Alto35 expansion board is manufactured by Gumstix Inc.
11 */
12
13#include "omap3-overo-common-peripherals.dtsi"
14
15#include <dt-bindings/input/input.h>
16
17/ {
18 leds {
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&led_pins>;
22 gpio148 {
23 label = "overo:red:gpio148";
24 gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; /* gpio 148 */
25 };
26 gpio150 {
27 label = "overo:yellow:gpio150";
28 gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio 150 */
29 };
30 gpio151 {
31 label = "overo:blue:gpio151";
32 gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* gpio 151 */
33 };
34 gpio170 {
35 label = "overo:green:gpio170";
36 gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* gpio 170 */
37 };
38 };
39
40 gpio_keys {
41 compatible = "gpio-keys";
42 #address-cells = <1>;
43 #size-cells = <0>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&button_pins>;
46 button0@10 {
47 label = "button0";
48 linux,code = <BTN_0>;
49 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio_10 */
50 gpio-key,wakeup;
51 };
52 };
53};
54
55&omap3_pmx_core {
56 led_pins: pinmux_led_pins {
57 pinctrl-single,pins = <
58 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */
59 OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */
60 OMAP3_CORE1_IOPAD(0x2182, PIN_OUTPUT | MUX_MODE4) /* uart1_rx.gpio_151 */
61 OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
62 >;
63 };
64};
65
66&omap3_pmx_wkup {
67 button_pins: pinmux_button_pins {
68 pinctrl-single,pins = <
69 OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */
70 >;
71 };
72};
73
74&usbhshost {
75 status = "disabled";
76};
77
diff --git a/arch/arm/boot/dts/omap3-overo-alto35.dts b/arch/arm/boot/dts/omap3-overo-alto35.dts
new file mode 100644
index 000000000000..a3249eb7501d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-alto35.dts
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Alto35 expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo.dtsi"
16#include "omap3-overo-alto35-common.dtsi"
17
18/ {
19 model = "OMAP35xx Gumstix Overo on Alto35";
20 compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
21};
22
diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi
new file mode 100644
index 000000000000..d36bf0250a05
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-base.dtsi
@@ -0,0 +1,221 @@
1/*
2 * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * The Gumstix Overo must be combined with an expansion board.
11 */
12
13/ {
14 pwmleds {
15 compatible = "pwm-leds";
16
17 overo {
18 label = "overo:blue:COM";
19 pwms = <&twl_pwmled 1 7812500>;
20 max-brightness = <127>;
21 linux,default-trigger = "mmc0";
22 };
23 };
24
25 sound {
26 compatible = "ti,omap-twl4030";
27 ti,model = "overo";
28
29 ti,mcbsp = <&mcbsp2>;
30 ti,codec = <&twl_audio>;
31 };
32
33 /* HS USB Port 2 Power */
34 hsusb2_power: hsusb2_power_reg {
35 compatible = "regulator-fixed";
36 regulator-name = "hsusb2_vbus";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
39 gpio = <&gpio6 8 0>; /* gpio_168: vbus enable */
40 startup-delay-us = <70000>;
41 enable-active-high;
42 };
43
44 /* HS USB Host PHY on PORT 2 */
45 hsusb2_phy: hsusb2_phy {
46 compatible = "usb-nop-xceiv";
47 reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */
48 vcc-supply = <&hsusb2_power>;
49 };
50
51 /* Regulator to trigger the nPoweron signal of the Wifi module */
52 w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
53 compatible = "regulator-fixed";
54 regulator-name = "regulator-w3cbw003c-npoweron";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */
58 enable-active-high;
59 };
60
61 /* Regulator to trigger the nReset signal of the Wifi module */
62 w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset {
63 pinctrl-names = "default";
64 pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>;
65 compatible = "regulator-fixed";
66 regulator-name = "regulator-w3cbw003c-wifi-nreset";
67 regulator-min-microvolt = <3300000>;
68 regulator-max-microvolt = <3300000>;
69 gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */
70 startup-delay-us = <10000>;
71 };
72
73 /* Regulator to trigger the nReset signal of the Bluetooth module */
74 w3cbw003c_bt_nreset: regulator-w3cbw003c-bt-nreset {
75 compatible = "regulator-fixed";
76 regulator-name = "regulator-w3cbw003c-bt-nreset";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164: BT nReset */
80 startup-delay-us = <10000>;
81 };
82};
83
84&omap3_pmx_core {
85 pinctrl-names = "default";
86 pinctrl-0 = <
87 &hsusb2_pins
88 >;
89
90 uart2_pins: pinmux_uart2_pins {
91 pinctrl-single,pins = <
92 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
93 OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
94 OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
95 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
96 >;
97 };
98
99 i2c1_pins: pinmux_i2c1_pins {
100 pinctrl-single,pins = <
101 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
102 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
103 >;
104 };
105
106 mmc1_pins: pinmux_mmc1_pins {
107 pinctrl-single,pins = <
108 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
109 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
110 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
111 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
112 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
113 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
114 >;
115 };
116
117 mmc2_pins: pinmux_mmc2_pins {
118 pinctrl-single,pins = <
119 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
120 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
121 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
122 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
123 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
124 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
125 >;
126 };
127
128 /* WiFi/BT combo */
129 w3cbw003c_pins: pinmux_w3cbw003c_pins {
130 pinctrl-single,pins = <
131 OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
132 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
133 >;
134 };
135
136 hsusb2_pins: pinmux_hsusb2_pins {
137 pinctrl-single,pins = <
138 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
139 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
140 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
141 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
142 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
143 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
144 OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */
145 OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */
146 >;
147 };
148};
149
150&i2c1 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&i2c1_pins>;
153 clock-frequency = <2600000>;
154
155 twl: twl@48 {
156 reg = <0x48>;
157 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
158 interrupt-parent = <&intc>;
159
160 twl_audio: audio {
161 compatible = "ti,twl4030-audio";
162 codec {
163 };
164 };
165 };
166};
167
168#include "twl4030.dtsi"
169#include "twl4030_omap3.dtsi"
170
171/* i2c2 pins are used for gpio */
172&i2c2 {
173 status = "disabled";
174};
175
176/* on board microSD slot */
177&mmc1 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&mmc1_pins>;
180 vmmc-supply = <&vmmc1>;
181 bus-width = <4>;
182};
183
184/* optional on board WiFi */
185&mmc2 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&mmc2_pins>;
188 vmmc-supply = <&w3cbw003c_npoweron>;
189 vqmmc-supply = <&w3cbw003c_bt_nreset>;
190 vmmc_aux-supply = <&w3cbw003c_wifi_nreset>;
191 bus-width = <4>;
192 cap-sdio-irq;
193 non-removable;
194};
195
196&twl_gpio {
197 ti,use-leds;
198};
199
200&usb_otg_hs {
201 interface-type = <0>;
202 usb-phy = <&usb2_phy>;
203 phys = <&usb2_phy>;
204 phy-names = "usb2-phy";
205 mode = <3>;
206 power = <50>;
207};
208
209&usbhshost {
210 port2-mode = "ehci-phy";
211};
212
213&usbhsehci {
214 phys = <0 &hsusb2_phy>;
215};
216
217&uart2 {
218 pinctrl-names = "default";
219 pinctrl-0 = <&uart2_pins>;
220};
221
diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi
new file mode 100644
index 000000000000..19de6ff79686
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi
@@ -0,0 +1,69 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Chestnut43 expansion board is manufactured by Gumstix Inc.
11 */
12
13#include "omap3-overo-common-peripherals.dtsi"
14
15#include <dt-bindings/input/input.h>
16
17/ {
18 leds {
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&led_pins>;
22 heartbeat {
23 label = "overo:red:gpio21";
24 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
25 linux,default-trigger = "heartbeat";
26 };
27 gpio22 {
28 label = "overo:blue:gpio22";
29 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */
30 };
31 };
32
33 gpio_keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
36 pinctrl-0 = <&button_pins>;
37 #address-cells = <1>;
38 #size-cells = <0>;
39 button0@23 {
40 label = "button0";
41 linux,code = <BTN_0>;
42 gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */
43 gpio-key,wakeup;
44 };
45 button1@14 {
46 label = "button1";
47 linux,code = <BTN_1>;
48 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */
49 gpio-key,wakeup;
50 };
51 };
52};
53
54#include "omap-gpmc-smsc9221.dtsi"
55
56&gpmc {
57 ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */
58
59 ethernet@gpmc {
60 reg = <5 0 0xff>;
61 interrupt-parent = <&gpio6>;
62 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */
63 };
64};
65
66&lis33de {
67 status = "disabled";
68};
69
diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-chestnut43.dts
new file mode 100644
index 000000000000..fe0824aca3c0
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-chestnut43.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Chestnut43 expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo.dtsi"
16#include "omap3-overo-chestnut43-common.dtsi"
17
18/ {
19 model = "OMAP35xx Gumstix Overo on Chestnut43";
20 compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
21};
22
23&omap3_pmx_core2 {
24 led_pins: pinmux_led_pins {
25 pinctrl-single,pins = <
26 OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */
27 OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */
28 >;
29 };
30
31 button_pins: pinmux_button_pins {
32 pinctrl-single,pins = <
33 OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */
34 OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */
35 >;
36 };
37};
38
diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
new file mode 100644
index 000000000000..5831bcc52966
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi
@@ -0,0 +1,94 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...)
11 */
12
13/ {
14 lis33_3v3: lis33-3v3-reg {
15 compatible = "regulator-fixed";
16 regulator-name = "lis33-3v3-reg";
17 regulator-min-microvolt = <3300000>;
18 regulator-max-microvolt = <3300000>;
19 };
20
21 lis33_1v8: lis33-1v8-reg {
22 compatible = "regulator-fixed";
23 regulator-name = "lis33-1v8-reg";
24 regulator-min-microvolt = <1800000>;
25 regulator-max-microvolt = <1800000>;
26 };
27};
28
29&omap3_pmx_core {
30 i2c3_pins: pinmux_i2c3_pins {
31 pinctrl-single,pins = <
32 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
33 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
34 >;
35 };
36
37 uart3_pins: pinmux_uart3_pins {
38 pinctrl-single,pins = <
39 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
40 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
41 >;
42 };
43};
44
45&i2c3 {
46 pinctrl-names = "default";
47 pinctrl-0 = <&i2c3_pins>;
48 clock-frequency = <100000>;
49
50 /* optional 1K EEPROM with revision information */
51 eeprom@51 {
52 compatible = "atmel,24c01";
53 reg = <0x51>;
54 pagesize = <8>;
55 };
56
57 lis33de: lis33de@1d {
58 compatible = "st,lis33de", "st,lis3lv02d";
59 reg = <0x1d>;
60 Vdd-supply = <&lis33_1v8>;
61 Vdd_IO-supply = <&lis33_3v3>;
62
63 st,click-single-x;
64 st,click-single-y;
65 st,click-single-z;
66 st,click-thresh-x = <10>;
67 st,click-thresh-y = <10>;
68 st,click-thresh-z = <10>;
69 st,irq1-click;
70 st,irq2-click;
71 st,wakeup-x-lo;
72 st,wakeup-x-hi;
73 st,wakeup-y-lo;
74 st,wakeup-y-hi;
75 st,wakeup-z-lo;
76 st,wakeup-z-hi;
77 st,min-limit-x = <120>;
78 st,min-limit-y = <120>;
79 st,min-limit-z = <140>;
80 st,max-limit-x = <550>;
81 st,max-limit-y = <550>;
82 st,max-limit-z = <750>;
83 };
84};
85
86&mmc3 {
87 status = "disabled";
88};
89
90&uart3 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&uart3_pins>;
93};
94
diff --git a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi
new file mode 100644
index 000000000000..5e848c26986b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi
@@ -0,0 +1,57 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Gallop43 expansion board is manufactured by Gumstix Inc.
11 */
12
13#include "omap3-overo-common-peripherals.dtsi"
14
15#include <dt-bindings/input/input.h>
16
17/ {
18 leds {
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&led_pins>;
22 heartbeat {
23 label = "overo:red:gpio21";
24 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
25 linux,default-trigger = "heartbeat";
26 };
27 gpio22 {
28 label = "overo:blue:gpio22";
29 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */
30 };
31 };
32
33 gpio_keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
36 pinctrl-0 = <&button_pins>;
37 #address-cells = <1>;
38 #size-cells = <0>;
39 button0@23 {
40 label = "button0";
41 linux,code = <BTN_0>;
42 gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */
43 gpio-key,wakeup;
44 };
45 button1@14 {
46 label = "button1";
47 linux,code = <BTN_1>;
48 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */
49 gpio-key,wakeup;
50 };
51 };
52};
53
54&usbhshost {
55 status = "disabled";
56};
57
diff --git a/arch/arm/boot/dts/omap3-overo-gallop43.dts b/arch/arm/boot/dts/omap3-overo-gallop43.dts
new file mode 100644
index 000000000000..241f5c1914e0
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-gallop43.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Gallop43 expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo.dtsi"
16#include "omap3-overo-gallop43-common.dtsi"
17
18/ {
19 model = "OMAP35xx Gumstix Overo on Gallop43";
20 compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
21};
22
23&omap3_pmx_core2 {
24 led_pins: pinmux_led_pins {
25 pinctrl-single,pins = <
26 OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */
27 OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */
28 >;
29 };
30
31 button_pins: pinmux_button_pins {
32 pinctrl-single,pins = <
33 OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */
34 OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */
35 >;
36 };
37};
38
diff --git a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi
new file mode 100644
index 000000000000..abea232825b9
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi
@@ -0,0 +1,53 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Palo43 expansion board is manufactured by Gumstix Inc.
11 */
12
13#include "omap3-overo-common-peripherals.dtsi"
14
15#include <dt-bindings/input/input.h>
16
17/ {
18 leds {
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&led_pins>;
22 heartbeat {
23 label = "overo:red:gpio21";
24 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
25 linux,default-trigger = "heartbeat";
26 };
27 gpio22 {
28 label = "overo:blue:gpio22";
29 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */
30 };
31 };
32
33 gpio_keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
36 pinctrl-0 = <&button_pins>;
37 #address-cells = <1>;
38 #size-cells = <0>;
39 button0@23 {
40 label = "button0";
41 linux,code = <BTN_0>;
42 gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */
43 gpio-key,wakeup;
44 };
45 button1@14 {
46 label = "button1";
47 linux,code = <BTN_1>;
48 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */
49 gpio-key,wakeup;
50 };
51 };
52};
53
diff --git a/arch/arm/boot/dts/omap3-overo-palo43.dts b/arch/arm/boot/dts/omap3-overo-palo43.dts
new file mode 100644
index 000000000000..cedb103b4b66
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-palo43.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Palo43 expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo.dtsi"
16#include "omap3-overo-palo43-common.dtsi"
17
18/ {
19 model = "OMAP35xx Gumstix Overo on Palo43";
20 compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
21};
22
23&omap3_pmx_core2 {
24 led_pins: pinmux_led_pins {
25 pinctrl-single,pins = <
26 OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */
27 OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */
28 >;
29 };
30
31 button_pins: pinmux_button_pins {
32 pinctrl-single,pins = <
33 OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */
34 OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */
35 >;
36 };
37};
38
diff --git a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
new file mode 100644
index 000000000000..e9cae52afc25
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Alto35 expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo-storm.dtsi"
16#include "omap3-overo-alto35-common.dtsi"
17
18/ {
19 model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35";
20 compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
21};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
new file mode 100644
index 000000000000..7d82fdfd9909
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Chestnut43 expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo-storm.dtsi"
16#include "omap3-overo-chestnut43-common.dtsi"
17
18/ {
19 model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43";
20 compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
21};
22
23&omap3_pmx_core2 {
24 led_pins: pinmux_led_pins {
25 pinctrl-single,pins = <
26 OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */
27 OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */
28 >;
29 };
30
31 button_pins: pinmux_button_pins {
32 pinctrl-single,pins = <
33 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */
34 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */
35 >;
36 };
37};
38
diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
new file mode 100644
index 000000000000..a1b57e0cf37f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Gallop43 expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo-storm.dtsi"
16#include "omap3-overo-gallop43-common.dtsi"
17
18/ {
19 model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43";
20 compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
21};
22
23&omap3_pmx_core2 {
24 led_pins: pinmux_led_pins {
25 pinctrl-single,pins = <
26 OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */
27 OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */
28 >;
29 };
30
31 button_pins: pinmux_button_pins {
32 pinctrl-single,pins = <
33 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */
34 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */
35 >;
36 };
37};
38
diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
new file mode 100644
index 000000000000..b585d8fbc347
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Palo43 expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo-storm.dtsi"
16#include "omap3-overo-palo43-common.dtsi"
17
18/ {
19 model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43";
20 compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
21};
22
23&omap3_pmx_core2 {
24 led_pins: pinmux_led_pins {
25 pinctrl-single,pins = <
26 OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */
27 OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */
28 >;
29 };
30
31 button_pins: pinmux_button_pins {
32 pinctrl-single,pins = <
33 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */
34 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */
35 >;
36 };
37};
38
diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
new file mode 100644
index 000000000000..a0d7fd8369d7
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Summit expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo-storm.dtsi"
16#include "omap3-overo-summit-common.dtsi"
17
18/ {
19 model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit";
20 compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
21};
22
23&omap3_pmx_core2 {
24 led_pins: pinmux_led_pins {
25 pinctrl-single,pins = <
26 OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */
27 >;
28 };
29};
30
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
index 966b5c9cd96a..879383acad87 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
@@ -12,7 +12,7 @@
12 12
13/dts-v1/; 13/dts-v1/;
14 14
15#include "omap36xx.dtsi" 15#include "omap3-overo-storm.dtsi"
16#include "omap3-overo-tobi-common.dtsi" 16#include "omap3-overo-tobi-common.dtsi"
17 17
18/ { 18/ {
diff --git a/arch/arm/boot/dts/omap3-overo-storm.dtsi b/arch/arm/boot/dts/omap3-overo-storm.dtsi
new file mode 100644
index 000000000000..6cb418b4124a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm.dtsi
@@ -0,0 +1,35 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "omap36xx.dtsi"
10#include "omap3-overo-base.dtsi"
11
12&omap3_pmx_core2 {
13 pinctrl-names = "default";
14 pinctrl-0 = <
15 &hsusb2_2_pins
16 >;
17
18 hsusb2_2_pins: pinmux_hsusb2_2_pins {
19 pinctrl-single,pins = <
20 OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
21 OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
22 OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
23 OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
24 OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
25 OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
26 >;
27 };
28
29 w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
30 pinctrl-single,pins = <
31 OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
32 >;
33 };
34};
35
diff --git a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi b/arch/arm/boot/dts/omap3-overo-summit-common.dtsi
new file mode 100644
index 000000000000..999d1cd4a09f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-summit-common.dtsi
@@ -0,0 +1,31 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Summit expansion board is manufactured by Gumstix Inc.
11 */
12
13#include "omap3-overo-common-peripherals.dtsi"
14
15/ {
16 leds {
17 compatible = "gpio-leds";
18 pinctrl-names = "default";
19 pinctrl-0 = <&led_pins>;
20 heartbeat {
21 label = "overo:red:gpio21";
22 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
23 linux,default-trigger = "heartbeat";
24 };
25 };
26};
27
28&lis33de {
29 status = "disabled";
30};
31
diff --git a/arch/arm/boot/dts/omap3-overo-summit.dts b/arch/arm/boot/dts/omap3-overo-summit.dts
new file mode 100644
index 000000000000..69765609455a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-summit.dts
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Summit expansion board is manufactured by Gumstix Inc.
11 */
12
13/dts-v1/;
14
15#include "omap3-overo.dtsi"
16#include "omap3-overo-summit-common.dtsi"
17
18/ {
19 model = "OMAP35xx Gumstix Overo on Summit";
20 compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
21};
22
23&omap3_pmx_core2 {
24 led_pins: pinmux_led_pins {
25 pinctrl-single,pins = <
26 OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */
27 >;
28 };
29};
30
diff --git a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
index 4edc013a91c1..13df50b39442 100644
--- a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
@@ -10,7 +10,7 @@
10 * Tobi expansion board is manufactured by Gumstix Inc. 10 * Tobi expansion board is manufactured by Gumstix Inc.
11 */ 11 */
12 12
13#include "omap3-overo.dtsi" 13#include "omap3-overo-common-peripherals.dtsi"
14 14
15/ { 15/ {
16 leds { 16 leds {
@@ -21,60 +21,21 @@
21 linux,default-trigger = "heartbeat"; 21 linux,default-trigger = "heartbeat";
22 }; 22 };
23 }; 23 };
24
25 vddvario: regulator-vddvario {
26 compatible = "regulator-fixed";
27 regulator-name = "vddvario";
28 regulator-always-on;
29 };
30
31 vdd33a: regulator-vdd33a {
32 compatible = "regulator-fixed";
33 regulator-name = "vdd33a";
34 regulator-always-on;
35 };
36}; 24};
37 25
26#include "omap-gpmc-smsc9221.dtsi"
27
38&gpmc { 28&gpmc {
39 ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ 29 ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */
40 30
41 ethernet@5,0 { 31 ethernet@gpmc {
42 compatible = "smsc,lan9221", "smsc,lan9115";
43 reg = <5 0 0xff>; 32 reg = <5 0 0xff>;
44 bank-width = <2>;
45
46 gpmc,mux-add-data;
47 gpmc,cs-on-ns = <0>;
48 gpmc,cs-rd-off-ns = <42>;
49 gpmc,cs-wr-off-ns = <36>;
50 gpmc,adv-on-ns = <6>;
51 gpmc,adv-rd-off-ns = <12>;
52 gpmc,adv-wr-off-ns = <12>;
53 gpmc,oe-on-ns = <0>;
54 gpmc,oe-off-ns = <42>;
55 gpmc,we-on-ns = <0>;
56 gpmc,we-off-ns = <36>;
57 gpmc,rd-cycle-ns = <60>;
58 gpmc,wr-cycle-ns = <54>;
59 gpmc,access-ns = <36>;
60 gpmc,page-burst-access-ns = <0>;
61 gpmc,bus-turnaround-ns = <0>;
62 gpmc,cycle2cycle-delay-ns = <0>;
63 gpmc,wr-data-mux-bus-ns = <18>;
64 gpmc,wr-access-ns = <42>;
65 gpmc,cycle2cycle-samecsen;
66 gpmc,cycle2cycle-diffcsen;
67
68 interrupt-parent = <&gpio6>; 33 interrupt-parent = <&gpio6>;
69 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ 34 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */
70 reg-io-width = <4>;
71 }; 35 };
72}; 36};
73 37
74&i2c3 { 38&lis33de {
75 clock-frequency = <100000>;
76};
77
78&mmc3 {
79 status = "disabled"; 39 status = "disabled";
80}; 40};
41
diff --git a/arch/arm/boot/dts/omap3-overo-tobi.dts b/arch/arm/boot/dts/omap3-overo-tobi.dts
index de5653e1b5ca..fd6400efcdee 100644
--- a/arch/arm/boot/dts/omap3-overo-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-tobi.dts
@@ -12,7 +12,7 @@
12 12
13/dts-v1/; 13/dts-v1/;
14 14
15#include "omap34xx.dtsi" 15#include "omap3-overo.dtsi"
16#include "omap3-overo-tobi-common.dtsi" 16#include "omap3-overo-tobi-common.dtsi"
17 17
18/ { 18/ {
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index 597099907f8e..69ca7c45bca2 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -1,94 +1,38 @@
1/* 1/*
2 * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group 2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9/* 9#include "omap34xx.dtsi"
10 * The Gumstix Overo must be combined with an expansion board. 10#include "omap3-overo-base.dtsi"
11 */
12 11
13/ { 12&omap3_pmx_core2 {
14 pwmleds { 13 pinctrl-names = "default";
15 compatible = "pwm-leds"; 14 pinctrl-0 = <
16 15 &hsusb2_2_pins
17 overo { 16 >;
18 label = "overo:blue:COM";
19 pwms = <&twl_pwmled 1 7812500>;
20 max-brightness = <127>;
21 linux,default-trigger = "mmc0";
22 };
23 };
24
25 sound {
26 compatible = "ti,omap-twl4030";
27 ti,model = "overo";
28
29 ti,mcbsp = <&mcbsp2>;
30 ti,codec = <&twl_audio>;
31 };
32};
33
34&i2c1 {
35 clock-frequency = <2600000>;
36
37 twl: twl@48 {
38 reg = <0x48>;
39 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
40 interrupt-parent = <&intc>;
41 17
42 twl_audio: audio { 18 hsusb2_2_pins: pinmux_hsusb2_2_pins {
43 compatible = "ti,twl4030-audio"; 19 pinctrl-single,pins = <
44 codec { 20 OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
45 }; 21 OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
46 }; 22 OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
23 OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
24 OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
25 OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
26 >;
47 }; 27 };
48};
49
50#include "twl4030.dtsi"
51#include "twl4030_omap3.dtsi"
52
53/* i2c2 pins are used for gpio */
54&i2c2 {
55 status = "disabled";
56};
57 28
58/* on board microSD slot */ 29 w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
59&mmc1 {
60 vmmc-supply = <&vmmc1>;
61 bus-width = <4>;
62};
63
64/* optional on board WiFi */
65&mmc2 {
66 bus-width = <4>;
67};
68
69&twl_gpio {
70 ti,use-leds;
71};
72
73&usb_otg_hs {
74 interface-type = <0>;
75 usb-phy = <&usb2_phy>;
76 phys = <&usb2_phy>;
77 phy-names = "usb2-phy";
78 mode = <3>;
79 power = <50>;
80};
81
82&omap3_pmx_core {
83 uart3_pins: pinmux_uart3_pins {
84 pinctrl-single,pins = < 30 pinctrl-single,pins = <
85 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 31 OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
86 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
87 >; 32 >;
88 }; 33 };
89}; 34};
90 35
91&uart3 { 36&mcbsp2 {
92 pinctrl-names = "default"; 37 status = "okay";
93 pinctrl-0 = <&uart3_pins>;
94}; 38};
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index b9a2fedce7ee..7909c51b05a5 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -2,11 +2,36 @@
2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
3 */ 3 */
4 4
5/ {
6 vddvario_sb_t35: regulator-vddvario-sb-t35 {
7 compatible = "regulator-fixed";
8 regulator-name = "vddvario";
9 regulator-always-on;
10 };
11
12 vdd33a_sb_t35: regulator-vdd33a-sb-t35 {
13 compatible = "regulator-fixed";
14 regulator-name = "vdd33a";
15 regulator-always-on;
16 };
17};
18
19&omap3_pmx_core {
20 smsc2_pins: pinmux_smsc2_pins {
21 pinctrl-single,pins = <
22 OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */
23 OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */
24 >;
25 };
26};
27
5&gpmc { 28&gpmc {
6 ranges = <4 0 0x2d000000 0x01000000>; 29 ranges = <4 0 0x2d000000 0x01000000>;
7 30
8 smsc2: ethernet@4,0 { 31 smsc2: ethernet@4,0 {
9 compatible = "smsc,lan9221", "smsc,lan9115"; 32 compatible = "smsc,lan9221", "smsc,lan9115";
33 pinctrl-names = "default";
34 pinctrl-0 = <&smsc2_pins>;
10 interrupt-parent = <&gpio3>; 35 interrupt-parent = <&gpio3>;
11 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 36 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
12 reg = <4 0 0xff>; 37 reg = <4 0 0xff>;
@@ -32,8 +57,8 @@
32 gpmc,wr-access-ns = <186>; 57 gpmc,wr-access-ns = <186>;
33 gpmc,cycle2cycle-samecsen; 58 gpmc,cycle2cycle-samecsen;
34 gpmc,cycle2cycle-diffcsen; 59 gpmc,cycle2cycle-diffcsen;
35 vddvario-supply = <&vddvario>; 60 vddvario-supply = <&vddvario_sb_t35>;
36 vdd33a-supply = <&vdd33a>; 61 vdd33a-supply = <&vdd33a_sb_t35>;
37 reg-io-width = <4>; 62 reg-io-width = <4>;
38 smsc,save-mac-address; 63 smsc,save-mac-address;
39 }; 64 };
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
new file mode 100644
index 000000000000..024c9c6c682d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -0,0 +1,43 @@
1/*
2 * Suppport for CompuLab SBC-T3517 with CM-T3517
3 */
4
5#include "omap3-cm-t3517.dts"
6#include "omap3-sb-t35.dtsi"
7
8/ {
9 model = "CompuLab SBC-T3517 with CM-T3517";
10 compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
11};
12
13&omap3_pmx_core {
14 pinctrl-names = "default";
15 pinctrl-0 = <
16 &sb_t35_usb_hub_pins
17 &usb_hub_pins
18 >;
19
20 mmc1_aux_pins: pinmux_mmc1_aux_pins {
21 pinctrl-single,pins = <
22 OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */
23 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */
24 >;
25 };
26
27 sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins {
28 pinctrl-single,pins = <
29 OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */
30 >;
31 };
32};
33
34&mmc1 {
35 pinctrl-names = "default";
36 pinctrl-0 = <
37 &mmc1_pins
38 &mmc1_aux_pins
39 >;
40
41 wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */
42 cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */
43};
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
new file mode 100644
index 000000000000..bbbeea6b1988
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -0,0 +1,36 @@
1/*
2 * Suppport for CompuLab SBC-T3530 with CM-T3530
3 */
4
5#include "omap3-cm-t3530.dts"
6#include "omap3-sb-t35.dtsi"
7
8/ {
9 model = "CompuLab SBC-T3530 with CM-T3530";
10 compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
11};
12
13&omap3_pmx_core {
14 pinctrl-names = "default";
15 pinctrl-0 = <&sb_t35_usb_hub_pins>;
16
17 sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins {
18 pinctrl-single,pins = <
19 OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */
20 >;
21 };
22};
23
24/*
25 * The following ranges correspond to SMSC9x eth chips on CM-T3530 CoM and
26 * SB-T35 baseboard respectively.
27 * This setting includes both chips in SBC-T3530 board device tree.
28 */
29&gpmc {
30 ranges = <5 0 0x2c000000 0x01000000>,
31 <4 0 0x2d000000 0x01000000>;
32};
33
34&mmc1 {
35 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
36};
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index c119bd545053..08e4a7086f22 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -10,21 +10,18 @@
10 compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
11}; 11};
12 12
13&gpmc { 13&omap3_pmx_core {
14 ranges = <5 0 0x2c000000 0x01000000>,
15 <4 0 0x2d000000 0x01000000>;
16};
17
18&smsc2 {
19 pinctrl-names = "default"; 14 pinctrl-names = "default";
20 pinctrl-0 = <&smsc2_pins>; 15 pinctrl-0 = <&sb_t35_usb_hub_pins>;
21};
22 16
23&omap3_pmx_core { 17 sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins {
24 smsc2_pins: pinmux_smsc2_pins {
25 pinctrl-single,pins = < 18 pinctrl-single,pins = <
26 0x86 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ 19 OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */
27 0xa2 (PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */
28 >; 20 >;
29 }; 21 };
30}; \ No newline at end of file 22};
23
24&gpmc {
25 ranges = <5 0 0x2c000000 0x01000000>,
26 <4 0 0x2d000000 0x01000000>;
27};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index a5fc83b9c835..5e5790f631eb 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -35,6 +35,11 @@
35 compatible = "arm,cortex-a8"; 35 compatible = "arm,cortex-a8";
36 device_type = "cpu"; 36 device_type = "cpu";
37 reg = <0x0>; 37 reg = <0x0>;
38
39 clocks = <&dpll1_ck>;
40 clock-names = "cpu";
41
42 clock-latency = <300000>; /* From omap-cpufreq driver */
38 }; 43 };
39 }; 44 };
40 45
@@ -176,6 +181,22 @@
176 pinctrl-single,function-mask = <0xff1f>; 181 pinctrl-single,function-mask = <0xff1f>;
177 }; 182 };
178 183
184 omap3_scm_general: tisyscon@48002270 {
185 compatible = "syscon";
186 reg = <0x48002270 0x2f0>;
187 };
188
189 pbias_regulator: pbias_regulator {
190 compatible = "ti,pbias-omap";
191 reg = <0x2b0 0x4>;
192 syscon = <&omap3_scm_general>;
193 pbias_mmc_reg: pbias_mmc_omap2430 {
194 regulator-name = "pbias_mmc_omap2430";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3000000>;
197 };
198 };
199
179 gpio1: gpio@48310000 { 200 gpio1: gpio@48310000 {
180 compatible = "ti,omap3-gpio"; 201 compatible = "ti,omap3-gpio";
181 reg = <0x48310000 0x200>; 202 reg = <0x48310000 0x200>;
@@ -390,6 +411,7 @@
390 ti,dual-volt; 411 ti,dual-volt;
391 dmas = <&sdma 61>, <&sdma 62>; 412 dmas = <&sdma 61>, <&sdma 62>;
392 dma-names = "tx", "rx"; 413 dma-names = "tx", "rx";
414 pbias-supply = <&pbias_mmc_reg>;
393 }; 415 };
394 416
395 mmc2: mmc@480b4000 { 417 mmc2: mmc@480b4000 {
@@ -411,10 +433,19 @@
411 }; 433 };
412 434
413 mmu_isp: mmu@480bd400 { 435 mmu_isp: mmu@480bd400 {
414 compatible = "ti,omap3-mmu-isp"; 436 compatible = "ti,omap2-iommu";
415 ti,hwmods = "mmu_isp";
416 reg = <0x480bd400 0x80>; 437 reg = <0x480bd400 0x80>;
417 interrupts = <8>; 438 interrupts = <24>;
439 ti,hwmods = "mmu_isp";
440 ti,#tlb-entries = <8>;
441 };
442
443 mmu_iva: mmu@5d000000 {
444 compatible = "ti,omap2-iommu";
445 reg = <0x5d000000 0x80>;
446 interrupts = <28>;
447 ti,hwmods = "mmu_iva";
448 status = "disabled";
418 }; 449 };
419 450
420 wdt2: wdt@48314000 { 451 wdt2: wdt@48314000 {
@@ -436,6 +467,7 @@
436 dmas = <&sdma 31>, 467 dmas = <&sdma 31>,
437 <&sdma 32>; 468 <&sdma 32>;
438 dma-names = "tx", "rx"; 469 dma-names = "tx", "rx";
470 status = "disabled";
439 }; 471 };
440 472
441 mcbsp2: mcbsp@49022000 { 473 mcbsp2: mcbsp@49022000 {
@@ -453,6 +485,7 @@
453 dmas = <&sdma 33>, 485 dmas = <&sdma 33>,
454 <&sdma 34>; 486 <&sdma 34>;
455 dma-names = "tx", "rx"; 487 dma-names = "tx", "rx";
488 status = "disabled";
456 }; 489 };
457 490
458 mcbsp3: mcbsp@49024000 { 491 mcbsp3: mcbsp@49024000 {
@@ -470,6 +503,7 @@
470 dmas = <&sdma 17>, 503 dmas = <&sdma 17>,
471 <&sdma 18>; 504 <&sdma 18>;
472 dma-names = "tx", "rx"; 505 dma-names = "tx", "rx";
506 status = "disabled";
473 }; 507 };
474 508
475 mcbsp4: mcbsp@49026000 { 509 mcbsp4: mcbsp@49026000 {
@@ -485,6 +519,7 @@
485 dmas = <&sdma 19>, 519 dmas = <&sdma 19>,
486 <&sdma 20>; 520 <&sdma 20>;
487 dma-names = "tx", "rx"; 521 dma-names = "tx", "rx";
522 status = "disabled";
488 }; 523 };
489 524
490 mcbsp5: mcbsp@48096000 { 525 mcbsp5: mcbsp@48096000 {
@@ -500,6 +535,7 @@
500 dmas = <&sdma 21>, 535 dmas = <&sdma 21>,
501 <&sdma 22>; 536 <&sdma 22>;
502 dma-names = "tx", "rx"; 537 dma-names = "tx", "rx";
538 status = "disabled";
503 }; 539 };
504 540
505 sham: sham@480c3000 { 541 sham: sham@480c3000 {
@@ -634,14 +670,14 @@
634 ranges; 670 ranges;
635 671
636 usbhsohci: ohci@48064400 { 672 usbhsohci: ohci@48064400 {
637 compatible = "ti,ohci-omap3", "usb-ohci"; 673 compatible = "ti,ohci-omap3";
638 reg = <0x48064400 0x400>; 674 reg = <0x48064400 0x400>;
639 interrupt-parent = <&intc>; 675 interrupt-parent = <&intc>;
640 interrupts = <76>; 676 interrupts = <76>;
641 }; 677 };
642 678
643 usbhsehci: ehci@48064800 { 679 usbhsehci: ehci@48064800 {
644 compatible = "ti,ehci-omap", "usb-ehci"; 680 compatible = "ti,ehci-omap";
645 reg = <0x48064800 0x400>; 681 reg = <0x48064800 0x400>;
646 interrupt-parent = <&intc>; 682 interrupt-parent = <&intc>;
647 interrupts = <77>; 683 interrupts = <77>;
@@ -669,6 +705,58 @@
669 num-eps = <16>; 705 num-eps = <16>;
670 ram-bits = <12>; 706 ram-bits = <12>;
671 }; 707 };
708
709 dss: dss@48050000 {
710 compatible = "ti,omap3-dss";
711 reg = <0x48050000 0x200>;
712 status = "disabled";
713 ti,hwmods = "dss_core";
714 clocks = <&dss1_alwon_fck>;
715 clock-names = "fck";
716 #address-cells = <1>;
717 #size-cells = <1>;
718 ranges;
719
720 dispc@48050400 {
721 compatible = "ti,omap3-dispc";
722 reg = <0x48050400 0x400>;
723 interrupts = <25>;
724 ti,hwmods = "dss_dispc";
725 clocks = <&dss1_alwon_fck>;
726 clock-names = "fck";
727 };
728
729 dsi: encoder@4804fc00 {
730 compatible = "ti,omap3-dsi";
731 reg = <0x4804fc00 0x200>,
732 <0x4804fe00 0x40>,
733 <0x4804ff00 0x20>;
734 reg-names = "proto", "phy", "pll";
735 interrupts = <25>;
736 status = "disabled";
737 ti,hwmods = "dss_dsi1";
738 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
739 clock-names = "fck", "sys_clk";
740 };
741
742 rfbi: encoder@48050800 {
743 compatible = "ti,omap3-rfbi";
744 reg = <0x48050800 0x100>;
745 status = "disabled";
746 ti,hwmods = "dss_rfbi";
747 clocks = <&dss1_alwon_fck>, <&dss_ick>;
748 clock-names = "fck", "ick";
749 };
750
751 venc: encoder@48050c00 {
752 compatible = "ti,omap3-venc";
753 reg = <0x48050c00 0x100>;
754 status = "disabled";
755 ti,hwmods = "dss_venc";
756 clocks = <&dss_tv_fck>;
757 clock-names = "fck";
758 };
759 };
672 }; 760 };
673}; 761};
674 762
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 281914ed0151..02f69f4a8fd3 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -34,6 +34,10 @@
34&mmc1 { 34&mmc1 {
35 vmmc-supply = <&vmmc1>; 35 vmmc-supply = <&vmmc1>;
36 vmmc_aux-supply = <&vsim>; 36 vmmc_aux-supply = <&vsim>;
37 /*
38 * S6-3 must be in ON position for 8 bit mode to function
39 * Else, use 4 bit mode
40 */
37 bus-width = <8>; 41 bus-width = <8>;
38}; 42};
39 43
@@ -103,9 +107,8 @@
103 #address-cells = <1>; 107 #address-cells = <1>;
104 #size-cells = <1>; 108 #size-cells = <1>;
105 reg = <1 0 0x08000000>; 109 reg = <1 0 0x08000000>;
110 ti,nand-ecc-opt = "ham1";
106 nand-bus-width = <8>; 111 nand-bus-width = <8>;
107
108 ti,nand-ecc-opt = "sw";
109 gpmc,cs-on-ns = <0>; 112 gpmc,cs-on-ns = <0>;
110 gpmc,cs-rd-off-ns = <36>; 113 gpmc,cs-rd-off-ns = <36>;
111 gpmc,cs-wr-off-ns = <36>; 114 gpmc,cs-wr-off-ns = <36>;
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
index 02f6c7fabbec..4c22f3a7f813 100644
--- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -82,16 +82,16 @@
82 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; 82 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
83 }; 83 };
84 84
85 ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 { 85 ssi_ssr_fck: ssi_ssr_fck_3430es1 {
86 #clock-cells = <0>; 86 #clock-cells = <0>;
87 compatible = "ti,composite-clock"; 87 compatible = "ti,composite-clock";
88 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; 88 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
89 }; 89 };
90 90
91 ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 { 91 ssi_sst_fck: ssi_sst_fck_3430es1 {
92 #clock-cells = <0>; 92 #clock-cells = <0>;
93 compatible = "fixed-factor-clock"; 93 compatible = "fixed-factor-clock";
94 clocks = <&ssi_ssr_fck_3430es1>; 94 clocks = <&ssi_ssr_fck>;
95 clock-mult = <1>; 95 clock-mult = <1>;
96 clock-div = <2>; 96 clock-div = <2>;
97 }; 97 };
@@ -120,7 +120,7 @@
120 clock-div = <1>; 120 clock-div = <1>;
121 }; 121 };
122 122
123 ssi_ick_3430es1: ssi_ick_3430es1 { 123 ssi_ick: ssi_ick_3430es1 {
124 #clock-cells = <0>; 124 #clock-cells = <0>;
125 compatible = "ti,omap3-no-wait-interface-clock"; 125 compatible = "ti,omap3-no-wait-interface-clock";
126 clocks = <&ssi_l4_ick>; 126 clocks = <&ssi_l4_ick>;
@@ -152,7 +152,7 @@
152 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; 152 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
153 }; 153 };
154 154
155 dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 { 155 dss1_alwon_fck: dss1_alwon_fck_3430es1 {
156 #clock-cells = <0>; 156 #clock-cells = <0>;
157 compatible = "ti,gate-clock"; 157 compatible = "ti,gate-clock";
158 clocks = <&dpll4_m4x2_ck>; 158 clocks = <&dpll4_m4x2_ck>;
@@ -161,7 +161,7 @@
161 ti,set-rate-parent; 161 ti,set-rate-parent;
162 }; 162 };
163 163
164 dss_ick_3430es1: dss_ick_3430es1 { 164 dss_ick: dss_ick_3430es1 {
165 #clock-cells = <0>; 165 #clock-cells = <0>;
166 compatible = "ti,omap3-no-wait-interface-clock"; 166 compatible = "ti,omap3-no-wait-interface-clock";
167 clocks = <&l4_ick>; 167 clocks = <&l4_ick>;
@@ -184,7 +184,7 @@
184 dss_clkdm: dss_clkdm { 184 dss_clkdm: dss_clkdm {
185 compatible = "ti,clockdomain"; 185 compatible = "ti,clockdomain";
186 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, 186 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
187 <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>; 187 <&dss1_alwon_fck>, <&dss_ick>;
188 }; 188 };
189 189
190 d2d_clkdm: d2d_clkdm { 190 d2d_clkdm: d2d_clkdm {
@@ -203,6 +203,6 @@
203 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, 203 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
204 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, 204 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
205 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, 205 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
206 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>; 206 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
207 }; 207 };
208}; 208};
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
index af9ae5346bf2..080fb3f4e429 100644
--- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -160,7 +160,7 @@
160 ti,bit-shift = <30>; 160 ti,bit-shift = <30>;
161 }; 161 };
162 162
163 dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 { 163 dss1_alwon_fck: dss1_alwon_fck_3430es2 {
164 #clock-cells = <0>; 164 #clock-cells = <0>;
165 compatible = "ti,dss-gate-clock"; 165 compatible = "ti,dss-gate-clock";
166 clocks = <&dpll4_m4x2_ck>; 166 clocks = <&dpll4_m4x2_ck>;
@@ -169,7 +169,7 @@
169 ti,set-rate-parent; 169 ti,set-rate-parent;
170 }; 170 };
171 171
172 dss_ick_3430es2: dss_ick_3430es2 { 172 dss_ick: dss_ick_3430es2 {
173 #clock-cells = <0>; 173 #clock-cells = <0>;
174 compatible = "ti,omap3-dss-interface-clock"; 174 compatible = "ti,omap3-dss-interface-clock";
175 clocks = <&l4_ick>; 175 clocks = <&l4_ick>;
@@ -216,7 +216,7 @@
216 dss_clkdm: dss_clkdm { 216 dss_clkdm: dss_clkdm {
217 compatible = "ti,clockdomain"; 217 compatible = "ti,clockdomain";
218 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, 218 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
219 <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; 219 <&dss1_alwon_fck>, <&dss_ick>;
220 }; 220 };
221 221
222 core_l4_clkdm: core_l4_clkdm { 222 core_l4_clkdm: core_l4_clkdm {
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
index 2fcf253b677c..6b5280d04a0e 100644
--- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -70,6 +70,26 @@
70 }; 70 };
71}; 71};
72 72
73&dpll4_m2x2_mul_ck {
74 clock-mult = <1>;
75};
76
77&dpll4_m3x2_mul_ck {
78 clock-mult = <1>;
79};
80
81&dpll4_m4x2_mul_ck {
82 ti,clock-mult = <1>;
83};
84
85&dpll4_m5x2_mul_ck {
86 clock-mult = <1>;
87};
88
89&dpll4_m6x2_mul_ck {
90 clock-mult = <1>;
91};
92
73&cm_clockdomains { 93&cm_clockdomains {
74 dpll4_clkdm: dpll4_clkdm { 94 dpll4_clkdm: dpll4_clkdm {
75 compatible = "ti,clockdomain"; 95 compatible = "ti,clockdomain";
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
index 8ed475dd63c9..877318c28364 100644
--- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -25,16 +25,16 @@
25 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; 25 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
26 }; 26 };
27 27
28 ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 { 28 ssi_ssr_fck: ssi_ssr_fck_3430es2 {
29 #clock-cells = <0>; 29 #clock-cells = <0>;
30 compatible = "ti,composite-clock"; 30 compatible = "ti,composite-clock";
31 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; 31 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
32 }; 32 };
33 33
34 ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 { 34 ssi_sst_fck: ssi_sst_fck_3430es2 {
35 #clock-cells = <0>; 35 #clock-cells = <0>;
36 compatible = "fixed-factor-clock"; 36 compatible = "fixed-factor-clock";
37 clocks = <&ssi_ssr_fck_3430es2>; 37 clocks = <&ssi_ssr_fck>;
38 clock-mult = <1>; 38 clock-mult = <1>;
39 clock-div = <2>; 39 clock-div = <2>;
40 }; 40 };
@@ -55,7 +55,7 @@
55 clock-div = <1>; 55 clock-div = <1>;
56 }; 56 };
57 57
58 ssi_ick_3430es2: ssi_ick_3430es2 { 58 ssi_ick: ssi_ick_3430es2 {
59 #clock-cells = <0>; 59 #clock-cells = <0>;
60 compatible = "ti,omap3-ssi-interface-clock"; 60 compatible = "ti,omap3-ssi-interface-clock";
61 clocks = <&ssi_l4_ick>; 61 clocks = <&ssi_l4_ick>;
@@ -193,6 +193,6 @@
193 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, 193 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
194 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, 194 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
195 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, 195 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
196 <&ssi_ick_3430es2>; 196 <&ssi_ick>;
197 }; 197 };
198}; 198};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 7e8dee9175d6..22cf4647087e 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -39,6 +39,26 @@
39 clock-frequency = <48000000>; 39 clock-frequency = <48000000>;
40 }; 40 };
41 41
42 abb_mpu_iva: regulator-abb-mpu {
43 compatible = "ti,abb-v1";
44 regulator-name = "abb_mpu_iva";
45 #address-cell = <0>;
46 #size-cells = <0>;
47 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
48 reg-names = "base-address", "int-address";
49 ti,tranxdone-status-mask = <0x4000000>;
50 clocks = <&sys_ck>;
51 ti,settling-time = <30>;
52 ti,clock-cycles = <8>;
53 ti,abb_info = <
54 /*uV ABB efuse rbb_m fbb_m vset_m*/
55 1012500 0 0 0 0 0
56 1200000 0 0 0 0 0
57 1325000 0 0 0 0 0
58 1375000 1 0 0 0 0
59 >;
60 };
61
42 omap3_pmx_core2: pinmux@480025a0 { 62 omap3_pmx_core2: pinmux@480025a0 {
43 compatible = "ti,omap3-padconf", "pinctrl-single"; 63 compatible = "ti,omap3-padconf", "pinctrl-single";
44 reg = <0x480025a0 0x5c>; 64 reg = <0x480025a0 0x5c>;
@@ -52,7 +72,13 @@
52 }; 72 };
53}; 73};
54 74
55/include/ "omap36xx-clocks.dtsi" 75/* OMAP3630 needs dss_96m_fck for VENC */
76&venc {
77 clocks = <&dss_tv_fck>, <&dss_96m_fck>;
78 clock-names = "fck", "tv_dac_clk";
79};
80
56/include/ "omap34xx-omap36xx-clocks.dtsi" 81/include/ "omap34xx-omap36xx-clocks.dtsi"
57/include/ "omap36xx-omap3430es2plus-clocks.dtsi" 82/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
58/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" 83/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
84/include/ "omap36xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index cb04d4b37e7f..12be2b35dae9 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -425,10 +425,11 @@
425 425
426 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { 426 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
427 #clock-cells = <0>; 427 #clock-cells = <0>;
428 compatible = "fixed-factor-clock"; 428 compatible = "ti,fixed-factor-clock";
429 clocks = <&dpll4_m4_ck>; 429 clocks = <&dpll4_m4_ck>;
430 clock-mult = <2>; 430 ti,clock-mult = <2>;
431 clock-div = <1>; 431 ti,clock-div = <1>;
432 ti,set-rate-parent;
432 }; 433 };
433 434
434 dpll4_m4x2_ck: dpll4_m4x2_ck { 435 dpll4_m4x2_ck: dpll4_m4x2_ck {
@@ -438,6 +439,7 @@
438 ti,bit-shift = <0x1d>; 439 ti,bit-shift = <0x1d>;
439 reg = <0x0d00>; 440 reg = <0x0d00>;
440 ti,set-bit-to-disable; 441 ti,set-bit-to-disable;
442 ti,set-rate-parent;
441 }; 443 };
442 444
443 dpll4_m5_ck: dpll4_m5_ck { 445 dpll4_m5_ck: dpll4_m5_ck {
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts
new file mode 100644
index 000000000000..96f51d870812
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts
@@ -0,0 +1,146 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "omap4-duovero.dtsi"
11
12#include <dt-bindings/input/input.h>
13
14/ {
15 model = "OMAP4430 Gumstix Duovero on Parlor";
16 compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
17
18 leds {
19 compatible = "gpio-leds";
20 led0 {
21 label = "duovero:blue:led0";
22 gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio_122 */
23 linux,default-trigger = "heartbeat";
24 };
25 };
26
27 gpio_keys {
28 compatible = "gpio-keys";
29 #address-cells = <1>;
30 #size-cells = <0>;
31 button0@121 {
32 label = "button0";
33 linux,code = <BTN_0>;
34 gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */
35 gpio-key,wakeup;
36 };
37 };
38};
39
40&omap4_pmx_core {
41 pinctrl-0 = <
42 &led_pins
43 &button_pins
44 &smsc_pins
45 >;
46
47 led_pins: pinmux_led_pins {
48 pinctrl-single,pins = <
49 0xd6 (PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */
50 >;
51 };
52
53 button_pins: pinmux_button_pins {
54 pinctrl-single,pins = <
55 0xd4 (PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */
56 >;
57 };
58
59 i2c2_pins: pinmux_i2c2_pins {
60 pinctrl-single,pins = <
61 0xe6 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
62 0xe8 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
63 >;
64 };
65
66 i2c3_pins: pinmux_i2c3_pins {
67 pinctrl-single,pins = <
68 0xea (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
69 0xec (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
70 >;
71 };
72
73 smsc_pins: pinmux_smsc_pins {
74 pinctrl-single,pins = <
75 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */
76 0x2a (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */
77 0x30 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */
78 >;
79 };
80};
81
82&i2c2 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&i2c2_pins>;
85
86 clock-frequency = <400000>;
87};
88
89&i2c3 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&i2c3_pins>;
92
93 clock-frequency = <100000>;
94
95 /* optional 1K EEPROM with revision information */
96 eeprom@51 {
97 compatible = "atmel,24c01";
98 reg = <0x51>;
99 pagesize = <8>;
100 };
101};
102
103&mmc3 {
104 status = "disabled";
105};
106
107#include "omap-gpmc-smsc911x.dtsi"
108
109&gpmc {
110 ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */
111
112 ethernet@gpmc {
113 reg = <5 0 0xff>;
114 interrupt-parent = <&gpio2>;
115 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */
116
117 phy-mode = "mii";
118
119 gpmc,cs-on-ns = <10>;
120 gpmc,cs-rd-off-ns = <50>;
121 gpmc,cs-wr-off-ns = <50>;
122 gpmc,adv-on-ns = <0>;
123 gpmc,adv-rd-off-ns = <10>;
124 gpmc,adv-wr-off-ns = <10>;
125 gpmc,oe-on-ns = <15>;
126 gpmc,oe-off-ns = <50>;
127 gpmc,we-on-ns = <15>;
128 gpmc,we-off-ns = <50>;
129 gpmc,rd-cycle-ns = <50>;
130 gpmc,wr-cycle-ns = <50>;
131 gpmc,access-ns = <50>;
132 gpmc,page-burst-access-ns = <0>;
133 gpmc,bus-turnaround-ns = <35>;
134 gpmc,cycle2cycle-delay-ns = <35>;
135 gpmc,wr-data-mux-bus-ns = <35>;
136 gpmc,wr-access-ns = <50>;
137
138 gpmc,mux-add-data = <2>;
139 gpmc,sync-read;
140 gpmc,sync-write;
141 gpmc,clk-activation-ns = <5>;
142 gpmc,sync-clk-ps = <20000>;
143 };
144};
145
146
diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi
new file mode 100644
index 000000000000..a514791154eb
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-duovero.dtsi
@@ -0,0 +1,252 @@
1/*
2 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "omap443x.dtsi"
10
11/ {
12 model = "Gumstix Duovero";
13 compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
14
15 memory {
16 device_type = "memory";
17 reg = <0x80000000 0x40000000>; /* 1 GB */
18 };
19
20 sound {
21 compatible = "ti,abe-twl6040";
22 ti,model = "DuoVero";
23
24 ti,mclk-freq = <38400000>;
25
26 ti,mcpdm = <&mcpdm>;
27
28 ti,twl6040 = <&twl6040>;
29
30 /* Audio routing */
31 ti,audio-routing =
32 "Headset Stereophone", "HSOL",
33 "Headset Stereophone", "HSOR",
34 "HSMIC", "Headset Mic",
35 "Headset Mic", "Headset Mic Bias";
36 };
37
38 /* HS USB Host PHY on PORT 1 */
39 hsusb1_phy: hsusb1_phy {
40 compatible = "usb-nop-xceiv";
41 reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
42
43 pinctrl-names = "default";
44 pinctrl-0 = <&hsusb1phy_pins>;
45
46 clocks = <&auxclk3_ck>;
47 clock-names = "main_clk";
48 clock-frequency = <19200000>;
49 };
50
51 /* regulator for w2cbw0015 on sdio5 */
52 w2cbw0015_vmmc: w2cbw0015_vmmc {
53 pinctrl-names = "default";
54 pinctrl-0 = <&w2cbw0015_pins>;
55 compatible = "regulator-fixed";
56 regulator-name = "w2cbw0015";
57 regulator-min-microvolt = <3000000>;
58 regulator-max-microvolt = <3000000>;
59 gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; /* gpio_43 */
60 startup-delay-us = <70000>;
61 enable-active-high;
62 regulator-boot-on;
63 };
64};
65
66&omap4_pmx_core {
67 pinctrl-names = "default";
68 pinctrl-0 = <
69 &twl6040_pins
70 &mcpdm_pins
71 &mcbsp1_pins
72 &hsusbb1_pins
73 >;
74
75 twl6040_pins: pinmux_twl6040_pins {
76 pinctrl-single,pins = <
77 0x126 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */
78 0x160 (PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
79 >;
80 };
81
82 mcpdm_pins: pinmux_mcpdm_pins {
83 pinctrl-single,pins = <
84 0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */
85 0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */
86 0xca (PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */
87 0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */
88 0xce (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */
89 >;
90 };
91
92 mcbsp1_pins: pinmux_mcbsp1_pins {
93 pinctrl-single,pins = <
94 0xbe (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
95 0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */
96 0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */
97 0xc4 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
98 >;
99 };
100
101 hsusbb1_pins: pinmux_hsusbb1_pins {
102 pinctrl-single,pins = <
103 0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
104 0x84 (PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
105 0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
106 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
107 0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
108 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
109 0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
110 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
111 0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
112 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
113 0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
114 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
115 >;
116 };
117
118 hsusb1phy_pins: pinmux_hsusb1phy_pins {
119 pinctrl-single,pins = <
120 0x4c (PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */
121 >;
122 };
123
124 w2cbw0015_pins: pinmux_w2cbw0015_pins {
125 pinctrl-single,pins = <
126 0x26 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */
127 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
128 >;
129 };
130
131 i2c1_pins: pinmux_i2c1_pins {
132 pinctrl-single,pins = <
133 0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
134 0xe4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
135 >;
136 };
137
138 i2c4_pins: pinmux_i2c4_pins {
139 pinctrl-single,pins = <
140 0xee (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
141 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
142 >;
143 };
144
145 mmc1_pins: pinmux_mmc1_pins {
146 pinctrl-single,pins = <
147 0xa2 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
148 0xa4 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */
149 0xa6 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */
150 0xa8 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
151 0xaa (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
152 0xac (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
153 >;
154 };
155
156 mmc5_pins: pinmux_mmc5_pins {
157 pinctrl-single,pins = <
158 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */
159 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */
160 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */
161 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */
162 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */
163 0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */
164 >;
165 };
166};
167
168/* PMIC */
169&i2c1 {
170 pinctrl-names = "default";
171 pinctrl-0 = <&i2c1_pins>;
172
173 clock-frequency = <400000>;
174
175 twl: twl@48 {
176 reg = <0x48>;
177 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
178 interrupt-parent = <&gic>;
179 };
180
181 twl6040: twl@4b {
182 compatible = "ti,twl6040";
183 reg = <0x4b>;
184 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
185 interrupt-parent = <&gic>;
186 ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */
187
188 vio-supply = <&v1v8>;
189 v2v1-supply = <&v2v1>;
190 enable-active-high;
191 };
192};
193
194#include "twl6030.dtsi"
195#include "twl6030_omap4.dtsi"
196
197/* on-board bluetooth / WiFi module */
198&i2c4 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&i2c4_pins>;
201
202 clock-frequency = <400000>;
203};
204
205&mmc1 {
206 pinctrl-names = "default";
207 pinctrl-0 = <&mmc1_pins>;
208
209 vmmc-supply = <&vmmc>;
210 ti,bus-width = <4>;
211 ti,non-removable; /* FIXME: use PMIC_MMC detect */
212};
213
214&mmc2 {
215 status = "disabled";
216};
217
218/* mmc3 is available to the expansion board */
219
220&mmc4 {
221 status = "disabled";
222};
223
224/* on-board WiFi module */
225&mmc5 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&mmc5_pins>;
228
229 vmmc-supply = <&w2cbw0015_vmmc>;
230 ti,bus-width = <4>;
231 ti,non-removable;
232 cap-power-off-card;
233};
234
235&twl_usb_comparator {
236 usb-supply = <&vusb>;
237};
238
239&usb_otg_hs {
240 interface-type = <1>;
241 mode = <3>;
242 power = <50>;
243};
244
245&usbhshost {
246 port1-mode = "ehci-phy";
247};
248
249&usbhsehci {
250 phys = <&hsusb1_phy>;
251};
252
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 88c6a05cab41..d2c45bfaaa2c 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,6 +16,11 @@
16 reg = <0x80000000 0x40000000>; /* 1 GB */ 16 reg = <0x80000000 0x40000000>; /* 1 GB */
17 }; 17 };
18 18
19 aliases {
20 display0 = &dvi0;
21 display1 = &hdmi0;
22 };
23
19 leds: leds { 24 leds: leds {
20 compatible = "gpio-leds"; 25 compatible = "gpio-leds";
21 pinctrl-names = "default"; 26 pinctrl-names = "default";
@@ -83,12 +88,8 @@
83 compatible = "usb-nop-xceiv"; 88 compatible = "usb-nop-xceiv";
84 reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */ 89 reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
85 vcc-supply = <&hsusb1_power>; 90 vcc-supply = <&hsusb1_power>;
86 /** 91 clocks = <&auxclk3_ck>;
87 * FIXME: 92 clock-names = "main_clk";
88 * put the right clock phandle here when available
89 * clocks = <&auxclk3>;
90 * clock-names = "main_clk";
91 */
92 clock-frequency = <19200000>; 93 clock-frequency = <19200000>;
93 }; 94 };
94 95
@@ -104,14 +105,94 @@
104 startup-delay-us = <70000>; 105 startup-delay-us = <70000>;
105 enable-active-high; 106 enable-active-high;
106 }; 107 };
108
109 tfp410: encoder@0 {
110 compatible = "ti,tfp410";
111 powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */
112
113 ports {
114 #address-cells = <1>;
115 #size-cells = <0>;
116
117 port@0 {
118 reg = <0>;
119
120 tfp410_in: endpoint@0 {
121 remote-endpoint = <&dpi_out>;
122 };
123 };
124
125 port@1 {
126 reg = <1>;
127
128 tfp410_out: endpoint@0 {
129 remote-endpoint = <&dvi_connector_in>;
130 };
131 };
132 };
133 };
134
135 dvi0: connector@0 {
136 compatible = "dvi-connector";
137 label = "dvi";
138
139 digital;
140
141 ddc-i2c-bus = <&i2c3>;
142
143 port {
144 dvi_connector_in: endpoint {
145 remote-endpoint = <&tfp410_out>;
146 };
147 };
148 };
149
150 tpd12s015: encoder@1 {
151 compatible = "ti,tpd12s015";
152
153 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
154 <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
155 <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
156
157 ports {
158 #address-cells = <1>;
159 #size-cells = <0>;
160
161 port@0 {
162 reg = <0>;
163
164 tpd12s015_in: endpoint@0 {
165 remote-endpoint = <&hdmi_out>;
166 };
167 };
168
169 port@1 {
170 reg = <1>;
171
172 tpd12s015_out: endpoint@0 {
173 remote-endpoint = <&hdmi_connector_in>;
174 };
175 };
176 };
177 };
178
179 hdmi0: connector@1 {
180 compatible = "hdmi-connector";
181 label = "hdmi";
182
183 type = "a";
184
185 port {
186 hdmi_connector_in: endpoint {
187 remote-endpoint = <&tpd12s015_out>;
188 };
189 };
190 };
107}; 191};
108 192
109&omap4_pmx_core { 193&omap4_pmx_core {
110 pinctrl-names = "default"; 194 pinctrl-names = "default";
111 pinctrl-0 = < 195 pinctrl-0 = <
112 &twl6040_pins
113 &mcpdm_pins
114 &mcbsp1_pins
115 &dss_dpi_pins 196 &dss_dpi_pins
116 &tfp410_pins 197 &tfp410_pins
117 &dss_hdmi_pins 198 &dss_hdmi_pins
@@ -300,6 +381,10 @@
300 twl6040: twl@4b { 381 twl6040: twl@4b {
301 compatible = "ti,twl6040"; 382 compatible = "ti,twl6040";
302 reg = <0x4b>; 383 reg = <0x4b>;
384
385 pinctrl-names = "default";
386 pinctrl-0 = <&twl6040_pins>;
387
303 /* IRQ# = 119 */ 388 /* IRQ# = 119 */
304 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ 389 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
305 interrupt-parent = <&gic>; 390 interrupt-parent = <&gic>;
@@ -380,16 +465,16 @@
380 device-handle = <&elpida_ECB240ABACN>; 465 device-handle = <&elpida_ECB240ABACN>;
381}; 466};
382 467
383&mcbsp2 { 468&mcbsp1 {
384 status = "disabled"; 469 pinctrl-names = "default";
385}; 470 pinctrl-0 = <&mcbsp1_pins>;
386 471 status = "okay";
387&mcbsp3 {
388 status = "disabled";
389}; 472};
390 473
391&dmic { 474&mcpdm {
392 status = "disabled"; 475 pinctrl-names = "default";
476 pinctrl-0 = <&mcpdm_pins>;
477 status = "okay";
393}; 478};
394 479
395&twl_usb_comparator { 480&twl_usb_comparator {
@@ -409,3 +494,30 @@
409&usbhsehci { 494&usbhsehci {
410 phys = <&hsusb1_phy>; 495 phys = <&hsusb1_phy>;
411}; 496};
497
498&dss {
499 status = "ok";
500
501 port {
502 dpi_out: endpoint {
503 remote-endpoint = <&tfp410_in>;
504 data-lines = <24>;
505 };
506 };
507};
508
509&dsi2 {
510 status = "ok";
511 vdd-supply = <&vcxio>;
512};
513
514&hdmi {
515 status = "ok";
516 vdda-supply = <&vdac>;
517
518 port {
519 hdmi_out: endpoint {
520 remote-endpoint = <&tpd12s015_in>;
521 };
522 };
523};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index dbc81fb6ef03..48983c8d56c2 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -19,6 +19,12 @@
19 reg = <0x80000000 0x40000000>; /* 1 GB */ 19 reg = <0x80000000 0x40000000>; /* 1 GB */
20 }; 20 };
21 21
22 aliases {
23 display0 = &lcd0;
24 display1 = &lcd1;
25 display2 = &hdmi0;
26 };
27
22 vdd_eth: fixedregulator-vdd-eth { 28 vdd_eth: fixedregulator-vdd-eth {
23 compatible = "regulator-fixed"; 29 compatible = "regulator-fixed";
24 regulator-name = "VDD_ETH"; 30 regulator-name = "VDD_ETH";
@@ -153,16 +159,53 @@
153 startup-delay-us = <70000>; 159 startup-delay-us = <70000>;
154 enable-active-high; 160 enable-active-high;
155 }; 161 };
162
163 tpd12s015: encoder@0 {
164 compatible = "ti,tpd12s015";
165
166 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
167 <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
168 <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
169
170 ports {
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 port@0 {
175 reg = <0>;
176
177 tpd12s015_in: endpoint@0 {
178 remote-endpoint = <&hdmi_out>;
179 };
180 };
181
182 port@1 {
183 reg = <1>;
184
185 tpd12s015_out: endpoint@0 {
186 remote-endpoint = <&hdmi_connector_in>;
187 };
188 };
189 };
190 };
191
192 hdmi0: connector@0 {
193 compatible = "hdmi-connector";
194 label = "hdmi";
195
196 type = "c";
197
198 port {
199 hdmi_connector_in: endpoint {
200 remote-endpoint = <&tpd12s015_out>;
201 };
202 };
203 };
156}; 204};
157 205
158&omap4_pmx_core { 206&omap4_pmx_core {
159 pinctrl-names = "default"; 207 pinctrl-names = "default";
160 pinctrl-0 = < 208 pinctrl-0 = <
161 &twl6040_pins
162 &mcpdm_pins
163 &dmic_pins
164 &mcbsp1_pins
165 &mcbsp2_pins
166 &dss_hdmi_pins 209 &dss_hdmi_pins
167 &tpd12s015_pins 210 &tpd12s015_pins
168 >; 211 >;
@@ -326,6 +369,10 @@
326 twl6040: twl@4b { 369 twl6040: twl@4b {
327 compatible = "ti,twl6040"; 370 compatible = "ti,twl6040";
328 reg = <0x4b>; 371 reg = <0x4b>;
372
373 pinctrl-names = "default";
374 pinctrl-0 = <&twl6040_pins>;
375
329 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ 376 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
330 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ 377 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
331 interrupt-parent = <&gic>; 378 interrupt-parent = <&gic>;
@@ -537,8 +584,28 @@
537 pinctrl-0 = <&uart4_pins>; 584 pinctrl-0 = <&uart4_pins>;
538}; 585};
539 586
540&mcbsp3 { 587&mcbsp1 {
541 status = "disabled"; 588 pinctrl-names = "default";
589 pinctrl-0 = <&mcbsp1_pins>;
590 status = "okay";
591};
592
593&mcbsp2 {
594 pinctrl-names = "default";
595 pinctrl-0 = <&mcbsp2_pins>;
596 status = "okay";
597};
598
599&dmic {
600 pinctrl-names = "default";
601 pinctrl-0 = <&dmic_pins>;
602 status = "okay";
603};
604
605&mcpdm {
606 pinctrl-names = "default";
607 pinctrl-0 = <&mcpdm_pins>;
608 status = "okay";
542}; 609};
543 610
544&twl_usb_comparator { 611&twl_usb_comparator {
@@ -550,3 +617,68 @@
550 mode = <3>; 617 mode = <3>;
551 power = <50>; 618 power = <50>;
552}; 619};
620
621&dss {
622 status = "ok";
623};
624
625&dsi1 {
626 status = "ok";
627 vdd-supply = <&vcxio>;
628
629 port {
630 dsi1_out_ep: endpoint {
631 remote-endpoint = <&lcd0_in>;
632 lanes = <0 1 2 3 4 5>;
633 };
634 };
635
636 lcd0: display {
637 compatible = "tpo,taal", "panel-dsi-cm";
638 label = "lcd0";
639
640 reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
641
642 port {
643 lcd0_in: endpoint {
644 remote-endpoint = <&dsi1_out_ep>;
645 };
646 };
647 };
648};
649
650&dsi2 {
651 status = "ok";
652 vdd-supply = <&vcxio>;
653
654 port {
655 dsi2_out_ep: endpoint {
656 remote-endpoint = <&lcd1_in>;
657 lanes = <0 1 2 3 4 5>;
658 };
659 };
660
661 lcd1: display {
662 compatible = "tpo,taal", "panel-dsi-cm";
663 label = "lcd1";
664
665 reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
666
667 port {
668 lcd1_in: endpoint {
669 remote-endpoint = <&dsi2_out_ep>;
670 };
671 };
672 };
673};
674
675&hdmi {
676 status = "ok";
677 vdda-supply = <&vdac>;
678
679 port {
680 hdmi_out: endpoint {
681 remote-endpoint = <&tpd12s015_in>;
682 };
683 };
684};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index d3f8a6e8ca20..27fcac874742 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -36,6 +36,11 @@
36 device_type = "cpu"; 36 device_type = "cpu";
37 next-level-cache = <&L2>; 37 next-level-cache = <&L2>;
38 reg = <0x0>; 38 reg = <0x0>;
39
40 clocks = <&dpll_mpu_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
39 }; 44 };
40 cpu@1 { 45 cpu@1 {
41 compatible = "arm,cortex-a9"; 46 compatible = "arm,cortex-a9";
@@ -186,6 +191,22 @@
186 pinctrl-single,function-mask = <0x7fff>; 191 pinctrl-single,function-mask = <0x7fff>;
187 }; 192 };
188 193
194 omap4_padconf_global: tisyscon@4a1005a0 {
195 compatible = "syscon";
196 reg = <0x4a1005a0 0x170>;
197 };
198
199 pbias_regulator: pbias_regulator {
200 compatible = "ti,pbias-omap";
201 reg = <0x60 0x4>;
202 syscon = <&omap4_padconf_global>;
203 pbias_mmc_reg: pbias_mmc_omap4 {
204 regulator-name = "pbias_mmc_omap4";
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <3000000>;
207 };
208 };
209
189 sdma: dma-controller@4a056000 { 210 sdma: dma-controller@4a056000 {
190 compatible = "ti,omap4430-sdma"; 211 compatible = "ti,omap4430-sdma";
191 reg = <0x4a056000 0x1000>; 212 reg = <0x4a056000 0x1000>;
@@ -275,6 +296,8 @@
275 gpmc,num-waitpins = <4>; 296 gpmc,num-waitpins = <4>;
276 ti,hwmods = "gpmc"; 297 ti,hwmods = "gpmc";
277 ti,no-idle-on-init; 298 ti,no-idle-on-init;
299 clocks = <&l3_div_ck>;
300 clock-names = "fck";
278 }; 301 };
279 302
280 uart1: serial@4806a000 { 303 uart1: serial@4806a000 {
@@ -313,6 +336,7 @@
313 compatible = "ti,omap4-hwspinlock"; 336 compatible = "ti,omap4-hwspinlock";
314 reg = <0x4a0f6000 0x1000>; 337 reg = <0x4a0f6000 0x1000>;
315 ti,hwmods = "spinlock"; 338 ti,hwmods = "spinlock";
339 #hwlock-cells = <1>;
316 }; 340 };
317 341
318 i2c1: i2c@48070000 { 342 i2c1: i2c@48070000 {
@@ -419,6 +443,7 @@
419 ti,needs-special-reset; 443 ti,needs-special-reset;
420 dmas = <&sdma 61>, <&sdma 62>; 444 dmas = <&sdma 61>, <&sdma 62>;
421 dma-names = "tx", "rx"; 445 dma-names = "tx", "rx";
446 pbias-supply = <&pbias_mmc_reg>;
422 }; 447 };
423 448
424 mmc2: mmc@480b4000 { 449 mmc2: mmc@480b4000 {
@@ -461,6 +486,21 @@
461 dma-names = "tx", "rx"; 486 dma-names = "tx", "rx";
462 }; 487 };
463 488
489 mmu_dsp: mmu@4a066000 {
490 compatible = "ti,omap4-iommu";
491 reg = <0x4a066000 0x100>;
492 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
493 ti,hwmods = "mmu_dsp";
494 };
495
496 mmu_ipu: mmu@55082000 {
497 compatible = "ti,omap4-iommu";
498 reg = <0x55082000 0x100>;
499 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
500 ti,hwmods = "mmu_ipu";
501 ti,iommu-bus-err-back;
502 };
503
464 wdt2: wdt@4a314000 { 504 wdt2: wdt@4a314000 {
465 compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 505 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
466 reg = <0x4a314000 0x80>; 506 reg = <0x4a314000 0x80>;
@@ -478,6 +518,7 @@
478 dmas = <&sdma 65>, 518 dmas = <&sdma 65>,
479 <&sdma 66>; 519 <&sdma 66>;
480 dma-names = "up_link", "dn_link"; 520 dma-names = "up_link", "dn_link";
521 status = "disabled";
481 }; 522 };
482 523
483 dmic: dmic@4012e000 { 524 dmic: dmic@4012e000 {
@@ -489,6 +530,7 @@
489 ti,hwmods = "dmic"; 530 ti,hwmods = "dmic";
490 dmas = <&sdma 67>; 531 dmas = <&sdma 67>;
491 dma-names = "up_link"; 532 dma-names = "up_link";
533 status = "disabled";
492 }; 534 };
493 535
494 mcbsp1: mcbsp@40122000 { 536 mcbsp1: mcbsp@40122000 {
@@ -503,6 +545,7 @@
503 dmas = <&sdma 33>, 545 dmas = <&sdma 33>,
504 <&sdma 34>; 546 <&sdma 34>;
505 dma-names = "tx", "rx"; 547 dma-names = "tx", "rx";
548 status = "disabled";
506 }; 549 };
507 550
508 mcbsp2: mcbsp@40124000 { 551 mcbsp2: mcbsp@40124000 {
@@ -517,6 +560,7 @@
517 dmas = <&sdma 17>, 560 dmas = <&sdma 17>,
518 <&sdma 18>; 561 <&sdma 18>;
519 dma-names = "tx", "rx"; 562 dma-names = "tx", "rx";
563 status = "disabled";
520 }; 564 };
521 565
522 mcbsp3: mcbsp@40126000 { 566 mcbsp3: mcbsp@40126000 {
@@ -531,6 +575,7 @@
531 dmas = <&sdma 19>, 575 dmas = <&sdma 19>,
532 <&sdma 20>; 576 <&sdma 20>;
533 dma-names = "tx", "rx"; 577 dma-names = "tx", "rx";
578 status = "disabled";
534 }; 579 };
535 580
536 mcbsp4: mcbsp@48096000 { 581 mcbsp4: mcbsp@48096000 {
@@ -544,6 +589,7 @@
544 dmas = <&sdma 31>, 589 dmas = <&sdma 31>,
545 <&sdma 32>; 590 <&sdma 32>;
546 dma-names = "tx", "rx"; 591 dma-names = "tx", "rx";
592 status = "disabled";
547 }; 593 };
548 594
549 keypad: keypad@4a31c000 { 595 keypad: keypad@4a31c000 {
@@ -554,6 +600,13 @@
554 ti,hwmods = "kbd"; 600 ti,hwmods = "kbd";
555 }; 601 };
556 602
603 dmm@4e000000 {
604 compatible = "ti,omap4-dmm";
605 reg = <0x4e000000 0x800>;
606 interrupts = <0 113 0x4>;
607 ti,hwmods = "dmm";
608 };
609
557 emif1: emif@4c000000 { 610 emif1: emif@4c000000 {
558 compatible = "ti,emif-4d"; 611 compatible = "ti,emif-4d";
559 reg = <0x4c000000 0x100>; 612 reg = <0x4c000000 0x100>;
@@ -697,16 +750,22 @@
697 #address-cells = <1>; 750 #address-cells = <1>;
698 #size-cells = <1>; 751 #size-cells = <1>;
699 ranges; 752 ranges;
753 clocks = <&init_60m_fclk>,
754 <&xclk60mhsp1_ck>,
755 <&xclk60mhsp2_ck>;
756 clock-names = "refclk_60m_int",
757 "refclk_60m_ext_p1",
758 "refclk_60m_ext_p2";
700 759
701 usbhsohci: ohci@4a064800 { 760 usbhsohci: ohci@4a064800 {
702 compatible = "ti,ohci-omap3", "usb-ohci"; 761 compatible = "ti,ohci-omap3";
703 reg = <0x4a064800 0x400>; 762 reg = <0x4a064800 0x400>;
704 interrupt-parent = <&gic>; 763 interrupt-parent = <&gic>;
705 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 764 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
706 }; 765 };
707 766
708 usbhsehci: ehci@4a064c00 { 767 usbhsehci: ehci@4a064c00 {
709 compatible = "ti,ehci-omap", "usb-ehci"; 768 compatible = "ti,ehci-omap";
710 reg = <0x4a064c00 0x400>; 769 reg = <0x4a064c00 0x400>;
711 interrupt-parent = <&gic>; 770 interrupt-parent = <&gic>;
712 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 771 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@@ -757,6 +816,111 @@
757 dmas = <&sdma 117>, <&sdma 116>; 816 dmas = <&sdma 117>, <&sdma 116>;
758 dma-names = "tx", "rx"; 817 dma-names = "tx", "rx";
759 }; 818 };
819
820 abb_mpu: regulator-abb-mpu {
821 compatible = "ti,abb-v2";
822 regulator-name = "abb_mpu";
823 #address-cells = <0>;
824 #size-cells = <0>;
825 ti,tranxdone-status-mask = <0x80>;
826 clocks = <&sys_clkin_ck>;
827 ti,settling-time = <50>;
828 ti,clock-cycles = <16>;
829
830 status = "disabled";
831 };
832
833 abb_iva: regulator-abb-iva {
834 compatible = "ti,abb-v2";
835 regulator-name = "abb_iva";
836 #address-cells = <0>;
837 #size-cells = <0>;
838 ti,tranxdone-status-mask = <0x80000000>;
839 clocks = <&sys_clkin_ck>;
840 ti,settling-time = <50>;
841 ti,clock-cycles = <16>;
842
843 status = "disabled";
844 };
845
846 dss: dss@58000000 {
847 compatible = "ti,omap4-dss";
848 reg = <0x58000000 0x80>;
849 status = "disabled";
850 ti,hwmods = "dss_core";
851 clocks = <&dss_dss_clk>;
852 clock-names = "fck";
853 #address-cells = <1>;
854 #size-cells = <1>;
855 ranges;
856
857 dispc@58001000 {
858 compatible = "ti,omap4-dispc";
859 reg = <0x58001000 0x1000>;
860 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
861 ti,hwmods = "dss_dispc";
862 clocks = <&dss_dss_clk>;
863 clock-names = "fck";
864 };
865
866 rfbi: encoder@58002000 {
867 compatible = "ti,omap4-rfbi";
868 reg = <0x58002000 0x1000>;
869 status = "disabled";
870 ti,hwmods = "dss_rfbi";
871 clocks = <&dss_dss_clk>, <&dss_fck>;
872 clock-names = "fck", "ick";
873 };
874
875 venc: encoder@58003000 {
876 compatible = "ti,omap4-venc";
877 reg = <0x58003000 0x1000>;
878 status = "disabled";
879 ti,hwmods = "dss_venc";
880 clocks = <&dss_tv_clk>;
881 clock-names = "fck";
882 };
883
884 dsi1: encoder@58004000 {
885 compatible = "ti,omap4-dsi";
886 reg = <0x58004000 0x200>,
887 <0x58004200 0x40>,
888 <0x58004300 0x20>;
889 reg-names = "proto", "phy", "pll";
890 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
891 status = "disabled";
892 ti,hwmods = "dss_dsi1";
893 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
894 clock-names = "fck", "sys_clk";
895 };
896
897 dsi2: encoder@58005000 {
898 compatible = "ti,omap4-dsi";
899 reg = <0x58005000 0x200>,
900 <0x58005200 0x40>,
901 <0x58005300 0x20>;
902 reg-names = "proto", "phy", "pll";
903 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
904 status = "disabled";
905 ti,hwmods = "dss_dsi2";
906 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
907 clock-names = "fck", "sys_clk";
908 };
909
910 hdmi: encoder@58006000 {
911 compatible = "ti,omap4-hdmi";
912 reg = <0x58006000 0x200>,
913 <0x58006200 0x100>,
914 <0x58006300 0x100>,
915 <0x58006400 0x1000>;
916 reg-names = "wp", "pll", "phy", "core";
917 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
918 status = "disabled";
919 ti,hwmods = "dss_hdmi";
920 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
921 clock-names = "fck", "sys_clk";
922 };
923 };
760 }; 924 };
761}; 925};
762 926
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index 8c1cfad30d60..0adfa1d1ef20 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -43,6 +43,32 @@
43 #thermal-sensor-cells = <0>; 43 #thermal-sensor-cells = <0>;
44 }; 44 };
45 }; 45 };
46
47 ocp {
48 abb_mpu: regulator-abb-mpu {
49 status = "okay";
50
51 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>;
52 reg-names = "base-address", "int-address";
53
54 ti,abb_info = <
55 /*uV ABB efuse rbb_m fbb_m vset_m*/
56 1025000 0 0 0 0 0
57 1200000 0 0 0 0 0
58 1313000 0 0 0 0 0
59 1375000 1 0 0 0 0
60 1389000 1 0 0 0 0
61 >;
62 };
63
64 /* Default unused, just provide register info for record */
65 abb_iva: regulator-abb-iva {
66 reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>;
67 reg-names = "base-address", "int-address";
68 };
69
70 };
71
46}; 72};
47 73
48/include/ "omap443x-clocks.dtsi" 74/include/ "omap443x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 6b32f520741a..194f9ef0a009 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -50,7 +50,44 @@
50 50
51 #thermal-sensor-cells = <0>; 51 #thermal-sensor-cells = <0>;
52 }; 52 };
53
54 abb_mpu: regulator-abb-mpu {
55 status = "okay";
56
57 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
58 <0x4A002268 0x4>;
59 reg-names = "base-address", "int-address",
60 "efuse-address";
61
62 ti,abb_info = <
63 /*uV ABB efuse rbb_m fbb_m vset_m*/
64 1025000 0 0 0 0 0
65 1200000 0 0 0 0 0
66 1313000 0 0 0x100000 0x40000 0
67 1375000 1 0 0 0 0
68 1389000 1 0 0 0 0
69 >;
70 };
71
72 abb_iva: regulator-abb-iva {
73 status = "okay";
74
75 reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
76 <0x4A002268 0x4>;
77 reg-names = "base-address", "int-address",
78 "efuse-address";
79
80 ti,abb_info = <
81 /*uV ABB efuse rbb_m fbb_m vset_m*/
82 950000 0 0 0 0 0
83 1140000 0 0 0 0 0
84 1291000 0 0 0x200000 0 0
85 1375000 1 0 0 0 0
86 1376000 1 0 0 0 0
87 >;
88 };
53 }; 89 };
90
54}; 91};
55 92
56/include/ "omap446x-clocks.dtsi" 93/include/ "omap446x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 002fa70180a5..3b99ec25b748 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -31,12 +31,8 @@
31 hsusb2_phy: hsusb2_phy { 31 hsusb2_phy: hsusb2_phy {
32 compatible = "usb-nop-xceiv"; 32 compatible = "usb-nop-xceiv";
33 reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ 33 reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
34 /** 34 clocks = <&auxclk1_ck>;
35 * FIXME 35 clock-names = "main_clk";
36 * Put the right clock phandle here when available
37 * clocks = <&auxclk1>;
38 * clock-names = "main_clk";
39 */
40 clock-frequency = <19200000>; 36 clock-frequency = <19200000>;
41 }; 37 };
42 38
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index a72813a9663e..6f3de22fb266 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -49,6 +49,12 @@
49 1000000 1060000 49 1000000 1060000
50 1500000 1250000 50 1500000 1250000
51 >; 51 >;
52
53 clocks = <&dpll_mpu_ck>;
54 clock-names = "cpu";
55
56 clock-latency = <300000>; /* From omap-cpufreq driver */
57
52 /* cooling options */ 58 /* cooling options */
53 cooling-min-level = <0>; 59 cooling-min-level = <0>;
54 cooling-max-level = <2>; 60 cooling-max-level = <2>;
@@ -192,6 +198,22 @@
192 pinctrl-single,function-mask = <0x7fff>; 198 pinctrl-single,function-mask = <0x7fff>;
193 }; 199 };
194 200
201 omap5_padconf_global: tisyscon@4a002da0 {
202 compatible = "syscon";
203 reg = <0x4A002da0 0xec>;
204 };
205
206 pbias_regulator: pbias_regulator {
207 compatible = "ti,pbias-omap";
208 reg = <0x60 0x4>;
209 syscon = <&omap5_padconf_global>;
210 pbias_mmc_reg: pbias_mmc_omap5 {
211 regulator-name = "pbias_mmc_omap5";
212 regulator-min-microvolt = <1800000>;
213 regulator-max-microvolt = <3000000>;
214 };
215 };
216
195 sdma: dma-controller@4a056000 { 217 sdma: dma-controller@4a056000 {
196 compatible = "ti,omap4430-sdma"; 218 compatible = "ti,omap4430-sdma";
197 reg = <0x4a056000 0x1000>; 219 reg = <0x4a056000 0x1000>;
@@ -302,6 +324,8 @@
302 gpmc,num-cs = <8>; 324 gpmc,num-cs = <8>;
303 gpmc,num-waitpins = <4>; 325 gpmc,num-waitpins = <4>;
304 ti,hwmods = "gpmc"; 326 ti,hwmods = "gpmc";
327 clocks = <&l3_iclk_div>;
328 clock-names = "fck";
305 }; 329 };
306 330
307 i2c1: i2c@48070000 { 331 i2c1: i2c@48070000 {
@@ -353,6 +377,7 @@
353 compatible = "ti,omap4-hwspinlock"; 377 compatible = "ti,omap4-hwspinlock";
354 reg = <0x4a0f6000 0x1000>; 378 reg = <0x4a0f6000 0x1000>;
355 ti,hwmods = "spinlock"; 379 ti,hwmods = "spinlock";
380 #hwlock-cells = <1>;
356 }; 381 };
357 382
358 mcspi1: spi@48098000 { 383 mcspi1: spi@48098000 {
@@ -471,6 +496,7 @@
471 ti,needs-special-reset; 496 ti,needs-special-reset;
472 dmas = <&sdma 61>, <&sdma 62>; 497 dmas = <&sdma 61>, <&sdma 62>;
473 dma-names = "tx", "rx"; 498 dma-names = "tx", "rx";
499 pbias-supply = <&pbias_mmc_reg>;
474 }; 500 };
475 501
476 mmc2: mmc@480b4000 { 502 mmc2: mmc@480b4000 {
@@ -513,6 +539,21 @@
513 dma-names = "tx", "rx"; 539 dma-names = "tx", "rx";
514 }; 540 };
515 541
542 mmu_dsp: mmu@4a066000 {
543 compatible = "ti,omap4-iommu";
544 reg = <0x4a066000 0x100>;
545 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
546 ti,hwmods = "mmu_dsp";
547 };
548
549 mmu_ipu: mmu@55082000 {
550 compatible = "ti,omap4-iommu";
551 reg = <0x55082000 0x100>;
552 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
553 ti,hwmods = "mmu_ipu";
554 ti,iommu-bus-err-back;
555 };
556
516 keypad: keypad@4ae1c000 { 557 keypad: keypad@4ae1c000 {
517 compatible = "ti,omap4-keypad"; 558 compatible = "ti,omap4-keypad";
518 reg = <0x4ae1c000 0x400>; 559 reg = <0x4ae1c000 0x400>;
@@ -529,6 +570,7 @@
529 dmas = <&sdma 65>, 570 dmas = <&sdma 65>,
530 <&sdma 66>; 571 <&sdma 66>;
531 dma-names = "up_link", "dn_link"; 572 dma-names = "up_link", "dn_link";
573 status = "disabled";
532 }; 574 };
533 575
534 dmic: dmic@4012e000 { 576 dmic: dmic@4012e000 {
@@ -540,6 +582,7 @@
540 ti,hwmods = "dmic"; 582 ti,hwmods = "dmic";
541 dmas = <&sdma 67>; 583 dmas = <&sdma 67>;
542 dma-names = "up_link"; 584 dma-names = "up_link";
585 status = "disabled";
543 }; 586 };
544 587
545 mcbsp1: mcbsp@40122000 { 588 mcbsp1: mcbsp@40122000 {
@@ -554,6 +597,7 @@
554 dmas = <&sdma 33>, 597 dmas = <&sdma 33>,
555 <&sdma 34>; 598 <&sdma 34>;
556 dma-names = "tx", "rx"; 599 dma-names = "tx", "rx";
600 status = "disabled";
557 }; 601 };
558 602
559 mcbsp2: mcbsp@40124000 { 603 mcbsp2: mcbsp@40124000 {
@@ -568,6 +612,7 @@
568 dmas = <&sdma 17>, 612 dmas = <&sdma 17>,
569 <&sdma 18>; 613 <&sdma 18>;
570 dma-names = "tx", "rx"; 614 dma-names = "tx", "rx";
615 status = "disabled";
571 }; 616 };
572 617
573 mcbsp3: mcbsp@40126000 { 618 mcbsp3: mcbsp@40126000 {
@@ -582,6 +627,7 @@
582 dmas = <&sdma 19>, 627 dmas = <&sdma 19>,
583 <&sdma 20>; 628 <&sdma 20>;
584 dma-names = "tx", "rx"; 629 dma-names = "tx", "rx";
630 status = "disabled";
585 }; 631 };
586 632
587 timer1: timer@4ae18000 { 633 timer1: timer@4ae18000 {
@@ -683,6 +729,13 @@
683 ti,hwmods = "wd_timer2"; 729 ti,hwmods = "wd_timer2";
684 }; 730 };
685 731
732 dmm@4e000000 {
733 compatible = "ti,omap5-dmm";
734 reg = <0x4e000000 0x800>;
735 interrupts = <0 113 0x4>;
736 ti,hwmods = "dmm";
737 };
738
686 emif1: emif@4c000000 { 739 emif1: emif@4c000000 {
687 compatible = "ti,emif-4d5"; 740 compatible = "ti,emif-4d5";
688 ti,hwmods = "emif1"; 741 ti,hwmods = "emif1";
@@ -732,7 +785,8 @@
732 compatible = "snps,dwc3"; 785 compatible = "snps,dwc3";
733 reg = <0x4a030000 0x10000>; 786 reg = <0x4a030000 0x10000>;
734 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 787 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
735 usb-phy = <&usb2_phy>, <&usb3_phy>; 788 phys = <&usb2_phy>, <&usb3_phy>;
789 phy-names = "usb2-phy", "usb3-phy";
736 dr_mode = "peripheral"; 790 dr_mode = "peripheral";
737 tx-fifo-resize; 791 tx-fifo-resize;
738 }; 792 };
@@ -749,6 +803,7 @@
749 compatible = "ti,omap-usb2"; 803 compatible = "ti,omap-usb2";
750 reg = <0x4a084000 0x7c>; 804 reg = <0x4a084000 0x7c>;
751 ctrl-module = <&omap_control_usb2phy>; 805 ctrl-module = <&omap_control_usb2phy>;
806 #phy-cells = <0>;
752 }; 807 };
753 808
754 usb3_phy: usb3phy@4a084400 { 809 usb3_phy: usb3phy@4a084400 {
@@ -758,6 +813,7 @@
758 <0x4a084c00 0x40>; 813 <0x4a084c00 0x40>;
759 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 814 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
760 ctrl-module = <&omap_control_usb3phy>; 815 ctrl-module = <&omap_control_usb3phy>;
816 #phy-cells = <0>;
761 }; 817 };
762 }; 818 };
763 819
@@ -775,16 +831,22 @@
775 #address-cells = <1>; 831 #address-cells = <1>;
776 #size-cells = <1>; 832 #size-cells = <1>;
777 ranges; 833 ranges;
834 clocks = <&l3init_60m_fclk>,
835 <&xclk60mhsp1_ck>,
836 <&xclk60mhsp2_ck>;
837 clock-names = "refclk_60m_int",
838 "refclk_60m_ext_p1",
839 "refclk_60m_ext_p2";
778 840
779 usbhsohci: ohci@4a064800 { 841 usbhsohci: ohci@4a064800 {
780 compatible = "ti,ohci-omap3", "usb-ohci"; 842 compatible = "ti,ohci-omap3";
781 reg = <0x4a064800 0x400>; 843 reg = <0x4a064800 0x400>;
782 interrupt-parent = <&gic>; 844 interrupt-parent = <&gic>;
783 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 845 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
784 }; 846 };
785 847
786 usbhsehci: ehci@4a064c00 { 848 usbhsehci: ehci@4a064c00 {
787 compatible = "ti,ehci-omap", "usb-ehci"; 849 compatible = "ti,ehci-omap";
788 reg = <0x4a064c00 0x400>; 850 reg = <0x4a064c00 0x400>;
789 interrupt-parent = <&gic>; 851 interrupt-parent = <&gic>;
790 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 852 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 0e219932d7cc..1e82571d6823 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -76,9 +76,10 @@
76 #clock-cells = <1>; 76 #clock-cells = <1>;
77 }; 77 };
78 78
79 reset-controller@88010000 { 79 rstc: reset-controller@88010000 {
80 compatible = "sirf,prima2-rstc"; 80 compatible = "sirf,prima2-rstc";
81 reg = <0x88010000 0x1000>; 81 reg = <0x88010000 0x1000>;
82 #reset-cells = <1>;
82 }; 83 };
83 84
84 rsc-controller@88020000 { 85 rsc-controller@88020000 {
@@ -223,8 +224,8 @@
223 interrupts = <17>; 224 interrupts = <17>;
224 fifosize = <128>; 225 fifosize = <128>;
225 clocks = <&clks 13>; 226 clocks = <&clks 13>;
226 sirf,uart-dma-rx-channel = <21>; 227 dmas = <&dmac1 5>, <&dmac0 2>;
227 sirf,uart-dma-tx-channel = <2>; 228 dma-names = "rx", "tx";
228 }; 229 };
229 230
230 uart1: uart@b0060000 { 231 uart1: uart@b0060000 {
@@ -243,8 +244,8 @@
243 interrupts = <19>; 244 interrupts = <19>;
244 fifosize = <128>; 245 fifosize = <128>;
245 clocks = <&clks 15>; 246 clocks = <&clks 15>;
246 sirf,uart-dma-rx-channel = <6>; 247 dmas = <&dmac0 6>, <&dmac0 7>;
247 sirf,uart-dma-tx-channel = <7>; 248 dma-names = "rx", "tx";
248 }; 249 };
249 250
250 usp0: usp@b0080000 { 251 usp0: usp@b0080000 {
@@ -254,8 +255,8 @@
254 interrupts = <20>; 255 interrupts = <20>;
255 fifosize = <128>; 256 fifosize = <128>;
256 clocks = <&clks 28>; 257 clocks = <&clks 28>;
257 sirf,usp-dma-rx-channel = <17>; 258 dmas = <&dmac1 1>, <&dmac1 2>;
258 sirf,usp-dma-tx-channel = <18>; 259 dma-names = "rx", "tx";
259 }; 260 };
260 261
261 usp1: usp@b0090000 { 262 usp1: usp@b0090000 {
@@ -265,8 +266,8 @@
265 interrupts = <21>; 266 interrupts = <21>;
266 fifosize = <128>; 267 fifosize = <128>;
267 clocks = <&clks 29>; 268 clocks = <&clks 29>;
268 sirf,usp-dma-rx-channel = <14>; 269 dmas = <&dmac0 14>, <&dmac0 15>;
269 sirf,usp-dma-tx-channel = <15>; 270 dma-names = "rx", "tx";
270 }; 271 };
271 272
272 usp2: usp@b00a0000 { 273 usp2: usp@b00a0000 {
@@ -276,8 +277,8 @@
276 interrupts = <22>; 277 interrupts = <22>;
277 fifosize = <128>; 278 fifosize = <128>;
278 clocks = <&clks 30>; 279 clocks = <&clks 30>;
279 sirf,usp-dma-rx-channel = <10>; 280 dmas = <&dmac0 10>, <&dmac0 11>;
280 sirf,usp-dma-tx-channel = <11>; 281 dma-names = "rx", "tx";
281 }; 282 };
282 283
283 dmac0: dma-controller@b00b0000 { 284 dmac0: dma-controller@b00b0000 {
@@ -286,6 +287,7 @@
286 reg = <0xb00b0000 0x10000>; 287 reg = <0xb00b0000 0x10000>;
287 interrupts = <12>; 288 interrupts = <12>;
288 clocks = <&clks 24>; 289 clocks = <&clks 24>;
290 #dma-cells = <1>;
289 }; 291 };
290 292
291 dmac1: dma-controller@b0160000 { 293 dmac1: dma-controller@b0160000 {
@@ -294,6 +296,7 @@
294 reg = <0xb0160000 0x10000>; 296 reg = <0xb0160000 0x10000>;
295 interrupts = <13>; 297 interrupts = <13>;
296 clocks = <&clks 25>; 298 clocks = <&clks 25>;
299 #dma-cells = <1>;
297 }; 300 };
298 301
299 vip@b00C0000 { 302 vip@b00C0000 {
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 68a72f5507b9..169bad90dac9 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -1,63 +1,6 @@
1/dts-v1/; 1#include "qcom-msm8660.dtsi"
2
3/include/ "skeleton.dtsi"
4
5#include <dt-bindings/clock/qcom,gcc-msm8660.h>
6 2
7/ { 3/ {
8 model = "Qualcomm MSM8660 SURF"; 4 model = "Qualcomm MSM8660 SURF";
9 compatible = "qcom,msm8660-surf", "qcom,msm8660"; 5 compatible = "qcom,msm8660-surf", "qcom,msm8660";
10 interrupt-parent = <&intc>;
11
12 intc: interrupt-controller@2080000 {
13 compatible = "qcom,msm-8660-qgic";
14 interrupt-controller;
15 #interrupt-cells = <3>;
16 reg = < 0x02080000 0x1000 >,
17 < 0x02081000 0x1000 >;
18 };
19
20 timer@2000000 {
21 compatible = "qcom,scss-timer", "qcom,msm-timer";
22 interrupts = <1 0 0x301>,
23 <1 1 0x301>,
24 <1 2 0x301>;
25 reg = <0x02000000 0x100>;
26 clock-frequency = <27000000>,
27 <32768>;
28 cpu-offset = <0x40000>;
29 };
30
31 msmgpio: gpio@800000 {
32 compatible = "qcom,msm-gpio";
33 reg = <0x00800000 0x4000>;
34 gpio-controller;
35 #gpio-cells = <2>;
36 ngpio = <173>;
37 interrupts = <0 16 0x4>;
38 interrupt-controller;
39 #interrupt-cells = <2>;
40 };
41
42 gcc: clock-controller@900000 {
43 compatible = "qcom,gcc-msm8660";
44 #clock-cells = <1>;
45 #reset-cells = <1>;
46 reg = <0x900000 0x4000>;
47 };
48
49 serial@19c40000 {
50 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
51 reg = <0x19c40000 0x1000>,
52 <0x19c00000 0x1000>;
53 interrupts = <0 195 0x0>;
54 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
55 clock-names = "core", "iface";
56 };
57
58 qcom,ssbi@500000 {
59 compatible = "qcom,ssbi";
60 reg = <0x500000 0x1000>;
61 qcom,controller-type = "pmic-arbiter";
62 };
63}; 6};
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
new file mode 100644
index 000000000000..c52a9e964a44
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -0,0 +1,87 @@
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5#include <dt-bindings/clock/qcom,gcc-msm8660.h>
6
7/ {
8 model = "Qualcomm MSM8660";
9 compatible = "qcom,msm8660";
10 interrupt-parent = <&intc>;
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15 compatible = "qcom,scorpion";
16 enable-method = "qcom,gcc-msm8660";
17
18 cpu@0 {
19 device_type = "cpu";
20 reg = <0>;
21 next-level-cache = <&L2>;
22 };
23
24 cpu@1 {
25 device_type = "cpu";
26 reg = <1>;
27 next-level-cache = <&L2>;
28 };
29
30 L2: l2-cache {
31 compatible = "cache";
32 cache-level = <2>;
33 };
34 };
35
36 intc: interrupt-controller@2080000 {
37 compatible = "qcom,msm-8660-qgic";
38 interrupt-controller;
39 #interrupt-cells = <3>;
40 reg = < 0x02080000 0x1000 >,
41 < 0x02081000 0x1000 >;
42 };
43
44 timer@2000000 {
45 compatible = "qcom,scss-timer", "qcom,msm-timer";
46 interrupts = <1 0 0x301>,
47 <1 1 0x301>,
48 <1 2 0x301>;
49 reg = <0x02000000 0x100>;
50 clock-frequency = <27000000>,
51 <32768>;
52 cpu-offset = <0x40000>;
53 };
54
55 msmgpio: gpio@800000 {
56 compatible = "qcom,msm-gpio";
57 reg = <0x00800000 0x4000>;
58 gpio-controller;
59 #gpio-cells = <2>;
60 ngpio = <173>;
61 interrupts = <0 16 0x4>;
62 interrupt-controller;
63 #interrupt-cells = <2>;
64 };
65
66 gcc: clock-controller@900000 {
67 compatible = "qcom,gcc-msm8660";
68 #clock-cells = <1>;
69 #reset-cells = <1>;
70 reg = <0x900000 0x4000>;
71 };
72
73 serial@19c40000 {
74 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
75 reg = <0x19c40000 0x1000>,
76 <0x19c00000 0x1000>;
77 interrupts = <0 195 0x0>;
78 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
79 clock-names = "core", "iface";
80 };
81
82 qcom,ssbi@500000 {
83 compatible = "qcom,ssbi";
84 reg = <0x500000 0x1000>;
85 qcom,controller-type = "pmic-arbiter";
86 };
87};
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 7c30de4fa302..a58fb88315f6 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -1,70 +1,6 @@
1/dts-v1/; 1#include "qcom-msm8960.dtsi"
2
3/include/ "skeleton.dtsi"
4
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 2
7/ { 3/ {
8 model = "Qualcomm MSM8960 CDP"; 4 model = "Qualcomm MSM8960 CDP";
9 compatible = "qcom,msm8960-cdp", "qcom,msm8960"; 5 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
10 interrupt-parent = <&intc>;
11
12 intc: interrupt-controller@2000000 {
13 compatible = "qcom,msm-qgic2";
14 interrupt-controller;
15 #interrupt-cells = <3>;
16 reg = < 0x02000000 0x1000 >,
17 < 0x02002000 0x1000 >;
18 };
19
20 timer@200a000 {
21 compatible = "qcom,kpss-timer", "qcom,msm-timer";
22 interrupts = <1 1 0x301>,
23 <1 2 0x301>,
24 <1 3 0x301>;
25 reg = <0x0200a000 0x100>;
26 clock-frequency = <27000000>,
27 <32768>;
28 cpu-offset = <0x80000>;
29 };
30
31 msmgpio: gpio@800000 {
32 compatible = "qcom,msm-gpio";
33 gpio-controller;
34 #gpio-cells = <2>;
35 ngpio = <150>;
36 interrupts = <0 16 0x4>;
37 interrupt-controller;
38 #interrupt-cells = <2>;
39 reg = <0x800000 0x4000>;
40 };
41
42 gcc: clock-controller@900000 {
43 compatible = "qcom,gcc-msm8960";
44 #clock-cells = <1>;
45 #reset-cells = <1>;
46 reg = <0x900000 0x4000>;
47 };
48
49 clock-controller@4000000 {
50 compatible = "qcom,mmcc-msm8960";
51 reg = <0x4000000 0x1000>;
52 #clock-cells = <1>;
53 #reset-cells = <1>;
54 };
55
56 serial@16440000 {
57 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
58 reg = <0x16440000 0x1000>,
59 <0x16400000 0x1000>;
60 interrupts = <0 154 0x0>;
61 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
62 clock-names = "core", "iface";
63 };
64
65 qcom,ssbi@500000 {
66 compatible = "qcom,ssbi";
67 reg = <0x500000 0x1000>;
68 qcom,controller-type = "pmic-arbiter";
69 };
70}; 6};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
new file mode 100644
index 000000000000..997b7b94e117
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -0,0 +1,135 @@
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6
7/ {
8 model = "Qualcomm MSM8960";
9 compatible = "qcom,msm8960";
10 interrupt-parent = <&intc>;
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15 interrupts = <1 14 0x304>;
16 compatible = "qcom,krait";
17 enable-method = "qcom,kpss-acc-v1";
18
19 cpu@0 {
20 device_type = "cpu";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 qcom,acc = <&acc0>;
24 qcom,saw = <&saw0>;
25 };
26
27 cpu@1 {
28 device_type = "cpu";
29 reg = <1>;
30 next-level-cache = <&L2>;
31 qcom,acc = <&acc1>;
32 qcom,saw = <&saw1>;
33 };
34
35 L2: l2-cache {
36 compatible = "cache";
37 cache-level = <2>;
38 interrupts = <0 2 0x4>;
39 };
40 };
41
42 cpu-pmu {
43 compatible = "qcom,krait-pmu";
44 interrupts = <1 10 0x304>;
45 qcom,no-pc-write;
46 };
47
48 intc: interrupt-controller@2000000 {
49 compatible = "qcom,msm-qgic2";
50 interrupt-controller;
51 #interrupt-cells = <3>;
52 reg = < 0x02000000 0x1000 >,
53 < 0x02002000 0x1000 >;
54 };
55
56 timer@200a000 {
57 compatible = "qcom,kpss-timer", "qcom,msm-timer";
58 interrupts = <1 1 0x301>,
59 <1 2 0x301>,
60 <1 3 0x301>;
61 reg = <0x0200a000 0x100>;
62 clock-frequency = <27000000>,
63 <32768>;
64 cpu-offset = <0x80000>;
65 };
66
67 msmgpio: gpio@800000 {
68 compatible = "qcom,msm-gpio";
69 gpio-controller;
70 #gpio-cells = <2>;
71 ngpio = <150>;
72 interrupts = <0 16 0x4>;
73 interrupt-controller;
74 #interrupt-cells = <2>;
75 reg = <0x800000 0x4000>;
76 };
77
78 gcc: clock-controller@900000 {
79 compatible = "qcom,gcc-msm8960";
80 #clock-cells = <1>;
81 #reset-cells = <1>;
82 reg = <0x900000 0x4000>;
83 };
84
85 clock-controller@4000000 {
86 compatible = "qcom,mmcc-msm8960";
87 reg = <0x4000000 0x1000>;
88 #clock-cells = <1>;
89 #reset-cells = <1>;
90 };
91
92 acc0: clock-controller@2088000 {
93 compatible = "qcom,kpss-acc-v1";
94 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
95 };
96
97 acc1: clock-controller@2098000 {
98 compatible = "qcom,kpss-acc-v1";
99 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
100 };
101
102 saw0: regulator@2089000 {
103 compatible = "qcom,saw2";
104 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
105 regulator;
106 };
107
108 saw1: regulator@2099000 {
109 compatible = "qcom,saw2";
110 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
111 regulator;
112 };
113
114 serial@16440000 {
115 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
116 reg = <0x16440000 0x1000>,
117 <0x16400000 0x1000>;
118 interrupts = <0 154 0x0>;
119 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
120 clock-names = "core", "iface";
121 };
122
123 qcom,ssbi@500000 {
124 compatible = "qcom,ssbi";
125 reg = <0x500000 0x1000>;
126 qcom,controller-type = "pmic-arbiter";
127 };
128
129 rng@1a500000 {
130 compatible = "qcom,prng";
131 reg = <0x1a500000 0x200>;
132 clocks = <&gcc PRNG_CLK>;
133 clock-names = "core";
134 };
135};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 9e5dadb101eb..f68723918b3f 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -9,6 +9,54 @@
9 compatible = "qcom,msm8974"; 9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>; 10 interrupt-parent = <&intc>;
11 11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15 interrupts = <1 9 0xf04>;
16 compatible = "qcom,krait";
17 enable-method = "qcom,kpss-acc-v2";
18
19 cpu@0 {
20 device_type = "cpu";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 qcom,acc = <&acc0>;
24 };
25
26 cpu@1 {
27 device_type = "cpu";
28 reg = <1>;
29 next-level-cache = <&L2>;
30 qcom,acc = <&acc1>;
31 };
32
33 cpu@2 {
34 device_type = "cpu";
35 reg = <2>;
36 next-level-cache = <&L2>;
37 qcom,acc = <&acc2>;
38 };
39
40 cpu@3 {
41 device_type = "cpu";
42 reg = <3>;
43 next-level-cache = <&L2>;
44 qcom,acc = <&acc3>;
45 };
46
47 L2: l2-cache {
48 compatible = "cache";
49 cache-level = <2>;
50 interrupts = <0 2 0x4>;
51 qcom,saw = <&saw_l2>;
52 };
53 };
54
55 cpu-pmu {
56 compatible = "qcom,krait-pmu";
57 interrupts = <1 7 0xf04>;
58 };
59
12 soc: soc { 60 soc: soc {
13 #address-cells = <1>; 61 #address-cells = <1>;
14 #size-cells = <1>; 62 #size-cells = <1>;
@@ -91,6 +139,32 @@
91 }; 139 };
92 }; 140 };
93 141
142 saw_l2: regulator@f9012000 {
143 compatible = "qcom,saw2";
144 reg = <0xf9012000 0x1000>;
145 regulator;
146 };
147
148 acc0: clock-controller@f9088000 {
149 compatible = "qcom,kpss-acc-v2";
150 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
151 };
152
153 acc1: clock-controller@f9098000 {
154 compatible = "qcom,kpss-acc-v2";
155 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
156 };
157
158 acc2: clock-controller@f90a8000 {
159 compatible = "qcom,kpss-acc-v2";
160 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
161 };
162
163 acc3: clock-controller@f90b8000 {
164 compatible = "qcom,kpss-acc-v2";
165 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
166 };
167
94 restart@fc4ab000 { 168 restart@fc4ab000 {
95 compatible = "qcom,pshold"; 169 compatible = "qcom,pshold";
96 reg = <0xfc4ab000 0x4>; 170 reg = <0xfc4ab000 0x4>;
@@ -117,5 +191,12 @@
117 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 191 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
118 clock-names = "core", "iface"; 192 clock-names = "core", "iface";
119 }; 193 };
194
195 rng@f9bff000 {
196 compatible = "qcom,prng";
197 reg = <0xf9bff000 0x200>;
198 clocks = <&gcc GCC_PRNG_AHB_CLK>;
199 clock-names = "core";
200 };
120 }; 201 };
121}; 202};
diff --git a/arch/arm/boot/dts/r7s72100-genmai-reference.dts b/arch/arm/boot/dts/r7s72100-genmai-reference.dts
index da19c70ed82b..e664611a47c8 100644
--- a/arch/arm/boot/dts/r7s72100-genmai-reference.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai-reference.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r7s72100.dtsi" 12#include "r7s72100.dtsi"
13 13
14/ { 14/ {
15 model = "Genmai"; 15 model = "Genmai";
@@ -29,3 +29,14 @@
29 #size-cells = <1>; 29 #size-cells = <1>;
30 }; 30 };
31}; 31};
32
33&i2c2 {
34 status = "okay";
35 clock-frequency = <400000>;
36
37 eeprom@50 {
38 compatible = "renesas,24c128";
39 reg = <0x50>;
40 pagesize = <64>;
41 };
42};
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 46b82aa7dc4e..ee700717a34b 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -8,12 +8,26 @@
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11#include <dt-bindings/interrupt-controller/irq.h>
12
11/ { 13/ {
12 compatible = "renesas,r7s72100"; 14 compatible = "renesas,r7s72100";
13 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
14 #address-cells = <1>; 16 #address-cells = <1>;
15 #size-cells = <1>; 17 #size-cells = <1>;
16 18
19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 spi0 = &spi0;
25 spi1 = &spi1;
26 spi2 = &spi2;
27 spi3 = &spi3;
28 spi4 = &spi4;
29 };
30
17 cpus { 31 cpus {
18 #address-cells = <1>; 32 #address-cells = <1>;
19 #size-cells = <0>; 33 #size-cells = <0>;
@@ -33,4 +47,137 @@
33 reg = <0xe8201000 0x1000>, 47 reg = <0xe8201000 0x1000>,
34 <0xe8202000 0x1000>; 48 <0xe8202000 0x1000>;
35 }; 49 };
50
51 i2c0: i2c@fcfee000 {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
55 reg = <0xfcfee000 0x44>;
56 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
57 <0 158 IRQ_TYPE_EDGE_RISING>,
58 <0 159 IRQ_TYPE_EDGE_RISING>,
59 <0 160 IRQ_TYPE_LEVEL_HIGH>,
60 <0 161 IRQ_TYPE_LEVEL_HIGH>,
61 <0 162 IRQ_TYPE_LEVEL_HIGH>,
62 <0 163 IRQ_TYPE_LEVEL_HIGH>,
63 <0 164 IRQ_TYPE_LEVEL_HIGH>;
64 clock-frequency = <100000>;
65 status = "disabled";
66 };
67
68 i2c1: i2c@fcfee400 {
69 #address-cells = <1>;
70 #size-cells = <0>;
71 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
72 reg = <0xfcfee400 0x44>;
73 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
74 <0 166 IRQ_TYPE_EDGE_RISING>,
75 <0 167 IRQ_TYPE_EDGE_RISING>,
76 <0 168 IRQ_TYPE_LEVEL_HIGH>,
77 <0 169 IRQ_TYPE_LEVEL_HIGH>,
78 <0 170 IRQ_TYPE_LEVEL_HIGH>,
79 <0 171 IRQ_TYPE_LEVEL_HIGH>,
80 <0 172 IRQ_TYPE_LEVEL_HIGH>;
81 clock-frequency = <100000>;
82 status = "disabled";
83 };
84
85 i2c2: i2c@fcfee800 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
89 reg = <0xfcfee800 0x44>;
90 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
91 <0 174 IRQ_TYPE_EDGE_RISING>,
92 <0 175 IRQ_TYPE_EDGE_RISING>,
93 <0 176 IRQ_TYPE_LEVEL_HIGH>,
94 <0 177 IRQ_TYPE_LEVEL_HIGH>,
95 <0 178 IRQ_TYPE_LEVEL_HIGH>,
96 <0 179 IRQ_TYPE_LEVEL_HIGH>,
97 <0 180 IRQ_TYPE_LEVEL_HIGH>;
98 clock-frequency = <100000>;
99 status = "disabled";
100 };
101
102 i2c3: i2c@fcfeec00 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
106 reg = <0xfcfeec00 0x44>;
107 interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
108 <0 182 IRQ_TYPE_EDGE_RISING>,
109 <0 183 IRQ_TYPE_EDGE_RISING>,
110 <0 184 IRQ_TYPE_LEVEL_HIGH>,
111 <0 185 IRQ_TYPE_LEVEL_HIGH>,
112 <0 186 IRQ_TYPE_LEVEL_HIGH>,
113 <0 187 IRQ_TYPE_LEVEL_HIGH>,
114 <0 188 IRQ_TYPE_LEVEL_HIGH>;
115 clock-frequency = <100000>;
116 status = "disabled";
117 };
118
119 spi0: spi@e800c800 {
120 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
121 reg = <0xe800c800 0x24>;
122 interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
123 <0 239 IRQ_TYPE_LEVEL_HIGH>,
124 <0 240 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-names = "error", "rx", "tx";
126 num-cs = <1>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 status = "disabled";
130 };
131
132 spi1: spi@e800d000 {
133 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
134 reg = <0xe800d000 0x24>;
135 interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>,
136 <0 242 IRQ_TYPE_LEVEL_HIGH>,
137 <0 243 IRQ_TYPE_LEVEL_HIGH>;
138 interrupt-names = "error", "rx", "tx";
139 num-cs = <1>;
140 #address-cells = <1>;
141 #size-cells = <0>;
142 status = "disabled";
143 };
144
145 spi2: spi@e800d800 {
146 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
147 reg = <0xe800d800 0x24>;
148 interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>,
149 <0 245 IRQ_TYPE_LEVEL_HIGH>,
150 <0 246 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-names = "error", "rx", "tx";
152 num-cs = <1>;
153 #address-cells = <1>;
154 #size-cells = <0>;
155 status = "disabled";
156 };
157
158 spi3: spi@e800e000 {
159 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
160 reg = <0xe800e000 0x24>;
161 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>,
162 <0 248 IRQ_TYPE_LEVEL_HIGH>,
163 <0 249 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-names = "error", "rx", "tx";
165 num-cs = <1>;
166 #address-cells = <1>;
167 #size-cells = <0>;
168 status = "disabled";
169 };
170
171 spi4: spi@e800e800 {
172 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
173 reg = <0xe800e800 0x24>;
174 interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>,
175 <0 251 IRQ_TYPE_LEVEL_HIGH>,
176 <0 252 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-names = "error", "rx", "tx";
178 num-cs = <1>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 status = "disabled";
182 };
36}; 183};
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index bb62c7a906f4..06cda19dac6a 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -17,6 +17,7 @@
17/dts-v1/; 17/dts-v1/;
18#include "r8a7778.dtsi" 18#include "r8a7778.dtsi"
19#include <dt-bindings/interrupt-controller/irq.h> 19#include <dt-bindings/interrupt-controller/irq.h>
20#include <dt-bindings/gpio/gpio.h>
20 21
21/ { 22/ {
22 model = "bockw"; 23 model = "bockw";
@@ -84,7 +85,7 @@
84 85
85 sdhi0_pins: sd0 { 86 sdhi0_pins: sd0 {
86 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", 87 renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
87 "sdhi0_cd", "sdhi0_wp"; 88 "sdhi0_cd";
88 renesas,function = "sdhi0"; 89 renesas,function = "sdhi0";
89 }; 90 };
90 91
@@ -101,6 +102,7 @@
101 vmmc-supply = <&fixedregulator3v3>; 102 vmmc-supply = <&fixedregulator3v3>;
102 bus-width = <4>; 103 bus-width = <4>;
103 status = "okay"; 104 status = "okay";
105 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
104}; 106};
105 107
106&hspi0 { 108&hspi0 {
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ddb3bd7a8838..85c5b3b99f5e 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -203,46 +203,6 @@
203 status = "disabled"; 203 status = "disabled";
204 }; 204 };
205 205
206 i2c0: i2c@ffc70000 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "renesas,i2c-r8a7778";
210 reg = <0xffc70000 0x1000>;
211 interrupt-parent = <&gic>;
212 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
213 status = "disabled";
214 };
215
216 i2c1: i2c@ffc71000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "renesas,i2c-r8a7778";
220 reg = <0xffc71000 0x1000>;
221 interrupt-parent = <&gic>;
222 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
223 status = "disabled";
224 };
225
226 i2c2: i2c@ffc72000 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "renesas,i2c-r8a7778";
230 reg = <0xffc72000 0x1000>;
231 interrupt-parent = <&gic>;
232 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
233 status = "disabled";
234 };
235
236 i2c3: i2c@ffc73000 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "renesas,i2c-r8a7778";
240 reg = <0xffc73000 0x1000>;
241 interrupt-parent = <&gic>;
242 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
243 status = "disabled";
244 };
245
246 hspi0: spi@fffc7000 { 206 hspi0: spi@fffc7000 {
247 compatible = "renesas,hspi"; 207 compatible = "renesas,hspi";
248 reg = <0xfffc7000 0x18>; 208 reg = <0xfffc7000 0x18>;
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 57569cba1528..6e99eb2df076 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -1,7 +1,8 @@
1/* 1/*
2 * Device Tree Source for the Lager board 2 * Device Tree Source for the Lager board
3 * 3 *
4 * Copyright (C) 2013 Renesas Solutions Corp. 4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded, Inc.
5 * 6 *
6 * This file is licensed under the terms of the GNU General Public License 7 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any 8 * version 2. This program is licensed "as is" without any warranty of any
@@ -56,6 +57,54 @@
56 regulator-boot-on; 57 regulator-boot-on;
57 regulator-always-on; 58 regulator-always-on;
58 }; 59 };
60
61 vcc_sdhi0: regulator@1 {
62 compatible = "regulator-fixed";
63
64 regulator-name = "SDHI0 Vcc";
65 regulator-min-microvolt = <3300000>;
66 regulator-max-microvolt = <3300000>;
67
68 gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
69 enable-active-high;
70 };
71
72 vccq_sdhi0: regulator@2 {
73 compatible = "regulator-gpio";
74
75 regulator-name = "SDHI0 VccQ";
76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <3300000>;
78
79 gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
80 gpios-states = <1>;
81 states = <3300000 1
82 1800000 0>;
83 };
84
85 vcc_sdhi2: regulator@3 {
86 compatible = "regulator-fixed";
87
88 regulator-name = "SDHI2 Vcc";
89 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <3300000>;
91
92 gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
93 enable-active-high;
94 };
95
96 vccq_sdhi2: regulator@4 {
97 compatible = "regulator-gpio";
98
99 regulator-name = "SDHI2 VccQ";
100 regulator-min-microvolt = <1800000>;
101 regulator-max-microvolt = <3300000>;
102
103 gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
104 gpios-states = <1>;
105 states = <3300000 1
106 1800000 0>;
107 };
59}; 108};
60 109
61&extal_clk { 110&extal_clk {
@@ -63,23 +112,68 @@
63}; 112};
64 113
65&pfc { 114&pfc {
66 pinctrl-0 = <&scif0_pins &scif1_pins>; 115 pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>;
67 pinctrl-names = "default"; 116 pinctrl-names = "default";
68 117
118 du_pins: du {
119 renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
120 renesas,function = "du";
121 };
122
69 scif0_pins: serial0 { 123 scif0_pins: serial0 {
70 renesas,groups = "scif0_data"; 124 renesas,groups = "scif0_data";
71 renesas,function = "scif0"; 125 renesas,function = "scif0";
72 }; 126 };
73 127
128 ether_pins: ether {
129 renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
130 renesas,function = "eth";
131 };
132
133 phy1_pins: phy1 {
134 renesas,groups = "intc_irq0";
135 renesas,function = "intc";
136 };
137
74 scif1_pins: serial1 { 138 scif1_pins: serial1 {
75 renesas,groups = "scif1_data"; 139 renesas,groups = "scif1_data";
76 renesas,function = "scif1"; 140 renesas,function = "scif1";
77 }; 141 };
78 142
143 sdhi0_pins: sd0 {
144 renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
145 renesas,function = "sdhi0";
146 };
147
148 sdhi2_pins: sd2 {
149 renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
150 renesas,function = "sdhi2";
151 };
152
79 mmc1_pins: mmc1 { 153 mmc1_pins: mmc1 {
80 renesas,groups = "mmc1_data8", "mmc1_ctrl"; 154 renesas,groups = "mmc1_data8", "mmc1_ctrl";
81 renesas,function = "mmc1"; 155 renesas,function = "mmc1";
82 }; 156 };
157
158 qspi_pins: spi {
159 renesas,groups = "qspi_ctrl", "qspi_data4";
160 renesas,function = "qspi";
161 };
162};
163
164&ether {
165 pinctrl-0 = <&ether_pins &phy1_pins>;
166 pinctrl-names = "default";
167
168 phy-handle = <&phy1>;
169 renesas,ether-link-active-low;
170 status = "ok";
171
172 phy1: ethernet-phy@1 {
173 reg = <1>;
174 interrupt-parent = <&irqc0>;
175 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
176 };
83}; 177};
84 178
85&mmcif1 { 179&mmcif1 {
@@ -91,3 +185,58 @@
91 non-removable; 185 non-removable;
92 status = "okay"; 186 status = "okay";
93}; 187};
188
189&sata1 {
190 status = "okay";
191};
192
193&spi {
194 pinctrl-0 = <&qspi_pins>;
195 pinctrl-names = "default";
196
197 status = "okay";
198
199 flash: flash@0 {
200 #address-cells = <1>;
201 #size-cells = <1>;
202 compatible = "spansion,s25fl512s";
203 reg = <0>;
204 spi-max-frequency = <30000000>;
205 m25p,fast-read;
206
207 partition@0 {
208 label = "loader";
209 reg = <0x00000000 0x00040000>;
210 read-only;
211 };
212 partition@40000 {
213 label = "user";
214 reg = <0x00040000 0x00400000>;
215 read-only;
216 };
217 partition@440000 {
218 label = "flash";
219 reg = <0x00440000 0x03bc0000>;
220 };
221 };
222};
223
224&sdhi0 {
225 pinctrl-0 = <&sdhi0_pins>;
226 pinctrl-names = "default";
227
228 vmmc-supply = <&vcc_sdhi0>;
229 vqmmc-supply = <&vccq_sdhi0>;
230 cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
231 status = "okay";
232};
233
234&sdhi2 {
235 pinctrl-0 = <&sdhi2_pins>;
236 pinctrl-names = "default";
237
238 vmmc-supply = <&vcc_sdhi2>;
239 vqmmc-supply = <&vccq_sdhi2>;
240 cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
241 status = "okay";
242};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 71b1251f79c7..618e5b537eaf 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1,7 +1,8 @@
1/* 1/*
2 * Device Tree Source for the r8a7790 SoC 2 * Device Tree Source for the r8a7790 SoC
3 * 3 *
4 * Copyright (C) 2013 Renesas Solutions Corp. 4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded Inc.
5 * 6 *
6 * This file is licensed under the terms of the GNU General Public License 7 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any 8 * version 2. This program is licensed "as is" without any warranty of any
@@ -18,6 +19,13 @@
18 #address-cells = <2>; 19 #address-cells = <2>;
19 #size-cells = <2>; 20 #size-cells = <2>;
20 21
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 };
28
21 cpus { 29 cpus {
22 #address-cells = <1>; 30 #address-cells = <1>;
23 #size-cells = <0>; 31 #size-cells = <0>;
@@ -94,7 +102,6 @@
94 gpio0: gpio@e6050000 { 102 gpio0: gpio@e6050000 {
95 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 103 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
96 reg = <0 0xe6050000 0 0x50>; 104 reg = <0 0xe6050000 0 0x50>;
97 interrupt-parent = <&gic>;
98 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 105 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
99 #gpio-cells = <2>; 106 #gpio-cells = <2>;
100 gpio-controller; 107 gpio-controller;
@@ -106,7 +113,6 @@
106 gpio1: gpio@e6051000 { 113 gpio1: gpio@e6051000 {
107 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 114 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
108 reg = <0 0xe6051000 0 0x50>; 115 reg = <0 0xe6051000 0 0x50>;
109 interrupt-parent = <&gic>;
110 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 116 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
111 #gpio-cells = <2>; 117 #gpio-cells = <2>;
112 gpio-controller; 118 gpio-controller;
@@ -118,7 +124,6 @@
118 gpio2: gpio@e6052000 { 124 gpio2: gpio@e6052000 {
119 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 125 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
120 reg = <0 0xe6052000 0 0x50>; 126 reg = <0 0xe6052000 0 0x50>;
121 interrupt-parent = <&gic>;
122 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 127 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
123 #gpio-cells = <2>; 128 #gpio-cells = <2>;
124 gpio-controller; 129 gpio-controller;
@@ -130,7 +135,6 @@
130 gpio3: gpio@e6053000 { 135 gpio3: gpio@e6053000 {
131 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 136 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
132 reg = <0 0xe6053000 0 0x50>; 137 reg = <0 0xe6053000 0 0x50>;
133 interrupt-parent = <&gic>;
134 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 138 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
135 #gpio-cells = <2>; 139 #gpio-cells = <2>;
136 gpio-controller; 140 gpio-controller;
@@ -142,7 +146,6 @@
142 gpio4: gpio@e6054000 { 146 gpio4: gpio@e6054000 {
143 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 147 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
144 reg = <0 0xe6054000 0 0x50>; 148 reg = <0 0xe6054000 0 0x50>;
145 interrupt-parent = <&gic>;
146 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 149 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
147 #gpio-cells = <2>; 150 #gpio-cells = <2>;
148 gpio-controller; 151 gpio-controller;
@@ -154,7 +157,6 @@
154 gpio5: gpio@e6055000 { 157 gpio5: gpio@e6055000 {
155 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 158 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
156 reg = <0 0xe6055000 0 0x50>; 159 reg = <0 0xe6055000 0 0x50>;
157 interrupt-parent = <&gic>;
158 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 160 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
159 #gpio-cells = <2>; 161 #gpio-cells = <2>;
160 gpio-controller; 162 gpio-controller;
@@ -166,8 +168,8 @@
166 thermal@e61f0000 { 168 thermal@e61f0000 {
167 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; 169 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
168 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 170 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
169 interrupt-parent = <&gic>;
170 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 171 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
171 }; 173 };
172 174
173 timer { 175 timer {
@@ -183,7 +185,6 @@
183 #interrupt-cells = <2>; 185 #interrupt-cells = <2>;
184 interrupt-controller; 186 interrupt-controller;
185 reg = <0 0xe61c0000 0 0x200>; 187 reg = <0 0xe61c0000 0 0x200>;
186 interrupt-parent = <&gic>;
187 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 188 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
188 <0 1 IRQ_TYPE_LEVEL_HIGH>, 189 <0 1 IRQ_TYPE_LEVEL_HIGH>,
189 <0 2 IRQ_TYPE_LEVEL_HIGH>, 190 <0 2 IRQ_TYPE_LEVEL_HIGH>,
@@ -195,7 +196,6 @@
195 #size-cells = <0>; 196 #size-cells = <0>;
196 compatible = "renesas,i2c-r8a7790"; 197 compatible = "renesas,i2c-r8a7790";
197 reg = <0 0xe6508000 0 0x40>; 198 reg = <0 0xe6508000 0 0x40>;
198 interrupt-parent = <&gic>;
199 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; 199 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp9_clks R8A7790_CLK_I2C0>; 200 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
201 status = "disabled"; 201 status = "disabled";
@@ -206,7 +206,6 @@
206 #size-cells = <0>; 206 #size-cells = <0>;
207 compatible = "renesas,i2c-r8a7790"; 207 compatible = "renesas,i2c-r8a7790";
208 reg = <0 0xe6518000 0 0x40>; 208 reg = <0 0xe6518000 0 0x40>;
209 interrupt-parent = <&gic>;
210 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; 209 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&mstp9_clks R8A7790_CLK_I2C1>; 210 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
212 status = "disabled"; 211 status = "disabled";
@@ -217,7 +216,6 @@
217 #size-cells = <0>; 216 #size-cells = <0>;
218 compatible = "renesas,i2c-r8a7790"; 217 compatible = "renesas,i2c-r8a7790";
219 reg = <0 0xe6530000 0 0x40>; 218 reg = <0 0xe6530000 0 0x40>;
220 interrupt-parent = <&gic>;
221 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; 219 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp9_clks R8A7790_CLK_I2C2>; 220 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
223 status = "disabled"; 221 status = "disabled";
@@ -228,7 +226,6 @@
228 #size-cells = <0>; 226 #size-cells = <0>;
229 compatible = "renesas,i2c-r8a7790"; 227 compatible = "renesas,i2c-r8a7790";
230 reg = <0 0xe6540000 0 0x40>; 228 reg = <0 0xe6540000 0 0x40>;
231 interrupt-parent = <&gic>;
232 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; 229 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&mstp9_clks R8A7790_CLK_I2C3>; 230 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
234 status = "disabled"; 231 status = "disabled";
@@ -237,7 +234,6 @@
237 mmcif0: mmcif@ee200000 { 234 mmcif0: mmcif@ee200000 {
238 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; 235 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
239 reg = <0 0xee200000 0 0x80>; 236 reg = <0 0xee200000 0 0x80>;
240 interrupt-parent = <&gic>;
241 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 237 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; 238 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
243 reg-io-width = <4>; 239 reg-io-width = <4>;
@@ -247,7 +243,6 @@
247 mmcif1: mmc@ee220000 { 243 mmcif1: mmc@ee220000 {
248 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; 244 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
249 reg = <0 0xee220000 0 0x80>; 245 reg = <0 0xee220000 0 0x80>;
250 interrupt-parent = <&gic>;
251 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; 246 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; 247 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
253 reg-io-width = <4>; 248 reg-io-width = <4>;
@@ -262,7 +257,6 @@
262 sdhi0: sd@ee100000 { 257 sdhi0: sd@ee100000 {
263 compatible = "renesas,sdhi-r8a7790"; 258 compatible = "renesas,sdhi-r8a7790";
264 reg = <0 0xee100000 0 0x200>; 259 reg = <0 0xee100000 0 0x200>;
265 interrupt-parent = <&gic>;
266 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 260 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; 261 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
268 cap-sd-highspeed; 262 cap-sd-highspeed;
@@ -272,7 +266,6 @@
272 sdhi1: sd@ee120000 { 266 sdhi1: sd@ee120000 {
273 compatible = "renesas,sdhi-r8a7790"; 267 compatible = "renesas,sdhi-r8a7790";
274 reg = <0 0xee120000 0 0x200>; 268 reg = <0 0xee120000 0 0x200>;
275 interrupt-parent = <&gic>;
276 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; 269 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; 270 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
278 cap-sd-highspeed; 271 cap-sd-highspeed;
@@ -282,7 +275,6 @@
282 sdhi2: sd@ee140000 { 275 sdhi2: sd@ee140000 {
283 compatible = "renesas,sdhi-r8a7790"; 276 compatible = "renesas,sdhi-r8a7790";
284 reg = <0 0xee140000 0 0x100>; 277 reg = <0 0xee140000 0 0x100>;
285 interrupt-parent = <&gic>;
286 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 278 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; 279 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
288 cap-sd-highspeed; 280 cap-sd-highspeed;
@@ -292,13 +284,129 @@
292 sdhi3: sd@ee160000 { 284 sdhi3: sd@ee160000 {
293 compatible = "renesas,sdhi-r8a7790"; 285 compatible = "renesas,sdhi-r8a7790";
294 reg = <0 0xee160000 0 0x100>; 286 reg = <0 0xee160000 0 0x100>;
295 interrupt-parent = <&gic>;
296 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; 287 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; 288 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
298 cap-sd-highspeed; 289 cap-sd-highspeed;
299 status = "disabled"; 290 status = "disabled";
300 }; 291 };
301 292
293 scifa0: serial@e6c40000 {
294 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
295 reg = <0 0xe6c40000 0 64>;
296 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
298 clock-names = "sci_ick";
299 status = "disabled";
300 };
301
302 scifa1: serial@e6c50000 {
303 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
304 reg = <0 0xe6c50000 0 64>;
305 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
307 clock-names = "sci_ick";
308 status = "disabled";
309 };
310
311 scifa2: serial@e6c60000 {
312 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
313 reg = <0 0xe6c60000 0 64>;
314 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
316 clock-names = "sci_ick";
317 status = "disabled";
318 };
319
320 scifb0: serial@e6c20000 {
321 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
322 reg = <0 0xe6c20000 0 64>;
323 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
325 clock-names = "sci_ick";
326 status = "disabled";
327 };
328
329 scifb1: serial@e6c30000 {
330 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
331 reg = <0 0xe6c30000 0 64>;
332 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
334 clock-names = "sci_ick";
335 status = "disabled";
336 };
337
338 scifb2: serial@e6ce0000 {
339 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
340 reg = <0 0xe6ce0000 0 64>;
341 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
343 clock-names = "sci_ick";
344 status = "disabled";
345 };
346
347 scif0: serial@e6e60000 {
348 compatible = "renesas,scif-r8a7790", "renesas,scif";
349 reg = <0 0xe6e60000 0 64>;
350 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
352 clock-names = "sci_ick";
353 status = "disabled";
354 };
355
356 scif1: serial@e6e68000 {
357 compatible = "renesas,scif-r8a7790", "renesas,scif";
358 reg = <0 0xe6e68000 0 64>;
359 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
361 clock-names = "sci_ick";
362 status = "disabled";
363 };
364
365 hscif0: serial@e62c0000 {
366 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
367 reg = <0 0xe62c0000 0 96>;
368 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
370 clock-names = "sci_ick";
371 status = "disabled";
372 };
373
374 hscif1: serial@e62c8000 {
375 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
376 reg = <0 0xe62c8000 0 96>;
377 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
379 clock-names = "sci_ick";
380 status = "disabled";
381 };
382
383 ether: ethernet@ee700000 {
384 compatible = "renesas,ether-r8a7790";
385 reg = <0 0xee700000 0 0x400>;
386 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
388 phy-mode = "rmii";
389 #address-cells = <1>;
390 #size-cells = <0>;
391 status = "disabled";
392 };
393
394 sata0: sata@ee300000 {
395 compatible = "renesas,sata-r8a7790";
396 reg = <0 0xee300000 0 0x2000>;
397 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
399 status = "disabled";
400 };
401
402 sata1: sata@ee500000 {
403 compatible = "renesas,sata-r8a7790";
404 reg = <0 0xee500000 0 0x2000>;
405 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
407 status = "disabled";
408 };
409
302 clocks { 410 clocks {
303 #address-cells = <2>; 411 #address-cells = <2>;
304 #size-cells = <2>; 412 #size-cells = <2>;
@@ -313,6 +421,29 @@
313 clock-output-names = "extal"; 421 clock-output-names = "extal";
314 }; 422 };
315 423
424 /*
425 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
426 * default. Boards that provide audio clocks should override them.
427 */
428 audio_clk_a: audio_clk_a {
429 compatible = "fixed-clock";
430 #clock-cells = <0>;
431 clock-frequency = <0>;
432 clock-output-names = "audio_clk_a";
433 };
434 audio_clk_b: audio_clk_b {
435 compatible = "fixed-clock";
436 #clock-cells = <0>;
437 clock-frequency = <0>;
438 clock-output-names = "audio_clk_b";
439 };
440 audio_clk_c: audio_clk_c {
441 compatible = "fixed-clock";
442 #clock-cells = <0>;
443 clock-frequency = <0>;
444 clock-output-names = "audio_clk_c";
445 };
446
316 /* Special CPG clocks */ 447 /* Special CPG clocks */
317 cpg_clocks: cpg_clocks@e6150000 { 448 cpg_clocks: cpg_clocks@e6150000 {
318 compatible = "renesas,r8a7790-cpg-clocks", 449 compatible = "renesas,r8a7790-cpg-clocks",
@@ -607,10 +738,16 @@
607 mstp8_clks: mstp8_clks@e6150990 { 738 mstp8_clks: mstp8_clks@e6150990 {
608 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 739 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
609 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 740 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
610 clocks = <&p_clk>; 741 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
742 <&zs_clk>, <&zs_clk>;
611 #clock-cells = <1>; 743 #clock-cells = <1>;
612 renesas,clock-indices = <R8A7790_CLK_ETHER>; 744 renesas,clock-indices = <
613 clock-output-names = "ether"; 745 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
746 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
747 R8A7790_CLK_SATA0
748 >;
749 clock-output-names =
750 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
614 }; 751 };
615 mstp9_clks: mstp9_clks@e6150994 { 752 mstp9_clks: mstp9_clks@e6150994 {
616 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 753 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -627,4 +764,15 @@
627 "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; 764 "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
628 }; 765 };
629 }; 766 };
767
768 spi: spi@e6b10000 {
769 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
770 reg = <0 0xe6b10000 0 0x2c>;
771 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
773 num-cs = <1>;
774 #address-cells = <1>;
775 #size-cells = <0>;
776 status = "disabled";
777 };
630}; 778};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
deleted file mode 100644
index 588ca17ea1f0..000000000000
--- a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Device Tree Source for the Koelsch board
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13#include "r8a7791.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15
16/ {
17 model = "Koelsch";
18 compatible = "renesas,koelsch-reference", "renesas,r8a7791";
19
20 chosen {
21 bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
22 };
23
24 memory@40000000 {
25 device_type = "memory";
26 reg = <0 0x40000000 0 0x80000000>;
27 };
28
29 lbsc {
30 #address-cells = <1>;
31 #size-cells = <1>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36
37 key-a {
38 gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
39 linux,code = <30>;
40 label = "SW30";
41 gpio-key,wakeup;
42 debounce-interval = <20>;
43 };
44 key-b {
45 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
46 linux,code = <48>;
47 label = "SW31";
48 gpio-key,wakeup;
49 debounce-interval = <20>;
50 };
51 key-c {
52 gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
53 linux,code = <46>;
54 label = "SW32";
55 gpio-key,wakeup;
56 debounce-interval = <20>;
57 };
58 key-d {
59 gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
60 linux,code = <32>;
61 label = "SW33";
62 gpio-key,wakeup;
63 debounce-interval = <20>;
64 };
65 key-e {
66 gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
67 linux,code = <18>;
68 label = "SW34";
69 gpio-key,wakeup;
70 debounce-interval = <20>;
71 };
72 key-f {
73 gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
74 linux,code = <33>;
75 label = "SW35";
76 gpio-key,wakeup;
77 debounce-interval = <20>;
78 };
79 key-g {
80 gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
81 linux,code = <34>;
82 label = "SW36";
83 gpio-key,wakeup;
84 debounce-interval = <20>;
85 };
86 };
87
88 leds {
89 compatible = "gpio-leds";
90 led6 {
91 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
92 };
93 led7 {
94 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
95 };
96 led8 {
97 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
98 };
99 };
100};
101
102&pfc {
103 pinctrl-0 = <&scif0_pins &scif1_pins>;
104 pinctrl-names = "default";
105
106 scif0_pins: serial0 {
107 renesas,groups = "scif0_data_d";
108 renesas,function = "scif0";
109 };
110
111 scif1_pins: serial1 {
112 renesas,groups = "scif1_data_d";
113 renesas,function = "scif1";
114 };
115};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index fd556c3483e3..bdd73e6657b2 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -2,7 +2,8 @@
2 * Device Tree Source for the Koelsch board 2 * Device Tree Source for the Koelsch board
3 * 3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation 4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded, Inc.
6 * 7 *
7 * This file is licensed under the terms of the GNU General Public License 8 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any 9 * version 2. This program is licensed "as is" without any warranty of any
@@ -23,7 +24,12 @@
23 24
24 memory@40000000 { 25 memory@40000000 {
25 device_type = "memory"; 26 device_type = "memory";
26 reg = <0 0x40000000 0 0x80000000>; 27 reg = <0 0x40000000 0 0x40000000>;
28 };
29
30 memory@200000000 {
31 device_type = "memory";
32 reg = <2 0x00000000 0 0x40000000>;
27 }; 33 };
28 34
29 lbsc { 35 lbsc {
@@ -31,6 +37,60 @@
31 #size-cells = <1>; 37 #size-cells = <1>;
32 }; 38 };
33 39
40 gpio-keys {
41 compatible = "gpio-keys";
42
43 key-a {
44 gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
45 linux,code = <30>;
46 label = "SW30";
47 gpio-key,wakeup;
48 debounce-interval = <20>;
49 };
50 key-b {
51 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
52 linux,code = <48>;
53 label = "SW31";
54 gpio-key,wakeup;
55 debounce-interval = <20>;
56 };
57 key-c {
58 gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
59 linux,code = <46>;
60 label = "SW32";
61 gpio-key,wakeup;
62 debounce-interval = <20>;
63 };
64 key-d {
65 gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
66 linux,code = <32>;
67 label = "SW33";
68 gpio-key,wakeup;
69 debounce-interval = <20>;
70 };
71 key-e {
72 gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
73 linux,code = <18>;
74 label = "SW34";
75 gpio-key,wakeup;
76 debounce-interval = <20>;
77 };
78 key-f {
79 gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
80 linux,code = <33>;
81 label = "SW35";
82 gpio-key,wakeup;
83 debounce-interval = <20>;
84 };
85 key-g {
86 gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
87 linux,code = <34>;
88 label = "SW36";
89 gpio-key,wakeup;
90 debounce-interval = <20>;
91 };
92 };
93
34 leds { 94 leds {
35 compatible = "gpio-leds"; 95 compatible = "gpio-leds";
36 led6 { 96 led6 {
@@ -43,16 +103,112 @@
43 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; 103 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
44 }; 104 };
45 }; 105 };
106
107 vcc_sdhi0: regulator@0 {
108 compatible = "regulator-fixed";
109
110 regulator-name = "SDHI0 Vcc";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113
114 gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
115 enable-active-high;
116 };
117
118 vccq_sdhi0: regulator@1 {
119 compatible = "regulator-gpio";
120
121 regulator-name = "SDHI0 VccQ";
122 regulator-min-microvolt = <1800000>;
123 regulator-max-microvolt = <3300000>;
124
125 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
126 gpios-states = <1>;
127 states = <3300000 1
128 1800000 0>;
129 };
130
131 vcc_sdhi1: regulator@2 {
132 compatible = "regulator-fixed";
133
134 regulator-name = "SDHI1 Vcc";
135 regulator-min-microvolt = <3300000>;
136 regulator-max-microvolt = <3300000>;
137
138 gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
139 enable-active-high;
140 };
141
142 vccq_sdhi1: regulator@3 {
143 compatible = "regulator-gpio";
144
145 regulator-name = "SDHI1 VccQ";
146 regulator-min-microvolt = <1800000>;
147 regulator-max-microvolt = <3300000>;
148
149 gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
150 gpios-states = <1>;
151 states = <3300000 1
152 1800000 0>;
153 };
154
155 vcc_sdhi2: regulator@4 {
156 compatible = "regulator-fixed";
157
158 regulator-name = "SDHI2 Vcc";
159 regulator-min-microvolt = <3300000>;
160 regulator-max-microvolt = <3300000>;
161
162 gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
163 enable-active-high;
164 };
165
166 vccq_sdhi2: regulator@5 {
167 compatible = "regulator-gpio";
168
169 regulator-name = "SDHI2 VccQ";
170 regulator-min-microvolt = <1800000>;
171 regulator-max-microvolt = <3300000>;
172
173 gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
174 gpios-states = <1>;
175 states = <3300000 1
176 1800000 0>;
177 };
46}; 178};
47 179
48&extal_clk { 180&extal_clk {
49 clock-frequency = <20000000>; 181 clock-frequency = <20000000>;
50}; 182};
51 183
184&i2c2 {
185 pinctrl-0 = <&i2c2_pins>;
186 pinctrl-names = "default";
187
188 status = "okay";
189 clock-frequency = <400000>;
190
191 eeprom@50 {
192 compatible = "renesas,24c02";
193 reg = <0x50>;
194 pagesize = <16>;
195 };
196};
197
52&pfc { 198&pfc {
53 pinctrl-0 = <&scif0_pins &scif1_pins>; 199 pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>;
54 pinctrl-names = "default"; 200 pinctrl-names = "default";
55 201
202 i2c2_pins: i2c {
203 renesas,groups = "i2c2";
204 renesas,function = "i2c2";
205 };
206
207 du_pins: du {
208 renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0";
209 renesas,function = "du";
210 };
211
56 scif0_pins: serial0 { 212 scif0_pins: serial0 {
57 renesas,groups = "scif0_data_d"; 213 renesas,groups = "scif0_data_d";
58 renesas,function = "scif0"; 214 renesas,function = "scif0";
@@ -62,4 +218,116 @@
62 renesas,groups = "scif1_data_d"; 218 renesas,groups = "scif1_data_d";
63 renesas,function = "scif1"; 219 renesas,function = "scif1";
64 }; 220 };
221
222 ether_pins: ether {
223 renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
224 renesas,function = "eth";
225 };
226
227 phy1_pins: phy1 {
228 renesas,groups = "intc_irq0";
229 renesas,function = "intc";
230 };
231
232 sdhi0_pins: sd0 {
233 renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
234 renesas,function = "sdhi0";
235 };
236
237 sdhi1_pins: sd1 {
238 renesas,gpios = "sdhi1_data4", "sdhi1_ctrl";
239 renesas,function = "sdhi1";
240 };
241
242 sdhi2_pins: sd2 {
243 renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
244 renesas,function = "sdhi2";
245 };
246
247 qspi_pins: spi {
248 renesas,groups = "qspi_ctrl", "qspi_data4";
249 renesas,function = "qspi";
250 };
251};
252
253&ether {
254 pinctrl-0 = <&ether_pins &phy1_pins>;
255 pinctrl-names = "default";
256
257 phy-handle = <&phy1>;
258 renesas,ether-link-active-low;
259 status = "ok";
260
261 phy1: ethernet-phy@1 {
262 reg = <1>;
263 interrupt-parent = <&irqc0>;
264 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
265 };
266};
267
268&sata0 {
269 status = "okay";
270};
271
272&sdhi0 {
273 pinctrl-0 = <&sdhi0_pins>;
274 pinctrl-names = "default";
275
276 vmmc-supply = <&vcc_sdhi0>;
277 vqmmc-supply = <&vccq_sdhi0>;
278 cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
279 wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
280 status = "okay";
281};
282
283&sdhi1 {
284 pinctrl-0 = <&sdhi1_pins>;
285 pinctrl-names = "default";
286
287 vmmc-supply = <&vcc_sdhi1>;
288 vqmmc-supply = <&vccq_sdhi1>;
289 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
290 wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
291 status = "okay";
292};
293
294&sdhi2 {
295 pinctrl-0 = <&sdhi2_pins>;
296 pinctrl-names = "default";
297
298 vmmc-supply = <&vcc_sdhi2>;
299 vqmmc-supply = <&vccq_sdhi2>;
300 cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
301 status = "okay";
302};
303
304&spi {
305 pinctrl-0 = <&qspi_pins>;
306 pinctrl-names = "default";
307
308 status = "okay";
309
310 flash: flash@0 {
311 #address-cells = <1>;
312 #size-cells = <1>;
313 compatible = "spansion,s25fl512s";
314 reg = <0>;
315 spi-max-frequency = <30000000>;
316 m25p,fast-read;
317
318 partition@0 {
319 label = "loader";
320 reg = <0x00000000 0x00080000>;
321 read-only;
322 };
323 partition@80000 {
324 label = "bootenv";
325 reg = <0x00080000 0x00080000>;
326 read-only;
327 };
328 partition@100000 {
329 label = "data";
330 reg = <0x00100000 0x03f00000>;
331 };
332 };
65}; 333};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 19c65509a22d..46181708e59c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -2,7 +2,8 @@
2 * Device Tree Source for the r8a7791 SoC 2 * Device Tree Source for the r8a7791 SoC
3 * 3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation 4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
6 * 7 *
7 * This file is licensed under the terms of the GNU General Public License 8 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any 9 * version 2. This program is licensed "as is" without any warranty of any
@@ -19,6 +20,15 @@
19 #address-cells = <2>; 20 #address-cells = <2>;
20 #size-cells = <2>; 21 #size-cells = <2>;
21 22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
30 };
31
22 cpus { 32 cpus {
23 #address-cells = <1>; 33 #address-cells = <1>;
24 #size-cells = <0>; 34 #size-cells = <0>;
@@ -53,7 +63,6 @@
53 gpio0: gpio@e6050000 { 63 gpio0: gpio@e6050000 {
54 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 64 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
55 reg = <0 0xe6050000 0 0x50>; 65 reg = <0 0xe6050000 0 0x50>;
56 interrupt-parent = <&gic>;
57 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 66 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
58 #gpio-cells = <2>; 67 #gpio-cells = <2>;
59 gpio-controller; 68 gpio-controller;
@@ -65,7 +74,6 @@
65 gpio1: gpio@e6051000 { 74 gpio1: gpio@e6051000 {
66 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 75 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
67 reg = <0 0xe6051000 0 0x50>; 76 reg = <0 0xe6051000 0 0x50>;
68 interrupt-parent = <&gic>;
69 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 77 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
70 #gpio-cells = <2>; 78 #gpio-cells = <2>;
71 gpio-controller; 79 gpio-controller;
@@ -77,7 +85,6 @@
77 gpio2: gpio@e6052000 { 85 gpio2: gpio@e6052000 {
78 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 86 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
79 reg = <0 0xe6052000 0 0x50>; 87 reg = <0 0xe6052000 0 0x50>;
80 interrupt-parent = <&gic>;
81 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 88 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
82 #gpio-cells = <2>; 89 #gpio-cells = <2>;
83 gpio-controller; 90 gpio-controller;
@@ -89,7 +96,6 @@
89 gpio3: gpio@e6053000 { 96 gpio3: gpio@e6053000 {
90 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 97 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
91 reg = <0 0xe6053000 0 0x50>; 98 reg = <0 0xe6053000 0 0x50>;
92 interrupt-parent = <&gic>;
93 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 99 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
94 #gpio-cells = <2>; 100 #gpio-cells = <2>;
95 gpio-controller; 101 gpio-controller;
@@ -101,7 +107,6 @@
101 gpio4: gpio@e6054000 { 107 gpio4: gpio@e6054000 {
102 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 108 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
103 reg = <0 0xe6054000 0 0x50>; 109 reg = <0 0xe6054000 0 0x50>;
104 interrupt-parent = <&gic>;
105 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 110 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
106 #gpio-cells = <2>; 111 #gpio-cells = <2>;
107 gpio-controller; 112 gpio-controller;
@@ -113,7 +118,6 @@
113 gpio5: gpio@e6055000 { 118 gpio5: gpio@e6055000 {
114 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 119 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
115 reg = <0 0xe6055000 0 0x50>; 120 reg = <0 0xe6055000 0 0x50>;
116 interrupt-parent = <&gic>;
117 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 121 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
118 #gpio-cells = <2>; 122 #gpio-cells = <2>;
119 gpio-controller; 123 gpio-controller;
@@ -125,7 +129,6 @@
125 gpio6: gpio@e6055400 { 129 gpio6: gpio@e6055400 {
126 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 130 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
127 reg = <0 0xe6055400 0 0x50>; 131 reg = <0 0xe6055400 0 0x50>;
128 interrupt-parent = <&gic>;
129 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 132 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
130 #gpio-cells = <2>; 133 #gpio-cells = <2>;
131 gpio-controller; 134 gpio-controller;
@@ -137,7 +140,6 @@
137 gpio7: gpio@e6055800 { 140 gpio7: gpio@e6055800 {
138 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 141 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
139 reg = <0 0xe6055800 0 0x50>; 142 reg = <0 0xe6055800 0 0x50>;
140 interrupt-parent = <&gic>;
141 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 143 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
142 #gpio-cells = <2>; 144 #gpio-cells = <2>;
143 gpio-controller; 145 gpio-controller;
@@ -149,8 +151,8 @@
149 thermal@e61f0000 { 151 thermal@e61f0000 {
150 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; 152 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
151 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 153 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
152 interrupt-parent = <&gic>;
153 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 154 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
154 }; 156 };
155 157
156 timer { 158 timer {
@@ -166,7 +168,6 @@
166 #interrupt-cells = <2>; 168 #interrupt-cells = <2>;
167 interrupt-controller; 169 interrupt-controller;
168 reg = <0 0xe61c0000 0 0x200>; 170 reg = <0 0xe61c0000 0 0x200>;
169 interrupt-parent = <&gic>;
170 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 171 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
171 <0 1 IRQ_TYPE_LEVEL_HIGH>, 172 <0 1 IRQ_TYPE_LEVEL_HIGH>,
172 <0 2 IRQ_TYPE_LEVEL_HIGH>, 173 <0 2 IRQ_TYPE_LEVEL_HIGH>,
@@ -179,12 +180,288 @@
179 <0 17 IRQ_TYPE_LEVEL_HIGH>; 180 <0 17 IRQ_TYPE_LEVEL_HIGH>;
180 }; 181 };
181 182
183 i2c0: i2c@e6508000 {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "renesas,i2c-r8a7791";
187 reg = <0 0xe6508000 0 0x40>;
188 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
190 status = "disabled";
191 };
192
193 i2c1: i2c@e6518000 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "renesas,i2c-r8a7791";
197 reg = <0 0xe6518000 0 0x40>;
198 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
200 status = "disabled";
201 };
202
203 i2c2: i2c@e6530000 {
204 #address-cells = <1>;
205 #size-cells = <0>;
206 compatible = "renesas,i2c-r8a7791";
207 reg = <0 0xe6530000 0 0x40>;
208 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
210 status = "disabled";
211 };
212
213 i2c3: i2c@e6540000 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "renesas,i2c-r8a7791";
217 reg = <0 0xe6540000 0 0x40>;
218 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
220 status = "disabled";
221 };
222
223 i2c4: i2c@e6520000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "renesas,i2c-r8a7791";
227 reg = <0 0xe6520000 0 0x40>;
228 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
230 status = "disabled";
231 };
232
233 i2c5: i2c@e6528000 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "renesas,i2c-r8a7791";
237 reg = <0 0xe6528000 0 0x40>;
238 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
240 status = "disabled";
241 };
242
182 pfc: pfc@e6060000 { 243 pfc: pfc@e6060000 {
183 compatible = "renesas,pfc-r8a7791"; 244 compatible = "renesas,pfc-r8a7791";
184 reg = <0 0xe6060000 0 0x250>; 245 reg = <0 0xe6060000 0 0x250>;
185 #gpio-range-cells = <3>; 246 #gpio-range-cells = <3>;
186 }; 247 };
187 248
249 sdhi0: sd@ee100000 {
250 compatible = "renesas,sdhi-r8a7791";
251 reg = <0 0xee100000 0 0x200>;
252 interrupt-parent = <&gic>;
253 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
255 status = "disabled";
256 };
257
258 sdhi1: sd@ee140000 {
259 compatible = "renesas,sdhi-r8a7791";
260 reg = <0 0xee140000 0 0x100>;
261 interrupt-parent = <&gic>;
262 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
264 status = "disabled";
265 };
266
267 sdhi2: sd@ee160000 {
268 compatible = "renesas,sdhi-r8a7791";
269 reg = <0 0xee160000 0 0x100>;
270 interrupt-parent = <&gic>;
271 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
273 status = "disabled";
274 };
275
276 scifa0: serial@e6c40000 {
277 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
278 reg = <0 0xe6c40000 0 64>;
279 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
281 clock-names = "sci_ick";
282 status = "disabled";
283 };
284
285 scifa1: serial@e6c50000 {
286 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
287 reg = <0 0xe6c50000 0 64>;
288 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
290 clock-names = "sci_ick";
291 status = "disabled";
292 };
293
294 scifa2: serial@e6c60000 {
295 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
296 reg = <0 0xe6c60000 0 64>;
297 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
299 clock-names = "sci_ick";
300 status = "disabled";
301 };
302
303 scifa3: serial@e6c70000 {
304 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
305 reg = <0 0xe6c70000 0 64>;
306 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
308 clock-names = "sci_ick";
309 status = "disabled";
310 };
311
312 scifa4: serial@e6c78000 {
313 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
314 reg = <0 0xe6c78000 0 64>;
315 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
317 clock-names = "sci_ick";
318 status = "disabled";
319 };
320
321 scifa5: serial@e6c80000 {
322 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
323 reg = <0 0xe6c80000 0 64>;
324 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
326 clock-names = "sci_ick";
327 status = "disabled";
328 };
329
330 scifb0: serial@e6c20000 {
331 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
332 reg = <0 0xe6c20000 0 64>;
333 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
335 clock-names = "sci_ick";
336 status = "disabled";
337 };
338
339 scifb1: serial@e6c30000 {
340 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
341 reg = <0 0xe6c30000 0 64>;
342 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
344 clock-names = "sci_ick";
345 status = "disabled";
346 };
347
348 scifb2: serial@e6ce0000 {
349 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
350 reg = <0 0xe6ce0000 0 64>;
351 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
353 clock-names = "sci_ick";
354 status = "disabled";
355 };
356
357 scif0: serial@e6e60000 {
358 compatible = "renesas,scif-r8a7791", "renesas,scif";
359 reg = <0 0xe6e60000 0 64>;
360 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
362 clock-names = "sci_ick";
363 status = "disabled";
364 };
365
366 scif1: serial@e6e68000 {
367 compatible = "renesas,scif-r8a7791", "renesas,scif";
368 reg = <0 0xe6e68000 0 64>;
369 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
371 clock-names = "sci_ick";
372 status = "disabled";
373 };
374
375 scif2: serial@e6e58000 {
376 compatible = "renesas,scif-r8a7791", "renesas,scif";
377 reg = <0 0xe6e58000 0 64>;
378 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
380 clock-names = "sci_ick";
381 status = "disabled";
382 };
383
384 scif3: serial@e6ea8000 {
385 compatible = "renesas,scif-r8a7791", "renesas,scif";
386 reg = <0 0xe6ea8000 0 64>;
387 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
389 clock-names = "sci_ick";
390 status = "disabled";
391 };
392
393 scif4: serial@e6ee0000 {
394 compatible = "renesas,scif-r8a7791", "renesas,scif";
395 reg = <0 0xe6ee0000 0 64>;
396 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
398 clock-names = "sci_ick";
399 status = "disabled";
400 };
401
402 scif5: serial@e6ee8000 {
403 compatible = "renesas,scif-r8a7791", "renesas,scif";
404 reg = <0 0xe6ee8000 0 64>;
405 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
407 clock-names = "sci_ick";
408 status = "disabled";
409 };
410
411 hscif0: serial@e62c0000 {
412 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
413 reg = <0 0xe62c0000 0 96>;
414 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
416 clock-names = "sci_ick";
417 status = "disabled";
418 };
419
420 hscif1: serial@e62c8000 {
421 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
422 reg = <0 0xe62c8000 0 96>;
423 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
425 clock-names = "sci_ick";
426 status = "disabled";
427 };
428
429 hscif2: serial@e62d0000 {
430 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
431 reg = <0 0xe62d0000 0 96>;
432 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
434 clock-names = "sci_ick";
435 status = "disabled";
436 };
437
438 ether: ethernet@ee700000 {
439 compatible = "renesas,ether-r8a7791";
440 reg = <0 0xee700000 0 0x400>;
441 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
443 phy-mode = "rmii";
444 #address-cells = <1>;
445 #size-cells = <0>;
446 status = "disabled";
447 };
448
449 sata0: sata@ee300000 {
450 compatible = "renesas,sata-r8a7791";
451 reg = <0 0xee300000 0 0x2000>;
452 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
454 status = "disabled";
455 };
456
457 sata1: sata@ee500000 {
458 compatible = "renesas,sata-r8a7791";
459 reg = <0 0xee500000 0 0x2000>;
460 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
462 status = "disabled";
463 };
464
188 clocks { 465 clocks {
189 #address-cells = <2>; 466 #address-cells = <2>;
190 #size-cells = <2>; 467 #size-cells = <2>;
@@ -429,7 +706,7 @@
429 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 706 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
430 >; 707 >;
431 clock-output-names = 708 clock-output-names =
432 "scifa2", "scifa1", "scifa0", "misof2", "scifb0", 709 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
433 "scifb1", "msiof1", "scifb2"; 710 "scifb1", "msiof1", "scifb2";
434 }; 711 };
435 mstp3_clks: mstp3_clks@e615013c { 712 mstp3_clks: mstp3_clks@e615013c {
@@ -474,10 +751,15 @@
474 mstp8_clks: mstp8_clks@e6150990 { 751 mstp8_clks: mstp8_clks@e6150990 {
475 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 752 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
476 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 753 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
477 clocks = <&p_clk>; 754 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
755 <&zs_clk>;
478 #clock-cells = <1>; 756 #clock-cells = <1>;
479 renesas,clock-indices = <R8A7791_CLK_ETHER>; 757 renesas,clock-indices = <
480 clock-output-names = "ether"; 758 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
759 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
760 >;
761 clock-output-names =
762 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
481 }; 763 };
482 mstp9_clks: mstp9_clks@e6150994 { 764 mstp9_clks: mstp9_clks@e6150994 {
483 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 765 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -488,7 +770,7 @@
488 #clock-cells = <1>; 770 #clock-cells = <1>;
489 renesas,clock-indices = < 771 renesas,clock-indices = <
490 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD 772 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
491 R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 773 R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
492 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 774 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
493 >; 775 >;
494 clock-output-names = 776 clock-output-names =
@@ -506,4 +788,15 @@
506 clock-output-names = "scifa3", "scifa4", "scifa5"; 788 clock-output-names = "scifa3", "scifa4", "scifa5";
507 }; 789 };
508 }; 790 };
791
792 spi: spi@e6b10000 {
793 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
794 reg = <0 0xe6b10000 0 0x2c>;
795 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
797 num-cs = <1>;
798 #address-cells = <1>;
799 #size-cells = <0>;
800 status = "disabled";
801 };
509}; 802};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index be5d2b09a363..4d4dfbb59f4b 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -64,6 +64,19 @@
64 clock-names = "timer", "pclk"; 64 clock-names = "timer", "pclk";
65 }; 65 };
66 66
67 sram: sram@10080000 {
68 compatible = "mmio-sram";
69 reg = <0x10080000 0x10000>;
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0 0x10080000 0x10000>;
73
74 smp-sram@0 {
75 compatible = "rockchip,rk3066-smp-sram";
76 reg = <0x0 0x50>;
77 };
78 };
79
67 pinctrl@20008000 { 80 pinctrl@20008000 {
68 compatible = "rockchip,rk3066a-pinctrl"; 81 compatible = "rockchip,rk3066a-pinctrl";
69 reg = <0x20008000 0x150>; 82 reg = <0x20008000 0x150>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 1a26b03b3649..bb36596ea205 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -60,6 +60,19 @@
60 interrupts = <GIC_PPI 13 0xf04>; 60 interrupts = <GIC_PPI 13 0xf04>;
61 }; 61 };
62 62
63 sram: sram@10080000 {
64 compatible = "mmio-sram";
65 reg = <0x10080000 0x8000>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0 0x10080000 0x8000>;
69
70 smp-sram@0 {
71 compatible = "rockchip,rk3066-smp-sram";
72 reg = <0x0 0x50>;
73 };
74 };
75
63 pinctrl@20008000 { 76 pinctrl@20008000 {
64 compatible = "rockchip,rk3188-pinctrl"; 77 compatible = "rockchip,rk3188-pinctrl";
65 reg = <0x20008000 0xa0>, 78 reg = <0x20008000 0xa0>,
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 0fcbcfd67de2..26e5a968d49d 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -26,6 +26,16 @@
26 compatible = "simple-bus"; 26 compatible = "simple-bus";
27 ranges; 27 ranges;
28 28
29 scu@1013c000 {
30 compatible = "arm,cortex-a9-scu";
31 reg = <0x1013c000 0x100>;
32 };
33
34 pmu@20004000 {
35 compatible = "rockchip,rk3066-pmu";
36 reg = <0x20004000 0x100>;
37 };
38
29 gic: interrupt-controller@1013d000 { 39 gic: interrupt-controller@1013d000 {
30 compatible = "arm,cortex-a9-gic"; 40 compatible = "arm,cortex-a9-gic";
31 interrupt-controller; 41 interrupt-controller;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 3d5faf85f51b..eabcfdbb403a 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -239,7 +239,9 @@
239 }; 239 };
240 240
241 adc0: adc@f8018000 { 241 adc0: adc@f8018000 {
242 compatible = "atmel,at91sam9260-adc"; 242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "atmel,at91sam9x5-adc";
243 reg = <0xf8018000 0x100>; 245 reg = <0xf8018000 0x100>;
244 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; 246 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
245 pinctrl-names = "default"; 247 pinctrl-names = "default";
@@ -261,52 +263,39 @@
261 clocks = <&adc_clk>, 263 clocks = <&adc_clk>,
262 <&adc_op_clk>; 264 <&adc_op_clk>;
263 clock-names = "adc_clk", "adc_op_clk"; 265 clock-names = "adc_clk", "adc_op_clk";
264 atmel,adc-channel-base = <0x50>;
265 atmel,adc-channels-used = <0xfff>; 266 atmel,adc-channels-used = <0xfff>;
266 atmel,adc-drdy-mask = <0x1000000>;
267 atmel,adc-num-channels = <12>;
268 atmel,adc-startup-time = <40>; 267 atmel,adc-startup-time = <40>;
269 atmel,adc-status-register = <0x30>; 268 atmel,adc-use-external-triggers;
270 atmel,adc-trigger-register = <0xc0>;
271 atmel,adc-use-external;
272 atmel,adc-vref = <3000>; 269 atmel,adc-vref = <3000>;
273 atmel,adc-res = <10 12>; 270 atmel,adc-res = <10 12>;
274 atmel,adc-res-names = "lowres", "highres"; 271 atmel,adc-res-names = "lowres", "highres";
275 status = "disabled"; 272 status = "disabled";
276 273
277 trigger@0 { 274 trigger@0 {
275 reg = <0>;
278 trigger-name = "external-rising"; 276 trigger-name = "external-rising";
279 trigger-value = <0x1>; 277 trigger-value = <0x1>;
280 trigger-external; 278 trigger-external;
281 }; 279 };
282 trigger@1 { 280 trigger@1 {
281 reg = <1>;
283 trigger-name = "external-falling"; 282 trigger-name = "external-falling";
284 trigger-value = <0x2>; 283 trigger-value = <0x2>;
285 trigger-external; 284 trigger-external;
286 }; 285 };
287 trigger@2 { 286 trigger@2 {
287 reg = <2>;
288 trigger-name = "external-any"; 288 trigger-name = "external-any";
289 trigger-value = <0x3>; 289 trigger-value = <0x3>;
290 trigger-external; 290 trigger-external;
291 }; 291 };
292 trigger@3 { 292 trigger@3 {
293 reg = <3>;
293 trigger-name = "continuous"; 294 trigger-name = "continuous";
294 trigger-value = <0x6>; 295 trigger-value = <0x6>;
295 }; 296 };
296 }; 297 };
297 298
298 tsadcc: tsadcc@f8018000 {
299 compatible = "atmel,at91sam9x5-tsadcc";
300 reg = <0xf8018000 0x4000>;
301 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
302 atmel,tsadcc_clock = <300000>;
303 atmel,filtering_average = <0x03>;
304 atmel,pendet_debounce = <0x08>;
305 atmel,pendet_sensitivity = <0x02>;
306 atmel,ts_sample_hold_time = <0x0a>;
307 status = "disabled";
308 };
309
310 i2c2: i2c@f801c000 { 299 i2c2: i2c@f801c000 {
311 compatible = "atmel,at91sam9x5-i2c"; 300 compatible = "atmel,at91sam9x5-i2c";
312 reg = <0xf801c000 0x4000>; 301 reg = <0xf801c000 0x4000>;
@@ -1256,6 +1245,7 @@
1256 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; 1245 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1257 atmel,nand-addr-offset = <21>; 1246 atmel,nand-addr-offset = <21>;
1258 atmel,nand-cmd-offset = <22>; 1247 atmel,nand-cmd-offset = <22>;
1248 atmel,nand-has-dma;
1259 pinctrl-names = "default"; 1249 pinctrl-names = "default";
1260 pinctrl-0 = <&pinctrl_nand0_ale_cle>; 1250 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1261 atmel,pmecc-lookup-table-offset = <0x0 0x8000>; 1251 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
index f9bdde542ced..035ab72b3990 100644
--- a/arch/arm/boot/dts/sama5d3xdm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -23,10 +23,8 @@
23 }; 23 };
24 24
25 adc0: adc@f8018000 { 25 adc0: adc@f8018000 {
26 status = "disabled"; 26 atmel,adc-ts-wires = <4>;
27 }; 27 atmel,adc-ts-pressure-threshold = <10000>;
28
29 tsadcc: tsadcc@f8018000 {
30 status = "okay"; 28 status = "okay";
31 }; 29 };
32 30
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 537f1a5c07f5..56fc214e6d2c 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -92,7 +92,12 @@
92 #address-cells = <1>; 92 #address-cells = <1>;
93 #size-cells = <0>; 93 #size-cells = <0>;
94 94
95 osc: osc1 { 95 osc1: osc1 {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 };
99
100 osc2: osc2 {
96 #clock-cells = <0>; 101 #clock-cells = <0>;
97 compatible = "fixed-clock"; 102 compatible = "fixed-clock";
98 }; 103 };
@@ -100,7 +105,11 @@
100 f2s_periph_ref_clk: f2s_periph_ref_clk { 105 f2s_periph_ref_clk: f2s_periph_ref_clk {
101 #clock-cells = <0>; 106 #clock-cells = <0>;
102 compatible = "fixed-clock"; 107 compatible = "fixed-clock";
103 clock-frequency = <10000000>; 108 };
109
110 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
104 }; 113 };
105 114
106 main_pll: main_pll { 115 main_pll: main_pll {
@@ -108,7 +117,7 @@
108 #size-cells = <0>; 117 #size-cells = <0>;
109 #clock-cells = <0>; 118 #clock-cells = <0>;
110 compatible = "altr,socfpga-pll-clock"; 119 compatible = "altr,socfpga-pll-clock";
111 clocks = <&osc>; 120 clocks = <&osc1>;
112 reg = <0x40>; 121 reg = <0x40>;
113 122
114 mpuclk: mpuclk { 123 mpuclk: mpuclk {
@@ -162,7 +171,7 @@
162 #size-cells = <0>; 171 #size-cells = <0>;
163 #clock-cells = <0>; 172 #clock-cells = <0>;
164 compatible = "altr,socfpga-pll-clock"; 173 compatible = "altr,socfpga-pll-clock";
165 clocks = <&osc>; 174 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
166 reg = <0x80>; 175 reg = <0x80>;
167 176
168 emac0_clk: emac0_clk { 177 emac0_clk: emac0_clk {
@@ -213,7 +222,7 @@
213 #size-cells = <0>; 222 #size-cells = <0>;
214 #clock-cells = <0>; 223 #clock-cells = <0>;
215 compatible = "altr,socfpga-pll-clock"; 224 compatible = "altr,socfpga-pll-clock";
216 clocks = <&osc>; 225 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
217 reg = <0xC0>; 226 reg = <0xC0>;
218 227
219 ddr_dqs_clk: ddr_dqs_clk { 228 ddr_dqs_clk: ddr_dqs_clk {
@@ -415,6 +424,7 @@
415 compatible = "altr,socfpga-gate-clk"; 424 compatible = "altr,socfpga-gate-clk";
416 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 425 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
417 clk-gate = <0xa0 8>; 426 clk-gate = <0xa0 8>;
427 clk-phase = <0 135>;
418 }; 428 };
419 429
420 nand_x_clk: nand_x_clk { 430 nand_x_clk: nand_x_clk {
@@ -443,6 +453,7 @@
443 453
444 gmac0: ethernet@ff700000 { 454 gmac0: ethernet@ff700000 {
445 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 455 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
456 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
446 reg = <0xff700000 0x2000>; 457 reg = <0xff700000 0x2000>;
447 interrupts = <0 115 4>; 458 interrupts = <0 115 4>;
448 interrupt-names = "macirq"; 459 interrupt-names = "macirq";
@@ -454,6 +465,7 @@
454 465
455 gmac1: ethernet@ff702000 { 466 gmac1: ethernet@ff702000 {
456 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 467 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
468 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
457 reg = <0xff702000 0x2000>; 469 reg = <0xff702000 0x2000>;
458 interrupts = <0 120 4>; 470 interrupts = <0 120 4>;
459 interrupt-names = "macirq"; 471 interrupt-names = "macirq";
@@ -473,6 +485,17 @@
473 arm,data-latency = <2 1 1>; 485 arm,data-latency = <2 1 1>;
474 }; 486 };
475 487
488 mmc: dwmmc0@ff704000 {
489 compatible = "altr,socfpga-dw-mshc";
490 reg = <0xff704000 0x1000>;
491 interrupts = <0 139 4>;
492 fifo-depth = <0x400>;
493 #address-cells = <1>;
494 #size-cells = <0>;
495 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
496 clock-names = "biu", "ciu";
497 };
498
476 /* Local timer */ 499 /* Local timer */
477 timer@fffec600 { 500 timer@fffec600 {
478 compatible = "arm,cortex-a9-twd-timer"; 501 compatible = "arm,cortex-a9-twd-timer";
@@ -526,9 +549,9 @@
526 reg = <0xffd05000 0x1000>; 549 reg = <0xffd05000 0x1000>;
527 }; 550 };
528 551
529 sysmgr@ffd08000 { 552 sysmgr: sysmgr@ffd08000 {
530 compatible = "altr,sys-mgr"; 553 compatible = "altr,sys-mgr", "syscon";
531 reg = <0xffd08000 0x4000>; 554 reg = <0xffd08000 0x4000>;
532 }; 555 };
533 }; 556 };
534}; 557};
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index a85b4043f888..6c87b7070ca7 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -27,6 +27,17 @@
27 }; 27 };
28 }; 28 };
29 29
30 dwmmc0@ff704000 {
31 num-slots = <1>;
32 supports-highspeed;
33 broken-cd;
34
35 slot@0 {
36 reg = <0>;
37 bus-width = <4>;
38 };
39 };
40
30 serial0@ffc02000 { 41 serial0@ffc02000 {
31 clock-frequency = <100000000>; 42 clock-frequency = <100000000>;
32 }; 43 };
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 5beffb2265f4..a87ee1c07661 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,4 +37,25 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 aliases {
42 /* this allow the ethaddr uboot environmnet variable contents
43 * to be added to the gmac1 device tree blob.
44 */
45 ethernet0 = &gmac1;
46 };
47};
48
49&gmac1 {
50 status = "okay";
51 phy-mode = "rgmii";
52
53 rxd0-skew-ps = <0>;
54 rxd1-skew-ps = <0>;
55 rxd2-skew-ps = <0>;
56 rxd3-skew-ps = <0>;
57 txen-skew-ps = <0>;
58 txc-skew-ps = <2600>;
59 rxdv-skew-ps = <0>;
60 rxc-skew-ps = <2000>;
40}; 61};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index a8716f6dbe2e..ca41b0ebf461 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -28,6 +28,17 @@
28 }; 28 };
29 }; 29 };
30 30
31 dwmmc0@ff704000 {
32 num-slots = <1>;
33 supports-highspeed;
34 broken-cd;
35
36 slot@0 {
37 reg = <0>;
38 bus-width = <4>;
39 };
40 };
41
31 ethernet@ff702000 { 42 ethernet@ff702000 {
32 phy-mode = "rgmii"; 43 phy-mode = "rgmii";
33 phy-addr = <0xffffffff>; /* probe for phy addr */ 44 phy-addr = <0xffffffff>; /* probe for phy addr */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 2ee52ab8cabb..ae16d975196d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -38,3 +38,17 @@
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40}; 40};
41
42&gmac1 {
43 status = "okay";
44 phy-mode = "rgmii";
45
46 rxd0-skew-ps = <0>;
47 rxd1-skew-ps = <0>;
48 rxd2-skew-ps = <0>;
49 rxd3-skew-ps = <0>;
50 txen-skew-ps = <0>;
51 txc-skew-ps = <2600>;
52 rxdv-skew-ps = <0>;
53 rxc-skew-ps = <2000>;
54};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index 50b99a2c12ae..b79e2a2bf175 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -30,8 +30,25 @@
30 device_type = "memory"; 30 device_type = "memory";
31 reg = <0x0 0x40000000>; /* 1GB */ 31 reg = <0x0 0x40000000>; /* 1GB */
32 }; 32 };
33
34 aliases {
35 /* this allow the ethaddr uboot environmnet variable contents
36 * to be added to the gmac1 device tree blob.
37 */
38 ethernet0 = &gmac1;
39 };
33}; 40};
34 41
35&gmac1 { 42&gmac1 {
36 status = "okay"; 43 status = "okay";
44 phy-mode = "rgmii";
45
46 rxd0-skew-ps = <0>;
47 rxd1-skew-ps = <0>;
48 rxd2-skew-ps = <0>;
49 rxd3-skew-ps = <0>;
50 txen-skew-ps = <0>;
51 txc-skew-ps = <2600>;
52 rxdv-skew-ps = <0>;
53 rxc-skew-ps = <2000>;
37}; 54};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index d1ec0cab2dee..87d6f759a9c1 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,17 @@
41 }; 41 };
42 }; 42 };
43 43
44 dwmmc0@ff704000 {
45 num-slots = <1>;
46 supports-highspeed;
47 broken-cd;
48
49 slot@0 {
50 reg = <0>;
51 bus-width = <4>;
52 };
53 };
54
44 ethernet@ff700000 { 55 ethernet@ff700000 {
45 phy-mode = "gmii"; 56 phy-mode = "gmii";
46 status = "okay"; 57 status = "okay";
@@ -75,3 +86,8 @@
75 }; 86 };
76 }; 87 };
77}; 88};
89
90&gmac0 {
91 status = "okay";
92 phy-mode = "gmii";
93};
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index e0853ea02df2..e41eedca3ce3 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -705,7 +705,7 @@
705 #address-cells = <1>; 705 #address-cells = <1>;
706 #size-cells = <0>; 706 #size-cells = <0>;
707 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; 707 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
708 clock-names = "ssp0clk", "apb_pclk"; 708 clock-names = "SSPCLK", "apb_pclk";
709 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ 709 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
710 <&dma 8 0 0x0>; /* Logical - MemToDev */ 710 <&dma 8 0 0x0>; /* Logical - MemToDev */
711 dma-names = "rx", "tx"; 711 dma-names = "rx", "tx";
@@ -718,7 +718,7 @@
718 #address-cells = <1>; 718 #address-cells = <1>;
719 #size-cells = <0>; 719 #size-cells = <0>;
720 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; 720 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
721 clock-names = "ssp1clk", "apb_pclk"; 721 clock-names = "SSPCLK", "apb_pclk";
722 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ 722 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
723 <&dma 9 0 0x0>; /* Logical - MemToDev */ 723 <&dma 9 0 0x0>; /* Logical - MemToDev */
724 dma-names = "rx", "tx"; 724 dma-names = "rx", "tx";
@@ -732,7 +732,7 @@
732 #size-cells = <0>; 732 #size-cells = <0>;
733 /* Same clock wired to kernel and pclk */ 733 /* Same clock wired to kernel and pclk */
734 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; 734 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
735 clock-names = "spi0clk", "apb_pclk"; 735 clock-names = "SSPCLK", "apb_pclk";
736 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ 736 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
737 <&dma 0 0 0x0>; /* Logical - MemToDev */ 737 <&dma 0 0 0x0>; /* Logical - MemToDev */
738 dma-names = "rx", "tx"; 738 dma-names = "rx", "tx";
@@ -746,7 +746,7 @@
746 #size-cells = <0>; 746 #size-cells = <0>;
747 /* Same clock wired to kernel and pclk */ 747 /* Same clock wired to kernel and pclk */
748 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; 748 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
749 clock-names = "spi1clk", "apb_pclk"; 749 clock-names = "SSPCLK", "apb_pclk";
750 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ 750 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
751 <&dma 35 0 0x0>; /* Logical - MemToDev */ 751 <&dma 35 0 0x0>; /* Logical - MemToDev */
752 dma-names = "rx", "tx"; 752 dma-names = "rx", "tx";
@@ -760,7 +760,7 @@
760 #size-cells = <0>; 760 #size-cells = <0>;
761 /* Same clock wired to kernel and pclk */ 761 /* Same clock wired to kernel and pclk */
762 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; 762 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
763 clock-names = "spi2clk", "apb_pclk"; 763 clock-names = "SSPCLK", "apb_pclk";
764 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ 764 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
765 <&dma 33 0 0x0>; /* Logical - MemToDev */ 765 <&dma 33 0 0x0>; /* Logical - MemToDev */
766 dma-names = "rx", "tx"; 766 dma-names = "rx", "tx";
@@ -774,7 +774,7 @@
774 #size-cells = <0>; 774 #size-cells = <0>;
775 /* Same clock wired to kernel and pclk */ 775 /* Same clock wired to kernel and pclk */
776 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; 776 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
777 clock-names = "spi3clk", "apb_pclk"; 777 clock-names = "SSPCLK", "apb_pclk";
778 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ 778 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
779 <&dma 40 0 0x0>; /* Logical - MemToDev */ 779 <&dma 40 0 0x0>; /* Logical - MemToDev */
780 dma-names = "rx", "tx"; 780 dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
new file mode 100644
index 000000000000..30f8601da323
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -0,0 +1,428 @@
1/*
2 * Copyright 2014 Linaro Ltd.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 soc {
14 prcmu@80157000 {
15 ab8500 {
16 ab8500-gpio {
17 /* Hog a few default settings */
18 pinctrl-names = "default";
19 pinctrl-0 = <&gpio2_default_mode>,
20 <&gpio4_default_mode>,
21 <&gpio10_default_mode>,
22 <&gpio11_default_mode>,
23 <&gpio12_default_mode>,
24 <&gpio13_default_mode>,
25 <&gpio16_default_mode>,
26 <&gpio24_default_mode>,
27 <&gpio25_default_mode>,
28 <&gpio36_default_mode>,
29 <&gpio37_default_mode>,
30 <&gpio38_default_mode>,
31 <&gpio39_default_mode>,
32 <&gpio42_default_mode>,
33 <&gpio26_default_mode>,
34 <&gpio35_default_mode>,
35 <&ycbcr_default_mode>,
36 <&pwm_default_mode>,
37 <&adi1_default_mode>,
38 <&usbuicc_default_mode>,
39 <&dmic_default_mode>,
40 <&extcpena_default_mode>,
41 <&modsclsda_default_mode>;
42
43 /*
44 * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
45 * are muxed in as GPIO, and configured as INPUT PULL DOWN
46 */
47 gpio2 {
48 gpio2_default_mode: gpio2_default {
49 default_mux {
50 ste,function = "gpio";
51 ste,pins = "gpio2_a_1";
52 };
53 default_cfg {
54 ste,pins = "GPIO2_T9";
55 input-enable;
56 bias-pull-down;
57 };
58 };
59 };
60 gpio4 {
61 gpio4_default_mode: gpio4_default {
62 default_mux {
63 ste,function = "gpio";
64 ste,pins = "gpio4_a_1";
65 };
66 default_cfg {
67 ste,pins = "GPIO4_W2";
68 input-enable;
69 bias-pull-down;
70 };
71 };
72 };
73 gpio10 {
74 gpio10_default_mode: gpio10_default {
75 default_mux {
76 ste,function = "gpio";
77 ste,pins = "gpio10_d_1";
78 };
79 default_cfg {
80 ste,pins = "GPIO10_U17";
81 input-enable;
82 bias-pull-down;
83 };
84 };
85 };
86 gpio11 {
87 gpio11_default_mode: gpio11_default {
88 default_mux {
89 ste,function = "gpio";
90 ste,pins = "gpio11_d_1";
91 };
92 default_cfg {
93 ste,pins = "GPIO11_AA18";
94 input-enable;
95 bias-pull-down;
96 };
97 };
98 };
99 gpio12 {
100 gpio12_default_mode: gpio12_default {
101 default_mux {
102 ste,function = "gpio";
103 ste,pins = "gpio12_d_1";
104 };
105 default_cfg {
106 ste,pins = "GPIO12_U16";
107 input-enable;
108 bias-pull-down;
109 };
110 };
111 };
112 gpio13 {
113 gpio13_default_mode: gpio13_default {
114 default_mux {
115 ste,function = "gpio";
116 ste,pins = "gpio13_d_1";
117 };
118 default_cfg {
119 ste,pins = "GPIO13_W17";
120 input-enable;
121 bias-pull-down;
122 };
123 };
124 };
125 gpio16 {
126 gpio16_default_mode: gpio16_default {
127 default_mux {
128 ste,function = "gpio";
129 ste,pins = "gpio16_a_1";
130 };
131 default_cfg {
132 ste,pins = "GPIO16_F15";
133 input-enable;
134 bias-pull-down;
135 };
136 };
137 };
138 gpio24 {
139 gpio24_default_mode: gpio24_default {
140 default_mux {
141 ste,function = "gpio";
142 ste,pins = "gpio24_a_1";
143 };
144 default_cfg {
145 ste,pins = "GPIO24_T14";
146 input-enable;
147 bias-pull-down;
148 };
149 };
150 };
151 gpio25 {
152 gpio25_default_mode: gpio25_default {
153 default_mux {
154 ste,function = "gpio";
155 ste,pins = "gpio25_a_1";
156 };
157 default_cfg {
158 ste,pins = "GPIO25_R16";
159 input-enable;
160 bias-pull-down;
161 };
162 };
163 };
164 gpio36 {
165 gpio36_default_mode: gpio36_default {
166 default_mux {
167 ste,function = "gpio";
168 ste,pins = "gpio36_a_1";
169 };
170 default_cfg {
171 ste,pins = "GPIO36_A17";
172 input-enable;
173 bias-pull-down;
174 };
175 };
176 };
177 gpio37 {
178 gpio37_default_mode: gpio37_default {
179 default_mux {
180 ste,function = "gpio";
181 ste,pins = "gpio37_a_1";
182 };
183 default_cfg {
184 ste,pins = "GPIO37_E15";
185 input-enable;
186 bias-pull-down;
187 };
188 };
189 };
190 gpio38 {
191 gpio38_default_mode: gpio38_default {
192 default_mux {
193 ste,function = "gpio";
194 ste,pins = "gpio38_a_1";
195 };
196 default_cfg {
197 ste,pins = "GPIO38_C17";
198 input-enable;
199 bias-pull-down;
200 };
201 };
202 };
203 gpio39 {
204 gpio39_default_mode: gpio39_default {
205 default_mux {
206 ste,function = "gpio";
207 ste,pins = "gpio39_a_1";
208 };
209 default_cfg {
210 ste,pins = "GPIO39_E16";
211 input-enable;
212 bias-pull-down;
213 };
214 };
215 };
216 gpio42 {
217 gpio42_default_mode: gpio42_default {
218 default_mux {
219 ste,function = "gpio";
220 ste,pins = "gpio42_a_1";
221 };
222 default_cfg {
223 ste,pins = "GPIO42_U2";
224 input-enable;
225 bias-pull-down;
226 };
227 };
228 };
229 /*
230 * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW
231 */
232 gpio26 {
233 gpio26_default_mode: gpio26_default {
234 default_mux {
235 ste,function = "gpio";
236 ste,pins = "gpio26_d_1";
237 };
238 default_cfg {
239 ste,pins = "GPIO26_M16";
240 output-low;
241 };
242 };
243 };
244 gpio35 {
245 gpio35_default_mode: gpio35_default {
246 default_mux {
247 ste,function = "gpio";
248 ste,pins = "gpio35_d_1";
249 };
250 default_cfg {
251 ste,pins = "GPIO35_W15";
252 output-low;
253 };
254 };
255 };
256 /*
257 * This sets up the YCBCR connector pins, i.e. analog video out.
258 * Set as input with no bias.
259 */
260 ycbcr {
261 ycbcr_default_mode: ycbcr_default {
262 default_mux {
263 ste,function = "ycbcr";
264 ste,pins = "ycbcr0123_d_1";
265 };
266 default_cfg {
267 ste,pins = "GPIO6_Y18",
268 "GPIO7_AA20",
269 "GPIO8_W18",
270 "GPIO9_AA19";
271 input-enable;
272 bias-disable;
273 };
274 };
275 };
276 /* This sets up the PWM pins 14 and 15 */
277 pwm {
278 pwm_default_mode: pwm_default {
279 default_mux {
280 ste,function = "pwmout";
281 ste,pins = "pwmout1_d_1", "pwmout2_d_1";
282 };
283 default_cfg {
284 ste,pins = "GPIO14_F14",
285 "GPIO15_B17";
286 input-enable;
287 bias-pull-down;
288 };
289 };
290 };
291 /* This sets up audio interface 1 */
292 adi1 {
293 adi1_default_mode: adi1_default {
294 default_mux {
295 ste,function = "adi1";
296 ste,pins = "adi1_d_1";
297 };
298 default_cfg {
299 ste,pins = "GPIO17_P5",
300 "GPIO18_R5",
301 "GPIO19_U5",
302 "GPIO20_T5";
303 input-enable;
304 bias-pull-down;
305 };
306 };
307 };
308 /* This sets up the USB UICC pins */
309 usbuicc {
310 usbuicc_default_mode: usbuicc_default {
311 default_mux {
312 ste,function = "usbuicc";
313 ste,pins = "usbuicc_d_1";
314 };
315 default_cfg {
316 ste,pins = "GPIO21_H19",
317 "GPIO22_G20",
318 "GPIO23_G19";
319 input-enable;
320 bias-pull-down;
321 };
322 };
323 };
324 /* This sets up the microphone pins */
325 dmic {
326 dmic_default_mode: dmic_default {
327 default_mux {
328 ste,function = "dmic";
329 ste,pins = "dmic12_d_1",
330 "dmic34_d_1",
331 "dmic56_d_1";
332 };
333 default_cfg {
334 ste,pins = "GPIO27_J6",
335 "GPIO28_K6",
336 "GPIO29_G6",
337 "GPIO30_H6",
338 "GPIO31_F5",
339 "GPIO32_G5";
340 input-enable;
341 bias-pull-down;
342 };
343 };
344 };
345 extcpena {
346 extcpena_default_mode: extcpena_default {
347 default_mux {
348 ste,function = "extcpena";
349 ste,pins = "extcpena_d_1";
350 };
351 default_cfg {
352 ste,pins = "GPIO34_R17";
353 input-enable;
354 bias-pull-down;
355 };
356 };
357 };
358 /* Modem I2C setup (SCL and SDA pins) */
359 modsclsda {
360 modsclsda_default_mode: modsclsda_default {
361 default_mux {
362 ste,function = "modsclsda";
363 ste,pins = "modsclsda_d_1";
364 };
365 default_cfg {
366 ste,pins = "GPIO40_T19",
367 "GPIO41_U19";
368 input-enable;
369 bias-pull-down;
370 };
371 };
372 };
373 /*
374 * Clock output pins associated with regulators.
375 */
376 sysclkreq2 {
377 sysclkreq2_default_mode: sysclkreq2_default {
378 default_mux {
379 ste,function = "sysclkreq";
380 ste,pins = "sysclkreq2_d_1";
381 };
382 default_cfg {
383 ste,pins = "GPIO1_T10";
384 input-enable;
385 bias-disable;
386 };
387 };
388 sysclkreq2_sleep_mode: sysclkreq2_sleep {
389 default_mux {
390 ste,function = "gpio";
391 ste,pins = "gpio1_a_1";
392 };
393 default_cfg {
394 ste,pins = "GPIO1_T10";
395 input-enable;
396 bias-pull-down;
397 };
398 };
399 };
400 sysclkreq4 {
401 sysclkreq4_default_mode: sysclkreq4_default {
402 default_mux {
403 ste,function = "sysclkreq";
404 ste,pins = "sysclkreq4_d_1";
405 };
406 default_cfg {
407 ste,pins = "GPIO3_U9";
408 input-enable;
409 bias-disable;
410 };
411 };
412 sysclkreq4_sleep_mode: sysclkreq4_sleep {
413 default_mux {
414 ste,function = "gpio";
415 ste,pins = "gpio3_a_1";
416 };
417 default_cfg {
418 ste,pins = "GPIO3_U9";
419 input-enable;
420 bias-pull-down;
421 };
422 };
423 };
424 };
425 };
426 };
427 };
428};
diff --git a/arch/arm/boot/dts/ste-href-ab8505.dtsi b/arch/arm/boot/dts/ste-href-ab8505.dtsi
new file mode 100644
index 000000000000..6006d62086a2
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-ab8505.dtsi
@@ -0,0 +1,240 @@
1/*
2 * Copyright 2014 Linaro Ltd.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 soc {
14 prcmu@80157000 {
15 ab8505 {
16 ab8505-gpio {
17 /* Hog a few default settings */
18 pinctrl-names = "default";
19 pinctrl-0 = <&gpio2_default_mode>,
20 <&gpio10_default_mode>,
21 <&gpio11_default_mode>,
22 <&gpio13_default_mode>,
23 <&gpio34_default_mode>,
24 <&gpio50_default_mode>,
25 <&pwm_default_mode>,
26 <&adi2_default_mode>,
27 <&modsclsda_default_mode>,
28 <&resethw_default_mode>,
29 <&service_default_mode>;
30
31 /*
32 * Pins 2, 10, 11, 13, 34 and 50
33 * are muxed in as GPIO, and configured as INPUT PULL DOWN
34 */
35 gpio2 {
36 gpio2_default_mode: gpio2_default {
37 default_mux {
38 ste,function = "gpio";
39 ste,pins = "gpio2_a_1";
40 };
41 default_cfg {
42 ste,pins = "GPIO2_R5";
43 input-enable;
44 bias-pull-down;
45 };
46 };
47 };
48 gpio10 {
49 gpio10_default_mode: gpio10_default {
50 default_mux {
51 ste,function = "gpio";
52 ste,pins = "gpio10_d_1";
53 };
54 default_cfg {
55 ste,pins = "GPIO10_B16";
56 input-enable;
57 bias-pull-down;
58 };
59 };
60 };
61 gpio11 {
62 gpio11_default_mode: gpio11_default {
63 default_mux {
64 ste,function = "gpio";
65 ste,pins = "gpio11_d_1";
66 };
67 default_cfg {
68 ste,pins = "GPIO11_B17";
69 input-enable;
70 bias-pull-down;
71 };
72 };
73 };
74 gpio13 {
75 gpio13_default_mode: gpio13_default {
76 default_mux {
77 ste,function = "gpio";
78 ste,pins = "gpio13_d_1";
79 };
80 default_cfg {
81 ste,pins = "GPIO13_D17";
82 input-enable;
83 bias-disable;
84 };
85 };
86 };
87 gpio34 {
88 gpio34_default_mode: gpio34_default {
89 default_mux {
90 ste,function = "gpio";
91 ste,pins = "gpio34_a_1";
92 };
93 default_cfg {
94 ste,pins = "GPIO34_H14";
95 input-enable;
96 bias-pull-down;
97 };
98 };
99 };
100 gpio50 {
101 gpio50_default_mode: gpio50_default {
102 default_mux {
103 ste,function = "gpio";
104 ste,pins = "gpio50_d_1";
105 };
106 default_cfg {
107 ste,pins = "GPIO50_L4";
108 input-enable;
109 bias-disable;
110 };
111 };
112 };
113 /* This sets up the PWM pin 14 */
114 pwm {
115 pwm_default_mode: pwm_default {
116 default_mux {
117 ste,function = "pwmout";
118 ste,pins = "pwmout1_d_1";
119 };
120 default_cfg {
121 ste,pins = "GPIO14_C16";
122 input-enable;
123 bias-pull-down;
124 };
125 };
126 };
127 /* This sets up audio interface 2 */
128 adi2 {
129 adi2_default_mode: adi2_default {
130 default_mux {
131 ste,function = "adi2";
132 ste,pins = "adi2_d_1";
133 };
134 default_cfg {
135 ste,pins = "GPIO17_P2",
136 "GPIO18_N3",
137 "GPIO19_T1",
138 "GPIO20_P3";
139 input-enable;
140 bias-pull-down;
141 };
142 };
143 };
144 /* Modem I2C setup (SCL and SDA pins) */
145 modsclsda {
146 modsclsda_default_mode: modsclsda_default {
147 default_mux {
148 ste,function = "modsclsda";
149 ste,pins = "modsclsda_d_1";
150 };
151 default_cfg {
152 ste,pins = "GPIO40_J15",
153 "GPIO41_J14";
154 input-enable;
155 bias-pull-down;
156 };
157 };
158 };
159 resethw {
160 resethw_default_mode: resethw_default {
161 default_mux {
162 ste,function = "resethw";
163 ste,pins = "resethw_d_1";
164 };
165 default_cfg {
166 ste,pins = "GPIO52_D16";
167 input-enable;
168 bias-pull-down;
169 };
170 };
171 };
172 service {
173 service_default_mode: service_default {
174 default_mux {
175 ste,function = "service";
176 ste,pins = "service_d_1";
177 };
178 default_cfg {
179 ste,pins = "GPIO53_D15";
180 input-enable;
181 bias-pull-down;
182 };
183 };
184 };
185 /*
186 * Clock output pins associated with regulators.
187 */
188 sysclkreq2 {
189 sysclkreq2_default_mode: sysclkreq2_default {
190 default_mux {
191 ste,function = "sysclkreq";
192 ste,pins = "sysclkreq2_d_1";
193 };
194 default_cfg {
195 ste,pins = "GPIO1_N4";
196 input-enable;
197 bias-disable;
198 };
199 };
200 sysclkreq2_sleep_mode: sysclkreq2_sleep {
201 default_mux {
202 ste,function = "gpio";
203 ste,pins = "gpio1_a_1";
204 };
205 default_cfg {
206 ste,pins = "GPIO1_N4";
207 input-enable;
208 bias-pull-down;
209 };
210 };
211 };
212 sysclkreq4 {
213 sysclkreq4_default_mode: sysclkreq4_default {
214 default_mux {
215 ste,function = "sysclkreq";
216 ste,pins = "sysclkreq4_d_1";
217 };
218 default_cfg {
219 ste,pins = "GPIO3_P5";
220 input-enable;
221 bias-disable;
222 };
223 };
224 sysclkreq4_sleep_mode: sysclkreq4_sleep {
225 default_mux {
226 ste,function = "gpio";
227 ste,pins = "gpio3_a_1";
228 };
229 default_cfg {
230 ste,pins = "GPIO3_P5";
231 input-enable;
232 bias-pull-down;
233 };
234 };
235 };
236 };
237 };
238 };
239 };
240};
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index 40f0ecdf9303..abc762e24fcb 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -12,6 +12,7 @@
12 */ 12 */
13 13
14#include "ste-dbx5x0.dtsi" 14#include "ste-dbx5x0.dtsi"
15#include "ste-href-ab8500.dtsi"
15#include "ste-href.dtsi" 16#include "ste-href.dtsi"
16 17
17/ { 18/ {
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 3b6d1181939b..c2341061b943 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include "ste-dbx5x0.dtsi" 12#include "ste-dbx5x0.dtsi"
13#include "ste-href-ab8500.dtsi"
13#include "ste-href.dtsi" 14#include "ste-href.dtsi"
14 15
15/ { 16/ {
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 97d5d21b7db7..a2f632d0be2a 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -11,6 +11,7 @@
11 11
12/dts-v1/; 12/dts-v1/;
13#include "ste-dbx5x0.dtsi" 13#include "ste-dbx5x0.dtsi"
14#include "ste-href-ab8500.dtsi"
14#include "ste-href-family-pinctrl.dtsi" 15#include "ste-href-family-pinctrl.dtsi"
15 16
16/ { 17/ {
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index a9da4800daf0..6fe688e9e4da 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -457,7 +457,7 @@
457 interrupt-parent = <&vica>; 457 interrupt-parent = <&vica>;
458 interrupts = <23>; 458 interrupts = <23>;
459 clocks = <&spi_clk>, <&spi_clk>; 459 clocks = <&spi_clk>, <&spi_clk>;
460 clock-names = "apb_pclk", "spi_clk"; 460 clock-names = "SSPCLK", "apb_pclk";
461 dmas = <&dmac 27 &dmac 28>; 461 dmas = <&dmac 27 &dmac 28>;
462 dma-names = "tx", "rx"; 462 dma-names = "tx", "rx";
463 num-cs = <3>; 463 num-cs = <3>;
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index 174c799df741..d047dbc28d61 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -34,5 +34,19 @@
34 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
35 clock-frequency = <100000000>; 35 clock-frequency = <100000000>;
36 }; 36 };
37
38 CLKS_GMAC0_PHY: clockgenA1@7 {
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <25000000>;
42 clock-output-names = "CLKS_GMAC0_PHY";
43 };
44
45 CLKS_ETH1_PHY: clockgenA0@7 {
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <25000000>;
49 clock-output-names = "CLKS_ETH1_PHY";
50 };
37 }; 51 };
38}; 52};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index e56449d41481..f09fb10a3791 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -7,6 +7,7 @@
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9#include "st-pincfg.h" 9#include "st-pincfg.h"
10#include <dt-bindings/interrupt-controller/arm-gic.h>
10/ { 11/ {
11 12
12 aliases { 13 aliases {
@@ -45,35 +46,49 @@
45 #size-cells = <1>; 46 #size-cells = <1>;
46 compatible = "st,stih415-sbc-pinctrl"; 47 compatible = "st,stih415-sbc-pinctrl";
47 st,syscfg = <&syscfg_sbc>; 48 st,syscfg = <&syscfg_sbc>;
49 reg = <0xfe61f080 0x4>;
50 reg-names = "irqmux";
51 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
52 interrupts-names = "irqmux";
48 ranges = <0 0xfe610000 0x5000>; 53 ranges = <0 0xfe610000 0x5000>;
49 54
50 PIO0: gpio@fe610000 { 55 PIO0: gpio@fe610000 {
51 gpio-controller; 56 gpio-controller;
52 #gpio-cells = <1>; 57 #gpio-cells = <1>;
58 interrupt-controller;
59 #interrupt-cells = <2>;
53 reg = <0 0x100>; 60 reg = <0 0x100>;
54 st,bank-name = "PIO0"; 61 st,bank-name = "PIO0";
55 }; 62 };
56 PIO1: gpio@fe611000 { 63 PIO1: gpio@fe611000 {
57 gpio-controller; 64 gpio-controller;
58 #gpio-cells = <1>; 65 #gpio-cells = <1>;
66 interrupt-controller;
67 #interrupt-cells = <2>;
59 reg = <0x1000 0x100>; 68 reg = <0x1000 0x100>;
60 st,bank-name = "PIO1"; 69 st,bank-name = "PIO1";
61 }; 70 };
62 PIO2: gpio@fe612000 { 71 PIO2: gpio@fe612000 {
63 gpio-controller; 72 gpio-controller;
64 #gpio-cells = <1>; 73 #gpio-cells = <1>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
65 reg = <0x2000 0x100>; 76 reg = <0x2000 0x100>;
66 st,bank-name = "PIO2"; 77 st,bank-name = "PIO2";
67 }; 78 };
68 PIO3: gpio@fe613000 { 79 PIO3: gpio@fe613000 {
69 gpio-controller; 80 gpio-controller;
70 #gpio-cells = <1>; 81 #gpio-cells = <1>;
82 interrupt-controller;
83 #interrupt-cells = <2>;
71 reg = <0x3000 0x100>; 84 reg = <0x3000 0x100>;
72 st,bank-name = "PIO3"; 85 st,bank-name = "PIO3";
73 }; 86 };
74 PIO4: gpio@fe614000 { 87 PIO4: gpio@fe614000 {
75 gpio-controller; 88 gpio-controller;
76 #gpio-cells = <1>; 89 #gpio-cells = <1>;
90 interrupt-controller;
91 #interrupt-cells = <2>;
77 reg = <0x4000 0x100>; 92 reg = <0x4000 0x100>;
78 st,bank-name = "PIO4"; 93 st,bank-name = "PIO4";
79 }; 94 };
@@ -104,6 +119,64 @@
104 }; 119 };
105 }; 120 };
106 }; 121 };
122
123 rc{
124 pinctrl_ir: ir0 {
125 st,pins {
126 ir = <&PIO4 0 ALT2 IN>;
127 };
128 };
129 };
130
131 gmac1 {
132 pinctrl_mii1: mii1 {
133 st,pins {
134 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
135 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
136 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
137 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
138 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
139 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
140 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
141 col = <&PIO0 7 ALT1 IN BYPASS 1000>;
142 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
143 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
144 crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
145 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
146 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
147 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
148 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
149 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
150 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
151 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
152 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
153 phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
154 };
155 };
156
157 pinctrl_rgmii1: rgmii1-0 {
158 st,pins {
159 txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
160 txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
161 txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
162 txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
163 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
164 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
165 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
166 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
167 rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
168 rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
169 rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
170 rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
171
172 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
173 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
174 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
175
176 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
177 };
178 };
179 };
107 }; 180 };
108 181
109 pin-controller-front { 182 pin-controller-front {
@@ -111,53 +184,73 @@
111 #size-cells = <1>; 184 #size-cells = <1>;
112 compatible = "st,stih415-front-pinctrl"; 185 compatible = "st,stih415-front-pinctrl";
113 st,syscfg = <&syscfg_front>; 186 st,syscfg = <&syscfg_front>;
187 reg = <0xfee0f080 0x4>;
188 reg-names = "irqmux";
189 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
190 interrupts-names = "irqmux";
114 ranges = <0 0xfee00000 0x8000>; 191 ranges = <0 0xfee00000 0x8000>;
115 192
116 PIO5: gpio@fee00000 { 193 PIO5: gpio@fee00000 {
117 gpio-controller; 194 gpio-controller;
118 #gpio-cells = <1>; 195 #gpio-cells = <1>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
119 reg = <0 0x100>; 198 reg = <0 0x100>;
120 st,bank-name = "PIO5"; 199 st,bank-name = "PIO5";
121 }; 200 };
122 PIO6: gpio@fee01000 { 201 PIO6: gpio@fee01000 {
123 gpio-controller; 202 gpio-controller;
124 #gpio-cells = <1>; 203 #gpio-cells = <1>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
125 reg = <0x1000 0x100>; 206 reg = <0x1000 0x100>;
126 st,bank-name = "PIO6"; 207 st,bank-name = "PIO6";
127 }; 208 };
128 PIO7: gpio@fee02000 { 209 PIO7: gpio@fee02000 {
129 gpio-controller; 210 gpio-controller;
130 #gpio-cells = <1>; 211 #gpio-cells = <1>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
131 reg = <0x2000 0x100>; 214 reg = <0x2000 0x100>;
132 st,bank-name = "PIO7"; 215 st,bank-name = "PIO7";
133 }; 216 };
134 PIO8: gpio@fee03000 { 217 PIO8: gpio@fee03000 {
135 gpio-controller; 218 gpio-controller;
136 #gpio-cells = <1>; 219 #gpio-cells = <1>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
137 reg = <0x3000 0x100>; 222 reg = <0x3000 0x100>;
138 st,bank-name = "PIO8"; 223 st,bank-name = "PIO8";
139 }; 224 };
140 PIO9: gpio@fee04000 { 225 PIO9: gpio@fee04000 {
141 gpio-controller; 226 gpio-controller;
142 #gpio-cells = <1>; 227 #gpio-cells = <1>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
143 reg = <0x4000 0x100>; 230 reg = <0x4000 0x100>;
144 st,bank-name = "PIO9"; 231 st,bank-name = "PIO9";
145 }; 232 };
146 PIO10: gpio@fee05000 { 233 PIO10: gpio@fee05000 {
147 gpio-controller; 234 gpio-controller;
148 #gpio-cells = <1>; 235 #gpio-cells = <1>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
149 reg = <0x5000 0x100>; 238 reg = <0x5000 0x100>;
150 st,bank-name = "PIO10"; 239 st,bank-name = "PIO10";
151 }; 240 };
152 PIO11: gpio@fee06000 { 241 PIO11: gpio@fee06000 {
153 gpio-controller; 242 gpio-controller;
154 #gpio-cells = <1>; 243 #gpio-cells = <1>;
244 interrupt-controller;
245 #interrupt-cells = <2>;
155 reg = <0x6000 0x100>; 246 reg = <0x6000 0x100>;
156 st,bank-name = "PIO11"; 247 st,bank-name = "PIO11";
157 }; 248 };
158 PIO12: gpio@fee07000 { 249 PIO12: gpio@fee07000 {
159 gpio-controller; 250 gpio-controller;
160 #gpio-cells = <1>; 251 #gpio-cells = <1>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
161 reg = <0x7000 0x100>; 254 reg = <0x7000 0x100>;
162 st,bank-name = "PIO12"; 255 st,bank-name = "PIO12";
163 }; 256 };
@@ -186,41 +279,57 @@
186 #size-cells = <1>; 279 #size-cells = <1>;
187 compatible = "st,stih415-rear-pinctrl"; 280 compatible = "st,stih415-rear-pinctrl";
188 st,syscfg = <&syscfg_rear>; 281 st,syscfg = <&syscfg_rear>;
282 reg = <0xfe82f080 0x4>;
283 reg-names = "irqmux";
284 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
285 interrupts-names = "irqmux";
189 ranges = <0 0xfe820000 0x8000>; 286 ranges = <0 0xfe820000 0x8000>;
190 287
191 PIO13: gpio@fe820000 { 288 PIO13: gpio@fe820000 {
192 gpio-controller; 289 gpio-controller;
193 #gpio-cells = <1>; 290 #gpio-cells = <1>;
291 interrupt-controller;
292 #interrupt-cells = <2>;
194 reg = <0 0x100>; 293 reg = <0 0x100>;
195 st,bank-name = "PIO13"; 294 st,bank-name = "PIO13";
196 }; 295 };
197 PIO14: gpio@fe821000 { 296 PIO14: gpio@fe821000 {
198 gpio-controller; 297 gpio-controller;
199 #gpio-cells = <1>; 298 #gpio-cells = <1>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
200 reg = <0x1000 0x100>; 301 reg = <0x1000 0x100>;
201 st,bank-name = "PIO14"; 302 st,bank-name = "PIO14";
202 }; 303 };
203 PIO15: gpio@fe822000 { 304 PIO15: gpio@fe822000 {
204 gpio-controller; 305 gpio-controller;
205 #gpio-cells = <1>; 306 #gpio-cells = <1>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
206 reg = <0x2000 0x100>; 309 reg = <0x2000 0x100>;
207 st,bank-name = "PIO15"; 310 st,bank-name = "PIO15";
208 }; 311 };
209 PIO16: gpio@fe823000 { 312 PIO16: gpio@fe823000 {
210 gpio-controller; 313 gpio-controller;
211 #gpio-cells = <1>; 314 #gpio-cells = <1>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
212 reg = <0x3000 0x100>; 317 reg = <0x3000 0x100>;
213 st,bank-name = "PIO16"; 318 st,bank-name = "PIO16";
214 }; 319 };
215 PIO17: gpio@fe824000 { 320 PIO17: gpio@fe824000 {
216 gpio-controller; 321 gpio-controller;
217 #gpio-cells = <1>; 322 #gpio-cells = <1>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
218 reg = <0x4000 0x100>; 325 reg = <0x4000 0x100>;
219 st,bank-name = "PIO17"; 326 st,bank-name = "PIO17";
220 }; 327 };
221 PIO18: gpio@fe825000 { 328 PIO18: gpio@fe825000 {
222 gpio-controller; 329 gpio-controller;
223 #gpio-cells = <1>; 330 #gpio-cells = <1>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
224 reg = <0x5000 0x100>; 333 reg = <0x5000 0x100>;
225 st,bank-name = "PIO18"; 334 st,bank-name = "PIO18";
226 }; 335 };
@@ -233,6 +342,77 @@
233 }; 342 };
234 }; 343 };
235 }; 344 };
345
346 gmac0{
347 pinctrl_mii0: mii0 {
348 st,pins {
349 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
350 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
351
352 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
353 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
354 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
355 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
356
357 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
358 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
359 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
360 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
361 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
362 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
363
364 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
365 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
366 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
367 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
368 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
369 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
370 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
371 phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
372
373 };
374 };
375
376 pinctrl_gmii0: gmii0 {
377 st,pins {
378 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
379 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
380 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
381 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
382
383 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
384 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
385 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
386 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
387 txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
388 txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
389 txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
390 txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
391
392 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
393 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
394 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
395 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
396 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
397 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
398
399 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
400 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
401 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
402 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
403 rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
404 rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
405 rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
406 rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
407
408 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
409 clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
410 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
411
412
413 };
414 };
415 };
236 }; 416 };
237 417
238 pin-controller-left { 418 pin-controller-left {
@@ -240,23 +420,33 @@
240 #size-cells = <1>; 420 #size-cells = <1>;
241 compatible = "st,stih415-left-pinctrl"; 421 compatible = "st,stih415-left-pinctrl";
242 st,syscfg = <&syscfg_left>; 422 st,syscfg = <&syscfg_left>;
423 reg = <0xfd6bf080 0x4>;
424 reg-names = "irqmux";
425 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
426 interrupts-names = "irqmux";
243 ranges = <0 0xfd6b0000 0x3000>; 427 ranges = <0 0xfd6b0000 0x3000>;
244 428
245 PIO100: gpio@fd6b0000 { 429 PIO100: gpio@fd6b0000 {
246 gpio-controller; 430 gpio-controller;
247 #gpio-cells = <1>; 431 #gpio-cells = <1>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
248 reg = <0 0x100>; 434 reg = <0 0x100>;
249 st,bank-name = "PIO100"; 435 st,bank-name = "PIO100";
250 }; 436 };
251 PIO101: gpio@fd6b1000 { 437 PIO101: gpio@fd6b1000 {
252 gpio-controller; 438 gpio-controller;
253 #gpio-cells = <1>; 439 #gpio-cells = <1>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
254 reg = <0x1000 0x100>; 442 reg = <0x1000 0x100>;
255 st,bank-name = "PIO101"; 443 st,bank-name = "PIO101";
256 }; 444 };
257 PIO102: gpio@fd6b2000 { 445 PIO102: gpio@fd6b2000 {
258 gpio-controller; 446 gpio-controller;
259 #gpio-cells = <1>; 447 #gpio-cells = <1>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
260 reg = <0x2000 0x100>; 450 reg = <0x2000 0x100>;
261 st,bank-name = "PIO102"; 451 st,bank-name = "PIO102";
262 }; 452 };
@@ -267,35 +457,49 @@
267 #size-cells = <1>; 457 #size-cells = <1>;
268 compatible = "st,stih415-right-pinctrl"; 458 compatible = "st,stih415-right-pinctrl";
269 st,syscfg = <&syscfg_right>; 459 st,syscfg = <&syscfg_right>;
460 reg = <0xfd33f080 0x4>;
461 reg-names = "irqmux";
462 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
463 interrupts-names = "irqmux";
270 ranges = <0 0xfd330000 0x5000>; 464 ranges = <0 0xfd330000 0x5000>;
271 465
272 PIO103: gpio@fd330000 { 466 PIO103: gpio@fd330000 {
273 gpio-controller; 467 gpio-controller;
274 #gpio-cells = <1>; 468 #gpio-cells = <1>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
275 reg = <0 0x100>; 471 reg = <0 0x100>;
276 st,bank-name = "PIO103"; 472 st,bank-name = "PIO103";
277 }; 473 };
278 PIO104: gpio@fd331000 { 474 PIO104: gpio@fd331000 {
279 gpio-controller; 475 gpio-controller;
280 #gpio-cells = <1>; 476 #gpio-cells = <1>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
281 reg = <0x1000 0x100>; 479 reg = <0x1000 0x100>;
282 st,bank-name = "PIO104"; 480 st,bank-name = "PIO104";
283 }; 481 };
284 PIO105: gpio@fd332000 { 482 PIO105: gpio@fd332000 {
285 gpio-controller; 483 gpio-controller;
286 #gpio-cells = <1>; 484 #gpio-cells = <1>;
485 interrupt-controller;
486 #interrupt-cells = <2>;
287 reg = <0x2000 0x100>; 487 reg = <0x2000 0x100>;
288 st,bank-name = "PIO105"; 488 st,bank-name = "PIO105";
289 }; 489 };
290 PIO106: gpio@fd333000 { 490 PIO106: gpio@fd333000 {
291 gpio-controller; 491 gpio-controller;
292 #gpio-cells = <1>; 492 #gpio-cells = <1>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
293 reg = <0x3000 0x100>; 495 reg = <0x3000 0x100>;
294 st,bank-name = "PIO106"; 496 st,bank-name = "PIO106";
295 }; 497 };
296 PIO107: gpio@fd334000 { 498 PIO107: gpio@fd334000 {
297 gpio-controller; 499 gpio-controller;
298 #gpio-cells = <1>; 500 #gpio-cells = <1>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
299 reg = <0x4000 0x100>; 503 reg = <0x4000 0x100>;
300 st,bank-name = "PIO107"; 504 st,bank-name = "PIO107";
301 }; 505 };
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d9c7dd1d95a4..d89064c20c8a 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -10,6 +10,7 @@
10#include "stih415-clock.dtsi" 10#include "stih415-clock.dtsi"
11#include "stih415-pinctrl.dtsi" 11#include "stih415-pinctrl.dtsi"
12#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset-controller/stih415-resets.h>
13/ { 14/ {
14 15
15 L2: cache-controller { 16 L2: cache-controller {
@@ -28,6 +29,16 @@
28 ranges; 29 ranges;
29 compatible = "simple-bus"; 30 compatible = "simple-bus";
30 31
32 powerdown: powerdown-controller {
33 #reset-cells = <1>;
34 compatible = "st,stih415-powerdown";
35 };
36
37 softreset: softreset-controller {
38 #reset-cells = <1>;
39 compatible = "st,stih415-softreset";
40 };
41
31 syscfg_sbc: sbc-syscfg@fe600000{ 42 syscfg_sbc: sbc-syscfg@fe600000{
32 compatible = "st,stih415-sbc-syscfg", "syscon"; 43 compatible = "st,stih415-sbc-syscfg", "syscon";
33 reg = <0xfe600000 0xb4>; 44 reg = <0xfe600000 0xb4>;
@@ -136,5 +147,64 @@
136 147
137 status = "disabled"; 148 status = "disabled";
138 }; 149 };
150
151 ethernet0: dwmac@fe810000 {
152 device_type = "network";
153 compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
154 status = "disabled";
155
156 reg = <0xfe810000 0x8000>, <0x148 0x4>;
157 reg-names = "stmmaceth", "sti-ethconf";
158
159 interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
160 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
161 resets = <&softreset STIH415_ETH0_SOFTRESET>;
162 reset-names = "stmmaceth";
163
164 snps,pbl = <32>;
165 snps,mixed-burst;
166 snps,force_sf_dma_mode;
167
168 st,syscon = <&syscfg_rear>;
169
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_mii0>;
172 clock-names = "stmmaceth";
173 clocks = <&CLKS_GMAC0_PHY>;
174 };
175
176 ethernet1: dwmac@fef08000 {
177 device_type = "network";
178 compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
179 status = "disabled";
180 reg = <0xfef08000 0x8000>, <0x74 0x4>;
181 reg-names = "stmmaceth", "sti-ethconf";
182 interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
183 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
184
185 snps,pbl = <32>;
186 snps,mixed-burst;
187 snps,force_sf_dma_mode;
188
189 st,syscon = <&syscfg_sbc>;
190
191 resets = <&softreset STIH415_ETH1_SOFTRESET>;
192 reset-names = "stmmaceth";
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_mii1>;
195 clock-names = "stmmaceth";
196 clocks = <&CLKS_ETH1_PHY>;
197 };
198
199 rc: rc@fe518000 {
200 compatible = "st,comms-irb";
201 reg = <0xfe518000 0x234>;
202 interrupts = <0 203 0>;
203 clocks = <&CLK_SYSIN>;
204 rx-mode = "infrared";
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_ir>;
207 resets = <&softreset STIH415_IRB_SOFTRESET>;
208 };
139 }; 209 };
140}; 210};
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1158d8..a6942c75cbbb 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
37 clock-frequency = <100000000>; 37 clock-frequency = <100000000>;
38 clock-output-names = "CLK_S_ICN_REG_0"; 38 clock-output-names = "CLK_S_ICN_REG_0";
39 }; 39 };
40
41 CLK_S_GMAC0_PHY: clockgenA1@7 {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <25000000>;
45 clock-output-names = "CLK_S_GMAC0_PHY";
46 };
47
48 CLK_S_ETH1_PHY: clockgenA0@7 {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <25000000>;
52 clock-output-names = "CLK_S_ETH1_PHY";
53 };
40 }; 54 };
41}; 55};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index b29ff4ba542c..aeea304086eb 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -8,6 +8,7 @@
8 * publishhed by the Free Software Foundation. 8 * publishhed by the Free Software Foundation.
9 */ 9 */
10#include "st-pincfg.h" 10#include "st-pincfg.h"
11#include <dt-bindings/interrupt-controller/arm-gic.h>
11/ { 12/ {
12 13
13 aliases { 14 aliases {
@@ -49,46 +50,69 @@
49 #size-cells = <1>; 50 #size-cells = <1>;
50 compatible = "st,stih416-sbc-pinctrl"; 51 compatible = "st,stih416-sbc-pinctrl";
51 st,syscfg = <&syscfg_sbc>; 52 st,syscfg = <&syscfg_sbc>;
53 reg = <0xfe61f080 0x4>;
54 reg-names = "irqmux";
55 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
56 interrupts-names = "irqmux";
52 ranges = <0 0xfe610000 0x6000>; 57 ranges = <0 0xfe610000 0x6000>;
53 58
54 PIO0: gpio@fe610000 { 59 PIO0: gpio@fe610000 {
55 gpio-controller; 60 gpio-controller;
56 #gpio-cells = <1>; 61 #gpio-cells = <1>;
62 interrupt-controller;
63 #interrupt-cells = <2>;
57 reg = <0 0x100>; 64 reg = <0 0x100>;
58 st,bank-name = "PIO0"; 65 st,bank-name = "PIO0";
59 }; 66 };
60 PIO1: gpio@fe611000 { 67 PIO1: gpio@fe611000 {
61 gpio-controller; 68 gpio-controller;
62 #gpio-cells = <1>; 69 #gpio-cells = <1>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
63 reg = <0x1000 0x100>; 72 reg = <0x1000 0x100>;
64 st,bank-name = "PIO1"; 73 st,bank-name = "PIO1";
65 }; 74 };
66 PIO2: gpio@fe612000 { 75 PIO2: gpio@fe612000 {
67 gpio-controller; 76 gpio-controller;
68 #gpio-cells = <1>; 77 #gpio-cells = <1>;
78 interrupt-controller;
79 #interrupt-cells = <2>;
69 reg = <0x2000 0x100>; 80 reg = <0x2000 0x100>;
70 st,bank-name = "PIO2"; 81 st,bank-name = "PIO2";
71 }; 82 };
72 PIO3: gpio@fe613000 { 83 PIO3: gpio@fe613000 {
73 gpio-controller; 84 gpio-controller;
74 #gpio-cells = <1>; 85 #gpio-cells = <1>;
86 interrupt-controller;
87 #interrupt-cells = <2>;
75 reg = <0x3000 0x100>; 88 reg = <0x3000 0x100>;
76 st,bank-name = "PIO3"; 89 st,bank-name = "PIO3";
77 }; 90 };
78 PIO4: gpio@fe614000 { 91 PIO4: gpio@fe614000 {
79 gpio-controller; 92 gpio-controller;
80 #gpio-cells = <1>; 93 #gpio-cells = <1>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
81 reg = <0x4000 0x100>; 96 reg = <0x4000 0x100>;
82 st,bank-name = "PIO4"; 97 st,bank-name = "PIO4";
83 }; 98 };
84 PIO40: gpio@fe615000 { 99 PIO40: gpio@fe615000 {
85 gpio-controller; 100 gpio-controller;
86 #gpio-cells = <1>; 101 #gpio-cells = <1>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
87 reg = <0x5000 0x100>; 104 reg = <0x5000 0x100>;
88 st,bank-name = "PIO40"; 105 st,bank-name = "PIO40";
89 st,retime-pin-mask = <0x7f>; 106 st,retime-pin-mask = <0x7f>;
90 }; 107 };
91 108
109 rc{
110 pinctrl_ir: ir0 {
111 st,pins {
112 ir = <&PIO4 0 ALT2 IN>;
113 };
114 };
115 };
92 sbc_serial1 { 116 sbc_serial1 {
93 pinctrl_sbc_serial1: sbc_serial1 { 117 pinctrl_sbc_serial1: sbc_serial1 {
94 st,pins { 118 st,pins {
@@ -115,6 +139,58 @@
115 }; 139 };
116 }; 140 };
117 }; 141 };
142
143 gmac1 {
144 pinctrl_mii1: mii1 {
145 st,pins {
146 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
147 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
148 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
149 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
150 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
151 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
152 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
153 col = <&PIO0 7 ALT1 IN BYPASS 1000>;
154
155 mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
156 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
157 crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
158 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
159 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
160 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
161 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
162 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
163
164 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
165 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
166 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
167 phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
168 };
169 };
170 pinctrl_rgmii1: rgmii1-0 {
171 st,pins {
172 txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
173 txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
174 txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
175 txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
176 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
177 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
178
179 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
180 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
181 rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
182 rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
183 rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
184 rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
185
186 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
187 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
188 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
189
190 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
191 };
192 };
193 };
118 }; 194 };
119 195
120 pin-controller-front { 196 pin-controller-front {
@@ -122,65 +198,89 @@
122 #size-cells = <1>; 198 #size-cells = <1>;
123 compatible = "st,stih416-front-pinctrl"; 199 compatible = "st,stih416-front-pinctrl";
124 st,syscfg = <&syscfg_front>; 200 st,syscfg = <&syscfg_front>;
201 reg = <0xfee0f080 0x4>;
202 reg-names = "irqmux";
203 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
204 interrupts-names = "irqmux";
125 ranges = <0 0xfee00000 0x10000>; 205 ranges = <0 0xfee00000 0x10000>;
126 206
127 PIO5: gpio@fee00000 { 207 PIO5: gpio@fee00000 {
128 gpio-controller; 208 gpio-controller;
129 #gpio-cells = <1>; 209 #gpio-cells = <1>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
130 reg = <0 0x100>; 212 reg = <0 0x100>;
131 st,bank-name = "PIO5"; 213 st,bank-name = "PIO5";
132 }; 214 };
133 PIO6: gpio@fee01000 { 215 PIO6: gpio@fee01000 {
134 gpio-controller; 216 gpio-controller;
135 #gpio-cells = <1>; 217 #gpio-cells = <1>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
136 reg = <0x1000 0x100>; 220 reg = <0x1000 0x100>;
137 st,bank-name = "PIO6"; 221 st,bank-name = "PIO6";
138 }; 222 };
139 PIO7: gpio@fee02000 { 223 PIO7: gpio@fee02000 {
140 gpio-controller; 224 gpio-controller;
141 #gpio-cells = <1>; 225 #gpio-cells = <1>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
142 reg = <0x2000 0x100>; 228 reg = <0x2000 0x100>;
143 st,bank-name = "PIO7"; 229 st,bank-name = "PIO7";
144 }; 230 };
145 PIO8: gpio@fee03000 { 231 PIO8: gpio@fee03000 {
146 gpio-controller; 232 gpio-controller;
147 #gpio-cells = <1>; 233 #gpio-cells = <1>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
148 reg = <0x3000 0x100>; 236 reg = <0x3000 0x100>;
149 st,bank-name = "PIO8"; 237 st,bank-name = "PIO8";
150 }; 238 };
151 PIO9: gpio@fee04000 { 239 PIO9: gpio@fee04000 {
152 gpio-controller; 240 gpio-controller;
153 #gpio-cells = <1>; 241 #gpio-cells = <1>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
154 reg = <0x4000 0x100>; 244 reg = <0x4000 0x100>;
155 st,bank-name = "PIO9"; 245 st,bank-name = "PIO9";
156 }; 246 };
157 PIO10: gpio@fee05000 { 247 PIO10: gpio@fee05000 {
158 gpio-controller; 248 gpio-controller;
159 #gpio-cells = <1>; 249 #gpio-cells = <1>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
160 reg = <0x5000 0x100>; 252 reg = <0x5000 0x100>;
161 st,bank-name = "PIO10"; 253 st,bank-name = "PIO10";
162 }; 254 };
163 PIO11: gpio@fee06000 { 255 PIO11: gpio@fee06000 {
164 gpio-controller; 256 gpio-controller;
165 #gpio-cells = <1>; 257 #gpio-cells = <1>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
166 reg = <0x6000 0x100>; 260 reg = <0x6000 0x100>;
167 st,bank-name = "PIO11"; 261 st,bank-name = "PIO11";
168 }; 262 };
169 PIO12: gpio@fee07000 { 263 PIO12: gpio@fee07000 {
170 gpio-controller; 264 gpio-controller;
171 #gpio-cells = <1>; 265 #gpio-cells = <1>;
266 interrupt-controller;
267 #interrupt-cells = <2>;
172 reg = <0x7000 0x100>; 268 reg = <0x7000 0x100>;
173 st,bank-name = "PIO12"; 269 st,bank-name = "PIO12";
174 }; 270 };
175 PIO30: gpio@fee08000 { 271 PIO30: gpio@fee08000 {
176 gpio-controller; 272 gpio-controller;
177 #gpio-cells = <1>; 273 #gpio-cells = <1>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
178 reg = <0x8000 0x100>; 276 reg = <0x8000 0x100>;
179 st,bank-name = "PIO30"; 277 st,bank-name = "PIO30";
180 }; 278 };
181 PIO31: gpio@fee09000 { 279 PIO31: gpio@fee09000 {
182 gpio-controller; 280 gpio-controller;
183 #gpio-cells = <1>; 281 #gpio-cells = <1>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
184 reg = <0x9000 0x100>; 284 reg = <0x9000 0x100>;
185 st,bank-name = "PIO31"; 285 st,bank-name = "PIO31";
186 }; 286 };
@@ -210,6 +310,19 @@
210 }; 310 };
211 }; 311 };
212 }; 312 };
313
314 fsm {
315 pinctrl_fsm: fsm {
316 st,pins {
317 spi-fsm-clk = <&PIO12 2 ALT1 OUT>;
318 spi-fsm-cs = <&PIO12 3 ALT1 OUT>;
319 spi-fsm-mosi = <&PIO12 4 ALT1 OUT>;
320 spi-fsm-miso = <&PIO12 5 ALT1 IN>;
321 spi-fsm-hol = <&PIO12 6 ALT1 OUT>;
322 spi-fsm-wp = <&PIO12 7 ALT1 OUT>;
323 };
324 };
325 };
213 }; 326 };
214 327
215 pin-controller-rear { 328 pin-controller-rear {
@@ -217,41 +330,57 @@
217 #size-cells = <1>; 330 #size-cells = <1>;
218 compatible = "st,stih416-rear-pinctrl"; 331 compatible = "st,stih416-rear-pinctrl";
219 st,syscfg = <&syscfg_rear>; 332 st,syscfg = <&syscfg_rear>;
333 reg = <0xfe82f080 0x4>;
334 reg-names = "irqmux";
335 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
336 interrupts-names = "irqmux";
220 ranges = <0 0xfe820000 0x6000>; 337 ranges = <0 0xfe820000 0x6000>;
221 338
222 PIO13: gpio@fe820000 { 339 PIO13: gpio@fe820000 {
223 gpio-controller; 340 gpio-controller;
224 #gpio-cells = <1>; 341 #gpio-cells = <1>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
225 reg = <0 0x100>; 344 reg = <0 0x100>;
226 st,bank-name = "PIO13"; 345 st,bank-name = "PIO13";
227 }; 346 };
228 PIO14: gpio@fe821000 { 347 PIO14: gpio@fe821000 {
229 gpio-controller; 348 gpio-controller;
230 #gpio-cells = <1>; 349 #gpio-cells = <1>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
231 reg = <0x1000 0x100>; 352 reg = <0x1000 0x100>;
232 st,bank-name = "PIO14"; 353 st,bank-name = "PIO14";
233 }; 354 };
234 PIO15: gpio@fe822000 { 355 PIO15: gpio@fe822000 {
235 gpio-controller; 356 gpio-controller;
236 #gpio-cells = <1>; 357 #gpio-cells = <1>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
237 reg = <0x2000 0x100>; 360 reg = <0x2000 0x100>;
238 st,bank-name = "PIO15"; 361 st,bank-name = "PIO15";
239 }; 362 };
240 PIO16: gpio@fe823000 { 363 PIO16: gpio@fe823000 {
241 gpio-controller; 364 gpio-controller;
242 #gpio-cells = <1>; 365 #gpio-cells = <1>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
243 reg = <0x3000 0x100>; 368 reg = <0x3000 0x100>;
244 st,bank-name = "PIO16"; 369 st,bank-name = "PIO16";
245 }; 370 };
246 PIO17: gpio@fe824000 { 371 PIO17: gpio@fe824000 {
247 gpio-controller; 372 gpio-controller;
248 #gpio-cells = <1>; 373 #gpio-cells = <1>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
249 reg = <0x4000 0x100>; 376 reg = <0x4000 0x100>;
250 st,bank-name = "PIO17"; 377 st,bank-name = "PIO17";
251 }; 378 };
252 PIO18: gpio@fe825000 { 379 PIO18: gpio@fe825000 {
253 gpio-controller; 380 gpio-controller;
254 #gpio-cells = <1>; 381 #gpio-cells = <1>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
255 reg = <0x5000 0x100>; 384 reg = <0x5000 0x100>;
256 st,bank-name = "PIO18"; 385 st,bank-name = "PIO18";
257 st,retime-pin-mask = <0xf>; 386 st,retime-pin-mask = <0xf>;
@@ -265,6 +394,63 @@
265 }; 394 };
266 }; 395 };
267 }; 396 };
397
398 gmac0 {
399 pinctrl_mii0: mii0 {
400 st,pins {
401 mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
402 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
403 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
404 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
405 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
406 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
407
408 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
409 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
410 crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
411 col = <&PIO15 3 ALT2 IN BYPASS 1000>;
412 mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
413 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
414
415 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
416 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
417 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
418 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
419 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
420 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
421 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
422 phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
423 };
424 };
425
426 pinctrl_gmii0: gmii0 {
427 st,pins {
428 };
429 };
430 pinctrl_rgmii0: rgmii0 {
431 st,pins {
432 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
433 txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
434 txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
435 txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
436 txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
437 txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
438 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
439
440 mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
441 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
442
443 rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
444 rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
445 rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
446 rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
447 rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
448 rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
449
450 clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
451 };
452 };
453 };
268 }; 454 };
269 455
270 pin-controller-fvdp-fe { 456 pin-controller-fvdp-fe {
@@ -272,23 +458,33 @@
272 #size-cells = <1>; 458 #size-cells = <1>;
273 compatible = "st,stih416-fvdp-fe-pinctrl"; 459 compatible = "st,stih416-fvdp-fe-pinctrl";
274 st,syscfg = <&syscfg_fvdp_fe>; 460 st,syscfg = <&syscfg_fvdp_fe>;
461 reg = <0xfd6bf080 0x4>;
462 reg-names = "irqmux";
463 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
464 interrupts-names = "irqmux";
275 ranges = <0 0xfd6b0000 0x3000>; 465 ranges = <0 0xfd6b0000 0x3000>;
276 466
277 PIO100: gpio@fd6b0000 { 467 PIO100: gpio@fd6b0000 {
278 gpio-controller; 468 gpio-controller;
279 #gpio-cells = <1>; 469 #gpio-cells = <1>;
470 interrupt-controller;
471 #interrupt-cells = <2>;
280 reg = <0 0x100>; 472 reg = <0 0x100>;
281 st,bank-name = "PIO100"; 473 st,bank-name = "PIO100";
282 }; 474 };
283 PIO101: gpio@fd6b1000 { 475 PIO101: gpio@fd6b1000 {
284 gpio-controller; 476 gpio-controller;
285 #gpio-cells = <1>; 477 #gpio-cells = <1>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
286 reg = <0x1000 0x100>; 480 reg = <0x1000 0x100>;
287 st,bank-name = "PIO101"; 481 st,bank-name = "PIO101";
288 }; 482 };
289 PIO102: gpio@fd6b2000 { 483 PIO102: gpio@fd6b2000 {
290 gpio-controller; 484 gpio-controller;
291 #gpio-cells = <1>; 485 #gpio-cells = <1>;
486 interrupt-controller;
487 #interrupt-cells = <2>;
292 reg = <0x2000 0x100>; 488 reg = <0x2000 0x100>;
293 st,bank-name = "PIO102"; 489 st,bank-name = "PIO102";
294 }; 490 };
@@ -299,29 +495,41 @@
299 #size-cells = <1>; 495 #size-cells = <1>;
300 compatible = "st,stih416-fvdp-lite-pinctrl"; 496 compatible = "st,stih416-fvdp-lite-pinctrl";
301 st,syscfg = <&syscfg_fvdp_lite>; 497 st,syscfg = <&syscfg_fvdp_lite>;
498 reg = <0xfd33f080 0x4>;
499 reg-names = "irqmux";
500 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
501 interrupts-names = "irqmux";
302 ranges = <0 0xfd330000 0x5000>; 502 ranges = <0 0xfd330000 0x5000>;
303 503
304 PIO103: gpio@fd330000 { 504 PIO103: gpio@fd330000 {
305 gpio-controller; 505 gpio-controller;
306 #gpio-cells = <1>; 506 #gpio-cells = <1>;
507 interrupt-controller;
508 #interrupt-cells = <2>;
307 reg = <0 0x100>; 509 reg = <0 0x100>;
308 st,bank-name = "PIO103"; 510 st,bank-name = "PIO103";
309 }; 511 };
310 PIO104: gpio@fd331000 { 512 PIO104: gpio@fd331000 {
311 gpio-controller; 513 gpio-controller;
312 #gpio-cells = <1>; 514 #gpio-cells = <1>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
313 reg = <0x1000 0x100>; 517 reg = <0x1000 0x100>;
314 st,bank-name = "PIO104"; 518 st,bank-name = "PIO104";
315 }; 519 };
316 PIO105: gpio@fd332000 { 520 PIO105: gpio@fd332000 {
317 gpio-controller; 521 gpio-controller;
318 #gpio-cells = <1>; 522 #gpio-cells = <1>;
523 interrupt-controller;
524 #interrupt-cells = <2>;
319 reg = <0x2000 0x100>; 525 reg = <0x2000 0x100>;
320 st,bank-name = "PIO105"; 526 st,bank-name = "PIO105";
321 }; 527 };
322 PIO106: gpio@fd333000 { 528 PIO106: gpio@fd333000 {
323 gpio-controller; 529 gpio-controller;
324 #gpio-cells = <1>; 530 #gpio-cells = <1>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
325 reg = <0x3000 0x100>; 533 reg = <0x3000 0x100>;
326 st,bank-name = "PIO106"; 534 st,bank-name = "PIO106";
327 }; 535 };
@@ -329,6 +537,8 @@
329 PIO107: gpio@fd334000 { 537 PIO107: gpio@fd334000 {
330 gpio-controller; 538 gpio-controller;
331 #gpio-cells = <1>; 539 #gpio-cells = <1>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
332 reg = <0x4000 0x100>; 542 reg = <0x4000 0x100>;
333 st,bank-name = "PIO107"; 543 st,bank-name = "PIO107";
334 st,retime-pin-mask = <0xf>; 544 st,retime-pin-mask = <0xf>;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index b7ab47b95816..78746d20382e 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -10,6 +10,7 @@
10#include "stih416-clock.dtsi" 10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi" 11#include "stih416-pinctrl.dtsi"
12#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset-controller/stih416-resets.h>
13/ { 14/ {
14 L2: cache-controller { 15 L2: cache-controller {
15 compatible = "arm,pl310-cache"; 16 compatible = "arm,pl310-cache";
@@ -27,6 +28,16 @@
27 ranges; 28 ranges;
28 compatible = "simple-bus"; 29 compatible = "simple-bus";
29 30
31 powerdown: powerdown-controller {
32 #reset-cells = <1>;
33 compatible = "st,stih416-powerdown";
34 };
35
36 softreset: softreset-controller {
37 #reset-cells = <1>;
38 compatible = "st,stih416-softreset";
39 };
40
30 syscfg_sbc:sbc-syscfg@fe600000{ 41 syscfg_sbc:sbc-syscfg@fe600000{
31 compatible = "st,stih416-sbc-syscfg", "syscon"; 42 compatible = "st,stih416-sbc-syscfg", "syscon";
32 reg = <0xfe600000 0x1000>; 43 reg = <0xfe600000 0x1000>;
@@ -145,5 +156,73 @@
145 156
146 status = "disabled"; 157 status = "disabled";
147 }; 158 };
159
160 ethernet0: dwmac@fe810000 {
161 device_type = "network";
162 compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
163 status = "disabled";
164 reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
165 reg-names = "stmmaceth", "sti-ethconf";
166
167 interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
168 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
169
170 snps,pbl = <32>;
171 snps,mixed-burst;
172
173 st,syscon = <&syscfg_rear>;
174 resets = <&softreset STIH416_ETH0_SOFTRESET>;
175 reset-names = "stmmaceth";
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_mii0>;
178 clock-names = "stmmaceth";
179 clocks = <&CLK_S_GMAC0_PHY>;
180 };
181
182 ethernet1: dwmac@fef08000 {
183 device_type = "network";
184 compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
185 status = "disabled";
186 reg = <0xfef08000 0x8000>, <0x7f0 0x4>;
187 reg-names = "stmmaceth", "sti-ethconf";
188 interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
189 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
190
191 snps,pbl = <32>;
192 snps,mixed-burst;
193
194 st,syscon = <&syscfg_sbc>;
195
196 resets = <&softreset STIH416_ETH1_SOFTRESET>;
197 reset-names = "stmmaceth";
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_mii1>;
200 clock-names = "stmmaceth";
201 clocks = <&CLK_S_ETH1_PHY>;
202 };
203
204 rc: rc@fe518000 {
205 compatible = "st,comms-irb";
206 reg = <0xfe518000 0x234>;
207 interrupts = <0 203 0>;
208 rx-mode = "infrared";
209 clocks = <&CLK_SYSIN>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_ir>;
212 resets = <&softreset STIH416_IRB_SOFTRESET>;
213 };
214
215 /* FSM */
216 spifsm: spifsm@fe902000 {
217 compatible = "st,spi-fsm";
218 reg = <0xfe902000 0x1000>;
219 pinctrl-0 = <&pinctrl_fsm>;
220
221 st,syscfg = <&syscfg_rear>;
222 st,boot-device-reg = <0x958>;
223 st,boot-device-spi = <0x1a>;
224
225 status = "disabled";
226 };
148 }; 227 };
149}; 228};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 1e6aa92772f5..bf65c49095af 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -20,6 +20,8 @@
20 20
21 aliases { 21 aliases {
22 ttyAS0 = &serial2; 22 ttyAS0 = &serial2;
23 ethernet0 = &ethernet0;
24 ethernet1 = &ethernet1;
23 }; 25 };
24 26
25 soc { 27 soc {
@@ -46,5 +48,25 @@
46 48
47 status = "okay"; 49 status = "okay";
48 }; 50 };
51
52 ethernet0: dwmac@fe810000 {
53 status = "okay";
54 phy-mode = "mii";
55 pinctrl-0 = <&pinctrl_mii0>;
56
57 snps,reset-gpio = <&PIO106 2>;
58 snps,reset-active-low;
59 snps,reset-delays-us = <0 10000 10000>;
60 };
61
62 ethernet1: dwmac@fef08000 {
63 status = "disabled";
64 phy-mode = "mii";
65 st,tx-retime-src = "txclk";
66
67 snps,reset-gpio = <&PIO4 7>;
68 snps,reset-active-low;
69 snps,reset-delays-us = <0 10000 10000>;
70 };
49 }; 71 };
50}; 72};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 0ef0a69df8ea..838513f9ddc0 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -6,6 +6,7 @@
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9#include "stih41x-b2020x.dtsi"
9/ { 10/ {
10 memory{ 11 memory{
11 device_type = "memory"; 12 device_type = "memory";
@@ -19,6 +20,7 @@
19 20
20 aliases { 21 aliases {
21 ttyAS0 = &sbc_serial1; 22 ttyAS0 = &sbc_serial1;
23 ethernet1 = &ethernet1;
22 }; 24 };
23 soc { 25 soc {
24 sbc_serial1: serial@fe531000 { 26 sbc_serial1: serial@fe531000 {
@@ -60,5 +62,17 @@
60 i2c@fe541000 { 62 i2c@fe541000 {
61 status = "okay"; 63 status = "okay";
62 }; 64 };
65
66 ethernet1: dwmac@fef08000 {
67 status = "okay";
68 phy-mode = "rgmii-id";
69 max-speed = <1000>;
70 st,tx-retime-src = "clk_125";
71 snps,reset-gpio = <&PIO3 0>;
72 snps,reset-active-low;
73 snps,reset-delays-us = <0 10000 10000>;
74
75 pinctrl-0 = <&pinctrl_rgmii1>;
76 };
63 }; 77 };
64}; 78};
diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi
new file mode 100644
index 000000000000..df01c1211b32
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2020x.dtsi
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Lee Jones <lee.jones@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9/ {
10 soc {
11 spifsm: spifsm@fe902000 {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 status = "okay";
16
17 partition@0 {
18 label = "SerialFlash1";
19 reg = <0x00000000 0x00500000>;
20 };
21
22 partition@500000 {
23 label = "SerialFlash2";
24 reg = <0x00500000 0x00b00000>;
25 };
26 };
27 };
28};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index d4b081d6a167..fa746aea5e66 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -13,6 +13,7 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun4i-a10.dtsi" 15/include/ "sun4i-a10.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "Mele A1000"; 19 model = "Mele A1000";
@@ -35,6 +36,32 @@
35 }; 36 };
36 }; 37 };
37 38
39 usbphy: phy@01c13400 {
40 usb1_vbus-supply = <&reg_usb1_vbus>;
41 usb2_vbus-supply = <&reg_usb2_vbus>;
42 status = "okay";
43 };
44
45 ehci0: usb@01c14000 {
46 status = "okay";
47 };
48
49 ohci0: usb@01c14400 {
50 status = "okay";
51 };
52
53 ahci: sata@01c18000 {
54 status = "okay";
55 };
56
57 ehci1: usb@01c1c000 {
58 status = "okay";
59 };
60
61 ohci1: usb@01c1c400 {
62 status = "okay";
63 };
64
38 pinctrl@01c20800 { 65 pinctrl@01c20800 {
39 emac_power_pin_a1000: emac_power_pin@0 { 66 emac_power_pin_a1000: emac_power_pin@0 {
40 allwinner,pins = "PH15"; 67 allwinner,pins = "PH15";
@@ -80,18 +107,22 @@
80 }; 107 };
81 }; 108 };
82 109
83 regulators { 110 reg_emac_3v3: emac-3v3 {
84 compatible = "simple-bus"; 111 compatible = "regulator-fixed";
112 pinctrl-names = "default";
113 pinctrl-0 = <&emac_power_pin_a1000>;
114 regulator-name = "emac-3v3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 enable-active-high;
118 gpio = <&pio 7 15 0>;
119 };
85 120
86 reg_emac_3v3: emac-3v3 { 121 reg_usb1_vbus: usb1-vbus {
87 compatible = "regulator-fixed"; 122 status = "okay";
88 pinctrl-names = "default"; 123 };
89 pinctrl-0 = <&emac_power_pin_a1000>; 124
90 regulator-name = "emac-3v3"; 125 reg_usb2_vbus: usb2-vbus {
91 regulator-min-microvolt = <3300000>; 126 status = "okay";
92 regulator-max-microvolt = <3300000>;
93 enable-active-high;
94 gpio = <&pio 7 15 0>;
95 };
96 }; 127 };
97}; 128};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b139ee6bcf99..4684cbe6843b 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -12,6 +12,7 @@
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "sun4i-a10.dtsi" 14/include/ "sun4i-a10.dtsi"
15/include/ "sunxi-common-regulators.dtsi"
15 16
16/ { 17/ {
17 model = "Cubietech Cubieboard"; 18 model = "Cubietech Cubieboard";
@@ -33,6 +34,33 @@
33 }; 34 };
34 }; 35 };
35 36
37 usbphy: phy@01c13400 {
38 usb1_vbus-supply = <&reg_usb1_vbus>;
39 usb2_vbus-supply = <&reg_usb2_vbus>;
40 status = "okay";
41 };
42
43 ehci0: usb@01c14000 {
44 status = "okay";
45 };
46
47 ohci0: usb@01c14400 {
48 status = "okay";
49 };
50
51 ahci: sata@01c18000 {
52 target-supply = <&reg_ahci_5v>;
53 status = "okay";
54 };
55
56 ehci1: usb@01c1c000 {
57 status = "okay";
58 };
59
60 ohci1: usb@01c1c400 {
61 status = "okay";
62 };
63
36 pinctrl@01c20800 { 64 pinctrl@01c20800 {
37 led_pins_cubieboard: led_pins@0 { 65 led_pins_cubieboard: led_pins@0 {
38 allwinner,pins = "PH20", "PH21"; 66 allwinner,pins = "PH20", "PH21";
@@ -77,4 +105,16 @@
77 linux,default-trigger = "heartbeat"; 105 linux,default-trigger = "heartbeat";
78 }; 106 };
79 }; 107 };
108
109 reg_ahci_5v: ahci-5v {
110 status = "okay";
111 };
112
113 reg_usb1_vbus: usb1-vbus {
114 status = "okay";
115 };
116
117 reg_usb2_vbus: usb2-vbus {
118 status = "okay";
119 };
80}; 120};
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 3a1595f67823..d7c17e46ce23 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -13,6 +13,7 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun4i-a10.dtsi" 15/include/ "sun4i-a10.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "Miniand Hackberry"; 19 model = "Miniand Hackberry";
@@ -35,6 +36,28 @@
35 }; 36 };
36 }; 37 };
37 38
39 usbphy: phy@01c13400 {
40 usb1_vbus-supply = <&reg_usb1_vbus>;
41 usb2_vbus-supply = <&reg_usb2_vbus>;
42 status = "okay";
43 };
44
45 ehci0: usb@01c14000 {
46 status = "okay";
47 };
48
49 ohci0: usb@01c14400 {
50 status = "okay";
51 };
52
53 ehci1: usb@01c1c000 {
54 status = "okay";
55 };
56
57 ohci1: usb@01c1c400 {
58 status = "okay";
59 };
60
38 pio: pinctrl@01c20800 { 61 pio: pinctrl@01c20800 {
39 pinctrl-names = "default"; 62 pinctrl-names = "default";
40 pinctrl-0 = <&hackberry_hogs>; 63 pinctrl-0 = <&hackberry_hogs>;
@@ -45,6 +68,13 @@
45 allwinner,drive = <0>; 68 allwinner,drive = <0>;
46 allwinner,pull = <0>; 69 allwinner,pull = <0>;
47 }; 70 };
71
72 usb2_vbus_pin_hackberry: usb2_vbus_pin@0 {
73 allwinner,pins = "PH12";
74 allwinner,function = "gpio_out";
75 allwinner,drive = <0>;
76 allwinner,pull = <0>;
77 };
48 }; 78 };
49 79
50 uart0: serial@01c28000 { 80 uart0: serial@01c28000 {
@@ -54,16 +84,22 @@
54 }; 84 };
55 }; 85 };
56 86
57 regulators { 87 reg_emac_3v3: emac-3v3 {
58 compatible = "simple-bus"; 88 compatible = "regulator-fixed";
89 regulator-name = "emac-3v3";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 enable-active-high;
93 gpio = <&pio 7 19 0>;
94 };
59 95
60 reg_emac_3v3: emac-3v3 { 96 reg_usb1_vbus: usb1-vbus {
61 compatible = "regulator-fixed"; 97 status = "okay";
62 regulator-name = "emac-3v3"; 98 };
63 regulator-min-microvolt = <3300000>; 99
64 regulator-max-microvolt = <3300000>; 100 reg_usb2_vbus: usb2-vbus {
65 enable-active-high; 101 pinctrl-0 = <&usb2_vbus_pin_hackberry>;
66 gpio = <&pio 7 19 0>; 102 gpio = <&pio 7 12 0>;
67 }; 103 status = "okay";
68 }; 104 };
69}; 105};
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
new file mode 100644
index 000000000000..fe9272ee55c3
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -0,0 +1,69 @@
1/*
2 * Copyright 2014 Open Source Support GmbH
3 *
4 * David Lanzendörfer <david.lanzendoerfer@o2s.ch>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun4i-a10.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
17
18/ {
19 model = "INet-97F Rev 02";
20 compatible = "primux,inet97fv2", "allwinner,sun4i-a10";
21
22 aliases {
23 serial0 = &uart0;
24 };
25
26 soc@01c00000 {
27 uart0: serial@01c28000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&uart0_pins_a>;
30 status = "okay";
31 };
32
33 i2c0: i2c@01c2ac00 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c0_pins_a>;
36 status = "okay";
37 };
38
39 usbphy: phy@01c13400 {
40 usb1_vbus-supply = <&reg_usb1_vbus>;
41 usb2_vbus-supply = <&reg_usb2_vbus>;
42 status = "okay";
43 };
44
45 ehci0: usb@01c14000 {
46 status = "okay";
47 };
48
49 ohci0: usb@01c14400 {
50 status = "okay";
51 };
52
53 ehci1: usb@01c1c000 {
54 status = "okay";
55 };
56
57 ohci1: usb@01c1c400 {
58 status = "okay";
59 };
60 };
61
62 reg_usb1_vbus: usb1-vbus {
63 status = "okay";
64 };
65
66 reg_usb2_vbus: usb2-vbus {
67 status = "okay";
68 };
69};
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 70b3323caf1a..dd84a9e313b3 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -13,16 +13,47 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun4i-a10.dtsi" 15/include/ "sun4i-a10.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "PineRiver Mini X-Plus"; 19 model = "PineRiver Mini X-Plus";
19 compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; 20 compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
20 21
21 soc@01c00000 { 22 soc@01c00000 {
23 usbphy: phy@01c13400 {
24 usb1_vbus-supply = <&reg_usb1_vbus>;
25 usb2_vbus-supply = <&reg_usb2_vbus>;
26 status = "okay";
27 };
28
29 ehci0: usb@01c14000 {
30 status = "okay";
31 };
32
33 ohci0: usb@01c14400 {
34 status = "okay";
35 };
36
37 ehci1: usb@01c1c000 {
38 status = "okay";
39 };
40
41 ohci1: usb@01c1c400 {
42 status = "okay";
43 };
44
22 uart0: serial@01c28000 { 45 uart0: serial@01c28000 {
23 pinctrl-names = "default"; 46 pinctrl-names = "default";
24 pinctrl-0 = <&uart0_pins_a>; 47 pinctrl-0 = <&uart0_pins_a>;
25 status = "okay"; 48 status = "okay";
26 }; 49 };
27 }; 50 };
51
52 reg_usb1_vbus: usb1-vbus {
53 status = "okay";
54 };
55
56 reg_usb2_vbus: usb2-vbus {
57 status = "okay";
58 };
28}; 59};
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
new file mode 100644
index 000000000000..66cf0c7cf5b7
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -0,0 +1,111 @@
1/*
2 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "sun4i-a10.dtsi"
14/include/ "sunxi-common-regulators.dtsi"
15
16/ {
17 model = "Olimex A10-OLinuXino-LIME";
18 compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
19
20 soc@01c00000 {
21 emac: ethernet@01c0b000 {
22 pinctrl-names = "default";
23 pinctrl-0 = <&emac_pins_a>;
24 phy = <&phy1>;
25 status = "okay";
26 };
27
28 mdio@01c0b080 {
29 status = "okay";
30
31 phy1: ethernet-phy@1 {
32 reg = <1>;
33 };
34 };
35
36 usbphy: phy@01c13400 {
37 usb1_vbus-supply = <&reg_usb1_vbus>;
38 usb2_vbus-supply = <&reg_usb2_vbus>;
39 status = "okay";
40 };
41
42 ehci0: usb@01c14000 {
43 status = "okay";
44 };
45
46 ohci0: usb@01c14400 {
47 status = "okay";
48 };
49
50 ahci: sata@01c18000 {
51 target-supply = <&reg_ahci_5v>;
52 status = "okay";
53 };
54
55 ehci1: usb@01c1c000 {
56 status = "okay";
57 };
58
59 ohci1: usb@01c1c400 {
60 status = "okay";
61 };
62
63 pinctrl@01c20800 {
64 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
65 allwinner,pins = "PC3";
66 allwinner,function = "gpio_out";
67 allwinner,drive = <0>;
68 allwinner,pull = <0>;
69 };
70
71 led_pins_olinuxinolime: led_pins@0 {
72 allwinner,pins = "PH2";
73 allwinner,function = "gpio_out";
74 allwinner,drive = <1>;
75 allwinner,pull = <0>;
76 };
77 };
78
79 uart0: serial@01c28000 {
80 pinctrl-names = "default";
81 pinctrl-0 = <&uart0_pins_a>;
82 status = "okay";
83 };
84 };
85
86 leds {
87 compatible = "gpio-leds";
88 pinctrl-names = "default";
89 pinctrl-0 = <&led_pins_olinuxinolime>;
90
91 green {
92 label = "a10-olinuxino-lime:green:usr";
93 gpios = <&pio 7 2 0>;
94 default-state = "on";
95 };
96 };
97
98 reg_ahci_5v: ahci-5v {
99 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
100 gpio = <&pio 2 3 0>;
101 status = "okay";
102 };
103
104 reg_usb1_vbus: usb1-vbus {
105 status = "okay";
106 };
107
108 reg_usb2_vbus: usb2-vbus {
109 status = "okay";
110 };
111};
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
new file mode 100644
index 000000000000..255b47e7019c
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -0,0 +1,79 @@
1/*
2 * Copyright 2014 Zoltan HERPAI
3 * Zoltan HERPAI <wigyori@uid0.hu>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "sun4i-a10.dtsi"
15/include/ "sunxi-common-regulators.dtsi"
16
17/ {
18 model = "LinkSprite pcDuino";
19 compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10";
20
21 soc@01c00000 {
22 emac: ethernet@01c0b000 {
23 pinctrl-names = "default";
24 pinctrl-0 = <&emac_pins_a>;
25 phy = <&phy1>;
26 status = "okay";
27 };
28
29 mdio@01c0b080 {
30 status = "okay";
31
32 phy1: ethernet-phy@1 {
33 reg = <1>;
34 };
35 };
36
37 usbphy: phy@01c13400 {
38 usb1_vbus-supply = <&reg_usb1_vbus>;
39 usb2_vbus-supply = <&reg_usb2_vbus>;
40 status = "okay";
41 };
42
43 ehci0: usb@01c14000 {
44 status = "okay";
45 };
46
47 ohci0: usb@01c14400 {
48 status = "okay";
49 };
50
51 ehci1: usb@01c1c000 {
52 status = "okay";
53 };
54
55 ohci1: usb@01c1c400 {
56 status = "okay";
57 };
58
59 uart0: serial@01c28000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&uart0_pins_a>;
62 status = "okay";
63 };
64
65 i2c0: i2c@01c2ac00 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&i2c0_pins_a>;
68 status = "okay";
69 };
70 };
71
72 reg_usb1_vbus: usb1-vbus {
73 status = "okay";
74 };
75
76 reg_usb2_vbus: usb2-vbus {
77 status = "okay";
78 };
79};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 249b6e0ba737..9174724571e2 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -19,6 +19,12 @@
19 ethernet0 = &emac; 19 ethernet0 = &emac;
20 serial0 = &uart0; 20 serial0 = &uart0;
21 serial1 = &uart1; 21 serial1 = &uart1;
22 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &uart5;
26 serial6 = &uart6;
27 serial7 = &uart7;
22 }; 28 };
23 29
24 cpus { 30 cpus {
@@ -52,44 +58,48 @@
52 clock-frequency = <0>; 58 clock-frequency = <0>;
53 }; 59 };
54 60
55 osc24M: osc24M@01c20050 { 61 osc24M: clk@01c20050 {
56 #clock-cells = <0>; 62 #clock-cells = <0>;
57 compatible = "allwinner,sun4i-osc-clk"; 63 compatible = "allwinner,sun4i-a10-osc-clk";
58 reg = <0x01c20050 0x4>; 64 reg = <0x01c20050 0x4>;
59 clock-frequency = <24000000>; 65 clock-frequency = <24000000>;
66 clock-output-names = "osc24M";
60 }; 67 };
61 68
62 osc32k: osc32k { 69 osc32k: clk@0 {
63 #clock-cells = <0>; 70 #clock-cells = <0>;
64 compatible = "fixed-clock"; 71 compatible = "fixed-clock";
65 clock-frequency = <32768>; 72 clock-frequency = <32768>;
73 clock-output-names = "osc32k";
66 }; 74 };
67 75
68 pll1: pll1@01c20000 { 76 pll1: clk@01c20000 {
69 #clock-cells = <0>; 77 #clock-cells = <0>;
70 compatible = "allwinner,sun4i-pll1-clk"; 78 compatible = "allwinner,sun4i-a10-pll1-clk";
71 reg = <0x01c20000 0x4>; 79 reg = <0x01c20000 0x4>;
72 clocks = <&osc24M>; 80 clocks = <&osc24M>;
81 clock-output-names = "pll1";
73 }; 82 };
74 83
75 pll4: pll4@01c20018 { 84 pll4: clk@01c20018 {
76 #clock-cells = <0>; 85 #clock-cells = <0>;
77 compatible = "allwinner,sun4i-pll1-clk"; 86 compatible = "allwinner,sun4i-a10-pll1-clk";
78 reg = <0x01c20018 0x4>; 87 reg = <0x01c20018 0x4>;
79 clocks = <&osc24M>; 88 clocks = <&osc24M>;
89 clock-output-names = "pll4";
80 }; 90 };
81 91
82 pll5: pll5@01c20020 { 92 pll5: clk@01c20020 {
83 #clock-cells = <1>; 93 #clock-cells = <1>;
84 compatible = "allwinner,sun4i-pll5-clk"; 94 compatible = "allwinner,sun4i-a10-pll5-clk";
85 reg = <0x01c20020 0x4>; 95 reg = <0x01c20020 0x4>;
86 clocks = <&osc24M>; 96 clocks = <&osc24M>;
87 clock-output-names = "pll5_ddr", "pll5_other"; 97 clock-output-names = "pll5_ddr", "pll5_other";
88 }; 98 };
89 99
90 pll6: pll6@01c20028 { 100 pll6: clk@01c20028 {
91 #clock-cells = <1>; 101 #clock-cells = <1>;
92 compatible = "allwinner,sun4i-pll6-clk"; 102 compatible = "allwinner,sun4i-a10-pll6-clk";
93 reg = <0x01c20028 0x4>; 103 reg = <0x01c20028 0x4>;
94 clocks = <&osc24M>; 104 clocks = <&osc24M>;
95 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 105 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -98,21 +108,23 @@
98 /* dummy is 200M */ 108 /* dummy is 200M */
99 cpu: cpu@01c20054 { 109 cpu: cpu@01c20054 {
100 #clock-cells = <0>; 110 #clock-cells = <0>;
101 compatible = "allwinner,sun4i-cpu-clk"; 111 compatible = "allwinner,sun4i-a10-cpu-clk";
102 reg = <0x01c20054 0x4>; 112 reg = <0x01c20054 0x4>;
103 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 113 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
114 clock-output-names = "cpu";
104 }; 115 };
105 116
106 axi: axi@01c20054 { 117 axi: axi@01c20054 {
107 #clock-cells = <0>; 118 #clock-cells = <0>;
108 compatible = "allwinner,sun4i-axi-clk"; 119 compatible = "allwinner,sun4i-a10-axi-clk";
109 reg = <0x01c20054 0x4>; 120 reg = <0x01c20054 0x4>;
110 clocks = <&cpu>; 121 clocks = <&cpu>;
122 clock-output-names = "axi";
111 }; 123 };
112 124
113 axi_gates: axi_gates@01c2005c { 125 axi_gates: clk@01c2005c {
114 #clock-cells = <1>; 126 #clock-cells = <1>;
115 compatible = "allwinner,sun4i-axi-gates-clk"; 127 compatible = "allwinner,sun4i-a10-axi-gates-clk";
116 reg = <0x01c2005c 0x4>; 128 reg = <0x01c2005c 0x4>;
117 clocks = <&axi>; 129 clocks = <&axi>;
118 clock-output-names = "axi_dram"; 130 clock-output-names = "axi_dram";
@@ -120,14 +132,15 @@
120 132
121 ahb: ahb@01c20054 { 133 ahb: ahb@01c20054 {
122 #clock-cells = <0>; 134 #clock-cells = <0>;
123 compatible = "allwinner,sun4i-ahb-clk"; 135 compatible = "allwinner,sun4i-a10-ahb-clk";
124 reg = <0x01c20054 0x4>; 136 reg = <0x01c20054 0x4>;
125 clocks = <&axi>; 137 clocks = <&axi>;
138 clock-output-names = "ahb";
126 }; 139 };
127 140
128 ahb_gates: ahb_gates@01c20060 { 141 ahb_gates: clk@01c20060 {
129 #clock-cells = <1>; 142 #clock-cells = <1>;
130 compatible = "allwinner,sun4i-ahb-gates-clk"; 143 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
131 reg = <0x01c20060 0x8>; 144 reg = <0x01c20060 0x8>;
132 clocks = <&ahb>; 145 clocks = <&ahb>;
133 clock-output-names = "ahb_usb0", "ahb_ehci0", 146 clock-output-names = "ahb_usb0", "ahb_ehci0",
@@ -145,14 +158,15 @@
145 158
146 apb0: apb0@01c20054 { 159 apb0: apb0@01c20054 {
147 #clock-cells = <0>; 160 #clock-cells = <0>;
148 compatible = "allwinner,sun4i-apb0-clk"; 161 compatible = "allwinner,sun4i-a10-apb0-clk";
149 reg = <0x01c20054 0x4>; 162 reg = <0x01c20054 0x4>;
150 clocks = <&ahb>; 163 clocks = <&ahb>;
164 clock-output-names = "apb0";
151 }; 165 };
152 166
153 apb0_gates: apb0_gates@01c20068 { 167 apb0_gates: clk@01c20068 {
154 #clock-cells = <1>; 168 #clock-cells = <1>;
155 compatible = "allwinner,sun4i-apb0-gates-clk"; 169 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
156 reg = <0x01c20068 0x4>; 170 reg = <0x01c20068 0x4>;
157 clocks = <&apb0>; 171 clocks = <&apb0>;
158 clock-output-names = "apb0_codec", "apb0_spdif", 172 clock-output-names = "apb0_codec", "apb0_spdif",
@@ -162,21 +176,23 @@
162 176
163 apb1_mux: apb1_mux@01c20058 { 177 apb1_mux: apb1_mux@01c20058 {
164 #clock-cells = <0>; 178 #clock-cells = <0>;
165 compatible = "allwinner,sun4i-apb1-mux-clk"; 179 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
166 reg = <0x01c20058 0x4>; 180 reg = <0x01c20058 0x4>;
167 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 181 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
182 clock-output-names = "apb1_mux";
168 }; 183 };
169 184
170 apb1: apb1@01c20058 { 185 apb1: apb1@01c20058 {
171 #clock-cells = <0>; 186 #clock-cells = <0>;
172 compatible = "allwinner,sun4i-apb1-clk"; 187 compatible = "allwinner,sun4i-a10-apb1-clk";
173 reg = <0x01c20058 0x4>; 188 reg = <0x01c20058 0x4>;
174 clocks = <&apb1_mux>; 189 clocks = <&apb1_mux>;
190 clock-output-names = "apb1";
175 }; 191 };
176 192
177 apb1_gates: apb1_gates@01c2006c { 193 apb1_gates: clk@01c2006c {
178 #clock-cells = <1>; 194 #clock-cells = <1>;
179 compatible = "allwinner,sun4i-apb1-gates-clk"; 195 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
180 reg = <0x01c2006c 0x4>; 196 reg = <0x01c2006c 0x4>;
181 clocks = <&apb1>; 197 clocks = <&apb1>;
182 clock-output-names = "apb1_i2c0", "apb1_i2c1", 198 clock-output-names = "apb1_i2c0", "apb1_i2c1",
@@ -189,7 +205,7 @@
189 205
190 nand_clk: clk@01c20080 { 206 nand_clk: clk@01c20080 {
191 #clock-cells = <0>; 207 #clock-cells = <0>;
192 compatible = "allwinner,sun4i-mod0-clk"; 208 compatible = "allwinner,sun4i-a10-mod0-clk";
193 reg = <0x01c20080 0x4>; 209 reg = <0x01c20080 0x4>;
194 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195 clock-output-names = "nand"; 211 clock-output-names = "nand";
@@ -197,7 +213,7 @@
197 213
198 ms_clk: clk@01c20084 { 214 ms_clk: clk@01c20084 {
199 #clock-cells = <0>; 215 #clock-cells = <0>;
200 compatible = "allwinner,sun4i-mod0-clk"; 216 compatible = "allwinner,sun4i-a10-mod0-clk";
201 reg = <0x01c20084 0x4>; 217 reg = <0x01c20084 0x4>;
202 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203 clock-output-names = "ms"; 219 clock-output-names = "ms";
@@ -205,7 +221,7 @@
205 221
206 mmc0_clk: clk@01c20088 { 222 mmc0_clk: clk@01c20088 {
207 #clock-cells = <0>; 223 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-mod0-clk"; 224 compatible = "allwinner,sun4i-a10-mod0-clk";
209 reg = <0x01c20088 0x4>; 225 reg = <0x01c20088 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "mmc0"; 227 clock-output-names = "mmc0";
@@ -213,7 +229,7 @@
213 229
214 mmc1_clk: clk@01c2008c { 230 mmc1_clk: clk@01c2008c {
215 #clock-cells = <0>; 231 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-mod0-clk"; 232 compatible = "allwinner,sun4i-a10-mod0-clk";
217 reg = <0x01c2008c 0x4>; 233 reg = <0x01c2008c 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "mmc1"; 235 clock-output-names = "mmc1";
@@ -221,7 +237,7 @@
221 237
222 mmc2_clk: clk@01c20090 { 238 mmc2_clk: clk@01c20090 {
223 #clock-cells = <0>; 239 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-mod0-clk"; 240 compatible = "allwinner,sun4i-a10-mod0-clk";
225 reg = <0x01c20090 0x4>; 241 reg = <0x01c20090 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "mmc2"; 243 clock-output-names = "mmc2";
@@ -229,7 +245,7 @@
229 245
230 mmc3_clk: clk@01c20094 { 246 mmc3_clk: clk@01c20094 {
231 #clock-cells = <0>; 247 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-mod0-clk"; 248 compatible = "allwinner,sun4i-a10-mod0-clk";
233 reg = <0x01c20094 0x4>; 249 reg = <0x01c20094 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc3"; 251 clock-output-names = "mmc3";
@@ -237,7 +253,7 @@
237 253
238 ts_clk: clk@01c20098 { 254 ts_clk: clk@01c20098 {
239 #clock-cells = <0>; 255 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-mod0-clk"; 256 compatible = "allwinner,sun4i-a10-mod0-clk";
241 reg = <0x01c20098 0x4>; 257 reg = <0x01c20098 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "ts"; 259 clock-output-names = "ts";
@@ -245,7 +261,7 @@
245 261
246 ss_clk: clk@01c2009c { 262 ss_clk: clk@01c2009c {
247 #clock-cells = <0>; 263 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-mod0-clk"; 264 compatible = "allwinner,sun4i-a10-mod0-clk";
249 reg = <0x01c2009c 0x4>; 265 reg = <0x01c2009c 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "ss"; 267 clock-output-names = "ss";
@@ -253,7 +269,7 @@
253 269
254 spi0_clk: clk@01c200a0 { 270 spi0_clk: clk@01c200a0 {
255 #clock-cells = <0>; 271 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-mod0-clk"; 272 compatible = "allwinner,sun4i-a10-mod0-clk";
257 reg = <0x01c200a0 0x4>; 273 reg = <0x01c200a0 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "spi0"; 275 clock-output-names = "spi0";
@@ -261,7 +277,7 @@
261 277
262 spi1_clk: clk@01c200a4 { 278 spi1_clk: clk@01c200a4 {
263 #clock-cells = <0>; 279 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-mod0-clk"; 280 compatible = "allwinner,sun4i-a10-mod0-clk";
265 reg = <0x01c200a4 0x4>; 281 reg = <0x01c200a4 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "spi1"; 283 clock-output-names = "spi1";
@@ -269,7 +285,7 @@
269 285
270 spi2_clk: clk@01c200a8 { 286 spi2_clk: clk@01c200a8 {
271 #clock-cells = <0>; 287 #clock-cells = <0>;
272 compatible = "allwinner,sun4i-mod0-clk"; 288 compatible = "allwinner,sun4i-a10-mod0-clk";
273 reg = <0x01c200a8 0x4>; 289 reg = <0x01c200a8 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "spi2"; 291 clock-output-names = "spi2";
@@ -277,7 +293,7 @@
277 293
278 pata_clk: clk@01c200ac { 294 pata_clk: clk@01c200ac {
279 #clock-cells = <0>; 295 #clock-cells = <0>;
280 compatible = "allwinner,sun4i-mod0-clk"; 296 compatible = "allwinner,sun4i-a10-mod0-clk";
281 reg = <0x01c200ac 0x4>; 297 reg = <0x01c200ac 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "pata"; 299 clock-output-names = "pata";
@@ -285,7 +301,7 @@
285 301
286 ir0_clk: clk@01c200b0 { 302 ir0_clk: clk@01c200b0 {
287 #clock-cells = <0>; 303 #clock-cells = <0>;
288 compatible = "allwinner,sun4i-mod0-clk"; 304 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c200b0 0x4>; 305 reg = <0x01c200b0 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "ir0"; 307 clock-output-names = "ir0";
@@ -293,15 +309,24 @@
293 309
294 ir1_clk: clk@01c200b4 { 310 ir1_clk: clk@01c200b4 {
295 #clock-cells = <0>; 311 #clock-cells = <0>;
296 compatible = "allwinner,sun4i-mod0-clk"; 312 compatible = "allwinner,sun4i-a10-mod0-clk";
297 reg = <0x01c200b4 0x4>; 313 reg = <0x01c200b4 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "ir1"; 315 clock-output-names = "ir1";
300 }; 316 };
301 317
318 usb_clk: clk@01c200cc {
319 #clock-cells = <1>;
320 #reset-cells = <1>;
321 compatible = "allwinner,sun4i-a10-usb-clk";
322 reg = <0x01c200cc 0x4>;
323 clocks = <&pll6 1>;
324 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
325 };
326
302 spi3_clk: clk@01c200d4 { 327 spi3_clk: clk@01c200d4 {
303 #clock-cells = <0>; 328 #clock-cells = <0>;
304 compatible = "allwinner,sun4i-mod0-clk"; 329 compatible = "allwinner,sun4i-a10-mod0-clk";
305 reg = <0x01c200d4 0x4>; 330 reg = <0x01c200d4 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 331 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "spi3"; 332 clock-output-names = "spi3";
@@ -314,6 +339,28 @@
314 #size-cells = <1>; 339 #size-cells = <1>;
315 ranges; 340 ranges;
316 341
342 spi0: spi@01c05000 {
343 compatible = "allwinner,sun4i-a10-spi";
344 reg = <0x01c05000 0x1000>;
345 interrupts = <10>;
346 clocks = <&ahb_gates 20>, <&spi0_clk>;
347 clock-names = "ahb", "mod";
348 status = "disabled";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 };
352
353 spi1: spi@01c06000 {
354 compatible = "allwinner,sun4i-a10-spi";
355 reg = <0x01c06000 0x1000>;
356 interrupts = <11>;
357 clocks = <&ahb_gates 21>, <&spi1_clk>;
358 clock-names = "ahb", "mod";
359 status = "disabled";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 };
363
317 emac: ethernet@01c0b000 { 364 emac: ethernet@01c0b000 {
318 compatible = "allwinner,sun4i-a10-emac"; 365 compatible = "allwinner,sun4i-a10-emac";
319 reg = <0x01c0b000 0x1000>; 366 reg = <0x01c0b000 0x1000>;
@@ -330,6 +377,88 @@
330 #size-cells = <0>; 377 #size-cells = <0>;
331 }; 378 };
332 379
380 usbphy: phy@01c13400 {
381 #phy-cells = <1>;
382 compatible = "allwinner,sun4i-a10-usb-phy";
383 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
384 reg-names = "phy_ctrl", "pmu1", "pmu2";
385 clocks = <&usb_clk 8>;
386 clock-names = "usb_phy";
387 resets = <&usb_clk 1>, <&usb_clk 2>;
388 reset-names = "usb1_reset", "usb2_reset";
389 status = "disabled";
390 };
391
392 ehci0: usb@01c14000 {
393 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
394 reg = <0x01c14000 0x100>;
395 interrupts = <39>;
396 clocks = <&ahb_gates 1>;
397 phys = <&usbphy 1>;
398 phy-names = "usb";
399 status = "disabled";
400 };
401
402 ohci0: usb@01c14400 {
403 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
404 reg = <0x01c14400 0x100>;
405 interrupts = <64>;
406 clocks = <&usb_clk 6>, <&ahb_gates 2>;
407 phys = <&usbphy 1>;
408 phy-names = "usb";
409 status = "disabled";
410 };
411
412 spi2: spi@01c17000 {
413 compatible = "allwinner,sun4i-a10-spi";
414 reg = <0x01c17000 0x1000>;
415 interrupts = <12>;
416 clocks = <&ahb_gates 22>, <&spi2_clk>;
417 clock-names = "ahb", "mod";
418 status = "disabled";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 };
422
423 ahci: sata@01c18000 {
424 compatible = "allwinner,sun4i-a10-ahci";
425 reg = <0x01c18000 0x1000>;
426 interrupts = <56>;
427 clocks = <&pll6 0>, <&ahb_gates 25>;
428 status = "disabled";
429 };
430
431 ehci1: usb@01c1c000 {
432 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
433 reg = <0x01c1c000 0x100>;
434 interrupts = <40>;
435 clocks = <&ahb_gates 3>;
436 phys = <&usbphy 2>;
437 phy-names = "usb";
438 status = "disabled";
439 };
440
441 ohci1: usb@01c1c400 {
442 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
443 reg = <0x01c1c400 0x100>;
444 interrupts = <65>;
445 clocks = <&usb_clk 7>, <&ahb_gates 4>;
446 phys = <&usbphy 2>;
447 phy-names = "usb";
448 status = "disabled";
449 };
450
451 spi3: spi@01c1f000 {
452 compatible = "allwinner,sun4i-a10-spi";
453 reg = <0x01c1f000 0x1000>;
454 interrupts = <50>;
455 clocks = <&ahb_gates 23>, <&spi3_clk>;
456 clock-names = "ahb", "mod";
457 status = "disabled";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 };
461
333 intc: interrupt-controller@01c20400 { 462 intc: interrupt-controller@01c20400 {
334 compatible = "allwinner,sun4i-a10-ic"; 463 compatible = "allwinner,sun4i-a10-ic";
335 reg = <0x01c20400 0x400>; 464 reg = <0x01c20400 0x400>;
@@ -410,18 +539,18 @@
410 }; 539 };
411 540
412 wdt: watchdog@01c20c90 { 541 wdt: watchdog@01c20c90 {
413 compatible = "allwinner,sun4i-wdt"; 542 compatible = "allwinner,sun4i-a10-wdt";
414 reg = <0x01c20c90 0x10>; 543 reg = <0x01c20c90 0x10>;
415 }; 544 };
416 545
417 rtc: rtc@01c20d00 { 546 rtc: rtc@01c20d00 {
418 compatible = "allwinner,sun4i-rtc"; 547 compatible = "allwinner,sun4i-a10-rtc";
419 reg = <0x01c20d00 0x20>; 548 reg = <0x01c20d00 0x20>;
420 interrupts = <24>; 549 interrupts = <24>;
421 }; 550 };
422 551
423 sid: eeprom@01c23800 { 552 sid: eeprom@01c23800 {
424 compatible = "allwinner,sun4i-sid"; 553 compatible = "allwinner,sun4i-a10-sid";
425 reg = <0x01c23800 0x10>; 554 reg = <0x01c23800 0x10>;
426 }; 555 };
427 556
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 3c9f8b3cd3e3..23611b71d3aa 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -13,6 +13,7 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun5i-a10s.dtsi" 15/include/ "sun5i-a10s.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "Olimex A10s-Olinuxino Micro"; 19 model = "Olimex A10s-Olinuxino Micro";
@@ -34,6 +35,19 @@
34 }; 35 };
35 }; 36 };
36 37
38 usbphy: phy@01c13400 {
39 usb1_vbus-supply = <&reg_usb1_vbus>;
40 status = "okay";
41 };
42
43 ehci0: usb@01c14000 {
44 status = "okay";
45 };
46
47 ohci0: usb@01c14400 {
48 status = "okay";
49 };
50
37 pinctrl@01c20800 { 51 pinctrl@01c20800 {
38 led_pins_olinuxino: led_pins@0 { 52 led_pins_olinuxino: led_pins@0 {
39 allwinner,pins = "PE3"; 53 allwinner,pins = "PE3";
@@ -41,6 +55,13 @@
41 allwinner,drive = <1>; 55 allwinner,drive = <1>;
42 allwinner,pull = <0>; 56 allwinner,pull = <0>;
43 }; 57 };
58
59 usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 {
60 allwinner,pins = "PB10";
61 allwinner,function = "gpio_out";
62 allwinner,drive = <0>;
63 allwinner,pull = <0>;
64 };
44 }; 65 };
45 66
46 uart0: serial@01c28000 { 67 uart0: serial@01c28000 {
@@ -98,4 +119,10 @@
98 default-state = "on"; 119 default-state = "on";
99 }; 120 };
100 }; 121 };
122
123 reg_usb1_vbus: usb1-vbus {
124 pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>;
125 gpio = <&pio 1 10 0>;
126 status = "okay";
127 };
101}; 128};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ddb25452d78e..79989ed5658d 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -18,6 +18,10 @@
18 18
19 aliases { 19 aliases {
20 ethernet0 = &emac; 20 ethernet0 = &emac;
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
21 }; 25 };
22 26
23 cpus { 27 cpus {
@@ -47,44 +51,48 @@
47 clock-frequency = <0>; 51 clock-frequency = <0>;
48 }; 52 };
49 53
50 osc24M: osc24M@01c20050 { 54 osc24M: clk@01c20050 {
51 #clock-cells = <0>; 55 #clock-cells = <0>;
52 compatible = "allwinner,sun4i-osc-clk"; 56 compatible = "allwinner,sun4i-a10-osc-clk";
53 reg = <0x01c20050 0x4>; 57 reg = <0x01c20050 0x4>;
54 clock-frequency = <24000000>; 58 clock-frequency = <24000000>;
59 clock-output-names = "osc24M";
55 }; 60 };
56 61
57 osc32k: osc32k { 62 osc32k: clk@0 {
58 #clock-cells = <0>; 63 #clock-cells = <0>;
59 compatible = "fixed-clock"; 64 compatible = "fixed-clock";
60 clock-frequency = <32768>; 65 clock-frequency = <32768>;
66 clock-output-names = "osc32k";
61 }; 67 };
62 68
63 pll1: pll1@01c20000 { 69 pll1: clk@01c20000 {
64 #clock-cells = <0>; 70 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk"; 71 compatible = "allwinner,sun4i-a10-pll1-clk";
66 reg = <0x01c20000 0x4>; 72 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 73 clocks = <&osc24M>;
74 clock-output-names = "pll1";
68 }; 75 };
69 76
70 pll4: pll4@01c20018 { 77 pll4: clk@01c20018 {
71 #clock-cells = <0>; 78 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 79 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20018 0x4>; 80 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>; 81 clocks = <&osc24M>;
82 clock-output-names = "pll4";
75 }; 83 };
76 84
77 pll5: pll5@01c20020 { 85 pll5: clk@01c20020 {
78 #clock-cells = <1>; 86 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk"; 87 compatible = "allwinner,sun4i-a10-pll5-clk";
80 reg = <0x01c20020 0x4>; 88 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>; 89 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other"; 90 clock-output-names = "pll5_ddr", "pll5_other";
83 }; 91 };
84 92
85 pll6: pll6@01c20028 { 93 pll6: clk@01c20028 {
86 #clock-cells = <1>; 94 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk"; 95 compatible = "allwinner,sun4i-a10-pll6-clk";
88 reg = <0x01c20028 0x4>; 96 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>; 97 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 98 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +101,23 @@
93 /* dummy is 200M */ 101 /* dummy is 200M */
94 cpu: cpu@01c20054 { 102 cpu: cpu@01c20054 {
95 #clock-cells = <0>; 103 #clock-cells = <0>;
96 compatible = "allwinner,sun4i-cpu-clk"; 104 compatible = "allwinner,sun4i-a10-cpu-clk";
97 reg = <0x01c20054 0x4>; 105 reg = <0x01c20054 0x4>;
98 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 106 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
107 clock-output-names = "cpu";
99 }; 108 };
100 109
101 axi: axi@01c20054 { 110 axi: axi@01c20054 {
102 #clock-cells = <0>; 111 #clock-cells = <0>;
103 compatible = "allwinner,sun4i-axi-clk"; 112 compatible = "allwinner,sun4i-a10-axi-clk";
104 reg = <0x01c20054 0x4>; 113 reg = <0x01c20054 0x4>;
105 clocks = <&cpu>; 114 clocks = <&cpu>;
115 clock-output-names = "axi";
106 }; 116 };
107 117
108 axi_gates: axi_gates@01c2005c { 118 axi_gates: clk@01c2005c {
109 #clock-cells = <1>; 119 #clock-cells = <1>;
110 compatible = "allwinner,sun4i-axi-gates-clk"; 120 compatible = "allwinner,sun4i-a10-axi-gates-clk";
111 reg = <0x01c2005c 0x4>; 121 reg = <0x01c2005c 0x4>;
112 clocks = <&axi>; 122 clocks = <&axi>;
113 clock-output-names = "axi_dram"; 123 clock-output-names = "axi_dram";
@@ -115,12 +125,13 @@
115 125
116 ahb: ahb@01c20054 { 126 ahb: ahb@01c20054 {
117 #clock-cells = <0>; 127 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk"; 128 compatible = "allwinner,sun4i-a10-ahb-clk";
119 reg = <0x01c20054 0x4>; 129 reg = <0x01c20054 0x4>;
120 clocks = <&axi>; 130 clocks = <&axi>;
131 clock-output-names = "ahb";
121 }; 132 };
122 133
123 ahb_gates: ahb_gates@01c20060 { 134 ahb_gates: clk@01c20060 {
124 #clock-cells = <1>; 135 #clock-cells = <1>;
125 compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; 136 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
126 reg = <0x01c20060 0x8>; 137 reg = <0x01c20060 0x8>;
@@ -136,12 +147,13 @@
136 147
137 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
138 #clock-cells = <0>; 149 #clock-cells = <0>;
139 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
140 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
141 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0";
142 }; 154 };
143 155
144 apb0_gates: apb0_gates@01c20068 { 156 apb0_gates: clk@01c20068 {
145 #clock-cells = <1>; 157 #clock-cells = <1>;
146 compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; 158 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
147 reg = <0x01c20068 0x4>; 159 reg = <0x01c20068 0x4>;
@@ -152,19 +164,21 @@
152 164
153 apb1_mux: apb1_mux@01c20058 { 165 apb1_mux: apb1_mux@01c20058 {
154 #clock-cells = <0>; 166 #clock-cells = <0>;
155 compatible = "allwinner,sun4i-apb1-mux-clk"; 167 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
156 reg = <0x01c20058 0x4>; 168 reg = <0x01c20058 0x4>;
157 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 169 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
170 clock-output-names = "apb1_mux";
158 }; 171 };
159 172
160 apb1: apb1@01c20058 { 173 apb1: apb1@01c20058 {
161 #clock-cells = <0>; 174 #clock-cells = <0>;
162 compatible = "allwinner,sun4i-apb1-clk"; 175 compatible = "allwinner,sun4i-a10-apb1-clk";
163 reg = <0x01c20058 0x4>; 176 reg = <0x01c20058 0x4>;
164 clocks = <&apb1_mux>; 177 clocks = <&apb1_mux>;
178 clock-output-names = "apb1";
165 }; 179 };
166 180
167 apb1_gates: apb1_gates@01c2006c { 181 apb1_gates: clk@01c2006c {
168 #clock-cells = <1>; 182 #clock-cells = <1>;
169 compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; 183 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
170 reg = <0x01c2006c 0x4>; 184 reg = <0x01c2006c 0x4>;
@@ -176,7 +190,7 @@
176 190
177 nand_clk: clk@01c20080 { 191 nand_clk: clk@01c20080 {
178 #clock-cells = <0>; 192 #clock-cells = <0>;
179 compatible = "allwinner,sun4i-mod0-clk"; 193 compatible = "allwinner,sun4i-a10-mod0-clk";
180 reg = <0x01c20080 0x4>; 194 reg = <0x01c20080 0x4>;
181 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
182 clock-output-names = "nand"; 196 clock-output-names = "nand";
@@ -184,7 +198,7 @@
184 198
185 ms_clk: clk@01c20084 { 199 ms_clk: clk@01c20084 {
186 #clock-cells = <0>; 200 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-mod0-clk"; 201 compatible = "allwinner,sun4i-a10-mod0-clk";
188 reg = <0x01c20084 0x4>; 202 reg = <0x01c20084 0x4>;
189 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
190 clock-output-names = "ms"; 204 clock-output-names = "ms";
@@ -192,7 +206,7 @@
192 206
193 mmc0_clk: clk@01c20088 { 207 mmc0_clk: clk@01c20088 {
194 #clock-cells = <0>; 208 #clock-cells = <0>;
195 compatible = "allwinner,sun4i-mod0-clk"; 209 compatible = "allwinner,sun4i-a10-mod0-clk";
196 reg = <0x01c20088 0x4>; 210 reg = <0x01c20088 0x4>;
197 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
198 clock-output-names = "mmc0"; 212 clock-output-names = "mmc0";
@@ -200,7 +214,7 @@
200 214
201 mmc1_clk: clk@01c2008c { 215 mmc1_clk: clk@01c2008c {
202 #clock-cells = <0>; 216 #clock-cells = <0>;
203 compatible = "allwinner,sun4i-mod0-clk"; 217 compatible = "allwinner,sun4i-a10-mod0-clk";
204 reg = <0x01c2008c 0x4>; 218 reg = <0x01c2008c 0x4>;
205 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 219 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
206 clock-output-names = "mmc1"; 220 clock-output-names = "mmc1";
@@ -208,7 +222,7 @@
208 222
209 mmc2_clk: clk@01c20090 { 223 mmc2_clk: clk@01c20090 {
210 #clock-cells = <0>; 224 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-mod0-clk"; 225 compatible = "allwinner,sun4i-a10-mod0-clk";
212 reg = <0x01c20090 0x4>; 226 reg = <0x01c20090 0x4>;
213 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
214 clock-output-names = "mmc2"; 228 clock-output-names = "mmc2";
@@ -216,7 +230,7 @@
216 230
217 ts_clk: clk@01c20098 { 231 ts_clk: clk@01c20098 {
218 #clock-cells = <0>; 232 #clock-cells = <0>;
219 compatible = "allwinner,sun4i-mod0-clk"; 233 compatible = "allwinner,sun4i-a10-mod0-clk";
220 reg = <0x01c20098 0x4>; 234 reg = <0x01c20098 0x4>;
221 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
222 clock-output-names = "ts"; 236 clock-output-names = "ts";
@@ -224,7 +238,7 @@
224 238
225 ss_clk: clk@01c2009c { 239 ss_clk: clk@01c2009c {
226 #clock-cells = <0>; 240 #clock-cells = <0>;
227 compatible = "allwinner,sun4i-mod0-clk"; 241 compatible = "allwinner,sun4i-a10-mod0-clk";
228 reg = <0x01c2009c 0x4>; 242 reg = <0x01c2009c 0x4>;
229 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
230 clock-output-names = "ss"; 244 clock-output-names = "ss";
@@ -232,7 +246,7 @@
232 246
233 spi0_clk: clk@01c200a0 { 247 spi0_clk: clk@01c200a0 {
234 #clock-cells = <0>; 248 #clock-cells = <0>;
235 compatible = "allwinner,sun4i-mod0-clk"; 249 compatible = "allwinner,sun4i-a10-mod0-clk";
236 reg = <0x01c200a0 0x4>; 250 reg = <0x01c200a0 0x4>;
237 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
238 clock-output-names = "spi0"; 252 clock-output-names = "spi0";
@@ -240,7 +254,7 @@
240 254
241 spi1_clk: clk@01c200a4 { 255 spi1_clk: clk@01c200a4 {
242 #clock-cells = <0>; 256 #clock-cells = <0>;
243 compatible = "allwinner,sun4i-mod0-clk"; 257 compatible = "allwinner,sun4i-a10-mod0-clk";
244 reg = <0x01c200a4 0x4>; 258 reg = <0x01c200a4 0x4>;
245 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
246 clock-output-names = "spi1"; 260 clock-output-names = "spi1";
@@ -248,7 +262,7 @@
248 262
249 spi2_clk: clk@01c200a8 { 263 spi2_clk: clk@01c200a8 {
250 #clock-cells = <0>; 264 #clock-cells = <0>;
251 compatible = "allwinner,sun4i-mod0-clk"; 265 compatible = "allwinner,sun4i-a10-mod0-clk";
252 reg = <0x01c200a8 0x4>; 266 reg = <0x01c200a8 0x4>;
253 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
254 clock-output-names = "spi2"; 268 clock-output-names = "spi2";
@@ -256,15 +270,24 @@
256 270
257 ir0_clk: clk@01c200b0 { 271 ir0_clk: clk@01c200b0 {
258 #clock-cells = <0>; 272 #clock-cells = <0>;
259 compatible = "allwinner,sun4i-mod0-clk"; 273 compatible = "allwinner,sun4i-a10-mod0-clk";
260 reg = <0x01c200b0 0x4>; 274 reg = <0x01c200b0 0x4>;
261 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
262 clock-output-names = "ir0"; 276 clock-output-names = "ir0";
263 }; 277 };
264 278
279 usb_clk: clk@01c200cc {
280 #clock-cells = <1>;
281 #reset-cells = <1>;
282 compatible = "allwinner,sun5i-a13-usb-clk";
283 reg = <0x01c200cc 0x4>;
284 clocks = <&pll6 1>;
285 clock-output-names = "usb_ohci0", "usb_phy";
286 };
287
265 mbus_clk: clk@01c2015c { 288 mbus_clk: clk@01c2015c {
266 #clock-cells = <0>; 289 #clock-cells = <0>;
267 compatible = "allwinner,sun4i-mod0-clk"; 290 compatible = "allwinner,sun4i-a10-mod0-clk";
268 reg = <0x01c2015c 0x4>; 291 reg = <0x01c2015c 0x4>;
269 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
270 clock-output-names = "mbus"; 293 clock-output-names = "mbus";
@@ -277,6 +300,28 @@
277 #size-cells = <1>; 300 #size-cells = <1>;
278 ranges; 301 ranges;
279 302
303 spi0: spi@01c05000 {
304 compatible = "allwinner,sun4i-a10-spi";
305 reg = <0x01c05000 0x1000>;
306 interrupts = <10>;
307 clocks = <&ahb_gates 20>, <&spi0_clk>;
308 clock-names = "ahb", "mod";
309 status = "disabled";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 };
313
314 spi1: spi@01c06000 {
315 compatible = "allwinner,sun4i-a10-spi";
316 reg = <0x01c06000 0x1000>;
317 interrupts = <11>;
318 clocks = <&ahb_gates 21>, <&spi1_clk>;
319 clock-names = "ahb", "mod";
320 status = "disabled";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 };
324
280 emac: ethernet@01c0b000 { 325 emac: ethernet@01c0b000 {
281 compatible = "allwinner,sun4i-a10-emac"; 326 compatible = "allwinner,sun4i-a10-emac";
282 reg = <0x01c0b000 0x1000>; 327 reg = <0x01c0b000 0x1000>;
@@ -293,6 +338,49 @@
293 #size-cells = <0>; 338 #size-cells = <0>;
294 }; 339 };
295 340
341 usbphy: phy@01c13400 {
342 #phy-cells = <1>;
343 compatible = "allwinner,sun5i-a13-usb-phy";
344 reg = <0x01c13400 0x10 0x01c14800 0x4>;
345 reg-names = "phy_ctrl", "pmu1";
346 clocks = <&usb_clk 8>;
347 clock-names = "usb_phy";
348 resets = <&usb_clk 1>;
349 reset-names = "usb1_reset";
350 status = "disabled";
351 };
352
353 ehci0: usb@01c14000 {
354 compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
355 reg = <0x01c14000 0x100>;
356 interrupts = <39>;
357 clocks = <&ahb_gates 1>;
358 phys = <&usbphy 1>;
359 phy-names = "usb";
360 status = "disabled";
361 };
362
363 ohci0: usb@01c14400 {
364 compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
365 reg = <0x01c14400 0x100>;
366 interrupts = <40>;
367 clocks = <&usb_clk 6>, <&ahb_gates 2>;
368 phys = <&usbphy 1>;
369 phy-names = "usb";
370 status = "disabled";
371 };
372
373 spi2: spi@01c17000 {
374 compatible = "allwinner,sun4i-a10-spi";
375 reg = <0x01c17000 0x1000>;
376 interrupts = <12>;
377 clocks = <&ahb_gates 22>, <&spi2_clk>;
378 clock-names = "ahb", "mod";
379 status = "disabled";
380 #address-cells = <1>;
381 #size-cells = <0>;
382 };
383
296 intc: interrupt-controller@01c20400 { 384 intc: interrupt-controller@01c20400 {
297 compatible = "allwinner,sun4i-a10-ic"; 385 compatible = "allwinner,sun4i-a10-ic";
298 reg = <0x01c20400 0x400>; 386 reg = <0x01c20400 0x400>;
@@ -373,12 +461,12 @@
373 }; 461 };
374 462
375 wdt: watchdog@01c20c90 { 463 wdt: watchdog@01c20c90 {
376 compatible = "allwinner,sun4i-wdt"; 464 compatible = "allwinner,sun4i-a10-wdt";
377 reg = <0x01c20c90 0x10>; 465 reg = <0x01c20c90 0x10>;
378 }; 466 };
379 467
380 sid: eeprom@01c23800 { 468 sid: eeprom@01c23800 {
381 compatible = "allwinner,sun4i-sid"; 469 compatible = "allwinner,sun4i-a10-sid";
382 reg = <0x01c23800 0x10>; 470 reg = <0x01c23800 0x10>;
383 }; 471 };
384 472
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index fe2ce0acdb06..11169d5b5b86 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -14,12 +14,26 @@
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "sun5i-a13.dtsi" 16/include/ "sun5i-a13.dtsi"
17/include/ "sunxi-common-regulators.dtsi"
17 18
18/ { 19/ {
19 model = "Olimex A13-Olinuxino Micro"; 20 model = "Olimex A13-Olinuxino Micro";
20 compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; 21 compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
21 22
22 soc@01c00000 { 23 soc@01c00000 {
24 usbphy: phy@01c13400 {
25 usb1_vbus-supply = <&reg_usb1_vbus>;
26 status = "okay";
27 };
28
29 ehci0: usb@01c14000 {
30 status = "okay";
31 };
32
33 ohci0: usb@01c14400 {
34 status = "okay";
35 };
36
23 pinctrl@01c20800 { 37 pinctrl@01c20800 {
24 led_pins_olinuxinom: led_pins@0 { 38 led_pins_olinuxinom: led_pins@0 {
25 allwinner,pins = "PG9"; 39 allwinner,pins = "PG9";
@@ -27,6 +41,13 @@
27 allwinner,drive = <1>; 41 allwinner,drive = <1>;
28 allwinner,pull = <0>; 42 allwinner,pull = <0>;
29 }; 43 };
44
45 usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 {
46 allwinner,pins = "PG11";
47 allwinner,function = "gpio_out";
48 allwinner,drive = <0>;
49 allwinner,pull = <0>;
50 };
30 }; 51 };
31 52
32 uart1: serial@01c28400 { 53 uart1: serial@01c28400 {
@@ -65,4 +86,10 @@
65 default-state = "on"; 86 default-state = "on";
66 }; 87 };
67 }; 88 };
89
90 reg_usb1_vbus: usb1-vbus {
91 pinctrl-0 = <&usb1_vbus_pin_olinuxinom>;
92 gpio = <&pio 6 11 0>;
93 status = "okay";
94 };
68}; 95};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index a4ba5ff010cf..7a9187bbeb28 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -13,12 +13,26 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun5i-a13.dtsi" 15/include/ "sun5i-a13.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "Olimex A13-Olinuxino"; 19 model = "Olimex A13-Olinuxino";
19 compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; 20 compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
20 21
21 soc@01c00000 { 22 soc@01c00000 {
23 usbphy: phy@01c13400 {
24 usb1_vbus-supply = <&reg_usb1_vbus>;
25 status = "okay";
26 };
27
28 ehci0: usb@01c14000 {
29 status = "okay";
30 };
31
32 ohci0: usb@01c14400 {
33 status = "okay";
34 };
35
22 pinctrl@01c20800 { 36 pinctrl@01c20800 {
23 led_pins_olinuxino: led_pins@0 { 37 led_pins_olinuxino: led_pins@0 {
24 allwinner,pins = "PG9"; 38 allwinner,pins = "PG9";
@@ -26,6 +40,13 @@
26 allwinner,drive = <1>; 40 allwinner,drive = <1>;
27 allwinner,pull = <0>; 41 allwinner,pull = <0>;
28 }; 42 };
43
44 usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
45 allwinner,pins = "PG11";
46 allwinner,function = "gpio_out";
47 allwinner,drive = <0>;
48 allwinner,pull = <0>;
49 };
29 }; 50 };
30 51
31 uart1: serial@01c28400 { 52 uart1: serial@01c28400 {
@@ -63,4 +84,10 @@
63 default-state = "on"; 84 default-state = "on";
64 }; 85 };
65 }; 86 };
87
88 reg_usb1_vbus: usb1-vbus {
89 pinctrl-0 = <&usb1_vbus_pin_olinuxino>;
90 gpio = <&pio 6 11 0>;
91 status = "okay";
92 };
66}; 93};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index b373c74a9b3d..f01c315bdc4b 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -16,6 +16,11 @@
16/ { 16/ {
17 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
18 18
19 aliases {
20 serial0 = &uart1;
21 serial1 = &uart3;
22 };
23
19 cpus { 24 cpus {
20 #address-cells = <1>; 25 #address-cells = <1>;
21 #size-cells = <0>; 26 #size-cells = <0>;
@@ -47,44 +52,48 @@
47 clock-frequency = <0>; 52 clock-frequency = <0>;
48 }; 53 };
49 54
50 osc24M: osc24M@01c20050 { 55 osc24M: clk@01c20050 {
51 #clock-cells = <0>; 56 #clock-cells = <0>;
52 compatible = "allwinner,sun4i-osc-clk"; 57 compatible = "allwinner,sun4i-a10-osc-clk";
53 reg = <0x01c20050 0x4>; 58 reg = <0x01c20050 0x4>;
54 clock-frequency = <24000000>; 59 clock-frequency = <24000000>;
60 clock-output-names = "osc24M";
55 }; 61 };
56 62
57 osc32k: osc32k { 63 osc32k: clk@0 {
58 #clock-cells = <0>; 64 #clock-cells = <0>;
59 compatible = "fixed-clock"; 65 compatible = "fixed-clock";
60 clock-frequency = <32768>; 66 clock-frequency = <32768>;
67 clock-output-names = "osc32k";
61 }; 68 };
62 69
63 pll1: pll1@01c20000 { 70 pll1: clk@01c20000 {
64 #clock-cells = <0>; 71 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk"; 72 compatible = "allwinner,sun4i-a10-pll1-clk";
66 reg = <0x01c20000 0x4>; 73 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 74 clocks = <&osc24M>;
75 clock-output-names = "pll1";
68 }; 76 };
69 77
70 pll4: pll4@01c20018 { 78 pll4: clk@01c20018 {
71 #clock-cells = <0>; 79 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 80 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20018 0x4>; 81 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>; 82 clocks = <&osc24M>;
83 clock-output-names = "pll4";
75 }; 84 };
76 85
77 pll5: pll5@01c20020 { 86 pll5: clk@01c20020 {
78 #clock-cells = <1>; 87 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk"; 88 compatible = "allwinner,sun4i-a10-pll5-clk";
80 reg = <0x01c20020 0x4>; 89 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>; 90 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other"; 91 clock-output-names = "pll5_ddr", "pll5_other";
83 }; 92 };
84 93
85 pll6: pll6@01c20028 { 94 pll6: clk@01c20028 {
86 #clock-cells = <1>; 95 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk"; 96 compatible = "allwinner,sun4i-a10-pll6-clk";
88 reg = <0x01c20028 0x4>; 97 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>; 98 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 99 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +102,23 @@
93 /* dummy is 200M */ 102 /* dummy is 200M */
94 cpu: cpu@01c20054 { 103 cpu: cpu@01c20054 {
95 #clock-cells = <0>; 104 #clock-cells = <0>;
96 compatible = "allwinner,sun4i-cpu-clk"; 105 compatible = "allwinner,sun4i-a10-cpu-clk";
97 reg = <0x01c20054 0x4>; 106 reg = <0x01c20054 0x4>;
98 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
108 clock-output-names = "cpu";
99 }; 109 };
100 110
101 axi: axi@01c20054 { 111 axi: axi@01c20054 {
102 #clock-cells = <0>; 112 #clock-cells = <0>;
103 compatible = "allwinner,sun4i-axi-clk"; 113 compatible = "allwinner,sun4i-a10-axi-clk";
104 reg = <0x01c20054 0x4>; 114 reg = <0x01c20054 0x4>;
105 clocks = <&cpu>; 115 clocks = <&cpu>;
116 clock-output-names = "axi";
106 }; 117 };
107 118
108 axi_gates: axi_gates@01c2005c { 119 axi_gates: clk@01c2005c {
109 #clock-cells = <1>; 120 #clock-cells = <1>;
110 compatible = "allwinner,sun4i-axi-gates-clk"; 121 compatible = "allwinner,sun4i-a10-axi-gates-clk";
111 reg = <0x01c2005c 0x4>; 122 reg = <0x01c2005c 0x4>;
112 clocks = <&axi>; 123 clocks = <&axi>;
113 clock-output-names = "axi_dram"; 124 clock-output-names = "axi_dram";
@@ -115,12 +126,13 @@
115 126
116 ahb: ahb@01c20054 { 127 ahb: ahb@01c20054 {
117 #clock-cells = <0>; 128 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk"; 129 compatible = "allwinner,sun4i-a10-ahb-clk";
119 reg = <0x01c20054 0x4>; 130 reg = <0x01c20054 0x4>;
120 clocks = <&axi>; 131 clocks = <&axi>;
132 clock-output-names = "ahb";
121 }; 133 };
122 134
123 ahb_gates: ahb_gates@01c20060 { 135 ahb_gates: clk@01c20060 {
124 #clock-cells = <1>; 136 #clock-cells = <1>;
125 compatible = "allwinner,sun5i-a13-ahb-gates-clk"; 137 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
126 reg = <0x01c20060 0x8>; 138 reg = <0x01c20060 0x8>;
@@ -135,12 +147,13 @@
135 147
136 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
137 #clock-cells = <0>; 149 #clock-cells = <0>;
138 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
139 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
140 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0";
141 }; 154 };
142 155
143 apb0_gates: apb0_gates@01c20068 { 156 apb0_gates: clk@01c20068 {
144 #clock-cells = <1>; 157 #clock-cells = <1>;
145 compatible = "allwinner,sun5i-a13-apb0-gates-clk"; 158 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
146 reg = <0x01c20068 0x4>; 159 reg = <0x01c20068 0x4>;
@@ -150,19 +163,21 @@
150 163
151 apb1_mux: apb1_mux@01c20058 { 164 apb1_mux: apb1_mux@01c20058 {
152 #clock-cells = <0>; 165 #clock-cells = <0>;
153 compatible = "allwinner,sun4i-apb1-mux-clk"; 166 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
154 reg = <0x01c20058 0x4>; 167 reg = <0x01c20058 0x4>;
155 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169 clock-output-names = "apb1_mux";
156 }; 170 };
157 171
158 apb1: apb1@01c20058 { 172 apb1: apb1@01c20058 {
159 #clock-cells = <0>; 173 #clock-cells = <0>;
160 compatible = "allwinner,sun4i-apb1-clk"; 174 compatible = "allwinner,sun4i-a10-apb1-clk";
161 reg = <0x01c20058 0x4>; 175 reg = <0x01c20058 0x4>;
162 clocks = <&apb1_mux>; 176 clocks = <&apb1_mux>;
177 clock-output-names = "apb1";
163 }; 178 };
164 179
165 apb1_gates: apb1_gates@01c2006c { 180 apb1_gates: clk@01c2006c {
166 #clock-cells = <1>; 181 #clock-cells = <1>;
167 compatible = "allwinner,sun5i-a13-apb1-gates-clk"; 182 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
168 reg = <0x01c2006c 0x4>; 183 reg = <0x01c2006c 0x4>;
@@ -173,7 +188,7 @@
173 188
174 nand_clk: clk@01c20080 { 189 nand_clk: clk@01c20080 {
175 #clock-cells = <0>; 190 #clock-cells = <0>;
176 compatible = "allwinner,sun4i-mod0-clk"; 191 compatible = "allwinner,sun4i-a10-mod0-clk";
177 reg = <0x01c20080 0x4>; 192 reg = <0x01c20080 0x4>;
178 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
179 clock-output-names = "nand"; 194 clock-output-names = "nand";
@@ -181,7 +196,7 @@
181 196
182 ms_clk: clk@01c20084 { 197 ms_clk: clk@01c20084 {
183 #clock-cells = <0>; 198 #clock-cells = <0>;
184 compatible = "allwinner,sun4i-mod0-clk"; 199 compatible = "allwinner,sun4i-a10-mod0-clk";
185 reg = <0x01c20084 0x4>; 200 reg = <0x01c20084 0x4>;
186 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
187 clock-output-names = "ms"; 202 clock-output-names = "ms";
@@ -189,7 +204,7 @@
189 204
190 mmc0_clk: clk@01c20088 { 205 mmc0_clk: clk@01c20088 {
191 #clock-cells = <0>; 206 #clock-cells = <0>;
192 compatible = "allwinner,sun4i-mod0-clk"; 207 compatible = "allwinner,sun4i-a10-mod0-clk";
193 reg = <0x01c20088 0x4>; 208 reg = <0x01c20088 0x4>;
194 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195 clock-output-names = "mmc0"; 210 clock-output-names = "mmc0";
@@ -197,7 +212,7 @@
197 212
198 mmc1_clk: clk@01c2008c { 213 mmc1_clk: clk@01c2008c {
199 #clock-cells = <0>; 214 #clock-cells = <0>;
200 compatible = "allwinner,sun4i-mod0-clk"; 215 compatible = "allwinner,sun4i-a10-mod0-clk";
201 reg = <0x01c2008c 0x4>; 216 reg = <0x01c2008c 0x4>;
202 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203 clock-output-names = "mmc1"; 218 clock-output-names = "mmc1";
@@ -205,7 +220,7 @@
205 220
206 mmc2_clk: clk@01c20090 { 221 mmc2_clk: clk@01c20090 {
207 #clock-cells = <0>; 222 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-mod0-clk"; 223 compatible = "allwinner,sun4i-a10-mod0-clk";
209 reg = <0x01c20090 0x4>; 224 reg = <0x01c20090 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "mmc2"; 226 clock-output-names = "mmc2";
@@ -213,7 +228,7 @@
213 228
214 ts_clk: clk@01c20098 { 229 ts_clk: clk@01c20098 {
215 #clock-cells = <0>; 230 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-mod0-clk"; 231 compatible = "allwinner,sun4i-a10-mod0-clk";
217 reg = <0x01c20098 0x4>; 232 reg = <0x01c20098 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ts"; 234 clock-output-names = "ts";
@@ -221,7 +236,7 @@
221 236
222 ss_clk: clk@01c2009c { 237 ss_clk: clk@01c2009c {
223 #clock-cells = <0>; 238 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-mod0-clk"; 239 compatible = "allwinner,sun4i-a10-mod0-clk";
225 reg = <0x01c2009c 0x4>; 240 reg = <0x01c2009c 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "ss"; 242 clock-output-names = "ss";
@@ -229,7 +244,7 @@
229 244
230 spi0_clk: clk@01c200a0 { 245 spi0_clk: clk@01c200a0 {
231 #clock-cells = <0>; 246 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-mod0-clk"; 247 compatible = "allwinner,sun4i-a10-mod0-clk";
233 reg = <0x01c200a0 0x4>; 248 reg = <0x01c200a0 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "spi0"; 250 clock-output-names = "spi0";
@@ -237,7 +252,7 @@
237 252
238 spi1_clk: clk@01c200a4 { 253 spi1_clk: clk@01c200a4 {
239 #clock-cells = <0>; 254 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-mod0-clk"; 255 compatible = "allwinner,sun4i-a10-mod0-clk";
241 reg = <0x01c200a4 0x4>; 256 reg = <0x01c200a4 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "spi1"; 258 clock-output-names = "spi1";
@@ -245,7 +260,7 @@
245 260
246 spi2_clk: clk@01c200a8 { 261 spi2_clk: clk@01c200a8 {
247 #clock-cells = <0>; 262 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-mod0-clk"; 263 compatible = "allwinner,sun4i-a10-mod0-clk";
249 reg = <0x01c200a8 0x4>; 264 reg = <0x01c200a8 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "spi2"; 266 clock-output-names = "spi2";
@@ -253,15 +268,24 @@
253 268
254 ir0_clk: clk@01c200b0 { 269 ir0_clk: clk@01c200b0 {
255 #clock-cells = <0>; 270 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-mod0-clk"; 271 compatible = "allwinner,sun4i-a10-mod0-clk";
257 reg = <0x01c200b0 0x4>; 272 reg = <0x01c200b0 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ir0"; 274 clock-output-names = "ir0";
260 }; 275 };
261 276
277 usb_clk: clk@01c200cc {
278 #clock-cells = <1>;
279 #reset-cells = <1>;
280 compatible = "allwinner,sun5i-a13-usb-clk";
281 reg = <0x01c200cc 0x4>;
282 clocks = <&pll6 1>;
283 clock-output-names = "usb_ohci0", "usb_phy";
284 };
285
262 mbus_clk: clk@01c2015c { 286 mbus_clk: clk@01c2015c {
263 #clock-cells = <0>; 287 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-mod0-clk"; 288 compatible = "allwinner,sun4i-a10-mod0-clk";
265 reg = <0x01c2015c 0x4>; 289 reg = <0x01c2015c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "mbus"; 291 clock-output-names = "mbus";
@@ -274,6 +298,71 @@
274 #size-cells = <1>; 298 #size-cells = <1>;
275 ranges; 299 ranges;
276 300
301 spi0: spi@01c05000 {
302 compatible = "allwinner,sun4i-a10-spi";
303 reg = <0x01c05000 0x1000>;
304 interrupts = <10>;
305 clocks = <&ahb_gates 20>, <&spi0_clk>;
306 clock-names = "ahb", "mod";
307 status = "disabled";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 };
311
312 spi1: spi@01c06000 {
313 compatible = "allwinner,sun4i-a10-spi";
314 reg = <0x01c06000 0x1000>;
315 interrupts = <11>;
316 clocks = <&ahb_gates 21>, <&spi1_clk>;
317 clock-names = "ahb", "mod";
318 status = "disabled";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 };
322
323 usbphy: phy@01c13400 {
324 #phy-cells = <1>;
325 compatible = "allwinner,sun5i-a13-usb-phy";
326 reg = <0x01c13400 0x10 0x01c14800 0x4>;
327 reg-names = "phy_ctrl", "pmu1";
328 clocks = <&usb_clk 8>;
329 clock-names = "usb_phy";
330 resets = <&usb_clk 1>;
331 reset-names = "usb1_reset";
332 status = "disabled";
333 };
334
335 ehci0: usb@01c14000 {
336 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
337 reg = <0x01c14000 0x100>;
338 interrupts = <39>;
339 clocks = <&ahb_gates 1>;
340 phys = <&usbphy 1>;
341 phy-names = "usb";
342 status = "disabled";
343 };
344
345 ohci0: usb@01c14400 {
346 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
347 reg = <0x01c14400 0x100>;
348 interrupts = <40>;
349 clocks = <&usb_clk 6>, <&ahb_gates 2>;
350 phys = <&usbphy 1>;
351 phy-names = "usb";
352 status = "disabled";
353 };
354
355 spi2: spi@01c17000 {
356 compatible = "allwinner,sun4i-a10-spi";
357 reg = <0x01c17000 0x1000>;
358 interrupts = <12>;
359 clocks = <&ahb_gates 22>, <&spi2_clk>;
360 clock-names = "ahb", "mod";
361 status = "disabled";
362 #address-cells = <1>;
363 #size-cells = <0>;
364 };
365
277 intc: interrupt-controller@01c20400 { 366 intc: interrupt-controller@01c20400 {
278 compatible = "allwinner,sun4i-a10-ic"; 367 compatible = "allwinner,sun4i-a10-ic";
279 reg = <0x01c20400 0x400>; 368 reg = <0x01c20400 0x400>;
@@ -336,12 +425,12 @@
336 }; 425 };
337 426
338 wdt: watchdog@01c20c90 { 427 wdt: watchdog@01c20c90 {
339 compatible = "allwinner,sun4i-wdt"; 428 compatible = "allwinner,sun4i-a10-wdt";
340 reg = <0x01c20c90 0x10>; 429 reg = <0x01c20c90 0x10>;
341 }; 430 };
342 431
343 sid: eeprom@01c23800 { 432 sid: eeprom@01c23800 {
344 compatible = "allwinner,sun4i-sid"; 433 compatible = "allwinner,sun4i-a10-sid";
345 reg = <0x01c23800 0x10>; 434 reg = <0x01c23800 0x10>;
346 }; 435 };
347 436
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index e5adae30899b..3898a7bce831 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -28,5 +28,23 @@
28 pinctrl-0 = <&uart0_pins_a>; 28 pinctrl-0 = <&uart0_pins_a>;
29 status = "okay"; 29 status = "okay";
30 }; 30 };
31
32 i2c0: i2c@01c2ac00 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&i2c0_pins_a>;
35 status = "fail";
36 };
37
38 i2c1: i2c@01c2b000 {
39 pinctrl-names = "default";
40 pinctrl-0 = <&i2c1_pins_a>;
41 status = "okay";
42 };
43
44 i2c2: i2c@01c2b400 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&i2c2_pins_a>;
47 status = "okay";
48 };
31 }; 49 };
32}; 50};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 38d43febda4c..d45efa74827c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -16,6 +16,16 @@
16/ { 16/ {
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 aliases {
20 serial0 = &uart0;
21 serial1 = &uart1;
22 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &uart5;
26 };
27
28
19 cpus { 29 cpus {
20 #address-cells = <1>; 30 #address-cells = <1>;
21 #size-cells = <0>; 31 #size-cells = <0>;
@@ -60,34 +70,32 @@
60 clock-frequency = <24000000>; 70 clock-frequency = <24000000>;
61 }; 71 };
62 72
63 osc32k: osc32k { 73 osc32k: clk@0 {
64 #clock-cells = <0>; 74 #clock-cells = <0>;
65 compatible = "fixed-clock"; 75 compatible = "fixed-clock";
66 clock-frequency = <32768>; 76 clock-frequency = <32768>;
77 clock-output-names = "osc32k";
67 }; 78 };
68 79
69 pll1: pll1@01c20000 { 80 pll1: clk@01c20000 {
70 #clock-cells = <0>; 81 #clock-cells = <0>;
71 compatible = "allwinner,sun6i-a31-pll1-clk"; 82 compatible = "allwinner,sun6i-a31-pll1-clk";
72 reg = <0x01c20000 0x4>; 83 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>; 84 clocks = <&osc24M>;
85 clock-output-names = "pll1";
74 }; 86 };
75 87
76 /* 88 pll6: clk@01c20028 {
77 * This is a dummy clock, to be used as placeholder on
78 * other mux clocks when a specific parent clock is not
79 * yet implemented. It should be dropped when the driver
80 * is complete.
81 */
82 pll6: pll6 {
83 #clock-cells = <0>; 89 #clock-cells = <0>;
84 compatible = "fixed-clock"; 90 compatible = "allwinner,sun6i-a31-pll6-clk";
85 clock-frequency = <0>; 91 reg = <0x01c20028 0x4>;
92 clocks = <&osc24M>;
93 clock-output-names = "pll6";
86 }; 94 };
87 95
88 cpu: cpu@01c20050 { 96 cpu: cpu@01c20050 {
89 #clock-cells = <0>; 97 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-cpu-clk"; 98 compatible = "allwinner,sun4i-a10-cpu-clk";
91 reg = <0x01c20050 0x4>; 99 reg = <0x01c20050 0x4>;
92 100
93 /* 101 /*
@@ -97,13 +105,15 @@
97 * Allwinner. 105 * Allwinner.
98 */ 106 */
99 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; 107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
108 clock-output-names = "cpu";
100 }; 109 };
101 110
102 axi: axi@01c20050 { 111 axi: axi@01c20050 {
103 #clock-cells = <0>; 112 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-axi-clk"; 113 compatible = "allwinner,sun4i-a10-axi-clk";
105 reg = <0x01c20050 0x4>; 114 reg = <0x01c20050 0x4>;
106 clocks = <&cpu>; 115 clocks = <&cpu>;
116 clock-output-names = "axi";
107 }; 117 };
108 118
109 ahb1_mux: ahb1_mux@01c20054 { 119 ahb1_mux: ahb1_mux@01c20054 {
@@ -111,16 +121,18 @@
111 compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; 121 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
112 reg = <0x01c20054 0x4>; 122 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; 123 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
124 clock-output-names = "ahb1_mux";
114 }; 125 };
115 126
116 ahb1: ahb1@01c20054 { 127 ahb1: ahb1@01c20054 {
117 #clock-cells = <0>; 128 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk"; 129 compatible = "allwinner,sun4i-a10-ahb-clk";
119 reg = <0x01c20054 0x4>; 130 reg = <0x01c20054 0x4>;
120 clocks = <&ahb1_mux>; 131 clocks = <&ahb1_mux>;
132 clock-output-names = "ahb1";
121 }; 133 };
122 134
123 ahb1_gates: ahb1_gates@01c20060 { 135 ahb1_gates: clk@01c20060 {
124 #clock-cells = <1>; 136 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; 137 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
126 reg = <0x01c20060 0x8>; 138 reg = <0x01c20060 0x8>;
@@ -143,12 +155,13 @@
143 155
144 apb1: apb1@01c20054 { 156 apb1: apb1@01c20054 {
145 #clock-cells = <0>; 157 #clock-cells = <0>;
146 compatible = "allwinner,sun4i-apb0-clk"; 158 compatible = "allwinner,sun4i-a10-apb0-clk";
147 reg = <0x01c20054 0x4>; 159 reg = <0x01c20054 0x4>;
148 clocks = <&ahb1>; 160 clocks = <&ahb1>;
161 clock-output-names = "apb1";
149 }; 162 };
150 163
151 apb1_gates: apb1_gates@01c20060 { 164 apb1_gates: clk@01c20068 {
152 #clock-cells = <1>; 165 #clock-cells = <1>;
153 compatible = "allwinner,sun6i-a31-apb1-gates-clk"; 166 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
154 reg = <0x01c20068 0x4>; 167 reg = <0x01c20068 0x4>;
@@ -160,9 +173,10 @@
160 173
161 apb2_mux: apb2_mux@01c20058 { 174 apb2_mux: apb2_mux@01c20058 {
162 #clock-cells = <0>; 175 #clock-cells = <0>;
163 compatible = "allwinner,sun4i-apb1-mux-clk"; 176 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
164 reg = <0x01c20058 0x4>; 177 reg = <0x01c20058 0x4>;
165 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 178 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
179 clock-output-names = "apb2_mux";
166 }; 180 };
167 181
168 apb2: apb2@01c20058 { 182 apb2: apb2@01c20058 {
@@ -170,9 +184,10 @@
170 compatible = "allwinner,sun6i-a31-apb2-div-clk"; 184 compatible = "allwinner,sun6i-a31-apb2-div-clk";
171 reg = <0x01c20058 0x4>; 185 reg = <0x01c20058 0x4>;
172 clocks = <&apb2_mux>; 186 clocks = <&apb2_mux>;
187 clock-output-names = "apb2";
173 }; 188 };
174 189
175 apb2_gates: apb2_gates@01c2006c { 190 apb2_gates: clk@01c2006c {
176 #clock-cells = <1>; 191 #clock-cells = <1>;
177 compatible = "allwinner,sun6i-a31-apb2-gates-clk"; 192 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
178 reg = <0x01c2006c 0x4>; 193 reg = <0x01c2006c 0x4>;
@@ -182,6 +197,38 @@
182 "apb2_uart1", "apb2_uart2", "apb2_uart3", 197 "apb2_uart1", "apb2_uart2", "apb2_uart3",
183 "apb2_uart4", "apb2_uart5"; 198 "apb2_uart4", "apb2_uart5";
184 }; 199 };
200
201 spi0_clk: clk@01c200a0 {
202 #clock-cells = <0>;
203 compatible = "allwinner,sun4i-a10-mod0-clk";
204 reg = <0x01c200a0 0x4>;
205 clocks = <&osc24M>, <&pll6>;
206 clock-output-names = "spi0";
207 };
208
209 spi1_clk: clk@01c200a4 {
210 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-a10-mod0-clk";
212 reg = <0x01c200a4 0x4>;
213 clocks = <&osc24M>, <&pll6>;
214 clock-output-names = "spi1";
215 };
216
217 spi2_clk: clk@01c200a8 {
218 #clock-cells = <0>;
219 compatible = "allwinner,sun4i-a10-mod0-clk";
220 reg = <0x01c200a8 0x4>;
221 clocks = <&osc24M>, <&pll6>;
222 clock-output-names = "spi2";
223 };
224
225 spi3_clk: clk@01c200ac {
226 #clock-cells = <0>;
227 compatible = "allwinner,sun4i-a10-mod0-clk";
228 reg = <0x01c200ac 0x4>;
229 clocks = <&osc24M>, <&pll6>;
230 clock-output-names = "spi3";
231 };
185 }; 232 };
186 233
187 soc@01c00000 { 234 soc@01c00000 {
@@ -218,6 +265,27 @@
218 allwinner,drive = <0>; 265 allwinner,drive = <0>;
219 allwinner,pull = <0>; 266 allwinner,pull = <0>;
220 }; 267 };
268
269 i2c0_pins_a: i2c0@0 {
270 allwinner,pins = "PH14", "PH15";
271 allwinner,function = "i2c0";
272 allwinner,drive = <0>;
273 allwinner,pull = <0>;
274 };
275
276 i2c1_pins_a: i2c1@0 {
277 allwinner,pins = "PH16", "PH17";
278 allwinner,function = "i2c1";
279 allwinner,drive = <0>;
280 allwinner,pull = <0>;
281 };
282
283 i2c2_pins_a: i2c2@0 {
284 allwinner,pins = "PH18", "PH19";
285 allwinner,function = "i2c2";
286 allwinner,drive = <0>;
287 allwinner,pull = <0>;
288 };
221 }; 289 };
222 290
223 ahb1_rst: reset@01c202c0 { 291 ahb1_rst: reset@01c202c0 {
@@ -250,7 +318,7 @@
250 }; 318 };
251 319
252 wdt1: watchdog@01c20ca0 { 320 wdt1: watchdog@01c20ca0 {
253 compatible = "allwinner,sun6i-wdt"; 321 compatible = "allwinner,sun6i-a31-wdt";
254 reg = <0x01c20ca0 0x20>; 322 reg = <0x01c20ca0 0x20>;
255 }; 323 };
256 324
@@ -320,6 +388,86 @@
320 status = "disabled"; 388 status = "disabled";
321 }; 389 };
322 390
391 i2c0: i2c@01c2ac00 {
392 compatible = "allwinner,sun6i-a31-i2c";
393 reg = <0x01c2ac00 0x400>;
394 interrupts = <0 6 4>;
395 clocks = <&apb2_gates 0>;
396 clock-frequency = <100000>;
397 resets = <&apb2_rst 0>;
398 status = "disabled";
399 };
400
401 i2c1: i2c@01c2b000 {
402 compatible = "allwinner,sun6i-a31-i2c";
403 reg = <0x01c2b000 0x400>;
404 interrupts = <0 7 4>;
405 clocks = <&apb2_gates 1>;
406 clock-frequency = <100000>;
407 resets = <&apb2_rst 1>;
408 status = "disabled";
409 };
410
411 i2c2: i2c@01c2b400 {
412 compatible = "allwinner,sun6i-a31-i2c";
413 reg = <0x01c2b400 0x400>;
414 interrupts = <0 8 4>;
415 clocks = <&apb2_gates 2>;
416 clock-frequency = <100000>;
417 resets = <&apb2_rst 2>;
418 status = "disabled";
419 };
420
421 i2c3: i2c@01c2b800 {
422 compatible = "allwinner,sun6i-a31-i2c";
423 reg = <0x01c2b800 0x400>;
424 interrupts = <0 9 4>;
425 clocks = <&apb2_gates 3>;
426 clock-frequency = <100000>;
427 resets = <&apb2_rst 3>;
428 status = "disabled";
429 };
430
431 spi0: spi@01c68000 {
432 compatible = "allwinner,sun6i-a31-spi";
433 reg = <0x01c68000 0x1000>;
434 interrupts = <0 65 4>;
435 clocks = <&ahb1_gates 20>, <&spi0_clk>;
436 clock-names = "ahb", "mod";
437 resets = <&ahb1_rst 20>;
438 status = "disabled";
439 };
440
441 spi1: spi@01c69000 {
442 compatible = "allwinner,sun6i-a31-spi";
443 reg = <0x01c69000 0x1000>;
444 interrupts = <0 66 4>;
445 clocks = <&ahb1_gates 21>, <&spi1_clk>;
446 clock-names = "ahb", "mod";
447 resets = <&ahb1_rst 21>;
448 status = "disabled";
449 };
450
451 spi2: spi@01c6a000 {
452 compatible = "allwinner,sun6i-a31-spi";
453 reg = <0x01c6a000 0x1000>;
454 interrupts = <0 67 4>;
455 clocks = <&ahb1_gates 22>, <&spi2_clk>;
456 clock-names = "ahb", "mod";
457 resets = <&ahb1_rst 22>;
458 status = "disabled";
459 };
460
461 spi3: spi@01c6b000 {
462 compatible = "allwinner,sun6i-a31-spi";
463 reg = <0x01c6b000 0x1000>;
464 interrupts = <0 68 4>;
465 clocks = <&ahb1_gates 23>, <&spi3_clk>;
466 clock-names = "ahb", "mod";
467 resets = <&ahb1_rst 23>;
468 status = "disabled";
469 };
470
323 gic: interrupt-controller@01c81000 { 471 gic: interrupt-controller@01c81000 {
324 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 472 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
325 reg = <0x01c81000 0x1000>, 473 reg = <0x01c81000 0x1000>,
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 5c51cb8a98b0..68de89ffbdfa 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -13,25 +13,38 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun7i-a20.dtsi" 15/include/ "sun7i-a20.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "Cubietech Cubieboard2"; 19 model = "Cubietech Cubieboard2";
19 compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; 20 compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
20 21
21 soc@01c00000 { 22 soc@01c00000 {
22 emac: ethernet@01c0b000 { 23 usbphy: phy@01c13400 {
23 pinctrl-names = "default"; 24 usb1_vbus-supply = <&reg_usb1_vbus>;
24 pinctrl-0 = <&emac_pins_a>; 25 usb2_vbus-supply = <&reg_usb2_vbus>;
25 phy = <&phy1>;
26 status = "okay"; 26 status = "okay";
27 }; 27 };
28 28
29 mdio@01c0b080 { 29 ehci0: usb@01c14000 {
30 status = "okay"; 30 status = "okay";
31 };
31 32
32 phy1: ethernet-phy@1 { 33 ohci0: usb@01c14400 {
33 reg = <1>; 34 status = "okay";
34 }; 35 };
36
37 ahci: sata@01c18000 {
38 target-supply = <&reg_ahci_5v>;
39 status = "okay";
40 };
41
42 ehci1: usb@01c1c000 {
43 status = "okay";
44 };
45
46 ohci1: usb@01c1c400 {
47 status = "okay";
35 }; 48 };
36 49
37 pinctrl@01c20800 { 50 pinctrl@01c20800 {
@@ -60,6 +73,18 @@
60 pinctrl-0 = <&i2c1_pins_a>; 73 pinctrl-0 = <&i2c1_pins_a>;
61 status = "okay"; 74 status = "okay";
62 }; 75 };
76
77 gmac: ethernet@01c50000 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&gmac_pins_mii_a>;
80 phy = <&phy1>;
81 phy-mode = "mii";
82 status = "okay";
83
84 phy1: ethernet-phy@1 {
85 reg = <1>;
86 };
87 };
63 }; 88 };
64 89
65 leds { 90 leds {
@@ -77,4 +102,16 @@
77 gpios = <&pio 7 20 0>; 102 gpios = <&pio 7 20 0>;
78 }; 103 };
79 }; 104 };
105
106 reg_ahci_5v: ahci-5v {
107 status = "okay";
108 };
109
110 reg_usb1_vbus: usb1-vbus {
111 status = "okay";
112 };
113
114 reg_usb2_vbus: usb2-vbus {
115 status = "okay";
116 };
80}; 117};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f9dcb61a5305..cb25d3c8da58 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -13,13 +13,48 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun7i-a20.dtsi" 15/include/ "sun7i-a20.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "Cubietech Cubietruck"; 19 model = "Cubietech Cubietruck";
19 compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; 20 compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
20 21
21 soc@01c00000 { 22 soc@01c00000 {
23 usbphy: phy@01c13400 {
24 usb1_vbus-supply = <&reg_usb1_vbus>;
25 usb2_vbus-supply = <&reg_usb2_vbus>;
26 status = "okay";
27 };
28
29 ehci0: usb@01c14000 {
30 status = "okay";
31 };
32
33 ohci0: usb@01c14400 {
34 status = "okay";
35 };
36
37 ahci: sata@01c18000 {
38 target-supply = <&reg_ahci_5v>;
39 status = "okay";
40 };
41
42 ehci1: usb@01c1c000 {
43 status = "okay";
44 };
45
46 ohci1: usb@01c1c400 {
47 status = "okay";
48 };
49
22 pinctrl@01c20800 { 50 pinctrl@01c20800 {
51 ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
52 allwinner,pins = "PH12";
53 allwinner,function = "gpio_out";
54 allwinner,drive = <0>;
55 allwinner,pull = <0>;
56 };
57
23 led_pins_cubietruck: led_pins@0 { 58 led_pins_cubietruck: led_pins@0 {
24 allwinner,pins = "PH7", "PH11", "PH20", "PH21"; 59 allwinner,pins = "PH7", "PH11", "PH20", "PH21";
25 allwinner,function = "gpio_out"; 60 allwinner,function = "gpio_out";
@@ -51,6 +86,18 @@
51 pinctrl-0 = <&i2c2_pins_a>; 86 pinctrl-0 = <&i2c2_pins_a>;
52 status = "okay"; 87 status = "okay";
53 }; 88 };
89
90 gmac: ethernet@01c50000 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&gmac_pins_rgmii_a>;
93 phy = <&phy1>;
94 phy-mode = "rgmii";
95 status = "okay";
96
97 phy1: ethernet-phy@1 {
98 reg = <1>;
99 };
100 };
54 }; 101 };
55 102
56 leds { 103 leds {
@@ -78,4 +125,18 @@
78 gpios = <&pio 7 7 0>; 125 gpios = <&pio 7 7 0>;
79 }; 126 };
80 }; 127 };
128
129 reg_ahci_5v: ahci-5v {
130 pinctrl-0 = <&ahci_pwr_pin_cubietruck>;
131 gpio = <&pio 7 12 0>;
132 status = "okay";
133 };
134
135 reg_usb1_vbus: usb1-vbus {
136 status = "okay";
137 };
138
139 reg_usb2_vbus: usb2-vbus {
140 status = "okay";
141 };
81}; 142};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index ead3013f9aca..eeadf76362fa 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -13,25 +13,55 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sun7i-a20.dtsi" 15/include/ "sun7i-a20.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
16 17
17/ { 18/ {
18 model = "Olimex A20-Olinuxino Micro"; 19 model = "Olimex A20-Olinuxino Micro";
19 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; 20 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
20 21
22 aliases {
23 spi0 = &spi1;
24 spi1 = &spi2;
25 };
26
21 soc@01c00000 { 27 soc@01c00000 {
22 emac: ethernet@01c0b000 { 28 spi1: spi@01c06000 {
23 pinctrl-names = "default"; 29 pinctrl-names = "default";
24 pinctrl-0 = <&emac_pins_a>; 30 pinctrl-0 = <&spi1_pins_a>;
25 phy = <&phy1>;
26 status = "okay"; 31 status = "okay";
27 }; 32 };
28 33
29 mdio@01c0b080 { 34 usbphy: phy@01c13400 {
35 usb1_vbus-supply = <&reg_usb1_vbus>;
36 usb2_vbus-supply = <&reg_usb2_vbus>;
30 status = "okay"; 37 status = "okay";
38 };
31 39
32 phy1: ethernet-phy@1 { 40 ehci0: usb@01c14000 {
33 reg = <1>; 41 status = "okay";
34 }; 42 };
43
44 ohci0: usb@01c14400 {
45 status = "okay";
46 };
47
48 spi2: spi@01c17000 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&spi2_pins_a>;
51 status = "okay";
52 };
53
54 ahci: sata@01c18000 {
55 target-supply = <&reg_ahci_5v>;
56 status = "okay";
57 };
58
59 ehci1: usb@01c1c000 {
60 status = "okay";
61 };
62
63 ohci1: usb@01c1c400 {
64 status = "okay";
35 }; 65 };
36 66
37 pinctrl@01c20800 { 67 pinctrl@01c20800 {
@@ -78,6 +108,18 @@
78 pinctrl-0 = <&i2c2_pins_a>; 108 pinctrl-0 = <&i2c2_pins_a>;
79 status = "okay"; 109 status = "okay";
80 }; 110 };
111
112 gmac: ethernet@01c50000 {
113 pinctrl-names = "default";
114 pinctrl-0 = <&gmac_pins_mii_a>;
115 phy = <&phy1>;
116 phy-mode = "mii";
117 status = "okay";
118
119 phy1: ethernet-phy@1 {
120 reg = <1>;
121 };
122 };
81 }; 123 };
82 124
83 leds { 125 leds {
@@ -91,4 +133,16 @@
91 default-state = "on"; 133 default-state = "on";
92 }; 134 };
93 }; 135 };
136
137 reg_ahci_5v: ahci-5v {
138 status = "okay";
139 };
140
141 reg_usb1_vbus: usb1-vbus {
142 status = "okay";
143 };
144
145 reg_usb2_vbus: usb2-vbus {
146 status = "okay";
147 };
94}; 148};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index cadcf2f9881d..32efc105df83 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -17,7 +17,15 @@
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 aliases { 19 aliases {
20 ethernet0 = &emac; 20 ethernet0 = &gmac;
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
27 serial6 = &uart6;
28 serial7 = &uart7;
21 }; 29 };
22 30
23 cpus { 31 cpus {
@@ -41,16 +49,25 @@
41 reg = <0x40000000 0x80000000>; 49 reg = <0x40000000 0x80000000>;
42 }; 50 };
43 51
52 timer {
53 compatible = "arm,armv7-timer";
54 interrupts = <1 13 0xf08>,
55 <1 14 0xf08>,
56 <1 11 0xf08>,
57 <1 10 0xf08>;
58 };
59
44 clocks { 60 clocks {
45 #address-cells = <1>; 61 #address-cells = <1>;
46 #size-cells = <1>; 62 #size-cells = <1>;
47 ranges; 63 ranges;
48 64
49 osc24M: osc24M@01c20050 { 65 osc24M: clk@01c20050 {
50 #clock-cells = <0>; 66 #clock-cells = <0>;
51 compatible = "allwinner,sun4i-osc-clk"; 67 compatible = "allwinner,sun4i-a10-osc-clk";
52 reg = <0x01c20050 0x4>; 68 reg = <0x01c20050 0x4>;
53 clock-frequency = <24000000>; 69 clock-frequency = <24000000>;
70 clock-output-names = "osc24M";
54 }; 71 };
55 72
56 osc32k: clk@0 { 73 osc32k: clk@0 {
@@ -60,31 +77,33 @@
60 clock-output-names = "osc32k"; 77 clock-output-names = "osc32k";
61 }; 78 };
62 79
63 pll1: pll1@01c20000 { 80 pll1: clk@01c20000 {
64 #clock-cells = <0>; 81 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk"; 82 compatible = "allwinner,sun4i-a10-pll1-clk";
66 reg = <0x01c20000 0x4>; 83 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 84 clocks = <&osc24M>;
85 clock-output-names = "pll1";
68 }; 86 };
69 87
70 pll4: pll4@01c20018 { 88 pll4: clk@01c20018 {
71 #clock-cells = <0>; 89 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 90 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20018 0x4>; 91 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>; 92 clocks = <&osc24M>;
93 clock-output-names = "pll4";
75 }; 94 };
76 95
77 pll5: pll5@01c20020 { 96 pll5: clk@01c20020 {
78 #clock-cells = <1>; 97 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk"; 98 compatible = "allwinner,sun4i-a10-pll5-clk";
80 reg = <0x01c20020 0x4>; 99 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>; 100 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other"; 101 clock-output-names = "pll5_ddr", "pll5_other";
83 }; 102 };
84 103
85 pll6: pll6@01c20028 { 104 pll6: clk@01c20028 {
86 #clock-cells = <1>; 105 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk"; 106 compatible = "allwinner,sun4i-a10-pll6-clk";
88 reg = <0x01c20028 0x4>; 107 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>; 108 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 109 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -92,26 +111,29 @@
92 111
93 cpu: cpu@01c20054 { 112 cpu: cpu@01c20054 {
94 #clock-cells = <0>; 113 #clock-cells = <0>;
95 compatible = "allwinner,sun4i-cpu-clk"; 114 compatible = "allwinner,sun4i-a10-cpu-clk";
96 reg = <0x01c20054 0x4>; 115 reg = <0x01c20054 0x4>;
97 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; 116 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
117 clock-output-names = "cpu";
98 }; 118 };
99 119
100 axi: axi@01c20054 { 120 axi: axi@01c20054 {
101 #clock-cells = <0>; 121 #clock-cells = <0>;
102 compatible = "allwinner,sun4i-axi-clk"; 122 compatible = "allwinner,sun4i-a10-axi-clk";
103 reg = <0x01c20054 0x4>; 123 reg = <0x01c20054 0x4>;
104 clocks = <&cpu>; 124 clocks = <&cpu>;
125 clock-output-names = "axi";
105 }; 126 };
106 127
107 ahb: ahb@01c20054 { 128 ahb: ahb@01c20054 {
108 #clock-cells = <0>; 129 #clock-cells = <0>;
109 compatible = "allwinner,sun4i-ahb-clk"; 130 compatible = "allwinner,sun4i-a10-ahb-clk";
110 reg = <0x01c20054 0x4>; 131 reg = <0x01c20054 0x4>;
111 clocks = <&axi>; 132 clocks = <&axi>;
133 clock-output-names = "ahb";
112 }; 134 };
113 135
114 ahb_gates: ahb_gates@01c20060 { 136 ahb_gates: clk@01c20060 {
115 #clock-cells = <1>; 137 #clock-cells = <1>;
116 compatible = "allwinner,sun7i-a20-ahb-gates-clk"; 138 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
117 reg = <0x01c20060 0x8>; 139 reg = <0x01c20060 0x8>;
@@ -133,12 +155,13 @@
133 155
134 apb0: apb0@01c20054 { 156 apb0: apb0@01c20054 {
135 #clock-cells = <0>; 157 #clock-cells = <0>;
136 compatible = "allwinner,sun4i-apb0-clk"; 158 compatible = "allwinner,sun4i-a10-apb0-clk";
137 reg = <0x01c20054 0x4>; 159 reg = <0x01c20054 0x4>;
138 clocks = <&ahb>; 160 clocks = <&ahb>;
161 clock-output-names = "apb0";
139 }; 162 };
140 163
141 apb0_gates: apb0_gates@01c20068 { 164 apb0_gates: clk@01c20068 {
142 #clock-cells = <1>; 165 #clock-cells = <1>;
143 compatible = "allwinner,sun7i-a20-apb0-gates-clk"; 166 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
144 reg = <0x01c20068 0x4>; 167 reg = <0x01c20068 0x4>;
@@ -151,19 +174,21 @@
151 174
152 apb1_mux: apb1_mux@01c20058 { 175 apb1_mux: apb1_mux@01c20058 {
153 #clock-cells = <0>; 176 #clock-cells = <0>;
154 compatible = "allwinner,sun4i-apb1-mux-clk"; 177 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
155 reg = <0x01c20058 0x4>; 178 reg = <0x01c20058 0x4>;
156 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 179 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
180 clock-output-names = "apb1_mux";
157 }; 181 };
158 182
159 apb1: apb1@01c20058 { 183 apb1: apb1@01c20058 {
160 #clock-cells = <0>; 184 #clock-cells = <0>;
161 compatible = "allwinner,sun4i-apb1-clk"; 185 compatible = "allwinner,sun4i-a10-apb1-clk";
162 reg = <0x01c20058 0x4>; 186 reg = <0x01c20058 0x4>;
163 clocks = <&apb1_mux>; 187 clocks = <&apb1_mux>;
188 clock-output-names = "apb1";
164 }; 189 };
165 190
166 apb1_gates: apb1_gates@01c2006c { 191 apb1_gates: clk@01c2006c {
167 #clock-cells = <1>; 192 #clock-cells = <1>;
168 compatible = "allwinner,sun7i-a20-apb1-gates-clk"; 193 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
169 reg = <0x01c2006c 0x4>; 194 reg = <0x01c2006c 0x4>;
@@ -178,7 +203,7 @@
178 203
179 nand_clk: clk@01c20080 { 204 nand_clk: clk@01c20080 {
180 #clock-cells = <0>; 205 #clock-cells = <0>;
181 compatible = "allwinner,sun4i-mod0-clk"; 206 compatible = "allwinner,sun4i-a10-mod0-clk";
182 reg = <0x01c20080 0x4>; 207 reg = <0x01c20080 0x4>;
183 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
184 clock-output-names = "nand"; 209 clock-output-names = "nand";
@@ -186,7 +211,7 @@
186 211
187 ms_clk: clk@01c20084 { 212 ms_clk: clk@01c20084 {
188 #clock-cells = <0>; 213 #clock-cells = <0>;
189 compatible = "allwinner,sun4i-mod0-clk"; 214 compatible = "allwinner,sun4i-a10-mod0-clk";
190 reg = <0x01c20084 0x4>; 215 reg = <0x01c20084 0x4>;
191 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
192 clock-output-names = "ms"; 217 clock-output-names = "ms";
@@ -194,7 +219,7 @@
194 219
195 mmc0_clk: clk@01c20088 { 220 mmc0_clk: clk@01c20088 {
196 #clock-cells = <0>; 221 #clock-cells = <0>;
197 compatible = "allwinner,sun4i-mod0-clk"; 222 compatible = "allwinner,sun4i-a10-mod0-clk";
198 reg = <0x01c20088 0x4>; 223 reg = <0x01c20088 0x4>;
199 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
200 clock-output-names = "mmc0"; 225 clock-output-names = "mmc0";
@@ -202,7 +227,7 @@
202 227
203 mmc1_clk: clk@01c2008c { 228 mmc1_clk: clk@01c2008c {
204 #clock-cells = <0>; 229 #clock-cells = <0>;
205 compatible = "allwinner,sun4i-mod0-clk"; 230 compatible = "allwinner,sun4i-a10-mod0-clk";
206 reg = <0x01c2008c 0x4>; 231 reg = <0x01c2008c 0x4>;
207 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
208 clock-output-names = "mmc1"; 233 clock-output-names = "mmc1";
@@ -210,7 +235,7 @@
210 235
211 mmc2_clk: clk@01c20090 { 236 mmc2_clk: clk@01c20090 {
212 #clock-cells = <0>; 237 #clock-cells = <0>;
213 compatible = "allwinner,sun4i-mod0-clk"; 238 compatible = "allwinner,sun4i-a10-mod0-clk";
214 reg = <0x01c20090 0x4>; 239 reg = <0x01c20090 0x4>;
215 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
216 clock-output-names = "mmc2"; 241 clock-output-names = "mmc2";
@@ -218,7 +243,7 @@
218 243
219 mmc3_clk: clk@01c20094 { 244 mmc3_clk: clk@01c20094 {
220 #clock-cells = <0>; 245 #clock-cells = <0>;
221 compatible = "allwinner,sun4i-mod0-clk"; 246 compatible = "allwinner,sun4i-a10-mod0-clk";
222 reg = <0x01c20094 0x4>; 247 reg = <0x01c20094 0x4>;
223 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
224 clock-output-names = "mmc3"; 249 clock-output-names = "mmc3";
@@ -226,7 +251,7 @@
226 251
227 ts_clk: clk@01c20098 { 252 ts_clk: clk@01c20098 {
228 #clock-cells = <0>; 253 #clock-cells = <0>;
229 compatible = "allwinner,sun4i-mod0-clk"; 254 compatible = "allwinner,sun4i-a10-mod0-clk";
230 reg = <0x01c20098 0x4>; 255 reg = <0x01c20098 0x4>;
231 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
232 clock-output-names = "ts"; 257 clock-output-names = "ts";
@@ -234,7 +259,7 @@
234 259
235 ss_clk: clk@01c2009c { 260 ss_clk: clk@01c2009c {
236 #clock-cells = <0>; 261 #clock-cells = <0>;
237 compatible = "allwinner,sun4i-mod0-clk"; 262 compatible = "allwinner,sun4i-a10-mod0-clk";
238 reg = <0x01c2009c 0x4>; 263 reg = <0x01c2009c 0x4>;
239 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 264 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
240 clock-output-names = "ss"; 265 clock-output-names = "ss";
@@ -242,7 +267,7 @@
242 267
243 spi0_clk: clk@01c200a0 { 268 spi0_clk: clk@01c200a0 {
244 #clock-cells = <0>; 269 #clock-cells = <0>;
245 compatible = "allwinner,sun4i-mod0-clk"; 270 compatible = "allwinner,sun4i-a10-mod0-clk";
246 reg = <0x01c200a0 0x4>; 271 reg = <0x01c200a0 0x4>;
247 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
248 clock-output-names = "spi0"; 273 clock-output-names = "spi0";
@@ -250,7 +275,7 @@
250 275
251 spi1_clk: clk@01c200a4 { 276 spi1_clk: clk@01c200a4 {
252 #clock-cells = <0>; 277 #clock-cells = <0>;
253 compatible = "allwinner,sun4i-mod0-clk"; 278 compatible = "allwinner,sun4i-a10-mod0-clk";
254 reg = <0x01c200a4 0x4>; 279 reg = <0x01c200a4 0x4>;
255 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
256 clock-output-names = "spi1"; 281 clock-output-names = "spi1";
@@ -258,7 +283,7 @@
258 283
259 spi2_clk: clk@01c200a8 { 284 spi2_clk: clk@01c200a8 {
260 #clock-cells = <0>; 285 #clock-cells = <0>;
261 compatible = "allwinner,sun4i-mod0-clk"; 286 compatible = "allwinner,sun4i-a10-mod0-clk";
262 reg = <0x01c200a8 0x4>; 287 reg = <0x01c200a8 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264 clock-output-names = "spi2"; 289 clock-output-names = "spi2";
@@ -266,7 +291,7 @@
266 291
267 pata_clk: clk@01c200ac { 292 pata_clk: clk@01c200ac {
268 #clock-cells = <0>; 293 #clock-cells = <0>;
269 compatible = "allwinner,sun4i-mod0-clk"; 294 compatible = "allwinner,sun4i-a10-mod0-clk";
270 reg = <0x01c200ac 0x4>; 295 reg = <0x01c200ac 0x4>;
271 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
272 clock-output-names = "pata"; 297 clock-output-names = "pata";
@@ -274,7 +299,7 @@
274 299
275 ir0_clk: clk@01c200b0 { 300 ir0_clk: clk@01c200b0 {
276 #clock-cells = <0>; 301 #clock-cells = <0>;
277 compatible = "allwinner,sun4i-mod0-clk"; 302 compatible = "allwinner,sun4i-a10-mod0-clk";
278 reg = <0x01c200b0 0x4>; 303 reg = <0x01c200b0 0x4>;
279 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
280 clock-output-names = "ir0"; 305 clock-output-names = "ir0";
@@ -282,15 +307,24 @@
282 307
283 ir1_clk: clk@01c200b4 { 308 ir1_clk: clk@01c200b4 {
284 #clock-cells = <0>; 309 #clock-cells = <0>;
285 compatible = "allwinner,sun4i-mod0-clk"; 310 compatible = "allwinner,sun4i-a10-mod0-clk";
286 reg = <0x01c200b4 0x4>; 311 reg = <0x01c200b4 0x4>;
287 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 312 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
288 clock-output-names = "ir1"; 313 clock-output-names = "ir1";
289 }; 314 };
290 315
316 usb_clk: clk@01c200cc {
317 #clock-cells = <1>;
318 #reset-cells = <1>;
319 compatible = "allwinner,sun4i-a10-usb-clk";
320 reg = <0x01c200cc 0x4>;
321 clocks = <&pll6 1>;
322 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
323 };
324
291 spi3_clk: clk@01c200d4 { 325 spi3_clk: clk@01c200d4 {
292 #clock-cells = <0>; 326 #clock-cells = <0>;
293 compatible = "allwinner,sun4i-mod0-clk"; 327 compatible = "allwinner,sun4i-a10-mod0-clk";
294 reg = <0x01c200d4 0x4>; 328 reg = <0x01c200d4 0x4>;
295 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
296 clock-output-names = "spi3"; 330 clock-output-names = "spi3";
@@ -298,13 +332,41 @@
298 332
299 mbus_clk: clk@01c2015c { 333 mbus_clk: clk@01c2015c {
300 #clock-cells = <0>; 334 #clock-cells = <0>;
301 compatible = "allwinner,sun4i-mod0-clk"; 335 compatible = "allwinner,sun4i-a10-mod0-clk";
302 reg = <0x01c2015c 0x4>; 336 reg = <0x01c2015c 0x4>;
303 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; 337 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
304 clock-output-names = "mbus"; 338 clock-output-names = "mbus";
305 }; 339 };
306 340
307 /* 341 /*
342 * The following two are dummy clocks, placeholders used in the gmac_tx
343 * clock. The gmac driver will choose one parent depending on the PHY
344 * interface mode, using clk_set_rate auto-reparenting.
345 * The actual TX clock rate is not controlled by the gmac_tx clock.
346 */
347 mii_phy_tx_clk: clk@2 {
348 #clock-cells = <0>;
349 compatible = "fixed-clock";
350 clock-frequency = <25000000>;
351 clock-output-names = "mii_phy_tx";
352 };
353
354 gmac_int_tx_clk: clk@3 {
355 #clock-cells = <0>;
356 compatible = "fixed-clock";
357 clock-frequency = <125000000>;
358 clock-output-names = "gmac_int_tx";
359 };
360
361 gmac_tx_clk: clk@01c20164 {
362 #clock-cells = <0>;
363 compatible = "allwinner,sun7i-a20-gmac-clk";
364 reg = <0x01c20164 0x4>;
365 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
366 clock-output-names = "gmac_tx";
367 };
368
369 /*
308 * Dummy clock used by output clocks 370 * Dummy clock used by output clocks
309 */ 371 */
310 osc24M_32k: clk@1 { 372 osc24M_32k: clk@1 {
@@ -347,6 +409,28 @@
347 interrupts = <0 0 4>; 409 interrupts = <0 0 4>;
348 }; 410 };
349 411
412 spi0: spi@01c05000 {
413 compatible = "allwinner,sun4i-a10-spi";
414 reg = <0x01c05000 0x1000>;
415 interrupts = <0 10 4>;
416 clocks = <&ahb_gates 20>, <&spi0_clk>;
417 clock-names = "ahb", "mod";
418 status = "disabled";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 };
422
423 spi1: spi@01c06000 {
424 compatible = "allwinner,sun4i-a10-spi";
425 reg = <0x01c06000 0x1000>;
426 interrupts = <0 11 4>;
427 clocks = <&ahb_gates 21>, <&spi1_clk>;
428 clock-names = "ahb", "mod";
429 status = "disabled";
430 #address-cells = <1>;
431 #size-cells = <0>;
432 };
433
350 emac: ethernet@01c0b000 { 434 emac: ethernet@01c0b000 {
351 compatible = "allwinner,sun4i-a10-emac"; 435 compatible = "allwinner,sun4i-a10-emac";
352 reg = <0x01c0b000 0x1000>; 436 reg = <0x01c0b000 0x1000>;
@@ -363,6 +447,88 @@
363 #size-cells = <0>; 447 #size-cells = <0>;
364 }; 448 };
365 449
450 usbphy: phy@01c13400 {
451 #phy-cells = <1>;
452 compatible = "allwinner,sun7i-a20-usb-phy";
453 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
454 reg-names = "phy_ctrl", "pmu1", "pmu2";
455 clocks = <&usb_clk 8>;
456 clock-names = "usb_phy";
457 resets = <&usb_clk 1>, <&usb_clk 2>;
458 reset-names = "usb1_reset", "usb2_reset";
459 status = "disabled";
460 };
461
462 ehci0: usb@01c14000 {
463 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
464 reg = <0x01c14000 0x100>;
465 interrupts = <0 39 4>;
466 clocks = <&ahb_gates 1>;
467 phys = <&usbphy 1>;
468 phy-names = "usb";
469 status = "disabled";
470 };
471
472 ohci0: usb@01c14400 {
473 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
474 reg = <0x01c14400 0x100>;
475 interrupts = <0 64 4>;
476 clocks = <&usb_clk 6>, <&ahb_gates 2>;
477 phys = <&usbphy 1>;
478 phy-names = "usb";
479 status = "disabled";
480 };
481
482 spi2: spi@01c17000 {
483 compatible = "allwinner,sun4i-a10-spi";
484 reg = <0x01c17000 0x1000>;
485 interrupts = <0 12 4>;
486 clocks = <&ahb_gates 22>, <&spi2_clk>;
487 clock-names = "ahb", "mod";
488 status = "disabled";
489 #address-cells = <1>;
490 #size-cells = <0>;
491 };
492
493 ahci: sata@01c18000 {
494 compatible = "allwinner,sun4i-a10-ahci";
495 reg = <0x01c18000 0x1000>;
496 interrupts = <0 56 4>;
497 clocks = <&pll6 0>, <&ahb_gates 25>;
498 status = "disabled";
499 };
500
501 ehci1: usb@01c1c000 {
502 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
503 reg = <0x01c1c000 0x100>;
504 interrupts = <0 40 4>;
505 clocks = <&ahb_gates 3>;
506 phys = <&usbphy 2>;
507 phy-names = "usb";
508 status = "disabled";
509 };
510
511 ohci1: usb@01c1c400 {
512 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
513 reg = <0x01c1c400 0x100>;
514 interrupts = <0 65 4>;
515 clocks = <&usb_clk 7>, <&ahb_gates 4>;
516 phys = <&usbphy 2>;
517 phy-names = "usb";
518 status = "disabled";
519 };
520
521 spi3: spi@01c1f000 {
522 compatible = "allwinner,sun4i-a10-spi";
523 reg = <0x01c1f000 0x1000>;
524 interrupts = <0 50 4>;
525 clocks = <&ahb_gates 23>, <&spi3_clk>;
526 clock-names = "ahb", "mod";
527 status = "disabled";
528 #address-cells = <1>;
529 #size-cells = <0>;
530 };
531
366 pio: pinctrl@01c20800 { 532 pio: pinctrl@01c20800 {
367 compatible = "allwinner,sun7i-a20-pinctrl"; 533 compatible = "allwinner,sun7i-a20-pinctrl";
368 reg = <0x01c20800 0x400>; 534 reg = <0x01c20800 0x400>;
@@ -381,6 +547,13 @@
381 allwinner,pull = <0>; 547 allwinner,pull = <0>;
382 }; 548 };
383 549
550 uart2_pins_a: uart2@0 {
551 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
552 allwinner,function = "uart2";
553 allwinner,drive = <0>;
554 allwinner,pull = <0>;
555 };
556
384 uart6_pins_a: uart6@0 { 557 uart6_pins_a: uart6@0 {
385 allwinner,pins = "PI12", "PI13"; 558 allwinner,pins = "PI12", "PI13";
386 allwinner,function = "uart6"; 559 allwinner,function = "uart6";
@@ -440,6 +613,46 @@
440 allwinner,drive = <0>; 613 allwinner,drive = <0>;
441 allwinner,pull = <0>; 614 allwinner,pull = <0>;
442 }; 615 };
616
617 gmac_pins_mii_a: gmac_mii@0 {
618 allwinner,pins = "PA0", "PA1", "PA2",
619 "PA3", "PA4", "PA5", "PA6",
620 "PA7", "PA8", "PA9", "PA10",
621 "PA11", "PA12", "PA13", "PA14",
622 "PA15", "PA16";
623 allwinner,function = "gmac";
624 allwinner,drive = <0>;
625 allwinner,pull = <0>;
626 };
627
628 gmac_pins_rgmii_a: gmac_rgmii@0 {
629 allwinner,pins = "PA0", "PA1", "PA2",
630 "PA3", "PA4", "PA5", "PA6",
631 "PA7", "PA8", "PA10",
632 "PA11", "PA12", "PA13",
633 "PA15", "PA16";
634 allwinner,function = "gmac";
635 /*
636 * data lines in RGMII mode use DDR mode
637 * and need a higher signal drive strength
638 */
639 allwinner,drive = <3>;
640 allwinner,pull = <0>;
641 };
642
643 spi1_pins_a: spi1@0 {
644 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
645 allwinner,function = "spi1";
646 allwinner,drive = <0>;
647 allwinner,pull = <0>;
648 };
649
650 spi2_pins_a: spi2@0 {
651 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
652 allwinner,function = "spi2";
653 allwinner,drive = <0>;
654 allwinner,pull = <0>;
655 };
443 }; 656 };
444 657
445 timer@01c20c00 { 658 timer@01c20c00 {
@@ -455,7 +668,7 @@
455 }; 668 };
456 669
457 wdt: watchdog@01c20c90 { 670 wdt: watchdog@01c20c90 {
458 compatible = "allwinner,sun4i-wdt"; 671 compatible = "allwinner,sun4i-a10-wdt";
459 reg = <0x01c20c90 0x10>; 672 reg = <0x01c20c90 0x10>;
460 }; 673 };
461 674
@@ -601,6 +814,21 @@
601 status = "disabled"; 814 status = "disabled";
602 }; 815 };
603 816
817 gmac: ethernet@01c50000 {
818 compatible = "allwinner,sun7i-a20-gmac";
819 reg = <0x01c50000 0x10000>;
820 interrupts = <0 85 4>;
821 interrupt-names = "macirq";
822 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
823 clock-names = "stmmaceth", "allwinner_gmac_tx";
824 snps,pbl = <2>;
825 snps,fixed-burst;
826 snps,force_sf_dma_mode;
827 status = "disabled";
828 #address-cells = <1>;
829 #size-cells = <0>;
830 };
831
604 hstimer@01c60000 { 832 hstimer@01c60000 {
605 compatible = "allwinner,sun7i-a20-hstimer"; 833 compatible = "allwinner,sun7i-a20-hstimer";
606 reg = <0x01c60000 0x1000>; 834 reg = <0x01c60000 0x1000>;
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
new file mode 100644
index 000000000000..18eeac0670b9
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -0,0 +1,75 @@
1/*
2 * sunxi boards common regulator (ahci target power supply, usb-vbus) code
3 *
4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/ {
15 soc@01c00000 {
16 pio: pinctrl@01c20800 {
17 ahci_pwr_pin_a: ahci_pwr_pin@0 {
18 allwinner,pins = "PB8";
19 allwinner,function = "gpio_out";
20 allwinner,drive = <0>;
21 allwinner,pull = <0>;
22 };
23
24 usb1_vbus_pin_a: usb1_vbus_pin@0 {
25 allwinner,pins = "PH6";
26 allwinner,function = "gpio_out";
27 allwinner,drive = <0>;
28 allwinner,pull = <0>;
29 };
30
31 usb2_vbus_pin_a: usb2_vbus_pin@0 {
32 allwinner,pins = "PH3";
33 allwinner,function = "gpio_out";
34 allwinner,drive = <0>;
35 allwinner,pull = <0>;
36 };
37 };
38 };
39
40 reg_ahci_5v: ahci-5v {
41 compatible = "regulator-fixed";
42 pinctrl-names = "default";
43 pinctrl-0 = <&ahci_pwr_pin_a>;
44 regulator-name = "ahci-5v";
45 regulator-min-microvolt = <5000000>;
46 regulator-max-microvolt = <5000000>;
47 enable-active-high;
48 gpio = <&pio 1 8 0>;
49 status = "disabled";
50 };
51
52 reg_usb1_vbus: usb1-vbus {
53 compatible = "regulator-fixed";
54 pinctrl-names = "default";
55 pinctrl-0 = <&usb1_vbus_pin_a>;
56 regulator-name = "usb1-vbus";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 enable-active-high;
60 gpio = <&pio 7 6 0>;
61 status = "disabled";
62 };
63
64 reg_usb2_vbus: usb2-vbus {
65 compatible = "regulator-fixed";
66 pinctrl-names = "default";
67 pinctrl-0 = <&usb2_vbus_pin_a>;
68 regulator-name = "usb2-vbus";
69 regulator-min-microvolt = <5000000>;
70 regulator-max-microvolt = <5000000>;
71 enable-active-high;
72 gpio = <&pio 7 3 0>;
73 status = "disabled";
74 };
75};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 73aecfb57ccb..a288a12823ed 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,3 +1,8 @@
1/*
2 * This dts file supports Dalmore A04.
3 * Other board revisions are not supported
4 */
5
1/dts-v1/; 6/dts-v1/;
2 7
3#include <dt-bindings/input/input.h> 8#include <dt-bindings/input/input.h>
@@ -715,7 +720,6 @@
715 nvidia,pins = "drive_sdio1"; 720 nvidia,pins = "drive_sdio1";
716 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 721 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
717 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 722 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
718 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
719 nvidia,pull-down-strength = <36>; 723 nvidia,pull-down-strength = <36>;
720 nvidia,pull-up-strength = <20>; 724 nvidia,pull-up-strength = <20>;
721 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; 725 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
@@ -725,7 +729,6 @@
725 nvidia,pins = "drive_sdio3"; 729 nvidia,pins = "drive_sdio3";
726 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 730 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
727 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 731 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
728 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
729 nvidia,pull-down-strength = <22>; 732 nvidia,pull-down-strength = <22>;
730 nvidia,pull-up-strength = <36>; 733 nvidia,pull-up-strength = <36>;
731 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 734 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
@@ -735,12 +738,10 @@
735 nvidia,pins = "drive_gma"; 738 nvidia,pins = "drive_gma";
736 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 739 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
737 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 740 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
738 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
739 nvidia,pull-down-strength = <2>; 741 nvidia,pull-down-strength = <2>;
740 nvidia,pull-up-strength = <1>; 742 nvidia,pull-up-strength = <1>;
741 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 743 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
742 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 744 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
743 nvidia,drive-type = <1>;
744 }; 745 };
745 }; 746 };
746 }; 747 };
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 44ec401ec366..fdc559ab2db3 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -604,7 +604,7 @@
604 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 604 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
605 resets = <&tegra_car 14>; 605 resets = <&tegra_car 14>;
606 reset-names = "sdhci"; 606 reset-names = "sdhci";
607 status = "disable"; 607 status = "disabled";
608 }; 608 };
609 609
610 sdhci@78000200 { 610 sdhci@78000200 {
@@ -614,7 +614,7 @@
614 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; 614 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
615 resets = <&tegra_car 9>; 615 resets = <&tegra_car 9>;
616 reset-names = "sdhci"; 616 reset-names = "sdhci";
617 status = "disable"; 617 status = "disabled";
618 }; 618 };
619 619
620 sdhci@78000400 { 620 sdhci@78000400 {
@@ -624,7 +624,7 @@
624 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; 624 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
625 resets = <&tegra_car 69>; 625 resets = <&tegra_car 69>;
626 reset-names = "sdhci"; 626 reset-names = "sdhci";
627 status = "disable"; 627 status = "disabled";
628 }; 628 };
629 629
630 sdhci@78000600 { 630 sdhci@78000600 {
@@ -634,7 +634,7 @@
634 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; 634 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
635 resets = <&tegra_car 15>; 635 resets = <&tegra_car 15>;
636 reset-names = "sdhci"; 636 reset-names = "sdhci";
637 status = "disable"; 637 status = "disabled";
638 }; 638 };
639 639
640 usb@7d000000 { 640 usb@7d000000 {
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index c6dcef513e5d..c17283c04598 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -8,15 +8,29 @@
8 compatible = "nvidia,venice2", "nvidia,tegra124"; 8 compatible = "nvidia,venice2", "nvidia,tegra124";
9 9
10 aliases { 10 aliases {
11 rtc0 = "/i2c@7000d000/as3722@40"; 11 rtc0 = "/i2c@0,7000d000/pmic@40";
12 rtc1 = "/rtc@7000e000"; 12 rtc1 = "/rtc@0,7000e000";
13 }; 13 };
14 14
15 memory { 15 memory {
16 reg = <0x80000000 0x80000000>; 16 reg = <0x0 0x80000000 0x0 0x80000000>;
17 }; 17 };
18 18
19 pinmux: pinmux@70000868 { 19 host1x@0,50000000 {
20 sor@0,54540000 {
21 status = "okay";
22
23 nvidia,dpaux = <&dpaux>;
24 nvidia,panel = <&panel>;
25 };
26
27 dpaux: dpaux@0,545c0000 {
28 vdd-supply = <&vdd_3v3_panel>;
29 status = "okay";
30 };
31 };
32
33 pinmux: pinmux@0,70000868 {
20 pinctrl-names = "default"; 34 pinctrl-names = "default";
21 pinctrl-0 = <&pinmux_default>; 35 pinctrl-0 = <&pinmux_default>;
22 36
@@ -138,14 +152,9 @@
138 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 152 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
139 }; 153 };
140 sdmmc1_clk_pz0 { 154 sdmmc1_clk_pz0 {
141 nvidia,pins = "sdmmc1_clk_pz0", 155 nvidia,pins = "sdmmc1_clk_pz0";
142 "sdmmc1_cmd_pz1",
143 "sdmmc1_dat0_py7",
144 "sdmmc1_dat1_py6",
145 "sdmmc1_dat2_py5",
146 "sdmmc1_dat3_py4";
147 nvidia,function = "sdmmc1"; 156 nvidia,function = "sdmmc1";
148 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 157 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
149 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 158 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
150 nvidia,tristate = <TEGRA_PIN_DISABLE>; 159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
151 }; 160 };
@@ -402,19 +411,11 @@
402 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 411 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
403 }; 412 };
404 usb_vbus_en0_pn4 { 413 usb_vbus_en0_pn4 {
405 nvidia,pins = "usb_vbus_en0_pn4"; 414 nvidia,pins = "usb_vbus_en0_pn4",
415 "usb_vbus_en1_pn5";
406 nvidia,function = "usb"; 416 nvidia,function = "usb";
407 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 417 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
408 nvidia,pull = <TEGRA_PIN_PULL_UP>; 418 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
409 nvidia,tristate = <TEGRA_PIN_DISABLE>;
410 nvidia,lock = <TEGRA_PIN_DISABLE>;
411 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
412 };
413 usb_vbus_en1_pn5 {
414 nvidia,pins = "usb_vbus_en1_pn5";
415 nvidia,function = "usb";
416 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
417 nvidia,pull = <TEGRA_PIN_PULL_UP>;
418 nvidia,tristate = <TEGRA_PIN_DISABLE>; 419 nvidia,tristate = <TEGRA_PIN_DISABLE>;
419 nvidia,lock = <TEGRA_PIN_DISABLE>; 420 nvidia,lock = <TEGRA_PIN_DISABLE>;
420 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 421 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
@@ -423,7 +424,6 @@
423 nvidia,pins = "drive_sdio1"; 424 nvidia,pins = "drive_sdio1";
424 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 425 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
425 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 426 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
426 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
427 nvidia,pull-down-strength = <32>; 427 nvidia,pull-down-strength = <32>;
428 nvidia,pull-up-strength = <42>; 428 nvidia,pull-up-strength = <42>;
429 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 429 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
@@ -433,7 +433,6 @@
433 nvidia,pins = "drive_sdio3"; 433 nvidia,pins = "drive_sdio3";
434 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 434 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
435 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 435 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
436 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
437 nvidia,pull-down-strength = <20>; 436 nvidia,pull-down-strength = <20>;
438 nvidia,pull-up-strength = <36>; 437 nvidia,pull-up-strength = <36>;
439 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 438 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
@@ -572,15 +571,15 @@
572 }; 571 };
573 }; 572 };
574 573
575 serial@70006000 { 574 serial@0,70006000 {
576 status = "okay"; 575 status = "okay";
577 }; 576 };
578 577
579 pwm: pwm@7000a000 { 578 pwm: pwm@0,7000a000 {
580 status = "okay"; 579 status = "okay";
581 }; 580 };
582 581
583 i2c@7000c000 { 582 i2c@0,7000c000 {
584 status = "okay"; 583 status = "okay";
585 clock-frequency = <100000>; 584 clock-frequency = <100000>;
586 585
@@ -592,30 +591,32 @@
592 }; 591 };
593 }; 592 };
594 593
595 i2c@7000c400 { 594 i2c@0,7000c400 {
596 status = "okay"; 595 status = "okay";
597 clock-frequency = <100000>; 596 clock-frequency = <100000>;
598 }; 597 };
599 598
600 i2c@7000c500 { 599 i2c@0,7000c500 {
601 status = "okay"; 600 status = "okay";
602 clock-frequency = <100000>; 601 clock-frequency = <100000>;
603 }; 602 };
604 603
605 i2c@7000c700 { 604 i2c@0,7000c700 {
606 status = "okay"; 605 status = "okay";
607 clock-frequency = <100000>; 606 clock-frequency = <100000>;
608 }; 607 };
609 608
610 i2c@7000d000 { 609 i2c@0,7000d000 {
611 status = "okay"; 610 status = "okay";
612 clock-frequency = <400000>; 611 clock-frequency = <400000>;
613 612
614 as3722: as3722@40 { 613 pmic: pmic@40 {
615 compatible = "ams,as3722"; 614 compatible = "ams,as3722";
616 reg = <0x40>; 615 reg = <0x40>;
617 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 616 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
618 617
618 ams,system-power-controller;
619
619 #interrupt-cells = <2>; 620 #interrupt-cells = <2>;
620 interrupt-controller; 621 interrupt-controller;
621 622
@@ -650,19 +651,19 @@
650 }; 651 };
651 652
652 regulators { 653 regulators {
653 vsup-sd2-supply = <&vdd_ac_bat_reg>; 654 vsup-sd2-supply = <&vdd_5v0_sys>;
654 vsup-sd3-supply = <&vdd_ac_bat_reg>; 655 vsup-sd3-supply = <&vdd_5v0_sys>;
655 vsup-sd4-supply = <&vdd_ac_bat_reg>; 656 vsup-sd4-supply = <&vdd_5v0_sys>;
656 vsup-sd5-supply = <&vdd_ac_bat_reg>; 657 vsup-sd5-supply = <&vdd_5v0_sys>;
657 vin-ldo0-supply = <&as3722_sd2>; 658 vin-ldo0-supply = <&vdd_1v35_lp0>;
658 vin-ldo1-6-supply = <&vdd_ac_bat_reg>; 659 vin-ldo1-6-supply = <&vdd_3v3_run>;
659 vin-ldo2-5-7-supply = <&as3722_sd5>; 660 vin-ldo2-5-7-supply = <&vddio_1v8>;
660 vin-ldo3-4-supply = <&vdd_ac_bat_reg>; 661 vin-ldo3-4-supply = <&vdd_3v3_sys>;
661 vin-ldo9-10-supply = <&vdd_ac_bat_reg>; 662 vin-ldo9-10-supply = <&vdd_5v0_sys>;
662 vin-ldo11-supply = <&vdd_ac_bat_reg>; 663 vin-ldo11-supply = <&vdd_3v3_run>;
663 664
664 sd0 { 665 sd0 {
665 regulator-name = "vdd-cpu"; 666 regulator-name = "+VDD_CPU_AP";
666 regulator-min-microvolt = <700000>; 667 regulator-min-microvolt = <700000>;
667 regulator-max-microvolt = <1400000>; 668 regulator-max-microvolt = <1400000>;
668 regulator-min-microamp = <3500000>; 669 regulator-min-microamp = <3500000>;
@@ -673,7 +674,7 @@
673 }; 674 };
674 675
675 sd1 { 676 sd1 {
676 regulator-name = "vdd-core"; 677 regulator-name = "+VDD_CORE";
677 regulator-min-microvolt = <700000>; 678 regulator-min-microvolt = <700000>;
678 regulator-max-microvolt = <1350000>; 679 regulator-max-microvolt = <1350000>;
679 regulator-min-microamp = <2500000>; 680 regulator-min-microamp = <2500000>;
@@ -683,8 +684,8 @@
683 ams,external-control = <1>; 684 ams,external-control = <1>;
684 }; 685 };
685 686
686 as3722_sd2: sd2 { 687 vdd_1v35_lp0: sd2 {
687 regulator-name = "vddio-ddr"; 688 regulator-name = "+1.35V_LP0(sd2)";
688 regulator-min-microvolt = <1350000>; 689 regulator-min-microvolt = <1350000>;
689 regulator-max-microvolt = <1350000>; 690 regulator-max-microvolt = <1350000>;
690 regulator-always-on; 691 regulator-always-on;
@@ -692,7 +693,7 @@
692 }; 693 };
693 694
694 sd3 { 695 sd3 {
695 regulator-name = "vddio-ddr-2phase"; 696 regulator-name = "+1.35V_LP0(sd3)";
696 regulator-min-microvolt = <1350000>; 697 regulator-min-microvolt = <1350000>;
697 regulator-max-microvolt = <1350000>; 698 regulator-max-microvolt = <1350000>;
698 regulator-always-on; 699 regulator-always-on;
@@ -700,15 +701,13 @@
700 }; 701 };
701 702
702 sd4 { 703 sd4 {
703 regulator-name = "avdd-pex-sata"; 704 regulator-name = "+1.05V_RUN";
704 regulator-min-microvolt = <1050000>; 705 regulator-min-microvolt = <1050000>;
705 regulator-max-microvolt = <1050000>; 706 regulator-max-microvolt = <1050000>;
706 regulator-boot-on;
707 regulator-always-on;
708 }; 707 };
709 708
710 as3722_sd5: sd5 { 709 vddio_1v8: sd5 {
711 regulator-name = "vddio-sys"; 710 regulator-name = "+1.8V_VDDIO";
712 regulator-min-microvolt = <1800000>; 711 regulator-min-microvolt = <1800000>;
713 regulator-max-microvolt = <1800000>; 712 regulator-max-microvolt = <1800000>;
714 regulator-boot-on; 713 regulator-boot-on;
@@ -716,7 +715,7 @@
716 }; 715 };
717 716
718 sd6 { 717 sd6 {
719 regulator-name = "vdd-gpu"; 718 regulator-name = "+VDD_GPU_AP";
720 regulator-min-microvolt = <650000>; 719 regulator-min-microvolt = <650000>;
721 regulator-max-microvolt = <1200000>; 720 regulator-max-microvolt = <1200000>;
722 regulator-min-microamp = <3500000>; 721 regulator-min-microamp = <3500000>;
@@ -726,7 +725,7 @@
726 }; 725 };
727 726
728 ldo0 { 727 ldo0 {
729 regulator-name = "avdd_pll"; 728 regulator-name = "+1.05V_RUN_AVDD";
730 regulator-min-microvolt = <1050000>; 729 regulator-min-microvolt = <1050000>;
731 regulator-max-microvolt = <1050000>; 730 regulator-max-microvolt = <1050000>;
732 regulator-boot-on; 731 regulator-boot-on;
@@ -735,13 +734,13 @@
735 }; 734 };
736 735
737 ldo1 { 736 ldo1 {
738 regulator-name = "run-cam-1.8"; 737 regulator-name = "+1.8V_RUN_CAM";
739 regulator-min-microvolt = <1800000>; 738 regulator-min-microvolt = <1800000>;
740 regulator-max-microvolt = <1800000>; 739 regulator-max-microvolt = <1800000>;
741 }; 740 };
742 741
743 ldo2 { 742 ldo2 {
744 regulator-name = "gen-avdd,vddio-hsic"; 743 regulator-name = "+1.2V_GEN_AVDD";
745 regulator-min-microvolt = <1200000>; 744 regulator-min-microvolt = <1200000>;
746 regulator-max-microvolt = <1200000>; 745 regulator-max-microvolt = <1200000>;
747 regulator-boot-on; 746 regulator-boot-on;
@@ -749,7 +748,7 @@
749 }; 748 };
750 749
751 ldo3 { 750 ldo3 {
752 regulator-name = "vdd-rtc"; 751 regulator-name = "+1.00V_LP0_VDD_RTC";
753 regulator-min-microvolt = <1000000>; 752 regulator-min-microvolt = <1000000>;
754 regulator-max-microvolt = <1000000>; 753 regulator-max-microvolt = <1000000>;
755 regulator-boot-on; 754 regulator-boot-on;
@@ -757,48 +756,44 @@
757 ams,enable-tracking; 756 ams,enable-tracking;
758 }; 757 };
759 758
760 ldo4 { 759 vdd_run_cam: ldo4 {
761 regulator-name = "vdd-cam"; 760 regulator-name = "+3.3V_RUN_CAM";
762 regulator-min-microvolt = <2800000>; 761 regulator-min-microvolt = <2800000>;
763 regulator-max-microvolt = <2800000>; 762 regulator-max-microvolt = <2800000>;
764 regulator-boot-on;
765 regulator-always-on;
766 }; 763 };
767 764
768 ldo5 { 765 ldo5 {
769 regulator-name = "vdd-cam-front"; 766 regulator-name = "+1.2V_RUN_CAM_FRONT";
770 regulator-min-microvolt = <1200000>; 767 regulator-min-microvolt = <1200000>;
771 regulator-max-microvolt = <1200000>; 768 regulator-max-microvolt = <1200000>;
772 }; 769 };
773 770
774 ldo6 { 771 vddio_sdmmc3: ldo6 {
775 regulator-name = "vddio-sdmmc3"; 772 regulator-name = "+VDDIO_SDMMC3";
776 regulator-min-microvolt = <1800000>; 773 regulator-min-microvolt = <1800000>;
777 regulator-max-microvolt = <3300000>; 774 regulator-max-microvolt = <3300000>;
778 regulator-boot-on;
779 regulator-always-on;
780 }; 775 };
781 776
782 ldo7 { 777 ldo7 {
783 regulator-name = "vdd-cam-rear"; 778 regulator-name = "+1.05V_RUN_CAM_REAR";
784 regulator-min-microvolt = <1050000>; 779 regulator-min-microvolt = <1050000>;
785 regulator-max-microvolt = <1050000>; 780 regulator-max-microvolt = <1050000>;
786 }; 781 };
787 782
788 ldo9 { 783 ldo9 {
789 regulator-name = "vdd-touch"; 784 regulator-name = "+2.8V_RUN_TOUCH";
790 regulator-min-microvolt = <2800000>; 785 regulator-min-microvolt = <2800000>;
791 regulator-max-microvolt = <2800000>; 786 regulator-max-microvolt = <2800000>;
792 }; 787 };
793 788
794 ldo10 { 789 ldo10 {
795 regulator-name = "vdd-cam-af"; 790 regulator-name = "+2.8V_RUN_CAM_AF";
796 regulator-min-microvolt = <2800000>; 791 regulator-min-microvolt = <2800000>;
797 regulator-max-microvolt = <2800000>; 792 regulator-max-microvolt = <2800000>;
798 }; 793 };
799 794
800 ldo11 { 795 ldo11 {
801 regulator-name = "vpp-fuse"; 796 regulator-name = "+1.8V_RUN_VPP_FUSE";
802 regulator-min-microvolt = <1800000>; 797 regulator-min-microvolt = <1800000>;
803 regulator-max-microvolt = <1800000>; 798 regulator-max-microvolt = <1800000>;
804 }; 799 };
@@ -806,7 +801,7 @@
806 }; 801 };
807 }; 802 };
808 803
809 spi@7000d400 { 804 spi@0,7000d400 {
810 status = "okay"; 805 status = "okay";
811 806
812 cros-ec@0 { 807 cros-ec@0 {
@@ -912,7 +907,17 @@
912 }; 907 };
913 }; 908 };
914 909
915 pmc@7000e400 { 910 spi@0,7000da00 {
911 status = "okay";
912 spi-max-frequency = <25000000>;
913 spi-flash@0 {
914 compatible = "winbond,w25q32dw";
915 reg = <0>;
916 spi-max-frequency = <20000000>;
917 };
918 };
919
920 pmc@0,7000e400 {
916 nvidia,invert-interrupt; 921 nvidia,invert-interrupt;
917 nvidia,suspend-mode = <1>; 922 nvidia,suspend-mode = <1>;
918 nvidia,cpu-pwr-good-time = <500>; 923 nvidia,cpu-pwr-good-time = <500>;
@@ -923,24 +928,63 @@
923 nvidia,sys-clock-req-active-high; 928 nvidia,sys-clock-req-active-high;
924 }; 929 };
925 930
926 sdhci@700b0400 { 931 sdhci@0,700b0400 {
927 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 932 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
928 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 933 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
929 status = "okay"; 934 status = "okay";
930 bus-width = <4>; 935 bus-width = <4>;
936 vmmc-supply = <&vddio_sdmmc3>;
931 }; 937 };
932 938
933 sdhci@700b0600 { 939 sdhci@0,700b0600 {
934 status = "okay"; 940 status = "okay";
935 bus-width = <8>; 941 bus-width = <8>;
936 }; 942 };
937 943
938 ahub@70300000 { 944 ahub@0,70300000 {
939 i2s@70301100 { 945 i2s@0,70301100 {
940 status = "okay"; 946 status = "okay";
941 }; 947 };
942 }; 948 };
943 949
950 usb@0,7d000000 {
951 status = "okay";
952 };
953
954 usb-phy@0,7d000000 {
955 status = "okay";
956 vbus-supply = <&vdd_usb1_vbus>;
957 };
958
959 usb@0,7d004000 {
960 status = "okay";
961 };
962
963 usb-phy@0,7d004000 {
964 status = "okay";
965 vbus-supply = <&vdd_run_cam>;
966 };
967
968 usb@0,7d008000 {
969 status = "okay";
970 };
971
972 usb-phy@0,7d008000 {
973 status = "okay";
974 vbus-supply = <&vdd_usb3_vbus>;
975 };
976
977 backlight: backlight {
978 compatible = "pwm-backlight";
979
980 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
981 power-supply = <&vdd_led>;
982 pwms = <&pwm 1 1000000>;
983
984 brightness-levels = <0 4 8 16 32 64 128 255>;
985 default-brightness-level = <6>;
986 };
987
944 clocks { 988 clocks {
945 compatible = "simple-bus"; 989 compatible = "simple-bus";
946 #address-cells = <1>; 990 #address-cells = <1>;
@@ -948,7 +992,7 @@
948 992
949 clk32k_in: clock@0 { 993 clk32k_in: clock@0 {
950 compatible = "fixed-clock"; 994 compatible = "fixed-clock";
951 reg=<0>; 995 reg = <0>;
952 #clock-cells = <0>; 996 #clock-cells = <0>;
953 clock-frequency = <32768>; 997 clock-frequency = <32768>;
954 }; 998 };
@@ -966,104 +1010,140 @@
966 }; 1010 };
967 }; 1011 };
968 1012
1013 panel: panel {
1014 compatible = "lg,lp129qe", "simple-panel";
1015
1016 backlight = <&backlight>;
1017 ddc-i2c-bus = <&dpaux>;
1018 };
1019
969 regulators { 1020 regulators {
970 compatible = "simple-bus"; 1021 compatible = "simple-bus";
971 #address-cells = <1>; 1022 #address-cells = <1>;
972 #size-cells = <0>; 1023 #size-cells = <0>;
973 1024
974 vdd_ac_bat_reg: regulator@0 { 1025 vdd_mux: regulator@0 {
975 compatible = "regulator-fixed"; 1026 compatible = "regulator-fixed";
976 reg = <0>; 1027 reg = <0>;
977 regulator-name = "vdd_ac_bat"; 1028 regulator-name = "+VDD_MUX";
978 regulator-min-microvolt = <5000000>; 1029 regulator-min-microvolt = <12000000>;
979 regulator-max-microvolt = <5000000>; 1030 regulator-max-microvolt = <12000000>;
980 regulator-always-on; 1031 regulator-always-on;
1032 regulator-boot-on;
981 }; 1033 };
982 1034
983 vdd_3v3_reg: regulator@1 { 1035 vdd_5v0_sys: regulator@1 {
984 compatible = "regulator-fixed"; 1036 compatible = "regulator-fixed";
985 reg = <1>; 1037 reg = <1>;
986 regulator-name = "vdd_3v3"; 1038 regulator-name = "+5V_SYS";
987 regulator-min-microvolt = <3300000>; 1039 regulator-min-microvolt = <5000000>;
988 regulator-max-microvolt = <3300000>; 1040 regulator-max-microvolt = <5000000>;
989 regulator-always-on; 1041 regulator-always-on;
990 regulator-boot-on; 1042 regulator-boot-on;
991 enable-active-high; 1043 vin-supply = <&vdd_mux>;
992 gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
993 }; 1044 };
994 1045
995 vdd_3v3_modem_reg: regulator@2 { 1046 vdd_3v3_sys: regulator@2 {
996 compatible = "regulator-fixed"; 1047 compatible = "regulator-fixed";
997 reg = <2>; 1048 reg = <2>;
998 regulator-name = "vdd-modem-3v3"; 1049 regulator-name = "+3.3V_SYS";
999 regulator-min-microvolt = <3300000>; 1050 regulator-min-microvolt = <3300000>;
1000 regulator-max-microvolt = <3300000>; 1051 regulator-max-microvolt = <3300000>;
1001 enable-active-high; 1052 regulator-always-on;
1002 gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; 1053 regulator-boot-on;
1054 vin-supply = <&vdd_mux>;
1003 }; 1055 };
1004 1056
1005 vdd_hdmi_5v0_reg: regulator@3 { 1057 vdd_3v3_run: regulator@3 {
1006 compatible = "regulator-fixed"; 1058 compatible = "regulator-fixed";
1007 reg = <3>; 1059 reg = <3>;
1008 regulator-name = "vdd-hdmi-5v0"; 1060 regulator-name = "+3.3V_RUN";
1009 regulator-min-microvolt = <5000000>; 1061 regulator-min-microvolt = <3300000>;
1010 regulator-max-microvolt = <5000000>; 1062 regulator-max-microvolt = <3300000>;
1063 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
1011 enable-active-high; 1064 enable-active-high;
1012 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; 1065 vin-supply = <&vdd_3v3_sys>;
1013 }; 1066 };
1014 1067
1015 vdd_bl_reg: regulator@4 { 1068 vdd_3v3_hdmi: regulator@4 {
1016 compatible = "regulator-fixed"; 1069 compatible = "regulator-fixed";
1017 reg = <4>; 1070 reg = <4>;
1018 regulator-name = "vdd-bl"; 1071 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
1019 regulator-min-microvolt = <3300000>; 1072 regulator-min-microvolt = <3300000>;
1020 regulator-max-microvolt = <3300000>; 1073 regulator-max-microvolt = <3300000>;
1021 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>; 1074 vin-supply = <&vdd_3v3_run>;
1022 }; 1075 };
1023 1076
1024 vdd_ts_sw_5v0: regulator@5 { 1077 vdd_led: regulator@5 {
1025 compatible = "regulator-fixed"; 1078 compatible = "regulator-fixed";
1026 reg = <5>; 1079 reg = <5>;
1027 regulator-name = "vdd_ts_sw"; 1080 regulator-name = "+VDD_LED";
1028 regulator-min-microvolt = <5000000>; 1081 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1029 regulator-max-microvolt = <5000000>;
1030 enable-active-high; 1082 enable-active-high;
1031 regulator-boot-on; 1083 vin-supply = <&vdd_mux>;
1032 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>;
1033 }; 1084 };
1034 1085
1035 usb1_vbus_reg: regulator@6 { 1086 vdd_5v0_ts: regulator@6 {
1036 compatible = "regulator-fixed"; 1087 compatible = "regulator-fixed";
1037 reg = <6>; 1088 reg = <6>;
1038 regulator-name = "usb1_vbus"; 1089 regulator-name = "+5V_VDD_TS_SW";
1039 regulator-min-microvolt = <5000000>; 1090 regulator-min-microvolt = <5000000>;
1040 regulator-max-microvolt = <5000000>; 1091 regulator-max-microvolt = <5000000>;
1041 regulator-boot-on; 1092 regulator-boot-on;
1093 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
1042 enable-active-high; 1094 enable-active-high;
1043 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; 1095 vin-supply = <&vdd_5v0_sys>;
1044 gpio-open-drain;
1045 }; 1096 };
1046 1097
1047 usb3_vbus_reg: regulator@7 { 1098 vdd_usb1_vbus: regulator@7 {
1048 compatible = "regulator-fixed"; 1099 compatible = "regulator-fixed";
1049 reg = <7>; 1100 reg = <7>;
1050 regulator-name = "usb3_vbus"; 1101 regulator-name = "+5V_USB_HS";
1051 regulator-min-microvolt = <5000000>; 1102 regulator-min-microvolt = <5000000>;
1052 regulator-max-microvolt = <5000000>; 1103 regulator-max-microvolt = <5000000>;
1053 regulator-boot-on; 1104 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1054 enable-active-high; 1105 enable-active-high;
1055 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1056 gpio-open-drain; 1106 gpio-open-drain;
1107 vin-supply = <&vdd_5v0_sys>;
1057 }; 1108 };
1058 1109
1059 panel_3v3_reg: regulator@8 { 1110 vdd_usb3_vbus: regulator@8 {
1060 compatible = "regulator-fixed"; 1111 compatible = "regulator-fixed";
1061 reg = <8>; 1112 reg = <8>;
1062 regulator-name = "panel_3v3"; 1113 regulator-name = "+5V_USB_SS";
1114 regulator-min-microvolt = <5000000>;
1115 regulator-max-microvolt = <5000000>;
1116 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1117 enable-active-high;
1118 gpio-open-drain;
1119 vin-supply = <&vdd_5v0_sys>;
1120 };
1121
1122 vdd_3v3_panel: regulator@9 {
1123 compatible = "regulator-fixed";
1124 reg = <9>;
1125 regulator-name = "+3.3V_PANEL";
1126 regulator-min-microvolt = <3300000>;
1127 regulator-max-microvolt = <3300000>;
1128 gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
1129 enable-active-high;
1130 vin-supply = <&vdd_3v3_run>;
1131 };
1132
1133 vdd_3v3_lp0: regulator@10 {
1134 compatible = "regulator-fixed";
1135 reg = <10>;
1136 regulator-name = "+3.3V_LP0";
1063 regulator-min-microvolt = <3300000>; 1137 regulator-min-microvolt = <3300000>;
1064 regulator-max-microvolt = <3300000>; 1138 regulator-max-microvolt = <3300000>;
1139 /*
1140 * TODO: find a way to wire this up with the USB EHCI
1141 * controllers so that it can be enabled on demand.
1142 */
1143 regulator-always-on;
1144 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1065 enable-active-high; 1145 enable-active-high;
1066 gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; 1146 vin-supply = <&vdd_3v3_sys>;
1067 }; 1147 };
1068 }; 1148 };
1069 1149
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index ec0698a8354a..cf45a1a39483 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -8,22 +8,91 @@
8/ { 8/ {
9 compatible = "nvidia,tegra124"; 9 compatible = "nvidia,tegra124";
10 interrupt-parent = <&gic>; 10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 host1x@0,50000000 {
15 compatible = "nvidia,tegra124-host1x", "simple-bus";
16 reg = <0x0 0x50000000 0x0 0x00034000>;
17 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
18 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
19 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
20 resets = <&tegra_car 28>;
21 reset-names = "host1x";
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
27
28 dc@0,54200000 {
29 compatible = "nvidia,tegra124-dc";
30 reg = <0x0 0x54200000 0x0 0x00040000>;
31 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
33 <&tegra_car TEGRA124_CLK_PLL_P>;
34 clock-names = "dc", "parent";
35 resets = <&tegra_car 27>;
36 reset-names = "dc";
37
38 nvidia,head = <0>;
39 };
40
41 dc@0,54240000 {
42 compatible = "nvidia,tegra124-dc";
43 reg = <0x0 0x54240000 0x0 0x00040000>;
44 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
45 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
46 <&tegra_car TEGRA124_CLK_PLL_P>;
47 clock-names = "dc", "parent";
48 resets = <&tegra_car 26>;
49 reset-names = "dc";
50
51 nvidia,head = <1>;
52 };
11 53
12 gic: interrupt-controller@50041000 { 54 sor@0,54540000 {
55 compatible = "nvidia,tegra124-sor";
56 reg = <0x0 0x54540000 0x0 0x00040000>;
57 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
59 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
60 <&tegra_car TEGRA124_CLK_PLL_DP>,
61 <&tegra_car TEGRA124_CLK_CLK_M>;
62 clock-names = "sor", "parent", "dp", "safe";
63 resets = <&tegra_car 182>;
64 reset-names = "sor";
65 status = "disabled";
66 };
67
68 dpaux@0,545c0000 {
69 compatible = "nvidia,tegra124-dpaux";
70 reg = <0x0 0x545c0000 0x0 0x00040000>;
71 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
72 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
73 <&tegra_car TEGRA124_CLK_PLL_DP>;
74 clock-names = "dpaux", "parent";
75 resets = <&tegra_car 181>;
76 reset-names = "dpaux";
77 status = "disabled";
78 };
79 };
80
81 gic: interrupt-controller@0,50041000 {
13 compatible = "arm,cortex-a15-gic"; 82 compatible = "arm,cortex-a15-gic";
14 #interrupt-cells = <3>; 83 #interrupt-cells = <3>;
15 interrupt-controller; 84 interrupt-controller;
16 reg = <0x50041000 0x1000>, 85 reg = <0x0 0x50041000 0x0 0x1000>,
17 <0x50042000 0x1000>, 86 <0x0 0x50042000 0x0 0x1000>,
18 <0x50044000 0x2000>, 87 <0x0 0x50044000 0x0 0x2000>,
19 <0x50046000 0x2000>; 88 <0x0 0x50046000 0x0 0x2000>;
20 interrupts = <GIC_PPI 9 89 interrupts = <GIC_PPI 9
21 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 90 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
22 }; 91 };
23 92
24 timer@60005000 { 93 timer@0,60005000 {
25 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 94 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
26 reg = <0x60005000 0x400>; 95 reg = <0x0 0x60005000 0x0 0x400>;
27 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 96 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
28 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -33,16 +102,16 @@
33 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 102 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
34 }; 103 };
35 104
36 tegra_car: clock@60006000 { 105 tegra_car: clock@0,60006000 {
37 compatible = "nvidia,tegra124-car"; 106 compatible = "nvidia,tegra124-car";
38 reg = <0x60006000 0x1000>; 107 reg = <0x0 0x60006000 0x0 0x1000>;
39 #clock-cells = <1>; 108 #clock-cells = <1>;
40 #reset-cells = <1>; 109 #reset-cells = <1>;
41 }; 110 };
42 111
43 gpio: gpio@6000d000 { 112 gpio: gpio@0,6000d000 {
44 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 113 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
45 reg = <0x6000d000 0x1000>; 114 reg = <0x0 0x6000d000 0x0 0x1000>;
46 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 115 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
@@ -57,9 +126,9 @@
57 interrupt-controller; 126 interrupt-controller;
58 }; 127 };
59 128
60 apbdma: dma@60020000 { 129 apbdma: dma@0,60020000 {
61 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 130 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
62 reg = <0x60020000 0x1400>; 131 reg = <0x0 0x60020000 0x0 0x1400>;
63 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 132 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
@@ -98,10 +167,10 @@
98 #dma-cells = <1>; 167 #dma-cells = <1>;
99 }; 168 };
100 169
101 pinmux: pinmux@70000868 { 170 pinmux: pinmux@0,70000868 {
102 compatible = "nvidia,tegra124-pinmux"; 171 compatible = "nvidia,tegra124-pinmux";
103 reg = <0x70000868 0x164>, /* Pad control registers */ 172 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
104 <0x70003000 0x434>; /* Mux registers */ 173 <0x0 0x70003000 0x0 0x434>; /* Mux registers */
105 }; 174 };
106 175
107 /* 176 /*
@@ -112,9 +181,9 @@
112 * the APB DMA based serial driver, the comptible is 181 * the APB DMA based serial driver, the comptible is
113 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 182 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
114 */ 183 */
115 serial@70006000 { 184 serial@0,70006000 {
116 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 185 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
117 reg = <0x70006000 0x40>; 186 reg = <0x0 0x70006000 0x0 0x40>;
118 reg-shift = <2>; 187 reg-shift = <2>;
119 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 188 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 189 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
@@ -125,9 +194,9 @@
125 status = "disabled"; 194 status = "disabled";
126 }; 195 };
127 196
128 serial@70006040 { 197 serial@0,70006040 {
129 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 198 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
130 reg = <0x70006040 0x40>; 199 reg = <0x0 0x70006040 0x0 0x40>;
131 reg-shift = <2>; 200 reg-shift = <2>;
132 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 201 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 202 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
@@ -138,9 +207,9 @@
138 status = "disabled"; 207 status = "disabled";
139 }; 208 };
140 209
141 serial@70006200 { 210 serial@0,70006200 {
142 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 211 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
143 reg = <0x70006200 0x40>; 212 reg = <0x0 0x70006200 0x0 0x40>;
144 reg-shift = <2>; 213 reg-shift = <2>;
145 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 214 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 215 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
@@ -151,9 +220,9 @@
151 status = "disabled"; 220 status = "disabled";
152 }; 221 };
153 222
154 serial@70006300 { 223 serial@0,70006300 {
155 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 224 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
156 reg = <0x70006300 0x40>; 225 reg = <0x0 0x70006300 0x0 0x40>;
157 reg-shift = <2>; 226 reg-shift = <2>;
158 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 227 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 228 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
@@ -164,9 +233,9 @@
164 status = "disabled"; 233 status = "disabled";
165 }; 234 };
166 235
167 serial@70006400 { 236 serial@0,70006400 {
168 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 237 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
169 reg = <0x70006400 0x40>; 238 reg = <0x0 0x70006400 0x0 0x40>;
170 reg-shift = <2>; 239 reg-shift = <2>;
171 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 240 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&tegra_car TEGRA124_CLK_UARTE>; 241 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
@@ -177,9 +246,9 @@
177 status = "disabled"; 246 status = "disabled";
178 }; 247 };
179 248
180 pwm@7000a000 { 249 pwm@0,7000a000 {
181 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 250 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
182 reg = <0x7000a000 0x100>; 251 reg = <0x0 0x7000a000 0x0 0x100>;
183 #pwm-cells = <2>; 252 #pwm-cells = <2>;
184 clocks = <&tegra_car TEGRA124_CLK_PWM>; 253 clocks = <&tegra_car TEGRA124_CLK_PWM>;
185 resets = <&tegra_car 17>; 254 resets = <&tegra_car 17>;
@@ -187,9 +256,9 @@
187 status = "disabled"; 256 status = "disabled";
188 }; 257 };
189 258
190 i2c@7000c000 { 259 i2c@0,7000c000 {
191 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 260 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
192 reg = <0x7000c000 0x100>; 261 reg = <0x0 0x7000c000 0x0 0x100>;
193 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>; 263 #address-cells = <1>;
195 #size-cells = <0>; 264 #size-cells = <0>;
@@ -202,9 +271,9 @@
202 status = "disabled"; 271 status = "disabled";
203 }; 272 };
204 273
205 i2c@7000c400 { 274 i2c@0,7000c400 {
206 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 275 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
207 reg = <0x7000c400 0x100>; 276 reg = <0x0 0x7000c400 0x0 0x100>;
208 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 277 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>; 278 #address-cells = <1>;
210 #size-cells = <0>; 279 #size-cells = <0>;
@@ -217,9 +286,9 @@
217 status = "disabled"; 286 status = "disabled";
218 }; 287 };
219 288
220 i2c@7000c500 { 289 i2c@0,7000c500 {
221 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 290 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
222 reg = <0x7000c500 0x100>; 291 reg = <0x0 0x7000c500 0x0 0x100>;
223 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 292 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
224 #address-cells = <1>; 293 #address-cells = <1>;
225 #size-cells = <0>; 294 #size-cells = <0>;
@@ -232,9 +301,9 @@
232 status = "disabled"; 301 status = "disabled";
233 }; 302 };
234 303
235 i2c@7000c700 { 304 i2c@0,7000c700 {
236 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 305 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
237 reg = <0x7000c700 0x100>; 306 reg = <0x0 0x7000c700 0x0 0x100>;
238 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
239 #address-cells = <1>; 308 #address-cells = <1>;
240 #size-cells = <0>; 309 #size-cells = <0>;
@@ -247,9 +316,9 @@
247 status = "disabled"; 316 status = "disabled";
248 }; 317 };
249 318
250 i2c@7000d000 { 319 i2c@0,7000d000 {
251 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 320 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
252 reg = <0x7000d000 0x100>; 321 reg = <0x0 0x7000d000 0x0 0x100>;
253 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 322 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>; 323 #address-cells = <1>;
255 #size-cells = <0>; 324 #size-cells = <0>;
@@ -262,9 +331,9 @@
262 status = "disabled"; 331 status = "disabled";
263 }; 332 };
264 333
265 i2c@7000d100 { 334 i2c@0,7000d100 {
266 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 335 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
267 reg = <0x7000d100 0x100>; 336 reg = <0x0 0x7000d100 0x0 0x100>;
268 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>; 338 #address-cells = <1>;
270 #size-cells = <0>; 339 #size-cells = <0>;
@@ -277,9 +346,9 @@
277 status = "disabled"; 346 status = "disabled";
278 }; 347 };
279 348
280 spi@7000d400 { 349 spi@0,7000d400 {
281 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 350 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
282 reg = <0x7000d400 0x200>; 351 reg = <0x0 0x7000d400 0x0 0x200>;
283 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>; 353 #address-cells = <1>;
285 #size-cells = <0>; 354 #size-cells = <0>;
@@ -292,9 +361,9 @@
292 status = "disabled"; 361 status = "disabled";
293 }; 362 };
294 363
295 spi@7000d600 { 364 spi@0,7000d600 {
296 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 365 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
297 reg = <0x7000d600 0x200>; 366 reg = <0x0 0x7000d600 0x0 0x200>;
298 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 367 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
299 #address-cells = <1>; 368 #address-cells = <1>;
300 #size-cells = <0>; 369 #size-cells = <0>;
@@ -307,9 +376,9 @@
307 status = "disabled"; 376 status = "disabled";
308 }; 377 };
309 378
310 spi@7000d800 { 379 spi@0,7000d800 {
311 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 380 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
312 reg = <0x7000d800 0x200>; 381 reg = <0x0 0x7000d800 0x0 0x200>;
313 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 382 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>; 383 #address-cells = <1>;
315 #size-cells = <0>; 384 #size-cells = <0>;
@@ -322,9 +391,9 @@
322 status = "disabled"; 391 status = "disabled";
323 }; 392 };
324 393
325 spi@7000da00 { 394 spi@0,7000da00 {
326 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 395 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
327 reg = <0x7000da00 0x200>; 396 reg = <0x0 0x7000da00 0x0 0x200>;
328 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 397 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>; 398 #address-cells = <1>;
330 #size-cells = <0>; 399 #size-cells = <0>;
@@ -337,9 +406,9 @@
337 status = "disabled"; 406 status = "disabled";
338 }; 407 };
339 408
340 spi@7000dc00 { 409 spi@0,7000dc00 {
341 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 410 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
342 reg = <0x7000dc00 0x200>; 411 reg = <0x0 0x7000dc00 0x0 0x200>;
343 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 412 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>; 413 #address-cells = <1>;
345 #size-cells = <0>; 414 #size-cells = <0>;
@@ -352,9 +421,9 @@
352 status = "disabled"; 421 status = "disabled";
353 }; 422 };
354 423
355 spi@7000de00 { 424 spi@0,7000de00 {
356 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 425 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
357 reg = <0x7000de00 0x200>; 426 reg = <0x0 0x7000de00 0x0 0x200>;
358 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 427 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>; 428 #address-cells = <1>;
360 #size-cells = <0>; 429 #size-cells = <0>;
@@ -367,65 +436,65 @@
367 status = "disabled"; 436 status = "disabled";
368 }; 437 };
369 438
370 rtc@7000e000 { 439 rtc@0,7000e000 {
371 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 440 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
372 reg = <0x7000e000 0x100>; 441 reg = <0x0 0x7000e000 0x0 0x100>;
373 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 442 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&tegra_car TEGRA124_CLK_RTC>; 443 clocks = <&tegra_car TEGRA124_CLK_RTC>;
375 }; 444 };
376 445
377 pmc@7000e400 { 446 pmc@0,7000e400 {
378 compatible = "nvidia,tegra124-pmc"; 447 compatible = "nvidia,tegra124-pmc";
379 reg = <0x7000e400 0x400>; 448 reg = <0x0 0x7000e400 0x0 0x400>;
380 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 449 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
381 clock-names = "pclk", "clk32k_in"; 450 clock-names = "pclk", "clk32k_in";
382 }; 451 };
383 452
384 sdhci@700b0000 { 453 sdhci@0,700b0000 {
385 compatible = "nvidia,tegra124-sdhci"; 454 compatible = "nvidia,tegra124-sdhci";
386 reg = <0x700b0000 0x200>; 455 reg = <0x0 0x700b0000 0x0 0x200>;
387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 456 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 457 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
389 resets = <&tegra_car 14>; 458 resets = <&tegra_car 14>;
390 reset-names = "sdhci"; 459 reset-names = "sdhci";
391 status = "disable"; 460 status = "disabled";
392 }; 461 };
393 462
394 sdhci@700b0200 { 463 sdhci@0,700b0200 {
395 compatible = "nvidia,tegra124-sdhci"; 464 compatible = "nvidia,tegra124-sdhci";
396 reg = <0x700b0200 0x200>; 465 reg = <0x0 0x700b0200 0x0 0x200>;
397 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 466 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 467 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
399 resets = <&tegra_car 9>; 468 resets = <&tegra_car 9>;
400 reset-names = "sdhci"; 469 reset-names = "sdhci";
401 status = "disable"; 470 status = "disabled";
402 }; 471 };
403 472
404 sdhci@700b0400 { 473 sdhci@0,700b0400 {
405 compatible = "nvidia,tegra124-sdhci"; 474 compatible = "nvidia,tegra124-sdhci";
406 reg = <0x700b0400 0x200>; 475 reg = <0x0 0x700b0400 0x0 0x200>;
407 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 476 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 477 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
409 resets = <&tegra_car 69>; 478 resets = <&tegra_car 69>;
410 reset-names = "sdhci"; 479 reset-names = "sdhci";
411 status = "disable"; 480 status = "disabled";
412 }; 481 };
413 482
414 sdhci@700b0600 { 483 sdhci@0,700b0600 {
415 compatible = "nvidia,tegra124-sdhci"; 484 compatible = "nvidia,tegra124-sdhci";
416 reg = <0x700b0600 0x200>; 485 reg = <0x0 0x700b0600 0x0 0x200>;
417 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 486 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 487 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
419 resets = <&tegra_car 15>; 488 resets = <&tegra_car 15>;
420 reset-names = "sdhci"; 489 reset-names = "sdhci";
421 status = "disable"; 490 status = "disabled";
422 }; 491 };
423 492
424 ahub@70300000 { 493 ahub@0,70300000 {
425 compatible = "nvidia,tegra124-ahub"; 494 compatible = "nvidia,tegra124-ahub";
426 reg = <0x70300000 0x200>, 495 reg = <0x0 0x70300000 0x0 0x200>,
427 <0x70300800 0x800>, 496 <0x0 0x70300800 0x0 0x800>,
428 <0x70300200 0x600>; 497 <0x0 0x70300200 0x0 0x600>;
429 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 498 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 499 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
431 <&tegra_car TEGRA124_CLK_APBIF>; 500 <&tegra_car TEGRA124_CLK_APBIF>;
@@ -470,12 +539,12 @@
470 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 539 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
471 "rx9", "tx9"; 540 "rx9", "tx9";
472 ranges; 541 ranges;
473 #address-cells = <1>; 542 #address-cells = <2>;
474 #size-cells = <1>; 543 #size-cells = <2>;
475 544
476 tegra_i2s0: i2s@70301000 { 545 tegra_i2s0: i2s@0,70301000 {
477 compatible = "nvidia,tegra124-i2s"; 546 compatible = "nvidia,tegra124-i2s";
478 reg = <0x70301000 0x100>; 547 reg = <0x0 0x70301000 0x0 0x100>;
479 nvidia,ahub-cif-ids = <4 4>; 548 nvidia,ahub-cif-ids = <4 4>;
480 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 549 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
481 resets = <&tegra_car 30>; 550 resets = <&tegra_car 30>;
@@ -483,9 +552,9 @@
483 status = "disabled"; 552 status = "disabled";
484 }; 553 };
485 554
486 tegra_i2s1: i2s@70301100 { 555 tegra_i2s1: i2s@0,70301100 {
487 compatible = "nvidia,tegra124-i2s"; 556 compatible = "nvidia,tegra124-i2s";
488 reg = <0x70301100 0x100>; 557 reg = <0x0 0x70301100 0x0 0x100>;
489 nvidia,ahub-cif-ids = <5 5>; 558 nvidia,ahub-cif-ids = <5 5>;
490 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 559 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
491 resets = <&tegra_car 11>; 560 resets = <&tegra_car 11>;
@@ -493,9 +562,9 @@
493 status = "disabled"; 562 status = "disabled";
494 }; 563 };
495 564
496 tegra_i2s2: i2s@70301200 { 565 tegra_i2s2: i2s@0,70301200 {
497 compatible = "nvidia,tegra124-i2s"; 566 compatible = "nvidia,tegra124-i2s";
498 reg = <0x70301200 0x100>; 567 reg = <0x0 0x70301200 0x0 0x100>;
499 nvidia,ahub-cif-ids = <6 6>; 568 nvidia,ahub-cif-ids = <6 6>;
500 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 569 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
501 resets = <&tegra_car 18>; 570 resets = <&tegra_car 18>;
@@ -503,9 +572,9 @@
503 status = "disabled"; 572 status = "disabled";
504 }; 573 };
505 574
506 tegra_i2s3: i2s@70301300 { 575 tegra_i2s3: i2s@0,70301300 {
507 compatible = "nvidia,tegra124-i2s"; 576 compatible = "nvidia,tegra124-i2s";
508 reg = <0x70301300 0x100>; 577 reg = <0x0 0x70301300 0x0 0x100>;
509 nvidia,ahub-cif-ids = <7 7>; 578 nvidia,ahub-cif-ids = <7 7>;
510 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 579 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
511 resets = <&tegra_car 101>; 580 resets = <&tegra_car 101>;
@@ -513,9 +582,9 @@
513 status = "disabled"; 582 status = "disabled";
514 }; 583 };
515 584
516 tegra_i2s4: i2s@70301400 { 585 tegra_i2s4: i2s@0,70301400 {
517 compatible = "nvidia,tegra124-i2s"; 586 compatible = "nvidia,tegra124-i2s";
518 reg = <0x70301400 0x100>; 587 reg = <0x0 0x70301400 0x0 0x100>;
519 nvidia,ahub-cif-ids = <8 8>; 588 nvidia,ahub-cif-ids = <8 8>;
520 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 589 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
521 resets = <&tegra_car 102>; 590 resets = <&tegra_car 102>;
@@ -524,6 +593,108 @@
524 }; 593 };
525 }; 594 };
526 595
596 usb@0,7d000000 {
597 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
598 reg = <0x0 0x7d000000 0x0 0x4000>;
599 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
600 phy_type = "utmi";
601 clocks = <&tegra_car TEGRA124_CLK_USBD>;
602 resets = <&tegra_car 22>;
603 reset-names = "usb";
604 nvidia,phy = <&phy1>;
605 status = "disabled";
606 };
607
608 phy1: usb-phy@0,7d000000 {
609 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
610 reg = <0x0 0x7d000000 0x0 0x4000>,
611 <0x0 0x7d000000 0x0 0x4000>;
612 phy_type = "utmi";
613 clocks = <&tegra_car TEGRA124_CLK_USBD>,
614 <&tegra_car TEGRA124_CLK_PLL_U>,
615 <&tegra_car TEGRA124_CLK_USBD>;
616 clock-names = "reg", "pll_u", "utmi-pads";
617 nvidia,hssync-start-delay = <0>;
618 nvidia,idle-wait-delay = <17>;
619 nvidia,elastic-limit = <16>;
620 nvidia,term-range-adj = <6>;
621 nvidia,xcvr-setup = <9>;
622 nvidia,xcvr-lsfslew = <0>;
623 nvidia,xcvr-lsrslew = <3>;
624 nvidia,hssquelch-level = <2>;
625 nvidia,hsdiscon-level = <5>;
626 nvidia,xcvr-hsslew = <12>;
627 status = "disabled";
628 };
629
630 usb@0,7d004000 {
631 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
632 reg = <0x0 0x7d004000 0x0 0x4000>;
633 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
634 phy_type = "utmi";
635 clocks = <&tegra_car TEGRA124_CLK_USB2>;
636 resets = <&tegra_car 58>;
637 reset-names = "usb";
638 nvidia,phy = <&phy2>;
639 status = "disabled";
640 };
641
642 phy2: usb-phy@0,7d004000 {
643 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
644 reg = <0x0 0x7d004000 0x0 0x4000>,
645 <0x0 0x7d000000 0x0 0x4000>;
646 phy_type = "utmi";
647 clocks = <&tegra_car TEGRA124_CLK_USB2>,
648 <&tegra_car TEGRA124_CLK_PLL_U>,
649 <&tegra_car TEGRA124_CLK_USBD>;
650 clock-names = "reg", "pll_u", "utmi-pads";
651 nvidia,hssync-start-delay = <0>;
652 nvidia,idle-wait-delay = <17>;
653 nvidia,elastic-limit = <16>;
654 nvidia,term-range-adj = <6>;
655 nvidia,xcvr-setup = <9>;
656 nvidia,xcvr-lsfslew = <0>;
657 nvidia,xcvr-lsrslew = <3>;
658 nvidia,hssquelch-level = <2>;
659 nvidia,hsdiscon-level = <5>;
660 nvidia,xcvr-hsslew = <12>;
661 status = "disabled";
662 };
663
664 usb@0,7d008000 {
665 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
666 reg = <0x0 0x7d008000 0x0 0x4000>;
667 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
668 phy_type = "utmi";
669 clocks = <&tegra_car TEGRA124_CLK_USB3>;
670 resets = <&tegra_car 59>;
671 reset-names = "usb";
672 nvidia,phy = <&phy3>;
673 status = "disabled";
674 };
675
676 phy3: usb-phy@0,7d008000 {
677 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
678 reg = <0x0 0x7d008000 0x0 0x4000>,
679 <0x0 0x7d000000 0x0 0x4000>;
680 phy_type = "utmi";
681 clocks = <&tegra_car TEGRA124_CLK_USB3>,
682 <&tegra_car TEGRA124_CLK_PLL_U>,
683 <&tegra_car TEGRA124_CLK_USBD>;
684 clock-names = "reg", "pll_u", "utmi-pads";
685 nvidia,hssync-start-delay = <0>;
686 nvidia,idle-wait-delay = <17>;
687 nvidia,elastic-limit = <16>;
688 nvidia,term-range-adj = <6>;
689 nvidia,xcvr-setup = <9>;
690 nvidia,xcvr-lsfslew = <0>;
691 nvidia,xcvr-lsrslew = <3>;
692 nvidia,hssquelch-level = <2>;
693 nvidia,hsdiscon-level = <5>;
694 nvidia,xcvr-hsslew = <12>;
695 status = "disabled";
696 };
697
527 cpus { 698 cpus {
528 #address-cells = <1>; 699 #address-cells = <1>;
529 #size-cells = <0>; 700 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index c7cd8e6802d7..9a39a8001f78 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -17,6 +17,14 @@
17 }; 17 };
18 18
19 host1x@50000000 { 19 host1x@50000000 {
20 dc@54200000 {
21 rgb {
22 status = "okay";
23
24 nvidia,panel = <&panel>;
25 };
26 };
27
20 hdmi@54280000 { 28 hdmi@54280000 {
21 status = "okay"; 29 status = "okay";
22 30
@@ -257,7 +265,11 @@
257 status = "okay"; 265 status = "okay";
258 }; 266 };
259 267
260 i2c@7000c000 { 268 pwm: pwm@7000a000 {
269 status = "okay";
270 };
271
272 lvds_ddc: i2c@7000c000 {
261 status = "okay"; 273 status = "okay";
262 clock-frequency = <400000>; 274 clock-frequency = <400000>;
263 275
@@ -475,6 +487,18 @@
475 non-removable; 487 non-removable;
476 }; 488 };
477 489
490 backlight: backlight {
491 compatible = "pwm-backlight";
492
493 enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
494 pwms = <&pwm 0 5000000>;
495
496 brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
497 default-brightness-level = <10>;
498
499 backlight-boot-off;
500 };
501
478 clocks { 502 clocks {
479 compatible = "simple-bus"; 503 compatible = "simple-bus";
480 #address-cells = <1>; 504 #address-cells = <1>;
@@ -509,6 +533,16 @@
509 }; 533 };
510 }; 534 };
511 535
536 panel: panel {
537 compatible = "samsung,ltn101nt05", "simple-panel";
538
539 ddc-i2c-bus = <&lvds_ddc>;
540 power-supply = <&vdd_pnl_reg>;
541 enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
542
543 backlight = <&backlight>;
544 };
545
512 regulators { 546 regulators {
513 compatible = "simple-bus"; 547 compatible = "simple-bus";
514 #address-cells = <1>; 548 #address-cells = <1>;
@@ -522,6 +556,16 @@
522 regulator-max-microvolt = <5000000>; 556 regulator-max-microvolt = <5000000>;
523 regulator-always-on; 557 regulator-always-on;
524 }; 558 };
559
560 vdd_pnl_reg: regulator@1 {
561 compatible = "regulator-fixed";
562 reg = <1>;
563 regulator-name = "+3VS,vdd_pnl";
564 regulator-min-microvolt = <3300000>;
565 regulator-max-microvolt = <3300000>;
566 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
567 enable-active-high;
568 };
525 }; 569 };
526 570
527 sound { 571 sound {
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index a11b6e7b4759..a1d4bf9895d7 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -17,6 +17,14 @@
17 }; 17 };
18 18
19 host1x@50000000 { 19 host1x@50000000 {
20 dc@54200000 {
21 rgb {
22 status = "okay";
23
24 nvidia,panel = <&panel>;
25 };
26 };
27
20 hdmi@54280000 { 28 hdmi@54280000 {
21 status = "okay"; 29 status = "okay";
22 30
@@ -312,6 +320,10 @@
312 status = "okay"; 320 status = "okay";
313 }; 321 };
314 322
323 pwm: pwm@7000a000 {
324 status = "okay";
325 };
326
315 i2c@7000c000 { 327 i2c@7000c000 {
316 status = "okay"; 328 status = "okay";
317 clock-frequency = <400000>; 329 clock-frequency = <400000>;
@@ -369,7 +381,7 @@
369 #size-cells = <0>; 381 #size-cells = <0>;
370 }; 382 };
371 383
372 i2c@1 { 384 lvds_ddc: i2c@1 {
373 reg = <1>; 385 reg = <1>;
374 #address-cells = <1>; 386 #address-cells = <1>;
375 #size-cells = <0>; 387 #size-cells = <0>;
@@ -762,6 +774,17 @@
762 non-removable; 774 non-removable;
763 }; 775 };
764 776
777 backlight: backlight {
778 compatible = "pwm-backlight";
779
780 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
781 power-supply = <&vdd_bl_reg>;
782 pwms = <&pwm 2 5000000>;
783
784 brightness-levels = <0 4 8 16 32 64 128 255>;
785 default-brightness-level = <6>;
786 };
787
765 clocks { 788 clocks {
766 compatible = "simple-bus"; 789 compatible = "simple-bus";
767 #address-cells = <1>; 790 #address-cells = <1>;
@@ -795,6 +818,16 @@
795 }; 818 };
796 }; 819 };
797 820
821 panel: panel {
822 compatible = "chunghwa,claa101wa01a", "simple-panel";
823
824 power-supply = <&vdd_pnl_reg>;
825 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
826
827 backlight = <&backlight>;
828 ddc-i2c-bus = <&lvds_ddc>;
829 };
830
798 regulators { 831 regulators {
799 compatible = "simple-bus"; 832 compatible = "simple-bus";
800 #address-cells = <1>; 833 #address-cells = <1>;
@@ -839,6 +872,26 @@
839 regulator-always-on; 872 regulator-always-on;
840 regulator-boot-on; 873 regulator-boot-on;
841 }; 874 };
875
876 vdd_pnl_reg: regulator@4 {
877 compatible = "regulator-fixed";
878 reg = <4>;
879 regulator-name = "vdd_pnl";
880 regulator-min-microvolt = <2800000>;
881 regulator-max-microvolt = <2800000>;
882 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
883 enable-active-high;
884 };
885
886 vdd_bl_reg: regulator@5 {
887 compatible = "regulator-fixed";
888 reg = <5>;
889 regulator-name = "vdd_bl";
890 regulator-min-microvolt = <2800000>;
891 regulator-max-microvolt = <2800000>;
892 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
893 enable-active-high;
894 };
842 }; 895 };
843 896
844 sound { 897 sound {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 571d12e6ac2d..ca8484cccddc 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -17,6 +17,14 @@
17 }; 17 };
18 18
19 host1x@50000000 { 19 host1x@50000000 {
20 dc@54200000 {
21 rgb {
22 status = "okay";
23
24 nvidia,panel = <&panel>;
25 };
26 };
27
20 hdmi@54280000 { 28 hdmi@54280000 {
21 status = "okay"; 29 status = "okay";
22 30
@@ -309,6 +317,10 @@
309 status = "okay"; 317 status = "okay";
310 }; 318 };
311 319
320 pwm: pwm@7000a000 {
321 status = "okay";
322 };
323
312 i2c@7000c000 { 324 i2c@7000c000 {
313 status = "okay"; 325 status = "okay";
314 clock-frequency = <400000>; 326 clock-frequency = <400000>;
@@ -359,7 +371,7 @@
359 #size-cells = <0>; 371 #size-cells = <0>;
360 }; 372 };
361 373
362 i2c@1 { 374 lvds_ddc: i2c@1 {
363 reg = <1>; 375 reg = <1>;
364 #address-cells = <1>; 376 #address-cells = <1>;
365 #size-cells = <0>; 377 #size-cells = <0>;
@@ -557,6 +569,17 @@
557 non-removable; 569 non-removable;
558 }; 570 };
559 571
572 backlight: backlight {
573 compatible = "pwm-backlight";
574
575 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
576 power-supply = <&vdd_bl_reg>;
577 pwms = <&pwm 2 5000000>;
578
579 brightness-levels = <0 4 8 16 32 64 128 255>;
580 default-brightness-level = <6>;
581 };
582
560 clocks { 583 clocks {
561 compatible = "simple-bus"; 584 compatible = "simple-bus";
562 #address-cells = <1>; 585 #address-cells = <1>;
@@ -581,6 +604,16 @@
581 }; 604 };
582 }; 605 };
583 606
607 panel: panel {
608 compatible = "chunghwa,claa101wa01a", "simple-panel";
609
610 power-supply = <&vdd_pnl_reg>;
611 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
612
613 backlight = <&backlight>;
614 ddc-i2c-bus = <&lvds_ddc>;
615 };
616
584 regulators { 617 regulators {
585 compatible = "simple-bus"; 618 compatible = "simple-bus";
586 #address-cells = <1>; 619 #address-cells = <1>;
@@ -614,7 +647,7 @@
614 enable-active-high; 647 enable-active-high;
615 }; 648 };
616 649
617 regulator@3 { 650 vdd_pnl_reg: regulator@3 {
618 compatible = "regulator-fixed"; 651 compatible = "regulator-fixed";
619 reg = <3>; 652 reg = <3>;
620 regulator-name = "vdd_pnl"; 653 regulator-name = "vdd_pnl";
@@ -624,7 +657,7 @@
624 enable-active-high; 657 enable-active-high;
625 }; 658 };
626 659
627 regulator@4 { 660 vdd_bl_reg: regulator@4 {
628 compatible = "regulator-fixed"; 661 compatible = "regulator-fixed";
629 reg = <4>; 662 reg = <4>;
630 regulator-name = "vdd_bl"; 663 regulator-name = "vdd_bl";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 48d2a7f4d0c0..a7ddf70df50b 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -556,6 +556,10 @@
556 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 556 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
557 interrupt-names = "intr", "msi"; 557 interrupt-names = "intr", "msi";
558 558
559 #interrupt-cells = <1>;
560 interrupt-map-mask = <0 0 0 0>;
561 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
562
559 bus-range = <0x00 0xff>; 563 bus-range = <0x00 0xff>;
560 #address-cells = <3>; 564 #address-cells = <3>;
561 #size-cells = <2>; 565 #size-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 1e156d9d0506..0cf0848a82d8 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -187,6 +187,13 @@
187 interrupt-parent = <&gpio>; 187 interrupt-parent = <&gpio>;
188 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; 188 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
189 }; 189 };
190
191 i2cmux@70 {
192 compatible = "nxp,pca9546";
193 #address-cells = <1>;
194 #size-cells = <0>;
195 reg = <0x70>;
196 };
190 }; 197 };
191 198
192 i2c@7000c700 { 199 i2c@7000c700 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 19a84e933f4e..dec4fc823901 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -28,6 +28,10 @@
28 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 28 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
29 interrupt-names = "intr", "msi"; 29 interrupt-names = "intr", "msi";
30 30
31 #interrupt-cells = <1>;
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34
31 bus-range = <0x00 0xff>; 35 bus-range = <0x00 0xff>;
32 #address-cells = <3>; 36 #address-cells = <3>;
33 #size-cells = <2>; 37 #size-cells = <2>;
@@ -144,9 +148,9 @@
144 compatible = "nvidia,tegra30-gr2d"; 148 compatible = "nvidia,tegra30-gr2d";
145 reg = <0x54140000 0x00040000>; 149 reg = <0x54140000 0x00040000>;
146 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 150 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
147 resets = <&tegra_car 21>; 152 resets = <&tegra_car 21>;
148 reset-names = "2d"; 153 reset-names = "2d";
149 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
150 }; 154 };
151 155
152 gr3d@54180000 { 156 gr3d@54180000 {
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
index 92693a89160e..b0ac6657a170 100644
--- a/arch/arm/boot/dts/tps65910.dtsi
+++ b/arch/arm/boot/dts/tps65910.dtsi
@@ -82,5 +82,10 @@
82 reg = <12>; 82 reg = <12>;
83 regulator-compatible = "vmmc"; 83 regulator-compatible = "vmmc";
84 }; 84 };
85
86 vbb_reg: regulator@13 {
87 reg = <13>;
88 regulator-compatible = "vbb";
89 };
85 }; 90 };
86}; 91};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 4217096ee677..86cfc7d15ca7 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -145,4 +145,11 @@
145 compatible = "ti,twl4030-pwrbutton"; 145 compatible = "ti,twl4030-pwrbutton";
146 interrupts = <8>; 146 interrupts = <8>;
147 }; 147 };
148
149 twl_keypad: keypad {
150 compatible = "ti,twl4030-keypad";
151 interrupts = <1>;
152 keypad,num-rows = <8>;
153 keypad,num-columns = <8>;
154 };
148}; 155};
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index c42e4f938dcd..3fd1b74e1216 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -36,12 +36,37 @@
36&fec1 { 36&fec1 {
37 phy-mode = "rmii"; 37 phy-mode = "rmii";
38 pinctrl-names = "default"; 38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_fec1_1>; 39 pinctrl-0 = <&pinctrl_fec1>;
40 status = "okay"; 40 status = "okay";
41}; 41};
42 42
43&iomuxc {
44 vf610-cosmic {
45 pinctrl_fec1: fec1grp {
46 fsl,pins = <
47 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
48 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
49 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
50 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
51 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
52 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
53 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
54 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
55 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
56 >;
57 };
58
59 pinctrl_uart1: uart1grp {
60 fsl,pins = <
61 VF610_PAD_PTB4__UART1_TX 0x21a2
62 VF610_PAD_PTB5__UART1_RX 0x21a1
63 >;
64 };
65 };
66};
67
43&uart1 { 68&uart1 {
44 pinctrl-names = "default"; 69 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_uart1_1>; 70 pinctrl-0 = <&pinctrl_uart1>;
46 status = "okay"; 71 status = "okay";
47}; 72};
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index c8047ca16501..7dd1d6ede525 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -34,12 +34,70 @@
34 }; 34 };
35 }; 35 };
36 36
37 regulators {
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 reg_3p3v: regulator@0 {
43 compatible = "regulator-fixed";
44 reg = <0>;
45 regulator-name = "3P3V";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 regulator-always-on;
49 };
50
51 reg_vcc_3v3_mcu: regulator@1 {
52 compatible = "regulator-fixed";
53 reg = <1>;
54 regulator-name = "vcc_3v3_mcu";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 };
58 };
59
60 sound {
61 compatible = "simple-audio-card";
62 simple-audio-card,format = "i2s";
63 simple-audio-card,widgets =
64 "Microphone", "Microphone Jack",
65 "Headphone", "Headphone Jack",
66 "Speaker", "Speaker Ext",
67 "Line", "Line In Jack";
68 simple-audio-card,routing =
69 "MIC_IN", "Microphone Jack",
70 "Microphone Jack", "Mic Bias",
71 "LINE_IN", "Line In Jack",
72 "Headphone Jack", "HP_OUT",
73 "Speaker Ext", "LINE_OUT";
74
75 simple-audio-card,cpu {
76 sound-dai = <&sai2>;
77 master-clkdir-out;
78 frame-master;
79 bitclock-master;
80 };
81
82 simple-audio-card,codec {
83 sound-dai = <&codec>;
84 frame-master;
85 bitclock-master;
86 };
87 };
88};
89
90&adc0 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_adc0_ad5>;
93 vref-supply = <&reg_vcc_3v3_mcu>;
94 status = "okay";
37}; 95};
38 96
39&dspi0 { 97&dspi0 {
40 bus-num = <0>; 98 bus-num = <0>;
41 pinctrl-names = "default"; 99 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_dspi0_1>; 100 pinctrl-0 = <&pinctrl_dspi0>;
43 status = "okay"; 101 status = "okay";
44 102
45 sflash: at26df081a@0 { 103 sflash: at26df081a@0 {
@@ -56,26 +114,116 @@
56&fec0 { 114&fec0 {
57 phy-mode = "rmii"; 115 phy-mode = "rmii";
58 pinctrl-names = "default"; 116 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_fec0_1>; 117 pinctrl-0 = <&pinctrl_fec0>;
60 status = "okay"; 118 status = "okay";
61}; 119};
62 120
63&fec1 { 121&fec1 {
64 phy-mode = "rmii"; 122 phy-mode = "rmii";
65 pinctrl-names = "default"; 123 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_fec1_1>; 124 pinctrl-0 = <&pinctrl_fec1>;
67 status = "okay"; 125 status = "okay";
68}; 126};
69 127
70&i2c0 { 128&i2c0 {
71 clock-frequency = <100000>; 129 clock-frequency = <100000>;
72 pinctrl-names = "default"; 130 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_i2c0_1>; 131 pinctrl-0 = <&pinctrl_i2c0>;
132 status = "okay";
133
134 codec: sgtl5000@0a {
135 #sound-dai-cells = <0>;
136 compatible = "fsl,sgtl5000";
137 reg = <0x0a>;
138 VDDA-supply = <&reg_3p3v>;
139 VDDIO-supply = <&reg_3p3v>;
140 clocks = <&clks VF610_CLK_SAI2>;
141 };
142};
143
144&iomuxc {
145 vf610-twr {
146 pinctrl_adc0_ad5: adc0ad5grp {
147 fsl,pins = <
148 VF610_PAD_PTC30__ADC0_SE5 0xa1
149 >;
150 };
151
152 pinctrl_dspi0: dspi0grp {
153 fsl,pins = <
154 VF610_PAD_PTB19__DSPI0_CS0 0x1182
155 VF610_PAD_PTB20__DSPI0_SIN 0x1181
156 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
157 VF610_PAD_PTB22__DSPI0_SCK 0x1182
158 >;
159 };
160
161 pinctrl_fec0: fec0grp {
162 fsl,pins = <
163 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
164 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
165 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
166 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
167 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
168 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
169 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
170 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
171 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
172 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
173 >;
174 };
175
176 pinctrl_fec1: fec1grp {
177 fsl,pins = <
178 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
179 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
180 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
181 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
182 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
183 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
184 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
185 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
186 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
187 >;
188 };
189
190 pinctrl_i2c0: i2c0grp {
191 fsl,pins = <
192 VF610_PAD_PTB14__I2C0_SCL 0x30d3
193 VF610_PAD_PTB15__I2C0_SDA 0x30d3
194 >;
195 };
196
197 pinctrl_sai2: sai2grp {
198 fsl,pins = <
199 VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
200 VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
201 VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
202 VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
203 VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
204 VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
205 VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
206 >;
207 };
208
209 pinctrl_uart1: uart1grp {
210 fsl,pins = <
211 VF610_PAD_PTB4__UART1_TX 0x21a2
212 VF610_PAD_PTB5__UART1_RX 0x21a1
213 >;
214 };
215 };
216};
217
218&sai2 {
219 #sound-dai-cells = <0>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_sai2>;
74 status = "okay"; 222 status = "okay";
75}; 223};
76 224
77&uart1 { 225&uart1 {
78 pinctrl-names = "default"; 226 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_uart1_1>; 227 pinctrl-0 = <&pinctrl_uart1>;
80 status = "okay"; 228 status = "okay";
81}; 229};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index d31ce1b4a7b0..804873367669 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -10,6 +10,7 @@
10#include "skeleton.dtsi" 10#include "skeleton.dtsi"
11#include "vf610-pinfunc.h" 11#include "vf610-pinfunc.h"
12#include <dt-bindings/clock/vf610-clock.h> 12#include <dt-bindings/clock/vf610-clock.h>
13#include <dt-bindings/interrupt-controller/irq.h>
13 14
14/ { 15/ {
15 aliases { 16 aliases {
@@ -87,39 +88,66 @@
87 arm,tag-latency = <2 2 2>; 88 arm,tag-latency = <2 2 2>;
88 }; 89 };
89 90
91 edma0: dma-controller@40018000 {
92 #dma-cells = <2>;
93 compatible = "fsl,vf610-edma";
94 reg = <0x40018000 0x2000>,
95 <0x40024000 0x1000>,
96 <0x40025000 0x1000>;
97 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
98 <0 9 IRQ_TYPE_LEVEL_HIGH>;
99 interrupt-names = "edma-tx", "edma-err";
100 dma-channels = <32>;
101 clock-names = "dmamux0", "dmamux1";
102 clocks = <&clks VF610_CLK_DMAMUX0>,
103 <&clks VF610_CLK_DMAMUX1>;
104 };
105
90 uart0: serial@40027000 { 106 uart0: serial@40027000 {
91 compatible = "fsl,vf610-lpuart"; 107 compatible = "fsl,vf610-lpuart";
92 reg = <0x40027000 0x1000>; 108 reg = <0x40027000 0x1000>;
93 interrupts = <0 61 0x00>; 109 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&clks VF610_CLK_UART0>; 110 clocks = <&clks VF610_CLK_UART0>;
95 clock-names = "ipg"; 111 clock-names = "ipg";
112 dmas = <&edma0 0 2>,
113 <&edma0 0 3>;
114 dma-names = "rx","tx";
96 status = "disabled"; 115 status = "disabled";
97 }; 116 };
98 117
99 uart1: serial@40028000 { 118 uart1: serial@40028000 {
100 compatible = "fsl,vf610-lpuart"; 119 compatible = "fsl,vf610-lpuart";
101 reg = <0x40028000 0x1000>; 120 reg = <0x40028000 0x1000>;
102 interrupts = <0 62 0x04>; 121 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&clks VF610_CLK_UART1>; 122 clocks = <&clks VF610_CLK_UART1>;
104 clock-names = "ipg"; 123 clock-names = "ipg";
124 dmas = <&edma0 0 4>,
125 <&edma0 0 5>;
126 dma-names = "rx","tx";
105 status = "disabled"; 127 status = "disabled";
106 }; 128 };
107 129
108 uart2: serial@40029000 { 130 uart2: serial@40029000 {
109 compatible = "fsl,vf610-lpuart"; 131 compatible = "fsl,vf610-lpuart";
110 reg = <0x40029000 0x1000>; 132 reg = <0x40029000 0x1000>;
111 interrupts = <0 63 0x04>; 133 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clks VF610_CLK_UART2>; 134 clocks = <&clks VF610_CLK_UART2>;
113 clock-names = "ipg"; 135 clock-names = "ipg";
136 dmas = <&edma0 0 6>,
137 <&edma0 0 7>;
138 dma-names = "rx","tx";
114 status = "disabled"; 139 status = "disabled";
115 }; 140 };
116 141
117 uart3: serial@4002a000 { 142 uart3: serial@4002a000 {
118 compatible = "fsl,vf610-lpuart"; 143 compatible = "fsl,vf610-lpuart";
119 reg = <0x4002a000 0x1000>; 144 reg = <0x4002a000 0x1000>;
120 interrupts = <0 64 0x04>; 145 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&clks VF610_CLK_UART3>; 146 clocks = <&clks VF610_CLK_UART3>;
122 clock-names = "ipg"; 147 clock-names = "ipg";
148 dmas = <&edma0 0 8>,
149 <&edma0 0 9>;
150 dma-names = "rx","tx";
123 status = "disabled"; 151 status = "disabled";
124 }; 152 };
125 153
@@ -128,7 +156,7 @@
128 #size-cells = <0>; 156 #size-cells = <0>;
129 compatible = "fsl,vf610-dspi"; 157 compatible = "fsl,vf610-dspi";
130 reg = <0x4002c000 0x1000>; 158 reg = <0x4002c000 0x1000>;
131 interrupts = <0 67 0x04>; 159 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&clks VF610_CLK_DSPI0>; 160 clocks = <&clks VF610_CLK_DSPI0>;
133 clock-names = "dspi"; 161 clock-names = "dspi";
134 spi-num-chipselects = <5>; 162 spi-num-chipselects = <5>;
@@ -138,20 +166,32 @@
138 sai2: sai@40031000 { 166 sai2: sai@40031000 {
139 compatible = "fsl,vf610-sai"; 167 compatible = "fsl,vf610-sai";
140 reg = <0x40031000 0x1000>; 168 reg = <0x40031000 0x1000>;
141 interrupts = <0 86 0x04>; 169 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&clks VF610_CLK_SAI2>; 170 clocks = <&clks VF610_CLK_SAI2>;
143 clock-names = "sai"; 171 clock-names = "sai";
172 dma-names = "tx", "rx";
173 dmas = <&edma0 0 21>,
174 <&edma0 0 20>;
144 status = "disabled"; 175 status = "disabled";
145 }; 176 };
146 177
147 pit: pit@40037000 { 178 pit: pit@40037000 {
148 compatible = "fsl,vf610-pit"; 179 compatible = "fsl,vf610-pit";
149 reg = <0x40037000 0x1000>; 180 reg = <0x40037000 0x1000>;
150 interrupts = <0 39 0x04>; 181 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&clks VF610_CLK_PIT>; 182 clocks = <&clks VF610_CLK_PIT>;
152 clock-names = "pit"; 183 clock-names = "pit";
153 }; 184 };
154 185
186 adc0: adc@4003b000 {
187 compatible = "fsl,vf610-adc";
188 reg = <0x4003b000 0x1000>;
189 interrupts = <0 53 0x04>;
190 clocks = <&clks VF610_CLK_ADC0>;
191 clock-names = "adc";
192 status = "disabled";
193 };
194
155 wdog@4003e000 { 195 wdog@4003e000 {
156 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; 196 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
157 reg = <0x4003e000 0x1000>; 197 reg = <0x4003e000 0x1000>;
@@ -164,7 +204,7 @@
164 #size-cells = <0>; 204 #size-cells = <0>;
165 compatible = "fsl,vf610-qspi"; 205 compatible = "fsl,vf610-qspi";
166 reg = <0x40044000 0x1000>; 206 reg = <0x40044000 0x1000>;
167 interrupts = <0 24 0x04>; 207 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&clks VF610_CLK_QSPI0_EN>, 208 clocks = <&clks VF610_CLK_QSPI0_EN>,
169 <&clks VF610_CLK_QSPI0>; 209 <&clks VF610_CLK_QSPI0>;
170 clock-names = "qspi_en", "qspi"; 210 clock-names = "qspi_en", "qspi";
@@ -175,182 +215,12 @@
175 compatible = "fsl,vf610-iomuxc"; 215 compatible = "fsl,vf610-iomuxc";
176 reg = <0x40048000 0x1000>; 216 reg = <0x40048000 0x1000>;
177 #gpio-range-cells = <3>; 217 #gpio-range-cells = <3>;
178
179 /* functions and groups pins */
180
181 dcu0 {
182 pinctrl_dcu0_1: dcu0grp_1 {
183 fsl,pins = <
184 VF610_PAD_PTB8__GPIO_30 0x42
185 VF610_PAD_PTE0__DCU0_HSYNC 0x42
186 VF610_PAD_PTE1__DCU0_VSYNC 0x42
187 VF610_PAD_PTE2__DCU0_PCLK 0x42
188 VF610_PAD_PTE4__DCU0_DE 0x42
189 VF610_PAD_PTE5__DCU0_R0 0x42
190 VF610_PAD_PTE6__DCU0_R1 0x42
191 VF610_PAD_PTE7__DCU0_R2 0x42
192 VF610_PAD_PTE8__DCU0_R3 0x42
193 VF610_PAD_PTE9__DCU0_R4 0x42
194 VF610_PAD_PTE10__DCU0_R5 0x42
195 VF610_PAD_PTE11__DCU0_R6 0x42
196 VF610_PAD_PTE12__DCU0_R7 0x42
197 VF610_PAD_PTE13__DCU0_G0 0x42
198 VF610_PAD_PTE14__DCU0_G1 0x42
199 VF610_PAD_PTE15__DCU0_G2 0x42
200 VF610_PAD_PTE16__DCU0_G3 0x42
201 VF610_PAD_PTE17__DCU0_G4 0x42
202 VF610_PAD_PTE18__DCU0_G5 0x42
203 VF610_PAD_PTE19__DCU0_G6 0x42
204 VF610_PAD_PTE20__DCU0_G7 0x42
205 VF610_PAD_PTE21__DCU0_B0 0x42
206 VF610_PAD_PTE22__DCU0_B1 0x42
207 VF610_PAD_PTE23__DCU0_B2 0x42
208 VF610_PAD_PTE24__DCU0_B3 0x42
209 VF610_PAD_PTE25__DCU0_B4 0x42
210 VF610_PAD_PTE26__DCU0_B5 0x42
211 VF610_PAD_PTE27__DCU0_B6 0x42
212 VF610_PAD_PTE28__DCU0_B7 0x42
213 >;
214 };
215 };
216
217 dspi0 {
218 pinctrl_dspi0_1: dspi0grp_1 {
219 fsl,pins = <
220 VF610_PAD_PTB19__DSPI0_CS0 0x1182
221 VF610_PAD_PTB20__DSPI0_SIN 0x1181
222 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
223 VF610_PAD_PTB22__DSPI0_SCK 0x1182
224 >;
225 };
226 };
227
228 esdhc1 {
229 pinctrl_esdhc1_1: esdhc1grp_1 {
230 fsl,pins = <
231 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
232 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
233 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
234 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
235 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
236 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
237 VF610_PAD_PTA7__GPIO_134 0x219d
238 >;
239 };
240 };
241
242 fec0 {
243 pinctrl_fec0_1: fec0grp_1 {
244 fsl,pins = <
245 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
246 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
247 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
248 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
249 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
250 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
251 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
252 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
253 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
254 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
255 >;
256 };
257 };
258
259 fec1 {
260 pinctrl_fec1_1: fec1grp_1 {
261 fsl,pins = <
262 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
263 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
264 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
265 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
266 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
267 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
268 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
269 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
270 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
271 >;
272 };
273 };
274
275 i2c0 {
276 pinctrl_i2c0_1: i2c0grp_1 {
277 fsl,pins = <
278 VF610_PAD_PTB14__I2C0_SCL 0x30d3
279 VF610_PAD_PTB15__I2C0_SDA 0x30d3
280 >;
281 };
282 };
283
284 pwm0 {
285 pinctrl_pwm0_1: pwm0grp_1 {
286 fsl,pins = <
287 VF610_PAD_PTB0__FTM0_CH0 0x1582
288 VF610_PAD_PTB1__FTM0_CH1 0x1582
289 VF610_PAD_PTB2__FTM0_CH2 0x1582
290 VF610_PAD_PTB3__FTM0_CH3 0x1582
291 VF610_PAD_PTB6__FTM0_CH6 0x1582
292 VF610_PAD_PTB7__FTM0_CH7 0x1582
293 >;
294 };
295 };
296
297 qspi0 {
298 pinctrl_qspi0_1: qspi0grp_1 {
299 fsl,pins = <
300 VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b
301 VF610_PAD_PTD1__QSPI0_A_CS0 0x307f
302 VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073
303 VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073
304 VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073
305 VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b
306 VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b
307 VF610_PAD_PTD8__QSPI0_B_CS0 0x307f
308 VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073
309 VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073
310 VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073
311 VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b
312 >;
313 };
314 };
315
316 sai2 {
317 pinctrl_sai2_1: sai2grp_1 {
318 fsl,pins = <
319 VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
320 VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
321 VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
322 VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
323 VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
324 VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
325 VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
326 >;
327 };
328 };
329
330 uart1 {
331 pinctrl_uart1_1: uart1grp_1 {
332 fsl,pins = <
333 VF610_PAD_PTB4__UART1_TX 0x21a2
334 VF610_PAD_PTB5__UART1_RX 0x21a1
335 >;
336 };
337 };
338
339 usbvbus {
340 pinctrl_usbvbus_1: usbvbusgrp_1 {
341 fsl,pins = <
342 VF610_PAD_PTA24__USB1_VBUS_EN 0x219c
343 VF610_PAD_PTA16__USB0_VBUS_EN 0x219c
344 >;
345 };
346 };
347
348 }; 218 };
349 219
350 gpio1: gpio@40049000 { 220 gpio1: gpio@40049000 {
351 compatible = "fsl,vf610-gpio"; 221 compatible = "fsl,vf610-gpio";
352 reg = <0x40049000 0x1000 0x400ff000 0x40>; 222 reg = <0x40049000 0x1000 0x400ff000 0x40>;
353 interrupts = <0 107 0x04>; 223 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
354 gpio-controller; 224 gpio-controller;
355 #gpio-cells = <2>; 225 #gpio-cells = <2>;
356 interrupt-controller; 226 interrupt-controller;
@@ -361,7 +231,7 @@
361 gpio2: gpio@4004a000 { 231 gpio2: gpio@4004a000 {
362 compatible = "fsl,vf610-gpio"; 232 compatible = "fsl,vf610-gpio";
363 reg = <0x4004a000 0x1000 0x400ff040 0x40>; 233 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
364 interrupts = <0 108 0x04>; 234 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
365 gpio-controller; 235 gpio-controller;
366 #gpio-cells = <2>; 236 #gpio-cells = <2>;
367 interrupt-controller; 237 interrupt-controller;
@@ -372,7 +242,7 @@
372 gpio3: gpio@4004b000 { 242 gpio3: gpio@4004b000 {
373 compatible = "fsl,vf610-gpio"; 243 compatible = "fsl,vf610-gpio";
374 reg = <0x4004b000 0x1000 0x400ff080 0x40>; 244 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
375 interrupts = <0 109 0x04>; 245 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
376 gpio-controller; 246 gpio-controller;
377 #gpio-cells = <2>; 247 #gpio-cells = <2>;
378 interrupt-controller; 248 interrupt-controller;
@@ -383,7 +253,7 @@
383 gpio4: gpio@4004c000 { 253 gpio4: gpio@4004c000 {
384 compatible = "fsl,vf610-gpio"; 254 compatible = "fsl,vf610-gpio";
385 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; 255 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
386 interrupts = <0 110 0x04>; 256 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
387 gpio-controller; 257 gpio-controller;
388 #gpio-cells = <2>; 258 #gpio-cells = <2>;
389 interrupt-controller; 259 interrupt-controller;
@@ -394,7 +264,7 @@
394 gpio5: gpio@4004d000 { 264 gpio5: gpio@4004d000 {
395 compatible = "fsl,vf610-gpio"; 265 compatible = "fsl,vf610-gpio";
396 reg = <0x4004d000 0x1000 0x400ff100 0x40>; 266 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
397 interrupts = <0 111 0x04>; 267 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
398 gpio-controller; 268 gpio-controller;
399 #gpio-cells = <2>; 269 #gpio-cells = <2>;
400 interrupt-controller; 270 interrupt-controller;
@@ -412,9 +282,12 @@
412 #size-cells = <0>; 282 #size-cells = <0>;
413 compatible = "fsl,vf610-i2c"; 283 compatible = "fsl,vf610-i2c";
414 reg = <0x40066000 0x1000>; 284 reg = <0x40066000 0x1000>;
415 interrupts =<0 71 0x04>; 285 interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clks VF610_CLK_I2C0>; 286 clocks = <&clks VF610_CLK_I2C0>;
417 clock-names = "ipg"; 287 clock-names = "ipg";
288 dmas = <&edma0 0 50>,
289 <&edma0 0 51>;
290 dma-names = "rx","tx";
418 status = "disabled"; 291 status = "disabled";
419 }; 292 };
420 293
@@ -432,10 +305,25 @@
432 reg = <0x40080000 0x80000>; 305 reg = <0x40080000 0x80000>;
433 ranges; 306 ranges;
434 307
308 edma1: dma-controller@40098000 {
309 #dma-cells = <2>;
310 compatible = "fsl,vf610-edma";
311 reg = <0x40098000 0x2000>,
312 <0x400a1000 0x1000>,
313 <0x400a2000 0x1000>;
314 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
315 <0 11 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-names = "edma-tx", "edma-err";
317 dma-channels = <32>;
318 clock-names = "dmamux0", "dmamux1";
319 clocks = <&clks VF610_CLK_DMAMUX2>,
320 <&clks VF610_CLK_DMAMUX3>;
321 };
322
435 uart4: serial@400a9000 { 323 uart4: serial@400a9000 {
436 compatible = "fsl,vf610-lpuart"; 324 compatible = "fsl,vf610-lpuart";
437 reg = <0x400a9000 0x1000>; 325 reg = <0x400a9000 0x1000>;
438 interrupts = <0 65 0x04>; 326 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&clks VF610_CLK_UART4>; 327 clocks = <&clks VF610_CLK_UART4>;
440 clock-names = "ipg"; 328 clock-names = "ipg";
441 status = "disabled"; 329 status = "disabled";
@@ -444,16 +332,25 @@
444 uart5: serial@400aa000 { 332 uart5: serial@400aa000 {
445 compatible = "fsl,vf610-lpuart"; 333 compatible = "fsl,vf610-lpuart";
446 reg = <0x400aa000 0x1000>; 334 reg = <0x400aa000 0x1000>;
447 interrupts = <0 66 0x04>; 335 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clks VF610_CLK_UART5>; 336 clocks = <&clks VF610_CLK_UART5>;
449 clock-names = "ipg"; 337 clock-names = "ipg";
450 status = "disabled"; 338 status = "disabled";
451 }; 339 };
452 340
341 adc1: adc@400bb000 {
342 compatible = "fsl,vf610-adc";
343 reg = <0x400bb000 0x1000>;
344 interrupts = <0 54 0x04>;
345 clocks = <&clks VF610_CLK_ADC1>;
346 clock-names = "adc";
347 status = "disabled";
348 };
349
453 fec0: ethernet@400d0000 { 350 fec0: ethernet@400d0000 {
454 compatible = "fsl,mvf600-fec"; 351 compatible = "fsl,mvf600-fec";
455 reg = <0x400d0000 0x1000>; 352 reg = <0x400d0000 0x1000>;
456 interrupts = <0 78 0x04>; 353 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clks VF610_CLK_ENET0>, 354 clocks = <&clks VF610_CLK_ENET0>,
458 <&clks VF610_CLK_ENET0>, 355 <&clks VF610_CLK_ENET0>,
459 <&clks VF610_CLK_ENET>; 356 <&clks VF610_CLK_ENET>;
@@ -464,7 +361,7 @@
464 fec1: ethernet@400d1000 { 361 fec1: ethernet@400d1000 {
465 compatible = "fsl,mvf600-fec"; 362 compatible = "fsl,mvf600-fec";
466 reg = <0x400d1000 0x1000>; 363 reg = <0x400d1000 0x1000>;
467 interrupts = <0 79 0x04>; 364 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&clks VF610_CLK_ENET1>, 365 clocks = <&clks VF610_CLK_ENET1>,
469 <&clks VF610_CLK_ENET1>, 366 <&clks VF610_CLK_ENET1>,
470 <&clks VF610_CLK_ENET>; 367 <&clks VF610_CLK_ENET>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 789d0bacc110..511180769af5 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -129,29 +129,28 @@
129 } ; 129 } ;
130 130
131 slcr: slcr@f8000000 { 131 slcr: slcr@f8000000 {
132 compatible = "xlnx,zynq-slcr"; 132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "xlnx,zynq-slcr", "syscon";
133 reg = <0xF8000000 0x1000>; 135 reg = <0xF8000000 0x1000>;
134 136 ranges;
135 clocks { 137 clkc: clkc@100 {
136 #address-cells = <1>; 138 #clock-cells = <1>;
137 #size-cells = <0>; 139 compatible = "xlnx,ps7-clkc";
138 140 ps-clk-frequency = <33333333>;
139 clkc: clkc { 141 fclk-enable = <0>;
140 #clock-cells = <1>; 142 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
141 compatible = "xlnx,ps7-clkc"; 143 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
142 ps-clk-frequency = <33333333>; 144 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
143 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 145 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
144 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 146 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
145 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 147 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
146 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 148 "gem1_aper", "sdio0_aper", "sdio1_aper",
147 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 149 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
148 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 150 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
149 "gem1_aper", "sdio0_aper", "sdio1_aper", 151 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
150 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 152 "dbg_trc", "dbg_apb";
151 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 153 reg = <0x100 0x100>;
152 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
153 "dbg_trc", "dbg_apb";
154 };
155 }; 154 };
156 }; 155 };
157 156
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 10:24:35 -0400