diff options
Diffstat (limited to 'arch/arm/plat-samsung/s5p-sleep.S')
-rw-r--r-- | arch/arm/plat-samsung/s5p-sleep.S | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index a030e7301da8..c5001659bdf8 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S | |||
@@ -23,18 +23,7 @@ | |||
23 | 23 | ||
24 | #include <linux/linkage.h> | 24 | #include <linux/linkage.h> |
25 | #include <asm/asm-offsets.h> | 25 | #include <asm/asm-offsets.h> |
26 | #include <asm/hardware/cache-l2x0.h> | ||
27 | 26 | ||
28 | #define CPU_MASK 0xff0ffff0 | ||
29 | #define CPU_CORTEX_A9 0x410fc090 | ||
30 | |||
31 | /* | ||
32 | * The following code is located into the .data section. This is to | ||
33 | * allow l2x0_regs_phys to be accessed with a relative load while we | ||
34 | * can't rely on any MMU translation. We could have put l2x0_regs_phys | ||
35 | * in the .text section as well, but some setups might insist on it to | ||
36 | * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) | ||
37 | */ | ||
38 | .data | 27 | .data |
39 | .align | 28 | .align |
40 | 29 | ||
@@ -53,37 +42,5 @@ | |||
53 | */ | 42 | */ |
54 | 43 | ||
55 | ENTRY(s3c_cpu_resume) | 44 | ENTRY(s3c_cpu_resume) |
56 | #ifdef CONFIG_CACHE_L2X0 | ||
57 | mrc p15, 0, r0, c0, c0, 0 | ||
58 | ldr r1, =CPU_MASK | ||
59 | and r0, r0, r1 | ||
60 | ldr r1, =CPU_CORTEX_A9 | ||
61 | cmp r0, r1 | ||
62 | bne resume_l2on | ||
63 | adr r0, l2x0_regs_phys | ||
64 | ldr r0, [r0] | ||
65 | ldr r1, [r0, #L2X0_R_PHY_BASE] | ||
66 | ldr r2, [r1, #L2X0_CTRL] | ||
67 | tst r2, #0x1 | ||
68 | bne resume_l2on | ||
69 | ldr r2, [r0, #L2X0_R_AUX_CTRL] | ||
70 | str r2, [r1, #L2X0_AUX_CTRL] | ||
71 | ldr r2, [r0, #L2X0_R_TAG_LATENCY] | ||
72 | str r2, [r1, #L2X0_TAG_LATENCY_CTRL] | ||
73 | ldr r2, [r0, #L2X0_R_DATA_LATENCY] | ||
74 | str r2, [r1, #L2X0_DATA_LATENCY_CTRL] | ||
75 | ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] | ||
76 | str r2, [r1, #L2X0_PREFETCH_CTRL] | ||
77 | ldr r2, [r0, #L2X0_R_PWR_CTRL] | ||
78 | str r2, [r1, #L2X0_POWER_CTRL] | ||
79 | mov r2, #1 | ||
80 | str r2, [r1, #L2X0_CTRL] | ||
81 | resume_l2on: | ||
82 | #endif | ||
83 | b cpu_resume | 45 | b cpu_resume |
84 | ENDPROC(s3c_cpu_resume) | 46 | ENDPROC(s3c_cpu_resume) |
85 | #ifdef CONFIG_CACHE_L2X0 | ||
86 | .globl l2x0_regs_phys | ||
87 | l2x0_regs_phys: | ||
88 | .long 0 | ||
89 | #endif | ||