diff options
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi')
-rw-r--r-- | arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi index a93c55a88560..0b8ccc5b4a46 100644 --- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | |||
@@ -67,61 +67,73 @@ | |||
67 | cpu0: PowerPC,e6500@0 { | 67 | cpu0: PowerPC,e6500@0 { |
68 | device_type = "cpu"; | 68 | device_type = "cpu"; |
69 | reg = <0 1>; | 69 | reg = <0 1>; |
70 | clocks = <&mux0>; | ||
70 | next-level-cache = <&L2_1>; | 71 | next-level-cache = <&L2_1>; |
71 | }; | 72 | }; |
72 | cpu1: PowerPC,e6500@2 { | 73 | cpu1: PowerPC,e6500@2 { |
73 | device_type = "cpu"; | 74 | device_type = "cpu"; |
74 | reg = <2 3>; | 75 | reg = <2 3>; |
76 | clocks = <&mux0>; | ||
75 | next-level-cache = <&L2_1>; | 77 | next-level-cache = <&L2_1>; |
76 | }; | 78 | }; |
77 | cpu2: PowerPC,e6500@4 { | 79 | cpu2: PowerPC,e6500@4 { |
78 | device_type = "cpu"; | 80 | device_type = "cpu"; |
79 | reg = <4 5>; | 81 | reg = <4 5>; |
82 | clocks = <&mux0>; | ||
80 | next-level-cache = <&L2_1>; | 83 | next-level-cache = <&L2_1>; |
81 | }; | 84 | }; |
82 | cpu3: PowerPC,e6500@6 { | 85 | cpu3: PowerPC,e6500@6 { |
83 | device_type = "cpu"; | 86 | device_type = "cpu"; |
84 | reg = <6 7>; | 87 | reg = <6 7>; |
88 | clocks = <&mux0>; | ||
85 | next-level-cache = <&L2_1>; | 89 | next-level-cache = <&L2_1>; |
86 | }; | 90 | }; |
87 | cpu4: PowerPC,e6500@8 { | 91 | cpu4: PowerPC,e6500@8 { |
88 | device_type = "cpu"; | 92 | device_type = "cpu"; |
89 | reg = <8 9>; | 93 | reg = <8 9>; |
94 | clocks = <&mux1>; | ||
90 | next-level-cache = <&L2_2>; | 95 | next-level-cache = <&L2_2>; |
91 | }; | 96 | }; |
92 | cpu5: PowerPC,e6500@10 { | 97 | cpu5: PowerPC,e6500@10 { |
93 | device_type = "cpu"; | 98 | device_type = "cpu"; |
94 | reg = <10 11>; | 99 | reg = <10 11>; |
100 | clocks = <&mux1>; | ||
95 | next-level-cache = <&L2_2>; | 101 | next-level-cache = <&L2_2>; |
96 | }; | 102 | }; |
97 | cpu6: PowerPC,e6500@12 { | 103 | cpu6: PowerPC,e6500@12 { |
98 | device_type = "cpu"; | 104 | device_type = "cpu"; |
99 | reg = <12 13>; | 105 | reg = <12 13>; |
106 | clocks = <&mux1>; | ||
100 | next-level-cache = <&L2_2>; | 107 | next-level-cache = <&L2_2>; |
101 | }; | 108 | }; |
102 | cpu7: PowerPC,e6500@14 { | 109 | cpu7: PowerPC,e6500@14 { |
103 | device_type = "cpu"; | 110 | device_type = "cpu"; |
104 | reg = <14 15>; | 111 | reg = <14 15>; |
112 | clocks = <&mux1>; | ||
105 | next-level-cache = <&L2_2>; | 113 | next-level-cache = <&L2_2>; |
106 | }; | 114 | }; |
107 | cpu8: PowerPC,e6500@16 { | 115 | cpu8: PowerPC,e6500@16 { |
108 | device_type = "cpu"; | 116 | device_type = "cpu"; |
109 | reg = <16 17>; | 117 | reg = <16 17>; |
118 | clocks = <&mux2>; | ||
110 | next-level-cache = <&L2_3>; | 119 | next-level-cache = <&L2_3>; |
111 | }; | 120 | }; |
112 | cpu9: PowerPC,e6500@18 { | 121 | cpu9: PowerPC,e6500@18 { |
113 | device_type = "cpu"; | 122 | device_type = "cpu"; |
114 | reg = <18 19>; | 123 | reg = <18 19>; |
124 | clocks = <&mux2>; | ||
115 | next-level-cache = <&L2_3>; | 125 | next-level-cache = <&L2_3>; |
116 | }; | 126 | }; |
117 | cpu10: PowerPC,e6500@20 { | 127 | cpu10: PowerPC,e6500@20 { |
118 | device_type = "cpu"; | 128 | device_type = "cpu"; |
119 | reg = <20 21>; | 129 | reg = <20 21>; |
130 | clocks = <&mux2>; | ||
120 | next-level-cache = <&L2_3>; | 131 | next-level-cache = <&L2_3>; |
121 | }; | 132 | }; |
122 | cpu11: PowerPC,e6500@22 { | 133 | cpu11: PowerPC,e6500@22 { |
123 | device_type = "cpu"; | 134 | device_type = "cpu"; |
124 | reg = <22 23>; | 135 | reg = <22 23>; |
136 | clocks = <&mux2>; | ||
125 | next-level-cache = <&L2_3>; | 137 | next-level-cache = <&L2_3>; |
126 | }; | 138 | }; |
127 | }; | 139 | }; |