diff options
Diffstat (limited to 'Documentation/devicetree')
475 files changed, 167 insertions, 24783 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt deleted file mode 100644 index ecdb57d69db..00000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt +++ /dev/null | |||
@@ -1,11 +0,0 @@ | |||
1 | Altera SOCFPGA Reset Manager | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "altr,rst-mgr" | ||
5 | - reg : Should contain 1 register ranges(address and length) | ||
6 | |||
7 | Example: | ||
8 | rstmgr@ffd05000 { | ||
9 | compatible = "altr,rst-mgr"; | ||
10 | reg = <0xffd05000 0x1000>; | ||
11 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt deleted file mode 100644 index 07c65e3cdcb..00000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt +++ /dev/null | |||
@@ -1,11 +0,0 @@ | |||
1 | Altera SOCFPGA System Manager | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "altr,sys-mgr" | ||
5 | - reg : Should contain 1 register ranges(address and length) | ||
6 | |||
7 | Example: | ||
8 | sysmgr@ffd08000 { | ||
9 | compatible = "altr,sys-mgr"; | ||
10 | reg = <0xffd08000 0x1000>; | ||
11 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt deleted file mode 100644 index 52478c83d0c..00000000000 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | * ARM architected timer | ||
2 | |||
3 | ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which | ||
4 | provides per-cpu timers. | ||
5 | |||
6 | The timer is attached to a GIC to deliver its per-processor interrupts. | ||
7 | |||
8 | ** Timer node properties: | ||
9 | |||
10 | - compatible : Should at least contain "arm,armv7-timer". | ||
11 | |||
12 | - interrupts : Interrupt list for secure, non-secure, virtual and | ||
13 | hypervisor timers, in that order. | ||
14 | |||
15 | - clock-frequency : The frequency of the main counter, in Hz. Optional. | ||
16 | |||
17 | Example: | ||
18 | |||
19 | timer { | ||
20 | compatible = "arm,cortex-a15-timer", | ||
21 | "arm,armv7-timer"; | ||
22 | interrupts = <1 13 0xf08>, | ||
23 | <1 14 0xf08>, | ||
24 | <1 11 0xf08>, | ||
25 | <1 10 0xf08>; | ||
26 | clock-frequency = <100000000>; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index db5858e32d3..91f26148af7 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards | |||
@@ -1,19 +1,3 @@ | |||
1 | ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform) | ||
2 | ----------------------------------------------------------------------------- | ||
3 | ARM's oldest Linux-supported platform with connectors for different core | ||
4 | tiles of ARMv4, ARMv5 and ARMv6 type. | ||
5 | |||
6 | Required properties (in root node): | ||
7 | compatible = "arm,integrator-ap"; /* Application Platform */ | ||
8 | compatible = "arm,integrator-cp"; /* Compact Platform */ | ||
9 | |||
10 | FPGA type interrupt controllers, see the versatile-fpga-irq binding doc. | ||
11 | |||
12 | In the root node the Integrator/CP must have a /cpcon node pointing | ||
13 | to the CP control registers, and the Integrator/AP must have a | ||
14 | /syscon node pointing to the Integrator/AP system controller. | ||
15 | |||
16 | |||
17 | ARM Versatile Application and Platform Baseboards | 1 | ARM Versatile Application and Platform Baseboards |
18 | ------------------------------------------------- | 2 | ------------------------------------------------- |
19 | ARM's development hardware platform with connectors for customizable | 3 | ARM's development hardware platform with connectors for customizable |
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt deleted file mode 100644 index 61df564c0d2..00000000000 --- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | Marvell Armada 370 and Armada XP Interrupt Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible: Should be "marvell,mpic" | ||
6 | - interrupt-controller: Identifies the node as an interrupt controller. | ||
7 | - #interrupt-cells: The number of cells to define the interrupts. Should be 1. | ||
8 | The cell is the IRQ number | ||
9 | |||
10 | - reg: Should contain PMIC registers location and length. First pair | ||
11 | for the main interrupt registers, second pair for the per-CPU | ||
12 | interrupt registers. For this last pair, to be compliant with SMP | ||
13 | support, the "virtual" must be use (For the record, these registers | ||
14 | automatically map to the interrupt controller registers of the | ||
15 | current CPU) | ||
16 | |||
17 | |||
18 | |||
19 | Example: | ||
20 | |||
21 | mpic: interrupt-controller@d0020000 { | ||
22 | compatible = "marvell,mpic"; | ||
23 | #interrupt-cells = <1>; | ||
24 | #address-cells = <1>; | ||
25 | #size-cells = <1>; | ||
26 | interrupt-controller; | ||
27 | reg = <0xd0020a00 0x1d0>, | ||
28 | <0xd0021070 0x58>; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt deleted file mode 100644 index 926b4d6aae7..00000000000 --- a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | Power Management Service Unit(PMSU) | ||
2 | ----------------------------------- | ||
3 | Available on Marvell SOCs: Armada 370 and Armada XP | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible: "marvell,armada-370-xp-pmsu" | ||
8 | |||
9 | - reg: Should contain PMSU registers location and length. First pair | ||
10 | for the per-CPU SW Reset Control registers, second pair for the | ||
11 | Power Management Service Unit. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | armada-370-xp-pmsu@d0022000 { | ||
16 | compatible = "marvell,armada-370-xp-pmsu"; | ||
17 | reg = <0xd0022100 0x430>, | ||
18 | <0xd0020800 0x20>; | ||
19 | }; | ||
20 | |||
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt deleted file mode 100644 index 64830118b01..00000000000 --- a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | Marvell Armada 370 and Armada XP Global Timers | ||
2 | ---------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible: Should be "marvell,armada-370-xp-timer" | ||
6 | - interrupts: Should contain the list of Global Timer interrupts | ||
7 | - reg: Should contain the base address of the Global Timer registers | ||
8 | - clocks: clock driving the timer hardware | ||
9 | |||
10 | Optional properties: | ||
11 | - marvell,timer-25Mhz: Tells whether the Global timer supports the 25 | ||
12 | Mhz fixed mode (available on Armada XP and not on Armada 370) | ||
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/armada-370-xp.txt deleted file mode 100644 index c6ed90ea6e1..00000000000 --- a/Documentation/devicetree/bindings/arm/armada-370-xp.txt +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | Marvell Armada 370 and Armada XP Platforms Device Tree Bindings | ||
2 | --------------------------------------------------------------- | ||
3 | |||
4 | Boards with a SoC of the Marvell Armada 370 and Armada XP families | ||
5 | shall have the following property: | ||
6 | |||
7 | Required root node property: | ||
8 | |||
9 | compatible: must contain "marvell,armada-370-xp" | ||
10 | |||
11 | In addition, boards using the Marvell Armada 370 SoC shall have the | ||
12 | following property: | ||
13 | |||
14 | Required root node property: | ||
15 | |||
16 | compatible: must contain "marvell,armada370" | ||
17 | |||
18 | In addition, boards using the Marvell Armada XP SoC shall have the | ||
19 | following property: | ||
20 | |||
21 | Required root node property: | ||
22 | |||
23 | compatible: must contain "marvell,armadaxp" | ||
24 | |||
diff --git a/Documentation/devicetree/bindings/arm/atmel-adc.txt b/Documentation/devicetree/bindings/arm/atmel-adc.txt deleted file mode 100644 index c63097d6afe..00000000000 --- a/Documentation/devicetree/bindings/arm/atmel-adc.txt +++ /dev/null | |||
@@ -1,65 +0,0 @@ | |||
1 | * AT91's Analog to Digital Converter (ADC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "atmel,at91sam9260-adc" | ||
5 | - reg: Should contain ADC registers location and length | ||
6 | - interrupts: Should contain the IRQ line for the ADC | ||
7 | - atmel,adc-channel-base: Offset of the first channel data register | ||
8 | - atmel,adc-channels-used: Bitmask of the channels muxed and enable for this | ||
9 | device | ||
10 | - atmel,adc-drdy-mask: Mask of the DRDY interruption in the ADC | ||
11 | - atmel,adc-num-channels: Number of channels available in the ADC | ||
12 | - atmel,adc-startup-time: Startup Time of the ADC in microseconds as | ||
13 | defined in the datasheet | ||
14 | - atmel,adc-status-register: Offset of the Interrupt Status Register | ||
15 | - atmel,adc-trigger-register: Offset of the Trigger Register | ||
16 | - atmel,adc-vref: Reference voltage in millivolts for the conversions | ||
17 | |||
18 | Optional properties: | ||
19 | - atmel,adc-use-external: Boolean to enable of external triggers | ||
20 | |||
21 | Optional trigger Nodes: | ||
22 | - Required properties: | ||
23 | * trigger-name: Name of the trigger exposed to the user | ||
24 | * trigger-value: Value to put in the Trigger register | ||
25 | to activate this trigger | ||
26 | - Optional properties: | ||
27 | * trigger-external: Is the trigger an external trigger? | ||
28 | |||
29 | Examples: | ||
30 | adc0: adc@fffb0000 { | ||
31 | compatible = "atmel,at91sam9260-adc"; | ||
32 | reg = <0xfffb0000 0x100>; | ||
33 | interrupts = <20 4>; | ||
34 | atmel,adc-channel-base = <0x30>; | ||
35 | atmel,adc-channels-used = <0xff>; | ||
36 | atmel,adc-drdy-mask = <0x10000>; | ||
37 | atmel,adc-num-channels = <8>; | ||
38 | atmel,adc-startup-time = <40>; | ||
39 | atmel,adc-status-register = <0x1c>; | ||
40 | atmel,adc-trigger-register = <0x08>; | ||
41 | atmel,adc-use-external; | ||
42 | atmel,adc-vref = <3300>; | ||
43 | |||
44 | trigger@0 { | ||
45 | trigger-name = "external-rising"; | ||
46 | trigger-value = <0x1>; | ||
47 | trigger-external; | ||
48 | }; | ||
49 | trigger@1 { | ||
50 | trigger-name = "external-falling"; | ||
51 | trigger-value = <0x2>; | ||
52 | trigger-external; | ||
53 | }; | ||
54 | |||
55 | trigger@2 { | ||
56 | trigger-name = "external-any"; | ||
57 | trigger-value = <0x3>; | ||
58 | trigger-external; | ||
59 | }; | ||
60 | |||
61 | trigger@3 { | ||
62 | trigger-name = "continuous"; | ||
63 | trigger-value = <0x6>; | ||
64 | }; | ||
65 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt deleted file mode 100644 index 19078bf5cca..00000000000 --- a/Documentation/devicetree/bindings/arm/atmel-aic.txt +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | * Advanced Interrupt Controller (AIC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "atmel,<chip>-aic" | ||
5 | - interrupt-controller: Identifies the node as an interrupt controller. | ||
6 | - interrupt-parent: For single AIC system, it is an empty property. | ||
7 | - #interrupt-cells: The number of cells to define the interrupts. It sould be 3. | ||
8 | The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet). | ||
9 | The second cell is used to specify flags: | ||
10 | bits[3:0] trigger type and level flags: | ||
11 | 1 = low-to-high edge triggered. | ||
12 | 2 = high-to-low edge triggered. | ||
13 | 4 = active high level-sensitive. | ||
14 | 8 = active low level-sensitive. | ||
15 | Valid combinations are 1, 2, 3, 4, 8. | ||
16 | Default flag for internal sources should be set to 4 (active high). | ||
17 | The third cell is used to specify the irq priority from 0 (lowest) to 7 | ||
18 | (highest). | ||
19 | - reg: Should contain AIC registers location and length | ||
20 | - atmel,external-irqs: u32 array of external irqs. | ||
21 | |||
22 | Examples: | ||
23 | /* | ||
24 | * AIC | ||
25 | */ | ||
26 | aic: interrupt-controller@fffff000 { | ||
27 | compatible = "atmel,at91rm9200-aic"; | ||
28 | interrupt-controller; | ||
29 | interrupt-parent; | ||
30 | #interrupt-cells = <3>; | ||
31 | reg = <0xfffff000 0x200>; | ||
32 | }; | ||
33 | |||
34 | /* | ||
35 | * An interrupt generating device that is wired to an AIC. | ||
36 | */ | ||
37 | dma: dma-controller@ffffec00 { | ||
38 | compatible = "atmel,at91sam9g45-dma"; | ||
39 | reg = <0xffffec00 0x200>; | ||
40 | interrupts = <21 4 5>; | ||
41 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt deleted file mode 100644 index 1196290082d..00000000000 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ /dev/null | |||
@@ -1,98 +0,0 @@ | |||
1 | Atmel AT91 device tree bindings. | ||
2 | ================================ | ||
3 | |||
4 | PIT Timer required properties: | ||
5 | - compatible: Should be "atmel,at91sam9260-pit" | ||
6 | - reg: Should contain registers location and length | ||
7 | - interrupts: Should contain interrupt for the PIT which is the IRQ line | ||
8 | shared across all System Controller members. | ||
9 | |||
10 | System Timer (ST) required properties: | ||
11 | - compatible: Should be "atmel,at91rm9200-st" | ||
12 | - reg: Should contain registers location and length | ||
13 | - interrupts: Should contain interrupt for the ST which is the IRQ line | ||
14 | shared across all System Controller members. | ||
15 | |||
16 | TC/TCLIB Timer required properties: | ||
17 | - compatible: Should be "atmel,<chip>-tcb". | ||
18 | <chip> can be "at91rm9200" or "at91sam9x5" | ||
19 | - reg: Should contain registers location and length | ||
20 | - interrupts: Should contain all interrupts for the TC block | ||
21 | Note that you can specify several interrupt cells if the TC | ||
22 | block has one interrupt per channel. | ||
23 | |||
24 | Examples: | ||
25 | |||
26 | One interrupt per TC block: | ||
27 | tcb0: timer@fff7c000 { | ||
28 | compatible = "atmel,at91rm9200-tcb"; | ||
29 | reg = <0xfff7c000 0x100>; | ||
30 | interrupts = <18 4>; | ||
31 | }; | ||
32 | |||
33 | One interrupt per TC channel in a TC block: | ||
34 | tcb1: timer@fffdc000 { | ||
35 | compatible = "atmel,at91rm9200-tcb"; | ||
36 | reg = <0xfffdc000 0x100>; | ||
37 | interrupts = <26 4 27 4 28 4>; | ||
38 | }; | ||
39 | |||
40 | RSTC Reset Controller required properties: | ||
41 | - compatible: Should be "atmel,<chip>-rstc". | ||
42 | <chip> can be "at91sam9260" or "at91sam9g45" | ||
43 | - reg: Should contain registers location and length | ||
44 | |||
45 | Example: | ||
46 | |||
47 | rstc@fffffd00 { | ||
48 | compatible = "atmel,at91sam9260-rstc"; | ||
49 | reg = <0xfffffd00 0x10>; | ||
50 | }; | ||
51 | |||
52 | RAMC SDRAM/DDR Controller required properties: | ||
53 | - compatible: Should be "atmel,at91sam9260-sdramc", | ||
54 | "atmel,at91sam9g45-ddramc", | ||
55 | - reg: Should contain registers location and length | ||
56 | For at91sam9263 and at91sam9g45 you must specify 2 entries. | ||
57 | |||
58 | Examples: | ||
59 | |||
60 | ramc0: ramc@ffffe800 { | ||
61 | compatible = "atmel,at91sam9g45-ddramc"; | ||
62 | reg = <0xffffe800 0x200>; | ||
63 | }; | ||
64 | |||
65 | ramc0: ramc@ffffe400 { | ||
66 | compatible = "atmel,at91sam9g45-ddramc"; | ||
67 | reg = <0xffffe400 0x200 | ||
68 | 0xffffe600 0x200>; | ||
69 | }; | ||
70 | |||
71 | SHDWC Shutdown Controller | ||
72 | |||
73 | required properties: | ||
74 | - compatible: Should be "atmel,<chip>-shdwc". | ||
75 | <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5". | ||
76 | - reg: Should contain registers location and length | ||
77 | |||
78 | optional properties: | ||
79 | - atmel,wakeup-mode: String, operation mode of the wakeup mode. | ||
80 | Supported values are: "none", "high", "low", "any". | ||
81 | - atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). | ||
82 | |||
83 | optional at91sam9260 properties: | ||
84 | - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. | ||
85 | |||
86 | optional at91sam9rl properties: | ||
87 | - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. | ||
88 | - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. | ||
89 | |||
90 | optional at91sam9x5 properties: | ||
91 | - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. | ||
92 | |||
93 | Example: | ||
94 | |||
95 | rstc@fffffd00 { | ||
96 | compatible = "atmel,at91sam9260-rstc"; | ||
97 | reg = <0xfffffd00 0x10>; | ||
98 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt deleted file mode 100644 index 389bed5056e..00000000000 --- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt +++ /dev/null | |||
@@ -1,11 +0,0 @@ | |||
1 | * Power Management Controller (PMC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "atmel,at91rm9200-pmc" | ||
5 | - reg: Should contain PMC registers location and length | ||
6 | |||
7 | Examples: | ||
8 | pmc: pmc@fffffc00 { | ||
9 | compatible = "atmel,at91rm9200-pmc"; | ||
10 | reg = <0xfffffc00 0x100>; | ||
11 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt deleted file mode 100644 index fb7b5cd2652..00000000000 --- a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt +++ /dev/null | |||
@@ -1,9 +0,0 @@ | |||
1 | Broadcom BCM11351 device tree bindings | ||
2 | ------------------------------------------- | ||
3 | |||
4 | Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140, | ||
5 | bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties: | ||
6 | |||
7 | Required root node property: | ||
8 | |||
9 | compatible = "bcm,bcm11351"; | ||
diff --git a/Documentation/devicetree/bindings/arm/bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm2835.txt deleted file mode 100644 index ac683480c48..00000000000 --- a/Documentation/devicetree/bindings/arm/bcm2835.txt +++ /dev/null | |||
@@ -1,8 +0,0 @@ | |||
1 | Broadcom BCM2835 device tree bindings | ||
2 | ------------------------------------------- | ||
3 | |||
4 | Boards with the BCM2835 SoC shall have the following properties: | ||
5 | |||
6 | Required root node property: | ||
7 | |||
8 | compatible = "brcm,bcm2835"; | ||
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt deleted file mode 100644 index 25fcf96795c..00000000000 --- a/Documentation/devicetree/bindings/arm/calxeda.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | Calxeda Platforms Device Tree Bindings | ||
2 | ----------------------------------------------- | ||
3 | |||
4 | Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the | ||
5 | following properties. | ||
6 | |||
7 | Required root node properties: | ||
8 | - compatible = "calxeda,highbank"; | ||
9 | |||
10 | |||
11 | Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following | ||
12 | properties. | ||
13 | |||
14 | Required root node properties: | ||
15 | - compatible = "calxeda,ecx-2000"; | ||
diff --git a/Documentation/devicetree/bindings/arm/calxeda/combophy.txt b/Documentation/devicetree/bindings/arm/calxeda/combophy.txt deleted file mode 100644 index 6622bdb2e8b..00000000000 --- a/Documentation/devicetree/bindings/arm/calxeda/combophy.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | Calxeda Highbank Combination Phys for SATA | ||
2 | |||
3 | Properties: | ||
4 | - compatible : Should be "calxeda,hb-combophy" | ||
5 | - #phy-cells: Should be 1. | ||
6 | - reg : Address and size for Combination Phy registers. | ||
7 | - phydev: device ID for programming the combophy. | ||
8 | |||
9 | Example: | ||
10 | |||
11 | combophy5: combo-phy@fff5d000 { | ||
12 | compatible = "calxeda,hb-combophy"; | ||
13 | #phy-cells = <1>; | ||
14 | reg = <0xfff5d000 0x1000>; | ||
15 | phydev = <31>; | ||
16 | }; | ||
17 | |||
diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt deleted file mode 100644 index 94e642a33db..00000000000 --- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | Calxeda Highbank L2 cache ECC | ||
2 | |||
3 | Properties: | ||
4 | - compatible : Should be "calxeda,hb-sregs-l2-ecc" | ||
5 | - reg : Address and size for ECC error interrupt clear registers. | ||
6 | - interrupts : Should be single bit error interrupt, then double bit error | ||
7 | interrupt. | ||
8 | |||
9 | Example: | ||
10 | |||
11 | sregs@fff3c200 { | ||
12 | compatible = "calxeda,hb-sregs-l2-ecc"; | ||
13 | reg = <0xfff3c200 0x100>; | ||
14 | interrupts = <0 71 4 0 72 4>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt b/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt deleted file mode 100644 index f770ac0893d..00000000000 --- a/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | Calxeda DDR memory controller | ||
2 | |||
3 | Properties: | ||
4 | - compatible : Should be "calxeda,hb-ddr-ctrl" | ||
5 | - reg : Address and size for DDR controller registers. | ||
6 | - interrupts : Interrupt for DDR controller. | ||
7 | |||
8 | Example: | ||
9 | |||
10 | memory-controller@fff00000 { | ||
11 | compatible = "calxeda,hb-ddr-ctrl"; | ||
12 | reg = <0xfff00000 0x1000>; | ||
13 | interrupts = <0 91 4>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt deleted file mode 100644 index 17d8cd10755..00000000000 --- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | Coherency fabric | ||
2 | ---------------- | ||
3 | Available on Marvell SOCs: Armada 370 and Armada XP | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible: "marvell,coherency-fabric" | ||
8 | |||
9 | - reg: Should contain coherency fabric registers location and | ||
10 | length. First pair for the coherency fabric registers, second pair | ||
11 | for the per-CPU fabric registers registers. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | coherency-fabric@d0020200 { | ||
16 | compatible = "marvell,coherency-fabric"; | ||
17 | reg = <0xd0020200 0xb0>, | ||
18 | <0xd0021810 0x1c>; | ||
19 | |||
20 | }; | ||
21 | |||
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt deleted file mode 100644 index f32494dbfe1..00000000000 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ /dev/null | |||
@@ -1,77 +0,0 @@ | |||
1 | * ARM CPUs binding description | ||
2 | |||
3 | The device tree allows to describe the layout of CPUs in a system through | ||
4 | the "cpus" node, which in turn contains a number of subnodes (ie "cpu") | ||
5 | defining properties for every cpu. | ||
6 | |||
7 | Bindings for CPU nodes follow the ePAPR standard, available from: | ||
8 | |||
9 | http://devicetree.org | ||
10 | |||
11 | For the ARM architecture every CPU node must contain the following properties: | ||
12 | |||
13 | - device_type: must be "cpu" | ||
14 | - reg: property matching the CPU MPIDR[23:0] register bits | ||
15 | reg[31:24] bits must be set to 0 | ||
16 | - compatible: should be one of: | ||
17 | "arm,arm1020" | ||
18 | "arm,arm1020e" | ||
19 | "arm,arm1022" | ||
20 | "arm,arm1026" | ||
21 | "arm,arm720" | ||
22 | "arm,arm740" | ||
23 | "arm,arm7tdmi" | ||
24 | "arm,arm920" | ||
25 | "arm,arm922" | ||
26 | "arm,arm925" | ||
27 | "arm,arm926" | ||
28 | "arm,arm940" | ||
29 | "arm,arm946" | ||
30 | "arm,arm9tdmi" | ||
31 | "arm,cortex-a5" | ||
32 | "arm,cortex-a7" | ||
33 | "arm,cortex-a8" | ||
34 | "arm,cortex-a9" | ||
35 | "arm,cortex-a15" | ||
36 | "arm,arm1136" | ||
37 | "arm,arm1156" | ||
38 | "arm,arm1176" | ||
39 | "arm,arm11mpcore" | ||
40 | "faraday,fa526" | ||
41 | "intel,sa110" | ||
42 | "intel,sa1100" | ||
43 | "marvell,feroceon" | ||
44 | "marvell,mohawk" | ||
45 | "marvell,xsc3" | ||
46 | "marvell,xscale" | ||
47 | |||
48 | Example: | ||
49 | |||
50 | cpus { | ||
51 | #size-cells = <0>; | ||
52 | #address-cells = <1>; | ||
53 | |||
54 | CPU0: cpu@0 { | ||
55 | device_type = "cpu"; | ||
56 | compatible = "arm,cortex-a15"; | ||
57 | reg = <0x0>; | ||
58 | }; | ||
59 | |||
60 | CPU1: cpu@1 { | ||
61 | device_type = "cpu"; | ||
62 | compatible = "arm,cortex-a15"; | ||
63 | reg = <0x1>; | ||
64 | }; | ||
65 | |||
66 | CPU2: cpu@100 { | ||
67 | device_type = "cpu"; | ||
68 | compatible = "arm,cortex-a7"; | ||
69 | reg = <0x100>; | ||
70 | }; | ||
71 | |||
72 | CPU3: cpu@101 { | ||
73 | device_type = "cpu"; | ||
74 | compatible = "arm,cortex-a7"; | ||
75 | reg = <0x101>; | ||
76 | }; | ||
77 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/davinci.txt b/Documentation/devicetree/bindings/arm/davinci.txt deleted file mode 100644 index cfaeda4274e..00000000000 --- a/Documentation/devicetree/bindings/arm/davinci.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | Texas Instruments DaVinci Platforms Device Tree Bindings | ||
2 | -------------------------------------------------------- | ||
3 | |||
4 | DA850/OMAP-L138/AM18x Evaluation Module (EVM) board | ||
5 | Required root node properties: | ||
6 | - compatible = "ti,da850-evm", "ti,da850"; | ||
7 | |||
8 | EnBW AM1808 based CMC board | ||
9 | Required root node properties: | ||
10 | - compatible = "enbw,cmc", "ti,da850; | ||
11 | |||
12 | Generic DaVinci Boards | ||
13 | ---------------------- | ||
14 | |||
15 | DA850/OMAP-L138/AM18x generic board | ||
16 | Required root node properties: | ||
17 | - compatible = "ti,da850"; | ||
diff --git a/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt b/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt deleted file mode 100644 index 597e8a089fe..00000000000 --- a/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | * TI Common Platform Interrupt Controller | ||
2 | |||
3 | Common Platform Interrupt Controller (cp_intc) is used on | ||
4 | OMAP-L1x SoCs and can support several configurable number | ||
5 | of interrupts. | ||
6 | |||
7 | Main node required properties: | ||
8 | |||
9 | - compatible : should be: | ||
10 | "ti,cp-intc" | ||
11 | - interrupt-controller : Identifies the node as an interrupt controller | ||
12 | - #interrupt-cells : Specifies the number of cells needed to encode an | ||
13 | interrupt source. The type shall be a <u32> and the value shall be 1. | ||
14 | |||
15 | The cell contains the interrupt number in the range [0-128]. | ||
16 | - ti,intc-size: Number of interrupts handled by the interrupt controller. | ||
17 | - reg: physical base address and size of the intc registers map. | ||
18 | |||
19 | Example: | ||
20 | |||
21 | intc: interrupt-controller@1 { | ||
22 | compatible = "ti,cp-intc"; | ||
23 | interrupt-controller; | ||
24 | #interrupt-cells = <1>; | ||
25 | ti,intc-size = <101>; | ||
26 | reg = <0xfffee000 0x2000>; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/davinci/nand.txt b/Documentation/devicetree/bindings/arm/davinci/nand.txt deleted file mode 100644 index 3545ea704b5..00000000000 --- a/Documentation/devicetree/bindings/arm/davinci/nand.txt +++ /dev/null | |||
@@ -1,46 +0,0 @@ | |||
1 | * Texas Instruments Davinci NAND | ||
2 | |||
3 | This file provides information, what the device node for the | ||
4 | davinci nand interface contain. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "ti,davinci-nand"; | ||
8 | - reg : contain 2 offset/length values: | ||
9 | - offset and length for the access window | ||
10 | - offset and length for accessing the aemif control registers | ||
11 | - ti,davinci-chipselect: Indicates on the davinci_nand driver which | ||
12 | chipselect is used for accessing the nand. | ||
13 | |||
14 | Recommended properties : | ||
15 | - ti,davinci-mask-ale: mask for ale | ||
16 | - ti,davinci-mask-cle: mask for cle | ||
17 | - ti,davinci-mask-chipsel: mask for chipselect | ||
18 | - ti,davinci-ecc-mode: ECC mode valid values for davinci driver: | ||
19 | - "none" | ||
20 | - "soft" | ||
21 | - "hw" | ||
22 | - ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4. | ||
23 | - ti,davinci-nand-buswidth: buswidth 8 or 16 | ||
24 | - ti,davinci-nand-use-bbt: use flash based bad block table support. | ||
25 | |||
26 | nand device bindings may contain additional sub-nodes describing | ||
27 | partitions of the address space. See partition.txt for more detail. | ||
28 | |||
29 | Example(da850 EVM ): | ||
30 | nand_cs3@62000000 { | ||
31 | compatible = "ti,davinci-nand"; | ||
32 | reg = <0x62000000 0x807ff | ||
33 | 0x68000000 0x8000>; | ||
34 | ti,davinci-chipselect = <1>; | ||
35 | ti,davinci-mask-ale = <0>; | ||
36 | ti,davinci-mask-cle = <0>; | ||
37 | ti,davinci-mask-chipsel = <0>; | ||
38 | ti,davinci-ecc-mode = "hw"; | ||
39 | ti,davinci-ecc-bits = <4>; | ||
40 | ti,davinci-nand-use-bbt; | ||
41 | |||
42 | partition@180000 { | ||
43 | label = "ubifs"; | ||
44 | reg = <0x180000 0x7e80000>; | ||
45 | }; | ||
46 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt deleted file mode 100644 index 5216b419016..00000000000 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | * Samsung Exynos Power Domains | ||
2 | |||
3 | Exynos processors include support for multiple power domains which are used | ||
4 | to gate power to one or more peripherals on the processor. | ||
5 | |||
6 | Required Properties: | ||
7 | - compatible: should be one of the following. | ||
8 | * samsung,exynos4210-pd - for exynos4210 type power domain. | ||
9 | - reg: physical base address of the controller and length of memory mapped | ||
10 | region. | ||
11 | |||
12 | Node of a device using power domains must have a samsung,power-domain property | ||
13 | defined with a phandle to respective power domain. | ||
14 | |||
15 | Example: | ||
16 | |||
17 | lcd0: power-domain-lcd0 { | ||
18 | compatible = "samsung,exynos4210-pd"; | ||
19 | reg = <0x10023C00 0x10>; | ||
20 | }; | ||
21 | |||
22 | Example of the node using power domain: | ||
23 | |||
24 | node { | ||
25 | /* ... */ | ||
26 | samsung,power-domain = <&lcd0>; | ||
27 | /* ... */ | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt deleted file mode 100644 index f79818711e8..00000000000 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ /dev/null | |||
@@ -1,68 +0,0 @@ | |||
1 | Freescale i.MX Platforms Device Tree Bindings | ||
2 | ----------------------------------------------- | ||
3 | |||
4 | i.MX23 Evaluation Kit | ||
5 | Required root node properties: | ||
6 | - compatible = "fsl,imx23-evk", "fsl,imx23"; | ||
7 | |||
8 | i.MX28 Evaluation Kit | ||
9 | Required root node properties: | ||
10 | - compatible = "fsl,imx28-evk", "fsl,imx28"; | ||
11 | |||
12 | i.MX51 Babbage Board | ||
13 | Required root node properties: | ||
14 | - compatible = "fsl,imx51-babbage", "fsl,imx51"; | ||
15 | |||
16 | i.MX53 Automotive Reference Design Board | ||
17 | Required root node properties: | ||
18 | - compatible = "fsl,imx53-ard", "fsl,imx53"; | ||
19 | |||
20 | i.MX53 Evaluation Kit | ||
21 | Required root node properties: | ||
22 | - compatible = "fsl,imx53-evk", "fsl,imx53"; | ||
23 | |||
24 | i.MX53 Quick Start Board | ||
25 | Required root node properties: | ||
26 | - compatible = "fsl,imx53-qsb", "fsl,imx53"; | ||
27 | |||
28 | i.MX53 Smart Mobile Reference Design Board | ||
29 | Required root node properties: | ||
30 | - compatible = "fsl,imx53-smd", "fsl,imx53"; | ||
31 | |||
32 | i.MX6 Quad Armadillo2 Board | ||
33 | Required root node properties: | ||
34 | - compatible = "fsl,imx6q-arm2", "fsl,imx6q"; | ||
35 | |||
36 | i.MX6 Quad SABRE Lite Board | ||
37 | Required root node properties: | ||
38 | - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; | ||
39 | |||
40 | i.MX6 Quad SABRE Smart Device Board | ||
41 | Required root node properties: | ||
42 | - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; | ||
43 | |||
44 | i.MX6 Quad SABRE Automotive Board | ||
45 | Required root node properties: | ||
46 | - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; | ||
47 | |||
48 | Generic i.MX boards | ||
49 | ------------------- | ||
50 | |||
51 | No iomux setup is done for these boards, so this must have been configured | ||
52 | by the bootloader for boards to work with the generic bindings. | ||
53 | |||
54 | i.MX27 generic board | ||
55 | Required root node properties: | ||
56 | - compatible = "fsl,imx27"; | ||
57 | |||
58 | i.MX51 generic board | ||
59 | Required root node properties: | ||
60 | - compatible = "fsl,imx51"; | ||
61 | |||
62 | i.MX53 generic board | ||
63 | Required root node properties: | ||
64 | - compatible = "fsl,imx53"; | ||
65 | |||
66 | i.MX6q generic board | ||
67 | Required root node properties: | ||
68 | - compatible = "fsl,imx6q"; | ||
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt deleted file mode 100644 index 62eb8df1e08..00000000000 --- a/Documentation/devicetree/bindings/arm/gic.txt +++ /dev/null | |||
@@ -1,90 +0,0 @@ | |||
1 | * ARM Generic Interrupt Controller | ||
2 | |||
3 | ARM SMP cores are often associated with a GIC, providing per processor | ||
4 | interrupts (PPI), shared processor interrupts (SPI) and software | ||
5 | generated interrupts (SGI). | ||
6 | |||
7 | Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. | ||
8 | Secondary GICs are cascaded into the upward interrupt controller and do not | ||
9 | have PPIs or SGIs. | ||
10 | |||
11 | Main node required properties: | ||
12 | |||
13 | - compatible : should be one of: | ||
14 | "arm,cortex-a15-gic" | ||
15 | "arm,cortex-a9-gic" | ||
16 | "arm,cortex-a7-gic" | ||
17 | "arm,arm11mp-gic" | ||
18 | - interrupt-controller : Identifies the node as an interrupt controller | ||
19 | - #interrupt-cells : Specifies the number of cells needed to encode an | ||
20 | interrupt source. The type shall be a <u32> and the value shall be 3. | ||
21 | |||
22 | The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI | ||
23 | interrupts. | ||
24 | |||
25 | The 2nd cell contains the interrupt number for the interrupt type. | ||
26 | SPI interrupts are in the range [0-987]. PPI interrupts are in the | ||
27 | range [0-15]. | ||
28 | |||
29 | The 3rd cell is the flags, encoded as follows: | ||
30 | bits[3:0] trigger type and level flags. | ||
31 | 1 = low-to-high edge triggered | ||
32 | 2 = high-to-low edge triggered | ||
33 | 4 = active high level-sensitive | ||
34 | 8 = active low level-sensitive | ||
35 | bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of | ||
36 | the 8 possible cpus attached to the GIC. A bit set to '1' indicated | ||
37 | the interrupt is wired to that CPU. Only valid for PPI interrupts. | ||
38 | |||
39 | - reg : Specifies base physical address(s) and size of the GIC registers. The | ||
40 | first region is the GIC distributor register base and size. The 2nd region is | ||
41 | the GIC cpu interface register base and size. | ||
42 | |||
43 | Optional | ||
44 | - interrupts : Interrupt source of the parent interrupt controller on | ||
45 | secondary GICs, or VGIC maintainance interrupt on primary GIC (see | ||
46 | below). | ||
47 | |||
48 | - cpu-offset : per-cpu offset within the distributor and cpu interface | ||
49 | regions, used when the GIC doesn't have banked registers. The offset is | ||
50 | cpu-offset * cpu-nr. | ||
51 | |||
52 | Example: | ||
53 | |||
54 | intc: interrupt-controller@fff11000 { | ||
55 | compatible = "arm,cortex-a9-gic"; | ||
56 | #interrupt-cells = <3>; | ||
57 | #address-cells = <1>; | ||
58 | interrupt-controller; | ||
59 | reg = <0xfff11000 0x1000>, | ||
60 | <0xfff10100 0x100>; | ||
61 | }; | ||
62 | |||
63 | |||
64 | * GIC virtualization extensions (VGIC) | ||
65 | |||
66 | For ARM cores that support the virtualization extensions, additional | ||
67 | properties must be described (they only exist if the GIC is the | ||
68 | primary interrupt controller). | ||
69 | |||
70 | Required properties: | ||
71 | |||
72 | - reg : Additional regions specifying the base physical address and | ||
73 | size of the VGIC registers. The first additional region is the GIC | ||
74 | virtual interface control register base and size. The 2nd additional | ||
75 | region is the GIC virtual cpu interface register base and size. | ||
76 | |||
77 | - interrupts : VGIC maintainance interrupt. | ||
78 | |||
79 | Example: | ||
80 | |||
81 | interrupt-controller@2c001000 { | ||
82 | compatible = "arm,cortex-a15-gic"; | ||
83 | #interrupt-cells = <3>; | ||
84 | interrupt-controller; | ||
85 | reg = <0x2c001000 0x1000>, | ||
86 | <0x2c002000 0x1000>, | ||
87 | <0x2c004000 0x2000>, | ||
88 | <0x2c006000 0x2000>; | ||
89 | interrupts = <1 9 0xf04>; | ||
90 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/insignal-boards.txt b/Documentation/devicetree/bindings/arm/insignal-boards.txt deleted file mode 100644 index 524c3dc5d80..00000000000 --- a/Documentation/devicetree/bindings/arm/insignal-boards.txt +++ /dev/null | |||
@@ -1,8 +0,0 @@ | |||
1 | * Insignal's Exynos4210 based Origen evaluation board | ||
2 | |||
3 | Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC. | ||
4 | |||
5 | Required root node properties: | ||
6 | - compatible = should be one or more of the following. | ||
7 | (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board. | ||
8 | (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC. | ||
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt deleted file mode 100644 index cbef09b5c8a..00000000000 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ /dev/null | |||
@@ -1,53 +0,0 @@ | |||
1 | * ARM L2 Cache Controller | ||
2 | |||
3 | ARM cores often have a separate level 2 cache controller. There are various | ||
4 | implementations of the L2 cache controller with compatible programming models. | ||
5 | The ARM L2 cache representation in the device tree should be done as follows: | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible : should be one of: | ||
10 | "arm,pl310-cache" | ||
11 | "arm,l220-cache" | ||
12 | "arm,l210-cache" | ||
13 | "marvell,aurora-system-cache": Marvell Controller designed to be | ||
14 | compatible with the ARM one, with system cache mode (meaning | ||
15 | maintenance operations on L1 are broadcasted to the L2 and L2 | ||
16 | performs the same operation). | ||
17 | "marvell,"aurora-outer-cache: Marvell Controller designed to be | ||
18 | compatible with the ARM one with outer cache mode. | ||
19 | - cache-unified : Specifies the cache is a unified cache. | ||
20 | - cache-level : Should be set to 2 for a level 2 cache. | ||
21 | - reg : Physical base address and size of cache controller's memory mapped | ||
22 | registers. | ||
23 | |||
24 | Optional properties: | ||
25 | |||
26 | - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of | ||
27 | read, write and setup latencies. Minimum valid values are 1. Controllers | ||
28 | without setup latency control should use a value of 0. | ||
29 | - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of | ||
30 | read, write and setup latencies. Controllers without setup latency control | ||
31 | should use 0. Controllers without separate read and write Tag RAM latency | ||
32 | values should only use the first cell. | ||
33 | - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. | ||
34 | - arm,filter-ranges : <start length> Starting address and length of window to | ||
35 | filter. Addresses in the filter window are directed to the M1 port. Other | ||
36 | addresses will go to the M0 port. | ||
37 | - interrupts : 1 combined interrupt. | ||
38 | - cache-id-part: cache id part number to be used if it is not present | ||
39 | on hardware | ||
40 | - wt-override: If present then L2 is forced to Write through mode | ||
41 | |||
42 | Example: | ||
43 | |||
44 | L2: cache-controller { | ||
45 | compatible = "arm,pl310-cache"; | ||
46 | reg = <0xfff12000 0x1000>; | ||
47 | arm,data-latency = <1 1 1>; | ||
48 | arm,tag-latency = <2 2 2>; | ||
49 | arm,filter-ranges = <0x80000000 0x8000000>; | ||
50 | cache-unified; | ||
51 | cache-level = <2>; | ||
52 | interrupts = <45>; | ||
53 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt b/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt deleted file mode 100644 index 539adca19e8..00000000000 --- a/Documentation/devicetree/bindings/arm/lpc32xx-mic.txt +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | * NXP LPC32xx Main Interrupt Controller | ||
2 | (MIC, including SIC1 and SIC2 secondary controllers) | ||
3 | |||
4 | Required properties: | ||
5 | - compatible: Should be "nxp,lpc3220-mic" | ||
6 | - interrupt-controller: Identifies the node as an interrupt controller. | ||
7 | - interrupt-parent: Empty for the interrupt controller itself | ||
8 | - #interrupt-cells: The number of cells to define the interrupts. Should be 2. | ||
9 | The first cell is the IRQ number | ||
10 | The second cell is used to specify mode: | ||
11 | 1 = low-to-high edge triggered | ||
12 | 2 = high-to-low edge triggered | ||
13 | 4 = active high level-sensitive | ||
14 | 8 = active low level-sensitive | ||
15 | Default for internal sources should be set to 4 (active high). | ||
16 | - reg: Should contain MIC registers location and length | ||
17 | |||
18 | Examples: | ||
19 | /* | ||
20 | * MIC | ||
21 | */ | ||
22 | mic: interrupt-controller@40008000 { | ||
23 | compatible = "nxp,lpc3220-mic"; | ||
24 | interrupt-controller; | ||
25 | interrupt-parent; | ||
26 | #interrupt-cells = <2>; | ||
27 | reg = <0x40008000 0xC000>; | ||
28 | }; | ||
29 | |||
30 | /* | ||
31 | * ADC | ||
32 | */ | ||
33 | adc@40048000 { | ||
34 | compatible = "nxp,lpc3220-adc"; | ||
35 | reg = <0x40048000 0x1000>; | ||
36 | interrupt-parent = <&mic>; | ||
37 | interrupts = <39 4>; | ||
38 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/lpc32xx.txt b/Documentation/devicetree/bindings/arm/lpc32xx.txt deleted file mode 100644 index 56ec8ddc4a3..00000000000 --- a/Documentation/devicetree/bindings/arm/lpc32xx.txt +++ /dev/null | |||
@@ -1,8 +0,0 @@ | |||
1 | NXP LPC32xx Platforms Device Tree Bindings | ||
2 | ------------------------------------------ | ||
3 | |||
4 | Boards with the NXP LPC32xx SoC shall have the following properties: | ||
5 | |||
6 | Required root node property: | ||
7 | |||
8 | compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250" | ||
diff --git a/Documentation/devicetree/bindings/arm/mrvl/intc.txt b/Documentation/devicetree/bindings/arm/mrvl/intc.txt deleted file mode 100644 index 8b53273cb22..00000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/intc.txt +++ /dev/null | |||
@@ -1,60 +0,0 @@ | |||
1 | * Marvell MMP Interrupt controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or | ||
5 | "mrvl,mmp2-mux-intc" | ||
6 | - reg : Address and length of the register set of the interrupt controller. | ||
7 | If the interrupt controller is intc, address and length means the range | ||
8 | of the whold interrupt controller. If the interrupt controller is mux-intc, | ||
9 | address and length means one register. Since address of mux-intc is in the | ||
10 | range of intc. mux-intc is secondary interrupt controller. | ||
11 | - reg-names : Name of the register set of the interrupt controller. It's | ||
12 | only required in mux-intc interrupt controller. | ||
13 | - interrupts : Should be the port interrupt shared by mux interrupts. It's | ||
14 | only required in mux-intc interrupt controller. | ||
15 | - interrupt-controller : Identifies the node as an interrupt controller. | ||
16 | - #interrupt-cells : Specifies the number of cells needed to encode an | ||
17 | interrupt source. | ||
18 | - mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt | ||
19 | controller. | ||
20 | - mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge | ||
21 | detection first. | ||
22 | |||
23 | Example: | ||
24 | intc: interrupt-controller@d4282000 { | ||
25 | compatible = "mrvl,mmp2-intc"; | ||
26 | interrupt-controller; | ||
27 | #interrupt-cells = <1>; | ||
28 | reg = <0xd4282000 0x1000>; | ||
29 | mrvl,intc-nr-irqs = <64>; | ||
30 | }; | ||
31 | |||
32 | intcmux4@d4282150 { | ||
33 | compatible = "mrvl,mmp2-mux-intc"; | ||
34 | interrupts = <4>; | ||
35 | interrupt-controller; | ||
36 | #interrupt-cells = <1>; | ||
37 | reg = <0x150 0x4>, <0x168 0x4>; | ||
38 | reg-names = "mux status", "mux mask"; | ||
39 | mrvl,intc-nr-irqs = <2>; | ||
40 | }; | ||
41 | |||
42 | * Marvell Orion Interrupt controller | ||
43 | |||
44 | Required properties | ||
45 | - compatible : Should be "marvell,orion-intc". | ||
46 | - #interrupt-cells: Specifies the number of cells needed to encode an | ||
47 | interrupt source. Supported value is <1>. | ||
48 | - interrupt-controller : Declare this node to be an interrupt controller. | ||
49 | - reg : Interrupt mask address. A list of 4 byte ranges, one per controller. | ||
50 | One entry in the list represents 32 interrupts. | ||
51 | |||
52 | Example: | ||
53 | |||
54 | intc: interrupt-controller { | ||
55 | compatible = "marvell,orion-intc", "marvell,intc"; | ||
56 | interrupt-controller; | ||
57 | #interrupt-cells = <1>; | ||
58 | reg = <0xfed20204 0x04>, | ||
59 | <0xfed20214 0x04>; | ||
60 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt deleted file mode 100644 index 117d741a2e4..00000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | Marvell Platforms Device Tree Bindings | ||
2 | ---------------------------------------------------- | ||
3 | |||
4 | PXA168 Aspenite Board | ||
5 | Required root node properties: | ||
6 | - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; | ||
7 | |||
8 | PXA910 DKB Board | ||
9 | Required root node properties: | ||
10 | - compatible = "mrvl,pxa910-dkb"; | ||
11 | |||
12 | MMP2 Brownstone Board | ||
13 | Required root node properties: | ||
14 | - compatible = "mrvl,mmp2-brownstone"; | ||
diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt deleted file mode 100644 index 31af1cbb60b..00000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * Marvell Tauros2 Cache | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "marvell,tauros2-cache". | ||
5 | - marvell,tauros2-cache-features : Specify the features supported for the | ||
6 | tauros2 cache. | ||
7 | The features including | ||
8 | CACHE_TAUROS2_PREFETCH_ON (1 << 0) | ||
9 | CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) | ||
10 | The definition can be found at | ||
11 | arch/arm/include/asm/hardware/cache-tauros2.h | ||
12 | |||
13 | Example: | ||
14 | L2: l2-cache { | ||
15 | compatible = "marvell,tauros2-cache"; | ||
16 | marvell,tauros2-cache-features = <0x3>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/mrvl/timer.txt b/Documentation/devicetree/bindings/arm/mrvl/timer.txt deleted file mode 100644 index 9a6e251462e..00000000000 --- a/Documentation/devicetree/bindings/arm/mrvl/timer.txt +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | * Marvell MMP Timer controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "mrvl,mmp-timer". | ||
5 | - reg : Address and length of the register set of timer controller. | ||
6 | - interrupts : Should be the interrupt number. | ||
7 | |||
8 | Example: | ||
9 | timer0: timer@d4014000 { | ||
10 | compatible = "mrvl,mmp-timer"; | ||
11 | reg = <0xd4014000 0x100>; | ||
12 | interrupts = <13>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt deleted file mode 100644 index 8c5907b9cae..00000000000 --- a/Documentation/devicetree/bindings/arm/msm/timer.txt +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | * MSM Timer | ||
2 | |||
3 | Properties: | ||
4 | |||
5 | - compatible : Should at least contain "qcom,msm-timer". More specific | ||
6 | properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general | ||
7 | purpose timer and a debug timer respectively. | ||
8 | |||
9 | - interrupts : Interrupt indicating a match event. | ||
10 | |||
11 | - reg : Specifies the base address of the timer registers. The second region | ||
12 | specifies an optional register used to configure the clock divider. | ||
13 | |||
14 | - clock-frequency : The frequency of the timer in Hz. | ||
15 | |||
16 | Optional: | ||
17 | |||
18 | - cpu-offset : per-cpu offset used when the timer is accessed without the | ||
19 | CPU remapping facilities. The offset is cpu-offset * cpu-nr. | ||
20 | |||
21 | Example: | ||
22 | |||
23 | timer@200a004 { | ||
24 | compatible = "qcom,msm-gpt", "qcom,msm-timer"; | ||
25 | interrupts = <1 2 0x301>; | ||
26 | reg = <0x0200a004 0x10>; | ||
27 | clock-frequency = <32768>; | ||
28 | cpu-offset = <0x40000>; | ||
29 | }; | ||
30 | |||
31 | timer@200a024 { | ||
32 | compatible = "qcom,msm-dgt", "qcom,msm-timer"; | ||
33 | interrupts = <1 3 0x301>; | ||
34 | reg = <0x0200a024 0x10>, | ||
35 | <0x0200a034 0x4>; | ||
36 | clock-frequency = <6750000>; | ||
37 | cpu-offset = <0x40000>; | ||
38 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt deleted file mode 100644 index 081c6a786c8..00000000000 --- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | MVEBU System Controller | ||
2 | ----------------------- | ||
3 | MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x) | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible: one of: | ||
8 | - "marvell,orion-system-controller" | ||
9 | - "marvell,armada-370-xp-system-controller" | ||
10 | - reg: Should contain system controller registers location and length. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | system-controller@d0018200 { | ||
15 | compatible = "marvell,armada-370-xp-system-controller"; | ||
16 | reg = <0xd0018200 0x500>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt deleted file mode 100644 index 007fb5c685a..00000000000 --- a/Documentation/devicetree/bindings/arm/olimex.txt +++ /dev/null | |||
@@ -1,6 +0,0 @@ | |||
1 | Olimex i.MX Platforms Device Tree Bindings | ||
2 | ------------------------------------------ | ||
3 | |||
4 | i.MX23 Olinuxino Low Cost Board | ||
5 | Required root node properties: | ||
6 | - compatible = "olimex,imx23-olinuxino", "fsl,imx23"; | ||
diff --git a/Documentation/devicetree/bindings/arm/omap/counter.txt b/Documentation/devicetree/bindings/arm/omap/counter.txt deleted file mode 100644 index 5bd8aa09131..00000000000 --- a/Documentation/devicetree/bindings/arm/omap/counter.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | OMAP Counter-32K bindings | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "ti,omap-counter32k" for OMAP controllers | ||
5 | - reg: Contains timer register address range (base address and length) | ||
6 | - ti,hwmods: Name of the hwmod associated to the counter, which is typically | ||
7 | "counter_32k" | ||
8 | |||
9 | Example: | ||
10 | |||
11 | counter32k: counter@4a304000 { | ||
12 | compatible = "ti,omap-counter32k"; | ||
13 | reg = <0x4a304000 0x20>; | ||
14 | ti,hwmods = "counter_32k"; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/omap/dsp.txt b/Documentation/devicetree/bindings/arm/omap/dsp.txt deleted file mode 100644 index d3830a32ce0..00000000000 --- a/Documentation/devicetree/bindings/arm/omap/dsp.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * TI - DSP (Digital Signal Processor) | ||
2 | |||
3 | TI DSP included in OMAP SoC | ||
4 | |||
5 | Required properties: | ||
6 | - compatible : Should be "ti,omap3-c64" for OMAP3 & 4 | ||
7 | - ti,hwmods: "dsp" | ||
8 | |||
9 | Examples: | ||
10 | |||
11 | dsp { | ||
12 | compatible = "ti,omap3-c64"; | ||
13 | ti,hwmods = "dsp"; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/omap/intc.txt b/Documentation/devicetree/bindings/arm/omap/intc.txt deleted file mode 100644 index f2583e6ec06..00000000000 --- a/Documentation/devicetree/bindings/arm/omap/intc.txt +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | * OMAP Interrupt Controller | ||
2 | |||
3 | OMAP2/3 are using a TI interrupt controller that can support several | ||
4 | configurable number of interrupts. | ||
5 | |||
6 | Main node required properties: | ||
7 | |||
8 | - compatible : should be: | ||
9 | "ti,omap2-intc" | ||
10 | - interrupt-controller : Identifies the node as an interrupt controller | ||
11 | - #interrupt-cells : Specifies the number of cells needed to encode an | ||
12 | interrupt source. The type shall be a <u32> and the value shall be 1. | ||
13 | |||
14 | The cell contains the interrupt number in the range [0-128]. | ||
15 | - ti,intc-size: Number of interrupts handled by the interrupt controller. | ||
16 | - reg: physical base address and size of the intc registers map. | ||
17 | |||
18 | Example: | ||
19 | |||
20 | intc: interrupt-controller@1 { | ||
21 | compatible = "ti,omap2-intc"; | ||
22 | interrupt-controller; | ||
23 | #interrupt-cells = <1>; | ||
24 | ti,intc-size = <96>; | ||
25 | reg = <0x48200000 0x1000>; | ||
26 | }; | ||
27 | |||
diff --git a/Documentation/devicetree/bindings/arm/omap/iva.txt b/Documentation/devicetree/bindings/arm/omap/iva.txt deleted file mode 100644 index 6d629517135..00000000000 --- a/Documentation/devicetree/bindings/arm/omap/iva.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | * TI - IVA (Imaging and Video Accelerator) subsystem | ||
2 | |||
3 | The IVA contain various audio, video or imaging HW accelerator | ||
4 | depending of the version. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : Should be: | ||
8 | - "ti,ivahd" for OMAP4 | ||
9 | - "ti,iva2.2" for OMAP3 | ||
10 | - "ti,iva2.1" for OMAP2430 | ||
11 | - "ti,iva1" for OMAP2420 | ||
12 | - ti,hwmods: "iva" | ||
13 | |||
14 | Examples: | ||
15 | |||
16 | iva { | ||
17 | compatible = "ti,ivahd", "ti,iva"; | ||
18 | ti,hwmods = "iva"; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt deleted file mode 100644 index 6888a5efc86..00000000000 --- a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | * TI - L3 Network On Chip (NoC) | ||
2 | |||
3 | This version is an implementation of the generic NoC IP | ||
4 | provided by Arteris. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family | ||
8 | Should be "ti,omap4-l3-noc" for OMAP4 family | ||
9 | - ti,hwmods: "l3_main_1", ... One hwmod for each noc domain. | ||
10 | |||
11 | Examples: | ||
12 | |||
13 | ocp { | ||
14 | compatible = "ti,omap4-l3-noc", "simple-bus"; | ||
15 | #address-cells = <1>; | ||
16 | #size-cells = <1>; | ||
17 | ranges; | ||
18 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt deleted file mode 100644 index 1a5a42ce21b..00000000000 --- a/Documentation/devicetree/bindings/arm/omap/mpu.txt +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | * TI - MPU (Main Processor Unit) subsystem | ||
2 | |||
3 | The MPU subsystem contain one or several ARM cores | ||
4 | depending of the version. | ||
5 | The MPU contain CPUs, GIC, L2 cache and a local PRCM. | ||
6 | |||
7 | Required properties: | ||
8 | - compatible : Should be "ti,omap3-mpu" for OMAP3 | ||
9 | Should be "ti,omap4-mpu" for OMAP4 | ||
10 | - ti,hwmods: "mpu" | ||
11 | |||
12 | Examples: | ||
13 | |||
14 | - For an OMAP4 SMP system: | ||
15 | |||
16 | mpu { | ||
17 | compatible = "ti,omap4-mpu"; | ||
18 | ti,hwmods = "mpu"; | ||
19 | }; | ||
20 | |||
21 | |||
22 | - For an OMAP3 monocore system: | ||
23 | |||
24 | mpu { | ||
25 | compatible = "ti,omap3-mpu"; | ||
26 | ti,hwmods = "mpu"; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt deleted file mode 100644 index d0051a75058..00000000000 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ /dev/null | |||
@@ -1,58 +0,0 @@ | |||
1 | * Texas Instruments OMAP | ||
2 | |||
3 | OMAP is currently using a static file per SoC family to describe the | ||
4 | IPs present in the SoC. | ||
5 | On top of that an omap_device is created to extend the platform_device | ||
6 | capabilities and to allow binding with one or several hwmods. | ||
7 | The hwmods will contain all the information to build the device: | ||
8 | address range, irq lines, dma lines, interconnect, PRCM register, | ||
9 | clock domain, input clocks. | ||
10 | For the moment just point to the existing hwmod, the next step will be | ||
11 | to move data from hwmod to device-tree representation. | ||
12 | |||
13 | |||
14 | Required properties: | ||
15 | - compatible: Every devices present in OMAP SoC should be in the | ||
16 | form: "ti,XXX" | ||
17 | - ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP | ||
18 | HW documentation, attached to a device. Must contain at least | ||
19 | one hwmod. | ||
20 | |||
21 | Optional properties: | ||
22 | - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module | ||
23 | during suspend. | ||
24 | |||
25 | |||
26 | Example: | ||
27 | |||
28 | spinlock@1 { | ||
29 | compatible = "ti,omap4-spinlock"; | ||
30 | ti,hwmods = "spinlock"; | ||
31 | }; | ||
32 | |||
33 | |||
34 | Boards: | ||
35 | |||
36 | - OMAP3 BeagleBoard : Low cost community board | ||
37 | compatible = "ti,omap3-beagle", "ti,omap3" | ||
38 | |||
39 | - OMAP3 Tobi with Overo : Commercial expansion board with daughter board | ||
40 | compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3" | ||
41 | |||
42 | - OMAP4 SDP : Software Developement Board | ||
43 | compatible = "ti,omap4-sdp", "ti,omap4430" | ||
44 | |||
45 | - OMAP4 PandaBoard : Low cost community board | ||
46 | compatible = "ti,omap4-panda", "ti,omap4430" | ||
47 | |||
48 | - OMAP3 EVM : Software Developement Board for OMAP35x, AM/DM37x | ||
49 | compatible = "ti,omap3-evm", "ti,omap3" | ||
50 | |||
51 | - AM335X EVM : Software Developement Board for AM335x | ||
52 | compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3" | ||
53 | |||
54 | - AM335X Bone : Low cost community board | ||
55 | compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3" | ||
56 | |||
57 | - OMAP5 EVM : Evaluation Module | ||
58 | compatible = "ti,omap5-evm", "ti,omap5" | ||
diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt deleted file mode 100644 index 8732d4d41f8..00000000000 --- a/Documentation/devicetree/bindings/arm/omap/timer.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | OMAP Timer bindings | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "ti,omap2-timer" for OMAP2+ controllers. | ||
5 | - reg: Contains timer register address range (base address and | ||
6 | length). | ||
7 | - interrupts: Contains the interrupt information for the timer. The | ||
8 | format is being dependent on which interrupt controller | ||
9 | the OMAP device uses. | ||
10 | - ti,hwmods: Name of the hwmod associated to the timer, "timer<X>", | ||
11 | where <X> is the instance number of the timer from the | ||
12 | HW spec. | ||
13 | |||
14 | Optional properties: | ||
15 | - ti,timer-alwon: Indicates the timer is in an alway-on power domain. | ||
16 | - ti,timer-dsp: Indicates the timer can interrupt the on-chip DSP in | ||
17 | addition to the ARM CPU. | ||
18 | - ti,timer-pwm: Indicates the timer can generate a PWM output. | ||
19 | - ti,timer-secure: Indicates the timer is reserved on a secure OMAP device | ||
20 | and therefore cannot be used by the kernel. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | timer12: timer@48304000 { | ||
25 | compatible = "ti,omap2-timer"; | ||
26 | reg = <0x48304000 0x400>; | ||
27 | interrupts = <95>; | ||
28 | ti,hwmods = "timer12" | ||
29 | ti,timer-alwon; | ||
30 | ti,timer-secure; | ||
31 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt deleted file mode 100644 index e75c0ef51e6..00000000000 --- a/Documentation/devicetree/bindings/arm/picoxcell.txt +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | Picochip picoXcell device tree bindings. | ||
2 | ======================================== | ||
3 | |||
4 | Required root node properties: | ||
5 | - compatible: | ||
6 | - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device. | ||
7 | - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device. | ||
8 | - "picochip,pc3x3" : picoXcell PC3X3 device based board. | ||
9 | - "picochip,pc3x2" : picoXcell PC3X2 device based board. | ||
10 | |||
11 | Timers required properties: | ||
12 | - compatible = "picochip,pc3x2-timer" | ||
13 | - interrupts : The single IRQ line for the timer. | ||
14 | - clock-freq : The frequency in HZ of the timer. | ||
15 | - reg : The register bank for the timer. | ||
16 | |||
17 | Note: two timers are required - one for the scheduler clock and one for the | ||
18 | event tick/NOHZ. | ||
19 | |||
20 | VIC required properties: | ||
21 | - compatible = "arm,pl192-vic". | ||
22 | - interrupt-controller. | ||
23 | - reg : The register bank for the device. | ||
24 | - #interrupt-cells : Must be 1. | ||
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt index 343781b9f24..1c044eb320c 100644 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ b/Documentation/devicetree/bindings/arm/pmu.txt | |||
@@ -7,12 +7,8 @@ representation in the device tree should be done as under:- | |||
7 | Required properties: | 7 | Required properties: |
8 | 8 | ||
9 | - compatible : should be one of | 9 | - compatible : should be one of |
10 | "arm,cortex-a15-pmu" | ||
11 | "arm,cortex-a9-pmu" | 10 | "arm,cortex-a9-pmu" |
12 | "arm,cortex-a8-pmu" | 11 | "arm,cortex-a8-pmu" |
13 | "arm,cortex-a7-pmu" | ||
14 | "arm,cortex-a5-pmu" | ||
15 | "arm,arm11mpcore-pmu" | ||
16 | "arm,arm1176-pmu" | 12 | "arm,arm1176-pmu" |
17 | "arm,arm1136-pmu" | 13 | "arm,arm1136-pmu" |
18 | - interrupts : 1 combined interrupt or 1 per core. | 14 | - interrupts : 1 combined interrupt or 1 per core. |
diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt index 64fc82bc892..1d5d7a870ec 100644 --- a/Documentation/devicetree/bindings/arm/primecell.txt +++ b/Documentation/devicetree/bindings/arm/primecell.txt | |||
@@ -6,24 +6,16 @@ driver matching. | |||
6 | 6 | ||
7 | Required properties: | 7 | Required properties: |
8 | 8 | ||
9 | - compatible : should be a specific name for the peripheral and | 9 | - compatible : should be a specific value for peripheral and "arm,primecell" |
10 | "arm,primecell". The specific name will match the ARM | ||
11 | engineering name for the logic block in the form: "arm,pl???" | ||
12 | 10 | ||
13 | Optional properties: | 11 | Optional properties: |
14 | 12 | ||
15 | - arm,primecell-periphid : Value to override the h/w value with | 13 | - arm,primecell-periphid : Value to override the h/w value with |
16 | - clocks : From common clock binding. First clock is phandle to clock for apb | ||
17 | pclk. Additional clocks are optional and specific to those peripherals. | ||
18 | - clock-names : From common clock binding. Shall be "apb_pclk" for first clock. | ||
19 | 14 | ||
20 | Example: | 15 | Example: |
21 | 16 | ||
22 | serial@fff36000 { | 17 | serial@fff36000 { |
23 | compatible = "arm,pl011", "arm,primecell"; | 18 | compatible = "arm,pl011", "arm,primecell"; |
24 | arm,primecell-periphid = <0x00341011>; | 19 | arm,primecell-periphid = <0x00341011>; |
25 | clocks = <&pclk>; | ||
26 | clock-names = "apb_pclk"; | ||
27 | |||
28 | }; | 20 | }; |
29 | 21 | ||
diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt deleted file mode 100644 index 0bf68be56fd..00000000000 --- a/Documentation/devicetree/bindings/arm/samsung-boards.txt +++ /dev/null | |||
@@ -1,8 +0,0 @@ | |||
1 | * Samsung's Exynos4210 based SMDKV310 evaluation board | ||
2 | |||
3 | SMDKV310 evaluation board is based on Samsung's Exynos4210 SoC. | ||
4 | |||
5 | Required root node properties: | ||
6 | - compatible = should be one or more of the following. | ||
7 | (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board. | ||
8 | (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC. | ||
diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt deleted file mode 100644 index f2f2171e530..00000000000 --- a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | * Samsung Exynos Interrupt Combiner Controller | ||
2 | |||
3 | Samsung's Exynos4 architecture includes a interrupt combiner controller which | ||
4 | can combine interrupt sources as a group and provide a single interrupt request | ||
5 | for the group. The interrupt request from each group are connected to a parent | ||
6 | interrupt controller, such as GIC in case of Exynos4210. | ||
7 | |||
8 | The interrupt combiner controller consists of multiple combiners. Upto eight | ||
9 | interrupt sources can be connected to a combiner. The combiner outputs one | ||
10 | combined interrupt for its eight interrupt sources. The combined interrupt | ||
11 | is usually connected to a parent interrupt controller. | ||
12 | |||
13 | A single node in the device tree is used to describe the interrupt combiner | ||
14 | controller module (which includes multiple combiners). A combiner in the | ||
15 | interrupt controller module shares config/control registers with other | ||
16 | combiners. For example, a 32-bit interrupt enable/disable config register | ||
17 | can accommodate upto 4 interrupt combiners (with each combiner supporting | ||
18 | upto 8 interrupt sources). | ||
19 | |||
20 | Required properties: | ||
21 | - compatible: should be "samsung,exynos4210-combiner". | ||
22 | - interrupt-controller: Identifies the node as an interrupt controller. | ||
23 | - #interrupt-cells: should be <2>. The meaning of the cells are | ||
24 | * First Cell: Combiner Group Number. | ||
25 | * Second Cell: Interrupt number within the group. | ||
26 | - reg: Base address and size of interrupt combiner registers. | ||
27 | - interrupts: The list of interrupts generated by the combiners which are then | ||
28 | connected to a parent interrupt controller. The format of the interrupt | ||
29 | specifier depends in the interrupt parent controller. | ||
30 | |||
31 | Optional properties: | ||
32 | - samsung,combiner-nr: The number of interrupt combiners supported. If this | ||
33 | property is not specified, the default number of combiners is assumed | ||
34 | to be 16. | ||
35 | - interrupt-parent: pHandle of the parent interrupt controller, if not | ||
36 | inherited from the parent node. | ||
37 | |||
38 | |||
39 | Example: | ||
40 | |||
41 | The following is a an example from the Exynos4210 SoC dtsi file. | ||
42 | |||
43 | combiner:interrupt-controller@10440000 { | ||
44 | compatible = "samsung,exynos4210-combiner"; | ||
45 | interrupt-controller; | ||
46 | #interrupt-cells = <2>; | ||
47 | reg = <0x10440000 0x1000>; | ||
48 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | ||
49 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | ||
50 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | ||
51 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; | ||
52 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/sirf.txt b/Documentation/devicetree/bindings/arm/sirf.txt index 1881e1c6dda..6b07f65b32d 100644 --- a/Documentation/devicetree/bindings/arm/sirf.txt +++ b/Documentation/devicetree/bindings/arm/sirf.txt | |||
@@ -1,3 +1,3 @@ | |||
1 | prima2 "cb" evaluation board | 1 | prima2 "cb" evalutation board |
2 | Required root node properties: | 2 | Required root node properties: |
3 | - compatible = "sirf,prima2-cb", "sirf,prima2"; | 3 | - compatible = "sirf,prima2-cb", "sirf,prima2"; |
diff --git a/Documentation/devicetree/bindings/arm/spear-timer.txt b/Documentation/devicetree/bindings/arm/spear-timer.txt deleted file mode 100644 index c0017221cf5..00000000000 --- a/Documentation/devicetree/bindings/arm/spear-timer.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | * SPEAr ARM Timer | ||
2 | |||
3 | ** Timer node required properties: | ||
4 | |||
5 | - compatible : Should be: | ||
6 | "st,spear-timer" | ||
7 | - reg: Address range of the timer registers | ||
8 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
9 | that services interrupts for this device | ||
10 | - interrupt: Should contain the timer interrupt number | ||
11 | |||
12 | Example: | ||
13 | |||
14 | timer@f0000000 { | ||
15 | compatible = "st,spear-timer"; | ||
16 | reg = <0xf0000000 0x400>; | ||
17 | interrupts = <2>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt deleted file mode 100644 index 0d42949df6c..00000000000 --- a/Documentation/devicetree/bindings/arm/spear.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | ST SPEAr Platforms Device Tree Bindings | ||
2 | --------------------------------------- | ||
3 | |||
4 | Boards with the ST SPEAr600 SoC shall have the following properties: | ||
5 | Required root node property: | ||
6 | compatible = "st,spear600"; | ||
7 | |||
8 | Boards with the ST SPEAr300 SoC shall have the following properties: | ||
9 | Required root node property: | ||
10 | compatible = "st,spear300"; | ||
11 | |||
12 | Boards with the ST SPEAr310 SoC shall have the following properties: | ||
13 | Required root node property: | ||
14 | compatible = "st,spear310"; | ||
15 | |||
16 | Boards with the ST SPEAr320 SoC shall have the following properties: | ||
17 | Required root node property: | ||
18 | compatible = "st,spear320"; | ||
19 | |||
20 | Boards with the ST SPEAr1310 SoC shall have the following properties: | ||
21 | Required root node property: | ||
22 | compatible = "st,spear1310"; | ||
23 | |||
24 | Boards with the ST SPEAr1340 SoC shall have the following properties: | ||
25 | Required root node property: | ||
26 | compatible = "st,spear1340"; | ||
diff --git a/Documentation/devicetree/bindings/arm/spear/shirq.txt b/Documentation/devicetree/bindings/arm/spear/shirq.txt deleted file mode 100644 index 13fbb8866bd..00000000000 --- a/Documentation/devicetree/bindings/arm/spear/shirq.txt +++ /dev/null | |||
@@ -1,48 +0,0 @@ | |||
1 | * SPEAr Shared IRQ layer (shirq) | ||
2 | |||
3 | SPEAr3xx architecture includes shared/multiplexed irqs for certain set | ||
4 | of devices. The multiplexor provides a single interrupt to parent | ||
5 | interrupt controller (VIC) on behalf of a group of devices. | ||
6 | |||
7 | There can be multiple groups available on SPEAr3xx variants but not | ||
8 | exceeding 4. The number of devices in a group can differ, further they | ||
9 | may share same set of status/mask registers spanning across different | ||
10 | bit masks. Also in some cases the group may not have enable or other | ||
11 | registers. This makes software little complex. | ||
12 | |||
13 | A single node in the device tree is used to describe the shared | ||
14 | interrupt multiplexor (one node for all groups). A group in the | ||
15 | interrupt controller shares config/control registers with other groups. | ||
16 | For example, a 32-bit interrupt enable/disable config register can | ||
17 | accommodate upto 4 interrupt groups. | ||
18 | |||
19 | Required properties: | ||
20 | - compatible: should be, either of | ||
21 | - "st,spear300-shirq" | ||
22 | - "st,spear310-shirq" | ||
23 | - "st,spear320-shirq" | ||
24 | - interrupt-controller: Identifies the node as an interrupt controller. | ||
25 | - #interrupt-cells: should be <1> which basically contains the offset | ||
26 | (starting from 0) of interrupts for all the groups. | ||
27 | - reg: Base address and size of shirq registers. | ||
28 | - interrupts: The list of interrupts generated by the groups which are | ||
29 | then connected to a parent interrupt controller. Each group is | ||
30 | associated with one of the interrupts, hence number of interrupts (to | ||
31 | parent) is equal to number of groups. The format of the interrupt | ||
32 | specifier depends in the interrupt parent controller. | ||
33 | |||
34 | Optional properties: | ||
35 | - interrupt-parent: pHandle of the parent interrupt controller, if not | ||
36 | inherited from the parent node. | ||
37 | |||
38 | Example: | ||
39 | |||
40 | The following is an example from the SPEAr320 SoC dtsi file. | ||
41 | |||
42 | shirq: interrupt-controller@0xb3000000 { | ||
43 | compatible = "st,spear320-shirq"; | ||
44 | reg = <0xb3000000 0x1000>; | ||
45 | interrupts = <28 29 30 1>; | ||
46 | #interrupt-cells = <1>; | ||
47 | interrupt-controller; | ||
48 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt deleted file mode 100644 index 6e69d2e5e76..00000000000 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | NVIDIA Tegra device tree bindings | ||
2 | ------------------------------------------- | ||
3 | |||
4 | Boards with the tegra20 SoC shall have the following properties: | ||
5 | |||
6 | Required root node property: | ||
7 | |||
8 | compatible = "nvidia,tegra20"; | ||
9 | |||
10 | Boards with the tegra30 SoC shall have the following properties: | ||
11 | |||
12 | Required root node property: | ||
13 | |||
14 | compatible = "nvidia,tegra30"; | ||
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt deleted file mode 100644 index 234406d41c1..00000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt +++ /dev/null | |||
@@ -1,11 +0,0 @@ | |||
1 | NVIDIA Tegra AHB | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb" | ||
5 | - reg : Should contain 1 register ranges(address and length) | ||
6 | |||
7 | Example: | ||
8 | ahb: ahb@6000c004 { | ||
9 | compatible = "nvidia,tegra20-ahb"; | ||
10 | reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ | ||
11 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt deleted file mode 100644 index 4c33b29dc66..00000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ /dev/null | |||
@@ -1,100 +0,0 @@ | |||
1 | Embedded Memory Controller | ||
2 | |||
3 | Properties: | ||
4 | - name : Should be emc | ||
5 | - #address-cells : Should be 1 | ||
6 | - #size-cells : Should be 0 | ||
7 | - compatible : Should contain "nvidia,tegra20-emc". | ||
8 | - reg : Offset and length of the register set for the device | ||
9 | - nvidia,use-ram-code : If present, the sub-nodes will be addressed | ||
10 | and chosen using the ramcode board selector. If omitted, only one | ||
11 | set of tables can be present and said tables will be used | ||
12 | irrespective of ram-code configuration. | ||
13 | |||
14 | Child device nodes describe the memory settings for different configurations and clock rates. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | memory-controller@7000f400 { | ||
19 | #address-cells = < 1 >; | ||
20 | #size-cells = < 0 >; | ||
21 | compatible = "nvidia,tegra20-emc"; | ||
22 | reg = <0x7000f4000 0x200>; | ||
23 | } | ||
24 | |||
25 | |||
26 | Embedded Memory Controller ram-code table | ||
27 | |||
28 | If the emc node has the nvidia,use-ram-code property present, then the | ||
29 | next level of nodes below the emc table are used to specify which settings | ||
30 | apply for which ram-code settings. | ||
31 | |||
32 | If the emc node lacks the nvidia,use-ram-code property, this level is omitted | ||
33 | and the tables are stored directly under the emc node (see below). | ||
34 | |||
35 | Properties: | ||
36 | |||
37 | - name : Should be emc-tables | ||
38 | - nvidia,ram-code : the binary representation of the ram-code board strappings | ||
39 | for which this node (and children) are valid. | ||
40 | |||
41 | |||
42 | |||
43 | Embedded Memory Controller configuration table | ||
44 | |||
45 | This is a table containing the EMC register settings for the various | ||
46 | operating speeds of the memory controller. They are always located as | ||
47 | subnodes of the emc controller node. | ||
48 | |||
49 | There are two ways of specifying which tables to use: | ||
50 | |||
51 | * The simplest is if there is just one set of tables in the device tree, | ||
52 | and they will always be used (based on which frequency is used). | ||
53 | This is the preferred method, especially when firmware can fill in | ||
54 | this information based on the specific system information and just | ||
55 | pass it on to the kernel. | ||
56 | |||
57 | * The slightly more complex one is when more than one memory configuration | ||
58 | might exist on the system. The Tegra20 platform handles this during | ||
59 | early boot by selecting one out of possible 4 memory settings based | ||
60 | on a 2-pin "ram code" bootstrap setting on the board. The values of | ||
61 | these strappings can be read through a register in the SoC, and thus | ||
62 | used to select which tables to use. | ||
63 | |||
64 | Properties: | ||
65 | - name : Should be emc-table | ||
66 | - compatible : Should contain "nvidia,tegra20-emc-table". | ||
67 | - reg : either an opaque enumerator to tell different tables apart, or | ||
68 | the valid frequency for which the table should be used (in kHz). | ||
69 | - clock-frequency : the clock frequency for the EMC at which this | ||
70 | table should be used (in kHz). | ||
71 | - nvidia,emc-registers : a 46 word array of EMC registers to be programmed | ||
72 | for operation at the 'clock-frequency' setting. | ||
73 | The order and contents of the registers are: | ||
74 | RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, | ||
75 | WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, | ||
76 | PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, | ||
77 | TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, | ||
78 | ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, | ||
79 | ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, | ||
80 | CFG_CLKTRIM_1, CFG_CLKTRIM_2 | ||
81 | |||
82 | emc-table@166000 { | ||
83 | reg = <166000>; | ||
84 | compatible = "nvidia,tegra20-emc-table"; | ||
85 | clock-frequency = < 166000 >; | ||
86 | nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
87 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
88 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
89 | 0 0 0 0 >; | ||
90 | }; | ||
91 | |||
92 | emc-table@333000 { | ||
93 | reg = <333000>; | ||
94 | compatible = "nvidia,tegra20-emc-table"; | ||
95 | clock-frequency = < 333000 >; | ||
96 | nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
97 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
98 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
99 | 0 0 0 0 >; | ||
100 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt deleted file mode 100644 index 866d93421eb..00000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | NVIDIA Tegra20 MC(Memory Controller) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra20-mc" | ||
5 | - reg : Should contain 2 register ranges(address and length); see the | ||
6 | example below. Note that the MC registers are interleaved with the | ||
7 | GART registers, and hence must be represented as multiple ranges. | ||
8 | - interrupts : Should contain MC General interrupt. | ||
9 | |||
10 | Example: | ||
11 | memory-controller@0x7000f000 { | ||
12 | compatible = "nvidia,tegra20-mc"; | ||
13 | reg = <0x7000f000 0x024 | ||
14 | 0x7000f03c 0x3c4>; | ||
15 | interrupts = <0 77 0x04>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt deleted file mode 100644 index b5846e21cc2..00000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | NVIDIA Tegra Power Management Controller (PMC) | ||
2 | |||
3 | Properties: | ||
4 | - name : Should be pmc | ||
5 | - compatible : Should contain "nvidia,tegra<chip>-pmc". | ||
6 | - reg : Offset and length of the register set for the device | ||
7 | - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. | ||
8 | The PMU is an external Power Management Unit, whose interrupt output | ||
9 | signal is fed into the PMC. This signal is optionally inverted, and then | ||
10 | fed into the ARM GIC. The PMC is not involved in the detection or | ||
11 | handling of this interrupt signal, merely its inversion. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | pmc@7000f400 { | ||
16 | compatible = "nvidia,tegra20-pmc"; | ||
17 | reg = <0x7000e400 0x400>; | ||
18 | nvidia,invert-interrupt; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt deleted file mode 100644 index bdf1a612422..00000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | NVIDIA Tegra30 MC(Memory Controller) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra30-mc" | ||
5 | - reg : Should contain 4 register ranges(address and length); see the | ||
6 | example below. Note that the MC registers are interleaved with the | ||
7 | SMMU registers, and hence must be represented as multiple ranges. | ||
8 | - interrupts : Should contain MC General interrupt. | ||
9 | |||
10 | Example: | ||
11 | memory-controller { | ||
12 | compatible = "nvidia,tegra30-mc"; | ||
13 | reg = <0x7000f000 0x010 | ||
14 | 0x7000f03c 0x1b4 | ||
15 | 0x7000f200 0x028 | ||
16 | 0x7000f284 0x17c>; | ||
17 | interrupts = <0 77 0x04>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/twd.txt b/Documentation/devicetree/bindings/arm/twd.txt deleted file mode 100644 index 75b8610939f..00000000000 --- a/Documentation/devicetree/bindings/arm/twd.txt +++ /dev/null | |||
@@ -1,48 +0,0 @@ | |||
1 | * ARM Timer Watchdog | ||
2 | |||
3 | ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core | ||
4 | Timer-Watchdog (aka TWD), which provides both a per-cpu local timer | ||
5 | and watchdog. | ||
6 | |||
7 | The TWD is usually attached to a GIC to deliver its two per-processor | ||
8 | interrupts. | ||
9 | |||
10 | ** Timer node required properties: | ||
11 | |||
12 | - compatible : Should be one of: | ||
13 | "arm,cortex-a9-twd-timer" | ||
14 | "arm,cortex-a5-twd-timer" | ||
15 | "arm,arm11mp-twd-timer" | ||
16 | |||
17 | - interrupts : One interrupt to each core | ||
18 | |||
19 | - reg : Specify the base address and the size of the TWD timer | ||
20 | register window. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | twd-timer@2c000600 { | ||
25 | compatible = "arm,arm11mp-twd-timer""; | ||
26 | reg = <0x2c000600 0x20>; | ||
27 | interrupts = <1 13 0xf01>; | ||
28 | }; | ||
29 | |||
30 | ** Watchdog node properties: | ||
31 | |||
32 | - compatible : Should be one of: | ||
33 | "arm,cortex-a9-twd-wdt" | ||
34 | "arm,cortex-a5-twd-wdt" | ||
35 | "arm,arm11mp-twd-wdt" | ||
36 | |||
37 | - interrupts : One interrupt to each core | ||
38 | |||
39 | - reg : Specify the base address and the size of the TWD watchdog | ||
40 | register window. | ||
41 | |||
42 | Example: | ||
43 | |||
44 | twd-watchdog@2c000620 { | ||
45 | compatible = "arm,arm11mp-twd-wdt"; | ||
46 | reg = <0x2c000620 0x20>; | ||
47 | interrupts = <1 14 0xf01>; | ||
48 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt b/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt deleted file mode 100644 index 9989eda755d..00000000000 --- a/Documentation/devicetree/bindings/arm/versatile-fpga-irq.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | * ARM Versatile FPGA interrupt controller | ||
2 | |||
3 | One or more FPGA IRQ controllers can be synthesized in an ARM reference board | ||
4 | such as the Integrator or Versatile family. The output of these different | ||
5 | controllers are OR:ed together and fed to the CPU tile's IRQ input. Each | ||
6 | instance can handle up to 32 interrupts. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible: "arm,versatile-fpga-irq" | ||
10 | - interrupt-controller: Identifies the node as an interrupt controller | ||
11 | - #interrupt-cells: The number of cells to define the interrupts. Must be 1 | ||
12 | as the FPGA IRQ controller has no configuration options for interrupt | ||
13 | sources. The cell is a u32 and defines the interrupt number. | ||
14 | - reg: The register bank for the FPGA interrupt controller. | ||
15 | - clear-mask: a u32 number representing the mask written to clear all IRQs | ||
16 | on the controller at boot for example. | ||
17 | - valid-mask: a u32 number representing a bit mask determining which of | ||
18 | the interrupts are valid. Unconnected/unused lines are set to 0, and | ||
19 | the system till not make it possible for devices to request these | ||
20 | interrupts. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | pic: pic@14000000 { | ||
25 | compatible = "arm,versatile-fpga-irq"; | ||
26 | #interrupt-cells = <1>; | ||
27 | interrupt-controller; | ||
28 | reg = <0x14000000 0x100>; | ||
29 | clear-mask = <0xffffffff>; | ||
30 | valid-mask = <0x003fffff>; | ||
31 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt deleted file mode 100644 index 9cf3f25544c..00000000000 --- a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | ARM Versatile Express system registers | ||
2 | -------------------------------------- | ||
3 | |||
4 | This is a system control registers block, providing multiple low level | ||
5 | platform functions like board detection and identification, software | ||
6 | interrupt generation, MMC and NOR Flash control etc. | ||
7 | |||
8 | Required node properties: | ||
9 | - compatible value : = "arm,vexpress,sysreg"; | ||
10 | - reg : physical base address and the size of the registers window | ||
11 | - gpio-controller : specifies that the node is a GPIO controller | ||
12 | - #gpio-cells : size of the GPIO specifier, should be 2: | ||
13 | - first cell is the pseudo-GPIO line number: | ||
14 | 0 - MMC CARDIN | ||
15 | 1 - MMC WPROT | ||
16 | 2 - NOR FLASH WPn | ||
17 | - second cell can take standard GPIO flags (currently ignored). | ||
18 | |||
19 | Example: | ||
20 | v2m_sysreg: sysreg@10000000 { | ||
21 | compatible = "arm,vexpress-sysreg"; | ||
22 | reg = <0x10000000 0x1000>; | ||
23 | gpio-controller; | ||
24 | #gpio-cells = <2>; | ||
25 | }; | ||
26 | |||
27 | This block also can also act a bridge to the platform's configuration | ||
28 | bus via "system control" interface, addressing devices with site number, | ||
29 | position in the board stack, config controller, function and device | ||
30 | numbers - see motherboard's TRM for more details. | ||
31 | |||
32 | The node describing a config device must refer to the sysreg node via | ||
33 | "arm,vexpress,config-bridge" phandle (can be also defined in the node's | ||
34 | parent) and relies on the board topology properties - see main vexpress | ||
35 | node documentation for more details. It must must also define the | ||
36 | following property: | ||
37 | - arm,vexpress-sysreg,func : must contain two cells: | ||
38 | - first cell defines function number (eg. 1 for clock generator, | ||
39 | 2 for voltage regulators etc.) | ||
40 | - device number (eg. osc 0, osc 1 etc.) | ||
41 | |||
42 | Example: | ||
43 | mcc { | ||
44 | arm,vexpress,config-bridge = <&v2m_sysreg>; | ||
45 | |||
46 | osc@0 { | ||
47 | compatible = "arm,vexpress-osc"; | ||
48 | arm,vexpress-sysreg,func = <1 0>; | ||
49 | }; | ||
50 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt deleted file mode 100644 index ae49161e478..00000000000 --- a/Documentation/devicetree/bindings/arm/vexpress.txt +++ /dev/null | |||
@@ -1,224 +0,0 @@ | |||
1 | ARM Versatile Express boards family | ||
2 | ----------------------------------- | ||
3 | |||
4 | ARM's Versatile Express platform consists of a motherboard and one | ||
5 | or more daughterboards (tiles). The motherboard provides a set of | ||
6 | peripherals. Processor and RAM "live" on the tiles. | ||
7 | |||
8 | The motherboard and each core tile should be described by a separate | ||
9 | Device Tree source file, with the tile's description including | ||
10 | the motherboard file using a /include/ directive. As the motherboard | ||
11 | can be initialized in one of two different configurations ("memory | ||
12 | maps"), care must be taken to include the correct one. | ||
13 | |||
14 | |||
15 | Root node | ||
16 | --------- | ||
17 | |||
18 | Required properties in the root node: | ||
19 | - compatible value: | ||
20 | compatible = "arm,vexpress,<model>", "arm,vexpress"; | ||
21 | where <model> is the full tile model name (as used in the tile's | ||
22 | Technical Reference Manual), eg.: | ||
23 | - for Coretile Express A5x2 (V2P-CA5s): | ||
24 | compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; | ||
25 | - for Coretile Express A9x4 (V2P-CA9): | ||
26 | compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; | ||
27 | If a tile comes in several variants or can be used in more then one | ||
28 | configuration, the compatible value should be: | ||
29 | compatible = "arm,vexpress,<model>,<variant>", \ | ||
30 | "arm,vexpress,<model>", "arm,vexpress"; | ||
31 | eg: | ||
32 | - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1: | ||
33 | compatible = "arm,vexpress,v2p-ca15,tc1", \ | ||
34 | "arm,vexpress,v2p-ca15", "arm,vexpress"; | ||
35 | - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM: | ||
36 | compatible = "arm,vexpress,v2f-2xv6,ca7x3", \ | ||
37 | "arm,vexpress,v2f-2xv6", "arm,vexpress"; | ||
38 | |||
39 | Optional properties in the root node: | ||
40 | - tile model name (use name from the tile's Technical Reference | ||
41 | Manual, eg. "V2P-CA5s") | ||
42 | model = "<model>"; | ||
43 | - tile's HBI number (unique ARM's board model ID, visible on the | ||
44 | PCB's silkscreen) in hexadecimal transcription: | ||
45 | arm,hbi = <0xhbi> | ||
46 | eg: | ||
47 | - for Coretile Express A5x2 (V2P-CA5s) HBI-0191: | ||
48 | arm,hbi = <0x191>; | ||
49 | - Coretile Express A9x4 (V2P-CA9) HBI-0225: | ||
50 | arm,hbi = <0x225>; | ||
51 | |||
52 | |||
53 | CPU nodes | ||
54 | --------- | ||
55 | |||
56 | Top-level standard "cpus" node is required. It must contain a node | ||
57 | with device_type = "cpu" property for every available core, eg.: | ||
58 | |||
59 | cpus { | ||
60 | #address-cells = <1>; | ||
61 | #size-cells = <0>; | ||
62 | |||
63 | cpu@0 { | ||
64 | device_type = "cpu"; | ||
65 | compatible = "arm,cortex-a5"; | ||
66 | reg = <0>; | ||
67 | }; | ||
68 | }; | ||
69 | |||
70 | |||
71 | Configuration infrastructure | ||
72 | ---------------------------- | ||
73 | |||
74 | The platform has an elaborated configuration system, consisting of | ||
75 | microcontrollers residing on the mother- and daughterboards known | ||
76 | as Motherboard/Daughterboard Configuration Controller (MCC and DCC). | ||
77 | The controllers are responsible for the platform initialization | ||
78 | (reset generation, flash programming, FPGA bitfiles loading etc.) | ||
79 | but also control clock generators, voltage regulators, gather | ||
80 | environmental data like temperature, power consumption etc. Even | ||
81 | the video output switch (FPGA) is controlled that way. | ||
82 | |||
83 | Nodes describing devices controlled by this infrastructure should | ||
84 | point at the bridge device node: | ||
85 | - bridge phandle: | ||
86 | arm,vexpress,config-bridge = <phandle>; | ||
87 | This property can be also defined in a parent node (eg. for a DCC) | ||
88 | and is effective for all children. | ||
89 | |||
90 | |||
91 | Platform topology | ||
92 | ----------------- | ||
93 | |||
94 | As Versatile Express can be configured in number of physically | ||
95 | different setups, the device tree should describe platform topology. | ||
96 | Root node and main motherboard node must define the following | ||
97 | property, describing physical location of the children nodes: | ||
98 | - site number: | ||
99 | arm,vexpress,site = <number>; | ||
100 | where 0 means motherboard, 1 or 2 are daugtherboard sites, | ||
101 | 0xf means "master" site (site containing main CPU tile) | ||
102 | - when daughterboards are stacked on one site, their position | ||
103 | in the stack be be described with: | ||
104 | arm,vexpress,position = <number>; | ||
105 | - when describing tiles consisting more than one DCC, its number | ||
106 | can be described with: | ||
107 | arm,vexpress,dcc = <number>; | ||
108 | |||
109 | Any of the numbers above defaults to zero if not defined in | ||
110 | the node or any of its parent. | ||
111 | |||
112 | |||
113 | Motherboard | ||
114 | ----------- | ||
115 | |||
116 | The motherboard description file provides a single "motherboard" node | ||
117 | using 2 address cells corresponding to the Static Memory Bus used | ||
118 | between the motherboard and the tile. The first cell defines the Chip | ||
119 | Select (CS) line number, the second cell address offset within the CS. | ||
120 | All interrupt lines between the motherboard and the tile are active | ||
121 | high and are described using single cell. | ||
122 | |||
123 | Optional properties of the "motherboard" node: | ||
124 | - motherboard's memory map variant: | ||
125 | arm,v2m-memory-map = "<name>"; | ||
126 | where name is one of: | ||
127 | - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also | ||
128 | referred to as "ARM Cortex-A Series memory map": | ||
129 | arm,v2m-memory-map = "rs1"; | ||
130 | When this property is missing, the motherboard is using the original | ||
131 | memory map (also known as the "Legacy memory map", primarily used | ||
132 | with the original CoreTile Express A9x4) with peripherals on CS7. | ||
133 | |||
134 | Motherboard .dtsi files provide a set of labelled peripherals that | ||
135 | can be used to obtain required phandle in the tile's "aliases" node: | ||
136 | - UARTs, note that the numbers correspond to the physical connectors | ||
137 | on the motherboard's back panel: | ||
138 | v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3 | ||
139 | - I2C controllers: | ||
140 | v2m_i2c_dvi and v2m_i2c_pcie | ||
141 | - SP804 timers: | ||
142 | v2m_timer01 and v2m_timer23 | ||
143 | |||
144 | The tile description should define a "smb" node, describing the | ||
145 | Static Memory Bus between the tile and motherboard. It must define | ||
146 | the following properties: | ||
147 | - "simple-bus" compatible value (to ensure creation of the children) | ||
148 | compatible = "simple-bus"; | ||
149 | - mapping of the SMB CS/offset addresses into main address space: | ||
150 | #address-cells = <2>; | ||
151 | #size-cells = <1>; | ||
152 | ranges = <...>; | ||
153 | - interrupts mapping: | ||
154 | #interrupt-cells = <1>; | ||
155 | interrupt-map-mask = <0 0 63>; | ||
156 | interrupt-map = <...>; | ||
157 | |||
158 | |||
159 | Example of a VE tile description (simplified) | ||
160 | --------------------------------------------- | ||
161 | |||
162 | /dts-v1/; | ||
163 | |||
164 | / { | ||
165 | model = "V2P-CA5s"; | ||
166 | arm,hbi = <0x225>; | ||
167 | arm,vexpress,site = <0xf>; | ||
168 | compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress"; | ||
169 | interrupt-parent = <&gic>; | ||
170 | #address-cells = <1>; | ||
171 | #size-cells = <1>; | ||
172 | |||
173 | chosen { }; | ||
174 | |||
175 | aliases { | ||
176 | serial0 = &v2m_serial0; | ||
177 | }; | ||
178 | |||
179 | cpus { | ||
180 | #address-cells = <1>; | ||
181 | #size-cells = <0>; | ||
182 | |||
183 | cpu@0 { | ||
184 | device_type = "cpu"; | ||
185 | compatible = "arm,cortex-a5"; | ||
186 | reg = <0>; | ||
187 | }; | ||
188 | }; | ||
189 | |||
190 | gic: interrupt-controller@2c001000 { | ||
191 | compatible = "arm,cortex-a9-gic"; | ||
192 | #interrupt-cells = <3>; | ||
193 | #address-cells = <0>; | ||
194 | interrupt-controller; | ||
195 | reg = <0x2c001000 0x1000>, | ||
196 | <0x2c000100 0x100>; | ||
197 | }; | ||
198 | |||
199 | dcc { | ||
200 | compatible = "simple-bus"; | ||
201 | arm,vexpress,config-bridge = <&v2m_sysreg>; | ||
202 | |||
203 | osc@0 { | ||
204 | compatible = "arm,vexpress-osc"; | ||
205 | }; | ||
206 | }; | ||
207 | |||
208 | smb { | ||
209 | compatible = "simple-bus"; | ||
210 | |||
211 | #address-cells = <2>; | ||
212 | #size-cells = <1>; | ||
213 | /* CS0 is visible at 0x08000000 */ | ||
214 | ranges = <0 0 0x08000000 0x04000000>; | ||
215 | |||
216 | #interrupt-cells = <1>; | ||
217 | interrupt-map-mask = <0 0 63>; | ||
218 | /* Active high IRQ 0 is connected to GIC's SPI0 */ | ||
219 | interrupt-map = <0 0 0 &gic 0 0 4>; | ||
220 | |||
221 | /include/ "vexpress-v2m-rs1.dtsi" | ||
222 | }; | ||
223 | }; | ||
224 | |||
diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt deleted file mode 100644 index 266716b2343..00000000000 --- a/Documentation/devicetree/bindings/arm/vic.txt +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | * ARM Vectored Interrupt Controller | ||
2 | |||
3 | One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM | ||
4 | system for interrupt routing. For multiple controllers they can either be | ||
5 | nested or have the outputs wire-OR'd together. | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible : should be one of | ||
10 | "arm,pl190-vic" | ||
11 | "arm,pl192-vic" | ||
12 | - interrupt-controller : Identifies the node as an interrupt controller | ||
13 | - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as | ||
14 | the VIC has no configuration options for interrupt sources. The cell is a u32 | ||
15 | and defines the interrupt number. | ||
16 | - reg : The register bank for the VIC. | ||
17 | |||
18 | Optional properties: | ||
19 | |||
20 | - interrupts : Interrupt source for parent controllers if the VIC is nested. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | vic0: interrupt-controller@60000 { | ||
25 | compatible = "arm,pl192-vic"; | ||
26 | interrupt-controller; | ||
27 | #interrupt-cells = <1>; | ||
28 | reg = <0x60000 0x1000>; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt deleted file mode 100644 index d657832c681..00000000000 --- a/Documentation/devicetree/bindings/arm/vt8500.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500 Platforms Device Tree Bindings | ||
2 | --------------------------------------- | ||
3 | |||
4 | Boards with the VIA VT8500 SoC shall have the following properties: | ||
5 | Required root node property: | ||
6 | compatible = "via,vt8500"; | ||
7 | |||
8 | Boards with the Wondermedia WM8505 SoC shall have the following properties: | ||
9 | Required root node property: | ||
10 | compatible = "wm,wm8505"; | ||
11 | |||
12 | Boards with the Wondermedia WM8650 SoC shall have the following properties: | ||
13 | Required root node property: | ||
14 | compatible = "wm,wm8650"; | ||
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt deleted file mode 100644 index 0a4ce1051b0..00000000000 --- a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500 Interrupt Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "via,vt8500-intc" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | - #interrupt-cells : should be <1> | ||
8 | |||
9 | Example: | ||
10 | |||
11 | intc: interrupt-controller@d8140000 { | ||
12 | compatible = "via,vt8500-intc"; | ||
13 | interrupt-controller; | ||
14 | reg = <0xd8140000 0x10000>; | ||
15 | #interrupt-cells = <1>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt deleted file mode 100644 index 521b9c7de93..00000000000 --- a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500 Power Management Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "via,vt8500-pmc" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | |||
8 | Example: | ||
9 | |||
10 | pmc@d8130000 { | ||
11 | compatible = "via,vt8500-pmc"; | ||
12 | reg = <0xd8130000 0x1000>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt deleted file mode 100644 index 901c73f0d8e..00000000000 --- a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500 Timer | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "via,vt8500-timer" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | - interrupts : interrupt for the timer | ||
8 | |||
9 | Example: | ||
10 | |||
11 | timer@d8130100 { | ||
12 | compatible = "via,vt8500-timer"; | ||
13 | reg = <0xd8130100 0x28>; | ||
14 | interrupts = <36>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/xen.txt b/Documentation/devicetree/bindings/arm/xen.txt deleted file mode 100644 index 0f7b9c2109f..00000000000 --- a/Documentation/devicetree/bindings/arm/xen.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * Xen hypervisor device tree bindings | ||
2 | |||
3 | Xen ARM virtual platforms shall have a top-level "hypervisor" node with | ||
4 | the following properties: | ||
5 | |||
6 | - compatible: | ||
7 | compatible = "xen,xen-<version>", "xen,xen"; | ||
8 | where <version> is the version of the Xen ABI of the platform. | ||
9 | |||
10 | - reg: specifies the base physical address and size of a region in | ||
11 | memory where the grant table should be mapped to, using an | ||
12 | HYPERVISOR_memory_op hypercall. The memory region is large enough to map | ||
13 | the whole grant table (it is larger or equal to gnttab_max_grant_frames()). | ||
14 | |||
15 | - interrupts: the interrupt used by Xen to inject event notifications. | ||
16 | A GIC node is also required. | ||
17 | |||
18 | |||
19 | Example (assuming #address-cells = <2> and #size-cells = <2>): | ||
20 | |||
21 | hypervisor { | ||
22 | compatible = "xen,xen-4.3", "xen,xen"; | ||
23 | reg = <0 0xb0000000 0 0x20000>; | ||
24 | interrupts = <1 15 0xf08>; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt deleted file mode 100644 index b519f9b699c..00000000000 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * AHCI SATA Controller | ||
2 | |||
3 | SATA nodes are defined to describe on-chip Serial ATA controllers. | ||
4 | Each SATA controller should have its own node. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : compatible list, contains "calxeda,hb-ahci" or "snps,spear-ahci" | ||
8 | - interrupts : <interrupt mapping for SATA IRQ> | ||
9 | - reg : <registers mapping> | ||
10 | |||
11 | Optional properties: | ||
12 | - calxeda,port-phys: phandle-combophy and lane assignment, which maps each | ||
13 | SATA port to a combophy and a lane within that | ||
14 | combophy | ||
15 | - dma-coherent : Present if dma operations are coherent | ||
16 | |||
17 | Example: | ||
18 | sata@ffe08000 { | ||
19 | compatible = "calxeda,hb-ahci"; | ||
20 | reg = <0xffe08000 0x1000>; | ||
21 | interrupts = <115>; | ||
22 | calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1 | ||
23 | &combophy0 2 &combophy0 3>; | ||
24 | |||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt deleted file mode 100644 index 93986a5a801..00000000000 --- a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | * Compact Flash | ||
2 | |||
3 | The Cavium Compact Flash device is connected to the Octeon Boot Bus, | ||
4 | and is thus a child of the Boot Bus device. It can read and write | ||
5 | industry standard compact flash devices. | ||
6 | |||
7 | Properties: | ||
8 | - compatible: "cavium,ebt3000-compact-flash"; | ||
9 | |||
10 | Compatibility with many Cavium evaluation boards. | ||
11 | |||
12 | - reg: The base address of the the CF chip select banks. Depending on | ||
13 | the device configuration, there may be one or two banks. | ||
14 | |||
15 | - cavium,bus-width: The width of the connection to the CF devices. Valid | ||
16 | values are 8 and 16. | ||
17 | |||
18 | - cavium,true-ide: Optional, if present the CF connection is in True IDE mode. | ||
19 | |||
20 | - cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected | ||
21 | to this device. | ||
22 | |||
23 | Example: | ||
24 | compact-flash@5,0 { | ||
25 | compatible = "cavium,ebt3000-compact-flash"; | ||
26 | reg = <5 0 0x10000>, <6 0 0x10000>; | ||
27 | cavium,bus-width = <16>; | ||
28 | cavium,true-ide; | ||
29 | cavium,dma-engine-handle = <&dma0>; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt deleted file mode 100644 index 37824fac688..00000000000 --- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * Samsung SATA PHY Controller | ||
2 | |||
3 | SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. | ||
4 | Each SATA PHY controller should have its own node. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : compatible list, contains "samsung,exynos5-sata-phy" | ||
8 | - reg : <registers mapping> | ||
9 | |||
10 | Example: | ||
11 | sata@ffe07000 { | ||
12 | compatible = "samsung,exynos5-sata-phy"; | ||
13 | reg = <0xffe07000 0x1000>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt deleted file mode 100644 index 0849f1025e3..00000000000 --- a/Documentation/devicetree/bindings/ata/exynos-sata.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * Samsung AHCI SATA Controller | ||
2 | |||
3 | SATA nodes are defined to describe on-chip Serial ATA controllers. | ||
4 | Each SATA controller should have its own node. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : compatible list, contains "samsung,exynos5-sata" | ||
8 | - interrupts : <interrupt mapping for SATA IRQ> | ||
9 | - reg : <registers mapping> | ||
10 | - samsung,sata-freq : <frequency in MHz> | ||
11 | |||
12 | Example: | ||
13 | sata@ffe08000 { | ||
14 | compatible = "samsung,exynos5-sata"; | ||
15 | reg = <0xffe08000 0x1000>; | ||
16 | interrupts = <115>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt deleted file mode 100644 index b5cdd20cde9..00000000000 --- a/Documentation/devicetree/bindings/ata/marvell.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | * Marvell Orion SATA | ||
2 | |||
3 | Required Properties: | ||
4 | - compatibility : "marvell,orion-sata" | ||
5 | - reg : Address range of controller | ||
6 | - interrupts : Interrupt controller is using | ||
7 | - nr-ports : Number of SATA ports in use. | ||
8 | |||
9 | Example: | ||
10 | |||
11 | sata@80000 { | ||
12 | compatible = "marvell,orion-sata"; | ||
13 | reg = <0x80000 0x5000>; | ||
14 | interrupts = <21>; | ||
15 | nr-ports = <2>; | ||
16 | } | ||
diff --git a/Documentation/devicetree/bindings/ata/pata-arasan.txt b/Documentation/devicetree/bindings/ata/pata-arasan.txt deleted file mode 100644 index 95ec7f825ed..00000000000 --- a/Documentation/devicetree/bindings/ata/pata-arasan.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * ARASAN PATA COMPACT FLASH CONTROLLER | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "arasan,cf-spear1340" | ||
5 | - reg: Address range of the CF registers | ||
6 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
7 | that services interrupts for this device | ||
8 | - interrupt: Should contain the CF interrupt number | ||
9 | |||
10 | Example: | ||
11 | |||
12 | cf@fc000000 { | ||
13 | compatible = "arasan,cf-spear1340"; | ||
14 | reg = <0xfc000000 0x1000>; | ||
15 | interrupt-parent = <&vic1>; | ||
16 | interrupts = <12>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt deleted file mode 100644 index 63dd8051521..00000000000 --- a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | * OMAP OCP2SCP - ocp interface to scp interface | ||
2 | |||
3 | properties: | ||
4 | - compatible : Should be "ti,omap-ocp2scp" | ||
5 | - reg : Address and length of the register set for the device | ||
6 | - #address-cells, #size-cells : Must be present if the device has sub-nodes | ||
7 | - ranges : the child address space are mapped 1:1 onto the parent address space | ||
8 | - ti,hwmods : must be "ocp2scp_usb_phy" | ||
9 | |||
10 | Sub-nodes: | ||
11 | All the devices connected to ocp2scp are described using sub-node to ocp2scp | ||
12 | |||
13 | ocp2scp@4a0ad000 { | ||
14 | compatible = "ti,omap-ocp2scp"; | ||
15 | reg = <0x4a0ad000 0x1f>; | ||
16 | #address-cells = <1>; | ||
17 | #size-cells = <1>; | ||
18 | ranges; | ||
19 | ti,hwmods = "ocp2scp_usb_phy"; | ||
20 | |||
21 | subnode1 { | ||
22 | ... | ||
23 | }; | ||
24 | |||
25 | subnode2 { | ||
26 | ... | ||
27 | }; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/c6x/clocks.txt b/Documentation/devicetree/bindings/c6x/clocks.txt deleted file mode 100644 index a04f5fd3012..00000000000 --- a/Documentation/devicetree/bindings/c6x/clocks.txt +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | C6X PLL Clock Controllers | ||
2 | ------------------------- | ||
3 | |||
4 | This is a first-cut support for the SoC clock controllers. This is still | ||
5 | under development and will probably change as the common device tree | ||
6 | clock support is added to the kernel. | ||
7 | |||
8 | Required properties: | ||
9 | |||
10 | - compatible: "ti,c64x+pll" | ||
11 | May also have SoC-specific value to support SoC-specific initialization | ||
12 | in the driver. One of: | ||
13 | "ti,c6455-pll" | ||
14 | "ti,c6457-pll" | ||
15 | "ti,c6472-pll" | ||
16 | "ti,c6474-pll" | ||
17 | |||
18 | - reg: base address and size of register area | ||
19 | - clock-frequency: input clock frequency in hz | ||
20 | |||
21 | |||
22 | Optional properties: | ||
23 | |||
24 | - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode | ||
25 | |||
26 | - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset | ||
27 | |||
28 | - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change | ||
29 | |||
30 | Example: | ||
31 | |||
32 | clock-controller@29a0000 { | ||
33 | compatible = "ti,c6472-pll", "ti,c64x+pll"; | ||
34 | reg = <0x029a0000 0x200>; | ||
35 | clock-frequency = <25000000>; | ||
36 | |||
37 | ti,c64x+pll-bypass-delay = <200>; | ||
38 | ti,c64x+pll-reset-delay = <12000>; | ||
39 | ti,c64x+pll-lock-delay = <80000>; | ||
40 | }; | ||
diff --git a/Documentation/devicetree/bindings/c6x/dscr.txt b/Documentation/devicetree/bindings/c6x/dscr.txt deleted file mode 100644 index d847758f2b2..00000000000 --- a/Documentation/devicetree/bindings/c6x/dscr.txt +++ /dev/null | |||
@@ -1,127 +0,0 @@ | |||
1 | Device State Configuration Registers | ||
2 | ------------------------------------ | ||
3 | |||
4 | TI C6X SoCs contain a region of miscellaneous registers which provide various | ||
5 | function for SoC control or status. Details vary considerably among from SoC | ||
6 | to SoC with no two being alike. | ||
7 | |||
8 | In general, the Device State Configuraion Registers (DSCR) will provide one or | ||
9 | more configuration registers often protected by a lock register where one or | ||
10 | more key values must be written to a lock register in order to unlock the | ||
11 | configuration register for writes. These configuration register may be used to | ||
12 | enable (and disable in some cases) SoC pin drivers, select peripheral clock | ||
13 | sources (internal or pin), etc. In some cases, a configuration register is | ||
14 | write once or the individual bits are write once. In addition to device config, | ||
15 | the DSCR block may provide registers which which are used to reset peripherals, | ||
16 | provide device ID information, provide ethernet MAC addresses, as well as other | ||
17 | miscellaneous functions. | ||
18 | |||
19 | For device state control (enable/disable), each device control is assigned an | ||
20 | id which is used by individual device drivers to control the state as needed. | ||
21 | |||
22 | Required properties: | ||
23 | |||
24 | - compatible: must be "ti,c64x+dscr" | ||
25 | - reg: register area base and size | ||
26 | |||
27 | Optional properties: | ||
28 | |||
29 | NOTE: These are optional in that not all SoCs will have all properties. For | ||
30 | SoCs which do support a given property, leaving the property out of the | ||
31 | device tree will result in reduced functionality or possibly driver | ||
32 | failure. | ||
33 | |||
34 | - ti,dscr-devstat | ||
35 | offset of the devstat register | ||
36 | |||
37 | - ti,dscr-silicon-rev | ||
38 | offset, start bit, and bitsize of silicon revision field | ||
39 | |||
40 | - ti,dscr-rmii-resets | ||
41 | offset and bitmask of RMII reset field. May have multiple tuples if more | ||
42 | than one ethernet port is available. | ||
43 | |||
44 | - ti,dscr-locked-regs | ||
45 | possibly multiple tuples describing registers which are write protected by | ||
46 | a lock register. Each tuple consists of the register offset, lock register | ||
47 | offsset, and the key value used to unlock the register. | ||
48 | |||
49 | - ti,dscr-kick-regs | ||
50 | offset and key values of two "kick" registers used to write protect other | ||
51 | registers in DSCR. On SoCs using kick registers, the first key must be | ||
52 | written to the first kick register and the second key must be written to | ||
53 | the second register before other registers in the area are write-enabled. | ||
54 | |||
55 | - ti,dscr-mac-fuse-regs | ||
56 | MAC addresses are contained in two registers. Each element of a MAC address | ||
57 | is contained in a single byte. This property has two tuples. Each tuple has | ||
58 | a register offset and four cells representing bytes in the register from | ||
59 | most significant to least. The value of these four cells is the MAC byte | ||
60 | index (1-6) of the byte within the register. A value of 0 means the byte | ||
61 | is unused in the MAC address. | ||
62 | |||
63 | - ti,dscr-devstate-ctl-regs | ||
64 | This property describes the bitfields used to control the state of devices. | ||
65 | Each tuple describes a range of identical bitfields used to control one or | ||
66 | more devices (one bitfield per device). The layout of each tuple is: | ||
67 | |||
68 | start_id num_ids reg enable disable start_bit nbits | ||
69 | |||
70 | Where: | ||
71 | start_id is device id for the first device control in the range | ||
72 | num_ids is the number of device controls in the range | ||
73 | reg is the offset of the register holding the control bits | ||
74 | enable is the value to enable a device | ||
75 | disable is the value to disable a device (0xffffffff if cannot disable) | ||
76 | start_bit is the bit number of the first bit in the range | ||
77 | nbits is the number of bits per device control | ||
78 | |||
79 | - ti,dscr-devstate-stat-regs | ||
80 | This property describes the bitfields used to provide device state status | ||
81 | for device states controlled by the DSCR. Each tuple describes a range of | ||
82 | identical bitfields used to provide status for one or more devices (one | ||
83 | bitfield per device). The layout of each tuple is: | ||
84 | |||
85 | start_id num_ids reg enable disable start_bit nbits | ||
86 | |||
87 | Where: | ||
88 | start_id is device id for the first device status in the range | ||
89 | num_ids is the number of devices covered by the range | ||
90 | reg is the offset of the register holding the status bits | ||
91 | enable is the value indicating device is enabled | ||
92 | disable is the value indicating device is disabled | ||
93 | start_bit is the bit number of the first bit in the range | ||
94 | nbits is the number of bits per device status | ||
95 | |||
96 | - ti,dscr-privperm | ||
97 | Offset and default value for register used to set access privilege for | ||
98 | some SoC devices. | ||
99 | |||
100 | |||
101 | Example: | ||
102 | |||
103 | device-state-config-regs@2a80000 { | ||
104 | compatible = "ti,c64x+dscr"; | ||
105 | reg = <0x02a80000 0x41000>; | ||
106 | |||
107 | ti,dscr-devstat = <0>; | ||
108 | ti,dscr-silicon-rev = <8 28 0xf>; | ||
109 | ti,dscr-rmii-resets = <0x40020 0x00040000>; | ||
110 | |||
111 | ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>; | ||
112 | ti,dscr-devstate-ctl-regs = | ||
113 | <0 12 0x40008 1 0 0 2 | ||
114 | 12 1 0x40008 3 0 30 2 | ||
115 | 13 2 0x4002c 1 0xffffffff 0 1>; | ||
116 | ti,dscr-devstate-stat-regs = | ||
117 | <0 10 0x40014 1 0 0 3 | ||
118 | 10 2 0x40018 1 0 0 3>; | ||
119 | |||
120 | ti,dscr-mac-fuse-regs = <0x700 1 2 3 4 | ||
121 | 0x704 5 6 0 0>; | ||
122 | |||
123 | ti,dscr-privperm = <0x41c 0xaaaaaaaa>; | ||
124 | |||
125 | ti,dscr-kick-regs = <0x38 0x83E70B13 | ||
126 | 0x3c 0x95A4F1E0>; | ||
127 | }; | ||
diff --git a/Documentation/devicetree/bindings/c6x/emifa.txt b/Documentation/devicetree/bindings/c6x/emifa.txt deleted file mode 100644 index 0ff6e9b9a13..00000000000 --- a/Documentation/devicetree/bindings/c6x/emifa.txt +++ /dev/null | |||
@@ -1,62 +0,0 @@ | |||
1 | External Memory Interface | ||
2 | ------------------------- | ||
3 | |||
4 | The emifa node describes a simple external bus controller found on some C6X | ||
5 | SoCs. This interface provides external busses with a number of chip selects. | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible: must be "ti,c64x+emifa", "simple-bus" | ||
10 | - reg: register area base and size | ||
11 | - #address-cells: must be 2 (chip-select + offset) | ||
12 | - #size-cells: must be 1 | ||
13 | - ranges: mapping from EMIFA space to parent space | ||
14 | |||
15 | |||
16 | Optional properties: | ||
17 | |||
18 | - ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR | ||
19 | |||
20 | - ti,emifa-burst-priority: | ||
21 | Number of memory transfers after which the EMIF will elevate the priority | ||
22 | of the oldest command in the command FIFO. Setting this field to 255 | ||
23 | disables this feature, thereby allowing old commands to stay in the FIFO | ||
24 | indefinitely. | ||
25 | |||
26 | - ti,emifa-ce-config: | ||
27 | Configuration values for each of the supported chip selects. | ||
28 | |||
29 | Example: | ||
30 | |||
31 | emifa@70000000 { | ||
32 | compatible = "ti,c64x+emifa", "simple-bus"; | ||
33 | #address-cells = <2>; | ||
34 | #size-cells = <1>; | ||
35 | reg = <0x70000000 0x100>; | ||
36 | ranges = <0x2 0x0 0xa0000000 0x00000008 | ||
37 | 0x3 0x0 0xb0000000 0x00400000 | ||
38 | 0x4 0x0 0xc0000000 0x10000000 | ||
39 | 0x5 0x0 0xD0000000 0x10000000>; | ||
40 | |||
41 | ti,dscr-dev-enable = <13>; | ||
42 | ti,emifa-burst-priority = <255>; | ||
43 | ti,emifa-ce-config = <0x00240120 | ||
44 | 0x00240120 | ||
45 | 0x00240122 | ||
46 | 0x00240122>; | ||
47 | |||
48 | flash@3,0 { | ||
49 | #address-cells = <1>; | ||
50 | #size-cells = <1>; | ||
51 | compatible = "cfi-flash"; | ||
52 | reg = <0x3 0x0 0x400000>; | ||
53 | bank-width = <1>; | ||
54 | device-width = <1>; | ||
55 | partition@0 { | ||
56 | reg = <0x0 0x400000>; | ||
57 | label = "NOR"; | ||
58 | }; | ||
59 | }; | ||
60 | }; | ||
61 | |||
62 | This shows a flash chip attached to chip select 3. | ||
diff --git a/Documentation/devicetree/bindings/c6x/interrupt.txt b/Documentation/devicetree/bindings/c6x/interrupt.txt deleted file mode 100644 index 42bb796cc4a..00000000000 --- a/Documentation/devicetree/bindings/c6x/interrupt.txt +++ /dev/null | |||
@@ -1,104 +0,0 @@ | |||
1 | C6X Interrupt Chips | ||
2 | ------------------- | ||
3 | |||
4 | * C64X+ Core Interrupt Controller | ||
5 | |||
6 | The core interrupt controller provides 16 prioritized interrupts to the | ||
7 | C64X+ core. Priority 0 and 1 are used for reset and NMI respectively. | ||
8 | Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt | ||
9 | sources coming from outside the core. | ||
10 | |||
11 | Required properties: | ||
12 | -------------------- | ||
13 | - compatible: Should be "ti,c64x+core-pic"; | ||
14 | - #interrupt-cells: <1> | ||
15 | |||
16 | Interrupt Specifier Definition | ||
17 | ------------------------------ | ||
18 | Single cell specifying the core interrupt priority level (4-15) where | ||
19 | 4 is highest priority and 15 is lowest priority. | ||
20 | |||
21 | Example | ||
22 | ------- | ||
23 | core_pic: interrupt-controller@0 { | ||
24 | interrupt-controller; | ||
25 | #interrupt-cells = <1>; | ||
26 | compatible = "ti,c64x+core-pic"; | ||
27 | }; | ||
28 | |||
29 | |||
30 | |||
31 | * C64x+ Megamodule Interrupt Controller | ||
32 | |||
33 | The megamodule PIC consists of four interrupt mupliplexers each of which | ||
34 | combine up to 32 interrupt inputs into a single interrupt output which | ||
35 | may be cascaded into the core interrupt controller. The megamodule PIC | ||
36 | has a total of 12 outputs cascading into the core interrupt controller. | ||
37 | One for each core interrupt priority level. In addition to the combined | ||
38 | interrupt sources, individual megamodule interrupts may be cascaded to | ||
39 | the core interrupt controller. When an individual interrupt is cascaded, | ||
40 | it is no longer handled through a megamodule interrupt combiner and is | ||
41 | considered to have the core interrupt controller as the parent. | ||
42 | |||
43 | Required properties: | ||
44 | -------------------- | ||
45 | - compatible: "ti,c64x+megamod-pic" | ||
46 | - interrupt-controller | ||
47 | - #interrupt-cells: <1> | ||
48 | - reg: base address and size of register area | ||
49 | - interrupt-parent: must be core interrupt controller | ||
50 | - interrupts: This should have four cells; one for each interrupt combiner. | ||
51 | The cells contain the core priority interrupt to which the | ||
52 | corresponding combiner output is wired. | ||
53 | |||
54 | Optional properties: | ||
55 | -------------------- | ||
56 | - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core | ||
57 | priority interrupts. The first cell corresponds to | ||
58 | core priority 4 and the last cell corresponds to | ||
59 | core priority 15. The value of each cell is the | ||
60 | megamodule interrupt source which is MUXed to | ||
61 | the core interrupt corresponding to the cell | ||
62 | position. Allowed values are 4 - 127. Mapping for | ||
63 | interrupts 0 - 3 (combined interrupt sources) are | ||
64 | ignored. | ||
65 | |||
66 | Interrupt Specifier Definition | ||
67 | ------------------------------ | ||
68 | Single cell specifying the megamodule interrupt source (4-127). Note that | ||
69 | interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will | ||
70 | use the core interrupt controller as their parent and the specifier will | ||
71 | be the core priority level, not the megamodule interrupt number. | ||
72 | |||
73 | Examples | ||
74 | -------- | ||
75 | megamod_pic: interrupt-controller@1800000 { | ||
76 | compatible = "ti,c64x+megamod-pic"; | ||
77 | interrupt-controller; | ||
78 | #interrupt-cells = <1>; | ||
79 | reg = <0x1800000 0x1000>; | ||
80 | interrupt-parent = <&core_pic>; | ||
81 | interrupts = < 12 13 14 15 >; | ||
82 | }; | ||
83 | |||
84 | This is a minimal example where all individual interrupts go through a | ||
85 | combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped | ||
86 | to interrupt 13, etc. | ||
87 | |||
88 | |||
89 | megamod_pic: interrupt-controller@1800000 { | ||
90 | compatible = "ti,c64x+megamod-pic"; | ||
91 | interrupt-controller; | ||
92 | #interrupt-cells = <1>; | ||
93 | reg = <0x1800000 0x1000>; | ||
94 | interrupt-parent = <&core_pic>; | ||
95 | interrupts = < 12 13 14 15 >; | ||
96 | ti,c64x+megamod-pic-mux = < 0 0 0 0 | ||
97 | 32 0 0 0 | ||
98 | 0 0 0 0 >; | ||
99 | }; | ||
100 | |||
101 | This the same as the first example except that megamodule interrupt 32 is | ||
102 | mapped directly to core priority interrupt 8. The node using this interrupt | ||
103 | must set the core controller as its interrupt parent and use 8 in the | ||
104 | interrupt specifier value. | ||
diff --git a/Documentation/devicetree/bindings/c6x/soc.txt b/Documentation/devicetree/bindings/c6x/soc.txt deleted file mode 100644 index b1e4973b576..00000000000 --- a/Documentation/devicetree/bindings/c6x/soc.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | C6X System-on-Chip | ||
2 | ------------------ | ||
3 | |||
4 | Required properties: | ||
5 | |||
6 | - compatible: "simple-bus" | ||
7 | - #address-cells: must be 1 | ||
8 | - #size-cells: must be 1 | ||
9 | - ranges | ||
10 | |||
11 | Optional properties: | ||
12 | |||
13 | - model: specific SoC model | ||
14 | |||
15 | - nodes for IP blocks within SoC | ||
16 | |||
17 | |||
18 | Example: | ||
19 | |||
20 | soc { | ||
21 | compatible = "simple-bus"; | ||
22 | model = "tms320c6455"; | ||
23 | #address-cells = <1>; | ||
24 | #size-cells = <1>; | ||
25 | ranges; | ||
26 | |||
27 | ... | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/c6x/timer64.txt b/Documentation/devicetree/bindings/c6x/timer64.txt deleted file mode 100644 index 95911fe7022..00000000000 --- a/Documentation/devicetree/bindings/c6x/timer64.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | Timer64 | ||
2 | ------- | ||
3 | |||
4 | The timer64 node describes C6X event timers. | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible: must be "ti,c64x+timer64" | ||
9 | - reg: base address and size of register region | ||
10 | - interrupt-parent: interrupt controller | ||
11 | - interrupts: interrupt id | ||
12 | |||
13 | Optional properties: | ||
14 | |||
15 | - ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface. | ||
16 | |||
17 | - ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer. | ||
18 | |||
19 | Example: | ||
20 | timer0: timer@25e0000 { | ||
21 | compatible = "ti,c64x+timer64"; | ||
22 | ti,core-mask = < 0x01 >; | ||
23 | reg = <0x25e0000 0x40>; | ||
24 | interrupt-parent = <&megamod_pic>; | ||
25 | interrupts = < 16 >; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt deleted file mode 100644 index 0a6ac1bdcda..00000000000 --- a/Documentation/devicetree/bindings/clock/calxeda.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | Device Tree Clock bindings for Calxeda highbank platform | ||
2 | |||
3 | This binding uses the common clock binding[1]. | ||
4 | |||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
6 | |||
7 | Required properties: | ||
8 | - compatible : shall be one of the following: | ||
9 | "calxeda,hb-pll-clock" - for a PLL clock | ||
10 | "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the | ||
11 | A9 clock. | ||
12 | "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock. | ||
13 | "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller. | ||
14 | - reg : shall be the control register offset from SYSREGs base for the clock. | ||
15 | - clocks : shall be the input parent clock phandle for the clock. This is | ||
16 | either an oscillator or a pll output. | ||
17 | - #clock-cells : from common clock binding; shall be set to 0. | ||
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt deleted file mode 100644 index eb65d417f8c..00000000000 --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt +++ /dev/null | |||
@@ -1,117 +0,0 @@ | |||
1 | This binding is a work-in-progress, and are based on some experimental | ||
2 | work by benh[1]. | ||
3 | |||
4 | Sources of clock signal can be represented by any node in the device | ||
5 | tree. Those nodes are designated as clock providers. Clock consumer | ||
6 | nodes use a phandle and clock specifier pair to connect clock provider | ||
7 | outputs to clock inputs. Similar to the gpio specifiers, a clock | ||
8 | specifier is an array of one more more cells identifying the clock | ||
9 | output on a device. The length of a clock specifier is defined by the | ||
10 | value of a #clock-cells property in the clock provider node. | ||
11 | |||
12 | [1] http://patchwork.ozlabs.org/patch/31551/ | ||
13 | |||
14 | ==Clock providers== | ||
15 | |||
16 | Required properties: | ||
17 | #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes | ||
18 | with a single clock output and 1 for nodes with multiple | ||
19 | clock outputs. | ||
20 | |||
21 | Optional properties: | ||
22 | clock-output-names: Recommended to be a list of strings of clock output signal | ||
23 | names indexed by the first cell in the clock specifier. | ||
24 | However, the meaning of clock-output-names is domain | ||
25 | specific to the clock provider, and is only provided to | ||
26 | encourage using the same meaning for the majority of clock | ||
27 | providers. This format may not work for clock providers | ||
28 | using a complex clock specifier format. In those cases it | ||
29 | is recommended to omit this property and create a binding | ||
30 | specific names property. | ||
31 | |||
32 | Clock consumer nodes must never directly reference | ||
33 | the provider's clock-output-names property. | ||
34 | |||
35 | For example: | ||
36 | |||
37 | oscillator { | ||
38 | #clock-cells = <1>; | ||
39 | clock-output-names = "ckil", "ckih"; | ||
40 | }; | ||
41 | |||
42 | - this node defines a device with two clock outputs, the first named | ||
43 | "ckil" and the second named "ckih". Consumer nodes always reference | ||
44 | clocks by index. The names should reflect the clock output signal | ||
45 | names for the device. | ||
46 | |||
47 | ==Clock consumers== | ||
48 | |||
49 | Required properties: | ||
50 | clocks: List of phandle and clock specifier pairs, one pair | ||
51 | for each clock input to the device. Note: if the | ||
52 | clock provider specifies '0' for #clock-cells, then | ||
53 | only the phandle portion of the pair will appear. | ||
54 | |||
55 | Optional properties: | ||
56 | clock-names: List of clock input name strings sorted in the same | ||
57 | order as the clocks property. Consumers drivers | ||
58 | will use clock-names to match clock input names | ||
59 | with clocks specifiers. | ||
60 | clock-ranges: Empty property indicating that child nodes can inherit named | ||
61 | clocks from this node. Useful for bus nodes to provide a | ||
62 | clock to their children. | ||
63 | |||
64 | For example: | ||
65 | |||
66 | device { | ||
67 | clocks = <&osc 1>, <&ref 0>; | ||
68 | clock-names = "baud", "register"; | ||
69 | }; | ||
70 | |||
71 | |||
72 | This represents a device with two clock inputs, named "baud" and "register". | ||
73 | The baud clock is connected to output 1 of the &osc device, and the register | ||
74 | clock is connected to output 0 of the &ref. | ||
75 | |||
76 | ==Example== | ||
77 | |||
78 | /* external oscillator */ | ||
79 | osc: oscillator { | ||
80 | compatible = "fixed-clock"; | ||
81 | #clock-cells = <1>; | ||
82 | clock-frequency = <32678>; | ||
83 | clock-output-names = "osc"; | ||
84 | }; | ||
85 | |||
86 | /* phase-locked-loop device, generates a higher frequency clock | ||
87 | * from the external oscillator reference */ | ||
88 | pll: pll@4c000 { | ||
89 | compatible = "vendor,some-pll-interface" | ||
90 | #clock-cells = <1>; | ||
91 | clocks = <&osc 0>; | ||
92 | clock-names = "ref"; | ||
93 | reg = <0x4c000 0x1000>; | ||
94 | clock-output-names = "pll", "pll-switched"; | ||
95 | }; | ||
96 | |||
97 | /* UART, using the low frequency oscillator for the baud clock, | ||
98 | * and the high frequency switched PLL output for register | ||
99 | * clocking */ | ||
100 | uart@a000 { | ||
101 | compatible = "fsl,imx-uart"; | ||
102 | reg = <0xa000 0x1000>; | ||
103 | interrupts = <33>; | ||
104 | clocks = <&osc 0>, <&pll 1>; | ||
105 | clock-names = "baud", "register"; | ||
106 | }; | ||
107 | |||
108 | This DT fragment defines three devices: an external oscillator to provide a | ||
109 | low-frequency reference clock, a PLL device to generate a higher frequency | ||
110 | clock signal, and a UART. | ||
111 | |||
112 | * The oscillator is fixed-frequency, and provides one clock output, named "osc". | ||
113 | * The PLL is both a clock provider and a clock consumer. It uses the clock | ||
114 | signal generated by the external oscillator, and provides two output signals | ||
115 | ("pll" and "pll-switched"). | ||
116 | * The UART has its baud clock connected the external oscillator and its | ||
117 | register clock connected to the PLL clock (the "pll-switched" signal) | ||
diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt deleted file mode 100644 index 0b1fe782409..00000000000 --- a/Documentation/devicetree/bindings/clock/fixed-clock.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | Binding for simple fixed-rate clock sources. | ||
2 | |||
3 | This binding uses the common clock binding[1]. | ||
4 | |||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
6 | |||
7 | Required properties: | ||
8 | - compatible : shall be "fixed-clock". | ||
9 | - #clock-cells : from common clock binding; shall be set to 0. | ||
10 | - clock-frequency : frequency of clock in Hz. Should be a single cell. | ||
11 | |||
12 | Optional properties: | ||
13 | - gpios : From common gpio binding; gpio connection to clock enable pin. | ||
14 | - clock-output-names : From common clock binding. | ||
15 | |||
16 | Example: | ||
17 | clock { | ||
18 | compatible = "fixed-clock"; | ||
19 | #clock-cells = <0>; | ||
20 | clock-frequency = <1000000000>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt deleted file mode 100644 index 5083c0b834b..00000000000 --- a/Documentation/devicetree/bindings/clock/imx23-clock.txt +++ /dev/null | |||
@@ -1,71 +0,0 @@ | |||
1 | * Clock bindings for Freescale i.MX23 | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,imx23-clkctrl" | ||
5 | - reg: Address and length of the register set | ||
6 | - #clock-cells: Should be <1> | ||
7 | |||
8 | The clock consumer should specify the desired clock by having the clock | ||
9 | ID in its "clocks" phandle cell. The following is a full list of i.MX23 | ||
10 | clocks and IDs. | ||
11 | |||
12 | Clock ID | ||
13 | ------------------ | ||
14 | ref_xtal 0 | ||
15 | pll 1 | ||
16 | ref_cpu 2 | ||
17 | ref_emi 3 | ||
18 | ref_pix 4 | ||
19 | ref_io 5 | ||
20 | saif_sel 6 | ||
21 | lcdif_sel 7 | ||
22 | gpmi_sel 8 | ||
23 | ssp_sel 9 | ||
24 | emi_sel 10 | ||
25 | cpu 11 | ||
26 | etm_sel 12 | ||
27 | cpu_pll 13 | ||
28 | cpu_xtal 14 | ||
29 | hbus 15 | ||
30 | xbus 16 | ||
31 | lcdif_div 17 | ||
32 | ssp_div 18 | ||
33 | gpmi_div 19 | ||
34 | emi_pll 20 | ||
35 | emi_xtal 21 | ||
36 | etm_div 22 | ||
37 | saif_div 23 | ||
38 | clk32k_div 24 | ||
39 | rtc 25 | ||
40 | adc 26 | ||
41 | spdif_div 27 | ||
42 | clk32k 28 | ||
43 | dri 29 | ||
44 | pwm 30 | ||
45 | filt 31 | ||
46 | uart 32 | ||
47 | ssp 33 | ||
48 | gpmi 34 | ||
49 | spdif 35 | ||
50 | emi 36 | ||
51 | saif 37 | ||
52 | lcdif 38 | ||
53 | etm 39 | ||
54 | usb 40 | ||
55 | usb_phy 41 | ||
56 | |||
57 | Examples: | ||
58 | |||
59 | clks: clkctrl@80040000 { | ||
60 | compatible = "fsl,imx23-clkctrl"; | ||
61 | reg = <0x80040000 0x2000>; | ||
62 | #clock-cells = <1>; | ||
63 | }; | ||
64 | |||
65 | auart0: serial@8006c000 { | ||
66 | compatible = "fsl,imx23-auart"; | ||
67 | reg = <0x8006c000 0x2000>; | ||
68 | interrupts = <24 25 23>; | ||
69 | clocks = <&clks 32>; | ||
70 | status = "disabled"; | ||
71 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt deleted file mode 100644 index db4f2f05c4d..00000000000 --- a/Documentation/devicetree/bindings/clock/imx25-clock.txt +++ /dev/null | |||
@@ -1,158 +0,0 @@ | |||
1 | * Clock bindings for Freescale i.MX25 | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,imx25-ccm" | ||
5 | - reg: Address and length of the register set | ||
6 | - interrupts: Should contain CCM interrupt | ||
7 | - #clock-cells: Should be <1> | ||
8 | |||
9 | The clock consumer should specify the desired clock by having the clock | ||
10 | ID in its "clocks" phandle cell. The following is a full list of i.MX25 | ||
11 | clocks and IDs. | ||
12 | |||
13 | Clock ID | ||
14 | --------------------------- | ||
15 | dummy 0 | ||
16 | osc 1 | ||
17 | mpll 2 | ||
18 | upll 3 | ||
19 | mpll_cpu_3_4 4 | ||
20 | cpu_sel 5 | ||
21 | cpu 6 | ||
22 | ahb 7 | ||
23 | usb_div 8 | ||
24 | ipg 9 | ||
25 | per0_sel 10 | ||
26 | per1_sel 11 | ||
27 | per2_sel 12 | ||
28 | per3_sel 13 | ||
29 | per4_sel 14 | ||
30 | per5_sel 15 | ||
31 | per6_sel 16 | ||
32 | per7_sel 17 | ||
33 | per8_sel 18 | ||
34 | per9_sel 19 | ||
35 | per10_sel 20 | ||
36 | per11_sel 21 | ||
37 | per12_sel 22 | ||
38 | per13_sel 23 | ||
39 | per14_sel 24 | ||
40 | per15_sel 25 | ||
41 | per0 26 | ||
42 | per1 27 | ||
43 | per2 28 | ||
44 | per3 29 | ||
45 | per4 30 | ||
46 | per5 31 | ||
47 | per6 32 | ||
48 | per7 33 | ||
49 | per8 34 | ||
50 | per9 35 | ||
51 | per10 36 | ||
52 | per11 37 | ||
53 | per12 38 | ||
54 | per13 39 | ||
55 | per14 40 | ||
56 | per15 41 | ||
57 | csi_ipg_per 42 | ||
58 | epit_ipg_per 43 | ||
59 | esai_ipg_per 44 | ||
60 | esdhc1_ipg_per 45 | ||
61 | esdhc2_ipg_per 46 | ||
62 | gpt_ipg_per 47 | ||
63 | i2c_ipg_per 48 | ||
64 | lcdc_ipg_per 49 | ||
65 | nfc_ipg_per 50 | ||
66 | owire_ipg_per 51 | ||
67 | pwm_ipg_per 52 | ||
68 | sim1_ipg_per 53 | ||
69 | sim2_ipg_per 54 | ||
70 | ssi1_ipg_per 55 | ||
71 | ssi2_ipg_per 56 | ||
72 | uart_ipg_per 57 | ||
73 | ata_ahb 58 | ||
74 | reserved 59 | ||
75 | csi_ahb 60 | ||
76 | emi_ahb 61 | ||
77 | esai_ahb 62 | ||
78 | esdhc1_ahb 63 | ||
79 | esdhc2_ahb 64 | ||
80 | fec_ahb 65 | ||
81 | lcdc_ahb 66 | ||
82 | rtic_ahb 67 | ||
83 | sdma_ahb 68 | ||
84 | slcdc_ahb 69 | ||
85 | usbotg_ahb 70 | ||
86 | reserved 71 | ||
87 | reserved 72 | ||
88 | reserved 73 | ||
89 | reserved 74 | ||
90 | can1_ipg 75 | ||
91 | can2_ipg 76 | ||
92 | csi_ipg 77 | ||
93 | cspi1_ipg 78 | ||
94 | cspi2_ipg 79 | ||
95 | cspi3_ipg 80 | ||
96 | dryice_ipg 81 | ||
97 | ect_ipg 82 | ||
98 | epit1_ipg 83 | ||
99 | epit2_ipg 84 | ||
100 | reserved 85 | ||
101 | esdhc1_ipg 86 | ||
102 | esdhc2_ipg 87 | ||
103 | fec_ipg 88 | ||
104 | reserved 89 | ||
105 | reserved 90 | ||
106 | reserved 91 | ||
107 | gpt1_ipg 92 | ||
108 | gpt2_ipg 93 | ||
109 | gpt3_ipg 94 | ||
110 | gpt4_ipg 95 | ||
111 | reserved 96 | ||
112 | reserved 97 | ||
113 | reserved 98 | ||
114 | iim_ipg 99 | ||
115 | reserved 100 | ||
116 | reserved 101 | ||
117 | kpp_ipg 102 | ||
118 | lcdc_ipg 103 | ||
119 | reserved 104 | ||
120 | pwm1_ipg 105 | ||
121 | pwm2_ipg 106 | ||
122 | pwm3_ipg 107 | ||
123 | pwm4_ipg 108 | ||
124 | rngb_ipg 109 | ||
125 | reserved 110 | ||
126 | scc_ipg 111 | ||
127 | sdma_ipg 112 | ||
128 | sim1_ipg 113 | ||
129 | sim2_ipg 114 | ||
130 | slcdc_ipg 115 | ||
131 | spba_ipg 116 | ||
132 | ssi1_ipg 117 | ||
133 | ssi2_ipg 118 | ||
134 | tsc_ipg 119 | ||
135 | uart1_ipg 120 | ||
136 | uart2_ipg 121 | ||
137 | uart3_ipg 122 | ||
138 | uart4_ipg 123 | ||
139 | uart5_ipg 124 | ||
140 | reserved 125 | ||
141 | wdt_ipg 126 | ||
142 | |||
143 | Examples: | ||
144 | |||
145 | clks: ccm@53f80000 { | ||
146 | compatible = "fsl,imx25-ccm"; | ||
147 | reg = <0x53f80000 0x4000>; | ||
148 | interrupts = <31>; | ||
149 | }; | ||
150 | |||
151 | uart1: serial@43f90000 { | ||
152 | compatible = "fsl,imx25-uart", "fsl,imx21-uart"; | ||
153 | reg = <0x43f90000 0x4000>; | ||
154 | interrupts = <45>; | ||
155 | clocks = <&clks 79>, <&clks 50>; | ||
156 | clock-names = "ipg", "per"; | ||
157 | status = "disabled"; | ||
158 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt deleted file mode 100644 index e6587af62ff..00000000000 --- a/Documentation/devicetree/bindings/clock/imx28-clock.txt +++ /dev/null | |||
@@ -1,94 +0,0 @@ | |||
1 | * Clock bindings for Freescale i.MX28 | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,imx28-clkctrl" | ||
5 | - reg: Address and length of the register set | ||
6 | - #clock-cells: Should be <1> | ||
7 | |||
8 | The clock consumer should specify the desired clock by having the clock | ||
9 | ID in its "clocks" phandle cell. The following is a full list of i.MX28 | ||
10 | clocks and IDs. | ||
11 | |||
12 | Clock ID | ||
13 | ------------------ | ||
14 | ref_xtal 0 | ||
15 | pll0 1 | ||
16 | pll1 2 | ||
17 | pll2 3 | ||
18 | ref_cpu 4 | ||
19 | ref_emi 5 | ||
20 | ref_io0 6 | ||
21 | ref_io1 7 | ||
22 | ref_pix 8 | ||
23 | ref_hsadc 9 | ||
24 | ref_gpmi 10 | ||
25 | saif0_sel 11 | ||
26 | saif1_sel 12 | ||
27 | gpmi_sel 13 | ||
28 | ssp0_sel 14 | ||
29 | ssp1_sel 15 | ||
30 | ssp2_sel 16 | ||
31 | ssp3_sel 17 | ||
32 | emi_sel 18 | ||
33 | etm_sel 19 | ||
34 | lcdif_sel 20 | ||
35 | cpu 21 | ||
36 | ptp_sel 22 | ||
37 | cpu_pll 23 | ||
38 | cpu_xtal 24 | ||
39 | hbus 25 | ||
40 | xbus 26 | ||
41 | ssp0_div 27 | ||
42 | ssp1_div 28 | ||
43 | ssp2_div 29 | ||
44 | ssp3_div 30 | ||
45 | gpmi_div 31 | ||
46 | emi_pll 32 | ||
47 | emi_xtal 33 | ||
48 | lcdif_div 34 | ||
49 | etm_div 35 | ||
50 | ptp 36 | ||
51 | saif0_div 37 | ||
52 | saif1_div 38 | ||
53 | clk32k_div 39 | ||
54 | rtc 40 | ||
55 | lradc 41 | ||
56 | spdif_div 42 | ||
57 | clk32k 43 | ||
58 | pwm 44 | ||
59 | uart 45 | ||
60 | ssp0 46 | ||
61 | ssp1 47 | ||
62 | ssp2 48 | ||
63 | ssp3 49 | ||
64 | gpmi 50 | ||
65 | spdif 51 | ||
66 | emi 52 | ||
67 | saif0 53 | ||
68 | saif1 54 | ||
69 | lcdif 55 | ||
70 | etm 56 | ||
71 | fec 57 | ||
72 | can0 58 | ||
73 | can1 59 | ||
74 | usb0 60 | ||
75 | usb1 61 | ||
76 | usb0_phy 62 | ||
77 | usb1_phy 63 | ||
78 | enet_out 64 | ||
79 | |||
80 | Examples: | ||
81 | |||
82 | clks: clkctrl@80040000 { | ||
83 | compatible = "fsl,imx28-clkctrl"; | ||
84 | reg = <0x80040000 0x2000>; | ||
85 | #clock-cells = <1>; | ||
86 | }; | ||
87 | |||
88 | auart0: serial@8006a000 { | ||
89 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | ||
90 | reg = <0x8006a000 0x2000>; | ||
91 | interrupts = <112 70 71>; | ||
92 | clocks = <&clks 45>; | ||
93 | status = "disabled"; | ||
94 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt deleted file mode 100644 index 04ad47876be..00000000000 --- a/Documentation/devicetree/bindings/clock/imx5-clock.txt +++ /dev/null | |||
@@ -1,191 +0,0 @@ | |||
1 | * Clock bindings for Freescale i.MX5 | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53 | ||
5 | - reg: Address and length of the register set | ||
6 | - interrupts: Should contain CCM interrupt | ||
7 | - #clock-cells: Should be <1> | ||
8 | |||
9 | The clock consumer should specify the desired clock by having the clock | ||
10 | ID in its "clocks" phandle cell. The following is a full list of i.MX5 | ||
11 | clocks and IDs. | ||
12 | |||
13 | Clock ID | ||
14 | --------------------------- | ||
15 | dummy 0 | ||
16 | ckil 1 | ||
17 | osc 2 | ||
18 | ckih1 3 | ||
19 | ckih2 4 | ||
20 | ahb 5 | ||
21 | ipg 6 | ||
22 | axi_a 7 | ||
23 | axi_b 8 | ||
24 | uart_pred 9 | ||
25 | uart_root 10 | ||
26 | esdhc_a_pred 11 | ||
27 | esdhc_b_pred 12 | ||
28 | esdhc_c_s 13 | ||
29 | esdhc_d_s 14 | ||
30 | emi_sel 15 | ||
31 | emi_slow_podf 16 | ||
32 | nfc_podf 17 | ||
33 | ecspi_pred 18 | ||
34 | ecspi_podf 19 | ||
35 | usboh3_pred 20 | ||
36 | usboh3_podf 21 | ||
37 | usb_phy_pred 22 | ||
38 | usb_phy_podf 23 | ||
39 | cpu_podf 24 | ||
40 | di_pred 25 | ||
41 | tve_di 26 | ||
42 | tve_s 27 | ||
43 | uart1_ipg_gate 28 | ||
44 | uart1_per_gate 29 | ||
45 | uart2_ipg_gate 30 | ||
46 | uart2_per_gate 31 | ||
47 | uart3_ipg_gate 32 | ||
48 | uart3_per_gate 33 | ||
49 | i2c1_gate 34 | ||
50 | i2c2_gate 35 | ||
51 | gpt_ipg_gate 36 | ||
52 | pwm1_ipg_gate 37 | ||
53 | pwm1_hf_gate 38 | ||
54 | pwm2_ipg_gate 39 | ||
55 | pwm2_hf_gate 40 | ||
56 | gpt_hf_gate 41 | ||
57 | fec_gate 42 | ||
58 | usboh3_per_gate 43 | ||
59 | esdhc1_ipg_gate 44 | ||
60 | esdhc2_ipg_gate 45 | ||
61 | esdhc3_ipg_gate 46 | ||
62 | esdhc4_ipg_gate 47 | ||
63 | ssi1_ipg_gate 48 | ||
64 | ssi2_ipg_gate 49 | ||
65 | ssi3_ipg_gate 50 | ||
66 | ecspi1_ipg_gate 51 | ||
67 | ecspi1_per_gate 52 | ||
68 | ecspi2_ipg_gate 53 | ||
69 | ecspi2_per_gate 54 | ||
70 | cspi_ipg_gate 55 | ||
71 | sdma_gate 56 | ||
72 | emi_slow_gate 57 | ||
73 | ipu_s 58 | ||
74 | ipu_gate 59 | ||
75 | nfc_gate 60 | ||
76 | ipu_di1_gate 61 | ||
77 | vpu_s 62 | ||
78 | vpu_gate 63 | ||
79 | vpu_reference_gate 64 | ||
80 | uart4_ipg_gate 65 | ||
81 | uart4_per_gate 66 | ||
82 | uart5_ipg_gate 67 | ||
83 | uart5_per_gate 68 | ||
84 | tve_gate 69 | ||
85 | tve_pred 70 | ||
86 | esdhc1_per_gate 71 | ||
87 | esdhc2_per_gate 72 | ||
88 | esdhc3_per_gate 73 | ||
89 | esdhc4_per_gate 74 | ||
90 | usb_phy_gate 75 | ||
91 | hsi2c_gate 76 | ||
92 | mipi_hsc1_gate 77 | ||
93 | mipi_hsc2_gate 78 | ||
94 | mipi_esc_gate 79 | ||
95 | mipi_hsp_gate 80 | ||
96 | ldb_di1_div_3_5 81 | ||
97 | ldb_di1_div 82 | ||
98 | ldb_di0_div_3_5 83 | ||
99 | ldb_di0_div 84 | ||
100 | ldb_di1_gate 85 | ||
101 | can2_serial_gate 86 | ||
102 | can2_ipg_gate 87 | ||
103 | i2c3_gate 88 | ||
104 | lp_apm 89 | ||
105 | periph_apm 90 | ||
106 | main_bus 91 | ||
107 | ahb_max 92 | ||
108 | aips_tz1 93 | ||
109 | aips_tz2 94 | ||
110 | tmax1 95 | ||
111 | tmax2 96 | ||
112 | tmax3 97 | ||
113 | spba 98 | ||
114 | uart_sel 99 | ||
115 | esdhc_a_sel 100 | ||
116 | esdhc_b_sel 101 | ||
117 | esdhc_a_podf 102 | ||
118 | esdhc_b_podf 103 | ||
119 | ecspi_sel 104 | ||
120 | usboh3_sel 105 | ||
121 | usb_phy_sel 106 | ||
122 | iim_gate 107 | ||
123 | usboh3_gate 108 | ||
124 | emi_fast_gate 109 | ||
125 | ipu_di0_gate 110 | ||
126 | gpc_dvfs 111 | ||
127 | pll1_sw 112 | ||
128 | pll2_sw 113 | ||
129 | pll3_sw 114 | ||
130 | ipu_di0_sel 115 | ||
131 | ipu_di1_sel 116 | ||
132 | tve_ext_sel 117 | ||
133 | mx51_mipi 118 | ||
134 | pll4_sw 119 | ||
135 | ldb_di1_sel 120 | ||
136 | di_pll4_podf 121 | ||
137 | ldb_di0_sel 122 | ||
138 | ldb_di0_gate 123 | ||
139 | usb_phy1_gate 124 | ||
140 | usb_phy2_gate 125 | ||
141 | per_lp_apm 126 | ||
142 | per_pred1 127 | ||
143 | per_pred2 128 | ||
144 | per_podf 129 | ||
145 | per_root 130 | ||
146 | ssi_apm 131 | ||
147 | ssi1_root_sel 132 | ||
148 | ssi2_root_sel 133 | ||
149 | ssi3_root_sel 134 | ||
150 | ssi_ext1_sel 135 | ||
151 | ssi_ext2_sel 136 | ||
152 | ssi_ext1_com_sel 137 | ||
153 | ssi_ext2_com_sel 138 | ||
154 | ssi1_root_pred 139 | ||
155 | ssi1_root_podf 140 | ||
156 | ssi2_root_pred 141 | ||
157 | ssi2_root_podf 142 | ||
158 | ssi_ext1_pred 143 | ||
159 | ssi_ext1_podf 144 | ||
160 | ssi_ext2_pred 145 | ||
161 | ssi_ext2_podf 146 | ||
162 | ssi1_root_gate 147 | ||
163 | ssi2_root_gate 148 | ||
164 | ssi3_root_gate 149 | ||
165 | ssi_ext1_gate 150 | ||
166 | ssi_ext2_gate 151 | ||
167 | epit1_ipg_gate 152 | ||
168 | epit1_hf_gate 153 | ||
169 | epit2_ipg_gate 154 | ||
170 | epit2_hf_gate 155 | ||
171 | can_sel 156 | ||
172 | can1_serial_gate 157 | ||
173 | can1_ipg_gate 158 | ||
174 | |||
175 | Examples (for mx53): | ||
176 | |||
177 | clks: ccm@53fd4000{ | ||
178 | compatible = "fsl,imx53-ccm"; | ||
179 | reg = <0x53fd4000 0x4000>; | ||
180 | interrupts = <0 71 0x04 0 72 0x04>; | ||
181 | #clock-cells = <1>; | ||
182 | }; | ||
183 | |||
184 | can1: can@53fc8000 { | ||
185 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | ||
186 | reg = <0x53fc8000 0x4000>; | ||
187 | interrupts = <82>; | ||
188 | clocks = <&clks 158>, <&clks 157>; | ||
189 | clock-names = "ipg", "per"; | ||
190 | status = "disabled"; | ||
191 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt deleted file mode 100644 index f73fdf59556..00000000000 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ /dev/null | |||
@@ -1,223 +0,0 @@ | |||
1 | * Clock bindings for Freescale i.MX6 Quad | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,imx6q-ccm" | ||
5 | - reg: Address and length of the register set | ||
6 | - interrupts: Should contain CCM interrupt | ||
7 | - #clock-cells: Should be <1> | ||
8 | |||
9 | The clock consumer should specify the desired clock by having the clock | ||
10 | ID in its "clocks" phandle cell. The following is a full list of i.MX6Q | ||
11 | clocks and IDs. | ||
12 | |||
13 | Clock ID | ||
14 | --------------------------- | ||
15 | dummy 0 | ||
16 | ckil 1 | ||
17 | ckih 2 | ||
18 | osc 3 | ||
19 | pll2_pfd0_352m 4 | ||
20 | pll2_pfd1_594m 5 | ||
21 | pll2_pfd2_396m 6 | ||
22 | pll3_pfd0_720m 7 | ||
23 | pll3_pfd1_540m 8 | ||
24 | pll3_pfd2_508m 9 | ||
25 | pll3_pfd3_454m 10 | ||
26 | pll2_198m 11 | ||
27 | pll3_120m 12 | ||
28 | pll3_80m 13 | ||
29 | pll3_60m 14 | ||
30 | twd 15 | ||
31 | step 16 | ||
32 | pll1_sw 17 | ||
33 | periph_pre 18 | ||
34 | periph2_pre 19 | ||
35 | periph_clk2_sel 20 | ||
36 | periph2_clk2_sel 21 | ||
37 | axi_sel 22 | ||
38 | esai_sel 23 | ||
39 | asrc_sel 24 | ||
40 | spdif_sel 25 | ||
41 | gpu2d_axi 26 | ||
42 | gpu3d_axi 27 | ||
43 | gpu2d_core_sel 28 | ||
44 | gpu3d_core_sel 29 | ||
45 | gpu3d_shader_sel 30 | ||
46 | ipu1_sel 31 | ||
47 | ipu2_sel 32 | ||
48 | ldb_di0_sel 33 | ||
49 | ldb_di1_sel 34 | ||
50 | ipu1_di0_pre_sel 35 | ||
51 | ipu1_di1_pre_sel 36 | ||
52 | ipu2_di0_pre_sel 37 | ||
53 | ipu2_di1_pre_sel 38 | ||
54 | ipu1_di0_sel 39 | ||
55 | ipu1_di1_sel 40 | ||
56 | ipu2_di0_sel 41 | ||
57 | ipu2_di1_sel 42 | ||
58 | hsi_tx_sel 43 | ||
59 | pcie_axi_sel 44 | ||
60 | ssi1_sel 45 | ||
61 | ssi2_sel 46 | ||
62 | ssi3_sel 47 | ||
63 | usdhc1_sel 48 | ||
64 | usdhc2_sel 49 | ||
65 | usdhc3_sel 50 | ||
66 | usdhc4_sel 51 | ||
67 | enfc_sel 52 | ||
68 | emi_sel 53 | ||
69 | emi_slow_sel 54 | ||
70 | vdo_axi_sel 55 | ||
71 | vpu_axi_sel 56 | ||
72 | cko1_sel 57 | ||
73 | periph 58 | ||
74 | periph2 59 | ||
75 | periph_clk2 60 | ||
76 | periph2_clk2 61 | ||
77 | ipg 62 | ||
78 | ipg_per 63 | ||
79 | esai_pred 64 | ||
80 | esai_podf 65 | ||
81 | asrc_pred 66 | ||
82 | asrc_podf 67 | ||
83 | spdif_pred 68 | ||
84 | spdif_podf 69 | ||
85 | can_root 70 | ||
86 | ecspi_root 71 | ||
87 | gpu2d_core_podf 72 | ||
88 | gpu3d_core_podf 73 | ||
89 | gpu3d_shader 74 | ||
90 | ipu1_podf 75 | ||
91 | ipu2_podf 76 | ||
92 | ldb_di0_podf 77 | ||
93 | ldb_di1_podf 78 | ||
94 | ipu1_di0_pre 79 | ||
95 | ipu1_di1_pre 80 | ||
96 | ipu2_di0_pre 81 | ||
97 | ipu2_di1_pre 82 | ||
98 | hsi_tx_podf 83 | ||
99 | ssi1_pred 84 | ||
100 | ssi1_podf 85 | ||
101 | ssi2_pred 86 | ||
102 | ssi2_podf 87 | ||
103 | ssi3_pred 88 | ||
104 | ssi3_podf 89 | ||
105 | uart_serial_podf 90 | ||
106 | usdhc1_podf 91 | ||
107 | usdhc2_podf 92 | ||
108 | usdhc3_podf 93 | ||
109 | usdhc4_podf 94 | ||
110 | enfc_pred 95 | ||
111 | enfc_podf 96 | ||
112 | emi_podf 97 | ||
113 | emi_slow_podf 98 | ||
114 | vpu_axi_podf 99 | ||
115 | cko1_podf 100 | ||
116 | axi 101 | ||
117 | mmdc_ch0_axi_podf 102 | ||
118 | mmdc_ch1_axi_podf 103 | ||
119 | arm 104 | ||
120 | ahb 105 | ||
121 | apbh_dma 106 | ||
122 | asrc 107 | ||
123 | can1_ipg 108 | ||
124 | can1_serial 109 | ||
125 | can2_ipg 110 | ||
126 | can2_serial 111 | ||
127 | ecspi1 112 | ||
128 | ecspi2 113 | ||
129 | ecspi3 114 | ||
130 | ecspi4 115 | ||
131 | ecspi5 116 | ||
132 | enet 117 | ||
133 | esai 118 | ||
134 | gpt_ipg 119 | ||
135 | gpt_ipg_per 120 | ||
136 | gpu2d_core 121 | ||
137 | gpu3d_core 122 | ||
138 | hdmi_iahb 123 | ||
139 | hdmi_isfr 124 | ||
140 | i2c1 125 | ||
141 | i2c2 126 | ||
142 | i2c3 127 | ||
143 | iim 128 | ||
144 | enfc 129 | ||
145 | ipu1 130 | ||
146 | ipu1_di0 131 | ||
147 | ipu1_di1 132 | ||
148 | ipu2 133 | ||
149 | ipu2_di0 134 | ||
150 | ldb_di0 135 | ||
151 | ldb_di1 136 | ||
152 | ipu2_di1 137 | ||
153 | hsi_tx 138 | ||
154 | mlb 139 | ||
155 | mmdc_ch0_axi 140 | ||
156 | mmdc_ch1_axi 141 | ||
157 | ocram 142 | ||
158 | openvg_axi 143 | ||
159 | pcie_axi 144 | ||
160 | pwm1 145 | ||
161 | pwm2 146 | ||
162 | pwm3 147 | ||
163 | pwm4 148 | ||
164 | per1_bch 149 | ||
165 | gpmi_bch_apb 150 | ||
166 | gpmi_bch 151 | ||
167 | gpmi_io 152 | ||
168 | gpmi_apb 153 | ||
169 | sata 154 | ||
170 | sdma 155 | ||
171 | spba 156 | ||
172 | ssi1 157 | ||
173 | ssi2 158 | ||
174 | ssi3 159 | ||
175 | uart_ipg 160 | ||
176 | uart_serial 161 | ||
177 | usboh3 162 | ||
178 | usdhc1 163 | ||
179 | usdhc2 164 | ||
180 | usdhc3 165 | ||
181 | usdhc4 166 | ||
182 | vdo_axi 167 | ||
183 | vpu_axi 168 | ||
184 | cko1 169 | ||
185 | pll1_sys 170 | ||
186 | pll2_bus 171 | ||
187 | pll3_usb_otg 172 | ||
188 | pll4_audio 173 | ||
189 | pll5_video 174 | ||
190 | pll8_mlb 175 | ||
191 | pll7_usb_host 176 | ||
192 | pll6_enet 177 | ||
193 | ssi1_ipg 178 | ||
194 | ssi2_ipg 179 | ||
195 | ssi3_ipg 180 | ||
196 | rom 181 | ||
197 | usbphy1 182 | ||
198 | usbphy2 183 | ||
199 | ldb_di0_div_3_5 184 | ||
200 | ldb_di1_div_3_5 185 | ||
201 | sata_ref 186 | ||
202 | sata_ref_100m 187 | ||
203 | pcie_ref 188 | ||
204 | pcie_ref_125m 189 | ||
205 | enet_ref 190 | ||
206 | |||
207 | Examples: | ||
208 | |||
209 | clks: ccm@020c4000 { | ||
210 | compatible = "fsl,imx6q-ccm"; | ||
211 | reg = <0x020c4000 0x4000>; | ||
212 | interrupts = <0 87 0x04 0 88 0x04>; | ||
213 | #clock-cells = <1>; | ||
214 | }; | ||
215 | |||
216 | uart1: serial@02020000 { | ||
217 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
218 | reg = <0x02020000 0x4000>; | ||
219 | interrupts = <0 26 0x04>; | ||
220 | clocks = <&clks 160>, <&clks 161>; | ||
221 | clock-names = "ipg", "per"; | ||
222 | status = "disabled"; | ||
223 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt deleted file mode 100644 index 1e662948661..00000000000 --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | * Core Clock bindings for Marvell MVEBU SoCs | ||
2 | |||
3 | Marvell MVEBU SoCs usually allow to determine core clock frequencies by | ||
4 | reading the Sample-At-Reset (SAR) register. The core clock consumer should | ||
5 | specify the desired clock by having the clock ID in its "clocks" phandle cell. | ||
6 | |||
7 | The following is a list of provided IDs and clock names on Armada 370/XP: | ||
8 | 0 = tclk (Internal Bus clock) | ||
9 | 1 = cpuclk (CPU clock) | ||
10 | 2 = nbclk (L2 Cache clock) | ||
11 | 3 = hclk (DRAM control clock) | ||
12 | 4 = dramclk (DDR clock) | ||
13 | |||
14 | The following is a list of provided IDs and clock names on Kirkwood and Dove: | ||
15 | 0 = tclk (Internal Bus clock) | ||
16 | 1 = cpuclk (CPU0 clock) | ||
17 | 2 = l2clk (L2 Cache clock derived from CPU0 clock) | ||
18 | 3 = ddrclk (DDR controller clock derived from CPU0 clock) | ||
19 | |||
20 | Required properties: | ||
21 | - compatible : shall be one of the following: | ||
22 | "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks | ||
23 | "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks | ||
24 | "marvell,dove-core-clock" - for Dove SoC core clocks | ||
25 | "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) | ||
26 | "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC | ||
27 | - reg : shall be the register address of the Sample-At-Reset (SAR) register | ||
28 | - #clock-cells : from common clock binding; shall be set to 1 | ||
29 | |||
30 | Optional properties: | ||
31 | - clock-output-names : from common clock binding; allows overwrite default clock | ||
32 | output names ("tclk", "cpuclk", "l2clk", "ddrclk") | ||
33 | |||
34 | Example: | ||
35 | |||
36 | core_clk: core-clocks@d0214 { | ||
37 | compatible = "marvell,dove-core-clock"; | ||
38 | reg = <0xd0214 0x4>; | ||
39 | #clock-cells = <1>; | ||
40 | }; | ||
41 | |||
42 | spi0: spi@10600 { | ||
43 | compatible = "marvell,orion-spi"; | ||
44 | /* ... */ | ||
45 | /* get tclk from core clock provider */ | ||
46 | clocks = <&core_clk 0>; | ||
47 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt deleted file mode 100644 index feb83013071..00000000000 --- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | Device Tree Clock bindings for cpu clock of Marvell EBU platforms | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : shall be one of the following: | ||
5 | "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP | ||
6 | - reg : Address and length of the clock complex register set | ||
7 | - #clock-cells : should be set to 1. | ||
8 | - clocks : shall be the input parent clock phandle for the clock. | ||
9 | |||
10 | cpuclk: clock-complex@d0018700 { | ||
11 | #clock-cells = <1>; | ||
12 | compatible = "marvell,armada-xp-cpu-clock"; | ||
13 | reg = <0xd0018700 0xA0>; | ||
14 | clocks = <&coreclk 1>; | ||
15 | } | ||
16 | |||
17 | cpu@0 { | ||
18 | compatible = "marvell,sheeva-v7"; | ||
19 | reg = <0>; | ||
20 | clocks = <&cpuclk 0>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt deleted file mode 100644 index 7337005ef5e..00000000000 --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +++ /dev/null | |||
@@ -1,119 +0,0 @@ | |||
1 | * Gated Clock bindings for Marvell Orion SoCs | ||
2 | |||
3 | Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save | ||
4 | some power. The clock consumer should specify the desired clock by having | ||
5 | the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to | ||
6 | the corresponding clock gating control bit in HW to ease manual clock lookup | ||
7 | in datasheet. | ||
8 | |||
9 | The following is a list of provided IDs for Armada 370: | ||
10 | ID Clock Peripheral | ||
11 | ----------------------------------- | ||
12 | 0 Audio AC97 Cntrl | ||
13 | 1 pex0_en PCIe 0 Clock out | ||
14 | 2 pex1_en PCIe 1 Clock out | ||
15 | 3 ge1 Gigabit Ethernet 1 | ||
16 | 4 ge0 Gigabit Ethernet 0 | ||
17 | 5 pex0 PCIe Cntrl 0 | ||
18 | 9 pex1 PCIe Cntrl 1 | ||
19 | 15 sata0 SATA Host 0 | ||
20 | 17 sdio SDHCI Host | ||
21 | 25 tdm Time Division Mplx | ||
22 | 28 ddr DDR Cntrl | ||
23 | 30 sata1 SATA Host 0 | ||
24 | |||
25 | The following is a list of provided IDs for Armada XP: | ||
26 | ID Clock Peripheral | ||
27 | ----------------------------------- | ||
28 | 0 audio Audio Cntrl | ||
29 | 1 ge3 Gigabit Ethernet 3 | ||
30 | 2 ge2 Gigabit Ethernet 2 | ||
31 | 3 ge1 Gigabit Ethernet 1 | ||
32 | 4 ge0 Gigabit Ethernet 0 | ||
33 | 5 pex0 PCIe Cntrl 0 | ||
34 | 6 pex1 PCIe Cntrl 1 | ||
35 | 7 pex2 PCIe Cntrl 2 | ||
36 | 8 pex3 PCIe Cntrl 3 | ||
37 | 13 bp | ||
38 | 14 sata0lnk | ||
39 | 15 sata0 SATA Host 0 | ||
40 | 16 lcd LCD Cntrl | ||
41 | 17 sdio SDHCI Host | ||
42 | 18 usb0 USB Host 0 | ||
43 | 19 usb1 USB Host 1 | ||
44 | 20 usb2 USB Host 2 | ||
45 | 22 xor0 XOR DMA 0 | ||
46 | 23 crypto CESA engine | ||
47 | 25 tdm Time Division Mplx | ||
48 | 28 xor1 XOR DMA 1 | ||
49 | 29 sata1lnk | ||
50 | 30 sata1 SATA Host 0 | ||
51 | |||
52 | The following is a list of provided IDs for Dove: | ||
53 | ID Clock Peripheral | ||
54 | ----------------------------------- | ||
55 | 0 usb0 USB Host 0 | ||
56 | 1 usb1 USB Host 1 | ||
57 | 2 ge Gigabit Ethernet | ||
58 | 3 sata SATA Host | ||
59 | 4 pex0 PCIe Cntrl 0 | ||
60 | 5 pex1 PCIe Cntrl 1 | ||
61 | 8 sdio0 SDHCI Host 0 | ||
62 | 9 sdio1 SDHCI Host 1 | ||
63 | 10 nand NAND Cntrl | ||
64 | 11 camera Camera Cntrl | ||
65 | 12 i2s0 I2S Cntrl 0 | ||
66 | 13 i2s1 I2S Cntrl 1 | ||
67 | 15 crypto CESA engine | ||
68 | 21 ac97 AC97 Cntrl | ||
69 | 22 pdma Peripheral DMA | ||
70 | 23 xor0 XOR DMA 0 | ||
71 | 24 xor1 XOR DMA 1 | ||
72 | 30 gephy Gigabit Ethernel PHY | ||
73 | Note: gephy(30) is implemented as a parent clock of ge(2) | ||
74 | |||
75 | The following is a list of provided IDs for Kirkwood: | ||
76 | ID Clock Peripheral | ||
77 | ----------------------------------- | ||
78 | 0 ge0 Gigabit Ethernet 0 | ||
79 | 2 pex0 PCIe Cntrl 0 | ||
80 | 3 usb0 USB Host 0 | ||
81 | 4 sdio SDIO Cntrl | ||
82 | 5 tsu Transp. Stream Unit | ||
83 | 6 dunit SDRAM Cntrl | ||
84 | 7 runit Runit | ||
85 | 8 xor0 XOR DMA 0 | ||
86 | 9 audio I2S Cntrl 0 | ||
87 | 14 sata0 SATA Host 0 | ||
88 | 15 sata1 SATA Host 1 | ||
89 | 16 xor1 XOR DMA 1 | ||
90 | 17 crypto CESA engine | ||
91 | 18 pex1 PCIe Cntrl 1 | ||
92 | 19 ge1 Gigabit Ethernet 0 | ||
93 | 20 tdm Time Division Mplx | ||
94 | |||
95 | Required properties: | ||
96 | - compatible : shall be one of the following: | ||
97 | "marvell,dove-gating-clock" - for Dove SoC clock gating | ||
98 | "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating | ||
99 | - reg : shall be the register address of the Clock Gating Control register | ||
100 | - #clock-cells : from common clock binding; shall be set to 1 | ||
101 | |||
102 | Optional properties: | ||
103 | - clocks : default parent clock phandle (e.g. tclk) | ||
104 | |||
105 | Example: | ||
106 | |||
107 | gate_clk: clock-gating-control@d0038 { | ||
108 | compatible = "marvell,dove-gating-clock"; | ||
109 | reg = <0xd0038 0x4>; | ||
110 | /* default parent clock is tclk */ | ||
111 | clocks = <&core_clk 0>; | ||
112 | #clock-cells = <1>; | ||
113 | }; | ||
114 | |||
115 | sdio0: sdio@92000 { | ||
116 | compatible = "marvell,dove-sdhci"; | ||
117 | /* get clk gate bit 8 (sdio0) */ | ||
118 | clocks = <&gate_clk 8>; | ||
119 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt deleted file mode 100644 index a880c70d004..00000000000 --- a/Documentation/devicetree/bindings/clock/vt8500.txt +++ /dev/null | |||
@@ -1,72 +0,0 @@ | |||
1 | Device Tree Clock bindings for arch-vt8500 | ||
2 | |||
3 | This binding uses the common clock binding[1]. | ||
4 | |||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
6 | |||
7 | Required properties: | ||
8 | - compatible : shall be one of the following: | ||
9 | "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock | ||
10 | "wm,wm8650-pll-clock" - for a WM8650 PLL clock | ||
11 | "via,vt8500-device-clock" - for a VT/WM device clock | ||
12 | |||
13 | Required properties for PLL clocks: | ||
14 | - reg : shall be the control register offset from PMC base for the pll clock. | ||
15 | - clocks : shall be the input parent clock phandle for the clock. This should | ||
16 | be the reference clock. | ||
17 | - #clock-cells : from common clock binding; shall be set to 0. | ||
18 | |||
19 | Required properties for device clocks: | ||
20 | - clocks : shall be the input parent clock phandle for the clock. This should | ||
21 | be a pll output. | ||
22 | - #clock-cells : from common clock binding; shall be set to 0. | ||
23 | |||
24 | |||
25 | Device Clocks | ||
26 | |||
27 | Device clocks are required to have one or both of the following sets of | ||
28 | properties: | ||
29 | |||
30 | |||
31 | Gated device clocks: | ||
32 | |||
33 | Required properties: | ||
34 | - enable-reg : shall be the register offset from PMC base for the enable | ||
35 | register. | ||
36 | - enable-bit : shall be the bit within enable-reg to enable/disable the clock. | ||
37 | |||
38 | |||
39 | Divisor device clocks: | ||
40 | |||
41 | Required property: | ||
42 | - divisor-reg : shall be the register offset from PMC base for the divisor | ||
43 | register. | ||
44 | Optional property: | ||
45 | - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f | ||
46 | if not specified. | ||
47 | |||
48 | |||
49 | For example: | ||
50 | |||
51 | ref25: ref25M { | ||
52 | #clock-cells = <0>; | ||
53 | compatible = "fixed-clock"; | ||
54 | clock-frequency = <25000000>; | ||
55 | }; | ||
56 | |||
57 | plla: plla { | ||
58 | #clock-cells = <0>; | ||
59 | compatible = "wm,wm8650-pll-clock"; | ||
60 | clocks = <&ref25>; | ||
61 | reg = <0x200>; | ||
62 | }; | ||
63 | |||
64 | sdhc: sdhc { | ||
65 | #clock-cells = <0>; | ||
66 | compatible = "via,vt8500-device-clock"; | ||
67 | clocks = <&pllb>; | ||
68 | divisor-reg = <0x328>; | ||
69 | divisor-mask = <0x3f>; | ||
70 | enable-reg = <0x254>; | ||
71 | enable-bit = <18>; | ||
72 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt deleted file mode 100644 index 23ae1db1bc1..00000000000 --- a/Documentation/devicetree/bindings/clock/zynq-7000.txt +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | Device Tree Clock bindings for the Zynq 7000 EPP | ||
2 | |||
3 | The Zynq EPP has several different clk providers, each with there own bindings. | ||
4 | The purpose of this document is to document their usage. | ||
5 | |||
6 | See clock_bindings.txt for more information on the generic clock bindings. | ||
7 | See Chapter 25 of Zynq TRM for more information about Zynq clocks. | ||
8 | |||
9 | == PLLs == | ||
10 | |||
11 | Used to describe the ARM_PLL, DDR_PLL, and IO_PLL. | ||
12 | |||
13 | Required properties: | ||
14 | - #clock-cells : shall be 0 (only one clock is output from this node) | ||
15 | - compatible : "xlnx,zynq-pll" | ||
16 | - reg : pair of u32 values, which are the address offsets within the SLCR | ||
17 | of the relevant PLL_CTRL register and PLL_CFG register respectively | ||
18 | - clocks : phandle for parent clock. should be the phandle for ps_clk | ||
19 | |||
20 | Optional properties: | ||
21 | - clock-output-names : name of the output clock | ||
22 | |||
23 | Example: | ||
24 | armpll: armpll { | ||
25 | #clock-cells = <0>; | ||
26 | compatible = "xlnx,zynq-pll"; | ||
27 | clocks = <&ps_clk>; | ||
28 | reg = <0x100 0x110>; | ||
29 | clock-output-names = "armpll"; | ||
30 | }; | ||
31 | |||
32 | == Peripheral clocks == | ||
33 | |||
34 | Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks. | ||
35 | |||
36 | Required properties: | ||
37 | - #clock-cells : shall be 1 | ||
38 | - compatible : "xlnx,zynq-periph-clock" | ||
39 | - reg : a single u32 value, describing the offset within the SLCR where | ||
40 | the CLK_CTRL register is found for this peripheral | ||
41 | - clocks : phandle for parent clocks. should hold phandles for | ||
42 | the IO_PLL, ARM_PLL, and DDR_PLL in order | ||
43 | - clock-output-names : names of the output clock(s). For peripherals that have | ||
44 | two output clocks (for example, the UART), two clocks | ||
45 | should be listed. | ||
46 | |||
47 | Example: | ||
48 | uart_clk: uart_clk { | ||
49 | #clock-cells = <1>; | ||
50 | compatible = "xlnx,zynq-periph-clock"; | ||
51 | clocks = <&iopll &armpll &ddrpll>; | ||
52 | reg = <0x154>; | ||
53 | clock-output-names = "uart0_ref_clk", | ||
54 | "uart1_ref_clk"; | ||
55 | }; | ||
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt deleted file mode 100644 index 4416ccc3347..00000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | Generic CPU0 cpufreq driver | ||
2 | |||
3 | It is a generic cpufreq driver for CPU0 frequency management. It | ||
4 | supports both uniprocessor (UP) and symmetric multiprocessor (SMP) | ||
5 | systems which share clock and voltage across all CPUs. | ||
6 | |||
7 | Both required and optional properties listed below must be defined | ||
8 | under node /cpus/cpu@0. | ||
9 | |||
10 | Required properties: | ||
11 | - operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt | ||
12 | for details | ||
13 | |||
14 | Optional properties: | ||
15 | - clock-latency: Specify the possible maximum transition latency for clock, | ||
16 | in unit of nanoseconds. | ||
17 | - voltage-tolerance: Specify the CPU voltage tolerance in percentage. | ||
18 | |||
19 | Examples: | ||
20 | |||
21 | cpus { | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | |||
25 | cpu@0 { | ||
26 | compatible = "arm,cortex-a9"; | ||
27 | reg = <0>; | ||
28 | next-level-cache = <&L2>; | ||
29 | operating-points = < | ||
30 | /* kHz uV */ | ||
31 | 792000 1100000 | ||
32 | 396000 950000 | ||
33 | 198000 850000 | ||
34 | >; | ||
35 | transition-latency = <61036>; /* two CLK32 periods */ | ||
36 | }; | ||
37 | |||
38 | cpu@1 { | ||
39 | compatible = "arm,cortex-a9"; | ||
40 | reg = <1>; | ||
41 | next-level-cache = <&L2>; | ||
42 | }; | ||
43 | |||
44 | cpu@2 { | ||
45 | compatible = "arm,cortex-a9"; | ||
46 | reg = <2>; | ||
47 | next-level-cache = <&L2>; | ||
48 | }; | ||
49 | |||
50 | cpu@3 { | ||
51 | compatible = "arm,cortex-a9"; | ||
52 | reg = <3>; | ||
53 | next-level-cache = <&L2>; | ||
54 | }; | ||
55 | }; | ||
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt deleted file mode 100644 index f3d44984d91..00000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt +++ /dev/null | |||
@@ -1,42 +0,0 @@ | |||
1 | SPEAr cpufreq driver | ||
2 | ------------------- | ||
3 | |||
4 | SPEAr SoC cpufreq driver for CPU frequency scaling. | ||
5 | It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems | ||
6 | which share clock across all CPUs. | ||
7 | |||
8 | Required properties: | ||
9 | - cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the | ||
10 | increasing order. | ||
11 | |||
12 | Optional properties: | ||
13 | - clock-latency: Specify the possible maximum transition latency for clock, in | ||
14 | unit of nanoseconds. | ||
15 | |||
16 | Both required and optional properties listed above must be defined under node | ||
17 | /cpus/cpu@0. | ||
18 | |||
19 | Examples: | ||
20 | -------- | ||
21 | cpus { | ||
22 | |||
23 | <...> | ||
24 | |||
25 | cpu@0 { | ||
26 | compatible = "arm,cortex-a9"; | ||
27 | reg = <0>; | ||
28 | |||
29 | <...> | ||
30 | |||
31 | cpufreq_tbl = < 166000 | ||
32 | 200000 | ||
33 | 250000 | ||
34 | 300000 | ||
35 | 400000 | ||
36 | 500000 | ||
37 | 600000 >; | ||
38 | }; | ||
39 | |||
40 | <...> | ||
41 | |||
42 | }; | ||
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index fc9ce6f1688..bf57ecd5d73 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt | |||
@@ -9,7 +9,6 @@ Copyright (C) 2008-2011 Freescale Semiconductor Inc. | |||
9 | -Run Time Integrity Check (RTIC) Node | 9 | -Run Time Integrity Check (RTIC) Node |
10 | -Run Time Integrity Check (RTIC) Memory Node | 10 | -Run Time Integrity Check (RTIC) Memory Node |
11 | -Secure Non-Volatile Storage (SNVS) Node | 11 | -Secure Non-Volatile Storage (SNVS) Node |
12 | -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node | ||
13 | -Full Example | 12 | -Full Example |
14 | 13 | ||
15 | NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator | 14 | NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator |
@@ -54,8 +53,7 @@ PROPERTIES | |||
54 | - compatible | 53 | - compatible |
55 | Usage: required | 54 | Usage: required |
56 | Value type: <string> | 55 | Value type: <string> |
57 | Definition: Must include "fsl,sec-v4.0". Also includes SEC | 56 | Definition: Must include "fsl,sec-v4.0" |
58 | ERA versions (optional) with which the device is compatible. | ||
59 | 57 | ||
60 | - #address-cells | 58 | - #address-cells |
61 | Usage: required | 59 | Usage: required |
@@ -107,7 +105,7 @@ PROPERTIES | |||
107 | 105 | ||
108 | EXAMPLE | 106 | EXAMPLE |
109 | crypto@300000 { | 107 | crypto@300000 { |
110 | compatible = "fsl,sec-v4.0", "fsl,sec-era-v2.0"; | 108 | compatible = "fsl,sec-v4.0"; |
111 | #address-cells = <1>; | 109 | #address-cells = <1>; |
112 | #size-cells = <1>; | 110 | #size-cells = <1>; |
113 | reg = <0x300000 0x10000>; | 111 | reg = <0x300000 0x10000>; |
@@ -296,27 +294,6 @@ Secure Non-Volatile Storage (SNVS) Node | |||
296 | address and length of the SEC4 configuration | 294 | address and length of the SEC4 configuration |
297 | registers. | 295 | registers. |
298 | 296 | ||
299 | - #address-cells | ||
300 | Usage: required | ||
301 | Value type: <u32> | ||
302 | Definition: A standard property. Defines the number of cells | ||
303 | for representing physical addresses in child nodes. Must | ||
304 | have a value of 1. | ||
305 | |||
306 | - #size-cells | ||
307 | Usage: required | ||
308 | Value type: <u32> | ||
309 | Definition: A standard property. Defines the number of cells | ||
310 | for representing the size of physical addresses in | ||
311 | child nodes. Must have a value of 1. | ||
312 | |||
313 | - ranges | ||
314 | Usage: required | ||
315 | Value type: <prop-encoded-array> | ||
316 | Definition: A standard property. Specifies the physical address | ||
317 | range of the SNVS register space. A triplet that includes | ||
318 | the child address, parent address, & length. | ||
319 | |||
320 | - interrupts | 297 | - interrupts |
321 | Usage: required | 298 | Usage: required |
322 | Value type: <prop_encoded-array> | 299 | Value type: <prop_encoded-array> |
@@ -337,34 +314,11 @@ EXAMPLE | |||
337 | sec_mon@314000 { | 314 | sec_mon@314000 { |
338 | compatible = "fsl,sec-v4.0-mon"; | 315 | compatible = "fsl,sec-v4.0-mon"; |
339 | reg = <0x314000 0x1000>; | 316 | reg = <0x314000 0x1000>; |
340 | ranges = <0 0x314000 0x1000>; | ||
341 | interrupt-parent = <&mpic>; | 317 | interrupt-parent = <&mpic>; |
342 | interrupts = <93 2>; | 318 | interrupts = <93 2>; |
343 | }; | 319 | }; |
344 | 320 | ||
345 | ===================================================================== | 321 | ===================================================================== |
346 | Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node | ||
347 | |||
348 | A SNVS child node that defines SNVS LP RTC. | ||
349 | |||
350 | - compatible | ||
351 | Usage: required | ||
352 | Value type: <string> | ||
353 | Definition: Must include "fsl,sec-v4.0-mon-rtc-lp". | ||
354 | |||
355 | - reg | ||
356 | Usage: required | ||
357 | Value type: <prop-encoded-array> | ||
358 | Definition: A standard property. Specifies the physical | ||
359 | address and length of the SNVS LP configuration registers. | ||
360 | |||
361 | EXAMPLE | ||
362 | sec_mon_rtc_lp@314000 { | ||
363 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | ||
364 | reg = <0x34 0x58>; | ||
365 | }; | ||
366 | |||
367 | ===================================================================== | ||
368 | FULL EXAMPLE | 322 | FULL EXAMPLE |
369 | 323 | ||
370 | crypto: crypto@300000 { | 324 | crypto: crypto@300000 { |
@@ -436,14 +390,8 @@ FULL EXAMPLE | |||
436 | sec_mon: sec_mon@314000 { | 390 | sec_mon: sec_mon@314000 { |
437 | compatible = "fsl,sec-v4.0-mon"; | 391 | compatible = "fsl,sec-v4.0-mon"; |
438 | reg = <0x314000 0x1000>; | 392 | reg = <0x314000 0x1000>; |
439 | ranges = <0 0x314000 0x1000>; | ||
440 | interrupt-parent = <&mpic>; | 393 | interrupt-parent = <&mpic>; |
441 | interrupts = <93 2>; | 394 | interrupts = <93 2>; |
442 | |||
443 | sec_mon_rtc_lp@34 { | ||
444 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | ||
445 | reg = <0x34 0x58>; | ||
446 | }; | ||
447 | }; | 395 | }; |
448 | 396 | ||
449 | ===================================================================== | 397 | ===================================================================== |
diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt deleted file mode 100644 index 47229b1a594..00000000000 --- a/Documentation/devicetree/bindings/crypto/mv_cesa.txt +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | Marvell Cryptographic Engines And Security Accelerator | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "marvell,orion-crypto" | ||
5 | - reg : base physical address of the engine and length of memory mapped | ||
6 | region, followed by base physical address of sram and its memory | ||
7 | length | ||
8 | - reg-names : "regs" , "sram"; | ||
9 | - interrupts : interrupt number | ||
10 | |||
11 | Examples: | ||
12 | |||
13 | crypto@30000 { | ||
14 | compatible = "marvell,orion-crypto"; | ||
15 | reg = <0x30000 0x10000>, | ||
16 | <0x4000000 0x800>; | ||
17 | reg-names = "regs" , "sram"; | ||
18 | interrupts = <22>; | ||
19 | status = "okay"; | ||
20 | }; | ||
diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt deleted file mode 100644 index d8609ece1f4..00000000000 --- a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings | ||
2 | |||
3 | Picochip picoXcell devices contain crypto offload engines that may be used for | ||
4 | IPSEC and femtocell layer 2 ciphering. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine | ||
8 | "picochip,spacc-l2" for the femtocell layer 2 ciphering engine. | ||
9 | - reg : Offset and length of the register set for this device | ||
10 | - interrupt-parent : The interrupt controller that controls the SPAcc | ||
11 | interrupt. | ||
12 | - interrupts : The interrupt line from the SPAcc. | ||
13 | - ref-clock : The input clock that drives the SPAcc. | ||
14 | |||
15 | Example SPAcc node: | ||
16 | |||
17 | spacc@10000 { | ||
18 | compatible = "picochip,spacc-ipsec"; | ||
19 | reg = <0x100000 0x10000>; | ||
20 | interrupt-parent = <&vic0>; | ||
21 | interrupts = <24>; | ||
22 | ref-clock = <&ipsec_clk>, "ref"; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/arm-pl330.txt b/Documentation/devicetree/bindings/dma/arm-pl330.txt deleted file mode 100644 index 36e27d54260..00000000000 --- a/Documentation/devicetree/bindings/dma/arm-pl330.txt +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | * ARM PrimeCell PL330 DMA Controller | ||
2 | |||
3 | The ARM PrimeCell PL330 DMA controller can move blocks of memory contents | ||
4 | between memory and peripherals or memory to memory. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: should include both "arm,pl330" and "arm,primecell". | ||
8 | - reg: physical base address of the controller and length of memory mapped | ||
9 | region. | ||
10 | - interrupts: interrupt number to the cpu. | ||
11 | |||
12 | Optional properties: | ||
13 | - dma-coherent : Present if dma operations are coherent | ||
14 | |||
15 | Example: | ||
16 | |||
17 | pdma0: pdma@12680000 { | ||
18 | compatible = "arm,pl330", "arm,primecell"; | ||
19 | reg = <0x12680000 0x1000>; | ||
20 | interrupts = <99>; | ||
21 | }; | ||
22 | |||
23 | Client drivers (device nodes requiring dma transfers from dev-to-mem or | ||
24 | mem-to-dev) should specify the DMA channel numbers using a two-value pair | ||
25 | as shown below. | ||
26 | |||
27 | [property name] = <[phandle of the dma controller] [dma request id]>; | ||
28 | |||
29 | where 'dma request id' is the dma request number which is connected | ||
30 | to the client controller. The 'property name' is recommended to be | ||
31 | of the form <name>-dma-channel. | ||
32 | |||
33 | Example: tx-dma-channel = <&pdma0 12>; | ||
diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt deleted file mode 100644 index 3c046ee6e8b..00000000000 --- a/Documentation/devicetree/bindings/dma/atmel-dma.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * Atmel Direct Memory Access Controller (DMA) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "atmel,<chip>-dma" | ||
5 | - reg: Should contain DMA registers location and length | ||
6 | - interrupts: Should contain DMA interrupt | ||
7 | |||
8 | Examples: | ||
9 | |||
10 | dma@ffffec00 { | ||
11 | compatible = "atmel,at91sam9g45-dma"; | ||
12 | reg = <0xffffec00 0x200>; | ||
13 | interrupts = <21>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt deleted file mode 100644 index ded0398d3bd..00000000000 --- a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | * Freescale MXS DMA | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx" | ||
5 | - reg : Should contain registers location and length | ||
6 | |||
7 | Supported chips: | ||
8 | imx23, imx28. | ||
9 | |||
10 | Examples: | ||
11 | dma-apbh@80004000 { | ||
12 | compatible = "fsl,imx28-dma-apbh"; | ||
13 | reg = <0x80004000 2000>; | ||
14 | }; | ||
15 | |||
16 | dma-apbx@80024000 { | ||
17 | compatible = "fsl,imx28-dma-apbx"; | ||
18 | reg = <0x80024000 2000>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt deleted file mode 100644 index a4fa4efa1d8..00000000000 --- a/Documentation/devicetree/bindings/dma/mmp-dma.txt +++ /dev/null | |||
@@ -1,74 +0,0 @@ | |||
1 | * MARVELL MMP DMA controller | ||
2 | |||
3 | Marvell Peripheral DMA Controller | ||
4 | Used platfroms: pxa688, pxa910, pxa3xx, etc | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: Should be "marvell,pdma-1.0" | ||
8 | - reg: Should contain DMA registers location and length. | ||
9 | - interrupts: Either contain all of the per-channel DMA interrupts | ||
10 | or one irq for pdma device | ||
11 | - #dma-channels: Number of DMA channels supported by the controller. | ||
12 | |||
13 | "marvell,pdma-1.0" | ||
14 | Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688. | ||
15 | |||
16 | Examples: | ||
17 | |||
18 | /* | ||
19 | * Each channel has specific irq | ||
20 | * ICU parse out irq channel from ICU register, | ||
21 | * while DMA controller may not able to distinguish the irq channel | ||
22 | * Using this method, interrupt-parent is required as demuxer | ||
23 | * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq, | ||
24 | * 18~21 is ADMA irq | ||
25 | */ | ||
26 | pdma: dma-controller@d4000000 { | ||
27 | compatible = "marvell,pdma-1.0"; | ||
28 | reg = <0xd4000000 0x10000>; | ||
29 | interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; | ||
30 | interrupt-parent = <&intcmux32>; | ||
31 | #dma-channels = <16>; | ||
32 | }; | ||
33 | |||
34 | /* | ||
35 | * One irq for all channels | ||
36 | * Dmaengine driver (DMA controller) distinguish irq channel via | ||
37 | * parsing internal register | ||
38 | */ | ||
39 | pdma: dma-controller@d4000000 { | ||
40 | compatible = "marvell,pdma-1.0"; | ||
41 | reg = <0xd4000000 0x10000>; | ||
42 | interrupts = <47>; | ||
43 | #dma-channels = <16>; | ||
44 | }; | ||
45 | |||
46 | |||
47 | Marvell Two Channel DMA Controller used specifically for audio | ||
48 | Used platfroms: pxa688, pxa910 | ||
49 | |||
50 | Required properties: | ||
51 | - compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ" | ||
52 | - reg: Should contain DMA registers location and length. | ||
53 | - interrupts: Either contain all of the per-channel DMA interrupts | ||
54 | or one irq for dma device | ||
55 | |||
56 | "marvell,adma-1.0" used on pxa688 | ||
57 | "marvell,pxa910-squ" used on pxa910 | ||
58 | |||
59 | Examples: | ||
60 | |||
61 | /* each channel has specific irq */ | ||
62 | adma0: dma-controller@d42a0800 { | ||
63 | compatible = "marvell,adma-1.0"; | ||
64 | reg = <0xd42a0800 0x100>; | ||
65 | interrupts = <18 19>; | ||
66 | interrupt-parent = <&intcmux32>; | ||
67 | }; | ||
68 | |||
69 | /* One irq for all channels */ | ||
70 | squ: dma-controller@d42a0800 { | ||
71 | compatible = "marvell,pxa910-squ"; | ||
72 | reg = <0xd42a0800 0x100>; | ||
73 | interrupts = <46>; | ||
74 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/mv-xor.txt b/Documentation/devicetree/bindings/dma/mv-xor.txt deleted file mode 100644 index 7c6cb7fcecd..00000000000 --- a/Documentation/devicetree/bindings/dma/mv-xor.txt +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | * Marvell XOR engines | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "marvell,orion-xor" | ||
5 | - reg: Should contain registers location and length (two sets) | ||
6 | the first set is the low registers, the second set the high | ||
7 | registers for the XOR engine. | ||
8 | - clocks: pointer to the reference clock | ||
9 | |||
10 | The DT node must also contains sub-nodes for each XOR channel that the | ||
11 | XOR engine has. Those sub-nodes have the following required | ||
12 | properties: | ||
13 | - interrupts: interrupt of the XOR channel | ||
14 | |||
15 | And the following optional properties: | ||
16 | - dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations | ||
17 | - dmacap,memset to indicate that the XOR channel is capable of memset operations | ||
18 | - dmacap,xor to indicate that the XOR channel is capable of xor operations | ||
19 | |||
20 | Example: | ||
21 | |||
22 | xor@d0060900 { | ||
23 | compatible = "marvell,orion-xor"; | ||
24 | reg = <0xd0060900 0x100 | ||
25 | 0xd0060b00 0x100>; | ||
26 | clocks = <&coreclk 0>; | ||
27 | status = "okay"; | ||
28 | |||
29 | xor00 { | ||
30 | interrupts = <51>; | ||
31 | dmacap,memcpy; | ||
32 | dmacap,xor; | ||
33 | }; | ||
34 | xor01 { | ||
35 | interrupts = <52>; | ||
36 | dmacap,memcpy; | ||
37 | dmacap,xor; | ||
38 | dmacap,memset; | ||
39 | }; | ||
40 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt deleted file mode 100644 index c0d85dbcada..00000000000 --- a/Documentation/devicetree/bindings/dma/snps-dma.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * Synopsys Designware DMA Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "snps,dma-spear1340" | ||
5 | - reg: Address range of the DMAC registers | ||
6 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
7 | that services interrupts for this device | ||
8 | - interrupt: Should contain the DMAC interrupt number | ||
9 | |||
10 | Example: | ||
11 | |||
12 | dma@fc000000 { | ||
13 | compatible = "snps,dma-spear1340"; | ||
14 | reg = <0xfc000000 0x1000>; | ||
15 | interrupt-parent = <&vic1>; | ||
16 | interrupts = <12>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt deleted file mode 100644 index 90fa7da525b..00000000000 --- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | * NVIDIA Tegra APB DMA controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "nvidia,<chip>-apbdma" | ||
5 | - reg: Should contain DMA registers location and length. This shuld include | ||
6 | all of the per-channel registers. | ||
7 | - interrupts: Should contain all of the per-channel DMA interrupts. | ||
8 | |||
9 | Examples: | ||
10 | |||
11 | apbdma: dma@6000a000 { | ||
12 | compatible = "nvidia,tegra20-apbdma"; | ||
13 | reg = <0x6000a000 0x1200>; | ||
14 | interrupts = < 0 136 0x04 | ||
15 | 0 137 0x04 | ||
16 | 0 138 0x04 | ||
17 | 0 139 0x04 | ||
18 | 0 140 0x04 | ||
19 | 0 141 0x04 | ||
20 | 0 142 0x04 | ||
21 | 0 143 0x04 | ||
22 | 0 144 0x04 | ||
23 | 0 145 0x04 | ||
24 | 0 146 0x04 | ||
25 | 0 147 0x04 | ||
26 | 0 148 0x04 | ||
27 | 0 149 0x04 | ||
28 | 0 150 0x04 | ||
29 | 0 151 0x04 >; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmi.txt b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt deleted file mode 100644 index 589edee3739..00000000000 --- a/Documentation/devicetree/bindings/drm/exynos/hdmi.txt +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | Device-Tree bindings for drm hdmi driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: value should be "samsung,exynos5-hdmi". | ||
5 | - reg: physical base address of the hdmi and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: interrupt number to the cpu. | ||
8 | - hpd-gpio: following information about the hotplug gpio pin. | ||
9 | a) phandle of the gpio controller node. | ||
10 | b) pin number within the gpio controller. | ||
11 | c) pin function mode. | ||
12 | d) optional flags and pull up/down. | ||
13 | e) drive strength. | ||
14 | |||
15 | Example: | ||
16 | |||
17 | hdmi { | ||
18 | compatible = "samsung,exynos5-hdmi"; | ||
19 | reg = <0x14530000 0x100000>; | ||
20 | interrupts = <0 95 0>; | ||
21 | hpd-gpio = <&gpx3 7 0xf 1 3>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt deleted file mode 100644 index fa166d94580..00000000000 --- a/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | Device-Tree bindings for hdmiddc driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: value should be "samsung,exynos5-hdmiddc". | ||
5 | - reg: I2C address of the hdmiddc device. | ||
6 | |||
7 | Example: | ||
8 | |||
9 | hdmiddc { | ||
10 | compatible = "samsung,exynos5-hdmiddc"; | ||
11 | reg = <0x50>; | ||
12 | }; | ||
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt deleted file mode 100644 index 858f4f9b902..00000000000 --- a/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | Device-Tree bindings for hdmiphy driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: value should be "samsung,exynos5-hdmiphy". | ||
5 | - reg: I2C address of the hdmiphy device. | ||
6 | |||
7 | Example: | ||
8 | |||
9 | hdmiphy { | ||
10 | compatible = "samsung,exynos5-hdmiphy"; | ||
11 | reg = <0x38>; | ||
12 | }; | ||
diff --git a/Documentation/devicetree/bindings/drm/exynos/mixer.txt b/Documentation/devicetree/bindings/drm/exynos/mixer.txt deleted file mode 100644 index 9b2ea034356..00000000000 --- a/Documentation/devicetree/bindings/drm/exynos/mixer.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | Device-Tree bindings for mixer driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: value should be "samsung,exynos5-mixer". | ||
5 | - reg: physical base address of the mixer and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: interrupt number to the cpu. | ||
8 | |||
9 | Example: | ||
10 | |||
11 | mixer { | ||
12 | compatible = "samsung,exynos5-mixer"; | ||
13 | reg = <0x14450000 0x10000>; | ||
14 | interrupts = <0 94 0>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/fb/mxsfb.txt b/Documentation/devicetree/bindings/fb/mxsfb.txt deleted file mode 100644 index b41e5e52a67..00000000000 --- a/Documentation/devicetree/bindings/fb/mxsfb.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | * Freescale MXS LCD Interface (LCDIF) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,<chip>-lcdif". Supported chips include | ||
5 | imx23 and imx28. | ||
6 | - reg: Address and length of the register set for lcdif | ||
7 | - interrupts: Should contain lcdif interrupts | ||
8 | |||
9 | Optional properties: | ||
10 | - panel-enable-gpios : Should specify the gpio for panel enable | ||
11 | |||
12 | Examples: | ||
13 | |||
14 | lcdif@80030000 { | ||
15 | compatible = "fsl,imx28-lcdif"; | ||
16 | reg = <0x80030000 2000>; | ||
17 | interrupts = <38 86>; | ||
18 | panel-enable-gpios = <&gpio3 30 0>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt deleted file mode 100644 index 9d6dcd3fe7f..00000000000 --- a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | * General Purpose Input Output (GPIO) bus. | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-3860-gpio" | ||
5 | |||
6 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
7 | |||
8 | - reg: The base address of the GPIO unit's register bank. | ||
9 | |||
10 | - gpio-controller: This is a GPIO controller. | ||
11 | |||
12 | - #gpio-cells: Must be <2>. The first cell is the GPIO pin. | ||
13 | |||
14 | - interrupt-controller: The GPIO controller is also an interrupt | ||
15 | controller, many of its pins may be configured as an interrupt | ||
16 | source. | ||
17 | |||
18 | - #interrupt-cells: Must be <2>. The first cell is the GPIO pin | ||
19 | connected to the interrupt source. The second cell is the interrupt | ||
20 | triggering protocol and may have one of four values: | ||
21 | 1 - edge triggered on the rising edge. | ||
22 | 2 - edge triggered on the falling edge | ||
23 | 4 - level triggered active high. | ||
24 | 8 - level triggered active low. | ||
25 | |||
26 | - interrupts: Interrupt routing for each pin. | ||
27 | |||
28 | Example: | ||
29 | |||
30 | gpio-controller@1070000000800 { | ||
31 | #gpio-cells = <2>; | ||
32 | compatible = "cavium,octeon-3860-gpio"; | ||
33 | reg = <0x10700 0x00000800 0x0 0x100>; | ||
34 | gpio-controller; | ||
35 | /* Interrupts are specified by two parts: | ||
36 | * 1) GPIO pin number (0..15) | ||
37 | * 2) Triggering (1 - edge rising | ||
38 | * 2 - edge falling | ||
39 | * 4 - level active high | ||
40 | * 8 - level active low) | ||
41 | */ | ||
42 | interrupt-controller; | ||
43 | #interrupt-cells = <2>; | ||
44 | /* The GPIO pin connect to 16 consecutive CUI bits */ | ||
45 | interrupts = <0 16>, <0 17>, <0 18>, <0 19>, | ||
46 | <0 20>, <0 21>, <0 22>, <0 23>, | ||
47 | <0 24>, <0 25>, <0 26>, <0 27>, | ||
48 | <0 28>, <0 29>, <0 30>, <0 31>; | ||
49 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt index dbd22e0df21..4363ae4b3c1 100644 --- a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt | |||
@@ -8,25 +8,15 @@ Required properties: | |||
8 | by low 16 pins and the second one is for high 16 pins. | 8 | by low 16 pins and the second one is for high 16 pins. |
9 | - gpio-controller : Marks the device node as a gpio controller. | 9 | - gpio-controller : Marks the device node as a gpio controller. |
10 | - #gpio-cells : Should be two. The first cell is the pin number and | 10 | - #gpio-cells : Should be two. The first cell is the pin number and |
11 | the second cell is used to specify the gpio polarity: | 11 | the second cell is used to specify optional parameters (currently |
12 | 0 = active high | 12 | unused). |
13 | 1 = active low | ||
14 | - interrupt-controller: Marks the device node as an interrupt controller. | ||
15 | - #interrupt-cells : Should be 2. The first cell is the GPIO number. | ||
16 | The second cell bits[3:0] is used to specify trigger type and level flags: | ||
17 | 1 = low-to-high edge triggered. | ||
18 | 2 = high-to-low edge triggered. | ||
19 | 4 = active high level-sensitive. | ||
20 | 8 = active low level-sensitive. | ||
21 | 13 | ||
22 | Example: | 14 | Example: |
23 | 15 | ||
24 | gpio0: gpio@73f84000 { | 16 | gpio0: gpio@73f84000 { |
25 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; | 17 | compatible = "fsl,imx51-gpio", "fsl,imx31-gpio"; |
26 | reg = <0x73f84000 0x4000>; | 18 | reg = <0x73f84000 0x4000>; |
27 | interrupts = <50 51>; | 19 | interrupts = <50 51>; |
28 | gpio-controller; | 20 | gpio-controller; |
29 | #gpio-cells = <2>; | 21 | #gpio-cells = <2>; |
30 | interrupt-controller; | ||
31 | #interrupt-cells = <2>; | ||
32 | }; | 22 | }; |
diff --git a/Documentation/devicetree/bindings/gpio/gpio-74x164.txt b/Documentation/devicetree/bindings/gpio/gpio-74x164.txt deleted file mode 100644 index cc2608021f2..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-74x164.txt +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | * Generic 8-bits shift register GPIO driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "fairchild,74hc595" | ||
5 | - reg : chip select number | ||
6 | - gpio-controller : Marks the device node as a gpio controller. | ||
7 | - #gpio-cells : Should be two. The first cell is the pin number and | ||
8 | the second cell is used to specify the gpio polarity: | ||
9 | 0 = active high | ||
10 | 1 = active low | ||
11 | - registers-number: Number of daisy-chained shift registers | ||
12 | |||
13 | Example: | ||
14 | |||
15 | gpio5: gpio5@0 { | ||
16 | compatible = "fairchild,74hc595"; | ||
17 | reg = <0>; | ||
18 | gpio-controller; | ||
19 | #gpio-cells = <2>; | ||
20 | registers-number = <4>; | ||
21 | spi-max-frequency = <100000>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-adnp.txt b/Documentation/devicetree/bindings/gpio/gpio-adnp.txt deleted file mode 100644 index af66b272483..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-adnp.txt +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | Avionic Design N-bit GPIO expander bindings | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "ad,gpio-adnp" | ||
5 | - reg: The I2C slave address for this device. | ||
6 | - interrupt-parent: phandle of the parent interrupt controller. | ||
7 | - interrupts: Interrupt specifier for the controllers interrupt. | ||
8 | - #gpio-cells: Should be 2. The first cell is the GPIO number and the | ||
9 | second cell is used to specify optional parameters: | ||
10 | - bit 0: polarity (0: normal, 1: inverted) | ||
11 | - gpio-controller: Marks the device as a GPIO controller | ||
12 | - nr-gpios: The number of pins supported by the controller. | ||
13 | |||
14 | The GPIO expander can optionally be used as an interrupt controller, in | ||
15 | which case it uses the default two cell specifier as described in | ||
16 | Documentation/devicetree/bindings/interrupt-controller/interrupts.txt. | ||
17 | |||
18 | Example: | ||
19 | |||
20 | gpioext: gpio-controller@41 { | ||
21 | compatible = "ad,gpio-adnp"; | ||
22 | reg = <0x41>; | ||
23 | |||
24 | interrupt-parent = <&gpio>; | ||
25 | interrupts = <160 1>; | ||
26 | |||
27 | gpio-controller; | ||
28 | #gpio-cells = <2>; | ||
29 | |||
30 | interrupt-controller; | ||
31 | #interrupt-cells = <2>; | ||
32 | |||
33 | nr-gpios = <64>; | ||
34 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-fan.txt b/Documentation/devicetree/bindings/gpio/gpio-fan.txt deleted file mode 100644 index 2dd457a3469..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-fan.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | Bindings for fan connected to GPIO lines | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "gpio-fan" | ||
5 | - gpios: Specifies the pins that map to bits in the control value, | ||
6 | ordered MSB-->LSB. | ||
7 | - gpio-fan,speed-map: A mapping of possible fan RPM speeds and the | ||
8 | control value that should be set to achieve them. This array | ||
9 | must have the RPM values in ascending order. | ||
10 | |||
11 | Optional properties: | ||
12 | - alarm-gpios: This pin going active indicates something is wrong with | ||
13 | the fan, and a udev event will be fired. | ||
14 | |||
15 | Examples: | ||
16 | |||
17 | gpio_fan { | ||
18 | compatible = "gpio-fan"; | ||
19 | gpios = <&gpio1 14 1 | ||
20 | &gpio1 13 1>; | ||
21 | gpio-fan,speed-map = <0 0 | ||
22 | 3000 1 | ||
23 | 6000 2>; | ||
24 | alarm-gpios = <&gpio1 15 1>; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt b/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt deleted file mode 100644 index f93d51478d5..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | Lantiq SoC External Bus memory mapped GPIO controller | ||
2 | |||
3 | By attaching hardware latches to the EBU it is possible to create output | ||
4 | only gpios. This driver configures a special memory address, which when | ||
5 | written to outputs 16 bit to the latches. | ||
6 | |||
7 | The node describing the memory mapped GPIOs needs to be a child of the node | ||
8 | describing the "lantiq,localbus". | ||
9 | |||
10 | Required properties: | ||
11 | - compatible : Should be "lantiq,gpio-mm-lantiq" | ||
12 | - reg : Address and length of the register set for the device | ||
13 | - #gpio-cells : Should be two. The first cell is the pin number and | ||
14 | the second cell is used to specify optional parameters (currently | ||
15 | unused). | ||
16 | - gpio-controller : Marks the device node as a gpio controller. | ||
17 | |||
18 | Optional properties: | ||
19 | - lantiq,shadow : The default value that we shall assume as already set on the | ||
20 | shift register cascade. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | localbus@0 { | ||
25 | #address-cells = <2>; | ||
26 | #size-cells = <1>; | ||
27 | ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ | ||
28 | 1 0 0x4000000 0x4000010>; /* addsel1 */ | ||
29 | compatible = "lantiq,localbus", "simple-bus"; | ||
30 | |||
31 | gpio_mm0: gpio@4000000 { | ||
32 | compatible = "lantiq,gpio-mm"; | ||
33 | reg = <1 0x0 0x10>; | ||
34 | gpio-controller; | ||
35 | #gpio-cells = <2>; | ||
36 | lantiq,shadow = <0x77f> | ||
37 | }; | ||
38 | } | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt deleted file mode 100644 index a6f3bec1da7..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +++ /dev/null | |||
@@ -1,53 +0,0 @@ | |||
1 | * Marvell EBU GPIO controller | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio" | ||
6 | or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for | ||
7 | Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada | ||
8 | 370. "marvell,mv78200-gpio" should be used for the Discovery | ||
9 | MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP | ||
10 | SoCs (MV78230, MV78260, MV78460). | ||
11 | |||
12 | - reg: Address and length of the register set for the device. Only one | ||
13 | entry is expected, except for the "marvell,armadaxp-gpio" variant | ||
14 | for which two entries are expected: one for the general registers, | ||
15 | one for the per-cpu registers. | ||
16 | |||
17 | - interrupts: The list of interrupts that are used for all the pins | ||
18 | managed by this GPIO bank. There can be more than one interrupt | ||
19 | (example: 1 interrupt per 8 pins on Armada XP, which means 4 | ||
20 | interrupts per bank of 32 GPIOs). | ||
21 | |||
22 | - interrupt-controller: identifies the node as an interrupt controller | ||
23 | |||
24 | - #interrupt-cells: specifies the number of cells needed to encode an | ||
25 | interrupt source. Should be two. | ||
26 | The first cell is the GPIO number. | ||
27 | The second cell is used to specify flags: | ||
28 | bits[3:0] trigger type and level flags: | ||
29 | 1 = low-to-high edge triggered. | ||
30 | 2 = high-to-low edge triggered. | ||
31 | 4 = active high level-sensitive. | ||
32 | 8 = active low level-sensitive. | ||
33 | |||
34 | - gpio-controller: marks the device node as a gpio controller | ||
35 | |||
36 | - ngpios: number of GPIOs this controller has | ||
37 | |||
38 | - #gpio-cells: Should be two. The first cell is the pin number. The | ||
39 | second cell is reserved for flags, unused at the moment. | ||
40 | |||
41 | Example: | ||
42 | |||
43 | gpio0: gpio@d0018100 { | ||
44 | compatible = "marvell,armadaxp-gpio"; | ||
45 | reg = <0xd0018100 0x40>, | ||
46 | <0xd0018800 0x30>; | ||
47 | ngpios = <32>; | ||
48 | gpio-controller; | ||
49 | #gpio-cells = <2>; | ||
50 | interrupt-controller; | ||
51 | #interrupt-cells = <2>; | ||
52 | interrupts = <16>, <17>, <18>, <19>; | ||
53 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt b/Documentation/devicetree/bindings/gpio/gpio-mxs.txt deleted file mode 100644 index 1e677a47b83..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt +++ /dev/null | |||
@@ -1,88 +0,0 @@ | |||
1 | * Freescale MXS GPIO controller | ||
2 | |||
3 | The Freescale MXS GPIO controller is part of MXS PIN controller. The | ||
4 | GPIOs are organized in port/bank. Each port consists of 32 GPIOs. | ||
5 | |||
6 | As the GPIO controller is embedded in the PIN controller and all the | ||
7 | GPIO ports share the same IO space with PIN controller, the GPIO node | ||
8 | will be represented as sub-nodes of MXS pinctrl node. | ||
9 | |||
10 | Required properties for GPIO node: | ||
11 | - compatible : Should be "fsl,<soc>-gpio". The supported SoCs include | ||
12 | imx23 and imx28. | ||
13 | - interrupts : Should be the port interrupt shared by all 32 pins. | ||
14 | - gpio-controller : Marks the device node as a gpio controller. | ||
15 | - #gpio-cells : Should be two. The first cell is the pin number and | ||
16 | the second cell is used to specify the gpio polarity: | ||
17 | 0 = active high | ||
18 | 1 = active low | ||
19 | - interrupt-controller: Marks the device node as an interrupt controller. | ||
20 | - #interrupt-cells : Should be 2. The first cell is the GPIO number. | ||
21 | The second cell bits[3:0] is used to specify trigger type and level flags: | ||
22 | 1 = low-to-high edge triggered. | ||
23 | 2 = high-to-low edge triggered. | ||
24 | 4 = active high level-sensitive. | ||
25 | 8 = active low level-sensitive. | ||
26 | |||
27 | Note: Each GPIO port should have an alias correctly numbered in "aliases" | ||
28 | node. | ||
29 | |||
30 | Examples: | ||
31 | |||
32 | aliases { | ||
33 | gpio0 = &gpio0; | ||
34 | gpio1 = &gpio1; | ||
35 | gpio2 = &gpio2; | ||
36 | gpio3 = &gpio3; | ||
37 | gpio4 = &gpio4; | ||
38 | }; | ||
39 | |||
40 | pinctrl@80018000 { | ||
41 | compatible = "fsl,imx28-pinctrl", "simple-bus"; | ||
42 | reg = <0x80018000 2000>; | ||
43 | |||
44 | gpio0: gpio@0 { | ||
45 | compatible = "fsl,imx28-gpio"; | ||
46 | interrupts = <127>; | ||
47 | gpio-controller; | ||
48 | #gpio-cells = <2>; | ||
49 | interrupt-controller; | ||
50 | #interrupt-cells = <2>; | ||
51 | }; | ||
52 | |||
53 | gpio1: gpio@1 { | ||
54 | compatible = "fsl,imx28-gpio"; | ||
55 | interrupts = <126>; | ||
56 | gpio-controller; | ||
57 | #gpio-cells = <2>; | ||
58 | interrupt-controller; | ||
59 | #interrupt-cells = <2>; | ||
60 | }; | ||
61 | |||
62 | gpio2: gpio@2 { | ||
63 | compatible = "fsl,imx28-gpio"; | ||
64 | interrupts = <125>; | ||
65 | gpio-controller; | ||
66 | #gpio-cells = <2>; | ||
67 | interrupt-controller; | ||
68 | #interrupt-cells = <2>; | ||
69 | }; | ||
70 | |||
71 | gpio3: gpio@3 { | ||
72 | compatible = "fsl,imx28-gpio"; | ||
73 | interrupts = <124>; | ||
74 | gpio-controller; | ||
75 | #gpio-cells = <2>; | ||
76 | interrupt-controller; | ||
77 | #interrupt-cells = <2>; | ||
78 | }; | ||
79 | |||
80 | gpio4: gpio@4 { | ||
81 | compatible = "fsl,imx28-gpio"; | ||
82 | interrupts = <123>; | ||
83 | gpio-controller; | ||
84 | #gpio-cells = <2>; | ||
85 | interrupt-controller; | ||
86 | #interrupt-cells = <2>; | ||
87 | }; | ||
88 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-nmk.txt b/Documentation/devicetree/bindings/gpio/gpio-nmk.txt deleted file mode 100644 index 8315ac7780e..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-nmk.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | Nomadik GPIO controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "st,nomadik-gpio". | ||
5 | - reg : Physical base address and length of the controller's registers. | ||
6 | - interrupts : The interrupt outputs from the controller. | ||
7 | - #gpio-cells : Should be two: | ||
8 | The first cell is the pin number. | ||
9 | The second cell is used to specify optional parameters: | ||
10 | - bits[3:0] trigger type and level flags: | ||
11 | 1 = low-to-high edge triggered. | ||
12 | 2 = high-to-low edge triggered. | ||
13 | 4 = active high level-sensitive. | ||
14 | 8 = active low level-sensitive. | ||
15 | - gpio-controller : Marks the device node as a GPIO controller. | ||
16 | - interrupt-controller : Marks the device node as an interrupt controller. | ||
17 | - gpio-bank : Specifies which bank a controller owns. | ||
18 | - st,supports-sleepmode : Specifies whether controller can sleep or not | ||
19 | |||
20 | Example: | ||
21 | |||
22 | gpio1: gpio@8012e080 { | ||
23 | compatible = "st,nomadik-gpio"; | ||
24 | reg = <0x8012e080 0x80>; | ||
25 | interrupts = <0 120 0x4>; | ||
26 | #gpio-cells = <2>; | ||
27 | gpio-controller; | ||
28 | interrupt-controller; | ||
29 | st,supports-sleepmode; | ||
30 | gpio-bank = <1>; | ||
31 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-omap.txt b/Documentation/devicetree/bindings/gpio/gpio-omap.txt deleted file mode 100644 index bff51a2fee1..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-omap.txt +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | OMAP GPIO controller bindings | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: | ||
5 | - "ti,omap2-gpio" for OMAP2 controllers | ||
6 | - "ti,omap3-gpio" for OMAP3 controllers | ||
7 | - "ti,omap4-gpio" for OMAP4 controllers | ||
8 | - #gpio-cells : Should be two. | ||
9 | - first cell is the pin number | ||
10 | - second cell is used to specify optional parameters (unused) | ||
11 | - gpio-controller : Marks the device node as a GPIO controller. | ||
12 | - #interrupt-cells : Should be 2. | ||
13 | - interrupt-controller: Mark the device node as an interrupt controller | ||
14 | The first cell is the GPIO number. | ||
15 | The second cell is used to specify flags: | ||
16 | bits[3:0] trigger type and level flags: | ||
17 | 1 = low-to-high edge triggered. | ||
18 | 2 = high-to-low edge triggered. | ||
19 | 4 = active high level-sensitive. | ||
20 | 8 = active low level-sensitive. | ||
21 | |||
22 | OMAP specific properties: | ||
23 | - ti,hwmods: Name of the hwmod associated to the GPIO: | ||
24 | "gpio<X>", <X> being the 1-based instance number from the HW spec | ||
25 | |||
26 | |||
27 | Example: | ||
28 | |||
29 | gpio4: gpio4 { | ||
30 | compatible = "ti,omap4-gpio"; | ||
31 | ti,hwmods = "gpio4"; | ||
32 | #gpio-cells = <2>; | ||
33 | gpio-controller; | ||
34 | #interrupt-cells = <2>; | ||
35 | interrupt-controller; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt deleted file mode 100644 index d4eab9227ea..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | Driver a GPIO line that can be used to turn the power off. | ||
2 | |||
3 | The driver supports both level triggered and edge triggered power off. | ||
4 | At driver load time, the driver will request the given gpio line and | ||
5 | install a pm_power_off handler. If the optional properties 'input' is | ||
6 | not found, the GPIO line will be driven in the inactive | ||
7 | state. Otherwise its configured as an input. | ||
8 | |||
9 | When the pm_power_off is called, the gpio is configured as an output, | ||
10 | and drive active, so triggering a level triggered power off | ||
11 | condition. This will also cause an inactive->active edge condition, so | ||
12 | triggering positive edge triggered power off. After a delay of 100ms, | ||
13 | the GPIO is set to inactive, thus causing an active->inactive edge, | ||
14 | triggering negative edge triggered power off. After another 100ms | ||
15 | delay the GPIO is driver active again. If the power is still on and | ||
16 | the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted. | ||
17 | |||
18 | Required properties: | ||
19 | - compatible : should be "gpio-poweroff". | ||
20 | - gpios : The GPIO to set high/low, see "gpios property" in | ||
21 | Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be | ||
22 | low to power down the board set it to "Active Low", otherwise set | ||
23 | gpio to "Active High". | ||
24 | |||
25 | Optional properties: | ||
26 | - input : Initially configure the GPIO line as an input. Only reconfigure | ||
27 | it to an output when the pm_power_off function is called. If this optional | ||
28 | property is not specified, the GPIO is initialized as an output in its | ||
29 | inactive state. | ||
30 | |||
31 | Examples: | ||
32 | |||
33 | gpio-poweroff { | ||
34 | compatible = "gpio-poweroff"; | ||
35 | gpios = <&gpio 4 0>; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt deleted file mode 100644 index f1e5dfecf55..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt +++ /dev/null | |||
@@ -1,84 +0,0 @@ | |||
1 | Samsung Exynos4 GPIO Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Compatible property value should be "samsung,exynos4-gpio>". | ||
5 | |||
6 | - reg: Physical base address of the controller and length of memory mapped | ||
7 | region. | ||
8 | |||
9 | - #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes | ||
10 | should be the following with values derived from the SoC user manual. | ||
11 | <[phandle of the gpio controller node] | ||
12 | [pin number within the gpio controller] | ||
13 | [mux function] | ||
14 | [flags and pull up/down] | ||
15 | [drive strength]> | ||
16 | |||
17 | Values for gpio specifier: | ||
18 | - Pin number: is a value between 0 to 7. | ||
19 | - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled. | ||
20 | 1 - Pull Down Enabled. | ||
21 | 3 - Pull Up Enabled. | ||
22 | Bit 16 (0x00010000) - Input is active low. | ||
23 | - Drive Strength: 0 - 1x, | ||
24 | 1 - 3x, | ||
25 | 2 - 2x, | ||
26 | 3 - 4x | ||
27 | |||
28 | - gpio-controller: Specifies that the node is a gpio controller. | ||
29 | - #address-cells: should be 1. | ||
30 | - #size-cells: should be 1. | ||
31 | |||
32 | Example: | ||
33 | |||
34 | gpa0: gpio-controller@11400000 { | ||
35 | #address-cells = <1>; | ||
36 | #size-cells = <1>; | ||
37 | compatible = "samsung,exynos4-gpio"; | ||
38 | reg = <0x11400000 0x20>; | ||
39 | #gpio-cells = <4>; | ||
40 | gpio-controller; | ||
41 | }; | ||
42 | |||
43 | |||
44 | Samsung S3C24XX GPIO Controller | ||
45 | |||
46 | Required properties: | ||
47 | - compatible: Compatible property value should be "samsung,s3c24xx-gpio". | ||
48 | |||
49 | - reg: Physical base address of the controller and length of memory mapped | ||
50 | region. | ||
51 | |||
52 | - #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes | ||
53 | should be the following with values derived from the SoC user manual. | ||
54 | <[phandle of the gpio controller node] | ||
55 | [pin number within the gpio controller] | ||
56 | [mux function] | ||
57 | [flags and pull up/down] | ||
58 | |||
59 | Values for gpio specifier: | ||
60 | - Pin number: depending on the controller a number from 0 up to 15. | ||
61 | - Mux function: Depending on the SoC and the gpio bank the gpio can be set | ||
62 | as input, output or a special function | ||
63 | - Flags and Pull Up/Down: the values to use differ for the individual SoCs | ||
64 | example S3C2416/S3C2450: | ||
65 | 0 - Pull Up/Down Disabled. | ||
66 | 1 - Pull Down Enabled. | ||
67 | 2 - Pull Up Enabled. | ||
68 | Bit 16 (0x00010000) - Input is active low. | ||
69 | Consult the user manual for the correct values of Mux and Pull Up/Down. | ||
70 | |||
71 | - gpio-controller: Specifies that the node is a gpio controller. | ||
72 | - #address-cells: should be 1. | ||
73 | - #size-cells: should be 1. | ||
74 | |||
75 | Example: | ||
76 | |||
77 | gpa: gpio-controller@56000000 { | ||
78 | #address-cells = <1>; | ||
79 | #size-cells = <1>; | ||
80 | compatible = "samsung,s3c24xx-gpio"; | ||
81 | reg = <0x56000000 0x10>; | ||
82 | #gpio-cells = <3>; | ||
83 | gpio-controller; | ||
84 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt b/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt deleted file mode 100644 index a0e4cf88521..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | STMPE gpio | ||
2 | ---------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible: "st,stmpe-gpio" | ||
6 | |||
7 | Optional properties: | ||
8 | - st,norequest-mask: bitmask specifying which GPIOs should _not_ be requestable | ||
9 | due to different usage (e.g. touch, keypad) | ||
10 | |||
11 | Node name must be stmpe_gpio and should be child node of stmpe node to which it | ||
12 | belongs. | ||
13 | |||
14 | Example: | ||
15 | stmpe_gpio { | ||
16 | compatible = "st,stmpe-gpio"; | ||
17 | st,norequest-mask = <0x20>; //gpio 5 can't be used | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt deleted file mode 100644 index 854de130a97..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt +++ /dev/null | |||
@@ -1,42 +0,0 @@ | |||
1 | Lantiq SoC Serial To Parallel (STP) GPIO controller | ||
2 | |||
3 | The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a | ||
4 | peripheral controller used to drive external shift register cascades. At most | ||
5 | 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem | ||
6 | to drive the 2 LSBs of the cascade automatically. | ||
7 | |||
8 | |||
9 | Required properties: | ||
10 | - compatible : Should be "lantiq,gpio-stp-xway" | ||
11 | - reg : Address and length of the register set for the device | ||
12 | - #gpio-cells : Should be two. The first cell is the pin number and | ||
13 | the second cell is used to specify optional parameters (currently | ||
14 | unused). | ||
15 | - gpio-controller : Marks the device node as a gpio controller. | ||
16 | |||
17 | Optional properties: | ||
18 | - lantiq,shadow : The default value that we shall assume as already set on the | ||
19 | shift register cascade. | ||
20 | - lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled | ||
21 | in the shift register cascade. | ||
22 | - lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit | ||
23 | property can enable this feature. | ||
24 | - lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade. | ||
25 | - lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade. | ||
26 | - lantiq,rising : use rising instead of falling edge for the shift register | ||
27 | |||
28 | Example: | ||
29 | |||
30 | gpio1: stp@E100BB0 { | ||
31 | compatible = "lantiq,gpio-stp-xway"; | ||
32 | reg = <0xE100BB0 0x40>; | ||
33 | #gpio-cells = <2>; | ||
34 | gpio-controller; | ||
35 | |||
36 | lantiq,shadow = <0xffff>; | ||
37 | lantiq,groups = <0x7>; | ||
38 | lantiq,dsl = <0x3>; | ||
39 | lantiq,phy1 = <0x7>; | ||
40 | lantiq,phy2 = <0x7>; | ||
41 | /* lantiq,rising; */ | ||
42 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt deleted file mode 100644 index 66788fda1db..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | twl4030 GPIO controller bindings | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: | ||
5 | - "ti,twl4030-gpio" for twl4030 GPIO controller | ||
6 | - #gpio-cells : Should be two. | ||
7 | - first cell is the pin number | ||
8 | - second cell is used to specify optional parameters (unused) | ||
9 | - gpio-controller : Marks the device node as a GPIO controller. | ||
10 | - #interrupt-cells : Should be 2. | ||
11 | - interrupt-controller: Mark the device node as an interrupt controller | ||
12 | The first cell is the GPIO number. | ||
13 | The second cell is not used. | ||
14 | - ti,use-leds : Enables LEDA and LEDB outputs if set | ||
15 | - ti,debounce : if n-th bit is set, debounces GPIO-n | ||
16 | - ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1) | ||
17 | - ti,pullups : if n-th bit is set, set a pullup on GPIO-n | ||
18 | - ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n | ||
19 | |||
20 | Example: | ||
21 | |||
22 | twl_gpio: gpio { | ||
23 | compatible = "ti,twl4030-gpio"; | ||
24 | #gpio-cells = <2>; | ||
25 | gpio-controller; | ||
26 | #interrupt-cells = <2>; | ||
27 | interrupt-controller; | ||
28 | ti,use-leds; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt deleted file mode 100644 index f4dc5233167..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500 GPIO Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "via,vt8500-gpio", "wm,wm8505-gpio" | ||
6 | or "wm,wm8650-gpio" depending on your SoC | ||
7 | - reg : Should contain 1 register range (address and length) | ||
8 | - #gpio-cells : should be <3>. | ||
9 | 1) bank | ||
10 | 2) pin number | ||
11 | 3) flags - should be 0 | ||
12 | |||
13 | Example: | ||
14 | |||
15 | gpio: gpio-controller@d8110000 { | ||
16 | compatible = "via,vt8500-gpio"; | ||
17 | gpio-controller; | ||
18 | reg = <0xd8110000 0x10000>; | ||
19 | #gpio-cells = <3>; | ||
20 | }; | ||
21 | |||
22 | vibrate { | ||
23 | gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */ | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index a33628759d3..4e16ba4feab 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt | |||
@@ -75,40 +75,4 @@ Example of two SOC GPIO banks defined as gpio-controller nodes: | |||
75 | gpio-controller; | 75 | gpio-controller; |
76 | }; | 76 | }; |
77 | 77 | ||
78 | 2.1) gpio-controller and pinctrl subsystem | ||
79 | ------------------------------------------ | ||
80 | 78 | ||
81 | gpio-controller on a SOC might be tightly coupled with the pinctrl | ||
82 | subsystem, in the sense that the pins can be used by other functions | ||
83 | together with optional gpio feature. | ||
84 | |||
85 | While the pin allocation is totally managed by the pin ctrl subsystem, | ||
86 | gpio (under gpiolib) is still maintained by gpio drivers. It may happen | ||
87 | that different pin ranges in a SoC is managed by different gpio drivers. | ||
88 | |||
89 | This makes it logical to let gpio drivers announce their pin ranges to | ||
90 | the pin ctrl subsystem and call 'pinctrl_request_gpio' in order to | ||
91 | request the corresponding pin before any gpio usage. | ||
92 | |||
93 | For this, the gpio controller can use a pinctrl phandle and pins to | ||
94 | announce the pinrange to the pin ctrl subsystem. For example, | ||
95 | |||
96 | qe_pio_e: gpio-controller@1460 { | ||
97 | #gpio-cells = <2>; | ||
98 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; | ||
99 | reg = <0x1460 0x18>; | ||
100 | gpio-controller; | ||
101 | gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>; | ||
102 | |||
103 | } | ||
104 | |||
105 | where, | ||
106 | &pinctrl1 and &pinctrl2 is the phandle to the pinctrl DT node. | ||
107 | |||
108 | Next values specify the base pin and number of pins for the range | ||
109 | handled by 'qe_pio_e' gpio. In the given example from base pin 20 to | ||
110 | pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled | ||
111 | by this gpio controller. | ||
112 | |||
113 | The pinctrl node must have "#gpio-range-cells" property to show number of | ||
114 | arguments to pass with phandle from gpio controllers node. | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt deleted file mode 100644 index 85f8c0d084f..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * Atmel GPIO controller (PIO) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5. | ||
5 | - reg: Should contain GPIO controller registers location and length | ||
6 | - interrupts: Should be the port interrupt shared by all the pins. | ||
7 | - #gpio-cells: Should be two. The first cell is the pin number and | ||
8 | the second cell is used to specify optional parameters (currently | ||
9 | unused). | ||
10 | - gpio-controller: Marks the device node as a GPIO controller. | ||
11 | |||
12 | optional properties: | ||
13 | - #gpio-lines: Number of gpio if absent 32. | ||
14 | |||
15 | |||
16 | Example: | ||
17 | pioA: gpio@fffff200 { | ||
18 | compatible = "atmel,at91rm9200-gpio"; | ||
19 | reg = <0xfffff200 0x100>; | ||
20 | interrupts = <2 4>; | ||
21 | #gpio-cells = <2>; | ||
22 | gpio-controller; | ||
23 | #gpio-lines = <19>; | ||
24 | }; | ||
25 | |||
diff --git a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt b/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt deleted file mode 100644 index 49819367a01..00000000000 --- a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt +++ /dev/null | |||
@@ -1,43 +0,0 @@ | |||
1 | NXP LPC32xx SoC GPIO controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "nxp,lpc3220-gpio" | ||
5 | - reg: Physical base address and length of the controller's registers. | ||
6 | - gpio-controller: Marks the device node as a GPIO controller. | ||
7 | - #gpio-cells: Should be 3: | ||
8 | 1) bank: | ||
9 | 0: GPIO P0 | ||
10 | 1: GPIO P1 | ||
11 | 2: GPIO P2 | ||
12 | 3: GPIO P3 | ||
13 | 4: GPI P3 | ||
14 | 5: GPO P3 | ||
15 | 2) pin number | ||
16 | 3) optional parameters: | ||
17 | - bit 0 specifies polarity (0 for normal, 1 for inverted) | ||
18 | - reg: Index of the GPIO group | ||
19 | |||
20 | Example: | ||
21 | |||
22 | gpio: gpio@40028000 { | ||
23 | compatible = "nxp,lpc3220-gpio"; | ||
24 | reg = <0x40028000 0x1000>; | ||
25 | gpio-controller; | ||
26 | #gpio-cells = <3>; /* bank, pin, flags */ | ||
27 | }; | ||
28 | |||
29 | leds { | ||
30 | compatible = "gpio-leds"; | ||
31 | |||
32 | led0 { | ||
33 | gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */ | ||
34 | linux,default-trigger = "heartbeat"; | ||
35 | default-state = "off"; | ||
36 | }; | ||
37 | |||
38 | led1 { | ||
39 | gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */ | ||
40 | linux,default-trigger = "timer"; | ||
41 | default-state = "off"; | ||
42 | }; | ||
43 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/leds-ns2.txt b/Documentation/devicetree/bindings/gpio/leds-ns2.txt deleted file mode 100644 index aef3aca34d2..00000000000 --- a/Documentation/devicetree/bindings/gpio/leds-ns2.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | Binding for dual-GPIO LED found on Network Space v2 (and parents). | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "lacie,ns2-leds". | ||
5 | |||
6 | Each LED is represented as a sub-node of the ns2-leds device. | ||
7 | |||
8 | Required sub-node properties: | ||
9 | - cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification. | ||
10 | - slow-gpio: Slow LED GPIO. See OF device-tree GPIO specification. | ||
11 | |||
12 | Optional sub-node properties: | ||
13 | - label: Name for this LED. If omitted, the label is taken from the node name. | ||
14 | - linux,default-trigger: Trigger assigned to the LED. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | ns2-leds { | ||
19 | compatible = "lacie,ns2-leds"; | ||
20 | |||
21 | blue-sata { | ||
22 | label = "ns2:blue:sata"; | ||
23 | slow-gpio = <&gpio0 29 0>; | ||
24 | cmd-gpio = <&gpio0 30 0>; | ||
25 | }; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt deleted file mode 100644 index e13787498bc..00000000000 --- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | * Marvell PXA GPIO controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio" | ||
5 | - reg : Address and length of the register set for the device | ||
6 | - interrupts : Should be the port interrupt shared by all gpio pins. | ||
7 | There're three gpio interrupts in arch-pxa, and they're gpio0, | ||
8 | gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp, | ||
9 | gpio_mux. | ||
10 | - interrupt-name : Should be the name of irq resource. Each interrupt | ||
11 | binds its interrupt-name. | ||
12 | - interrupt-controller : Identifies the node as an interrupt controller. | ||
13 | - #interrupt-cells: Specifies the number of cells needed to encode an | ||
14 | interrupt source. | ||
15 | - gpio-controller : Marks the device node as a gpio controller. | ||
16 | - #gpio-cells : Should be one. It is the pin number. | ||
17 | |||
18 | Example: | ||
19 | |||
20 | gpio: gpio@d4019000 { | ||
21 | compatible = "mrvl,mmp-gpio"; | ||
22 | reg = <0xd4019000 0x1000>; | ||
23 | interrupts = <49>; | ||
24 | interrupt-name = "gpio_mux"; | ||
25 | gpio-controller; | ||
26 | #gpio-cells = <1>; | ||
27 | interrupt-controller; | ||
28 | #interrupt-cells = <1>; | ||
29 | }; | ||
30 | |||
31 | * Marvell Orion GPIO Controller | ||
32 | |||
33 | Required properties: | ||
34 | - compatible : Should be "marvell,orion-gpio" | ||
35 | - reg : Address and length of the register set for controller. | ||
36 | - gpio-controller : So we know this is a gpio controller. | ||
37 | - ngpio : How many gpios this controller has. | ||
38 | - interrupts : Up to 4 Interrupts for the controller. | ||
39 | |||
40 | Optional properties: | ||
41 | - mask-offset : For SMP Orions, offset for Nth CPU | ||
42 | |||
43 | Example: | ||
44 | |||
45 | gpio0: gpio@10100 { | ||
46 | compatible = "marvell,orion-gpio"; | ||
47 | #gpio-cells = <2>; | ||
48 | gpio-controller; | ||
49 | reg = <0x10100 0x40>; | ||
50 | ngpio = <32>; | ||
51 | interrupts = <35>, <36>, <37>, <38>; | ||
52 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt b/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt deleted file mode 100644 index 023c9526e5f..00000000000 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | NVIDIA Tegra GPIO controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra<chip>-gpio" | ||
5 | - reg : Physical base address and length of the controller's registers. | ||
6 | - interrupts : The interrupt outputs from the controller. For Tegra20, | ||
7 | there should be 7 interrupts specified, and for Tegra30, there should | ||
8 | be 8 interrupts specified. | ||
9 | - #gpio-cells : Should be two. The first cell is the pin number and the | ||
10 | second cell is used to specify optional parameters: | ||
11 | - bit 0 specifies polarity (0 for normal, 1 for inverted) | ||
12 | - gpio-controller : Marks the device node as a GPIO controller. | ||
13 | - #interrupt-cells : Should be 2. | ||
14 | The first cell is the GPIO number. | ||
15 | The second cell is used to specify flags: | ||
16 | bits[3:0] trigger type and level flags: | ||
17 | 1 = low-to-high edge triggered. | ||
18 | 2 = high-to-low edge triggered. | ||
19 | 4 = active high level-sensitive. | ||
20 | 8 = active low level-sensitive. | ||
21 | Valid combinations are 1, 2, 3, 4, 8. | ||
22 | - interrupt-controller : Marks the device node as an interrupt controller. | ||
23 | |||
24 | Example: | ||
25 | |||
26 | gpio: gpio@6000d000 { | ||
27 | compatible = "nvidia,tegra20-gpio"; | ||
28 | reg = < 0x6000d000 0x1000 >; | ||
29 | interrupts = < 0 32 0x04 | ||
30 | 0 33 0x04 | ||
31 | 0 34 0x04 | ||
32 | 0 35 0x04 | ||
33 | 0 55 0x04 | ||
34 | 0 87 0x04 | ||
35 | 0 89 0x04 >; | ||
36 | #gpio-cells = <2>; | ||
37 | gpio-controller; | ||
38 | #interrupt-cells = <2>; | ||
39 | interrupt-controller; | ||
40 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt deleted file mode 100644 index a2c416bcbcc..00000000000 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt +++ /dev/null | |||
@@ -1,10 +0,0 @@ | |||
1 | ARM PL061 GPIO controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "arm,pl061", "arm,primecell" | ||
5 | - #gpio-cells : Should be two. The first cell is the pin number and the | ||
6 | second cell is used to specify optional parameters: | ||
7 | - bit 0 specifies polarity (0 for normal, 1 for inverted) | ||
8 | - gpio-controller : Marks the device node as a GPIO controller. | ||
9 | - interrupts : Interrupt mapping for GPIO IRQ. | ||
10 | |||
diff --git a/Documentation/devicetree/bindings/gpio/sodaville.txt b/Documentation/devicetree/bindings/gpio/sodaville.txt deleted file mode 100644 index 563eff22b97..00000000000 --- a/Documentation/devicetree/bindings/gpio/sodaville.txt +++ /dev/null | |||
@@ -1,48 +0,0 @@ | |||
1 | GPIO controller on CE4100 / Sodaville SoCs | ||
2 | ========================================== | ||
3 | |||
4 | The bindings for CE4100's GPIO controller match the generic description | ||
5 | which is covered by the gpio.txt file in this folder. | ||
6 | |||
7 | The only additional property is the intel,muxctl property which holds the | ||
8 | value which is written into the MUXCNTL register. | ||
9 | |||
10 | There is no compatible property for now because the driver is probed via | ||
11 | PCI id (vendor 0x8086 device 0x2e67). | ||
12 | |||
13 | The interrupt specifier consists of two cells encoded as follows: | ||
14 | - <1st cell>: The interrupt-number that identifies the interrupt source. | ||
15 | - <2nd cell>: The level-sense information, encoded as follows: | ||
16 | 4 - active high level-sensitive | ||
17 | 8 - active low level-sensitive | ||
18 | |||
19 | Example of the GPIO device and one user: | ||
20 | |||
21 | pcigpio: gpio@b,1 { | ||
22 | /* two cells for GPIO and interrupt */ | ||
23 | #gpio-cells = <2>; | ||
24 | #interrupt-cells = <2>; | ||
25 | compatible = "pci8086,2e67.2", | ||
26 | "pci8086,2e67", | ||
27 | "pciclassff0000", | ||
28 | "pciclassff00"; | ||
29 | |||
30 | reg = <0x15900 0x0 0x0 0x0 0x0>; | ||
31 | /* Interrupt line of the gpio device */ | ||
32 | interrupts = <15 1>; | ||
33 | /* It is an interrupt and GPIO controller itself */ | ||
34 | interrupt-controller; | ||
35 | gpio-controller; | ||
36 | intel,muxctl = <0>; | ||
37 | }; | ||
38 | |||
39 | testuser@20 { | ||
40 | compatible = "example,testuser"; | ||
41 | /* User the 11th GPIO line as an active high triggered | ||
42 | * level interrupt | ||
43 | */ | ||
44 | interrupts = <11 8>; | ||
45 | interrupt-parent = <&pcigpio>; | ||
46 | /* Use this GPIO also with the gpio functions */ | ||
47 | gpios = <&pcigpio 11 0>; | ||
48 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/spear_spics.txt b/Documentation/devicetree/bindings/gpio/spear_spics.txt deleted file mode 100644 index 96c37eb1507..00000000000 --- a/Documentation/devicetree/bindings/gpio/spear_spics.txt +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | === ST Microelectronics SPEAr SPI CS Driver === | ||
2 | |||
3 | SPEAr platform provides a provision to control chipselects of ARM PL022 Prime | ||
4 | Cell spi controller through its system registers, which otherwise remains under | ||
5 | PL022 control. If chipselect remain under PL022 control then they would be | ||
6 | released as soon as transfer is over and TxFIFO becomes empty. This is not | ||
7 | desired by some of the device protocols above spi which expect (multiple) | ||
8 | transfers without releasing their chipselects. | ||
9 | |||
10 | Chipselects can be controlled by software by turning them as GPIOs. SPEAr | ||
11 | provides another interface through system registers through which software can | ||
12 | directly control each PL022 chipselect. Hence, it is natural for SPEAr to export | ||
13 | the control of this interface as gpio. | ||
14 | |||
15 | Required properties: | ||
16 | |||
17 | * compatible: should be defined as "st,spear-spics-gpio" | ||
18 | * reg: mentioning address range of spics controller | ||
19 | * st-spics,peripcfg-reg: peripheral configuration register offset | ||
20 | * st-spics,sw-enable-bit: bit offset to enable sw control | ||
21 | * st-spics,cs-value-bit: bit offset to drive chipselect low or high | ||
22 | * st-spics,cs-enable-mask: chip select number bit mask | ||
23 | * st-spics,cs-enable-shift: chip select number program offset | ||
24 | * gpio-controller: Marks the device node as gpio controller | ||
25 | * #gpio-cells: should be 1 and will mention chip select number | ||
26 | |||
27 | All the above bit offsets are within peripcfg register. | ||
28 | |||
29 | Example: | ||
30 | ------- | ||
31 | spics: spics@e0700000{ | ||
32 | compatible = "st,spear-spics-gpio"; | ||
33 | reg = <0xe0700000 0x1000>; | ||
34 | st-spics,peripcfg-reg = <0x3b0>; | ||
35 | st-spics,sw-enable-bit = <12>; | ||
36 | st-spics,cs-value-bit = <11>; | ||
37 | st-spics,cs-enable-mask = <3>; | ||
38 | st-spics,cs-enable-shift = <8>; | ||
39 | gpio-controller; | ||
40 | #gpio-cells = <2>; | ||
41 | }; | ||
42 | |||
43 | |||
44 | spi0: spi@e0100000 { | ||
45 | status = "okay"; | ||
46 | num-cs = <3>; | ||
47 | cs-gpios = <&gpio1 7 0>, <&spics 0>, | ||
48 | <&spics 1>; | ||
49 | ... | ||
50 | } | ||
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt deleted file mode 100644 index b4fa934ae3a..00000000000 --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt +++ /dev/null | |||
@@ -1,191 +0,0 @@ | |||
1 | NVIDIA Tegra host1x | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "nvidia,tegra<chip>-host1x" | ||
5 | - reg: Physical base address and length of the controller's registers. | ||
6 | - interrupts: The interrupt outputs from the controller. | ||
7 | - #address-cells: The number of cells used to represent physical base addresses | ||
8 | in the host1x address space. Should be 1. | ||
9 | - #size-cells: The number of cells used to represent the size of an address | ||
10 | range in the host1x address space. Should be 1. | ||
11 | - ranges: The mapping of the host1x address space to the CPU address space. | ||
12 | |||
13 | The host1x top-level node defines a number of children, each representing one | ||
14 | of the following host1x client modules: | ||
15 | |||
16 | - mpe: video encoder | ||
17 | |||
18 | Required properties: | ||
19 | - compatible: "nvidia,tegra<chip>-mpe" | ||
20 | - reg: Physical base address and length of the controller's registers. | ||
21 | - interrupts: The interrupt outputs from the controller. | ||
22 | |||
23 | - vi: video input | ||
24 | |||
25 | Required properties: | ||
26 | - compatible: "nvidia,tegra<chip>-vi" | ||
27 | - reg: Physical base address and length of the controller's registers. | ||
28 | - interrupts: The interrupt outputs from the controller. | ||
29 | |||
30 | - epp: encoder pre-processor | ||
31 | |||
32 | Required properties: | ||
33 | - compatible: "nvidia,tegra<chip>-epp" | ||
34 | - reg: Physical base address and length of the controller's registers. | ||
35 | - interrupts: The interrupt outputs from the controller. | ||
36 | |||
37 | - isp: image signal processor | ||
38 | |||
39 | Required properties: | ||
40 | - compatible: "nvidia,tegra<chip>-isp" | ||
41 | - reg: Physical base address and length of the controller's registers. | ||
42 | - interrupts: The interrupt outputs from the controller. | ||
43 | |||
44 | - gr2d: 2D graphics engine | ||
45 | |||
46 | Required properties: | ||
47 | - compatible: "nvidia,tegra<chip>-gr2d" | ||
48 | - reg: Physical base address and length of the controller's registers. | ||
49 | - interrupts: The interrupt outputs from the controller. | ||
50 | |||
51 | - gr3d: 3D graphics engine | ||
52 | |||
53 | Required properties: | ||
54 | - compatible: "nvidia,tegra<chip>-gr3d" | ||
55 | - reg: Physical base address and length of the controller's registers. | ||
56 | |||
57 | - dc: display controller | ||
58 | |||
59 | Required properties: | ||
60 | - compatible: "nvidia,tegra<chip>-dc" | ||
61 | - reg: Physical base address and length of the controller's registers. | ||
62 | - interrupts: The interrupt outputs from the controller. | ||
63 | |||
64 | Each display controller node has a child node, named "rgb", that represents | ||
65 | the RGB output associated with the controller. It can take the following | ||
66 | optional properties: | ||
67 | - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
68 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | ||
69 | - nvidia,edid: supplies a binary EDID blob | ||
70 | |||
71 | - hdmi: High Definition Multimedia Interface | ||
72 | |||
73 | Required properties: | ||
74 | - compatible: "nvidia,tegra<chip>-hdmi" | ||
75 | - reg: Physical base address and length of the controller's registers. | ||
76 | - interrupts: The interrupt outputs from the controller. | ||
77 | - vdd-supply: regulator for supply voltage | ||
78 | - pll-supply: regulator for PLL | ||
79 | |||
80 | Optional properties: | ||
81 | - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
82 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | ||
83 | - nvidia,edid: supplies a binary EDID blob | ||
84 | |||
85 | - tvo: TV encoder output | ||
86 | |||
87 | Required properties: | ||
88 | - compatible: "nvidia,tegra<chip>-tvo" | ||
89 | - reg: Physical base address and length of the controller's registers. | ||
90 | - interrupts: The interrupt outputs from the controller. | ||
91 | |||
92 | - dsi: display serial interface | ||
93 | |||
94 | Required properties: | ||
95 | - compatible: "nvidia,tegra<chip>-dsi" | ||
96 | - reg: Physical base address and length of the controller's registers. | ||
97 | |||
98 | Example: | ||
99 | |||
100 | / { | ||
101 | ... | ||
102 | |||
103 | host1x { | ||
104 | compatible = "nvidia,tegra20-host1x", "simple-bus"; | ||
105 | reg = <0x50000000 0x00024000>; | ||
106 | interrupts = <0 65 0x04 /* mpcore syncpt */ | ||
107 | 0 67 0x04>; /* mpcore general */ | ||
108 | |||
109 | #address-cells = <1>; | ||
110 | #size-cells = <1>; | ||
111 | |||
112 | ranges = <0x54000000 0x54000000 0x04000000>; | ||
113 | |||
114 | mpe { | ||
115 | compatible = "nvidia,tegra20-mpe"; | ||
116 | reg = <0x54040000 0x00040000>; | ||
117 | interrupts = <0 68 0x04>; | ||
118 | }; | ||
119 | |||
120 | vi { | ||
121 | compatible = "nvidia,tegra20-vi"; | ||
122 | reg = <0x54080000 0x00040000>; | ||
123 | interrupts = <0 69 0x04>; | ||
124 | }; | ||
125 | |||
126 | epp { | ||
127 | compatible = "nvidia,tegra20-epp"; | ||
128 | reg = <0x540c0000 0x00040000>; | ||
129 | interrupts = <0 70 0x04>; | ||
130 | }; | ||
131 | |||
132 | isp { | ||
133 | compatible = "nvidia,tegra20-isp"; | ||
134 | reg = <0x54100000 0x00040000>; | ||
135 | interrupts = <0 71 0x04>; | ||
136 | }; | ||
137 | |||
138 | gr2d { | ||
139 | compatible = "nvidia,tegra20-gr2d"; | ||
140 | reg = <0x54140000 0x00040000>; | ||
141 | interrupts = <0 72 0x04>; | ||
142 | }; | ||
143 | |||
144 | gr3d { | ||
145 | compatible = "nvidia,tegra20-gr3d"; | ||
146 | reg = <0x54180000 0x00040000>; | ||
147 | }; | ||
148 | |||
149 | dc@54200000 { | ||
150 | compatible = "nvidia,tegra20-dc"; | ||
151 | reg = <0x54200000 0x00040000>; | ||
152 | interrupts = <0 73 0x04>; | ||
153 | |||
154 | rgb { | ||
155 | status = "disabled"; | ||
156 | }; | ||
157 | }; | ||
158 | |||
159 | dc@54240000 { | ||
160 | compatible = "nvidia,tegra20-dc"; | ||
161 | reg = <0x54240000 0x00040000>; | ||
162 | interrupts = <0 74 0x04>; | ||
163 | |||
164 | rgb { | ||
165 | status = "disabled"; | ||
166 | }; | ||
167 | }; | ||
168 | |||
169 | hdmi { | ||
170 | compatible = "nvidia,tegra20-hdmi"; | ||
171 | reg = <0x54280000 0x00040000>; | ||
172 | interrupts = <0 75 0x04>; | ||
173 | status = "disabled"; | ||
174 | }; | ||
175 | |||
176 | tvo { | ||
177 | compatible = "nvidia,tegra20-tvo"; | ||
178 | reg = <0x542c0000 0x00040000>; | ||
179 | interrupts = <0 76 0x04>; | ||
180 | status = "disabled"; | ||
181 | }; | ||
182 | |||
183 | dsi { | ||
184 | compatible = "nvidia,tegra20-dsi"; | ||
185 | reg = <0x54300000 0x00040000>; | ||
186 | status = "disabled"; | ||
187 | }; | ||
188 | }; | ||
189 | |||
190 | ... | ||
191 | }; | ||
diff --git a/Documentation/devicetree/bindings/hwmon/vexpress.txt b/Documentation/devicetree/bindings/hwmon/vexpress.txt deleted file mode 100644 index 9c27ed694bb..00000000000 --- a/Documentation/devicetree/bindings/hwmon/vexpress.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | Versatile Express hwmon sensors | ||
2 | ------------------------------- | ||
3 | |||
4 | Requires node properties: | ||
5 | - "compatible" value : one of | ||
6 | "arm,vexpress-volt" | ||
7 | "arm,vexpress-amp" | ||
8 | "arm,vexpress-temp" | ||
9 | "arm,vexpress-power" | ||
10 | "arm,vexpress-energy" | ||
11 | - "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg | ||
12 | (see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt | ||
13 | for more details) | ||
14 | |||
15 | Optional node properties: | ||
16 | - label : string describing the monitored value | ||
17 | |||
18 | Example: | ||
19 | energy@0 { | ||
20 | compatible = "arm,vexpress-energy"; | ||
21 | arm,vexpress-sysreg,func = <13 0>; | ||
22 | label = "A15 Jcore"; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt deleted file mode 100644 index b689a0d9441..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | I2C for Atmel platforms | ||
2 | |||
3 | Required properties : | ||
4 | - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c", | ||
5 | "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c" | ||
6 | or "atmel,at91sam9x5-i2c" | ||
7 | - reg: physical base address of the controller and length of memory mapped | ||
8 | region. | ||
9 | - interrupts: interrupt number to the cpu. | ||
10 | - #address-cells = <1>; | ||
11 | - #size-cells = <0>; | ||
12 | |||
13 | Optional properties: | ||
14 | - Child nodes conforming to i2c bus binding | ||
15 | |||
16 | Examples : | ||
17 | |||
18 | i2c0: i2c@fff84000 { | ||
19 | compatible = "atmel,at91sam9g20-i2c"; | ||
20 | reg = <0xfff84000 0x100>; | ||
21 | interrupts = <12 4 6>; | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | |||
25 | 24c512@50 { | ||
26 | compatible = "24c512"; | ||
27 | reg = <0x50>; | ||
28 | pagesize = <128>; | ||
29 | } | ||
30 | } | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt deleted file mode 100644 index 8ce9cd2855b..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | Device tree bindings for i2c-cbus-gpio driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible = "i2c-cbus-gpio"; | ||
5 | - gpios: clk, dat, sel | ||
6 | - #address-cells = <1>; | ||
7 | - #size-cells = <0>; | ||
8 | |||
9 | Optional properties: | ||
10 | - child nodes conforming to i2c bus binding | ||
11 | |||
12 | Example: | ||
13 | |||
14 | i2c@0 { | ||
15 | compatible = "i2c-cbus-gpio"; | ||
16 | gpios = <&gpio 66 0 /* clk */ | ||
17 | &gpio 65 0 /* dat */ | ||
18 | &gpio 64 0 /* sel */ | ||
19 | >; | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <0>; | ||
22 | |||
23 | retu-mfd: retu@1 { | ||
24 | compatible = "retu-mfd"; | ||
25 | reg = <0x1>; | ||
26 | }; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt deleted file mode 100644 index 2dc935b4113..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | * Texas Instruments Davinci I2C | ||
2 | |||
3 | This file provides information, what the device node for the | ||
4 | davinci i2c interface contain. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "ti,davinci-i2c"; | ||
8 | - reg : Offset and length of the register set for the device | ||
9 | |||
10 | Recommended properties : | ||
11 | - interrupts : standard interrupt property. | ||
12 | - clock-frequency : desired I2C bus clock frequency in Hz. | ||
13 | |||
14 | Example (enbw_cmc board): | ||
15 | i2c@1c22000 { | ||
16 | compatible = "ti,davinci-i2c"; | ||
17 | reg = <0x22000 0x1000>; | ||
18 | clock-frequency = <100000>; | ||
19 | interrupts = <15>; | ||
20 | interrupt-parent = <&intc>; | ||
21 | #address-cells = <1>; | ||
22 | #size-cells = <0>; | ||
23 | |||
24 | dtt@48 { | ||
25 | compatible = "national,lm75"; | ||
26 | reg = <0x48>; | ||
27 | }; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt deleted file mode 100644 index e42a2ee233e..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | * Synopsys DesignWare I2C | ||
2 | |||
3 | Required properties : | ||
4 | |||
5 | - compatible : should be "snps,designware-i2c" | ||
6 | - reg : Offset and length of the register set for the device | ||
7 | - interrupts : <IRQ> where IRQ is the interrupt number. | ||
8 | |||
9 | Recommended properties : | ||
10 | |||
11 | - clock-frequency : desired I2C bus clock frequency in Hz. | ||
12 | |||
13 | Example : | ||
14 | |||
15 | i2c@f0000 { | ||
16 | #address-cells = <1>; | ||
17 | #size-cells = <0>; | ||
18 | compatible = "snps,designware-i2c"; | ||
19 | reg = <0xf0000 0x1000>; | ||
20 | interrupts = <11>; | ||
21 | clock-frequency = <400000>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt deleted file mode 100644 index 4f8ec947c6b..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-gpio.txt +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | Device-Tree bindings for i2c gpio driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible = "i2c-gpio"; | ||
5 | - gpios: sda and scl gpio | ||
6 | |||
7 | |||
8 | Optional properties: | ||
9 | - i2c-gpio,sda-open-drain: sda as open drain | ||
10 | - i2c-gpio,scl-open-drain: scl as open drain | ||
11 | - i2c-gpio,scl-output-only: scl as output only | ||
12 | - i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform) | ||
13 | - i2c-gpio,timeout-ms: timeout to get data | ||
14 | |||
15 | Example nodes: | ||
16 | |||
17 | i2c@0 { | ||
18 | compatible = "i2c-gpio"; | ||
19 | gpios = <&pioA 23 0 /* sda */ | ||
20 | &pioA 24 0 /* scl */ | ||
21 | >; | ||
22 | i2c-gpio,sda-open-drain; | ||
23 | i2c-gpio,scl-open-drain; | ||
24 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | ||
25 | #address-cells = <1>; | ||
26 | #size-cells = <0>; | ||
27 | |||
28 | rv3029c2@56 { | ||
29 | compatible = "rv3029c2"; | ||
30 | reg = <0x56>; | ||
31 | }; | ||
32 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.txt b/Documentation/devicetree/bindings/i2c/i2c-imx.txt deleted file mode 100644 index 3614242e773..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-imx.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "fsl,<chip>-i2c" | ||
5 | - reg : Should contain I2C/HS-I2C registers location and length | ||
6 | - interrupts : Should contain I2C/HS-I2C interrupt | ||
7 | |||
8 | Optional properties: | ||
9 | - clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz. | ||
10 | The absence of the propoerty indicates the default frequency 100 kHz. | ||
11 | |||
12 | Examples: | ||
13 | |||
14 | i2c@83fc4000 { /* I2C2 on i.MX51 */ | ||
15 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; | ||
16 | reg = <0x83fc4000 0x4000>; | ||
17 | interrupts = <63>; | ||
18 | }; | ||
19 | |||
20 | i2c@70038000 { /* HS-I2C on i.MX51 */ | ||
21 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; | ||
22 | reg = <0x70038000 0x4000>; | ||
23 | interrupts = <64>; | ||
24 | clock-frequency = <400000>; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mpc.txt b/Documentation/devicetree/bindings/i2c/i2c-mpc.txt deleted file mode 100644 index 1eacd6b20ed..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mpc.txt +++ /dev/null | |||
@@ -1,64 +0,0 @@ | |||
1 | * I2C | ||
2 | |||
3 | Required properties : | ||
4 | |||
5 | - reg : Offset and length of the register set for the device | ||
6 | - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a | ||
7 | compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121, | ||
8 | mpc5200 or mpc5200b. For the mpc5121, an additional node | ||
9 | "fsl,mpc5121-i2c-ctrl" is required as shown in the example below. | ||
10 | |||
11 | Recommended properties : | ||
12 | |||
13 | - interrupts : <a b> where a is the interrupt number and b is a | ||
14 | field that represents an encoding of the sense and level | ||
15 | information for the interrupt. This should be encoded based on | ||
16 | the information in section 2) depending on the type of interrupt | ||
17 | controller you have. | ||
18 | - interrupt-parent : the phandle for the interrupt controller that | ||
19 | services interrupts for this device. | ||
20 | - fsl,preserve-clocking : boolean; if defined, the clock settings | ||
21 | from the bootloader are preserved (not touched). | ||
22 | - clock-frequency : desired I2C bus clock frequency in Hz. | ||
23 | - fsl,timeout : I2C bus timeout in microseconds. | ||
24 | |||
25 | Examples : | ||
26 | |||
27 | /* MPC5121 based board */ | ||
28 | i2c@1740 { | ||
29 | #address-cells = <1>; | ||
30 | #size-cells = <0>; | ||
31 | compatible = "fsl,mpc5121-i2c", "fsl-i2c"; | ||
32 | reg = <0x1740 0x20>; | ||
33 | interrupts = <11 0x8>; | ||
34 | interrupt-parent = <&ipic>; | ||
35 | clock-frequency = <100000>; | ||
36 | }; | ||
37 | |||
38 | i2ccontrol@1760 { | ||
39 | compatible = "fsl,mpc5121-i2c-ctrl"; | ||
40 | reg = <0x1760 0x8>; | ||
41 | }; | ||
42 | |||
43 | /* MPC5200B based board */ | ||
44 | i2c@3d00 { | ||
45 | #address-cells = <1>; | ||
46 | #size-cells = <0>; | ||
47 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | ||
48 | reg = <0x3d00 0x40>; | ||
49 | interrupts = <2 15 0>; | ||
50 | interrupt-parent = <&mpc5200_pic>; | ||
51 | fsl,preserve-clocking; | ||
52 | }; | ||
53 | |||
54 | /* MPC8544 base board */ | ||
55 | i2c@3100 { | ||
56 | #address-cells = <1>; | ||
57 | #size-cells = <0>; | ||
58 | compatible = "fsl,mpc8544-i2c", "fsl-i2c"; | ||
59 | reg = <0x3100 0x100>; | ||
60 | interrupts = <43 2>; | ||
61 | interrupt-parent = <&mpic>; | ||
62 | clock-frequency = <400000>; | ||
63 | fsl,timeout = <10000>; | ||
64 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt deleted file mode 100644 index 66709a82554..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt +++ /dev/null | |||
@@ -1,81 +0,0 @@ | |||
1 | GPIO-based I2C Bus Mux | ||
2 | |||
3 | This binding describes an I2C bus multiplexer that uses GPIOs to | ||
4 | route the I2C signals. | ||
5 | |||
6 | +-----+ +-----+ | ||
7 | | dev | | dev | | ||
8 | +------------+ +-----+ +-----+ | ||
9 | | SoC | | | | ||
10 | | | /--------+--------+ | ||
11 | | +------+ | +------+ child bus A, on GPIO value set to 0 | ||
12 | | | I2C |-|--| Mux | | ||
13 | | +------+ | +--+---+ child bus B, on GPIO value set to 1 | ||
14 | | | | \----------+--------+--------+ | ||
15 | | +------+ | | | | | | ||
16 | | | GPIO |-|-----+ +-----+ +-----+ +-----+ | ||
17 | | +------+ | | dev | | dev | | dev | | ||
18 | +------------+ +-----+ +-----+ +-----+ | ||
19 | |||
20 | Required properties: | ||
21 | - compatible: i2c-mux-gpio | ||
22 | - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side | ||
23 | port is connected to. | ||
24 | - mux-gpios: list of gpios used to control the muxer | ||
25 | * Standard I2C mux properties. See mux.txt in this directory. | ||
26 | * I2C child bus nodes. See mux.txt in this directory. | ||
27 | |||
28 | Optional properties: | ||
29 | - idle-state: value to set the muxer to when idle. When no value is | ||
30 | given, it defaults to the last value used. | ||
31 | |||
32 | For each i2c child node, an I2C child bus will be created. They will | ||
33 | be numbered based on their order in the device tree. | ||
34 | |||
35 | Whenever an access is made to a device on a child bus, the value set | ||
36 | in the revelant node's reg property will be output using the list of | ||
37 | GPIOs, the first in the list holding the least-significant value. | ||
38 | |||
39 | If an idle state is defined, using the idle-state (optional) property, | ||
40 | whenever an access is not being made to a device on a child bus, the | ||
41 | GPIOs will be set according to the idle value. | ||
42 | |||
43 | If an idle state is not defined, the most recently used value will be | ||
44 | left programmed into hardware whenever no access is being made to a | ||
45 | device on a child bus. | ||
46 | |||
47 | Example: | ||
48 | i2cmux { | ||
49 | compatible = "i2c-mux-gpio"; | ||
50 | #address-cells = <1>; | ||
51 | #size-cells = <0>; | ||
52 | mux-gpios = <&gpio1 22 0 &gpio1 23 0>; | ||
53 | i2c-parent = <&i2c1>; | ||
54 | |||
55 | i2c@1 { | ||
56 | reg = <1>; | ||
57 | #address-cells = <1>; | ||
58 | #size-cells = <0>; | ||
59 | |||
60 | ssd1307: oled@3c { | ||
61 | compatible = "solomon,ssd1307fb-i2c"; | ||
62 | reg = <0x3c>; | ||
63 | pwms = <&pwm 4 3000>; | ||
64 | reset-gpios = <&gpio2 7 1>; | ||
65 | reset-active-low; | ||
66 | }; | ||
67 | }; | ||
68 | |||
69 | i2c@3 { | ||
70 | reg = <3>; | ||
71 | #address-cells = <1>; | ||
72 | #size-cells = <0>; | ||
73 | |||
74 | pca9555: pca9555@20 { | ||
75 | compatible = "nxp,pca9555"; | ||
76 | gpio-controller; | ||
77 | #gpio-cells = <2>; | ||
78 | reg = <0x20>; | ||
79 | }; | ||
80 | }; | ||
81 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt deleted file mode 100644 index ae8af1694e9..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt +++ /dev/null | |||
@@ -1,93 +0,0 @@ | |||
1 | Pinctrl-based I2C Bus Mux | ||
2 | |||
3 | This binding describes an I2C bus multiplexer that uses pin multiplexing to | ||
4 | route the I2C signals, and represents the pin multiplexing configuration | ||
5 | using the pinctrl device tree bindings. | ||
6 | |||
7 | +-----+ +-----+ | ||
8 | | dev | | dev | | ||
9 | +------------------------+ +-----+ +-----+ | ||
10 | | SoC | | | | ||
11 | | /----|------+--------+ | ||
12 | | +---+ +------+ | child bus A, on first set of pins | ||
13 | | |I2C|---|Pinmux| | | ||
14 | | +---+ +------+ | child bus B, on second set of pins | ||
15 | | \----|------+--------+--------+ | ||
16 | | | | | | | ||
17 | +------------------------+ +-----+ +-----+ +-----+ | ||
18 | | dev | | dev | | dev | | ||
19 | +-----+ +-----+ +-----+ | ||
20 | |||
21 | Required properties: | ||
22 | - compatible: i2c-mux-pinctrl | ||
23 | - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side | ||
24 | port is connected to. | ||
25 | |||
26 | Also required are: | ||
27 | |||
28 | * Standard pinctrl properties that specify the pin mux state for each child | ||
29 | bus. See ../pinctrl/pinctrl-bindings.txt. | ||
30 | |||
31 | * Standard I2C mux properties. See mux.txt in this directory. | ||
32 | |||
33 | * I2C child bus nodes. See mux.txt in this directory. | ||
34 | |||
35 | For each named state defined in the pinctrl-names property, an I2C child bus | ||
36 | will be created. I2C child bus numbers are assigned based on the index into | ||
37 | the pinctrl-names property. | ||
38 | |||
39 | The only exception is that no bus will be created for a state named "idle". If | ||
40 | such a state is defined, it must be the last entry in pinctrl-names. For | ||
41 | example: | ||
42 | |||
43 | pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1 | ||
44 | pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last) | ||
45 | pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last) | ||
46 | |||
47 | Whenever an access is made to a device on a child bus, the relevant pinctrl | ||
48 | state will be programmed into hardware. | ||
49 | |||
50 | If an idle state is defined, whenever an access is not being made to a device | ||
51 | on a child bus, the idle pinctrl state will be programmed into hardware. | ||
52 | |||
53 | If an idle state is not defined, the most recently used pinctrl state will be | ||
54 | left programmed into hardware whenever no access is being made of a device on | ||
55 | a child bus. | ||
56 | |||
57 | Example: | ||
58 | |||
59 | i2cmux { | ||
60 | compatible = "i2c-mux-pinctrl"; | ||
61 | #address-cells = <1>; | ||
62 | #size-cells = <0>; | ||
63 | |||
64 | i2c-parent = <&i2c1>; | ||
65 | |||
66 | pinctrl-names = "ddc", "pta", "idle"; | ||
67 | pinctrl-0 = <&state_i2cmux_ddc>; | ||
68 | pinctrl-1 = <&state_i2cmux_pta>; | ||
69 | pinctrl-2 = <&state_i2cmux_idle>; | ||
70 | |||
71 | i2c@0 { | ||
72 | reg = <0>; | ||
73 | #address-cells = <1>; | ||
74 | #size-cells = <0>; | ||
75 | |||
76 | eeprom { | ||
77 | compatible = "eeprom"; | ||
78 | reg = <0x50>; | ||
79 | }; | ||
80 | }; | ||
81 | |||
82 | i2c@1 { | ||
83 | reg = <1>; | ||
84 | #address-cells = <1>; | ||
85 | #size-cells = <0>; | ||
86 | |||
87 | eeprom { | ||
88 | compatible = "eeprom"; | ||
89 | reg = <0x50>; | ||
90 | }; | ||
91 | }; | ||
92 | }; | ||
93 | |||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux.txt deleted file mode 100644 index af84cce5cd7..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux.txt +++ /dev/null | |||
@@ -1,60 +0,0 @@ | |||
1 | Common i2c bus multiplexer/switch properties. | ||
2 | |||
3 | An i2c bus multiplexer/switch will have several child busses that are | ||
4 | numbered uniquely in a device dependent manner. The nodes for an i2c bus | ||
5 | multiplexer/switch will have one child node for each child | ||
6 | bus. | ||
7 | |||
8 | Required properties: | ||
9 | - #address-cells = <1>; | ||
10 | - #size-cells = <0>; | ||
11 | |||
12 | Required properties for child nodes: | ||
13 | - #address-cells = <1>; | ||
14 | - #size-cells = <0>; | ||
15 | - reg : The sub-bus number. | ||
16 | |||
17 | Optional properties for child nodes: | ||
18 | - Other properties specific to the multiplexer/switch hardware. | ||
19 | - Child nodes conforming to i2c bus binding | ||
20 | |||
21 | |||
22 | Example : | ||
23 | |||
24 | /* | ||
25 | An NXP pca9548 8 channel I2C multiplexer at address 0x70 | ||
26 | with two NXP pca8574 GPIO expanders attached, one each to | ||
27 | ports 3 and 4. | ||
28 | */ | ||
29 | |||
30 | mux@70 { | ||
31 | compatible = "nxp,pca9548"; | ||
32 | reg = <0x70>; | ||
33 | #address-cells = <1>; | ||
34 | #size-cells = <0>; | ||
35 | |||
36 | i2c@3 { | ||
37 | #address-cells = <1>; | ||
38 | #size-cells = <0>; | ||
39 | reg = <3>; | ||
40 | |||
41 | gpio1: gpio@38 { | ||
42 | compatible = "nxp,pca8574"; | ||
43 | reg = <0x38>; | ||
44 | #gpio-cells = <2>; | ||
45 | gpio-controller; | ||
46 | }; | ||
47 | }; | ||
48 | i2c@4 { | ||
49 | #address-cells = <1>; | ||
50 | #size-cells = <0>; | ||
51 | reg = <4>; | ||
52 | |||
53 | gpio2: gpio@38 { | ||
54 | compatible = "nxp,pca8574"; | ||
55 | reg = <0x38>; | ||
56 | #gpio-cells = <2>; | ||
57 | gpio-controller; | ||
58 | }; | ||
59 | }; | ||
60 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt deleted file mode 100644 index f46d928aa73..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | |||
2 | * Marvell MV64XXX I2C controller | ||
3 | |||
4 | Required properties : | ||
5 | |||
6 | - reg : Offset and length of the register set for the device | ||
7 | - compatible : Should be "marvell,mv64xxx-i2c" | ||
8 | - interrupts : The interrupt number | ||
9 | - clock-frequency : Desired I2C bus clock frequency in Hz. | ||
10 | |||
11 | Examples: | ||
12 | |||
13 | i2c@11000 { | ||
14 | compatible = "marvell,mv64xxx-i2c"; | ||
15 | reg = <0x11000 0x20>; | ||
16 | interrupts = <29>; | ||
17 | clock-frequency = <100000>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt deleted file mode 100644 index 7a3fe9e5f4c..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | * Freescale MXS Inter IC (I2C) Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,<chip>-i2c" | ||
5 | - reg: Should contain registers location and length | ||
6 | - interrupts: Should contain ERROR and DMA interrupts | ||
7 | - clock-frequency: Desired I2C bus clock frequency in Hz. | ||
8 | Only 100000Hz and 400000Hz modes are supported. | ||
9 | - fsl,i2c-dma-channel: APBX DMA channel for the I2C | ||
10 | |||
11 | Examples: | ||
12 | |||
13 | i2c0: i2c@80058000 { | ||
14 | #address-cells = <1>; | ||
15 | #size-cells = <0>; | ||
16 | compatible = "fsl,imx28-i2c"; | ||
17 | reg = <0x80058000 2000>; | ||
18 | interrupts = <111 68>; | ||
19 | clock-frequency = <100000>; | ||
20 | fsl,i2c-dma-channel = <6>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt b/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt deleted file mode 100644 index 72065b0ff68..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | I2C for Nomadik based systems | ||
2 | |||
3 | Required (non-standard) properties: | ||
4 | - Nil | ||
5 | |||
6 | Recommended (non-standard) properties: | ||
7 | - clock-frequency : Maximum bus clock frequency for the device | ||
8 | |||
9 | Optional (non-standard) properties: | ||
10 | - Nil | ||
11 | |||
12 | Example : | ||
13 | |||
14 | i2c@80004000 { | ||
15 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; | ||
16 | reg = <0x80004000 0x1000>; | ||
17 | interrupts = <0 21 0x4>; | ||
18 | #address-cells = <1>; | ||
19 | #size-cells = <0>; | ||
20 | v-i2c-supply = <&db8500_vape_reg>; | ||
21 | |||
22 | clock-frequency = <400000>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt deleted file mode 100644 index 1637c298a1b..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | Device tree configuration for i2c-ocores | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst" | ||
5 | - reg : bus address start and address range size of device | ||
6 | - interrupts : interrupt number | ||
7 | - clock-frequency : frequency of bus clock in Hz | ||
8 | - #address-cells : should be <1> | ||
9 | - #size-cells : should be <0> | ||
10 | |||
11 | Optional properties: | ||
12 | - reg-shift : device register offsets are shifted by this value | ||
13 | - reg-io-width : io register width in bytes (1, 2 or 4) | ||
14 | - regstep : deprecated, use reg-shift above | ||
15 | |||
16 | Example: | ||
17 | |||
18 | i2c0: ocores@a0000000 { | ||
19 | #address-cells = <1>; | ||
20 | #size-cells = <0>; | ||
21 | compatible = "opencores,i2c-ocores"; | ||
22 | reg = <0xa0000000 0x8>; | ||
23 | interrupts = <10>; | ||
24 | clock-frequency = <20000000>; | ||
25 | |||
26 | reg-shift = <0>; /* 8 bit registers */ | ||
27 | reg-io-width = <1>; /* 8 bit read/write */ | ||
28 | |||
29 | dummy@60 { | ||
30 | compatible = "dummy"; | ||
31 | reg = <0x60>; | ||
32 | }; | ||
33 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt deleted file mode 100644 index dced82ebe31..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | * Two Wire Serial Interface (TWSI) / I2C | ||
2 | |||
3 | - compatible: "cavium,octeon-3860-twsi" | ||
4 | |||
5 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
6 | |||
7 | - reg: The base address of the TWSI/I2C bus controller register bank. | ||
8 | |||
9 | - #address-cells: Must be <1>. | ||
10 | |||
11 | - #size-cells: Must be <0>. I2C addresses have no size component. | ||
12 | |||
13 | - interrupts: A single interrupt specifier. | ||
14 | |||
15 | - clock-frequency: The I2C bus clock rate in Hz. | ||
16 | |||
17 | Example: | ||
18 | twsi0: i2c@1180000001000 { | ||
19 | #address-cells = <1>; | ||
20 | #size-cells = <0>; | ||
21 | compatible = "cavium,octeon-3860-twsi"; | ||
22 | reg = <0x11800 0x00001000 0x0 0x200>; | ||
23 | interrupts = <0 45>; | ||
24 | clock-frequency = <100000>; | ||
25 | |||
26 | rtc@68 { | ||
27 | compatible = "dallas,ds1337"; | ||
28 | reg = <0x68>; | ||
29 | }; | ||
30 | tmp@4c { | ||
31 | compatible = "ti,tmp421"; | ||
32 | reg = <0x4c>; | ||
33 | }; | ||
34 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-omap.txt b/Documentation/devicetree/bindings/i2c/i2c-omap.txt deleted file mode 100644 index 56564aa4b44..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-omap.txt +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | I2C for OMAP platforms | ||
2 | |||
3 | Required properties : | ||
4 | - compatible : Must be "ti,omap3-i2c" or "ti,omap4-i2c" | ||
5 | - ti,hwmods : Must be "i2c<n>", n being the instance number (1-based) | ||
6 | - #address-cells = <1>; | ||
7 | - #size-cells = <0>; | ||
8 | |||
9 | Recommended properties : | ||
10 | - clock-frequency : Desired I2C bus clock frequency in Hz. Otherwise | ||
11 | the default 100 kHz frequency will be used. | ||
12 | |||
13 | Optional properties: | ||
14 | - Child nodes conforming to i2c bus binding | ||
15 | |||
16 | Note: Current implementation will fetch base address, irq and dma | ||
17 | from omap hwmod data base during device registration. | ||
18 | Future plan is to migrate hwmod data base contents into device tree | ||
19 | blob so that, all the required data will be used from device tree dts | ||
20 | file. | ||
21 | |||
22 | Examples : | ||
23 | |||
24 | i2c1: i2c@0 { | ||
25 | compatible = "ti,omap3-i2c"; | ||
26 | #address-cells = <1>; | ||
27 | #size-cells = <0>; | ||
28 | ti,hwmods = "i2c1"; | ||
29 | clock-frequency = <400000>; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pnx.txt b/Documentation/devicetree/bindings/i2c/i2c-pnx.txt deleted file mode 100644 index fe98ada33ee..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-pnx.txt +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | * NXP PNX I2C Controller | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - reg: Offset and length of the register set for the device | ||
6 | - compatible: should be "nxp,pnx-i2c" | ||
7 | - interrupts: configure one interrupt line | ||
8 | - #address-cells: always 1 (for i2c addresses) | ||
9 | - #size-cells: always 0 | ||
10 | - interrupt-parent: the phandle for the interrupt controller that | ||
11 | services interrupts for this device. | ||
12 | |||
13 | Optional properties: | ||
14 | |||
15 | - clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz | ||
16 | |||
17 | Examples: | ||
18 | |||
19 | i2c1: i2c@400a0000 { | ||
20 | compatible = "nxp,pnx-i2c"; | ||
21 | reg = <0x400a0000 0x100>; | ||
22 | interrupt-parent = <&mic>; | ||
23 | interrupts = <51 0>; | ||
24 | #address-cells = <1>; | ||
25 | #size-cells = <0>; | ||
26 | }; | ||
27 | |||
28 | i2c2: i2c@400a8000 { | ||
29 | compatible = "nxp,pnx-i2c"; | ||
30 | reg = <0x400a8000 0x100>; | ||
31 | interrupt-parent = <&mic>; | ||
32 | interrupts = <50 0>; | ||
33 | #address-cells = <1>; | ||
34 | #size-cells = <0>; | ||
35 | clock-frequency = <100000>; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt deleted file mode 100644 index 569b1624851..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt +++ /dev/null | |||
@@ -1,93 +0,0 @@ | |||
1 | CE4100 I2C | ||
2 | ---------- | ||
3 | |||
4 | CE4100 has one PCI device which is described as the I2C-Controller. This | ||
5 | PCI device has three PCI-bars, each bar contains a complete I2C | ||
6 | controller. So we have a total of three independent I2C-Controllers | ||
7 | which share only an interrupt line. | ||
8 | The driver is probed via the PCI-ID and is gathering the information of | ||
9 | attached devices from the devices tree. | ||
10 | Grant Likely recommended to use the ranges property to map the PCI-Bar | ||
11 | number to its physical address and to use this to find the child nodes | ||
12 | of the specific I2C controller. This were his exact words: | ||
13 | |||
14 | Here's where the magic happens. Each entry in | ||
15 | ranges describes how the parent pci address space | ||
16 | (middle group of 3) is translated to the local | ||
17 | address space (first group of 2) and the size of | ||
18 | each range (last cell). In this particular case, | ||
19 | the first cell of the local address is chosen to be | ||
20 | 1:1 mapped to the BARs, and the second is the | ||
21 | offset from be base of the BAR (which would be | ||
22 | non-zero if you had 2 or more devices mapped off | ||
23 | the same BAR) | ||
24 | |||
25 | ranges allows the address mapping to be described | ||
26 | in a way that the OS can interpret without | ||
27 | requiring custom device driver code. | ||
28 | |||
29 | This is an example which is used on FalconFalls: | ||
30 | ------------------------------------------------ | ||
31 | i2c-controller@b,2 { | ||
32 | #address-cells = <2>; | ||
33 | #size-cells = <1>; | ||
34 | compatible = "pci8086,2e68.2", | ||
35 | "pci8086,2e68", | ||
36 | "pciclass,ff0000", | ||
37 | "pciclass,ff00"; | ||
38 | |||
39 | reg = <0x15a00 0x0 0x0 0x0 0x0>; | ||
40 | interrupts = <16 1>; | ||
41 | |||
42 | /* as described by Grant, the first number in the group of | ||
43 | * three is the bar number followed by the 64bit bar address | ||
44 | * followed by size of the mapping. The bar address | ||
45 | * requires also a valid translation in parents ranges | ||
46 | * property. | ||
47 | */ | ||
48 | ranges = <0 0 0x02000000 0 0xdffe0500 0x100 | ||
49 | 1 0 0x02000000 0 0xdffe0600 0x100 | ||
50 | 2 0 0x02000000 0 0xdffe0700 0x100>; | ||
51 | |||
52 | i2c@0 { | ||
53 | #address-cells = <1>; | ||
54 | #size-cells = <0>; | ||
55 | compatible = "intel,ce4100-i2c-controller"; | ||
56 | |||
57 | /* The first number in the reg property is the | ||
58 | * number of the bar | ||
59 | */ | ||
60 | reg = <0 0 0x100>; | ||
61 | |||
62 | /* This I2C controller has no devices */ | ||
63 | }; | ||
64 | |||
65 | i2c@1 { | ||
66 | #address-cells = <1>; | ||
67 | #size-cells = <0>; | ||
68 | compatible = "intel,ce4100-i2c-controller"; | ||
69 | reg = <1 0 0x100>; | ||
70 | |||
71 | /* This I2C controller has one gpio controller */ | ||
72 | gpio@26 { | ||
73 | #gpio-cells = <2>; | ||
74 | compatible = "ti,pcf8575"; | ||
75 | reg = <0x26>; | ||
76 | gpio-controller; | ||
77 | }; | ||
78 | }; | ||
79 | |||
80 | i2c@2 { | ||
81 | #address-cells = <1>; | ||
82 | #size-cells = <0>; | ||
83 | compatible = "intel,ce4100-i2c-controller"; | ||
84 | reg = <2 0 0x100>; | ||
85 | |||
86 | gpio@26 { | ||
87 | #gpio-cells = <2>; | ||
88 | compatible = "ti,pcf8575"; | ||
89 | reg = <0x26>; | ||
90 | gpio-controller; | ||
91 | }; | ||
92 | }; | ||
93 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt deleted file mode 100644 index 12b78ac507e..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | * Marvell MMP I2C controller | ||
2 | |||
3 | Required properties : | ||
4 | |||
5 | - reg : Offset and length of the register set for the device | ||
6 | - compatible : should be "mrvl,mmp-twsi" where mmp is the name of a | ||
7 | compatible processor, e.g. pxa168, pxa910, mmp2, mmp3. | ||
8 | For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required | ||
9 | as shown in the example below. | ||
10 | |||
11 | Recommended properties : | ||
12 | |||
13 | - interrupts : the interrupt number | ||
14 | - interrupt-parent : the phandle for the interrupt controller that | ||
15 | services interrupts for this device. If the parent is the default | ||
16 | interrupt controller in device tree, it could be ignored. | ||
17 | - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling | ||
18 | status register of i2c controller instead. | ||
19 | - mrvl,i2c-fast-mode : Enable fast mode of i2c controller. | ||
20 | |||
21 | Examples: | ||
22 | twsi1: i2c@d4011000 { | ||
23 | compatible = "mrvl,mmp-twsi"; | ||
24 | reg = <0xd4011000 0x1000>; | ||
25 | interrupts = <7>; | ||
26 | mrvl,i2c-fast-mode; | ||
27 | }; | ||
28 | |||
29 | twsi2: i2c@d4025000 { | ||
30 | compatible = "mrvl,mmp-twsi"; | ||
31 | reg = <0xd4025000 0x1000>; | ||
32 | interrupts = <58>; | ||
33 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt deleted file mode 100644 index e9611ace879..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | * Samsung's I2C controller | ||
2 | |||
3 | The Samsung's I2C controller is used to interface with I2C devices. | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: value should be either of the following. | ||
7 | (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c. | ||
8 | (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c. | ||
9 | (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used | ||
10 | inside HDMIPHY block found on several samsung SoCs | ||
11 | - reg: physical base address of the controller and length of memory mapped | ||
12 | region. | ||
13 | - interrupts: interrupt number to the cpu. | ||
14 | - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges. | ||
15 | |||
16 | Required for all cases except "samsung,s3c2440-hdmiphy-i2c": | ||
17 | - Samsung GPIO variant (deprecated): | ||
18 | - gpios: The order of the gpios should be the following: <SDA, SCL>. | ||
19 | The gpio specifier depends on the gpio controller. Required in all | ||
20 | cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output | ||
21 | lines are permanently wired to the respective clienta | ||
22 | - Pinctrl variant (preferred, if available): | ||
23 | - pinctrl-0: Pin control group to be used for this controller. | ||
24 | - pinctrl-names: Should contain only one value - "default". | ||
25 | |||
26 | Optional properties: | ||
27 | - samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not | ||
28 | specified, default value is 0. | ||
29 | - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not | ||
30 | specified, the default value in Hz is 100000. | ||
31 | |||
32 | Example: | ||
33 | |||
34 | i2c@13870000 { | ||
35 | compatible = "samsung,s3c2440-i2c"; | ||
36 | reg = <0x13870000 0x100>; | ||
37 | interrupts = <345>; | ||
38 | samsung,i2c-sda-delay = <100>; | ||
39 | samsung,i2c-max-bus-freq = <100000>; | ||
40 | /* Samsung GPIO variant begins here */ | ||
41 | gpios = <&gpd1 2 0 /* SDA */ | ||
42 | &gpd1 3 0 /* SCL */>; | ||
43 | /* Samsung GPIO variant ends here */ | ||
44 | /* Pinctrl variant begins here */ | ||
45 | pinctrl-0 = <&i2c3_bus>; | ||
46 | pinctrl-names = "default"; | ||
47 | /* Pinctrl variant ends here */ | ||
48 | #address-cells = <1>; | ||
49 | #size-cells = <0>; | ||
50 | |||
51 | wm8994@1a { | ||
52 | compatible = "wlf,wm8994"; | ||
53 | reg = <0x1a>; | ||
54 | }; | ||
55 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sirf.txt b/Documentation/devicetree/bindings/i2c/i2c-sirf.txt deleted file mode 100644 index 7baf9e133fa..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-sirf.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | I2C for SiRFprimaII platforms | ||
2 | |||
3 | Required properties : | ||
4 | - compatible : Must be "sirf,prima2-i2c" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: interrupt number to the cpu. | ||
8 | |||
9 | Optional properties: | ||
10 | - clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz. | ||
11 | The absence of the propoerty indicates the default frequency 100 kHz. | ||
12 | |||
13 | Examples : | ||
14 | |||
15 | i2c0: i2c@b00e0000 { | ||
16 | compatible = "sirf,prima2-i2c"; | ||
17 | reg = <0xb00e0000 0x10000>; | ||
18 | interrupts = <24>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt b/Documentation/devicetree/bindings/i2c/i2c-versatile.txt deleted file mode 100644 index 361d31c51b6..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt +++ /dev/null | |||
@@ -1,10 +0,0 @@ | |||
1 | i2c Controller on ARM Versatile platform: | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Must be "arm,versatile-i2c"; | ||
5 | - reg | ||
6 | - #address-cells = <1>; | ||
7 | - #size-cells = <0>; | ||
8 | |||
9 | Optional properties: | ||
10 | - Child nodes conforming to i2c bus binding | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-xiic.txt b/Documentation/devicetree/bindings/i2c/i2c-xiic.txt deleted file mode 100644 index ceabbe91ae4..00000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-xiic.txt +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | Xilinx IIC controller: | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Must be "xlnx,xps-iic-2.00.a" | ||
5 | - reg : IIC register location and length | ||
6 | - interrupts : IIC controller unterrupt | ||
7 | - #address-cells = <1> | ||
8 | - #size-cells = <0> | ||
9 | |||
10 | Optional properties: | ||
11 | - Child nodes conforming to i2c bus binding | ||
12 | |||
13 | Example: | ||
14 | |||
15 | axi_iic_0: i2c@40800000 { | ||
16 | compatible = "xlnx,xps-iic-2.00.a"; | ||
17 | interrupts = < 1 2 >; | ||
18 | reg = < 0x40800000 0x10000 >; | ||
19 | |||
20 | #size-cells = <0>; | ||
21 | #address-cells = <1>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt deleted file mode 100644 index 446859fcdca..00000000000 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ /dev/null | |||
@@ -1,61 +0,0 @@ | |||
1 | This is a list of trivial i2c devices that have simple device tree | ||
2 | bindings, consisting only of a compatible field, an address and | ||
3 | possibly an interrupt line. | ||
4 | |||
5 | If a device needs more specific bindings, such as properties to | ||
6 | describe some aspect of it, there needs to be a specific binding | ||
7 | document for it just like any other devices. | ||
8 | |||
9 | |||
10 | Compatible Vendor / Chip | ||
11 | ========== ============= | ||
12 | ad,ad7414 SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin | ||
13 | ad,adm9240 ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems | ||
14 | adi,adt7461 +/-1C TDM Extended Temp Range I.C | ||
15 | adt7461 +/-1C TDM Extended Temp Range I.C | ||
16 | at,24c08 i2c serial eeprom (24cxx) | ||
17 | atmel,24c02 i2c serial eeprom (24cxx) | ||
18 | catalyst,24c32 i2c serial eeprom | ||
19 | dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock | ||
20 | dallas,ds1338 I2C RTC with 56-Byte NV RAM | ||
21 | dallas,ds1339 I2C Serial Real-Time Clock | ||
22 | dallas,ds1340 I2C RTC with Trickle Charger | ||
23 | dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output | ||
24 | dallas,ds1631 High-Precision Digital Thermometer | ||
25 | dallas,ds1682 Total-Elapsed-Time Recorder with Alarm | ||
26 | dallas,ds1775 Tiny Digital Thermometer and Thermostat | ||
27 | dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM | ||
28 | dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O | ||
29 | dallas,ds75 Digital Thermometer and Thermostat | ||
30 | dialog,da9053 DA9053: flexible system level PMIC with multicore support | ||
31 | epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE | ||
32 | epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE | ||
33 | fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer | ||
34 | fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51 | ||
35 | fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer | ||
36 | fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller | ||
37 | fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec | ||
38 | maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator | ||
39 | maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs | ||
40 | maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface | ||
41 | mc,rv3029c2 Real Time Clock Module with I2C-Bus | ||
42 | national,lm75 I2C TEMP SENSOR | ||
43 | national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor | ||
44 | national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface | ||
45 | nxp,pca9556 Octal SMBus and I2C registered interface | ||
46 | nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset | ||
47 | nxp,pcf8563 Real-time clock/calendar | ||
48 | ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus | ||
49 | pericom,pt7c4338 Real-time Clock Module | ||
50 | plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch | ||
51 | ramtron,24c64 i2c serial eeprom (24cxx) | ||
52 | ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC | ||
53 | samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) | ||
54 | st-micro,24c256 i2c serial eeprom (24cxx) | ||
55 | stm,m41t00 Serial Access TIMEKEEPER | ||
56 | stm,m41t62 Serial real-time clock (RTC) with alarm | ||
57 | stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS | ||
58 | taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface | ||
59 | ti,tsc2003 I2C Touch-Screen Controller | ||
60 | ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface | ||
61 | ti,tmp275 Digital Temperature Sensor | ||
diff --git a/Documentation/devicetree/bindings/input/fsl-mma8450.txt b/Documentation/devicetree/bindings/input/fsl-mma8450.txt index 0b96e5737d3..a00c94ccbde 100644 --- a/Documentation/devicetree/bindings/input/fsl-mma8450.txt +++ b/Documentation/devicetree/bindings/input/fsl-mma8450.txt | |||
@@ -2,7 +2,6 @@ | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "fsl,mma8450". | 4 | - compatible : "fsl,mma8450". |
5 | - reg: the I2C address of MMA8450 | ||
6 | 5 | ||
7 | Example: | 6 | Example: |
8 | 7 | ||
diff --git a/Documentation/devicetree/bindings/input/gpio-keys-polled.txt b/Documentation/devicetree/bindings/input/gpio-keys-polled.txt deleted file mode 100644 index 313abefa37c..00000000000 --- a/Documentation/devicetree/bindings/input/gpio-keys-polled.txt +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | Device-Tree bindings for input/gpio_keys_polled.c keyboard driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible = "gpio-keys-polled"; | ||
5 | - poll-interval: Poll interval time in milliseconds | ||
6 | |||
7 | Optional properties: | ||
8 | - autorepeat: Boolean, Enable auto repeat feature of Linux input | ||
9 | subsystem. | ||
10 | |||
11 | Each button (key) is represented as a sub-node of "gpio-keys-polled": | ||
12 | Subnode properties: | ||
13 | |||
14 | - gpios: OF device-tree gpio specification. | ||
15 | - label: Descriptive name of the key. | ||
16 | - linux,code: Keycode to emit. | ||
17 | |||
18 | Optional subnode-properties: | ||
19 | - linux,input-type: Specify event type this button/key generates. | ||
20 | If not specified defaults to <1> == EV_KEY. | ||
21 | - debounce-interval: Debouncing interval time in milliseconds. | ||
22 | If not specified defaults to 5. | ||
23 | - gpio-key,wakeup: Boolean, button can wake-up the system. | ||
24 | |||
25 | Example nodes: | ||
26 | |||
27 | gpio_keys_polled { | ||
28 | compatible = "gpio-keys-polled"; | ||
29 | #address-cells = <1>; | ||
30 | #size-cells = <0>; | ||
31 | poll-interval = <100>; | ||
32 | autorepeat; | ||
33 | button@21 { | ||
34 | label = "GPIO Key UP"; | ||
35 | linux,code = <103>; | ||
36 | gpios = <&gpio1 0 1>; | ||
37 | }; | ||
38 | ... | ||
diff --git a/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt b/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt deleted file mode 100644 index ead641c65e0..00000000000 --- a/Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt +++ /dev/null | |||
@@ -1,46 +0,0 @@ | |||
1 | * GPIO driven matrix keypad device tree bindings | ||
2 | |||
3 | GPIO driven matrix keypad is used to interface a SoC with a matrix keypad. | ||
4 | The matrix keypad supports multiple row and column lines, a key can be | ||
5 | placed at each intersection of a unique row and a unique column. The matrix | ||
6 | keypad can sense a key-press and key-release by means of GPIO lines and | ||
7 | report the event using GPIO interrupts to the cpu. | ||
8 | |||
9 | Required Properties: | ||
10 | - compatible: Should be "gpio-matrix-keypad" | ||
11 | - row-gpios: List of gpios used as row lines. The gpio specifier | ||
12 | for this property depends on the gpio controller to | ||
13 | which these row lines are connected. | ||
14 | - col-gpios: List of gpios used as column lines. The gpio specifier | ||
15 | for this property depends on the gpio controller to | ||
16 | which these column lines are connected. | ||
17 | - linux,keymap: The definition can be found at | ||
18 | bindings/input/matrix-keymap.txt | ||
19 | |||
20 | Optional Properties: | ||
21 | - linux,no-autorepeat: do no enable autorepeat feature. | ||
22 | - linux,wakeup: use any event on keypad as wakeup event. | ||
23 | - debounce-delay-ms: debounce interval in milliseconds | ||
24 | - col-scan-delay-us: delay, measured in microseconds, that is needed | ||
25 | before we can scan keypad after activating column gpio | ||
26 | |||
27 | Example: | ||
28 | matrix-keypad { | ||
29 | compatible = "gpio-matrix-keypad"; | ||
30 | debounce-delay-ms = <5>; | ||
31 | col-scan-delay-us = <2>; | ||
32 | |||
33 | row-gpios = <&gpio2 25 0 | ||
34 | &gpio2 26 0 | ||
35 | &gpio2 27 0>; | ||
36 | |||
37 | col-gpios = <&gpio2 21 0 | ||
38 | &gpio2 22 0>; | ||
39 | |||
40 | linux,keymap = <0x0000008B | ||
41 | 0x0100009E | ||
42 | 0x02000069 | ||
43 | 0x0001006A | ||
44 | 0x0101001C | ||
45 | 0x0201006C>; | ||
46 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/lpc32xx-key.txt b/Documentation/devicetree/bindings/input/lpc32xx-key.txt deleted file mode 100644 index 31afd5014c4..00000000000 --- a/Documentation/devicetree/bindings/input/lpc32xx-key.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | NXP LPC32xx Key Scan Interface | ||
2 | |||
3 | Required Properties: | ||
4 | - compatible: Should be "nxp,lpc3220-key" | ||
5 | - reg: Physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: The interrupt number to the cpu. | ||
8 | - keypad,num-rows: Number of rows and columns, e.g. 1: 1x1, 6: 6x6 | ||
9 | - keypad,num-columns: Must be equal to keypad,num-rows since LPC32xx only | ||
10 | supports square matrices | ||
11 | - nxp,debounce-delay-ms: Debounce delay in ms | ||
12 | - nxp,scan-delay-ms: Repeated scan period in ms | ||
13 | - linux,keymap: the key-code to be reported when the key is pressed | ||
14 | and released, see also | ||
15 | Documentation/devicetree/bindings/input/matrix-keymap.txt | ||
16 | |||
17 | Example: | ||
18 | |||
19 | key@40050000 { | ||
20 | compatible = "nxp,lpc3220-key"; | ||
21 | reg = <0x40050000 0x1000>; | ||
22 | interrupts = <54 0>; | ||
23 | keypad,num-rows = <1>; | ||
24 | keypad,num-columns = <1>; | ||
25 | nxp,debounce-delay-ms = <3>; | ||
26 | nxp,scan-delay-ms = <34>; | ||
27 | linux,keymap = <0x00000002>; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/matrix-keymap.txt b/Documentation/devicetree/bindings/input/matrix-keymap.txt deleted file mode 100644 index 3cd8b98ccd2..00000000000 --- a/Documentation/devicetree/bindings/input/matrix-keymap.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | A simple common binding for matrix-connected key boards. Currently targeted at | ||
2 | defining the keys in the scope of linux key codes since that is a stable and | ||
3 | standardized interface at this time. | ||
4 | |||
5 | Required properties: | ||
6 | - linux,keymap: an array of packed 1-cell entries containing the equivalent | ||
7 | of row, column and linux key-code. The 32-bit big endian cell is packed | ||
8 | as: | ||
9 | row << 24 | column << 16 | key-code | ||
10 | |||
11 | Optional properties: | ||
12 | Some users of this binding might choose to specify secondary keymaps for | ||
13 | cases where there is a modifier key such as a Fn key. Proposed names | ||
14 | for said properties are "linux,fn-keymap" or with another descriptive | ||
15 | word for the modifier other from "Fn". | ||
16 | |||
17 | Example: | ||
18 | linux,keymap = < 0x00030012 | ||
19 | 0x0102003a >; | ||
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt deleted file mode 100644 index 72683be6de3..00000000000 --- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | * Tegra keyboard controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "nvidia,tegra20-kbc" | ||
5 | |||
6 | Optional properties, in addition to those specified by the shared | ||
7 | matrix-keyboard bindings: | ||
8 | |||
9 | - linux,fn-keymap: a second keymap, same specification as the | ||
10 | matrix-keyboard-controller spec but to be used when the KEY_FN modifier | ||
11 | key is pressed. | ||
12 | - nvidia,debounce-delay-ms: delay in milliseconds per row scan for debouncing | ||
13 | - nvidia,repeat-delay-ms: delay in milliseconds before repeat starts | ||
14 | - nvidia,ghost-filter: enable ghost filtering for this device | ||
15 | - nvidia,wakeup-source: configure keyboard as a wakeup source for suspend/resume | ||
16 | |||
17 | Example: | ||
18 | |||
19 | keyboard: keyboard { | ||
20 | compatible = "nvidia,tegra20-kbc"; | ||
21 | reg = <0x7000e200 0x100>; | ||
22 | nvidia,ghost-filter; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/omap-keypad.txt b/Documentation/devicetree/bindings/input/omap-keypad.txt deleted file mode 100644 index f2fa5e10493..00000000000 --- a/Documentation/devicetree/bindings/input/omap-keypad.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | * TI's Keypad Controller device tree bindings | ||
2 | |||
3 | TI's Keypad controller is used to interface a SoC with a matrix-type | ||
4 | keypad device. The keypad controller supports multiple row and column lines. | ||
5 | A key can be placed at each intersection of a unique row and a unique column. | ||
6 | The keypad controller can sense a key-press and key-release and report the | ||
7 | event using a interrupt to the cpu. | ||
8 | |||
9 | Required SoC Specific Properties: | ||
10 | - compatible: should be one of the following | ||
11 | - "ti,omap4-keypad": For controllers compatible with omap4 keypad | ||
12 | controller. | ||
13 | |||
14 | Required Board Specific Properties, in addition to those specified by | ||
15 | the shared matrix-keyboard bindings: | ||
16 | - keypad,num-rows: Number of row lines connected to the keypad | ||
17 | controller. | ||
18 | |||
19 | - keypad,num-columns: Number of column lines connected to the | ||
20 | keypad controller. | ||
21 | |||
22 | Optional Properties specific to linux: | ||
23 | - linux,keypad-no-autorepeat: do no enable autorepeat feature. | ||
24 | |||
25 | Example: | ||
26 | keypad@4ae1c000{ | ||
27 | compatible = "ti,omap4-keypad"; | ||
28 | keypad,num-rows = <2>; | ||
29 | keypad,num-columns = <8>; | ||
30 | linux,keypad-no-autorepeat; | ||
31 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/pwm-beeper.txt b/Documentation/devicetree/bindings/input/pwm-beeper.txt deleted file mode 100644 index be332ae4f2d..00000000000 --- a/Documentation/devicetree/bindings/input/pwm-beeper.txt +++ /dev/null | |||
@@ -1,7 +0,0 @@ | |||
1 | * PWM beeper device tree bindings | ||
2 | |||
3 | Registers a PWM device as beeper. | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: should be "pwm-beeper" | ||
7 | - pwms: phandle to the physical PWM device | ||
diff --git a/Documentation/devicetree/bindings/input/rotary-encoder.txt b/Documentation/devicetree/bindings/input/rotary-encoder.txt deleted file mode 100644 index 331549593ed..00000000000 --- a/Documentation/devicetree/bindings/input/rotary-encoder.txt +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | Rotary encoder DT bindings | ||
2 | |||
3 | Required properties: | ||
4 | - gpios: a spec for two GPIOs to be used | ||
5 | |||
6 | Optional properties: | ||
7 | - linux,axis: the input subsystem axis to map to this rotary encoder. | ||
8 | Defaults to 0 (ABS_X / REL_X) | ||
9 | - rotary-encoder,steps: Number of steps in a full turnaround of the | ||
10 | encoder. Only relevant for absolute axis. Defaults to 24 which is a | ||
11 | typical value for such devices. | ||
12 | - rotary-encoder,relative-axis: register a relative axis rather than an | ||
13 | absolute one. Relative axis will only generate +1/-1 events on the input | ||
14 | device, hence no steps need to be passed. | ||
15 | - rotary-encoder,rollover: Automatic rollove when the rotary value becomes | ||
16 | greater than the specified steps or smaller than 0. For absolute axis only. | ||
17 | - rotary-encoder,half-period: Makes the driver work on half-period mode. | ||
18 | |||
19 | See Documentation/input/rotary-encoder.txt for more information. | ||
20 | |||
21 | Example: | ||
22 | |||
23 | rotary@0 { | ||
24 | compatible = "rotary-encoder"; | ||
25 | gpios = <&gpio 19 1>, <&gpio 20 0>; /* GPIO19 is inverted */ | ||
26 | linux,axis = <0>; /* REL_X */ | ||
27 | rotary-encoder,relative-axis; | ||
28 | }; | ||
29 | |||
30 | rotary@1 { | ||
31 | compatible = "rotary-encoder"; | ||
32 | gpios = <&gpio 21 0>, <&gpio 22 0>; | ||
33 | linux,axis = <1>; /* ABS_Y */ | ||
34 | rotary-encoder,steps = <24>; | ||
35 | rotary-encoder,rollover; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/samsung-keypad.txt b/Documentation/devicetree/bindings/input/samsung-keypad.txt deleted file mode 100644 index ce3e394c0e6..00000000000 --- a/Documentation/devicetree/bindings/input/samsung-keypad.txt +++ /dev/null | |||
@@ -1,88 +0,0 @@ | |||
1 | * Samsung's Keypad Controller device tree bindings | ||
2 | |||
3 | Samsung's Keypad controller is used to interface a SoC with a matrix-type | ||
4 | keypad device. The keypad controller supports multiple row and column lines. | ||
5 | A key can be placed at each intersection of a unique row and a unique column. | ||
6 | The keypad controller can sense a key-press and key-release and report the | ||
7 | event using a interrupt to the cpu. | ||
8 | |||
9 | Required SoC Specific Properties: | ||
10 | - compatible: should be one of the following | ||
11 | - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad | ||
12 | controller. | ||
13 | - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad | ||
14 | controller. | ||
15 | |||
16 | - reg: physical base address of the controller and length of memory mapped | ||
17 | region. | ||
18 | |||
19 | - interrupts: The interrupt number to the cpu. | ||
20 | |||
21 | Required Board Specific Properties: | ||
22 | - samsung,keypad-num-rows: Number of row lines connected to the keypad | ||
23 | controller. | ||
24 | |||
25 | - samsung,keypad-num-columns: Number of column lines connected to the | ||
26 | keypad controller. | ||
27 | |||
28 | - row-gpios: List of gpios used as row lines. The gpio specifier for | ||
29 | this property depends on the gpio controller to which these row lines | ||
30 | are connected. | ||
31 | |||
32 | - col-gpios: List of gpios used as column lines. The gpio specifier for | ||
33 | this property depends on the gpio controller to which these column | ||
34 | lines are connected. | ||
35 | |||
36 | - Keys represented as child nodes: Each key connected to the keypad | ||
37 | controller is represented as a child node to the keypad controller | ||
38 | device node and should include the following properties. | ||
39 | - keypad,row: the row number to which the key is connected. | ||
40 | - keypad,column: the column number to which the key is connected. | ||
41 | - linux,code: the key-code to be reported when the key is pressed | ||
42 | and released. | ||
43 | |||
44 | Optional Properties specific to linux: | ||
45 | - linux,keypad-no-autorepeat: do no enable autorepeat feature. | ||
46 | - linux,keypad-wakeup: use any event on keypad as wakeup event. | ||
47 | |||
48 | |||
49 | Example: | ||
50 | keypad@100A0000 { | ||
51 | compatible = "samsung,s5pv210-keypad"; | ||
52 | reg = <0x100A0000 0x100>; | ||
53 | interrupts = <173>; | ||
54 | samsung,keypad-num-rows = <2>; | ||
55 | samsung,keypad-num-columns = <8>; | ||
56 | linux,input-no-autorepeat; | ||
57 | linux,input-wakeup; | ||
58 | |||
59 | row-gpios = <&gpx2 0 3 3 0 | ||
60 | &gpx2 1 3 3 0>; | ||
61 | |||
62 | col-gpios = <&gpx1 0 3 0 0 | ||
63 | &gpx1 1 3 0 0 | ||
64 | &gpx1 2 3 0 0 | ||
65 | &gpx1 3 3 0 0 | ||
66 | &gpx1 4 3 0 0 | ||
67 | &gpx1 5 3 0 0 | ||
68 | &gpx1 6 3 0 0 | ||
69 | &gpx1 7 3 0 0>; | ||
70 | |||
71 | key_1 { | ||
72 | keypad,row = <0>; | ||
73 | keypad,column = <3>; | ||
74 | linux,code = <2>; | ||
75 | }; | ||
76 | |||
77 | key_2 { | ||
78 | keypad,row = <0>; | ||
79 | keypad,column = <4>; | ||
80 | linux,code = <3>; | ||
81 | }; | ||
82 | |||
83 | key_3 { | ||
84 | keypad,row = <0>; | ||
85 | keypad,column = <5>; | ||
86 | linux,code = <4>; | ||
87 | }; | ||
88 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/spear-keyboard.txt b/Documentation/devicetree/bindings/input/spear-keyboard.txt deleted file mode 100644 index 4a846d26da2..00000000000 --- a/Documentation/devicetree/bindings/input/spear-keyboard.txt +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | * SPEAr keyboard controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "st,spear300-kbd" | ||
5 | |||
6 | Optional properties, in addition to those specified by the shared | ||
7 | matrix-keyboard bindings: | ||
8 | - autorepeat: bool: enables key autorepeat | ||
9 | - st,mode: keyboard mode: 0 - 9x9, 1 - 6x6, 2 - 2x2 | ||
10 | |||
11 | Example: | ||
12 | |||
13 | kbd@fc400000 { | ||
14 | compatible = "st,spear300-kbd"; | ||
15 | reg = <0xfc400000 0x100>; | ||
16 | linux,keymap = < 0x00030012 | ||
17 | 0x0102003a >; | ||
18 | autorepeat; | ||
19 | st,mode = <0>; | ||
20 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/stmpe-keypad.txt b/Documentation/devicetree/bindings/input/stmpe-keypad.txt deleted file mode 100644 index 1b97222e8a0..00000000000 --- a/Documentation/devicetree/bindings/input/stmpe-keypad.txt +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | * STMPE Keypad | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "st,stmpe-keypad" | ||
5 | - linux,keymap : See ./matrix-keymap.txt | ||
6 | |||
7 | Optional properties: | ||
8 | - debounce-interval : Debouncing interval time in milliseconds | ||
9 | - st,scan-count : Scanning cycles elapsed before key data is updated | ||
10 | - st,no-autorepeat : If specified device will not autorepeat | ||
11 | |||
12 | Example: | ||
13 | |||
14 | stmpe_keypad { | ||
15 | compatible = "st,stmpe-keypad"; | ||
16 | |||
17 | debounce-interval = <64>; | ||
18 | st,scan-count = <8>; | ||
19 | st,no-autorepeat; | ||
20 | |||
21 | linux,keymap = <0x205006b | ||
22 | 0x4010074 | ||
23 | 0x3050072 | ||
24 | 0x1030004 | ||
25 | 0x502006a | ||
26 | 0x500000a | ||
27 | 0x5008b | ||
28 | 0x706001c | ||
29 | 0x405000b | ||
30 | 0x6070003 | ||
31 | 0x3040067 | ||
32 | 0x303006c | ||
33 | 0x60400e7 | ||
34 | 0x602009e | ||
35 | 0x4020073 | ||
36 | 0x5050002 | ||
37 | 0x4030069 | ||
38 | 0x3020008>; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/tca8418_keypad.txt b/Documentation/devicetree/bindings/input/tca8418_keypad.txt deleted file mode 100644 index 2a1538f0053..00000000000 --- a/Documentation/devicetree/bindings/input/tca8418_keypad.txt +++ /dev/null | |||
@@ -1,8 +0,0 @@ | |||
1 | |||
2 | Required properties: | ||
3 | - compatible: "ti,tca8418" | ||
4 | - reg: the I2C address | ||
5 | - interrupts: IRQ line number, should trigger on falling edge | ||
6 | - keypad,num-rows: The number of rows | ||
7 | - keypad,num-columns: The number of columns | ||
8 | - linux,keymap: Keys definitions, see keypad-matrix. | ||
diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt deleted file mode 100644 index ca5a2c86480..00000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | * Rohm BU21013 Touch Screen | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "rohm,bu21013_tp" | ||
5 | - reg : I2C device address | ||
6 | |||
7 | Optional properties: | ||
8 | - touch-gpio : GPIO pin registering a touch event | ||
9 | - <supply_name>-supply : Phandle to a regulator supply | ||
10 | - rohm,touch-max-x : Maximum outward permitted limit in the X axis | ||
11 | - rohm,touch-max-y : Maximum outward permitted limit in the Y axis | ||
12 | - rohm,flip-x : Flip touch coordinates on the X axis | ||
13 | - rohm,flip-y : Flip touch coordinates on the Y axis | ||
14 | |||
15 | Example: | ||
16 | |||
17 | i2c@80110000 { | ||
18 | bu21013_tp@0x5c { | ||
19 | compatible = "rohm,bu21013_tp"; | ||
20 | reg = <0x5c>; | ||
21 | touch-gpio = <&gpio2 20 0x4>; | ||
22 | avdd-supply = <&ab8500_ldo_aux1_reg>; | ||
23 | |||
24 | rohm,touch-max-x = <384>; | ||
25 | rohm,touch-max-y = <704>; | ||
26 | rohm,flip-y; | ||
27 | }; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt deleted file mode 100644 index df70318a617..00000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | * EETI eGalax Multiple Touch Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "eeti,egalax_ts" | ||
5 | - reg: i2c slave address | ||
6 | - interrupt-parent: the phandle for the interrupt controller | ||
7 | - interrupts: touch controller interrupt | ||
8 | - wakeup-gpios: the gpio pin to be used for waking up the controller | ||
9 | as well as uased as irq pin | ||
10 | |||
11 | Example: | ||
12 | |||
13 | egalax_ts@04 { | ||
14 | compatible = "eeti,egalax_ts"; | ||
15 | reg = <0x04>; | ||
16 | interrupt-parent = <&gpio1>; | ||
17 | interrupts = <9 2>; | ||
18 | wakeup-gpios = <&gpio1 9 0>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt b/Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt deleted file mode 100644 index 41cbf4b7a67..00000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/lpc32xx-tsc.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | * NXP LPC32xx SoC Touchscreen Controller (TSC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "nxp,lpc3220-tsc" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: The TSC/ADC interrupt | ||
8 | |||
9 | Example: | ||
10 | |||
11 | tsc@40048000 { | ||
12 | compatible = "nxp,lpc3220-tsc"; | ||
13 | reg = <0x40048000 0x1000>; | ||
14 | interrupt-parent = <&mic>; | ||
15 | interrupts = <39 0>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/touchscreen/mms114.txt b/Documentation/devicetree/bindings/input/touchscreen/mms114.txt deleted file mode 100644 index 89d4c56c567..00000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/mms114.txt +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | * MELFAS MMS114 touchscreen controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "melfas,mms114" | ||
5 | - reg: I2C address of the chip | ||
6 | - interrupts: interrupt to which the chip is connected | ||
7 | - x-size: horizontal resolution of touchscreen | ||
8 | - y-size: vertical resolution of touchscreen | ||
9 | |||
10 | Optional properties: | ||
11 | - contact-threshold: | ||
12 | - moving-threshold: | ||
13 | - x-invert: invert X axis | ||
14 | - y-invert: invert Y axis | ||
15 | |||
16 | Example: | ||
17 | |||
18 | i2c@00000000 { | ||
19 | /* ... */ | ||
20 | |||
21 | touchscreen@48 { | ||
22 | compatible = "melfas,mms114"; | ||
23 | reg = <0x48>; | ||
24 | interrupts = <39 0>; | ||
25 | x-size = <720>; | ||
26 | y-size = <1280>; | ||
27 | contact-threshold = <10>; | ||
28 | moving-threshold = <10>; | ||
29 | x-invert; | ||
30 | y-invert; | ||
31 | }; | ||
32 | |||
33 | /* ... */ | ||
34 | }; | ||
diff --git a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt deleted file mode 100644 index 127baa31a77..00000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt +++ /dev/null | |||
@@ -1,43 +0,0 @@ | |||
1 | STMPE Touchscreen | ||
2 | ---------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible: "st,stmpe-ts" | ||
6 | |||
7 | Optional properties: | ||
8 | - st,sample-time: ADC converstion time in number of clock. (0 -> 36 clocks, 1 -> | ||
9 | 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, 4 -> 80 clocks, 5 -> 96 clocks, 6 | ||
10 | -> 144 clocks), recommended is 4. | ||
11 | - st,mod-12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC) | ||
12 | - st,ref-sel: ADC reference source (0 -> internal reference, 1 -> external | ||
13 | reference) | ||
14 | - st,adc-freq: ADC Clock speed (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz) | ||
15 | - st,ave-ctrl: Sample average control (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 | ||
16 | samples, 3 -> 8 samples) | ||
17 | - st,touch-det-delay: Touch detect interrupt delay (0 -> 10 us, 1 -> 50 us, 2 -> | ||
18 | 100 us, 3 -> 500 us, 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms) recommended | ||
19 | is 3 | ||
20 | - st,settling: Panel driver settling time (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3 | ||
21 | -> 1 ms, 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms) recommended is 2 | ||
22 | - st,fraction-z: Length of the fractional part in z (fraction-z ([0..7]) = Count of | ||
23 | the fractional part) recommended is 7 | ||
24 | - st,i-drive: current limit value of the touchscreen drivers (0 -> 20 mA typical 35 | ||
25 | mA max, 1 -> 50 mA typical 80 mA max) | ||
26 | |||
27 | Node name must be stmpe_touchscreen and should be child node of stmpe node to | ||
28 | which it belongs. | ||
29 | |||
30 | Example: | ||
31 | |||
32 | stmpe_touchscreen { | ||
33 | compatible = "st,stmpe-ts"; | ||
34 | st,sample-time = <4>; | ||
35 | st,mod-12b = <1>; | ||
36 | st,ref-sel = <0>; | ||
37 | st,adc-freq = <1>; | ||
38 | st,ave-ctrl = <1>; | ||
39 | st,touch-det-delay = <2>; | ||
40 | st,settling = <2>; | ||
41 | st,fraction-z = <7>; | ||
42 | st,i-drive = <1>; | ||
43 | }; | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt deleted file mode 100644 index 7f9fb85f545..00000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt +++ /dev/null | |||
@@ -1,104 +0,0 @@ | |||
1 | Allwinner Sunxi Interrupt Controller | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "allwinner,sunxi-ic" | ||
6 | - reg : Specifies base physical address and size of the registers. | ||
7 | - interrupt-controller : Identifies the node as an interrupt controller | ||
8 | - #interrupt-cells : Specifies the number of cells needed to encode an | ||
9 | interrupt source. The value shall be 1. | ||
10 | |||
11 | The interrupt sources are as follows: | ||
12 | |||
13 | 0: ENMI | ||
14 | 1: UART0 | ||
15 | 2: UART1 | ||
16 | 3: UART2 | ||
17 | 4: UART3 | ||
18 | 5: IR0 | ||
19 | 6: IR1 | ||
20 | 7: I2C0 | ||
21 | 8: I2C1 | ||
22 | 9: I2C2 | ||
23 | 10: SPI0 | ||
24 | 11: SPI1 | ||
25 | 12: SPI2 | ||
26 | 13: SPDIF | ||
27 | 14: AC97 | ||
28 | 15: TS | ||
29 | 16: I2S | ||
30 | 17: UART4 | ||
31 | 18: UART5 | ||
32 | 19: UART6 | ||
33 | 20: UART7 | ||
34 | 21: KEYPAD | ||
35 | 22: TIMER0 | ||
36 | 23: TIMER1 | ||
37 | 24: TIMER2 | ||
38 | 25: TIMER3 | ||
39 | 26: CAN | ||
40 | 27: DMA | ||
41 | 28: PIO | ||
42 | 29: TOUCH_PANEL | ||
43 | 30: AUDIO_CODEC | ||
44 | 31: LRADC | ||
45 | 32: SDMC0 | ||
46 | 33: SDMC1 | ||
47 | 34: SDMC2 | ||
48 | 35: SDMC3 | ||
49 | 36: MEMSTICK | ||
50 | 37: NAND | ||
51 | 38: USB0 | ||
52 | 39: USB1 | ||
53 | 40: USB2 | ||
54 | 41: SCR | ||
55 | 42: CSI0 | ||
56 | 43: CSI1 | ||
57 | 44: LCDCTRL0 | ||
58 | 45: LCDCTRL1 | ||
59 | 46: MP | ||
60 | 47: DEFEBE0 | ||
61 | 48: DEFEBE1 | ||
62 | 49: PMU | ||
63 | 50: SPI3 | ||
64 | 51: TZASC | ||
65 | 52: PATA | ||
66 | 53: VE | ||
67 | 54: SS | ||
68 | 55: EMAC | ||
69 | 56: SATA | ||
70 | 57: GPS | ||
71 | 58: HDMI | ||
72 | 59: TVE | ||
73 | 60: ACE | ||
74 | 61: TVD | ||
75 | 62: PS2_0 | ||
76 | 63: PS2_1 | ||
77 | 64: USB3 | ||
78 | 65: USB4 | ||
79 | 66: PLE_PFM | ||
80 | 67: TIMER4 | ||
81 | 68: TIMER5 | ||
82 | 69: GPU_GP | ||
83 | 70: GPU_GPMMU | ||
84 | 71: GPU_PP0 | ||
85 | 72: GPU_PPMMU0 | ||
86 | 73: GPU_PMU | ||
87 | 74: GPU_RSV0 | ||
88 | 75: GPU_RSV1 | ||
89 | 76: GPU_RSV2 | ||
90 | 77: GPU_RSV3 | ||
91 | 78: GPU_RSV4 | ||
92 | 79: GPU_RSV5 | ||
93 | 80: GPU_RSV6 | ||
94 | 82: SYNC_TIMER0 | ||
95 | 83: SYNC_TIMER1 | ||
96 | |||
97 | Example: | ||
98 | |||
99 | intc: interrupt-controller { | ||
100 | compatible = "allwinner,sunxi-ic"; | ||
101 | reg = <0x01c20400 0x400>; | ||
102 | interrupt-controller; | ||
103 | #interrupt-cells = <2>; | ||
104 | }; | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt deleted file mode 100644 index 7da578d7212..00000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt +++ /dev/null | |||
@@ -1,110 +0,0 @@ | |||
1 | BCM2835 Top-Level ("ARMCTRL") Interrupt Controller | ||
2 | |||
3 | The BCM2835 contains a custom top-level interrupt controller, which supports | ||
4 | 72 interrupt sources using a 2-level register scheme. The interrupt | ||
5 | controller, or the HW block containing it, is referred to occasionally | ||
6 | as "armctrl" in the SoC documentation, hence naming of this binding. | ||
7 | |||
8 | Required properties: | ||
9 | |||
10 | - compatible : should be "brcm,bcm2835-armctrl-ic" | ||
11 | - reg : Specifies base physical address and size of the registers. | ||
12 | - interrupt-controller : Identifies the node as an interrupt controller | ||
13 | - #interrupt-cells : Specifies the number of cells needed to encode an | ||
14 | interrupt source. The value shall be 2. | ||
15 | |||
16 | The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic | ||
17 | pending" register, or 1/2 respectively for interrupts in the "IRQ pending | ||
18 | 1/2" register. | ||
19 | |||
20 | The 2nd cell contains the interrupt number within the bank. Valid values | ||
21 | are 0..7 for bank 0, and 0..31 for bank 1. | ||
22 | |||
23 | The interrupt sources are as follows: | ||
24 | |||
25 | Bank 0: | ||
26 | 0: ARM_TIMER | ||
27 | 1: ARM_MAILBOX | ||
28 | 2: ARM_DOORBELL_0 | ||
29 | 3: ARM_DOORBELL_1 | ||
30 | 4: VPU0_HALTED | ||
31 | 5: VPU1_HALTED | ||
32 | 6: ILLEGAL_TYPE0 | ||
33 | 7: ILLEGAL_TYPE1 | ||
34 | |||
35 | Bank 1: | ||
36 | 0: TIMER0 | ||
37 | 1: TIMER1 | ||
38 | 2: TIMER2 | ||
39 | 3: TIMER3 | ||
40 | 4: CODEC0 | ||
41 | 5: CODEC1 | ||
42 | 6: CODEC2 | ||
43 | 7: VC_JPEG | ||
44 | 8: ISP | ||
45 | 9: VC_USB | ||
46 | 10: VC_3D | ||
47 | 11: TRANSPOSER | ||
48 | 12: MULTICORESYNC0 | ||
49 | 13: MULTICORESYNC1 | ||
50 | 14: MULTICORESYNC2 | ||
51 | 15: MULTICORESYNC3 | ||
52 | 16: DMA0 | ||
53 | 17: DMA1 | ||
54 | 18: VC_DMA2 | ||
55 | 19: VC_DMA3 | ||
56 | 20: DMA4 | ||
57 | 21: DMA5 | ||
58 | 22: DMA6 | ||
59 | 23: DMA7 | ||
60 | 24: DMA8 | ||
61 | 25: DMA9 | ||
62 | 26: DMA10 | ||
63 | 27: DMA11 | ||
64 | 28: DMA12 | ||
65 | 29: AUX | ||
66 | 30: ARM | ||
67 | 31: VPUDMA | ||
68 | |||
69 | Bank 2: | ||
70 | 0: HOSTPORT | ||
71 | 1: VIDEOSCALER | ||
72 | 2: CCP2TX | ||
73 | 3: SDC | ||
74 | 4: DSI0 | ||
75 | 5: AVE | ||
76 | 6: CAM0 | ||
77 | 7: CAM1 | ||
78 | 8: HDMI0 | ||
79 | 9: HDMI1 | ||
80 | 10: PIXELVALVE1 | ||
81 | 11: I2CSPISLV | ||
82 | 12: DSI1 | ||
83 | 13: PWA0 | ||
84 | 14: PWA1 | ||
85 | 15: CPR | ||
86 | 16: SMI | ||
87 | 17: GPIO0 | ||
88 | 18: GPIO1 | ||
89 | 19: GPIO2 | ||
90 | 20: GPIO3 | ||
91 | 21: VC_I2C | ||
92 | 22: VC_SPI | ||
93 | 23: VC_I2SPCM | ||
94 | 24: VC_SDIO | ||
95 | 25: VC_UART | ||
96 | 26: SLIMBUS | ||
97 | 27: VEC | ||
98 | 28: CPG | ||
99 | 29: RNG | ||
100 | 30: VC_ARASANSDIO | ||
101 | 31: AVSPMON | ||
102 | |||
103 | Example: | ||
104 | |||
105 | intc: interrupt-controller { | ||
106 | compatible = "brcm,bcm2835-armctrl-ic"; | ||
107 | reg = <0x7e00b200 0x200>; | ||
108 | interrupt-controller; | ||
109 | #interrupt-cells = <2>; | ||
110 | }; | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt deleted file mode 100644 index 72a06c0ab1d..00000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +++ /dev/null | |||
@@ -1,95 +0,0 @@ | |||
1 | Specifying interrupt information for devices | ||
2 | ============================================ | ||
3 | |||
4 | 1) Interrupt client nodes | ||
5 | ------------------------- | ||
6 | |||
7 | Nodes that describe devices which generate interrupts must contain an | ||
8 | "interrupts" property. This property must contain a list of interrupt | ||
9 | specifiers, one per output interrupt. The format of the interrupt specifier is | ||
10 | determined by the interrupt controller to which the interrupts are routed; see | ||
11 | section 2 below for details. | ||
12 | |||
13 | The "interrupt-parent" property is used to specify the controller to which | ||
14 | interrupts are routed and contains a single phandle referring to the interrupt | ||
15 | controller node. This property is inherited, so it may be specified in an | ||
16 | interrupt client node or in any of its parent nodes. | ||
17 | |||
18 | 2) Interrupt controller nodes | ||
19 | ----------------------------- | ||
20 | |||
21 | A device is marked as an interrupt controller with the "interrupt-controller" | ||
22 | property. This is a empty, boolean property. An additional "#interrupt-cells" | ||
23 | property defines the number of cells needed to specify a single interrupt. | ||
24 | |||
25 | It is the responsibility of the interrupt controller's binding to define the | ||
26 | length and format of the interrupt specifier. The following two variants are | ||
27 | commonly used: | ||
28 | |||
29 | a) one cell | ||
30 | ----------- | ||
31 | The #interrupt-cells property is set to 1 and the single cell defines the | ||
32 | index of the interrupt within the controller. | ||
33 | |||
34 | Example: | ||
35 | |||
36 | vic: intc@10140000 { | ||
37 | compatible = "arm,versatile-vic"; | ||
38 | interrupt-controller; | ||
39 | #interrupt-cells = <1>; | ||
40 | reg = <0x10140000 0x1000>; | ||
41 | }; | ||
42 | |||
43 | sic: intc@10003000 { | ||
44 | compatible = "arm,versatile-sic"; | ||
45 | interrupt-controller; | ||
46 | #interrupt-cells = <1>; | ||
47 | reg = <0x10003000 0x1000>; | ||
48 | interrupt-parent = <&vic>; | ||
49 | interrupts = <31>; /* Cascaded to vic */ | ||
50 | }; | ||
51 | |||
52 | b) two cells | ||
53 | ------------ | ||
54 | The #interrupt-cells property is set to 2 and the first cell defines the | ||
55 | index of the interrupt within the controller, while the second cell is used | ||
56 | to specify any of the following flags: | ||
57 | - bits[3:0] trigger type and level flags | ||
58 | 1 = low-to-high edge triggered | ||
59 | 2 = high-to-low edge triggered | ||
60 | 4 = active high level-sensitive | ||
61 | 8 = active low level-sensitive | ||
62 | |||
63 | Example: | ||
64 | |||
65 | i2c@7000c000 { | ||
66 | gpioext: gpio-adnp@41 { | ||
67 | compatible = "ad,gpio-adnp"; | ||
68 | reg = <0x41>; | ||
69 | |||
70 | interrupt-parent = <&gpio>; | ||
71 | interrupts = <160 1>; | ||
72 | |||
73 | gpio-controller; | ||
74 | #gpio-cells = <1>; | ||
75 | |||
76 | interrupt-controller; | ||
77 | #interrupt-cells = <2>; | ||
78 | |||
79 | nr-gpios = <64>; | ||
80 | }; | ||
81 | |||
82 | sx8634@2b { | ||
83 | compatible = "smtc,sx8634"; | ||
84 | reg = <0x2b>; | ||
85 | |||
86 | interrupt-parent = <&gpioext>; | ||
87 | interrupts = <3 0x8>; | ||
88 | |||
89 | #address-cells = <1>; | ||
90 | #size-cells = <0>; | ||
91 | |||
92 | threshold = <0x40>; | ||
93 | sensitivity = <7>; | ||
94 | }; | ||
95 | }; | ||
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt deleted file mode 100644 index 099d9362ebc..00000000000 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | NVIDIA Tegra 20 GART | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "nvidia,tegra20-gart" | ||
5 | - reg: Two pairs of cells specifying the physical address and size of | ||
6 | the memory controller registers and the GART aperture respectively. | ||
7 | |||
8 | Example: | ||
9 | |||
10 | gart { | ||
11 | compatible = "nvidia,tegra20-gart"; | ||
12 | reg = <0x7000f024 0x00000018 /* controller registers */ | ||
13 | 0x58000000 0x02000000>; /* GART aperture */ | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt deleted file mode 100644 index 89fb5434b73..00000000000 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra30-smmu" | ||
5 | - reg : Should contain 3 register banks(address and length) for each | ||
6 | of the SMMU register blocks. | ||
7 | - interrupts : Should contain MC General interrupt. | ||
8 | - nvidia,#asids : # of ASIDs | ||
9 | - dma-window : IOVA start address and length. | ||
10 | - nvidia,ahb : phandle to the ahb bus connected to SMMU. | ||
11 | |||
12 | Example: | ||
13 | smmu { | ||
14 | compatible = "nvidia,tegra30-smmu"; | ||
15 | reg = <0x7000f010 0x02c | ||
16 | 0x7000f1f0 0x010 | ||
17 | 0x7000f228 0x05c>; | ||
18 | nvidia,#asids = <4>; /* # of ASIDs */ | ||
19 | dma-window = <0 0x40000000>; /* IOVA start & length */ | ||
20 | nvidia,ahb = <&ahb>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt deleted file mode 100644 index 2d88816dd55..00000000000 --- a/Documentation/devicetree/bindings/leds/common.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | Common leds properties. | ||
2 | |||
3 | Optional properties for child nodes: | ||
4 | - label : The label for this LED. If omitted, the label is | ||
5 | taken from the node name (excluding the unit address). | ||
6 | |||
7 | - linux,default-trigger : This parameter, if present, is a | ||
8 | string defining the trigger assigned to the LED. Current triggers are: | ||
9 | "backlight" - LED will act as a back-light, controlled by the framebuffer | ||
10 | system | ||
11 | "default-on" - LED will turn on (but for leds-gpio see "default-state" | ||
12 | property in Documentation/devicetree/bindings/gpio/led.txt) | ||
13 | "heartbeat" - LED "double" flashes at a load average based rate | ||
14 | "ide-disk" - LED indicates disk activity | ||
15 | "timer" - LED flashes at a fixed, configurable rate | ||
16 | |||
17 | Examples: | ||
18 | |||
19 | system-status { | ||
20 | label = "Status"; | ||
21 | linux,default-trigger = "heartbeat"; | ||
22 | ... | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/leds/leds-gpio.txt b/Documentation/devicetree/bindings/leds/leds-gpio.txt deleted file mode 100644 index df1b3080f6b..00000000000 --- a/Documentation/devicetree/bindings/leds/leds-gpio.txt +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | LEDs connected to GPIO lines | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "gpio-leds". | ||
5 | |||
6 | Each LED is represented as a sub-node of the gpio-leds device. Each | ||
7 | node's name represents the name of the corresponding LED. | ||
8 | |||
9 | LED sub-node properties: | ||
10 | - gpios : Should specify the LED's GPIO, see "gpios property" in | ||
11 | Documentation/devicetree/bindings/gpio/gpio.txt. Active low LEDs should be | ||
12 | indicated using flags in the GPIO specifier. | ||
13 | - label : (optional) | ||
14 | see Documentation/devicetree/bindings/leds/common.txt | ||
15 | - linux,default-trigger : (optional) | ||
16 | see Documentation/devicetree/bindings/leds/common.txt | ||
17 | - default-state: (optional) The initial state of the LED. Valid | ||
18 | values are "on", "off", and "keep". If the LED is already on or off | ||
19 | and the default-state property is set the to same value, then no | ||
20 | glitch should be produced where the LED momentarily turns off (or | ||
21 | on). The "keep" setting will keep the LED at whatever its current | ||
22 | state is, without producing a glitch. The default is off if this | ||
23 | property is not present. | ||
24 | |||
25 | Examples: | ||
26 | |||
27 | leds { | ||
28 | compatible = "gpio-leds"; | ||
29 | hdd { | ||
30 | label = "IDE Activity"; | ||
31 | gpios = <&mcu_pio 0 1>; /* Active low */ | ||
32 | linux,default-trigger = "ide-disk"; | ||
33 | }; | ||
34 | |||
35 | fault { | ||
36 | gpios = <&mcu_pio 1 0>; | ||
37 | /* Keep LED on if BIOS detected hardware fault */ | ||
38 | default-state = "keep"; | ||
39 | }; | ||
40 | }; | ||
41 | |||
42 | run-control { | ||
43 | compatible = "gpio-leds"; | ||
44 | red { | ||
45 | gpios = <&mpc8572 6 0>; | ||
46 | default-state = "off"; | ||
47 | }; | ||
48 | green { | ||
49 | gpios = <&mpc8572 7 0>; | ||
50 | default-state = "on"; | ||
51 | }; | ||
52 | }; | ||
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt deleted file mode 100644 index 9ceb19e0c7f..00000000000 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "jedec,lpddr2-timings" | ||
5 | - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32> | ||
6 | - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32> | ||
7 | |||
8 | Optional properties: | ||
9 | |||
10 | The following properties represent AC timing parameters from the memory | ||
11 | data-sheet of the device for a given speed-bin. All these properties are | ||
12 | of type <u32> and the default unit is ps (pico seconds). Parameters with | ||
13 | a different unit have a suffix indicating the unit such as 'tRAS-max-ns' | ||
14 | - tRCD | ||
15 | - tWR | ||
16 | - tRAS-min | ||
17 | - tRRD | ||
18 | - tWTR | ||
19 | - tXP | ||
20 | - tRTP | ||
21 | - tDQSCK-max | ||
22 | - tFAW | ||
23 | - tZQCS | ||
24 | - tZQinit | ||
25 | - tRPab | ||
26 | - tZQCL | ||
27 | - tCKESR | ||
28 | - tRAS-max-ns | ||
29 | - tDQSCK-max-derated | ||
30 | |||
31 | Example: | ||
32 | |||
33 | timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { | ||
34 | compatible = "jedec,lpddr2-timings"; | ||
35 | min-freq = <10000000>; | ||
36 | max-freq = <400000000>; | ||
37 | tRPab = <21000>; | ||
38 | tRCD = <18000>; | ||
39 | tWR = <15000>; | ||
40 | tRAS-min = <42000>; | ||
41 | tRRD = <10000>; | ||
42 | tWTR = <7500>; | ||
43 | tXP = <7500>; | ||
44 | tRTP = <7500>; | ||
45 | tCKESR = <15000>; | ||
46 | tDQSCK-max = <5500>; | ||
47 | tFAW = <50000>; | ||
48 | tZQCS = <90000>; | ||
49 | tZQCL = <360000>; | ||
50 | tZQinit = <1000000>; | ||
51 | tRAS-max-ns = <70000>; | ||
52 | }; | ||
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt deleted file mode 100644 index 58354a075e1..00000000000 --- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt +++ /dev/null | |||
@@ -1,102 +0,0 @@ | |||
1 | * LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", | ||
5 | "jedec,lpddr2-s4" | ||
6 | |||
7 | "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type | ||
8 | |||
9 | "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type | ||
10 | |||
11 | "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type | ||
12 | |||
13 | - density : <u32> representing density in Mb (Mega bits) | ||
14 | |||
15 | - io-width : <u32> representing bus width. Possible values are 8, 16, and 32 | ||
16 | |||
17 | Optional properties: | ||
18 | |||
19 | The following optional properties represent the minimum value of some AC | ||
20 | timing parameters of the DDR device in terms of number of clock cycles. | ||
21 | These values shall be obtained from the device data-sheet. | ||
22 | - tRRD-min-tck | ||
23 | - tWTR-min-tck | ||
24 | - tXP-min-tck | ||
25 | - tRTP-min-tck | ||
26 | - tCKE-min-tck | ||
27 | - tRPab-min-tck | ||
28 | - tRCD-min-tck | ||
29 | - tWR-min-tck | ||
30 | - tRASmin-min-tck | ||
31 | - tCKESR-min-tck | ||
32 | - tFAW-min-tck | ||
33 | |||
34 | Child nodes: | ||
35 | - The lpddr2 node may have one or more child nodes of type "lpddr2-timings". | ||
36 | "lpddr2-timings" provides AC timing parameters of the device for | ||
37 | a given speed-bin. The user may provide the timings for as many | ||
38 | speed-bins as is required. Please see Documentation/devicetree/ | ||
39 | bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" | ||
40 | |||
41 | Example: | ||
42 | |||
43 | elpida_ECB240ABACN : lpddr2 { | ||
44 | compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; | ||
45 | density = <2048>; | ||
46 | io-width = <32>; | ||
47 | |||
48 | tRPab-min-tck = <3>; | ||
49 | tRCD-min-tck = <3>; | ||
50 | tWR-min-tck = <3>; | ||
51 | tRASmin-min-tck = <3>; | ||
52 | tRRD-min-tck = <2>; | ||
53 | tWTR-min-tck = <2>; | ||
54 | tXP-min-tck = <2>; | ||
55 | tRTP-min-tck = <2>; | ||
56 | tCKE-min-tck = <3>; | ||
57 | tCKESR-min-tck = <3>; | ||
58 | tFAW-min-tck = <8>; | ||
59 | |||
60 | timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { | ||
61 | compatible = "jedec,lpddr2-timings"; | ||
62 | min-freq = <10000000>; | ||
63 | max-freq = <400000000>; | ||
64 | tRPab = <21000>; | ||
65 | tRCD = <18000>; | ||
66 | tWR = <15000>; | ||
67 | tRAS-min = <42000>; | ||
68 | tRRD = <10000>; | ||
69 | tWTR = <7500>; | ||
70 | tXP = <7500>; | ||
71 | tRTP = <7500>; | ||
72 | tCKESR = <15000>; | ||
73 | tDQSCK-max = <5500>; | ||
74 | tFAW = <50000>; | ||
75 | tZQCS = <90000>; | ||
76 | tZQCL = <360000>; | ||
77 | tZQinit = <1000000>; | ||
78 | tRAS-max-ns = <70000>; | ||
79 | }; | ||
80 | |||
81 | timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { | ||
82 | compatible = "jedec,lpddr2-timings"; | ||
83 | min-freq = <10000000>; | ||
84 | max-freq = <200000000>; | ||
85 | tRPab = <21000>; | ||
86 | tRCD = <18000>; | ||
87 | tWR = <15000>; | ||
88 | tRAS-min = <42000>; | ||
89 | tRRD = <10000>; | ||
90 | tWTR = <10000>; | ||
91 | tXP = <7500>; | ||
92 | tRTP = <7500>; | ||
93 | tCKESR = <15000>; | ||
94 | tDQSCK-max = <5500>; | ||
95 | tFAW = <50000>; | ||
96 | tZQCS = <90000>; | ||
97 | tZQCL = <360000>; | ||
98 | tZQinit = <1000000>; | ||
99 | tRAS-max-ns = <70000>; | ||
100 | }; | ||
101 | |||
102 | } | ||
diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt b/Documentation/devicetree/bindings/media/exynos5-gsc.txt deleted file mode 100644 index 0604d42f38d..00000000000 --- a/Documentation/devicetree/bindings/media/exynos5-gsc.txt +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | * Samsung Exynos5 G-Scaler device | ||
2 | |||
3 | G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs. | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: should be "samsung,exynos5-gsc" | ||
7 | - reg: should contain G-Scaler physical address location and length. | ||
8 | - interrupts: should contain G-Scaler interrupt number | ||
9 | |||
10 | Example: | ||
11 | |||
12 | gsc_0: gsc@0x13e00000 { | ||
13 | compatible = "samsung,exynos5-gsc"; | ||
14 | reg = <0x13e00000 0x1000>; | ||
15 | interrupts = <0 85 0>; | ||
16 | }; | ||
17 | |||
18 | Aliases: | ||
19 | Each G-Scaler node should have a numbered alias in the aliases node, | ||
20 | in the form of gscN, N = 0...3. G-Scaler driver uses these aliases | ||
21 | to retrieve the device IDs using "of_alias_get_id()" call. | ||
22 | |||
23 | Example: | ||
24 | |||
25 | aliases { | ||
26 | gsc0 =&gsc_0; | ||
27 | gsc1 =&gsc_1; | ||
28 | gsc2 =&gsc_2; | ||
29 | gsc3 =&gsc_3; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt deleted file mode 100644 index 67ec3d4ccc7..00000000000 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | * Samsung Multi Format Codec (MFC) | ||
2 | |||
3 | Multi Format Codec (MFC) is the IP present in Samsung SoCs which | ||
4 | supports high resolution decoding and encoding functionalities. | ||
5 | The MFC device driver is a v4l2 driver which can encode/decode | ||
6 | video raw/elementary streams and has support for all popular | ||
7 | video codecs. | ||
8 | |||
9 | Required properties: | ||
10 | - compatible : value should be either one among the following | ||
11 | (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs | ||
12 | (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs | ||
13 | |||
14 | - reg : Physical base address of the IP registers and length of memory | ||
15 | mapped region. | ||
16 | |||
17 | - interrupts : MFC interrupt number to the CPU. | ||
18 | |||
19 | - samsung,mfc-r : Base address of the first memory bank used by MFC | ||
20 | for DMA contiguous memory allocation and its size. | ||
21 | |||
22 | - samsung,mfc-l : Base address of the second memory bank used by MFC | ||
23 | for DMA contiguous memory allocation and its size. | ||
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt deleted file mode 100644 index 938f8e1ba20..00000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | * EMIF family of TI SDRAM controllers | ||
2 | |||
3 | EMIF - External Memory Interface - is an SDRAM controller used in | ||
4 | TI SoCs. EMIF supports, based on the IP revision, one or more of | ||
5 | DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance | ||
6 | of the EMIF IP and memory parts attached to it. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev> | ||
10 | is the IP revision of the specific EMIF instance. | ||
11 | |||
12 | - phy-type : <u32> indicating the DDR phy type. Following are the | ||
13 | allowed values | ||
14 | <1> : Attila PHY | ||
15 | <2> : Intelli PHY | ||
16 | |||
17 | - device-handle : phandle to a "lpddr2" node representing the memory part | ||
18 | |||
19 | - ti,hwmods : For TI hwmods processing and omap device creation | ||
20 | the value shall be "emif<n>" where <n> is the number of the EMIF | ||
21 | instance with base 1. | ||
22 | |||
23 | Optional properties: | ||
24 | - cs1-used : Have this property if CS1 of this EMIF | ||
25 | instance has a memory part attached to it. If there is a memory | ||
26 | part attached to CS1, it should be the same type as the one on CS0, | ||
27 | so there is no need to give the details of this memory part. | ||
28 | |||
29 | - cal-resistor-per-cs : Have this property if the board has one | ||
30 | calibration resistor per chip-select. | ||
31 | |||
32 | - hw-caps-read-idle-ctrl: Have this property if the controller | ||
33 | supports read idle window programming | ||
34 | |||
35 | - hw-caps-dll-calib-ctrl: Have this property if the controller | ||
36 | supports dll calibration control | ||
37 | |||
38 | - hw-caps-ll-interface : Have this property if the controller | ||
39 | has a low latency interface and corresponding interrupt events | ||
40 | |||
41 | - hw-caps-temp-alert : Have this property if the controller | ||
42 | has capability for generating SDRAM temperature alerts | ||
43 | |||
44 | Example: | ||
45 | |||
46 | emif1: emif@0x4c000000 { | ||
47 | compatible = "ti,emif-4d"; | ||
48 | ti,hwmods = "emif2"; | ||
49 | phy-type = <1>; | ||
50 | device-handle = <&elpida_ECB240ABACN>; | ||
51 | cs1-used; | ||
52 | hw-caps-read-idle-ctrl; | ||
53 | hw-caps-ll-interface; | ||
54 | hw-caps-temp-alert; | ||
55 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/88pm860x.txt b/Documentation/devicetree/bindings/mfd/88pm860x.txt deleted file mode 100644 index 63f3ee33759..00000000000 --- a/Documentation/devicetree/bindings/mfd/88pm860x.txt +++ /dev/null | |||
@@ -1,85 +0,0 @@ | |||
1 | * Marvell 88PM860x Power Management IC | ||
2 | |||
3 | Required parent device properties: | ||
4 | - compatible : "marvell,88pm860x" | ||
5 | - reg : the I2C slave address for the 88pm860x chip | ||
6 | - interrupts : IRQ line for the 88pm860x chip | ||
7 | - interrupt-controller: describes the 88pm860x as an interrupt controller (has its own domain) | ||
8 | - #interrupt-cells : should be 1. | ||
9 | - The cell is the 88pm860x local IRQ number | ||
10 | |||
11 | Optional parent device properties: | ||
12 | - marvell,88pm860x-irq-read-clr: inicates whether interrupt status is cleared by read | ||
13 | - marvell,88pm860x-slave-addr: 88pm860x are two chips solution. <reg> stores the I2C address | ||
14 | of one chip, and this property stores the I2C address of | ||
15 | another chip. | ||
16 | |||
17 | 88pm860x consists of a large and varied group of sub-devices: | ||
18 | |||
19 | Device Supply Names Description | ||
20 | ------ ------------ ----------- | ||
21 | 88pm860x-onkey : : On key | ||
22 | 88pm860x-rtc : : RTC | ||
23 | 88pm8607 : : Regulators | ||
24 | 88pm860x-backlight : : Backlight | ||
25 | 88pm860x-led : : Led | ||
26 | 88pm860x-touch : : Touchscreen | ||
27 | |||
28 | Example: | ||
29 | |||
30 | pmic: 88pm860x@34 { | ||
31 | compatible = "marvell,88pm860x"; | ||
32 | reg = <0x34>; | ||
33 | interrupts = <4>; | ||
34 | interrupt-parent = <&intc>; | ||
35 | interrupt-controller; | ||
36 | #interrupt-cells = <1>; | ||
37 | |||
38 | marvell,88pm860x-irq-read-clr; | ||
39 | marvell,88pm860x-slave-addr = <0x11>; | ||
40 | |||
41 | regulators { | ||
42 | BUCK1 { | ||
43 | regulator-min-microvolt = <1000000>; | ||
44 | regulator-max-microvolt = <1500000>; | ||
45 | regulator-boot-on; | ||
46 | regulator-always-on; | ||
47 | }; | ||
48 | LDO1 { | ||
49 | regulator-min-microvolt = <1200000>; | ||
50 | regulator-max-microvolt = <2800000>; | ||
51 | regulator-boot-on; | ||
52 | regulator-always-on; | ||
53 | }; | ||
54 | }; | ||
55 | rtc { | ||
56 | marvell,88pm860x-vrtc = <1>; | ||
57 | }; | ||
58 | touch { | ||
59 | marvell,88pm860x-gpadc-prebias = <1>; | ||
60 | marvell,88pm860x-gpadc-slot-cycle = <1>; | ||
61 | marvell,88pm860x-tsi-prebias = <6>; | ||
62 | marvell,88pm860x-pen-prebias = <16>; | ||
63 | marvell,88pm860x-pen-prechg = <2>; | ||
64 | marvell,88pm860x-resistor-X = <300>; | ||
65 | }; | ||
66 | backlights { | ||
67 | backlight-0 { | ||
68 | marvell,88pm860x-iset = <4>; | ||
69 | marvell,88pm860x-pwm = <3>; | ||
70 | }; | ||
71 | backlight-2 { | ||
72 | }; | ||
73 | }; | ||
74 | leds { | ||
75 | led0-red { | ||
76 | marvell,88pm860x-iset = <12>; | ||
77 | }; | ||
78 | led0-green { | ||
79 | marvell,88pm860x-iset = <12>; | ||
80 | }; | ||
81 | led0-blue { | ||
82 | marvell,88pm860x-iset = <12>; | ||
83 | }; | ||
84 | }; | ||
85 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt deleted file mode 100644 index 13b707b7355..00000000000 --- a/Documentation/devicetree/bindings/mfd/ab8500.txt +++ /dev/null | |||
@@ -1,163 +0,0 @@ | |||
1 | * AB8500 Multi-Functional Device (MFD) | ||
2 | |||
3 | Required parent device properties: | ||
4 | - compatible : contains "stericsson,ab8500"; | ||
5 | - interrupts : contains the IRQ line for the AB8500 | ||
6 | - interrupt-controller : describes the AB8500 as an Interrupt Controller (has its own domain) | ||
7 | - #interrupt-cells : should be 2, for 2-cell format | ||
8 | - The first cell is the AB8500 local IRQ number | ||
9 | - The second cell is used to specify optional parameters | ||
10 | - bits[3:0] trigger type and level flags: | ||
11 | 1 = low-to-high edge triggered | ||
12 | 2 = high-to-low edge triggered | ||
13 | 4 = active high level-sensitive | ||
14 | 8 = active low level-sensitive | ||
15 | |||
16 | Optional parent device properties: | ||
17 | - reg : contains the PRCMU mailbox address for the AB8500 i2c port | ||
18 | |||
19 | The AB8500 consists of a large and varied group of sub-devices: | ||
20 | |||
21 | Device IRQ Names Supply Names Description | ||
22 | ------ --------- ------------ ----------- | ||
23 | ab8500-bm : : : Battery Manager | ||
24 | ab8500-btemp : : : Battery Temperature | ||
25 | ab8500-charger : : : Battery Charger | ||
26 | ab8500-codec : : : Audio Codec | ||
27 | ab8500-fg : : vddadc : Fuel Gauge | ||
28 | : NCONV_ACCU : : Accumulate N Sample Conversion | ||
29 | : BATT_OVV : : Battery Over Voltage | ||
30 | : LOW_BAT_F : : LOW threshold battery voltage | ||
31 | : CC_INT_CALIB : : Coulomb Counter Internal Calibration | ||
32 | : CCEOC : : Coulomb Counter End of Conversion | ||
33 | ab8500-btemp : : vtvout : Battery Temperature | ||
34 | : BAT_CTRL_INDB : : Battery Removal Indicator | ||
35 | : BTEMP_LOW : : Btemp < BtempLow, if battery temperature is lower than -10°C | ||
36 | : BTEMP_LOW_MEDIUM : : BtempLow < Btemp < BtempMedium,if battery temperature is between -10 and 0°C | ||
37 | : BTEMP_MEDIUM_HIGH : : BtempMedium < Btemp < BtempHigh,if battery temperature is between 0°C and“MaxTemp | ||
38 | : BTEMP_HIGH : : Btemp > BtempHigh, if battery temperature is higher than “MaxTemp | ||
39 | ab8500-charger : : vddadc : Charger interface | ||
40 | : MAIN_CH_UNPLUG_DET : : main charger unplug detection management (not in 8505) | ||
41 | : MAIN_CHARGE_PLUG_DET : : main charger plug detection management (not in 8505) | ||
42 | : MAIN_EXT_CH_NOT_OK : : main charger not OK | ||
43 | : MAIN_CH_TH_PROT_R : : Die temp is above main charger | ||
44 | : MAIN_CH_TH_PROT_F : : Die temp is below main charger | ||
45 | : VBUS_DET_F : : VBUS falling detected | ||
46 | : VBUS_DET_R : : VBUS rising detected | ||
47 | : USB_LINK_STATUS : : USB link status has changed | ||
48 | : USB_CH_TH_PROT_R : : Die temp is above usb charger | ||
49 | : USB_CH_TH_PROT_F : : Die temp is below usb charger | ||
50 | : USB_CHARGER_NOT_OKR : : allowed USB charger not ok detection | ||
51 | : VBUS_OVV : : Overvoltage on Vbus ball detected (USB charge is stopped) | ||
52 | : CH_WD_EXP : : Charger watchdog detected | ||
53 | ab8500-gpadc : HW_CONV_END : vddadc : Analogue to Digital Converter | ||
54 | SW_CONV_END : : | ||
55 | ab8500-gpio : : : GPIO Controller | ||
56 | ab8500-ponkey : ONKEY_DBF : : Power-on Key | ||
57 | ONKEY_DBR : : | ||
58 | ab8500-pwm : : : Pulse Width Modulator | ||
59 | ab8500-regulator : : : Regulators | ||
60 | ab8500-rtc : 60S : : Real Time Clock | ||
61 | : ALARM : : | ||
62 | ab8500-sysctrl : : : System Control | ||
63 | ab8500-usb : ID_WAKEUP_R : vddulpivio18 : Universal Serial Bus | ||
64 | : ID_WAKEUP_F : v-ape : | ||
65 | : VBUS_DET_F : musb_1v8 : | ||
66 | : VBUS_DET_R : : | ||
67 | : USB_LINK_STATUS : : | ||
68 | : USB_ADP_PROBE_PLUG : : | ||
69 | : USB_ADP_PROBE_UNPLUG : : | ||
70 | |||
71 | Required child device properties: | ||
72 | - compatible : "stericsson,ab8500-[bm|btemp|charger|fg|gpadc|gpio|ponkey| | ||
73 | pwm|regulator|rtc|sysctrl|usb]"; | ||
74 | |||
75 | Optional child device properties: | ||
76 | - interrupts : contains the device IRQ(s) using the 2-cell format (see above) | ||
77 | - interrupt-names : contains names of IRQ resource in the order in which they were | ||
78 | supplied in the interrupts property | ||
79 | - <supply_name>-supply : contains a phandle to the regulator supply node in Device Tree | ||
80 | |||
81 | Non-standard child device properties: | ||
82 | - Audio CODEC: | ||
83 | - stericsson,amic[1|2]-type-single-ended : Single-ended Analoge Mic (default: differential) | ||
84 | - stericsson,amic1a-bias-vamic2 : Analoge Mic wishes to use a non-standard Vamic | ||
85 | - stericsson,amic1b-bias-vamic2 : Analoge Mic wishes to use a non-standard Vamic | ||
86 | - stericsson,amic2-bias-vamic1 : Analoge Mic wishes to use a non-standard Vamic | ||
87 | - stericsson,earpeice-cmv : Earpeice voltage (only: 950 | 1100 | 1270 | 1580) | ||
88 | |||
89 | ab8500@5 { | ||
90 | compatible = "stericsson,ab8500"; | ||
91 | reg = <5>; /* mailbox 5 is i2c */ | ||
92 | interrupts = <0 40 0x4>; | ||
93 | interrupt-controller; | ||
94 | #interrupt-cells = <2>; | ||
95 | |||
96 | ab8500-rtc { | ||
97 | compatible = "stericsson,ab8500-rtc"; | ||
98 | interrupts = <17 0x4 | ||
99 | 18 0x4>; | ||
100 | interrupt-names = "60S", "ALARM"; | ||
101 | }; | ||
102 | |||
103 | ab8500-gpadc { | ||
104 | compatible = "stericsson,ab8500-gpadc"; | ||
105 | interrupts = <32 0x4 | ||
106 | 39 0x4>; | ||
107 | interrupt-names = "HW_CONV_END", "SW_CONV_END"; | ||
108 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | ||
109 | }; | ||
110 | |||
111 | ab8500-usb { | ||
112 | compatible = "stericsson,ab8500-usb"; | ||
113 | interrupts = < 90 0x4 | ||
114 | 96 0x4 | ||
115 | 14 0x4 | ||
116 | 15 0x4 | ||
117 | 79 0x4 | ||
118 | 74 0x4 | ||
119 | 75 0x4>; | ||
120 | interrupt-names = "ID_WAKEUP_R", | ||
121 | "ID_WAKEUP_F", | ||
122 | "VBUS_DET_F", | ||
123 | "VBUS_DET_R", | ||
124 | "USB_LINK_STATUS", | ||
125 | "USB_ADP_PROBE_PLUG", | ||
126 | "USB_ADP_PROBE_UNPLUG"; | ||
127 | vddulpivio18-supply = <&ab8500_ldo_initcore_reg>; | ||
128 | v-ape-supply = <&db8500_vape_reg>; | ||
129 | musb_1v8-supply = <&db8500_vsmps2_reg>; | ||
130 | }; | ||
131 | |||
132 | ab8500-ponkey { | ||
133 | compatible = "stericsson,ab8500-ponkey"; | ||
134 | interrupts = <6 0x4 | ||
135 | 7 0x4>; | ||
136 | interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; | ||
137 | }; | ||
138 | |||
139 | ab8500-sysctrl { | ||
140 | compatible = "stericsson,ab8500-sysctrl"; | ||
141 | }; | ||
142 | |||
143 | ab8500-pwm { | ||
144 | compatible = "stericsson,ab8500-pwm"; | ||
145 | }; | ||
146 | |||
147 | codec: ab8500-codec { | ||
148 | compatible = "stericsson,ab8500-codec"; | ||
149 | |||
150 | stericsson,earpeice-cmv = <950>; /* Units in mV. */ | ||
151 | }; | ||
152 | |||
153 | ab8500-regulators { | ||
154 | compatible = "stericsson,ab8500-regulator"; | ||
155 | |||
156 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { | ||
157 | /* | ||
158 | * See: Documentation/devicetree/bindings/regulator/regulator.txt | ||
159 | * for more information on regulators | ||
160 | */ | ||
161 | }; | ||
162 | }; | ||
163 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt b/Documentation/devicetree/bindings/mfd/da9052-i2c.txt deleted file mode 100644 index 1857f4a6b9a..00000000000 --- a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt +++ /dev/null | |||
@@ -1,60 +0,0 @@ | |||
1 | * Dialog DA9052/53 Power Management Integrated Circuit (PMIC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "dlg,da9052", "dlg,da9053-aa", | ||
5 | "dlg,da9053-ab", or "dlg,da9053-bb" | ||
6 | |||
7 | Sub-nodes: | ||
8 | - regulators : Contain the regulator nodes. The DA9052/53 regulators are | ||
9 | bound using their names as listed below: | ||
10 | |||
11 | buck0 : regulator BUCK0 | ||
12 | buck1 : regulator BUCK1 | ||
13 | buck2 : regulator BUCK2 | ||
14 | buck3 : regulator BUCK3 | ||
15 | ldo4 : regulator LDO4 | ||
16 | ldo5 : regulator LDO5 | ||
17 | ldo6 : regulator LDO6 | ||
18 | ldo7 : regulator LDO7 | ||
19 | ldo8 : regulator LDO8 | ||
20 | ldo9 : regulator LDO9 | ||
21 | ldo10 : regulator LDO10 | ||
22 | ldo11 : regulator LDO11 | ||
23 | ldo12 : regulator LDO12 | ||
24 | ldo13 : regulator LDO13 | ||
25 | |||
26 | The bindings details of individual regulator device can be found in: | ||
27 | Documentation/devicetree/bindings/regulator/regulator.txt | ||
28 | |||
29 | Examples: | ||
30 | |||
31 | i2c@63fc8000 { /* I2C1 */ | ||
32 | status = "okay"; | ||
33 | |||
34 | pmic: dialog@48 { | ||
35 | compatible = "dlg,da9053-aa"; | ||
36 | reg = <0x48>; | ||
37 | |||
38 | regulators { | ||
39 | buck0 { | ||
40 | regulator-min-microvolt = <500000>; | ||
41 | regulator-max-microvolt = <2075000>; | ||
42 | }; | ||
43 | |||
44 | buck1 { | ||
45 | regulator-min-microvolt = <500000>; | ||
46 | regulator-max-microvolt = <2075000>; | ||
47 | }; | ||
48 | |||
49 | buck2 { | ||
50 | regulator-min-microvolt = <925000>; | ||
51 | regulator-max-microvolt = <2500000>; | ||
52 | }; | ||
53 | |||
54 | buck3 { | ||
55 | regulator-min-microvolt = <925000>; | ||
56 | regulator-max-microvolt = <2500000>; | ||
57 | }; | ||
58 | }; | ||
59 | }; | ||
60 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/max77686.txt b/Documentation/devicetree/bindings/mfd/max77686.txt deleted file mode 100644 index c6a3469d343..00000000000 --- a/Documentation/devicetree/bindings/mfd/max77686.txt +++ /dev/null | |||
@@ -1,59 +0,0 @@ | |||
1 | Maxim MAX77686 multi-function device | ||
2 | |||
3 | MAX77686 is a Mulitifunction device with PMIC, RTC and Charger on chip. It is | ||
4 | interfaced to host controller using i2c interface. PMIC and Charger submodules | ||
5 | are addressed using same i2c slave address whereas RTC submodule uses | ||
6 | different i2c slave address,presently for which we are statically creating i2c | ||
7 | client while probing.This document describes the binding for mfd device and | ||
8 | PMIC submodule. | ||
9 | |||
10 | Required properties: | ||
11 | - compatible : Must be "maxim,max77686"; | ||
12 | - reg : Specifies the i2c slave address of PMIC block. | ||
13 | - interrupts : This i2c device has an IRQ line connected to the main SoC. | ||
14 | - interrupt-parent : The parent interrupt controller. | ||
15 | |||
16 | Optional node: | ||
17 | - voltage-regulators : The regulators of max77686 have to be instantiated | ||
18 | under subnode named "voltage-regulators" using the following format. | ||
19 | |||
20 | regulator_name { | ||
21 | regulator-compatible = LDOn/BUCKn | ||
22 | standard regulator constraints.... | ||
23 | }; | ||
24 | refer Documentation/devicetree/bindings/regulator/regulator.txt | ||
25 | |||
26 | The regulator-compatible property of regulator should initialized with string | ||
27 | to get matched with their hardware counterparts as follow: | ||
28 | |||
29 | -LDOn : for LDOs, where n can lie in range 1 to 26. | ||
30 | example: LDO1, LDO2, LDO26. | ||
31 | -BUCKn : for BUCKs, where n can lie in range 1 to 9. | ||
32 | example: BUCK1, BUCK5, BUCK9. | ||
33 | |||
34 | Example: | ||
35 | |||
36 | max77686@09 { | ||
37 | compatible = "maxim,max77686"; | ||
38 | interrupt-parent = <&wakeup_eint>; | ||
39 | interrupts = <26 0>; | ||
40 | reg = <0x09>; | ||
41 | |||
42 | voltage-regulators { | ||
43 | ldo11_reg { | ||
44 | regulator-compatible = "LDO11"; | ||
45 | regulator-name = "vdd_ldo11"; | ||
46 | regulator-min-microvolt = <1900000>; | ||
47 | regulator-max-microvolt = <1900000>; | ||
48 | regulator-always-on; | ||
49 | }; | ||
50 | |||
51 | buck1_reg { | ||
52 | regulator-compatible = "BUCK1"; | ||
53 | regulator-name = "vdd_mif"; | ||
54 | regulator-min-microvolt = <950000>; | ||
55 | regulator-max-microvolt = <1300000>; | ||
56 | regulator-always-on; | ||
57 | regulator-boot-on; | ||
58 | }; | ||
59 | } | ||
diff --git a/Documentation/devicetree/bindings/mfd/mc13xxx.txt b/Documentation/devicetree/bindings/mfd/mc13xxx.txt deleted file mode 100644 index baf07987ae6..00000000000 --- a/Documentation/devicetree/bindings/mfd/mc13xxx.txt +++ /dev/null | |||
@@ -1,78 +0,0 @@ | |||
1 | * Freescale MC13783/MC13892 Power Management Integrated Circuit (PMIC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "fsl,mc13783" or "fsl,mc13892" | ||
5 | |||
6 | Optional properties: | ||
7 | - fsl,mc13xxx-uses-adc : Indicate the ADC is being used | ||
8 | - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used | ||
9 | - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used | ||
10 | - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used | ||
11 | |||
12 | Sub-nodes: | ||
13 | - regulators : Contain the regulator nodes. The MC13892 regulators are | ||
14 | bound using their names as listed below with their registers and bits | ||
15 | for enabling. | ||
16 | |||
17 | vcoincell : regulator VCOINCELL (register 13, bit 23) | ||
18 | sw1 : regulator SW1 (register 24, bit 0) | ||
19 | sw2 : regulator SW2 (register 25, bit 0) | ||
20 | sw3 : regulator SW3 (register 26, bit 0) | ||
21 | sw4 : regulator SW4 (register 27, bit 0) | ||
22 | swbst : regulator SWBST (register 29, bit 20) | ||
23 | vgen1 : regulator VGEN1 (register 32, bit 0) | ||
24 | viohi : regulator VIOHI (register 32, bit 3) | ||
25 | vdig : regulator VDIG (register 32, bit 9) | ||
26 | vgen2 : regulator VGEN2 (register 32, bit 12) | ||
27 | vpll : regulator VPLL (register 32, bit 15) | ||
28 | vusb2 : regulator VUSB2 (register 32, bit 18) | ||
29 | vgen3 : regulator VGEN3 (register 33, bit 0) | ||
30 | vcam : regulator VCAM (register 33, bit 6) | ||
31 | vvideo : regulator VVIDEO (register 33, bit 12) | ||
32 | vaudio : regulator VAUDIO (register 33, bit 15) | ||
33 | vsd : regulator VSD (register 33, bit 18) | ||
34 | gpo1 : regulator GPO1 (register 34, bit 6) | ||
35 | gpo2 : regulator GPO2 (register 34, bit 8) | ||
36 | gpo3 : regulator GPO3 (register 34, bit 10) | ||
37 | gpo4 : regulator GPO4 (register 34, bit 12) | ||
38 | pwgt1spi : regulator PWGT1SPI (register 34, bit 15) | ||
39 | pwgt2spi : regulator PWGT2SPI (register 34, bit 16) | ||
40 | vusb : regulator VUSB (register 50, bit 3) | ||
41 | |||
42 | The bindings details of individual regulator device can be found in: | ||
43 | Documentation/devicetree/bindings/regulator/regulator.txt | ||
44 | |||
45 | Examples: | ||
46 | |||
47 | ecspi@70010000 { /* ECSPI1 */ | ||
48 | fsl,spi-num-chipselects = <2>; | ||
49 | cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */ | ||
50 | <&gpio4 25 0>; /* GPIO4_25 */ | ||
51 | status = "okay"; | ||
52 | |||
53 | pmic: mc13892@0 { | ||
54 | #address-cells = <1>; | ||
55 | #size-cells = <0>; | ||
56 | compatible = "fsl,mc13892"; | ||
57 | spi-max-frequency = <6000000>; | ||
58 | reg = <0>; | ||
59 | interrupt-parent = <&gpio0>; | ||
60 | interrupts = <8>; | ||
61 | |||
62 | regulators { | ||
63 | sw1_reg: mc13892__sw1 { | ||
64 | regulator-min-microvolt = <600000>; | ||
65 | regulator-max-microvolt = <1375000>; | ||
66 | regulator-boot-on; | ||
67 | regulator-always-on; | ||
68 | }; | ||
69 | |||
70 | sw2_reg: mc13892__sw2 { | ||
71 | regulator-min-microvolt = <900000>; | ||
72 | regulator-max-microvolt = <1850000>; | ||
73 | regulator-boot-on; | ||
74 | regulator-always-on; | ||
75 | }; | ||
76 | }; | ||
77 | }; | ||
78 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/stmpe.txt b/Documentation/devicetree/bindings/mfd/stmpe.txt deleted file mode 100644 index 56edb552068..00000000000 --- a/Documentation/devicetree/bindings/mfd/stmpe.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | * ST Microelectronics STMPE Multi-Functional Device | ||
2 | |||
3 | STMPE is an MFD device which may expose the following inbuilt devices: gpio, | ||
4 | keypad, touchscreen, adc, pwm, rotator. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : "st,stmpe[610|801|811|1601|2401|2403]" | ||
8 | - reg : I2C/SPI address of the device | ||
9 | |||
10 | Optional properties: | ||
11 | - interrupts : The interrupt outputs from the controller | ||
12 | - interrupt-controller : Marks the device node as an interrupt controller | ||
13 | - interrupt-parent : Specifies which IRQ controller we're connected to | ||
14 | - wakeup-source : Marks the input device as wakable | ||
15 | - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024 | ||
16 | |||
17 | Example: | ||
18 | |||
19 | stmpe1601: stmpe1601@40 { | ||
20 | compatible = "st,stmpe1601"; | ||
21 | reg = <0x40>; | ||
22 | interrupts = <26 0x4>; | ||
23 | interrupt-parent = <&gpio6>; | ||
24 | interrupt-controller; | ||
25 | |||
26 | wakeup-source; | ||
27 | st,autosleep-timeout = <1024>; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt deleted file mode 100644 index fe8150bb324..00000000000 --- a/Documentation/devicetree/bindings/mfd/syscon.txt +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | * System Controller Registers R/W driver | ||
2 | |||
3 | System controller node represents a register region containing a set | ||
4 | of miscellaneous registers. The registers are not cohesive enough to | ||
5 | represent as any specific type of device. The typical use-case is for | ||
6 | some other node's driver, or platform-specific code, to acquire a | ||
7 | reference to the syscon node (e.g. by phandle, node path, or search | ||
8 | using a specific compatible value), interrogate the node (or associated | ||
9 | OS driver) to determine the location of the registers, and access the | ||
10 | registers directly. | ||
11 | |||
12 | Required properties: | ||
13 | - compatible: Should contain "syscon". | ||
14 | - reg: the register region can be accessed from syscon | ||
15 | |||
16 | Examples: | ||
17 | gpr: iomuxc-gpr@020e0000 { | ||
18 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | ||
19 | reg = <0x020e0000 0x38>; | ||
20 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/tps65910.txt b/Documentation/devicetree/bindings/mfd/tps65910.txt deleted file mode 100644 index 2e3304888ff..00000000000 --- a/Documentation/devicetree/bindings/mfd/tps65910.txt +++ /dev/null | |||
@@ -1,201 +0,0 @@ | |||
1 | TPS65910 Power Management Integrated Circuit | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,tps65910" or "ti,tps65911" | ||
5 | - reg: I2C slave address | ||
6 | - interrupts: the interrupt outputs of the controller | ||
7 | - #gpio-cells: number of cells to describe a GPIO, this should be 2. | ||
8 | The first cell is the GPIO number. | ||
9 | The second cell is used to specify additional options <unused>. | ||
10 | - gpio-controller: mark the device as a GPIO controller | ||
11 | - #interrupt-cells: the number of cells to describe an IRQ, this should be 2. | ||
12 | The first cell is the IRQ number. | ||
13 | The second cell is the flags, encoded as the trigger masks from | ||
14 | Documentation/devicetree/bindings/interrupts.txt | ||
15 | - regulators: This is the list of child nodes that specify the regulator | ||
16 | initialization data for defined regulators. Not all regulators for the given | ||
17 | device need to be present. The definition for each of these nodes is defined | ||
18 | using the standard binding for regulators found at | ||
19 | Documentation/devicetree/bindings/regulator/regulator.txt. | ||
20 | The regulator is matched with the regulator-compatible. | ||
21 | |||
22 | The valid regulator-compatible values are: | ||
23 | tps65910: vrtc, vio, vdd1, vdd2, vdd3, vdig1, vdig2, vpll, vdac, vaux1, | ||
24 | vaux2, vaux33, vmmc | ||
25 | tps65911: vrtc, vio, vdd1, vdd3, vddctrl, ldo1, ldo2, ldo3, ldo4, ldo5, | ||
26 | ldo6, ldo7, ldo8 | ||
27 | |||
28 | - xxx-supply: Input voltage supply regulator. | ||
29 | These entries are require if regulators are enabled for a device. Missing of these | ||
30 | properties can cause the regulator registration fails. | ||
31 | If some of input supply is powered through battery or always-on supply then | ||
32 | also it is require to have these parameters with proper node handle of always | ||
33 | on power supply. | ||
34 | tps65910: | ||
35 | vcc1-supply: VDD1 input. | ||
36 | vcc2-supply: VDD2 input. | ||
37 | vcc3-supply: VAUX33 and VMMC input. | ||
38 | vcc4-supply: VAUX1 and VAUX2 input. | ||
39 | vcc5-supply: VPLL and VDAC input. | ||
40 | vcc6-supply: VDIG1 and VDIG2 input. | ||
41 | vcc7-supply: VRTC input. | ||
42 | vccio-supply: VIO input. | ||
43 | tps65911: | ||
44 | vcc1-supply: VDD1 input. | ||
45 | vcc2-supply: VDD2 input. | ||
46 | vcc3-supply: LDO6, LDO7 and LDO8 input. | ||
47 | vcc4-supply: LDO5 input. | ||
48 | vcc5-supply: LDO3 and LDO4 input. | ||
49 | vcc6-supply: LDO1 and LDO2 input. | ||
50 | vcc7-supply: VRTC input. | ||
51 | vccio-supply: VIO input. | ||
52 | |||
53 | Optional properties: | ||
54 | - ti,vmbch-threshold: (tps65911) main battery charged threshold | ||
55 | comparator. (see VMBCH_VSEL in TPS65910 datasheet) | ||
56 | - ti,vmbch2-threshold: (tps65911) main battery discharged threshold | ||
57 | comparator. (see VMBCH_VSEL in TPS65910 datasheet) | ||
58 | - ti,en-ck32k-xtal: enable external 32-kHz crystal oscillator (see CK32K_CTRL | ||
59 | in TPS6591X datasheet) | ||
60 | - ti,en-gpio-sleep: enable sleep control for gpios | ||
61 | There should be 9 entries here, one for each gpio. | ||
62 | - ti,system-power-controller: Telling whether or not this pmic is controlling | ||
63 | the system power. | ||
64 | |||
65 | Regulator Optional properties: | ||
66 | - ti,regulator-ext-sleep-control: enable external sleep | ||
67 | control through external inputs [0 (not enabled), 1 (EN1), 2 (EN2) or 4(EN3)] | ||
68 | If this property is not defined, it defaults to 0 (not enabled). | ||
69 | |||
70 | Example: | ||
71 | |||
72 | pmu: tps65910@d2 { | ||
73 | compatible = "ti,tps65910"; | ||
74 | reg = <0xd2>; | ||
75 | interrupt-parent = <&intc>; | ||
76 | interrupts = < 0 118 0x04 >; | ||
77 | |||
78 | #gpio-cells = <2>; | ||
79 | gpio-controller; | ||
80 | |||
81 | #interrupt-cells = <2>; | ||
82 | interrupt-controller; | ||
83 | |||
84 | ti,system-power-controller; | ||
85 | |||
86 | ti,vmbch-threshold = 0; | ||
87 | ti,vmbch2-threshold = 0; | ||
88 | ti,en-ck32k-xtal; | ||
89 | ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; | ||
90 | |||
91 | vcc1-supply = <®_parent>; | ||
92 | vcc2-supply = <&some_reg>; | ||
93 | vcc3-supply = <...>; | ||
94 | vcc4-supply = <...>; | ||
95 | vcc5-supply = <...>; | ||
96 | vcc6-supply = <...>; | ||
97 | vcc7-supply = <...>; | ||
98 | vccio-supply = <...>; | ||
99 | |||
100 | regulators { | ||
101 | #address-cells = <1>; | ||
102 | #size-cells = <0>; | ||
103 | |||
104 | vdd1_reg: regulator@0 { | ||
105 | regulator-compatible = "vdd1"; | ||
106 | reg = <0>; | ||
107 | regulator-min-microvolt = < 600000>; | ||
108 | regulator-max-microvolt = <1500000>; | ||
109 | regulator-always-on; | ||
110 | regulator-boot-on; | ||
111 | ti,regulator-ext-sleep-control = <0>; | ||
112 | }; | ||
113 | vdd2_reg: regulator@1 { | ||
114 | regulator-compatible = "vdd2"; | ||
115 | reg = <1>; | ||
116 | regulator-min-microvolt = < 600000>; | ||
117 | regulator-max-microvolt = <1500000>; | ||
118 | regulator-always-on; | ||
119 | regulator-boot-on; | ||
120 | ti,regulator-ext-sleep-control = <4>; | ||
121 | }; | ||
122 | vddctrl_reg: regulator@2 { | ||
123 | regulator-compatible = "vddctrl"; | ||
124 | reg = <2>; | ||
125 | regulator-min-microvolt = < 600000>; | ||
126 | regulator-max-microvolt = <1400000>; | ||
127 | regulator-always-on; | ||
128 | regulator-boot-on; | ||
129 | ti,regulator-ext-sleep-control = <0>; | ||
130 | }; | ||
131 | vio_reg: regulator@3 { | ||
132 | regulator-compatible = "vio"; | ||
133 | reg = <3>; | ||
134 | regulator-min-microvolt = <1500000>; | ||
135 | regulator-max-microvolt = <1800000>; | ||
136 | regulator-always-on; | ||
137 | regulator-boot-on; | ||
138 | ti,regulator-ext-sleep-control = <1>; | ||
139 | }; | ||
140 | ldo1_reg: regulator@4 { | ||
141 | regulator-compatible = "ldo1"; | ||
142 | reg = <4>; | ||
143 | regulator-min-microvolt = <1000000>; | ||
144 | regulator-max-microvolt = <3300000>; | ||
145 | ti,regulator-ext-sleep-control = <0>; | ||
146 | }; | ||
147 | ldo2_reg: regulator@5 { | ||
148 | regulator-compatible = "ldo2"; | ||
149 | reg = <5>; | ||
150 | regulator-min-microvolt = <1050000>; | ||
151 | regulator-max-microvolt = <1050000>; | ||
152 | ti,regulator-ext-sleep-control = <0>; | ||
153 | }; | ||
154 | ldo3_reg: regulator@6 { | ||
155 | regulator-compatible = "ldo3"; | ||
156 | reg = <6>; | ||
157 | regulator-min-microvolt = <1000000>; | ||
158 | regulator-max-microvolt = <3300000>; | ||
159 | ti,regulator-ext-sleep-control = <0>; | ||
160 | }; | ||
161 | ldo4_reg: regulator@7 { | ||
162 | regulator-compatible = "ldo4"; | ||
163 | reg = <7>; | ||
164 | regulator-min-microvolt = <1000000>; | ||
165 | regulator-max-microvolt = <3300000>; | ||
166 | regulator-always-on; | ||
167 | ti,regulator-ext-sleep-control = <0>; | ||
168 | }; | ||
169 | ldo5_reg: regulator@8 { | ||
170 | regulator-compatible = "ldo5"; | ||
171 | reg = <8>; | ||
172 | regulator-min-microvolt = <1000000>; | ||
173 | regulator-max-microvolt = <3300000>; | ||
174 | ti,regulator-ext-sleep-control = <0>; | ||
175 | }; | ||
176 | ldo6_reg: regulator@9 { | ||
177 | regulator-compatible = "ldo6"; | ||
178 | reg = <9>; | ||
179 | regulator-min-microvolt = <1200000>; | ||
180 | regulator-max-microvolt = <1200000>; | ||
181 | ti,regulator-ext-sleep-control = <0>; | ||
182 | }; | ||
183 | ldo7_reg: regulator@10 { | ||
184 | regulator-compatible = "ldo7"; | ||
185 | reg = <10>; | ||
186 | regulator-min-microvolt = <1200000>; | ||
187 | regulator-max-microvolt = <1200000>; | ||
188 | regulator-always-on; | ||
189 | regulator-boot-on; | ||
190 | ti,regulator-ext-sleep-control = <1>; | ||
191 | }; | ||
192 | ldo8_reg: regulator@11 { | ||
193 | regulator-compatible = "ldo8"; | ||
194 | reg = <11>; | ||
195 | regulator-min-microvolt = <1000000>; | ||
196 | regulator-max-microvolt = <3300000>; | ||
197 | regulator-always-on; | ||
198 | ti,regulator-ext-sleep-control = <1>; | ||
199 | }; | ||
200 | }; | ||
201 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/twl-familly.txt b/Documentation/devicetree/bindings/mfd/twl-familly.txt deleted file mode 100644 index a66fcf94675..00000000000 --- a/Documentation/devicetree/bindings/mfd/twl-familly.txt +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | Texas Instruments TWL family | ||
2 | |||
3 | The TWLs are Integrated Power Management Chips. | ||
4 | Some version might contain much more analog function like | ||
5 | USB transceiver or Audio amplifier. | ||
6 | These chips are connected to an i2c bus. | ||
7 | |||
8 | |||
9 | Required properties: | ||
10 | - compatible : Must be "ti,twl4030"; | ||
11 | For Integrated power-management/audio CODEC device used in OMAP3 | ||
12 | based boards | ||
13 | - compatible : Must be "ti,twl6030"; | ||
14 | For Integrated power-management used in OMAP4 based boards | ||
15 | - interrupts : This i2c device has an IRQ line connected to the main SoC | ||
16 | - interrupt-controller : Since the twl support several interrupts internally, | ||
17 | it is considered as an interrupt controller cascaded to the SoC one. | ||
18 | - #interrupt-cells = <1>; | ||
19 | - interrupt-parent : The parent interrupt controller. | ||
20 | |||
21 | Optional node: | ||
22 | - Child nodes contain in the twl. The twl family is made of several variants | ||
23 | that support a different number of features. | ||
24 | The children nodes will thus depend of the capability of the variant. | ||
25 | |||
26 | |||
27 | Example: | ||
28 | /* | ||
29 | * Integrated Power Management Chip | ||
30 | * http://www.ti.com/lit/ds/symlink/twl6030.pdf | ||
31 | */ | ||
32 | twl@48 { | ||
33 | compatible = "ti,twl6030"; | ||
34 | reg = <0x48>; | ||
35 | interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */ | ||
36 | interrupt-controller; | ||
37 | #interrupt-cells = <1>; | ||
38 | interrupt-parent = <&gic>; | ||
39 | #address-cells = <1>; | ||
40 | #size-cells = <0>; | ||
41 | |||
42 | twl_rtc { | ||
43 | compatible = "ti,twl_rtc"; | ||
44 | interrupts = <11>; | ||
45 | reg = <0>; | ||
46 | }; | ||
47 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt deleted file mode 100644 index 414d2ae0adf..00000000000 --- a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt +++ /dev/null | |||
@@ -1,46 +0,0 @@ | |||
1 | Texas Instruments TWL family (twl4030) audio module | ||
2 | |||
3 | The audio module inside the TWL family consist of an audio codec and a vibra | ||
4 | driver. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : must be "ti,twl4030-audio" | ||
8 | |||
9 | Optional properties, nodes: | ||
10 | |||
11 | Audio functionality: | ||
12 | - codec { }: Need to be present if the audio functionality is used. Within this | ||
13 | section the following options can be used: | ||
14 | - ti,digimic_delay: Delay need after enabling the digimic to reduce artifacts | ||
15 | from the start of the recorded sample (in ms) | ||
16 | -ti,ramp_delay_value: HS ramp delay configuration to reduce pop noise | ||
17 | -ti,hs_extmute: Use external mute for HS pop reduction | ||
18 | -ti,hs_extmute_gpio: Use external GPIO to control the external mute | ||
19 | -ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the | ||
20 | valid values. | ||
21 | |||
22 | Vibra functionality | ||
23 | - ti,enable-vibra: Need to be set to <1> if the vibra functionality is used. if | ||
24 | missing or it is 0, the vibra functionality is disabled. | ||
25 | |||
26 | Example: | ||
27 | &i2c1 { | ||
28 | clock-frequency = <2600000>; | ||
29 | |||
30 | twl: twl@48 { | ||
31 | reg = <0x48>; | ||
32 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ | ||
33 | interrupt-parent = <&intc>; | ||
34 | |||
35 | twl_audio: audio { | ||
36 | compatible = "ti,twl4030-audio"; | ||
37 | |||
38 | ti,enable-vibra = <1>; | ||
39 | |||
40 | codec { | ||
41 | ti,ramp_delay_value = <3>; | ||
42 | }; | ||
43 | |||
44 | }; | ||
45 | }; | ||
46 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/twl6040.txt b/Documentation/devicetree/bindings/mfd/twl6040.txt deleted file mode 100644 index 0f5dd709d75..00000000000 --- a/Documentation/devicetree/bindings/mfd/twl6040.txt +++ /dev/null | |||
@@ -1,65 +0,0 @@ | |||
1 | Texas Instruments TWL6040 family | ||
2 | |||
3 | The TWL6040s are 8-channel high quality low-power audio codecs providing audio, | ||
4 | vibra and GPO functionality on OMAP4+ platforms. | ||
5 | They are connected ot the host processor via i2c for commands, McPDM for audio | ||
6 | data and commands. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible : "ti,twl6040" for twl6040, "ti,twl6041" for twl6041 | ||
10 | - reg: must be 0x4b for i2c address | ||
11 | - interrupts: twl6040 has one interrupt line connecteded to the main SoC | ||
12 | - interrupt-parent: The parent interrupt controller | ||
13 | - gpio-controller: | ||
14 | - #gpio-cells = <1>: twl6040 provides GPO lines. | ||
15 | - twl6040,audpwron-gpio: Power on GPIO line for the twl6040 | ||
16 | |||
17 | - vio-supply: Regulator for the twl6040 VIO supply | ||
18 | - v2v1-supply: Regulator for the twl6040 V2V1 supply | ||
19 | |||
20 | Optional properties, nodes: | ||
21 | - enable-active-high: To power on the twl6040 during boot. | ||
22 | |||
23 | Vibra functionality | ||
24 | Required properties: | ||
25 | - vddvibl-supply: Regulator for the left vibra motor | ||
26 | - vddvibr-supply: Regulator for the right vibra motor | ||
27 | - vibra { }: Configuration section for vibra parameters containing the following | ||
28 | properties: | ||
29 | - ti,vibldrv-res: Resistance parameter for left driver | ||
30 | - ti,vibrdrv-res: Resistance parameter for right driver | ||
31 | - ti,viblmotor-res: Resistance parameter for left motor | ||
32 | - ti,viblmotor-res: Resistance parameter for right motor | ||
33 | |||
34 | Optional properties within vibra { } section: | ||
35 | - vddvibl_uV: If the vddvibl default voltage need to be changed | ||
36 | - vddvibr_uV: If the vddvibr default voltage need to be changed | ||
37 | |||
38 | Example: | ||
39 | &i2c1 { | ||
40 | twl6040: twl@4b { | ||
41 | compatible = "ti,twl6040"; | ||
42 | |||
43 | interrupts = <0 119 4>; | ||
44 | interrupt-parent = <&gic>; | ||
45 | twl6040,audpwron-gpio = <&gpio4 31 0>; | ||
46 | |||
47 | vio-supply = <&v1v8>; | ||
48 | v2v1-supply = <&v2v1>; | ||
49 | enable-active-high; | ||
50 | |||
51 | /* regulators for vibra motor */ | ||
52 | vddvibl-supply = <&vbat>; | ||
53 | vddvibr-supply = <&vbat>; | ||
54 | |||
55 | vibra { | ||
56 | /* Vibra driver, motor resistance parameters */ | ||
57 | ti,vibldrv-res = <8>; | ||
58 | ti,vibrdrv-res = <3>; | ||
59 | ti,viblmotor-res = <10>; | ||
60 | ti,vibrmotor-res = <10>; | ||
61 | }; | ||
62 | }; | ||
63 | }; | ||
64 | |||
65 | /include/ "twl6040.dtsi" | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt deleted file mode 100644 index 6581478225a..00000000000 --- a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt +++ /dev/null | |||
@@ -1,126 +0,0 @@ | |||
1 | * Boot Bus | ||
2 | |||
3 | The Octeon Boot Bus is a configurable parallel bus with 8 chip | ||
4 | selects. Each chip select is independently configurable. | ||
5 | |||
6 | Properties: | ||
7 | - compatible: "cavium,octeon-3860-bootbus" | ||
8 | |||
9 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
10 | |||
11 | - reg: The base address of the Boot Bus' register bank. | ||
12 | |||
13 | - #address-cells: Must be <2>. The first cell is the chip select | ||
14 | within the bootbus. The second cell is the offset from the chip select. | ||
15 | |||
16 | - #size-cells: Must be <1>. | ||
17 | |||
18 | - ranges: There must be one one triplet of (child-bus-address, | ||
19 | parent-bus-address, length) for each active chip select. If the | ||
20 | length element for any triplet is zero, the chip select is disabled, | ||
21 | making it inactive. | ||
22 | |||
23 | The configuration parameters for each chip select are stored in child | ||
24 | nodes. | ||
25 | |||
26 | Configuration Properties: | ||
27 | - compatible: "cavium,octeon-3860-bootbus-config" | ||
28 | |||
29 | - cavium,cs-index: A single cell indicating the chip select that | ||
30 | corresponds to this configuration. | ||
31 | |||
32 | - cavium,t-adr: A cell specifying the ADR timing (in nS). | ||
33 | |||
34 | - cavium,t-ce: A cell specifying the CE timing (in nS). | ||
35 | |||
36 | - cavium,t-oe: A cell specifying the OE timing (in nS). | ||
37 | |||
38 | - cavium,t-we: A cell specifying the WE timing (in nS). | ||
39 | |||
40 | - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). | ||
41 | |||
42 | - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). | ||
43 | |||
44 | - cavium,t-pause: A cell specifying the PAUSE timing (in nS). | ||
45 | |||
46 | - cavium,t-wait: A cell specifying the WAIT timing (in nS). | ||
47 | |||
48 | - cavium,t-page: A cell specifying the PAGE timing (in nS). | ||
49 | |||
50 | - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS). | ||
51 | |||
52 | - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1 | ||
53 | = 2 bytes, 2 = 4 bytes, 3 = 8 bytes). | ||
54 | |||
55 | - cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected. | ||
56 | |||
57 | - cavium,page-mode: Optional. If present, page mode (PAGEM) is selected. | ||
58 | |||
59 | - cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of | ||
60 | the bus for this chip select. | ||
61 | |||
62 | - cavium,ale-mode: Optional. If present, ALE mode is selected. | ||
63 | |||
64 | - cavium,sam-mode: Optional. If present, SAM mode is selected. | ||
65 | |||
66 | - cavium,or-mode: Optional. If present, OR mode is selected. | ||
67 | |||
68 | Example: | ||
69 | bootbus: bootbus@1180000000000 { | ||
70 | compatible = "cavium,octeon-3860-bootbus"; | ||
71 | reg = <0x11800 0x00000000 0x0 0x200>; | ||
72 | /* The chip select number and offset */ | ||
73 | #address-cells = <2>; | ||
74 | /* The size of the chip select region */ | ||
75 | #size-cells = <1>; | ||
76 | ranges = <0 0 0x0 0x1f400000 0xc00000>, | ||
77 | <1 0 0x10000 0x30000000 0>, | ||
78 | <2 0 0x10000 0x40000000 0>, | ||
79 | <3 0 0x10000 0x50000000 0>, | ||
80 | <4 0 0x0 0x1d020000 0x10000>, | ||
81 | <5 0 0x0 0x1d040000 0x10000>, | ||
82 | <6 0 0x0 0x1d050000 0x10000>, | ||
83 | <7 0 0x10000 0x90000000 0>; | ||
84 | |||
85 | cavium,cs-config@0 { | ||
86 | compatible = "cavium,octeon-3860-bootbus-config"; | ||
87 | cavium,cs-index = <0>; | ||
88 | cavium,t-adr = <20>; | ||
89 | cavium,t-ce = <60>; | ||
90 | cavium,t-oe = <60>; | ||
91 | cavium,t-we = <45>; | ||
92 | cavium,t-rd-hld = <35>; | ||
93 | cavium,t-wr-hld = <45>; | ||
94 | cavium,t-pause = <0>; | ||
95 | cavium,t-wait = <0>; | ||
96 | cavium,t-page = <35>; | ||
97 | cavium,t-rd-dly = <0>; | ||
98 | |||
99 | cavium,pages = <0>; | ||
100 | cavium,bus-width = <8>; | ||
101 | }; | ||
102 | . | ||
103 | . | ||
104 | . | ||
105 | cavium,cs-config@6 { | ||
106 | compatible = "cavium,octeon-3860-bootbus-config"; | ||
107 | cavium,cs-index = <6>; | ||
108 | cavium,t-adr = <5>; | ||
109 | cavium,t-ce = <300>; | ||
110 | cavium,t-oe = <270>; | ||
111 | cavium,t-we = <150>; | ||
112 | cavium,t-rd-hld = <100>; | ||
113 | cavium,t-wr-hld = <70>; | ||
114 | cavium,t-pause = <0>; | ||
115 | cavium,t-wait = <0>; | ||
116 | cavium,t-page = <320>; | ||
117 | cavium,t-rd-dly = <0>; | ||
118 | |||
119 | cavium,pages = <0>; | ||
120 | cavium,wait-mode; | ||
121 | cavium,bus-width = <16>; | ||
122 | }; | ||
123 | . | ||
124 | . | ||
125 | . | ||
126 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt deleted file mode 100644 index 2c2d0746b43..00000000000 --- a/Documentation/devicetree/bindings/mips/cavium/ciu.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | * Central Interrupt Unit | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-3860-ciu" | ||
5 | |||
6 | Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs. | ||
7 | |||
8 | - interrupt-controller: This is an interrupt controller. | ||
9 | |||
10 | - reg: The base address of the CIU's register bank. | ||
11 | |||
12 | - #interrupt-cells: Must be <2>. The first cell is the bank within | ||
13 | the CIU and may have a value of 0 or 1. The second cell is the bit | ||
14 | within the bank and may have a value between 0 and 63. | ||
15 | |||
16 | Example: | ||
17 | interrupt-controller@1070000000000 { | ||
18 | compatible = "cavium,octeon-3860-ciu"; | ||
19 | interrupt-controller; | ||
20 | /* Interrupts are specified by two parts: | ||
21 | * 1) Controller register (0 or 1) | ||
22 | * 2) Bit within the register (0..63) | ||
23 | */ | ||
24 | #interrupt-cells = <2>; | ||
25 | reg = <0x10700 0x00000000 0x0 0x7000>; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt deleted file mode 100644 index 0ec7ba8bbbc..00000000000 --- a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | * Central Interrupt Unit | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-6880-ciu2" | ||
5 | |||
6 | Compatibility with 68XX SOCs. | ||
7 | |||
8 | - interrupt-controller: This is an interrupt controller. | ||
9 | |||
10 | - reg: The base address of the CIU's register bank. | ||
11 | |||
12 | - #interrupt-cells: Must be <2>. The first cell is the bank within | ||
13 | the CIU and may have a value between 0 and 63. The second cell is | ||
14 | the bit within the bank and may also have a value between 0 and 63. | ||
15 | |||
16 | Example: | ||
17 | interrupt-controller@1070100000000 { | ||
18 | compatible = "cavium,octeon-6880-ciu2"; | ||
19 | interrupt-controller; | ||
20 | /* Interrupts are specified by two parts: | ||
21 | * 1) Controller register (0..63) | ||
22 | * 2) Bit within the register (0..63) | ||
23 | */ | ||
24 | #address-cells = <0>; | ||
25 | #interrupt-cells = <2>; | ||
26 | reg = <0x10701 0x00000000 0x0 0x4000000>; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt deleted file mode 100644 index cb4291e3b1d..00000000000 --- a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | * DMA Engine. | ||
2 | |||
3 | The Octeon DMA Engine transfers between the Boot Bus and main memory. | ||
4 | The DMA Engine will be refered to by phandle by any device that is | ||
5 | connected to it. | ||
6 | |||
7 | Properties: | ||
8 | - compatible: "cavium,octeon-5750-bootbus-dma" | ||
9 | |||
10 | Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. | ||
11 | |||
12 | - reg: The base address of the DMA Engine's register bank. | ||
13 | |||
14 | - interrupts: A single interrupt specifier. | ||
15 | |||
16 | Example: | ||
17 | dma0: dma-engine@1180000000100 { | ||
18 | compatible = "cavium,octeon-5750-bootbus-dma"; | ||
19 | reg = <0x11800 0x00000100 0x0 0x8>; | ||
20 | interrupts = <0 63>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt deleted file mode 100644 index aa66b9b8d80..00000000000 --- a/Documentation/devicetree/bindings/mips/cavium/uctl.txt +++ /dev/null | |||
@@ -1,46 +0,0 @@ | |||
1 | * UCTL USB controller glue | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-6335-uctl" | ||
5 | |||
6 | Compatibility with all cn6XXX SOCs. | ||
7 | |||
8 | - reg: The base address of the UCTL register bank. | ||
9 | |||
10 | - #address-cells: Must be <2>. | ||
11 | |||
12 | - #size-cells: Must be <2>. | ||
13 | |||
14 | - ranges: Empty to signify direct mapping of the children. | ||
15 | |||
16 | - refclk-frequency: A single cell containing the reference clock | ||
17 | frequency in Hz. | ||
18 | |||
19 | - refclk-type: A string describing the reference clock connection | ||
20 | either "crystal" or "external". | ||
21 | |||
22 | Example: | ||
23 | uctl@118006f000000 { | ||
24 | compatible = "cavium,octeon-6335-uctl"; | ||
25 | reg = <0x11800 0x6f000000 0x0 0x100>; | ||
26 | ranges; /* Direct mapping */ | ||
27 | #address-cells = <2>; | ||
28 | #size-cells = <2>; | ||
29 | /* 12MHz, 24MHz and 48MHz allowed */ | ||
30 | refclk-frequency = <24000000>; | ||
31 | /* Either "crystal" or "external" */ | ||
32 | refclk-type = "crystal"; | ||
33 | |||
34 | ehci@16f0000000000 { | ||
35 | compatible = "cavium,octeon-6335-ehci","usb-ehci"; | ||
36 | reg = <0x16f00 0x00000000 0x0 0x100>; | ||
37 | interrupts = <0 56>; | ||
38 | big-endian-regs; | ||
39 | }; | ||
40 | ohci@16f0000000400 { | ||
41 | compatible = "cavium,octeon-6335-ohci","usb-ohci"; | ||
42 | reg = <0x16f00 0x00000400 0x0 0x100>; | ||
43 | interrupts = <0 56>; | ||
44 | big-endian-regs; | ||
45 | }; | ||
46 | }; | ||
diff --git a/Documentation/devicetree/bindings/misc/at25.txt b/Documentation/devicetree/bindings/misc/at25.txt deleted file mode 100644 index 1d3447165c3..00000000000 --- a/Documentation/devicetree/bindings/misc/at25.txt +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | EEPROMs (SPI) compatible with Atmel at25. | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "atmel,at25". | ||
5 | - reg : chip select number | ||
6 | - spi-max-frequency : max spi frequency to use | ||
7 | - pagesize : size of the eeprom page | ||
8 | - size : total eeprom size in bytes | ||
9 | - address-width : number of address bits (one of 8, 16, or 24) | ||
10 | |||
11 | Optional properties: | ||
12 | - spi-cpha : SPI shifted clock phase, as per spi-bus bindings. | ||
13 | - spi-cpol : SPI inverse clock polarity, as per spi-bus bindings. | ||
14 | - read-only : this parameter-less property disables writes to the eeprom | ||
15 | |||
16 | Obsolete legacy properties are can be used in place of "size", "pagesize", | ||
17 | "address-width", and "read-only": | ||
18 | - at25,byte-len : total eeprom size in bytes | ||
19 | - at25,addr-mode : addr-mode flags, as defined in include/linux/spi/eeprom.h | ||
20 | - at25,page-size : size of the eeprom page | ||
21 | |||
22 | Additional compatible properties are also allowed. | ||
23 | |||
24 | Example: | ||
25 | at25@0 { | ||
26 | compatible = "atmel,at25", "st,m95256"; | ||
27 | reg = <0> | ||
28 | spi-max-frequency = <5000000>; | ||
29 | spi-cpha; | ||
30 | spi-cpol; | ||
31 | |||
32 | pagesize = <64>; | ||
33 | size = <32768>; | ||
34 | address-width = <16>; | ||
35 | }; | ||
diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt deleted file mode 100644 index 38e51ad2e07..00000000000 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | * Atmel SSC driver. | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" | ||
5 | - atmel,at91rm9200-ssc: support pdc transfer | ||
6 | - atmel,at91sam9g45-ssc: support dma transfer | ||
7 | - reg: Should contain SSC registers location and length | ||
8 | - interrupts: Should contain SSC interrupt | ||
9 | |||
10 | Example: | ||
11 | ssc0: ssc@fffbc000 { | ||
12 | compatible = "atmel,at91rm9200-ssc"; | ||
13 | reg = <0xfffbc000 0x4000>; | ||
14 | interrupts = <14 4 5>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/misc/bmp085.txt b/Documentation/devicetree/bindings/misc/bmp085.txt deleted file mode 100644 index 91dfda2e4e1..00000000000 --- a/Documentation/devicetree/bindings/misc/bmp085.txt +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | BMP085/BMP18x digital pressure sensors | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: bosch,bmp085 | ||
5 | |||
6 | Optional properties: | ||
7 | - chip-id: configurable chip id for non-default chip revisions | ||
8 | - temp-measurement-period: temperature measurement period (milliseconds) | ||
9 | - default-oversampling: default oversampling value to be used at startup, | ||
10 | value range is 0-3 with rising sensitivity. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | pressure@77 { | ||
15 | compatible = "bosch,bmp085"; | ||
16 | reg = <0x77>; | ||
17 | chip-id = <10>; | ||
18 | temp-measurement-period = <100>; | ||
19 | default-oversampling = <2>; | ||
20 | }; | ||
diff --git a/Documentation/devicetree/bindings/misc/ifm-csi.txt b/Documentation/devicetree/bindings/misc/ifm-csi.txt deleted file mode 100644 index 5bdfffb0b9f..00000000000 --- a/Documentation/devicetree/bindings/misc/ifm-csi.txt +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | IFM camera sensor interface on mpc5200 LocalPlus bus | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ifm,o2d-csi" | ||
5 | - reg: specifies sensor chip select number and associated address range | ||
6 | - interrupts: external interrupt line number and interrupt sense mode | ||
7 | of the interrupt line signaling frame valid events | ||
8 | - gpios: three gpio-specifiers for "capture", "reset" and "master enable" | ||
9 | GPIOs (strictly in this order). | ||
10 | - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor | ||
11 | clock generator. This node is usually a general purpose timer controller. | ||
12 | - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25) | ||
13 | - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16) | ||
14 | - ifm,csi-wait-cycles: sensor bus wait cycles | ||
15 | |||
16 | Optional properties: | ||
17 | - ifm,csi-byte-swap: if this property is present, the byte swapping on | ||
18 | the bus will be enabled. | ||
19 | |||
20 | Example: | ||
21 | |||
22 | csi@3,0 { | ||
23 | compatible = "ifm,o2d-csi"; | ||
24 | reg = <3 0 0x00100000>; /* CS 3, 1 MiB range */ | ||
25 | interrupts = <1 1 2>; /* IRQ1, edge falling */ | ||
26 | |||
27 | ifm,csi-clk-handle = <&timer7>; | ||
28 | gpios = <&gpio_simple 23 0 /* image_capture */ | ||
29 | &gpio_simple 26 0 /* image_reset */ | ||
30 | &gpio_simple 29 0>; /* image_master_en */ | ||
31 | |||
32 | ifm,csi-addr-bus-width = <24>; | ||
33 | ifm,csi-data-bus-width = <8>; | ||
34 | ifm,csi-wait-cycles = <0>; | ||
35 | }; | ||
36 | |||
37 | The base address of the used chip select is specified in the | ||
38 | ranges property of the parent localbus node, for example: | ||
39 | |||
40 | ranges = <0 0 0xff000000 0x01000000 | ||
41 | 3 0 0xe3000000 0x00100000>; | ||
diff --git a/Documentation/devicetree/bindings/misc/lis302.txt b/Documentation/devicetree/bindings/misc/lis302.txt deleted file mode 100644 index 6def86f6b05..00000000000 --- a/Documentation/devicetree/bindings/misc/lis302.txt +++ /dev/null | |||
@@ -1,112 +0,0 @@ | |||
1 | LIS302 accelerometer devicetree bindings | ||
2 | |||
3 | This device is matched via its bus drivers, and has a number of properties | ||
4 | that apply in on the generic device (independent from the bus). | ||
5 | |||
6 | |||
7 | Required properties for the SPI bindings: | ||
8 | - compatible: should be set to "st,lis3lv02d_spi" | ||
9 | - reg: the chipselect index | ||
10 | - spi-max-frequency: maximal bus speed, should be set to 1000000 unless | ||
11 | constrained by external circuitry | ||
12 | - interrupts: the interrupt generated by the device | ||
13 | |||
14 | Required properties for the I2C bindings: | ||
15 | - compatible: should be set to "st,lis3lv02d" | ||
16 | - reg: i2c slave address | ||
17 | - Vdd-supply: The input supply for Vdd | ||
18 | - Vdd_IO-supply: The input supply for Vdd_IO | ||
19 | |||
20 | |||
21 | Optional properties for all bus drivers: | ||
22 | |||
23 | - st,click-single-{x,y,z}: if present, tells the device to issue an | ||
24 | interrupt on single click events on the | ||
25 | x/y/z axis. | ||
26 | - st,click-double-{x,y,z}: if present, tells the device to issue an | ||
27 | interrupt on double click events on the | ||
28 | x/y/z axis. | ||
29 | - st,click-thresh-{x,y,z}: set the x/y/z axis threshold | ||
30 | - st,click-click-time-limit: click time limit, from 0 to 127.5msec | ||
31 | with step of 0.5 msec | ||
32 | - st,click-latency: click latency, from 0 to 255 msec with | ||
33 | step of 1 msec. | ||
34 | - st,click-window: click window, from 0 to 255 msec with | ||
35 | step of 1 msec. | ||
36 | - st,irq{1,2}-disable: disable IRQ 1/2 | ||
37 | - st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition | ||
38 | - st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition | ||
39 | - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready contition | ||
40 | - st,irq{1,2}-click: raise IRQ 1/2 on click condition | ||
41 | - st,irq-open-drain: consider IRQ lines open-drain | ||
42 | - st,irq-active-low: make IRQ lines active low | ||
43 | - st,wu-duration-1: duration register for Free-Fall/Wake-Up | ||
44 | interrupt 1 | ||
45 | - st,wu-duration-2: duration register for Free-Fall/Wake-Up | ||
46 | interrupt 2 | ||
47 | - st,wakeup-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for | ||
48 | upper/lower limit | ||
49 | - st,highpass-cutoff-hz=: 1, 2, 4 or 8 for 1Hz, 2Hz, 4Hz or 8Hz of | ||
50 | highpass cut-off frequency | ||
51 | - st,hipass{1,2}-disable: disable highpass 1/2. | ||
52 | - st,default-rate=: set the default rate | ||
53 | - st,axis-{x,y,z}=: set the axis to map to the three coordinates | ||
54 | - st,{min,max}-limit-{x,y,z} set the min/max limits for x/y/z axis | ||
55 | (used by self-test) | ||
56 | |||
57 | |||
58 | Example for a SPI device node: | ||
59 | |||
60 | lis302@0 { | ||
61 | compatible = "st,lis302dl-spi"; | ||
62 | reg = <0>; | ||
63 | spi-max-frequency = <1000000>; | ||
64 | interrupt-parent = <&gpio>; | ||
65 | interrupts = <104 0>; | ||
66 | |||
67 | st,click-single-x; | ||
68 | st,click-single-y; | ||
69 | st,click-single-z; | ||
70 | st,click-thresh-x = <10>; | ||
71 | st,click-thresh-y = <10>; | ||
72 | st,click-thresh-z = <10>; | ||
73 | st,irq1-click; | ||
74 | st,irq2-click; | ||
75 | st,wakeup-x-lo; | ||
76 | st,wakeup-x-hi; | ||
77 | st,wakeup-y-lo; | ||
78 | st,wakeup-y-hi; | ||
79 | st,wakeup-z-lo; | ||
80 | st,wakeup-z-hi; | ||
81 | }; | ||
82 | |||
83 | Example for a I2C device node: | ||
84 | |||
85 | lis331dlh: lis331dlh@18 { | ||
86 | compatible = "st,lis331dlh", "st,lis3lv02d"; | ||
87 | reg = <0x18>; | ||
88 | Vdd-supply = <&lis3_reg>; | ||
89 | Vdd_IO-supply = <&lis3_reg>; | ||
90 | |||
91 | st,click-single-x; | ||
92 | st,click-single-y; | ||
93 | st,click-single-z; | ||
94 | st,click-thresh-x = <10>; | ||
95 | st,click-thresh-y = <10>; | ||
96 | st,click-thresh-z = <10>; | ||
97 | st,irq1-click; | ||
98 | st,irq2-click; | ||
99 | st,wakeup-x-lo; | ||
100 | st,wakeup-x-hi; | ||
101 | st,wakeup-y-lo; | ||
102 | st,wakeup-y-hi; | ||
103 | st,wakeup-z-lo; | ||
104 | st,wakeup-z-hi; | ||
105 | st,min-limit-x = <120>; | ||
106 | st,min-limit-y = <120>; | ||
107 | st,min-limit-z = <140>; | ||
108 | st,max-limit-x = <550>; | ||
109 | st,max-limit-y = <550>; | ||
110 | st,max-limit-z = <750>; | ||
111 | }; | ||
112 | |||
diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt deleted file mode 100644 index 0a85c70cd30..00000000000 --- a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt +++ /dev/null | |||
@@ -1,68 +0,0 @@ | |||
1 | * Atmel High Speed MultiMedia Card Interface | ||
2 | |||
3 | This controller on atmel products provides an interface for MMC, SD and SDIO | ||
4 | types of memory cards. | ||
5 | |||
6 | This file documents differences between the core properties described | ||
7 | by mmc.txt and the properties used by the atmel-mci driver. | ||
8 | |||
9 | 1) MCI node | ||
10 | |||
11 | Required properties: | ||
12 | - compatible: should be "atmel,hsmci" | ||
13 | - #address-cells: should be one. The cell is the slot id. | ||
14 | - #size-cells: should be zero. | ||
15 | - at least one slot node | ||
16 | |||
17 | The node contains child nodes for each slot that the platform uses | ||
18 | |||
19 | Example MCI node: | ||
20 | |||
21 | mmc0: mmc@f0008000 { | ||
22 | compatible = "atmel,hsmci"; | ||
23 | reg = <0xf0008000 0x600>; | ||
24 | interrupts = <12 4>; | ||
25 | #address-cells = <1>; | ||
26 | #size-cells = <0>; | ||
27 | |||
28 | [ child node definitions...] | ||
29 | }; | ||
30 | |||
31 | 2) slot nodes | ||
32 | |||
33 | Required properties: | ||
34 | - reg: should contain the slot id. | ||
35 | - bus-width: number of data lines connected to the controller | ||
36 | |||
37 | Optional properties: | ||
38 | - cd-gpios: specify GPIOs for card detection | ||
39 | - cd-inverted: invert the value of external card detect gpio line | ||
40 | - wp-gpios: specify GPIOs for write protection | ||
41 | |||
42 | Example slot node: | ||
43 | |||
44 | slot@0 { | ||
45 | reg = <0>; | ||
46 | bus-width = <4>; | ||
47 | cd-gpios = <&pioD 15 0> | ||
48 | cd-inverted; | ||
49 | }; | ||
50 | |||
51 | Example full MCI node: | ||
52 | mmc0: mmc@f0008000 { | ||
53 | compatible = "atmel,hsmci"; | ||
54 | reg = <0xf0008000 0x600>; | ||
55 | interrupts = <12 4>; | ||
56 | #address-cells = <1>; | ||
57 | #size-cells = <0>; | ||
58 | slot@0 { | ||
59 | reg = <0>; | ||
60 | bus-width = <4>; | ||
61 | cd-gpios = <&pioD 15 0> | ||
62 | cd-inverted; | ||
63 | }; | ||
64 | slot@1 { | ||
65 | reg = <1>; | ||
66 | bus-width = <4>; | ||
67 | }; | ||
68 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt deleted file mode 100644 index 79276895333..00000000000 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ /dev/null | |||
@@ -1,87 +0,0 @@ | |||
1 | * Samsung Exynos specific extensions to the Synopsis Designware Mobile | ||
2 | Storage Host Controller | ||
3 | |||
4 | The Synopsis designware mobile storage host controller is used to interface | ||
5 | a SoC with storage medium such as eMMC or SD/MMC cards. This file documents | ||
6 | differences between the core Synopsis dw mshc controller properties described | ||
7 | by synposis-dw-mshc.txt and the properties used by the Samsung Exynos specific | ||
8 | extensions to the Synopsis Designware Mobile Storage Host Controller. | ||
9 | |||
10 | Required Properties: | ||
11 | |||
12 | * compatible: should be | ||
13 | - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210 | ||
14 | specific extentions. | ||
15 | - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412 | ||
16 | specific extentions. | ||
17 | - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 | ||
18 | specific extentions. | ||
19 | |||
20 | * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface | ||
21 | unit (ciu) clock. This property is applicable only for Exynos5 SoC's and | ||
22 | ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. | ||
23 | |||
24 | * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value | ||
25 | in transmit mode and CIU clock phase shift value in receive mode for single | ||
26 | data rate mode operation. Refer notes below for the order of the cells and the | ||
27 | valid values. | ||
28 | |||
29 | * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value | ||
30 | in transmit mode and CIU clock phase shift value in receive mode for double | ||
31 | data rate mode operation. Refer notes below for the order of the cells and the | ||
32 | valid values. | ||
33 | |||
34 | Notes for the sdr-timing and ddr-timing values: | ||
35 | |||
36 | The order of the cells should be | ||
37 | - First Cell: CIU clock phase shift value for tx mode. | ||
38 | - Second Cell: CIU clock phase shift value for rx mode. | ||
39 | |||
40 | Valid values for SDR and DDR CIU clock timing for Exynos5250: | ||
41 | - valid value for tx phase shift and rx phase shift is 0 to 7. | ||
42 | - when CIU clock divider value is set to 3, all possible 8 phase shift | ||
43 | values can be used. | ||
44 | - if CIU clock divider value is 0 (that is divide by 1), both tx and rx | ||
45 | phase shift clocks should be 0. | ||
46 | |||
47 | Required properties for a slot: | ||
48 | |||
49 | * gpios: specifies a list of gpios used for command, clock and data bus. The | ||
50 | first gpio is the command line and the second gpio is the clock line. The | ||
51 | rest of the gpios (depending on the bus-width property) are the data lines in | ||
52 | no particular order. The format of the gpio specifier depends on the gpio | ||
53 | controller. | ||
54 | |||
55 | Example: | ||
56 | |||
57 | The MSHC controller node can be split into two portions, SoC specific and | ||
58 | board specific portions as listed below. | ||
59 | |||
60 | dwmmc0@12200000 { | ||
61 | compatible = "samsung,exynos5250-dw-mshc"; | ||
62 | reg = <0x12200000 0x1000>; | ||
63 | interrupts = <0 75 0>; | ||
64 | #address-cells = <1>; | ||
65 | #size-cells = <0>; | ||
66 | }; | ||
67 | |||
68 | dwmmc0@12200000 { | ||
69 | num-slots = <1>; | ||
70 | supports-highspeed; | ||
71 | broken-cd; | ||
72 | fifo-depth = <0x80>; | ||
73 | card-detect-delay = <200>; | ||
74 | samsung,dw-mshc-ciu-div = <3>; | ||
75 | samsung,dw-mshc-sdr-timing = <2 3>; | ||
76 | samsung,dw-mshc-ddr-timing = <1 2>; | ||
77 | |||
78 | slot@0 { | ||
79 | reg = <0>; | ||
80 | bus-width = <8>; | ||
81 | gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>, | ||
82 | <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>, | ||
83 | <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>, | ||
84 | <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>, | ||
85 | <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>; | ||
86 | }; | ||
87 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt index bd9be0b5bc2..64bcb8be973 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | |||
@@ -3,22 +3,19 @@ | |||
3 | The Enhanced Secure Digital Host Controller provides an interface | 3 | The Enhanced Secure Digital Host Controller provides an interface |
4 | for MMC, SD, and SDIO types of memory cards. | 4 | for MMC, SD, and SDIO types of memory cards. |
5 | 5 | ||
6 | This file documents differences between the core properties described | ||
7 | by mmc.txt and the properties used by the sdhci-esdhc driver. | ||
8 | |||
9 | Required properties: | 6 | Required properties: |
7 | - compatible : should be | ||
8 | "fsl,<chip>-esdhc", "fsl,esdhc" | ||
9 | - reg : should contain eSDHC registers location and length. | ||
10 | - interrupts : should contain eSDHC interrupt. | ||
10 | - interrupt-parent : interrupt source phandle. | 11 | - interrupt-parent : interrupt source phandle. |
11 | - clock-frequency : specifies eSDHC base clock frequency. | 12 | - clock-frequency : specifies eSDHC base clock frequency. |
12 | 13 | - sdhci,wp-inverted : (optional) specifies that eSDHC controller | |
13 | Optional properties: | 14 | reports inverted write-protect state; |
14 | - sdhci,wp-inverted : specifies that eSDHC controller reports | 15 | - sdhci,1-bit-only : (optional) specifies that a controller can |
15 | inverted write-protect state; New devices should use the generic | 16 | only handle 1-bit data transfers. |
16 | "wp-inverted" property. | 17 | - sdhci,auto-cmd12: (optional) specifies that a controller can |
17 | - sdhci,1-bit-only : specifies that a controller can only handle | 18 | only handle auto CMD12. |
18 | 1-bit data transfers. New devices should use the generic | ||
19 | "bus-width = <1>" property. | ||
20 | - sdhci,auto-cmd12: specifies that a controller can only handle auto | ||
21 | CMD12. | ||
22 | 19 | ||
23 | Example: | 20 | Example: |
24 | 21 | ||
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 1dd622546d0..ab22fe6e73a 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | |||
@@ -3,15 +3,17 @@ | |||
3 | The Enhanced Secure Digital Host Controller on Freescale i.MX family | 3 | The Enhanced Secure Digital Host Controller on Freescale i.MX family |
4 | provides an interface for MMC, SD, and SDIO types of memory cards. | 4 | provides an interface for MMC, SD, and SDIO types of memory cards. |
5 | 5 | ||
6 | This file documents differences between the core properties described | ||
7 | by mmc.txt and the properties used by the sdhci-esdhc-imx driver. | ||
8 | |||
9 | Required properties: | 6 | Required properties: |
10 | - compatible : Should be "fsl,<chip>-esdhc" | 7 | - compatible : Should be "fsl,<chip>-esdhc" |
8 | - reg : Should contain eSDHC registers location and length | ||
9 | - interrupts : Should contain eSDHC interrupt | ||
11 | 10 | ||
12 | Optional properties: | 11 | Optional properties: |
13 | - fsl,cd-controller : Indicate to use controller internal card detection | 12 | - fsl,card-wired : Indicate the card is wired to host permanently |
14 | - fsl,wp-controller : Indicate to use controller internal write protection | 13 | - fsl,cd-internal : Indicate to use controller internal card detection |
14 | - fsl,wp-internal : Indicate to use controller internal write protection | ||
15 | - cd-gpios : Specify GPIOs for card detection | ||
16 | - wp-gpios : Specify GPIOs for write protection | ||
15 | 17 | ||
16 | Examples: | 18 | Examples: |
17 | 19 | ||
@@ -19,14 +21,14 @@ esdhc@70004000 { | |||
19 | compatible = "fsl,imx51-esdhc"; | 21 | compatible = "fsl,imx51-esdhc"; |
20 | reg = <0x70004000 0x4000>; | 22 | reg = <0x70004000 0x4000>; |
21 | interrupts = <1>; | 23 | interrupts = <1>; |
22 | fsl,cd-controller; | 24 | fsl,cd-internal; |
23 | fsl,wp-controller; | 25 | fsl,wp-internal; |
24 | }; | 26 | }; |
25 | 27 | ||
26 | esdhc@70008000 { | 28 | esdhc@70008000 { |
27 | compatible = "fsl,imx51-esdhc"; | 29 | compatible = "fsl,imx51-esdhc"; |
28 | reg = <0x70008000 0x4000>; | 30 | reg = <0x70008000 0x4000>; |
29 | interrupts = <2>; | 31 | interrupts = <2>; |
30 | cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */ | 32 | cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */ |
31 | wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */ | 33 | wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */ |
32 | }; | 34 | }; |
diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt index 0e5e2ec4001..89a0084df2f 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt +++ b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt | |||
@@ -1,9 +1,8 @@ | |||
1 | MMC/SD/SDIO slot directly connected to a SPI bus | 1 | MMC/SD/SDIO slot directly connected to a SPI bus |
2 | 2 | ||
3 | This file documents differences between the core properties described | ||
4 | by mmc.txt and the properties used by the mmc_spi driver. | ||
5 | |||
6 | Required properties: | 3 | Required properties: |
4 | - compatible : should be "mmc-spi-slot". | ||
5 | - reg : should specify SPI address (chip-select number). | ||
7 | - spi-max-frequency : maximum frequency for this device (Hz). | 6 | - spi-max-frequency : maximum frequency for this device (Hz). |
8 | - voltage-ranges : two cells are required, first cell specifies minimum | 7 | - voltage-ranges : two cells are required, first cell specifies minimum |
9 | slot voltage (mV), second cell specifies maximum slot voltage (mV). | 8 | slot voltage (mV), second cell specifies maximum slot voltage (mV). |
@@ -11,8 +10,8 @@ Required properties: | |||
11 | 10 | ||
12 | Optional properties: | 11 | Optional properties: |
13 | - gpios : may specify GPIOs in this order: Card-Detect GPIO, | 12 | - gpios : may specify GPIOs in this order: Card-Detect GPIO, |
14 | Write-Protect GPIO. Note that this does not follow the | 13 | Write-Protect GPIO. |
15 | binding from mmc.txt, for historical reasons. | 14 | - interrupts : the interrupt of a card detect interrupt. |
16 | - interrupt-parent : the phandle for the interrupt controller that | 15 | - interrupt-parent : the phandle for the interrupt controller that |
17 | services interrupts for this device. | 16 | services interrupts for this device. |
18 | 17 | ||
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt deleted file mode 100644 index a591c6741d7..00000000000 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ /dev/null | |||
@@ -1,44 +0,0 @@ | |||
1 | These properties are common to multiple MMC host controllers. Any host | ||
2 | that requires the respective functionality should implement them using | ||
3 | these definitions. | ||
4 | |||
5 | Interpreted by the OF core: | ||
6 | - reg: Registers location and length. | ||
7 | - interrupts: Interrupts used by the MMC controller. | ||
8 | |||
9 | Required properties: | ||
10 | - bus-width: Number of data lines, can be <1>, <4>, or <8> | ||
11 | |||
12 | Card detection: | ||
13 | If no property below is supplied, standard SDHCI card detect is used. | ||
14 | Only one of the properties in this section should be supplied: | ||
15 | - broken-cd: There is no card detection available; polling must be used. | ||
16 | - cd-gpios: Specify GPIOs for card detection, see gpio binding | ||
17 | - non-removable: non-removable slot (like eMMC); assume always present. | ||
18 | |||
19 | Optional properties: | ||
20 | - wp-gpios: Specify GPIOs for write protection, see gpio binding | ||
21 | - cd-inverted: when present, polarity on the cd gpio line is inverted | ||
22 | - wp-inverted: when present, polarity on the wp gpio line is inverted | ||
23 | - max-frequency: maximum operating clock frequency | ||
24 | - no-1-8-v: when present, denotes that 1.8v card voltage is not supported on | ||
25 | this system, even if the controller claims it is. | ||
26 | |||
27 | Optional SDIO properties: | ||
28 | - keep-power-in-suspend: Preserves card power during a suspend/resume cycle | ||
29 | - enable-sdio-wakeup: Enables wake up of host system on SDIO IRQ assertion | ||
30 | |||
31 | Example: | ||
32 | |||
33 | sdhci@ab000000 { | ||
34 | compatible = "sdhci"; | ||
35 | reg = <0xab000000 0x200>; | ||
36 | interrupts = <23>; | ||
37 | bus-width = <4>; | ||
38 | cd-gpios = <&gpio 69 0>; | ||
39 | cd-inverted; | ||
40 | wp-gpios = <&gpio 70 0>; | ||
41 | max-frequency = <50000000>; | ||
42 | keep-power-in-suspend; | ||
43 | enable-sdio-wakeup; | ||
44 | } | ||
diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt deleted file mode 100644 index 2b584cae352..00000000000 --- a/Documentation/devicetree/bindings/mmc/mmci.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | * ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1 | ||
2 | |||
3 | The ARM PrimeCell MMCI PL180 and PL181 provides an interface for | ||
4 | reading and writing to MultiMedia and SD cards alike. | ||
5 | |||
6 | This file documents differences between the core properties described | ||
7 | by mmc.txt and the properties used by the mmci driver. | ||
8 | |||
9 | Required properties: | ||
10 | - compatible : contains "arm,pl18x", "arm,primecell". | ||
11 | - arm,primecell-periphid : contains the PrimeCell Peripheral ID. | ||
12 | |||
13 | Optional properties: | ||
14 | - mmc-cap-mmc-highspeed : indicates whether MMC is high speed capable | ||
15 | - mmc-cap-sd-highspeed : indicates whether SD is high speed capable | ||
diff --git a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/mxs-mmc.txt deleted file mode 100644 index 54949f6faed..00000000000 --- a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | * Freescale MXS MMC controller | ||
2 | |||
3 | The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller | ||
4 | to support MMC, SD, and SDIO types of memory cards. | ||
5 | |||
6 | This file documents differences between the core properties in mmc.txt | ||
7 | and the properties used by the mxsmmc driver. | ||
8 | |||
9 | Required properties: | ||
10 | - compatible: Should be "fsl,<chip>-mmc". The supported chips include | ||
11 | imx23 and imx28. | ||
12 | - interrupts: Should contain ERROR and DMA interrupts | ||
13 | - fsl,ssp-dma-channel: APBH DMA channel for the SSP | ||
14 | |||
15 | Examples: | ||
16 | |||
17 | ssp0: ssp@80010000 { | ||
18 | compatible = "fsl,imx28-mmc"; | ||
19 | reg = <0x80010000 2000>; | ||
20 | interrupts = <96 82>; | ||
21 | fsl,ssp-dma-channel = <0>; | ||
22 | bus-width = <8>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt deleted file mode 100644 index c6d7b11db9e..00000000000 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * NVIDIA Tegra Secure Digital Host Controller | ||
2 | |||
3 | This controller on Tegra family SoCs provides an interface for MMC, SD, | ||
4 | and SDIO types of memory cards. | ||
5 | |||
6 | This file documents differences between the core properties described | ||
7 | by mmc.txt and the properties used by the sdhci-tegra driver. | ||
8 | |||
9 | Required properties: | ||
10 | - compatible : Should be "nvidia,<chip>-sdhci" | ||
11 | |||
12 | Optional properties: | ||
13 | - power-gpios : Specify GPIOs for power control | ||
14 | |||
15 | Example: | ||
16 | |||
17 | sdhci@c8000200 { | ||
18 | compatible = "nvidia,tegra20-sdhci"; | ||
19 | reg = <0xc8000200 0x200>; | ||
20 | interrupts = <47>; | ||
21 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | ||
22 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | ||
23 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ | ||
24 | bus-width = <8>; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/pxa-mmc.txt b/Documentation/devicetree/bindings/mmc/pxa-mmc.txt deleted file mode 100644 index b7025de7dce..00000000000 --- a/Documentation/devicetree/bindings/mmc/pxa-mmc.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * PXA MMC drivers | ||
2 | |||
3 | Driver bindings for the PXA MCI (MMC/SDIO) interfaces | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: Should be "marvell,pxa-mmc". | ||
7 | - vmmc-supply: A regulator for VMMC | ||
8 | |||
9 | Optional properties: | ||
10 | - marvell,detect-delay-ms: sets the detection delay timeout in ms. | ||
11 | - marvell,gpio-power: GPIO spec for the card power enable pin | ||
12 | |||
13 | This file documents differences between the core properties in mmc.txt | ||
14 | and the properties used by the pxa-mmc driver. | ||
15 | |||
16 | Examples: | ||
17 | |||
18 | mmc0: mmc@41100000 { | ||
19 | compatible = "marvell,pxa-mmc"; | ||
20 | reg = <0x41100000 0x1000>; | ||
21 | interrupts = <23>; | ||
22 | cd-gpios = <&gpio 23 0>; | ||
23 | wp-gpios = <&gpio 24 0>; | ||
24 | }; | ||
25 | |||
diff --git a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt deleted file mode 100644 index 97e9e315400..00000000000 --- a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt +++ /dev/null | |||
@@ -1,59 +0,0 @@ | |||
1 | * Samsung's SDHCI Controller device tree bindings | ||
2 | |||
3 | Samsung's SDHCI controller is used as a connectivity interface with external | ||
4 | MMC, SD and eMMC storage mediums. This file documents differences between the | ||
5 | core mmc properties described by mmc.txt and the properties used by the | ||
6 | Samsung implmentation of the SDHCI controller. | ||
7 | |||
8 | Note: The mmc core bindings documentation states that if none of the core | ||
9 | card-detect bindings are used, then the standard sdhci card detect mechanism | ||
10 | is used. The Samsung's SDHCI controller bindings extends this as listed below. | ||
11 | |||
12 | [A] The property "samsung,cd-pinmux-gpio" can be used as stated in the | ||
13 | "Optional Board Specific Properties" section below. | ||
14 | |||
15 | Required SoC Specific Properties: | ||
16 | - compatible: should be one of the following | ||
17 | - "samsung,s3c6410-sdhci": For controllers compatible with s3c6410 sdhci | ||
18 | controller. | ||
19 | - "samsung,exynos4210-sdhci": For controllers compatible with Exynos4 sdhci | ||
20 | controller. | ||
21 | |||
22 | Required Board Specific Properties: | ||
23 | - Samsung GPIO variant (will be completely replaced by pinctrl): | ||
24 | - gpios: Should specify the gpios used for clock, command and data lines. The | ||
25 | gpio specifier format depends on the gpio controller. | ||
26 | - Pinctrl variant (preferred if available): | ||
27 | - pinctrl-0: Should specify pin control groups used for this controller. | ||
28 | - pinctrl-names: Should contain only one value - "default". | ||
29 | |||
30 | Optional Board Specific Properties: | ||
31 | - samsung,cd-pinmux-gpio: Specifies the card detect line that is routed | ||
32 | through a pinmux to the card-detect pin of the card slot. This property | ||
33 | should be used only if none of the mmc core card-detect properties are | ||
34 | used. Only for Samsung GPIO variant. | ||
35 | |||
36 | Example: | ||
37 | sdhci@12530000 { | ||
38 | compatible = "samsung,exynos4210-sdhci"; | ||
39 | reg = <0x12530000 0x100>; | ||
40 | interrupts = <0 75 0>; | ||
41 | bus-width = <4>; | ||
42 | cd-gpios = <&gpk2 2 2 3 3>; | ||
43 | |||
44 | /* Samsung GPIO variant */ | ||
45 | gpios = <&gpk2 0 2 0 3>, /* clock line */ | ||
46 | <&gpk2 1 2 0 3>, /* command line */ | ||
47 | <&gpk2 3 2 3 3>, /* data line 0 */ | ||
48 | <&gpk2 4 2 3 3>, /* data line 1 */ | ||
49 | <&gpk2 5 2 3 3>, /* data line 2 */ | ||
50 | <&gpk2 6 2 3 3>; /* data line 3 */ | ||
51 | |||
52 | /* Pinctrl variant */ | ||
53 | pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; | ||
54 | pinctrl-names = "default"; | ||
55 | }; | ||
56 | |||
57 | Note: This example shows both SoC specific and board specific properties | ||
58 | in a single device node. The properties can be actually be seperated | ||
59 | into SoC specific node and board specific node. | ||
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-dove.txt b/Documentation/devicetree/bindings/mmc/sdhci-dove.txt deleted file mode 100644 index ae9aab9abcd..00000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-dove.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * Marvell sdhci-dove controller | ||
2 | |||
3 | This file documents differences between the core properties in mmc.txt | ||
4 | and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers. | ||
5 | |||
6 | - compatible: Should be "marvell,dove-sdhci". | ||
7 | |||
8 | Example: | ||
9 | |||
10 | sdio0: sdio@92000 { | ||
11 | compatible = "marvell,dove-sdhci"; | ||
12 | reg = <0x92000 0x100>; | ||
13 | interrupts = <35>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt deleted file mode 100644 index dbe98a3c183..00000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | * Marvell sdhci-pxa v2/v3 controller | ||
2 | |||
3 | This file documents differences between the core properties in mmc.txt | ||
4 | and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: Should be "mrvl,pxav2-mmc" or "mrvl,pxav3-mmc". | ||
8 | |||
9 | Optional properties: | ||
10 | - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | sdhci@d4280800 { | ||
15 | compatible = "mrvl,pxav3-mmc"; | ||
16 | reg = <0xd4280800 0x800>; | ||
17 | bus-width = <8>; | ||
18 | interrupts = <27>; | ||
19 | non-removable; | ||
20 | mrvl,clk-delay-cycles = <31>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-spear.txt b/Documentation/devicetree/bindings/mmc/sdhci-spear.txt deleted file mode 100644 index fd3643e7e46..00000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-spear.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | * SPEAr SDHCI Controller | ||
2 | |||
3 | This file documents differences between the core properties in mmc.txt | ||
4 | and the properties used by the sdhci-spear driver. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "st,spear300-sdhci" | ||
8 | |||
9 | Optional properties: | ||
10 | - cd-gpios: card detect gpio, with zero flags. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | sdhci@fc000000 { | ||
15 | compatible = "st,spear300-sdhci"; | ||
16 | reg = <0xfc000000 0x1000>; | ||
17 | cd-gpios = <&gpio0 6 0>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt deleted file mode 100644 index 06cd32d0805..00000000000 --- a/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +++ /dev/null | |||
@@ -1,79 +0,0 @@ | |||
1 | * Synopsis Designware Mobile Storage Host Controller | ||
2 | |||
3 | The Synopsis designware mobile storage host controller is used to interface | ||
4 | a SoC with storage medium such as eMMC or SD/MMC cards. This file documents | ||
5 | differences between the core mmc properties described by mmc.txt and the | ||
6 | properties used by the Synopsis Designware Mobile Storage Host Controller. | ||
7 | |||
8 | Required Properties: | ||
9 | |||
10 | * compatible: should be | ||
11 | - snps,dw-mshc: for controllers compliant with synopsis dw-mshc. | ||
12 | * #address-cells: should be 1. | ||
13 | * #size-cells: should be 0. | ||
14 | |||
15 | # Slots: The slot specific information are contained within child-nodes with | ||
16 | each child-node representing a supported slot. There should be atleast one | ||
17 | child node representing a card slot. The name of the child node representing | ||
18 | the slot is recommended to be slot@n where n is the unique number of the slot | ||
19 | connnected to the controller. The following are optional properties which | ||
20 | can be included in the slot child node. | ||
21 | |||
22 | * reg: specifies the physical slot number. The valid values of this | ||
23 | property is 0 to (num-slots -1), where num-slots is the value | ||
24 | specified by the num-slots property. | ||
25 | |||
26 | * bus-width: as documented in mmc core bindings. | ||
27 | |||
28 | * wp-gpios: specifies the write protect gpio line. The format of the | ||
29 | gpio specifier depends on the gpio controller. If the write-protect | ||
30 | line is not available, this property is optional. | ||
31 | |||
32 | Optional properties: | ||
33 | |||
34 | * num-slots: specifies the number of slots supported by the controller. | ||
35 | The number of physical slots actually used could be equal or less than the | ||
36 | value specified by num-slots. If this property is not specified, the value | ||
37 | of num-slot property is assumed to be 1. | ||
38 | |||
39 | * fifo-depth: The maximum size of the tx/rx fifo's. If this property is not | ||
40 | specified, the default value of the fifo size is determined from the | ||
41 | controller registers. | ||
42 | |||
43 | * card-detect-delay: Delay in milli-seconds before detecting card after card | ||
44 | insert event. The default value is 0. | ||
45 | |||
46 | * supports-highspeed: Enables support for high speed cards (upto 50MHz) | ||
47 | |||
48 | * broken-cd: as documented in mmc core bindings. | ||
49 | |||
50 | Aliases: | ||
51 | |||
52 | - All the MSHC controller nodes should be represented in the aliases node using | ||
53 | the following format 'mshc{n}' where n is a unique number for the alias. | ||
54 | |||
55 | Example: | ||
56 | |||
57 | The MSHC controller node can be split into two portions, SoC specific and | ||
58 | board specific portions as listed below. | ||
59 | |||
60 | dwmmc0@12200000 { | ||
61 | compatible = "snps,dw-mshc"; | ||
62 | reg = <0x12200000 0x1000>; | ||
63 | interrupts = <0 75 0>; | ||
64 | #address-cells = <1>; | ||
65 | #size-cells = <0>; | ||
66 | }; | ||
67 | |||
68 | dwmmc0@12200000 { | ||
69 | num-slots = <1>; | ||
70 | supports-highspeed; | ||
71 | broken-cd; | ||
72 | fifo-depth = <0x80>; | ||
73 | card-detect-delay = <200>; | ||
74 | |||
75 | slot@0 { | ||
76 | reg = <0>; | ||
77 | bus-width = <8>; | ||
78 | }; | ||
79 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt deleted file mode 100644 index ed271fc255b..00000000000 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | * TI Highspeed MMC host controller for OMAP | ||
2 | |||
3 | The Highspeed MMC Host Controller on TI OMAP family | ||
4 | provides an interface for MMC, SD, and SDIO types of memory cards. | ||
5 | |||
6 | This file documents differences between the core properties described | ||
7 | by mmc.txt and the properties used by the omap_hsmmc driver. | ||
8 | |||
9 | Required properties: | ||
10 | - compatible: | ||
11 | Should be "ti,omap2-hsmmc", for OMAP2 controllers | ||
12 | Should be "ti,omap3-hsmmc", for OMAP3 controllers | ||
13 | Should be "ti,omap4-hsmmc", for OMAP4 controllers | ||
14 | - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1 | ||
15 | |||
16 | Optional properties: | ||
17 | ti,dual-volt: boolean, supports dual voltage cards | ||
18 | <supply-name>-supply: phandle to the regulator device tree node | ||
19 | "supply-name" examples are "vmmc", "vmmc_aux" etc | ||
20 | ti,non-removable: non-removable slot (like eMMC) | ||
21 | ti,needs-special-reset: Requires a special softreset sequence | ||
22 | ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed | ||
23 | |||
24 | Example: | ||
25 | mmc1: mmc@0x4809c000 { | ||
26 | compatible = "ti,omap4-hsmmc"; | ||
27 | reg = <0x4809c000 0x400>; | ||
28 | ti,hwmods = "mmc1"; | ||
29 | ti,dual-volt; | ||
30 | bus-width = <4>; | ||
31 | vmmc-supply = <&vmmc>; /* phandle to regulator node */ | ||
32 | ti,non-removable; | ||
33 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt b/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt deleted file mode 100644 index d7fb6abb3eb..00000000000 --- a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | * Wondermedia WM8505/WM8650 SD/MMC Host Controller | ||
2 | |||
3 | This file documents differences between the core properties described | ||
4 | by mmc.txt and the properties used by the wmt-sdmmc driver. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: Should be "wm,wm8505-sdhc". | ||
8 | - interrupts: Two interrupts are required - regular irq and dma irq. | ||
9 | |||
10 | Optional properties: | ||
11 | - sdon-inverted: SD_ON bit is inverted on the controller | ||
12 | |||
13 | Examples: | ||
14 | |||
15 | sdhc@d800a000 { | ||
16 | compatible = "wm,wm8505-sdhc"; | ||
17 | reg = <0xd800a000 0x1000>; | ||
18 | interrupts = <20 21>; | ||
19 | clocks = <&sdhc>; | ||
20 | bus-width = <4>; | ||
21 | sdon-inverted; | ||
22 | }; | ||
23 | |||
diff --git a/Documentation/devicetree/bindings/mtd/arm-versatile.txt b/Documentation/devicetree/bindings/mtd/arm-versatile.txt index beace4b89da..476845db94d 100644 --- a/Documentation/devicetree/bindings/mtd/arm-versatile.txt +++ b/Documentation/devicetree/bindings/mtd/arm-versatile.txt | |||
@@ -4,5 +4,5 @@ Required properties: | |||
4 | - compatible : must be "arm,versatile-flash"; | 4 | - compatible : must be "arm,versatile-flash"; |
5 | - bank-width : width in bytes of flash interface. | 5 | - bank-width : width in bytes of flash interface. |
6 | 6 | ||
7 | The device tree may optionally contain sub-nodes describing partitions of the | 7 | Optional properties: |
8 | address space. See partition.txt for more detail. | 8 | - Subnode partition map from mtd flash binding |
diff --git a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt b/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt deleted file mode 100644 index 1889a4db5b7..00000000000 --- a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * Atmel Data Flash | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "atmel,<model>", "atmel,<series>", "atmel,dataflash". | ||
5 | |||
6 | The device tree may optionally contain sub-nodes describing partitions of the | ||
7 | address space. See partition.txt for more detail. | ||
8 | |||
9 | Example: | ||
10 | |||
11 | flash@1 { | ||
12 | #address-cells = <1>; | ||
13 | #size-cells = <1>; | ||
14 | compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; | ||
15 | spi-max-frequency = <25000000>; | ||
16 | reg = <1>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt deleted file mode 100644 index d555421ea49..00000000000 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ /dev/null | |||
@@ -1,79 +0,0 @@ | |||
1 | Atmel NAND flash | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "atmel,at91rm9200-nand". | ||
5 | - reg : should specify localbus address and size used for the chip, | ||
6 | and hardware ECC controller if available. | ||
7 | If the hardware ECC is PMECC, it should contain address and size for | ||
8 | PMECC, PMECC Error Location controller and ROM which has lookup tables. | ||
9 | - atmel,nand-addr-offset : offset for the address latch. | ||
10 | - atmel,nand-cmd-offset : offset for the command latch. | ||
11 | - #address-cells, #size-cells : Must be present if the device has sub-nodes | ||
12 | representing partitions. | ||
13 | |||
14 | - gpios : specifies the gpio pins to control the NAND device. detect is an | ||
15 | optional gpio and may be set to 0 if not present. | ||
16 | |||
17 | Optional properties: | ||
18 | - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default. | ||
19 | Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", | ||
20 | "soft_bch". | ||
21 | - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware. | ||
22 | Only supported by at91sam9x5 or later sam9 product. | ||
23 | - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC | ||
24 | Controller. Supported values are: 2, 4, 8, 12, 24. | ||
25 | - atmel,pmecc-sector-size : sector size for ECC computation. Supported values | ||
26 | are: 512, 1024. | ||
27 | - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM | ||
28 | for different sector size. First one is for sector size 512, the next is for | ||
29 | sector size 1024. | ||
30 | - nand-bus-width : 8 or 16 bus width if not present 8 | ||
31 | - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false | ||
32 | |||
33 | Examples: | ||
34 | nand0: nand@40000000,0 { | ||
35 | compatible = "atmel,at91rm9200-nand"; | ||
36 | #address-cells = <1>; | ||
37 | #size-cells = <1>; | ||
38 | reg = <0x40000000 0x10000000 | ||
39 | 0xffffe800 0x200 | ||
40 | >; | ||
41 | atmel,nand-addr-offset = <21>; /* ale */ | ||
42 | atmel,nand-cmd-offset = <22>; /* cle */ | ||
43 | nand-on-flash-bbt; | ||
44 | nand-ecc-mode = "soft"; | ||
45 | gpios = <&pioC 13 0 /* rdy */ | ||
46 | &pioC 14 0 /* nce */ | ||
47 | 0 /* cd */ | ||
48 | >; | ||
49 | partition@0 { | ||
50 | ... | ||
51 | }; | ||
52 | }; | ||
53 | |||
54 | /* for PMECC supported chips */ | ||
55 | nand0: nand@40000000 { | ||
56 | compatible = "atmel,at91rm9200-nand"; | ||
57 | #address-cells = <1>; | ||
58 | #size-cells = <1>; | ||
59 | reg = < 0x40000000 0x10000000 /* bus addr & size */ | ||
60 | 0xffffe000 0x00000600 /* PMECC addr & size */ | ||
61 | 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */ | ||
62 | 0x00100000 0x00100000 /* ROM addr & size */ | ||
63 | >; | ||
64 | atmel,nand-addr-offset = <21>; /* ale */ | ||
65 | atmel,nand-cmd-offset = <22>; /* cle */ | ||
66 | nand-on-flash-bbt; | ||
67 | nand-ecc-mode = "hw"; | ||
68 | atmel,has-pmecc; /* enable PMECC */ | ||
69 | atmel,pmecc-cap = <2>; | ||
70 | atmel,pmecc-sector-size = <512>; | ||
71 | atmel,pmecc-lookup-table-offset = <0x8000 0x10000>; | ||
72 | gpios = <&pioD 5 0 /* rdy */ | ||
73 | &pioD 4 0 /* nce */ | ||
74 | 0 /* cd */ | ||
75 | >; | ||
76 | partition@0 { | ||
77 | ... | ||
78 | }; | ||
79 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt deleted file mode 100644 index b04d03a1d49..00000000000 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | * Denali NAND controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "denali,denali-nand-dt" | ||
5 | - reg : should contain registers location and length for data and reg. | ||
6 | - reg-names: Should contain the reg names "nand_data" and "denali_reg" | ||
7 | - interrupts : The interrupt number. | ||
8 | - dm-mask : DMA bit mask | ||
9 | |||
10 | The device tree may optionally contain sub-nodes describing partitions of the | ||
11 | address space. See partition.txt for more detail. | ||
12 | |||
13 | Examples: | ||
14 | |||
15 | nand: nand@ff900000 { | ||
16 | #address-cells = <1>; | ||
17 | #size-cells = <1>; | ||
18 | compatible = "denali,denali-nand-dt"; | ||
19 | reg = <0xff900000 0x100000>, <0xffb80000 0x10000>; | ||
20 | reg-names = "nand_data", "denali_reg"; | ||
21 | interrupts = <0 144 4>; | ||
22 | dma-mask = <0xffffffff>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/flctl-nand.txt b/Documentation/devicetree/bindings/mtd/flctl-nand.txt deleted file mode 100644 index 427f46dc60a..00000000000 --- a/Documentation/devicetree/bindings/mtd/flctl-nand.txt +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | FLCTL NAND controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "renesas,shmobile-flctl-sh7372" | ||
5 | - reg : Address range of the FLCTL | ||
6 | - interrupts : flste IRQ number | ||
7 | - nand-bus-width : bus width to NAND chip | ||
8 | |||
9 | Optional properties: | ||
10 | - dmas: DMA specifier(s) | ||
11 | - dma-names: name for each DMA specifier. Valid names are | ||
12 | "data_tx", "data_rx", "ecc_tx", "ecc_rx" | ||
13 | |||
14 | The DMA fields are not used yet in the driver but are listed here for | ||
15 | completing the bindings. | ||
16 | |||
17 | The device tree may optionally contain sub-nodes describing partitions of the | ||
18 | address space. See partition.txt for more detail. | ||
19 | |||
20 | Example: | ||
21 | |||
22 | flctl@e6a30000 { | ||
23 | #address-cells = <1>; | ||
24 | #size-cells = <1>; | ||
25 | compatible = "renesas,shmobile-flctl-sh7372"; | ||
26 | reg = <0xe6a30000 0x100>; | ||
27 | interrupts = <0x0d80>; | ||
28 | |||
29 | nand-bus-width = <16>; | ||
30 | |||
31 | dmas = <&dmac 1 /* data_tx */ | ||
32 | &dmac 2;> /* data_rx */ | ||
33 | dma-names = "data_tx", "data_rx"; | ||
34 | |||
35 | system@0 { | ||
36 | label = "system"; | ||
37 | reg = <0x0 0x8000000>; | ||
38 | }; | ||
39 | |||
40 | userdata@8000000 { | ||
41 | label = "userdata"; | ||
42 | reg = <0x8000000 0x10000000>; | ||
43 | }; | ||
44 | |||
45 | cache@18000000 { | ||
46 | label = "cache"; | ||
47 | reg = <0x18000000 0x8000000>; | ||
48 | }; | ||
49 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt index fce4894f5a9..00f1f546b32 100644 --- a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt +++ b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt | |||
@@ -19,10 +19,6 @@ Optional properties: | |||
19 | read registers (tR). Required if property "gpios" is not used | 19 | read registers (tR). Required if property "gpios" is not used |
20 | (R/B# pins not connected). | 20 | (R/B# pins not connected). |
21 | 21 | ||
22 | Each flash chip described may optionally contain additional sub-nodes | ||
23 | describing partitions of the address space. See partition.txt for more | ||
24 | detail. | ||
25 | |||
26 | Examples: | 22 | Examples: |
27 | 23 | ||
28 | upm@1,0 { | 24 | upm@1,0 { |
diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt deleted file mode 100644 index e3ea32e7de3..00000000000 --- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | * FSMC NAND | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "st,spear600-fsmc-nand" | ||
5 | - reg : Address range of the mtd chip | ||
6 | - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd" | ||
7 | |||
8 | Optional properties: | ||
9 | - bank-width : Width (in bytes) of the device. If not present, the width | ||
10 | defaults to 1 byte | ||
11 | - nand-skip-bbtscan: Indicates the the BBT scanning should be skipped | ||
12 | |||
13 | Example: | ||
14 | |||
15 | fsmc: flash@d1800000 { | ||
16 | compatible = "st,spear600-fsmc-nand"; | ||
17 | #address-cells = <1>; | ||
18 | #size-cells = <1>; | ||
19 | reg = <0xd1800000 0x1000 /* FSMC Register */ | ||
20 | 0xd2000000 0x0010 /* NAND Base DATA */ | ||
21 | 0xd2020000 0x0010 /* NAND Base ADDR */ | ||
22 | 0xd2010000 0x0010>; /* NAND Base CMD */ | ||
23 | reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; | ||
24 | |||
25 | bank-width = <1>; | ||
26 | nand-skip-bbtscan; | ||
27 | |||
28 | partition@0 { | ||
29 | ... | ||
30 | }; | ||
31 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt deleted file mode 100644 index 36ef07d3c90..00000000000 --- a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | GPIO assisted NAND flash | ||
2 | |||
3 | The GPIO assisted NAND flash uses a memory mapped interface to | ||
4 | read/write the NAND commands and data and GPIO pins for the control | ||
5 | signals. | ||
6 | |||
7 | Required properties: | ||
8 | - compatible : "gpio-control-nand" | ||
9 | - reg : should specify localbus chip select and size used for the chip. The | ||
10 | resource describes the data bus connected to the NAND flash and all accesses | ||
11 | are made in native endianness. | ||
12 | - #address-cells, #size-cells : Must be present if the device has sub-nodes | ||
13 | representing partitions. | ||
14 | - gpios : specifies the gpio pins to control the NAND device. nwp is an | ||
15 | optional gpio and may be set to 0 if not present. | ||
16 | |||
17 | Optional properties: | ||
18 | - bank-width : Width (in bytes) of the device. If not present, the width | ||
19 | defaults to 1 byte. | ||
20 | - chip-delay : chip dependent delay for transferring data from array to | ||
21 | read registers (tR). If not present then a default of 20us is used. | ||
22 | - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read | ||
23 | location used to guard against bus reordering with regards to accesses to | ||
24 | the GPIO's and the NAND flash data bus. If present, then after changing | ||
25 | GPIO state and before and after command byte writes, this register will be | ||
26 | read to ensure that the GPIO accesses have completed. | ||
27 | |||
28 | The device tree may optionally contain sub-nodes describing partitions of the | ||
29 | address space. See partition.txt for more detail. | ||
30 | |||
31 | Examples: | ||
32 | |||
33 | gpio-nand@1,0 { | ||
34 | compatible = "gpio-control-nand"; | ||
35 | reg = <1 0x0000 0x2>; | ||
36 | #address-cells = <1>; | ||
37 | #size-cells = <1>; | ||
38 | gpios = <&banka 1 0 /* rdy */ | ||
39 | &banka 2 0 /* nce */ | ||
40 | &banka 3 0 /* ale */ | ||
41 | &banka 4 0 /* cle */ | ||
42 | 0 /* nwp */>; | ||
43 | |||
44 | partition@0 { | ||
45 | ... | ||
46 | }; | ||
47 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt deleted file mode 100644 index 3fb3f901536..00000000000 --- a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | * Freescale General-Purpose Media Interface (GPMI) | ||
2 | |||
3 | The GPMI nand controller provides an interface to control the | ||
4 | NAND flash chips. We support only one NAND chip now. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : should be "fsl,<chip>-gpmi-nand" | ||
8 | - reg : should contain registers location and length for gpmi and bch. | ||
9 | - reg-names: Should contain the reg names "gpmi-nand" and "bch" | ||
10 | - interrupts : The first is the DMA interrupt number for GPMI. | ||
11 | The second is the BCH interrupt number. | ||
12 | - interrupt-names : The interrupt names "gpmi-dma", "bch"; | ||
13 | - fsl,gpmi-dma-channel : Should contain the dma channel it uses. | ||
14 | |||
15 | Optional properties: | ||
16 | - nand-on-flash-bbt: boolean to enable on flash bbt option if not | ||
17 | present false | ||
18 | |||
19 | The device tree may optionally contain sub-nodes describing partitions of the | ||
20 | address space. See partition.txt for more detail. | ||
21 | |||
22 | Examples: | ||
23 | |||
24 | gpmi-nand@8000c000 { | ||
25 | compatible = "fsl,imx28-gpmi-nand"; | ||
26 | #address-cells = <1>; | ||
27 | #size-cells = <1>; | ||
28 | reg = <0x8000c000 2000>, <0x8000a000 2000>; | ||
29 | reg-names = "gpmi-nand", "bch"; | ||
30 | interrupts = <88>, <41>; | ||
31 | interrupt-names = "gpmi-dma", "bch"; | ||
32 | fsl,gpmi-dma-channel = <4>; | ||
33 | |||
34 | partition@0 { | ||
35 | ... | ||
36 | }; | ||
37 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt deleted file mode 100644 index d0a37252eb2..00000000000 --- a/Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | NXP LPC32xx SoC NAND MLC controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "nxp,lpc3220-mlc" | ||
5 | - reg: Address and size of the controller | ||
6 | - interrupts: The NAND interrupt specification | ||
7 | - gpios: GPIO specification for NAND write protect | ||
8 | |||
9 | The following required properties are very controller specific. See the LPC32xx | ||
10 | User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in | ||
11 | Hz, to make them independent of actual clock speed and to provide for good | ||
12 | accuracy:) | ||
13 | - nxp,tcea_delay: TCEA_DELAY | ||
14 | - nxp,busy_delay: BUSY_DELAY | ||
15 | - nxp,nand_ta: NAND_TA | ||
16 | - nxp,rd_high: RD_HIGH | ||
17 | - nxp,rd_low: RD_LOW | ||
18 | - nxp,wr_high: WR_HIGH | ||
19 | - nxp,wr_low: WR_LOW | ||
20 | |||
21 | Optional subnodes: | ||
22 | - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt | ||
23 | |||
24 | Example: | ||
25 | |||
26 | mlc: flash@200A8000 { | ||
27 | compatible = "nxp,lpc3220-mlc"; | ||
28 | reg = <0x200A8000 0x11000>; | ||
29 | interrupts = <11 0>; | ||
30 | #address-cells = <1>; | ||
31 | #size-cells = <1>; | ||
32 | |||
33 | nxp,tcea-delay = <333333333>; | ||
34 | nxp,busy-delay = <10000000>; | ||
35 | nxp,nand-ta = <18181818>; | ||
36 | nxp,rd-high = <31250000>; | ||
37 | nxp,rd-low = <45454545>; | ||
38 | nxp,wr-high = <40000000>; | ||
39 | nxp,wr-low = <83333333>; | ||
40 | gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ | ||
41 | |||
42 | mtd0@00000000 { | ||
43 | label = "boot"; | ||
44 | reg = <0x00000000 0x00064000>; | ||
45 | read-only; | ||
46 | }; | ||
47 | |||
48 | ... | ||
49 | |||
50 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt b/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt deleted file mode 100644 index d94edc0fc55..00000000000 --- a/Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | NXP LPC32xx SoC NAND SLC controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "nxp,lpc3220-slc" | ||
5 | - reg: Address and size of the controller | ||
6 | - nand-on-flash-bbt: Use bad block table on flash | ||
7 | - gpios: GPIO specification for NAND write protect | ||
8 | |||
9 | The following required properties are very controller specific. See the LPC32xx | ||
10 | User Manual: | ||
11 | - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY) | ||
12 | - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY) | ||
13 | (The following values are specified in Hz, to make them independent of actual | ||
14 | clock speed:) | ||
15 | - nxp,wwidth: Write pulse width (W_WIDTH) | ||
16 | - nxp,whold: Write hold time (W_HOLD) | ||
17 | - nxp,wsetup: Write setup time (W_SETUP) | ||
18 | - nxp,rwidth: Read pulse width (R_WIDTH) | ||
19 | - nxp,rhold: Read hold time (R_HOLD) | ||
20 | - nxp,rsetup: Read setup time (R_SETUP) | ||
21 | |||
22 | Optional subnodes: | ||
23 | - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt | ||
24 | |||
25 | Example: | ||
26 | |||
27 | slc: flash@20020000 { | ||
28 | compatible = "nxp,lpc3220-slc"; | ||
29 | reg = <0x20020000 0x1000>; | ||
30 | #address-cells = <1>; | ||
31 | #size-cells = <1>; | ||
32 | |||
33 | nxp,wdr-clks = <14>; | ||
34 | nxp,wwidth = <40000000>; | ||
35 | nxp,whold = <100000000>; | ||
36 | nxp,wsetup = <100000000>; | ||
37 | nxp,rdr-clks = <14>; | ||
38 | nxp,rwidth = <40000000>; | ||
39 | nxp,rhold = <66666666>; | ||
40 | nxp,rsetup = <100000000>; | ||
41 | nand-on-flash-bbt; | ||
42 | gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ | ||
43 | |||
44 | mtd0@00000000 { | ||
45 | label = "phy3250-boot"; | ||
46 | reg = <0x00000000 0x00064000>; | ||
47 | read-only; | ||
48 | }; | ||
49 | |||
50 | ... | ||
51 | |||
52 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt b/Documentation/devicetree/bindings/mtd/m25p80.txt deleted file mode 100644 index 6d3d5760947..00000000000 --- a/Documentation/devicetree/bindings/mtd/m25p80.txt +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips | ||
2 | |||
3 | Required properties: | ||
4 | - #address-cells, #size-cells : Must be present if the device has sub-nodes | ||
5 | representing partitions. | ||
6 | - compatible : Should be the manufacturer and the name of the chip. Bear in mind | ||
7 | the DT binding is not Linux-only, but in case of Linux, see the | ||
8 | "m25p_ids" table in drivers/mtd/devices/m25p80.c for the list of | ||
9 | supported chips. | ||
10 | - reg : Chip-Select number | ||
11 | - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at | ||
12 | |||
13 | Optional properties: | ||
14 | - m25p,fast-read : Use the "fast read" opcode to read data from the chip instead | ||
15 | of the usual "read" opcode. This opcode is not supported by | ||
16 | all chips and support for it can not be detected at runtime. | ||
17 | Refer to your chips' datasheet to check if this is supported | ||
18 | by your chip. | ||
19 | |||
20 | Example: | ||
21 | |||
22 | flash: m25p80@0 { | ||
23 | #address-cells = <1>; | ||
24 | #size-cells = <1>; | ||
25 | compatible = "spansion,m25p80"; | ||
26 | reg = <0>; | ||
27 | spi-max-frequency = <40000000>; | ||
28 | m25p,fast-read; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt index dab7847fc80..80152cb567d 100644 --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt | |||
@@ -16,16 +16,6 @@ file systems on embedded devices. | |||
16 | - #address-cells, #size-cells : Must be present if the device has | 16 | - #address-cells, #size-cells : Must be present if the device has |
17 | sub-nodes representing partitions (see below). In this case | 17 | sub-nodes representing partitions (see below). In this case |
18 | both #address-cells and #size-cells must be equal to 1. | 18 | both #address-cells and #size-cells must be equal to 1. |
19 | - no-unaligned-direct-access: boolean to disable the default direct | ||
20 | mapping of the flash. | ||
21 | On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause | ||
22 | problems with JFFS2 usage, as the local bus (LPB) doesn't support | ||
23 | unaligned accesses as implemented in the JFFS2 code via memcpy(). | ||
24 | By defining "no-unaligned-direct-access", the flash will not be | ||
25 | exposed directly to the MTD users (e.g. JFFS2) any more. | ||
26 | - linux,mtd-name: allow to specify the mtd name for retro capability with | ||
27 | physmap-flash drivers as boot loader pass the mtd partition via the old | ||
28 | device name physmap-flash. | ||
29 | 19 | ||
30 | For JEDEC compatible devices, the following additional properties | 20 | For JEDEC compatible devices, the following additional properties |
31 | are defined: | 21 | are defined: |
@@ -33,8 +23,27 @@ are defined: | |||
33 | - vendor-id : Contains the flash chip's vendor id (1 byte). | 23 | - vendor-id : Contains the flash chip's vendor id (1 byte). |
34 | - device-id : Contains the flash chip's device id (1 byte). | 24 | - device-id : Contains the flash chip's device id (1 byte). |
35 | 25 | ||
36 | The device tree may optionally contain sub-nodes describing partitions of the | 26 | In addition to the information on the mtd bank itself, the |
37 | address space. See partition.txt for more detail. | 27 | device tree may optionally contain additional information |
28 | describing partitions of the address space. This can be | ||
29 | used on platforms which have strong conventions about which | ||
30 | portions of a flash are used for what purposes, but which don't | ||
31 | use an on-flash partition table such as RedBoot. | ||
32 | |||
33 | Each partition is represented as a sub-node of the mtd device. | ||
34 | Each node's name represents the name of the corresponding | ||
35 | partition of the mtd device. | ||
36 | |||
37 | Flash partitions | ||
38 | - reg : The partition's offset and size within the mtd bank. | ||
39 | - label : (optional) The label / name for this partition. | ||
40 | If omitted, the label is taken from the node name (excluding | ||
41 | the unit address). | ||
42 | - read-only : (optional) This parameter, if present, is a hint to | ||
43 | Linux that this partition should only be mounted | ||
44 | read-only. This is usually used for flash partitions | ||
45 | containing early-boot firmware images or data which should not | ||
46 | be clobbered. | ||
38 | 47 | ||
39 | Example: | 48 | Example: |
40 | 49 | ||
diff --git a/Documentation/devicetree/bindings/mtd/mxc-nand.txt b/Documentation/devicetree/bindings/mtd/mxc-nand.txt deleted file mode 100644 index b5833d11c7b..00000000000 --- a/Documentation/devicetree/bindings/mtd/mxc-nand.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | * Freescale's mxc_nand | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "fsl,imxXX-nand" | ||
5 | - reg: address range of the nfc block | ||
6 | - interrupts: irq to be used | ||
7 | - nand-bus-width: see nand.txt | ||
8 | - nand-ecc-mode: see nand.txt | ||
9 | - nand-on-flash-bbt: see nand.txt | ||
10 | |||
11 | Example: | ||
12 | |||
13 | nand@d8000000 { | ||
14 | compatible = "fsl,imx27-nand"; | ||
15 | reg = <0xd8000000 0x1000>; | ||
16 | interrupts = <29>; | ||
17 | nand-bus-width = <8>; | ||
18 | nand-ecc-mode = "hw"; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt deleted file mode 100644 index 03855c8c492..00000000000 --- a/Documentation/devicetree/bindings/mtd/nand.txt +++ /dev/null | |||
@@ -1,7 +0,0 @@ | |||
1 | * MTD generic binding | ||
2 | |||
3 | - nand-ecc-mode : String, operation mode of the NAND ecc mode. | ||
4 | Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", | ||
5 | "soft_bch". | ||
6 | - nand-bus-width : 8 or 16 bus width if not present 8 | ||
7 | - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false | ||
diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt deleted file mode 100644 index 2d6ab660e60..00000000000 --- a/Documentation/devicetree/bindings/mtd/orion-nand.txt +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | NAND support for Marvell Orion SoC platforms | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "marvell,orion-nand". | ||
5 | - reg : Base physical address of the NAND and length of memory mapped | ||
6 | region | ||
7 | |||
8 | Optional properties: | ||
9 | - cle : Address line number connected to CLE. Default is 0 | ||
10 | - ale : Address line number connected to ALE. Default is 1 | ||
11 | - bank-width : Width in bytes of the device. Default is 1 | ||
12 | - chip-delay : Chip dependent delay for transferring data from array to read | ||
13 | registers in usecs | ||
14 | |||
15 | The device tree may optionally contain sub-nodes describing partitions of the | ||
16 | address space. See partition.txt for more detail. | ||
17 | |||
18 | Example: | ||
19 | |||
20 | nand@f4000000 { | ||
21 | #address-cells = <1>; | ||
22 | #size-cells = <1>; | ||
23 | cle = <0>; | ||
24 | ale = <1>; | ||
25 | bank-width = <1>; | ||
26 | chip-delay = <25>; | ||
27 | compatible = "marvell,orion-nand"; | ||
28 | reg = <0xf4000000 0x400>; | ||
29 | |||
30 | partition@0 { | ||
31 | label = "u-boot"; | ||
32 | reg = <0x0000000 0x100000>; | ||
33 | read-only; | ||
34 | }; | ||
35 | |||
36 | partition@100000 { | ||
37 | label = "uImage"; | ||
38 | reg = <0x0100000 0x200000>; | ||
39 | }; | ||
40 | |||
41 | partition@300000 { | ||
42 | label = "dtb"; | ||
43 | reg = <0x0300000 0x100000>; | ||
44 | }; | ||
45 | |||
46 | partition@400000 { | ||
47 | label = "root"; | ||
48 | reg = <0x0400000 0x7d00000>; | ||
49 | }; | ||
50 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt deleted file mode 100644 index 6e1f61f1e78..00000000000 --- a/Documentation/devicetree/bindings/mtd/partition.txt +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | Representing flash partitions in devicetree | ||
2 | |||
3 | Partitions can be represented by sub-nodes of an mtd device. This can be used | ||
4 | on platforms which have strong conventions about which portions of a flash are | ||
5 | used for what purposes, but which don't use an on-flash partition table such | ||
6 | as RedBoot. | ||
7 | |||
8 | #address-cells & #size-cells must both be present in the mtd device and be | ||
9 | equal to 1. | ||
10 | |||
11 | Required properties: | ||
12 | - reg : The partition's offset and size within the mtd bank. | ||
13 | |||
14 | Optional properties: | ||
15 | - label : The label / name for this partition. If omitted, the label is taken | ||
16 | from the node name (excluding the unit address). | ||
17 | - read-only : This parameter, if present, is a hint to Linux that this | ||
18 | partition should only be mounted read-only. This is usually used for flash | ||
19 | partitions containing early-boot firmware images or data which should not be | ||
20 | clobbered. | ||
21 | |||
22 | Examples: | ||
23 | |||
24 | |||
25 | flash@0 { | ||
26 | #address-cells = <1>; | ||
27 | #size-cells = <1>; | ||
28 | |||
29 | partition@0 { | ||
30 | label = "u-boot"; | ||
31 | reg = <0x0000000 0x100000>; | ||
32 | read-only; | ||
33 | }; | ||
34 | |||
35 | uimage@100000 { | ||
36 | reg = <0x0100000 0x200000>; | ||
37 | }; | ||
38 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt deleted file mode 100644 index f1421e2bbab..00000000000 --- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | PXA3xx NAND DT bindings | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible: Should be "marvell,pxa3xx-nand" | ||
6 | - reg: The register base for the controller | ||
7 | - interrupts: The interrupt to map | ||
8 | - #address-cells: Set to <1> if the node includes partitions | ||
9 | |||
10 | Optional properties: | ||
11 | |||
12 | - marvell,nand-enable-arbiter: Set to enable the bus arbiter | ||
13 | - marvell,nand-keep-config: Set to keep the NAND controller config as set | ||
14 | by the bootloader | ||
15 | - num-cs: Number of chipselect lines to usw | ||
16 | |||
17 | Example: | ||
18 | |||
19 | nand0: nand@43100000 { | ||
20 | compatible = "marvell,pxa3xx-nand"; | ||
21 | reg = <0x43100000 90>; | ||
22 | interrupts = <45>; | ||
23 | #address-cells = <1>; | ||
24 | |||
25 | marvell,nand-enable-arbiter; | ||
26 | marvell,nand-keep-config; | ||
27 | num-cs = <1>; | ||
28 | |||
29 | /* partitions (optional) */ | ||
30 | }; | ||
31 | |||
diff --git a/Documentation/devicetree/bindings/mtd/spear_smi.txt b/Documentation/devicetree/bindings/mtd/spear_smi.txt deleted file mode 100644 index 7248aadd89e..00000000000 --- a/Documentation/devicetree/bindings/mtd/spear_smi.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | * SPEAr SMI | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "st,spear600-smi" | ||
5 | - reg : Address range of the mtd chip | ||
6 | - #address-cells, #size-cells : Must be present if the device has sub-nodes | ||
7 | representing partitions. | ||
8 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
9 | that services interrupts for this device | ||
10 | - interrupts: Should contain the STMMAC interrupts | ||
11 | - clock-rate : Functional clock rate of SMI in Hz | ||
12 | |||
13 | Optional properties: | ||
14 | - st,smi-fast-mode : Flash supports read in fast mode | ||
15 | |||
16 | Example: | ||
17 | |||
18 | smi: flash@fc000000 { | ||
19 | compatible = "st,spear600-smi"; | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <1>; | ||
22 | reg = <0xfc000000 0x1000>; | ||
23 | interrupt-parent = <&vic1>; | ||
24 | interrupts = <12>; | ||
25 | clock-rate = <50000000>; /* 50MHz */ | ||
26 | |||
27 | flash@f8000000 { | ||
28 | st,smi-fast-mode; | ||
29 | ... | ||
30 | }; | ||
31 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt b/Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt deleted file mode 100644 index 7c86d5e28a0..00000000000 --- a/Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | The Broadcom BCM87XX devices are a family of 10G Ethernet PHYs. They | ||
2 | have these bindings in addition to the standard PHY bindings. | ||
3 | |||
4 | Compatible: Should contain "broadcom,bcm8706" or "broadcom,bcm8727" and | ||
5 | "ethernet-phy-ieee802.3-c45" | ||
6 | |||
7 | Optional Properties: | ||
8 | |||
9 | - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell | ||
10 | is the MDIO Manageable Device (MMD) address, the second a register | ||
11 | address within the MMD, the third cell contains a mask to be ANDed | ||
12 | with the existing register value, and the fourth cell is ORed with | ||
13 | he result to yield the new register value. If the third cell has a | ||
14 | value of zero, no read of the existing value is performed. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | ethernet-phy@5 { | ||
19 | reg = <5>; | ||
20 | compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45"; | ||
21 | interrupt-parent = <&gpio>; | ||
22 | interrupts = <12 8>; /* Pin 12, active low */ | ||
23 | /* | ||
24 | * Set PMD Digital Control Register for | ||
25 | * GPIO[1] Tx/Rx | ||
26 | * GPIO[0] R64 Sync Acquired | ||
27 | */ | ||
28 | broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt deleted file mode 100644 index c8ae996bd8f..00000000000 --- a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | * Calxeda Highbank 10Gb XGMAC Ethernet | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "calxeda,hb-xgmac" | ||
5 | - reg : Address and length of the register set for the device | ||
6 | - interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt. | ||
7 | The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt. | ||
8 | |||
9 | Optional properties: | ||
10 | - dma-coherent : Present if dma operations are coherent | ||
11 | |||
12 | Example: | ||
13 | |||
14 | ethernet@fff50000 { | ||
15 | compatible = "calxeda,hb-xgmac"; | ||
16 | reg = <0xfff50000 0x1000>; | ||
17 | interrupts = <0 77 4 0 78 4 0 79 4>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt deleted file mode 100644 index 8f1ae81228e..00000000000 --- a/Documentation/devicetree/bindings/net/can/c_can.txt +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | Bosch C_CAN/D_CAN controller Device Tree Bindings | ||
2 | ------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : Should be "bosch,c_can" for C_CAN controllers and | ||
6 | "bosch,d_can" for D_CAN controllers. | ||
7 | - reg : physical base address and size of the C_CAN/D_CAN | ||
8 | registers map | ||
9 | - interrupts : property with a value describing the interrupt | ||
10 | number | ||
11 | |||
12 | Optional properties: | ||
13 | - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the | ||
14 | instance number | ||
15 | |||
16 | Note: "ti,hwmods" field is used to fetch the base address and irq | ||
17 | resources from TI, omap hwmod data base during device registration. | ||
18 | Future plan is to migrate hwmod data base contents into device tree | ||
19 | blob so that, all the required data will be used from device tree dts | ||
20 | file. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | Step1: SoC common .dtsi file | ||
25 | |||
26 | dcan1: d_can@481d0000 { | ||
27 | compatible = "bosch,d_can"; | ||
28 | reg = <0x481d0000 0x2000>; | ||
29 | interrupts = <55>; | ||
30 | interrupt-parent = <&intc>; | ||
31 | status = "disabled"; | ||
32 | }; | ||
33 | |||
34 | (or) | ||
35 | |||
36 | dcan1: d_can@481d0000 { | ||
37 | compatible = "bosch,d_can"; | ||
38 | ti,hwmods = "d_can1"; | ||
39 | reg = <0x481d0000 0x2000>; | ||
40 | interrupts = <55>; | ||
41 | interrupt-parent = <&intc>; | ||
42 | status = "disabled"; | ||
43 | }; | ||
44 | |||
45 | Step 2: board specific .dts file | ||
46 | |||
47 | &dcan1 { | ||
48 | status = "okay"; | ||
49 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/can/cc770.txt b/Documentation/devicetree/bindings/net/can/cc770.txt deleted file mode 100644 index 77027bf6460..00000000000 --- a/Documentation/devicetree/bindings/net/can/cc770.txt +++ /dev/null | |||
@@ -1,53 +0,0 @@ | |||
1 | Memory mapped Bosch CC770 and Intel AN82527 CAN controller | ||
2 | |||
3 | Note: The CC770 is a CAN controller from Bosch, which is 100% | ||
4 | compatible with the old AN82527 from Intel, but with "bugs" being fixed. | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : should be "bosch,cc770" for the CC770 and "intc,82527" | ||
9 | for the AN82527. | ||
10 | |||
11 | - reg : should specify the chip select, address offset and size required | ||
12 | to map the registers of the controller. The size is usually 0x80. | ||
13 | |||
14 | - interrupts : property with a value describing the interrupt source | ||
15 | (number and sensitivity) required for the controller. | ||
16 | |||
17 | Optional properties: | ||
18 | |||
19 | - bosch,external-clock-frequency : frequency of the external oscillator | ||
20 | clock in Hz. Note that the internal clock frequency used by the | ||
21 | controller is half of that value. If not specified, a default | ||
22 | value of 16000000 (16 MHz) is used. | ||
23 | |||
24 | - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin. | ||
25 | If not specified or if the specified value is 0, the CLKOUT pin | ||
26 | will be disabled. | ||
27 | |||
28 | - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified, | ||
29 | a resonable value will be calculated. | ||
30 | |||
31 | - bosch,disconnect-rx0-input : see data sheet. | ||
32 | |||
33 | - bosch,disconnect-rx1-input : see data sheet. | ||
34 | |||
35 | - bosch,disconnect-tx1-output : see data sheet. | ||
36 | |||
37 | - bosch,polarity-dominant : see data sheet. | ||
38 | |||
39 | - bosch,divide-memory-clock : see data sheet. | ||
40 | |||
41 | - bosch,iso-low-speed-mux : see data sheet. | ||
42 | |||
43 | For further information, please have a look to the CC770 or AN82527. | ||
44 | |||
45 | Examples: | ||
46 | |||
47 | can@3,100 { | ||
48 | compatible = "bosch,cc770"; | ||
49 | reg = <3 0x100 0x80>; | ||
50 | interrupts = <2 0>; | ||
51 | interrupt-parent = <&mpic>; | ||
52 | bosch,external-clock-frequency = <16000000>; | ||
53 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index 8ff324eaa88..1a729f08986 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt | |||
@@ -1,27 +1,61 @@ | |||
1 | Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC). | 1 | CAN Device Tree Bindings |
2 | 2 | ------------------------ | |
3 | Required properties: | 3 | 2011 Freescale Semiconductor, Inc. |
4 | 4 | ||
5 | - compatible : Should be "fsl,<processor>-flexcan" | 5 | fsl,flexcan-v1.0 nodes |
6 | 6 | ----------------------- | |
7 | An implementation should also claim any of the following compatibles | 7 | In addition to the required compatible-, reg- and interrupt-properties, you can |
8 | that it is fully backwards compatible with: | 8 | also specify which clock source shall be used for the controller. |
9 | 9 | ||
10 | - fsl,p1010-flexcan | 10 | CPI Clock- Can Protocol Interface Clock |
11 | 11 | This CLK_SRC bit of CTRL(control register) selects the clock source to | |
12 | - reg : Offset and length of the register set for this device | 12 | the CAN Protocol Interface(CPI) to be either the peripheral clock |
13 | - interrupts : Interrupt tuple for this device | 13 | (driven by the PLL) or the crystal oscillator clock. The selected clock |
14 | 14 | is the one fed to the prescaler to generate the Serial Clock (Sclock). | |
15 | Optional properties: | 15 | The PRESDIV field of CTRL(control register) controls a prescaler that |
16 | 16 | generates the Serial Clock (Sclock), whose period defines the | |
17 | - clock-frequency : The oscillator frequency driving the flexcan device | 17 | time quantum used to compose the CAN waveform. |
18 | 18 | ||
19 | Example: | 19 | Can Engine Clock Source |
20 | 20 | There are two sources for CAN clock | |
21 | can@1c000 { | 21 | - Platform Clock It represents the bus clock |
22 | compatible = "fsl,p1010-flexcan"; | 22 | - Oscillator Clock |
23 | |||
24 | Peripheral Clock (PLL) | ||
25 | -------------- | ||
26 | | | ||
27 | --------- ------------- | ||
28 | | |CPI Clock | Prescaler | Sclock | ||
29 | | |---------------->| (1.. 256) |------------> | ||
30 | --------- ------------- | ||
31 | | | | ||
32 | -------------- ---------------------CLK_SRC | ||
33 | Oscillator Clock | ||
34 | |||
35 | - fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects | ||
36 | the peripheral clock. PLL clock is fed to the | ||
37 | prescaler to generate the Serial Clock (Sclock). | ||
38 | Valid values are "oscillator" and "platform" | ||
39 | "oscillator": CAN engine clock source is oscillator clock. | ||
40 | "platform" The CAN engine clock source is the bus clock | ||
41 | (platform clock). | ||
42 | |||
43 | - fsl,flexcan-clock-divider : for the reference and system clock, an additional | ||
44 | clock divider can be specified. | ||
45 | - clock-frequency: frequency required to calculate the bitrate for FlexCAN. | ||
46 | |||
47 | Note: | ||
48 | - v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC. | ||
49 | - P1010 does not have oscillator as the Clock Source.So the default | ||
50 | Clock Source is platform clock. | ||
51 | Examples: | ||
52 | |||
53 | can0@1c000 { | ||
54 | compatible = "fsl,flexcan-v1.0"; | ||
23 | reg = <0x1c000 0x1000>; | 55 | reg = <0x1c000 0x1000>; |
24 | interrupts = <48 0x2>; | 56 | interrupts = <48 0x2>; |
25 | interrupt-parent = <&mpic>; | 57 | interrupt-parent = <&mpic>; |
26 | clock-frequency = <200000000>; // filled in by bootloader | 58 | fsl,flexcan-clock-source = "platform"; |
59 | fsl,flexcan-clock-divider = <2>; | ||
60 | clock-frequency = <fixed by u-boot>; | ||
27 | }; | 61 | }; |
diff --git a/Documentation/devicetree/bindings/net/can/grcan.txt b/Documentation/devicetree/bindings/net/can/grcan.txt deleted file mode 100644 index 34ef3498f88..00000000000 --- a/Documentation/devicetree/bindings/net/can/grcan.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | Aeroflex Gaisler GRCAN and GRHCAN CAN controllers. | ||
2 | |||
3 | The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core | ||
4 | library. | ||
5 | |||
6 | Note: These properties are built from the AMBA plug&play in a Leon SPARC system | ||
7 | (the ordinary environment for GRCAN and GRHCAN). There are no dts files for | ||
8 | sparc. | ||
9 | |||
10 | Required properties: | ||
11 | |||
12 | - name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034" | ||
13 | |||
14 | - reg : Address and length of the register set for the device | ||
15 | |||
16 | - freq : Frequency of the external oscillator clock in Hz (the frequency of | ||
17 | the amba bus in the ordinary case) | ||
18 | |||
19 | - interrupts : Interrupt number for this device | ||
20 | |||
21 | Optional properties: | ||
22 | |||
23 | - systemid : If not present or if the value of the least significant 16 bits | ||
24 | of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION | ||
25 | a bug workaround is activated. | ||
26 | |||
27 | For further information look in the documentation for the GLIB IP core library: | ||
28 | http://www.gaisler.com/products/grlib/grip.pdf | ||
diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt deleted file mode 100644 index 04cb7491d23..00000000000 --- a/Documentation/devicetree/bindings/net/cavium-mdio.txt +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | * System Management Interface (SMI) / MDIO | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-3860-mdio" | ||
5 | |||
6 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
7 | |||
8 | - reg: The base address of the MDIO bus controller register bank. | ||
9 | |||
10 | - #address-cells: Must be <1>. | ||
11 | |||
12 | - #size-cells: Must be <0>. MDIO addresses have no size component. | ||
13 | |||
14 | Typically an MDIO bus might have several children. | ||
15 | |||
16 | Example: | ||
17 | mdio@1180000001800 { | ||
18 | compatible = "cavium,octeon-3860-mdio"; | ||
19 | #address-cells = <1>; | ||
20 | #size-cells = <0>; | ||
21 | reg = <0x11800 0x00001800 0x0 0x40>; | ||
22 | |||
23 | ethernet-phy@0 { | ||
24 | ... | ||
25 | reg = <0>; | ||
26 | }; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt deleted file mode 100644 index 5da628db68b..00000000000 --- a/Documentation/devicetree/bindings/net/cavium-mix.txt +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | * MIX Ethernet controller. | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-5750-mix" | ||
5 | |||
6 | Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX | ||
7 | devices. | ||
8 | |||
9 | - reg: The base addresses of four separate register banks. The first | ||
10 | bank contains the MIX registers. The second bank the corresponding | ||
11 | AGL registers. The third bank are the AGL registers shared by all | ||
12 | MIX devices present. The fourth bank is the AGL_PRT_CTL shared by | ||
13 | all MIX devices present. | ||
14 | |||
15 | - cell-index: A single cell specifying which portion of the shared | ||
16 | register banks corresponds to this MIX device. | ||
17 | |||
18 | - interrupts: Two interrupt specifiers. The first is the MIX | ||
19 | interrupt routing and the second the routing for the AGL interrupts. | ||
20 | |||
21 | - mac-address: Optional, the MAC address to assign to the device. | ||
22 | |||
23 | - local-mac-address: Optional, the MAC address to assign to the device | ||
24 | if mac-address is not specified. | ||
25 | |||
26 | - phy-handle: Optional, a phandle for the PHY device connected to this device. | ||
27 | |||
28 | Example: | ||
29 | ethernet@1070000100800 { | ||
30 | compatible = "cavium,octeon-5750-mix"; | ||
31 | reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ | ||
32 | <0x11800 0xE0000800 0x0 0x300>, /* AGL */ | ||
33 | <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ | ||
34 | <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ | ||
35 | cell-index = <1>; | ||
36 | interrupts = <1 18>, < 1 46>; | ||
37 | local-mac-address = [ 00 0f b7 10 63 54 ]; | ||
38 | phy-handle = <&phy1>; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt deleted file mode 100644 index d4c53ba04b3..00000000000 --- a/Documentation/devicetree/bindings/net/cavium-pip.txt +++ /dev/null | |||
@@ -1,98 +0,0 @@ | |||
1 | * PIP Ethernet nexus. | ||
2 | |||
3 | The PIP Ethernet nexus can control several data packet input/output | ||
4 | devices. The devices have a two level grouping scheme. There may be | ||
5 | several interfaces, and each interface may have several ports. These | ||
6 | ports might be an individual Ethernet PHY. | ||
7 | |||
8 | |||
9 | Properties for the PIP nexus: | ||
10 | - compatible: "cavium,octeon-3860-pip" | ||
11 | |||
12 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
13 | |||
14 | - reg: The base address of the PIP's register bank. | ||
15 | |||
16 | - #address-cells: Must be <1>. | ||
17 | |||
18 | - #size-cells: Must be <0>. | ||
19 | |||
20 | Properties for PIP interfaces which is a child the PIP nexus: | ||
21 | - compatible: "cavium,octeon-3860-pip-interface" | ||
22 | |||
23 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
24 | |||
25 | - reg: The interface number. | ||
26 | |||
27 | - #address-cells: Must be <1>. | ||
28 | |||
29 | - #size-cells: Must be <0>. | ||
30 | |||
31 | Properties for PIP port which is a child the PIP interface: | ||
32 | - compatible: "cavium,octeon-3860-pip-port" | ||
33 | |||
34 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
35 | |||
36 | - reg: The port number within the interface group. | ||
37 | |||
38 | - mac-address: Optional, the MAC address to assign to the device. | ||
39 | |||
40 | - local-mac-address: Optional, the MAC address to assign to the device | ||
41 | if mac-address is not specified. | ||
42 | |||
43 | - phy-handle: Optional, a phandle for the PHY device connected to this device. | ||
44 | |||
45 | Example: | ||
46 | |||
47 | pip@11800a0000000 { | ||
48 | compatible = "cavium,octeon-3860-pip"; | ||
49 | #address-cells = <1>; | ||
50 | #size-cells = <0>; | ||
51 | reg = <0x11800 0xa0000000 0x0 0x2000>; | ||
52 | |||
53 | interface@0 { | ||
54 | compatible = "cavium,octeon-3860-pip-interface"; | ||
55 | #address-cells = <1>; | ||
56 | #size-cells = <0>; | ||
57 | reg = <0>; /* interface */ | ||
58 | |||
59 | ethernet@0 { | ||
60 | compatible = "cavium,octeon-3860-pip-port"; | ||
61 | reg = <0x0>; /* Port */ | ||
62 | local-mac-address = [ 00 0f b7 10 63 60 ]; | ||
63 | phy-handle = <&phy2>; | ||
64 | }; | ||
65 | ethernet@1 { | ||
66 | compatible = "cavium,octeon-3860-pip-port"; | ||
67 | reg = <0x1>; /* Port */ | ||
68 | local-mac-address = [ 00 0f b7 10 63 61 ]; | ||
69 | phy-handle = <&phy3>; | ||
70 | }; | ||
71 | ethernet@2 { | ||
72 | compatible = "cavium,octeon-3860-pip-port"; | ||
73 | reg = <0x2>; /* Port */ | ||
74 | local-mac-address = [ 00 0f b7 10 63 62 ]; | ||
75 | phy-handle = <&phy4>; | ||
76 | }; | ||
77 | ethernet@3 { | ||
78 | compatible = "cavium,octeon-3860-pip-port"; | ||
79 | reg = <0x3>; /* Port */ | ||
80 | local-mac-address = [ 00 0f b7 10 63 63 ]; | ||
81 | phy-handle = <&phy5>; | ||
82 | }; | ||
83 | }; | ||
84 | |||
85 | interface@1 { | ||
86 | compatible = "cavium,octeon-3860-pip-interface"; | ||
87 | #address-cells = <1>; | ||
88 | #size-cells = <0>; | ||
89 | reg = <1>; /* interface */ | ||
90 | |||
91 | ethernet@0 { | ||
92 | compatible = "cavium,octeon-3860-pip-port"; | ||
93 | reg = <0x0>; /* Port */ | ||
94 | local-mac-address = [ 00 0f b7 10 63 64 ]; | ||
95 | phy-handle = <&phy6>; | ||
96 | }; | ||
97 | }; | ||
98 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/cdns-emac.txt b/Documentation/devicetree/bindings/net/cdns-emac.txt deleted file mode 100644 index 09055c2495f..00000000000 --- a/Documentation/devicetree/bindings/net/cdns-emac.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | * Cadence EMAC Ethernet controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "cdns,[<chip>-]{emac}" | ||
5 | Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC. | ||
6 | or the generic form: "cdns,emac". | ||
7 | - reg: Address and length of the register set for the device | ||
8 | - interrupts: Should contain macb interrupt | ||
9 | - phy-mode: String, operation mode of the PHY interface. | ||
10 | Supported values are: "mii", "rmii". | ||
11 | |||
12 | Optional properties: | ||
13 | - local-mac-address: 6 bytes, mac address | ||
14 | |||
15 | Examples: | ||
16 | |||
17 | macb0: ethernet@fffc4000 { | ||
18 | compatible = "cdns,at91rm9200-emac"; | ||
19 | reg = <0xfffc4000 0x4000>; | ||
20 | interrupts = <21>; | ||
21 | phy-mode = "rmii"; | ||
22 | local-mac-address = [3a 0e 03 04 05 06]; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt deleted file mode 100644 index 6ddd0286a9b..00000000000 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ /dev/null | |||
@@ -1,87 +0,0 @@ | |||
1 | TI SoC Ethernet Switch Controller Device Tree Bindings | ||
2 | ------------------------------------------------------ | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : Should be "ti,cpsw" | ||
6 | - reg : physical base address and size of the cpsw | ||
7 | registers map | ||
8 | - interrupts : property with a value describing the interrupt | ||
9 | number | ||
10 | - interrupt-parent : The parent interrupt controller | ||
11 | - cpdma_channels : Specifies number of channels in CPDMA | ||
12 | - ale_entries : Specifies No of entries ALE can hold | ||
13 | - bd_ram_size : Specifies internal descriptor RAM size | ||
14 | - rx_descs : Specifies number of Rx descriptors | ||
15 | - mac_control : Specifies Default MAC control register content | ||
16 | for the specific platform | ||
17 | - slaves : Specifies number for slaves | ||
18 | - cpts_active_slave : Specifies the slave to use for time stamping | ||
19 | - cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds | ||
20 | - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds | ||
21 | - phy_id : Specifies slave phy id | ||
22 | - mac-address : Specifies slave MAC address | ||
23 | |||
24 | Optional properties: | ||
25 | - ti,hwmods : Must be "cpgmac0" | ||
26 | - no_bd_ram : Must be 0 or 1 | ||
27 | |||
28 | Note: "ti,hwmods" field is used to fetch the base address and irq | ||
29 | resources from TI, omap hwmod data base during device registration. | ||
30 | Future plan is to migrate hwmod data base contents into device tree | ||
31 | blob so that, all the required data will be used from device tree dts | ||
32 | file. | ||
33 | |||
34 | Examples: | ||
35 | |||
36 | mac: ethernet@4A100000 { | ||
37 | compatible = "ti,cpsw"; | ||
38 | reg = <0x4A100000 0x1000>; | ||
39 | interrupts = <55 0x4>; | ||
40 | interrupt-parent = <&intc>; | ||
41 | cpdma_channels = <8>; | ||
42 | ale_entries = <1024>; | ||
43 | bd_ram_size = <0x2000>; | ||
44 | no_bd_ram = <0>; | ||
45 | rx_descs = <64>; | ||
46 | mac_control = <0x20>; | ||
47 | slaves = <2>; | ||
48 | cpts_active_slave = <0>; | ||
49 | cpts_clock_mult = <0x80000000>; | ||
50 | cpts_clock_shift = <29>; | ||
51 | cpsw_emac0: slave@0 { | ||
52 | phy_id = <&davinci_mdio>, <0>; | ||
53 | /* Filled in by U-Boot */ | ||
54 | mac-address = [ 00 00 00 00 00 00 ]; | ||
55 | }; | ||
56 | cpsw_emac1: slave@1 { | ||
57 | phy_id = <&davinci_mdio>, <1>; | ||
58 | /* Filled in by U-Boot */ | ||
59 | mac-address = [ 00 00 00 00 00 00 ]; | ||
60 | }; | ||
61 | }; | ||
62 | |||
63 | (or) | ||
64 | mac: ethernet@4A100000 { | ||
65 | compatible = "ti,cpsw"; | ||
66 | ti,hwmods = "cpgmac0"; | ||
67 | cpdma_channels = <8>; | ||
68 | ale_entries = <1024>; | ||
69 | bd_ram_size = <0x2000>; | ||
70 | no_bd_ram = <0>; | ||
71 | rx_descs = <64>; | ||
72 | mac_control = <0x20>; | ||
73 | slaves = <2>; | ||
74 | cpts_active_slave = <0>; | ||
75 | cpts_clock_mult = <0x80000000>; | ||
76 | cpts_clock_shift = <29>; | ||
77 | cpsw_emac0: slave@0 { | ||
78 | phy_id = <&davinci_mdio>, <0>; | ||
79 | /* Filled in by U-Boot */ | ||
80 | mac-address = [ 00 00 00 00 00 00 ]; | ||
81 | }; | ||
82 | cpsw_emac1: slave@1 { | ||
83 | phy_id = <&davinci_mdio>, <1>; | ||
84 | /* Filled in by U-Boot */ | ||
85 | mac-address = [ 00 00 00 00 00 00 ]; | ||
86 | }; | ||
87 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/davinci-mdio.txt b/Documentation/devicetree/bindings/net/davinci-mdio.txt deleted file mode 100644 index 72efaaf764f..00000000000 --- a/Documentation/devicetree/bindings/net/davinci-mdio.txt +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | TI SoC Davinci MDIO Controller Device Tree Bindings | ||
2 | --------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : Should be "ti,davinci_mdio" | ||
6 | - reg : physical base address and size of the davinci mdio | ||
7 | registers map | ||
8 | - bus_freq : Mdio Bus frequency | ||
9 | |||
10 | Optional properties: | ||
11 | - ti,hwmods : Must be "davinci_mdio" | ||
12 | |||
13 | Note: "ti,hwmods" field is used to fetch the base address and irq | ||
14 | resources from TI, omap hwmod data base during device registration. | ||
15 | Future plan is to migrate hwmod data base contents into device tree | ||
16 | blob so that, all the required data will be used from device tree dts | ||
17 | file. | ||
18 | |||
19 | Examples: | ||
20 | |||
21 | mdio: davinci_mdio@4A101000 { | ||
22 | compatible = "ti,cpsw"; | ||
23 | reg = <0x4A101000 0x1000>; | ||
24 | bus_freq = <1000000>; | ||
25 | }; | ||
26 | |||
27 | (or) | ||
28 | |||
29 | mdio: davinci_mdio@4A101000 { | ||
30 | compatible = "ti,cpsw"; | ||
31 | ti,hwmods = "davinci_mdio"; | ||
32 | bus_freq = <1000000>; | ||
33 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/davinci_emac.txt b/Documentation/devicetree/bindings/net/davinci_emac.txt deleted file mode 100644 index 48b259e29e8..00000000000 --- a/Documentation/devicetree/bindings/net/davinci_emac.txt +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | * Texas Instruments Davinci EMAC | ||
2 | |||
3 | This file provides information, what the device node | ||
4 | for the davinci_emac interface contains. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "ti,davinci-dm6467-emac"; | ||
8 | - reg: Offset and length of the register set for the device | ||
9 | - ti,davinci-ctrl-reg-offset: offset to control register | ||
10 | - ti,davinci-ctrl-mod-reg-offset: offset to control module register | ||
11 | - ti,davinci-ctrl-ram-offset: offset to control module ram | ||
12 | - ti,davinci-ctrl-ram-size: size of control module ram | ||
13 | - ti,davinci-rmii-en: use RMII | ||
14 | - ti,davinci-no-bd-ram: has the emac controller BD RAM | ||
15 | - phy-handle: Contains a phandle to an Ethernet PHY. | ||
16 | if not, davinci_emac driver defaults to 100/FULL | ||
17 | - interrupts: interrupt mapping for the davinci emac interrupts sources: | ||
18 | 4 sources: <Receive Threshold Interrupt | ||
19 | Receive Interrupt | ||
20 | Transmit Interrupt | ||
21 | Miscellaneous Interrupt> | ||
22 | |||
23 | Optional properties: | ||
24 | - local-mac-address : 6 bytes, mac address | ||
25 | |||
26 | Example (enbw_cmc board): | ||
27 | eth0: emac@1e20000 { | ||
28 | compatible = "ti,davinci-dm6467-emac"; | ||
29 | reg = <0x220000 0x4000>; | ||
30 | ti,davinci-ctrl-reg-offset = <0x3000>; | ||
31 | ti,davinci-ctrl-mod-reg-offset = <0x2000>; | ||
32 | ti,davinci-ctrl-ram-offset = <0>; | ||
33 | ti,davinci-ctrl-ram-size = <0x2000>; | ||
34 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
35 | interrupts = <33 | ||
36 | 34 | ||
37 | 35 | ||
38 | 36 | ||
39 | >; | ||
40 | interrupt-parent = <&intc>; | ||
41 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index d5363922140..de439517dff 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt | |||
@@ -7,22 +7,18 @@ Required properties: | |||
7 | - phy-mode : String, operation mode of the PHY interface. | 7 | - phy-mode : String, operation mode of the PHY interface. |
8 | Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii", | 8 | Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii", |
9 | "rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii". | 9 | "rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii". |
10 | - phy-reset-gpios : Should specify the gpio for phy reset | ||
10 | 11 | ||
11 | Optional properties: | 12 | Optional properties: |
12 | - local-mac-address : 6 bytes, mac address | 13 | - local-mac-address : 6 bytes, mac address |
13 | - phy-reset-gpios : Should specify the gpio for phy reset | ||
14 | - phy-reset-duration : Reset duration in milliseconds. Should present | ||
15 | only if property "phy-reset-gpios" is available. Missing the property | ||
16 | will have the duration be 1 millisecond. Numbers greater than 1000 are | ||
17 | invalid and 1 millisecond will be used instead. | ||
18 | 14 | ||
19 | Example: | 15 | Example: |
20 | 16 | ||
21 | ethernet@83fec000 { | 17 | fec@83fec000 { |
22 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; | 18 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
23 | reg = <0x83fec000 0x4000>; | 19 | reg = <0x83fec000 0x4000>; |
24 | interrupts = <87>; | 20 | interrupts = <87>; |
25 | phy-mode = "mii"; | 21 | phy-mode = "mii"; |
26 | phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */ | 22 | phy-reset-gpios = <&gpio1 14 0>; /* GPIO2_14 */ |
27 | local-mac-address = [00 04 9F 01 1B B9]; | 23 | local-mac-address = [00 04 9F 01 1B B9]; |
28 | }; | 24 | }; |
diff --git a/Documentation/devicetree/bindings/net/lpc-eth.txt b/Documentation/devicetree/bindings/net/lpc-eth.txt deleted file mode 100644 index 585021acd17..00000000000 --- a/Documentation/devicetree/bindings/net/lpc-eth.txt +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | * NXP LPC32xx SoC Ethernet Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "nxp,lpc-eth" | ||
5 | - reg: Address and length of the register set for the device | ||
6 | - interrupts: Should contain ethernet controller interrupt | ||
7 | |||
8 | Optional properties: | ||
9 | - phy-mode: String, operation mode of the PHY interface. | ||
10 | Supported values are: "mii", "rmii" (default) | ||
11 | - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering | ||
12 | - local-mac-address : 6 bytes, mac address | ||
13 | |||
14 | Example: | ||
15 | |||
16 | mac: ethernet@31060000 { | ||
17 | compatible = "nxp,lpc-eth"; | ||
18 | reg = <0x31060000 0x1000>; | ||
19 | interrupt-parent = <&mic>; | ||
20 | interrupts = <29 0>; | ||
21 | |||
22 | phy-mode = "rmii"; | ||
23 | use-iram; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt deleted file mode 100644 index 44afa0e5057..00000000000 --- a/Documentation/devicetree/bindings/net/macb.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * Cadence MACB/GEM Ethernet controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "cdns,[<chip>-]{macb|gem}" | ||
5 | Use "cdns,at91sam9260-macb" Atmel at91sam9260 and at91sam9263 SoCs. | ||
6 | Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". | ||
7 | Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on | ||
8 | the Cadence GEM, or the generic form: "cdns,gem". | ||
9 | - reg: Address and length of the register set for the device | ||
10 | - interrupts: Should contain macb interrupt | ||
11 | - phy-mode: String, operation mode of the PHY interface. | ||
12 | Supported values are: "mii", "rmii", "gmii", "rgmii". | ||
13 | |||
14 | Optional properties: | ||
15 | - local-mac-address: 6 bytes, mac address | ||
16 | |||
17 | Examples: | ||
18 | |||
19 | macb0: ethernet@fffc4000 { | ||
20 | compatible = "cdns,at32ap7000-macb"; | ||
21 | reg = <0xfffc4000 0x4000>; | ||
22 | interrupts = <21>; | ||
23 | phy-mode = "rmii"; | ||
24 | local-mac-address = [3a 0e 03 04 05 06]; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt deleted file mode 100644 index 859a6fa7569..00000000000 --- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | * Marvell Armada 370 / Armada XP Ethernet Controller (NETA) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "marvell,armada-370-neta". | ||
5 | - reg: address and length of the register set for the device. | ||
6 | - interrupts: interrupt for the device | ||
7 | - phy: A phandle to a phy node defining the PHY address (as the reg | ||
8 | property, a single integer). | ||
9 | - phy-mode: The interface between the SoC and the PHY (a string that | ||
10 | of_get_phy_mode() can understand) | ||
11 | - clocks: a pointer to the reference clock for this device. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | ethernet@d0070000 { | ||
16 | compatible = "marvell,armada-370-neta"; | ||
17 | reg = <0xd0070000 0x2500>; | ||
18 | interrupts = <8>; | ||
19 | clocks = <&gate_clk 4>; | ||
20 | status = "okay"; | ||
21 | phy = <&phy0>; | ||
22 | phy-mode = "rgmii-id"; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt b/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt deleted file mode 100644 index 34e7aafa321..00000000000 --- a/Documentation/devicetree/bindings/net/marvell-orion-mdio.txt +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | * Marvell MDIO Ethernet Controller interface | ||
2 | |||
3 | The Ethernet controllers of the Marvel Kirkwood, Dove, Orion5x, | ||
4 | MV78xx0, Armada 370 and Armada XP have an identical unit that provides | ||
5 | an interface with the MDIO bus. This driver handles this MDIO | ||
6 | interface. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible: "marvell,orion-mdio" | ||
10 | - reg: address and length of the SMI register | ||
11 | |||
12 | The child nodes of the MDIO driver are the individual PHY devices | ||
13 | connected to this MDIO bus. They must have a "reg" property given the | ||
14 | PHY address on the MDIO bus. | ||
15 | |||
16 | Example at the SoC level: | ||
17 | |||
18 | mdio { | ||
19 | #address-cells = <1>; | ||
20 | #size-cells = <0>; | ||
21 | compatible = "marvell,orion-mdio"; | ||
22 | reg = <0xd0072004 0x4>; | ||
23 | }; | ||
24 | |||
25 | And at the board level: | ||
26 | |||
27 | mdio { | ||
28 | phy0: ethernet-phy@0 { | ||
29 | reg = <0>; | ||
30 | }; | ||
31 | |||
32 | phy1: ethernet-phy@1 { | ||
33 | reg = <1>; | ||
34 | }; | ||
35 | } | ||
diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.txt b/Documentation/devicetree/bindings/net/mdio-gpio.txt index c79bab02536..bc954952901 100644 --- a/Documentation/devicetree/bindings/net/mdio-gpio.txt +++ b/Documentation/devicetree/bindings/net/mdio-gpio.txt | |||
@@ -8,16 +8,9 @@ gpios property as described in section VIII.1 in the following order: | |||
8 | 8 | ||
9 | MDC, MDIO. | 9 | MDC, MDIO. |
10 | 10 | ||
11 | Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases" | ||
12 | node. | ||
13 | |||
14 | Example: | 11 | Example: |
15 | 12 | ||
16 | aliases { | 13 | mdio { |
17 | mdio-gpio0 = <&mdio0>; | ||
18 | }; | ||
19 | |||
20 | mdio0: mdio { | ||
21 | compatible = "virtual,mdio-gpio"; | 14 | compatible = "virtual,mdio-gpio"; |
22 | #address-cells = <1>; | 15 | #address-cells = <1>; |
23 | #size-cells = <0>; | 16 | #size-cells = <0>; |
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt b/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt deleted file mode 100644 index 79384113c2b..00000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt +++ /dev/null | |||
@@ -1,127 +0,0 @@ | |||
1 | Properties for an MDIO bus multiplexer/switch controlled by GPIO pins. | ||
2 | |||
3 | This is a special case of a MDIO bus multiplexer. One or more GPIO | ||
4 | lines are used to control which child bus is connected. | ||
5 | |||
6 | Required properties in addition to the generic multiplexer properties: | ||
7 | |||
8 | - compatible : mdio-mux-gpio. | ||
9 | - gpios : GPIO specifiers for each GPIO line. One or more must be specified. | ||
10 | |||
11 | |||
12 | Example : | ||
13 | |||
14 | /* The parent MDIO bus. */ | ||
15 | smi1: mdio@1180000001900 { | ||
16 | compatible = "cavium,octeon-3860-mdio"; | ||
17 | #address-cells = <1>; | ||
18 | #size-cells = <0>; | ||
19 | reg = <0x11800 0x00001900 0x0 0x40>; | ||
20 | }; | ||
21 | |||
22 | /* | ||
23 | An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a | ||
24 | pair of GPIO lines. Child busses 2 and 3 populated with 4 | ||
25 | PHYs each. | ||
26 | */ | ||
27 | mdio-mux { | ||
28 | compatible = "mdio-mux-gpio"; | ||
29 | gpios = <&gpio1 3 0>, <&gpio1 4 0>; | ||
30 | mdio-parent-bus = <&smi1>; | ||
31 | #address-cells = <1>; | ||
32 | #size-cells = <0>; | ||
33 | |||
34 | mdio@2 { | ||
35 | reg = <2>; | ||
36 | #address-cells = <1>; | ||
37 | #size-cells = <0>; | ||
38 | |||
39 | phy11: ethernet-phy@1 { | ||
40 | reg = <1>; | ||
41 | compatible = "marvell,88e1149r"; | ||
42 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
43 | <3 0x11 0 0x00aa>, | ||
44 | <3 0x12 0 0x4105>, | ||
45 | <3 0x13 0 0x0a60>; | ||
46 | interrupt-parent = <&gpio>; | ||
47 | interrupts = <10 8>; /* Pin 10, active low */ | ||
48 | }; | ||
49 | phy12: ethernet-phy@2 { | ||
50 | reg = <2>; | ||
51 | compatible = "marvell,88e1149r"; | ||
52 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
53 | <3 0x11 0 0x00aa>, | ||
54 | <3 0x12 0 0x4105>, | ||
55 | <3 0x13 0 0x0a60>; | ||
56 | interrupt-parent = <&gpio>; | ||
57 | interrupts = <10 8>; /* Pin 10, active low */ | ||
58 | }; | ||
59 | phy13: ethernet-phy@3 { | ||
60 | reg = <3>; | ||
61 | compatible = "marvell,88e1149r"; | ||
62 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
63 | <3 0x11 0 0x00aa>, | ||
64 | <3 0x12 0 0x4105>, | ||
65 | <3 0x13 0 0x0a60>; | ||
66 | interrupt-parent = <&gpio>; | ||
67 | interrupts = <10 8>; /* Pin 10, active low */ | ||
68 | }; | ||
69 | phy14: ethernet-phy@4 { | ||
70 | reg = <4>; | ||
71 | compatible = "marvell,88e1149r"; | ||
72 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
73 | <3 0x11 0 0x00aa>, | ||
74 | <3 0x12 0 0x4105>, | ||
75 | <3 0x13 0 0x0a60>; | ||
76 | interrupt-parent = <&gpio>; | ||
77 | interrupts = <10 8>; /* Pin 10, active low */ | ||
78 | }; | ||
79 | }; | ||
80 | |||
81 | mdio@3 { | ||
82 | reg = <3>; | ||
83 | #address-cells = <1>; | ||
84 | #size-cells = <0>; | ||
85 | |||
86 | phy21: ethernet-phy@1 { | ||
87 | reg = <1>; | ||
88 | compatible = "marvell,88e1149r"; | ||
89 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
90 | <3 0x11 0 0x00aa>, | ||
91 | <3 0x12 0 0x4105>, | ||
92 | <3 0x13 0 0x0a60>; | ||
93 | interrupt-parent = <&gpio>; | ||
94 | interrupts = <12 8>; /* Pin 12, active low */ | ||
95 | }; | ||
96 | phy22: ethernet-phy@2 { | ||
97 | reg = <2>; | ||
98 | compatible = "marvell,88e1149r"; | ||
99 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
100 | <3 0x11 0 0x00aa>, | ||
101 | <3 0x12 0 0x4105>, | ||
102 | <3 0x13 0 0x0a60>; | ||
103 | interrupt-parent = <&gpio>; | ||
104 | interrupts = <12 8>; /* Pin 12, active low */ | ||
105 | }; | ||
106 | phy23: ethernet-phy@3 { | ||
107 | reg = <3>; | ||
108 | compatible = "marvell,88e1149r"; | ||
109 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
110 | <3 0x11 0 0x00aa>, | ||
111 | <3 0x12 0 0x4105>, | ||
112 | <3 0x13 0 0x0a60>; | ||
113 | interrupt-parent = <&gpio>; | ||
114 | interrupts = <12 8>; /* Pin 12, active low */ | ||
115 | }; | ||
116 | phy24: ethernet-phy@4 { | ||
117 | reg = <4>; | ||
118 | compatible = "marvell,88e1149r"; | ||
119 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
120 | <3 0x11 0 0x00aa>, | ||
121 | <3 0x12 0 0x4105>, | ||
122 | <3 0x13 0 0x0a60>; | ||
123 | interrupt-parent = <&gpio>; | ||
124 | interrupts = <12 8>; /* Pin 12, active low */ | ||
125 | }; | ||
126 | }; | ||
127 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt deleted file mode 100644 index 8516929c725..00000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt +++ /dev/null | |||
@@ -1,75 +0,0 @@ | |||
1 | Properties for an MDIO bus multiplexer controlled by a memory-mapped device | ||
2 | |||
3 | This is a special case of a MDIO bus multiplexer. A memory-mapped device, | ||
4 | like an FPGA, is used to control which child bus is connected. The mdio-mux | ||
5 | node must be a child of the memory-mapped device. The driver currently only | ||
6 | supports devices with eight-bit registers. | ||
7 | |||
8 | Required properties in addition to the generic multiplexer properties: | ||
9 | |||
10 | - compatible : string, must contain "mdio-mux-mmioreg" | ||
11 | |||
12 | - reg : integer, contains the offset of the register that controls the bus | ||
13 | multiplexer. The size field in the 'reg' property is the size of | ||
14 | register, and must therefore be 1. | ||
15 | |||
16 | - mux-mask : integer, contains an eight-bit mask that specifies which | ||
17 | bits in the register control the actual bus multiplexer. The | ||
18 | 'reg' property of each child mdio-mux node must be constrained by | ||
19 | this mask. | ||
20 | |||
21 | Example: | ||
22 | |||
23 | The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes. | ||
24 | For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus. | ||
25 | A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on | ||
26 | BRDCFG1 that control the actual mux. | ||
27 | |||
28 | /* The FPGA node */ | ||
29 | fpga: board-control@3,0 { | ||
30 | #address-cells = <1>; | ||
31 | #size-cells = <1>; | ||
32 | compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; | ||
33 | reg = <3 0 0x30>; | ||
34 | ranges = <0 3 0 0x30>; | ||
35 | |||
36 | mdio-mux-emi2 { | ||
37 | compatible = "mdio-mux-mmioreg", "mdio-mux"; | ||
38 | mdio-parent-bus = <&xmdio0>; | ||
39 | #address-cells = <1>; | ||
40 | #size-cells = <0>; | ||
41 | reg = <9 1>; // BRDCFG1 | ||
42 | mux-mask = <0x6>; // EMI2 | ||
43 | |||
44 | emi2_slot1: mdio@0 { // Slot 1 XAUI (FM2) | ||
45 | reg = <0>; | ||
46 | #address-cells = <1>; | ||
47 | #size-cells = <0>; | ||
48 | |||
49 | phy_xgmii_slot1: ethernet-phy@0 { | ||
50 | compatible = "ethernet-phy-ieee802.3-c45"; | ||
51 | reg = <4>; | ||
52 | }; | ||
53 | }; | ||
54 | |||
55 | emi2_slot2: mdio@2 { // Slot 2 XAUI (FM1) | ||
56 | reg = <2>; | ||
57 | #address-cells = <1>; | ||
58 | #size-cells = <0>; | ||
59 | |||
60 | phy_xgmii_slot2: ethernet-phy@4 { | ||
61 | compatible = "ethernet-phy-ieee802.3-c45"; | ||
62 | reg = <0>; | ||
63 | }; | ||
64 | }; | ||
65 | }; | ||
66 | }; | ||
67 | |||
68 | /* The parent MDIO bus. */ | ||
69 | xmdio0: mdio@f1000 { | ||
70 | #address-cells = <1>; | ||
71 | #size-cells = <0>; | ||
72 | compatible = "fsl,fman-xmdio"; | ||
73 | reg = <0xf1000 0x1000>; | ||
74 | interrupts = <100 1 0 0>; | ||
75 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/mdio-mux.txt b/Documentation/devicetree/bindings/net/mdio-mux.txt deleted file mode 100644 index f65606f8d63..00000000000 --- a/Documentation/devicetree/bindings/net/mdio-mux.txt +++ /dev/null | |||
@@ -1,136 +0,0 @@ | |||
1 | Common MDIO bus multiplexer/switch properties. | ||
2 | |||
3 | An MDIO bus multiplexer/switch will have several child busses that are | ||
4 | numbered uniquely in a device dependent manner. The nodes for an MDIO | ||
5 | bus multiplexer/switch will have one child node for each child bus. | ||
6 | |||
7 | Required properties: | ||
8 | - mdio-parent-bus : phandle to the parent MDIO bus. | ||
9 | - #address-cells = <1>; | ||
10 | - #size-cells = <0>; | ||
11 | |||
12 | Optional properties: | ||
13 | - Other properties specific to the multiplexer/switch hardware. | ||
14 | |||
15 | Required properties for child nodes: | ||
16 | - #address-cells = <1>; | ||
17 | - #size-cells = <0>; | ||
18 | - reg : The sub-bus number. | ||
19 | |||
20 | |||
21 | Example : | ||
22 | |||
23 | /* The parent MDIO bus. */ | ||
24 | smi1: mdio@1180000001900 { | ||
25 | compatible = "cavium,octeon-3860-mdio"; | ||
26 | #address-cells = <1>; | ||
27 | #size-cells = <0>; | ||
28 | reg = <0x11800 0x00001900 0x0 0x40>; | ||
29 | }; | ||
30 | |||
31 | /* | ||
32 | An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a | ||
33 | pair of GPIO lines. Child busses 2 and 3 populated with 4 | ||
34 | PHYs each. | ||
35 | */ | ||
36 | mdio-mux { | ||
37 | compatible = "mdio-mux-gpio"; | ||
38 | gpios = <&gpio1 3 0>, <&gpio1 4 0>; | ||
39 | mdio-parent-bus = <&smi1>; | ||
40 | #address-cells = <1>; | ||
41 | #size-cells = <0>; | ||
42 | |||
43 | mdio@2 { | ||
44 | reg = <2>; | ||
45 | #address-cells = <1>; | ||
46 | #size-cells = <0>; | ||
47 | |||
48 | phy11: ethernet-phy@1 { | ||
49 | reg = <1>; | ||
50 | compatible = "marvell,88e1149r"; | ||
51 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
52 | <3 0x11 0 0x00aa>, | ||
53 | <3 0x12 0 0x4105>, | ||
54 | <3 0x13 0 0x0a60>; | ||
55 | interrupt-parent = <&gpio>; | ||
56 | interrupts = <10 8>; /* Pin 10, active low */ | ||
57 | }; | ||
58 | phy12: ethernet-phy@2 { | ||
59 | reg = <2>; | ||
60 | compatible = "marvell,88e1149r"; | ||
61 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
62 | <3 0x11 0 0x00aa>, | ||
63 | <3 0x12 0 0x4105>, | ||
64 | <3 0x13 0 0x0a60>; | ||
65 | interrupt-parent = <&gpio>; | ||
66 | interrupts = <10 8>; /* Pin 10, active low */ | ||
67 | }; | ||
68 | phy13: ethernet-phy@3 { | ||
69 | reg = <3>; | ||
70 | compatible = "marvell,88e1149r"; | ||
71 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
72 | <3 0x11 0 0x00aa>, | ||
73 | <3 0x12 0 0x4105>, | ||
74 | <3 0x13 0 0x0a60>; | ||
75 | interrupt-parent = <&gpio>; | ||
76 | interrupts = <10 8>; /* Pin 10, active low */ | ||
77 | }; | ||
78 | phy14: ethernet-phy@4 { | ||
79 | reg = <4>; | ||
80 | compatible = "marvell,88e1149r"; | ||
81 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
82 | <3 0x11 0 0x00aa>, | ||
83 | <3 0x12 0 0x4105>, | ||
84 | <3 0x13 0 0x0a60>; | ||
85 | interrupt-parent = <&gpio>; | ||
86 | interrupts = <10 8>; /* Pin 10, active low */ | ||
87 | }; | ||
88 | }; | ||
89 | |||
90 | mdio@3 { | ||
91 | reg = <3>; | ||
92 | #address-cells = <1>; | ||
93 | #size-cells = <0>; | ||
94 | |||
95 | phy21: ethernet-phy@1 { | ||
96 | reg = <1>; | ||
97 | compatible = "marvell,88e1149r"; | ||
98 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
99 | <3 0x11 0 0x00aa>, | ||
100 | <3 0x12 0 0x4105>, | ||
101 | <3 0x13 0 0x0a60>; | ||
102 | interrupt-parent = <&gpio>; | ||
103 | interrupts = <12 8>; /* Pin 12, active low */ | ||
104 | }; | ||
105 | phy22: ethernet-phy@2 { | ||
106 | reg = <2>; | ||
107 | compatible = "marvell,88e1149r"; | ||
108 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
109 | <3 0x11 0 0x00aa>, | ||
110 | <3 0x12 0 0x4105>, | ||
111 | <3 0x13 0 0x0a60>; | ||
112 | interrupt-parent = <&gpio>; | ||
113 | interrupts = <12 8>; /* Pin 12, active low */ | ||
114 | }; | ||
115 | phy23: ethernet-phy@3 { | ||
116 | reg = <3>; | ||
117 | compatible = "marvell,88e1149r"; | ||
118 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
119 | <3 0x11 0 0x00aa>, | ||
120 | <3 0x12 0 0x4105>, | ||
121 | <3 0x13 0 0x0a60>; | ||
122 | interrupt-parent = <&gpio>; | ||
123 | interrupts = <12 8>; /* Pin 12, active low */ | ||
124 | }; | ||
125 | phy24: ethernet-phy@4 { | ||
126 | reg = <4>; | ||
127 | compatible = "marvell,88e1149r"; | ||
128 | marvell,reg-init = <3 0x10 0 0x5777>, | ||
129 | <3 0x11 0 0x00aa>, | ||
130 | <3 0x12 0 0x4105>, | ||
131 | <3 0x13 0 0x0a60>; | ||
132 | interrupt-parent = <&gpio>; | ||
133 | interrupts = <12 8>; /* Pin 12, active low */ | ||
134 | }; | ||
135 | }; | ||
136 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt index 7cd18fbfcf7..bb8c742eb8c 100644 --- a/Documentation/devicetree/bindings/net/phy.txt +++ b/Documentation/devicetree/bindings/net/phy.txt | |||
@@ -14,20 +14,10 @@ Required properties: | |||
14 | - linux,phandle : phandle for this node; likely referenced by an | 14 | - linux,phandle : phandle for this node; likely referenced by an |
15 | ethernet controller node. | 15 | ethernet controller node. |
16 | 16 | ||
17 | Optional Properties: | ||
18 | |||
19 | - compatible: Compatible list, may contain | ||
20 | "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for | ||
21 | PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45 | ||
22 | specifications. If neither of these are specified, the default is to | ||
23 | assume clause 22. The compatible list may also contain other | ||
24 | elements. | ||
25 | |||
26 | Example: | 17 | Example: |
27 | 18 | ||
28 | ethernet-phy@0 { | 19 | ethernet-phy@0 { |
29 | compatible = "ethernet-phy-ieee802.3-c22"; | 20 | linux,phandle = <2452000> |
30 | linux,phandle = <2452000>; | ||
31 | interrupt-parent = <40000>; | 21 | interrupt-parent = <40000>; |
32 | interrupts = <35 1>; | 22 | interrupts = <35 1>; |
33 | reg = <0>; | 23 | reg = <0>; |
diff --git a/Documentation/devicetree/bindings/net/smsc911x.txt b/Documentation/devicetree/bindings/net/smsc911x.txt deleted file mode 100644 index adb5b5744ec..00000000000 --- a/Documentation/devicetree/bindings/net/smsc911x.txt +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "smsc,lan<model>", "smsc,lan9115" | ||
5 | - reg : Address and length of the io space for SMSC LAN | ||
6 | - interrupts : Should contain SMSC LAN interrupt line | ||
7 | - interrupt-parent : Should be the phandle for the interrupt controller | ||
8 | that services interrupts for this device | ||
9 | - phy-mode : String, operation mode of the PHY interface. | ||
10 | Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii", | ||
11 | "rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii". | ||
12 | |||
13 | Optional properties: | ||
14 | - reg-shift : Specify the quantity to shift the register offsets by | ||
15 | - reg-io-width : Specify the size (in bytes) of the IO accesses that | ||
16 | should be performed on the device. Valid value for SMSC LAN is | ||
17 | 2 or 4. If it's omitted or invalid, the size would be 2. | ||
18 | - smsc,irq-active-high : Indicates the IRQ polarity is active-high | ||
19 | - smsc,irq-push-pull : Indicates the IRQ type is push-pull | ||
20 | - smsc,force-internal-phy : Forces SMSC LAN controller to use | ||
21 | internal PHY | ||
22 | - smsc,force-external-phy : Forces SMSC LAN controller to use | ||
23 | external PHY | ||
24 | - smsc,save-mac-address : Indicates that mac address needs to be saved | ||
25 | before resetting the controller | ||
26 | - local-mac-address : 6 bytes, mac address | ||
27 | |||
28 | Examples: | ||
29 | |||
30 | lan9220@f4000000 { | ||
31 | compatible = "smsc,lan9220", "smsc,lan9115"; | ||
32 | reg = <0xf4000000 0x2000000>; | ||
33 | phy-mode = "mii"; | ||
34 | interrupt-parent = <&gpio1>; | ||
35 | interrupts = <31>; | ||
36 | reg-io-width = <4>; | ||
37 | smsc,irq-push-pull; | ||
38 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt deleted file mode 100644 index 060bbf098ef..00000000000 --- a/Documentation/devicetree/bindings/net/stmmac.txt +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | * STMicroelectronics 10/100/1000 Ethernet driver (GMAC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac" | ||
5 | For backwards compatibility: "st,spear600-gmac" is also supported. | ||
6 | - reg: Address and length of the register set for the device | ||
7 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
8 | that services interrupts for this device | ||
9 | - interrupts: Should contain the STMMAC interrupts | ||
10 | - interrupt-names: Should contain the interrupt names "macirq" | ||
11 | "eth_wake_irq" if this interrupt is supported in the "interrupts" | ||
12 | property | ||
13 | - phy-mode: String, operation mode of the PHY interface. | ||
14 | Supported values are: "mii", "rmii", "gmii", "rgmii". | ||
15 | |||
16 | Optional properties: | ||
17 | - mac-address: 6 bytes, mac address | ||
18 | |||
19 | Examples: | ||
20 | |||
21 | gmac0: ethernet@e0800000 { | ||
22 | compatible = "st,spear600-gmac"; | ||
23 | reg = <0xe0800000 0x8000>; | ||
24 | interrupt-parent = <&vic1>; | ||
25 | interrupts = <24 23>; | ||
26 | interrupt-names = "macirq", "eth_wake_irq"; | ||
27 | mac-address = [000000000000]; /* Filled in by U-Boot */ | ||
28 | phy-mode = "gmii"; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt deleted file mode 100644 index 5aeee53ff9f..00000000000 --- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt +++ /dev/null | |||
@@ -1,9 +0,0 @@ | |||
1 | NVIDIA compliant embedded controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "nvidia,nvec". | ||
5 | - reg : the iomem of the i2c slave controller | ||
6 | - interrupts : the interrupt line of the i2c slave controller | ||
7 | - clock-frequency : the frequency of the i2c bus | ||
8 | - gpios : the gpio used for ec request | ||
9 | - slave-addr: the i2c address of the slave controller | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt deleted file mode 100644 index 3a268127b05..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ /dev/null | |||
@@ -1,141 +0,0 @@ | |||
1 | * Atmel AT91 Pinmux Controller | ||
2 | |||
3 | The AT91 Pinmux Controler, enables the IC | ||
4 | to share one PAD to several functional blocks. The sharing is done by | ||
5 | multiplexing the PAD input/output signals. For each PAD there are up to | ||
6 | 8 muxing options (called periph modes). Since different modules require | ||
7 | different PAD settings (like pull up, keeper, etc) the contoller controls | ||
8 | also the PAD settings parameters. | ||
9 | |||
10 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
11 | common pinctrl bindings used by client devices, including the meaning of the | ||
12 | phrase "pin configuration node". | ||
13 | |||
14 | Atmel AT91 pin configuration node is a node of a group of pins which can be | ||
15 | used for a specific device or function. This node represents both mux and config | ||
16 | of the pins in that group. The 'pins' selects the function mode(also named pin | ||
17 | mode) this pin can work on and the 'config' configures various pad settings | ||
18 | such as pull-up, multi drive, etc. | ||
19 | |||
20 | Required properties for iomux controller: | ||
21 | - compatible: "atmel,at91rm9200-pinctrl" | ||
22 | - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be | ||
23 | configured in this periph mode. All the periph and bank need to be describe. | ||
24 | |||
25 | How to create such array: | ||
26 | |||
27 | Each column will represent the possible peripheral of the pinctrl | ||
28 | Each line will represent a pio bank | ||
29 | |||
30 | Take an example on the 9260 | ||
31 | Peripheral: 2 ( A and B) | ||
32 | Bank: 3 (A, B and C) | ||
33 | => | ||
34 | |||
35 | /* A B */ | ||
36 | 0xffffffff 0xffc00c3b /* pioA */ | ||
37 | 0xffffffff 0x7fff3ccf /* pioB */ | ||
38 | 0xffffffff 0x007fffff /* pioC */ | ||
39 | |||
40 | For each peripheral/bank we will descibe in a u32 if a pin can can be | ||
41 | configured in it by putting 1 to the pin bit (1 << pin) | ||
42 | |||
43 | Let's take the pioA on peripheral B | ||
44 | From the datasheet Table 10-2. | ||
45 | Peripheral B | ||
46 | PA0 MCDB0 | ||
47 | PA1 MCCDB | ||
48 | PA2 | ||
49 | PA3 MCDB3 | ||
50 | PA4 MCDB2 | ||
51 | PA5 MCDB1 | ||
52 | PA6 | ||
53 | PA7 | ||
54 | PA8 | ||
55 | PA9 | ||
56 | PA10 ETX2 | ||
57 | PA11 ETX3 | ||
58 | PA12 | ||
59 | PA13 | ||
60 | PA14 | ||
61 | PA15 | ||
62 | PA16 | ||
63 | PA17 | ||
64 | PA18 | ||
65 | PA19 | ||
66 | PA20 | ||
67 | PA21 | ||
68 | PA22 ETXER | ||
69 | PA23 ETX2 | ||
70 | PA24 ETX3 | ||
71 | PA25 ERX2 | ||
72 | PA26 ERX3 | ||
73 | PA27 ERXCK | ||
74 | PA28 ECRS | ||
75 | PA29 ECOL | ||
76 | PA30 RXD4 | ||
77 | PA31 TXD4 | ||
78 | |||
79 | => 0xffc00c3b | ||
80 | |||
81 | Required properties for pin configuration node: | ||
82 | - atmel,pins: 4 integers array, represents a group of pins mux and config | ||
83 | setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. | ||
84 | The PERIPH 0 means gpio. | ||
85 | |||
86 | Bits used for CONFIG: | ||
87 | PULL_UP (1 << 0): indicate this pin need a pull up. | ||
88 | MULTIDRIVE (1 << 1): indicate this pin need to be configured as multidrive. | ||
89 | DEGLITCH (1 << 2): indicate this pin need deglitch. | ||
90 | PULL_DOWN (1 << 3): indicate this pin need a pull down. | ||
91 | DIS_SCHMIT (1 << 4): indicate this pin need to disable schmit trigger. | ||
92 | DEBOUNCE (1 << 16): indicate this pin need debounce. | ||
93 | DEBOUNCE_VAL (0x3fff << 17): debounce val. | ||
94 | |||
95 | NOTE: | ||
96 | Some requirements for using atmel,at91rm9200-pinctrl binding: | ||
97 | 1. We have pin function node defined under at91 controller node to represent | ||
98 | what pinmux functions this SoC supports. | ||
99 | 2. The driver can use the function node's name and pin configuration node's | ||
100 | name describe the pin function and group hierarchy. | ||
101 | For example, Linux at91 pinctrl driver takes the function node's name | ||
102 | as the function name and pin configuration node's name as group name to | ||
103 | create the map table. | ||
104 | 3. Each pin configuration node should have a phandle, devices can set pins | ||
105 | configurations by referring to the phandle of that pin configuration node. | ||
106 | 4. The gpio controller must be describe in the pinctrl simple-bus. | ||
107 | |||
108 | Examples: | ||
109 | |||
110 | pinctrl@fffff400 { | ||
111 | #address-cells = <1>; | ||
112 | #size-cells = <1>; | ||
113 | ranges; | ||
114 | compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; | ||
115 | reg = <0xfffff400 0x600>; | ||
116 | |||
117 | atmel,mux-mask = < | ||
118 | /* A B */ | ||
119 | 0xffffffff 0xffc00c3b /* pioA */ | ||
120 | 0xffffffff 0x7fff3ccf /* pioB */ | ||
121 | 0xffffffff 0x007fffff /* pioC */ | ||
122 | >; | ||
123 | |||
124 | /* shared pinctrl settings */ | ||
125 | dbgu { | ||
126 | pinctrl_dbgu: dbgu-0 { | ||
127 | atmel,pins = | ||
128 | <1 14 0x1 0x0 /* PB14 periph A */ | ||
129 | 1 15 0x1 0x1>; /* PB15 periph with pullup */ | ||
130 | }; | ||
131 | }; | ||
132 | }; | ||
133 | |||
134 | dbgu: serial@fffff200 { | ||
135 | compatible = "atmel,at91sam9260-usart"; | ||
136 | reg = <0xfffff200 0x200>; | ||
137 | interrupts = <1 4 7>; | ||
138 | pinctrl-names = "default"; | ||
139 | pinctrl-0 = <&pinctrl_dbgu>; | ||
140 | status = "disabled"; | ||
141 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt deleted file mode 100644 index 8edc20e1b09..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +++ /dev/null | |||
@@ -1,74 +0,0 @@ | |||
1 | Broadcom BCM2835 GPIO (and pinmux) controller | ||
2 | |||
3 | The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt | ||
4 | controller, and pinmux/control device. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "brcm,bcm2835-gpio" | ||
8 | - reg: Should contain the physical address of the GPIO module's registes. | ||
9 | - gpio-controller: Marks the device node as a GPIO controller. | ||
10 | - #gpio-cells : Should be two. The first cell is the pin number and the | ||
11 | second cell is used to specify optional parameters: | ||
12 | - bit 0 specifies polarity (0 for normal, 1 for inverted) | ||
13 | - interrupts : The interrupt outputs from the controller. One interrupt per | ||
14 | individual bank followed by the "all banks" interrupt. | ||
15 | - interrupt-controller: Marks the device node as an interrupt controller. | ||
16 | - #interrupt-cells : Should be 2. | ||
17 | The first cell is the GPIO number. | ||
18 | The second cell is used to specify flags: | ||
19 | bits[3:0] trigger type and level flags: | ||
20 | 1 = low-to-high edge triggered. | ||
21 | 2 = high-to-low edge triggered. | ||
22 | 4 = active high level-sensitive. | ||
23 | 8 = active low level-sensitive. | ||
24 | Valid combinations are 1, 2, 3, 4, 8. | ||
25 | |||
26 | Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. | ||
27 | |||
28 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
29 | common pinctrl bindings used by client devices, including the meaning of the | ||
30 | phrase "pin configuration node". | ||
31 | |||
32 | Each pin configuration node lists the pin(s) to which it applies, and one or | ||
33 | more of the mux function to select on those pin(s), and pull-up/down | ||
34 | configuration. Each subnode only affects those parameters that are explicitly | ||
35 | listed. In other words, a subnode that lists only a mux function implies no | ||
36 | information about any pull configuration. Similarly, a subnode that lists only | ||
37 | a pul parameter implies no information about the mux function. | ||
38 | |||
39 | Required subnode-properties: | ||
40 | - brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs | ||
41 | are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53. | ||
42 | |||
43 | Optional subnode-properties: | ||
44 | - brcm,function: Integer, containing the function to mux to the pin(s): | ||
45 | 0: GPIO in | ||
46 | 1: GPIO out | ||
47 | 2: alt5 | ||
48 | 3: alt4 | ||
49 | 4: alt0 | ||
50 | 5: alt1 | ||
51 | 6: alt2 | ||
52 | 7: alt3 | ||
53 | - brcm,pull: Integer, representing the pull-down/up to apply to the pin(s): | ||
54 | 0: none | ||
55 | 1: down | ||
56 | 2: up | ||
57 | |||
58 | Each of brcm,function and brcm,pull may contain either a single value which | ||
59 | will be applied to all pins in brcm,pins, or 1 value for each entry in | ||
60 | brcm,pins. | ||
61 | |||
62 | Example: | ||
63 | |||
64 | gpio: gpio { | ||
65 | compatible = "brcm,bcm2835-gpio"; | ||
66 | reg = <0x2200000 0xb4>; | ||
67 | interrupts = <2 17>, <2 19>, <2 18>, <2 20>; | ||
68 | |||
69 | gpio-controller; | ||
70 | #gpio-cells = <2>; | ||
71 | |||
72 | interrupt-controller; | ||
73 | #interrupt-cells = <2>; | ||
74 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt deleted file mode 100644 index ab19e6bc7d3..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +++ /dev/null | |||
@@ -1,95 +0,0 @@ | |||
1 | * Freescale IOMUX Controller (IOMUXC) for i.MX | ||
2 | |||
3 | The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC | ||
4 | to share one PAD to several functional blocks. The sharing is done by | ||
5 | multiplexing the PAD input/output signals. For each PAD there are up to | ||
6 | 8 muxing options (called ALT modes). Since different modules require | ||
7 | different PAD settings (like pull up, keeper, etc) the IOMUXC controls | ||
8 | also the PAD settings parameters. | ||
9 | |||
10 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
11 | common pinctrl bindings used by client devices, including the meaning of the | ||
12 | phrase "pin configuration node". | ||
13 | |||
14 | Freescale IMX pin configuration node is a node of a group of pins which can be | ||
15 | used for a specific device or function. This node represents both mux and config | ||
16 | of the pins in that group. The 'mux' selects the function mode(also named mux | ||
17 | mode) this pin can work on and the 'config' configures various pad settings | ||
18 | such as pull-up, open drain, drive strength, etc. | ||
19 | |||
20 | Required properties for iomux controller: | ||
21 | - compatible: "fsl,<soc>-iomuxc" | ||
22 | Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs. | ||
23 | |||
24 | Required properties for pin configuration node: | ||
25 | - fsl,pins: two integers array, represents a group of pins mux and config | ||
26 | setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a | ||
27 | pin working on a specific function, CONFIG is the pad setting value like | ||
28 | pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid | ||
29 | pins and functions of each SoC. | ||
30 | |||
31 | Bits used for CONFIG: | ||
32 | NO_PAD_CTL(1 << 31): indicate this pin does not need config. | ||
33 | |||
34 | SION(1 << 30): Software Input On Field. | ||
35 | Force the selected mux mode input path no matter of MUX_MODE functionality. | ||
36 | By default the input path is determined by functionality of the selected | ||
37 | mux mode (regular). | ||
38 | |||
39 | Other bits are used for PAD setting. | ||
40 | Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part | ||
41 | of bits definitions. | ||
42 | |||
43 | NOTE: | ||
44 | Some requirements for using fsl,imx-pinctrl binding: | ||
45 | 1. We have pin function node defined under iomux controller node to represent | ||
46 | what pinmux functions this SoC supports. | ||
47 | 2. The pin configuration node intends to work on a specific function should | ||
48 | to be defined under that specific function node. | ||
49 | The function node's name should represent well about what function | ||
50 | this group of pins in this pin configuration node are working on. | ||
51 | 3. The driver can use the function node's name and pin configuration node's | ||
52 | name describe the pin function and group hierarchy. | ||
53 | For example, Linux IMX pinctrl driver takes the function node's name | ||
54 | as the function name and pin configuration node's name as group name to | ||
55 | create the map table. | ||
56 | 4. Each pin configuration node should have a phandle, devices can set pins | ||
57 | configurations by referring to the phandle of that pin configuration node. | ||
58 | |||
59 | Examples: | ||
60 | usdhc@0219c000 { /* uSDHC4 */ | ||
61 | fsl,card-wired; | ||
62 | vmmc-supply = <®_3p3v>; | ||
63 | status = "okay"; | ||
64 | pinctrl-names = "default"; | ||
65 | pinctrl-0 = <&pinctrl_usdhc4_1>; | ||
66 | }; | ||
67 | |||
68 | iomuxc@020e0000 { | ||
69 | compatible = "fsl,imx6q-iomuxc"; | ||
70 | reg = <0x020e0000 0x4000>; | ||
71 | |||
72 | /* shared pinctrl settings */ | ||
73 | usdhc4 { | ||
74 | pinctrl_usdhc4_1: usdhc4grp-1 { | ||
75 | fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ | ||
76 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ | ||
77 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ | ||
78 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ | ||
79 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ | ||
80 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ | ||
81 | 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ | ||
82 | 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ | ||
83 | 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ | ||
84 | 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | ||
85 | }; | ||
86 | }; | ||
87 | .... | ||
88 | }; | ||
89 | Refer to the IOMUXC controller chapter in imx6q datasheet, | ||
90 | 0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, | ||
91 | 80Ohm driver strength and Fast Slew Rate. | ||
92 | User should refer to each SoC spec to set the correct value. | ||
93 | |||
94 | TODO: when dtc macro support is available, we can change above raw data | ||
95 | to dt macro which can get better readability in dts file. | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt deleted file mode 100644 index 1183f1a3be3..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt +++ /dev/null | |||
@@ -1,984 +0,0 @@ | |||
1 | * Freescale IMX35 IOMUX Controller | ||
2 | |||
3 | Please refer to fsl,imx-pinctrl.txt in this directory for common binding part | ||
4 | and usage. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "fsl,imx35-iomuxc" | ||
8 | - fsl,pins: two integers array, represents a group of pins mux and config | ||
9 | setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a | ||
10 | pin working on a specific function, CONFIG is the pad setting value like | ||
11 | pull-up for this pin. Please refer to imx35 datasheet for the valid pad | ||
12 | config settings. | ||
13 | |||
14 | CONFIG bits definition: | ||
15 | PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) | ||
16 | PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) | ||
17 | PAD_CTL_HYS (1 << 8) | ||
18 | PAD_CTL_PKE (1 << 7) | ||
19 | PAD_CTL_PUE (1 << 6) | ||
20 | PAD_CTL_PUS_100K_DOWN (0 << 4) | ||
21 | PAD_CTL_PUS_47K_UP (1 << 4) | ||
22 | PAD_CTL_PUS_100K_UP (2 << 4) | ||
23 | PAD_CTL_PUS_22K_UP (3 << 4) | ||
24 | PAD_CTL_ODE_CMOS (0 << 3) | ||
25 | PAD_CTL_ODE_OPENDRAIN (1 << 3) | ||
26 | PAD_CTL_DSE_NOMINAL (0 << 1) | ||
27 | PAD_CTL_DSE_HIGH (1 << 1) | ||
28 | PAD_CTL_DSE_MAX (2 << 1) | ||
29 | PAD_CTL_SRE_FAST (1 << 0) | ||
30 | PAD_CTL_SRE_SLOW (0 << 0) | ||
31 | |||
32 | See below for available PIN_FUNC_ID for imx35: | ||
33 | 0 MX35_PAD_CAPTURE__GPT_CAPIN1 | ||
34 | 1 MX35_PAD_CAPTURE__GPT_CMPOUT2 | ||
35 | 2 MX35_PAD_CAPTURE__CSPI2_SS1 | ||
36 | 3 MX35_PAD_CAPTURE__EPIT1_EPITO | ||
37 | 4 MX35_PAD_CAPTURE__CCM_CLK32K | ||
38 | 5 MX35_PAD_CAPTURE__GPIO1_4 | ||
39 | 6 MX35_PAD_COMPARE__GPT_CMPOUT1 | ||
40 | 7 MX35_PAD_COMPARE__GPT_CAPIN2 | ||
41 | 8 MX35_PAD_COMPARE__GPT_CMPOUT3 | ||
42 | 9 MX35_PAD_COMPARE__EPIT2_EPITO | ||
43 | 10 MX35_PAD_COMPARE__GPIO1_5 | ||
44 | 11 MX35_PAD_COMPARE__SDMA_EXTDMA_2 | ||
45 | 12 MX35_PAD_WDOG_RST__WDOG_WDOG_B | ||
46 | 13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE | ||
47 | 14 MX35_PAD_WDOG_RST__GPIO1_6 | ||
48 | 15 MX35_PAD_GPIO1_0__GPIO1_0 | ||
49 | 16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY | ||
50 | 17 MX35_PAD_GPIO1_0__OWIRE_LINE | ||
51 | 18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 | ||
52 | 19 MX35_PAD_GPIO1_1__GPIO1_1 | ||
53 | 20 MX35_PAD_GPIO1_1__PWM_PWMO | ||
54 | 21 MX35_PAD_GPIO1_1__CSPI1_SS2 | ||
55 | 22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT | ||
56 | 23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 | ||
57 | 24 MX35_PAD_GPIO2_0__GPIO2_0 | ||
58 | 25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK | ||
59 | 26 MX35_PAD_GPIO3_0__GPIO3_0 | ||
60 | 27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK | ||
61 | 28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B | ||
62 | 29 MX35_PAD_POR_B__CCM_POR_B | ||
63 | 30 MX35_PAD_CLKO__CCM_CLKO | ||
64 | 31 MX35_PAD_CLKO__GPIO1_8 | ||
65 | 32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 | ||
66 | 33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 | ||
67 | 34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 | ||
68 | 35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 | ||
69 | 36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 | ||
70 | 37 MX35_PAD_VSTBY__CCM_VSTBY | ||
71 | 38 MX35_PAD_VSTBY__GPIO1_7 | ||
72 | 39 MX35_PAD_A0__EMI_EIM_DA_L_0 | ||
73 | 40 MX35_PAD_A1__EMI_EIM_DA_L_1 | ||
74 | 41 MX35_PAD_A2__EMI_EIM_DA_L_2 | ||
75 | 42 MX35_PAD_A3__EMI_EIM_DA_L_3 | ||
76 | 43 MX35_PAD_A4__EMI_EIM_DA_L_4 | ||
77 | 44 MX35_PAD_A5__EMI_EIM_DA_L_5 | ||
78 | 45 MX35_PAD_A6__EMI_EIM_DA_L_6 | ||
79 | 46 MX35_PAD_A7__EMI_EIM_DA_L_7 | ||
80 | 47 MX35_PAD_A8__EMI_EIM_DA_H_8 | ||
81 | 48 MX35_PAD_A9__EMI_EIM_DA_H_9 | ||
82 | 49 MX35_PAD_A10__EMI_EIM_DA_H_10 | ||
83 | 50 MX35_PAD_MA10__EMI_MA10 | ||
84 | 51 MX35_PAD_A11__EMI_EIM_DA_H_11 | ||
85 | 52 MX35_PAD_A12__EMI_EIM_DA_H_12 | ||
86 | 53 MX35_PAD_A13__EMI_EIM_DA_H_13 | ||
87 | 54 MX35_PAD_A14__EMI_EIM_DA_H2_14 | ||
88 | 55 MX35_PAD_A15__EMI_EIM_DA_H2_15 | ||
89 | 56 MX35_PAD_A16__EMI_EIM_A_16 | ||
90 | 57 MX35_PAD_A17__EMI_EIM_A_17 | ||
91 | 58 MX35_PAD_A18__EMI_EIM_A_18 | ||
92 | 59 MX35_PAD_A19__EMI_EIM_A_19 | ||
93 | 60 MX35_PAD_A20__EMI_EIM_A_20 | ||
94 | 61 MX35_PAD_A21__EMI_EIM_A_21 | ||
95 | 62 MX35_PAD_A22__EMI_EIM_A_22 | ||
96 | 63 MX35_PAD_A23__EMI_EIM_A_23 | ||
97 | 64 MX35_PAD_A24__EMI_EIM_A_24 | ||
98 | 65 MX35_PAD_A25__EMI_EIM_A_25 | ||
99 | 66 MX35_PAD_SDBA1__EMI_EIM_SDBA1 | ||
100 | 67 MX35_PAD_SDBA0__EMI_EIM_SDBA0 | ||
101 | 68 MX35_PAD_SD0__EMI_DRAM_D_0 | ||
102 | 69 MX35_PAD_SD1__EMI_DRAM_D_1 | ||
103 | 70 MX35_PAD_SD2__EMI_DRAM_D_2 | ||
104 | 71 MX35_PAD_SD3__EMI_DRAM_D_3 | ||
105 | 72 MX35_PAD_SD4__EMI_DRAM_D_4 | ||
106 | 73 MX35_PAD_SD5__EMI_DRAM_D_5 | ||
107 | 74 MX35_PAD_SD6__EMI_DRAM_D_6 | ||
108 | 75 MX35_PAD_SD7__EMI_DRAM_D_7 | ||
109 | 76 MX35_PAD_SD8__EMI_DRAM_D_8 | ||
110 | 77 MX35_PAD_SD9__EMI_DRAM_D_9 | ||
111 | 78 MX35_PAD_SD10__EMI_DRAM_D_10 | ||
112 | 79 MX35_PAD_SD11__EMI_DRAM_D_11 | ||
113 | 80 MX35_PAD_SD12__EMI_DRAM_D_12 | ||
114 | 81 MX35_PAD_SD13__EMI_DRAM_D_13 | ||
115 | 82 MX35_PAD_SD14__EMI_DRAM_D_14 | ||
116 | 83 MX35_PAD_SD15__EMI_DRAM_D_15 | ||
117 | 84 MX35_PAD_SD16__EMI_DRAM_D_16 | ||
118 | 85 MX35_PAD_SD17__EMI_DRAM_D_17 | ||
119 | 86 MX35_PAD_SD18__EMI_DRAM_D_18 | ||
120 | 87 MX35_PAD_SD19__EMI_DRAM_D_19 | ||
121 | 88 MX35_PAD_SD20__EMI_DRAM_D_20 | ||
122 | 89 MX35_PAD_SD21__EMI_DRAM_D_21 | ||
123 | 90 MX35_PAD_SD22__EMI_DRAM_D_22 | ||
124 | 91 MX35_PAD_SD23__EMI_DRAM_D_23 | ||
125 | 92 MX35_PAD_SD24__EMI_DRAM_D_24 | ||
126 | 93 MX35_PAD_SD25__EMI_DRAM_D_25 | ||
127 | 94 MX35_PAD_SD26__EMI_DRAM_D_26 | ||
128 | 95 MX35_PAD_SD27__EMI_DRAM_D_27 | ||
129 | 96 MX35_PAD_SD28__EMI_DRAM_D_28 | ||
130 | 97 MX35_PAD_SD29__EMI_DRAM_D_29 | ||
131 | 98 MX35_PAD_SD30__EMI_DRAM_D_30 | ||
132 | 99 MX35_PAD_SD31__EMI_DRAM_D_31 | ||
133 | 100 MX35_PAD_DQM0__EMI_DRAM_DQM_0 | ||
134 | 101 MX35_PAD_DQM1__EMI_DRAM_DQM_1 | ||
135 | 102 MX35_PAD_DQM2__EMI_DRAM_DQM_2 | ||
136 | 103 MX35_PAD_DQM3__EMI_DRAM_DQM_3 | ||
137 | 104 MX35_PAD_EB0__EMI_EIM_EB0_B | ||
138 | 105 MX35_PAD_EB1__EMI_EIM_EB1_B | ||
139 | 106 MX35_PAD_OE__EMI_EIM_OE | ||
140 | 107 MX35_PAD_CS0__EMI_EIM_CS0 | ||
141 | 108 MX35_PAD_CS1__EMI_EIM_CS1 | ||
142 | 109 MX35_PAD_CS1__EMI_NANDF_CE3 | ||
143 | 110 MX35_PAD_CS2__EMI_EIM_CS2 | ||
144 | 111 MX35_PAD_CS3__EMI_EIM_CS3 | ||
145 | 112 MX35_PAD_CS4__EMI_EIM_CS4 | ||
146 | 113 MX35_PAD_CS4__EMI_DTACK_B | ||
147 | 114 MX35_PAD_CS4__EMI_NANDF_CE1 | ||
148 | 115 MX35_PAD_CS4__GPIO1_20 | ||
149 | 116 MX35_PAD_CS5__EMI_EIM_CS5 | ||
150 | 117 MX35_PAD_CS5__CSPI2_SS2 | ||
151 | 118 MX35_PAD_CS5__CSPI1_SS2 | ||
152 | 119 MX35_PAD_CS5__EMI_NANDF_CE2 | ||
153 | 120 MX35_PAD_CS5__GPIO1_21 | ||
154 | 121 MX35_PAD_NF_CE0__EMI_NANDF_CE0 | ||
155 | 122 MX35_PAD_NF_CE0__GPIO1_22 | ||
156 | 123 MX35_PAD_ECB__EMI_EIM_ECB | ||
157 | 124 MX35_PAD_LBA__EMI_EIM_LBA | ||
158 | 125 MX35_PAD_BCLK__EMI_EIM_BCLK | ||
159 | 126 MX35_PAD_RW__EMI_EIM_RW | ||
160 | 127 MX35_PAD_RAS__EMI_DRAM_RAS | ||
161 | 128 MX35_PAD_CAS__EMI_DRAM_CAS | ||
162 | 129 MX35_PAD_SDWE__EMI_DRAM_SDWE | ||
163 | 130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 | ||
164 | 131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 | ||
165 | 132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK | ||
166 | 133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 | ||
167 | 134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 | ||
168 | 135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 | ||
169 | 136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 | ||
170 | 137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B | ||
171 | 138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 | ||
172 | 139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC | ||
173 | 140 MX35_PAD_NFWE_B__GPIO2_18 | ||
174 | 141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 | ||
175 | 142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B | ||
176 | 143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR | ||
177 | 144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK | ||
178 | 145 MX35_PAD_NFRE_B__GPIO2_19 | ||
179 | 146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 | ||
180 | 147 MX35_PAD_NFALE__EMI_NANDF_ALE | ||
181 | 148 MX35_PAD_NFALE__USB_TOP_USBH2_STP | ||
182 | 149 MX35_PAD_NFALE__IPU_DISPB_CS0 | ||
183 | 150 MX35_PAD_NFALE__GPIO2_20 | ||
184 | 151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 | ||
185 | 152 MX35_PAD_NFCLE__EMI_NANDF_CLE | ||
186 | 153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT | ||
187 | 154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS | ||
188 | 155 MX35_PAD_NFCLE__GPIO2_21 | ||
189 | 156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 | ||
190 | 157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B | ||
191 | 158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 | ||
192 | 159 MX35_PAD_NFWP_B__IPU_DISPB_WR | ||
193 | 160 MX35_PAD_NFWP_B__GPIO2_22 | ||
194 | 161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL | ||
195 | 162 MX35_PAD_NFRB__EMI_NANDF_RB | ||
196 | 163 MX35_PAD_NFRB__IPU_DISPB_RD | ||
197 | 164 MX35_PAD_NFRB__GPIO2_23 | ||
198 | 165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK | ||
199 | 166 MX35_PAD_D15__EMI_EIM_D_15 | ||
200 | 167 MX35_PAD_D14__EMI_EIM_D_14 | ||
201 | 168 MX35_PAD_D13__EMI_EIM_D_13 | ||
202 | 169 MX35_PAD_D12__EMI_EIM_D_12 | ||
203 | 170 MX35_PAD_D11__EMI_EIM_D_11 | ||
204 | 171 MX35_PAD_D10__EMI_EIM_D_10 | ||
205 | 172 MX35_PAD_D9__EMI_EIM_D_9 | ||
206 | 173 MX35_PAD_D8__EMI_EIM_D_8 | ||
207 | 174 MX35_PAD_D7__EMI_EIM_D_7 | ||
208 | 175 MX35_PAD_D6__EMI_EIM_D_6 | ||
209 | 176 MX35_PAD_D5__EMI_EIM_D_5 | ||
210 | 177 MX35_PAD_D4__EMI_EIM_D_4 | ||
211 | 178 MX35_PAD_D3__EMI_EIM_D_3 | ||
212 | 179 MX35_PAD_D2__EMI_EIM_D_2 | ||
213 | 180 MX35_PAD_D1__EMI_EIM_D_1 | ||
214 | 181 MX35_PAD_D0__EMI_EIM_D_0 | ||
215 | 182 MX35_PAD_CSI_D8__IPU_CSI_D_8 | ||
216 | 183 MX35_PAD_CSI_D8__KPP_COL_0 | ||
217 | 184 MX35_PAD_CSI_D8__GPIO1_20 | ||
218 | 185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 | ||
219 | 186 MX35_PAD_CSI_D9__IPU_CSI_D_9 | ||
220 | 187 MX35_PAD_CSI_D9__KPP_COL_1 | ||
221 | 188 MX35_PAD_CSI_D9__GPIO1_21 | ||
222 | 189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 | ||
223 | 190 MX35_PAD_CSI_D10__IPU_CSI_D_10 | ||
224 | 191 MX35_PAD_CSI_D10__KPP_COL_2 | ||
225 | 192 MX35_PAD_CSI_D10__GPIO1_22 | ||
226 | 193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 | ||
227 | 194 MX35_PAD_CSI_D11__IPU_CSI_D_11 | ||
228 | 195 MX35_PAD_CSI_D11__KPP_COL_3 | ||
229 | 196 MX35_PAD_CSI_D11__GPIO1_23 | ||
230 | 197 MX35_PAD_CSI_D12__IPU_CSI_D_12 | ||
231 | 198 MX35_PAD_CSI_D12__KPP_ROW_0 | ||
232 | 199 MX35_PAD_CSI_D12__GPIO1_24 | ||
233 | 200 MX35_PAD_CSI_D13__IPU_CSI_D_13 | ||
234 | 201 MX35_PAD_CSI_D13__KPP_ROW_1 | ||
235 | 202 MX35_PAD_CSI_D13__GPIO1_25 | ||
236 | 203 MX35_PAD_CSI_D14__IPU_CSI_D_14 | ||
237 | 204 MX35_PAD_CSI_D14__KPP_ROW_2 | ||
238 | 205 MX35_PAD_CSI_D14__GPIO1_26 | ||
239 | 206 MX35_PAD_CSI_D15__IPU_CSI_D_15 | ||
240 | 207 MX35_PAD_CSI_D15__KPP_ROW_3 | ||
241 | 208 MX35_PAD_CSI_D15__GPIO1_27 | ||
242 | 209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK | ||
243 | 210 MX35_PAD_CSI_MCLK__GPIO1_28 | ||
244 | 211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC | ||
245 | 212 MX35_PAD_CSI_VSYNC__GPIO1_29 | ||
246 | 213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC | ||
247 | 214 MX35_PAD_CSI_HSYNC__GPIO1_30 | ||
248 | 215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK | ||
249 | 216 MX35_PAD_CSI_PIXCLK__GPIO1_31 | ||
250 | 217 MX35_PAD_I2C1_CLK__I2C1_SCL | ||
251 | 218 MX35_PAD_I2C1_CLK__GPIO2_24 | ||
252 | 219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK | ||
253 | 220 MX35_PAD_I2C1_DAT__I2C1_SDA | ||
254 | 221 MX35_PAD_I2C1_DAT__GPIO2_25 | ||
255 | 222 MX35_PAD_I2C2_CLK__I2C2_SCL | ||
256 | 223 MX35_PAD_I2C2_CLK__CAN1_TXCAN | ||
257 | 224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR | ||
258 | 225 MX35_PAD_I2C2_CLK__GPIO2_26 | ||
259 | 226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 | ||
260 | 227 MX35_PAD_I2C2_DAT__I2C2_SDA | ||
261 | 228 MX35_PAD_I2C2_DAT__CAN1_RXCAN | ||
262 | 229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC | ||
263 | 230 MX35_PAD_I2C2_DAT__GPIO2_27 | ||
264 | 231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 | ||
265 | 232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD | ||
266 | 233 MX35_PAD_STXD4__GPIO2_28 | ||
267 | 234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 | ||
268 | 235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD | ||
269 | 236 MX35_PAD_SRXD4__GPIO2_29 | ||
270 | 237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 | ||
271 | 238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC | ||
272 | 239 MX35_PAD_SCK4__GPIO2_30 | ||
273 | 240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 | ||
274 | 241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS | ||
275 | 242 MX35_PAD_STXFS4__GPIO2_31 | ||
276 | 243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 | ||
277 | 244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD | ||
278 | 245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 | ||
279 | 246 MX35_PAD_STXD5__CSPI2_MOSI | ||
280 | 247 MX35_PAD_STXD5__GPIO1_0 | ||
281 | 248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 | ||
282 | 249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD | ||
283 | 250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 | ||
284 | 251 MX35_PAD_SRXD5__CSPI2_MISO | ||
285 | 252 MX35_PAD_SRXD5__GPIO1_1 | ||
286 | 253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 | ||
287 | 254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC | ||
288 | 255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK | ||
289 | 256 MX35_PAD_SCK5__CSPI2_SCLK | ||
290 | 257 MX35_PAD_SCK5__GPIO1_2 | ||
291 | 258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 | ||
292 | 259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS | ||
293 | 260 MX35_PAD_STXFS5__CSPI2_RDY | ||
294 | 261 MX35_PAD_STXFS5__GPIO1_3 | ||
295 | 262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 | ||
296 | 263 MX35_PAD_SCKR__ESAI_SCKR | ||
297 | 264 MX35_PAD_SCKR__GPIO1_4 | ||
298 | 265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 | ||
299 | 266 MX35_PAD_FSR__ESAI_FSR | ||
300 | 267 MX35_PAD_FSR__GPIO1_5 | ||
301 | 268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 | ||
302 | 269 MX35_PAD_HCKR__ESAI_HCKR | ||
303 | 270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS | ||
304 | 271 MX35_PAD_HCKR__CSPI2_SS0 | ||
305 | 272 MX35_PAD_HCKR__IPU_FLASH_STROBE | ||
306 | 273 MX35_PAD_HCKR__GPIO1_6 | ||
307 | 274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 | ||
308 | 275 MX35_PAD_SCKT__ESAI_SCKT | ||
309 | 276 MX35_PAD_SCKT__GPIO1_7 | ||
310 | 277 MX35_PAD_SCKT__IPU_CSI_D_0 | ||
311 | 278 MX35_PAD_SCKT__KPP_ROW_2 | ||
312 | 279 MX35_PAD_FST__ESAI_FST | ||
313 | 280 MX35_PAD_FST__GPIO1_8 | ||
314 | 281 MX35_PAD_FST__IPU_CSI_D_1 | ||
315 | 282 MX35_PAD_FST__KPP_ROW_3 | ||
316 | 283 MX35_PAD_HCKT__ESAI_HCKT | ||
317 | 284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC | ||
318 | 285 MX35_PAD_HCKT__GPIO1_9 | ||
319 | 286 MX35_PAD_HCKT__IPU_CSI_D_2 | ||
320 | 287 MX35_PAD_HCKT__KPP_COL_3 | ||
321 | 288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0 | ||
322 | 289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC | ||
323 | 290 MX35_PAD_TX5_RX0__CSPI2_SS2 | ||
324 | 291 MX35_PAD_TX5_RX0__CAN2_TXCAN | ||
325 | 292 MX35_PAD_TX5_RX0__UART2_DTR | ||
326 | 293 MX35_PAD_TX5_RX0__GPIO1_10 | ||
327 | 294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 | ||
328 | 295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1 | ||
329 | 296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS | ||
330 | 297 MX35_PAD_TX4_RX1__CSPI2_SS3 | ||
331 | 298 MX35_PAD_TX4_RX1__CAN2_RXCAN | ||
332 | 299 MX35_PAD_TX4_RX1__UART2_DSR | ||
333 | 300 MX35_PAD_TX4_RX1__GPIO1_11 | ||
334 | 301 MX35_PAD_TX4_RX1__IPU_CSI_D_3 | ||
335 | 302 MX35_PAD_TX4_RX1__KPP_ROW_0 | ||
336 | 303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2 | ||
337 | 304 MX35_PAD_TX3_RX2__I2C3_SCL | ||
338 | 305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1 | ||
339 | 306 MX35_PAD_TX3_RX2__GPIO1_12 | ||
340 | 307 MX35_PAD_TX3_RX2__IPU_CSI_D_4 | ||
341 | 308 MX35_PAD_TX3_RX2__KPP_ROW_1 | ||
342 | 309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3 | ||
343 | 310 MX35_PAD_TX2_RX3__I2C3_SDA | ||
344 | 311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2 | ||
345 | 312 MX35_PAD_TX2_RX3__GPIO1_13 | ||
346 | 313 MX35_PAD_TX2_RX3__IPU_CSI_D_5 | ||
347 | 314 MX35_PAD_TX2_RX3__KPP_COL_0 | ||
348 | 315 MX35_PAD_TX1__ESAI_TX1 | ||
349 | 316 MX35_PAD_TX1__CCM_PMIC_RDY | ||
350 | 317 MX35_PAD_TX1__CSPI1_SS2 | ||
351 | 318 MX35_PAD_TX1__EMI_NANDF_CE3 | ||
352 | 319 MX35_PAD_TX1__UART2_RI | ||
353 | 320 MX35_PAD_TX1__GPIO1_14 | ||
354 | 321 MX35_PAD_TX1__IPU_CSI_D_6 | ||
355 | 322 MX35_PAD_TX1__KPP_COL_1 | ||
356 | 323 MX35_PAD_TX0__ESAI_TX0 | ||
357 | 324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK | ||
358 | 325 MX35_PAD_TX0__CSPI1_SS3 | ||
359 | 326 MX35_PAD_TX0__EMI_DTACK_B | ||
360 | 327 MX35_PAD_TX0__UART2_DCD | ||
361 | 328 MX35_PAD_TX0__GPIO1_15 | ||
362 | 329 MX35_PAD_TX0__IPU_CSI_D_7 | ||
363 | 330 MX35_PAD_TX0__KPP_COL_2 | ||
364 | 331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI | ||
365 | 332 MX35_PAD_CSPI1_MOSI__GPIO1_16 | ||
366 | 333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 | ||
367 | 334 MX35_PAD_CSPI1_MISO__CSPI1_MISO | ||
368 | 335 MX35_PAD_CSPI1_MISO__GPIO1_17 | ||
369 | 336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 | ||
370 | 337 MX35_PAD_CSPI1_SS0__CSPI1_SS0 | ||
371 | 338 MX35_PAD_CSPI1_SS0__OWIRE_LINE | ||
372 | 339 MX35_PAD_CSPI1_SS0__CSPI2_SS3 | ||
373 | 340 MX35_PAD_CSPI1_SS0__GPIO1_18 | ||
374 | 341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 | ||
375 | 342 MX35_PAD_CSPI1_SS1__CSPI1_SS1 | ||
376 | 343 MX35_PAD_CSPI1_SS1__PWM_PWMO | ||
377 | 344 MX35_PAD_CSPI1_SS1__CCM_CLK32K | ||
378 | 345 MX35_PAD_CSPI1_SS1__GPIO1_19 | ||
379 | 346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 | ||
380 | 347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 | ||
381 | 348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK | ||
382 | 349 MX35_PAD_CSPI1_SCLK__GPIO3_4 | ||
383 | 350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 | ||
384 | 351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 | ||
385 | 352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY | ||
386 | 353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 | ||
387 | 354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 | ||
388 | 355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 | ||
389 | 356 MX35_PAD_RXD1__UART1_RXD_MUX | ||
390 | 357 MX35_PAD_RXD1__CSPI2_MOSI | ||
391 | 358 MX35_PAD_RXD1__KPP_COL_4 | ||
392 | 359 MX35_PAD_RXD1__GPIO3_6 | ||
393 | 360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 | ||
394 | 361 MX35_PAD_TXD1__UART1_TXD_MUX | ||
395 | 362 MX35_PAD_TXD1__CSPI2_MISO | ||
396 | 363 MX35_PAD_TXD1__KPP_COL_5 | ||
397 | 364 MX35_PAD_TXD1__GPIO3_7 | ||
398 | 365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 | ||
399 | 366 MX35_PAD_RTS1__UART1_RTS | ||
400 | 367 MX35_PAD_RTS1__CSPI2_SCLK | ||
401 | 368 MX35_PAD_RTS1__I2C3_SCL | ||
402 | 369 MX35_PAD_RTS1__IPU_CSI_D_0 | ||
403 | 370 MX35_PAD_RTS1__KPP_COL_6 | ||
404 | 371 MX35_PAD_RTS1__GPIO3_8 | ||
405 | 372 MX35_PAD_RTS1__EMI_NANDF_CE1 | ||
406 | 373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 | ||
407 | 374 MX35_PAD_CTS1__UART1_CTS | ||
408 | 375 MX35_PAD_CTS1__CSPI2_RDY | ||
409 | 376 MX35_PAD_CTS1__I2C3_SDA | ||
410 | 377 MX35_PAD_CTS1__IPU_CSI_D_1 | ||
411 | 378 MX35_PAD_CTS1__KPP_COL_7 | ||
412 | 379 MX35_PAD_CTS1__GPIO3_9 | ||
413 | 380 MX35_PAD_CTS1__EMI_NANDF_CE2 | ||
414 | 381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 | ||
415 | 382 MX35_PAD_RXD2__UART2_RXD_MUX | ||
416 | 383 MX35_PAD_RXD2__KPP_ROW_4 | ||
417 | 384 MX35_PAD_RXD2__GPIO3_10 | ||
418 | 385 MX35_PAD_TXD2__UART2_TXD_MUX | ||
419 | 386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK | ||
420 | 387 MX35_PAD_TXD2__KPP_ROW_5 | ||
421 | 388 MX35_PAD_TXD2__GPIO3_11 | ||
422 | 389 MX35_PAD_RTS2__UART2_RTS | ||
423 | 390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1 | ||
424 | 391 MX35_PAD_RTS2__CAN2_RXCAN | ||
425 | 392 MX35_PAD_RTS2__IPU_CSI_D_2 | ||
426 | 393 MX35_PAD_RTS2__KPP_ROW_6 | ||
427 | 394 MX35_PAD_RTS2__GPIO3_12 | ||
428 | 395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC | ||
429 | 396 MX35_PAD_RTS2__UART3_RXD_MUX | ||
430 | 397 MX35_PAD_CTS2__UART2_CTS | ||
431 | 398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 | ||
432 | 399 MX35_PAD_CTS2__CAN2_TXCAN | ||
433 | 400 MX35_PAD_CTS2__IPU_CSI_D_3 | ||
434 | 401 MX35_PAD_CTS2__KPP_ROW_7 | ||
435 | 402 MX35_PAD_CTS2__GPIO3_13 | ||
436 | 403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS | ||
437 | 404 MX35_PAD_CTS2__UART3_TXD_MUX | ||
438 | 405 MX35_PAD_RTCK__ARM11P_TOP_RTCK | ||
439 | 406 MX35_PAD_TCK__SJC_TCK | ||
440 | 407 MX35_PAD_TMS__SJC_TMS | ||
441 | 408 MX35_PAD_TDI__SJC_TDI | ||
442 | 409 MX35_PAD_TDO__SJC_TDO | ||
443 | 410 MX35_PAD_TRSTB__SJC_TRSTB | ||
444 | 411 MX35_PAD_DE_B__SJC_DE_B | ||
445 | 412 MX35_PAD_SJC_MOD__SJC_MOD | ||
446 | 413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR | ||
447 | 414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR | ||
448 | 415 MX35_PAD_USBOTG_PWR__GPIO3_14 | ||
449 | 416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC | ||
450 | 417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC | ||
451 | 418 MX35_PAD_USBOTG_OC__GPIO3_15 | ||
452 | 419 MX35_PAD_LD0__IPU_DISPB_DAT_0 | ||
453 | 420 MX35_PAD_LD0__GPIO2_0 | ||
454 | 421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 | ||
455 | 422 MX35_PAD_LD1__IPU_DISPB_DAT_1 | ||
456 | 423 MX35_PAD_LD1__GPIO2_1 | ||
457 | 424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 | ||
458 | 425 MX35_PAD_LD2__IPU_DISPB_DAT_2 | ||
459 | 426 MX35_PAD_LD2__GPIO2_2 | ||
460 | 427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 | ||
461 | 428 MX35_PAD_LD3__IPU_DISPB_DAT_3 | ||
462 | 429 MX35_PAD_LD3__GPIO2_3 | ||
463 | 430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 | ||
464 | 431 MX35_PAD_LD4__IPU_DISPB_DAT_4 | ||
465 | 432 MX35_PAD_LD4__GPIO2_4 | ||
466 | 433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 | ||
467 | 434 MX35_PAD_LD5__IPU_DISPB_DAT_5 | ||
468 | 435 MX35_PAD_LD5__GPIO2_5 | ||
469 | 436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 | ||
470 | 437 MX35_PAD_LD6__IPU_DISPB_DAT_6 | ||
471 | 438 MX35_PAD_LD6__GPIO2_6 | ||
472 | 439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 | ||
473 | 440 MX35_PAD_LD7__IPU_DISPB_DAT_7 | ||
474 | 441 MX35_PAD_LD7__GPIO2_7 | ||
475 | 442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 | ||
476 | 443 MX35_PAD_LD8__IPU_DISPB_DAT_8 | ||
477 | 444 MX35_PAD_LD8__GPIO2_8 | ||
478 | 445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 | ||
479 | 446 MX35_PAD_LD9__IPU_DISPB_DAT_9 | ||
480 | 447 MX35_PAD_LD9__GPIO2_9 | ||
481 | 448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 | ||
482 | 449 MX35_PAD_LD10__IPU_DISPB_DAT_10 | ||
483 | 450 MX35_PAD_LD10__GPIO2_10 | ||
484 | 451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 | ||
485 | 452 MX35_PAD_LD11__IPU_DISPB_DAT_11 | ||
486 | 453 MX35_PAD_LD11__GPIO2_11 | ||
487 | 454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 | ||
488 | 455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4 | ||
489 | 456 MX35_PAD_LD12__IPU_DISPB_DAT_12 | ||
490 | 457 MX35_PAD_LD12__GPIO2_12 | ||
491 | 458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 | ||
492 | 459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5 | ||
493 | 460 MX35_PAD_LD13__IPU_DISPB_DAT_13 | ||
494 | 461 MX35_PAD_LD13__GPIO2_13 | ||
495 | 462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 | ||
496 | 463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6 | ||
497 | 464 MX35_PAD_LD14__IPU_DISPB_DAT_14 | ||
498 | 465 MX35_PAD_LD14__GPIO2_14 | ||
499 | 466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 | ||
500 | 467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7 | ||
501 | 468 MX35_PAD_LD15__IPU_DISPB_DAT_15 | ||
502 | 469 MX35_PAD_LD15__GPIO2_15 | ||
503 | 470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 | ||
504 | 471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8 | ||
505 | 472 MX35_PAD_LD16__IPU_DISPB_DAT_16 | ||
506 | 473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC | ||
507 | 474 MX35_PAD_LD16__GPIO2_16 | ||
508 | 475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 | ||
509 | 476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9 | ||
510 | 477 MX35_PAD_LD17__IPU_DISPB_DAT_17 | ||
511 | 478 MX35_PAD_LD17__IPU_DISPB_CS2 | ||
512 | 479 MX35_PAD_LD17__GPIO2_17 | ||
513 | 480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 | ||
514 | 481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10 | ||
515 | 482 MX35_PAD_LD18__IPU_DISPB_DAT_18 | ||
516 | 483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC | ||
517 | 484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC | ||
518 | 485 MX35_PAD_LD18__ESDHC3_CMD | ||
519 | 486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 | ||
520 | 487 MX35_PAD_LD18__GPIO3_24 | ||
521 | 488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 | ||
522 | 489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11 | ||
523 | 490 MX35_PAD_LD19__IPU_DISPB_DAT_19 | ||
524 | 491 MX35_PAD_LD19__IPU_DISPB_BCLK | ||
525 | 492 MX35_PAD_LD19__IPU_DISPB_CS1 | ||
526 | 493 MX35_PAD_LD19__ESDHC3_CLK | ||
527 | 494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR | ||
528 | 495 MX35_PAD_LD19__GPIO3_25 | ||
529 | 496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 | ||
530 | 497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12 | ||
531 | 498 MX35_PAD_LD20__IPU_DISPB_DAT_20 | ||
532 | 499 MX35_PAD_LD20__IPU_DISPB_CS0 | ||
533 | 500 MX35_PAD_LD20__IPU_DISPB_SD_CLK | ||
534 | 501 MX35_PAD_LD20__ESDHC3_DAT0 | ||
535 | 502 MX35_PAD_LD20__GPIO3_26 | ||
536 | 503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 | ||
537 | 504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13 | ||
538 | 505 MX35_PAD_LD21__IPU_DISPB_DAT_21 | ||
539 | 506 MX35_PAD_LD21__IPU_DISPB_PAR_RS | ||
540 | 507 MX35_PAD_LD21__IPU_DISPB_SER_RS | ||
541 | 508 MX35_PAD_LD21__ESDHC3_DAT1 | ||
542 | 509 MX35_PAD_LD21__USB_TOP_USBOTG_STP | ||
543 | 510 MX35_PAD_LD21__GPIO3_27 | ||
544 | 511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL | ||
545 | 512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14 | ||
546 | 513 MX35_PAD_LD22__IPU_DISPB_DAT_22 | ||
547 | 514 MX35_PAD_LD22__IPU_DISPB_WR | ||
548 | 515 MX35_PAD_LD22__IPU_DISPB_SD_D_I | ||
549 | 516 MX35_PAD_LD22__ESDHC3_DAT2 | ||
550 | 517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT | ||
551 | 518 MX35_PAD_LD22__GPIO3_28 | ||
552 | 519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR | ||
553 | 520 MX35_PAD_LD22__ARM11P_TOP_TRCTL | ||
554 | 521 MX35_PAD_LD23__IPU_DISPB_DAT_23 | ||
555 | 522 MX35_PAD_LD23__IPU_DISPB_RD | ||
556 | 523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO | ||
557 | 524 MX35_PAD_LD23__ESDHC3_DAT3 | ||
558 | 525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 | ||
559 | 526 MX35_PAD_LD23__GPIO3_29 | ||
560 | 527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS | ||
561 | 528 MX35_PAD_LD23__ARM11P_TOP_TRCLK | ||
562 | 529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC | ||
563 | 530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO | ||
564 | 531 MX35_PAD_D3_HSYNC__GPIO3_30 | ||
565 | 532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE | ||
566 | 533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 | ||
567 | 534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK | ||
568 | 535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK | ||
569 | 536 MX35_PAD_D3_FPSHIFT__GPIO3_31 | ||
570 | 537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 | ||
571 | 538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 | ||
572 | 539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY | ||
573 | 540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O | ||
574 | 541 MX35_PAD_D3_DRDY__GPIO1_0 | ||
575 | 542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 | ||
576 | 543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 | ||
577 | 544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR | ||
578 | 545 MX35_PAD_CONTRAST__GPIO1_1 | ||
579 | 546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 | ||
580 | 547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 | ||
581 | 548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC | ||
582 | 549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 | ||
583 | 550 MX35_PAD_D3_VSYNC__GPIO1_2 | ||
584 | 551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD | ||
585 | 552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 | ||
586 | 553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV | ||
587 | 554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS | ||
588 | 555 MX35_PAD_D3_REV__GPIO1_3 | ||
589 | 556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB | ||
590 | 557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 | ||
591 | 558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS | ||
592 | 559 MX35_PAD_D3_CLS__IPU_DISPB_CS2 | ||
593 | 560 MX35_PAD_D3_CLS__GPIO1_4 | ||
594 | 561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 | ||
595 | 562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 | ||
596 | 563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL | ||
597 | 564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC | ||
598 | 565 MX35_PAD_D3_SPL__GPIO1_5 | ||
599 | 566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 | ||
600 | 567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 | ||
601 | 568 MX35_PAD_SD1_CMD__ESDHC1_CMD | ||
602 | 569 MX35_PAD_SD1_CMD__MSHC_SCLK | ||
603 | 570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC | ||
604 | 571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 | ||
605 | 572 MX35_PAD_SD1_CMD__GPIO1_6 | ||
606 | 573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL | ||
607 | 574 MX35_PAD_SD1_CLK__ESDHC1_CLK | ||
608 | 575 MX35_PAD_SD1_CLK__MSHC_BS | ||
609 | 576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK | ||
610 | 577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 | ||
611 | 578 MX35_PAD_SD1_CLK__GPIO1_7 | ||
612 | 579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK | ||
613 | 580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0 | ||
614 | 581 MX35_PAD_SD1_DATA0__MSHC_DATA_0 | ||
615 | 582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 | ||
616 | 583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 | ||
617 | 584 MX35_PAD_SD1_DATA0__GPIO1_8 | ||
618 | 585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 | ||
619 | 586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1 | ||
620 | 587 MX35_PAD_SD1_DATA1__MSHC_DATA_1 | ||
621 | 588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS | ||
622 | 589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 | ||
623 | 590 MX35_PAD_SD1_DATA1__GPIO1_9 | ||
624 | 591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 | ||
625 | 592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2 | ||
626 | 593 MX35_PAD_SD1_DATA2__MSHC_DATA_2 | ||
627 | 594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR | ||
628 | 595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 | ||
629 | 596 MX35_PAD_SD1_DATA2__GPIO1_10 | ||
630 | 597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 | ||
631 | 598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3 | ||
632 | 599 MX35_PAD_SD1_DATA3__MSHC_DATA_3 | ||
633 | 600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD | ||
634 | 601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 | ||
635 | 602 MX35_PAD_SD1_DATA3__GPIO1_11 | ||
636 | 603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 | ||
637 | 604 MX35_PAD_SD2_CMD__ESDHC2_CMD | ||
638 | 605 MX35_PAD_SD2_CMD__I2C3_SCL | ||
639 | 606 MX35_PAD_SD2_CMD__ESDHC1_DAT4 | ||
640 | 607 MX35_PAD_SD2_CMD__IPU_CSI_D_2 | ||
641 | 608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 | ||
642 | 609 MX35_PAD_SD2_CMD__GPIO2_0 | ||
643 | 610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 | ||
644 | 611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC | ||
645 | 612 MX35_PAD_SD2_CLK__ESDHC2_CLK | ||
646 | 613 MX35_PAD_SD2_CLK__I2C3_SDA | ||
647 | 614 MX35_PAD_SD2_CLK__ESDHC1_DAT5 | ||
648 | 615 MX35_PAD_SD2_CLK__IPU_CSI_D_3 | ||
649 | 616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 | ||
650 | 617 MX35_PAD_SD2_CLK__GPIO2_1 | ||
651 | 618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 | ||
652 | 619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2 | ||
653 | 620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0 | ||
654 | 621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX | ||
655 | 622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6 | ||
656 | 623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4 | ||
657 | 624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 | ||
658 | 625 MX35_PAD_SD2_DATA0__GPIO2_2 | ||
659 | 626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK | ||
660 | 627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1 | ||
661 | 628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX | ||
662 | 629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7 | ||
663 | 630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5 | ||
664 | 631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 | ||
665 | 632 MX35_PAD_SD2_DATA1__GPIO2_3 | ||
666 | 633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2 | ||
667 | 634 MX35_PAD_SD2_DATA2__UART3_RTS | ||
668 | 635 MX35_PAD_SD2_DATA2__CAN1_RXCAN | ||
669 | 636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6 | ||
670 | 637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 | ||
671 | 638 MX35_PAD_SD2_DATA2__GPIO2_4 | ||
672 | 639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3 | ||
673 | 640 MX35_PAD_SD2_DATA3__UART3_CTS | ||
674 | 641 MX35_PAD_SD2_DATA3__CAN1_TXCAN | ||
675 | 642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7 | ||
676 | 643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 | ||
677 | 644 MX35_PAD_SD2_DATA3__GPIO2_5 | ||
678 | 645 MX35_PAD_ATA_CS0__ATA_CS0 | ||
679 | 646 MX35_PAD_ATA_CS0__CSPI1_SS3 | ||
680 | 647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1 | ||
681 | 648 MX35_PAD_ATA_CS0__GPIO2_6 | ||
682 | 649 MX35_PAD_ATA_CS0__IPU_DIAGB_0 | ||
683 | 650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 | ||
684 | 651 MX35_PAD_ATA_CS1__ATA_CS1 | ||
685 | 652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2 | ||
686 | 653 MX35_PAD_ATA_CS1__CSPI2_SS0 | ||
687 | 654 MX35_PAD_ATA_CS1__GPIO2_7 | ||
688 | 655 MX35_PAD_ATA_CS1__IPU_DIAGB_1 | ||
689 | 656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 | ||
690 | 657 MX35_PAD_ATA_DIOR__ATA_DIOR | ||
691 | 658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0 | ||
692 | 659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR | ||
693 | 660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 | ||
694 | 661 MX35_PAD_ATA_DIOR__CSPI2_SS1 | ||
695 | 662 MX35_PAD_ATA_DIOR__GPIO2_8 | ||
696 | 663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2 | ||
697 | 664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 | ||
698 | 665 MX35_PAD_ATA_DIOW__ATA_DIOW | ||
699 | 666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1 | ||
700 | 667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP | ||
701 | 668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 | ||
702 | 669 MX35_PAD_ATA_DIOW__CSPI2_MOSI | ||
703 | 670 MX35_PAD_ATA_DIOW__GPIO2_9 | ||
704 | 671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3 | ||
705 | 672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 | ||
706 | 673 MX35_PAD_ATA_DMACK__ATA_DMACK | ||
707 | 674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2 | ||
708 | 675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT | ||
709 | 676 MX35_PAD_ATA_DMACK__CSPI2_MISO | ||
710 | 677 MX35_PAD_ATA_DMACK__GPIO2_10 | ||
711 | 678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4 | ||
712 | 679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 | ||
713 | 680 MX35_PAD_ATA_RESET_B__ATA_RESET_B | ||
714 | 681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 | ||
715 | 682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 | ||
716 | 683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O | ||
717 | 684 MX35_PAD_ATA_RESET_B__CSPI2_RDY | ||
718 | 685 MX35_PAD_ATA_RESET_B__GPIO2_11 | ||
719 | 686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 | ||
720 | 687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 | ||
721 | 688 MX35_PAD_ATA_IORDY__ATA_IORDY | ||
722 | 689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4 | ||
723 | 690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 | ||
724 | 691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO | ||
725 | 692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4 | ||
726 | 693 MX35_PAD_ATA_IORDY__GPIO2_12 | ||
727 | 694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6 | ||
728 | 695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 | ||
729 | 696 MX35_PAD_ATA_DATA0__ATA_DATA_0 | ||
730 | 697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5 | ||
731 | 698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 | ||
732 | 699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC | ||
733 | 700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5 | ||
734 | 701 MX35_PAD_ATA_DATA0__GPIO2_13 | ||
735 | 702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7 | ||
736 | 703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 | ||
737 | 704 MX35_PAD_ATA_DATA1__ATA_DATA_1 | ||
738 | 705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6 | ||
739 | 706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 | ||
740 | 707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK | ||
741 | 708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6 | ||
742 | 709 MX35_PAD_ATA_DATA1__GPIO2_14 | ||
743 | 710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8 | ||
744 | 711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 | ||
745 | 712 MX35_PAD_ATA_DATA2__ATA_DATA_2 | ||
746 | 713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7 | ||
747 | 714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 | ||
748 | 715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS | ||
749 | 716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7 | ||
750 | 717 MX35_PAD_ATA_DATA2__GPIO2_15 | ||
751 | 718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9 | ||
752 | 719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 | ||
753 | 720 MX35_PAD_ATA_DATA3__ATA_DATA_3 | ||
754 | 721 MX35_PAD_ATA_DATA3__ESDHC3_CLK | ||
755 | 722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 | ||
756 | 723 MX35_PAD_ATA_DATA3__CSPI2_SCLK | ||
757 | 724 MX35_PAD_ATA_DATA3__GPIO2_16 | ||
758 | 725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10 | ||
759 | 726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 | ||
760 | 727 MX35_PAD_ATA_DATA4__ATA_DATA_4 | ||
761 | 728 MX35_PAD_ATA_DATA4__ESDHC3_CMD | ||
762 | 729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 | ||
763 | 730 MX35_PAD_ATA_DATA4__GPIO2_17 | ||
764 | 731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11 | ||
765 | 732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 | ||
766 | 733 MX35_PAD_ATA_DATA5__ATA_DATA_5 | ||
767 | 734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 | ||
768 | 735 MX35_PAD_ATA_DATA5__GPIO2_18 | ||
769 | 736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12 | ||
770 | 737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 | ||
771 | 738 MX35_PAD_ATA_DATA6__ATA_DATA_6 | ||
772 | 739 MX35_PAD_ATA_DATA6__CAN1_TXCAN | ||
773 | 740 MX35_PAD_ATA_DATA6__UART1_DTR | ||
774 | 741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD | ||
775 | 742 MX35_PAD_ATA_DATA6__GPIO2_19 | ||
776 | 743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13 | ||
777 | 744 MX35_PAD_ATA_DATA7__ATA_DATA_7 | ||
778 | 745 MX35_PAD_ATA_DATA7__CAN1_RXCAN | ||
779 | 746 MX35_PAD_ATA_DATA7__UART1_DSR | ||
780 | 747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD | ||
781 | 748 MX35_PAD_ATA_DATA7__GPIO2_20 | ||
782 | 749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14 | ||
783 | 750 MX35_PAD_ATA_DATA8__ATA_DATA_8 | ||
784 | 751 MX35_PAD_ATA_DATA8__UART3_RTS | ||
785 | 752 MX35_PAD_ATA_DATA8__UART1_RI | ||
786 | 753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC | ||
787 | 754 MX35_PAD_ATA_DATA8__GPIO2_21 | ||
788 | 755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15 | ||
789 | 756 MX35_PAD_ATA_DATA9__ATA_DATA_9 | ||
790 | 757 MX35_PAD_ATA_DATA9__UART3_CTS | ||
791 | 758 MX35_PAD_ATA_DATA9__UART1_DCD | ||
792 | 759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS | ||
793 | 760 MX35_PAD_ATA_DATA9__GPIO2_22 | ||
794 | 761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16 | ||
795 | 762 MX35_PAD_ATA_DATA10__ATA_DATA_10 | ||
796 | 763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX | ||
797 | 764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC | ||
798 | 765 MX35_PAD_ATA_DATA10__GPIO2_23 | ||
799 | 766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17 | ||
800 | 767 MX35_PAD_ATA_DATA11__ATA_DATA_11 | ||
801 | 768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX | ||
802 | 769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS | ||
803 | 770 MX35_PAD_ATA_DATA11__GPIO2_24 | ||
804 | 771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18 | ||
805 | 772 MX35_PAD_ATA_DATA12__ATA_DATA_12 | ||
806 | 773 MX35_PAD_ATA_DATA12__I2C3_SCL | ||
807 | 774 MX35_PAD_ATA_DATA12__GPIO2_25 | ||
808 | 775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19 | ||
809 | 776 MX35_PAD_ATA_DATA13__ATA_DATA_13 | ||
810 | 777 MX35_PAD_ATA_DATA13__I2C3_SDA | ||
811 | 778 MX35_PAD_ATA_DATA13__GPIO2_26 | ||
812 | 779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20 | ||
813 | 780 MX35_PAD_ATA_DATA14__ATA_DATA_14 | ||
814 | 781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0 | ||
815 | 782 MX35_PAD_ATA_DATA14__KPP_ROW_0 | ||
816 | 783 MX35_PAD_ATA_DATA14__GPIO2_27 | ||
817 | 784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21 | ||
818 | 785 MX35_PAD_ATA_DATA15__ATA_DATA_15 | ||
819 | 786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1 | ||
820 | 787 MX35_PAD_ATA_DATA15__KPP_ROW_1 | ||
821 | 788 MX35_PAD_ATA_DATA15__GPIO2_28 | ||
822 | 789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22 | ||
823 | 790 MX35_PAD_ATA_INTRQ__ATA_INTRQ | ||
824 | 791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 | ||
825 | 792 MX35_PAD_ATA_INTRQ__KPP_ROW_2 | ||
826 | 793 MX35_PAD_ATA_INTRQ__GPIO2_29 | ||
827 | 794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 | ||
828 | 795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN | ||
829 | 796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 | ||
830 | 797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 | ||
831 | 798 MX35_PAD_ATA_BUFF_EN__GPIO2_30 | ||
832 | 799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 | ||
833 | 800 MX35_PAD_ATA_DMARQ__ATA_DMARQ | ||
834 | 801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 | ||
835 | 802 MX35_PAD_ATA_DMARQ__KPP_COL_0 | ||
836 | 803 MX35_PAD_ATA_DMARQ__GPIO2_31 | ||
837 | 804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 | ||
838 | 805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 | ||
839 | 806 MX35_PAD_ATA_DA0__ATA_DA_0 | ||
840 | 807 MX35_PAD_ATA_DA0__IPU_CSI_D_5 | ||
841 | 808 MX35_PAD_ATA_DA0__KPP_COL_1 | ||
842 | 809 MX35_PAD_ATA_DA0__GPIO3_0 | ||
843 | 810 MX35_PAD_ATA_DA0__IPU_DIAGB_26 | ||
844 | 811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 | ||
845 | 812 MX35_PAD_ATA_DA1__ATA_DA_1 | ||
846 | 813 MX35_PAD_ATA_DA1__IPU_CSI_D_6 | ||
847 | 814 MX35_PAD_ATA_DA1__KPP_COL_2 | ||
848 | 815 MX35_PAD_ATA_DA1__GPIO3_1 | ||
849 | 816 MX35_PAD_ATA_DA1__IPU_DIAGB_27 | ||
850 | 817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 | ||
851 | 818 MX35_PAD_ATA_DA2__ATA_DA_2 | ||
852 | 819 MX35_PAD_ATA_DA2__IPU_CSI_D_7 | ||
853 | 820 MX35_PAD_ATA_DA2__KPP_COL_3 | ||
854 | 821 MX35_PAD_ATA_DA2__GPIO3_2 | ||
855 | 822 MX35_PAD_ATA_DA2__IPU_DIAGB_28 | ||
856 | 823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 | ||
857 | 824 MX35_PAD_MLB_CLK__MLB_MLBCLK | ||
858 | 825 MX35_PAD_MLB_CLK__GPIO3_3 | ||
859 | 826 MX35_PAD_MLB_DAT__MLB_MLBDAT | ||
860 | 827 MX35_PAD_MLB_DAT__GPIO3_4 | ||
861 | 828 MX35_PAD_MLB_SIG__MLB_MLBSIG | ||
862 | 829 MX35_PAD_MLB_SIG__GPIO3_5 | ||
863 | 830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK | ||
864 | 831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 | ||
865 | 832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX | ||
866 | 833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR | ||
867 | 834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI | ||
868 | 835 MX35_PAD_FEC_TX_CLK__GPIO3_6 | ||
869 | 836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC | ||
870 | 837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 | ||
871 | 838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK | ||
872 | 839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 | ||
873 | 840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX | ||
874 | 841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP | ||
875 | 842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO | ||
876 | 843 MX35_PAD_FEC_RX_CLK__GPIO3_7 | ||
877 | 844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I | ||
878 | 845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 | ||
879 | 846 MX35_PAD_FEC_RX_DV__FEC_RX_DV | ||
880 | 847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 | ||
881 | 848 MX35_PAD_FEC_RX_DV__UART3_RTS | ||
882 | 849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT | ||
883 | 850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK | ||
884 | 851 MX35_PAD_FEC_RX_DV__GPIO3_8 | ||
885 | 852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK | ||
886 | 853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 | ||
887 | 854 MX35_PAD_FEC_COL__FEC_COL | ||
888 | 855 MX35_PAD_FEC_COL__ESDHC1_DAT7 | ||
889 | 856 MX35_PAD_FEC_COL__UART3_CTS | ||
890 | 857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 | ||
891 | 858 MX35_PAD_FEC_COL__CSPI2_RDY | ||
892 | 859 MX35_PAD_FEC_COL__GPIO3_9 | ||
893 | 860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS | ||
894 | 861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 | ||
895 | 862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0 | ||
896 | 863 MX35_PAD_FEC_RDATA0__PWM_PWMO | ||
897 | 864 MX35_PAD_FEC_RDATA0__UART3_DTR | ||
898 | 865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 | ||
899 | 866 MX35_PAD_FEC_RDATA0__CSPI2_SS0 | ||
900 | 867 MX35_PAD_FEC_RDATA0__GPIO3_10 | ||
901 | 868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 | ||
902 | 869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 | ||
903 | 870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0 | ||
904 | 871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 | ||
905 | 872 MX35_PAD_FEC_TDATA0__UART3_DSR | ||
906 | 873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 | ||
907 | 874 MX35_PAD_FEC_TDATA0__CSPI2_SS1 | ||
908 | 875 MX35_PAD_FEC_TDATA0__GPIO3_11 | ||
909 | 876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 | ||
910 | 877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 | ||
911 | 878 MX35_PAD_FEC_TX_EN__FEC_TX_EN | ||
912 | 879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 | ||
913 | 880 MX35_PAD_FEC_TX_EN__UART3_RI | ||
914 | 881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 | ||
915 | 882 MX35_PAD_FEC_TX_EN__GPIO3_12 | ||
916 | 883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS | ||
917 | 884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 | ||
918 | 885 MX35_PAD_FEC_MDC__FEC_MDC | ||
919 | 886 MX35_PAD_FEC_MDC__CAN2_TXCAN | ||
920 | 887 MX35_PAD_FEC_MDC__UART3_DCD | ||
921 | 888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 | ||
922 | 889 MX35_PAD_FEC_MDC__GPIO3_13 | ||
923 | 890 MX35_PAD_FEC_MDC__IPU_DISPB_WR | ||
924 | 891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 | ||
925 | 892 MX35_PAD_FEC_MDIO__FEC_MDIO | ||
926 | 893 MX35_PAD_FEC_MDIO__CAN2_RXCAN | ||
927 | 894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 | ||
928 | 895 MX35_PAD_FEC_MDIO__GPIO3_14 | ||
929 | 896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD | ||
930 | 897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 | ||
931 | 898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR | ||
932 | 899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE | ||
933 | 900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK | ||
934 | 901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 | ||
935 | 902 MX35_PAD_FEC_TX_ERR__GPIO3_15 | ||
936 | 903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC | ||
937 | 904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 | ||
938 | 905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR | ||
939 | 906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 | ||
940 | 907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 | ||
941 | 908 MX35_PAD_FEC_RX_ERR__KPP_COL_4 | ||
942 | 909 MX35_PAD_FEC_RX_ERR__GPIO3_16 | ||
943 | 910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO | ||
944 | 911 MX35_PAD_FEC_CRS__FEC_CRS | ||
945 | 912 MX35_PAD_FEC_CRS__IPU_CSI_D_1 | ||
946 | 913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR | ||
947 | 914 MX35_PAD_FEC_CRS__KPP_COL_5 | ||
948 | 915 MX35_PAD_FEC_CRS__GPIO3_17 | ||
949 | 916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE | ||
950 | 917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1 | ||
951 | 918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 | ||
952 | 919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC | ||
953 | 920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC | ||
954 | 921 MX35_PAD_FEC_RDATA1__KPP_COL_6 | ||
955 | 922 MX35_PAD_FEC_RDATA1__GPIO3_18 | ||
956 | 923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 | ||
957 | 924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1 | ||
958 | 925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 | ||
959 | 926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS | ||
960 | 927 MX35_PAD_FEC_TDATA1__KPP_COL_7 | ||
961 | 928 MX35_PAD_FEC_TDATA1__GPIO3_19 | ||
962 | 929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 | ||
963 | 930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2 | ||
964 | 931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 | ||
965 | 932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD | ||
966 | 933 MX35_PAD_FEC_RDATA2__KPP_ROW_4 | ||
967 | 934 MX35_PAD_FEC_RDATA2__GPIO3_20 | ||
968 | 935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2 | ||
969 | 936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 | ||
970 | 937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD | ||
971 | 938 MX35_PAD_FEC_TDATA2__KPP_ROW_5 | ||
972 | 939 MX35_PAD_FEC_TDATA2__GPIO3_21 | ||
973 | 940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3 | ||
974 | 941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 | ||
975 | 942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC | ||
976 | 943 MX35_PAD_FEC_RDATA3__KPP_ROW_6 | ||
977 | 944 MX35_PAD_FEC_RDATA3__GPIO3_22 | ||
978 | 945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3 | ||
979 | 946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 | ||
980 | 947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS | ||
981 | 948 MX35_PAD_FEC_TDATA3__KPP_ROW_7 | ||
982 | 949 MX35_PAD_FEC_TDATA3__GPIO3_23 | ||
983 | 950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK | ||
984 | 951 MX35_PAD_TEST_MODE__TCU_TEST_MODE | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt deleted file mode 100644 index b96fa4c3174..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt +++ /dev/null | |||
@@ -1,787 +0,0 @@ | |||
1 | * Freescale IMX51 IOMUX Controller | ||
2 | |||
3 | Please refer to fsl,imx-pinctrl.txt in this directory for common binding part | ||
4 | and usage. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "fsl,imx51-iomuxc" | ||
8 | - fsl,pins: two integers array, represents a group of pins mux and config | ||
9 | setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a | ||
10 | pin working on a specific function, CONFIG is the pad setting value like | ||
11 | pull-up for this pin. Please refer to imx51 datasheet for the valid pad | ||
12 | config settings. | ||
13 | |||
14 | CONFIG bits definition: | ||
15 | PAD_CTL_HVE (1 << 13) | ||
16 | PAD_CTL_HYS (1 << 8) | ||
17 | PAD_CTL_PKE (1 << 7) | ||
18 | PAD_CTL_PUE (1 << 6) | ||
19 | PAD_CTL_PUS_100K_DOWN (0 << 4) | ||
20 | PAD_CTL_PUS_47K_UP (1 << 4) | ||
21 | PAD_CTL_PUS_100K_UP (2 << 4) | ||
22 | PAD_CTL_PUS_22K_UP (3 << 4) | ||
23 | PAD_CTL_ODE (1 << 3) | ||
24 | PAD_CTL_DSE_LOW (0 << 1) | ||
25 | PAD_CTL_DSE_MED (1 << 1) | ||
26 | PAD_CTL_DSE_HIGH (2 << 1) | ||
27 | PAD_CTL_DSE_MAX (3 << 1) | ||
28 | PAD_CTL_SRE_FAST (1 << 0) | ||
29 | PAD_CTL_SRE_SLOW (0 << 0) | ||
30 | |||
31 | See below for available PIN_FUNC_ID for imx51: | ||
32 | MX51_PAD_EIM_D16__AUD4_RXFS 0 | ||
33 | MX51_PAD_EIM_D16__AUD5_TXD 1 | ||
34 | MX51_PAD_EIM_D16__EIM_D16 2 | ||
35 | MX51_PAD_EIM_D16__GPIO2_0 3 | ||
36 | MX51_PAD_EIM_D16__I2C1_SDA 4 | ||
37 | MX51_PAD_EIM_D16__UART2_CTS 5 | ||
38 | MX51_PAD_EIM_D16__USBH2_DATA0 6 | ||
39 | MX51_PAD_EIM_D17__AUD5_RXD 7 | ||
40 | MX51_PAD_EIM_D17__EIM_D17 8 | ||
41 | MX51_PAD_EIM_D17__GPIO2_1 9 | ||
42 | MX51_PAD_EIM_D17__UART2_RXD 10 | ||
43 | MX51_PAD_EIM_D17__UART3_CTS 11 | ||
44 | MX51_PAD_EIM_D17__USBH2_DATA1 12 | ||
45 | MX51_PAD_EIM_D18__AUD5_TXC 13 | ||
46 | MX51_PAD_EIM_D18__EIM_D18 14 | ||
47 | MX51_PAD_EIM_D18__GPIO2_2 15 | ||
48 | MX51_PAD_EIM_D18__UART2_TXD 16 | ||
49 | MX51_PAD_EIM_D18__UART3_RTS 17 | ||
50 | MX51_PAD_EIM_D18__USBH2_DATA2 18 | ||
51 | MX51_PAD_EIM_D19__AUD4_RXC 19 | ||
52 | MX51_PAD_EIM_D19__AUD5_TXFS 20 | ||
53 | MX51_PAD_EIM_D19__EIM_D19 21 | ||
54 | MX51_PAD_EIM_D19__GPIO2_3 22 | ||
55 | MX51_PAD_EIM_D19__I2C1_SCL 23 | ||
56 | MX51_PAD_EIM_D19__UART2_RTS 24 | ||
57 | MX51_PAD_EIM_D19__USBH2_DATA3 25 | ||
58 | MX51_PAD_EIM_D20__AUD4_TXD 26 | ||
59 | MX51_PAD_EIM_D20__EIM_D20 27 | ||
60 | MX51_PAD_EIM_D20__GPIO2_4 28 | ||
61 | MX51_PAD_EIM_D20__SRTC_ALARM_DEB 29 | ||
62 | MX51_PAD_EIM_D20__USBH2_DATA4 30 | ||
63 | MX51_PAD_EIM_D21__AUD4_RXD 31 | ||
64 | MX51_PAD_EIM_D21__EIM_D21 32 | ||
65 | MX51_PAD_EIM_D21__GPIO2_5 33 | ||
66 | MX51_PAD_EIM_D21__SRTC_ALARM_DEB 34 | ||
67 | MX51_PAD_EIM_D21__USBH2_DATA5 35 | ||
68 | MX51_PAD_EIM_D22__AUD4_TXC 36 | ||
69 | MX51_PAD_EIM_D22__EIM_D22 37 | ||
70 | MX51_PAD_EIM_D22__GPIO2_6 38 | ||
71 | MX51_PAD_EIM_D22__USBH2_DATA6 39 | ||
72 | MX51_PAD_EIM_D23__AUD4_TXFS 40 | ||
73 | MX51_PAD_EIM_D23__EIM_D23 41 | ||
74 | MX51_PAD_EIM_D23__GPIO2_7 42 | ||
75 | MX51_PAD_EIM_D23__SPDIF_OUT1 43 | ||
76 | MX51_PAD_EIM_D23__USBH2_DATA7 44 | ||
77 | MX51_PAD_EIM_D24__AUD6_RXFS 45 | ||
78 | MX51_PAD_EIM_D24__EIM_D24 46 | ||
79 | MX51_PAD_EIM_D24__GPIO2_8 47 | ||
80 | MX51_PAD_EIM_D24__I2C2_SDA 48 | ||
81 | MX51_PAD_EIM_D24__UART3_CTS 49 | ||
82 | MX51_PAD_EIM_D24__USBOTG_DATA0 50 | ||
83 | MX51_PAD_EIM_D25__EIM_D25 51 | ||
84 | MX51_PAD_EIM_D25__KEY_COL6 52 | ||
85 | MX51_PAD_EIM_D25__UART2_CTS 53 | ||
86 | MX51_PAD_EIM_D25__UART3_RXD 54 | ||
87 | MX51_PAD_EIM_D25__USBOTG_DATA1 55 | ||
88 | MX51_PAD_EIM_D26__EIM_D26 56 | ||
89 | MX51_PAD_EIM_D26__KEY_COL7 57 | ||
90 | MX51_PAD_EIM_D26__UART2_RTS 58 | ||
91 | MX51_PAD_EIM_D26__UART3_TXD 59 | ||
92 | MX51_PAD_EIM_D26__USBOTG_DATA2 60 | ||
93 | MX51_PAD_EIM_D27__AUD6_RXC 61 | ||
94 | MX51_PAD_EIM_D27__EIM_D27 62 | ||
95 | MX51_PAD_EIM_D27__GPIO2_9 63 | ||
96 | MX51_PAD_EIM_D27__I2C2_SCL 64 | ||
97 | MX51_PAD_EIM_D27__UART3_RTS 65 | ||
98 | MX51_PAD_EIM_D27__USBOTG_DATA3 66 | ||
99 | MX51_PAD_EIM_D28__AUD6_TXD 67 | ||
100 | MX51_PAD_EIM_D28__EIM_D28 68 | ||
101 | MX51_PAD_EIM_D28__KEY_ROW4 69 | ||
102 | MX51_PAD_EIM_D28__USBOTG_DATA4 70 | ||
103 | MX51_PAD_EIM_D29__AUD6_RXD 71 | ||
104 | MX51_PAD_EIM_D29__EIM_D29 72 | ||
105 | MX51_PAD_EIM_D29__KEY_ROW5 73 | ||
106 | MX51_PAD_EIM_D29__USBOTG_DATA5 74 | ||
107 | MX51_PAD_EIM_D30__AUD6_TXC 75 | ||
108 | MX51_PAD_EIM_D30__EIM_D30 76 | ||
109 | MX51_PAD_EIM_D30__KEY_ROW6 77 | ||
110 | MX51_PAD_EIM_D30__USBOTG_DATA6 78 | ||
111 | MX51_PAD_EIM_D31__AUD6_TXFS 79 | ||
112 | MX51_PAD_EIM_D31__EIM_D31 80 | ||
113 | MX51_PAD_EIM_D31__KEY_ROW7 81 | ||
114 | MX51_PAD_EIM_D31__USBOTG_DATA7 82 | ||
115 | MX51_PAD_EIM_A16__EIM_A16 83 | ||
116 | MX51_PAD_EIM_A16__GPIO2_10 84 | ||
117 | MX51_PAD_EIM_A16__OSC_FREQ_SEL0 85 | ||
118 | MX51_PAD_EIM_A17__EIM_A17 86 | ||
119 | MX51_PAD_EIM_A17__GPIO2_11 87 | ||
120 | MX51_PAD_EIM_A17__OSC_FREQ_SEL1 88 | ||
121 | MX51_PAD_EIM_A18__BOOT_LPB0 89 | ||
122 | MX51_PAD_EIM_A18__EIM_A18 90 | ||
123 | MX51_PAD_EIM_A18__GPIO2_12 91 | ||
124 | MX51_PAD_EIM_A19__BOOT_LPB1 92 | ||
125 | MX51_PAD_EIM_A19__EIM_A19 93 | ||
126 | MX51_PAD_EIM_A19__GPIO2_13 94 | ||
127 | MX51_PAD_EIM_A20__BOOT_UART_SRC0 95 | ||
128 | MX51_PAD_EIM_A20__EIM_A20 96 | ||
129 | MX51_PAD_EIM_A20__GPIO2_14 97 | ||
130 | MX51_PAD_EIM_A21__BOOT_UART_SRC1 98 | ||
131 | MX51_PAD_EIM_A21__EIM_A21 99 | ||
132 | MX51_PAD_EIM_A21__GPIO2_15 100 | ||
133 | MX51_PAD_EIM_A22__EIM_A22 101 | ||
134 | MX51_PAD_EIM_A22__GPIO2_16 102 | ||
135 | MX51_PAD_EIM_A23__BOOT_HPN_EN 103 | ||
136 | MX51_PAD_EIM_A23__EIM_A23 104 | ||
137 | MX51_PAD_EIM_A23__GPIO2_17 105 | ||
138 | MX51_PAD_EIM_A24__EIM_A24 106 | ||
139 | MX51_PAD_EIM_A24__GPIO2_18 107 | ||
140 | MX51_PAD_EIM_A24__USBH2_CLK 108 | ||
141 | MX51_PAD_EIM_A25__DISP1_PIN4 109 | ||
142 | MX51_PAD_EIM_A25__EIM_A25 110 | ||
143 | MX51_PAD_EIM_A25__GPIO2_19 111 | ||
144 | MX51_PAD_EIM_A25__USBH2_DIR 112 | ||
145 | MX51_PAD_EIM_A26__CSI1_DATA_EN 113 | ||
146 | MX51_PAD_EIM_A26__DISP2_EXT_CLK 114 | ||
147 | MX51_PAD_EIM_A26__EIM_A26 115 | ||
148 | MX51_PAD_EIM_A26__GPIO2_20 116 | ||
149 | MX51_PAD_EIM_A26__USBH2_STP 117 | ||
150 | MX51_PAD_EIM_A27__CSI2_DATA_EN 118 | ||
151 | MX51_PAD_EIM_A27__DISP1_PIN1 119 | ||
152 | MX51_PAD_EIM_A27__EIM_A27 120 | ||
153 | MX51_PAD_EIM_A27__GPIO2_21 121 | ||
154 | MX51_PAD_EIM_A27__USBH2_NXT 122 | ||
155 | MX51_PAD_EIM_EB0__EIM_EB0 123 | ||
156 | MX51_PAD_EIM_EB1__EIM_EB1 124 | ||
157 | MX51_PAD_EIM_EB2__AUD5_RXFS 125 | ||
158 | MX51_PAD_EIM_EB2__CSI1_D2 126 | ||
159 | MX51_PAD_EIM_EB2__EIM_EB2 127 | ||
160 | MX51_PAD_EIM_EB2__FEC_MDIO 128 | ||
161 | MX51_PAD_EIM_EB2__GPIO2_22 129 | ||
162 | MX51_PAD_EIM_EB2__GPT_CMPOUT1 130 | ||
163 | MX51_PAD_EIM_EB3__AUD5_RXC 131 | ||
164 | MX51_PAD_EIM_EB3__CSI1_D3 132 | ||
165 | MX51_PAD_EIM_EB3__EIM_EB3 133 | ||
166 | MX51_PAD_EIM_EB3__FEC_RDATA1 134 | ||
167 | MX51_PAD_EIM_EB3__GPIO2_23 135 | ||
168 | MX51_PAD_EIM_EB3__GPT_CMPOUT2 136 | ||
169 | MX51_PAD_EIM_OE__EIM_OE 137 | ||
170 | MX51_PAD_EIM_OE__GPIO2_24 138 | ||
171 | MX51_PAD_EIM_CS0__EIM_CS0 139 | ||
172 | MX51_PAD_EIM_CS0__GPIO2_25 140 | ||
173 | MX51_PAD_EIM_CS1__EIM_CS1 141 | ||
174 | MX51_PAD_EIM_CS1__GPIO2_26 142 | ||
175 | MX51_PAD_EIM_CS2__AUD5_TXD 143 | ||
176 | MX51_PAD_EIM_CS2__CSI1_D4 144 | ||
177 | MX51_PAD_EIM_CS2__EIM_CS2 145 | ||
178 | MX51_PAD_EIM_CS2__FEC_RDATA2 146 | ||
179 | MX51_PAD_EIM_CS2__GPIO2_27 147 | ||
180 | MX51_PAD_EIM_CS2__USBOTG_STP 148 | ||
181 | MX51_PAD_EIM_CS3__AUD5_RXD 149 | ||
182 | MX51_PAD_EIM_CS3__CSI1_D5 150 | ||
183 | MX51_PAD_EIM_CS3__EIM_CS3 151 | ||
184 | MX51_PAD_EIM_CS3__FEC_RDATA3 152 | ||
185 | MX51_PAD_EIM_CS3__GPIO2_28 153 | ||
186 | MX51_PAD_EIM_CS3__USBOTG_NXT 154 | ||
187 | MX51_PAD_EIM_CS4__AUD5_TXC 155 | ||
188 | MX51_PAD_EIM_CS4__CSI1_D6 156 | ||
189 | MX51_PAD_EIM_CS4__EIM_CS4 157 | ||
190 | MX51_PAD_EIM_CS4__FEC_RX_ER 158 | ||
191 | MX51_PAD_EIM_CS4__GPIO2_29 159 | ||
192 | MX51_PAD_EIM_CS4__USBOTG_CLK 160 | ||
193 | MX51_PAD_EIM_CS5__AUD5_TXFS 161 | ||
194 | MX51_PAD_EIM_CS5__CSI1_D7 162 | ||
195 | MX51_PAD_EIM_CS5__DISP1_EXT_CLK 163 | ||
196 | MX51_PAD_EIM_CS5__EIM_CS5 164 | ||
197 | MX51_PAD_EIM_CS5__FEC_CRS 165 | ||
198 | MX51_PAD_EIM_CS5__GPIO2_30 166 | ||
199 | MX51_PAD_EIM_CS5__USBOTG_DIR 167 | ||
200 | MX51_PAD_EIM_DTACK__EIM_DTACK 168 | ||
201 | MX51_PAD_EIM_DTACK__GPIO2_31 169 | ||
202 | MX51_PAD_EIM_LBA__EIM_LBA 170 | ||
203 | MX51_PAD_EIM_LBA__GPIO3_1 171 | ||
204 | MX51_PAD_EIM_CRE__EIM_CRE 172 | ||
205 | MX51_PAD_EIM_CRE__GPIO3_2 173 | ||
206 | MX51_PAD_DRAM_CS1__DRAM_CS1 174 | ||
207 | MX51_PAD_NANDF_WE_B__GPIO3_3 175 | ||
208 | MX51_PAD_NANDF_WE_B__NANDF_WE_B 176 | ||
209 | MX51_PAD_NANDF_WE_B__PATA_DIOW 177 | ||
210 | MX51_PAD_NANDF_WE_B__SD3_DATA0 178 | ||
211 | MX51_PAD_NANDF_RE_B__GPIO3_4 179 | ||
212 | MX51_PAD_NANDF_RE_B__NANDF_RE_B 180 | ||
213 | MX51_PAD_NANDF_RE_B__PATA_DIOR 181 | ||
214 | MX51_PAD_NANDF_RE_B__SD3_DATA1 182 | ||
215 | MX51_PAD_NANDF_ALE__GPIO3_5 183 | ||
216 | MX51_PAD_NANDF_ALE__NANDF_ALE 184 | ||
217 | MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 185 | ||
218 | MX51_PAD_NANDF_CLE__GPIO3_6 186 | ||
219 | MX51_PAD_NANDF_CLE__NANDF_CLE 187 | ||
220 | MX51_PAD_NANDF_CLE__PATA_RESET_B 188 | ||
221 | MX51_PAD_NANDF_WP_B__GPIO3_7 189 | ||
222 | MX51_PAD_NANDF_WP_B__NANDF_WP_B 190 | ||
223 | MX51_PAD_NANDF_WP_B__PATA_DMACK 191 | ||
224 | MX51_PAD_NANDF_WP_B__SD3_DATA2 192 | ||
225 | MX51_PAD_NANDF_RB0__ECSPI2_SS1 193 | ||
226 | MX51_PAD_NANDF_RB0__GPIO3_8 194 | ||
227 | MX51_PAD_NANDF_RB0__NANDF_RB0 195 | ||
228 | MX51_PAD_NANDF_RB0__PATA_DMARQ 196 | ||
229 | MX51_PAD_NANDF_RB0__SD3_DATA3 197 | ||
230 | MX51_PAD_NANDF_RB1__CSPI_MOSI 198 | ||
231 | MX51_PAD_NANDF_RB1__ECSPI2_RDY 199 | ||
232 | MX51_PAD_NANDF_RB1__GPIO3_9 200 | ||
233 | MX51_PAD_NANDF_RB1__NANDF_RB1 201 | ||
234 | MX51_PAD_NANDF_RB1__PATA_IORDY 202 | ||
235 | MX51_PAD_NANDF_RB1__SD4_CMD 203 | ||
236 | MX51_PAD_NANDF_RB2__DISP2_WAIT 204 | ||
237 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 205 | ||
238 | MX51_PAD_NANDF_RB2__FEC_COL 206 | ||
239 | MX51_PAD_NANDF_RB2__GPIO3_10 207 | ||
240 | MX51_PAD_NANDF_RB2__NANDF_RB2 208 | ||
241 | MX51_PAD_NANDF_RB2__USBH3_H3_DP 209 | ||
242 | MX51_PAD_NANDF_RB2__USBH3_NXT 210 | ||
243 | MX51_PAD_NANDF_RB3__DISP1_WAIT 211 | ||
244 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 212 | ||
245 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 213 | ||
246 | MX51_PAD_NANDF_RB3__GPIO3_11 214 | ||
247 | MX51_PAD_NANDF_RB3__NANDF_RB3 215 | ||
248 | MX51_PAD_NANDF_RB3__USBH3_CLK 216 | ||
249 | MX51_PAD_NANDF_RB3__USBH3_H3_DM 217 | ||
250 | MX51_PAD_GPIO_NAND__GPIO_NAND 218 | ||
251 | MX51_PAD_GPIO_NAND__PATA_INTRQ 219 | ||
252 | MX51_PAD_NANDF_CS0__GPIO3_16 220 | ||
253 | MX51_PAD_NANDF_CS0__NANDF_CS0 221 | ||
254 | MX51_PAD_NANDF_CS1__GPIO3_17 222 | ||
255 | MX51_PAD_NANDF_CS1__NANDF_CS1 223 | ||
256 | MX51_PAD_NANDF_CS2__CSPI_SCLK 224 | ||
257 | MX51_PAD_NANDF_CS2__FEC_TX_ER 225 | ||
258 | MX51_PAD_NANDF_CS2__GPIO3_18 226 | ||
259 | MX51_PAD_NANDF_CS2__NANDF_CS2 227 | ||
260 | MX51_PAD_NANDF_CS2__PATA_CS_0 228 | ||
261 | MX51_PAD_NANDF_CS2__SD4_CLK 229 | ||
262 | MX51_PAD_NANDF_CS2__USBH3_H1_DP 230 | ||
263 | MX51_PAD_NANDF_CS3__FEC_MDC 231 | ||
264 | MX51_PAD_NANDF_CS3__GPIO3_19 232 | ||
265 | MX51_PAD_NANDF_CS3__NANDF_CS3 233 | ||
266 | MX51_PAD_NANDF_CS3__PATA_CS_1 234 | ||
267 | MX51_PAD_NANDF_CS3__SD4_DAT0 235 | ||
268 | MX51_PAD_NANDF_CS3__USBH3_H1_DM 236 | ||
269 | MX51_PAD_NANDF_CS4__FEC_TDATA1 237 | ||
270 | MX51_PAD_NANDF_CS4__GPIO3_20 238 | ||
271 | MX51_PAD_NANDF_CS4__NANDF_CS4 239 | ||
272 | MX51_PAD_NANDF_CS4__PATA_DA_0 240 | ||
273 | MX51_PAD_NANDF_CS4__SD4_DAT1 241 | ||
274 | MX51_PAD_NANDF_CS4__USBH3_STP 242 | ||
275 | MX51_PAD_NANDF_CS5__FEC_TDATA2 243 | ||
276 | MX51_PAD_NANDF_CS5__GPIO3_21 244 | ||
277 | MX51_PAD_NANDF_CS5__NANDF_CS5 245 | ||
278 | MX51_PAD_NANDF_CS5__PATA_DA_1 246 | ||
279 | MX51_PAD_NANDF_CS5__SD4_DAT2 247 | ||
280 | MX51_PAD_NANDF_CS5__USBH3_DIR 248 | ||
281 | MX51_PAD_NANDF_CS6__CSPI_SS3 249 | ||
282 | MX51_PAD_NANDF_CS6__FEC_TDATA3 250 | ||
283 | MX51_PAD_NANDF_CS6__GPIO3_22 251 | ||
284 | MX51_PAD_NANDF_CS6__NANDF_CS6 252 | ||
285 | MX51_PAD_NANDF_CS6__PATA_DA_2 253 | ||
286 | MX51_PAD_NANDF_CS6__SD4_DAT3 254 | ||
287 | MX51_PAD_NANDF_CS7__FEC_TX_EN 255 | ||
288 | MX51_PAD_NANDF_CS7__GPIO3_23 256 | ||
289 | MX51_PAD_NANDF_CS7__NANDF_CS7 257 | ||
290 | MX51_PAD_NANDF_CS7__SD3_CLK 258 | ||
291 | MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 259 | ||
292 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 260 | ||
293 | MX51_PAD_NANDF_RDY_INT__GPIO3_24 261 | ||
294 | MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 262 | ||
295 | MX51_PAD_NANDF_RDY_INT__SD3_CMD 263 | ||
296 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 264 | ||
297 | MX51_PAD_NANDF_D15__GPIO3_25 265 | ||
298 | MX51_PAD_NANDF_D15__NANDF_D15 266 | ||
299 | MX51_PAD_NANDF_D15__PATA_DATA15 267 | ||
300 | MX51_PAD_NANDF_D15__SD3_DAT7 268 | ||
301 | MX51_PAD_NANDF_D14__ECSPI2_SS3 269 | ||
302 | MX51_PAD_NANDF_D14__GPIO3_26 270 | ||
303 | MX51_PAD_NANDF_D14__NANDF_D14 271 | ||
304 | MX51_PAD_NANDF_D14__PATA_DATA14 272 | ||
305 | MX51_PAD_NANDF_D14__SD3_DAT6 273 | ||
306 | MX51_PAD_NANDF_D13__ECSPI2_SS2 274 | ||
307 | MX51_PAD_NANDF_D13__GPIO3_27 275 | ||
308 | MX51_PAD_NANDF_D13__NANDF_D13 276 | ||
309 | MX51_PAD_NANDF_D13__PATA_DATA13 277 | ||
310 | MX51_PAD_NANDF_D13__SD3_DAT5 278 | ||
311 | MX51_PAD_NANDF_D12__ECSPI2_SS1 279 | ||
312 | MX51_PAD_NANDF_D12__GPIO3_28 280 | ||
313 | MX51_PAD_NANDF_D12__NANDF_D12 281 | ||
314 | MX51_PAD_NANDF_D12__PATA_DATA12 282 | ||
315 | MX51_PAD_NANDF_D12__SD3_DAT4 283 | ||
316 | MX51_PAD_NANDF_D11__FEC_RX_DV 284 | ||
317 | MX51_PAD_NANDF_D11__GPIO3_29 285 | ||
318 | MX51_PAD_NANDF_D11__NANDF_D11 286 | ||
319 | MX51_PAD_NANDF_D11__PATA_DATA11 287 | ||
320 | MX51_PAD_NANDF_D11__SD3_DATA3 288 | ||
321 | MX51_PAD_NANDF_D10__GPIO3_30 289 | ||
322 | MX51_PAD_NANDF_D10__NANDF_D10 290 | ||
323 | MX51_PAD_NANDF_D10__PATA_DATA10 291 | ||
324 | MX51_PAD_NANDF_D10__SD3_DATA2 292 | ||
325 | MX51_PAD_NANDF_D9__FEC_RDATA0 293 | ||
326 | MX51_PAD_NANDF_D9__GPIO3_31 294 | ||
327 | MX51_PAD_NANDF_D9__NANDF_D9 295 | ||
328 | MX51_PAD_NANDF_D9__PATA_DATA9 296 | ||
329 | MX51_PAD_NANDF_D9__SD3_DATA1 297 | ||
330 | MX51_PAD_NANDF_D8__FEC_TDATA0 298 | ||
331 | MX51_PAD_NANDF_D8__GPIO4_0 299 | ||
332 | MX51_PAD_NANDF_D8__NANDF_D8 300 | ||
333 | MX51_PAD_NANDF_D8__PATA_DATA8 301 | ||
334 | MX51_PAD_NANDF_D8__SD3_DATA0 302 | ||
335 | MX51_PAD_NANDF_D7__GPIO4_1 303 | ||
336 | MX51_PAD_NANDF_D7__NANDF_D7 304 | ||
337 | MX51_PAD_NANDF_D7__PATA_DATA7 305 | ||
338 | MX51_PAD_NANDF_D7__USBH3_DATA0 306 | ||
339 | MX51_PAD_NANDF_D6__GPIO4_2 307 | ||
340 | MX51_PAD_NANDF_D6__NANDF_D6 308 | ||
341 | MX51_PAD_NANDF_D6__PATA_DATA6 309 | ||
342 | MX51_PAD_NANDF_D6__SD4_LCTL 310 | ||
343 | MX51_PAD_NANDF_D6__USBH3_DATA1 311 | ||
344 | MX51_PAD_NANDF_D5__GPIO4_3 312 | ||
345 | MX51_PAD_NANDF_D5__NANDF_D5 313 | ||
346 | MX51_PAD_NANDF_D5__PATA_DATA5 314 | ||
347 | MX51_PAD_NANDF_D5__SD4_WP 315 | ||
348 | MX51_PAD_NANDF_D5__USBH3_DATA2 316 | ||
349 | MX51_PAD_NANDF_D4__GPIO4_4 317 | ||
350 | MX51_PAD_NANDF_D4__NANDF_D4 318 | ||
351 | MX51_PAD_NANDF_D4__PATA_DATA4 319 | ||
352 | MX51_PAD_NANDF_D4__SD4_CD 320 | ||
353 | MX51_PAD_NANDF_D4__USBH3_DATA3 321 | ||
354 | MX51_PAD_NANDF_D3__GPIO4_5 322 | ||
355 | MX51_PAD_NANDF_D3__NANDF_D3 323 | ||
356 | MX51_PAD_NANDF_D3__PATA_DATA3 324 | ||
357 | MX51_PAD_NANDF_D3__SD4_DAT4 325 | ||
358 | MX51_PAD_NANDF_D3__USBH3_DATA4 326 | ||
359 | MX51_PAD_NANDF_D2__GPIO4_6 327 | ||
360 | MX51_PAD_NANDF_D2__NANDF_D2 328 | ||
361 | MX51_PAD_NANDF_D2__PATA_DATA2 329 | ||
362 | MX51_PAD_NANDF_D2__SD4_DAT5 330 | ||
363 | MX51_PAD_NANDF_D2__USBH3_DATA5 331 | ||
364 | MX51_PAD_NANDF_D1__GPIO4_7 332 | ||
365 | MX51_PAD_NANDF_D1__NANDF_D1 333 | ||
366 | MX51_PAD_NANDF_D1__PATA_DATA1 334 | ||
367 | MX51_PAD_NANDF_D1__SD4_DAT6 335 | ||
368 | MX51_PAD_NANDF_D1__USBH3_DATA6 336 | ||
369 | MX51_PAD_NANDF_D0__GPIO4_8 337 | ||
370 | MX51_PAD_NANDF_D0__NANDF_D0 338 | ||
371 | MX51_PAD_NANDF_D0__PATA_DATA0 339 | ||
372 | MX51_PAD_NANDF_D0__SD4_DAT7 340 | ||
373 | MX51_PAD_NANDF_D0__USBH3_DATA7 341 | ||
374 | MX51_PAD_CSI1_D8__CSI1_D8 342 | ||
375 | MX51_PAD_CSI1_D8__GPIO3_12 343 | ||
376 | MX51_PAD_CSI1_D9__CSI1_D9 344 | ||
377 | MX51_PAD_CSI1_D9__GPIO3_13 345 | ||
378 | MX51_PAD_CSI1_D10__CSI1_D10 346 | ||
379 | MX51_PAD_CSI1_D11__CSI1_D11 347 | ||
380 | MX51_PAD_CSI1_D12__CSI1_D12 348 | ||
381 | MX51_PAD_CSI1_D13__CSI1_D13 349 | ||
382 | MX51_PAD_CSI1_D14__CSI1_D14 350 | ||
383 | MX51_PAD_CSI1_D15__CSI1_D15 351 | ||
384 | MX51_PAD_CSI1_D16__CSI1_D16 352 | ||
385 | MX51_PAD_CSI1_D17__CSI1_D17 353 | ||
386 | MX51_PAD_CSI1_D18__CSI1_D18 354 | ||
387 | MX51_PAD_CSI1_D19__CSI1_D19 355 | ||
388 | MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 356 | ||
389 | MX51_PAD_CSI1_VSYNC__GPIO3_14 357 | ||
390 | MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 358 | ||
391 | MX51_PAD_CSI1_HSYNC__GPIO3_15 359 | ||
392 | MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 360 | ||
393 | MX51_PAD_CSI1_MCLK__CSI1_MCLK 361 | ||
394 | MX51_PAD_CSI2_D12__CSI2_D12 362 | ||
395 | MX51_PAD_CSI2_D12__GPIO4_9 363 | ||
396 | MX51_PAD_CSI2_D13__CSI2_D13 364 | ||
397 | MX51_PAD_CSI2_D13__GPIO4_10 365 | ||
398 | MX51_PAD_CSI2_D14__CSI2_D14 366 | ||
399 | MX51_PAD_CSI2_D15__CSI2_D15 367 | ||
400 | MX51_PAD_CSI2_D16__CSI2_D16 368 | ||
401 | MX51_PAD_CSI2_D17__CSI2_D17 369 | ||
402 | MX51_PAD_CSI2_D18__CSI2_D18 370 | ||
403 | MX51_PAD_CSI2_D18__GPIO4_11 371 | ||
404 | MX51_PAD_CSI2_D19__CSI2_D19 372 | ||
405 | MX51_PAD_CSI2_D19__GPIO4_12 373 | ||
406 | MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 374 | ||
407 | MX51_PAD_CSI2_VSYNC__GPIO4_13 375 | ||
408 | MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 376 | ||
409 | MX51_PAD_CSI2_HSYNC__GPIO4_14 377 | ||
410 | MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 378 | ||
411 | MX51_PAD_CSI2_PIXCLK__GPIO4_15 379 | ||
412 | MX51_PAD_I2C1_CLK__GPIO4_16 380 | ||
413 | MX51_PAD_I2C1_CLK__I2C1_CLK 381 | ||
414 | MX51_PAD_I2C1_DAT__GPIO4_17 382 | ||
415 | MX51_PAD_I2C1_DAT__I2C1_DAT 383 | ||
416 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 384 | ||
417 | MX51_PAD_AUD3_BB_TXD__GPIO4_18 385 | ||
418 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 386 | ||
419 | MX51_PAD_AUD3_BB_RXD__GPIO4_19 387 | ||
420 | MX51_PAD_AUD3_BB_RXD__UART3_RXD 388 | ||
421 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 389 | ||
422 | MX51_PAD_AUD3_BB_CK__GPIO4_20 390 | ||
423 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 391 | ||
424 | MX51_PAD_AUD3_BB_FS__GPIO4_21 392 | ||
425 | MX51_PAD_AUD3_BB_FS__UART3_TXD 393 | ||
426 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 394 | ||
427 | MX51_PAD_CSPI1_MOSI__GPIO4_22 395 | ||
428 | MX51_PAD_CSPI1_MOSI__I2C1_SDA 396 | ||
429 | MX51_PAD_CSPI1_MISO__AUD4_RXD 397 | ||
430 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 398 | ||
431 | MX51_PAD_CSPI1_MISO__GPIO4_23 399 | ||
432 | MX51_PAD_CSPI1_SS0__AUD4_TXC 400 | ||
433 | MX51_PAD_CSPI1_SS0__ECSPI1_SS0 401 | ||
434 | MX51_PAD_CSPI1_SS0__GPIO4_24 402 | ||
435 | MX51_PAD_CSPI1_SS1__AUD4_TXD 403 | ||
436 | MX51_PAD_CSPI1_SS1__ECSPI1_SS1 404 | ||
437 | MX51_PAD_CSPI1_SS1__GPIO4_25 405 | ||
438 | MX51_PAD_CSPI1_RDY__AUD4_TXFS 406 | ||
439 | MX51_PAD_CSPI1_RDY__ECSPI1_RDY 407 | ||
440 | MX51_PAD_CSPI1_RDY__GPIO4_26 408 | ||
441 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 409 | ||
442 | MX51_PAD_CSPI1_SCLK__GPIO4_27 410 | ||
443 | MX51_PAD_CSPI1_SCLK__I2C1_SCL 411 | ||
444 | MX51_PAD_UART1_RXD__GPIO4_28 412 | ||
445 | MX51_PAD_UART1_RXD__UART1_RXD 413 | ||
446 | MX51_PAD_UART1_TXD__GPIO4_29 414 | ||
447 | MX51_PAD_UART1_TXD__PWM2_PWMO 415 | ||
448 | MX51_PAD_UART1_TXD__UART1_TXD 416 | ||
449 | MX51_PAD_UART1_RTS__GPIO4_30 417 | ||
450 | MX51_PAD_UART1_RTS__UART1_RTS 418 | ||
451 | MX51_PAD_UART1_CTS__GPIO4_31 419 | ||
452 | MX51_PAD_UART1_CTS__UART1_CTS 420 | ||
453 | MX51_PAD_UART2_RXD__FIRI_TXD 421 | ||
454 | MX51_PAD_UART2_RXD__GPIO1_20 422 | ||
455 | MX51_PAD_UART2_RXD__UART2_RXD 423 | ||
456 | MX51_PAD_UART2_TXD__FIRI_RXD 424 | ||
457 | MX51_PAD_UART2_TXD__GPIO1_21 425 | ||
458 | MX51_PAD_UART2_TXD__UART2_TXD 426 | ||
459 | MX51_PAD_UART3_RXD__CSI1_D0 427 | ||
460 | MX51_PAD_UART3_RXD__GPIO1_22 428 | ||
461 | MX51_PAD_UART3_RXD__UART1_DTR 429 | ||
462 | MX51_PAD_UART3_RXD__UART3_RXD 430 | ||
463 | MX51_PAD_UART3_TXD__CSI1_D1 431 | ||
464 | MX51_PAD_UART3_TXD__GPIO1_23 432 | ||
465 | MX51_PAD_UART3_TXD__UART1_DSR 433 | ||
466 | MX51_PAD_UART3_TXD__UART3_TXD 434 | ||
467 | MX51_PAD_OWIRE_LINE__GPIO1_24 435 | ||
468 | MX51_PAD_OWIRE_LINE__OWIRE_LINE 436 | ||
469 | MX51_PAD_OWIRE_LINE__SPDIF_OUT 437 | ||
470 | MX51_PAD_KEY_ROW0__KEY_ROW0 438 | ||
471 | MX51_PAD_KEY_ROW1__KEY_ROW1 439 | ||
472 | MX51_PAD_KEY_ROW2__KEY_ROW2 440 | ||
473 | MX51_PAD_KEY_ROW3__KEY_ROW3 441 | ||
474 | MX51_PAD_KEY_COL0__KEY_COL0 442 | ||
475 | MX51_PAD_KEY_COL0__PLL1_BYP 443 | ||
476 | MX51_PAD_KEY_COL1__KEY_COL1 444 | ||
477 | MX51_PAD_KEY_COL1__PLL2_BYP 445 | ||
478 | MX51_PAD_KEY_COL2__KEY_COL2 446 | ||
479 | MX51_PAD_KEY_COL2__PLL3_BYP 447 | ||
480 | MX51_PAD_KEY_COL3__KEY_COL3 448 | ||
481 | MX51_PAD_KEY_COL4__I2C2_SCL 449 | ||
482 | MX51_PAD_KEY_COL4__KEY_COL4 450 | ||
483 | MX51_PAD_KEY_COL4__SPDIF_OUT1 451 | ||
484 | MX51_PAD_KEY_COL4__UART1_RI 452 | ||
485 | MX51_PAD_KEY_COL4__UART3_RTS 453 | ||
486 | MX51_PAD_KEY_COL5__I2C2_SDA 454 | ||
487 | MX51_PAD_KEY_COL5__KEY_COL5 455 | ||
488 | MX51_PAD_KEY_COL5__UART1_DCD 456 | ||
489 | MX51_PAD_KEY_COL5__UART3_CTS 457 | ||
490 | MX51_PAD_USBH1_CLK__CSPI_SCLK 458 | ||
491 | MX51_PAD_USBH1_CLK__GPIO1_25 459 | ||
492 | MX51_PAD_USBH1_CLK__I2C2_SCL 460 | ||
493 | MX51_PAD_USBH1_CLK__USBH1_CLK 461 | ||
494 | MX51_PAD_USBH1_DIR__CSPI_MOSI 462 | ||
495 | MX51_PAD_USBH1_DIR__GPIO1_26 463 | ||
496 | MX51_PAD_USBH1_DIR__I2C2_SDA 464 | ||
497 | MX51_PAD_USBH1_DIR__USBH1_DIR 465 | ||
498 | MX51_PAD_USBH1_STP__CSPI_RDY 466 | ||
499 | MX51_PAD_USBH1_STP__GPIO1_27 467 | ||
500 | MX51_PAD_USBH1_STP__UART3_RXD 468 | ||
501 | MX51_PAD_USBH1_STP__USBH1_STP 469 | ||
502 | MX51_PAD_USBH1_NXT__CSPI_MISO 470 | ||
503 | MX51_PAD_USBH1_NXT__GPIO1_28 471 | ||
504 | MX51_PAD_USBH1_NXT__UART3_TXD 472 | ||
505 | MX51_PAD_USBH1_NXT__USBH1_NXT 473 | ||
506 | MX51_PAD_USBH1_DATA0__GPIO1_11 474 | ||
507 | MX51_PAD_USBH1_DATA0__UART2_CTS 475 | ||
508 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 476 | ||
509 | MX51_PAD_USBH1_DATA1__GPIO1_12 477 | ||
510 | MX51_PAD_USBH1_DATA1__UART2_RXD 478 | ||
511 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 479 | ||
512 | MX51_PAD_USBH1_DATA2__GPIO1_13 480 | ||
513 | MX51_PAD_USBH1_DATA2__UART2_TXD 481 | ||
514 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 482 | ||
515 | MX51_PAD_USBH1_DATA3__GPIO1_14 483 | ||
516 | MX51_PAD_USBH1_DATA3__UART2_RTS 484 | ||
517 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 485 | ||
518 | MX51_PAD_USBH1_DATA4__CSPI_SS0 486 | ||
519 | MX51_PAD_USBH1_DATA4__GPIO1_15 487 | ||
520 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 488 | ||
521 | MX51_PAD_USBH1_DATA5__CSPI_SS1 489 | ||
522 | MX51_PAD_USBH1_DATA5__GPIO1_16 490 | ||
523 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 491 | ||
524 | MX51_PAD_USBH1_DATA6__CSPI_SS3 492 | ||
525 | MX51_PAD_USBH1_DATA6__GPIO1_17 493 | ||
526 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 494 | ||
527 | MX51_PAD_USBH1_DATA7__ECSPI1_SS3 495 | ||
528 | MX51_PAD_USBH1_DATA7__ECSPI2_SS3 496 | ||
529 | MX51_PAD_USBH1_DATA7__GPIO1_18 497 | ||
530 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 498 | ||
531 | MX51_PAD_DI1_PIN11__DI1_PIN11 499 | ||
532 | MX51_PAD_DI1_PIN11__ECSPI1_SS2 500 | ||
533 | MX51_PAD_DI1_PIN11__GPIO3_0 501 | ||
534 | MX51_PAD_DI1_PIN12__DI1_PIN12 502 | ||
535 | MX51_PAD_DI1_PIN12__GPIO3_1 503 | ||
536 | MX51_PAD_DI1_PIN13__DI1_PIN13 504 | ||
537 | MX51_PAD_DI1_PIN13__GPIO3_2 505 | ||
538 | MX51_PAD_DI1_D0_CS__DI1_D0_CS 506 | ||
539 | MX51_PAD_DI1_D0_CS__GPIO3_3 507 | ||
540 | MX51_PAD_DI1_D1_CS__DI1_D1_CS 508 | ||
541 | MX51_PAD_DI1_D1_CS__DISP1_PIN14 509 | ||
542 | MX51_PAD_DI1_D1_CS__DISP1_PIN5 510 | ||
543 | MX51_PAD_DI1_D1_CS__GPIO3_4 511 | ||
544 | MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 512 | ||
545 | MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 513 | ||
546 | MX51_PAD_DISPB2_SER_DIN__GPIO3_5 514 | ||
547 | MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 515 | ||
548 | MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 516 | ||
549 | MX51_PAD_DISPB2_SER_DIO__GPIO3_6 517 | ||
550 | MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 518 | ||
551 | MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 519 | ||
552 | MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 520 | ||
553 | MX51_PAD_DISPB2_SER_CLK__GPIO3_7 521 | ||
554 | MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 522 | ||
555 | MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 523 | ||
556 | MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 524 | ||
557 | MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 525 | ||
558 | MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 526 | ||
559 | MX51_PAD_DISPB2_SER_RS__GPIO3_8 527 | ||
560 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 528 | ||
561 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 529 | ||
562 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 530 | ||
563 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 531 | ||
564 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 532 | ||
565 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 533 | ||
566 | MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 534 | ||
567 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 535 | ||
568 | MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 536 | ||
569 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 537 | ||
570 | MX51_PAD_DISP1_DAT8__BOOT_SRC0 538 | ||
571 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 539 | ||
572 | MX51_PAD_DISP1_DAT9__BOOT_SRC1 540 | ||
573 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 541 | ||
574 | MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 542 | ||
575 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 543 | ||
576 | MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 544 | ||
577 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 545 | ||
578 | MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 546 | ||
579 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 547 | ||
580 | MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 548 | ||
581 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 549 | ||
582 | MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 550 | ||
583 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 551 | ||
584 | MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 552 | ||
585 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 553 | ||
586 | MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 554 | ||
587 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 555 | ||
588 | MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 556 | ||
589 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 557 | ||
590 | MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 558 | ||
591 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 559 | ||
592 | MX51_PAD_DISP1_DAT18__DISP2_PIN11 560 | ||
593 | MX51_PAD_DISP1_DAT18__DISP2_PIN5 561 | ||
594 | MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 562 | ||
595 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 563 | ||
596 | MX51_PAD_DISP1_DAT19__DISP2_PIN12 564 | ||
597 | MX51_PAD_DISP1_DAT19__DISP2_PIN6 565 | ||
598 | MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 566 | ||
599 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 567 | ||
600 | MX51_PAD_DISP1_DAT20__DISP2_PIN13 568 | ||
601 | MX51_PAD_DISP1_DAT20__DISP2_PIN7 569 | ||
602 | MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 570 | ||
603 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 571 | ||
604 | MX51_PAD_DISP1_DAT21__DISP2_PIN14 572 | ||
605 | MX51_PAD_DISP1_DAT21__DISP2_PIN8 573 | ||
606 | MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 574 | ||
607 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 575 | ||
608 | MX51_PAD_DISP1_DAT22__DISP2_D0_CS 576 | ||
609 | MX51_PAD_DISP1_DAT22__DISP2_DAT16 577 | ||
610 | MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 578 | ||
611 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 579 | ||
612 | MX51_PAD_DISP1_DAT23__DISP2_D1_CS 580 | ||
613 | MX51_PAD_DISP1_DAT23__DISP2_DAT17 581 | ||
614 | MX51_PAD_DISP1_DAT23__DISP2_SER_CS 582 | ||
615 | MX51_PAD_DI1_PIN3__DI1_PIN3 583 | ||
616 | MX51_PAD_DI1_PIN2__DI1_PIN2 584 | ||
617 | MX51_PAD_DI_GP2__DISP1_SER_CLK 585 | ||
618 | MX51_PAD_DI_GP2__DISP2_WAIT 586 | ||
619 | MX51_PAD_DI_GP3__CSI1_DATA_EN 587 | ||
620 | MX51_PAD_DI_GP3__DISP1_SER_DIO 588 | ||
621 | MX51_PAD_DI_GP3__FEC_TX_ER 589 | ||
622 | MX51_PAD_DI2_PIN4__CSI2_DATA_EN 590 | ||
623 | MX51_PAD_DI2_PIN4__DI2_PIN4 591 | ||
624 | MX51_PAD_DI2_PIN4__FEC_CRS 592 | ||
625 | MX51_PAD_DI2_PIN2__DI2_PIN2 593 | ||
626 | MX51_PAD_DI2_PIN2__FEC_MDC 594 | ||
627 | MX51_PAD_DI2_PIN3__DI2_PIN3 595 | ||
628 | MX51_PAD_DI2_PIN3__FEC_MDIO 596 | ||
629 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 597 | ||
630 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 598 | ||
631 | MX51_PAD_DI_GP4__DI2_PIN15 599 | ||
632 | MX51_PAD_DI_GP4__DISP1_SER_DIN 600 | ||
633 | MX51_PAD_DI_GP4__DISP2_PIN1 601 | ||
634 | MX51_PAD_DI_GP4__FEC_RDATA2 602 | ||
635 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 603 | ||
636 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 604 | ||
637 | MX51_PAD_DISP2_DAT0__KEY_COL6 605 | ||
638 | MX51_PAD_DISP2_DAT0__UART3_RXD 606 | ||
639 | MX51_PAD_DISP2_DAT0__USBH3_CLK 607 | ||
640 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 608 | ||
641 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 609 | ||
642 | MX51_PAD_DISP2_DAT1__KEY_COL7 610 | ||
643 | MX51_PAD_DISP2_DAT1__UART3_TXD 611 | ||
644 | MX51_PAD_DISP2_DAT1__USBH3_DIR 612 | ||
645 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 613 | ||
646 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 614 | ||
647 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 615 | ||
648 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 616 | ||
649 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 617 | ||
650 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 618 | ||
651 | MX51_PAD_DISP2_DAT6__GPIO1_19 619 | ||
652 | MX51_PAD_DISP2_DAT6__KEY_ROW4 620 | ||
653 | MX51_PAD_DISP2_DAT6__USBH3_STP 621 | ||
654 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 622 | ||
655 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 623 | ||
656 | MX51_PAD_DISP2_DAT7__GPIO1_29 624 | ||
657 | MX51_PAD_DISP2_DAT7__KEY_ROW5 625 | ||
658 | MX51_PAD_DISP2_DAT7__USBH3_NXT 626 | ||
659 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 627 | ||
660 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 628 | ||
661 | MX51_PAD_DISP2_DAT8__GPIO1_30 629 | ||
662 | MX51_PAD_DISP2_DAT8__KEY_ROW6 630 | ||
663 | MX51_PAD_DISP2_DAT8__USBH3_DATA0 631 | ||
664 | MX51_PAD_DISP2_DAT9__AUD6_RXC 632 | ||
665 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 633 | ||
666 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 634 | ||
667 | MX51_PAD_DISP2_DAT9__GPIO1_31 635 | ||
668 | MX51_PAD_DISP2_DAT9__USBH3_DATA1 636 | ||
669 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 637 | ||
670 | MX51_PAD_DISP2_DAT10__DISP2_SER_CS 638 | ||
671 | MX51_PAD_DISP2_DAT10__FEC_COL 639 | ||
672 | MX51_PAD_DISP2_DAT10__KEY_ROW7 640 | ||
673 | MX51_PAD_DISP2_DAT10__USBH3_DATA2 641 | ||
674 | MX51_PAD_DISP2_DAT11__AUD6_TXD 642 | ||
675 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 643 | ||
676 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 644 | ||
677 | MX51_PAD_DISP2_DAT11__GPIO1_10 645 | ||
678 | MX51_PAD_DISP2_DAT11__USBH3_DATA3 646 | ||
679 | MX51_PAD_DISP2_DAT12__AUD6_RXD 647 | ||
680 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 648 | ||
681 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 649 | ||
682 | MX51_PAD_DISP2_DAT12__USBH3_DATA4 650 | ||
683 | MX51_PAD_DISP2_DAT13__AUD6_TXC 651 | ||
684 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 652 | ||
685 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 653 | ||
686 | MX51_PAD_DISP2_DAT13__USBH3_DATA5 654 | ||
687 | MX51_PAD_DISP2_DAT14__AUD6_TXFS 655 | ||
688 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 656 | ||
689 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 657 | ||
690 | MX51_PAD_DISP2_DAT14__USBH3_DATA6 658 | ||
691 | MX51_PAD_DISP2_DAT15__AUD6_RXFS 659 | ||
692 | MX51_PAD_DISP2_DAT15__DISP1_SER_CS 660 | ||
693 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 661 | ||
694 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 662 | ||
695 | MX51_PAD_DISP2_DAT15__USBH3_DATA7 663 | ||
696 | MX51_PAD_SD1_CMD__AUD5_RXFS 664 | ||
697 | MX51_PAD_SD1_CMD__CSPI_MOSI 665 | ||
698 | MX51_PAD_SD1_CMD__SD1_CMD 666 | ||
699 | MX51_PAD_SD1_CLK__AUD5_RXC 667 | ||
700 | MX51_PAD_SD1_CLK__CSPI_SCLK 668 | ||
701 | MX51_PAD_SD1_CLK__SD1_CLK 669 | ||
702 | MX51_PAD_SD1_DATA0__AUD5_TXD 670 | ||
703 | MX51_PAD_SD1_DATA0__CSPI_MISO 671 | ||
704 | MX51_PAD_SD1_DATA0__SD1_DATA0 672 | ||
705 | MX51_PAD_EIM_DA0__EIM_DA0 673 | ||
706 | MX51_PAD_EIM_DA1__EIM_DA1 674 | ||
707 | MX51_PAD_EIM_DA2__EIM_DA2 675 | ||
708 | MX51_PAD_EIM_DA3__EIM_DA3 676 | ||
709 | MX51_PAD_SD1_DATA1__AUD5_RXD 677 | ||
710 | MX51_PAD_SD1_DATA1__SD1_DATA1 678 | ||
711 | MX51_PAD_EIM_DA4__EIM_DA4 679 | ||
712 | MX51_PAD_EIM_DA5__EIM_DA5 680 | ||
713 | MX51_PAD_EIM_DA6__EIM_DA6 681 | ||
714 | MX51_PAD_EIM_DA7__EIM_DA7 682 | ||
715 | MX51_PAD_SD1_DATA2__AUD5_TXC 683 | ||
716 | MX51_PAD_SD1_DATA2__SD1_DATA2 684 | ||
717 | MX51_PAD_EIM_DA10__EIM_DA10 685 | ||
718 | MX51_PAD_EIM_DA11__EIM_DA11 686 | ||
719 | MX51_PAD_EIM_DA8__EIM_DA8 687 | ||
720 | MX51_PAD_EIM_DA9__EIM_DA9 688 | ||
721 | MX51_PAD_SD1_DATA3__AUD5_TXFS 689 | ||
722 | MX51_PAD_SD1_DATA3__CSPI_SS1 690 | ||
723 | MX51_PAD_SD1_DATA3__SD1_DATA3 691 | ||
724 | MX51_PAD_GPIO1_0__CSPI_SS2 692 | ||
725 | MX51_PAD_GPIO1_0__GPIO1_0 693 | ||
726 | MX51_PAD_GPIO1_0__SD1_CD 694 | ||
727 | MX51_PAD_GPIO1_1__CSPI_MISO 695 | ||
728 | MX51_PAD_GPIO1_1__GPIO1_1 696 | ||
729 | MX51_PAD_GPIO1_1__SD1_WP 697 | ||
730 | MX51_PAD_EIM_DA12__EIM_DA12 698 | ||
731 | MX51_PAD_EIM_DA13__EIM_DA13 699 | ||
732 | MX51_PAD_EIM_DA14__EIM_DA14 700 | ||
733 | MX51_PAD_EIM_DA15__EIM_DA15 701 | ||
734 | MX51_PAD_SD2_CMD__CSPI_MOSI 702 | ||
735 | MX51_PAD_SD2_CMD__I2C1_SCL 703 | ||
736 | MX51_PAD_SD2_CMD__SD2_CMD 704 | ||
737 | MX51_PAD_SD2_CLK__CSPI_SCLK 705 | ||
738 | MX51_PAD_SD2_CLK__I2C1_SDA 706 | ||
739 | MX51_PAD_SD2_CLK__SD2_CLK 707 | ||
740 | MX51_PAD_SD2_DATA0__CSPI_MISO 708 | ||
741 | MX51_PAD_SD2_DATA0__SD1_DAT4 709 | ||
742 | MX51_PAD_SD2_DATA0__SD2_DATA0 710 | ||
743 | MX51_PAD_SD2_DATA1__SD1_DAT5 711 | ||
744 | MX51_PAD_SD2_DATA1__SD2_DATA1 712 | ||
745 | MX51_PAD_SD2_DATA1__USBH3_H2_DP 713 | ||
746 | MX51_PAD_SD2_DATA2__SD1_DAT6 714 | ||
747 | MX51_PAD_SD2_DATA2__SD2_DATA2 715 | ||
748 | MX51_PAD_SD2_DATA2__USBH3_H2_DM 716 | ||
749 | MX51_PAD_SD2_DATA3__CSPI_SS2 717 | ||
750 | MX51_PAD_SD2_DATA3__SD1_DAT7 718 | ||
751 | MX51_PAD_SD2_DATA3__SD2_DATA3 719 | ||
752 | MX51_PAD_GPIO1_2__CCM_OUT_2 720 | ||
753 | MX51_PAD_GPIO1_2__GPIO1_2 721 | ||
754 | MX51_PAD_GPIO1_2__I2C2_SCL 722 | ||
755 | MX51_PAD_GPIO1_2__PLL1_BYP 723 | ||
756 | MX51_PAD_GPIO1_2__PWM1_PWMO 724 | ||
757 | MX51_PAD_GPIO1_3__GPIO1_3 725 | ||
758 | MX51_PAD_GPIO1_3__I2C2_SDA 726 | ||
759 | MX51_PAD_GPIO1_3__PLL2_BYP 727 | ||
760 | MX51_PAD_GPIO1_3__PWM2_PWMO 728 | ||
761 | MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 729 | ||
762 | MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 730 | ||
763 | MX51_PAD_GPIO1_4__DISP2_EXT_CLK 731 | ||
764 | MX51_PAD_GPIO1_4__EIM_RDY 732 | ||
765 | MX51_PAD_GPIO1_4__GPIO1_4 733 | ||
766 | MX51_PAD_GPIO1_4__WDOG1_WDOG_B 734 | ||
767 | MX51_PAD_GPIO1_5__CSI2_MCLK 735 | ||
768 | MX51_PAD_GPIO1_5__DISP2_PIN16 736 | ||
769 | MX51_PAD_GPIO1_5__GPIO1_5 737 | ||
770 | MX51_PAD_GPIO1_5__WDOG2_WDOG_B 738 | ||
771 | MX51_PAD_GPIO1_6__DISP2_PIN17 739 | ||
772 | MX51_PAD_GPIO1_6__GPIO1_6 740 | ||
773 | MX51_PAD_GPIO1_6__REF_EN_B 741 | ||
774 | MX51_PAD_GPIO1_7__CCM_OUT_0 742 | ||
775 | MX51_PAD_GPIO1_7__GPIO1_7 743 | ||
776 | MX51_PAD_GPIO1_7__SD2_WP 744 | ||
777 | MX51_PAD_GPIO1_7__SPDIF_OUT1 745 | ||
778 | MX51_PAD_GPIO1_8__CSI2_DATA_EN 746 | ||
779 | MX51_PAD_GPIO1_8__GPIO1_8 747 | ||
780 | MX51_PAD_GPIO1_8__SD2_CD 748 | ||
781 | MX51_PAD_GPIO1_8__USBH3_PWR 749 | ||
782 | MX51_PAD_GPIO1_9__CCM_OUT_1 750 | ||
783 | MX51_PAD_GPIO1_9__DISP2_D1_CS 751 | ||
784 | MX51_PAD_GPIO1_9__DISP2_SER_CS 752 | ||
785 | MX51_PAD_GPIO1_9__GPIO1_9 753 | ||
786 | MX51_PAD_GPIO1_9__SD2_LCTL 754 | ||
787 | MX51_PAD_GPIO1_9__USBH3_OC 755 | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt deleted file mode 100644 index ca85ca432ef..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt +++ /dev/null | |||
@@ -1,1202 +0,0 @@ | |||
1 | * Freescale IMX53 IOMUX Controller | ||
2 | |||
3 | Please refer to fsl,imx-pinctrl.txt in this directory for common binding part | ||
4 | and usage. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "fsl,imx53-iomuxc" | ||
8 | - fsl,pins: two integers array, represents a group of pins mux and config | ||
9 | setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a | ||
10 | pin working on a specific function, CONFIG is the pad setting value like | ||
11 | pull-up for this pin. Please refer to imx53 datasheet for the valid pad | ||
12 | config settings. | ||
13 | |||
14 | CONFIG bits definition: | ||
15 | PAD_CTL_HVE (1 << 13) | ||
16 | PAD_CTL_HYS (1 << 8) | ||
17 | PAD_CTL_PKE (1 << 7) | ||
18 | PAD_CTL_PUE (1 << 6) | ||
19 | PAD_CTL_PUS_100K_DOWN (0 << 4) | ||
20 | PAD_CTL_PUS_47K_UP (1 << 4) | ||
21 | PAD_CTL_PUS_100K_UP (2 << 4) | ||
22 | PAD_CTL_PUS_22K_UP (3 << 4) | ||
23 | PAD_CTL_ODE (1 << 3) | ||
24 | PAD_CTL_DSE_LOW (0 << 1) | ||
25 | PAD_CTL_DSE_MED (1 << 1) | ||
26 | PAD_CTL_DSE_HIGH (2 << 1) | ||
27 | PAD_CTL_DSE_MAX (3 << 1) | ||
28 | PAD_CTL_SRE_FAST (1 << 0) | ||
29 | PAD_CTL_SRE_SLOW (0 << 0) | ||
30 | |||
31 | See below for available PIN_FUNC_ID for imx53: | ||
32 | MX53_PAD_GPIO_19__KPP_COL_5 0 | ||
33 | MX53_PAD_GPIO_19__GPIO4_5 1 | ||
34 | MX53_PAD_GPIO_19__CCM_CLKO 2 | ||
35 | MX53_PAD_GPIO_19__SPDIF_OUT1 3 | ||
36 | MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 4 | ||
37 | MX53_PAD_GPIO_19__ECSPI1_RDY 5 | ||
38 | MX53_PAD_GPIO_19__FEC_TDATA_3 6 | ||
39 | MX53_PAD_GPIO_19__SRC_INT_BOOT 7 | ||
40 | MX53_PAD_KEY_COL0__KPP_COL_0 8 | ||
41 | MX53_PAD_KEY_COL0__GPIO4_6 9 | ||
42 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 10 | ||
43 | MX53_PAD_KEY_COL0__UART4_TXD_MUX 11 | ||
44 | MX53_PAD_KEY_COL0__ECSPI1_SCLK 12 | ||
45 | MX53_PAD_KEY_COL0__FEC_RDATA_3 13 | ||
46 | MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 14 | ||
47 | MX53_PAD_KEY_ROW0__KPP_ROW_0 15 | ||
48 | MX53_PAD_KEY_ROW0__GPIO4_7 16 | ||
49 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 17 | ||
50 | MX53_PAD_KEY_ROW0__UART4_RXD_MUX 18 | ||
51 | MX53_PAD_KEY_ROW0__ECSPI1_MOSI 19 | ||
52 | MX53_PAD_KEY_ROW0__FEC_TX_ER 20 | ||
53 | MX53_PAD_KEY_COL1__KPP_COL_1 21 | ||
54 | MX53_PAD_KEY_COL1__GPIO4_8 22 | ||
55 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 23 | ||
56 | MX53_PAD_KEY_COL1__UART5_TXD_MUX 24 | ||
57 | MX53_PAD_KEY_COL1__ECSPI1_MISO 25 | ||
58 | MX53_PAD_KEY_COL1__FEC_RX_CLK 26 | ||
59 | MX53_PAD_KEY_COL1__USBPHY1_TXREADY 27 | ||
60 | MX53_PAD_KEY_ROW1__KPP_ROW_1 28 | ||
61 | MX53_PAD_KEY_ROW1__GPIO4_9 29 | ||
62 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 30 | ||
63 | MX53_PAD_KEY_ROW1__UART5_RXD_MUX 31 | ||
64 | MX53_PAD_KEY_ROW1__ECSPI1_SS0 32 | ||
65 | MX53_PAD_KEY_ROW1__FEC_COL 33 | ||
66 | MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 34 | ||
67 | MX53_PAD_KEY_COL2__KPP_COL_2 35 | ||
68 | MX53_PAD_KEY_COL2__GPIO4_10 36 | ||
69 | MX53_PAD_KEY_COL2__CAN1_TXCAN 37 | ||
70 | MX53_PAD_KEY_COL2__FEC_MDIO 38 | ||
71 | MX53_PAD_KEY_COL2__ECSPI1_SS1 39 | ||
72 | MX53_PAD_KEY_COL2__FEC_RDATA_2 40 | ||
73 | MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 41 | ||
74 | MX53_PAD_KEY_ROW2__KPP_ROW_2 42 | ||
75 | MX53_PAD_KEY_ROW2__GPIO4_11 43 | ||
76 | MX53_PAD_KEY_ROW2__CAN1_RXCAN 44 | ||
77 | MX53_PAD_KEY_ROW2__FEC_MDC 45 | ||
78 | MX53_PAD_KEY_ROW2__ECSPI1_SS2 46 | ||
79 | MX53_PAD_KEY_ROW2__FEC_TDATA_2 47 | ||
80 | MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 48 | ||
81 | MX53_PAD_KEY_COL3__KPP_COL_3 49 | ||
82 | MX53_PAD_KEY_COL3__GPIO4_12 50 | ||
83 | MX53_PAD_KEY_COL3__USBOH3_H2_DP 51 | ||
84 | MX53_PAD_KEY_COL3__SPDIF_IN1 52 | ||
85 | MX53_PAD_KEY_COL3__I2C2_SCL 53 | ||
86 | MX53_PAD_KEY_COL3__ECSPI1_SS3 54 | ||
87 | MX53_PAD_KEY_COL3__FEC_CRS 55 | ||
88 | MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 56 | ||
89 | MX53_PAD_KEY_ROW3__KPP_ROW_3 57 | ||
90 | MX53_PAD_KEY_ROW3__GPIO4_13 58 | ||
91 | MX53_PAD_KEY_ROW3__USBOH3_H2_DM 59 | ||
92 | MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 60 | ||
93 | MX53_PAD_KEY_ROW3__I2C2_SDA 61 | ||
94 | MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 62 | ||
95 | MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 63 | ||
96 | MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 64 | ||
97 | MX53_PAD_KEY_COL4__KPP_COL_4 65 | ||
98 | MX53_PAD_KEY_COL4__GPIO4_14 66 | ||
99 | MX53_PAD_KEY_COL4__CAN2_TXCAN 67 | ||
100 | MX53_PAD_KEY_COL4__IPU_SISG_4 68 | ||
101 | MX53_PAD_KEY_COL4__UART5_RTS 69 | ||
102 | MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 70 | ||
103 | MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 71 | ||
104 | MX53_PAD_KEY_ROW4__KPP_ROW_4 72 | ||
105 | MX53_PAD_KEY_ROW4__GPIO4_15 73 | ||
106 | MX53_PAD_KEY_ROW4__CAN2_RXCAN 74 | ||
107 | MX53_PAD_KEY_ROW4__IPU_SISG_5 75 | ||
108 | MX53_PAD_KEY_ROW4__UART5_CTS 76 | ||
109 | MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 77 | ||
110 | MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 78 | ||
111 | MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 79 | ||
112 | MX53_PAD_DI0_DISP_CLK__GPIO4_16 80 | ||
113 | MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 81 | ||
114 | MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 82 | ||
115 | MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 83 | ||
116 | MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 84 | ||
117 | MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 85 | ||
118 | MX53_PAD_DI0_PIN15__GPIO4_17 86 | ||
119 | MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 87 | ||
120 | MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 88 | ||
121 | MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 89 | ||
122 | MX53_PAD_DI0_PIN15__USBPHY1_BVALID 90 | ||
123 | MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 91 | ||
124 | MX53_PAD_DI0_PIN2__GPIO4_18 92 | ||
125 | MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 93 | ||
126 | MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 94 | ||
127 | MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 95 | ||
128 | MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 96 | ||
129 | MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 97 | ||
130 | MX53_PAD_DI0_PIN3__GPIO4_19 98 | ||
131 | MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 99 | ||
132 | MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 100 | ||
133 | MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 101 | ||
134 | MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 102 | ||
135 | MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 103 | ||
136 | MX53_PAD_DI0_PIN4__GPIO4_20 104 | ||
137 | MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 105 | ||
138 | MX53_PAD_DI0_PIN4__ESDHC1_WP 106 | ||
139 | MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 107 | ||
140 | MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 108 | ||
141 | MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 109 | ||
142 | MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 110 | ||
143 | MX53_PAD_DISP0_DAT0__GPIO4_21 111 | ||
144 | MX53_PAD_DISP0_DAT0__CSPI_SCLK 112 | ||
145 | MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 113 | ||
146 | MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 114 | ||
147 | MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 115 | ||
148 | MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 116 | ||
149 | MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 117 | ||
150 | MX53_PAD_DISP0_DAT1__GPIO4_22 118 | ||
151 | MX53_PAD_DISP0_DAT1__CSPI_MOSI 119 | ||
152 | MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 120 | ||
153 | MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 121 | ||
154 | MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 122 | ||
155 | MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 123 | ||
156 | MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 124 | ||
157 | MX53_PAD_DISP0_DAT2__GPIO4_23 125 | ||
158 | MX53_PAD_DISP0_DAT2__CSPI_MISO 126 | ||
159 | MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 127 | ||
160 | MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 128 | ||
161 | MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 129 | ||
162 | MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 130 | ||
163 | MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 131 | ||
164 | MX53_PAD_DISP0_DAT3__GPIO4_24 132 | ||
165 | MX53_PAD_DISP0_DAT3__CSPI_SS0 133 | ||
166 | MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 134 | ||
167 | MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 135 | ||
168 | MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 136 | ||
169 | MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 137 | ||
170 | MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 138 | ||
171 | MX53_PAD_DISP0_DAT4__GPIO4_25 139 | ||
172 | MX53_PAD_DISP0_DAT4__CSPI_SS1 140 | ||
173 | MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 141 | ||
174 | MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 142 | ||
175 | MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 143 | ||
176 | MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 144 | ||
177 | MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 145 | ||
178 | MX53_PAD_DISP0_DAT5__GPIO4_26 146 | ||
179 | MX53_PAD_DISP0_DAT5__CSPI_SS2 147 | ||
180 | MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 148 | ||
181 | MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 149 | ||
182 | MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 150 | ||
183 | MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 151 | ||
184 | MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 152 | ||
185 | MX53_PAD_DISP0_DAT6__GPIO4_27 153 | ||
186 | MX53_PAD_DISP0_DAT6__CSPI_SS3 154 | ||
187 | MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 155 | ||
188 | MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 156 | ||
189 | MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 157 | ||
190 | MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 158 | ||
191 | MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 159 | ||
192 | MX53_PAD_DISP0_DAT7__GPIO4_28 160 | ||
193 | MX53_PAD_DISP0_DAT7__CSPI_RDY 161 | ||
194 | MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 162 | ||
195 | MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 163 | ||
196 | MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 164 | ||
197 | MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 165 | ||
198 | MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 166 | ||
199 | MX53_PAD_DISP0_DAT8__GPIO4_29 167 | ||
200 | MX53_PAD_DISP0_DAT8__PWM1_PWMO 168 | ||
201 | MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 169 | ||
202 | MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 170 | ||
203 | MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 171 | ||
204 | MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 172 | ||
205 | MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 173 | ||
206 | MX53_PAD_DISP0_DAT9__GPIO4_30 174 | ||
207 | MX53_PAD_DISP0_DAT9__PWM2_PWMO 175 | ||
208 | MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 176 | ||
209 | MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 177 | ||
210 | MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 178 | ||
211 | MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 179 | ||
212 | MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 180 | ||
213 | MX53_PAD_DISP0_DAT10__GPIO4_31 181 | ||
214 | MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 182 | ||
215 | MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 183 | ||
216 | MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 184 | ||
217 | MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 185 | ||
218 | MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 186 | ||
219 | MX53_PAD_DISP0_DAT11__GPIO5_5 187 | ||
220 | MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 188 | ||
221 | MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 189 | ||
222 | MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 190 | ||
223 | MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 191 | ||
224 | MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 192 | ||
225 | MX53_PAD_DISP0_DAT12__GPIO5_6 193 | ||
226 | MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 194 | ||
227 | MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 195 | ||
228 | MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 196 | ||
229 | MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 197 | ||
230 | MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 198 | ||
231 | MX53_PAD_DISP0_DAT13__GPIO5_7 199 | ||
232 | MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 200 | ||
233 | MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 201 | ||
234 | MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 202 | ||
235 | MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 203 | ||
236 | MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 204 | ||
237 | MX53_PAD_DISP0_DAT14__GPIO5_8 205 | ||
238 | MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 206 | ||
239 | MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 207 | ||
240 | MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 208 | ||
241 | MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 209 | ||
242 | MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 210 | ||
243 | MX53_PAD_DISP0_DAT15__GPIO5_9 211 | ||
244 | MX53_PAD_DISP0_DAT15__ECSPI1_SS1 212 | ||
245 | MX53_PAD_DISP0_DAT15__ECSPI2_SS1 213 | ||
246 | MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 214 | ||
247 | MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 215 | ||
248 | MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 216 | ||
249 | MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 217 | ||
250 | MX53_PAD_DISP0_DAT16__GPIO5_10 218 | ||
251 | MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 219 | ||
252 | MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 220 | ||
253 | MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 221 | ||
254 | MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 222 | ||
255 | MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 223 | ||
256 | MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 224 | ||
257 | MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 225 | ||
258 | MX53_PAD_DISP0_DAT17__GPIO5_11 226 | ||
259 | MX53_PAD_DISP0_DAT17__ECSPI2_MISO 227 | ||
260 | MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 228 | ||
261 | MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 229 | ||
262 | MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 230 | ||
263 | MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 231 | ||
264 | MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 232 | ||
265 | MX53_PAD_DISP0_DAT18__GPIO5_12 233 | ||
266 | MX53_PAD_DISP0_DAT18__ECSPI2_SS0 234 | ||
267 | MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 235 | ||
268 | MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 236 | ||
269 | MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 237 | ||
270 | MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 238 | ||
271 | MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 239 | ||
272 | MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 240 | ||
273 | MX53_PAD_DISP0_DAT19__GPIO5_13 241 | ||
274 | MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 242 | ||
275 | MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 243 | ||
276 | MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 244 | ||
277 | MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 245 | ||
278 | MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 246 | ||
279 | MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 247 | ||
280 | MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 248 | ||
281 | MX53_PAD_DISP0_DAT20__GPIO5_14 249 | ||
282 | MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 250 | ||
283 | MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 251 | ||
284 | MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 252 | ||
285 | MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 253 | ||
286 | MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 254 | ||
287 | MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 255 | ||
288 | MX53_PAD_DISP0_DAT21__GPIO5_15 256 | ||
289 | MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 257 | ||
290 | MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 258 | ||
291 | MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 259 | ||
292 | MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 260 | ||
293 | MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 261 | ||
294 | MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 262 | ||
295 | MX53_PAD_DISP0_DAT22__GPIO5_16 263 | ||
296 | MX53_PAD_DISP0_DAT22__ECSPI1_MISO 264 | ||
297 | MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 265 | ||
298 | MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 266 | ||
299 | MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 267 | ||
300 | MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 268 | ||
301 | MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 269 | ||
302 | MX53_PAD_DISP0_DAT23__GPIO5_17 270 | ||
303 | MX53_PAD_DISP0_DAT23__ECSPI1_SS0 271 | ||
304 | MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 272 | ||
305 | MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 273 | ||
306 | MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 274 | ||
307 | MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 275 | ||
308 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 276 | ||
309 | MX53_PAD_CSI0_PIXCLK__GPIO5_18 277 | ||
310 | MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 278 | ||
311 | MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 279 | ||
312 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 280 | ||
313 | MX53_PAD_CSI0_MCLK__GPIO5_19 281 | ||
314 | MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 282 | ||
315 | MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 283 | ||
316 | MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 284 | ||
317 | MX53_PAD_CSI0_MCLK__TPIU_TRCTL 285 | ||
318 | MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 286 | ||
319 | MX53_PAD_CSI0_DATA_EN__GPIO5_20 287 | ||
320 | MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 288 | ||
321 | MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 289 | ||
322 | MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 290 | ||
323 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 291 | ||
324 | MX53_PAD_CSI0_VSYNC__GPIO5_21 292 | ||
325 | MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 293 | ||
326 | MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 294 | ||
327 | MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 295 | ||
328 | MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 296 | ||
329 | MX53_PAD_CSI0_DAT4__GPIO5_22 297 | ||
330 | MX53_PAD_CSI0_DAT4__KPP_COL_5 298 | ||
331 | MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 299 | ||
332 | MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 300 | ||
333 | MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 301 | ||
334 | MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 302 | ||
335 | MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 303 | ||
336 | MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 304 | ||
337 | MX53_PAD_CSI0_DAT5__GPIO5_23 305 | ||
338 | MX53_PAD_CSI0_DAT5__KPP_ROW_5 306 | ||
339 | MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 307 | ||
340 | MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 308 | ||
341 | MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 309 | ||
342 | MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 310 | ||
343 | MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 311 | ||
344 | MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 312 | ||
345 | MX53_PAD_CSI0_DAT6__GPIO5_24 313 | ||
346 | MX53_PAD_CSI0_DAT6__KPP_COL_6 314 | ||
347 | MX53_PAD_CSI0_DAT6__ECSPI1_MISO 315 | ||
348 | MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 316 | ||
349 | MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 317 | ||
350 | MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 318 | ||
351 | MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 319 | ||
352 | MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 320 | ||
353 | MX53_PAD_CSI0_DAT7__GPIO5_25 321 | ||
354 | MX53_PAD_CSI0_DAT7__KPP_ROW_6 322 | ||
355 | MX53_PAD_CSI0_DAT7__ECSPI1_SS0 323 | ||
356 | MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 324 | ||
357 | MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 325 | ||
358 | MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 326 | ||
359 | MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 327 | ||
360 | MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 328 | ||
361 | MX53_PAD_CSI0_DAT8__GPIO5_26 329 | ||
362 | MX53_PAD_CSI0_DAT8__KPP_COL_7 330 | ||
363 | MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 331 | ||
364 | MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 332 | ||
365 | MX53_PAD_CSI0_DAT8__I2C1_SDA 333 | ||
366 | MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 334 | ||
367 | MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 335 | ||
368 | MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 336 | ||
369 | MX53_PAD_CSI0_DAT9__GPIO5_27 337 | ||
370 | MX53_PAD_CSI0_DAT9__KPP_ROW_7 338 | ||
371 | MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 339 | ||
372 | MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 340 | ||
373 | MX53_PAD_CSI0_DAT9__I2C1_SCL 341 | ||
374 | MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 342 | ||
375 | MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 343 | ||
376 | MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 344 | ||
377 | MX53_PAD_CSI0_DAT10__GPIO5_28 345 | ||
378 | MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 346 | ||
379 | MX53_PAD_CSI0_DAT10__ECSPI2_MISO 347 | ||
380 | MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 348 | ||
381 | MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 349 | ||
382 | MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 350 | ||
383 | MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 351 | ||
384 | MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 352 | ||
385 | MX53_PAD_CSI0_DAT11__GPIO5_29 353 | ||
386 | MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 354 | ||
387 | MX53_PAD_CSI0_DAT11__ECSPI2_SS0 355 | ||
388 | MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 356 | ||
389 | MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 357 | ||
390 | MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 358 | ||
391 | MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 359 | ||
392 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 360 | ||
393 | MX53_PAD_CSI0_DAT12__GPIO5_30 361 | ||
394 | MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 362 | ||
395 | MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 363 | ||
396 | MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 364 | ||
397 | MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 365 | ||
398 | MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 366 | ||
399 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 367 | ||
400 | MX53_PAD_CSI0_DAT13__GPIO5_31 368 | ||
401 | MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 369 | ||
402 | MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 370 | ||
403 | MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 371 | ||
404 | MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 372 | ||
405 | MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 373 | ||
406 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 374 | ||
407 | MX53_PAD_CSI0_DAT14__GPIO6_0 375 | ||
408 | MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 376 | ||
409 | MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 377 | ||
410 | MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 378 | ||
411 | MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 379 | ||
412 | MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 380 | ||
413 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 381 | ||
414 | MX53_PAD_CSI0_DAT15__GPIO6_1 382 | ||
415 | MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 383 | ||
416 | MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 384 | ||
417 | MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 385 | ||
418 | MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 386 | ||
419 | MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 387 | ||
420 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 388 | ||
421 | MX53_PAD_CSI0_DAT16__GPIO6_2 389 | ||
422 | MX53_PAD_CSI0_DAT16__UART4_RTS 390 | ||
423 | MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 391 | ||
424 | MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 392 | ||
425 | MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 393 | ||
426 | MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 394 | ||
427 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 395 | ||
428 | MX53_PAD_CSI0_DAT17__GPIO6_3 396 | ||
429 | MX53_PAD_CSI0_DAT17__UART4_CTS 397 | ||
430 | MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 398 | ||
431 | MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 399 | ||
432 | MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 400 | ||
433 | MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 401 | ||
434 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 402 | ||
435 | MX53_PAD_CSI0_DAT18__GPIO6_4 403 | ||
436 | MX53_PAD_CSI0_DAT18__UART5_RTS 404 | ||
437 | MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 405 | ||
438 | MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 406 | ||
439 | MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 407 | ||
440 | MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 408 | ||
441 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 409 | ||
442 | MX53_PAD_CSI0_DAT19__GPIO6_5 410 | ||
443 | MX53_PAD_CSI0_DAT19__UART5_CTS 411 | ||
444 | MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 412 | ||
445 | MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 413 | ||
446 | MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 414 | ||
447 | MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 415 | ||
448 | MX53_PAD_EIM_A25__EMI_WEIM_A_25 416 | ||
449 | MX53_PAD_EIM_A25__GPIO5_2 417 | ||
450 | MX53_PAD_EIM_A25__ECSPI2_RDY 418 | ||
451 | MX53_PAD_EIM_A25__IPU_DI1_PIN12 419 | ||
452 | MX53_PAD_EIM_A25__CSPI_SS1 420 | ||
453 | MX53_PAD_EIM_A25__IPU_DI0_D1_CS 421 | ||
454 | MX53_PAD_EIM_A25__USBPHY1_BISTOK 422 | ||
455 | MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 423 | ||
456 | MX53_PAD_EIM_EB2__GPIO2_30 424 | ||
457 | MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 425 | ||
458 | MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 426 | ||
459 | MX53_PAD_EIM_EB2__ECSPI1_SS0 427 | ||
460 | MX53_PAD_EIM_EB2__I2C2_SCL 428 | ||
461 | MX53_PAD_EIM_D16__EMI_WEIM_D_16 429 | ||
462 | MX53_PAD_EIM_D16__GPIO3_16 430 | ||
463 | MX53_PAD_EIM_D16__IPU_DI0_PIN5 431 | ||
464 | MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 432 | ||
465 | MX53_PAD_EIM_D16__ECSPI1_SCLK 433 | ||
466 | MX53_PAD_EIM_D16__I2C2_SDA 434 | ||
467 | MX53_PAD_EIM_D17__EMI_WEIM_D_17 435 | ||
468 | MX53_PAD_EIM_D17__GPIO3_17 436 | ||
469 | MX53_PAD_EIM_D17__IPU_DI0_PIN6 437 | ||
470 | MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 438 | ||
471 | MX53_PAD_EIM_D17__ECSPI1_MISO 439 | ||
472 | MX53_PAD_EIM_D17__I2C3_SCL 440 | ||
473 | MX53_PAD_EIM_D18__EMI_WEIM_D_18 441 | ||
474 | MX53_PAD_EIM_D18__GPIO3_18 442 | ||
475 | MX53_PAD_EIM_D18__IPU_DI0_PIN7 443 | ||
476 | MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 444 | ||
477 | MX53_PAD_EIM_D18__ECSPI1_MOSI 445 | ||
478 | MX53_PAD_EIM_D18__I2C3_SDA 446 | ||
479 | MX53_PAD_EIM_D18__IPU_DI1_D0_CS 447 | ||
480 | MX53_PAD_EIM_D19__EMI_WEIM_D_19 448 | ||
481 | MX53_PAD_EIM_D19__GPIO3_19 449 | ||
482 | MX53_PAD_EIM_D19__IPU_DI0_PIN8 450 | ||
483 | MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 451 | ||
484 | MX53_PAD_EIM_D19__ECSPI1_SS1 452 | ||
485 | MX53_PAD_EIM_D19__EPIT1_EPITO 453 | ||
486 | MX53_PAD_EIM_D19__UART1_CTS 454 | ||
487 | MX53_PAD_EIM_D19__USBOH3_USBH2_OC 455 | ||
488 | MX53_PAD_EIM_D20__EMI_WEIM_D_20 456 | ||
489 | MX53_PAD_EIM_D20__GPIO3_20 457 | ||
490 | MX53_PAD_EIM_D20__IPU_DI0_PIN16 458 | ||
491 | MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 459 | ||
492 | MX53_PAD_EIM_D20__CSPI_SS0 460 | ||
493 | MX53_PAD_EIM_D20__EPIT2_EPITO 461 | ||
494 | MX53_PAD_EIM_D20__UART1_RTS 462 | ||
495 | MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 463 | ||
496 | MX53_PAD_EIM_D21__EMI_WEIM_D_21 464 | ||
497 | MX53_PAD_EIM_D21__GPIO3_21 465 | ||
498 | MX53_PAD_EIM_D21__IPU_DI0_PIN17 466 | ||
499 | MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 467 | ||
500 | MX53_PAD_EIM_D21__CSPI_SCLK 468 | ||
501 | MX53_PAD_EIM_D21__I2C1_SCL 469 | ||
502 | MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 470 | ||
503 | MX53_PAD_EIM_D22__EMI_WEIM_D_22 471 | ||
504 | MX53_PAD_EIM_D22__GPIO3_22 472 | ||
505 | MX53_PAD_EIM_D22__IPU_DI0_PIN1 473 | ||
506 | MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 474 | ||
507 | MX53_PAD_EIM_D22__CSPI_MISO 475 | ||
508 | MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 476 | ||
509 | MX53_PAD_EIM_D23__EMI_WEIM_D_23 477 | ||
510 | MX53_PAD_EIM_D23__GPIO3_23 478 | ||
511 | MX53_PAD_EIM_D23__UART3_CTS 479 | ||
512 | MX53_PAD_EIM_D23__UART1_DCD 480 | ||
513 | MX53_PAD_EIM_D23__IPU_DI0_D0_CS 481 | ||
514 | MX53_PAD_EIM_D23__IPU_DI1_PIN2 482 | ||
515 | MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 483 | ||
516 | MX53_PAD_EIM_D23__IPU_DI1_PIN14 484 | ||
517 | MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 485 | ||
518 | MX53_PAD_EIM_EB3__GPIO2_31 486 | ||
519 | MX53_PAD_EIM_EB3__UART3_RTS 487 | ||
520 | MX53_PAD_EIM_EB3__UART1_RI 488 | ||
521 | MX53_PAD_EIM_EB3__IPU_DI1_PIN3 489 | ||
522 | MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 490 | ||
523 | MX53_PAD_EIM_EB3__IPU_DI1_PIN16 491 | ||
524 | MX53_PAD_EIM_D24__EMI_WEIM_D_24 492 | ||
525 | MX53_PAD_EIM_D24__GPIO3_24 493 | ||
526 | MX53_PAD_EIM_D24__UART3_TXD_MUX 494 | ||
527 | MX53_PAD_EIM_D24__ECSPI1_SS2 495 | ||
528 | MX53_PAD_EIM_D24__CSPI_SS2 496 | ||
529 | MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 497 | ||
530 | MX53_PAD_EIM_D24__ECSPI2_SS2 498 | ||
531 | MX53_PAD_EIM_D24__UART1_DTR 499 | ||
532 | MX53_PAD_EIM_D25__EMI_WEIM_D_25 500 | ||
533 | MX53_PAD_EIM_D25__GPIO3_25 501 | ||
534 | MX53_PAD_EIM_D25__UART3_RXD_MUX 502 | ||
535 | MX53_PAD_EIM_D25__ECSPI1_SS3 503 | ||
536 | MX53_PAD_EIM_D25__CSPI_SS3 504 | ||
537 | MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 505 | ||
538 | MX53_PAD_EIM_D25__ECSPI2_SS3 506 | ||
539 | MX53_PAD_EIM_D25__UART1_DSR 507 | ||
540 | MX53_PAD_EIM_D26__EMI_WEIM_D_26 508 | ||
541 | MX53_PAD_EIM_D26__GPIO3_26 509 | ||
542 | MX53_PAD_EIM_D26__UART2_TXD_MUX 510 | ||
543 | MX53_PAD_EIM_D26__FIRI_RXD 511 | ||
544 | MX53_PAD_EIM_D26__IPU_CSI0_D_1 512 | ||
545 | MX53_PAD_EIM_D26__IPU_DI1_PIN11 513 | ||
546 | MX53_PAD_EIM_D26__IPU_SISG_2 514 | ||
547 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 515 | ||
548 | MX53_PAD_EIM_D27__EMI_WEIM_D_27 516 | ||
549 | MX53_PAD_EIM_D27__GPIO3_27 517 | ||
550 | MX53_PAD_EIM_D27__UART2_RXD_MUX 518 | ||
551 | MX53_PAD_EIM_D27__FIRI_TXD 519 | ||
552 | MX53_PAD_EIM_D27__IPU_CSI0_D_0 520 | ||
553 | MX53_PAD_EIM_D27__IPU_DI1_PIN13 521 | ||
554 | MX53_PAD_EIM_D27__IPU_SISG_3 522 | ||
555 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 523 | ||
556 | MX53_PAD_EIM_D28__EMI_WEIM_D_28 524 | ||
557 | MX53_PAD_EIM_D28__GPIO3_28 525 | ||
558 | MX53_PAD_EIM_D28__UART2_CTS 526 | ||
559 | MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 527 | ||
560 | MX53_PAD_EIM_D28__CSPI_MOSI 528 | ||
561 | MX53_PAD_EIM_D28__I2C1_SDA 529 | ||
562 | MX53_PAD_EIM_D28__IPU_EXT_TRIG 530 | ||
563 | MX53_PAD_EIM_D28__IPU_DI0_PIN13 531 | ||
564 | MX53_PAD_EIM_D29__EMI_WEIM_D_29 532 | ||
565 | MX53_PAD_EIM_D29__GPIO3_29 533 | ||
566 | MX53_PAD_EIM_D29__UART2_RTS 534 | ||
567 | MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 535 | ||
568 | MX53_PAD_EIM_D29__CSPI_SS0 536 | ||
569 | MX53_PAD_EIM_D29__IPU_DI1_PIN15 537 | ||
570 | MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 538 | ||
571 | MX53_PAD_EIM_D29__IPU_DI0_PIN14 539 | ||
572 | MX53_PAD_EIM_D30__EMI_WEIM_D_30 540 | ||
573 | MX53_PAD_EIM_D30__GPIO3_30 541 | ||
574 | MX53_PAD_EIM_D30__UART3_CTS 542 | ||
575 | MX53_PAD_EIM_D30__IPU_CSI0_D_3 543 | ||
576 | MX53_PAD_EIM_D30__IPU_DI0_PIN11 544 | ||
577 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 545 | ||
578 | MX53_PAD_EIM_D30__USBOH3_USBH1_OC 546 | ||
579 | MX53_PAD_EIM_D30__USBOH3_USBH2_OC 547 | ||
580 | MX53_PAD_EIM_D31__EMI_WEIM_D_31 548 | ||
581 | MX53_PAD_EIM_D31__GPIO3_31 549 | ||
582 | MX53_PAD_EIM_D31__UART3_RTS 550 | ||
583 | MX53_PAD_EIM_D31__IPU_CSI0_D_2 551 | ||
584 | MX53_PAD_EIM_D31__IPU_DI0_PIN12 552 | ||
585 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 553 | ||
586 | MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 554 | ||
587 | MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 555 | ||
588 | MX53_PAD_EIM_A24__EMI_WEIM_A_24 556 | ||
589 | MX53_PAD_EIM_A24__GPIO5_4 557 | ||
590 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 558 | ||
591 | MX53_PAD_EIM_A24__IPU_CSI1_D_19 559 | ||
592 | MX53_PAD_EIM_A24__IPU_SISG_2 560 | ||
593 | MX53_PAD_EIM_A24__USBPHY2_BVALID 561 | ||
594 | MX53_PAD_EIM_A23__EMI_WEIM_A_23 562 | ||
595 | MX53_PAD_EIM_A23__GPIO6_6 563 | ||
596 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 564 | ||
597 | MX53_PAD_EIM_A23__IPU_CSI1_D_18 565 | ||
598 | MX53_PAD_EIM_A23__IPU_SISG_3 566 | ||
599 | MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 567 | ||
600 | MX53_PAD_EIM_A22__EMI_WEIM_A_22 568 | ||
601 | MX53_PAD_EIM_A22__GPIO2_16 569 | ||
602 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 570 | ||
603 | MX53_PAD_EIM_A22__IPU_CSI1_D_17 571 | ||
604 | MX53_PAD_EIM_A22__SRC_BT_CFG1_7 572 | ||
605 | MX53_PAD_EIM_A21__EMI_WEIM_A_21 573 | ||
606 | MX53_PAD_EIM_A21__GPIO2_17 574 | ||
607 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 575 | ||
608 | MX53_PAD_EIM_A21__IPU_CSI1_D_16 576 | ||
609 | MX53_PAD_EIM_A21__SRC_BT_CFG1_6 577 | ||
610 | MX53_PAD_EIM_A20__EMI_WEIM_A_20 578 | ||
611 | MX53_PAD_EIM_A20__GPIO2_18 579 | ||
612 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 580 | ||
613 | MX53_PAD_EIM_A20__IPU_CSI1_D_15 581 | ||
614 | MX53_PAD_EIM_A20__SRC_BT_CFG1_5 582 | ||
615 | MX53_PAD_EIM_A19__EMI_WEIM_A_19 583 | ||
616 | MX53_PAD_EIM_A19__GPIO2_19 584 | ||
617 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 585 | ||
618 | MX53_PAD_EIM_A19__IPU_CSI1_D_14 586 | ||
619 | MX53_PAD_EIM_A19__SRC_BT_CFG1_4 587 | ||
620 | MX53_PAD_EIM_A18__EMI_WEIM_A_18 588 | ||
621 | MX53_PAD_EIM_A18__GPIO2_20 589 | ||
622 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 590 | ||
623 | MX53_PAD_EIM_A18__IPU_CSI1_D_13 591 | ||
624 | MX53_PAD_EIM_A18__SRC_BT_CFG1_3 592 | ||
625 | MX53_PAD_EIM_A17__EMI_WEIM_A_17 593 | ||
626 | MX53_PAD_EIM_A17__GPIO2_21 594 | ||
627 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 595 | ||
628 | MX53_PAD_EIM_A17__IPU_CSI1_D_12 596 | ||
629 | MX53_PAD_EIM_A17__SRC_BT_CFG1_2 597 | ||
630 | MX53_PAD_EIM_A16__EMI_WEIM_A_16 598 | ||
631 | MX53_PAD_EIM_A16__GPIO2_22 599 | ||
632 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 600 | ||
633 | MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 601 | ||
634 | MX53_PAD_EIM_A16__SRC_BT_CFG1_1 602 | ||
635 | MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 603 | ||
636 | MX53_PAD_EIM_CS0__GPIO2_23 604 | ||
637 | MX53_PAD_EIM_CS0__ECSPI2_SCLK 605 | ||
638 | MX53_PAD_EIM_CS0__IPU_DI1_PIN5 606 | ||
639 | MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 607 | ||
640 | MX53_PAD_EIM_CS1__GPIO2_24 608 | ||
641 | MX53_PAD_EIM_CS1__ECSPI2_MOSI 609 | ||
642 | MX53_PAD_EIM_CS1__IPU_DI1_PIN6 610 | ||
643 | MX53_PAD_EIM_OE__EMI_WEIM_OE 611 | ||
644 | MX53_PAD_EIM_OE__GPIO2_25 612 | ||
645 | MX53_PAD_EIM_OE__ECSPI2_MISO 613 | ||
646 | MX53_PAD_EIM_OE__IPU_DI1_PIN7 614 | ||
647 | MX53_PAD_EIM_OE__USBPHY2_IDDIG 615 | ||
648 | MX53_PAD_EIM_RW__EMI_WEIM_RW 616 | ||
649 | MX53_PAD_EIM_RW__GPIO2_26 617 | ||
650 | MX53_PAD_EIM_RW__ECSPI2_SS0 618 | ||
651 | MX53_PAD_EIM_RW__IPU_DI1_PIN8 619 | ||
652 | MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 620 | ||
653 | MX53_PAD_EIM_LBA__EMI_WEIM_LBA 621 | ||
654 | MX53_PAD_EIM_LBA__GPIO2_27 622 | ||
655 | MX53_PAD_EIM_LBA__ECSPI2_SS1 623 | ||
656 | MX53_PAD_EIM_LBA__IPU_DI1_PIN17 624 | ||
657 | MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 625 | ||
658 | MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 626 | ||
659 | MX53_PAD_EIM_EB0__GPIO2_28 627 | ||
660 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 628 | ||
661 | MX53_PAD_EIM_EB0__IPU_CSI1_D_11 629 | ||
662 | MX53_PAD_EIM_EB0__GPC_PMIC_RDY 630 | ||
663 | MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 631 | ||
664 | MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 632 | ||
665 | MX53_PAD_EIM_EB1__GPIO2_29 633 | ||
666 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 634 | ||
667 | MX53_PAD_EIM_EB1__IPU_CSI1_D_10 635 | ||
668 | MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 636 | ||
669 | MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 637 | ||
670 | MX53_PAD_EIM_DA0__GPIO3_0 638 | ||
671 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 639 | ||
672 | MX53_PAD_EIM_DA0__IPU_CSI1_D_9 640 | ||
673 | MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 641 | ||
674 | MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 642 | ||
675 | MX53_PAD_EIM_DA1__GPIO3_1 643 | ||
676 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 644 | ||
677 | MX53_PAD_EIM_DA1__IPU_CSI1_D_8 645 | ||
678 | MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 646 | ||
679 | MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 647 | ||
680 | MX53_PAD_EIM_DA2__GPIO3_2 648 | ||
681 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 649 | ||
682 | MX53_PAD_EIM_DA2__IPU_CSI1_D_7 650 | ||
683 | MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 651 | ||
684 | MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 652 | ||
685 | MX53_PAD_EIM_DA3__GPIO3_3 653 | ||
686 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 654 | ||
687 | MX53_PAD_EIM_DA3__IPU_CSI1_D_6 655 | ||
688 | MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 656 | ||
689 | MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 657 | ||
690 | MX53_PAD_EIM_DA4__GPIO3_4 658 | ||
691 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 659 | ||
692 | MX53_PAD_EIM_DA4__IPU_CSI1_D_5 660 | ||
693 | MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 661 | ||
694 | MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 662 | ||
695 | MX53_PAD_EIM_DA5__GPIO3_5 663 | ||
696 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 664 | ||
697 | MX53_PAD_EIM_DA5__IPU_CSI1_D_4 665 | ||
698 | MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 666 | ||
699 | MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 667 | ||
700 | MX53_PAD_EIM_DA6__GPIO3_6 668 | ||
701 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 669 | ||
702 | MX53_PAD_EIM_DA6__IPU_CSI1_D_3 670 | ||
703 | MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 671 | ||
704 | MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 672 | ||
705 | MX53_PAD_EIM_DA7__GPIO3_7 673 | ||
706 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 674 | ||
707 | MX53_PAD_EIM_DA7__IPU_CSI1_D_2 675 | ||
708 | MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 676 | ||
709 | MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 677 | ||
710 | MX53_PAD_EIM_DA8__GPIO3_8 678 | ||
711 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 679 | ||
712 | MX53_PAD_EIM_DA8__IPU_CSI1_D_1 680 | ||
713 | MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 681 | ||
714 | MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 682 | ||
715 | MX53_PAD_EIM_DA9__GPIO3_9 683 | ||
716 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 684 | ||
717 | MX53_PAD_EIM_DA9__IPU_CSI1_D_0 685 | ||
718 | MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 686 | ||
719 | MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 687 | ||
720 | MX53_PAD_EIM_DA10__GPIO3_10 688 | ||
721 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 689 | ||
722 | MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 690 | ||
723 | MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 691 | ||
724 | MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 692 | ||
725 | MX53_PAD_EIM_DA11__GPIO3_11 693 | ||
726 | MX53_PAD_EIM_DA11__IPU_DI1_PIN2 694 | ||
727 | MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 695 | ||
728 | MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 696 | ||
729 | MX53_PAD_EIM_DA12__GPIO3_12 697 | ||
730 | MX53_PAD_EIM_DA12__IPU_DI1_PIN3 698 | ||
731 | MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 699 | ||
732 | MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 700 | ||
733 | MX53_PAD_EIM_DA13__GPIO3_13 701 | ||
734 | MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 702 | ||
735 | MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 703 | ||
736 | MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 704 | ||
737 | MX53_PAD_EIM_DA14__GPIO3_14 705 | ||
738 | MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 706 | ||
739 | MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 707 | ||
740 | MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 708 | ||
741 | MX53_PAD_EIM_DA15__GPIO3_15 709 | ||
742 | MX53_PAD_EIM_DA15__IPU_DI1_PIN1 710 | ||
743 | MX53_PAD_EIM_DA15__IPU_DI1_PIN4 711 | ||
744 | MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 712 | ||
745 | MX53_PAD_NANDF_WE_B__GPIO6_12 713 | ||
746 | MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 714 | ||
747 | MX53_PAD_NANDF_RE_B__GPIO6_13 715 | ||
748 | MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 716 | ||
749 | MX53_PAD_EIM_WAIT__GPIO5_0 717 | ||
750 | MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 718 | ||
751 | MX53_PAD_LVDS1_TX3_P__GPIO6_22 719 | ||
752 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 720 | ||
753 | MX53_PAD_LVDS1_TX2_P__GPIO6_24 721 | ||
754 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 722 | ||
755 | MX53_PAD_LVDS1_CLK_P__GPIO6_26 723 | ||
756 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 724 | ||
757 | MX53_PAD_LVDS1_TX1_P__GPIO6_28 725 | ||
758 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 726 | ||
759 | MX53_PAD_LVDS1_TX0_P__GPIO6_30 727 | ||
760 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 728 | ||
761 | MX53_PAD_LVDS0_TX3_P__GPIO7_22 729 | ||
762 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 730 | ||
763 | MX53_PAD_LVDS0_CLK_P__GPIO7_24 731 | ||
764 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 732 | ||
765 | MX53_PAD_LVDS0_TX2_P__GPIO7_26 733 | ||
766 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 734 | ||
767 | MX53_PAD_LVDS0_TX1_P__GPIO7_28 735 | ||
768 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 736 | ||
769 | MX53_PAD_LVDS0_TX0_P__GPIO7_30 737 | ||
770 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 738 | ||
771 | MX53_PAD_GPIO_10__GPIO4_0 739 | ||
772 | MX53_PAD_GPIO_10__OSC32k_32K_OUT 740 | ||
773 | MX53_PAD_GPIO_11__GPIO4_1 741 | ||
774 | MX53_PAD_GPIO_12__GPIO4_2 742 | ||
775 | MX53_PAD_GPIO_13__GPIO4_3 743 | ||
776 | MX53_PAD_GPIO_14__GPIO4_4 744 | ||
777 | MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 745 | ||
778 | MX53_PAD_NANDF_CLE__GPIO6_7 746 | ||
779 | MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 747 | ||
780 | MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 748 | ||
781 | MX53_PAD_NANDF_ALE__GPIO6_8 749 | ||
782 | MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 750 | ||
783 | MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 751 | ||
784 | MX53_PAD_NANDF_WP_B__GPIO6_9 752 | ||
785 | MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 753 | ||
786 | MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 754 | ||
787 | MX53_PAD_NANDF_RB0__GPIO6_10 755 | ||
788 | MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 756 | ||
789 | MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 757 | ||
790 | MX53_PAD_NANDF_CS0__GPIO6_11 758 | ||
791 | MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 759 | ||
792 | MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 760 | ||
793 | MX53_PAD_NANDF_CS1__GPIO6_14 761 | ||
794 | MX53_PAD_NANDF_CS1__MLB_MLBCLK 762 | ||
795 | MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 763 | ||
796 | MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 764 | ||
797 | MX53_PAD_NANDF_CS2__GPIO6_15 765 | ||
798 | MX53_PAD_NANDF_CS2__IPU_SISG_0 766 | ||
799 | MX53_PAD_NANDF_CS2__ESAI1_TX0 767 | ||
800 | MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 768 | ||
801 | MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 769 | ||
802 | MX53_PAD_NANDF_CS2__MLB_MLBSIG 770 | ||
803 | MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 771 | ||
804 | MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 772 | ||
805 | MX53_PAD_NANDF_CS3__GPIO6_16 773 | ||
806 | MX53_PAD_NANDF_CS3__IPU_SISG_1 774 | ||
807 | MX53_PAD_NANDF_CS3__ESAI1_TX1 775 | ||
808 | MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 776 | ||
809 | MX53_PAD_NANDF_CS3__MLB_MLBDAT 777 | ||
810 | MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 778 | ||
811 | MX53_PAD_FEC_MDIO__FEC_MDIO 779 | ||
812 | MX53_PAD_FEC_MDIO__GPIO1_22 780 | ||
813 | MX53_PAD_FEC_MDIO__ESAI1_SCKR 781 | ||
814 | MX53_PAD_FEC_MDIO__FEC_COL 782 | ||
815 | MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 783 | ||
816 | MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 784 | ||
817 | MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 785 | ||
818 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 786 | ||
819 | MX53_PAD_FEC_REF_CLK__GPIO1_23 787 | ||
820 | MX53_PAD_FEC_REF_CLK__ESAI1_FSR 788 | ||
821 | MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 789 | ||
822 | MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 790 | ||
823 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 791 | ||
824 | MX53_PAD_FEC_RX_ER__GPIO1_24 792 | ||
825 | MX53_PAD_FEC_RX_ER__ESAI1_HCKR 793 | ||
826 | MX53_PAD_FEC_RX_ER__FEC_RX_CLK 794 | ||
827 | MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 795 | ||
828 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 796 | ||
829 | MX53_PAD_FEC_CRS_DV__GPIO1_25 797 | ||
830 | MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 798 | ||
831 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 799 | ||
832 | MX53_PAD_FEC_RXD1__GPIO1_26 800 | ||
833 | MX53_PAD_FEC_RXD1__ESAI1_FST 801 | ||
834 | MX53_PAD_FEC_RXD1__MLB_MLBSIG 802 | ||
835 | MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 803 | ||
836 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 804 | ||
837 | MX53_PAD_FEC_RXD0__GPIO1_27 805 | ||
838 | MX53_PAD_FEC_RXD0__ESAI1_HCKT 806 | ||
839 | MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 807 | ||
840 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 808 | ||
841 | MX53_PAD_FEC_TX_EN__GPIO1_28 809 | ||
842 | MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 810 | ||
843 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 811 | ||
844 | MX53_PAD_FEC_TXD1__GPIO1_29 812 | ||
845 | MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 813 | ||
846 | MX53_PAD_FEC_TXD1__MLB_MLBCLK 814 | ||
847 | MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 815 | ||
848 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 816 | ||
849 | MX53_PAD_FEC_TXD0__GPIO1_30 817 | ||
850 | MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 818 | ||
851 | MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 819 | ||
852 | MX53_PAD_FEC_MDC__FEC_MDC 820 | ||
853 | MX53_PAD_FEC_MDC__GPIO1_31 821 | ||
854 | MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 822 | ||
855 | MX53_PAD_FEC_MDC__MLB_MLBDAT 823 | ||
856 | MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 824 | ||
857 | MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 825 | ||
858 | MX53_PAD_PATA_DIOW__PATA_DIOW 826 | ||
859 | MX53_PAD_PATA_DIOW__GPIO6_17 827 | ||
860 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 828 | ||
861 | MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 829 | ||
862 | MX53_PAD_PATA_DMACK__PATA_DMACK 830 | ||
863 | MX53_PAD_PATA_DMACK__GPIO6_18 831 | ||
864 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 832 | ||
865 | MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 833 | ||
866 | MX53_PAD_PATA_DMARQ__PATA_DMARQ 834 | ||
867 | MX53_PAD_PATA_DMARQ__GPIO7_0 835 | ||
868 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 836 | ||
869 | MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 837 | ||
870 | MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 838 | ||
871 | MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 839 | ||
872 | MX53_PAD_PATA_BUFFER_EN__GPIO7_1 840 | ||
873 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 841 | ||
874 | MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 842 | ||
875 | MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 843 | ||
876 | MX53_PAD_PATA_INTRQ__PATA_INTRQ 844 | ||
877 | MX53_PAD_PATA_INTRQ__GPIO7_2 845 | ||
878 | MX53_PAD_PATA_INTRQ__UART2_CTS 846 | ||
879 | MX53_PAD_PATA_INTRQ__CAN1_TXCAN 847 | ||
880 | MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 848 | ||
881 | MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 849 | ||
882 | MX53_PAD_PATA_DIOR__PATA_DIOR 850 | ||
883 | MX53_PAD_PATA_DIOR__GPIO7_3 851 | ||
884 | MX53_PAD_PATA_DIOR__UART2_RTS 852 | ||
885 | MX53_PAD_PATA_DIOR__CAN1_RXCAN 853 | ||
886 | MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 854 | ||
887 | MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 855 | ||
888 | MX53_PAD_PATA_RESET_B__GPIO7_4 856 | ||
889 | MX53_PAD_PATA_RESET_B__ESDHC3_CMD 857 | ||
890 | MX53_PAD_PATA_RESET_B__UART1_CTS 858 | ||
891 | MX53_PAD_PATA_RESET_B__CAN2_TXCAN 859 | ||
892 | MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 860 | ||
893 | MX53_PAD_PATA_IORDY__PATA_IORDY 861 | ||
894 | MX53_PAD_PATA_IORDY__GPIO7_5 862 | ||
895 | MX53_PAD_PATA_IORDY__ESDHC3_CLK 863 | ||
896 | MX53_PAD_PATA_IORDY__UART1_RTS 864 | ||
897 | MX53_PAD_PATA_IORDY__CAN2_RXCAN 865 | ||
898 | MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 866 | ||
899 | MX53_PAD_PATA_DA_0__PATA_DA_0 867 | ||
900 | MX53_PAD_PATA_DA_0__GPIO7_6 868 | ||
901 | MX53_PAD_PATA_DA_0__ESDHC3_RST 869 | ||
902 | MX53_PAD_PATA_DA_0__OWIRE_LINE 870 | ||
903 | MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 871 | ||
904 | MX53_PAD_PATA_DA_1__PATA_DA_1 872 | ||
905 | MX53_PAD_PATA_DA_1__GPIO7_7 873 | ||
906 | MX53_PAD_PATA_DA_1__ESDHC4_CMD 874 | ||
907 | MX53_PAD_PATA_DA_1__UART3_CTS 875 | ||
908 | MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 876 | ||
909 | MX53_PAD_PATA_DA_2__PATA_DA_2 877 | ||
910 | MX53_PAD_PATA_DA_2__GPIO7_8 878 | ||
911 | MX53_PAD_PATA_DA_2__ESDHC4_CLK 879 | ||
912 | MX53_PAD_PATA_DA_2__UART3_RTS 880 | ||
913 | MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 881 | ||
914 | MX53_PAD_PATA_CS_0__PATA_CS_0 882 | ||
915 | MX53_PAD_PATA_CS_0__GPIO7_9 883 | ||
916 | MX53_PAD_PATA_CS_0__UART3_TXD_MUX 884 | ||
917 | MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 885 | ||
918 | MX53_PAD_PATA_CS_1__PATA_CS_1 886 | ||
919 | MX53_PAD_PATA_CS_1__GPIO7_10 887 | ||
920 | MX53_PAD_PATA_CS_1__UART3_RXD_MUX 888 | ||
921 | MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 889 | ||
922 | MX53_PAD_PATA_DATA0__PATA_DATA_0 890 | ||
923 | MX53_PAD_PATA_DATA0__GPIO2_0 891 | ||
924 | MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 892 | ||
925 | MX53_PAD_PATA_DATA0__ESDHC3_DAT4 893 | ||
926 | MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 894 | ||
927 | MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 895 | ||
928 | MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 896 | ||
929 | MX53_PAD_PATA_DATA1__PATA_DATA_1 897 | ||
930 | MX53_PAD_PATA_DATA1__GPIO2_1 898 | ||
931 | MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 899 | ||
932 | MX53_PAD_PATA_DATA1__ESDHC3_DAT5 900 | ||
933 | MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 901 | ||
934 | MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 902 | ||
935 | MX53_PAD_PATA_DATA2__PATA_DATA_2 903 | ||
936 | MX53_PAD_PATA_DATA2__GPIO2_2 904 | ||
937 | MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 905 | ||
938 | MX53_PAD_PATA_DATA2__ESDHC3_DAT6 906 | ||
939 | MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 907 | ||
940 | MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 908 | ||
941 | MX53_PAD_PATA_DATA3__PATA_DATA_3 909 | ||
942 | MX53_PAD_PATA_DATA3__GPIO2_3 910 | ||
943 | MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 911 | ||
944 | MX53_PAD_PATA_DATA3__ESDHC3_DAT7 912 | ||
945 | MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 913 | ||
946 | MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 914 | ||
947 | MX53_PAD_PATA_DATA4__PATA_DATA_4 915 | ||
948 | MX53_PAD_PATA_DATA4__GPIO2_4 916 | ||
949 | MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 917 | ||
950 | MX53_PAD_PATA_DATA4__ESDHC4_DAT4 918 | ||
951 | MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 919 | ||
952 | MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 920 | ||
953 | MX53_PAD_PATA_DATA5__PATA_DATA_5 921 | ||
954 | MX53_PAD_PATA_DATA5__GPIO2_5 922 | ||
955 | MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 923 | ||
956 | MX53_PAD_PATA_DATA5__ESDHC4_DAT5 924 | ||
957 | MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 925 | ||
958 | MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 926 | ||
959 | MX53_PAD_PATA_DATA6__PATA_DATA_6 927 | ||
960 | MX53_PAD_PATA_DATA6__GPIO2_6 928 | ||
961 | MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 929 | ||
962 | MX53_PAD_PATA_DATA6__ESDHC4_DAT6 930 | ||
963 | MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 931 | ||
964 | MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 932 | ||
965 | MX53_PAD_PATA_DATA7__PATA_DATA_7 933 | ||
966 | MX53_PAD_PATA_DATA7__GPIO2_7 934 | ||
967 | MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 935 | ||
968 | MX53_PAD_PATA_DATA7__ESDHC4_DAT7 936 | ||
969 | MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 937 | ||
970 | MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 938 | ||
971 | MX53_PAD_PATA_DATA8__PATA_DATA_8 939 | ||
972 | MX53_PAD_PATA_DATA8__GPIO2_8 940 | ||
973 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4 941 | ||
974 | MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 942 | ||
975 | MX53_PAD_PATA_DATA8__ESDHC3_DAT0 943 | ||
976 | MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 944 | ||
977 | MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 945 | ||
978 | MX53_PAD_PATA_DATA9__PATA_DATA_9 946 | ||
979 | MX53_PAD_PATA_DATA9__GPIO2_9 947 | ||
980 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5 948 | ||
981 | MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 949 | ||
982 | MX53_PAD_PATA_DATA9__ESDHC3_DAT1 950 | ||
983 | MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 951 | ||
984 | MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 952 | ||
985 | MX53_PAD_PATA_DATA10__PATA_DATA_10 953 | ||
986 | MX53_PAD_PATA_DATA10__GPIO2_10 954 | ||
987 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6 955 | ||
988 | MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 956 | ||
989 | MX53_PAD_PATA_DATA10__ESDHC3_DAT2 957 | ||
990 | MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 958 | ||
991 | MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 959 | ||
992 | MX53_PAD_PATA_DATA11__PATA_DATA_11 960 | ||
993 | MX53_PAD_PATA_DATA11__GPIO2_11 961 | ||
994 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7 962 | ||
995 | MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 963 | ||
996 | MX53_PAD_PATA_DATA11__ESDHC3_DAT3 964 | ||
997 | MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 965 | ||
998 | MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 966 | ||
999 | MX53_PAD_PATA_DATA12__PATA_DATA_12 967 | ||
1000 | MX53_PAD_PATA_DATA12__GPIO2_12 968 | ||
1001 | MX53_PAD_PATA_DATA12__ESDHC2_DAT4 969 | ||
1002 | MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 970 | ||
1003 | MX53_PAD_PATA_DATA12__ESDHC4_DAT0 971 | ||
1004 | MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 972 | ||
1005 | MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 973 | ||
1006 | MX53_PAD_PATA_DATA13__PATA_DATA_13 974 | ||
1007 | MX53_PAD_PATA_DATA13__GPIO2_13 975 | ||
1008 | MX53_PAD_PATA_DATA13__ESDHC2_DAT5 976 | ||
1009 | MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 977 | ||
1010 | MX53_PAD_PATA_DATA13__ESDHC4_DAT1 978 | ||
1011 | MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 979 | ||
1012 | MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 980 | ||
1013 | MX53_PAD_PATA_DATA14__PATA_DATA_14 981 | ||
1014 | MX53_PAD_PATA_DATA14__GPIO2_14 982 | ||
1015 | MX53_PAD_PATA_DATA14__ESDHC2_DAT6 983 | ||
1016 | MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 984 | ||
1017 | MX53_PAD_PATA_DATA14__ESDHC4_DAT2 985 | ||
1018 | MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 986 | ||
1019 | MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 987 | ||
1020 | MX53_PAD_PATA_DATA15__PATA_DATA_15 988 | ||
1021 | MX53_PAD_PATA_DATA15__GPIO2_15 989 | ||
1022 | MX53_PAD_PATA_DATA15__ESDHC2_DAT7 990 | ||
1023 | MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 991 | ||
1024 | MX53_PAD_PATA_DATA15__ESDHC4_DAT3 992 | ||
1025 | MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 993 | ||
1026 | MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 994 | ||
1027 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 995 | ||
1028 | MX53_PAD_SD1_DATA0__GPIO1_16 996 | ||
1029 | MX53_PAD_SD1_DATA0__GPT_CAPIN1 997 | ||
1030 | MX53_PAD_SD1_DATA0__CSPI_MISO 998 | ||
1031 | MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 999 | ||
1032 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 1000 | ||
1033 | MX53_PAD_SD1_DATA1__GPIO1_17 1001 | ||
1034 | MX53_PAD_SD1_DATA1__GPT_CAPIN2 1002 | ||
1035 | MX53_PAD_SD1_DATA1__CSPI_SS0 1003 | ||
1036 | MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 1004 | ||
1037 | MX53_PAD_SD1_CMD__ESDHC1_CMD 1005 | ||
1038 | MX53_PAD_SD1_CMD__GPIO1_18 1006 | ||
1039 | MX53_PAD_SD1_CMD__GPT_CMPOUT1 1007 | ||
1040 | MX53_PAD_SD1_CMD__CSPI_MOSI 1008 | ||
1041 | MX53_PAD_SD1_CMD__CCM_PLL1_BYP 1009 | ||
1042 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 1010 | ||
1043 | MX53_PAD_SD1_DATA2__GPIO1_19 1011 | ||
1044 | MX53_PAD_SD1_DATA2__GPT_CMPOUT2 1012 | ||
1045 | MX53_PAD_SD1_DATA2__PWM2_PWMO 1013 | ||
1046 | MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 1014 | ||
1047 | MX53_PAD_SD1_DATA2__CSPI_SS1 1015 | ||
1048 | MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 1016 | ||
1049 | MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 1017 | ||
1050 | MX53_PAD_SD1_CLK__ESDHC1_CLK 1018 | ||
1051 | MX53_PAD_SD1_CLK__GPIO1_20 1019 | ||
1052 | MX53_PAD_SD1_CLK__OSC32k_32K_OUT 1020 | ||
1053 | MX53_PAD_SD1_CLK__GPT_CLKIN 1021 | ||
1054 | MX53_PAD_SD1_CLK__CSPI_SCLK 1022 | ||
1055 | MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 1023 | ||
1056 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 1024 | ||
1057 | MX53_PAD_SD1_DATA3__GPIO1_21 1025 | ||
1058 | MX53_PAD_SD1_DATA3__GPT_CMPOUT3 1026 | ||
1059 | MX53_PAD_SD1_DATA3__PWM1_PWMO 1027 | ||
1060 | MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 1028 | ||
1061 | MX53_PAD_SD1_DATA3__CSPI_SS2 1029 | ||
1062 | MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 1030 | ||
1063 | MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 1031 | ||
1064 | MX53_PAD_SD2_CLK__ESDHC2_CLK 1032 | ||
1065 | MX53_PAD_SD2_CLK__GPIO1_10 1033 | ||
1066 | MX53_PAD_SD2_CLK__KPP_COL_5 1034 | ||
1067 | MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1035 | ||
1068 | MX53_PAD_SD2_CLK__CSPI_SCLK 1036 | ||
1069 | MX53_PAD_SD2_CLK__SCC_RANDOM_V 1037 | ||
1070 | MX53_PAD_SD2_CMD__ESDHC2_CMD 1038 | ||
1071 | MX53_PAD_SD2_CMD__GPIO1_11 1039 | ||
1072 | MX53_PAD_SD2_CMD__KPP_ROW_5 1040 | ||
1073 | MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1041 | ||
1074 | MX53_PAD_SD2_CMD__CSPI_MOSI 1042 | ||
1075 | MX53_PAD_SD2_CMD__SCC_RANDOM 1043 | ||
1076 | MX53_PAD_SD2_DATA3__ESDHC2_DAT3 1044 | ||
1077 | MX53_PAD_SD2_DATA3__GPIO1_12 1045 | ||
1078 | MX53_PAD_SD2_DATA3__KPP_COL_6 1046 | ||
1079 | MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 1047 | ||
1080 | MX53_PAD_SD2_DATA3__CSPI_SS2 1048 | ||
1081 | MX53_PAD_SD2_DATA3__SJC_DONE 1049 | ||
1082 | MX53_PAD_SD2_DATA2__ESDHC2_DAT2 1050 | ||
1083 | MX53_PAD_SD2_DATA2__GPIO1_13 1051 | ||
1084 | MX53_PAD_SD2_DATA2__KPP_ROW_6 1052 | ||
1085 | MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 1053 | ||
1086 | MX53_PAD_SD2_DATA2__CSPI_SS1 1054 | ||
1087 | MX53_PAD_SD2_DATA2__SJC_FAIL 1055 | ||
1088 | MX53_PAD_SD2_DATA1__ESDHC2_DAT1 1056 | ||
1089 | MX53_PAD_SD2_DATA1__GPIO1_14 1057 | ||
1090 | MX53_PAD_SD2_DATA1__KPP_COL_7 1058 | ||
1091 | MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 1059 | ||
1092 | MX53_PAD_SD2_DATA1__CSPI_SS0 1060 | ||
1093 | MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 1061 | ||
1094 | MX53_PAD_SD2_DATA0__ESDHC2_DAT0 1062 | ||
1095 | MX53_PAD_SD2_DATA0__GPIO1_15 1063 | ||
1096 | MX53_PAD_SD2_DATA0__KPP_ROW_7 1064 | ||
1097 | MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 1065 | ||
1098 | MX53_PAD_SD2_DATA0__CSPI_MISO 1066 | ||
1099 | MX53_PAD_SD2_DATA0__RTIC_DONE_INT 1067 | ||
1100 | MX53_PAD_GPIO_0__CCM_CLKO 1068 | ||
1101 | MX53_PAD_GPIO_0__GPIO1_0 1069 | ||
1102 | MX53_PAD_GPIO_0__KPP_COL_5 1070 | ||
1103 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 1071 | ||
1104 | MX53_PAD_GPIO_0__EPIT1_EPITO 1072 | ||
1105 | MX53_PAD_GPIO_0__SRTC_ALARM_DEB 1073 | ||
1106 | MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 1074 | ||
1107 | MX53_PAD_GPIO_0__CSU_TD 1075 | ||
1108 | MX53_PAD_GPIO_1__ESAI1_SCKR 1076 | ||
1109 | MX53_PAD_GPIO_1__GPIO1_1 1077 | ||
1110 | MX53_PAD_GPIO_1__KPP_ROW_5 1078 | ||
1111 | MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 1079 | ||
1112 | MX53_PAD_GPIO_1__PWM2_PWMO 1080 | ||
1113 | MX53_PAD_GPIO_1__WDOG2_WDOG_B 1081 | ||
1114 | MX53_PAD_GPIO_1__ESDHC1_CD 1082 | ||
1115 | MX53_PAD_GPIO_1__SRC_TESTER_ACK 1083 | ||
1116 | MX53_PAD_GPIO_9__ESAI1_FSR 1084 | ||
1117 | MX53_PAD_GPIO_9__GPIO1_9 1085 | ||
1118 | MX53_PAD_GPIO_9__KPP_COL_6 1086 | ||
1119 | MX53_PAD_GPIO_9__CCM_REF_EN_B 1087 | ||
1120 | MX53_PAD_GPIO_9__PWM1_PWMO 1088 | ||
1121 | MX53_PAD_GPIO_9__WDOG1_WDOG_B 1089 | ||
1122 | MX53_PAD_GPIO_9__ESDHC1_WP 1090 | ||
1123 | MX53_PAD_GPIO_9__SCC_FAIL_STATE 1091 | ||
1124 | MX53_PAD_GPIO_3__ESAI1_HCKR 1092 | ||
1125 | MX53_PAD_GPIO_3__GPIO1_3 1093 | ||
1126 | MX53_PAD_GPIO_3__I2C3_SCL 1094 | ||
1127 | MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 1095 | ||
1128 | MX53_PAD_GPIO_3__CCM_CLKO2 1096 | ||
1129 | MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 1097 | ||
1130 | MX53_PAD_GPIO_3__USBOH3_USBH1_OC 1098 | ||
1131 | MX53_PAD_GPIO_3__MLB_MLBCLK 1099 | ||
1132 | MX53_PAD_GPIO_6__ESAI1_SCKT 1100 | ||
1133 | MX53_PAD_GPIO_6__GPIO1_6 1101 | ||
1134 | MX53_PAD_GPIO_6__I2C3_SDA 1102 | ||
1135 | MX53_PAD_GPIO_6__CCM_CCM_OUT_0 1103 | ||
1136 | MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 1104 | ||
1137 | MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 1105 | ||
1138 | MX53_PAD_GPIO_6__ESDHC2_LCTL 1106 | ||
1139 | MX53_PAD_GPIO_6__MLB_MLBSIG 1107 | ||
1140 | MX53_PAD_GPIO_2__ESAI1_FST 1108 | ||
1141 | MX53_PAD_GPIO_2__GPIO1_2 1109 | ||
1142 | MX53_PAD_GPIO_2__KPP_ROW_6 1110 | ||
1143 | MX53_PAD_GPIO_2__CCM_CCM_OUT_1 1111 | ||
1144 | MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 1112 | ||
1145 | MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 1113 | ||
1146 | MX53_PAD_GPIO_2__ESDHC2_WP 1114 | ||
1147 | MX53_PAD_GPIO_2__MLB_MLBDAT 1115 | ||
1148 | MX53_PAD_GPIO_4__ESAI1_HCKT 1116 | ||
1149 | MX53_PAD_GPIO_4__GPIO1_4 1117 | ||
1150 | MX53_PAD_GPIO_4__KPP_COL_7 1118 | ||
1151 | MX53_PAD_GPIO_4__CCM_CCM_OUT_2 1119 | ||
1152 | MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1120 | ||
1153 | MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 1121 | ||
1154 | MX53_PAD_GPIO_4__ESDHC2_CD 1122 | ||
1155 | MX53_PAD_GPIO_4__SCC_SEC_STATE 1123 | ||
1156 | MX53_PAD_GPIO_5__ESAI1_TX2_RX3 1124 | ||
1157 | MX53_PAD_GPIO_5__GPIO1_5 1125 | ||
1158 | MX53_PAD_GPIO_5__KPP_ROW_7 1126 | ||
1159 | MX53_PAD_GPIO_5__CCM_CLKO 1127 | ||
1160 | MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1128 | ||
1161 | MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 1129 | ||
1162 | MX53_PAD_GPIO_5__I2C3_SCL 1130 | ||
1163 | MX53_PAD_GPIO_5__CCM_PLL1_BYP 1131 | ||
1164 | MX53_PAD_GPIO_7__ESAI1_TX4_RX1 1132 | ||
1165 | MX53_PAD_GPIO_7__GPIO1_7 1133 | ||
1166 | MX53_PAD_GPIO_7__EPIT1_EPITO 1134 | ||
1167 | MX53_PAD_GPIO_7__CAN1_TXCAN 1135 | ||
1168 | MX53_PAD_GPIO_7__UART2_TXD_MUX 1136 | ||
1169 | MX53_PAD_GPIO_7__FIRI_RXD 1137 | ||
1170 | MX53_PAD_GPIO_7__SPDIF_PLOCK 1138 | ||
1171 | MX53_PAD_GPIO_7__CCM_PLL2_BYP 1139 | ||
1172 | MX53_PAD_GPIO_8__ESAI1_TX5_RX0 1140 | ||
1173 | MX53_PAD_GPIO_8__GPIO1_8 1141 | ||
1174 | MX53_PAD_GPIO_8__EPIT2_EPITO 1142 | ||
1175 | MX53_PAD_GPIO_8__CAN1_RXCAN 1143 | ||
1176 | MX53_PAD_GPIO_8__UART2_RXD_MUX 1144 | ||
1177 | MX53_PAD_GPIO_8__FIRI_TXD 1145 | ||
1178 | MX53_PAD_GPIO_8__SPDIF_SRCLK 1146 | ||
1179 | MX53_PAD_GPIO_8__CCM_PLL3_BYP 1147 | ||
1180 | MX53_PAD_GPIO_16__ESAI1_TX3_RX2 1148 | ||
1181 | MX53_PAD_GPIO_16__GPIO7_11 1149 | ||
1182 | MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 1150 | ||
1183 | MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 1151 | ||
1184 | MX53_PAD_GPIO_16__SPDIF_IN1 1152 | ||
1185 | MX53_PAD_GPIO_16__I2C3_SDA 1153 | ||
1186 | MX53_PAD_GPIO_16__SJC_DE_B 1154 | ||
1187 | MX53_PAD_GPIO_17__ESAI1_TX0 1155 | ||
1188 | MX53_PAD_GPIO_17__GPIO7_12 1156 | ||
1189 | MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 1157 | ||
1190 | MX53_PAD_GPIO_17__GPC_PMIC_RDY 1158 | ||
1191 | MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 1159 | ||
1192 | MX53_PAD_GPIO_17__SPDIF_OUT1 1160 | ||
1193 | MX53_PAD_GPIO_17__IPU_SNOOP2 1161 | ||
1194 | MX53_PAD_GPIO_17__SJC_JTAG_ACT 1162 | ||
1195 | MX53_PAD_GPIO_18__ESAI1_TX1 1163 | ||
1196 | MX53_PAD_GPIO_18__GPIO7_13 1164 | ||
1197 | MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 1165 | ||
1198 | MX53_PAD_GPIO_18__OWIRE_LINE 1166 | ||
1199 | MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 1167 | ||
1200 | MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 1168 | ||
1201 | MX53_PAD_GPIO_18__ESDHC1_LCTL 1169 | ||
1202 | MX53_PAD_GPIO_18__SRC_SYSTEM_RST 1170 | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt deleted file mode 100644 index a4119f6422d..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt +++ /dev/null | |||
@@ -1,1630 +0,0 @@ | |||
1 | * Freescale IMX6Q IOMUX Controller | ||
2 | |||
3 | Please refer to fsl,imx-pinctrl.txt in this directory for common binding part | ||
4 | and usage. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "fsl,imx6q-iomuxc" | ||
8 | - fsl,pins: two integers array, represents a group of pins mux and config | ||
9 | setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a | ||
10 | pin working on a specific function, CONFIG is the pad setting value like | ||
11 | pull-up for this pin. Please refer to imx6q datasheet for the valid pad | ||
12 | config settings. | ||
13 | |||
14 | CONFIG bits definition: | ||
15 | PAD_CTL_HYS (1 << 16) | ||
16 | PAD_CTL_PUS_100K_DOWN (0 << 14) | ||
17 | PAD_CTL_PUS_47K_UP (1 << 14) | ||
18 | PAD_CTL_PUS_100K_UP (2 << 14) | ||
19 | PAD_CTL_PUS_22K_UP (3 << 14) | ||
20 | PAD_CTL_PUE (1 << 13) | ||
21 | PAD_CTL_PKE (1 << 12) | ||
22 | PAD_CTL_ODE (1 << 11) | ||
23 | PAD_CTL_SPEED_LOW (1 << 6) | ||
24 | PAD_CTL_SPEED_MED (2 << 6) | ||
25 | PAD_CTL_SPEED_HIGH (3 << 6) | ||
26 | PAD_CTL_DSE_DISABLE (0 << 3) | ||
27 | PAD_CTL_DSE_240ohm (1 << 3) | ||
28 | PAD_CTL_DSE_120ohm (2 << 3) | ||
29 | PAD_CTL_DSE_80ohm (3 << 3) | ||
30 | PAD_CTL_DSE_60ohm (4 << 3) | ||
31 | PAD_CTL_DSE_48ohm (5 << 3) | ||
32 | PAD_CTL_DSE_40ohm (6 << 3) | ||
33 | PAD_CTL_DSE_34ohm (7 << 3) | ||
34 | PAD_CTL_SRE_FAST (1 << 0) | ||
35 | PAD_CTL_SRE_SLOW (0 << 0) | ||
36 | |||
37 | See below for available PIN_FUNC_ID for imx6q: | ||
38 | MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0 | ||
39 | MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1 | ||
40 | MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2 | ||
41 | MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3 | ||
42 | MX6Q_PAD_SD2_DAT1__KPP_COL_7 4 | ||
43 | MX6Q_PAD_SD2_DAT1__GPIO_1_14 5 | ||
44 | MX6Q_PAD_SD2_DAT1__CCM_WAIT 6 | ||
45 | MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7 | ||
46 | MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8 | ||
47 | MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9 | ||
48 | MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10 | ||
49 | MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11 | ||
50 | MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12 | ||
51 | MX6Q_PAD_SD2_DAT2__GPIO_1_13 13 | ||
52 | MX6Q_PAD_SD2_DAT2__CCM_STOP 14 | ||
53 | MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15 | ||
54 | MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16 | ||
55 | MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17 | ||
56 | MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18 | ||
57 | MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19 | ||
58 | MX6Q_PAD_SD2_DAT0__GPIO_1_15 20 | ||
59 | MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21 | ||
60 | MX6Q_PAD_SD2_DAT0__TESTO_2 22 | ||
61 | MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23 | ||
62 | MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24 | ||
63 | MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25 | ||
64 | MX6Q_PAD_RGMII_TXC__GPIO_6_19 26 | ||
65 | MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27 | ||
66 | MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28 | ||
67 | MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29 | ||
68 | MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30 | ||
69 | MX6Q_PAD_RGMII_TD0__GPIO_6_20 31 | ||
70 | MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32 | ||
71 | MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33 | ||
72 | MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34 | ||
73 | MX6Q_PAD_RGMII_TD1__GPIO_6_21 35 | ||
74 | MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36 | ||
75 | MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37 | ||
76 | MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38 | ||
77 | MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39 | ||
78 | MX6Q_PAD_RGMII_TD2__GPIO_6_22 40 | ||
79 | MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41 | ||
80 | MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42 | ||
81 | MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43 | ||
82 | MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44 | ||
83 | MX6Q_PAD_RGMII_TD3__GPIO_6_23 45 | ||
84 | MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46 | ||
85 | MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47 | ||
86 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48 | ||
87 | MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49 | ||
88 | MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50 | ||
89 | MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51 | ||
90 | MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52 | ||
91 | MX6Q_PAD_RGMII_RD0__GPIO_6_25 53 | ||
92 | MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54 | ||
93 | MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55 | ||
94 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56 | ||
95 | MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57 | ||
96 | MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58 | ||
97 | MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59 | ||
98 | MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60 | ||
99 | MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61 | ||
100 | MX6Q_PAD_RGMII_RD1__GPIO_6_27 62 | ||
101 | MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63 | ||
102 | MX6Q_PAD_RGMII_RD1__SJC_FAIL 64 | ||
103 | MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65 | ||
104 | MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66 | ||
105 | MX6Q_PAD_RGMII_RD2__GPIO_6_28 67 | ||
106 | MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68 | ||
107 | MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69 | ||
108 | MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70 | ||
109 | MX6Q_PAD_RGMII_RD3__GPIO_6_29 71 | ||
110 | MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72 | ||
111 | MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73 | ||
112 | MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74 | ||
113 | MX6Q_PAD_RGMII_RXC__GPIO_6_30 75 | ||
114 | MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76 | ||
115 | MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77 | ||
116 | MX6Q_PAD_EIM_A25__ECSPI4_SS1 78 | ||
117 | MX6Q_PAD_EIM_A25__ECSPI2_RDY 79 | ||
118 | MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80 | ||
119 | MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81 | ||
120 | MX6Q_PAD_EIM_A25__GPIO_5_2 82 | ||
121 | MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83 | ||
122 | MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84 | ||
123 | MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85 | ||
124 | MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86 | ||
125 | MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87 | ||
126 | MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88 | ||
127 | MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89 | ||
128 | MX6Q_PAD_EIM_EB2__GPIO_2_30 90 | ||
129 | MX6Q_PAD_EIM_EB2__I2C2_SCL 91 | ||
130 | MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92 | ||
131 | MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93 | ||
132 | MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94 | ||
133 | MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95 | ||
134 | MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96 | ||
135 | MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97 | ||
136 | MX6Q_PAD_EIM_D16__GPIO_3_16 98 | ||
137 | MX6Q_PAD_EIM_D16__I2C2_SDA 99 | ||
138 | MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100 | ||
139 | MX6Q_PAD_EIM_D17__ECSPI1_MISO 101 | ||
140 | MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102 | ||
141 | MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103 | ||
142 | MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104 | ||
143 | MX6Q_PAD_EIM_D17__GPIO_3_17 105 | ||
144 | MX6Q_PAD_EIM_D17__I2C3_SCL 106 | ||
145 | MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107 | ||
146 | MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108 | ||
147 | MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109 | ||
148 | MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110 | ||
149 | MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111 | ||
150 | MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112 | ||
151 | MX6Q_PAD_EIM_D18__GPIO_3_18 113 | ||
152 | MX6Q_PAD_EIM_D18__I2C3_SDA 114 | ||
153 | MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115 | ||
154 | MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116 | ||
155 | MX6Q_PAD_EIM_D19__ECSPI1_SS1 117 | ||
156 | MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118 | ||
157 | MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119 | ||
158 | MX6Q_PAD_EIM_D19__UART1_CTS 120 | ||
159 | MX6Q_PAD_EIM_D19__GPIO_3_19 121 | ||
160 | MX6Q_PAD_EIM_D19__EPIT1_EPITO 122 | ||
161 | MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123 | ||
162 | MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124 | ||
163 | MX6Q_PAD_EIM_D20__ECSPI4_SS0 125 | ||
164 | MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126 | ||
165 | MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127 | ||
166 | MX6Q_PAD_EIM_D20__UART1_RTS 128 | ||
167 | MX6Q_PAD_EIM_D20__GPIO_3_20 129 | ||
168 | MX6Q_PAD_EIM_D20__EPIT2_EPITO 130 | ||
169 | MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131 | ||
170 | MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132 | ||
171 | MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133 | ||
172 | MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134 | ||
173 | MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135 | ||
174 | MX6Q_PAD_EIM_D21__GPIO_3_21 136 | ||
175 | MX6Q_PAD_EIM_D21__I2C1_SCL 137 | ||
176 | MX6Q_PAD_EIM_D21__SPDIF_IN1 138 | ||
177 | MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139 | ||
178 | MX6Q_PAD_EIM_D22__ECSPI4_MISO 140 | ||
179 | MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141 | ||
180 | MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142 | ||
181 | MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143 | ||
182 | MX6Q_PAD_EIM_D22__GPIO_3_22 144 | ||
183 | MX6Q_PAD_EIM_D22__SPDIF_OUT1 145 | ||
184 | MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146 | ||
185 | MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147 | ||
186 | MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148 | ||
187 | MX6Q_PAD_EIM_D23__UART3_CTS 149 | ||
188 | MX6Q_PAD_EIM_D23__UART1_DCD 150 | ||
189 | MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151 | ||
190 | MX6Q_PAD_EIM_D23__GPIO_3_23 152 | ||
191 | MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153 | ||
192 | MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154 | ||
193 | MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155 | ||
194 | MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156 | ||
195 | MX6Q_PAD_EIM_EB3__UART3_RTS 157 | ||
196 | MX6Q_PAD_EIM_EB3__UART1_RI 158 | ||
197 | MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159 | ||
198 | MX6Q_PAD_EIM_EB3__GPIO_2_31 160 | ||
199 | MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161 | ||
200 | MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162 | ||
201 | MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163 | ||
202 | MX6Q_PAD_EIM_D24__ECSPI4_SS2 164 | ||
203 | MX6Q_PAD_EIM_D24__UART3_TXD 165 | ||
204 | MX6Q_PAD_EIM_D24__ECSPI1_SS2 166 | ||
205 | MX6Q_PAD_EIM_D24__ECSPI2_SS2 167 | ||
206 | MX6Q_PAD_EIM_D24__GPIO_3_24 168 | ||
207 | MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169 | ||
208 | MX6Q_PAD_EIM_D24__UART1_DTR 170 | ||
209 | MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171 | ||
210 | MX6Q_PAD_EIM_D25__ECSPI4_SS3 172 | ||
211 | MX6Q_PAD_EIM_D25__UART3_RXD 173 | ||
212 | MX6Q_PAD_EIM_D25__ECSPI1_SS3 174 | ||
213 | MX6Q_PAD_EIM_D25__ECSPI2_SS3 175 | ||
214 | MX6Q_PAD_EIM_D25__GPIO_3_25 176 | ||
215 | MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177 | ||
216 | MX6Q_PAD_EIM_D25__UART1_DSR 178 | ||
217 | MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179 | ||
218 | MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180 | ||
219 | MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181 | ||
220 | MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182 | ||
221 | MX6Q_PAD_EIM_D26__UART2_TXD 183 | ||
222 | MX6Q_PAD_EIM_D26__GPIO_3_26 184 | ||
223 | MX6Q_PAD_EIM_D26__IPU1_SISG_2 185 | ||
224 | MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186 | ||
225 | MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187 | ||
226 | MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188 | ||
227 | MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189 | ||
228 | MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190 | ||
229 | MX6Q_PAD_EIM_D27__UART2_RXD 191 | ||
230 | MX6Q_PAD_EIM_D27__GPIO_3_27 192 | ||
231 | MX6Q_PAD_EIM_D27__IPU1_SISG_3 193 | ||
232 | MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194 | ||
233 | MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195 | ||
234 | MX6Q_PAD_EIM_D28__I2C1_SDA 196 | ||
235 | MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197 | ||
236 | MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198 | ||
237 | MX6Q_PAD_EIM_D28__UART2_CTS 199 | ||
238 | MX6Q_PAD_EIM_D28__GPIO_3_28 200 | ||
239 | MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201 | ||
240 | MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202 | ||
241 | MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203 | ||
242 | MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204 | ||
243 | MX6Q_PAD_EIM_D29__ECSPI4_SS0 205 | ||
244 | MX6Q_PAD_EIM_D29__UART2_RTS 206 | ||
245 | MX6Q_PAD_EIM_D29__GPIO_3_29 207 | ||
246 | MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208 | ||
247 | MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209 | ||
248 | MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210 | ||
249 | MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211 | ||
250 | MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212 | ||
251 | MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213 | ||
252 | MX6Q_PAD_EIM_D30__UART3_CTS 214 | ||
253 | MX6Q_PAD_EIM_D30__GPIO_3_30 215 | ||
254 | MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216 | ||
255 | MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217 | ||
256 | MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218 | ||
257 | MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219 | ||
258 | MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220 | ||
259 | MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221 | ||
260 | MX6Q_PAD_EIM_D31__UART3_RTS 222 | ||
261 | MX6Q_PAD_EIM_D31__GPIO_3_31 223 | ||
262 | MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224 | ||
263 | MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225 | ||
264 | MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226 | ||
265 | MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227 | ||
266 | MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228 | ||
267 | MX6Q_PAD_EIM_A24__IPU2_SISG_2 229 | ||
268 | MX6Q_PAD_EIM_A24__IPU1_SISG_2 230 | ||
269 | MX6Q_PAD_EIM_A24__GPIO_5_4 231 | ||
270 | MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232 | ||
271 | MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233 | ||
272 | MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234 | ||
273 | MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235 | ||
274 | MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236 | ||
275 | MX6Q_PAD_EIM_A23__IPU2_SISG_3 237 | ||
276 | MX6Q_PAD_EIM_A23__IPU1_SISG_3 238 | ||
277 | MX6Q_PAD_EIM_A23__GPIO_6_6 239 | ||
278 | MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240 | ||
279 | MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241 | ||
280 | MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242 | ||
281 | MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243 | ||
282 | MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244 | ||
283 | MX6Q_PAD_EIM_A22__GPIO_2_16 245 | ||
284 | MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246 | ||
285 | MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247 | ||
286 | MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248 | ||
287 | MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249 | ||
288 | MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250 | ||
289 | MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251 | ||
290 | MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252 | ||
291 | MX6Q_PAD_EIM_A21__GPIO_2_17 253 | ||
292 | MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254 | ||
293 | MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255 | ||
294 | MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256 | ||
295 | MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257 | ||
296 | MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258 | ||
297 | MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259 | ||
298 | MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260 | ||
299 | MX6Q_PAD_EIM_A20__GPIO_2_18 261 | ||
300 | MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262 | ||
301 | MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263 | ||
302 | MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264 | ||
303 | MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265 | ||
304 | MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266 | ||
305 | MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267 | ||
306 | MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268 | ||
307 | MX6Q_PAD_EIM_A19__GPIO_2_19 269 | ||
308 | MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270 | ||
309 | MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271 | ||
310 | MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272 | ||
311 | MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273 | ||
312 | MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274 | ||
313 | MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275 | ||
314 | MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276 | ||
315 | MX6Q_PAD_EIM_A18__GPIO_2_20 277 | ||
316 | MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278 | ||
317 | MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279 | ||
318 | MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280 | ||
319 | MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281 | ||
320 | MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282 | ||
321 | MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283 | ||
322 | MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284 | ||
323 | MX6Q_PAD_EIM_A17__GPIO_2_21 285 | ||
324 | MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286 | ||
325 | MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287 | ||
326 | MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288 | ||
327 | MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289 | ||
328 | MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290 | ||
329 | MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291 | ||
330 | MX6Q_PAD_EIM_A16__GPIO_2_22 292 | ||
331 | MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293 | ||
332 | MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294 | ||
333 | MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295 | ||
334 | MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296 | ||
335 | MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297 | ||
336 | MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298 | ||
337 | MX6Q_PAD_EIM_CS0__GPIO_2_23 299 | ||
338 | MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300 | ||
339 | MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301 | ||
340 | MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302 | ||
341 | MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303 | ||
342 | MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304 | ||
343 | MX6Q_PAD_EIM_CS1__GPIO_2_24 305 | ||
344 | MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306 | ||
345 | MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307 | ||
346 | MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308 | ||
347 | MX6Q_PAD_EIM_OE__ECSPI2_MISO 309 | ||
348 | MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310 | ||
349 | MX6Q_PAD_EIM_OE__GPIO_2_25 311 | ||
350 | MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312 | ||
351 | MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313 | ||
352 | MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314 | ||
353 | MX6Q_PAD_EIM_RW__ECSPI2_SS0 315 | ||
354 | MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316 | ||
355 | MX6Q_PAD_EIM_RW__GPIO_2_26 317 | ||
356 | MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318 | ||
357 | MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319 | ||
358 | MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320 | ||
359 | MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321 | ||
360 | MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322 | ||
361 | MX6Q_PAD_EIM_LBA__GPIO_2_27 323 | ||
362 | MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324 | ||
363 | MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325 | ||
364 | MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326 | ||
365 | MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327 | ||
366 | MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328 | ||
367 | MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329 | ||
368 | MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330 | ||
369 | MX6Q_PAD_EIM_EB0__GPIO_2_28 331 | ||
370 | MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332 | ||
371 | MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333 | ||
372 | MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334 | ||
373 | MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335 | ||
374 | MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336 | ||
375 | MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337 | ||
376 | MX6Q_PAD_EIM_EB1__GPIO_2_29 338 | ||
377 | MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339 | ||
378 | MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340 | ||
379 | MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341 | ||
380 | MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342 | ||
381 | MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343 | ||
382 | MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344 | ||
383 | MX6Q_PAD_EIM_DA0__GPIO_3_0 345 | ||
384 | MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346 | ||
385 | MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347 | ||
386 | MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348 | ||
387 | MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349 | ||
388 | MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350 | ||
389 | MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351 | ||
390 | MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352 | ||
391 | MX6Q_PAD_EIM_DA1__GPIO_3_1 353 | ||
392 | MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354 | ||
393 | MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355 | ||
394 | MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356 | ||
395 | MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357 | ||
396 | MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358 | ||
397 | MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359 | ||
398 | MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360 | ||
399 | MX6Q_PAD_EIM_DA2__GPIO_3_2 361 | ||
400 | MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362 | ||
401 | MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363 | ||
402 | MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364 | ||
403 | MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365 | ||
404 | MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366 | ||
405 | MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367 | ||
406 | MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368 | ||
407 | MX6Q_PAD_EIM_DA3__GPIO_3_3 369 | ||
408 | MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370 | ||
409 | MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371 | ||
410 | MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372 | ||
411 | MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373 | ||
412 | MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374 | ||
413 | MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375 | ||
414 | MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376 | ||
415 | MX6Q_PAD_EIM_DA4__GPIO_3_4 377 | ||
416 | MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378 | ||
417 | MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379 | ||
418 | MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380 | ||
419 | MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381 | ||
420 | MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382 | ||
421 | MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383 | ||
422 | MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384 | ||
423 | MX6Q_PAD_EIM_DA5__GPIO_3_5 385 | ||
424 | MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386 | ||
425 | MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387 | ||
426 | MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388 | ||
427 | MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389 | ||
428 | MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390 | ||
429 | MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391 | ||
430 | MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392 | ||
431 | MX6Q_PAD_EIM_DA6__GPIO_3_6 393 | ||
432 | MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394 | ||
433 | MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395 | ||
434 | MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396 | ||
435 | MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397 | ||
436 | MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398 | ||
437 | MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399 | ||
438 | MX6Q_PAD_EIM_DA7__GPIO_3_7 400 | ||
439 | MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 401 | ||
440 | MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 402 | ||
441 | MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 403 | ||
442 | MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 404 | ||
443 | MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 405 | ||
444 | MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 406 | ||
445 | MX6Q_PAD_EIM_DA8__GPIO_3_8 407 | ||
446 | MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 408 | ||
447 | MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 409 | ||
448 | MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 410 | ||
449 | MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 411 | ||
450 | MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 412 | ||
451 | MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 413 | ||
452 | MX6Q_PAD_EIM_DA9__GPIO_3_9 414 | ||
453 | MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 415 | ||
454 | MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 416 | ||
455 | MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 417 | ||
456 | MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 418 | ||
457 | MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 419 | ||
458 | MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 420 | ||
459 | MX6Q_PAD_EIM_DA10__GPIO_3_10 421 | ||
460 | MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 422 | ||
461 | MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 423 | ||
462 | MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 424 | ||
463 | MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 425 | ||
464 | MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 426 | ||
465 | MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 427 | ||
466 | MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 428 | ||
467 | MX6Q_PAD_EIM_DA11__GPIO_3_11 429 | ||
468 | MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 430 | ||
469 | MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 431 | ||
470 | MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 432 | ||
471 | MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 433 | ||
472 | MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 434 | ||
473 | MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 435 | ||
474 | MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 436 | ||
475 | MX6Q_PAD_EIM_DA12__GPIO_3_12 437 | ||
476 | MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 438 | ||
477 | MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 439 | ||
478 | MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 440 | ||
479 | MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 441 | ||
480 | MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK 442 | ||
481 | MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 443 | ||
482 | MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 444 | ||
483 | MX6Q_PAD_EIM_DA13__GPIO_3_13 445 | ||
484 | MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 446 | ||
485 | MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 447 | ||
486 | MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 448 | ||
487 | MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 449 | ||
488 | MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK 450 | ||
489 | MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 451 | ||
490 | MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 452 | ||
491 | MX6Q_PAD_EIM_DA14__GPIO_3_14 453 | ||
492 | MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 454 | ||
493 | MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 455 | ||
494 | MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 456 | ||
495 | MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 457 | ||
496 | MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 458 | ||
497 | MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 459 | ||
498 | MX6Q_PAD_EIM_DA15__GPIO_3_15 460 | ||
499 | MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 461 | ||
500 | MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 462 | ||
501 | MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT 463 | ||
502 | MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B 464 | ||
503 | MX6Q_PAD_EIM_WAIT__GPIO_5_0 465 | ||
504 | MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 466 | ||
505 | MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 467 | ||
506 | MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK 468 | ||
507 | MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 469 | ||
508 | MX6Q_PAD_EIM_BCLK__GPIO_6_31 470 | ||
509 | MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 471 | ||
510 | MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK 472 | ||
511 | MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK 473 | ||
512 | MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 474 | ||
513 | MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 475 | ||
514 | MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 476 | ||
515 | MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 477 | ||
516 | MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 478 | ||
517 | MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 479 | ||
518 | MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 480 | ||
519 | MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 481 | ||
520 | MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 482 | ||
521 | MX6Q_PAD_DI0_PIN15__GPIO_4_17 483 | ||
522 | MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 484 | ||
523 | MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 485 | ||
524 | MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 486 | ||
525 | MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 487 | ||
526 | MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 488 | ||
527 | MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 489 | ||
528 | MX6Q_PAD_DI0_PIN2__GPIO_4_18 490 | ||
529 | MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 491 | ||
530 | MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 492 | ||
531 | MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 493 | ||
532 | MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 494 | ||
533 | MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 495 | ||
534 | MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 496 | ||
535 | MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 497 | ||
536 | MX6Q_PAD_DI0_PIN3__GPIO_4_19 498 | ||
537 | MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 499 | ||
538 | MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 500 | ||
539 | MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 501 | ||
540 | MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 502 | ||
541 | MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 503 | ||
542 | MX6Q_PAD_DI0_PIN4__USDHC1_WP 504 | ||
543 | MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 505 | ||
544 | MX6Q_PAD_DI0_PIN4__GPIO_4_20 506 | ||
545 | MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 507 | ||
546 | MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 508 | ||
547 | MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 509 | ||
548 | MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 510 | ||
549 | MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 511 | ||
550 | MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 512 | ||
551 | MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN 513 | ||
552 | MX6Q_PAD_DISP0_DAT0__GPIO_4_21 514 | ||
553 | MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 515 | ||
554 | MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 516 | ||
555 | MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 517 | ||
556 | MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 518 | ||
557 | MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 519 | ||
558 | MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL 520 | ||
559 | MX6Q_PAD_DISP0_DAT1__GPIO_4_22 521 | ||
560 | MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 522 | ||
561 | MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 523 | ||
562 | MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 524 | ||
563 | MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 525 | ||
564 | MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 526 | ||
565 | MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 527 | ||
566 | MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 528 | ||
567 | MX6Q_PAD_DISP0_DAT2__GPIO_4_23 529 | ||
568 | MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 530 | ||
569 | MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 531 | ||
570 | MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 532 | ||
571 | MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 533 | ||
572 | MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 534 | ||
573 | MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 535 | ||
574 | MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR 536 | ||
575 | MX6Q_PAD_DISP0_DAT3__GPIO_4_24 537 | ||
576 | MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 538 | ||
577 | MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 539 | ||
578 | MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 540 | ||
579 | MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 541 | ||
580 | MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 542 | ||
581 | MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 543 | ||
582 | MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 544 | ||
583 | MX6Q_PAD_DISP0_DAT4__GPIO_4_25 545 | ||
584 | MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 546 | ||
585 | MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 547 | ||
586 | MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 548 | ||
587 | MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 549 | ||
588 | MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 550 | ||
589 | MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS 551 | ||
590 | MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS 552 | ||
591 | MX6Q_PAD_DISP0_DAT5__GPIO_4_26 553 | ||
592 | MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 554 | ||
593 | MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 555 | ||
594 | MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 556 | ||
595 | MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 557 | ||
596 | MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 558 | ||
597 | MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC 559 | ||
598 | MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT 560 | ||
599 | MX6Q_PAD_DISP0_DAT6__GPIO_4_27 561 | ||
600 | MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 562 | ||
601 | MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 563 | ||
602 | MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 564 | ||
603 | MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 565 | ||
604 | MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 566 | ||
605 | MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 567 | ||
606 | MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 568 | ||
607 | MX6Q_PAD_DISP0_DAT7__GPIO_4_28 569 | ||
608 | MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 570 | ||
609 | MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 571 | ||
610 | MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 572 | ||
611 | MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 573 | ||
612 | MX6Q_PAD_DISP0_DAT8__PWM1_PWMO 574 | ||
613 | MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B 575 | ||
614 | MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 576 | ||
615 | MX6Q_PAD_DISP0_DAT8__GPIO_4_29 577 | ||
616 | MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 578 | ||
617 | MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 579 | ||
618 | MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 580 | ||
619 | MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 581 | ||
620 | MX6Q_PAD_DISP0_DAT9__PWM2_PWMO 582 | ||
621 | MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B 583 | ||
622 | MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 584 | ||
623 | MX6Q_PAD_DISP0_DAT9__GPIO_4_30 585 | ||
624 | MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 586 | ||
625 | MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 587 | ||
626 | MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 588 | ||
627 | MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 589 | ||
628 | MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 590 | ||
629 | MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 591 | ||
630 | MX6Q_PAD_DISP0_DAT10__GPIO_4_31 592 | ||
631 | MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 593 | ||
632 | MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 594 | ||
633 | MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 595 | ||
634 | MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 596 | ||
635 | MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 597 | ||
636 | MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 598 | ||
637 | MX6Q_PAD_DISP0_DAT11__GPIO_5_5 599 | ||
638 | MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 600 | ||
639 | MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 601 | ||
640 | MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 602 | ||
641 | MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 603 | ||
642 | MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED 604 | ||
643 | MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 605 | ||
644 | MX6Q_PAD_DISP0_DAT12__GPIO_5_6 606 | ||
645 | MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 607 | ||
646 | MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 608 | ||
647 | MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 609 | ||
648 | MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 610 | ||
649 | MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 611 | ||
650 | MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 612 | ||
651 | MX6Q_PAD_DISP0_DAT13__GPIO_5_7 613 | ||
652 | MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 614 | ||
653 | MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 615 | ||
654 | MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 616 | ||
655 | MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 617 | ||
656 | MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 618 | ||
657 | MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 619 | ||
658 | MX6Q_PAD_DISP0_DAT14__GPIO_5_8 620 | ||
659 | MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 621 | ||
660 | MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 622 | ||
661 | MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 623 | ||
662 | MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 624 | ||
663 | MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 625 | ||
664 | MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 626 | ||
665 | MX6Q_PAD_DISP0_DAT15__GPIO_5_9 627 | ||
666 | MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 628 | ||
667 | MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 629 | ||
668 | MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 630 | ||
669 | MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 631 | ||
670 | MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 632 | ||
671 | MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 633 | ||
672 | MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 634 | ||
673 | MX6Q_PAD_DISP0_DAT16__GPIO_5_10 635 | ||
674 | MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 636 | ||
675 | MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 637 | ||
676 | MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 638 | ||
677 | MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 639 | ||
678 | MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 640 | ||
679 | MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 641 | ||
680 | MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 642 | ||
681 | MX6Q_PAD_DISP0_DAT17__GPIO_5_11 643 | ||
682 | MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 644 | ||
683 | MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 645 | ||
684 | MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 646 | ||
685 | MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 647 | ||
686 | MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 648 | ||
687 | MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 649 | ||
688 | MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 650 | ||
689 | MX6Q_PAD_DISP0_DAT18__GPIO_5_12 651 | ||
690 | MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 652 | ||
691 | MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 653 | ||
692 | MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 654 | ||
693 | MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 655 | ||
694 | MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 656 | ||
695 | MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 657 | ||
696 | MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 658 | ||
697 | MX6Q_PAD_DISP0_DAT19__GPIO_5_13 659 | ||
698 | MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 660 | ||
699 | MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 661 | ||
700 | MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 662 | ||
701 | MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 663 | ||
702 | MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 664 | ||
703 | MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 665 | ||
704 | MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 666 | ||
705 | MX6Q_PAD_DISP0_DAT20__GPIO_5_14 667 | ||
706 | MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 668 | ||
707 | MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 669 | ||
708 | MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 670 | ||
709 | MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 671 | ||
710 | MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 672 | ||
711 | MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 673 | ||
712 | MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 674 | ||
713 | MX6Q_PAD_DISP0_DAT21__GPIO_5_15 675 | ||
714 | MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 676 | ||
715 | MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 677 | ||
716 | MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 678 | ||
717 | MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 679 | ||
718 | MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 680 | ||
719 | MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 681 | ||
720 | MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 682 | ||
721 | MX6Q_PAD_DISP0_DAT22__GPIO_5_16 683 | ||
722 | MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 684 | ||
723 | MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 685 | ||
724 | MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 686 | ||
725 | MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 687 | ||
726 | MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 688 | ||
727 | MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 689 | ||
728 | MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 690 | ||
729 | MX6Q_PAD_DISP0_DAT23__GPIO_5_17 691 | ||
730 | MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 692 | ||
731 | MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 693 | ||
732 | MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED 694 | ||
733 | MX6Q_PAD_ENET_MDIO__ENET_MDIO 695 | ||
734 | MX6Q_PAD_ENET_MDIO__ESAI1_SCKR 696 | ||
735 | MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 697 | ||
736 | MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT 698 | ||
737 | MX6Q_PAD_ENET_MDIO__GPIO_1_22 699 | ||
738 | MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK 700 | ||
739 | MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED 701 | ||
740 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 702 | ||
741 | MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR 703 | ||
742 | MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 704 | ||
743 | MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 705 | ||
744 | MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK 706 | ||
745 | MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH 707 | ||
746 | MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 708 | ||
747 | MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR 709 | ||
748 | MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 710 | ||
749 | MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT 711 | ||
750 | MX6Q_PAD_ENET_RX_ER__GPIO_1_24 712 | ||
751 | MX6Q_PAD_ENET_RX_ER__PHY_TDI 713 | ||
752 | MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD 714 | ||
753 | MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED 715 | ||
754 | MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 716 | ||
755 | MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT 717 | ||
756 | MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK 718 | ||
757 | MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 719 | ||
758 | MX6Q_PAD_ENET_CRS_DV__PHY_TDO 720 | ||
759 | MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD 721 | ||
760 | MX6Q_PAD_ENET_RXD1__MLB_MLBSIG 722 | ||
761 | MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 723 | ||
762 | MX6Q_PAD_ENET_RXD1__ESAI1_FST 724 | ||
763 | MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT 725 | ||
764 | MX6Q_PAD_ENET_RXD1__GPIO_1_26 726 | ||
765 | MX6Q_PAD_ENET_RXD1__PHY_TCK 727 | ||
766 | MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON 728 | ||
767 | MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT 729 | ||
768 | MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 730 | ||
769 | MX6Q_PAD_ENET_RXD0__ESAI1_HCKT 731 | ||
770 | MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 732 | ||
771 | MX6Q_PAD_ENET_RXD0__GPIO_1_27 733 | ||
772 | MX6Q_PAD_ENET_RXD0__PHY_TMS 734 | ||
773 | MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV 735 | ||
774 | MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED 736 | ||
775 | MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 737 | ||
776 | MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 738 | ||
777 | MX6Q_PAD_ENET_TX_EN__GPIO_1_28 739 | ||
778 | MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI 740 | ||
779 | MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH 741 | ||
780 | MX6Q_PAD_ENET_TXD1__MLB_MLBCLK 742 | ||
781 | MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 743 | ||
782 | MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 744 | ||
783 | MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 745 | ||
784 | MX6Q_PAD_ENET_TXD1__GPIO_1_29 746 | ||
785 | MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO 747 | ||
786 | MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD 748 | ||
787 | MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED 749 | ||
788 | MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 750 | ||
789 | MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 751 | ||
790 | MX6Q_PAD_ENET_TXD0__GPIO_1_30 752 | ||
791 | MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK 753 | ||
792 | MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD 754 | ||
793 | MX6Q_PAD_ENET_MDC__MLB_MLBDAT 755 | ||
794 | MX6Q_PAD_ENET_MDC__ENET_MDC 756 | ||
795 | MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 757 | ||
796 | MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 758 | ||
797 | MX6Q_PAD_ENET_MDC__GPIO_1_31 759 | ||
798 | MX6Q_PAD_ENET_MDC__SATA_PHY_TMS 760 | ||
799 | MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON 761 | ||
800 | MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 762 | ||
801 | MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 763 | ||
802 | MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 764 | ||
803 | MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 765 | ||
804 | MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 766 | ||
805 | MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 767 | ||
806 | MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 768 | ||
807 | MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 769 | ||
808 | MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 770 | ||
809 | MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 771 | ||
810 | MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 772 | ||
811 | MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 773 | ||
812 | MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 774 | ||
813 | MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 775 | ||
814 | MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 776 | ||
815 | MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 777 | ||
816 | MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 778 | ||
817 | MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 779 | ||
818 | MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 780 | ||
819 | MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 781 | ||
820 | MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 782 | ||
821 | MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 783 | ||
822 | MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 784 | ||
823 | MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 785 | ||
824 | MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 786 | ||
825 | MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 787 | ||
826 | MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 788 | ||
827 | MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 789 | ||
828 | MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 790 | ||
829 | MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 791 | ||
830 | MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 792 | ||
831 | MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 793 | ||
832 | MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 794 | ||
833 | MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 795 | ||
834 | MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 796 | ||
835 | MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 797 | ||
836 | MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 798 | ||
837 | MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 799 | ||
838 | MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 800 | ||
839 | MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 801 | ||
840 | MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 802 | ||
841 | MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 803 | ||
842 | MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 804 | ||
843 | MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 805 | ||
844 | MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 806 | ||
845 | MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 807 | ||
846 | MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 808 | ||
847 | MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 809 | ||
848 | MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 810 | ||
849 | MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 811 | ||
850 | MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 812 | ||
851 | MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 813 | ||
852 | MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 814 | ||
853 | MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 815 | ||
854 | MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 816 | ||
855 | MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 817 | ||
856 | MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS 818 | ||
857 | MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 819 | ||
858 | MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 820 | ||
859 | MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS 821 | ||
860 | MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET 822 | ||
861 | MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 823 | ||
862 | MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 824 | ||
863 | MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 825 | ||
864 | MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 826 | ||
865 | MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 827 | ||
866 | MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 828 | ||
867 | MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 829 | ||
868 | MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 830 | ||
869 | MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 831 | ||
870 | MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE 832 | ||
871 | MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 833 | ||
872 | MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 834 | ||
873 | MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 835 | ||
874 | MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 836 | ||
875 | MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 837 | ||
876 | MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 838 | ||
877 | MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 839 | ||
878 | MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 840 | ||
879 | MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 841 | ||
880 | MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 842 | ||
881 | MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 843 | ||
882 | MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 844 | ||
883 | MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 845 | ||
884 | MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 846 | ||
885 | MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 847 | ||
886 | MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 848 | ||
887 | MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 849 | ||
888 | MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 850 | ||
889 | MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 851 | ||
890 | MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 852 | ||
891 | MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 853 | ||
892 | MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 854 | ||
893 | MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 855 | ||
894 | MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 856 | ||
895 | MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 857 | ||
896 | MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 858 | ||
897 | MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 859 | ||
898 | MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 860 | ||
899 | MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 861 | ||
900 | MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 862 | ||
901 | MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 863 | ||
902 | MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 864 | ||
903 | MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 865 | ||
904 | MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 866 | ||
905 | MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 867 | ||
906 | MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 868 | ||
907 | MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 869 | ||
908 | MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 870 | ||
909 | MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 871 | ||
910 | MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 872 | ||
911 | MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 873 | ||
912 | MX6Q_PAD_KEY_COL0__ENET_RDATA_3 874 | ||
913 | MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC 875 | ||
914 | MX6Q_PAD_KEY_COL0__KPP_COL_0 876 | ||
915 | MX6Q_PAD_KEY_COL0__UART4_TXD 877 | ||
916 | MX6Q_PAD_KEY_COL0__GPIO_4_6 878 | ||
917 | MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT 879 | ||
918 | MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST 880 | ||
919 | MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 881 | ||
920 | MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 882 | ||
921 | MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 883 | ||
922 | MX6Q_PAD_KEY_ROW0__KPP_ROW_0 884 | ||
923 | MX6Q_PAD_KEY_ROW0__UART4_RXD 885 | ||
924 | MX6Q_PAD_KEY_ROW0__GPIO_4_7 886 | ||
925 | MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT 887 | ||
926 | MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 888 | ||
927 | MX6Q_PAD_KEY_COL1__ECSPI1_MISO 889 | ||
928 | MX6Q_PAD_KEY_COL1__ENET_MDIO 890 | ||
929 | MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 891 | ||
930 | MX6Q_PAD_KEY_COL1__KPP_COL_1 892 | ||
931 | MX6Q_PAD_KEY_COL1__UART5_TXD 893 | ||
932 | MX6Q_PAD_KEY_COL1__GPIO_4_8 894 | ||
933 | MX6Q_PAD_KEY_COL1__USDHC1_VSELECT 895 | ||
934 | MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 896 | ||
935 | MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 897 | ||
936 | MX6Q_PAD_KEY_ROW1__ENET_COL 898 | ||
937 | MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 899 | ||
938 | MX6Q_PAD_KEY_ROW1__KPP_ROW_1 900 | ||
939 | MX6Q_PAD_KEY_ROW1__UART5_RXD 901 | ||
940 | MX6Q_PAD_KEY_ROW1__GPIO_4_9 902 | ||
941 | MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT 903 | ||
942 | MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 904 | ||
943 | MX6Q_PAD_KEY_COL2__ECSPI1_SS1 905 | ||
944 | MX6Q_PAD_KEY_COL2__ENET_RDATA_2 906 | ||
945 | MX6Q_PAD_KEY_COL2__CAN1_TXCAN 907 | ||
946 | MX6Q_PAD_KEY_COL2__KPP_COL_2 908 | ||
947 | MX6Q_PAD_KEY_COL2__ENET_MDC 909 | ||
948 | MX6Q_PAD_KEY_COL2__GPIO_4_10 910 | ||
949 | MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP 911 | ||
950 | MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 912 | ||
951 | MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 913 | ||
952 | MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 914 | ||
953 | MX6Q_PAD_KEY_ROW2__CAN1_RXCAN 915 | ||
954 | MX6Q_PAD_KEY_ROW2__KPP_ROW_2 916 | ||
955 | MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT 917 | ||
956 | MX6Q_PAD_KEY_ROW2__GPIO_4_11 918 | ||
957 | MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 919 | ||
958 | MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 920 | ||
959 | MX6Q_PAD_KEY_COL3__ECSPI1_SS3 921 | ||
960 | MX6Q_PAD_KEY_COL3__ENET_CRS 922 | ||
961 | MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 923 | ||
962 | MX6Q_PAD_KEY_COL3__KPP_COL_3 924 | ||
963 | MX6Q_PAD_KEY_COL3__I2C2_SCL 925 | ||
964 | MX6Q_PAD_KEY_COL3__GPIO_4_12 926 | ||
965 | MX6Q_PAD_KEY_COL3__SPDIF_IN1 927 | ||
966 | MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 928 | ||
967 | MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT 929 | ||
968 | MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK 930 | ||
969 | MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 931 | ||
970 | MX6Q_PAD_KEY_ROW3__KPP_ROW_3 932 | ||
971 | MX6Q_PAD_KEY_ROW3__I2C2_SDA 933 | ||
972 | MX6Q_PAD_KEY_ROW3__GPIO_4_13 934 | ||
973 | MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT 935 | ||
974 | MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 936 | ||
975 | MX6Q_PAD_KEY_COL4__CAN2_TXCAN 937 | ||
976 | MX6Q_PAD_KEY_COL4__IPU1_SISG_4 938 | ||
977 | MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC 939 | ||
978 | MX6Q_PAD_KEY_COL4__KPP_COL_4 940 | ||
979 | MX6Q_PAD_KEY_COL4__UART5_RTS 941 | ||
980 | MX6Q_PAD_KEY_COL4__GPIO_4_14 942 | ||
981 | MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 943 | ||
982 | MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944 | ||
983 | MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945 | ||
984 | MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946 | ||
985 | MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947 | ||
986 | MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948 | ||
987 | MX6Q_PAD_KEY_ROW4__UART5_CTS 949 | ||
988 | MX6Q_PAD_KEY_ROW4__GPIO_4_15 950 | ||
989 | MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951 | ||
990 | MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952 | ||
991 | MX6Q_PAD_GPIO_0__CCM_CLKO 953 | ||
992 | MX6Q_PAD_GPIO_0__KPP_COL_5 954 | ||
993 | MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955 | ||
994 | MX6Q_PAD_GPIO_0__EPIT1_EPITO 956 | ||
995 | MX6Q_PAD_GPIO_0__GPIO_1_0 957 | ||
996 | MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958 | ||
997 | MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959 | ||
998 | MX6Q_PAD_GPIO_1__ESAI1_SCKR 960 | ||
999 | MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961 | ||
1000 | MX6Q_PAD_GPIO_1__KPP_ROW_5 962 | ||
1001 | MX6Q_PAD_GPIO_1__PWM2_PWMO 963 | ||
1002 | MX6Q_PAD_GPIO_1__GPIO_1_1 964 | ||
1003 | MX6Q_PAD_GPIO_1__USDHC1_CD 965 | ||
1004 | MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966 | ||
1005 | MX6Q_PAD_GPIO_9__ESAI1_FSR 967 | ||
1006 | MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968 | ||
1007 | MX6Q_PAD_GPIO_9__KPP_COL_6 969 | ||
1008 | MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970 | ||
1009 | MX6Q_PAD_GPIO_9__PWM1_PWMO 971 | ||
1010 | MX6Q_PAD_GPIO_9__GPIO_1_9 972 | ||
1011 | MX6Q_PAD_GPIO_9__USDHC1_WP 973 | ||
1012 | MX6Q_PAD_GPIO_9__SRC_EARLY_RST 974 | ||
1013 | MX6Q_PAD_GPIO_3__ESAI1_HCKR 975 | ||
1014 | MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 976 | ||
1015 | MX6Q_PAD_GPIO_3__I2C3_SCL 977 | ||
1016 | MX6Q_PAD_GPIO_3__ANATOP_24M_OUT 978 | ||
1017 | MX6Q_PAD_GPIO_3__CCM_CLKO2 979 | ||
1018 | MX6Q_PAD_GPIO_3__GPIO_1_3 980 | ||
1019 | MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC 981 | ||
1020 | MX6Q_PAD_GPIO_3__MLB_MLBCLK 982 | ||
1021 | MX6Q_PAD_GPIO_6__ESAI1_SCKT 983 | ||
1022 | MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 984 | ||
1023 | MX6Q_PAD_GPIO_6__I2C3_SDA 985 | ||
1024 | MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 986 | ||
1025 | MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB 987 | ||
1026 | MX6Q_PAD_GPIO_6__GPIO_1_6 988 | ||
1027 | MX6Q_PAD_GPIO_6__USDHC2_LCTL 989 | ||
1028 | MX6Q_PAD_GPIO_6__MLB_MLBSIG 990 | ||
1029 | MX6Q_PAD_GPIO_2__ESAI1_FST 991 | ||
1030 | MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 992 | ||
1031 | MX6Q_PAD_GPIO_2__KPP_ROW_6 993 | ||
1032 | MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 994 | ||
1033 | MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 995 | ||
1034 | MX6Q_PAD_GPIO_2__GPIO_1_2 996 | ||
1035 | MX6Q_PAD_GPIO_2__USDHC2_WP 997 | ||
1036 | MX6Q_PAD_GPIO_2__MLB_MLBDAT 998 | ||
1037 | MX6Q_PAD_GPIO_4__ESAI1_HCKT 999 | ||
1038 | MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 1000 | ||
1039 | MX6Q_PAD_GPIO_4__KPP_COL_7 1001 | ||
1040 | MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 1002 | ||
1041 | MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 1003 | ||
1042 | MX6Q_PAD_GPIO_4__GPIO_1_4 1004 | ||
1043 | MX6Q_PAD_GPIO_4__USDHC2_CD 1005 | ||
1044 | MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA 1006 | ||
1045 | MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 1007 | ||
1046 | MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 1008 | ||
1047 | MX6Q_PAD_GPIO_5__KPP_ROW_7 1009 | ||
1048 | MX6Q_PAD_GPIO_5__CCM_CLKO 1010 | ||
1049 | MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 1011 | ||
1050 | MX6Q_PAD_GPIO_5__GPIO_1_5 1012 | ||
1051 | MX6Q_PAD_GPIO_5__I2C3_SCL 1013 | ||
1052 | MX6Q_PAD_GPIO_5__CHEETAH_EVENTI 1014 | ||
1053 | MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 1015 | ||
1054 | MX6Q_PAD_GPIO_7__ECSPI5_RDY 1016 | ||
1055 | MX6Q_PAD_GPIO_7__EPIT1_EPITO 1017 | ||
1056 | MX6Q_PAD_GPIO_7__CAN1_TXCAN 1018 | ||
1057 | MX6Q_PAD_GPIO_7__UART2_TXD 1019 | ||
1058 | MX6Q_PAD_GPIO_7__GPIO_1_7 1020 | ||
1059 | MX6Q_PAD_GPIO_7__SPDIF_PLOCK 1021 | ||
1060 | MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE 1022 | ||
1061 | MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 1023 | ||
1062 | MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT 1024 | ||
1063 | MX6Q_PAD_GPIO_8__EPIT2_EPITO 1025 | ||
1064 | MX6Q_PAD_GPIO_8__CAN1_RXCAN 1026 | ||
1065 | MX6Q_PAD_GPIO_8__UART2_RXD 1027 | ||
1066 | MX6Q_PAD_GPIO_8__GPIO_1_8 1028 | ||
1067 | MX6Q_PAD_GPIO_8__SPDIF_SRCLK 1029 | ||
1068 | MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK 1030 | ||
1069 | MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 1031 | ||
1070 | MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 1032 | ||
1071 | MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT 1033 | ||
1072 | MX6Q_PAD_GPIO_16__USDHC1_LCTL 1034 | ||
1073 | MX6Q_PAD_GPIO_16__SPDIF_IN1 1035 | ||
1074 | MX6Q_PAD_GPIO_16__GPIO_7_11 1036 | ||
1075 | MX6Q_PAD_GPIO_16__I2C3_SDA 1037 | ||
1076 | MX6Q_PAD_GPIO_16__SJC_DE_B 1038 | ||
1077 | MX6Q_PAD_GPIO_17__ESAI1_TX0 1039 | ||
1078 | MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 1040 | ||
1079 | MX6Q_PAD_GPIO_17__CCM_PMIC_RDY 1041 | ||
1080 | MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 1042 | ||
1081 | MX6Q_PAD_GPIO_17__SPDIF_OUT1 1043 | ||
1082 | MX6Q_PAD_GPIO_17__GPIO_7_12 1044 | ||
1083 | MX6Q_PAD_GPIO_17__SJC_JTAG_ACT 1045 | ||
1084 | MX6Q_PAD_GPIO_18__ESAI1_TX1 1046 | ||
1085 | MX6Q_PAD_GPIO_18__ENET_RX_CLK 1047 | ||
1086 | MX6Q_PAD_GPIO_18__USDHC3_VSELECT 1048 | ||
1087 | MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 1049 | ||
1088 | MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK 1050 | ||
1089 | MX6Q_PAD_GPIO_18__GPIO_7_13 1051 | ||
1090 | MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 1052 | ||
1091 | MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST 1053 | ||
1092 | MX6Q_PAD_GPIO_19__KPP_COL_5 1054 | ||
1093 | MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 1055 | ||
1094 | MX6Q_PAD_GPIO_19__SPDIF_OUT1 1056 | ||
1095 | MX6Q_PAD_GPIO_19__CCM_CLKO 1057 | ||
1096 | MX6Q_PAD_GPIO_19__ECSPI1_RDY 1058 | ||
1097 | MX6Q_PAD_GPIO_19__GPIO_4_5 1059 | ||
1098 | MX6Q_PAD_GPIO_19__ENET_TX_ER 1060 | ||
1099 | MX6Q_PAD_GPIO_19__SRC_INT_BOOT 1061 | ||
1100 | MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 1062 | ||
1101 | MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 1063 | ||
1102 | MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 1064 | ||
1103 | MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 1065 | ||
1104 | MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 1066 | ||
1105 | MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO 1067 | ||
1106 | MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 1068 | ||
1107 | MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 1069 | ||
1108 | MX6Q_PAD_CSI0_MCLK__CCM_CLKO 1070 | ||
1109 | MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 1071 | ||
1110 | MX6Q_PAD_CSI0_MCLK__GPIO_5_19 1072 | ||
1111 | MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 1073 | ||
1112 | MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL 1074 | ||
1113 | MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN 1075 | ||
1114 | MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 1076 | ||
1115 | MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 1077 | ||
1116 | MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 1078 | ||
1117 | MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 1079 | ||
1118 | MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 1080 | ||
1119 | MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK 1081 | ||
1120 | MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 1082 | ||
1121 | MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 1083 | ||
1122 | MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 1084 | ||
1123 | MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 1085 | ||
1124 | MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 1086 | ||
1125 | MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 1087 | ||
1126 | MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 1088 | ||
1127 | MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 1089 | ||
1128 | MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 1090 | ||
1129 | MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 1091 | ||
1130 | MX6Q_PAD_CSI0_DAT4__KPP_COL_5 1092 | ||
1131 | MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 1093 | ||
1132 | MX6Q_PAD_CSI0_DAT4__GPIO_5_22 1094 | ||
1133 | MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 1095 | ||
1134 | MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 1096 | ||
1135 | MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 1097 | ||
1136 | MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 1098 | ||
1137 | MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 1099 | ||
1138 | MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 1100 | ||
1139 | MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 1101 | ||
1140 | MX6Q_PAD_CSI0_DAT5__GPIO_5_23 1102 | ||
1141 | MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 1103 | ||
1142 | MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 1104 | ||
1143 | MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 1105 | ||
1144 | MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 1106 | ||
1145 | MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 1107 | ||
1146 | MX6Q_PAD_CSI0_DAT6__KPP_COL_6 1108 | ||
1147 | MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 1109 | ||
1148 | MX6Q_PAD_CSI0_DAT6__GPIO_5_24 1110 | ||
1149 | MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 1111 | ||
1150 | MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 1112 | ||
1151 | MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 1113 | ||
1152 | MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 1114 | ||
1153 | MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 1115 | ||
1154 | MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 1116 | ||
1155 | MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 1117 | ||
1156 | MX6Q_PAD_CSI0_DAT7__GPIO_5_25 1118 | ||
1157 | MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 1119 | ||
1158 | MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 1120 | ||
1159 | MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 1121 | ||
1160 | MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 1122 | ||
1161 | MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 1123 | ||
1162 | MX6Q_PAD_CSI0_DAT8__KPP_COL_7 1124 | ||
1163 | MX6Q_PAD_CSI0_DAT8__I2C1_SDA 1125 | ||
1164 | MX6Q_PAD_CSI0_DAT8__GPIO_5_26 1126 | ||
1165 | MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 1127 | ||
1166 | MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 1128 | ||
1167 | MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 1129 | ||
1168 | MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 1130 | ||
1169 | MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 1131 | ||
1170 | MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 1132 | ||
1171 | MX6Q_PAD_CSI0_DAT9__I2C1_SCL 1133 | ||
1172 | MX6Q_PAD_CSI0_DAT9__GPIO_5_27 1134 | ||
1173 | MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 1135 | ||
1174 | MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 1136 | ||
1175 | MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 1137 | ||
1176 | MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 1138 | ||
1177 | MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 1139 | ||
1178 | MX6Q_PAD_CSI0_DAT10__UART1_TXD 1140 | ||
1179 | MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 1141 | ||
1180 | MX6Q_PAD_CSI0_DAT10__GPIO_5_28 1142 | ||
1181 | MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 1143 | ||
1182 | MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 1144 | ||
1183 | MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 1145 | ||
1184 | MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 1146 | ||
1185 | MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 1147 | ||
1186 | MX6Q_PAD_CSI0_DAT11__UART1_RXD 1148 | ||
1187 | MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 1149 | ||
1188 | MX6Q_PAD_CSI0_DAT11__GPIO_5_29 1150 | ||
1189 | MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 1151 | ||
1190 | MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 1152 | ||
1191 | MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 1153 | ||
1192 | MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 1154 | ||
1193 | MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 1155 | ||
1194 | MX6Q_PAD_CSI0_DAT12__UART4_TXD 1156 | ||
1195 | MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 1157 | ||
1196 | MX6Q_PAD_CSI0_DAT12__GPIO_5_30 1158 | ||
1197 | MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 1159 | ||
1198 | MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 1160 | ||
1199 | MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 1161 | ||
1200 | MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 1162 | ||
1201 | MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 1163 | ||
1202 | MX6Q_PAD_CSI0_DAT13__UART4_RXD 1164 | ||
1203 | MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 1165 | ||
1204 | MX6Q_PAD_CSI0_DAT13__GPIO_5_31 1166 | ||
1205 | MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 1167 | ||
1206 | MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 1168 | ||
1207 | MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 1169 | ||
1208 | MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 1170 | ||
1209 | MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 1171 | ||
1210 | MX6Q_PAD_CSI0_DAT14__UART5_TXD 1172 | ||
1211 | MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 1173 | ||
1212 | MX6Q_PAD_CSI0_DAT14__GPIO_6_0 1174 | ||
1213 | MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 1175 | ||
1214 | MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 1176 | ||
1215 | MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 1177 | ||
1216 | MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 1178 | ||
1217 | MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 1179 | ||
1218 | MX6Q_PAD_CSI0_DAT15__UART5_RXD 1180 | ||
1219 | MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 1181 | ||
1220 | MX6Q_PAD_CSI0_DAT15__GPIO_6_1 1182 | ||
1221 | MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 1183 | ||
1222 | MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 1184 | ||
1223 | MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 1185 | ||
1224 | MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 1186 | ||
1225 | MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 1187 | ||
1226 | MX6Q_PAD_CSI0_DAT16__UART4_RTS 1188 | ||
1227 | MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 1189 | ||
1228 | MX6Q_PAD_CSI0_DAT16__GPIO_6_2 1190 | ||
1229 | MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 1191 | ||
1230 | MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 1192 | ||
1231 | MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 1193 | ||
1232 | MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 1194 | ||
1233 | MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 1195 | ||
1234 | MX6Q_PAD_CSI0_DAT17__UART4_CTS 1196 | ||
1235 | MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 1197 | ||
1236 | MX6Q_PAD_CSI0_DAT17__GPIO_6_3 1198 | ||
1237 | MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 1199 | ||
1238 | MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 1200 | ||
1239 | MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 1201 | ||
1240 | MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 1202 | ||
1241 | MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 1203 | ||
1242 | MX6Q_PAD_CSI0_DAT18__UART5_RTS 1204 | ||
1243 | MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 1205 | ||
1244 | MX6Q_PAD_CSI0_DAT18__GPIO_6_4 1206 | ||
1245 | MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 1207 | ||
1246 | MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 1208 | ||
1247 | MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 1209 | ||
1248 | MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 1210 | ||
1249 | MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 1211 | ||
1250 | MX6Q_PAD_CSI0_DAT19__UART5_CTS 1212 | ||
1251 | MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 1213 | ||
1252 | MX6Q_PAD_CSI0_DAT19__GPIO_6_5 1214 | ||
1253 | MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 1215 | ||
1254 | MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 1216 | ||
1255 | MX6Q_PAD_JTAG_TMS__SJC_TMS 1217 | ||
1256 | MX6Q_PAD_JTAG_MOD__SJC_MOD 1218 | ||
1257 | MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB 1219 | ||
1258 | MX6Q_PAD_JTAG_TDI__SJC_TDI 1220 | ||
1259 | MX6Q_PAD_JTAG_TCK__SJC_TCK 1221 | ||
1260 | MX6Q_PAD_JTAG_TDO__SJC_TDO 1222 | ||
1261 | MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 1223 | ||
1262 | MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 1224 | ||
1263 | MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 1225 | ||
1264 | MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 1226 | ||
1265 | MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 1227 | ||
1266 | MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 1228 | ||
1267 | MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 1229 | ||
1268 | MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 1230 | ||
1269 | MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 1231 | ||
1270 | MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 1232 | ||
1271 | MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 1233 | ||
1272 | MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM 1234 | ||
1273 | MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ 1235 | ||
1274 | MX6Q_PAD_POR_B__SRC_POR_B 1236 | ||
1275 | MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 1237 | ||
1276 | MX6Q_PAD_RESET_IN_B__SRC_RESET_B 1238 | ||
1277 | MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 1239 | ||
1278 | MX6Q_PAD_TEST_MODE__TCU_TEST_MODE 1240 | ||
1279 | MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 1241 | ||
1280 | MX6Q_PAD_SD3_DAT7__UART1_TXD 1242 | ||
1281 | MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 1243 | ||
1282 | MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 1244 | ||
1283 | MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 1245 | ||
1284 | MX6Q_PAD_SD3_DAT7__GPIO_6_17 1246 | ||
1285 | MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 1247 | ||
1286 | MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV 1248 | ||
1287 | MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 1249 | ||
1288 | MX6Q_PAD_SD3_DAT6__UART1_RXD 1250 | ||
1289 | MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 1251 | ||
1290 | MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 1252 | ||
1291 | MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 1253 | ||
1292 | MX6Q_PAD_SD3_DAT6__GPIO_6_18 1254 | ||
1293 | MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 1255 | ||
1294 | MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 1256 | ||
1295 | MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 1257 | ||
1296 | MX6Q_PAD_SD3_DAT5__UART2_TXD 1258 | ||
1297 | MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 1259 | ||
1298 | MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 1260 | ||
1299 | MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 1261 | ||
1300 | MX6Q_PAD_SD3_DAT5__GPIO_7_0 1262 | ||
1301 | MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 1263 | ||
1302 | MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 1264 | ||
1303 | MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 1265 | ||
1304 | MX6Q_PAD_SD3_DAT4__UART2_RXD 1266 | ||
1305 | MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 1267 | ||
1306 | MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 1268 | ||
1307 | MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 1269 | ||
1308 | MX6Q_PAD_SD3_DAT4__GPIO_7_1 1270 | ||
1309 | MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 1271 | ||
1310 | MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 1272 | ||
1311 | MX6Q_PAD_SD3_CMD__USDHC3_CMD 1273 | ||
1312 | MX6Q_PAD_SD3_CMD__UART2_CTS 1274 | ||
1313 | MX6Q_PAD_SD3_CMD__CAN1_TXCAN 1275 | ||
1314 | MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 1276 | ||
1315 | MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 1277 | ||
1316 | MX6Q_PAD_SD3_CMD__GPIO_7_2 1278 | ||
1317 | MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 1279 | ||
1318 | MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 1280 | ||
1319 | MX6Q_PAD_SD3_CLK__USDHC3_CLK 1281 | ||
1320 | MX6Q_PAD_SD3_CLK__UART2_RTS 1282 | ||
1321 | MX6Q_PAD_SD3_CLK__CAN1_RXCAN 1283 | ||
1322 | MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 1284 | ||
1323 | MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 1285 | ||
1324 | MX6Q_PAD_SD3_CLK__GPIO_7_3 1286 | ||
1325 | MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 1287 | ||
1326 | MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 1288 | ||
1327 | MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 1289 | ||
1328 | MX6Q_PAD_SD3_DAT0__UART1_CTS 1290 | ||
1329 | MX6Q_PAD_SD3_DAT0__CAN2_TXCAN 1291 | ||
1330 | MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 1292 | ||
1331 | MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 1293 | ||
1332 | MX6Q_PAD_SD3_DAT0__GPIO_7_4 1294 | ||
1333 | MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 1295 | ||
1334 | MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 1296 | ||
1335 | MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 1297 | ||
1336 | MX6Q_PAD_SD3_DAT1__UART1_RTS 1298 | ||
1337 | MX6Q_PAD_SD3_DAT1__CAN2_RXCAN 1299 | ||
1338 | MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 1300 | ||
1339 | MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 1301 | ||
1340 | MX6Q_PAD_SD3_DAT1__GPIO_7_5 1302 | ||
1341 | MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 1303 | ||
1342 | MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 1304 | ||
1343 | MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 1305 | ||
1344 | MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 1306 | ||
1345 | MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 1307 | ||
1346 | MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 1308 | ||
1347 | MX6Q_PAD_SD3_DAT2__GPIO_7_6 1309 | ||
1348 | MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 1310 | ||
1349 | MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 1311 | ||
1350 | MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 1312 | ||
1351 | MX6Q_PAD_SD3_DAT3__UART3_CTS 1313 | ||
1352 | MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 1314 | ||
1353 | MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 1315 | ||
1354 | MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 1316 | ||
1355 | MX6Q_PAD_SD3_DAT3__GPIO_7_7 1317 | ||
1356 | MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 1318 | ||
1357 | MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 1319 | ||
1358 | MX6Q_PAD_SD3_RST__USDHC3_RST 1320 | ||
1359 | MX6Q_PAD_SD3_RST__UART3_RTS 1321 | ||
1360 | MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 1322 | ||
1361 | MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 1323 | ||
1362 | MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 1324 | ||
1363 | MX6Q_PAD_SD3_RST__GPIO_7_8 1325 | ||
1364 | MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 1326 | ||
1365 | MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 1327 | ||
1366 | MX6Q_PAD_NANDF_CLE__RAWNAND_CLE 1328 | ||
1367 | MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 1329 | ||
1368 | MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 1330 | ||
1369 | MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 1331 | ||
1370 | MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 1332 | ||
1371 | MX6Q_PAD_NANDF_CLE__GPIO_6_7 1333 | ||
1372 | MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 1334 | ||
1373 | MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 1335 | ||
1374 | MX6Q_PAD_NANDF_ALE__RAWNAND_ALE 1336 | ||
1375 | MX6Q_PAD_NANDF_ALE__USDHC4_RST 1337 | ||
1376 | MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 1338 | ||
1377 | MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 1339 | ||
1378 | MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 1340 | ||
1379 | MX6Q_PAD_NANDF_ALE__GPIO_6_8 1341 | ||
1380 | MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 1342 | ||
1381 | MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 1343 | ||
1382 | MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN 1344 | ||
1383 | MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 1345 | ||
1384 | MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 1346 | ||
1385 | MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 1347 | ||
1386 | MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 1348 | ||
1387 | MX6Q_PAD_NANDF_WP_B__GPIO_6_9 1349 | ||
1388 | MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 1350 | ||
1389 | MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 1351 | ||
1390 | MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 1352 | ||
1391 | MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 1353 | ||
1392 | MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 1354 | ||
1393 | MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 1355 | ||
1394 | MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 1356 | ||
1395 | MX6Q_PAD_NANDF_RB0__GPIO_6_10 1357 | ||
1396 | MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 1358 | ||
1397 | MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 1359 | ||
1398 | MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N 1360 | ||
1399 | MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 1361 | ||
1400 | MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 1362 | ||
1401 | MX6Q_PAD_NANDF_CS0__GPIO_6_11 1363 | ||
1402 | MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 1364 | ||
1403 | MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N 1365 | ||
1404 | MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT 1366 | ||
1405 | MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT 1367 | ||
1406 | MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 1368 | ||
1407 | MX6Q_PAD_NANDF_CS1__GPIO_6_14 1369 | ||
1408 | MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT 1370 | ||
1409 | MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N 1371 | ||
1410 | MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 1372 | ||
1411 | MX6Q_PAD_NANDF_CS2__ESAI1_TX0 1373 | ||
1412 | MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE 1374 | ||
1413 | MX6Q_PAD_NANDF_CS2__CCM_CLKO2 1375 | ||
1414 | MX6Q_PAD_NANDF_CS2__GPIO_6_15 1376 | ||
1415 | MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 1377 | ||
1416 | MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N 1378 | ||
1417 | MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 1379 | ||
1418 | MX6Q_PAD_NANDF_CS3__ESAI1_TX1 1380 | ||
1419 | MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 1381 | ||
1420 | MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 1382 | ||
1421 | MX6Q_PAD_NANDF_CS3__GPIO_6_16 1383 | ||
1422 | MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 1384 | ||
1423 | MX6Q_PAD_NANDF_CS3__TPSMP_CLK 1385 | ||
1424 | MX6Q_PAD_SD4_CMD__USDHC4_CMD 1386 | ||
1425 | MX6Q_PAD_SD4_CMD__RAWNAND_RDN 1387 | ||
1426 | MX6Q_PAD_SD4_CMD__UART3_TXD 1388 | ||
1427 | MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 1389 | ||
1428 | MX6Q_PAD_SD4_CMD__GPIO_7_9 1390 | ||
1429 | MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR 1391 | ||
1430 | MX6Q_PAD_SD4_CLK__USDHC4_CLK 1392 | ||
1431 | MX6Q_PAD_SD4_CLK__RAWNAND_WRN 1393 | ||
1432 | MX6Q_PAD_SD4_CLK__UART3_RXD 1394 | ||
1433 | MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 1395 | ||
1434 | MX6Q_PAD_SD4_CLK__GPIO_7_10 1396 | ||
1435 | MX6Q_PAD_NANDF_D0__RAWNAND_D0 1397 | ||
1436 | MX6Q_PAD_NANDF_D0__USDHC1_DAT4 1398 | ||
1437 | MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 1399 | ||
1438 | MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 1400 | ||
1439 | MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 1401 | ||
1440 | MX6Q_PAD_NANDF_D0__GPIO_2_0 1402 | ||
1441 | MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 1403 | ||
1442 | MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 1404 | ||
1443 | MX6Q_PAD_NANDF_D1__RAWNAND_D1 1405 | ||
1444 | MX6Q_PAD_NANDF_D1__USDHC1_DAT5 1406 | ||
1445 | MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 1407 | ||
1446 | MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 1408 | ||
1447 | MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 1409 | ||
1448 | MX6Q_PAD_NANDF_D1__GPIO_2_1 1410 | ||
1449 | MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 1411 | ||
1450 | MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 1412 | ||
1451 | MX6Q_PAD_NANDF_D2__RAWNAND_D2 1413 | ||
1452 | MX6Q_PAD_NANDF_D2__USDHC1_DAT6 1414 | ||
1453 | MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 1415 | ||
1454 | MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 1416 | ||
1455 | MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 1417 | ||
1456 | MX6Q_PAD_NANDF_D2__GPIO_2_2 1418 | ||
1457 | MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 1419 | ||
1458 | MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 1420 | ||
1459 | MX6Q_PAD_NANDF_D3__RAWNAND_D3 1421 | ||
1460 | MX6Q_PAD_NANDF_D3__USDHC1_DAT7 1422 | ||
1461 | MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 1423 | ||
1462 | MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 1424 | ||
1463 | MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 1425 | ||
1464 | MX6Q_PAD_NANDF_D3__GPIO_2_3 1426 | ||
1465 | MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 1427 | ||
1466 | MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 1428 | ||
1467 | MX6Q_PAD_NANDF_D4__RAWNAND_D4 1429 | ||
1468 | MX6Q_PAD_NANDF_D4__USDHC2_DAT4 1430 | ||
1469 | MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 1431 | ||
1470 | MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 1432 | ||
1471 | MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 1433 | ||
1472 | MX6Q_PAD_NANDF_D4__GPIO_2_4 1434 | ||
1473 | MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 1435 | ||
1474 | MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 1436 | ||
1475 | MX6Q_PAD_NANDF_D5__RAWNAND_D5 1437 | ||
1476 | MX6Q_PAD_NANDF_D5__USDHC2_DAT5 1438 | ||
1477 | MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 1439 | ||
1478 | MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 1440 | ||
1479 | MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 1441 | ||
1480 | MX6Q_PAD_NANDF_D5__GPIO_2_5 1442 | ||
1481 | MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 1443 | ||
1482 | MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 1444 | ||
1483 | MX6Q_PAD_NANDF_D6__RAWNAND_D6 1445 | ||
1484 | MX6Q_PAD_NANDF_D6__USDHC2_DAT6 1446 | ||
1485 | MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 1447 | ||
1486 | MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 1448 | ||
1487 | MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 1449 | ||
1488 | MX6Q_PAD_NANDF_D6__GPIO_2_6 1450 | ||
1489 | MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 1451 | ||
1490 | MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 1452 | ||
1491 | MX6Q_PAD_NANDF_D7__RAWNAND_D7 1453 | ||
1492 | MX6Q_PAD_NANDF_D7__USDHC2_DAT7 1454 | ||
1493 | MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 1455 | ||
1494 | MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 1456 | ||
1495 | MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 1457 | ||
1496 | MX6Q_PAD_NANDF_D7__GPIO_2_7 1458 | ||
1497 | MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 1459 | ||
1498 | MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 1460 | ||
1499 | MX6Q_PAD_SD4_DAT0__RAWNAND_D8 1461 | ||
1500 | MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 1462 | ||
1501 | MX6Q_PAD_SD4_DAT0__RAWNAND_DQS 1463 | ||
1502 | MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 1464 | ||
1503 | MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 1465 | ||
1504 | MX6Q_PAD_SD4_DAT0__GPIO_2_8 1466 | ||
1505 | MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 1467 | ||
1506 | MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 1468 | ||
1507 | MX6Q_PAD_SD4_DAT1__RAWNAND_D9 1469 | ||
1508 | MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 1470 | ||
1509 | MX6Q_PAD_SD4_DAT1__PWM3_PWMO 1471 | ||
1510 | MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 1472 | ||
1511 | MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 1473 | ||
1512 | MX6Q_PAD_SD4_DAT1__GPIO_2_9 1474 | ||
1513 | MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 1475 | ||
1514 | MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 1476 | ||
1515 | MX6Q_PAD_SD4_DAT2__RAWNAND_D10 1477 | ||
1516 | MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 1478 | ||
1517 | MX6Q_PAD_SD4_DAT2__PWM4_PWMO 1479 | ||
1518 | MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 1480 | ||
1519 | MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 1481 | ||
1520 | MX6Q_PAD_SD4_DAT2__GPIO_2_10 1482 | ||
1521 | MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 1483 | ||
1522 | MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 1484 | ||
1523 | MX6Q_PAD_SD4_DAT3__RAWNAND_D11 1485 | ||
1524 | MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 1486 | ||
1525 | MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 1487 | ||
1526 | MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 1488 | ||
1527 | MX6Q_PAD_SD4_DAT3__GPIO_2_11 1489 | ||
1528 | MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 1490 | ||
1529 | MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 1491 | ||
1530 | MX6Q_PAD_SD4_DAT4__RAWNAND_D12 1492 | ||
1531 | MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 1493 | ||
1532 | MX6Q_PAD_SD4_DAT4__UART2_RXD 1494 | ||
1533 | MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 1495 | ||
1534 | MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 1496 | ||
1535 | MX6Q_PAD_SD4_DAT4__GPIO_2_12 1497 | ||
1536 | MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 1498 | ||
1537 | MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 1499 | ||
1538 | MX6Q_PAD_SD4_DAT5__RAWNAND_D13 1500 | ||
1539 | MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 1501 | ||
1540 | MX6Q_PAD_SD4_DAT5__UART2_RTS 1502 | ||
1541 | MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 1503 | ||
1542 | MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 1504 | ||
1543 | MX6Q_PAD_SD4_DAT5__GPIO_2_13 1505 | ||
1544 | MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 1506 | ||
1545 | MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 1507 | ||
1546 | MX6Q_PAD_SD4_DAT6__RAWNAND_D14 1508 | ||
1547 | MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 1509 | ||
1548 | MX6Q_PAD_SD4_DAT6__UART2_CTS 1510 | ||
1549 | MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 1511 | ||
1550 | MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 1512 | ||
1551 | MX6Q_PAD_SD4_DAT6__GPIO_2_14 1513 | ||
1552 | MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 1514 | ||
1553 | MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 1515 | ||
1554 | MX6Q_PAD_SD4_DAT7__RAWNAND_D15 1516 | ||
1555 | MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 1517 | ||
1556 | MX6Q_PAD_SD4_DAT7__UART2_TXD 1518 | ||
1557 | MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 1519 | ||
1558 | MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 1520 | ||
1559 | MX6Q_PAD_SD4_DAT7__GPIO_2_15 1521 | ||
1560 | MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 1522 | ||
1561 | MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 1523 | ||
1562 | MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 1524 | ||
1563 | MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 1525 | ||
1564 | MX6Q_PAD_SD1_DAT1__PWM3_PWMO 1526 | ||
1565 | MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 1527 | ||
1566 | MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 1528 | ||
1567 | MX6Q_PAD_SD1_DAT1__GPIO_1_17 1529 | ||
1568 | MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 1530 | ||
1569 | MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 1531 | ||
1570 | MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 1532 | ||
1571 | MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 1533 | ||
1572 | MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS 1534 | ||
1573 | MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 1535 | ||
1574 | MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 1536 | ||
1575 | MX6Q_PAD_SD1_DAT0__GPIO_1_16 1537 | ||
1576 | MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 1538 | ||
1577 | MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 1539 | ||
1578 | MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 1540 | ||
1579 | MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 1541 | ||
1580 | MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 1542 | ||
1581 | MX6Q_PAD_SD1_DAT3__PWM1_PWMO 1543 | ||
1582 | MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B 1544 | ||
1583 | MX6Q_PAD_SD1_DAT3__GPIO_1_21 1545 | ||
1584 | MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB 1546 | ||
1585 | MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 1547 | ||
1586 | MX6Q_PAD_SD1_CMD__USDHC1_CMD 1548 | ||
1587 | MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 1549 | ||
1588 | MX6Q_PAD_SD1_CMD__PWM4_PWMO 1550 | ||
1589 | MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 1551 | ||
1590 | MX6Q_PAD_SD1_CMD__GPIO_1_18 1552 | ||
1591 | MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 1553 | ||
1592 | MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 1554 | ||
1593 | MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 1555 | ||
1594 | MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 1556 | ||
1595 | MX6Q_PAD_SD1_DAT2__PWM2_PWMO 1557 | ||
1596 | MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B 1558 | ||
1597 | MX6Q_PAD_SD1_DAT2__GPIO_1_19 1559 | ||
1598 | MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB 1560 | ||
1599 | MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 1561 | ||
1600 | MX6Q_PAD_SD1_CLK__USDHC1_CLK 1562 | ||
1601 | MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 1563 | ||
1602 | MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT 1564 | ||
1603 | MX6Q_PAD_SD1_CLK__GPT_CLKIN 1565 | ||
1604 | MX6Q_PAD_SD1_CLK__GPIO_1_20 1566 | ||
1605 | MX6Q_PAD_SD1_CLK__PHY_DTB_0 1567 | ||
1606 | MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 1568 | ||
1607 | MX6Q_PAD_SD2_CLK__USDHC2_CLK 1569 | ||
1608 | MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 1570 | ||
1609 | MX6Q_PAD_SD2_CLK__KPP_COL_5 1571 | ||
1610 | MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 1572 | ||
1611 | MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 1573 | ||
1612 | MX6Q_PAD_SD2_CLK__GPIO_1_10 1574 | ||
1613 | MX6Q_PAD_SD2_CLK__PHY_DTB_1 1575 | ||
1614 | MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 1576 | ||
1615 | MX6Q_PAD_SD2_CMD__USDHC2_CMD 1577 | ||
1616 | MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 1578 | ||
1617 | MX6Q_PAD_SD2_CMD__KPP_ROW_5 1579 | ||
1618 | MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC 1580 | ||
1619 | MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 1581 | ||
1620 | MX6Q_PAD_SD2_CMD__GPIO_1_11 1582 | ||
1621 | MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 1583 | ||
1622 | MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 1584 | ||
1623 | MX6Q_PAD_SD2_DAT3__KPP_COL_6 1585 | ||
1624 | MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC 1586 | ||
1625 | MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 1587 | ||
1626 | MX6Q_PAD_SD2_DAT3__GPIO_1_12 1588 | ||
1627 | MX6Q_PAD_SD2_DAT3__SJC_DONE 1589 | ||
1628 | MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 1590 | ||
1629 | MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID 1591 | ||
1630 | MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID 1592 | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt deleted file mode 100644 index f7e8e8f4d9a..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt +++ /dev/null | |||
@@ -1,918 +0,0 @@ | |||
1 | * Freescale MXS Pin Controller | ||
2 | |||
3 | The pins controlled by mxs pin controller are organized in banks, each bank | ||
4 | has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th | ||
5 | function is GPIO. The configuration on the pins includes drive strength, | ||
6 | voltage and pull-up. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl" | ||
10 | - reg: Should contain the register physical address and length for the | ||
11 | pin controller. | ||
12 | |||
13 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
14 | common pinctrl bindings used by client devices. | ||
15 | |||
16 | The node of mxs pin controller acts as a container for an arbitrary number of | ||
17 | subnodes. Each of these subnodes represents some desired configuration for | ||
18 | a group of pins, and only affects those parameters that are explicitly listed. | ||
19 | In other words, a subnode that describes a drive strength parameter implies no | ||
20 | information about pull-up. For this reason, even seemingly boolean values are | ||
21 | actually tristates in this binding: unspecified, off, or on. Unspecified is | ||
22 | represented as an absent property, and off/on are represented as integer | ||
23 | values 0 and 1. | ||
24 | |||
25 | Those subnodes under mxs pin controller node will fall into two categories. | ||
26 | One is to set up a group of pins for a function, both mux selection and pin | ||
27 | configurations, and it's called group node in the binding document. The other | ||
28 | one is to adjust the pin configuration for some particular pins that need a | ||
29 | different configuration than what is defined in group node. The binding | ||
30 | document calls this type of node config node. | ||
31 | |||
32 | On mxs, there is no hardware pin group. The pin group in this binding only | ||
33 | means a group of pins put together for particular peripheral to work in | ||
34 | particular function, like SSP0 functioning as mmc0-8bit. That said, the | ||
35 | group node should include all the pins needed for one function rather than | ||
36 | having these pins defined in several group nodes. It also means each of | ||
37 | "pinctrl-*" phandle in client device node should only have one group node | ||
38 | pointed in there, while the phandle can have multiple config node referenced | ||
39 | there to adjust configurations for some pins in the group. | ||
40 | |||
41 | Required subnode-properties: | ||
42 | - fsl,pinmux-ids: An integer array. Each integer in the array specify a pin | ||
43 | with given mux function, with bank, pin and mux packed as below. | ||
44 | |||
45 | [15..12] : bank number | ||
46 | [11..4] : pin number | ||
47 | [3..0] : mux selection | ||
48 | |||
49 | This integer with mux selection packed is used as an entity by both group | ||
50 | and config nodes to identify a pin. The mux selection in the integer takes | ||
51 | effects only on group node, and will get ignored by driver with config node, | ||
52 | since config node is only meant to set up pin configurations. | ||
53 | |||
54 | Valid values for these integers are listed below. | ||
55 | |||
56 | - reg: Should be the index of the group nodes for same function. This property | ||
57 | is required only for group nodes, and should not be present in any config | ||
58 | nodes. | ||
59 | |||
60 | Optional subnode-properties: | ||
61 | - fsl,drive-strength: Integer. | ||
62 | 0: 4 mA | ||
63 | 1: 8 mA | ||
64 | 2: 12 mA | ||
65 | 3: 16 mA | ||
66 | - fsl,voltage: Integer. | ||
67 | 0: 1.8 V | ||
68 | 1: 3.3 V | ||
69 | - fsl,pull-up: Integer. | ||
70 | 0: Disable the internal pull-up | ||
71 | 1: Enable the internal pull-up | ||
72 | |||
73 | Examples: | ||
74 | |||
75 | pinctrl@80018000 { | ||
76 | #address-cells = <1>; | ||
77 | #size-cells = <0>; | ||
78 | compatible = "fsl,imx28-pinctrl"; | ||
79 | reg = <0x80018000 2000>; | ||
80 | |||
81 | mmc0_8bit_pins_a: mmc0-8bit@0 { | ||
82 | reg = <0>; | ||
83 | fsl,pinmux-ids = < | ||
84 | 0x2000 0x2010 0x2020 0x2030 | ||
85 | 0x2040 0x2050 0x2060 0x2070 | ||
86 | 0x2080 0x2090 0x20a0>; | ||
87 | fsl,drive-strength = <1>; | ||
88 | fsl,voltage = <1>; | ||
89 | fsl,pull-up = <1>; | ||
90 | }; | ||
91 | |||
92 | mmc_cd_cfg: mmc-cd-cfg { | ||
93 | fsl,pinmux-ids = <0x2090>; | ||
94 | fsl,pull-up = <0>; | ||
95 | }; | ||
96 | |||
97 | mmc_sck_cfg: mmc-sck-cfg { | ||
98 | fsl,pinmux-ids = <0x20a0>; | ||
99 | fsl,drive-strength = <2>; | ||
100 | fsl,pull-up = <0>; | ||
101 | }; | ||
102 | }; | ||
103 | |||
104 | In this example, group node mmc0-8bit defines a group of pins for mxs SSP0 | ||
105 | to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations | ||
106 | applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are | ||
107 | adjusting the configuration for pins card-detection and clock from what group | ||
108 | node mmc0-8bit defines. Only the configuration properties to be adjusted need | ||
109 | to be listed in the config nodes. | ||
110 | |||
111 | Valid values for i.MX28 pinmux-id: | ||
112 | |||
113 | pinmux id | ||
114 | ------ -- | ||
115 | MX28_PAD_GPMI_D00__GPMI_D0 0x0000 | ||
116 | MX28_PAD_GPMI_D01__GPMI_D1 0x0010 | ||
117 | MX28_PAD_GPMI_D02__GPMI_D2 0x0020 | ||
118 | MX28_PAD_GPMI_D03__GPMI_D3 0x0030 | ||
119 | MX28_PAD_GPMI_D04__GPMI_D4 0x0040 | ||
120 | MX28_PAD_GPMI_D05__GPMI_D5 0x0050 | ||
121 | MX28_PAD_GPMI_D06__GPMI_D6 0x0060 | ||
122 | MX28_PAD_GPMI_D07__GPMI_D7 0x0070 | ||
123 | MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 | ||
124 | MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 | ||
125 | MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 | ||
126 | MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 | ||
127 | MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 | ||
128 | MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 | ||
129 | MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 | ||
130 | MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 | ||
131 | MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 | ||
132 | MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 | ||
133 | MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 | ||
134 | MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 | ||
135 | MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 | ||
136 | MX28_PAD_LCD_D00__LCD_D0 0x1000 | ||
137 | MX28_PAD_LCD_D01__LCD_D1 0x1010 | ||
138 | MX28_PAD_LCD_D02__LCD_D2 0x1020 | ||
139 | MX28_PAD_LCD_D03__LCD_D3 0x1030 | ||
140 | MX28_PAD_LCD_D04__LCD_D4 0x1040 | ||
141 | MX28_PAD_LCD_D05__LCD_D5 0x1050 | ||
142 | MX28_PAD_LCD_D06__LCD_D6 0x1060 | ||
143 | MX28_PAD_LCD_D07__LCD_D7 0x1070 | ||
144 | MX28_PAD_LCD_D08__LCD_D8 0x1080 | ||
145 | MX28_PAD_LCD_D09__LCD_D9 0x1090 | ||
146 | MX28_PAD_LCD_D10__LCD_D10 0x10a0 | ||
147 | MX28_PAD_LCD_D11__LCD_D11 0x10b0 | ||
148 | MX28_PAD_LCD_D12__LCD_D12 0x10c0 | ||
149 | MX28_PAD_LCD_D13__LCD_D13 0x10d0 | ||
150 | MX28_PAD_LCD_D14__LCD_D14 0x10e0 | ||
151 | MX28_PAD_LCD_D15__LCD_D15 0x10f0 | ||
152 | MX28_PAD_LCD_D16__LCD_D16 0x1100 | ||
153 | MX28_PAD_LCD_D17__LCD_D17 0x1110 | ||
154 | MX28_PAD_LCD_D18__LCD_D18 0x1120 | ||
155 | MX28_PAD_LCD_D19__LCD_D19 0x1130 | ||
156 | MX28_PAD_LCD_D20__LCD_D20 0x1140 | ||
157 | MX28_PAD_LCD_D21__LCD_D21 0x1150 | ||
158 | MX28_PAD_LCD_D22__LCD_D22 0x1160 | ||
159 | MX28_PAD_LCD_D23__LCD_D23 0x1170 | ||
160 | MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 | ||
161 | MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 | ||
162 | MX28_PAD_LCD_RS__LCD_RS 0x11a0 | ||
163 | MX28_PAD_LCD_CS__LCD_CS 0x11b0 | ||
164 | MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 | ||
165 | MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 | ||
166 | MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 | ||
167 | MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 | ||
168 | MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 | ||
169 | MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 | ||
170 | MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 | ||
171 | MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 | ||
172 | MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 | ||
173 | MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 | ||
174 | MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 | ||
175 | MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 | ||
176 | MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 | ||
177 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 | ||
178 | MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 | ||
179 | MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 | ||
180 | MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 | ||
181 | MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 | ||
182 | MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 | ||
183 | MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 | ||
184 | MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 | ||
185 | MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 | ||
186 | MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 | ||
187 | MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 | ||
188 | MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 | ||
189 | MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 | ||
190 | MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 | ||
191 | MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 | ||
192 | MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 | ||
193 | MX28_PAD_AUART0_RX__AUART0_RX 0x3000 | ||
194 | MX28_PAD_AUART0_TX__AUART0_TX 0x3010 | ||
195 | MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 | ||
196 | MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 | ||
197 | MX28_PAD_AUART1_RX__AUART1_RX 0x3040 | ||
198 | MX28_PAD_AUART1_TX__AUART1_TX 0x3050 | ||
199 | MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 | ||
200 | MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 | ||
201 | MX28_PAD_AUART2_RX__AUART2_RX 0x3080 | ||
202 | MX28_PAD_AUART2_TX__AUART2_TX 0x3090 | ||
203 | MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 | ||
204 | MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 | ||
205 | MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 | ||
206 | MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 | ||
207 | MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 | ||
208 | MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 | ||
209 | MX28_PAD_PWM0__PWM_0 0x3100 | ||
210 | MX28_PAD_PWM1__PWM_1 0x3110 | ||
211 | MX28_PAD_PWM2__PWM_2 0x3120 | ||
212 | MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 | ||
213 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 | ||
214 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 | ||
215 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 | ||
216 | MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 | ||
217 | MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 | ||
218 | MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 | ||
219 | MX28_PAD_SPDIF__SPDIF_TX 0x31b0 | ||
220 | MX28_PAD_PWM3__PWM_3 0x31c0 | ||
221 | MX28_PAD_PWM4__PWM_4 0x31d0 | ||
222 | MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 | ||
223 | MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 | ||
224 | MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 | ||
225 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 | ||
226 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 | ||
227 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 | ||
228 | MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 | ||
229 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 | ||
230 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 | ||
231 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 | ||
232 | MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 | ||
233 | MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 | ||
234 | MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 | ||
235 | MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 | ||
236 | MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 | ||
237 | MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 | ||
238 | MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 | ||
239 | MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 | ||
240 | MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 | ||
241 | MX28_PAD_EMI_D00__EMI_DATA0 0x5000 | ||
242 | MX28_PAD_EMI_D01__EMI_DATA1 0x5010 | ||
243 | MX28_PAD_EMI_D02__EMI_DATA2 0x5020 | ||
244 | MX28_PAD_EMI_D03__EMI_DATA3 0x5030 | ||
245 | MX28_PAD_EMI_D04__EMI_DATA4 0x5040 | ||
246 | MX28_PAD_EMI_D05__EMI_DATA5 0x5050 | ||
247 | MX28_PAD_EMI_D06__EMI_DATA6 0x5060 | ||
248 | MX28_PAD_EMI_D07__EMI_DATA7 0x5070 | ||
249 | MX28_PAD_EMI_D08__EMI_DATA8 0x5080 | ||
250 | MX28_PAD_EMI_D09__EMI_DATA9 0x5090 | ||
251 | MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 | ||
252 | MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 | ||
253 | MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 | ||
254 | MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 | ||
255 | MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 | ||
256 | MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 | ||
257 | MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 | ||
258 | MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 | ||
259 | MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 | ||
260 | MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 | ||
261 | MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 | ||
262 | MX28_PAD_EMI_CLK__EMI_CLK 0x5150 | ||
263 | MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 | ||
264 | MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 | ||
265 | MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 | ||
266 | MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 | ||
267 | MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 | ||
268 | MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 | ||
269 | MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 | ||
270 | MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 | ||
271 | MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 | ||
272 | MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 | ||
273 | MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 | ||
274 | MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 | ||
275 | MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 | ||
276 | MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 | ||
277 | MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 | ||
278 | MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 | ||
279 | MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 | ||
280 | MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 | ||
281 | MX28_PAD_EMI_BA0__EMI_BA0 0x6100 | ||
282 | MX28_PAD_EMI_BA1__EMI_BA1 0x6110 | ||
283 | MX28_PAD_EMI_BA2__EMI_BA2 0x6120 | ||
284 | MX28_PAD_EMI_CASN__EMI_CASN 0x6130 | ||
285 | MX28_PAD_EMI_RASN__EMI_RASN 0x6140 | ||
286 | MX28_PAD_EMI_WEN__EMI_WEN 0x6150 | ||
287 | MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 | ||
288 | MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 | ||
289 | MX28_PAD_EMI_CKE__EMI_CKE 0x6180 | ||
290 | MX28_PAD_GPMI_D00__SSP1_D0 0x0001 | ||
291 | MX28_PAD_GPMI_D01__SSP1_D1 0x0011 | ||
292 | MX28_PAD_GPMI_D02__SSP1_D2 0x0021 | ||
293 | MX28_PAD_GPMI_D03__SSP1_D3 0x0031 | ||
294 | MX28_PAD_GPMI_D04__SSP1_D4 0x0041 | ||
295 | MX28_PAD_GPMI_D05__SSP1_D5 0x0051 | ||
296 | MX28_PAD_GPMI_D06__SSP1_D6 0x0061 | ||
297 | MX28_PAD_GPMI_D07__SSP1_D7 0x0071 | ||
298 | MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 | ||
299 | MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 | ||
300 | MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 | ||
301 | MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 | ||
302 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 | ||
303 | MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 | ||
304 | MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 | ||
305 | MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 | ||
306 | MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 | ||
307 | MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 | ||
308 | MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 | ||
309 | MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 | ||
310 | MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 | ||
311 | MX28_PAD_LCD_D03__ETM_DA8 0x1031 | ||
312 | MX28_PAD_LCD_D04__ETM_DA9 0x1041 | ||
313 | MX28_PAD_LCD_D08__ETM_DA3 0x1081 | ||
314 | MX28_PAD_LCD_D09__ETM_DA4 0x1091 | ||
315 | MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 | ||
316 | MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 | ||
317 | MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 | ||
318 | MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 | ||
319 | MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 | ||
320 | MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 | ||
321 | MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 | ||
322 | MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 | ||
323 | MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 | ||
324 | MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 | ||
325 | MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 | ||
326 | MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 | ||
327 | MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 | ||
328 | MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 | ||
329 | MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 | ||
330 | MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 | ||
331 | MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 | ||
332 | MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 | ||
333 | MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 | ||
334 | MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 | ||
335 | MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 | ||
336 | MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 | ||
337 | MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 | ||
338 | MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 | ||
339 | MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 | ||
340 | MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 | ||
341 | MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 | ||
342 | MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 | ||
343 | MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 | ||
344 | MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 | ||
345 | MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 | ||
346 | MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 | ||
347 | MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 | ||
348 | MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 | ||
349 | MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 | ||
350 | MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 | ||
351 | MX28_PAD_AUART1_RTS__USB0_ID 0x3071 | ||
352 | MX28_PAD_AUART2_RX__SSP3_D1 0x3081 | ||
353 | MX28_PAD_AUART2_TX__SSP3_D2 0x3091 | ||
354 | MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 | ||
355 | MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 | ||
356 | MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 | ||
357 | MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 | ||
358 | MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 | ||
359 | MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 | ||
360 | MX28_PAD_PWM0__I2C1_SCL 0x3101 | ||
361 | MX28_PAD_PWM1__I2C1_SDA 0x3111 | ||
362 | MX28_PAD_PWM2__USB0_ID 0x3121 | ||
363 | MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 | ||
364 | MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 | ||
365 | MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 | ||
366 | MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 | ||
367 | MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 | ||
368 | MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 | ||
369 | MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 | ||
370 | MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 | ||
371 | MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 | ||
372 | MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 | ||
373 | MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 | ||
374 | MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 | ||
375 | MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 | ||
376 | MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 | ||
377 | MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 | ||
378 | MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 | ||
379 | MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 | ||
380 | MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 | ||
381 | MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 | ||
382 | MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 | ||
383 | MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 | ||
384 | MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 | ||
385 | MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 | ||
386 | MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 | ||
387 | MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 | ||
388 | MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 | ||
389 | MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 | ||
390 | MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 | ||
391 | MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 | ||
392 | MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 | ||
393 | MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 | ||
394 | MX28_PAD_LCD_D00__ETM_DA0 0x1002 | ||
395 | MX28_PAD_LCD_D01__ETM_DA1 0x1012 | ||
396 | MX28_PAD_LCD_D02__ETM_DA2 0x1022 | ||
397 | MX28_PAD_LCD_D03__ETM_DA3 0x1032 | ||
398 | MX28_PAD_LCD_D04__ETM_DA4 0x1042 | ||
399 | MX28_PAD_LCD_D05__ETM_DA5 0x1052 | ||
400 | MX28_PAD_LCD_D06__ETM_DA6 0x1062 | ||
401 | MX28_PAD_LCD_D07__ETM_DA7 0x1072 | ||
402 | MX28_PAD_LCD_D08__ETM_DA8 0x1082 | ||
403 | MX28_PAD_LCD_D09__ETM_DA9 0x1092 | ||
404 | MX28_PAD_LCD_D10__ETM_DA10 0x10a2 | ||
405 | MX28_PAD_LCD_D11__ETM_DA11 0x10b2 | ||
406 | MX28_PAD_LCD_D12__ETM_DA12 0x10c2 | ||
407 | MX28_PAD_LCD_D13__ETM_DA13 0x10d2 | ||
408 | MX28_PAD_LCD_D14__ETM_DA14 0x10e2 | ||
409 | MX28_PAD_LCD_D15__ETM_DA15 0x10f2 | ||
410 | MX28_PAD_LCD_D16__ETM_DA7 0x1102 | ||
411 | MX28_PAD_LCD_D17__ETM_DA6 0x1112 | ||
412 | MX28_PAD_LCD_D18__ETM_DA5 0x1122 | ||
413 | MX28_PAD_LCD_D19__ETM_DA4 0x1132 | ||
414 | MX28_PAD_LCD_D20__ETM_DA3 0x1142 | ||
415 | MX28_PAD_LCD_D21__ETM_DA2 0x1152 | ||
416 | MX28_PAD_LCD_D22__ETM_DA1 0x1162 | ||
417 | MX28_PAD_LCD_D23__ETM_DA0 0x1172 | ||
418 | MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 | ||
419 | MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 | ||
420 | MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 | ||
421 | MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 | ||
422 | MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 | ||
423 | MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 | ||
424 | MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 | ||
425 | MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 | ||
426 | MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 | ||
427 | MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 | ||
428 | MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 | ||
429 | MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 | ||
430 | MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 | ||
431 | MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 | ||
432 | MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 | ||
433 | MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 | ||
434 | MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 | ||
435 | MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 | ||
436 | MX28_PAD_AUART0_RX__DUART_CTS 0x3002 | ||
437 | MX28_PAD_AUART0_TX__DUART_RTS 0x3012 | ||
438 | MX28_PAD_AUART0_CTS__DUART_RX 0x3022 | ||
439 | MX28_PAD_AUART0_RTS__DUART_TX 0x3032 | ||
440 | MX28_PAD_AUART1_RX__PWM_0 0x3042 | ||
441 | MX28_PAD_AUART1_TX__PWM_1 0x3052 | ||
442 | MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 | ||
443 | MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 | ||
444 | MX28_PAD_AUART2_RX__SSP3_D4 0x3082 | ||
445 | MX28_PAD_AUART2_TX__SSP3_D5 0x3092 | ||
446 | MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 | ||
447 | MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 | ||
448 | MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 | ||
449 | MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 | ||
450 | MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 | ||
451 | MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 | ||
452 | MX28_PAD_PWM0__DUART_RX 0x3102 | ||
453 | MX28_PAD_PWM1__DUART_TX 0x3112 | ||
454 | MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 | ||
455 | MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 | ||
456 | MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 | ||
457 | MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 | ||
458 | MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 | ||
459 | MX28_PAD_I2C0_SCL__DUART_RX 0x3182 | ||
460 | MX28_PAD_I2C0_SDA__DUART_TX 0x3192 | ||
461 | MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 | ||
462 | MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 | ||
463 | MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 | ||
464 | MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 | ||
465 | MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 | ||
466 | MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 | ||
467 | MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 | ||
468 | MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 | ||
469 | MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 | ||
470 | MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 | ||
471 | MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 | ||
472 | MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 | ||
473 | MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 | ||
474 | MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 | ||
475 | MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 | ||
476 | MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 | ||
477 | MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 | ||
478 | MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 | ||
479 | MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 | ||
480 | MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 | ||
481 | MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 | ||
482 | MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 | ||
483 | MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 | ||
484 | MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 | ||
485 | MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 | ||
486 | MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 | ||
487 | MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 | ||
488 | MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 | ||
489 | MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 | ||
490 | MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 | ||
491 | MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 | ||
492 | MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 | ||
493 | MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 | ||
494 | MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 | ||
495 | MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 | ||
496 | MX28_PAD_LCD_D00__GPIO_1_0 0x1003 | ||
497 | MX28_PAD_LCD_D01__GPIO_1_1 0x1013 | ||
498 | MX28_PAD_LCD_D02__GPIO_1_2 0x1023 | ||
499 | MX28_PAD_LCD_D03__GPIO_1_3 0x1033 | ||
500 | MX28_PAD_LCD_D04__GPIO_1_4 0x1043 | ||
501 | MX28_PAD_LCD_D05__GPIO_1_5 0x1053 | ||
502 | MX28_PAD_LCD_D06__GPIO_1_6 0x1063 | ||
503 | MX28_PAD_LCD_D07__GPIO_1_7 0x1073 | ||
504 | MX28_PAD_LCD_D08__GPIO_1_8 0x1083 | ||
505 | MX28_PAD_LCD_D09__GPIO_1_9 0x1093 | ||
506 | MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 | ||
507 | MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 | ||
508 | MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 | ||
509 | MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 | ||
510 | MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 | ||
511 | MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 | ||
512 | MX28_PAD_LCD_D16__GPIO_1_16 0x1103 | ||
513 | MX28_PAD_LCD_D17__GPIO_1_17 0x1113 | ||
514 | MX28_PAD_LCD_D18__GPIO_1_18 0x1123 | ||
515 | MX28_PAD_LCD_D19__GPIO_1_19 0x1133 | ||
516 | MX28_PAD_LCD_D20__GPIO_1_20 0x1143 | ||
517 | MX28_PAD_LCD_D21__GPIO_1_21 0x1153 | ||
518 | MX28_PAD_LCD_D22__GPIO_1_22 0x1163 | ||
519 | MX28_PAD_LCD_D23__GPIO_1_23 0x1173 | ||
520 | MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 | ||
521 | MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 | ||
522 | MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 | ||
523 | MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 | ||
524 | MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 | ||
525 | MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 | ||
526 | MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 | ||
527 | MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 | ||
528 | MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 | ||
529 | MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 | ||
530 | MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 | ||
531 | MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 | ||
532 | MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 | ||
533 | MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 | ||
534 | MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 | ||
535 | MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 | ||
536 | MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 | ||
537 | MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 | ||
538 | MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 | ||
539 | MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 | ||
540 | MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 | ||
541 | MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 | ||
542 | MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 | ||
543 | MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 | ||
544 | MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 | ||
545 | MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 | ||
546 | MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 | ||
547 | MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 | ||
548 | MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 | ||
549 | MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 | ||
550 | MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 | ||
551 | MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 | ||
552 | MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 | ||
553 | MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 | ||
554 | MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 | ||
555 | MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 | ||
556 | MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 | ||
557 | MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 | ||
558 | MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 | ||
559 | MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 | ||
560 | MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 | ||
561 | MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 | ||
562 | MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 | ||
563 | MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 | ||
564 | MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 | ||
565 | MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 | ||
566 | MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 | ||
567 | MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 | ||
568 | MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 | ||
569 | MX28_PAD_PWM0__GPIO_3_16 0x3103 | ||
570 | MX28_PAD_PWM1__GPIO_3_17 0x3113 | ||
571 | MX28_PAD_PWM2__GPIO_3_18 0x3123 | ||
572 | MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 | ||
573 | MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 | ||
574 | MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 | ||
575 | MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 | ||
576 | MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 | ||
577 | MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 | ||
578 | MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 | ||
579 | MX28_PAD_SPDIF__GPIO_3_27 0x31b3 | ||
580 | MX28_PAD_PWM3__GPIO_3_28 0x31c3 | ||
581 | MX28_PAD_PWM4__GPIO_3_29 0x31d3 | ||
582 | MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 | ||
583 | MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 | ||
584 | MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 | ||
585 | MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 | ||
586 | MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 | ||
587 | MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 | ||
588 | MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 | ||
589 | MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 | ||
590 | MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 | ||
591 | MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 | ||
592 | MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 | ||
593 | MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 | ||
594 | MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 | ||
595 | MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 | ||
596 | MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 | ||
597 | MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 | ||
598 | MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 | ||
599 | MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 | ||
600 | MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 | ||
601 | |||
602 | Valid values for i.MX23 pinmux-id: | ||
603 | |||
604 | pinmux id | ||
605 | ------ -- | ||
606 | MX23_PAD_GPMI_D00__GPMI_D00 0x0000 | ||
607 | MX23_PAD_GPMI_D01__GPMI_D01 0x0010 | ||
608 | MX23_PAD_GPMI_D02__GPMI_D02 0x0020 | ||
609 | MX23_PAD_GPMI_D03__GPMI_D03 0x0030 | ||
610 | MX23_PAD_GPMI_D04__GPMI_D04 0x0040 | ||
611 | MX23_PAD_GPMI_D05__GPMI_D05 0x0050 | ||
612 | MX23_PAD_GPMI_D06__GPMI_D06 0x0060 | ||
613 | MX23_PAD_GPMI_D07__GPMI_D07 0x0070 | ||
614 | MX23_PAD_GPMI_D08__GPMI_D08 0x0080 | ||
615 | MX23_PAD_GPMI_D09__GPMI_D09 0x0090 | ||
616 | MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 | ||
617 | MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 | ||
618 | MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 | ||
619 | MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 | ||
620 | MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 | ||
621 | MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 | ||
622 | MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 | ||
623 | MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 | ||
624 | MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 | ||
625 | MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 | ||
626 | MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 | ||
627 | MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 | ||
628 | MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 | ||
629 | MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 | ||
630 | MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 | ||
631 | MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 | ||
632 | MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 | ||
633 | MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 | ||
634 | MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 | ||
635 | MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 | ||
636 | MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 | ||
637 | MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 | ||
638 | MX23_PAD_LCD_D00__LCD_D00 0x1000 | ||
639 | MX23_PAD_LCD_D01__LCD_D01 0x1010 | ||
640 | MX23_PAD_LCD_D02__LCD_D02 0x1020 | ||
641 | MX23_PAD_LCD_D03__LCD_D03 0x1030 | ||
642 | MX23_PAD_LCD_D04__LCD_D04 0x1040 | ||
643 | MX23_PAD_LCD_D05__LCD_D05 0x1050 | ||
644 | MX23_PAD_LCD_D06__LCD_D06 0x1060 | ||
645 | MX23_PAD_LCD_D07__LCD_D07 0x1070 | ||
646 | MX23_PAD_LCD_D08__LCD_D08 0x1080 | ||
647 | MX23_PAD_LCD_D09__LCD_D09 0x1090 | ||
648 | MX23_PAD_LCD_D10__LCD_D10 0x10a0 | ||
649 | MX23_PAD_LCD_D11__LCD_D11 0x10b0 | ||
650 | MX23_PAD_LCD_D12__LCD_D12 0x10c0 | ||
651 | MX23_PAD_LCD_D13__LCD_D13 0x10d0 | ||
652 | MX23_PAD_LCD_D14__LCD_D14 0x10e0 | ||
653 | MX23_PAD_LCD_D15__LCD_D15 0x10f0 | ||
654 | MX23_PAD_LCD_D16__LCD_D16 0x1100 | ||
655 | MX23_PAD_LCD_D17__LCD_D17 0x1110 | ||
656 | MX23_PAD_LCD_RESET__LCD_RESET 0x1120 | ||
657 | MX23_PAD_LCD_RS__LCD_RS 0x1130 | ||
658 | MX23_PAD_LCD_WR__LCD_WR 0x1140 | ||
659 | MX23_PAD_LCD_CS__LCD_CS 0x1150 | ||
660 | MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 | ||
661 | MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 | ||
662 | MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 | ||
663 | MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 | ||
664 | MX23_PAD_PWM0__PWM0 0x11a0 | ||
665 | MX23_PAD_PWM1__PWM1 0x11b0 | ||
666 | MX23_PAD_PWM2__PWM2 0x11c0 | ||
667 | MX23_PAD_PWM3__PWM3 0x11d0 | ||
668 | MX23_PAD_PWM4__PWM4 0x11e0 | ||
669 | MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 | ||
670 | MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 | ||
671 | MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 | ||
672 | MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 | ||
673 | MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 | ||
674 | MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 | ||
675 | MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 | ||
676 | MX23_PAD_ROTARYA__ROTARYA 0x2070 | ||
677 | MX23_PAD_ROTARYB__ROTARYB 0x2080 | ||
678 | MX23_PAD_EMI_A00__EMI_A00 0x2090 | ||
679 | MX23_PAD_EMI_A01__EMI_A01 0x20a0 | ||
680 | MX23_PAD_EMI_A02__EMI_A02 0x20b0 | ||
681 | MX23_PAD_EMI_A03__EMI_A03 0x20c0 | ||
682 | MX23_PAD_EMI_A04__EMI_A04 0x20d0 | ||
683 | MX23_PAD_EMI_A05__EMI_A05 0x20e0 | ||
684 | MX23_PAD_EMI_A06__EMI_A06 0x20f0 | ||
685 | MX23_PAD_EMI_A07__EMI_A07 0x2100 | ||
686 | MX23_PAD_EMI_A08__EMI_A08 0x2110 | ||
687 | MX23_PAD_EMI_A09__EMI_A09 0x2120 | ||
688 | MX23_PAD_EMI_A10__EMI_A10 0x2130 | ||
689 | MX23_PAD_EMI_A11__EMI_A11 0x2140 | ||
690 | MX23_PAD_EMI_A12__EMI_A12 0x2150 | ||
691 | MX23_PAD_EMI_BA0__EMI_BA0 0x2160 | ||
692 | MX23_PAD_EMI_BA1__EMI_BA1 0x2170 | ||
693 | MX23_PAD_EMI_CASN__EMI_CASN 0x2180 | ||
694 | MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 | ||
695 | MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 | ||
696 | MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 | ||
697 | MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 | ||
698 | MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 | ||
699 | MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 | ||
700 | MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 | ||
701 | MX23_PAD_EMI_D00__EMI_D00 0x3000 | ||
702 | MX23_PAD_EMI_D01__EMI_D01 0x3010 | ||
703 | MX23_PAD_EMI_D02__EMI_D02 0x3020 | ||
704 | MX23_PAD_EMI_D03__EMI_D03 0x3030 | ||
705 | MX23_PAD_EMI_D04__EMI_D04 0x3040 | ||
706 | MX23_PAD_EMI_D05__EMI_D05 0x3050 | ||
707 | MX23_PAD_EMI_D06__EMI_D06 0x3060 | ||
708 | MX23_PAD_EMI_D07__EMI_D07 0x3070 | ||
709 | MX23_PAD_EMI_D08__EMI_D08 0x3080 | ||
710 | MX23_PAD_EMI_D09__EMI_D09 0x3090 | ||
711 | MX23_PAD_EMI_D10__EMI_D10 0x30a0 | ||
712 | MX23_PAD_EMI_D11__EMI_D11 0x30b0 | ||
713 | MX23_PAD_EMI_D12__EMI_D12 0x30c0 | ||
714 | MX23_PAD_EMI_D13__EMI_D13 0x30d0 | ||
715 | MX23_PAD_EMI_D14__EMI_D14 0x30e0 | ||
716 | MX23_PAD_EMI_D15__EMI_D15 0x30f0 | ||
717 | MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 | ||
718 | MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 | ||
719 | MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 | ||
720 | MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 | ||
721 | MX23_PAD_EMI_CLK__EMI_CLK 0x3140 | ||
722 | MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 | ||
723 | MX23_PAD_GPMI_D00__LCD_D8 0x0001 | ||
724 | MX23_PAD_GPMI_D01__LCD_D9 0x0011 | ||
725 | MX23_PAD_GPMI_D02__LCD_D10 0x0021 | ||
726 | MX23_PAD_GPMI_D03__LCD_D11 0x0031 | ||
727 | MX23_PAD_GPMI_D04__LCD_D12 0x0041 | ||
728 | MX23_PAD_GPMI_D05__LCD_D13 0x0051 | ||
729 | MX23_PAD_GPMI_D06__LCD_D14 0x0061 | ||
730 | MX23_PAD_GPMI_D07__LCD_D15 0x0071 | ||
731 | MX23_PAD_GPMI_D08__LCD_D18 0x0081 | ||
732 | MX23_PAD_GPMI_D09__LCD_D19 0x0091 | ||
733 | MX23_PAD_GPMI_D10__LCD_D20 0x00a1 | ||
734 | MX23_PAD_GPMI_D11__LCD_D21 0x00b1 | ||
735 | MX23_PAD_GPMI_D12__LCD_D22 0x00c1 | ||
736 | MX23_PAD_GPMI_D13__LCD_D23 0x00d1 | ||
737 | MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 | ||
738 | MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 | ||
739 | MX23_PAD_GPMI_CLE__LCD_D16 0x0101 | ||
740 | MX23_PAD_GPMI_ALE__LCD_D17 0x0111 | ||
741 | MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 | ||
742 | MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 | ||
743 | MX23_PAD_AUART1_RX__IR_RX 0x01c1 | ||
744 | MX23_PAD_AUART1_TX__IR_TX 0x01d1 | ||
745 | MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 | ||
746 | MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 | ||
747 | MX23_PAD_LCD_D00__ETM_DA8 0x1001 | ||
748 | MX23_PAD_LCD_D01__ETM_DA9 0x1011 | ||
749 | MX23_PAD_LCD_D02__ETM_DA10 0x1021 | ||
750 | MX23_PAD_LCD_D03__ETM_DA11 0x1031 | ||
751 | MX23_PAD_LCD_D04__ETM_DA12 0x1041 | ||
752 | MX23_PAD_LCD_D05__ETM_DA13 0x1051 | ||
753 | MX23_PAD_LCD_D06__ETM_DA14 0x1061 | ||
754 | MX23_PAD_LCD_D07__ETM_DA15 0x1071 | ||
755 | MX23_PAD_LCD_D08__ETM_DA0 0x1081 | ||
756 | MX23_PAD_LCD_D09__ETM_DA1 0x1091 | ||
757 | MX23_PAD_LCD_D10__ETM_DA2 0x10a1 | ||
758 | MX23_PAD_LCD_D11__ETM_DA3 0x10b1 | ||
759 | MX23_PAD_LCD_D12__ETM_DA4 0x10c1 | ||
760 | MX23_PAD_LCD_D13__ETM_DA5 0x10d1 | ||
761 | MX23_PAD_LCD_D14__ETM_DA6 0x10e1 | ||
762 | MX23_PAD_LCD_D15__ETM_DA7 0x10f1 | ||
763 | MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 | ||
764 | MX23_PAD_LCD_RS__ETM_TCLK 0x1131 | ||
765 | MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 | ||
766 | MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 | ||
767 | MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 | ||
768 | MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 | ||
769 | MX23_PAD_PWM0__ROTARYA 0x11a1 | ||
770 | MX23_PAD_PWM1__ROTARYB 0x11b1 | ||
771 | MX23_PAD_PWM2__GPMI_RDY3 0x11c1 | ||
772 | MX23_PAD_PWM3__ETM_TCTL 0x11d1 | ||
773 | MX23_PAD_PWM4__ETM_TCLK 0x11e1 | ||
774 | MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 | ||
775 | MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 | ||
776 | MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 | ||
777 | MX23_PAD_ROTARYA__AUART2_RTS 0x2071 | ||
778 | MX23_PAD_ROTARYB__AUART2_CTS 0x2081 | ||
779 | MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 | ||
780 | MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 | ||
781 | MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 | ||
782 | MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 | ||
783 | MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 | ||
784 | MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 | ||
785 | MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 | ||
786 | MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 | ||
787 | MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 | ||
788 | MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 | ||
789 | MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 | ||
790 | MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 | ||
791 | MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 | ||
792 | MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 | ||
793 | MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 | ||
794 | MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 | ||
795 | MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 | ||
796 | MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 | ||
797 | MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 | ||
798 | MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 | ||
799 | MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 | ||
800 | MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 | ||
801 | MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 | ||
802 | MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 | ||
803 | MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 | ||
804 | MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 | ||
805 | MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 | ||
806 | MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 | ||
807 | MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 | ||
808 | MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 | ||
809 | MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 | ||
810 | MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 | ||
811 | MX23_PAD_PWM0__DUART_RX 0x11a2 | ||
812 | MX23_PAD_PWM1__DUART_TX 0x11b2 | ||
813 | MX23_PAD_PWM3__AUART1_CTS 0x11d2 | ||
814 | MX23_PAD_PWM4__AUART1_RTS 0x11e2 | ||
815 | MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 | ||
816 | MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 | ||
817 | MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 | ||
818 | MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 | ||
819 | MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 | ||
820 | MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 | ||
821 | MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 | ||
822 | MX23_PAD_ROTARYA__SPDIF 0x2072 | ||
823 | MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 | ||
824 | MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 | ||
825 | MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 | ||
826 | MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 | ||
827 | MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 | ||
828 | MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 | ||
829 | MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 | ||
830 | MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 | ||
831 | MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 | ||
832 | MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 | ||
833 | MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 | ||
834 | MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 | ||
835 | MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 | ||
836 | MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 | ||
837 | MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 | ||
838 | MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 | ||
839 | MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 | ||
840 | MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 | ||
841 | MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 | ||
842 | MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 | ||
843 | MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 | ||
844 | MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 | ||
845 | MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 | ||
846 | MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 | ||
847 | MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 | ||
848 | MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 | ||
849 | MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 | ||
850 | MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 | ||
851 | MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 | ||
852 | MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 | ||
853 | MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 | ||
854 | MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 | ||
855 | MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 | ||
856 | MX23_PAD_LCD_D00__GPIO_1_0 0x1003 | ||
857 | MX23_PAD_LCD_D01__GPIO_1_1 0x1013 | ||
858 | MX23_PAD_LCD_D02__GPIO_1_2 0x1023 | ||
859 | MX23_PAD_LCD_D03__GPIO_1_3 0x1033 | ||
860 | MX23_PAD_LCD_D04__GPIO_1_4 0x1043 | ||
861 | MX23_PAD_LCD_D05__GPIO_1_5 0x1053 | ||
862 | MX23_PAD_LCD_D06__GPIO_1_6 0x1063 | ||
863 | MX23_PAD_LCD_D07__GPIO_1_7 0x1073 | ||
864 | MX23_PAD_LCD_D08__GPIO_1_8 0x1083 | ||
865 | MX23_PAD_LCD_D09__GPIO_1_9 0x1093 | ||
866 | MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 | ||
867 | MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 | ||
868 | MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 | ||
869 | MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 | ||
870 | MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 | ||
871 | MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 | ||
872 | MX23_PAD_LCD_D16__GPIO_1_16 0x1103 | ||
873 | MX23_PAD_LCD_D17__GPIO_1_17 0x1113 | ||
874 | MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 | ||
875 | MX23_PAD_LCD_RS__GPIO_1_19 0x1133 | ||
876 | MX23_PAD_LCD_WR__GPIO_1_20 0x1143 | ||
877 | MX23_PAD_LCD_CS__GPIO_1_21 0x1153 | ||
878 | MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 | ||
879 | MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 | ||
880 | MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 | ||
881 | MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 | ||
882 | MX23_PAD_PWM0__GPIO_1_26 0x11a3 | ||
883 | MX23_PAD_PWM1__GPIO_1_27 0x11b3 | ||
884 | MX23_PAD_PWM2__GPIO_1_28 0x11c3 | ||
885 | MX23_PAD_PWM3__GPIO_1_29 0x11d3 | ||
886 | MX23_PAD_PWM4__GPIO_1_30 0x11e3 | ||
887 | MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 | ||
888 | MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 | ||
889 | MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 | ||
890 | MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 | ||
891 | MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 | ||
892 | MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 | ||
893 | MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 | ||
894 | MX23_PAD_ROTARYA__GPIO_2_7 0x2073 | ||
895 | MX23_PAD_ROTARYB__GPIO_2_8 0x2083 | ||
896 | MX23_PAD_EMI_A00__GPIO_2_9 0x2093 | ||
897 | MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 | ||
898 | MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 | ||
899 | MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 | ||
900 | MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 | ||
901 | MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 | ||
902 | MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 | ||
903 | MX23_PAD_EMI_A07__GPIO_2_16 0x2103 | ||
904 | MX23_PAD_EMI_A08__GPIO_2_17 0x2113 | ||
905 | MX23_PAD_EMI_A09__GPIO_2_18 0x2123 | ||
906 | MX23_PAD_EMI_A10__GPIO_2_19 0x2133 | ||
907 | MX23_PAD_EMI_A11__GPIO_2_20 0x2143 | ||
908 | MX23_PAD_EMI_A12__GPIO_2_21 0x2153 | ||
909 | MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 | ||
910 | MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 | ||
911 | MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 | ||
912 | MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 | ||
913 | MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 | ||
914 | MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 | ||
915 | MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 | ||
916 | MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 | ||
917 | MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 | ||
918 | MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt deleted file mode 100644 index daa76895606..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt +++ /dev/null | |||
@@ -1,83 +0,0 @@ | |||
1 | Lantiq FALCON pinmux controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "lantiq,pinctrl-falcon" | ||
5 | - reg: Should contain the physical address and length of the gpio/pinmux | ||
6 | register range | ||
7 | |||
8 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
9 | common pinctrl bindings used by client devices, including the meaning of the | ||
10 | phrase "pin configuration node". | ||
11 | |||
12 | Lantiq's pin configuration nodes act as a container for an abitrary number of | ||
13 | subnodes. Each of these subnodes represents some desired configuration for a | ||
14 | pin, a group, or a list of pins or groups. This configuration can include the | ||
15 | mux function to select on those group(s), and two pin configuration parameters: | ||
16 | pull-up and open-drain | ||
17 | |||
18 | The name of each subnode is not important as long as it is unique; all subnodes | ||
19 | should be enumerated and processed purely based on their content. | ||
20 | |||
21 | Each subnode only affects those parameters that are explicitly listed. In | ||
22 | other words, a subnode that lists a mux function but no pin configuration | ||
23 | parameters implies no information about any pin configuration parameters. | ||
24 | Similarly, a pin subnode that describes a pullup parameter implies no | ||
25 | information about e.g. the mux function. | ||
26 | |||
27 | We support 2 types of nodes. | ||
28 | |||
29 | Definition of mux function groups: | ||
30 | |||
31 | Required subnode-properties: | ||
32 | - lantiq,groups : An array of strings. Each string contains the name of a group. | ||
33 | Valid values for these names are listed below. | ||
34 | - lantiq,function: A string containing the name of the function to mux to the | ||
35 | group. Valid values for function names are listed below. | ||
36 | |||
37 | Valid values for group and function names: | ||
38 | |||
39 | mux groups: | ||
40 | por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c, | ||
41 | jtag, slic, pcm, asc1 | ||
42 | |||
43 | functions: | ||
44 | rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm | ||
45 | |||
46 | |||
47 | Definition of pin configurations: | ||
48 | |||
49 | Required subnode-properties: | ||
50 | - lantiq,pins : An array of strings. Each string contains the name of a pin. | ||
51 | Valid values for these names are listed below. | ||
52 | |||
53 | Optional subnode-properties: | ||
54 | - lantiq,pull: Integer, representing the pull-down/up to apply to the pin. | ||
55 | 0: none, 1: down | ||
56 | - lantiq,drive-current: Boolean, enables drive-current | ||
57 | - lantiq,slew-rate: Boolean, enables slew-rate | ||
58 | |||
59 | Example: | ||
60 | pinmux0 { | ||
61 | compatible = "lantiq,pinctrl-falcon"; | ||
62 | pinctrl-names = "default"; | ||
63 | pinctrl-0 = <&state_default>; | ||
64 | |||
65 | state_default: pinmux { | ||
66 | asc0 { | ||
67 | lantiq,groups = "asc0"; | ||
68 | lantiq,function = "asc"; | ||
69 | }; | ||
70 | ntr { | ||
71 | lantiq,groups = "ntr8k"; | ||
72 | lantiq,function = "ntr"; | ||
73 | }; | ||
74 | i2c { | ||
75 | lantiq,groups = "i2c"; | ||
76 | lantiq,function = "i2c"; | ||
77 | }; | ||
78 | hrst { | ||
79 | lantiq,groups = "hrst"; | ||
80 | lantiq,function = "rst"; | ||
81 | }; | ||
82 | }; | ||
83 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt deleted file mode 100644 index b5469db1d7a..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt +++ /dev/null | |||
@@ -1,97 +0,0 @@ | |||
1 | Lantiq XWAY pinmux controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9" | ||
5 | - reg: Should contain the physical address and length of the gpio/pinmux | ||
6 | register range | ||
7 | |||
8 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
9 | common pinctrl bindings used by client devices, including the meaning of the | ||
10 | phrase "pin configuration node". | ||
11 | |||
12 | Lantiq's pin configuration nodes act as a container for an abitrary number of | ||
13 | subnodes. Each of these subnodes represents some desired configuration for a | ||
14 | pin, a group, or a list of pins or groups. This configuration can include the | ||
15 | mux function to select on those group(s), and two pin configuration parameters: | ||
16 | pull-up and open-drain | ||
17 | |||
18 | The name of each subnode is not important as long as it is unique; all subnodes | ||
19 | should be enumerated and processed purely based on their content. | ||
20 | |||
21 | Each subnode only affects those parameters that are explicitly listed. In | ||
22 | other words, a subnode that lists a mux function but no pin configuration | ||
23 | parameters implies no information about any pin configuration parameters. | ||
24 | Similarly, a pin subnode that describes a pullup parameter implies no | ||
25 | information about e.g. the mux function. | ||
26 | |||
27 | We support 2 types of nodes. | ||
28 | |||
29 | Definition of mux function groups: | ||
30 | |||
31 | Required subnode-properties: | ||
32 | - lantiq,groups : An array of strings. Each string contains the name of a group. | ||
33 | Valid values for these names are listed below. | ||
34 | - lantiq,function: A string containing the name of the function to mux to the | ||
35 | group. Valid values for function names are listed below. | ||
36 | |||
37 | Valid values for group and function names: | ||
38 | |||
39 | mux groups: | ||
40 | exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, | ||
41 | ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, | ||
42 | spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2, | ||
43 | gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, | ||
44 | req3 | ||
45 | |||
46 | additional mux groups (XR9 only): | ||
47 | mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4 | ||
48 | |||
49 | functions: | ||
50 | spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio | ||
51 | |||
52 | |||
53 | |||
54 | Definition of pin configurations: | ||
55 | |||
56 | Required subnode-properties: | ||
57 | - lantiq,pins : An array of strings. Each string contains the name of a pin. | ||
58 | Valid values for these names are listed below. | ||
59 | |||
60 | Optional subnode-properties: | ||
61 | - lantiq,pull: Integer, representing the pull-down/up to apply to the pin. | ||
62 | 0: none, 1: down, 2: up. | ||
63 | - lantiq,open-drain: Boolean, enables open-drain on the defined pin. | ||
64 | |||
65 | Valid values for XWAY pin names: | ||
66 | Pinconf pins can be referenced via the names io0-io31. | ||
67 | |||
68 | Valid values for XR9 pin names: | ||
69 | Pinconf pins can be referenced via the names io0-io55. | ||
70 | |||
71 | Example: | ||
72 | gpio: pinmux@E100B10 { | ||
73 | compatible = "lantiq,pinctrl-xway"; | ||
74 | pinctrl-names = "default"; | ||
75 | pinctrl-0 = <&state_default>; | ||
76 | |||
77 | #gpio-cells = <2>; | ||
78 | gpio-controller; | ||
79 | reg = <0xE100B10 0xA0>; | ||
80 | |||
81 | state_default: pinmux { | ||
82 | stp { | ||
83 | lantiq,groups = "stp"; | ||
84 | lantiq,function = "stp"; | ||
85 | }; | ||
86 | pci { | ||
87 | lantiq,groups = "gnt1"; | ||
88 | lantiq,function = "pci"; | ||
89 | }; | ||
90 | conf_out { | ||
91 | lantiq,pins = "io4", "io5", "io6"; /* stp */ | ||
92 | lantiq,open-drain; | ||
93 | lantiq,pull = <0>; | ||
94 | }; | ||
95 | }; | ||
96 | }; | ||
97 | |||
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt deleted file mode 100644 index 01ef408e205..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +++ /dev/null | |||
@@ -1,95 +0,0 @@ | |||
1 | * Marvell Armada 370 SoC pinctrl driver for mpp | ||
2 | |||
3 | Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding | ||
4 | part and usage. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "marvell,88f6710-pinctrl" | ||
8 | |||
9 | Available mpp pins/groups and functions: | ||
10 | Note: brackets (x) are not part of the mpp name for marvell,function and given | ||
11 | only for more detailed description in this document. | ||
12 | |||
13 | name pins functions | ||
14 | ================================================================================ | ||
15 | mpp0 0 gpio, uart0(rxd) | ||
16 | mpp1 1 gpo, uart0(txd) | ||
17 | mpp2 2 gpio, i2c0(sck), uart0(txd) | ||
18 | mpp3 3 gpio, i2c0(sda), uart0(rxd) | ||
19 | mpp4 4 gpio, cpu_pd(vdd) | ||
20 | mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk) | ||
21 | mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) | ||
22 | mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk) | ||
23 | mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) | ||
24 | mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo) | ||
25 | mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi) | ||
26 | mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1), | ||
27 | sata1(prsnt), spi1(cs1) | ||
28 | mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0), | ||
29 | audio(spdifi) | ||
30 | mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk), | ||
31 | audio(rmclk) | ||
32 | mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi), | ||
33 | spi0(cs2) | ||
34 | mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso), | ||
35 | spi0(cs3) | ||
36 | mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk) | ||
37 | mpp17 17 gpo, ge(mdc) | ||
38 | mpp18 18 gpio, ge(mdio) | ||
39 | mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk) | ||
40 | mpp20 20 gpo, ge0(txd4), ge1(txd0) | ||
41 | mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd) | ||
42 | mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts) | ||
43 | mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi) | ||
44 | mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0) | ||
45 | mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd) | ||
46 | mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso) | ||
47 | mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts) | ||
48 | mpp28 28 gpio, ge0(rxd5), ge1(rxd3) | ||
49 | mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda) | ||
50 | mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck) | ||
51 | mpp31 31 gpio, tclk, ge0(txerr) | ||
52 | mpp32 32 gpio, spi0(cs0) | ||
53 | mpp33 33 gpio, dev(bootcs), spi0(cs0) | ||
54 | mpp34 34 gpo, dev(wen0), spi0(mosi) | ||
55 | mpp35 35 gpo, dev(oen), spi0(sck) | ||
56 | mpp36 36 gpo, dev(a1), spi0(miso) | ||
57 | mpp37 37 gpo, dev(a0), sata0(prsnt) | ||
58 | mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts) | ||
59 | mpp39 39 gpo, dev(ad0), audio(spdifo) | ||
60 | mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts) | ||
61 | mpp41 41 gpio, dev(ad2), uart1(rxd) | ||
62 | mpp42 42 gpo, dev(ad3), uart1(txd) | ||
63 | mpp43 43 gpo, dev(ad4), audio(bclk) | ||
64 | mpp44 44 gpo, dev(ad5), audio(mclk) | ||
65 | mpp45 45 gpo, dev(ad6), audio(lrclk) | ||
66 | mpp46 46 gpo, dev(ad7), audio(sdo) | ||
67 | mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo) | ||
68 | mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt), | ||
69 | spi0(cs1) | ||
70 | mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0), | ||
71 | audio(spdifi) | ||
72 | mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso), | ||
73 | audio(rmclk) | ||
74 | mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi) | ||
75 | mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck) | ||
76 | mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2), | ||
77 | pcie(clkreq1) | ||
78 | mpp54 54 gpo, dev(ad15), tdm(dtx) | ||
79 | mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt), | ||
80 | sata0(prsnt) | ||
81 | mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3), | ||
82 | pcie(clkreq0), spi1(cs1) | ||
83 | mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt), | ||
84 | audio(sdo) | ||
85 | mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), | ||
86 | uart0(rts) | ||
87 | mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) | ||
88 | mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out), | ||
89 | audio(sdi) | ||
90 | mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk) | ||
91 | mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), | ||
92 | audio(mclk), uart0(cts) | ||
93 | mpp63 63 gpo, spi0(sck), tclk | ||
94 | mpp64 64 gpio, spi0(miso), spi0-1(cs1) | ||
95 | mpp65 65 gpio, spi0(mosi), spi0-1(cs2) | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt deleted file mode 100644 index bfa0a2e5e0c..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +++ /dev/null | |||
@@ -1,100 +0,0 @@ | |||
1 | * Marvell Armada XP SoC pinctrl driver for mpp | ||
2 | |||
3 | Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding | ||
4 | part and usage. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl", | ||
8 | "marvell,mv78460-pinctrl" | ||
9 | |||
10 | This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460. | ||
11 | |||
12 | Available mpp pins/groups and functions: | ||
13 | Note: brackets (x) are not part of the mpp name for marvell,function and given | ||
14 | only for more detailed description in this document. | ||
15 | |||
16 | * Marvell Armada XP (all variants) | ||
17 | |||
18 | name pins functions | ||
19 | ================================================================================ | ||
20 | mpp0 0 gpio, ge0(txclko), lcd(d0) | ||
21 | mpp1 1 gpio, ge0(txd0), lcd(d1) | ||
22 | mpp2 2 gpio, ge0(txd1), lcd(d2) | ||
23 | mpp3 3 gpio, ge0(txd2), lcd(d3) | ||
24 | mpp4 4 gpio, ge0(txd3), lcd(d4) | ||
25 | mpp5 5 gpio, ge0(txctl), lcd(d5) | ||
26 | mpp6 6 gpio, ge0(rxd0), lcd(d6) | ||
27 | mpp7 7 gpio, ge0(rxd1), lcd(d7) | ||
28 | mpp8 8 gpio, ge0(rxd2), lcd(d8) | ||
29 | mpp9 9 gpio, ge0(rxd3), lcd(d9) | ||
30 | mpp10 10 gpio, ge0(rxctl), lcd(d10) | ||
31 | mpp11 11 gpio, ge0(rxclk), lcd(d11) | ||
32 | mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12) | ||
33 | mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13) | ||
34 | mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15) | ||
35 | mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16) | ||
36 | mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16) | ||
37 | mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) | ||
38 | mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) | ||
39 | mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) | ||
40 | mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) | ||
41 | mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) | ||
42 | mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) | ||
43 | mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) | ||
44 | mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst) | ||
45 | mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk) | ||
46 | mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) | ||
47 | mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) | ||
48 | mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) | ||
49 | mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd) | ||
50 | mpp30 30 gpio, tdm(int1), sd0(clk) | ||
51 | mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd) | ||
52 | mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd) | ||
53 | mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) | ||
54 | mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) | ||
55 | mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) | ||
56 | mpp36 36 gpio, spi(mosi) | ||
57 | mpp37 37 gpio, spi(miso) | ||
58 | mpp38 38 gpio, spi(sck) | ||
59 | mpp39 39 gpio, spi(cs0) | ||
60 | mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd), | ||
61 | pcie(clkreq0) | ||
62 | mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), | ||
63 | pcie(clkreq1) | ||
64 | mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer), | ||
65 | vdd(cpu0-pd) | ||
66 | mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout), | ||
67 | vdd(cpu2-3-pd){1} | ||
68 | mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), | ||
69 | mem(bat) | ||
70 | mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) | ||
71 | mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) | ||
72 | mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), | ||
73 | ref(clkout) | ||
74 | mpp48 48 gpio, tclk, dev(burst/last) | ||
75 | |||
76 | * Marvell Armada XP (mv78260 and mv78460 only) | ||
77 | |||
78 | name pins functions | ||
79 | ================================================================================ | ||
80 | mpp49 49 gpio, dev(we3) | ||
81 | mpp50 50 gpio, dev(we2) | ||
82 | mpp51 51 gpio, dev(ad16) | ||
83 | mpp52 52 gpio, dev(ad17) | ||
84 | mpp53 53 gpio, dev(ad18) | ||
85 | mpp54 54 gpio, dev(ad19) | ||
86 | mpp55 55 gpio, dev(ad20), vdd(cpu0-pd) | ||
87 | mpp56 56 gpio, dev(ad21), vdd(cpu1-pd) | ||
88 | mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1} | ||
89 | mpp58 58 gpio, dev(ad23) | ||
90 | mpp59 59 gpio, dev(ad24) | ||
91 | mpp60 60 gpio, dev(ad25) | ||
92 | mpp61 61 gpio, dev(ad26) | ||
93 | mpp62 62 gpio, dev(ad27) | ||
94 | mpp63 63 gpio, dev(ad28) | ||
95 | mpp64 64 gpio, dev(ad29) | ||
96 | mpp65 65 gpio, dev(ad30) | ||
97 | mpp66 66 gpio, dev(ad31) | ||
98 | |||
99 | Notes: | ||
100 | * {1} vdd(cpu2-3-pd) only available on mv78460. | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt deleted file mode 100644 index a648aaad611..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt +++ /dev/null | |||
@@ -1,72 +0,0 @@ | |||
1 | * Marvell Dove SoC pinctrl driver for mpp | ||
2 | |||
3 | Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding | ||
4 | part and usage. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "marvell,dove-pinctrl" | ||
8 | - clocks: (optional) phandle of pdma clock | ||
9 | |||
10 | Available mpp pins/groups and functions: | ||
11 | Note: brackets (x) are not part of the mpp name for marvell,function and given | ||
12 | only for more detailed description in this document. | ||
13 | |||
14 | name pins functions | ||
15 | ================================================================================ | ||
16 | mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm) | ||
17 | mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm) | ||
18 | mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt), | ||
19 | uart1(rts) | ||
20 | mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act), | ||
21 | uart1(cts), lcd-spi(cs1) | ||
22 | mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso) | ||
23 | mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs) | ||
24 | mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi) | ||
25 | mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck) | ||
26 | mpp8 8 gpio, pmu, watchdog(rstout) | ||
27 | mpp9 9 gpio, pmu, pex1(clkreq) | ||
28 | mpp10 10 gpio, pmu, ssp(sclk) | ||
29 | mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl), | ||
30 | sdio1(ledctrl), pex0(clkreq) | ||
31 | mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act) | ||
32 | mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp), | ||
33 | ssp(extclk) | ||
34 | mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd) | ||
35 | mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm) | ||
36 | mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1) | ||
37 | mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda), | ||
38 | ac97-1(sysclko) | ||
39 | mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm) | ||
40 | mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck) | ||
41 | mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso), | ||
42 | ac97(sysclko) | ||
43 | mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0), | ||
44 | uart1(cts), ssp(sfrm) | ||
45 | mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi), | ||
46 | lcd-spi(mosi), uart1(cts), ssp(txd) | ||
47 | mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck), | ||
48 | lcd-spi(sck), ssp(sclk) | ||
49 | mpp_camera 24-39 gpio, camera | ||
50 | mpp_sdio0 40-45 gpio, sdio0 | ||
51 | mpp_sdio1 46-51 gpio, sdio1 | ||
52 | mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp, | ||
53 | ssp/twsi | ||
54 | mpp_spi0 58-61 gpio, spi0 | ||
55 | mpp_uart1 62-63 gpio, uart1 | ||
56 | mpp_nand 64-71 gpo, nand | ||
57 | audio0 - i2s, ac97 | ||
58 | twsi - none, opt1, opt2, opt3 | ||
59 | |||
60 | Notes: | ||
61 | * group "mpp_audio1" allows the following functions and gpio pins: | ||
62 | - gpio : gpio on pins 52-57 | ||
63 | - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios | ||
64 | - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57 | ||
65 | - spdifo : spdifo on pin 57, gpio on pins 52-55 | ||
66 | - twsi : twsi on pins 56,57, gpio on pins 52-55 | ||
67 | - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios | ||
68 | - ssp : ssp on pins 52-55, gpio on pins 56,57 | ||
69 | - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios | ||
70 | * group "audio0" internally muxes i2s0 or ac97 controller to the dedicated | ||
71 | audio0 pins. | ||
72 | * group "twsi" internally muxes twsi controller to the dedicated or option pins. | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt deleted file mode 100644 index 95daf6335c3..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt +++ /dev/null | |||
@@ -1,318 +0,0 @@ | |||
1 | * Marvell Kirkwood SoC pinctrl driver for mpp | ||
2 | |||
3 | Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding | ||
4 | part and usage. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "marvell,88f6180-pinctrl", | ||
8 | "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", | ||
9 | "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl" | ||
10 | "marvell,98dx4122-pinctrl" | ||
11 | |||
12 | This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x. | ||
13 | It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs. | ||
14 | |||
15 | Available mpp pins/groups and functions: | ||
16 | Note: brackets (x) are not part of the mpp name for marvell,function and given | ||
17 | only for more detailed description in this document. | ||
18 | |||
19 | * Marvell Kirkwood 88f6180 | ||
20 | |||
21 | name pins functions | ||
22 | ================================================================================ | ||
23 | mpp0 0 gpio, nand(io2), spi(cs) | ||
24 | mpp1 1 gpo, nand(io3), spi(mosi) | ||
25 | mpp2 2 gpo, nand(io4), spi(sck) | ||
26 | mpp3 3 gpo, nand(io5), spi(miso) | ||
27 | mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk) | ||
28 | mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig) | ||
29 | mpp6 6 sysrst(out), spi(mosi), ptp(trig) | ||
30 | mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) | ||
31 | mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), | ||
32 | mii(col) | ||
33 | mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), | ||
34 | mii(crs) | ||
35 | mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig) | ||
36 | mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), | ||
37 | ptp-2(trig) | ||
38 | mpp12 12 gpo, sdio(clk) | ||
39 | mpp13 13 gpio, sdio(cmd), uart1(txd) | ||
40 | mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col) | ||
41 | mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd) | ||
42 | mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) | ||
43 | mpp17 17 gpio, sdio(d3) | ||
44 | mpp18 18 gpo, nand(io0) | ||
45 | mpp19 19 gpo, nand(io1) | ||
46 | mpp20 20 gpio, mii(rxerr) | ||
47 | mpp21 21 gpio, audio(spdifi) | ||
48 | mpp22 22 gpio, audio(spdifo) | ||
49 | mpp23 23 gpio, audio(rmclk) | ||
50 | mpp24 24 gpio, audio(bclk) | ||
51 | mpp25 25 gpio, audio(sdo) | ||
52 | mpp26 26 gpio, audio(lrclk) | ||
53 | mpp27 27 gpio, audio(mclk) | ||
54 | mpp28 28 gpio, audio(sdi) | ||
55 | mpp29 29 gpio, audio(extclk) | ||
56 | |||
57 | * Marvell Kirkwood 88f6190 | ||
58 | |||
59 | name pins functions | ||
60 | ================================================================================ | ||
61 | mpp0 0 gpio, nand(io2), spi(cs) | ||
62 | mpp1 1 gpo, nand(io3), spi(mosi) | ||
63 | mpp2 2 gpo, nand(io4), spi(sck) | ||
64 | mpp3 3 gpo, nand(io5), spi(miso) | ||
65 | mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk) | ||
66 | mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) | ||
67 | mpp6 6 sysrst(out), spi(mosi), ptp(trig) | ||
68 | mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) | ||
69 | mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), | ||
70 | mii(col), mii-1(rxerr) | ||
71 | mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), | ||
72 | mii(crs), sata0(prsnt) | ||
73 | mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig) | ||
74 | mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), | ||
75 | ptp-2(trig), sata0(act) | ||
76 | mpp12 12 gpo, sdio(clk) | ||
77 | mpp13 13 gpio, sdio(cmd), uart1(txd) | ||
78 | mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col) | ||
79 | mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) | ||
80 | mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) | ||
81 | mpp17 17 gpio, sdio(d3), sata0(prsnt) | ||
82 | mpp18 18 gpo, nand(io0) | ||
83 | mpp19 19 gpo, nand(io1) | ||
84 | mpp20 20 gpio, ge1(txd0) | ||
85 | mpp21 21 gpio, ge1(txd1), sata0(act) | ||
86 | mpp22 22 gpio, ge1(txd2) | ||
87 | mpp23 23 gpio, ge1(txd3), sata0(prsnt) | ||
88 | mpp24 24 gpio, ge1(rxd0) | ||
89 | mpp25 25 gpio, ge1(rxd1) | ||
90 | mpp26 26 gpio, ge1(rxd2) | ||
91 | mpp27 27 gpio, ge1(rxd3) | ||
92 | mpp28 28 gpio, ge1(col) | ||
93 | mpp29 29 gpio, ge1(txclk) | ||
94 | mpp30 30 gpio, ge1(rxclk) | ||
95 | mpp31 31 gpio, ge1(rxclk) | ||
96 | mpp32 32 gpio, ge1(txclko) | ||
97 | mpp33 33 gpo, ge1(txclk) | ||
98 | mpp34 34 gpio, ge1(txen) | ||
99 | mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr) | ||
100 | |||
101 | * Marvell Kirkwood 88f6192 | ||
102 | |||
103 | name pins functions | ||
104 | ================================================================================ | ||
105 | mpp0 0 gpio, nand(io2), spi(cs) | ||
106 | mpp1 1 gpo, nand(io3), spi(mosi) | ||
107 | mpp2 2 gpo, nand(io4), spi(sck) | ||
108 | mpp3 3 gpo, nand(io5), spi(miso) | ||
109 | mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act) | ||
110 | mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) | ||
111 | mpp6 6 sysrst(out), spi(mosi), ptp(trig) | ||
112 | mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) | ||
113 | mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), | ||
114 | mii(col), mii-1(rxerr), sata1(prsnt) | ||
115 | mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), | ||
116 | mii(crs), sata0(prsnt) | ||
117 | mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act) | ||
118 | mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), | ||
119 | ptp-2(trig), sata0(act) | ||
120 | mpp12 12 gpo, sdio(clk) | ||
121 | mpp13 13 gpio, sdio(cmd), uart1(txd) | ||
122 | mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt) | ||
123 | mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) | ||
124 | mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), | ||
125 | sata1(act) | ||
126 | mpp17 17 gpio, sdio(d3), sata0(prsnt) | ||
127 | mpp18 18 gpo, nand(io0) | ||
128 | mpp19 19 gpo, nand(io1) | ||
129 | mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), | ||
130 | sata1(act) | ||
131 | mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), | ||
132 | audio(spdifo) | ||
133 | mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), | ||
134 | sata1(prsnt) | ||
135 | mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), | ||
136 | audio(bclk) | ||
137 | mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo) | ||
138 | mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk) | ||
139 | mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk) | ||
140 | mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi) | ||
141 | mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk) | ||
142 | mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst) | ||
143 | mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk) | ||
144 | mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs) | ||
145 | mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx) | ||
146 | mpp33 33 gpo, ge1(txclk), tdm(drx) | ||
147 | mpp34 34 gpio, ge1(txen), tdm(spi-cs1) | ||
148 | mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql) | ||
149 | |||
150 | * Marvell Kirkwood 88f6281 | ||
151 | |||
152 | name pins functions | ||
153 | ================================================================================ | ||
154 | mpp0 0 gpio, nand(io2), spi(cs) | ||
155 | mpp1 1 gpo, nand(io3), spi(mosi) | ||
156 | mpp2 2 gpo, nand(io4), spi(sck) | ||
157 | mpp3 3 gpo, nand(io5), spi(miso) | ||
158 | mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act) | ||
159 | mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) | ||
160 | mpp6 6 sysrst(out), spi(mosi), ptp(trig) | ||
161 | mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) | ||
162 | mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), | ||
163 | mii(col), mii-1(rxerr), sata1(prsnt) | ||
164 | mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), | ||
165 | mii(crs), sata0(prsnt) | ||
166 | mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act) | ||
167 | mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), | ||
168 | ptp-2(trig), sata0(act) | ||
169 | mpp12 12 gpio, sdio(clk) | ||
170 | mpp13 13 gpio, sdio(cmd), uart1(txd) | ||
171 | mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt) | ||
172 | mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) | ||
173 | mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), | ||
174 | sata1(act) | ||
175 | mpp17 17 gpio, sdio(d3), sata0(prsnt) | ||
176 | mpp18 18 gpo, nand(io0) | ||
177 | mpp19 19 gpo, nand(io1) | ||
178 | mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), | ||
179 | sata1(act) | ||
180 | mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), | ||
181 | audio(spdifo) | ||
182 | mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), | ||
183 | sata1(prsnt) | ||
184 | mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), | ||
185 | audio(bclk) | ||
186 | mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo) | ||
187 | mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk) | ||
188 | mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk) | ||
189 | mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi) | ||
190 | mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk) | ||
191 | mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst) | ||
192 | mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk) | ||
193 | mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs) | ||
194 | mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx) | ||
195 | mpp33 33 gpo, ge1(txclk), tdm(drx) | ||
196 | mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act) | ||
197 | mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql) | ||
198 | mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi) | ||
199 | mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo) | ||
200 | mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk) | ||
201 | mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk) | ||
202 | mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo) | ||
203 | mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk) | ||
204 | mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk) | ||
205 | mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi) | ||
206 | mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk) | ||
207 | mpp45 45 gpio, ts(mp9), tdm(pclk) | ||
208 | mpp46 46 gpio, ts(mp10), tdm(fs) | ||
209 | mpp47 47 gpio, ts(mp11), tdm(drx) | ||
210 | mpp48 48 gpio, ts(mp12), tdm(dtx) | ||
211 | mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk) | ||
212 | |||
213 | * Marvell Kirkwood 88f6282 | ||
214 | |||
215 | name pins functions | ||
216 | ================================================================================ | ||
217 | mpp0 0 gpio, nand(io2), spi(cs) | ||
218 | mpp1 1 gpo, nand(io3), spi(mosi) | ||
219 | mpp2 2 gpo, nand(io4), spi(sck) | ||
220 | mpp3 3 gpo, nand(io5), spi(miso) | ||
221 | mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync) | ||
222 | mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync) | ||
223 | mpp6 6 sysrst(out), spi(mosi) | ||
224 | mpp7 7 gpo, spi(cs), lcd(pwm) | ||
225 | mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col), | ||
226 | mii-1(rxerr), sata1(prsnt) | ||
227 | mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs), | ||
228 | sata0(prsnt) | ||
229 | mpp10 10 gpo, spi(sck), uart0(txd), sata1(act) | ||
230 | mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act) | ||
231 | mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda) | ||
232 | mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm) | ||
233 | mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt), | ||
234 | audio(spdifi), audio-1(sdi) | ||
235 | mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act), | ||
236 | spi(cs) | ||
237 | mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), | ||
238 | sata1(act), lcd(extclk) | ||
239 | mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck) | ||
240 | mpp18 18 gpo, nand(io0), pex(clkreq) | ||
241 | mpp19 19 gpo, nand(io1) | ||
242 | mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), | ||
243 | sata1(act), lcd(d0) | ||
244 | mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), | ||
245 | audio(spdifo), lcd(d1) | ||
246 | mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), | ||
247 | sata1(prsnt), lcd(d2) | ||
248 | mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), | ||
249 | audio(bclk), lcd(d3) | ||
250 | mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo), | ||
251 | lcd(d4) | ||
252 | mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk), | ||
253 | lcd(d5) | ||
254 | mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk), | ||
255 | lcd(d6) | ||
256 | mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi), | ||
257 | lcd(d7) | ||
258 | mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk), | ||
259 | lcd(d8) | ||
260 | mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9) | ||
261 | mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10) | ||
262 | mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11) | ||
263 | mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12) | ||
264 | mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13) | ||
265 | mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14) | ||
266 | mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql), | ||
267 | lcd(d15) | ||
268 | mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda) | ||
269 | mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck) | ||
270 | mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18) | ||
271 | mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19) | ||
272 | mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20) | ||
273 | mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21) | ||
274 | mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22) | ||
275 | mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23) | ||
276 | mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk) | ||
277 | mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e) | ||
278 | mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync) | ||
279 | mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync) | ||
280 | mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16) | ||
281 | mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17) | ||
282 | |||
283 | * Marvell Bobcat 98dx4122 | ||
284 | |||
285 | name pins functions | ||
286 | ================================================================================ | ||
287 | mpp0 0 gpio, nand(io2), spi(cs) | ||
288 | mpp1 1 gpo, nand(io3), spi(mosi) | ||
289 | mpp2 2 gpo, nand(io4), spi(sck) | ||
290 | mpp3 3 gpo, nand(io5), spi(miso) | ||
291 | mpp4 4 gpio, nand(io6), uart0(rxd) | ||
292 | mpp5 5 gpo, nand(io7), uart0(txd) | ||
293 | mpp6 6 sysrst(out), spi(mosi) | ||
294 | mpp7 7 gpo, pex(rsto), spi(cs) | ||
295 | mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts) | ||
296 | mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts) | ||
297 | mpp10 10 gpo, spi(sck), uart0(txd) | ||
298 | mpp11 11 gpio, spi(miso), uart0(rxd) | ||
299 | mpp13 13 gpio, uart1(txd) | ||
300 | mpp14 14 gpio, uart1(rxd) | ||
301 | mpp15 15 gpio, uart0(rts) | ||
302 | mpp16 16 gpio, uart0(cts) | ||
303 | mpp18 18 gpo, nand(io0) | ||
304 | mpp19 19 gpo, nand(io1) | ||
305 | mpp34 34 gpio | ||
306 | mpp35 35 gpio | ||
307 | mpp36 36 gpio | ||
308 | mpp37 37 gpio | ||
309 | mpp38 38 gpio | ||
310 | mpp39 39 gpio | ||
311 | mpp40 40 gpio | ||
312 | mpp41 41 gpio | ||
313 | mpp42 42 gpio | ||
314 | mpp43 43 gpio | ||
315 | mpp44 44 gpio | ||
316 | mpp45 45 gpio | ||
317 | mpp49 49 gpio | ||
318 | |||
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt deleted file mode 100644 index 0a26c3aa4e6..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt +++ /dev/null | |||
@@ -1,46 +0,0 @@ | |||
1 | * Marvell SoC pinctrl core driver for mpp | ||
2 | |||
3 | The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins | ||
4 | (mpp) to a specific function. For each SoC family there is a SoC specific | ||
5 | driver using this core driver. | ||
6 | |||
7 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
8 | common pinctrl bindings used by client devices, including the meaning of the | ||
9 | phrase "pin configuration node". | ||
10 | |||
11 | A Marvell SoC pin configuration node is a node of a group of pins which can | ||
12 | be used for a specific device or function. Each node requires one or more | ||
13 | mpp pins or group of pins and a mpp function common to all pins. | ||
14 | |||
15 | Required properties for pinctrl driver: | ||
16 | - compatible: "marvell,<soc>-pinctrl" | ||
17 | Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs. | ||
18 | |||
19 | Required properties for pin configuration node: | ||
20 | - marvell,pins: string array of mpp pins or group of pins to be muxed. | ||
21 | - marvell,function: string representing a function to mux to for all | ||
22 | marvell,pins given in this pin configuration node. The function has to be | ||
23 | common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for | ||
24 | valid pin/pin group names and available function names for each SoC. | ||
25 | |||
26 | Examples: | ||
27 | |||
28 | uart1: serial@12100 { | ||
29 | compatible = "ns16550a"; | ||
30 | reg = <0x12100 0x100>; | ||
31 | reg-shift = <2>; | ||
32 | interrupts = <7>; | ||
33 | |||
34 | pinctrl-0 = <&pmx_uart1_sw>; | ||
35 | pinctrl-names = "default"; | ||
36 | }; | ||
37 | |||
38 | pinctrl: pinctrl@d0200 { | ||
39 | compatible = "marvell,dove-pinctrl"; | ||
40 | reg = <0xd0200 0x20>; | ||
41 | |||
42 | pmx_uart1_sw: pmx-uart1-sw { | ||
43 | marvell,pins = "mpp_uart1"; | ||
44 | marvell,function = "uart1"; | ||
45 | }; | ||
46 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt deleted file mode 100644 index 683fde93c4f..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt +++ /dev/null | |||
@@ -1,132 +0,0 @@ | |||
1 | NVIDIA Tegra20 pinmux controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "nvidia,tegra20-pinmux" | ||
5 | - reg: Should contain the register physical address and length for each of | ||
6 | the tri-state, mux, pull-up/down, and pad control register sets. | ||
7 | |||
8 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
9 | common pinctrl bindings used by client devices, including the meaning of the | ||
10 | phrase "pin configuration node". | ||
11 | |||
12 | Tegra's pin configuration nodes act as a container for an abitrary number of | ||
13 | subnodes. Each of these subnodes represents some desired configuration for a | ||
14 | pin, a group, or a list of pins or groups. This configuration can include the | ||
15 | mux function to select on those pin(s)/group(s), and various pin configuration | ||
16 | parameters, such as pull-up, tristate, drive strength, etc. | ||
17 | |||
18 | The name of each subnode is not important; all subnodes should be enumerated | ||
19 | and processed purely based on their content. | ||
20 | |||
21 | Each subnode only affects those parameters that are explicitly listed. In | ||
22 | other words, a subnode that lists a mux function but no pin configuration | ||
23 | parameters implies no information about any pin configuration parameters. | ||
24 | Similarly, a pin subnode that describes a pullup parameter implies no | ||
25 | information about e.g. the mux function or tristate parameter. For this | ||
26 | reason, even seemingly boolean values are actually tristates in this binding: | ||
27 | unspecified, off, or on. Unspecified is represented as an absent property, | ||
28 | and off/on are represented as integer values 0 and 1. | ||
29 | |||
30 | Required subnode-properties: | ||
31 | - nvidia,pins : An array of strings. Each string contains the name of a pin or | ||
32 | group. Valid values for these names are listed below. | ||
33 | |||
34 | Optional subnode-properties: | ||
35 | - nvidia,function: A string containing the name of the function to mux to the | ||
36 | pin or group. Valid values for function names are listed below. See the Tegra | ||
37 | TRM to determine which are valid for each pin or group. | ||
38 | - nvidia,pull: Integer, representing the pull-down/up to apply to the pin. | ||
39 | 0: none, 1: down, 2: up. | ||
40 | - nvidia,tristate: Integer. | ||
41 | 0: drive, 1: tristate. | ||
42 | - nvidia,high-speed-mode: Integer. Enable high speed mode the pins. | ||
43 | 0: no, 1: yes. | ||
44 | - nvidia,schmitt: Integer. Enables Schmitt Trigger on the input. | ||
45 | 0: no, 1: yes. | ||
46 | - nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is | ||
47 | most power. Controls the drive power or current. See "Low Power Mode" | ||
48 | or "LPMD1" and "LPMD0" in the Tegra TRM. | ||
49 | - nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest. | ||
50 | The range of valid values depends on the pingroup. See "CAL_DRVDN" in the | ||
51 | Tegra TRM. | ||
52 | - nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest. | ||
53 | The range of valid values depends on the pingroup. See "CAL_DRVUP" in the | ||
54 | Tegra TRM. | ||
55 | - nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is | ||
56 | fastest. The range of valid values depends on the pingroup. See | ||
57 | "DRVDN_SLWR" in the Tegra TRM. | ||
58 | - nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is | ||
59 | fastest. The range of valid values depends on the pingroup. See | ||
60 | "DRVUP_SLWF" in the Tegra TRM. | ||
61 | |||
62 | Note that many of these properties are only valid for certain specific pins | ||
63 | or groups. See the Tegra TRM and various pinmux spreadsheets for complete | ||
64 | details regarding which groups support which functionality. The Linux pinctrl | ||
65 | driver may also be a useful reference, since it consolidates, disambiguates, | ||
66 | and corrects data from all those sources. | ||
67 | |||
68 | Valid values for pin and group names are: | ||
69 | |||
70 | mux groups: | ||
71 | |||
72 | These all support nvidia,function, nvidia,tristate, and many support | ||
73 | nvidia,pull. | ||
74 | |||
75 | ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4, | ||
76 | ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7, | ||
77 | gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, | ||
78 | ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13, | ||
79 | ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp, | ||
80 | lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs, | ||
81 | owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, | ||
82 | spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad, | ||
83 | uca, ucb, uda. | ||
84 | |||
85 | tristate groups: | ||
86 | |||
87 | These only support nvidia,pull. | ||
88 | |||
89 | ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0, | ||
90 | ld19_18, ld21_20, ld23_22. | ||
91 | |||
92 | drive groups: | ||
93 | |||
94 | With some exceptions, these support nvidia,high-speed-mode, | ||
95 | nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength, | ||
96 | nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling. | ||
97 | |||
98 | drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2, | ||
99 | drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg, | ||
100 | drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa, | ||
101 | drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a, | ||
102 | drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc, | ||
103 | drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr, | ||
104 | drive_uda. | ||
105 | |||
106 | Example: | ||
107 | |||
108 | pinctrl@70000000 { | ||
109 | compatible = "nvidia,tegra20-pinmux"; | ||
110 | reg = < 0x70000014 0x10 /* Tri-state registers */ | ||
111 | 0x70000080 0x20 /* Mux registers */ | ||
112 | 0x700000a0 0x14 /* Pull-up/down registers */ | ||
113 | 0x70000868 0xa8 >; /* Pad control registers */ | ||
114 | }; | ||
115 | |||
116 | Example board file extract: | ||
117 | |||
118 | pinctrl@70000000 { | ||
119 | sdio4_default: sdio4_default { | ||
120 | atb { | ||
121 | nvidia,pins = "atb", "gma", "gme"; | ||
122 | nvidia,function = "sdio4"; | ||
123 | nvidia,pull = <0>; | ||
124 | nvidia,tristate = <0>; | ||
125 | }; | ||
126 | }; | ||
127 | }; | ||
128 | |||
129 | sdhci@c8000600 { | ||
130 | pinctrl-names = "default"; | ||
131 | pinctrl-0 = <&sdio4_default>; | ||
132 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt deleted file mode 100644 index 6f426ed7009..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt +++ /dev/null | |||
@@ -1,132 +0,0 @@ | |||
1 | NVIDIA Tegra30 pinmux controller | ||
2 | |||
3 | The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding, | ||
4 | as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes | ||
5 | that binding as a baseline, and only documents the differences between the | ||
6 | two bindings. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible: "nvidia,tegra30-pinmux" | ||
10 | - reg: Should contain the register physical address and length for each of | ||
11 | the pad control and mux registers. | ||
12 | |||
13 | Tegra30 adds the following optional properties for pin configuration subnodes: | ||
14 | - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes. | ||
15 | - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes. | ||
16 | - nvidia,lock: Integer. Lock the pin configuration against further changes | ||
17 | until reset. 0: no, 1: yes. | ||
18 | - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes. | ||
19 | |||
20 | As with Tegra20, see the Tegra TRM for complete details regarding which groups | ||
21 | support which functionality. | ||
22 | |||
23 | Valid values for pin and group names are: | ||
24 | |||
25 | per-pin mux groups: | ||
26 | |||
27 | These all support nvidia,function, nvidia,tristate, nvidia,pull, | ||
28 | nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain, | ||
29 | nvidia,io-reset. | ||
30 | |||
31 | clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3, | ||
32 | dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0, | ||
33 | gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5, | ||
34 | sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1, | ||
35 | uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, | ||
36 | lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2, | ||
37 | sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7, | ||
38 | lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5, | ||
39 | lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3, | ||
40 | lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0, | ||
41 | gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, | ||
42 | gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2, | ||
43 | gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7, | ||
44 | gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4, | ||
45 | gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1, | ||
46 | gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5, | ||
47 | uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2, | ||
48 | gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7, | ||
49 | vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5, | ||
50 | vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3, | ||
51 | lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0, | ||
52 | dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5, | ||
53 | lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2, | ||
54 | ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6, | ||
55 | ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, | ||
56 | dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0, | ||
57 | kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, | ||
58 | kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, | ||
59 | kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, | ||
60 | kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, | ||
61 | kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1, | ||
62 | vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, | ||
63 | sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0, | ||
64 | pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7, | ||
65 | lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4, | ||
66 | clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1, | ||
67 | spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6, | ||
68 | spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, | ||
69 | sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7, | ||
70 | sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4, | ||
71 | sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0, | ||
72 | sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, | ||
73 | sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0, | ||
74 | cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, | ||
75 | cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4, | ||
76 | clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7, | ||
77 | pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, | ||
78 | pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5, | ||
79 | pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1, | ||
80 | clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr, | ||
81 | pwr_int_n. | ||
82 | |||
83 | drive groups: | ||
84 | |||
85 | These all support nvidia,pull-down-strength, nvidia,pull-up-strength, | ||
86 | nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all | ||
87 | support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode. | ||
88 | |||
89 | ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1, | ||
90 | dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg, | ||
91 | gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2, | ||
92 | uart3, uda, vi1. | ||
93 | |||
94 | Example: | ||
95 | |||
96 | pinctrl@70000000 { | ||
97 | compatible = "nvidia,tegra30-pinmux"; | ||
98 | reg = < 0x70000868 0xd0 /* Pad control registers */ | ||
99 | 0x70003000 0x3e0 >; /* Mux registers */ | ||
100 | }; | ||
101 | |||
102 | Example board file extract: | ||
103 | |||
104 | pinctrl@70000000 { | ||
105 | sdmmc4_default: pinmux { | ||
106 | sdmmc4_clk_pcc4 { | ||
107 | nvidia,pins = "sdmmc4_clk_pcc4", | ||
108 | "sdmmc4_rst_n_pcc3"; | ||
109 | nvidia,function = "sdmmc4"; | ||
110 | nvidia,pull = <0>; | ||
111 | nvidia,tristate = <0>; | ||
112 | }; | ||
113 | sdmmc4_dat0_paa0 { | ||
114 | nvidia,pins = "sdmmc4_dat0_paa0", | ||
115 | "sdmmc4_dat1_paa1", | ||
116 | "sdmmc4_dat2_paa2", | ||
117 | "sdmmc4_dat3_paa3", | ||
118 | "sdmmc4_dat4_paa4", | ||
119 | "sdmmc4_dat5_paa5", | ||
120 | "sdmmc4_dat6_paa6", | ||
121 | "sdmmc4_dat7_paa7"; | ||
122 | nvidia,function = "sdmmc4"; | ||
123 | nvidia,pull = <2>; | ||
124 | nvidia,tristate = <0>; | ||
125 | }; | ||
126 | }; | ||
127 | }; | ||
128 | |||
129 | sdhci@78000400 { | ||
130 | pinctrl-names = "default"; | ||
131 | pinctrl-0 = <&sdmmc4_default>; | ||
132 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt deleted file mode 100644 index c95ea8278f8..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ /dev/null | |||
@@ -1,128 +0,0 @@ | |||
1 | == Introduction == | ||
2 | |||
3 | Hardware modules that control pin multiplexing or configuration parameters | ||
4 | such as pull-up/down, tri-state, drive-strength etc are designated as pin | ||
5 | controllers. Each pin controller must be represented as a node in device tree, | ||
6 | just like any other hardware module. | ||
7 | |||
8 | Hardware modules whose signals are affected by pin configuration are | ||
9 | designated client devices. Again, each client device must be represented as a | ||
10 | node in device tree, just like any other hardware module. | ||
11 | |||
12 | For a client device to operate correctly, certain pin controllers must | ||
13 | set up certain specific pin configurations. Some client devices need a | ||
14 | single static pin configuration, e.g. set up during initialization. Others | ||
15 | need to reconfigure pins at run-time, for example to tri-state pins when the | ||
16 | device is inactive. Hence, each client device can define a set of named | ||
17 | states. The number and names of those states is defined by the client device's | ||
18 | own binding. | ||
19 | |||
20 | The common pinctrl bindings defined in this file provide an infrastructure | ||
21 | for client device device tree nodes to map those state names to the pin | ||
22 | configuration used by those states. | ||
23 | |||
24 | Note that pin controllers themselves may also be client devices of themselves. | ||
25 | For example, a pin controller may set up its own "active" state when the | ||
26 | driver loads. This would allow representing a board's static pin configuration | ||
27 | in a single place, rather than splitting it across multiple client device | ||
28 | nodes. The decision to do this or not somewhat rests with the author of | ||
29 | individual board device tree files, and any requirements imposed by the | ||
30 | bindings for the individual client devices in use by that board, i.e. whether | ||
31 | they require certain specific named states for dynamic pin configuration. | ||
32 | |||
33 | == Pinctrl client devices == | ||
34 | |||
35 | For each client device individually, every pin state is assigned an integer | ||
36 | ID. These numbers start at 0, and are contiguous. For each state ID, a unique | ||
37 | property exists to define the pin configuration. Each state may also be | ||
38 | assigned a name. When names are used, another property exists to map from | ||
39 | those names to the integer IDs. | ||
40 | |||
41 | Each client device's own binding determines the set of states the must be | ||
42 | defined in its device tree node, and whether to define the set of state | ||
43 | IDs that must be provided, or whether to define the set of state names that | ||
44 | must be provided. | ||
45 | |||
46 | Required properties: | ||
47 | pinctrl-0: List of phandles, each pointing at a pin configuration | ||
48 | node. These referenced pin configuration nodes must be child | ||
49 | nodes of the pin controller that they configure. Multiple | ||
50 | entries may exist in this list so that multiple pin | ||
51 | controllers may be configured, or so that a state may be built | ||
52 | from multiple nodes for a single pin controller, each | ||
53 | contributing part of the overall configuration. See the next | ||
54 | section of this document for details of the format of these | ||
55 | pin configuration nodes. | ||
56 | |||
57 | In some cases, it may be useful to define a state, but for it | ||
58 | to be empty. This may be required when a common IP block is | ||
59 | used in an SoC either without a pin controller, or where the | ||
60 | pin controller does not affect the HW module in question. If | ||
61 | the binding for that IP block requires certain pin states to | ||
62 | exist, they must still be defined, but may be left empty. | ||
63 | |||
64 | Optional properties: | ||
65 | pinctrl-1: List of phandles, each pointing at a pin configuration | ||
66 | node within a pin controller. | ||
67 | ... | ||
68 | pinctrl-n: List of phandles, each pointing at a pin configuration | ||
69 | node within a pin controller. | ||
70 | pinctrl-names: The list of names to assign states. List entry 0 defines the | ||
71 | name for integer state ID 0, list entry 1 for state ID 1, and | ||
72 | so on. | ||
73 | |||
74 | For example: | ||
75 | |||
76 | /* For a client device requiring named states */ | ||
77 | device { | ||
78 | pinctrl-names = "active", "idle"; | ||
79 | pinctrl-0 = <&state_0_node_a>; | ||
80 | pinctrl-1 = <&state_1_node_a &state_1_node_b>; | ||
81 | }; | ||
82 | |||
83 | /* For the same device if using state IDs */ | ||
84 | device { | ||
85 | pinctrl-0 = <&state_0_node_a>; | ||
86 | pinctrl-1 = <&state_1_node_a &state_1_node_b>; | ||
87 | }; | ||
88 | |||
89 | /* | ||
90 | * For an IP block whose binding supports pin configuration, | ||
91 | * but in use on an SoC that doesn't have any pin control hardware | ||
92 | */ | ||
93 | device { | ||
94 | pinctrl-names = "active", "idle"; | ||
95 | pinctrl-0 = <>; | ||
96 | pinctrl-1 = <>; | ||
97 | }; | ||
98 | |||
99 | == Pin controller devices == | ||
100 | |||
101 | Pin controller devices should contain the pin configuration nodes that client | ||
102 | devices reference. | ||
103 | |||
104 | For example: | ||
105 | |||
106 | pincontroller { | ||
107 | ... /* Standard DT properties for the device itself elided */ | ||
108 | |||
109 | state_0_node_a { | ||
110 | ... | ||
111 | }; | ||
112 | state_1_node_a { | ||
113 | ... | ||
114 | }; | ||
115 | state_1_node_b { | ||
116 | ... | ||
117 | }; | ||
118 | } | ||
119 | |||
120 | The contents of each of those pin configuration child nodes is defined | ||
121 | entirely by the binding for the individual pin controller device. There | ||
122 | exists no common standard for this content. | ||
123 | |||
124 | The pin configuration nodes need not be direct children of the pin controller | ||
125 | device; they may be grandchildren, for example. Whether this is legal, and | ||
126 | whether there is any interaction between the child and intermediate parent | ||
127 | nodes, is again defined entirely by the binding for the individual pin | ||
128 | controller device. | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt deleted file mode 100644 index 2c81e45f137..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ /dev/null | |||
@@ -1,128 +0,0 @@ | |||
1 | One-register-per-pin type device tree based pinctrl driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "pinctrl-single" | ||
5 | |||
6 | - reg : offset and length of the register set for the mux registers | ||
7 | |||
8 | - pinctrl-single,register-width : pinmux register access width in bits | ||
9 | |||
10 | - pinctrl-single,function-mask : mask of allowed pinmux function bits | ||
11 | in the pinmux register | ||
12 | |||
13 | Optional properties: | ||
14 | - pinctrl-single,function-off : function off mode for disabled state if | ||
15 | available and same for all registers; if not specified, disabling of | ||
16 | pin functions is ignored | ||
17 | - pinctrl-single,bit-per-mux : boolean to indicate that one register controls | ||
18 | more than one pin | ||
19 | |||
20 | This driver assumes that there is only one register for each pin (unless the | ||
21 | pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as | ||
22 | specified in the pinctrl-bindings.txt document in this directory. | ||
23 | |||
24 | The pin configuration nodes for pinctrl-single are specified as pinctrl | ||
25 | register offset and value pairs using pinctrl-single,pins. Only the bits | ||
26 | specified in pinctrl-single,function-mask are updated. For example, setting | ||
27 | a pin for a device could be done with: | ||
28 | |||
29 | pinctrl-single,pins = <0xdc 0x118>; | ||
30 | |||
31 | Where 0xdc is the offset from the pinctrl register base address for the | ||
32 | device pinctrl register, and 0x118 contains the desired value of the | ||
33 | pinctrl register. See the device example and static board pins example | ||
34 | below for more information. | ||
35 | |||
36 | In case when one register changes more than one pin's mux the | ||
37 | pinctrl-single,bits need to be used which takes three parameters: | ||
38 | |||
39 | pinctrl-single,bits = <0xdc 0x18, 0xff>; | ||
40 | |||
41 | Where 0xdc is the offset from the pinctrl register base address for the | ||
42 | device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to | ||
43 | be used when applying this change to the register. | ||
44 | |||
45 | Example: | ||
46 | |||
47 | /* SoC common file */ | ||
48 | |||
49 | /* first controller instance for pins in core domain */ | ||
50 | pmx_core: pinmux@4a100040 { | ||
51 | compatible = "pinctrl-single"; | ||
52 | reg = <0x4a100040 0x0196>; | ||
53 | #address-cells = <1>; | ||
54 | #size-cells = <0>; | ||
55 | pinctrl-single,register-width = <16>; | ||
56 | pinctrl-single,function-mask = <0xffff>; | ||
57 | }; | ||
58 | |||
59 | /* second controller instance for pins in wkup domain */ | ||
60 | pmx_wkup: pinmux@4a31e040 { | ||
61 | compatible = "pinctrl-single; | ||
62 | reg = <0x4a31e040 0x0038>; | ||
63 | #address-cells = <1>; | ||
64 | #size-cells = <0>; | ||
65 | pinctrl-single,register-width = <16>; | ||
66 | pinctrl-single,function-mask = <0xffff>; | ||
67 | }; | ||
68 | |||
69 | control_devconf0: pinmux@48002274 { | ||
70 | compatible = "pinctrl-single"; | ||
71 | reg = <0x48002274 4>; /* Single register */ | ||
72 | #address-cells = <1>; | ||
73 | #size-cells = <0>; | ||
74 | pinctrl-single,bit-per-mux; | ||
75 | pinctrl-single,register-width = <32>; | ||
76 | pinctrl-single,function-mask = <0x5F>; | ||
77 | }; | ||
78 | |||
79 | /* board specific .dts file */ | ||
80 | |||
81 | &pmx_core { | ||
82 | |||
83 | /* | ||
84 | * map all board specific static pins enabled by the pinctrl driver | ||
85 | * itself during the boot (or just set them up in the bootloader) | ||
86 | */ | ||
87 | pinctrl-names = "default"; | ||
88 | pinctrl-0 = <&board_pins>; | ||
89 | |||
90 | board_pins: pinmux_board_pins { | ||
91 | pinctrl-single,pins = < | ||
92 | 0x6c 0xf | ||
93 | 0x6e 0xf | ||
94 | 0x70 0xf | ||
95 | 0x72 0xf | ||
96 | >; | ||
97 | }; | ||
98 | |||
99 | /* map uart2 pins */ | ||
100 | uart2_pins: pinmux_uart2_pins { | ||
101 | pinctrl-single,pins = < | ||
102 | 0xd8 0x118 | ||
103 | 0xda 0 | ||
104 | 0xdc 0x118 | ||
105 | 0xde 0 | ||
106 | >; | ||
107 | }; | ||
108 | }; | ||
109 | |||
110 | &control_devconf0 { | ||
111 | mcbsp1_pins: pinmux_mcbsp1_pins { | ||
112 | pinctrl-single,bits = < | ||
113 | 0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */ | ||
114 | >; | ||
115 | }; | ||
116 | |||
117 | mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins { | ||
118 | pinctrl-single,bits = < | ||
119 | 0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */ | ||
120 | >; | ||
121 | }; | ||
122 | |||
123 | }; | ||
124 | |||
125 | &uart2 { | ||
126 | pinctrl-names = "default"; | ||
127 | pinctrl-0 = <&uart2_pins>; | ||
128 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt deleted file mode 100644 index c596a6ad328..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | CSR SiRFprimaII pinmux controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "sirf,prima2-pinctrl" | ||
5 | - reg : Address range of the pinctrl registers | ||
6 | - interrupts : Interrupts used by every GPIO group | ||
7 | - gpio-controller : Indicates this device is a GPIO controller | ||
8 | - interrupt-controller : Marks the device node as an interrupt controller | ||
9 | Optional properties: | ||
10 | - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m | ||
11 | - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m | ||
12 | |||
13 | Please refer to pinctrl-bindings.txt in this directory for details of the common | ||
14 | pinctrl bindings used by client devices. | ||
15 | |||
16 | SiRFprimaII's pinmux nodes act as a container for an abitrary number of subnodes. | ||
17 | Each of these subnodes represents some desired configuration for a group of pins. | ||
18 | |||
19 | Required subnode-properties: | ||
20 | - sirf,pins : An array of strings. Each string contains the name of a group. | ||
21 | - sirf,function: A string containing the name of the function to mux to the | ||
22 | group. | ||
23 | |||
24 | Valid values for group and function names can be found from looking at the | ||
25 | group and function arrays in driver files: | ||
26 | drivers/pinctrl/pinctrl-sirf.c | ||
27 | |||
28 | For example, pinctrl might have subnodes like the following: | ||
29 | uart2_pins_a: uart2@0 { | ||
30 | uart { | ||
31 | sirf,pins = "uart2grp"; | ||
32 | sirf,function = "uart2"; | ||
33 | }; | ||
34 | }; | ||
35 | uart2_noflow_pins_a: uart2@1 { | ||
36 | uart { | ||
37 | sirf,pins = "uart2_nostreamctrlgrp"; | ||
38 | sirf,function = "uart2_nostreamctrl"; | ||
39 | }; | ||
40 | }; | ||
41 | |||
42 | For a specific board, if it wants to use uart2 without hardware flow control, | ||
43 | it can add the following to its board-specific .dts file. | ||
44 | uart2: uart@0xb0070000 { | ||
45 | pinctrl-names = "default"; | ||
46 | pinctrl-0 = <&uart2_noflow_pins_a>; | ||
47 | } | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt deleted file mode 100644 index b4480d5c3ac..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt +++ /dev/null | |||
@@ -1,155 +0,0 @@ | |||
1 | ST Microelectronics, SPEAr pinmux controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "st,spear300-pinmux" | ||
5 | : "st,spear310-pinmux" | ||
6 | : "st,spear320-pinmux" | ||
7 | : "st,spear1310-pinmux" | ||
8 | : "st,spear1340-pinmux" | ||
9 | - reg : Address range of the pinctrl registers | ||
10 | - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others. | ||
11 | - Its values for SPEAr300: | ||
12 | - NAND_MODE : <0> | ||
13 | - NOR_MODE : <1> | ||
14 | - PHOTO_FRAME_MODE : <2> | ||
15 | - LEND_IP_PHONE_MODE : <3> | ||
16 | - HEND_IP_PHONE_MODE : <4> | ||
17 | - LEND_WIFI_PHONE_MODE : <5> | ||
18 | - HEND_WIFI_PHONE_MODE : <6> | ||
19 | - ATA_PABX_WI2S_MODE : <7> | ||
20 | - ATA_PABX_I2S_MODE : <8> | ||
21 | - CAML_LCDW_MODE : <9> | ||
22 | - CAMU_LCD_MODE : <10> | ||
23 | - CAMU_WLCD_MODE : <11> | ||
24 | - CAML_LCD_MODE : <12> | ||
25 | - Its values for SPEAr320: | ||
26 | - AUTO_NET_SMII_MODE : <0> | ||
27 | - AUTO_NET_MII_MODE : <1> | ||
28 | - AUTO_EXP_MODE : <2> | ||
29 | - SMALL_PRINTERS_MODE : <3> | ||
30 | - EXTENDED_MODE : <4> | ||
31 | |||
32 | Please refer to pinctrl-bindings.txt in this directory for details of the common | ||
33 | pinctrl bindings used by client devices. | ||
34 | |||
35 | SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each | ||
36 | of these subnodes represents muxing for a pin, a group, or a list of pins or | ||
37 | groups. | ||
38 | |||
39 | The name of each subnode is not important; all subnodes should be enumerated | ||
40 | and processed purely based on their content. | ||
41 | |||
42 | Required subnode-properties: | ||
43 | - st,pins : An array of strings. Each string contains the name of a pin or | ||
44 | group. | ||
45 | - st,function: A string containing the name of the function to mux to the pin or | ||
46 | group. See the SPEAr's TRM to determine which are valid for each pin or group. | ||
47 | |||
48 | Valid values for group and function names can be found from looking at the | ||
49 | group and function arrays in driver files: | ||
50 | drivers/pinctrl/spear/pinctrl-spear3*0.c | ||
51 | |||
52 | Valid values for group names are: | ||
53 | For All SPEAr3xx machines: | ||
54 | "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp", | ||
55 | "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp", | ||
56 | "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp", | ||
57 | "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp" | ||
58 | |||
59 | For SPEAr300 machines: | ||
60 | "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp", | ||
61 | "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp", | ||
62 | "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp", | ||
63 | "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" | ||
64 | |||
65 | For SPEAr310 machines: | ||
66 | "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp", | ||
67 | "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp" | ||
68 | |||
69 | For SPEAr320 machines: | ||
70 | "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp", | ||
71 | "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp", | ||
72 | "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp", | ||
73 | "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp", | ||
74 | "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp", | ||
75 | "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp", | ||
76 | "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp", | ||
77 | "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", | ||
78 | "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp", | ||
79 | "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp", | ||
80 | "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp", | ||
81 | "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp", | ||
82 | "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp", | ||
83 | "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp", | ||
84 | "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp", | ||
85 | "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp", | ||
86 | "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp", | ||
87 | "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp", | ||
88 | "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp", | ||
89 | "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp", | ||
90 | "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp", | ||
91 | "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp", | ||
92 | "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" | ||
93 | |||
94 | For SPEAr1310 machines: | ||
95 | "i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp", | ||
96 | "i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp", | ||
97 | "smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp", | ||
98 | "smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp", | ||
99 | "nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp", | ||
100 | "keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp", | ||
101 | "gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp", | ||
102 | "sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp", | ||
103 | "uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp", | ||
104 | "uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp", | ||
105 | "i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp", | ||
106 | "i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp", | ||
107 | "i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp", | ||
108 | "can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp", | ||
109 | "pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp", | ||
110 | "ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp" | ||
111 | |||
112 | For SPEAr1340 machines: | ||
113 | "pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp", | ||
114 | "keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp", | ||
115 | "spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp", | ||
116 | "pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp", | ||
117 | "vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp", | ||
118 | "cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp", | ||
119 | "ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp", | ||
120 | "uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp", | ||
121 | "rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp", | ||
122 | "sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp", | ||
123 | "miphy_dbg_grp", "pcie_grp", "sata_grp" | ||
124 | |||
125 | Valid values for function names are: | ||
126 | For All SPEAr3xx machines: | ||
127 | "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext", | ||
128 | "uart0", "timer_0_1", "timer_2_3" | ||
129 | |||
130 | For SPEAr300 machines: | ||
131 | "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1" | ||
132 | |||
133 | For SPEAr310 machines: | ||
134 | "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0", | ||
135 | "rs485_1", "tdm" | ||
136 | |||
137 | For SPEAr320 machines: | ||
138 | "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem", | ||
139 | "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen", | ||
140 | "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2", | ||
141 | "mii0_1", "i2c1", "i2c2" | ||
142 | |||
143 | |||
144 | For SPEAr1310 machines: | ||
145 | "i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii", | ||
146 | "rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0", | ||
147 | "gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3", | ||
148 | "uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1", | ||
149 | "i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64" | ||
150 | |||
151 | For SPEAr1340 machines: | ||
152 | "pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1", | ||
153 | "pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0", | ||
154 | "uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf", | ||
155 | "xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata" | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt deleted file mode 100644 index e97a27856b2..00000000000 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ /dev/null | |||
@@ -1,265 +0,0 @@ | |||
1 | Samsung GPIO and Pin Mux/Config controller | ||
2 | |||
3 | Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware | ||
4 | controller. It controls the input/output settings on the available pads/pins | ||
5 | and also provides ability to multiplex and configure the output of various | ||
6 | on-chip controllers onto these pads. | ||
7 | |||
8 | Required Properties: | ||
9 | - compatible: should be one of the following. | ||
10 | - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller. | ||
11 | - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller. | ||
12 | - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller. | ||
13 | |||
14 | - reg: Base address of the pin controller hardware module and length of | ||
15 | the address space it occupies. | ||
16 | |||
17 | - Pin banks as child nodes: Pin banks of the controller are represented by child | ||
18 | nodes of the controller node. Bank name is taken from name of the node. Each | ||
19 | bank node must contain following properties: | ||
20 | |||
21 | - gpio-controller: identifies the node as a gpio controller and pin bank. | ||
22 | - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO | ||
23 | binding is used, the amount of cells must be specified as 2. See generic | ||
24 | GPIO binding documentation for description of particular cells. | ||
25 | |||
26 | - Pin mux/config groups as child nodes: The pin mux (selecting pin function | ||
27 | mode) and pin config (pull up/down, driver strength) settings are represented | ||
28 | as child nodes of the pin-controller node. There should be atleast one | ||
29 | child node and there is no limit on the count of these child nodes. | ||
30 | |||
31 | The child node should contain a list of pin(s) on which a particular pin | ||
32 | function selection or pin configuration (or both) have to applied. This | ||
33 | list of pins is specified using the property name "samsung,pins". There | ||
34 | should be atleast one pin specfied for this property and there is no upper | ||
35 | limit on the count of pins that can be specified. The pins are specified | ||
36 | using pin names which are derived from the hardware manual of the SoC. As | ||
37 | an example, the pins in GPA0 bank of the pin controller can be represented | ||
38 | as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. | ||
39 | The format of the pin names should be (as per the hardware manual) | ||
40 | "[pin bank name]-[pin number within the bank]". | ||
41 | |||
42 | The pin function selection that should be applied on the pins listed in the | ||
43 | child node is specified using the "samsung,pin-function" property. The value | ||
44 | of this property that should be applied to each of the pins listed in the | ||
45 | "samsung,pins" property should be picked from the hardware manual of the SoC | ||
46 | for the specified pin group. This property is optional in the child node if | ||
47 | no specific function selection is desired for the pins listed in the child | ||
48 | node. The value of this property is used as-is to program the pin-controller | ||
49 | function selector register of the pin-bank. | ||
50 | |||
51 | The child node can also optionally specify one or more of the pin | ||
52 | configuration that should be applied on all the pins listed in the | ||
53 | "samsung,pins" property of the child node. The following pin configuration | ||
54 | properties are supported. | ||
55 | |||
56 | - samsung,pin-pud: Pull up/down configuration. | ||
57 | - samsung,pin-drv: Drive strength configuration. | ||
58 | - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. | ||
59 | - samsung,pin-drv-pdn: Drive strength configuration in power down mode. | ||
60 | |||
61 | The values specified by these config properties should be derived from the | ||
62 | hardware manual and these values are programmed as-is into the pin | ||
63 | pull up/down and driver strength register of the pin-controller. | ||
64 | |||
65 | Note: A child should include atleast a pin function selection property or | ||
66 | pin configuration property (one or more) or both. | ||
67 | |||
68 | The client nodes that require a particular pin function selection and/or | ||
69 | pin configuration should use the bindings listed in the "pinctrl-bindings.txt" | ||
70 | file. | ||
71 | |||
72 | External GPIO and Wakeup Interrupts: | ||
73 | |||
74 | The controller supports two types of external interrupts over gpio. The first | ||
75 | is the external gpio interrupt and second is the external wakeup interrupts. | ||
76 | The difference between the two is that the external wakeup interrupts can be | ||
77 | used as system wakeup events. | ||
78 | |||
79 | A. External GPIO Interrupts: For supporting external gpio interrupts, the | ||
80 | following properties should be specified in the pin-controller device node. | ||
81 | |||
82 | - interrupt-parent: phandle of the interrupt parent to which the external | ||
83 | GPIO interrupts are forwarded to. | ||
84 | - interrupts: interrupt specifier for the controller. The format and value of | ||
85 | the interrupt specifier depends on the interrupt parent for the controller. | ||
86 | |||
87 | In addition, following properties must be present in node of every bank | ||
88 | of pins supporting GPIO interrupts: | ||
89 | |||
90 | - interrupt-controller: identifies the controller node as interrupt-parent. | ||
91 | - #interrupt-cells: the value of this property should be 2. | ||
92 | - First Cell: represents the external gpio interrupt number local to the | ||
93 | external gpio interrupt space of the controller. | ||
94 | - Second Cell: flags to identify the type of the interrupt | ||
95 | - 1 = rising edge triggered | ||
96 | - 2 = falling edge triggered | ||
97 | - 3 = rising and falling edge triggered | ||
98 | - 4 = high level triggered | ||
99 | - 8 = low level triggered | ||
100 | |||
101 | B. External Wakeup Interrupts: For supporting external wakeup interrupts, a | ||
102 | child node representing the external wakeup interrupt controller should be | ||
103 | included in the pin-controller device node. This child node should include | ||
104 | the following properties. | ||
105 | |||
106 | - compatible: identifies the type of the external wakeup interrupt controller | ||
107 | The possible values are: | ||
108 | - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller | ||
109 | found on Samsung Exynos4210 SoC. | ||
110 | - interrupt-parent: phandle of the interrupt parent to which the external | ||
111 | wakeup interrupts are forwarded to. | ||
112 | - interrupts: interrupt used by multiplexed wakeup interrupts. | ||
113 | |||
114 | In addition, following properties must be present in node of every bank | ||
115 | of pins supporting wake-up interrupts: | ||
116 | |||
117 | - interrupt-controller: identifies the node as interrupt-parent. | ||
118 | - #interrupt-cells: the value of this property should be 2 | ||
119 | - First Cell: represents the external wakeup interrupt number local to | ||
120 | the external wakeup interrupt space of the controller. | ||
121 | - Second Cell: flags to identify the type of the interrupt | ||
122 | - 1 = rising edge triggered | ||
123 | - 2 = falling edge triggered | ||
124 | - 3 = rising and falling edge triggered | ||
125 | - 4 = high level triggered | ||
126 | - 8 = low level triggered | ||
127 | |||
128 | Node of every bank of pins supporting direct wake-up interrupts (without | ||
129 | multiplexing) must contain following properties: | ||
130 | |||
131 | - interrupt-parent: phandle of the interrupt parent to which the external | ||
132 | wakeup interrupts are forwarded to. | ||
133 | - interrupts: interrupts of the interrupt parent which are used for external | ||
134 | wakeup interrupts from pins of the bank, must contain interrupts for all | ||
135 | pins of the bank. | ||
136 | |||
137 | Aliases: | ||
138 | |||
139 | All the pin controller nodes should be represented in the aliases node using | ||
140 | the following format 'pinctrl{n}' where n is a unique number for the alias. | ||
141 | |||
142 | Example: A pin-controller node with pin banks: | ||
143 | |||
144 | pinctrl_0: pinctrl@11400000 { | ||
145 | compatible = "samsung,pinctrl-exynos4210"; | ||
146 | reg = <0x11400000 0x1000>; | ||
147 | interrupts = <0 47 0>; | ||
148 | |||
149 | /* ... */ | ||
150 | |||
151 | /* Pin bank without external interrupts */ | ||
152 | gpy0: gpy0 { | ||
153 | gpio-controller; | ||
154 | #gpio-cells = <2>; | ||
155 | }; | ||
156 | |||
157 | /* ... */ | ||
158 | |||
159 | /* Pin bank with external GPIO or muxed wake-up interrupts */ | ||
160 | gpj0: gpj0 { | ||
161 | gpio-controller; | ||
162 | #gpio-cells = <2>; | ||
163 | |||
164 | interrupt-controller; | ||
165 | #interrupt-cells = <2>; | ||
166 | }; | ||
167 | |||
168 | /* ... */ | ||
169 | |||
170 | /* Pin bank with external direct wake-up interrupts */ | ||
171 | gpx0: gpx0 { | ||
172 | gpio-controller; | ||
173 | #gpio-cells = <2>; | ||
174 | |||
175 | interrupt-controller; | ||
176 | interrupt-parent = <&gic>; | ||
177 | interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, | ||
178 | <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; | ||
179 | #interrupt-cells = <2>; | ||
180 | }; | ||
181 | |||
182 | /* ... */ | ||
183 | }; | ||
184 | |||
185 | Example 1: A pin-controller node with pin groups. | ||
186 | |||
187 | pinctrl_0: pinctrl@11400000 { | ||
188 | compatible = "samsung,pinctrl-exynos4210"; | ||
189 | reg = <0x11400000 0x1000>; | ||
190 | interrupts = <0 47 0>; | ||
191 | |||
192 | /* ... */ | ||
193 | |||
194 | uart0_data: uart0-data { | ||
195 | samsung,pins = "gpa0-0", "gpa0-1"; | ||
196 | samsung,pin-function = <2>; | ||
197 | samsung,pin-pud = <0>; | ||
198 | samsung,pin-drv = <0>; | ||
199 | }; | ||
200 | |||
201 | uart0_fctl: uart0-fctl { | ||
202 | samsung,pins = "gpa0-2", "gpa0-3"; | ||
203 | samsung,pin-function = <2>; | ||
204 | samsung,pin-pud = <0>; | ||
205 | samsung,pin-drv = <0>; | ||
206 | }; | ||
207 | |||
208 | uart1_data: uart1-data { | ||
209 | samsung,pins = "gpa0-4", "gpa0-5"; | ||
210 | samsung,pin-function = <2>; | ||
211 | samsung,pin-pud = <0>; | ||
212 | samsung,pin-drv = <0>; | ||
213 | }; | ||
214 | |||
215 | uart1_fctl: uart1-fctl { | ||
216 | samsung,pins = "gpa0-6", "gpa0-7"; | ||
217 | samsung,pin-function = <2>; | ||
218 | samsung,pin-pud = <0>; | ||
219 | samsung,pin-drv = <0>; | ||
220 | }; | ||
221 | |||
222 | i2c2_bus: i2c2-bus { | ||
223 | samsung,pins = "gpa0-6", "gpa0-7"; | ||
224 | samsung,pin-function = <3>; | ||
225 | samsung,pin-pud = <3>; | ||
226 | samsung,pin-drv = <0>; | ||
227 | }; | ||
228 | }; | ||
229 | |||
230 | Example 2: A pin-controller node with external wakeup interrupt controller node. | ||
231 | |||
232 | pinctrl_1: pinctrl@11000000 { | ||
233 | compatible = "samsung,pinctrl-exynos4210"; | ||
234 | reg = <0x11000000 0x1000>; | ||
235 | interrupts = <0 46 0> | ||
236 | |||
237 | /* ... */ | ||
238 | |||
239 | wakeup-interrupt-controller { | ||
240 | compatible = "samsung,exynos4210-wakeup-eint"; | ||
241 | interrupt-parent = <&gic>; | ||
242 | interrupts = <0 32 0>; | ||
243 | }; | ||
244 | }; | ||
245 | |||
246 | Example 3: A uart client node that supports 'default' and 'flow-control' states. | ||
247 | |||
248 | uart@13800000 { | ||
249 | compatible = "samsung,exynos4210-uart"; | ||
250 | reg = <0x13800000 0x100>; | ||
251 | interrupts = <0 52 0>; | ||
252 | pinctrl-names = "default", "flow-control; | ||
253 | pinctrl-0 = <&uart0_data>; | ||
254 | pinctrl-1 = <&uart0_data &uart0_fctl>; | ||
255 | }; | ||
256 | |||
257 | Example 4: Set up the default pin state for uart controller. | ||
258 | |||
259 | static int s3c24xx_serial_probe(struct platform_device *pdev) { | ||
260 | struct pinctrl *pinctrl; | ||
261 | |||
262 | /* ... */ | ||
263 | |||
264 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
265 | } | ||
diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt deleted file mode 100644 index 74499e5033f..00000000000 --- a/Documentation/devicetree/bindings/power/opp.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * Generic OPP Interface | ||
2 | |||
3 | SoCs have a standard set of tuples consisting of frequency and | ||
4 | voltage pairs that the device will support per voltage domain. These | ||
5 | are called Operating Performance Points or OPPs. | ||
6 | |||
7 | Properties: | ||
8 | - operating-points: An array of 2-tuples items, and each item consists | ||
9 | of frequency and voltage like <freq-kHz vol-uV>. | ||
10 | freq: clock frequency in kHz | ||
11 | vol: voltage in microvolt | ||
12 | |||
13 | Examples: | ||
14 | |||
15 | cpu@0 { | ||
16 | compatible = "arm,cortex-a9"; | ||
17 | reg = <0>; | ||
18 | next-level-cache = <&L2>; | ||
19 | operating-points = < | ||
20 | /* kHz uV */ | ||
21 | 792000 1100000 | ||
22 | 396000 950000 | ||
23 | 198000 850000 | ||
24 | >; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt b/Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt deleted file mode 100644 index 0ba1bcc7f33..00000000000 --- a/Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | === AB8500 Battery Temperature Monitor Driver === | ||
2 | |||
3 | The properties below describes the node for btemp driver. | ||
4 | |||
5 | Required Properties: | ||
6 | - compatible = Shall be: "stericsson,ab8500-btemp" | ||
7 | - battery = Shall be battery specific information | ||
8 | |||
9 | Example: | ||
10 | ab8500_btemp { | ||
11 | compatible = "stericsson,ab8500-btemp"; | ||
12 | battery = <&ab8500_battery>; | ||
13 | }; | ||
14 | |||
15 | For information on battery specific node, Ref: | ||
16 | Documentation/devicetree/bindings/power_supply/ab8500/fg.txt | ||
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt b/Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt deleted file mode 100644 index ef532837112..00000000000 --- a/Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | === AB8500 Charging Algorithm Driver === | ||
2 | |||
3 | The properties below describes the node for chargalg driver. | ||
4 | |||
5 | Required Properties: | ||
6 | - compatible = Shall be: "stericsson,ab8500-chargalg" | ||
7 | - battery = Shall be battery specific information | ||
8 | |||
9 | Example: | ||
10 | ab8500_chargalg { | ||
11 | compatible = "stericsson,ab8500-chargalg"; | ||
12 | battery = <&ab8500_battery>; | ||
13 | }; | ||
14 | |||
15 | For information on battery specific node, Ref: | ||
16 | Documentation/devicetree/bindings/power_supply/ab8500/fg.txt | ||
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/charger.txt b/Documentation/devicetree/bindings/power_supply/ab8500/charger.txt deleted file mode 100644 index 6bdbb08ea9e..00000000000 --- a/Documentation/devicetree/bindings/power_supply/ab8500/charger.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | === AB8500 Charger Driver === | ||
2 | |||
3 | Required Properties: | ||
4 | - compatible = Shall be "stericsson,ab8500-charger" | ||
5 | - battery = Shall be battery specific information | ||
6 | Example: | ||
7 | ab8500_charger { | ||
8 | compatible = "stericsson,ab8500-charger"; | ||
9 | battery = <&ab8500_battery>; | ||
10 | }; | ||
11 | |||
12 | - vddadc-supply: Supply for USB and Main charger | ||
13 | Example: | ||
14 | ab8500-charger { | ||
15 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | ||
16 | } | ||
17 | - autopower_cfg: | ||
18 | Boolean value depicting the presence of 'automatic poweron after powerloss' | ||
19 | Example: | ||
20 | ab8500-charger { | ||
21 | autopower_cfg; | ||
22 | }; | ||
23 | |||
24 | For information on battery specific node, Ref: | ||
25 | Documentation/devicetree/bindings/power_supply/ab8500/fg.txt | ||
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/fg.txt b/Documentation/devicetree/bindings/power_supply/ab8500/fg.txt deleted file mode 100644 index ccafcb9112f..00000000000 --- a/Documentation/devicetree/bindings/power_supply/ab8500/fg.txt +++ /dev/null | |||
@@ -1,58 +0,0 @@ | |||
1 | === AB8500 Fuel Gauge Driver === | ||
2 | |||
3 | AB8500 is a mixed signal multimedia and power management | ||
4 | device comprising: power and energy-management-module, | ||
5 | wall-charger, usb-charger, audio codec, general purpose adc, | ||
6 | tvout, clock management and sim card interface. | ||
7 | |||
8 | Fuelgauge support is part of energy-management-modules, other | ||
9 | components of this module are: | ||
10 | main-charger, usb-combo-charger and battery-temperature-monitoring. | ||
11 | |||
12 | The properties below describes the node for fuelgauge driver. | ||
13 | |||
14 | Required Properties: | ||
15 | - compatible = This shall be: "stericsson,ab8500-fg" | ||
16 | - battery = Shall be battery specific information | ||
17 | Example: | ||
18 | ab8500_fg { | ||
19 | compatible = "stericsson,ab8500-fg"; | ||
20 | battery = <&ab8500_battery>; | ||
21 | }; | ||
22 | |||
23 | dependent node: | ||
24 | ab8500_battery: ab8500_battery { | ||
25 | }; | ||
26 | This node will provide information on 'thermistor interface' and | ||
27 | 'battery technology type' used. | ||
28 | |||
29 | Properties of this node are: | ||
30 | thermistor-on-batctrl: | ||
31 | A boolean value indicating thermistor interface to battery | ||
32 | |||
33 | Note: | ||
34 | 'btemp' and 'batctrl' are the pins interfaced for battery temperature | ||
35 | measurement, 'btemp' signal is used when NTC(negative temperature | ||
36 | coefficient) resister is interfaced external to battery whereas | ||
37 | 'batctrl' pin is used when NTC resister is internal to battery. | ||
38 | |||
39 | Example: | ||
40 | ab8500_battery: ab8500_battery { | ||
41 | thermistor-on-batctrl; | ||
42 | }; | ||
43 | indicates: NTC resister is internal to battery, 'batctrl' is used | ||
44 | for thermal measurement. | ||
45 | |||
46 | The absence of property 'thermal-on-batctrl' indicates | ||
47 | NTC resister is external to battery and 'btemp' signal is used | ||
48 | for thermal measurement. | ||
49 | |||
50 | battery-type: | ||
51 | This shall be the battery manufacturing technology type, | ||
52 | allowed types are: | ||
53 | "UNKNOWN" "NiMH" "LION" "LIPO" "LiFe" "NiCd" "LiMn" | ||
54 | Example: | ||
55 | ab8500_battery: ab8500_battery { | ||
56 | stericsson,battery-type = "LIPO"; | ||
57 | } | ||
58 | |||
diff --git a/Documentation/devicetree/bindings/power_supply/max17042_battery.txt b/Documentation/devicetree/bindings/power_supply/max17042_battery.txt deleted file mode 100644 index 5bc9b685cf8..00000000000 --- a/Documentation/devicetree/bindings/power_supply/max17042_battery.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | max17042_battery | ||
2 | ~~~~~~~~~~~~~~~~ | ||
3 | |||
4 | Required properties : | ||
5 | - compatible : "maxim,max17042" | ||
6 | |||
7 | Optional properties : | ||
8 | - maxim,rsns-microohm : Resistance of rsns resistor in micro Ohms | ||
9 | (datasheet-recommended value is 10000). | ||
10 | Defining this property enables current-sense functionality. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | battery-charger@36 { | ||
15 | compatible = "maxim,max17042"; | ||
16 | reg = <0x36>; | ||
17 | maxim,rsns-microohm = <10000>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/power_supply/olpc_battery.txt b/Documentation/devicetree/bindings/power_supply/olpc_battery.txt deleted file mode 100644 index c8901b3992d..00000000000 --- a/Documentation/devicetree/bindings/power_supply/olpc_battery.txt +++ /dev/null | |||
@@ -1,5 +0,0 @@ | |||
1 | OLPC battery | ||
2 | ~~~~~~~~~~~~ | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "olpc,xo1-battery" | ||
diff --git a/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt b/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt deleted file mode 100644 index c40e8926fac..00000000000 --- a/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | SBS sbs-battery | ||
2 | ~~~~~~~~~~ | ||
3 | |||
4 | Required properties : | ||
5 | - compatible : "sbs,sbs-battery" | ||
6 | |||
7 | Optional properties : | ||
8 | - sbs,i2c-retry-count : The number of times to retry i2c transactions on i2c | ||
9 | IO failure. | ||
10 | - sbs,poll-retry-count : The number of times to try looking for new status | ||
11 | after an external change notification. | ||
12 | - sbs,battery-detect-gpios : The gpio which signals battery detection and | ||
13 | a flag specifying its polarity. | ||
14 | |||
15 | Example: | ||
16 | |||
17 | bq20z75@b { | ||
18 | compatible = "sbs,sbs-battery"; | ||
19 | reg = < 0xb >; | ||
20 | sbs,i2c-retry-count = <2>; | ||
21 | sbs,poll-retry-count = <10>; | ||
22 | sbs,battery-detect-gpios = <&gpio-controller 122 1>; | ||
23 | } | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/powerpc/fsl/board.txt index 380914e965e..39e941515a3 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/board.txt | |||
@@ -1,8 +1,3 @@ | |||
1 | Freescale Reference Board Bindings | ||
2 | |||
3 | This document describes device tree bindings for various devices that | ||
4 | exist on some Freescale reference boards. | ||
5 | |||
6 | * Board Control and Status (BCSR) | 1 | * Board Control and Status (BCSR) |
7 | 2 | ||
8 | Required properties: | 3 | Required properties: |
@@ -17,26 +12,25 @@ Example: | |||
17 | reg = <f8000000 8000>; | 12 | reg = <f8000000 8000>; |
18 | }; | 13 | }; |
19 | 14 | ||
20 | * Freescale on-board FPGA | 15 | * Freescale on board FPGA |
21 | 16 | ||
22 | This is the memory-mapped registers for on board FPGA. | 17 | This is the memory-mapped registers for on board FPGA. |
23 | 18 | ||
24 | Required properities: | 19 | Required properities: |
25 | - compatible: should be a board-specific string followed by a string | 20 | - compatible : should be "fsl,fpga-pixis". |
26 | indicating the type of FPGA. Example: | 21 | - reg : should contain the address and the length of the FPPGA register |
27 | "fsl,<board>-fpga", "fsl,fpga-pixis" | 22 | set. |
28 | - reg: should contain the address and the length of the FPGA register set. | ||
29 | - interrupt-parent: should specify phandle for the interrupt controller. | 23 | - interrupt-parent: should specify phandle for the interrupt controller. |
30 | - interrupts: should specify event (wakeup) IRQ. | 24 | - interrupts : should specify event (wakeup) IRQ. |
31 | 25 | ||
32 | Example (P1022DS): | 26 | Example (MPC8610HPCD): |
33 | 27 | ||
34 | board-control@3,0 { | 28 | board-control@e8000000 { |
35 | compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis"; | 29 | compatible = "fsl,fpga-pixis"; |
36 | reg = <3 0 0x30>; | 30 | reg = <0xe8000000 32>; |
37 | interrupt-parent = <&mpic>; | 31 | interrupt-parent = <&mpic>; |
38 | interrupts = <8 8 0 0>; | 32 | interrupts = <8 8>; |
39 | }; | 33 | }; |
40 | 34 | ||
41 | * Freescale BCSR GPIO banks | 35 | * Freescale BCSR GPIO banks |
42 | 36 | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt b/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt deleted file mode 100644 index 9d54eb5a295..00000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt +++ /dev/null | |||
@@ -1,395 +0,0 @@ | |||
1 | =================================================================== | ||
2 | Debug Control and Status Register (DCSR) Binding | ||
3 | Copyright 2011 Freescale Semiconductor Inc. | ||
4 | |||
5 | NOTE: The bindings described in this document are preliminary and subject | ||
6 | to change. Some of the compatible strings that contain only generic names | ||
7 | may turn out to be inappropriate, or need additional properties to describe | ||
8 | the integration of the block with the rest of the chip. | ||
9 | |||
10 | ===================================================================== | ||
11 | Debug Control and Status Register Memory Map | ||
12 | |||
13 | Description | ||
14 | |||
15 | This node defines the base address and range for the | ||
16 | defined DCSR Memory Map. Child nodes will describe the individual | ||
17 | debug blocks defined within this memory space. | ||
18 | |||
19 | PROPERTIES | ||
20 | |||
21 | - compatible | ||
22 | Usage: required | ||
23 | Value type: <string> | ||
24 | Definition: Must include "fsl,dcsr" and "simple-bus". | ||
25 | The DCSR space exists in the memory-mapped bus. | ||
26 | |||
27 | - #address-cells | ||
28 | Usage: required | ||
29 | Value type: <u32> | ||
30 | Definition: A standard property. Defines the number of cells | ||
31 | or representing physical addresses in child nodes. | ||
32 | |||
33 | - #size-cells | ||
34 | Usage: required | ||
35 | Value type: <u32> | ||
36 | Definition: A standard property. Defines the number of cells | ||
37 | or representing the size of physical addresses in | ||
38 | child nodes. | ||
39 | |||
40 | - ranges | ||
41 | Usage: required | ||
42 | Value type: <prop-encoded-array> | ||
43 | Definition: A standard property. Specifies the physical address | ||
44 | range of the DCSR space. | ||
45 | |||
46 | EXAMPLE | ||
47 | dcsr: dcsr@f00000000 { | ||
48 | #address-cells = <1>; | ||
49 | #size-cells = <1>; | ||
50 | compatible = "fsl,dcsr", "simple-bus"; | ||
51 | ranges = <0x00000000 0xf 0x00000000 0x01008000>; | ||
52 | }; | ||
53 | |||
54 | ===================================================================== | ||
55 | Event Processing Unit | ||
56 | |||
57 | This node represents the region of DCSR space allocated to the EPU | ||
58 | |||
59 | PROPERTIES | ||
60 | |||
61 | - compatible | ||
62 | Usage: required | ||
63 | Value type: <string> | ||
64 | Definition: Must include "fsl,dcsr-epu" | ||
65 | |||
66 | - interrupts | ||
67 | Usage: required | ||
68 | Value type: <prop_encoded-array> | ||
69 | Definition: Specifies the interrupts generated by the EPU. | ||
70 | The value of the interrupts property consists of three | ||
71 | interrupt specifiers. The format of the specifier is defined | ||
72 | by the binding document describing the node's interrupt parent. | ||
73 | |||
74 | The EPU counters can be configured to assert the performance | ||
75 | monitor interrupt signal based on either counter overflow or value | ||
76 | match. Which counter asserted the interrupt is captured in an EPU | ||
77 | Counter Interrupt Status Register (EPCPUISR). | ||
78 | |||
79 | The EPU unit can also be configured to assert either or both of | ||
80 | two interrupt signals based on debug event sources within the SoC. | ||
81 | The interrupt signals are epu_xt_int0 and epu_xt_int1. | ||
82 | Which event source asserted the interrupt is captured in an EPU | ||
83 | Interrupt Status Register (EPISR0,EPISR1). | ||
84 | |||
85 | Interrupt numbers are lised in order (perfmon, event0, event1). | ||
86 | |||
87 | - interrupt-parent | ||
88 | Usage: required | ||
89 | Value type: <phandle> | ||
90 | Definition: A single <phandle> value that points | ||
91 | to the interrupt parent to which the child domain | ||
92 | is being mapped. Value must be "&mpic" | ||
93 | |||
94 | - reg | ||
95 | Usage: required | ||
96 | Value type: <prop-encoded-array> | ||
97 | Definition: A standard property. Specifies the physical address | ||
98 | offset and length of the DCSR space registers of the device | ||
99 | configuration block. | ||
100 | |||
101 | EXAMPLE | ||
102 | dcsr-epu@0 { | ||
103 | compatible = "fsl,dcsr-epu"; | ||
104 | interrupts = <52 2 0 0 | ||
105 | 84 2 0 0 | ||
106 | 85 2 0 0>; | ||
107 | interrupt-parent = <&mpic>; | ||
108 | reg = <0x0 0x1000>; | ||
109 | }; | ||
110 | |||
111 | ======================================================================= | ||
112 | Nexus Port Controller | ||
113 | |||
114 | This node represents the region of DCSR space allocated to the NPC | ||
115 | |||
116 | PROPERTIES | ||
117 | |||
118 | - compatible | ||
119 | Usage: required | ||
120 | Value type: <string> | ||
121 | Definition: Must include "fsl,dcsr-npc" | ||
122 | |||
123 | - reg | ||
124 | Usage: required | ||
125 | Value type: <prop-encoded-array> | ||
126 | Definition: A standard property. Specifies the physical address | ||
127 | offset and length of the DCSR space registers of the device | ||
128 | configuration block. | ||
129 | The Nexus Port controller occupies two regions in the DCSR space | ||
130 | with distinct functionality. | ||
131 | |||
132 | The first register range describes the Nexus Port Controller | ||
133 | control and status registers. | ||
134 | |||
135 | The second register range describes the Nexus Port Controller | ||
136 | internal trace buffer. The NPC trace buffer is a small memory buffer | ||
137 | which stages the nexus trace data for transmission via the Aurora port | ||
138 | or to a DDR based trace buffer. In some configurations the NPC trace | ||
139 | buffer can be the only trace buffer used. | ||
140 | |||
141 | |||
142 | EXAMPLE | ||
143 | dcsr-npc { | ||
144 | compatible = "fsl,dcsr-npc"; | ||
145 | reg = <0x1000 0x1000 0x1000000 0x8000>; | ||
146 | }; | ||
147 | |||
148 | ======================================================================= | ||
149 | Nexus Concentrator | ||
150 | |||
151 | This node represents the region of DCSR space allocated to the NXC | ||
152 | |||
153 | PROPERTIES | ||
154 | |||
155 | - compatible | ||
156 | Usage: required | ||
157 | Value type: <string> | ||
158 | Definition: Must include "fsl,dcsr-nxc" | ||
159 | |||
160 | - reg | ||
161 | Usage: required | ||
162 | Value type: <prop-encoded-array> | ||
163 | Definition: A standard property. Specifies the physical address | ||
164 | offset and length of the DCSR space registers of the device | ||
165 | configuration block. | ||
166 | |||
167 | EXAMPLE | ||
168 | dcsr-nxc@2000 { | ||
169 | compatible = "fsl,dcsr-nxc"; | ||
170 | reg = <0x2000 0x1000>; | ||
171 | }; | ||
172 | ======================================================================= | ||
173 | CoreNet Debug Controller | ||
174 | |||
175 | This node represents the region of DCSR space allocated to | ||
176 | the CoreNet Debug controller. | ||
177 | |||
178 | PROPERTIES | ||
179 | |||
180 | - compatible | ||
181 | Usage: required | ||
182 | Value type: <string> | ||
183 | Definition: Must include "fsl,dcsr-corenet" | ||
184 | |||
185 | - reg | ||
186 | Usage: required | ||
187 | Value type: <prop-encoded-array> | ||
188 | Definition: A standard property. Specifies the physical address | ||
189 | offset and length of the DCSR space registers of the device | ||
190 | configuration block. | ||
191 | The CoreNet Debug controller occupies two regions in the DCSR space | ||
192 | with distinct functionality. | ||
193 | |||
194 | The first register range describes the CoreNet Debug Controller | ||
195 | functionalty to perform transaction and transaction attribute matches. | ||
196 | |||
197 | The second register range describes the CoreNet Debug Controller | ||
198 | functionalty to trigger event notifications and debug traces. | ||
199 | |||
200 | EXAMPLE | ||
201 | dcsr-corenet { | ||
202 | compatible = "fsl,dcsr-corenet"; | ||
203 | reg = <0x8000 0x1000 0xB0000 0x1000>; | ||
204 | }; | ||
205 | |||
206 | ======================================================================= | ||
207 | Data Path Debug controller | ||
208 | |||
209 | This node represents the region of DCSR space allocated to | ||
210 | the DPAA Debug Controller. This controller controls debug configuration | ||
211 | for the QMAN and FMAN blocks. | ||
212 | |||
213 | PROPERTIES | ||
214 | |||
215 | - compatible | ||
216 | Usage: required | ||
217 | Value type: <string> | ||
218 | Definition: Must include both an identifier specific to the SoC | ||
219 | or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the | ||
220 | generic compatible string "fsl,dcsr-dpaa". | ||
221 | |||
222 | - reg | ||
223 | Usage: required | ||
224 | Value type: <prop-encoded-array> | ||
225 | Definition: A standard property. Specifies the physical address | ||
226 | offset and length of the DCSR space registers of the device | ||
227 | configuration block. | ||
228 | |||
229 | EXAMPLE | ||
230 | dcsr-dpaa@9000 { | ||
231 | compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa"; | ||
232 | reg = <0x9000 0x1000>; | ||
233 | }; | ||
234 | |||
235 | ======================================================================= | ||
236 | OCeaN Debug controller | ||
237 | |||
238 | This node represents the region of DCSR space allocated to | ||
239 | the OCN Debug Controller. | ||
240 | |||
241 | PROPERTIES | ||
242 | |||
243 | - compatible | ||
244 | Usage: required | ||
245 | Value type: <string> | ||
246 | Definition: Must include both an identifier specific to the SoC | ||
247 | or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the | ||
248 | generic compatible string "fsl,dcsr-ocn". | ||
249 | |||
250 | - reg | ||
251 | Usage: required | ||
252 | Value type: <prop-encoded-array> | ||
253 | Definition: A standard property. Specifies the physical address | ||
254 | offset and length of the DCSR space registers of the device | ||
255 | configuration block. | ||
256 | |||
257 | EXAMPLE | ||
258 | dcsr-ocn@11000 { | ||
259 | compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn"; | ||
260 | reg = <0x11000 0x1000>; | ||
261 | }; | ||
262 | |||
263 | ======================================================================= | ||
264 | DDR Controller Debug controller | ||
265 | |||
266 | This node represents the region of DCSR space allocated to | ||
267 | the OCN Debug Controller. | ||
268 | |||
269 | PROPERTIES | ||
270 | |||
271 | - compatible | ||
272 | Usage: required | ||
273 | Value type: <string> | ||
274 | Definition: Must include "fsl,dcsr-ddr" | ||
275 | |||
276 | - dev-handle | ||
277 | Usage: required | ||
278 | Definition: A phandle to associate this debug node with its | ||
279 | component controller. | ||
280 | |||
281 | - reg | ||
282 | Usage: required | ||
283 | Value type: <prop-encoded-array> | ||
284 | Definition: A standard property. Specifies the physical address | ||
285 | offset and length of the DCSR space registers of the device | ||
286 | configuration block. | ||
287 | |||
288 | EXAMPLE | ||
289 | dcsr-ddr@12000 { | ||
290 | compatible = "fsl,dcsr-ddr"; | ||
291 | dev-handle = <&ddr1>; | ||
292 | reg = <0x12000 0x1000>; | ||
293 | }; | ||
294 | |||
295 | ======================================================================= | ||
296 | Nexus Aurora Link Controller | ||
297 | |||
298 | This node represents the region of DCSR space allocated to | ||
299 | the NAL Controller. | ||
300 | |||
301 | PROPERTIES | ||
302 | |||
303 | - compatible | ||
304 | Usage: required | ||
305 | Value type: <string> | ||
306 | Definition: Must include both an identifier specific to the SoC | ||
307 | or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the | ||
308 | generic compatible string "fsl,dcsr-nal". | ||
309 | |||
310 | - reg | ||
311 | Usage: required | ||
312 | Value type: <prop-encoded-array> | ||
313 | Definition: A standard property. Specifies the physical address | ||
314 | offset and length of the DCSR space registers of the device | ||
315 | configuration block. | ||
316 | |||
317 | EXAMPLE | ||
318 | dcsr-nal@18000 { | ||
319 | compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal"; | ||
320 | reg = <0x18000 0x1000>; | ||
321 | }; | ||
322 | |||
323 | |||
324 | ======================================================================= | ||
325 | Run Control and Power Management | ||
326 | |||
327 | This node represents the region of DCSR space allocated to | ||
328 | the RCPM Debug Controller. This functionlity is limited to the | ||
329 | control the debug operations of the SoC and cores. | ||
330 | |||
331 | PROPERTIES | ||
332 | |||
333 | - compatible | ||
334 | Usage: required | ||
335 | Value type: <string> | ||
336 | Definition: Must include both an identifier specific to the SoC | ||
337 | or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the | ||
338 | generic compatible string "fsl,dcsr-rcpm". | ||
339 | |||
340 | - reg | ||
341 | Usage: required | ||
342 | Value type: <prop-encoded-array> | ||
343 | Definition: A standard property. Specifies the physical address | ||
344 | offset and length of the DCSR space registers of the device | ||
345 | configuration block. | ||
346 | |||
347 | EXAMPLE | ||
348 | dcsr-rcpm@22000 { | ||
349 | compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm"; | ||
350 | reg = <0x22000 0x1000>; | ||
351 | }; | ||
352 | |||
353 | ======================================================================= | ||
354 | Core Service Bridge Proxy | ||
355 | |||
356 | This node represents the region of DCSR space allocated to | ||
357 | the Core Service Bridge Proxies. | ||
358 | There is one Core Service Bridge Proxy device for each CPU in the system. | ||
359 | This functionlity provides access to the debug operations of the CPU. | ||
360 | |||
361 | PROPERTIES | ||
362 | |||
363 | - compatible | ||
364 | Usage: required | ||
365 | Value type: <string> | ||
366 | Definition: Must include both an identifier specific to the cpu | ||
367 | of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the | ||
368 | generic compatible string "fsl,dcsr-cpu-sb-proxy". | ||
369 | |||
370 | - cpu-handle | ||
371 | Usage: required | ||
372 | Definition: A phandle to associate this debug node with its cpu. | ||
373 | |||
374 | - reg | ||
375 | Usage: required | ||
376 | Value type: <prop-encoded-array> | ||
377 | Definition: A standard property. Specifies the physical address | ||
378 | offset and length of the DCSR space registers of the device | ||
379 | configuration block. | ||
380 | |||
381 | EXAMPLE | ||
382 | dcsr-cpu-sb-proxy@40000 { | ||
383 | compatible = "fsl,dcsr-e500mc-sb-proxy", | ||
384 | "fsl,dcsr-cpu-sb-proxy"; | ||
385 | cpu-handle = <&cpu0>; | ||
386 | reg = <0x40000 0x1000>; | ||
387 | }; | ||
388 | dcsr-cpu-sb-proxy@41000 { | ||
389 | compatible = "fsl,dcsr-e500mc-sb-proxy", | ||
390 | "fsl,dcsr-cpu-sb-proxy"; | ||
391 | cpu-handle = <&cpu1>; | ||
392 | reg = <0x41000 0x1000>; | ||
393 | }; | ||
394 | |||
395 | ======================================================================= | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt index d5e370450ac..939a26d541f 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt | |||
@@ -12,12 +12,9 @@ Properties: | |||
12 | - #size-cells : Either one or two, depending on how large each chipselect | 12 | - #size-cells : Either one or two, depending on how large each chipselect |
13 | can be. | 13 | can be. |
14 | - reg : Offset and length of the register set for the device | 14 | - reg : Offset and length of the register set for the device |
15 | - interrupts: IFC may have one or two interrupts. If two interrupt | 15 | - interrupts : IFC has two interrupts. The first one is the "common" |
16 | specifiers are present, the first is the "common" | 16 | interrupt(CM_EVTER_STAT), and second is the NAND interrupt |
17 | interrupt (CM_EVTER_STAT), and the second is the NAND | 17 | (NAND_EVTER_STAT). |
18 | interrupt (NAND_EVTER_STAT). If there is only one, | ||
19 | that interrupt reports both types of event. | ||
20 | |||
21 | 18 | ||
22 | - ranges : Each range corresponds to a single chipselect, and covers | 19 | - ranges : Each range corresponds to a single chipselect, and covers |
23 | the entire access window as configured. | 20 | the entire access window as configured. |
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt deleted file mode 100644 index bc8ded641ab..00000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt +++ /dev/null | |||
@@ -1,63 +0,0 @@ | |||
1 | * FSL MPIC Message Registers | ||
2 | |||
3 | This binding specifies what properties must be available in the device tree | ||
4 | representation of the message register blocks found in some FSL MPIC | ||
5 | implementations. | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible: Specifies the compatibility list for the message register | ||
10 | block. The type shall be <string-list> and the value shall be of the form | ||
11 | "fsl,mpic-v<version>-msgr", where <version> is the version number of | ||
12 | the MPIC containing the message registers. | ||
13 | |||
14 | - reg: Specifies the base physical address(s) and size(s) of the | ||
15 | message register block's addressable register space. The type shall be | ||
16 | <prop-encoded-array>. | ||
17 | |||
18 | - interrupts: Specifies a list of interrupt-specifiers which are available | ||
19 | for receiving interrupts. Interrupt-specifier consists of two cells: first | ||
20 | cell is interrupt-number and second cell is level-sense. The type shall be | ||
21 | <prop-encoded-array>. | ||
22 | |||
23 | Optional properties: | ||
24 | |||
25 | - mpic-msgr-receive-mask: Specifies what registers in the containing block | ||
26 | are allowed to receive interrupts. The value is a bit mask where a set | ||
27 | bit at bit 'n' indicates that message register 'n' can receive interrupts. | ||
28 | Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall | ||
29 | be <u32>. If not present, then all of the message registers in the block | ||
30 | are available. | ||
31 | |||
32 | Aliases: | ||
33 | |||
34 | An alias should be created for every message register block. They are not | ||
35 | required, though. However, a particular implementation of this binding | ||
36 | may require aliases to be present. Aliases are of the form | ||
37 | 'mpic-msgr-block<n>', where <n> is an integer specifying the block's number. | ||
38 | Numbers shall start at 0. | ||
39 | |||
40 | Example: | ||
41 | |||
42 | aliases { | ||
43 | mpic-msgr-block0 = &mpic_msgr_block0; | ||
44 | mpic-msgr-block1 = &mpic_msgr_block1; | ||
45 | }; | ||
46 | |||
47 | mpic_msgr_block0: mpic-msgr-block@41400 { | ||
48 | compatible = "fsl,mpic-v3.1-msgr"; | ||
49 | reg = <0x41400 0x200>; | ||
50 | // Message registers 0 and 2 in this block can receive interrupts on | ||
51 | // sources 0xb0 and 0xb2, respectively. | ||
52 | interrupts = <0xb0 2 0xb2 2>; | ||
53 | mpic-msgr-receive-mask = <0x5>; | ||
54 | }; | ||
55 | |||
56 | mpic_msgr_block1: mpic-msgr-block@42400 { | ||
57 | compatible = "fsl,mpic-v3.1-msgr"; | ||
58 | reg = <0x42400 0x200>; | ||
59 | // Message registers 0 and 2 in this block can receive interrupts on | ||
60 | // sources 0xb4 and 0xb6, respectively. | ||
61 | interrupts = <0xb4 2 0xb6 2>; | ||
62 | mpic-msgr-receive-mask = <0x5>; | ||
63 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt index dc5744636a5..2cf38bd841f 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt | |||
@@ -56,27 +56,7 @@ PROPERTIES | |||
56 | to the client. The presence of this property also mandates | 56 | to the client. The presence of this property also mandates |
57 | that any initialization related to interrupt sources shall | 57 | that any initialization related to interrupt sources shall |
58 | be limited to sources explicitly referenced in the device tree. | 58 | be limited to sources explicitly referenced in the device tree. |
59 | 59 | ||
60 | - big-endian | ||
61 | Usage: optional | ||
62 | Value type: <empty> | ||
63 | If present the MPIC will be assumed to be big-endian. Some | ||
64 | device-trees omit this property on MPIC nodes even when the MPIC is | ||
65 | in fact big-endian, so certain boards override this property. | ||
66 | |||
67 | - single-cpu-affinity | ||
68 | Usage: optional | ||
69 | Value type: <empty> | ||
70 | If present the MPIC will be assumed to only be able to route | ||
71 | non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC). | ||
72 | |||
73 | - last-interrupt-source | ||
74 | Usage: optional | ||
75 | Value type: <u32> | ||
76 | Some MPICs do not correctly report the number of hardware sources | ||
77 | in the global feature registers. If specified, this field will | ||
78 | override the value read from MPIC_GREG_FEATURE_LAST_SRC. | ||
79 | |||
80 | INTERRUPT SPECIFIER DEFINITION | 60 | INTERRUPT SPECIFIER DEFINITION |
81 | 61 | ||
82 | Interrupt specifiers consists of 4 cells encoded as | 62 | Interrupt specifiers consists of 4 cells encoded as |
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt index 5693877ab37..70558c3f368 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt | |||
@@ -6,10 +6,8 @@ Required properties: | |||
6 | etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on | 6 | etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on |
7 | the parent type. | 7 | the parent type. |
8 | 8 | ||
9 | - reg : It may contain one or two regions. The first region should contain | 9 | - reg : should contain the address and the length of the shared message |
10 | the address and the length of the shared message interrupt register set. | 10 | interrupt register set. |
11 | The second region should contain the address of aliased MSIIR register for | ||
12 | platforms that have such an alias. | ||
13 | 11 | ||
14 | - msi-available-ranges: use <start count> style section to define which | 12 | - msi-available-ranges: use <start count> style section to define which |
15 | msi interrupt can be used in the 256 msi interrupts. This property is | 13 | msi interrupt can be used in the 256 msi interrupts. This property is |
@@ -27,16 +25,6 @@ Required properties: | |||
27 | are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed | 25 | are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed |
28 | to MPIC. | 26 | to MPIC. |
29 | 27 | ||
30 | Optional properties: | ||
31 | - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register | ||
32 | is used for MSI messaging. The address of MSIIR in PCI address space is | ||
33 | the MSI message address. | ||
34 | |||
35 | This property may be used in virtualized environments where the hypervisor | ||
36 | has created an alternate mapping for the MSIR block. See below for an | ||
37 | explanation. | ||
38 | |||
39 | |||
40 | Example: | 28 | Example: |
41 | msi@41600 { | 29 | msi@41600 { |
42 | compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; | 30 | compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; |
@@ -53,35 +41,3 @@ Example: | |||
53 | 0xe7 0>; | 41 | 0xe7 0>; |
54 | interrupt-parent = <&mpic>; | 42 | interrupt-parent = <&mpic>; |
55 | }; | 43 | }; |
56 | |||
57 | The Freescale hypervisor and msi-address-64 | ||
58 | ------------------------------------------- | ||
59 | Normally, PCI devices have access to all of CCSR via an ATMU mapping. The | ||
60 | Freescale MSI driver calculates the address of MSIIR (in the MSI register | ||
61 | block) and sets that address as the MSI message address. | ||
62 | |||
63 | In a virtualized environment, the hypervisor may need to create an IOMMU | ||
64 | mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement | ||
65 | because of hardware limitations of the Peripheral Access Management Unit | ||
66 | (PAMU), which is currently the only IOMMU that the hypervisor supports. | ||
67 | The ATMU is programmed with the guest physical address, and the PAMU | ||
68 | intercepts transactions and reroutes them to the true physical address. | ||
69 | |||
70 | In the PAMU, each PCI controller is given only one primary window. The | ||
71 | PAMU restricts DMA operations so that they can only occur within a window. | ||
72 | Because PCI devices must be able to DMA to memory, the primary window must | ||
73 | be used to cover all of the guest's memory space. | ||
74 | |||
75 | PAMU primary windows can be divided into 256 subwindows, and each | ||
76 | subwindow can have its own address mapping ("guest physical" to "true | ||
77 | physical"). However, each subwindow has to have the same alignment, which | ||
78 | means they cannot be located at just any address. Because of these | ||
79 | restrictions, it is usually impossible to create a 4KB subwindow that | ||
80 | covers MSIIR where it's normally located. | ||
81 | |||
82 | Therefore, the hypervisor has to create a subwindow inside the same | ||
83 | primary window used for memory, but mapped to the MSIR block (where MSIIR | ||
84 | lives). The first subwindow after the end of guest memory is used for | ||
85 | this. The address specified in the msi-address-64 property is the PCI | ||
86 | address of MSIIR. The hypervisor configures the PAMU to map that address to | ||
87 | the true physical address of MSIIR. | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt b/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt deleted file mode 100644 index 4ad29b9ac2a..00000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt +++ /dev/null | |||
@@ -1,81 +0,0 @@ | |||
1 | * Freescale 85xx RAID Engine nodes | ||
2 | |||
3 | RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID | ||
4 | Engine should have a separate node. | ||
5 | |||
6 | Supported chips: | ||
7 | P5020, P5040 | ||
8 | |||
9 | Required properties: | ||
10 | |||
11 | - compatible: Should contain "fsl,raideng-v1.0" as the value | ||
12 | This identifies RAID Engine block. 1 in 1.0 represents | ||
13 | major number whereas 0 represents minor number. The | ||
14 | version matches the hardware IP version. | ||
15 | - reg: offset and length of the register set for the device | ||
16 | - ranges: standard ranges property specifying the translation | ||
17 | between child address space and parent address space | ||
18 | |||
19 | Example: | ||
20 | /* P5020 */ | ||
21 | raideng: raideng@320000 { | ||
22 | compatible = "fsl,raideng-v1.0"; | ||
23 | #address-cells = <1>; | ||
24 | #size-cells = <1>; | ||
25 | reg = <0x320000 0x10000>; | ||
26 | ranges = <0 0x320000 0x10000>; | ||
27 | }; | ||
28 | |||
29 | |||
30 | There must be a sub-node for each job queue present in RAID Engine | ||
31 | This node must be a sub-node of the main RAID Engine node | ||
32 | |||
33 | - compatible: Should contain "fsl,raideng-v1.0-job-queue" as the value | ||
34 | This identifies the job queue interface | ||
35 | - reg: offset and length of the register set for job queue | ||
36 | - ranges: standard ranges property specifying the translation | ||
37 | between child address space and parent address space | ||
38 | |||
39 | Example: | ||
40 | /* P5020 */ | ||
41 | raideng_jq0@1000 { | ||
42 | compatible = "fsl,raideng-v1.0-job-queue"; | ||
43 | reg = <0x1000 0x1000>; | ||
44 | ranges = <0x0 0x1000 0x1000>; | ||
45 | }; | ||
46 | |||
47 | |||
48 | There must be a sub-node for each job ring present in RAID Engine | ||
49 | This node must be a sub-node of job queue node | ||
50 | |||
51 | - compatible: Must contain "fsl,raideng-v1.0-job-ring" as the value | ||
52 | This identifies job ring. Should contain either | ||
53 | "fsl,raideng-v1.0-hp-ring" or "fsl,raideng-v1.0-lp-ring" | ||
54 | depending upon whether ring has high or low priority | ||
55 | - reg: offset and length of the register set for job ring | ||
56 | - interrupts: interrupt mapping for job ring IRQ | ||
57 | |||
58 | Optional property: | ||
59 | |||
60 | - fsl,liodn: Specifies the LIODN to be used for Job Ring. This | ||
61 | property is normally set by firmware. Value | ||
62 | is of 12-bits which is the LIODN number for this JR. | ||
63 | This property is used by the IOMMU (PAMU) to distinquish | ||
64 | transactions from this JR and than be able to do address | ||
65 | translation & protection accordingly. | ||
66 | |||
67 | Example: | ||
68 | /* P5020 */ | ||
69 | raideng_jq0@1000 { | ||
70 | compatible = "fsl,raideng-v1.0-job-queue"; | ||
71 | reg = <0x1000 0x1000>; | ||
72 | ranges = <0x0 0x1000 0x1000>; | ||
73 | |||
74 | raideng_jr0: jr@0 { | ||
75 | compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring"; | ||
76 | reg = <0x0 0x400>; | ||
77 | interrupts = <139 2 0 0>; | ||
78 | interrupt-parent = <&mpic>; | ||
79 | fsl,liodn = <0x41>; | ||
80 | }; | ||
81 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt deleted file mode 100644 index b9a8a2bcfae..00000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt +++ /dev/null | |||
@@ -1,163 +0,0 @@ | |||
1 | Message unit node: | ||
2 | |||
3 | For SRIO controllers that implement the message unit as part of the controller | ||
4 | this node is required. For devices with RMAN this node should NOT exist. The | ||
5 | node is composed of three types of sub-nodes ("fsl-srio-msg-unit", | ||
6 | "fsl-srio-dbell-unit" and "fsl-srio-port-write-unit"). | ||
7 | |||
8 | See srio.txt for more details about generic SRIO controller details. | ||
9 | |||
10 | - compatible | ||
11 | Usage: required | ||
12 | Value type: <string> | ||
13 | Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu". | ||
14 | |||
15 | The version X.Y should match the general SRIO controller's IP Block | ||
16 | revision register's Major(X) and Minor (Y) value. | ||
17 | |||
18 | - reg | ||
19 | Usage: required | ||
20 | Value type: <prop-encoded-array> | ||
21 | Definition: A standard property. Specifies the physical address and | ||
22 | length of the SRIO configuration registers for message units | ||
23 | and doorbell units. | ||
24 | |||
25 | - fsl,liodn | ||
26 | Usage: optional-but-recommended (for devices with PAMU) | ||
27 | Value type: <prop-encoded-array> | ||
28 | Definition: The logical I/O device number for the PAMU (IOMMU) to be | ||
29 | correctly configured for SRIO accesses. The property should | ||
30 | not exist on devices that do not support PAMU. | ||
31 | |||
32 | The LIODN value is associated with all RMU transactions | ||
33 | (msg-unit, doorbell, port-write). | ||
34 | |||
35 | Sub-Nodes for RMU: The RMU node is composed of multiple sub-nodes that | ||
36 | correspond to the actual sub-controllers in the RMU. The manual for a given | ||
37 | SoC will detail which and how many of these sub-controllers are implemented. | ||
38 | |||
39 | Message Unit: | ||
40 | |||
41 | - compatible | ||
42 | Usage: required | ||
43 | Value type: <string> | ||
44 | Definition: Must include "fsl,srio-msg-unit-vX.Y", "fsl,srio-msg-unit". | ||
45 | |||
46 | The version X.Y should match the general SRIO controller's IP Block | ||
47 | revision register's Major(X) and Minor (Y) value. | ||
48 | |||
49 | - reg | ||
50 | Usage: required | ||
51 | Value type: <prop-encoded-array> | ||
52 | Definition: A standard property. Specifies the physical address and | ||
53 | length of the SRIO configuration registers for message units | ||
54 | and doorbell units. | ||
55 | |||
56 | - interrupts | ||
57 | Usage: required | ||
58 | Value type: <prop_encoded-array> | ||
59 | Definition: Specifies the interrupts generated by this device. The | ||
60 | value of the interrupts property consists of one interrupt | ||
61 | specifier. The format of the specifier is defined by the | ||
62 | binding document describing the node's interrupt parent. | ||
63 | |||
64 | A pair of IRQs are specified in this property. The first | ||
65 | element is associated with the transmit (TX) interrupt and the | ||
66 | second element is associated with the receive (RX) interrupt. | ||
67 | |||
68 | Doorbell Unit: | ||
69 | |||
70 | - compatible | ||
71 | Usage: required | ||
72 | Value type: <string> | ||
73 | Definition: Must include: | ||
74 | "fsl,srio-dbell-unit-vX.Y", "fsl,srio-dbell-unit" | ||
75 | |||
76 | The version X.Y should match the general SRIO controller's IP Block | ||
77 | revision register's Major(X) and Minor (Y) value. | ||
78 | |||
79 | - reg | ||
80 | Usage: required | ||
81 | Value type: <prop-encoded-array> | ||
82 | Definition: A standard property. Specifies the physical address and | ||
83 | length of the SRIO configuration registers for message units | ||
84 | and doorbell units. | ||
85 | |||
86 | - interrupts | ||
87 | Usage: required | ||
88 | Value type: <prop_encoded-array> | ||
89 | Definition: Specifies the interrupts generated by this device. The | ||
90 | value of the interrupts property consists of one interrupt | ||
91 | specifier. The format of the specifier is defined by the | ||
92 | binding document describing the node's interrupt parent. | ||
93 | |||
94 | A pair of IRQs are specified in this property. The first | ||
95 | element is associated with the transmit (TX) interrupt and the | ||
96 | second element is associated with the receive (RX) interrupt. | ||
97 | |||
98 | Port-Write Unit: | ||
99 | |||
100 | - compatible | ||
101 | Usage: required | ||
102 | Value type: <string> | ||
103 | Definition: Must include: | ||
104 | "fsl,srio-port-write-unit-vX.Y", "fsl,srio-port-write-unit" | ||
105 | |||
106 | The version X.Y should match the general SRIO controller's IP Block | ||
107 | revision register's Major(X) and Minor (Y) value. | ||
108 | |||
109 | - reg | ||
110 | Usage: required | ||
111 | Value type: <prop-encoded-array> | ||
112 | Definition: A standard property. Specifies the physical address and | ||
113 | length of the SRIO configuration registers for message units | ||
114 | and doorbell units. | ||
115 | |||
116 | - interrupts | ||
117 | Usage: required | ||
118 | Value type: <prop_encoded-array> | ||
119 | Definition: Specifies the interrupts generated by this device. The | ||
120 | value of the interrupts property consists of one interrupt | ||
121 | specifier. The format of the specifier is defined by the | ||
122 | binding document describing the node's interrupt parent. | ||
123 | |||
124 | A single IRQ that handles port-write conditions is | ||
125 | specified by this property. (Typically shared with error). | ||
126 | |||
127 | Note: All other standard properties (see the ePAPR) are allowed | ||
128 | but are optional. | ||
129 | |||
130 | Example: | ||
131 | rmu: rmu@d3000 { | ||
132 | compatible = "fsl,srio-rmu"; | ||
133 | reg = <0xd3000 0x400>; | ||
134 | ranges = <0x0 0xd3000 0x400>; | ||
135 | fsl,liodn = <0xc8>; | ||
136 | |||
137 | message-unit@0 { | ||
138 | compatible = "fsl,srio-msg-unit"; | ||
139 | reg = <0x0 0x100>; | ||
140 | interrupts = < | ||
141 | 60 2 0 0 /* msg1_tx_irq */ | ||
142 | 61 2 0 0>;/* msg1_rx_irq */ | ||
143 | }; | ||
144 | message-unit@100 { | ||
145 | compatible = "fsl,srio-msg-unit"; | ||
146 | reg = <0x100 0x100>; | ||
147 | interrupts = < | ||
148 | 62 2 0 0 /* msg2_tx_irq */ | ||
149 | 63 2 0 0>;/* msg2_rx_irq */ | ||
150 | }; | ||
151 | doorbell-unit@400 { | ||
152 | compatible = "fsl,srio-dbell-unit"; | ||
153 | reg = <0x400 0x80>; | ||
154 | interrupts = < | ||
155 | 56 2 0 0 /* bell_outb_irq */ | ||
156 | 57 2 0 0>;/* bell_inb_irq */ | ||
157 | }; | ||
158 | port-write-unit@4e0 { | ||
159 | compatible = "fsl,srio-port-write-unit"; | ||
160 | reg = <0x4e0 0x20>; | ||
161 | interrupts = <16 2 1 11>; | ||
162 | }; | ||
163 | }; | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt deleted file mode 100644 index b039bcbee13..00000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt +++ /dev/null | |||
@@ -1,103 +0,0 @@ | |||
1 | * Freescale Serial RapidIO (SRIO) Controller | ||
2 | |||
3 | RapidIO port node: | ||
4 | Properties: | ||
5 | - compatible | ||
6 | Usage: required | ||
7 | Value type: <string> | ||
8 | Definition: Must include "fsl,srio" for IP blocks with IP Block | ||
9 | Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0. | ||
10 | |||
11 | Optionally, a compatiable string of "fsl,srio-vX.Y" where X is Major | ||
12 | version in IP Block Revision Register and Y is Minor version. If this | ||
13 | compatiable is provided it should be ordered before "fsl,srio". | ||
14 | |||
15 | - reg | ||
16 | Usage: required | ||
17 | Value type: <prop-encoded-array> | ||
18 | Definition: A standard property. Specifies the physical address and | ||
19 | length of the SRIO configuration registers. The size should | ||
20 | be set to 0x11000. | ||
21 | |||
22 | - interrupts | ||
23 | Usage: required | ||
24 | Value type: <prop_encoded-array> | ||
25 | Definition: Specifies the interrupts generated by this device. The | ||
26 | value of the interrupts property consists of one interrupt | ||
27 | specifier. The format of the specifier is defined by the | ||
28 | binding document describing the node's interrupt parent. | ||
29 | |||
30 | A single IRQ that handles error conditions is specified by this | ||
31 | property. (Typically shared with port-write). | ||
32 | |||
33 | - fsl,srio-rmu-handle: | ||
34 | Usage: required if rmu node is defined | ||
35 | Value type: <phandle> | ||
36 | Definition: A single <phandle> value that points to the RMU. | ||
37 | (See srio-rmu.txt for more details on RMU node binding) | ||
38 | |||
39 | Port Child Nodes: There should a port child node for each port that exists in | ||
40 | the controller. The ports are numbered starting at one (1) and should have | ||
41 | the following properties: | ||
42 | |||
43 | - cell-index | ||
44 | Usage: required | ||
45 | Value type: <u32> | ||
46 | Definition: A standard property. Matches the port id. | ||
47 | |||
48 | - ranges | ||
49 | Usage: required if local access windows preset | ||
50 | Value type: <prop-encoded-array> | ||
51 | Definition: A standard property. Utilized to describe the memory mapped | ||
52 | IO space utilized by the controller. This corresponds to the | ||
53 | setting of the local access windows that are targeted to this | ||
54 | SRIO port. | ||
55 | |||
56 | - fsl,liodn | ||
57 | Usage: optional-but-recommended (for devices with PAMU) | ||
58 | Value type: <prop-encoded-array> | ||
59 | Definition: The logical I/O device number for the PAMU (IOMMU) to be | ||
60 | correctly configured for SRIO accesses. The property should | ||
61 | not exist on devices that do not support PAMU. | ||
62 | |||
63 | For HW (ie, the P4080) that only supports a LIODN for both | ||
64 | memory and maintenance transactions then a single LIODN is | ||
65 | represented in the property for both transactions. | ||
66 | |||
67 | For HW (ie, the P304x/P5020, etc) that supports an LIODN for | ||
68 | memory transactions and a unique LIODN for maintenance | ||
69 | transactions then a pair of LIODNs are represented in the | ||
70 | property. Within the pair, the first element represents the | ||
71 | LIODN associated with memory transactions and the second element | ||
72 | represents the LIODN associated with maintenance transactions | ||
73 | for the port. | ||
74 | |||
75 | Note: All other standard properties (see ePAPR) are allowed but are optional. | ||
76 | |||
77 | Example: | ||
78 | |||
79 | rapidio: rapidio@ffe0c0000 { | ||
80 | #address-cells = <2>; | ||
81 | #size-cells = <2>; | ||
82 | reg = <0xf 0xfe0c0000 0 0x11000>; | ||
83 | compatible = "fsl,srio"; | ||
84 | interrupts = <16 2 1 11>; /* err_irq */ | ||
85 | fsl,srio-rmu-handle = <&rmu>; | ||
86 | ranges; | ||
87 | |||
88 | port1 { | ||
89 | cell-index = <1>; | ||
90 | #address-cells = <2>; | ||
91 | #size-cells = <2>; | ||
92 | fsl,liodn = <34>; | ||
93 | ranges = <0 0 0xc 0x20000000 0 0x10000000>; | ||
94 | }; | ||
95 | |||
96 | port2 { | ||
97 | cell-index = <2>; | ||
98 | #address-cells = <2>; | ||
99 | #size-cells = <2>; | ||
100 | fsl,liodn = <48>; | ||
101 | ranges = <0 0 0xc 0x30000000 0 0x10000000>; | ||
102 | }; | ||
103 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt deleted file mode 100644 index 8522bfbccfd..00000000000 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | Freescale i.MX PWM controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "fsl,<soc>-pwm" | ||
5 | - reg: physical base address and length of the controller's registers | ||
6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index | ||
7 | of the PWM to use and the second cell is the period in nanoseconds. | ||
8 | - interrupts: The interrupt for the pwm controller | ||
9 | |||
10 | Example: | ||
11 | |||
12 | pwm1: pwm@53fb4000 { | ||
13 | #pwm-cells = <2>; | ||
14 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | ||
15 | reg = <0x53fb4000 0x4000>; | ||
16 | interrupts = <61>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt deleted file mode 100644 index cfe1db3bb6e..00000000000 --- a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | LPC32XX PWM controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "nxp,lpc3220-pwm" | ||
5 | - reg: physical base address and length of the controller's registers | ||
6 | |||
7 | Examples: | ||
8 | |||
9 | pwm@0x4005C000 { | ||
10 | compatible = "nxp,lpc3220-pwm"; | ||
11 | reg = <0x4005C000 0x8>; | ||
12 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt deleted file mode 100644 index 9e3f8f1d46a..00000000000 --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | Freescale MXS PWM controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "fsl,imx23-pwm" | ||
5 | - reg: physical base address and length of the controller's registers | ||
6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index | ||
7 | of the PWM to use and the second cell is the period in nanoseconds. | ||
8 | - fsl,pwm-number: the number of PWM devices | ||
9 | |||
10 | Example: | ||
11 | |||
12 | pwm: pwm@80064000 { | ||
13 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; | ||
14 | reg = <0x80064000 0x2000>; | ||
15 | #pwm-cells = <2>; | ||
16 | fsl,pwm-number = <8>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt deleted file mode 100644 index 01438ecd662..00000000000 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | Tegra SoC PWFM controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be one of: | ||
5 | - "nvidia,tegra20-pwm" | ||
6 | - "nvidia,tegra30-pwm" | ||
7 | - reg: physical base address and length of the controller's registers | ||
8 | - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The | ||
9 | first cell specifies the per-chip index of the PWM to use and the second | ||
10 | cell is the period in nanoseconds. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | pwm: pwm@7000a000 { | ||
15 | compatible = "nvidia,tegra20-pwm"; | ||
16 | reg = <0x7000a000 0x100>; | ||
17 | #pwm-cells = <2>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt deleted file mode 100644 index 131e8c11d26..00000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | TI SOC ECAP based APWM controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "ti,am33xx-ecap" | ||
5 | - #pwm-cells: Should be 3. Number of cells being used to specify PWM property. | ||
6 | First cell specifies the per-chip index of the PWM to use, the second | ||
7 | cell is the period in nanoseconds and bit 0 in the third cell is used to | ||
8 | encode the polarity of PWM output. Set bit 0 of the third in PWM specifier | ||
9 | to 1 for inverse polarity & set to 0 for normal polarity. | ||
10 | - reg: physical base address and size of the registers map. | ||
11 | |||
12 | Optional properties: | ||
13 | - ti,hwmods: Name of the hwmod associated to the ECAP: | ||
14 | "ecap<x>", <x> being the 0-based instance number from the HW spec | ||
15 | |||
16 | Example: | ||
17 | |||
18 | ecap0: ecap@0 { | ||
19 | compatible = "ti,am33xx-ecap"; | ||
20 | #pwm-cells = <3>; | ||
21 | reg = <0x48300100 0x80>; | ||
22 | ti,hwmods = "ecap0"; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt deleted file mode 100644 index 4fc7079d822..00000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | TI SOC EHRPWM based PWM controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Must be "ti,am33xx-ehrpwm" | ||
5 | - #pwm-cells: Should be 3. Number of cells being used to specify PWM property. | ||
6 | First cell specifies the per-chip index of the PWM to use, the second | ||
7 | cell is the period in nanoseconds and bit 0 in the third cell is used to | ||
8 | encode the polarity of PWM output. Set bit 0 of the third in PWM specifier | ||
9 | to 1 for inverse polarity & set to 0 for normal polarity. | ||
10 | - reg: physical base address and size of the registers map. | ||
11 | |||
12 | Optional properties: | ||
13 | - ti,hwmods: Name of the hwmod associated to the EHRPWM: | ||
14 | "ehrpwm<x>", <x> being the 0-based instance number from the HW spec | ||
15 | |||
16 | Example: | ||
17 | |||
18 | ehrpwm0: ehrpwm@0 { | ||
19 | compatible = "ti,am33xx-ehrpwm"; | ||
20 | #pwm-cells = <3>; | ||
21 | reg = <0x48300200 0x100>; | ||
22 | ti,hwmods = "ehrpwm0"; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt deleted file mode 100644 index f7eae77f835..00000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | TI SOC based PWM Subsystem | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "ti,am33xx-pwmss"; | ||
5 | - reg: physical base address and size of the registers map. | ||
6 | - address-cells: Specify the number of u32 entries needed in child nodes. | ||
7 | Should set to 1. | ||
8 | - size-cells: specify number of u32 entries needed to specify child nodes size | ||
9 | in reg property. Should set to 1. | ||
10 | - ranges: describes the address mapping of a memory-mapped bus. Should set to | ||
11 | physical address map of child's base address, physical address within | ||
12 | parent's address space and length of the address map. For am33xx, | ||
13 | 3 set of child register maps present, ECAP register space, EQEP | ||
14 | register space, EHRPWM register space. | ||
15 | |||
16 | Also child nodes should also populated under PWMSS DT node. | ||
17 | |||
18 | Example: | ||
19 | pwmss0: pwmss@48300000 { | ||
20 | compatible = "ti,am33xx-pwmss"; | ||
21 | reg = <0x48300000 0x10>; | ||
22 | ti,hwmods = "epwmss0"; | ||
23 | #address-cells = <1>; | ||
24 | #size-cells = <1>; | ||
25 | status = "disabled"; | ||
26 | ranges = <0x48300100 0x48300100 0x80 /* ECAP */ | ||
27 | 0x48300180 0x48300180 0x80 /* EQEP */ | ||
28 | 0x48300200 0x48300200 0x80>; /* EHRPWM */ | ||
29 | |||
30 | /* child nodes go here */ | ||
31 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/pwm.txt b/Documentation/devicetree/bindings/pwm/pwm.txt deleted file mode 100644 index 06e67247859..00000000000 --- a/Documentation/devicetree/bindings/pwm/pwm.txt +++ /dev/null | |||
@@ -1,68 +0,0 @@ | |||
1 | Specifying PWM information for devices | ||
2 | ====================================== | ||
3 | |||
4 | 1) PWM user nodes | ||
5 | ----------------- | ||
6 | |||
7 | PWM users should specify a list of PWM devices that they want to use | ||
8 | with a property containing a 'pwm-list': | ||
9 | |||
10 | pwm-list ::= <single-pwm> [pwm-list] | ||
11 | single-pwm ::= <pwm-phandle> <pwm-specifier> | ||
12 | pwm-phandle : phandle to PWM controller node | ||
13 | pwm-specifier : array of #pwm-cells specifying the given PWM | ||
14 | (controller specific) | ||
15 | |||
16 | PWM properties should be named "pwms". The exact meaning of each pwms | ||
17 | property must be documented in the device tree binding for each device. | ||
18 | An optional property "pwm-names" may contain a list of strings to label | ||
19 | each of the PWM devices listed in the "pwms" property. If no "pwm-names" | ||
20 | property is given, the name of the user node will be used as fallback. | ||
21 | |||
22 | Drivers for devices that use more than a single PWM device can use the | ||
23 | "pwm-names" property to map the name of the PWM device requested by the | ||
24 | pwm_get() call to an index into the list given by the "pwms" property. | ||
25 | |||
26 | The following example could be used to describe a PWM-based backlight | ||
27 | device: | ||
28 | |||
29 | pwm: pwm { | ||
30 | #pwm-cells = <2>; | ||
31 | }; | ||
32 | |||
33 | [...] | ||
34 | |||
35 | bl: backlight { | ||
36 | pwms = <&pwm 0 5000000>; | ||
37 | pwm-names = "backlight"; | ||
38 | }; | ||
39 | |||
40 | Note that in the example above, specifying the "pwm-names" is redundant | ||
41 | because the name "backlight" would be used as fallback anyway. | ||
42 | |||
43 | pwm-specifier typically encodes the chip-relative PWM number and the PWM | ||
44 | period in nanoseconds. | ||
45 | |||
46 | Optionally, the pwm-specifier can encode a number of flags in a third cell: | ||
47 | - bit 0: PWM signal polarity (0: normal polarity, 1: inverse polarity) | ||
48 | |||
49 | Example with optional PWM specifier for inverse polarity | ||
50 | |||
51 | bl: backlight { | ||
52 | pwms = <&pwm 0 5000000 1>; | ||
53 | pwm-names = "backlight"; | ||
54 | }; | ||
55 | |||
56 | 2) PWM controller nodes | ||
57 | ----------------------- | ||
58 | |||
59 | PWM controller nodes must specify the number of cells used for the | ||
60 | specifier using the '#pwm-cells' property. | ||
61 | |||
62 | An example PWM controller might look like this: | ||
63 | |||
64 | pwm: pwm@7000a000 { | ||
65 | compatible = "nvidia,tegra20-pwm"; | ||
66 | reg = <0x7000a000 0x100>; | ||
67 | #pwm-cells = <2>; | ||
68 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/spear-pwm.txt b/Documentation/devicetree/bindings/pwm/spear-pwm.txt deleted file mode 100644 index 3ac779d8338..00000000000 --- a/Documentation/devicetree/bindings/pwm/spear-pwm.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | == ST SPEAr SoC PWM controller == | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be one of: | ||
5 | - "st,spear320-pwm" | ||
6 | - "st,spear1340-pwm" | ||
7 | - reg: physical base address and length of the controller's registers | ||
8 | - #pwm-cells: number of cells used to specify PWM which is fixed to 2 on | ||
9 | SPEAr. The first cell specifies the per-chip index of the PWM to use and | ||
10 | the second cell is the period in nanoseconds. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | pwm: pwm@a8000000 { | ||
15 | compatible ="st,spear320-pwm"; | ||
16 | reg = <0xa8000000 0x1000>; | ||
17 | #pwm-cells = <2>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt deleted file mode 100644 index 2943ee5fce0..00000000000 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | Texas Instruments TWL series PWM drivers | ||
2 | |||
3 | Supported PWMs: | ||
4 | On TWL4030 series: PWM1 and PWM2 | ||
5 | On TWL6030 series: PWM0 and PWM1 | ||
6 | |||
7 | Required properties: | ||
8 | - compatible: "ti,twl4030-pwm" or "ti,twl6030-pwm" | ||
9 | - #pwm-cells: should be 2. The first cell specifies the per-chip index | ||
10 | of the PWM to use and the second cell is the period in nanoseconds. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | twl_pwm: pwm { | ||
15 | compatible = "ti,twl6030-pwm"; | ||
16 | #pwm-cells = <2>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt deleted file mode 100644 index cb64f3acc10..00000000000 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | Texas Instruments TWL series PWM drivers connected to LED terminals | ||
2 | |||
3 | Supported PWMs: | ||
4 | On TWL4030 series: PWMA and PWMB (connected to LEDA and LEDB terminals) | ||
5 | On TWL6030 series: LED PWM (mainly used as charging indicator LED) | ||
6 | |||
7 | Required properties: | ||
8 | - compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled" | ||
9 | - #pwm-cells: should be 2. The first cell specifies the per-chip index | ||
10 | of the PWM to use and the second cell is the period in nanoseconds. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | twl_pwmled: pwmled { | ||
15 | compatible = "ti,twl6030-pwmled"; | ||
16 | #pwm-cells = <2>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt deleted file mode 100644 index bcc63678a9a..00000000000 --- a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "via,vt8500-pwm" | ||
5 | - reg: physical base address and length of the controller's registers | ||
6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index | ||
7 | of the PWM to use and the second cell is the period in nanoseconds. | ||
8 | - clocks: phandle to the PWM source clock | ||
9 | |||
10 | Example: | ||
11 | |||
12 | pwm1: pwm@d8220000 { | ||
13 | #pwm-cells = <2>; | ||
14 | compatible = "via,vt8500-pwm"; | ||
15 | reg = <0xd8220000 0x1000>; | ||
16 | clocks = <&clkpwm>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/88pm860x.txt b/Documentation/devicetree/bindings/regulator/88pm860x.txt deleted file mode 100644 index 1267b3e1a2c..00000000000 --- a/Documentation/devicetree/bindings/regulator/88pm860x.txt +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | Marvell 88PM860x regulator | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "marvell,88pm860x" | ||
5 | - reg: I2C slave address | ||
6 | - regulators: A node that houses a sub-node for each regulator within the | ||
7 | device. Each sub-node is identified using the regulator-compatible | ||
8 | property, with valid values listed below. | ||
9 | |||
10 | Example: | ||
11 | |||
12 | pmic: 88pm860x@34 { | ||
13 | compatible = "marvell,88pm860x"; | ||
14 | reg = <0x34>; | ||
15 | |||
16 | regulators { | ||
17 | BUCK1 { | ||
18 | regulator-min-microvolt = <1000000>; | ||
19 | regulator-max-microvolt = <1500000>; | ||
20 | regulator-boot-on; | ||
21 | regulator-always-on; | ||
22 | }; | ||
23 | BUCK3 { | ||
24 | regulator-min-microvolt = <1000000>; | ||
25 | regulator-max-microvolt = <3000000>; | ||
26 | regulator-boot-on; | ||
27 | regulator-always-on; | ||
28 | }; | ||
29 | }; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt deleted file mode 100644 index 357758cb6e9..00000000000 --- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | Anatop Voltage regulators | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "fsl,anatop-regulator" | ||
5 | - anatop-reg-offset: Anatop MFD register offset | ||
6 | - anatop-vol-bit-shift: Bit shift for the register | ||
7 | - anatop-vol-bit-width: Number of bits used in the register | ||
8 | - anatop-min-bit-val: Minimum value of this register | ||
9 | - anatop-min-voltage: Minimum voltage of this regulator | ||
10 | - anatop-max-voltage: Maximum voltage of this regulator | ||
11 | |||
12 | Any property defined as part of the core regulator | ||
13 | binding, defined in regulator.txt, can also be used. | ||
14 | |||
15 | Example: | ||
16 | |||
17 | regulator-vddpu { | ||
18 | compatible = "fsl,anatop-regulator"; | ||
19 | regulator-name = "vddpu"; | ||
20 | regulator-min-microvolt = <725000>; | ||
21 | regulator-max-microvolt = <1300000>; | ||
22 | regulator-always-on; | ||
23 | anatop-reg-offset = <0x140>; | ||
24 | anatop-vol-bit-shift = <9>; | ||
25 | anatop-vol-bit-width = <5>; | ||
26 | anatop-min-bit-val = <1>; | ||
27 | anatop-min-voltage = <725000>; | ||
28 | anatop-max-voltage = <1300000>; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt deleted file mode 100644 index 4fae41d5479..00000000000 --- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | Fixed Voltage regulators | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "regulator-fixed"; | ||
5 | |||
6 | Optional properties: | ||
7 | - gpio: gpio to use for enable control | ||
8 | - startup-delay-us: startup time in microseconds | ||
9 | - enable-active-high: Polarity of GPIO is Active high | ||
10 | If this property is missing, the default assumed is Active low. | ||
11 | - gpio-open-drain: GPIO is open drain type. | ||
12 | If this property is missing then default assumption is false. | ||
13 | -vin-supply: Input supply name. | ||
14 | |||
15 | Any property defined as part of the core regulator | ||
16 | binding, defined in regulator.txt, can also be used. | ||
17 | However a fixed voltage regulator is expected to have the | ||
18 | regulator-min-microvolt and regulator-max-microvolt | ||
19 | to be the same. | ||
20 | |||
21 | Example: | ||
22 | |||
23 | abc: fixedregulator@0 { | ||
24 | compatible = "regulator-fixed"; | ||
25 | regulator-name = "fixed-supply"; | ||
26 | regulator-min-microvolt = <1800000>; | ||
27 | regulator-max-microvolt = <1800000>; | ||
28 | gpio = <&gpio1 16 0>; | ||
29 | startup-delay-us = <70000>; | ||
30 | enable-active-high; | ||
31 | regulator-boot-on; | ||
32 | gpio-open-drain; | ||
33 | vin-supply = <&parent_reg>; | ||
34 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt deleted file mode 100644 index 63c659800c0..00000000000 --- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | GPIO controlled regulators | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Must be "regulator-gpio". | ||
5 | - states : Selection of available voltages and GPIO configs. | ||
6 | if there are no states, then use a fixed regulator | ||
7 | |||
8 | Optional properties: | ||
9 | - enable-gpio : GPIO to use to enable/disable the regulator. | ||
10 | - gpios : GPIO group used to control voltage. | ||
11 | - startup-delay-us : Startup time in microseconds. | ||
12 | - enable-active-high : Polarity of GPIO is active high (default is low). | ||
13 | |||
14 | Any property defined as part of the core regulator binding defined in | ||
15 | regulator.txt can also be used. | ||
16 | |||
17 | Example: | ||
18 | |||
19 | mmciv: gpio-regulator { | ||
20 | compatible = "regulator-gpio"; | ||
21 | |||
22 | regulator-name = "mmci-gpio-supply"; | ||
23 | regulator-min-microvolt = <1800000>; | ||
24 | regulator-max-microvolt = <2600000>; | ||
25 | regulator-boot-on; | ||
26 | |||
27 | enable-gpio = <&gpio0 23 0x4>; | ||
28 | gpios = <&gpio0 24 0x4 | ||
29 | &gpio0 25 0x4>; | ||
30 | states = <1800000 0x3 | ||
31 | 2200000 0x2 | ||
32 | 2600000 0x1 | ||
33 | 2900000 0x0>; | ||
34 | |||
35 | startup-delay-us = <100000>; | ||
36 | enable-active-high; | ||
37 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/max8907.txt b/Documentation/devicetree/bindings/regulator/max8907.txt deleted file mode 100644 index 371eccd1cd6..00000000000 --- a/Documentation/devicetree/bindings/regulator/max8907.txt +++ /dev/null | |||
@@ -1,69 +0,0 @@ | |||
1 | MAX8907 regulator | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "maxim,max8907" | ||
5 | - reg: I2C slave address | ||
6 | - interrupts: The interrupt output of the controller | ||
7 | - mbatt-supply: The input supply for MBATT, BBAT, SDBY, VRTC. | ||
8 | - in-v1-supply: The input supply for SD1. | ||
9 | - in-v2-supply: The input supply for SD2. | ||
10 | - in-v3-supply: The input supply for SD3. | ||
11 | - in1-supply: The input supply for LDO1. | ||
12 | ... | ||
13 | - in20-supply: The input supply for LDO20. | ||
14 | - regulators: A node that houses a sub-node for each regulator within the | ||
15 | device. Each sub-node is identified using the node's name (or the deprecated | ||
16 | regulator-compatible property if present), with valid values listed below. | ||
17 | The content of each sub-node is defined by the standard binding for | ||
18 | regulators; see regulator.txt. | ||
19 | |||
20 | Optional properties: | ||
21 | - maxim,system-power-controller: Boolean property indicating that the PMIC | ||
22 | controls the overall system power. | ||
23 | |||
24 | The valid names for regulators are: | ||
25 | |||
26 | sd1, sd2, sd3, ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8, ldo9, ldo10, | ||
27 | ldo11, ldo12, ldo13, ldo14, ldo15, ldo16, ldo17, ldo18, ldo19, ldo20, out5v, | ||
28 | out33v, bbat, sdby, vrtc. | ||
29 | |||
30 | Example: | ||
31 | |||
32 | max8907@3c { | ||
33 | compatible = "maxim,max8907"; | ||
34 | reg = <0x3c>; | ||
35 | interrupts = <0 86 0x4>; | ||
36 | |||
37 | maxim,system-power-controller; | ||
38 | |||
39 | mbatt-supply = <&some_reg>; | ||
40 | in-v1-supply = <&mbatt_reg>; | ||
41 | ... | ||
42 | in1-supply = <&mbatt_reg>; | ||
43 | ... | ||
44 | |||
45 | regulators { | ||
46 | mbatt_reg: mbatt { | ||
47 | regulator-name = "vbat_pmu"; | ||
48 | regulator-min-microvolt = <5000000>; | ||
49 | regulator-max-microvolt = <5000000>; | ||
50 | regulator-always-on; | ||
51 | }; | ||
52 | |||
53 | sd1 { | ||
54 | regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; | ||
55 | regulator-min-microvolt = <1000000>; | ||
56 | regulator-max-microvolt = <1000000>; | ||
57 | regulator-always-on; | ||
58 | }; | ||
59 | |||
60 | sd2 { | ||
61 | regulator-name = "nvvdd_sv2,vdd_core"; | ||
62 | regulator-min-microvolt = <1200000>; | ||
63 | regulator-max-microvolt = <1200000>; | ||
64 | regulator-always-on; | ||
65 | }; | ||
66 | ... | ||
67 | }; | ||
68 | }; | ||
69 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/max8925-regulator.txt b/Documentation/devicetree/bindings/regulator/max8925-regulator.txt deleted file mode 100644 index 0057695aae8..00000000000 --- a/Documentation/devicetree/bindings/regulator/max8925-regulator.txt +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | Max8925 Voltage regulators | ||
2 | |||
3 | Required nodes: | ||
4 | -nodes: | ||
5 | - SDV1 for SDV SDV1 | ||
6 | - SDV2 for SDV SDV2 | ||
7 | - SDV3 for SDV SDV3 | ||
8 | - LDO1 for LDO LDO1 | ||
9 | - LDO2 for LDO LDO2 | ||
10 | - LDO3 for LDO LDO3 | ||
11 | - LDO4 for LDO LDO4 | ||
12 | - LDO5 for LDO LDO5 | ||
13 | - LDO6 for LDO LDO6 | ||
14 | - LDO7 for LDO LDO7 | ||
15 | - LDO8 for LDO LDO8 | ||
16 | - LDO9 for LDO LDO9 | ||
17 | - LDO10 for LDO LDO10 | ||
18 | - LDO11 for LDO LDO11 | ||
19 | - LDO12 for LDO LDO12 | ||
20 | - LDO13 for LDO LDO13 | ||
21 | - LDO14 for LDO LDO14 | ||
22 | - LDO15 for LDO LDO15 | ||
23 | - LDO16 for LDO LDO16 | ||
24 | - LDO17 for LDO LDO17 | ||
25 | - LDO18 for LDO LDO18 | ||
26 | - LDO19 for LDO LDO19 | ||
27 | - LDO20 for LDO LDO20 | ||
28 | |||
29 | Optional properties: | ||
30 | - Any optional property defined in bindings/regulator/regulator.txt | ||
31 | |||
32 | Example: | ||
33 | |||
34 | SDV1 { | ||
35 | regulator-min-microvolt = <637500>; | ||
36 | regulator-max-microvolt = <1425000>; | ||
37 | regulator-boot-on; | ||
38 | regulator-always-on; | ||
39 | }; | ||
40 | |||
diff --git a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt deleted file mode 100644 index 9fd69a18b0b..00000000000 --- a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt +++ /dev/null | |||
@@ -1,146 +0,0 @@ | |||
1 | * Maxim MAX8997 Voltage and Current Regulator | ||
2 | |||
3 | The Maxim MAX8997 is a multi-function device which includes volatage and | ||
4 | current regulators, rtc, charger controller and other sub-blocks. It is | ||
5 | interfaced to the host controller using a i2c interface. Each sub-block is | ||
6 | addressed by the host system using different i2c slave address. This document | ||
7 | describes the bindings for 'pmic' sub-block of max8997. | ||
8 | |||
9 | Required properties: | ||
10 | - compatible: Should be "maxim,max8997-pmic". | ||
11 | - reg: Specifies the i2c slave address of the pmic block. It should be 0x66. | ||
12 | |||
13 | - max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV) | ||
14 | units for buck1 when changing voltage using gpio dvs. Refer to [1] below | ||
15 | for additional information. | ||
16 | |||
17 | - max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV) | ||
18 | units for buck2 when changing voltage using gpio dvs. Refer to [1] below | ||
19 | for additional information. | ||
20 | |||
21 | - max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV) | ||
22 | units for buck5 when changing voltage using gpio dvs. Refer to [1] below | ||
23 | for additional information. | ||
24 | |||
25 | [1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional | ||
26 | property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage' | ||
27 | property should specify atleast one voltage level (which would be a | ||
28 | safe operating voltage). | ||
29 | |||
30 | If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional | ||
31 | property is specified, then all the eigth voltage values for the | ||
32 | 'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified. | ||
33 | |||
34 | Optional properties: | ||
35 | - interrupt-parent: Specifies the phandle of the interrupt controller to which | ||
36 | the interrupts from max8997 are delivered to. | ||
37 | - interrupts: Interrupt specifiers for two interrupt sources. | ||
38 | - First interrupt specifier is for 'irq1' interrupt. | ||
39 | - Second interrupt specifier is for 'alert' interrupt. | ||
40 | - max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs. | ||
41 | - max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs. | ||
42 | - max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs. | ||
43 | |||
44 | Additional properties required if either of the optional properties are used: | ||
45 | - max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for | ||
46 | multiple bucks, changing the voltage value of one of the bucks may affect | ||
47 | that of another buck, which is the side effect of the change (set_voltage). | ||
48 | Use this property to ignore such side effects and change the voltage. | ||
49 | |||
50 | - max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from | ||
51 | the possible 8 options selectable by the dvs gpios. The value of this | ||
52 | property should be between 0 and 7. If not specified or if out of range, the | ||
53 | default value of this property is set to 0. | ||
54 | |||
55 | - max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used | ||
56 | for dvs. The format of the gpio specifier depends in the gpio controller. | ||
57 | |||
58 | Regulators: The regulators of max8997 that have to be instantiated should be | ||
59 | included in a sub-node named 'regulators'. Regulator nodes included in this | ||
60 | sub-node should be of the format as listed below. | ||
61 | |||
62 | regulator_name { | ||
63 | standard regulator bindings here | ||
64 | }; | ||
65 | |||
66 | The following are the names of the regulators that the max8997 pmic block | ||
67 | supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number | ||
68 | as per the datasheet of max8997. | ||
69 | |||
70 | - LDOn | ||
71 | - valid values for n are 1 to 18 and 21 | ||
72 | - Example: LDO0, LD01, LDO2, LDO21 | ||
73 | - BUCKn | ||
74 | - valid values for n are 1 to 7. | ||
75 | - Example: BUCK1, BUCK2, BUCK3, BUCK7 | ||
76 | |||
77 | - ENVICHG: Battery Charging Current Monitor Output. This is a fixed | ||
78 | voltage type regulator | ||
79 | |||
80 | - ESAFEOUT1: (ldo19) | ||
81 | - ESAFEOUT2: (ld020) | ||
82 | |||
83 | - CHARGER_CV: main battery charger voltage control | ||
84 | - CHARGER: main battery charger current control | ||
85 | - CHARGER_TOPOFF: end of charge current threshold level | ||
86 | |||
87 | The bindings inside the regulator nodes use the standard regulator bindings | ||
88 | which are documented elsewhere. | ||
89 | |||
90 | Example: | ||
91 | |||
92 | max8997_pmic@66 { | ||
93 | compatible = "maxim,max8997-pmic"; | ||
94 | interrupt-parent = <&wakeup_eint>; | ||
95 | reg = <0x66>; | ||
96 | interrupts = <4 0>, <3 0>; | ||
97 | |||
98 | max8997,pmic-buck1-uses-gpio-dvs; | ||
99 | max8997,pmic-buck2-uses-gpio-dvs; | ||
100 | max8997,pmic-buck5-uses-gpio-dvs; | ||
101 | |||
102 | max8997,pmic-ignore-gpiodvs-side-effect; | ||
103 | max8997,pmic-buck125-default-dvs-idx = <0>; | ||
104 | |||
105 | max8997,pmic-buck125-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */ | ||
106 | <&gpx0 1 1 0 0>, /* SET2 */ | ||
107 | <&gpx0 2 1 0 0>; /* SET3 */ | ||
108 | |||
109 | max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, | ||
110 | <1250000>, <1200000>, | ||
111 | <1150000>, <1100000>, | ||
112 | <1000000>, <950000>; | ||
113 | |||
114 | max8997,pmic-buck2-dvs-voltage = <1100000>, <1100000>, | ||
115 | <1100000>, <1100000>, | ||
116 | <1000000>, <1000000>, | ||
117 | <1000000>, <1000000>; | ||
118 | |||
119 | max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, | ||
120 | <1200000>, <1200000>, | ||
121 | <1200000>, <1200000>, | ||
122 | <1200000>, <1200000>; | ||
123 | |||
124 | regulators { | ||
125 | ldo1_reg: LDO1 { | ||
126 | regulator-name = "VDD_ABB_3.3V"; | ||
127 | regulator-min-microvolt = <3300000>; | ||
128 | regulator-max-microvolt = <3300000>; | ||
129 | }; | ||
130 | |||
131 | ldo2_reg: LDO2 { | ||
132 | regulator-name = "VDD_ALIVE_1.1V"; | ||
133 | regulator-min-microvolt = <1100000>; | ||
134 | regulator-max-microvolt = <1100000>; | ||
135 | regulator-always-on; | ||
136 | }; | ||
137 | |||
138 | buck1_reg: BUCK1 { | ||
139 | regulator-name = "VDD_ARM_1.2V"; | ||
140 | regulator-min-microvolt = <950000>; | ||
141 | regulator-max-microvolt = <1350000>; | ||
142 | regulator-always-on; | ||
143 | regulator-boot-on; | ||
144 | }; | ||
145 | }; | ||
146 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt deleted file mode 100644 index ecfc6ccd67e..00000000000 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ /dev/null | |||
@@ -1,62 +0,0 @@ | |||
1 | Voltage/Current Regulators | ||
2 | |||
3 | Optional properties: | ||
4 | - regulator-name: A string used as a descriptive name for regulator outputs | ||
5 | - regulator-min-microvolt: smallest voltage consumers may set | ||
6 | - regulator-max-microvolt: largest voltage consumers may set | ||
7 | - regulator-microvolt-offset: Offset applied to voltages to compensate for voltage drops | ||
8 | - regulator-min-microamp: smallest current consumers may set | ||
9 | - regulator-max-microamp: largest current consumers may set | ||
10 | - regulator-always-on: boolean, regulator should never be disabled | ||
11 | - regulator-boot-on: bootloader/firmware enabled regulator | ||
12 | - <name>-supply: phandle to the parent supply/regulator node | ||
13 | - regulator-ramp-delay: ramp delay for regulator(in uV/uS) | ||
14 | |||
15 | Deprecated properties: | ||
16 | - regulator-compatible: If a regulator chip contains multiple | ||
17 | regulators, and if the chip's binding contains a child node that | ||
18 | describes each regulator, then this property indicates which regulator | ||
19 | this child node is intended to configure. If this property is missing, | ||
20 | the node's name will be used instead. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | xyzreg: regulator@0 { | ||
25 | regulator-min-microvolt = <1000000>; | ||
26 | regulator-max-microvolt = <2500000>; | ||
27 | regulator-always-on; | ||
28 | vin-supply = <&vin>; | ||
29 | }; | ||
30 | |||
31 | Regulator Consumers: | ||
32 | Consumer nodes can reference one or more of its supplies/ | ||
33 | regulators using the below bindings. | ||
34 | |||
35 | - <name>-supply: phandle to the regulator node | ||
36 | |||
37 | These are the same bindings that a regulator in the above | ||
38 | example used to reference its own supply, in which case | ||
39 | its just seen as a special case of a regulator being a | ||
40 | consumer itself. | ||
41 | |||
42 | Example of a consumer device node (mmc) referencing two | ||
43 | regulators (twl_reg1 and twl_reg2), | ||
44 | |||
45 | twl_reg1: regulator@0 { | ||
46 | ... | ||
47 | ... | ||
48 | ... | ||
49 | }; | ||
50 | |||
51 | twl_reg2: regulator@1 { | ||
52 | ... | ||
53 | ... | ||
54 | ... | ||
55 | }; | ||
56 | |||
57 | mmc: mmc@0x0 { | ||
58 | ... | ||
59 | ... | ||
60 | vmmc-supply = <&twl_reg1>; | ||
61 | vmmcaux-supply = <&twl_reg2>; | ||
62 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt b/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt deleted file mode 100644 index c8ca6b8f658..00000000000 --- a/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt +++ /dev/null | |||
@@ -1,44 +0,0 @@ | |||
1 | TPS62360 Voltage regulators | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be one of the following. | ||
5 | "ti,tps62360" | ||
6 | "ti,tps62361", | ||
7 | "ti,tps62362", | ||
8 | "ti,tps62363", | ||
9 | - reg: I2C slave address | ||
10 | |||
11 | Optional properties: | ||
12 | - ti,enable-vout-discharge: Enable output discharge. This is boolean value. | ||
13 | - ti,enable-pull-down: Enable pull down. This is boolean value. | ||
14 | - ti,vsel0-gpio: GPIO for controlling VSEL0 line. | ||
15 | If this property is missing, then assume that there is no GPIO | ||
16 | for vsel0 control. | ||
17 | - ti,vsel1-gpio: Gpio for controlling VSEL1 line. | ||
18 | If this property is missing, then assume that there is no GPIO | ||
19 | for vsel1 control. | ||
20 | - ti,vsel0-state-high: Inital state of vsel0 input is high. | ||
21 | If this property is missing, then assume the state as low (0). | ||
22 | - ti,vsel1-state-high: Inital state of vsel1 input is high. | ||
23 | If this property is missing, then assume the state as low (0). | ||
24 | |||
25 | Any property defined as part of the core regulator binding, defined in | ||
26 | regulator.txt, can also be used. | ||
27 | |||
28 | Example: | ||
29 | |||
30 | abc: tps62360 { | ||
31 | compatible = "ti,tps62361"; | ||
32 | reg = <0x60>; | ||
33 | regulator-name = "tps62361-vout"; | ||
34 | regulator-min-microvolt = <500000>; | ||
35 | regulator-max-microvolt = <1500000>; | ||
36 | regulator-boot-on | ||
37 | ti,vsel0-gpio = <&gpio1 16 0>; | ||
38 | ti,vsel1-gpio = <&gpio1 17 0>; | ||
39 | ti,vsel0-state-high; | ||
40 | ti,vsel1-state-high; | ||
41 | ti,enable-pull-down; | ||
42 | ti,enable-force-pwm; | ||
43 | ti,enable-vout-discharge; | ||
44 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/tps65217.txt b/Documentation/devicetree/bindings/regulator/tps65217.txt deleted file mode 100644 index 4f05d208c95..00000000000 --- a/Documentation/devicetree/bindings/regulator/tps65217.txt +++ /dev/null | |||
@@ -1,78 +0,0 @@ | |||
1 | TPS65217 family of regulators | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,tps65217" | ||
5 | - reg: I2C slave address | ||
6 | - regulators: list of regulators provided by this controller, must be named | ||
7 | after their hardware counterparts: dcdc[1-3] and ldo[1-4] | ||
8 | - regulators: This is the list of child nodes that specify the regulator | ||
9 | initialization data for defined regulators. Not all regulators for the given | ||
10 | device need to be present. The definition for each of these nodes is defined | ||
11 | using the standard binding for regulators found at | ||
12 | Documentation/devicetree/bindings/regulator/regulator.txt. | ||
13 | |||
14 | Optional properties: | ||
15 | - ti,pmic-shutdown-controller: Telling the PMIC to shutdown on PWR_EN toggle. | ||
16 | |||
17 | The valid names for regulators are: | ||
18 | tps65217: dcdc1, dcdc2, dcdc3, ldo1, ldo2, ldo3 and ldo4 | ||
19 | |||
20 | Each regulator is defined using the standard binding for regulators. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | tps: tps@24 { | ||
25 | compatible = "ti,tps65217"; | ||
26 | ti,pmic-shutdown-controller; | ||
27 | |||
28 | regulators { | ||
29 | dcdc1_reg: dcdc1 { | ||
30 | regulator-min-microvolt = <900000>; | ||
31 | regulator-max-microvolt = <1800000>; | ||
32 | regulator-boot-on; | ||
33 | regulator-always-on; | ||
34 | }; | ||
35 | |||
36 | dcdc2_reg: dcdc2 { | ||
37 | regulator-min-microvolt = <900000>; | ||
38 | regulator-max-microvolt = <3300000>; | ||
39 | regulator-boot-on; | ||
40 | regulator-always-on; | ||
41 | }; | ||
42 | |||
43 | dcdc3_reg: dcc3 { | ||
44 | regulator-min-microvolt = <900000>; | ||
45 | regulator-max-microvolt = <1500000>; | ||
46 | regulator-boot-on; | ||
47 | regulator-always-on; | ||
48 | }; | ||
49 | |||
50 | ldo1_reg: ldo1 { | ||
51 | regulator-min-microvolt = <1000000>; | ||
52 | regulator-max-microvolt = <3300000>; | ||
53 | regulator-boot-on; | ||
54 | regulator-always-on; | ||
55 | }; | ||
56 | |||
57 | ldo2_reg: ldo2 { | ||
58 | regulator-min-microvolt = <900000>; | ||
59 | regulator-max-microvolt = <3300000>; | ||
60 | regulator-boot-on; | ||
61 | regulator-always-on; | ||
62 | }; | ||
63 | |||
64 | ldo3_reg: ldo3 { | ||
65 | regulator-min-microvolt = <1800000>; | ||
66 | regulator-max-microvolt = <3300000>; | ||
67 | regulator-boot-on; | ||
68 | regulator-always-on; | ||
69 | }; | ||
70 | |||
71 | ldo4_reg: ldo4 { | ||
72 | regulator-min-microvolt = <1800000>; | ||
73 | regulator-max-microvolt = <3300000>; | ||
74 | regulator-boot-on; | ||
75 | regulator-always-on; | ||
76 | }; | ||
77 | }; | ||
78 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/tps6586x.txt b/Documentation/devicetree/bindings/regulator/tps6586x.txt deleted file mode 100644 index 8b40cac24d9..00000000000 --- a/Documentation/devicetree/bindings/regulator/tps6586x.txt +++ /dev/null | |||
@@ -1,135 +0,0 @@ | |||
1 | TPS6586x family of regulators | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,tps6586x" | ||
5 | - reg: I2C slave address | ||
6 | - interrupts: the interrupt outputs of the controller | ||
7 | - #gpio-cells: number of cells to describe a GPIO | ||
8 | - gpio-controller: mark the device as a GPIO controller | ||
9 | - regulators: A node that houses a sub-node for each regulator within the | ||
10 | device. Each sub-node is identified using the node's name (or the deprecated | ||
11 | regulator-compatible property if present), with valid values listed below. | ||
12 | The content of each sub-node is defined by the standard binding for | ||
13 | regulators; see regulator.txt. | ||
14 | sys, sm[0-2], ldo[0-9] and ldo_rtc | ||
15 | - sys-supply: The input supply for SYS. | ||
16 | - vin-sm0-supply: The input supply for the SM0. | ||
17 | - vin-sm1-supply: The input supply for the SM1. | ||
18 | - vin-sm2-supply: The input supply for the SM2. | ||
19 | - vinldo01-supply: The input supply for the LDO1 and LDO2 | ||
20 | - vinldo23-supply: The input supply for the LDO2 and LDO3 | ||
21 | - vinldo4-supply: The input supply for the LDO4 | ||
22 | - vinldo678-supply: The input supply for the LDO6, LDO7 and LDO8 | ||
23 | - vinldo9-supply: The input supply for the LDO9 | ||
24 | |||
25 | Optional properties: | ||
26 | - ti,system-power-controller: Telling whether or not this pmic is controlling | ||
27 | the system power. | ||
28 | |||
29 | Each regulator is defined using the standard binding for regulators. | ||
30 | |||
31 | Note: LDO5 and LDO_RTC is supplied by SYS regulator internally and driver | ||
32 | take care of making proper parent child relationship. | ||
33 | |||
34 | Example: | ||
35 | |||
36 | pmu: tps6586x@34 { | ||
37 | compatible = "ti,tps6586x"; | ||
38 | reg = <0x34>; | ||
39 | interrupts = <0 88 0x4>; | ||
40 | |||
41 | #gpio-cells = <2>; | ||
42 | gpio-controller; | ||
43 | |||
44 | ti,system-power-controller; | ||
45 | |||
46 | sys-supply = <&some_reg>; | ||
47 | vin-sm0-supply = <&some_reg>; | ||
48 | vin-sm1-supply = <&some_reg>; | ||
49 | vin-sm2-supply = <&some_reg>; | ||
50 | vinldo01-supply = <...>; | ||
51 | vinldo23-supply = <...>; | ||
52 | vinldo4-supply = <...>; | ||
53 | vinldo678-supply = <...>; | ||
54 | vinldo9-supply = <...>; | ||
55 | |||
56 | regulators { | ||
57 | sys_reg: sys { | ||
58 | regulator-name = "vdd_sys"; | ||
59 | regulator-boot-on; | ||
60 | regulator-always-on; | ||
61 | }; | ||
62 | |||
63 | sm0_reg: sm0 { | ||
64 | regulator-min-microvolt = < 725000>; | ||
65 | regulator-max-microvolt = <1500000>; | ||
66 | regulator-boot-on; | ||
67 | regulator-always-on; | ||
68 | }; | ||
69 | |||
70 | sm1_reg: sm1 { | ||
71 | regulator-min-microvolt = < 725000>; | ||
72 | regulator-max-microvolt = <1500000>; | ||
73 | regulator-boot-on; | ||
74 | regulator-always-on; | ||
75 | }; | ||
76 | |||
77 | sm2_reg: sm2 { | ||
78 | regulator-min-microvolt = <3000000>; | ||
79 | regulator-max-microvolt = <4550000>; | ||
80 | regulator-boot-on; | ||
81 | regulator-always-on; | ||
82 | }; | ||
83 | |||
84 | ldo0_reg: ldo0 { | ||
85 | regulator-name = "PCIE CLK"; | ||
86 | regulator-min-microvolt = <3300000>; | ||
87 | regulator-max-microvolt = <3300000>; | ||
88 | }; | ||
89 | |||
90 | ldo1_reg: ldo1 { | ||
91 | regulator-min-microvolt = < 725000>; | ||
92 | regulator-max-microvolt = <1500000>; | ||
93 | }; | ||
94 | |||
95 | ldo2_reg: ldo2 { | ||
96 | regulator-min-microvolt = < 725000>; | ||
97 | regulator-max-microvolt = <1500000>; | ||
98 | }; | ||
99 | |||
100 | ldo3_reg: ldo3 { | ||
101 | regulator-min-microvolt = <1250000>; | ||
102 | regulator-max-microvolt = <3300000>; | ||
103 | }; | ||
104 | |||
105 | ldo4_reg: ldo4 { | ||
106 | regulator-min-microvolt = <1700000>; | ||
107 | regulator-max-microvolt = <2475000>; | ||
108 | }; | ||
109 | |||
110 | ldo5_reg: ldo5 { | ||
111 | regulator-min-microvolt = <1250000>; | ||
112 | regulator-max-microvolt = <3300000>; | ||
113 | }; | ||
114 | |||
115 | ldo6_reg: ldo6 { | ||
116 | regulator-min-microvolt = <1250000>; | ||
117 | regulator-max-microvolt = <3300000>; | ||
118 | }; | ||
119 | |||
120 | ldo7_reg: ldo7 { | ||
121 | regulator-min-microvolt = <1250000>; | ||
122 | regulator-max-microvolt = <3300000>; | ||
123 | }; | ||
124 | |||
125 | ldo8_reg: ldo8 { | ||
126 | regulator-min-microvolt = <1250000>; | ||
127 | regulator-max-microvolt = <3300000>; | ||
128 | }; | ||
129 | |||
130 | ldo9_reg: ldo9 { | ||
131 | regulator-min-microvolt = <1250000>; | ||
132 | regulator-max-microvolt = <3300000>; | ||
133 | }; | ||
134 | }; | ||
135 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/twl-regulator.txt b/Documentation/devicetree/bindings/regulator/twl-regulator.txt deleted file mode 100644 index 658749b90b9..00000000000 --- a/Documentation/devicetree/bindings/regulator/twl-regulator.txt +++ /dev/null | |||
@@ -1,67 +0,0 @@ | |||
1 | TWL family of regulators | ||
2 | |||
3 | Required properties: | ||
4 | For twl6030 regulators/LDOs | ||
5 | - compatible: | ||
6 | - "ti,twl6030-vaux1" for VAUX1 LDO | ||
7 | - "ti,twl6030-vaux2" for VAUX2 LDO | ||
8 | - "ti,twl6030-vaux3" for VAUX3 LDO | ||
9 | - "ti,twl6030-vmmc" for VMMC LDO | ||
10 | - "ti,twl6030-vpp" for VPP LDO | ||
11 | - "ti,twl6030-vusim" for VUSIM LDO | ||
12 | - "ti,twl6030-vana" for VANA LDO | ||
13 | - "ti,twl6030-vcxio" for VCXIO LDO | ||
14 | - "ti,twl6030-vdac" for VDAC LDO | ||
15 | - "ti,twl6030-vusb" for VUSB LDO | ||
16 | - "ti,twl6030-v1v8" for V1V8 LDO | ||
17 | - "ti,twl6030-v2v1" for V2V1 LDO | ||
18 | - "ti,twl6030-vdd1" for VDD1 SMPS | ||
19 | - "ti,twl6030-vdd2" for VDD2 SMPS | ||
20 | - "ti,twl6030-vdd3" for VDD3 SMPS | ||
21 | For twl6025 regulators/LDOs | ||
22 | - compatible: | ||
23 | - "ti,twl6025-ldo1" for LDO1 LDO | ||
24 | - "ti,twl6025-ldo2" for LDO2 LDO | ||
25 | - "ti,twl6025-ldo3" for LDO3 LDO | ||
26 | - "ti,twl6025-ldo4" for LDO4 LDO | ||
27 | - "ti,twl6025-ldo5" for LDO5 LDO | ||
28 | - "ti,twl6025-ldo6" for LDO6 LDO | ||
29 | - "ti,twl6025-ldo7" for LDO7 LDO | ||
30 | - "ti,twl6025-ldoln" for LDOLN LDO | ||
31 | - "ti,twl6025-ldousb" for LDOUSB LDO | ||
32 | - "ti,twl6025-smps3" for SMPS3 SMPS | ||
33 | - "ti,twl6025-smps4" for SMPS4 SMPS | ||
34 | - "ti,twl6025-vio" for VIO SMPS | ||
35 | For twl4030 regulators/LDOs | ||
36 | - compatible: | ||
37 | - "ti,twl4030-vaux1" for VAUX1 LDO | ||
38 | - "ti,twl4030-vaux2" for VAUX2 LDO | ||
39 | - "ti,twl5030-vaux2" for VAUX2 LDO | ||
40 | - "ti,twl4030-vaux3" for VAUX3 LDO | ||
41 | - "ti,twl4030-vaux4" for VAUX4 LDO | ||
42 | - "ti,twl4030-vmmc1" for VMMC1 LDO | ||
43 | - "ti,twl4030-vmmc2" for VMMC2 LDO | ||
44 | - "ti,twl4030-vpll1" for VPLL1 LDO | ||
45 | - "ti,twl4030-vpll2" for VPLL2 LDO | ||
46 | - "ti,twl4030-vsim" for VSIM LDO | ||
47 | - "ti,twl4030-vdac" for VDAC LDO | ||
48 | - "ti,twl4030-vintana2" for VINTANA2 LDO | ||
49 | - "ti,twl4030-vio" for VIO LDO | ||
50 | - "ti,twl4030-vdd1" for VDD1 SMPS | ||
51 | - "ti,twl4030-vdd2" for VDD2 SMPS | ||
52 | - "ti,twl4030-vintana1" for VINTANA1 LDO | ||
53 | - "ti,twl4030-vintdig" for VINTDIG LDO | ||
54 | - "ti,twl4030-vusb1v5" for VUSB1V5 LDO | ||
55 | - "ti,twl4030-vusb1v8" for VUSB1V8 LDO | ||
56 | - "ti,twl4030-vusb3v1" for VUSB3V1 LDO | ||
57 | |||
58 | Optional properties: | ||
59 | - Any optional property defined in bindings/regulator/regulator.txt | ||
60 | |||
61 | Example: | ||
62 | |||
63 | xyz: regulator@0 { | ||
64 | compatible = "ti,twl6030-vaux1"; | ||
65 | regulator-min-microvolt = <1000000>; | ||
66 | regulator-max-microvolt = <3000000>; | ||
67 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/vexpress.txt b/Documentation/devicetree/bindings/regulator/vexpress.txt deleted file mode 100644 index d775f72487a..00000000000 --- a/Documentation/devicetree/bindings/regulator/vexpress.txt +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | Versatile Express voltage regulators | ||
2 | ------------------------------------ | ||
3 | |||
4 | Requires node properties: | ||
5 | - "compatible" value: "arm,vexpress-volt" | ||
6 | - "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg | ||
7 | (see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt | ||
8 | for more details) | ||
9 | |||
10 | Required regulator properties: | ||
11 | - "regulator-name" | ||
12 | - "regulator-always-on" | ||
13 | |||
14 | Optional regulator properties: | ||
15 | - "regulator-min-microvolt" | ||
16 | - "regulator-max-microvolt" | ||
17 | |||
18 | See Documentation/devicetree/bindings/regulator/regulator.txt | ||
19 | for more details about the regulator properties. | ||
20 | |||
21 | When no "regulator-[min|max]-microvolt" properties are defined, | ||
22 | the device is treated as fixed (or rather "read-only") regulator. | ||
23 | |||
24 | Example: | ||
25 | volt@0 { | ||
26 | compatible = "arm,vexpress-volt"; | ||
27 | arm,vexpress-sysreg,func = <2 0>; | ||
28 | regulator-name = "Cores"; | ||
29 | regulator-min-microvolt = <800000>; | ||
30 | regulator-max-microvolt = <1050000>; | ||
31 | regulator-always-on; | ||
32 | }; | ||
diff --git a/Documentation/devicetree/bindings/resource-names.txt b/Documentation/devicetree/bindings/resource-names.txt deleted file mode 100644 index e280fef6f26..00000000000 --- a/Documentation/devicetree/bindings/resource-names.txt +++ /dev/null | |||
@@ -1,54 +0,0 @@ | |||
1 | Some properties contain an ordered list of 1 or more datum which are | ||
2 | normally accessed by index. However, some devices will have multiple | ||
3 | values which are more naturally accessed by name. Device nodes can | ||
4 | include a supplemental property for assigning names to each of the list | ||
5 | items. The names property consists of a list of strings in the same | ||
6 | order as the data in the resource property. | ||
7 | |||
8 | The following supplemental names properties are defined. | ||
9 | |||
10 | Resource Property Supplemental Names Property | ||
11 | ----------------- --------------------------- | ||
12 | reg reg-names | ||
13 | clocks clock-names | ||
14 | interrupts interrupt-names | ||
15 | |||
16 | Usage: | ||
17 | |||
18 | The -names property must be used in conjunction with the normal resource | ||
19 | property. If not it will be ignored. | ||
20 | |||
21 | Examples: | ||
22 | |||
23 | l4-abe { | ||
24 | compatible = "simple-bus"; | ||
25 | #address-cells = <2>; | ||
26 | #size-cells = <1>; | ||
27 | ranges = <0 0 0x48000000 0x00001000>, /* MPU path */ | ||
28 | <1 0 0x49000000 0x00001000>; /* L3 path */ | ||
29 | mcasp { | ||
30 | compatible = "ti,mcasp"; | ||
31 | reg = <0 0x10 0x10>, <0 0x20 0x10>, | ||
32 | <1 0x10 0x10>, <1 0x20 0x10>; | ||
33 | reg-names = "mpu", "dat", | ||
34 | "dma", "dma_dat"; | ||
35 | interrupts = <11>, <12>; | ||
36 | interrupt-names = "rx", "tx"; | ||
37 | }; | ||
38 | |||
39 | timer { | ||
40 | compatible = "ti,timer"; | ||
41 | reg = <0 0x40 0x10>, <1 0x40 0x10>; | ||
42 | reg-names = "mpu", "dma"; | ||
43 | }; | ||
44 | }; | ||
45 | |||
46 | |||
47 | usb { | ||
48 | compatible = "ti,usb-host"; | ||
49 | reg = <0x4a064000 0x800>, <0x4a064800 0x200>, | ||
50 | <0x4a064c00 0x200>; | ||
51 | reg-names = "config", "ohci", "ehci"; | ||
52 | interrupts = <14>, <15>; | ||
53 | interrupt-names = "ohci", "ehci"; | ||
54 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt deleted file mode 100644 index 93e2b0f048e..00000000000 --- a/Documentation/devicetree/bindings/rtc/dw-apb.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * Designware APB timer | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "snps,dw-apb-timer-sp" or "snps,dw-apb-timer-osc" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: IRQ line for the timer. | ||
8 | - clock-frequency: The frequency in HZ of the timer. | ||
9 | - clock-freq: For backwards compatibility with picoxcell | ||
10 | |||
11 | Example: | ||
12 | |||
13 | timer1: timer@ffc09000 { | ||
14 | compatible = "snps,dw-apb-timer-sp"; | ||
15 | interrupts = <0 168 4>; | ||
16 | clock-frequency = <200000000>; | ||
17 | reg = <0xffc09000 0x1000>; | ||
18 | }; | ||
19 | |||
20 | timer2: timer@ffd00000 { | ||
21 | compatible = "snps,dw-apb-timer-osc"; | ||
22 | interrupts = <0 169 4>; | ||
23 | clock-frequency = <200000000>; | ||
24 | reg = <0xffd00000 0x1000>; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt deleted file mode 100644 index c9d80d7da14..00000000000 --- a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * i.MX25 Real Time Clock controller | ||
2 | |||
3 | This binding supports the following chips: i.MX25, i.MX53 | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: should be: "fsl,imx25-rtc" | ||
7 | - reg: physical base address of the controller and length of memory mapped | ||
8 | region. | ||
9 | - interrupts: rtc alarm interrupt | ||
10 | |||
11 | Example: | ||
12 | |||
13 | rtc@80056000 { | ||
14 | compatible = "fsl,imx53-rtc", "fsl,imx25-rtc"; | ||
15 | reg = <0x80056000 2000>; | ||
16 | interrupts = <29>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt b/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt deleted file mode 100644 index a87a1e9bc06..00000000000 --- a/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | * NXP LPC32xx SoC Real Time Clock controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "nxp,lpc3220-rtc" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: The RTC interrupt | ||
8 | |||
9 | Example: | ||
10 | |||
11 | rtc@40024000 { | ||
12 | compatible = "nxp,lpc3220-rtc"; | ||
13 | reg = <0x40024000 0x1000>; | ||
14 | interrupts = <52 0>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt deleted file mode 100644 index 93f45e9dce7..00000000000 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | NVIDIA Tegra20 real-time clock | ||
2 | |||
3 | The Tegra RTC maintains seconds and milliseconds counters, and five alarm | ||
4 | registers. The alarms and other interrupts may wake the system from low-power | ||
5 | state. | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible : should be "nvidia,tegra20-rtc". | ||
10 | - reg : Specifies base physical address and size of the registers. | ||
11 | - interrupts : A single interrupt specifier. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | timer { | ||
16 | compatible = "nvidia,tegra20-rtc"; | ||
17 | reg = <0x7000e000 0x100>; | ||
18 | interrupts = <0 2 0x04>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/orion-rtc.txt b/Documentation/devicetree/bindings/rtc/orion-rtc.txt deleted file mode 100644 index 3bf63ffa516..00000000000 --- a/Documentation/devicetree/bindings/rtc/orion-rtc.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | * Mvebu Real Time Clock | ||
2 | |||
3 | RTC controller for the Kirkwood, the Dove, the Armada 370 and the | ||
4 | Armada XP SoCs | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : Should be "marvell,orion-rtc" | ||
8 | - reg: physical base address of the controller and length of memory mapped | ||
9 | region. | ||
10 | - interrupts: IRQ line for the RTC. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | rtc@10300 { | ||
15 | compatible = "marvell,orion-rtc"; | ||
16 | reg = <0xd0010300 0x20>; | ||
17 | interrupts = <50>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt deleted file mode 100644 index 8c6672a1b7d..00000000000 --- a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * PXA RTC | ||
2 | |||
3 | PXA specific RTC driver. | ||
4 | |||
5 | Required properties: | ||
6 | - compatible : Should be "marvell,pxa-rtc" | ||
7 | |||
8 | Examples: | ||
9 | |||
10 | rtc@40900000 { | ||
11 | compatible = "marvell,pxa-rtc"; | ||
12 | reg = <0x40900000 0x3c>; | ||
13 | interrupts = <30 31>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/rtc-omap.txt b/Documentation/devicetree/bindings/rtc/rtc-omap.txt deleted file mode 100644 index b47aa415c82..00000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-omap.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | TI Real Time Clock | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,da830-rtc" | ||
5 | - reg: Address range of rtc register set | ||
6 | - interrupts: rtc timer, alarm interrupts in order | ||
7 | - interrupt-parent: phandle for the interrupt controller | ||
8 | |||
9 | Example: | ||
10 | |||
11 | rtc@1c23000 { | ||
12 | compatible = "ti,da830-rtc"; | ||
13 | reg = <0x23000 0x1000>; | ||
14 | interrupts = <19 | ||
15 | 19>; | ||
16 | interrupt-parent = <&intc>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt deleted file mode 100644 index 90ec45fd33e..00000000000 --- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | * Samsung's S3C Real Time Clock controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be one of the following. | ||
5 | * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc. | ||
6 | * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc. | ||
7 | - reg: physical base address of the controller and length of memory mapped | ||
8 | region. | ||
9 | - interrupts: Two interrupt numbers to the cpu should be specified. First | ||
10 | interrupt number is the rtc alarm interupt and second interrupt number | ||
11 | is the rtc tick interrupt. The number of cells representing a interrupt | ||
12 | depends on the parent interrupt controller. | ||
13 | |||
14 | Example: | ||
15 | |||
16 | rtc@10070000 { | ||
17 | compatible = "samsung,s3c6410-rtc"; | ||
18 | reg = <0x10070000 0x100>; | ||
19 | interrupts = <44 0 45 0>; | ||
20 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt b/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt deleted file mode 100644 index 0cda19ad485..00000000000 --- a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * Marvell Real Time Clock controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "mrvl,sa1100-rtc" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: Should be two. The first interrupt number is the rtc alarm | ||
8 | interrupt and the second interrupt number is the rtc hz interrupt. | ||
9 | - interrupt-names: Assign name of irq resource. | ||
10 | |||
11 | Example: | ||
12 | rtc: rtc@d4010000 { | ||
13 | compatible = "mrvl,mmp-rtc"; | ||
14 | reg = <0xd4010000 0x1000>; | ||
15 | interrupts = <5>, <6>; | ||
16 | interrupt-name = "rtc 1Hz", "rtc alarm"; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/snvs-rtc.txt b/Documentation/devicetree/bindings/rtc/snvs-rtc.txt deleted file mode 100644 index fb61ed77ada..00000000000 --- a/Documentation/devicetree/bindings/rtc/snvs-rtc.txt +++ /dev/null | |||
@@ -1 +0,0 @@ | |||
1 | See Documentation/devicetree/bindings/crypto/fsl-sec4.txt for details. | ||
diff --git a/Documentation/devicetree/bindings/rtc/spear-rtc.txt b/Documentation/devicetree/bindings/rtc/spear-rtc.txt deleted file mode 100644 index ca67ac62108..00000000000 --- a/Documentation/devicetree/bindings/rtc/spear-rtc.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * SPEAr RTC | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "st,spear600-rtc" | ||
5 | - reg : Address range of the rtc registers | ||
6 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
7 | that services interrupts for this device | ||
8 | - interrupt: Should contain the rtc interrupt number | ||
9 | |||
10 | Example: | ||
11 | |||
12 | rtc@fc000000 { | ||
13 | compatible = "st,spear600-rtc"; | ||
14 | reg = <0xfc000000 0x1000>; | ||
15 | interrupt-parent = <&vic1>; | ||
16 | interrupts = <12>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt b/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt deleted file mode 100644 index b800070fe6e..00000000000 --- a/Documentation/devicetree/bindings/rtc/stmp3xxx-rtc.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | * STMP3xxx/i.MX28 Time Clock controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be one of the following. | ||
5 | * "fsl,stmp3xxx-rtc" | ||
6 | - reg: physical base address of the controller and length of memory mapped | ||
7 | region. | ||
8 | - interrupts: rtc alarm interrupt | ||
9 | |||
10 | Example: | ||
11 | |||
12 | rtc@80056000 { | ||
13 | compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; | ||
14 | reg = <0x80056000 2000>; | ||
15 | interrupts = <29>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/twl-rtc.txt b/Documentation/devicetree/bindings/rtc/twl-rtc.txt deleted file mode 100644 index 596e0c97be7..00000000000 --- a/Documentation/devicetree/bindings/rtc/twl-rtc.txt +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | * TI twl RTC | ||
2 | |||
3 | The TWL family (twl4030/6030) contains a RTC. | ||
4 | |||
5 | Required properties: | ||
6 | - compatible : Should be twl4030-rtc | ||
7 | |||
8 | Examples: | ||
9 | |||
10 | rtc@0 { | ||
11 | compatible = "ti,twl4030-rtc"; | ||
12 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt deleted file mode 100644 index 3c0484c4958..00000000000 --- a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500 Realtime Clock Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "via,vt8500-rtc" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | - interrupts : alarm interrupt | ||
8 | |||
9 | Example: | ||
10 | |||
11 | rtc@d8100000 { | ||
12 | compatible = "via,vt8500-rtc"; | ||
13 | reg = <0xd8100000 0x10000>; | ||
14 | interrupts = <48>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/cavium-uart.txt b/Documentation/devicetree/bindings/serial/cavium-uart.txt deleted file mode 100644 index 87a6c375cd4..00000000000 --- a/Documentation/devicetree/bindings/serial/cavium-uart.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | * Universal Asynchronous Receiver/Transmitter (UART) | ||
2 | |||
3 | - compatible: "cavium,octeon-3860-uart" | ||
4 | |||
5 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
6 | |||
7 | - reg: The base address of the UART register bank. | ||
8 | |||
9 | - interrupts: A single interrupt specifier. | ||
10 | |||
11 | - current-speed: Optional, the current bit rate in bits per second. | ||
12 | |||
13 | Example: | ||
14 | uart1: serial@1180000000c00 { | ||
15 | compatible = "cavium,octeon-3860-uart","ns16550"; | ||
16 | reg = <0x11800 0x00000c00 0x0 0x400>; | ||
17 | current-speed = <115200>; | ||
18 | interrupts = <0 35>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt deleted file mode 100644 index c58573b5b1a..00000000000 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | * Freescale i.MX UART controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "fsl,imx21-uart" | ||
5 | - reg : Address and length of the register set for the device | ||
6 | - interrupts : Should contain UART interrupt number | ||
7 | |||
8 | Optional properties: | ||
9 | - fsl,uart-has-rtscts: indicate that RTS/CTS signals are used | ||
10 | |||
11 | Note: Each uart controller should have an alias correctly numbered | ||
12 | in "aliases" node. | ||
13 | |||
14 | Example: | ||
15 | |||
16 | - From imx51.dtsi: | ||
17 | aliases { | ||
18 | serial0 = &uart1; | ||
19 | serial1 = &uart2; | ||
20 | serial2 = &uart3; | ||
21 | }; | ||
22 | |||
23 | uart1: serial@73fbc000 { | ||
24 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; | ||
25 | reg = <0x73fbc000 0x4000>; | ||
26 | interrupts = <31>; | ||
27 | status = "disabled"; | ||
28 | } | ||
29 | |||
30 | - From imx51-babbage.dts: | ||
31 | uart1: serial@73fbc000 { | ||
32 | fsl,uart-has-rtscts; | ||
33 | status = "okay"; | ||
34 | }; | ||
35 | |||
diff --git a/Documentation/devicetree/bindings/serial/mrvl-serial.txt b/Documentation/devicetree/bindings/serial/mrvl-serial.txt deleted file mode 100644 index d744340de88..00000000000 --- a/Documentation/devicetree/bindings/serial/mrvl-serial.txt +++ /dev/null | |||
@@ -1,4 +0,0 @@ | |||
1 | PXA UART controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "mrvl,mmp-uart" or "mrvl,pxa-uart". | ||
diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt deleted file mode 100644 index 342eedd1005..00000000000 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ /dev/null | |||
@@ -1,10 +0,0 @@ | |||
1 | OMAP UART controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "ti,omap2-uart" for OMAP2 controllers | ||
5 | - compatible : should be "ti,omap3-uart" for OMAP3 controllers | ||
6 | - compatible : should be "ti,omap4-uart" for OMAP4 controllers | ||
7 | - ti,hwmods : Must be "uart<n>", n being the instance number (1-based) | ||
8 | |||
9 | Optional properties: | ||
10 | - clock-frequency : frequency of the clock input to the UART | ||
diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt deleted file mode 100644 index 1e753c69fc8..00000000000 --- a/Documentation/devicetree/bindings/serial/rs485.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | * RS485 serial communications | ||
2 | |||
3 | The RTS signal is capable of automatically controlling line direction for | ||
4 | the built-in half-duplex mode. | ||
5 | The properties described hereafter shall be given to a half-duplex capable | ||
6 | UART node. | ||
7 | |||
8 | Required properties: | ||
9 | - rs485-rts-delay: prop-encoded-array <a b> where: | ||
10 | * a is the delay beteween rts signal and beginning of data sent in milliseconds. | ||
11 | it corresponds to the delay before sending data. | ||
12 | * b is the delay between end of data sent and rts signal in milliseconds | ||
13 | it corresponds to the delay after sending data and actual release of the line. | ||
14 | |||
15 | Optional properties: | ||
16 | - linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485 | ||
17 | feature at boot time. It can be disabled later with proper ioctl. | ||
18 | - rs485-rx-during-tx: empty property that enables the receiving of data even | ||
19 | whilst sending data. | ||
20 | |||
21 | RS485 example for Atmel USART: | ||
22 | usart0: serial@fff8c000 { | ||
23 | compatible = "atmel,at91sam9260-usart"; | ||
24 | reg = <0xfff8c000 0x4000>; | ||
25 | interrupts = <7>; | ||
26 | atmel,use-dma-rx; | ||
27 | atmel,use-dma-tx; | ||
28 | linux,rs485-enabled-at-boot-time; | ||
29 | rs485-rts-delay = <0 200>; // in milliseconds | ||
30 | }; | ||
31 | |||
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.txt b/Documentation/devicetree/bindings/serial/samsung_uart.txt deleted file mode 100644 index 2c8a17cf5cb..00000000000 --- a/Documentation/devicetree/bindings/serial/samsung_uart.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * Samsung's UART Controller | ||
2 | |||
3 | The Samsung's UART controller is used for interfacing SoC with serial communicaion | ||
4 | devices. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: should be | ||
8 | - "samsung,exynos4210-uart", for UART's compatible with Exynos4210 uart ports. | ||
9 | |||
10 | - reg: base physical address of the controller and length of memory mapped | ||
11 | region. | ||
12 | |||
13 | - interrupts: interrupt number to the cpu. The interrupt specifier format depends | ||
14 | on the interrupt controller parent. | ||
diff --git a/Documentation/devicetree/bindings/sound/ak4104.txt b/Documentation/devicetree/bindings/sound/ak4104.txt deleted file mode 100644 index b902ee39cf8..00000000000 --- a/Documentation/devicetree/bindings/sound/ak4104.txt +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | AK4104 S/PDIF transmitter | ||
2 | |||
3 | This device supports SPI mode only. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "asahi-kasei,ak4104" | ||
8 | |||
9 | - reg : The chip select number on the SPI bus | ||
10 | |||
11 | Optional properties: | ||
12 | |||
13 | - reset-gpio : a GPIO spec for the reset pin. If specified, it will be | ||
14 | deasserted before communication to the device starts. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | spdif: ak4104@0 { | ||
19 | compatible = "asahi-kasei,ak4104"; | ||
20 | reg = <0>; | ||
21 | spi-max-frequency = <5000000>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/alc5632.txt b/Documentation/devicetree/bindings/sound/alc5632.txt deleted file mode 100644 index 8608f747dcf..00000000000 --- a/Documentation/devicetree/bindings/sound/alc5632.txt +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | ALC5632 audio CODEC | ||
2 | |||
3 | This device supports I2C only. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "realtek,alc5632" | ||
8 | |||
9 | - reg : the I2C address of the device. | ||
10 | |||
11 | - gpio-controller : Indicates this device is a GPIO controller. | ||
12 | |||
13 | - #gpio-cells : Should be two. The first cell is the pin number and the | ||
14 | second cell is used to specify optional parameters (currently unused). | ||
15 | |||
16 | Example: | ||
17 | |||
18 | alc5632: alc5632@1e { | ||
19 | compatible = "realtek,alc5632"; | ||
20 | reg = <0x1a>; | ||
21 | |||
22 | gpio-controller; | ||
23 | #gpio-cells = <2>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt b/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt deleted file mode 100644 index 9c5a9947b64..00000000000 --- a/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | * Atmel at91sam9g20ek wm8731 audio complex | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "atmel,at91sam9g20ek-wm8731-audio" | ||
5 | - atmel,model: The user-visible name of this sound complex. | ||
6 | - atmel,audio-routing: A list of the connections between audio components. | ||
7 | - atmel,ssc-controller: The phandle of the SSC controller | ||
8 | - atmel,audio-codec: The phandle of the WM8731 audio codec | ||
9 | Optional properties: | ||
10 | - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt | ||
11 | |||
12 | Example: | ||
13 | sound { | ||
14 | compatible = "atmel,at91sam9g20ek-wm8731-audio"; | ||
15 | pinctrl-names = "default"; | ||
16 | pinctrl-0 = <&pinctrl_pck0_as_mck>; | ||
17 | |||
18 | atmel,model = "wm8731 @ AT91SAMG20EK"; | ||
19 | |||
20 | atmel,audio-routing = | ||
21 | "Ext Spk", "LHPOUT", | ||
22 | "Int MIC", "MICIN"; | ||
23 | |||
24 | atmel,ssc-controller = <&ssc0>; | ||
25 | atmel,audio-codec = <&wm8731>; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/cs4270.txt b/Documentation/devicetree/bindings/sound/cs4270.txt deleted file mode 100644 index 6b222f9b8ef..00000000000 --- a/Documentation/devicetree/bindings/sound/cs4270.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | CS4270 audio CODEC | ||
2 | |||
3 | The driver for this device currently only supports I2C. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "cirrus,cs4270" | ||
8 | |||
9 | - reg : the I2C address of the device for I2C | ||
10 | |||
11 | Optional properties: | ||
12 | |||
13 | - reset-gpio : a GPIO spec for the reset pin. If specified, it will be | ||
14 | deasserted before communication to the codec starts. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | codec: cs4270@48 { | ||
19 | compatible = "cirrus,cs4270"; | ||
20 | reg = <0x48>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/cs4271.txt b/Documentation/devicetree/bindings/sound/cs4271.txt deleted file mode 100644 index a850fb9c88e..00000000000 --- a/Documentation/devicetree/bindings/sound/cs4271.txt +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | Cirrus Logic CS4271 DT bindings | ||
2 | |||
3 | This driver supports both the I2C and the SPI bus. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible: "cirrus,cs4271" | ||
8 | |||
9 | For required properties on SPI, please consult | ||
10 | Documentation/devicetree/bindings/spi/spi-bus.txt | ||
11 | |||
12 | Required properties on I2C: | ||
13 | |||
14 | - reg: the i2c address | ||
15 | |||
16 | |||
17 | Optional properties: | ||
18 | |||
19 | - reset-gpio: a GPIO spec to define which pin is connected to the chip's | ||
20 | !RESET pin | ||
21 | - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag | ||
22 | is enabled. | ||
23 | |||
24 | Examples: | ||
25 | |||
26 | codec_i2c: cs4271@10 { | ||
27 | compatible = "cirrus,cs4271"; | ||
28 | reg = <0x10>; | ||
29 | reset-gpio = <&gpio 23 0>; | ||
30 | }; | ||
31 | |||
32 | codec_spi: cs4271@0 { | ||
33 | compatible = "cirrus,cs4271"; | ||
34 | reg = <0x0>; | ||
35 | reset-gpio = <&gpio 23 0>; | ||
36 | spi-max-frequency = <6000000>; | ||
37 | }; | ||
38 | |||
diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt deleted file mode 100644 index 374e145c2ef..00000000000 --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt +++ /dev/null | |||
@@ -1,45 +0,0 @@ | |||
1 | Texas Instruments McASP controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : | ||
5 | "ti,dm646x-mcasp-audio" : for DM646x platforms | ||
6 | "ti,da830-mcasp-audio" : for both DA830 & DA850 platforms | ||
7 | "ti,omap2-mcasp-audio" : for OMAP2 platforms (TI81xx, AM33xx) | ||
8 | |||
9 | - reg : Should contain McASP registers offset and length | ||
10 | - interrupts : Interrupt number for McASP | ||
11 | - op-mode : I2S/DIT ops mode. | ||
12 | - tdm-slots : Slots for TDM operation. | ||
13 | - num-serializer : Serializers used by McASP. | ||
14 | - serial-dir : A list of serializer pin mode. The list number should be equal | ||
15 | to "num-serializer" parameter. Each entry is a number indication | ||
16 | serializer pin direction. (0 - INACTIVE, 1 - TX, 2 - RX) | ||
17 | |||
18 | |||
19 | Optional properties: | ||
20 | |||
21 | - ti,hwmods : Must be "mcasp<n>", n is controller instance starting 0 | ||
22 | - tx-num-evt : FIFO levels. | ||
23 | - rx-num-evt : FIFO levels. | ||
24 | - sram-size-playback : size of sram to be allocated during playback | ||
25 | - sram-size-capture : size of sram to be allocated during capture | ||
26 | |||
27 | Example: | ||
28 | |||
29 | mcasp0: mcasp0@1d00000 { | ||
30 | compatible = "ti,da830-mcasp-audio"; | ||
31 | #address-cells = <1>; | ||
32 | #size-cells = <0>; | ||
33 | reg = <0x100000 0x3000>; | ||
34 | interrupts = <82 83>; | ||
35 | op-mode = <0>; /* MCASP_IIS_MODE */ | ||
36 | tdm-slots = <2>; | ||
37 | num-serializer = <16>; | ||
38 | serial-dir = < | ||
39 | 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */ | ||
40 | 0 0 0 0 | ||
41 | 0 0 0 1 | ||
42 | 2 0 0 0 >; | ||
43 | tx-num-evt = <1>; | ||
44 | rx-num-evt = <1>; | ||
45 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt deleted file mode 100644 index e4acdd891e4..00000000000 --- a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | Freescale i.MX audio complex with SGTL5000 codec | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "fsl,imx-audio-sgtl5000" | ||
5 | - model : The user-visible name of this sound complex | ||
6 | - ssi-controller : The phandle of the i.MX SSI controller | ||
7 | - audio-codec : The phandle of the SGTL5000 audio codec | ||
8 | - audio-routing : A list of the connections between audio components. | ||
9 | Each entry is a pair of strings, the first being the connection's sink, | ||
10 | the second being the connection's source. Valid names could be power | ||
11 | supplies, SGTL5000 pins, and the jacks on the board: | ||
12 | |||
13 | Power supplies: | ||
14 | * Mic Bias | ||
15 | |||
16 | SGTL5000 pins: | ||
17 | * MIC_IN | ||
18 | * LINE_IN | ||
19 | * HP_OUT | ||
20 | * LINE_OUT | ||
21 | |||
22 | Board connectors: | ||
23 | * Mic Jack | ||
24 | * Line In Jack | ||
25 | * Headphone Jack | ||
26 | * Line Out Jack | ||
27 | * Ext Spk | ||
28 | |||
29 | - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) | ||
30 | - mux-ext-port : The external port of the i.MX audio muxer | ||
31 | |||
32 | Note: The AUDMUX port numbering should start at 1, which is consistent with | ||
33 | hardware manual. | ||
34 | |||
35 | Example: | ||
36 | |||
37 | sound { | ||
38 | compatible = "fsl,imx51-babbage-sgtl5000", | ||
39 | "fsl,imx-audio-sgtl5000"; | ||
40 | model = "imx51-babbage-sgtl5000"; | ||
41 | ssi-controller = <&ssi1>; | ||
42 | audio-codec = <&sgtl5000>; | ||
43 | audio-routing = | ||
44 | "MIC_IN", "Mic Jack", | ||
45 | "Mic Jack", "Mic Bias", | ||
46 | "Headphone Jack", "HP_OUT"; | ||
47 | mux-int-port = <1>; | ||
48 | mux-ext-port = <3>; | ||
49 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/imx-audmux.txt b/Documentation/devicetree/bindings/sound/imx-audmux.txt deleted file mode 100644 index 215aa981721..00000000000 --- a/Documentation/devicetree/bindings/sound/imx-audmux.txt +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | Freescale Digital Audio Mux (AUDMUX) device | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "fsl,imx21-audmux" for AUDMUX version firstly used on i.MX21, | ||
5 | or "fsl,imx31-audmux" for the version firstly used on i.MX31. | ||
6 | - reg : Should contain AUDMUX registers location and length | ||
7 | |||
8 | Example: | ||
9 | |||
10 | audmux@021d8000 { | ||
11 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; | ||
12 | reg = <0x021d8000 0x4000>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt deleted file mode 100644 index 601c518edda..00000000000 --- a/Documentation/devicetree/bindings/sound/mxs-audio-sgtl5000.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * Freescale MXS audio complex with SGTL5000 codec | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "fsl,mxs-audio-sgtl5000" | ||
5 | - model: The user-visible name of this sound complex | ||
6 | - saif-controllers: The phandle list of the MXS SAIF controller | ||
7 | - audio-codec: The phandle of the SGTL5000 audio codec | ||
8 | |||
9 | Example: | ||
10 | |||
11 | sound { | ||
12 | compatible = "fsl,imx28-evk-sgtl5000", | ||
13 | "fsl,mxs-audio-sgtl5000"; | ||
14 | model = "imx28-evk-sgtl5000"; | ||
15 | saif-controllers = <&saif0 &saif1>; | ||
16 | audio-codec = <&sgtl5000>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/mxs-saif.txt b/Documentation/devicetree/bindings/sound/mxs-saif.txt deleted file mode 100644 index c37ba6143d9..00000000000 --- a/Documentation/devicetree/bindings/sound/mxs-saif.txt +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | * Freescale MXS Serial Audio Interface (SAIF) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,<chip>-saif" | ||
5 | - reg: Should contain registers location and length | ||
6 | - interrupts: Should contain ERROR and DMA interrupts | ||
7 | - fsl,saif-dma-channel: APBX DMA channel for the SAIF | ||
8 | |||
9 | Optional properties: | ||
10 | - fsl,saif-master: phandle to the master SAIF. It's only required for | ||
11 | the slave SAIF. | ||
12 | |||
13 | Note: Each SAIF controller should have an alias correctly numbered | ||
14 | in "aliases" node. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | aliases { | ||
19 | saif0 = &saif0; | ||
20 | saif1 = &saif1; | ||
21 | }; | ||
22 | |||
23 | saif0: saif@80042000 { | ||
24 | compatible = "fsl,imx28-saif"; | ||
25 | reg = <0x80042000 2000>; | ||
26 | interrupts = <59 80>; | ||
27 | fsl,saif-dma-channel = <4>; | ||
28 | }; | ||
29 | |||
30 | saif1: saif@80046000 { | ||
31 | compatible = "fsl,imx28-saif"; | ||
32 | reg = <0x80046000 2000>; | ||
33 | interrupts = <58 81>; | ||
34 | fsl,saif-dma-channel = <5>; | ||
35 | fsl,saif-master = <&saif0>; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt deleted file mode 100644 index b77a97c9101..00000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt +++ /dev/null | |||
@@ -1,59 +0,0 @@ | |||
1 | NVIDIA Tegra audio complex | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra-audio-alc5632" | ||
5 | - nvidia,model : The user-visible name of this sound complex. | ||
6 | - nvidia,audio-routing : A list of the connections between audio components. | ||
7 | Each entry is a pair of strings, the first being the connection's sink, | ||
8 | the second being the connection's source. Valid names for sources and | ||
9 | sinks are the ALC5632's pins: | ||
10 | |||
11 | ALC5632 pins: | ||
12 | |||
13 | * SPK_OUTP | ||
14 | * SPK_OUTN | ||
15 | * HP_OUT_L | ||
16 | * HP_OUT_R | ||
17 | * AUX_OUT_P | ||
18 | * AUX_OUT_N | ||
19 | * LINE_IN_L | ||
20 | * LINE_IN_R | ||
21 | * PHONE_P | ||
22 | * PHONE_N | ||
23 | * MIC1_P | ||
24 | * MIC1_N | ||
25 | * MIC2_P | ||
26 | * MIC2_N | ||
27 | * MICBIAS1 | ||
28 | * DMICDAT | ||
29 | |||
30 | Board connectors: | ||
31 | |||
32 | * Headset Stereophone | ||
33 | * Int Spk | ||
34 | * Headset Mic | ||
35 | * Digital Mic | ||
36 | |||
37 | - nvidia,i2s-controller : The phandle of the Tegra I2S controller | ||
38 | - nvidia,audio-codec : The phandle of the ALC5632 audio codec | ||
39 | |||
40 | Example: | ||
41 | |||
42 | sound { | ||
43 | compatible = "nvidia,tegra-audio-alc5632-paz00", | ||
44 | "nvidia,tegra-audio-alc5632"; | ||
45 | |||
46 | nvidia,model = "Compal PAZ00"; | ||
47 | |||
48 | nvidia,audio-routing = | ||
49 | "Int Spk", "SPK_OUTP", | ||
50 | "Int Spk", "SPK_OUTN", | ||
51 | "Headset Mic","MICBIAS1", | ||
52 | "MIC1_N", "Headset Mic", | ||
53 | "MIC1_P", "Headset Mic", | ||
54 | "Headset Stereophone", "HP_OUT_R", | ||
55 | "Headset Stereophone", "HP_OUT_L"; | ||
56 | |||
57 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
58 | nvidia,audio-codec = <&alc5632>; | ||
59 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt deleted file mode 100644 index 04b14cfb1f1..00000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | NVIDIA Tegra audio complex for TrimSlice | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra-audio-trimslice" | ||
5 | - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller | ||
6 | - nvidia,audio-codec : The phandle of the WM8903 audio codec | ||
7 | |||
8 | Example: | ||
9 | |||
10 | sound { | ||
11 | compatible = "nvidia,tegra-audio-trimslice"; | ||
12 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
13 | nvidia,audio-codec = <&codec>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt deleted file mode 100644 index c4dd39ce616..00000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt +++ /dev/null | |||
@@ -1,54 +0,0 @@ | |||
1 | NVIDIA Tegra audio complex | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra-audio-wm8753" | ||
5 | - nvidia,model : The user-visible name of this sound complex. | ||
6 | - nvidia,audio-routing : A list of the connections between audio components. | ||
7 | Each entry is a pair of strings, the first being the connection's sink, | ||
8 | the second being the connection's source. Valid names for sources and | ||
9 | sinks are the WM8753's pins, and the jacks on the board: | ||
10 | |||
11 | WM8753 pins: | ||
12 | |||
13 | * LOUT1 | ||
14 | * LOUT2 | ||
15 | * ROUT1 | ||
16 | * ROUT2 | ||
17 | * MONO1 | ||
18 | * MONO2 | ||
19 | * OUT3 | ||
20 | * OUT4 | ||
21 | * LINE1 | ||
22 | * LINE2 | ||
23 | * RXP | ||
24 | * RXN | ||
25 | * ACIN | ||
26 | * ACOP | ||
27 | * MIC1N | ||
28 | * MIC1 | ||
29 | * MIC2N | ||
30 | * MIC2 | ||
31 | * Mic Bias | ||
32 | |||
33 | Board connectors: | ||
34 | |||
35 | * Headphone Jack | ||
36 | * Mic Jack | ||
37 | |||
38 | - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller | ||
39 | - nvidia,audio-codec : The phandle of the WM8753 audio codec | ||
40 | Example: | ||
41 | |||
42 | sound { | ||
43 | compatible = "nvidia,tegra-audio-wm8753-whistler", | ||
44 | "nvidia,tegra-audio-wm8753" | ||
45 | nvidia,model = "tegra-wm8753-harmony"; | ||
46 | |||
47 | nvidia,audio-routing = | ||
48 | "Headphone Jack", "LOUT1", | ||
49 | "Headphone Jack", "ROUT1"; | ||
50 | |||
51 | nvidia,i2s-controller = <&i2s1>; | ||
52 | nvidia,audio-codec = <&wm8753>; | ||
53 | }; | ||
54 | |||
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt deleted file mode 100644 index d5b0da8bf1d..00000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt +++ /dev/null | |||
@@ -1,71 +0,0 @@ | |||
1 | NVIDIA Tegra audio complex | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra-audio-wm8903" | ||
5 | - nvidia,model : The user-visible name of this sound complex. | ||
6 | - nvidia,audio-routing : A list of the connections between audio components. | ||
7 | Each entry is a pair of strings, the first being the connection's sink, | ||
8 | the second being the connection's source. Valid names for sources and | ||
9 | sinks are the WM8903's pins, and the jacks on the board: | ||
10 | |||
11 | WM8903 pins: | ||
12 | |||
13 | * IN1L | ||
14 | * IN1R | ||
15 | * IN2L | ||
16 | * IN2R | ||
17 | * IN3L | ||
18 | * IN3R | ||
19 | * DMICDAT | ||
20 | * HPOUTL | ||
21 | * HPOUTR | ||
22 | * LINEOUTL | ||
23 | * LINEOUTR | ||
24 | * LOP | ||
25 | * LON | ||
26 | * ROP | ||
27 | * RON | ||
28 | * MICBIAS | ||
29 | |||
30 | Board connectors: | ||
31 | |||
32 | * Headphone Jack | ||
33 | * Int Spk | ||
34 | * Mic Jack | ||
35 | |||
36 | - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller | ||
37 | - nvidia,audio-codec : The phandle of the WM8903 audio codec | ||
38 | |||
39 | Optional properties: | ||
40 | - nvidia,spkr-en-gpios : The GPIO that enables the speakers | ||
41 | - nvidia,hp-mute-gpios : The GPIO that mutes the headphones | ||
42 | - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in | ||
43 | - nvidia,int-mic-en-gpios : The GPIO that enables the internal microphone | ||
44 | - nvidia,ext-mic-en-gpios : The GPIO that enables the external microphone | ||
45 | |||
46 | Example: | ||
47 | |||
48 | sound { | ||
49 | compatible = "nvidia,tegra-audio-wm8903-harmony", | ||
50 | "nvidia,tegra-audio-wm8903" | ||
51 | nvidia,model = "tegra-wm8903-harmony"; | ||
52 | |||
53 | nvidia,audio-routing = | ||
54 | "Headphone Jack", "HPOUTR", | ||
55 | "Headphone Jack", "HPOUTL", | ||
56 | "Int Spk", "ROP", | ||
57 | "Int Spk", "RON", | ||
58 | "Int Spk", "LOP", | ||
59 | "Int Spk", "LON", | ||
60 | "Mic Jack", "MICBIAS", | ||
61 | "IN1L", "Mic Jack"; | ||
62 | |||
63 | nvidia,i2s-controller = <&i2s1>; | ||
64 | nvidia,audio-codec = <&wm8903>; | ||
65 | |||
66 | nvidia,spkr-en-gpios = <&codec 2 0>; | ||
67 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | ||
68 | nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ | ||
69 | nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ | ||
70 | }; | ||
71 | |||
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt deleted file mode 100644 index 6de3a7ee4ef..00000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | NVIDIA Tegra 20 DAS (Digital Audio Switch) controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra20-das" | ||
5 | - reg : Should contain DAS registers location and length | ||
6 | |||
7 | Example: | ||
8 | |||
9 | das@70000c00 { | ||
10 | compatible = "nvidia,tegra20-das"; | ||
11 | reg = <0x70000c00 0x80>; | ||
12 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt deleted file mode 100644 index 0df2b5c816e..00000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | NVIDIA Tegra 20 I2S controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra20-i2s" | ||
5 | - reg : Should contain I2S registers location and length | ||
6 | - interrupts : Should contain I2S interrupt | ||
7 | - nvidia,dma-request-selector : The Tegra DMA controller's phandle and | ||
8 | request selector for this I2S controller | ||
9 | |||
10 | Example: | ||
11 | |||
12 | i2s@70002800 { | ||
13 | compatible = "nvidia,tegra20-i2s"; | ||
14 | reg = <0x70002800 0x200>; | ||
15 | interrupts = < 45 >; | ||
16 | nvidia,dma-request-selector = < &apbdma 2 >; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt deleted file mode 100644 index 1ac7b164218..00000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | NVIDIA Tegra30 AHUB (Audio Hub) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra30-ahub" | ||
5 | - reg : Should contain the register physical address and length for each of | ||
6 | the AHUB's APBIF registers and the AHUB's own registers. | ||
7 | - interrupts : Should contain AHUB interrupt | ||
8 | - nvidia,dma-request-selector : The Tegra DMA controller's phandle and | ||
9 | request selector for the first APBIF channel. | ||
10 | - ranges : The bus address mapping for the configlink register bus. | ||
11 | Can be empty since the mapping is 1:1. | ||
12 | - #address-cells : For the configlink bus. Should be <1>; | ||
13 | - #size-cells : For the configlink bus. Should be <1>. | ||
14 | |||
15 | AHUB client modules need to specify the IDs of their CIFs (Client InterFaces). | ||
16 | For RX CIFs, the numbers indicate the register number within AHUB routing | ||
17 | register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1). | ||
18 | For TX CIFs, the numbers indicate the bit position within the AHUB routing | ||
19 | registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1). | ||
20 | |||
21 | Example: | ||
22 | |||
23 | ahub@70080000 { | ||
24 | compatible = "nvidia,tegra30-ahub"; | ||
25 | reg = <0x70080000 0x200 0x70080200 0x100>; | ||
26 | interrupts = < 0 103 0x04 >; | ||
27 | nvidia,dma-request-selector = <&apbdma 1>; | ||
28 | |||
29 | ranges; | ||
30 | #address-cells = <1>; | ||
31 | #size-cells = <1>; | ||
32 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt deleted file mode 100644 index dfa6c037124..00000000000 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | NVIDIA Tegra30 I2S controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra30-i2s" | ||
5 | - reg : Should contain I2S registers location and length | ||
6 | - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback) | ||
7 | first, tx (capture) second. See nvidia,tegra30-ahub.txt for values. | ||
8 | |||
9 | Example: | ||
10 | |||
11 | i2s@70002800 { | ||
12 | compatible = "nvidia,tegra30-i2s"; | ||
13 | reg = <0x70080300 0x100>; | ||
14 | nvidia,ahub-cif-ids = <4 4>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt b/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt deleted file mode 100644 index fd40c852d7c..00000000000 --- a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt +++ /dev/null | |||
@@ -1,91 +0,0 @@ | |||
1 | * Texas Instruments OMAP4+ and twl6040 based audio setups | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,abe-twl6040" | ||
5 | - ti,model: Name of the sound card ( for example "SDP4430") | ||
6 | - ti,mclk-freq: MCLK frequency for HPPLL operation | ||
7 | - ti,mcpdm: phandle for the McPDM node | ||
8 | - ti,twl6040: phandle for the twl6040 core node | ||
9 | - ti,audio-routing: List of connections between audio components. | ||
10 | Each entry is a pair of strings, the first being the connection's sink, | ||
11 | the second being the connection's source. | ||
12 | |||
13 | Optional properties: | ||
14 | - ti,dmic: phandle for the OMAP dmic node if the machine have it connected | ||
15 | - ti,jack_detection: Need to be present if the board capable to detect jack | ||
16 | insertion, removal. | ||
17 | |||
18 | Available audio endpoints for the audio-routing table: | ||
19 | |||
20 | Board connectors: | ||
21 | * Headset Stereophone | ||
22 | * Earphone Spk | ||
23 | * Ext Spk | ||
24 | * Line Out | ||
25 | * Vibrator | ||
26 | * Headset Mic | ||
27 | * Main Handset Mic | ||
28 | * Sub Handset Mic | ||
29 | * Line In | ||
30 | * Digital Mic | ||
31 | |||
32 | twl6040 pins: | ||
33 | * HSOL | ||
34 | * HSOR | ||
35 | * EP | ||
36 | * HFL | ||
37 | * HFR | ||
38 | * AUXL | ||
39 | * AUXR | ||
40 | * VIBRAL | ||
41 | * VIBRAR | ||
42 | * HSMIC | ||
43 | * MAINMIC | ||
44 | * SUBMIC | ||
45 | * AFML | ||
46 | * AFMR | ||
47 | |||
48 | * Headset Mic Bias | ||
49 | * Main Mic Bias | ||
50 | * Digital Mic1 Bias | ||
51 | * Digital Mic2 Bias | ||
52 | |||
53 | Digital mic pins: | ||
54 | * DMic | ||
55 | |||
56 | Example: | ||
57 | |||
58 | sound { | ||
59 | compatible = "ti,abe-twl6040"; | ||
60 | ti,model = "SDP4430"; | ||
61 | |||
62 | ti,jack-detection; | ||
63 | ti,mclk-freq = <38400000>; | ||
64 | |||
65 | ti,mcpdm = <&mcpdm>; | ||
66 | ti,dmic = <&dmic>; | ||
67 | |||
68 | ti,twl6040 = <&twl6040>; | ||
69 | |||
70 | /* Audio routing */ | ||
71 | ti,audio-routing = | ||
72 | "Headset Stereophone", "HSOL", | ||
73 | "Headset Stereophone", "HSOR", | ||
74 | "Earphone Spk", "EP", | ||
75 | "Ext Spk", "HFL", | ||
76 | "Ext Spk", "HFR", | ||
77 | "Line Out", "AUXL", | ||
78 | "Line Out", "AUXR", | ||
79 | "Vibrator", "VIBRAL", | ||
80 | "Vibrator", "VIBRAR", | ||
81 | "HSMIC", "Headset Mic", | ||
82 | "Headset Mic", "Headset Mic Bias", | ||
83 | "MAINMIC", "Main Handset Mic", | ||
84 | "Main Handset Mic", "Main Mic Bias", | ||
85 | "SUBMIC", "Sub Handset Mic", | ||
86 | "Sub Handset Mic", "Main Mic Bias", | ||
87 | "AFML", "Line In", | ||
88 | "AFMR", "Line In", | ||
89 | "DMic", "Digital Mic", | ||
90 | "Digital Mic", "Digital Mic1 Bias"; | ||
91 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/omap-dmic.txt b/Documentation/devicetree/bindings/sound/omap-dmic.txt deleted file mode 100644 index fd8105f1897..00000000000 --- a/Documentation/devicetree/bindings/sound/omap-dmic.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | * Texas Instruments OMAP4+ Digital Microphone Module | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,omap4-dmic" | ||
5 | - reg: Register location and size as an array: | ||
6 | <MPU access base address, size>, | ||
7 | <L3 interconnect address, size>; | ||
8 | - interrupts: Interrupt number for DMIC | ||
9 | - interrupt-parent: The parent interrupt controller | ||
10 | - ti,hwmods: Name of the hwmod associated with OMAP dmic IP | ||
11 | |||
12 | Example: | ||
13 | |||
14 | dmic: dmic@4012e000 { | ||
15 | compatible = "ti,omap4-dmic"; | ||
16 | reg = <0x4012e000 0x7f>, /* MPU private access */ | ||
17 | <0x4902e000 0x7f>; /* L3 Interconnect */ | ||
18 | interrupts = <0 114 0x4>; | ||
19 | interrupt-parent = <&gic>; | ||
20 | ti,hwmods = "dmic"; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt deleted file mode 100644 index 17cce449045..00000000000 --- a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | * Texas Instruments OMAP2+ McBSP module | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420 | ||
5 | "ti,omap2430-mcbsp" for McBSP on OMAP2430 | ||
6 | "ti,omap3-mcbsp" for McBSP on OMAP3 | ||
7 | "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC | ||
8 | - reg: Register location and size, for OMAP4+ as an array: | ||
9 | <MPU access base address, size>, | ||
10 | <L3 interconnect address, size>; | ||
11 | - reg-names: Array of strings associated with the address space | ||
12 | - interrupts: Interrupt numbers for the McBSP port, as an array in case the | ||
13 | McBSP IP have more interrupt lines: | ||
14 | <OCP compliant irq>, | ||
15 | <TX irq>, | ||
16 | <RX irq>; | ||
17 | - interrupt-names: Array of strings associated with the interrupt numbers | ||
18 | - interrupt-parent: The parent interrupt controller | ||
19 | - ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC) | ||
20 | - ti,hwmods: Name of the hwmod associated to the McBSP port | ||
21 | |||
22 | Example: | ||
23 | |||
24 | mcbsp2: mcbsp@49022000 { | ||
25 | compatible = "ti,omap3-mcbsp"; | ||
26 | reg = <0x49022000 0xff>, | ||
27 | <0x49028000 0xff>; | ||
28 | reg-names = "mpu", "sidetone"; | ||
29 | interrupts = <0 17 0x4>, /* OCP compliant interrupt */ | ||
30 | <0 62 0x4>, /* TX interrupt */ | ||
31 | <0 63 0x4>, /* RX interrupt */ | ||
32 | <0 4 0x4>; /* Sidetone */ | ||
33 | interrupt-names = "common", "tx", "rx", "sidetone"; | ||
34 | interrupt-parent = <&intc>; | ||
35 | ti,buffer-size = <1280>; | ||
36 | ti,hwmods = "mcbsp2"; | ||
37 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt deleted file mode 100644 index 0741dff048d..00000000000 --- a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | * Texas Instruments OMAP4+ McPDM | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,omap4-mcpdm" | ||
5 | - reg: Register location and size as an array: | ||
6 | <MPU access base address, size>, | ||
7 | <L3 interconnect address, size>; | ||
8 | - interrupts: Interrupt number for McPDM | ||
9 | - interrupt-parent: The parent interrupt controller | ||
10 | - ti,hwmods: Name of the hwmod associated to the McPDM | ||
11 | |||
12 | Example: | ||
13 | |||
14 | mcpdm: mcpdm@40132000 { | ||
15 | compatible = "ti,omap4-mcpdm"; | ||
16 | reg = <0x40132000 0x7f>, /* MPU private access */ | ||
17 | <0x49032000 0x7f>; /* L3 Interconnect */ | ||
18 | interrupts = <0 112 0x4>; | ||
19 | interrupt-parent = <&gic>; | ||
20 | ti,hwmods = "mcpdm"; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt deleted file mode 100644 index 6fae51c7f76..00000000000 --- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * Texas Instruments SoC with twl4030 based audio setups | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,omap-twl4030" | ||
5 | - ti,model: Name of the sound card (for example "omap3beagle") | ||
6 | - ti,mcbsp: phandle for the McBSP node | ||
7 | - ti,codec: phandle for the twl4030 audio node | ||
8 | |||
9 | Example: | ||
10 | |||
11 | sound { | ||
12 | compatible = "ti,omap-twl4030"; | ||
13 | ti,model = "omap3beagle"; | ||
14 | |||
15 | ti,mcbsp = <&mcbsp2>; | ||
16 | ti,codec = <&twl_audio>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt deleted file mode 100644 index 9cc44449508..00000000000 --- a/Documentation/devicetree/bindings/sound/sgtl5000.txt +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | * Freescale SGTL5000 Stereo Codec | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "fsl,sgtl5000". | ||
5 | |||
6 | - reg : the I2C address of the device | ||
7 | |||
8 | Example: | ||
9 | |||
10 | codec: sgtl5000@0a { | ||
11 | compatible = "fsl,sgtl5000"; | ||
12 | reg = <0x0a>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt deleted file mode 100644 index e7b98f41fa5..00000000000 --- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | Texas Instruments - tlv320aic3x Codec module | ||
2 | |||
3 | The tlv320aic3x serial control bus communicates through I2C protocols | ||
4 | |||
5 | Required properties: | ||
6 | - compatible - "string" - "ti,tlv320aic3x" | ||
7 | - reg - <int> - I2C slave address | ||
8 | |||
9 | |||
10 | Optional properties: | ||
11 | |||
12 | - gpio-reset - gpio pin number used for codec reset | ||
13 | - ai3x-gpio-func - <array of 2 int> - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality | ||
14 | |||
15 | Example: | ||
16 | |||
17 | tlv320aic3x: tlv320aic3x@1b { | ||
18 | compatible = "ti,tlv320aic3x"; | ||
19 | reg = <0x1b>; | ||
20 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/ux500-mop500.txt b/Documentation/devicetree/bindings/sound/ux500-mop500.txt deleted file mode 100644 index 48e071c96b4..00000000000 --- a/Documentation/devicetree/bindings/sound/ux500-mop500.txt +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | * MOP500 Audio Machine Driver | ||
2 | |||
3 | This node is responsible for linking together all ux500 Audio Driver components. | ||
4 | |||
5 | Required properties: | ||
6 | - compatible : "stericsson,snd-soc-mop500" | ||
7 | |||
8 | Non-standard properties: | ||
9 | - stericsson,cpu-dai : Phandle to the CPU-side DAI | ||
10 | - stericsson,audio-codec : Phandle to the Audio CODEC | ||
11 | - stericsson,card-name : Over-ride default card name | ||
12 | |||
13 | Example: | ||
14 | |||
15 | sound { | ||
16 | compatible = "stericsson,snd-soc-mop500"; | ||
17 | |||
18 | stericsson,cpu-dai = <&msp1 &msp3>; | ||
19 | stericsson,audio-codec = <&codec>; | ||
20 | }; | ||
21 | |||
22 | msp1: msp@80124000 { | ||
23 | compatible = "stericsson,ux500-msp-i2s"; | ||
24 | reg = <0x80124000 0x1000>; | ||
25 | interrupts = <0 62 0x4>; | ||
26 | v-ape-supply = <&db8500_vape_reg>; | ||
27 | }; | ||
28 | |||
29 | msp3: msp@80125000 { | ||
30 | compatible = "stericsson,ux500-msp-i2s"; | ||
31 | reg = <0x80125000 0x1000>; | ||
32 | interrupts = <0 62 0x4>; | ||
33 | v-ape-supply = <&db8500_vape_reg>; | ||
34 | }; | ||
35 | |||
36 | codec: ab8500-codec { | ||
37 | compatible = "stericsson,ab8500-codec"; | ||
38 | stericsson,earpeice-cmv = <950>; /* Units in mV. */ | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/ux500-msp.txt b/Documentation/devicetree/bindings/sound/ux500-msp.txt deleted file mode 100644 index 99acd9c774e..00000000000 --- a/Documentation/devicetree/bindings/sound/ux500-msp.txt +++ /dev/null | |||
@@ -1,43 +0,0 @@ | |||
1 | * ux500 MSP (CPU-side Digital Audio Interface) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible :"stericsson,ux500-msp-i2s" | ||
5 | - reg : Physical base address and length of the device's registers. | ||
6 | |||
7 | Optional properties: | ||
8 | - interrupts : The interrupt output from the device. | ||
9 | - interrupt-parent : The parent interrupt controller. | ||
10 | - <name>-supply : Phandle to the regulator <name> supply | ||
11 | |||
12 | Example: | ||
13 | |||
14 | sound { | ||
15 | compatible = "stericsson,snd-soc-mop500"; | ||
16 | |||
17 | stericsson,platform-pcm-dma = <&pcm>; | ||
18 | stericsson,cpu-dai = <&msp1 &msp3>; | ||
19 | stericsson,audio-codec = <&codec>; | ||
20 | }; | ||
21 | |||
22 | pcm: ux500-pcm { | ||
23 | compatible = "stericsson,ux500-pcm"; | ||
24 | }; | ||
25 | |||
26 | msp1: msp@80124000 { | ||
27 | compatible = "stericsson,ux500-msp-i2s"; | ||
28 | reg = <0x80124000 0x1000>; | ||
29 | interrupts = <0 62 0x4>; | ||
30 | v-ape-supply = <&db8500_vape_reg>; | ||
31 | }; | ||
32 | |||
33 | msp3: msp@80125000 { | ||
34 | compatible = "stericsson,ux500-msp-i2s"; | ||
35 | reg = <0x80125000 0x1000>; | ||
36 | interrupts = <0 62 0x4>; | ||
37 | v-ape-supply = <&db8500_vape_reg>; | ||
38 | }; | ||
39 | |||
40 | codec: ab8500-codec { | ||
41 | compatible = "stericsson,ab8500-codec"; | ||
42 | stericsson,earpeice-cmv = <950>; /* Units in mV. */ | ||
43 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8510.txt b/Documentation/devicetree/bindings/sound/wm8510.txt deleted file mode 100644 index fa1a32b8557..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8510.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8510 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8510" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8510@1a { | ||
16 | compatible = "wlf,wm8510"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8523.txt b/Documentation/devicetree/bindings/sound/wm8523.txt deleted file mode 100644 index 04746186b28..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8523.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | WM8523 audio CODEC | ||
2 | |||
3 | This device supports I2C only. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "wlf,wm8523" | ||
8 | |||
9 | - reg : the I2C address of the device. | ||
10 | |||
11 | Example: | ||
12 | |||
13 | codec: wm8523@1a { | ||
14 | compatible = "wlf,wm8523"; | ||
15 | reg = <0x1a>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8580.txt b/Documentation/devicetree/bindings/sound/wm8580.txt deleted file mode 100644 index 7d9821f348d..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8580.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | WM8580 audio CODEC | ||
2 | |||
3 | This device supports I2C only. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "wlf,wm8580" | ||
8 | |||
9 | - reg : the I2C address of the device. | ||
10 | |||
11 | Example: | ||
12 | |||
13 | codec: wm8580@1a { | ||
14 | compatible = "wlf,wm8580"; | ||
15 | reg = <0x1a>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8711.txt b/Documentation/devicetree/bindings/sound/wm8711.txt deleted file mode 100644 index 8ed9998cd23..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8711.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8711 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8711" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8711@1a { | ||
16 | compatible = "wlf,wm8711"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8728.txt b/Documentation/devicetree/bindings/sound/wm8728.txt deleted file mode 100644 index a8b5c3668e6..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8728.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8728 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8728" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8728@1a { | ||
16 | compatible = "wlf,wm8728"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8731.txt b/Documentation/devicetree/bindings/sound/wm8731.txt deleted file mode 100644 index 15f70048469..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8731.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8731 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8731" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8731@1a { | ||
16 | compatible = "wlf,wm8731"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8737.txt b/Documentation/devicetree/bindings/sound/wm8737.txt deleted file mode 100644 index 4bc2cea3b14..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8737.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8737 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8737" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8737@1a { | ||
16 | compatible = "wlf,wm8737"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8741.txt b/Documentation/devicetree/bindings/sound/wm8741.txt deleted file mode 100644 index 74bda58c1bc..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8741.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8741 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8741" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8741@1a { | ||
16 | compatible = "wlf,wm8741"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8750.txt b/Documentation/devicetree/bindings/sound/wm8750.txt deleted file mode 100644 index 8db239fd5ec..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8750.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8750 and WM8987 audio CODECs | ||
2 | |||
3 | These devices support both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8750" or "wlf,wm8987" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8750@1a { | ||
16 | compatible = "wlf,wm8750"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8753.txt b/Documentation/devicetree/bindings/sound/wm8753.txt deleted file mode 100644 index e65277a0fb6..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8753.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8753 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8753" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8737@1a { | ||
16 | compatible = "wlf,wm8753"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8770.txt b/Documentation/devicetree/bindings/sound/wm8770.txt deleted file mode 100644 index 866e00ca150..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8770.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | WM8770 audio CODEC | ||
2 | |||
3 | This device supports SPI. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "wlf,wm8770" | ||
8 | |||
9 | - reg : the chip select number. | ||
10 | |||
11 | Example: | ||
12 | |||
13 | codec: wm8770@1 { | ||
14 | compatible = "wlf,wm8770"; | ||
15 | reg = <1>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8776.txt b/Documentation/devicetree/bindings/sound/wm8776.txt deleted file mode 100644 index 3b9ca49abc2..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8776.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8776 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8776" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8776@1a { | ||
16 | compatible = "wlf,wm8776"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8804.txt b/Documentation/devicetree/bindings/sound/wm8804.txt deleted file mode 100644 index 4d3a56f38ad..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8804.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM8804 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm8804" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8804@1a { | ||
16 | compatible = "wlf,wm8804"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8903.txt b/Documentation/devicetree/bindings/sound/wm8903.txt deleted file mode 100644 index f102cbc4269..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8903.txt +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | WM8903 audio CODEC | ||
2 | |||
3 | This device supports I2C only. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "wlf,wm8903" | ||
8 | |||
9 | - reg : the I2C address of the device. | ||
10 | |||
11 | - gpio-controller : Indicates this device is a GPIO controller. | ||
12 | |||
13 | - #gpio-cells : Should be two. The first cell is the pin number and the | ||
14 | second cell is used to specify optional parameters (currently unused). | ||
15 | |||
16 | Optional properties: | ||
17 | |||
18 | - interrupts : The interrupt line the codec is connected to. | ||
19 | |||
20 | - micdet-cfg : Default register value for R6 (Mic Bias). If absent, the | ||
21 | default is 0. | ||
22 | |||
23 | - micdet-delay : The debounce delay for microphone detection in mS. If | ||
24 | absent, the default is 100. | ||
25 | |||
26 | - gpio-cfg : A list of GPIO configuration register values. The list must | ||
27 | be 5 entries long. If absent, no configuration of these registers is | ||
28 | performed. If any entry has the value 0xffffffff, that GPIO's | ||
29 | configuration will not be modified. | ||
30 | |||
31 | Example: | ||
32 | |||
33 | codec: wm8903@1a { | ||
34 | compatible = "wlf,wm8903"; | ||
35 | reg = <0x1a>; | ||
36 | interrupts = < 347 >; | ||
37 | |||
38 | gpio-controller; | ||
39 | #gpio-cells = <2>; | ||
40 | |||
41 | micdet-cfg = <0>; | ||
42 | micdet-delay = <100>; | ||
43 | gpio-cfg = < | ||
44 | 0x0600 /* DMIC_LR, output */ | ||
45 | 0x0680 /* DMIC_DAT, input */ | ||
46 | 0x0000 /* GPIO, output, low */ | ||
47 | 0x0200 /* Interrupt, output */ | ||
48 | 0x01a0 /* BCLK, input, active high */ | ||
49 | >; | ||
50 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8994.txt b/Documentation/devicetree/bindings/sound/wm8994.txt deleted file mode 100644 index 7a7eb1e7bda..00000000000 --- a/Documentation/devicetree/bindings/sound/wm8994.txt +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | WM1811/WM8994/WM8958 audio CODEC | ||
2 | |||
3 | These devices support both I2C and SPI (configured with pin strapping | ||
4 | on the board). | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : "wlf,wm1811", "wlf,wm8994", "wlf,wm8958" | ||
9 | |||
10 | - reg : the I2C address of the device for I2C, the chip select | ||
11 | number for SPI. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | codec: wm8994@1a { | ||
16 | compatible = "wlf,wm8994"; | ||
17 | reg = <0x1a>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt index 4256a6df9b7..9841057d112 100644 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt | |||
@@ -17,6 +17,6 @@ ecspi@70010000 { | |||
17 | reg = <0x70010000 0x4000>; | 17 | reg = <0x70010000 0x4000>; |
18 | interrupts = <36>; | 18 | interrupts = <36>; |
19 | fsl,spi-num-chipselects = <2>; | 19 | fsl,spi-num-chipselects = <2>; |
20 | cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */ | 20 | cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */ |
21 | <&gpio3 25 0>; /* GPIO3_25 */ | 21 | <&gpio3 25 0>; /* GPIO4_25 */ |
22 | }; | 22 | }; |
diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.txt b/Documentation/devicetree/bindings/spi/mxs-spi.txt deleted file mode 100644 index e2e13957c2a..00000000000 --- a/Documentation/devicetree/bindings/spi/mxs-spi.txt +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | * Freescale MX233/MX28 SSP/SPI | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28" | ||
5 | - reg: Offset and length of the register set for the device | ||
6 | - interrupts: Should contain SSP interrupts (error irq first, dma irq second) | ||
7 | - fsl,ssp-dma-channel: APBX DMA channel for the SSP | ||
8 | |||
9 | Optional properties: | ||
10 | - clock-frequency : Input clock frequency to the SPI block in Hz. | ||
11 | Default is 160000000 Hz. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | ssp0: ssp@80010000 { | ||
16 | #address-cells = <1>; | ||
17 | #size-cells = <0>; | ||
18 | compatible = "fsl,imx28-spi"; | ||
19 | reg = <0x80010000 0x2000>; | ||
20 | interrupts = <96 82>; | ||
21 | fsl,ssp-dma-channel = <0>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt deleted file mode 100644 index 7b53da5cb75..00000000000 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | NVIDIA Tegra20 SFLASH controller. | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "nvidia,tegra20-sflash". | ||
5 | - reg: Should contain SFLASH registers location and length. | ||
6 | - interrupts: Should contain SFLASH interrupts. | ||
7 | - nvidia,dma-request-selector : The Tegra DMA controller's phandle and | ||
8 | request selector for this SFLASH controller. | ||
9 | |||
10 | Recommended properties: | ||
11 | - spi-max-frequency: Definition as per | ||
12 | Documentation/devicetree/bindings/spi/spi-bus.txt | ||
13 | |||
14 | Example: | ||
15 | |||
16 | spi@7000c380 { | ||
17 | compatible = "nvidia,tegra20-sflash"; | ||
18 | reg = <0x7000c380 0x80>; | ||
19 | interrupts = <0 39 0x04>; | ||
20 | nvidia,dma-request-selector = <&apbdma 16>; | ||
21 | spi-max-frequency = <25000000>; | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | status = "disabled"; | ||
25 | }; | ||
26 | |||
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt deleted file mode 100644 index eefe15e3d95..00000000000 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | NVIDIA Tegra20/Tegra30 SLINK controller. | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink". | ||
5 | - reg: Should contain SLINK registers location and length. | ||
6 | - interrupts: Should contain SLINK interrupts. | ||
7 | - nvidia,dma-request-selector : The Tegra DMA controller's phandle and | ||
8 | request selector for this SLINK controller. | ||
9 | |||
10 | Recommended properties: | ||
11 | - spi-max-frequency: Definition as per | ||
12 | Documentation/devicetree/bindings/spi/spi-bus.txt | ||
13 | |||
14 | Example: | ||
15 | |||
16 | spi@7000d600 { | ||
17 | compatible = "nvidia,tegra20-slink"; | ||
18 | reg = <0x7000d600 0x200>; | ||
19 | interrupts = <0 82 0x04>; | ||
20 | nvidia,dma-request-selector = <&apbdma 16>; | ||
21 | spi-max-frequency = <25000000>; | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | status = "disabled"; | ||
25 | }; | ||
26 | |||
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt deleted file mode 100644 index 6b9e5189669..00000000000 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt +++ /dev/null | |||
@@ -1,5 +0,0 @@ | |||
1 | NVIDIA Tegra 2 SPI device | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "nvidia,tegra20-spi". | ||
5 | - gpios : should specify GPIOs used for chipselect. | ||
diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt deleted file mode 100644 index 938809c6829..00000000000 --- a/Documentation/devicetree/bindings/spi/omap-spi.txt +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | OMAP2+ McSPI device | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : | ||
5 | - "ti,omap2-spi" for OMAP2 & OMAP3. | ||
6 | - "ti,omap4-spi" for OMAP4+. | ||
7 | - ti,spi-num-cs : Number of chipselect supported by the instance. | ||
8 | - ti,hwmods: Name of the hwmod associated to the McSPI | ||
9 | - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as | ||
10 | input. The default is D0 as input and | ||
11 | D1 as output. | ||
12 | |||
13 | Example: | ||
14 | |||
15 | mcspi1: mcspi@1 { | ||
16 | #address-cells = <1>; | ||
17 | #size-cells = <0>; | ||
18 | compatible = "ti,omap4-mcspi"; | ||
19 | ti,hwmods = "mcspi1"; | ||
20 | ti,spi-num-cs = <4>; | ||
21 | }; | ||
22 | |||
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index 296015e3c63..e782add2e45 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt | |||
@@ -12,7 +12,6 @@ The SPI master node requires the following properties: | |||
12 | - #size-cells - should be zero. | 12 | - #size-cells - should be zero. |
13 | - compatible - name of SPI bus controller following generic names | 13 | - compatible - name of SPI bus controller following generic names |
14 | recommended practice. | 14 | recommended practice. |
15 | - cs-gpios - (optional) gpios chip select. | ||
16 | No other properties are required in the SPI bus node. It is assumed | 15 | No other properties are required in the SPI bus node. It is assumed |
17 | that a driver for an SPI bus device will understand that it is an SPI bus. | 16 | that a driver for an SPI bus device will understand that it is an SPI bus. |
18 | However, the binding does not attempt to define the specific method for | 17 | However, the binding does not attempt to define the specific method for |
@@ -22,25 +21,6 @@ assumption that board specific platform code will be used to manage | |||
22 | chip selects. Individual drivers can define additional properties to | 21 | chip selects. Individual drivers can define additional properties to |
23 | support describing the chip select layout. | 22 | support describing the chip select layout. |
24 | 23 | ||
25 | Optional property: | ||
26 | - num-cs : total number of chipselects | ||
27 | |||
28 | If cs-gpios is used the number of chip select will automatically increased | ||
29 | with max(cs-gpios > hw cs) | ||
30 | |||
31 | So if for example the controller has 2 CS lines, and the cs-gpios | ||
32 | property looks like this: | ||
33 | |||
34 | cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; | ||
35 | |||
36 | Then it should be configured so that num_chipselect = 4 with the | ||
37 | following mapping: | ||
38 | |||
39 | cs0 : &gpio1 0 0 | ||
40 | cs1 : native | ||
41 | cs2 : &gpio1 1 0 | ||
42 | cs3 : &gpio1 2 0 | ||
43 | |||
44 | SPI slave nodes must be children of the SPI master node and can | 24 | SPI slave nodes must be children of the SPI master node and can |
45 | contain the following properties. | 25 | contain the following properties. |
46 | - reg - (required) chip select address of device. | 26 | - reg - (required) chip select address of device. |
@@ -53,11 +33,6 @@ contain the following properties. | |||
53 | shifted clock phase (CPHA) mode | 33 | shifted clock phase (CPHA) mode |
54 | - spi-cs-high - (optional) Empty property indicating device requires | 34 | - spi-cs-high - (optional) Empty property indicating device requires |
55 | chip select active high | 35 | chip select active high |
56 | - spi-3wire - (optional) Empty property indicating device requires | ||
57 | 3-wire mode. | ||
58 | |||
59 | If a gpio chipselect is used for the SPI slave the gpio number will be passed | ||
60 | via the cs_gpio | ||
61 | 36 | ||
62 | SPI example for an MPC5200 SPI bus: | 37 | SPI example for an MPC5200 SPI bus: |
63 | spi@f00 { | 38 | spi@f00 { |
diff --git a/Documentation/devicetree/bindings/spi/spi-gpio.txt b/Documentation/devicetree/bindings/spi/spi-gpio.txt deleted file mode 100644 index 8a824be1575..00000000000 --- a/Documentation/devicetree/bindings/spi/spi-gpio.txt +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | SPI-GPIO devicetree bindings | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible: should be set to "spi-gpio" | ||
6 | - #address-cells: should be set to <0x1> | ||
7 | - ranges | ||
8 | - gpio-sck: GPIO spec for the SCK line to use | ||
9 | - gpio-miso: GPIO spec for the MISO line to use | ||
10 | - gpio-mosi: GPIO spec for the MOSI line to use | ||
11 | - cs-gpios: GPIOs to use for chipselect lines | ||
12 | - num-chipselects: number of chipselect lines | ||
13 | |||
14 | Example: | ||
15 | |||
16 | spi { | ||
17 | compatible = "spi-gpio"; | ||
18 | #address-cells = <0x1>; | ||
19 | ranges; | ||
20 | |||
21 | gpio-sck = <&gpio 95 0>; | ||
22 | gpio-miso = <&gpio 98 0>; | ||
23 | gpio-mosi = <&gpio 97 0>; | ||
24 | cs-gpios = <&gpio 125 0>; | ||
25 | num-chipselects = <1>; | ||
26 | |||
27 | /* clients */ | ||
28 | }; | ||
29 | |||
diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt deleted file mode 100644 index 431add19234..00000000000 --- a/Documentation/devicetree/bindings/spi/spi-octeon.txt +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | Cavium, Inc. OCTEON SOC SPI master controller. | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "cavium,octeon-3010-spi" | ||
5 | - reg : The register base for the controller. | ||
6 | - interrupts : One interrupt, used by the controller. | ||
7 | - #address-cells : <1>, as required by generic SPI binding. | ||
8 | - #size-cells : <0>, also as required by generic SPI binding. | ||
9 | |||
10 | Child nodes as per the generic SPI binding. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | spi@1070000001000 { | ||
15 | compatible = "cavium,octeon-3010-spi"; | ||
16 | reg = <0x10700 0x00001000 0x0 0x100>; | ||
17 | interrupts = <0 58>; | ||
18 | #address-cells = <1>; | ||
19 | #size-cells = <0>; | ||
20 | |||
21 | eeprom@0 { | ||
22 | compatible = "st,m95256", "atmel,at25"; | ||
23 | reg = <0>; | ||
24 | spi-max-frequency = <5000000>; | ||
25 | spi-cpha; | ||
26 | spi-cpol; | ||
27 | |||
28 | pagesize = <64>; | ||
29 | size = <32768>; | ||
30 | address-width = <16>; | ||
31 | }; | ||
32 | }; | ||
33 | |||
diff --git a/Documentation/devicetree/bindings/spi/spi-orion.txt b/Documentation/devicetree/bindings/spi/spi-orion.txt deleted file mode 100644 index a3ff50fc76f..00000000000 --- a/Documentation/devicetree/bindings/spi/spi-orion.txt +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | Marvell Orion SPI device | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "marvell,orion-spi". | ||
5 | - reg : offset and length of the register set for the device | ||
6 | - cell-index : Which of multiple SPI controllers is this. | ||
7 | Optional properties: | ||
8 | - interrupts : Is currently not used. | ||
9 | |||
10 | Example: | ||
11 | spi@10600 { | ||
12 | compatible = "marvell,orion-spi"; | ||
13 | #address-cells = <1>; | ||
14 | #size-cells = <0>; | ||
15 | cell-index = <0>; | ||
16 | reg = <0x10600 0x28>; | ||
17 | interrupts = <23>; | ||
18 | status = "disabled"; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt deleted file mode 100644 index a15ffeddfba..00000000000 --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt +++ /dev/null | |||
@@ -1,116 +0,0 @@ | |||
1 | * Samsung SPI Controller | ||
2 | |||
3 | The Samsung SPI controller is used to interface with various devices such as flash | ||
4 | and display controllers using the SPI communication interface. | ||
5 | |||
6 | Required SoC Specific Properties: | ||
7 | |||
8 | - compatible: should be one of the following. | ||
9 | - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms | ||
10 | - samsung,s3c6410-spi: for s3c6410 platforms | ||
11 | - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms | ||
12 | - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms | ||
13 | - samsung,exynos4210-spi: for exynos4 and exynos5 platforms | ||
14 | |||
15 | - reg: physical base address of the controller and length of memory mapped | ||
16 | region. | ||
17 | |||
18 | - interrupts: The interrupt number to the cpu. The interrupt specifier format | ||
19 | depends on the interrupt controller. | ||
20 | |||
21 | [PRELIMINARY: the dma channel allocation will change once there are | ||
22 | official DMA bindings] | ||
23 | |||
24 | - tx-dma-channel: The dma channel specifier for tx operations. The format of | ||
25 | the dma specifier depends on the dma controller. | ||
26 | |||
27 | - rx-dma-channel: The dma channel specifier for rx operations. The format of | ||
28 | the dma specifier depends on the dma controller. | ||
29 | |||
30 | Required Board Specific Properties: | ||
31 | |||
32 | - #address-cells: should be 1. | ||
33 | - #size-cells: should be 0. | ||
34 | - gpios: The gpio specifier for clock, mosi and miso interface lines (in the | ||
35 | order specified). The format of the gpio specifier depends on the gpio | ||
36 | controller. | ||
37 | |||
38 | Optional Board Specific Properties: | ||
39 | |||
40 | - samsung,spi-src-clk: If the spi controller includes a internal clock mux to | ||
41 | select the clock source for the spi bus clock, this property can be used to | ||
42 | indicate the clock to be used for driving the spi bus clock. If not specified, | ||
43 | the clock number 0 is used as default. | ||
44 | |||
45 | - num-cs: Specifies the number of chip select lines supported. If | ||
46 | not specified, the default number of chip select lines is set to 1. | ||
47 | |||
48 | SPI Controller specific data in SPI slave nodes: | ||
49 | |||
50 | - The spi slave nodes should provide the following information which is required | ||
51 | by the spi controller. | ||
52 | |||
53 | - cs-gpio: A gpio specifier that specifies the gpio line used as | ||
54 | the slave select line by the spi controller. The format of the gpio | ||
55 | specifier depends on the gpio controller. | ||
56 | |||
57 | - samsung,spi-feedback-delay: The sampling phase shift to be applied on the | ||
58 | miso line (to account for any lag in the miso line). The following are the | ||
59 | valid values. | ||
60 | |||
61 | - 0: No phase shift. | ||
62 | - 1: 90 degree phase shift sampling. | ||
63 | - 2: 180 degree phase shift sampling. | ||
64 | - 3: 270 degree phase shift sampling. | ||
65 | |||
66 | Aliases: | ||
67 | |||
68 | - All the SPI controller nodes should be represented in the aliases node using | ||
69 | the following format 'spi{n}' where n is a unique number for the alias. | ||
70 | |||
71 | |||
72 | Example: | ||
73 | |||
74 | - SoC Specific Portion: | ||
75 | |||
76 | spi_0: spi@12d20000 { | ||
77 | compatible = "samsung,exynos4210-spi"; | ||
78 | reg = <0x12d20000 0x100>; | ||
79 | interrupts = <0 66 0>; | ||
80 | tx-dma-channel = <&pdma0 5>; | ||
81 | rx-dma-channel = <&pdma0 4>; | ||
82 | }; | ||
83 | |||
84 | - Board Specific Portion: | ||
85 | |||
86 | spi_0: spi@12d20000 { | ||
87 | #address-cells = <1>; | ||
88 | #size-cells = <0>; | ||
89 | gpios = <&gpa2 4 2 3 0>, | ||
90 | <&gpa2 6 2 3 0>, | ||
91 | <&gpa2 7 2 3 0>; | ||
92 | |||
93 | w25q80bw@0 { | ||
94 | #address-cells = <1>; | ||
95 | #size-cells = <1>; | ||
96 | compatible = "w25x80"; | ||
97 | reg = <0>; | ||
98 | spi-max-frequency = <10000>; | ||
99 | |||
100 | controller-data { | ||
101 | cs-gpio = <&gpa2 5 1 0 3>; | ||
102 | samsung,spi-feedback-delay = <0>; | ||
103 | }; | ||
104 | |||
105 | partition@0 { | ||
106 | label = "U-Boot"; | ||
107 | reg = <0x0 0x40000>; | ||
108 | read-only; | ||
109 | }; | ||
110 | |||
111 | partition@40000 { | ||
112 | label = "Kernel"; | ||
113 | reg = <0x40000 0xc0000>; | ||
114 | }; | ||
115 | }; | ||
116 | }; | ||
diff --git a/Documentation/devicetree/bindings/spi/spi-sc18is602.txt b/Documentation/devicetree/bindings/spi/spi-sc18is602.txt deleted file mode 100644 index 02f9033270a..00000000000 --- a/Documentation/devicetree/bindings/spi/spi-sc18is602.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | NXP SC18IS602/SCIS603 | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be one of | ||
5 | "nxp,sc18is602" | ||
6 | "nxp,sc18is602b" | ||
7 | "nxp,sc18is603" | ||
8 | - reg: I2C bus address | ||
9 | |||
10 | Optional properties: | ||
11 | - clock-frequency : external oscillator clock frequency. If not | ||
12 | specified, the SC18IS602 default frequency (7372000) will be used. | ||
13 | |||
14 | The clock-frequency property is relevant and needed only if the chip has an | ||
15 | external oscillator (SC18IS603). | ||
16 | |||
17 | Example: | ||
18 | |||
19 | sc18is603@28 { | ||
20 | compatible = "nxp,sc18is603"; | ||
21 | reg = <0x28>; | ||
22 | clock-frequency = <14744000>; | ||
23 | } | ||
diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt deleted file mode 100644 index 07e04cdc0c9..00000000000 --- a/Documentation/devicetree/bindings/spi/spi_atmel.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | Atmel SPI device | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "atmel,at91rm9200-spi". | ||
5 | - reg: Address and length of the register set for the device | ||
6 | - interrupts: Should contain spi interrupt | ||
7 | - cs-gpios: chipselects | ||
8 | |||
9 | Example: | ||
10 | |||
11 | spi1: spi@fffcc000 { | ||
12 | compatible = "atmel,at91rm9200-spi"; | ||
13 | reg = <0xfffcc000 0x4000>; | ||
14 | interrupts = <13 4 5>; | ||
15 | #address-cells = <1>; | ||
16 | #size-cells = <0>; | ||
17 | cs-gpios = <&pioB 3 0>; | ||
18 | status = "okay"; | ||
19 | |||
20 | mmc-slot@0 { | ||
21 | compatible = "mmc-spi-slot"; | ||
22 | reg = <0>; | ||
23 | gpios = <&pioC 4 0>; /* CD */ | ||
24 | spi-max-frequency = <25000000>; | ||
25 | }; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt deleted file mode 100644 index f158fd31cfd..00000000000 --- a/Documentation/devicetree/bindings/spi/spi_pl022.txt +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | ARM PL022 SPI controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "arm,pl022", "arm,primecell" | ||
5 | - reg : Offset and length of the register set for the device | ||
6 | - interrupts : Should contain SPI controller interrupt | ||
7 | |||
8 | Optional properties: | ||
9 | - num-cs : total number of chipselects | ||
10 | - cs-gpios : should specify GPIOs used for chipselects. | ||
11 | The gpios will be referred to as reg = <index> in the SPI child nodes. | ||
12 | If unspecified, a single SPI device without a chip select can be used. | ||
13 | - pl022,autosuspend-delay : delay in ms following transfer completion before | ||
14 | the runtime power management system suspends the | ||
15 | device. A setting of 0 indicates no delay and the | ||
16 | device will be suspended immediately | ||
17 | - pl022,rt : indicates the controller should run the message pump with realtime | ||
18 | priority to minimise the transfer latency on the bus (boolean) | ||
19 | |||
20 | |||
21 | SPI slave nodes must be children of the SPI master node and can | ||
22 | contain the following properties. | ||
23 | |||
24 | - pl022,interface : interface type: | ||
25 | 0: SPI | ||
26 | 1: Texas Instruments Synchronous Serial Frame Format | ||
27 | 2: Microwire (Half Duplex) | ||
28 | - pl022,com-mode : polling, interrupt or dma | ||
29 | - pl022,rx-level-trig : Rx FIFO watermark level | ||
30 | - pl022,tx-level-trig : Tx FIFO watermark level | ||
31 | - pl022,ctrl-len : Microwire interface: Control length | ||
32 | - pl022,wait-state : Microwire interface: Wait state | ||
33 | - pl022,duplex : Microwire interface: Full/Half duplex | ||
34 | |||
diff --git a/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt b/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt deleted file mode 100644 index b3629d3a9ad..00000000000 --- a/Documentation/devicetree/bindings/staging/iio/adc/lpc32xx-adc.txt +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | * NXP LPC32xx SoC ADC controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "nxp,lpc3220-adc" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: The ADC interrupt | ||
8 | |||
9 | Example: | ||
10 | |||
11 | adc@40048000 { | ||
12 | compatible = "nxp,lpc3220-adc"; | ||
13 | reg = <0x40048000 0x1000>; | ||
14 | interrupt-parent = <&mic>; | ||
15 | interrupts = <39 0>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt b/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt deleted file mode 100644 index 801d58cb6d4..00000000000 --- a/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | * Freescale i.MX28 LRADC device driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,imx28-lradc" | ||
5 | - reg: Address and length of the register set for the device | ||
6 | - interrupts: Should contain the LRADC interrupts | ||
7 | |||
8 | Examples: | ||
9 | |||
10 | lradc@80050000 { | ||
11 | compatible = "fsl,imx28-lradc"; | ||
12 | reg = <0x80050000 0x2000>; | ||
13 | interrupts = <10 14 15 16 17 18 19 | ||
14 | 20 21 22 23 24 25>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt b/Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt deleted file mode 100644 index 02ea23a63f2..00000000000 --- a/Documentation/devicetree/bindings/staging/iio/adc/spear-adc.txt +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | * ST SPEAr ADC device driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "st,spear600-adc" | ||
5 | - reg: Address and length of the register set for the device | ||
6 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
7 | that services interrupts for this device | ||
8 | - interrupts: Should contain the ADC interrupt | ||
9 | - sampling-frequency: Default sampling frequency | ||
10 | |||
11 | Optional properties: | ||
12 | - vref-external: External voltage reference in milli-volts. If omitted | ||
13 | the internal voltage reference will be used. | ||
14 | - average-samples: Number of samples to generate an average value. If | ||
15 | omitted, single data conversion will be used. | ||
16 | |||
17 | Examples: | ||
18 | |||
19 | adc: adc@d8200000 { | ||
20 | compatible = "st,spear600-adc"; | ||
21 | reg = <0xd8200000 0x1000>; | ||
22 | interrupt-parent = <&vic1>; | ||
23 | interrupts = <6>; | ||
24 | sampling-frequency = <5000000>; | ||
25 | vref-external = <2500>; /* 2.5V VRef */ | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt deleted file mode 100644 index 07654f0338b..00000000000 --- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | Freescale i.MX IPUv3 | ||
2 | ==================== | ||
3 | |||
4 | Required properties: | ||
5 | - compatible: Should be "fsl,<chip>-ipu" | ||
6 | - reg: should be register base and length as documented in the | ||
7 | datasheet | ||
8 | - interrupts: Should contain sync interrupt and error interrupt, | ||
9 | in this order. | ||
10 | - #crtc-cells: 1, See below | ||
11 | |||
12 | example: | ||
13 | |||
14 | ipu: ipu@18000000 { | ||
15 | #crtc-cells = <1>; | ||
16 | compatible = "fsl,imx53-ipu"; | ||
17 | reg = <0x18000000 0x080000000>; | ||
18 | interrupts = <11 10>; | ||
19 | }; | ||
20 | |||
21 | Parallel display support | ||
22 | ======================== | ||
23 | |||
24 | Required properties: | ||
25 | - compatible: Should be "fsl,imx-parallel-display" | ||
26 | - crtc: the crtc this display is connected to, see below | ||
27 | Optional properties: | ||
28 | - interface_pix_fmt: How this display is connected to the | ||
29 | crtc. Currently supported types: "rgb24", "rgb565" | ||
30 | - edid: verbatim EDID data block describing attached display. | ||
31 | - ddc: phandle describing the i2c bus handling the display data | ||
32 | channel | ||
33 | |||
34 | example: | ||
35 | |||
36 | display@di0 { | ||
37 | compatible = "fsl,imx-parallel-display"; | ||
38 | edid = [edid-data]; | ||
39 | crtc = <&ipu 0>; | ||
40 | interface-pix-fmt = "rgb24"; | ||
41 | }; | ||
diff --git a/Documentation/devicetree/bindings/thermal/db8500-thermal.txt b/Documentation/devicetree/bindings/thermal/db8500-thermal.txt deleted file mode 100644 index 2e1c06fad81..00000000000 --- a/Documentation/devicetree/bindings/thermal/db8500-thermal.txt +++ /dev/null | |||
@@ -1,44 +0,0 @@ | |||
1 | * ST-Ericsson DB8500 Thermal | ||
2 | |||
3 | ** Thermal node properties: | ||
4 | |||
5 | - compatible : "stericsson,db8500-thermal"; | ||
6 | - reg : address range of the thermal sensor registers; | ||
7 | - interrupts : interrupts generated from PRCMU; | ||
8 | - interrupt-names : "IRQ_HOTMON_LOW" and "IRQ_HOTMON_HIGH"; | ||
9 | - num-trips : number of total trip points, this is required, set it 0 if none, | ||
10 | if greater than 0, the following properties must be defined; | ||
11 | - tripN-temp : temperature of trip point N, should be in ascending order; | ||
12 | - tripN-type : type of trip point N, should be one of "active" "passive" "hot" | ||
13 | "critical"; | ||
14 | - tripN-cdev-num : number of the cooling devices which can be bound to trip | ||
15 | point N, this is required if trip point N is defined, set it 0 if none, | ||
16 | otherwise the following cooling device names must be defined; | ||
17 | - tripN-cdev-nameM : name of the No. M cooling device of trip point N; | ||
18 | |||
19 | Usually the num-trips and tripN-*** are separated in board related dts files. | ||
20 | |||
21 | Example: | ||
22 | thermal@801573c0 { | ||
23 | compatible = "stericsson,db8500-thermal"; | ||
24 | reg = <0x801573c0 0x40>; | ||
25 | interrupts = <21 0x4>, <22 0x4>; | ||
26 | interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; | ||
27 | |||
28 | num-trips = <3>; | ||
29 | |||
30 | trip0-temp = <75000>; | ||
31 | trip0-type = "active"; | ||
32 | trip0-cdev-num = <1>; | ||
33 | trip0-cdev-name0 = "thermal-cpufreq-0"; | ||
34 | |||
35 | trip1-temp = <80000>; | ||
36 | trip1-type = "active"; | ||
37 | trip1-cdev-num = <2>; | ||
38 | trip1-cdev-name0 = "thermal-cpufreq-0"; | ||
39 | trip1-cdev-name1 = "thermal-fan"; | ||
40 | |||
41 | trip2-temp = <85000>; | ||
42 | trip2-type = "critical"; | ||
43 | trip2-cdev-num = <0>; | ||
44 | } | ||
diff --git a/Documentation/devicetree/bindings/thermal/spear-thermal.txt b/Documentation/devicetree/bindings/thermal/spear-thermal.txt deleted file mode 100644 index 93e3b67c102..00000000000 --- a/Documentation/devicetree/bindings/thermal/spear-thermal.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * SPEAr Thermal | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "st,thermal-spear1340" | ||
5 | - reg : Address range of the thermal registers | ||
6 | - st,thermal-flags: flags used to enable thermal sensor | ||
7 | |||
8 | Example: | ||
9 | |||
10 | thermal@fc000000 { | ||
11 | compatible = "st,thermal-spear1340"; | ||
12 | reg = <0xfc000000 0x1000>; | ||
13 | st,thermal-flags = <0x7000>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt deleted file mode 100644 index 0c7b64e95a6..00000000000 --- a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | Allwinner A1X SoCs Timer Controller | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "allwinner,sunxi-timer" | ||
6 | - reg : Specifies base physical address and size of the registers. | ||
7 | - interrupts : The interrupt of the first timer | ||
8 | - clocks: phandle to the source clock (usually a 24 MHz fixed clock) | ||
9 | |||
10 | Example: | ||
11 | |||
12 | timer { | ||
13 | compatible = "allwinner,sunxi-timer"; | ||
14 | reg = <0x01c20c00 0x400>; | ||
15 | interrupts = <22>; | ||
16 | clocks = <&osc>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt b/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt deleted file mode 100644 index 844bd5fbd04..00000000000 --- a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | BCM2835 System Timer | ||
2 | |||
3 | The System Timer peripheral provides four 32-bit timer channels and a | ||
4 | single 64-bit free running counter. Each channel has an output compare | ||
5 | register, which is compared against the 32 least significant bits of the | ||
6 | free running counter values, and generates an interrupt. | ||
7 | |||
8 | Required properties: | ||
9 | |||
10 | - compatible : should be "brcm,bcm2835-system-timer" | ||
11 | - reg : Specifies base physical address and size of the registers. | ||
12 | - interrupts : A list of 4 interrupt sinks; one per timer channel. | ||
13 | - clock-frequency : The frequency of the clock that drives the counter, in Hz. | ||
14 | |||
15 | Example: | ||
16 | |||
17 | timer { | ||
18 | compatible = "brcm,bcm2835-system-timer"; | ||
19 | reg = <0x7e003000 0x1000>; | ||
20 | interrupts = <1 0>, <1 1>, <1 2>, <1 3>; | ||
21 | clock-frequency = <1000000>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt deleted file mode 100644 index e019fdc3877..00000000000 --- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | NVIDIA Tegra20 timer | ||
2 | |||
3 | The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free | ||
4 | running counter. The first two channels may also trigger a watchdog reset. | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible : should be "nvidia,tegra20-timer". | ||
9 | - reg : Specifies base physical address and size of the registers. | ||
10 | - interrupts : A list of 4 interrupts; one per timer channel. | ||
11 | |||
12 | Example: | ||
13 | |||
14 | timer { | ||
15 | compatible = "nvidia,tegra20-timer"; | ||
16 | reg = <0x60005000 0x60>; | ||
17 | interrupts = <0 0 0x04 | ||
18 | 0 1 0x04 | ||
19 | 0 41 0x04 | ||
20 | 0 42 0x04>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt deleted file mode 100644 index 906109d4c59..00000000000 --- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | NVIDIA Tegra30 timer | ||
2 | |||
3 | The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free | ||
4 | running counter, and 5 watchdog modules. The first two channels may also | ||
5 | trigger a legacy watchdog reset. | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer". | ||
10 | - reg : Specifies base physical address and size of the registers. | ||
11 | - interrupts : A list of 6 interrupts; one per each of timer channels 1 | ||
12 | through 5, and one for the shared interrupt for the remaining channels. | ||
13 | |||
14 | timer { | ||
15 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; | ||
16 | reg = <0x60005000 0x400>; | ||
17 | interrupts = <0 0 0x04 | ||
18 | 0 1 0x04 | ||
19 | 0 41 0x04 | ||
20 | 0 42 0x04 | ||
21 | 0 121 0x04 | ||
22 | 0 122 0x04>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt deleted file mode 100644 index a49d9a1d4cc..00000000000 --- a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "atmel,<chip>-usart" | ||
5 | The compatible <chip> indicated will be the first SoC to support an | ||
6 | additional mode or an USART new feature. | ||
7 | - reg: Should contain registers location and length | ||
8 | - interrupts: Should contain interrupt | ||
9 | |||
10 | Optional properties: | ||
11 | - atmel,use-dma-rx: use of PDC or DMA for receiving data | ||
12 | - atmel,use-dma-tx: use of PDC or DMA for transmitting data | ||
13 | |||
14 | <chip> compatible description: | ||
15 | - at91rm9200: legacy USART support | ||
16 | - at91sam9260: generic USART implementation for SAM9 SoCs | ||
17 | |||
18 | Example: | ||
19 | |||
20 | usart0: serial@fff8c000 { | ||
21 | compatible = "atmel,at91sam9260-usart"; | ||
22 | reg = <0xfff8c000 0x4000>; | ||
23 | interrupts = <7>; | ||
24 | atmel,use-dma-rx; | ||
25 | atmel,use-dma-tx; | ||
26 | }; | ||
27 | |||
diff --git a/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt b/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt deleted file mode 100644 index 6588b6950a7..00000000000 --- a/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * Energymicro efm32 UART | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "efm32,uart" | ||
5 | - reg : Address and length of the register set | ||
6 | - interrupts : Should contain uart interrupt | ||
7 | |||
8 | Example: | ||
9 | |||
10 | uart@0x4000c400 { | ||
11 | compatible = "efm32,uart"; | ||
12 | reg = <0x4000c400 0x400>; | ||
13 | interrupts = <15>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt index b462d0c5482..a9c0406280e 100644 --- a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt +++ b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt | |||
@@ -11,7 +11,7 @@ Optional properties: | |||
11 | 11 | ||
12 | Example: | 12 | Example: |
13 | 13 | ||
14 | serial@73fbc000 { | 14 | uart@73fbc000 { |
15 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; | 15 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
16 | reg = <0x73fbc000 0x4000>; | 16 | reg = <0x73fbc000 0x4000>; |
17 | interrupts = <31>; | 17 | interrupts = <31>; |
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt deleted file mode 100644 index 273a8d5b330..00000000000 --- a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | * Freescale MXS Application UART (AUART) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "fsl,<soc>-auart". The supported SoCs include | ||
5 | imx23 and imx28. | ||
6 | - reg : Address and length of the register set for the device | ||
7 | - interrupts : Should contain the auart interrupt numbers | ||
8 | |||
9 | Optional properties: | ||
10 | - fsl,auart-dma-channel : The DMA channels, the first is for RX, the other | ||
11 | is for TX. If you add this property, it also means that you | ||
12 | will enable the DMA support for the auart. | ||
13 | Note: due to the hardware bug in imx23(see errata : 2836), | ||
14 | only the imx28 can enable the DMA support for the auart. | ||
15 | |||
16 | Example: | ||
17 | auart0: serial@8006a000 { | ||
18 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | ||
19 | reg = <0x8006a000 0x2000>; | ||
20 | interrupts = <112 70 71>; | ||
21 | fsl,auart-dma-channel = <8 9>; | ||
22 | }; | ||
23 | |||
24 | Note: Each auart port should have an alias correctly numbered in "aliases" | ||
25 | node. | ||
26 | |||
27 | Example: | ||
28 | |||
29 | aliases { | ||
30 | serial0 = &auart0; | ||
31 | serial1 = &auart1; | ||
32 | serial2 = &auart2; | ||
33 | serial3 = &auart3; | ||
34 | serial4 = &auart4; | ||
35 | }; | ||
diff --git a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt deleted file mode 100644 index aef383eb887..00000000000 --- a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | * Qualcomm MSM UART | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : | ||
5 | - "qcom,msm-uart", and one of "qcom,msm-hsuart" or | ||
6 | "qcom,msm-lsuart". | ||
7 | - reg : offset and length of the register set for the device | ||
8 | for the hsuart operating in compatible mode, there should be a | ||
9 | second pair describing the gsbi registers. | ||
10 | - interrupts : should contain the uart interrupt. | ||
11 | |||
12 | There are two different UART blocks used in MSM devices, | ||
13 | "qcom,msm-hsuart" and "qcom,msm-lsuart". The msm-serial driver is | ||
14 | able to handle both of these, and matches against the "qcom,msm-uart" | ||
15 | as the compatibility. | ||
16 | |||
17 | The registers for the "qcom,msm-hsuart" device need to specify both | ||
18 | register blocks, even for the common driver. | ||
19 | |||
20 | Example: | ||
21 | |||
22 | uart@19c400000 { | ||
23 | compatible = "qcom,msm-hsuart", "qcom,msm-uart"; | ||
24 | reg = <0x19c40000 0x1000>, | ||
25 | <0x19c00000 0x1000>; | ||
26 | interrupts = <195>; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt b/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt deleted file mode 100644 index 0d439dfc1aa..00000000000 --- a/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * NXP LPC32xx SoC High Speed UART | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "nxp,lpc3220-hsuart" | ||
5 | - reg: Should contain registers location and length | ||
6 | - interrupts: Should contain interrupt | ||
7 | |||
8 | Example: | ||
9 | |||
10 | uart1: serial@40014000 { | ||
11 | compatible = "nxp,lpc3220-hsuart"; | ||
12 | reg = <0x40014000 0x1000>; | ||
13 | interrupts = <26 0>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/Documentation/devicetree/bindings/tty/serial/of-serial.txt index 1e1145ca4f3..b8b27b0aca1 100644 --- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt +++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt | |||
@@ -9,15 +9,11 @@ Required properties: | |||
9 | - "ns16750" | 9 | - "ns16750" |
10 | - "ns16850" | 10 | - "ns16850" |
11 | - "nvidia,tegra20-uart" | 11 | - "nvidia,tegra20-uart" |
12 | - "nxp,lpc3220-uart" | ||
13 | - "ibm,qpace-nwp-serial" | 12 | - "ibm,qpace-nwp-serial" |
14 | - "serial" if the port type is unknown. | 13 | - "serial" if the port type is unknown. |
15 | - reg : offset and length of the register set for the device. | 14 | - reg : offset and length of the register set for the device. |
16 | - interrupts : should contain uart interrupt. | 15 | - interrupts : should contain uart interrupt. |
17 | - clock-frequency : the input clock frequency for the UART | 16 | - clock-frequency : the input clock frequency for the UART. |
18 | or | ||
19 | clocks phandle to refer to the clk used as per Documentation/devicetree | ||
20 | /bindings/clock/clock-bindings.txt | ||
21 | 17 | ||
22 | Optional properties: | 18 | Optional properties: |
23 | - current-speed : the current active speed of the UART. | 19 | - current-speed : the current active speed of the UART. |
@@ -28,8 +24,6 @@ Optional properties: | |||
28 | accesses to the UART (e.g. TI davinci). | 24 | accesses to the UART (e.g. TI davinci). |
29 | - used-by-rtas : set to indicate that the port is in use by the OpenFirmware | 25 | - used-by-rtas : set to indicate that the port is in use by the OpenFirmware |
30 | RTAS and should not be registered. | 26 | RTAS and should not be registered. |
31 | - no-loopback-test: set to indicate that the port does not implements loopback | ||
32 | test mode | ||
33 | 27 | ||
34 | Example: | 28 | Example: |
35 | 29 | ||
diff --git a/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt deleted file mode 100644 index f13f1c5be91..00000000000 --- a/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * Synopsys DesignWare ABP UART | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "snps,dw-apb-uart" | ||
5 | - reg : offset and length of the register set for the device. | ||
6 | - interrupts : should contain uart interrupt. | ||
7 | - clock-frequency : the input clock frequency for the UART. | ||
8 | |||
9 | Optional properties: | ||
10 | - reg-shift : quantity to shift the register offsets by. If this property is | ||
11 | not present then the register offsets are not shifted. | ||
12 | - reg-io-width : the size (in bytes) of the IO accesses that should be | ||
13 | performed on the device. If this property is not present then single byte | ||
14 | accesses are used. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | uart@80230000 { | ||
19 | compatible = "snps,dw-apb-uart"; | ||
20 | reg = <0x80230000 0x100>; | ||
21 | clock-frequency = <3686400>; | ||
22 | interrupts = <10>; | ||
23 | reg-shift = <2>; | ||
24 | reg-io-width = <4>; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt deleted file mode 100644 index 5feef1ef167..00000000000 --- a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500 UART Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "via,vt8500-uart" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | - interrupts : UART interrupt | ||
8 | - clocks : phandle to the uart source clock (usually a 24Mhz fixed clock) | ||
9 | |||
10 | Example: | ||
11 | |||
12 | uart@d8210000 { | ||
13 | compatible = "via,vt8500-uart"; | ||
14 | reg = <0xd8210000 0x1040>; | ||
15 | interrupts = <47>; | ||
16 | clocks = <&ref24>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt deleted file mode 100644 index ea840f7f925..00000000000 --- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | AM33XX MUSB GLUE | ||
2 | - compatible : Should be "ti,musb-am33xx" | ||
3 | - reg : offset and length of register sets, first usbss, then for musb instances | ||
4 | - interrupts : usbss, musb instance interrupts in order | ||
5 | - ti,hwmods : must be "usb_otg_hs" | ||
6 | - multipoint : Should be "1" indicating the musb controller supports | ||
7 | multipoint. This is a MUSB configuration-specific setting. | ||
8 | - num-eps : Specifies the number of endpoints. This is also a | ||
9 | MUSB configuration-specific setting. Should be set to "16" | ||
10 | - ram-bits : Specifies the ram address size. Should be set to "12" | ||
11 | - port0-mode : Should be "3" to represent OTG. "1" signifies HOST and "2" | ||
12 | represents PERIPHERAL. | ||
13 | - port1-mode : Should be "1" to represent HOST. "3" signifies OTG and "2" | ||
14 | represents PERIPHERAL. | ||
15 | - power : Should be "250". This signifies the controller can supply upto | ||
16 | 500mA when operating in host mode. | ||
17 | |||
18 | Example: | ||
19 | |||
20 | usb@47400000 { | ||
21 | compatible = "ti,musb-am33xx"; | ||
22 | reg = <0x47400000 0x1000 /* usbss */ | ||
23 | 0x47401000 0x800 /* musb instance 0 */ | ||
24 | 0x47401800 0x800>; /* musb instance 1 */ | ||
25 | interrupts = <17 /* usbss */ | ||
26 | 18 /* musb instance 0 */ | ||
27 | 19>; /* musb instance 1 */ | ||
28 | multipoint = <1>; | ||
29 | num-eps = <16>; | ||
30 | ram-bits = <12>; | ||
31 | port0-mode = <3>; | ||
32 | port1-mode = <3>; | ||
33 | power = <250>; | ||
34 | ti,hwmods = "usb_otg_hs"; | ||
35 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt deleted file mode 100644 index 60bd2150a3e..00000000000 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | Atmel SOC USB controllers | ||
2 | |||
3 | OHCI | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers | ||
7 | used in host mode. | ||
8 | - num-ports: Number of ports. | ||
9 | - atmel,vbus-gpio: If present, specifies a gpio that needs to be | ||
10 | activated for the bus to be powered. | ||
11 | - atmel,oc-gpio: If present, specifies a gpio that needs to be | ||
12 | activated for the overcurrent detection. | ||
13 | |||
14 | usb0: ohci@00500000 { | ||
15 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | ||
16 | reg = <0x00500000 0x100000>; | ||
17 | interrupts = <20 4>; | ||
18 | num-ports = <2>; | ||
19 | }; | ||
20 | |||
21 | EHCI | ||
22 | |||
23 | Required properties: | ||
24 | - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers | ||
25 | used in host mode. | ||
26 | |||
27 | usb1: ehci@00800000 { | ||
28 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | ||
29 | reg = <0x00800000 0x100000>; | ||
30 | interrupts = <22 4>; | ||
31 | }; | ||
32 | |||
33 | AT91 USB device controller | ||
34 | |||
35 | Required properties: | ||
36 | - compatible: Should be "atmel,at91rm9200-udc" | ||
37 | - reg: Address and length of the register set for the device | ||
38 | - interrupts: Should contain macb interrupt | ||
39 | |||
40 | Optional properties: | ||
41 | - atmel,vbus-gpio: If present, specifies a gpio that needs to be | ||
42 | activated for the bus to be powered. | ||
43 | |||
44 | usb1: gadget@fffa4000 { | ||
45 | compatible = "atmel,at91rm9200-udc"; | ||
46 | reg = <0xfffa4000 0x4000>; | ||
47 | interrupts = <10 4>; | ||
48 | atmel,vbus-gpio = <&pioC 5 0>; | ||
49 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt deleted file mode 100644 index 5778b9c83bd..00000000000 --- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | * Freescale i.MX ci13xxx usb controllers | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,imx27-usb" | ||
5 | - reg: Should contain registers location and length | ||
6 | - interrupts: Should contain controller interrupt | ||
7 | |||
8 | Optional properties: | ||
9 | - fsl,usbphy: phandler of usb phy that connects to the only one port | ||
10 | - fsl,usbmisc: phandler of non-core register device, with one argument | ||
11 | that indicate usb controller index | ||
12 | - vbus-supply: regulator for vbus | ||
13 | - disable-over-current: disable over current detect | ||
14 | |||
15 | Examples: | ||
16 | usb@02184000 { /* USB OTG */ | ||
17 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | ||
18 | reg = <0x02184000 0x200>; | ||
19 | interrupts = <0 43 0x04>; | ||
20 | fsl,usbphy = <&usbphy1>; | ||
21 | fsl,usbmisc = <&usbmisc 0>; | ||
22 | disable-over-current; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt deleted file mode 100644 index 6bc09ec14c4..00000000000 --- a/Documentation/devicetree/bindings/usb/ehci-orion.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | * EHCI controller, Orion Marvell variants | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "marvell,orion-ehci" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: The EHCI interrupt | ||
8 | |||
9 | Example: | ||
10 | |||
11 | ehci@50000 { | ||
12 | compatible = "marvell,orion-ehci"; | ||
13 | reg = <0x50000 0x1000>; | ||
14 | interrupts = <19>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/isp1301.txt b/Documentation/devicetree/bindings/usb/isp1301.txt deleted file mode 100644 index 5405d99d9aa..00000000000 --- a/Documentation/devicetree/bindings/usb/isp1301.txt +++ /dev/null | |||
@@ -1,25 +0,0 @@ | |||
1 | * NXP ISP1301 USB transceiver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "nxp,isp1301" | ||
5 | - reg: I2C address of the ISP1301 device | ||
6 | |||
7 | Optional properties of devices using ISP1301: | ||
8 | - transceiver: phandle of isp1301 - this helps the ISP1301 driver to find the | ||
9 | ISP1301 instance associated with the respective USB driver | ||
10 | |||
11 | Example: | ||
12 | |||
13 | isp1301: usb-transceiver@2c { | ||
14 | compatible = "nxp,isp1301"; | ||
15 | reg = <0x2c>; | ||
16 | }; | ||
17 | |||
18 | usbd@31020000 { | ||
19 | compatible = "nxp,lpc3220-udc"; | ||
20 | reg = <0x31020000 0x300>; | ||
21 | interrupt-parent = <&mic>; | ||
22 | interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; | ||
23 | transceiver = <&isp1301>; | ||
24 | status = "okay"; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/lpc32xx-udc.txt b/Documentation/devicetree/bindings/usb/lpc32xx-udc.txt deleted file mode 100644 index 29f12a533f6..00000000000 --- a/Documentation/devicetree/bindings/usb/lpc32xx-udc.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | * NXP LPC32xx SoC USB Device Controller (UDC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "nxp,lpc3220-udc" | ||
5 | - reg: Physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: The USB interrupts: | ||
8 | * USB Device Low Priority Interrupt | ||
9 | * USB Device High Priority Interrupt | ||
10 | * USB Device DMA Interrupt | ||
11 | * External USB Transceiver Interrupt (OTG ATX) | ||
12 | - transceiver: phandle of the associated ISP1301 device - this is necessary for | ||
13 | the UDC controller for connecting to the USB physical layer | ||
14 | |||
15 | Example: | ||
16 | |||
17 | isp1301: usb-transceiver@2c { | ||
18 | compatible = "nxp,isp1301"; | ||
19 | reg = <0x2c>; | ||
20 | }; | ||
21 | |||
22 | usbd@31020000 { | ||
23 | compatible = "nxp,lpc3220-udc"; | ||
24 | reg = <0x31020000 0x300>; | ||
25 | interrupt-parent = <&mic>; | ||
26 | interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; | ||
27 | transceiver = <&isp1301>; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/mxs-phy.txt b/Documentation/devicetree/bindings/usb/mxs-phy.txt deleted file mode 100644 index 5835b27146e..00000000000 --- a/Documentation/devicetree/bindings/usb/mxs-phy.txt +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | * Freescale MXS USB Phy Device | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,imx23-usbphy" | ||
5 | - reg: Should contain registers location and length | ||
6 | - interrupts: Should contain phy interrupt | ||
7 | |||
8 | Example: | ||
9 | usbphy1: usbphy@020c9000 { | ||
10 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | ||
11 | reg = <0x020c9000 0x1000>; | ||
12 | interrupts = <0 44 0x04>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt deleted file mode 100644 index e9b005dc762..00000000000 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | Tegra SOC USB controllers | ||
2 | |||
3 | The device node for a USB controller that is part of a Tegra | ||
4 | SOC is as described in the document "Open Firmware Recommended | ||
5 | Practice : Universal Serial Bus" with the following modifications | ||
6 | and additions : | ||
7 | |||
8 | Required properties : | ||
9 | - compatible : Should be "nvidia,tegra20-ehci" for USB controllers | ||
10 | used in host mode. | ||
11 | - phy_type : Should be one of "ulpi" or "utmi". | ||
12 | - nvidia,vbus-gpio : If present, specifies a gpio that needs to be | ||
13 | activated for the bus to be powered. | ||
14 | |||
15 | Required properties for phy_type == ulpi: | ||
16 | - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. | ||
17 | |||
18 | Optional properties: | ||
19 | - dr_mode : dual role mode. Indicates the working mode for | ||
20 | nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", | ||
21 | or "otg". Default to "host" if not defined for backward compatibility. | ||
22 | host means this is a host controller | ||
23 | peripheral means it is device controller | ||
24 | otg means it can operate as either ("on the go") | ||
25 | - nvidia,has-legacy-mode : boolean indicates whether this controller can | ||
26 | operate in legacy mode (as APX 2500 / 2600). In legacy mode some | ||
27 | registers are accessed through the APB_MISC base address instead of | ||
28 | the USB controller. Since this is a legacy issue it probably does not | ||
29 | warrant a compatible string of its own. | ||
diff --git a/Documentation/devicetree/bindings/usb/ohci-nxp.txt b/Documentation/devicetree/bindings/usb/ohci-nxp.txt deleted file mode 100644 index 71e28c1017e..00000000000 --- a/Documentation/devicetree/bindings/usb/ohci-nxp.txt +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | * OHCI controller, NXP ohci-nxp variant | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "nxp,ohci-nxp" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: The OHCI interrupt | ||
8 | - transceiver: phandle of the associated ISP1301 device - this is necessary for | ||
9 | the UDC controller for connecting to the USB physical layer | ||
10 | |||
11 | Example (LPC32xx): | ||
12 | |||
13 | isp1301: usb-transceiver@2c { | ||
14 | compatible = "nxp,isp1301"; | ||
15 | reg = <0x2c>; | ||
16 | }; | ||
17 | |||
18 | ohci@31020000 { | ||
19 | compatible = "nxp,ohci-nxp"; | ||
20 | reg = <0x31020000 0x300>; | ||
21 | interrupt-parent = <&mic>; | ||
22 | interrupts = <0x3b 0>; | ||
23 | transceiver = <&isp1301>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt deleted file mode 100644 index 29a043ecda5..00000000000 --- a/Documentation/devicetree/bindings/usb/omap-usb.txt +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | OMAP GLUE | ||
2 | |||
3 | OMAP MUSB GLUE | ||
4 | - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb" | ||
5 | - ti,hwmods : must be "usb_otg_hs" | ||
6 | - multipoint : Should be "1" indicating the musb controller supports | ||
7 | multipoint. This is a MUSB configuration-specific setting. | ||
8 | - num_eps : Specifies the number of endpoints. This is also a | ||
9 | MUSB configuration-specific setting. Should be set to "16" | ||
10 | - ram_bits : Specifies the ram address size. Should be set to "12" | ||
11 | - interface_type : This is a board specific setting to describe the type of | ||
12 | interface between the controller and the phy. It should be "0" or "1" | ||
13 | specifying ULPI and UTMI respectively. | ||
14 | - mode : Should be "3" to represent OTG. "1" signifies HOST and "2" | ||
15 | represents PERIPHERAL. | ||
16 | - power : Should be "50". This signifies the controller can supply upto | ||
17 | 100mA when operating in host mode. | ||
18 | |||
19 | SOC specific device node entry | ||
20 | usb_otg_hs: usb_otg_hs@4a0ab000 { | ||
21 | compatible = "ti,omap4-musb"; | ||
22 | ti,hwmods = "usb_otg_hs"; | ||
23 | multipoint = <1>; | ||
24 | num_eps = <16>; | ||
25 | ram_bits = <12>; | ||
26 | }; | ||
27 | |||
28 | Board specific device node entry | ||
29 | &usb_otg_hs { | ||
30 | interface_type = <1>; | ||
31 | mode = <3>; | ||
32 | power = <50>; | ||
33 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/platform-uhci.txt deleted file mode 100644 index a4fb0719d15..00000000000 --- a/Documentation/devicetree/bindings/usb/platform-uhci.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | Generic Platform UHCI Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "platform-uhci" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | - interrupts : UHCI controller interrupt | ||
8 | |||
9 | Example: | ||
10 | |||
11 | uhci@d8007b00 { | ||
12 | compatible = "platform-uhci"; | ||
13 | reg = <0xd8007b00 0x200>; | ||
14 | interrupts = <43>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/pxa-usb.txt b/Documentation/devicetree/bindings/usb/pxa-usb.txt deleted file mode 100644 index 79729a948d5..00000000000 --- a/Documentation/devicetree/bindings/usb/pxa-usb.txt +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | PXA USB controllers | ||
2 | |||
3 | OHCI | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: Should be "marvell,pxa-ohci" for USB controllers | ||
7 | used in host mode. | ||
8 | |||
9 | Optional properties: | ||
10 | - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3" | ||
11 | If present, enables the appropriate USB port of the controller. | ||
12 | - "marvell,port-mode" selects the mode of the ports: | ||
13 | 1 = PMM_NPS_MODE | ||
14 | 2 = PMM_GLOBAL_MODE | ||
15 | 3 = PMM_PERPORT_MODE | ||
16 | - "marvell,power-sense-low" - power sense pin is low-active. | ||
17 | - "marvell,power-control-low" - power control pin is low-active. | ||
18 | - "marvell,no-oc-protection" - disable over-current protection. | ||
19 | - "marvell,oc-mode-perport" - enable per-port over-current protection. | ||
20 | - "marvell,power_on_delay" Power On to Power Good time - in ms. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | usb0: ohci@4c000000 { | ||
25 | compatible = "marvell,pxa-ohci", "usb-ohci"; | ||
26 | reg = <0x4c000000 0x100000>; | ||
27 | interrupts = <18>; | ||
28 | marvell,enable-port1; | ||
29 | marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ | ||
30 | }; | ||
31 | |||
diff --git a/Documentation/devicetree/bindings/usb/spear-usb.txt b/Documentation/devicetree/bindings/usb/spear-usb.txt deleted file mode 100644 index f8a464a2565..00000000000 --- a/Documentation/devicetree/bindings/usb/spear-usb.txt +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | ST SPEAr SoC USB controllers: | ||
2 | ----------------------------- | ||
3 | |||
4 | EHCI: | ||
5 | ----- | ||
6 | |||
7 | Required properties: | ||
8 | - compatible: "st,spear600-ehci" | ||
9 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
10 | that services interrupts for this device | ||
11 | - interrupts: Should contain the EHCI interrupt | ||
12 | |||
13 | Example: | ||
14 | |||
15 | ehci@e1800000 { | ||
16 | compatible = "st,spear600-ehci", "usb-ehci"; | ||
17 | reg = <0xe1800000 0x1000>; | ||
18 | interrupt-parent = <&vic1>; | ||
19 | interrupts = <27>; | ||
20 | }; | ||
21 | |||
22 | |||
23 | OHCI: | ||
24 | ----- | ||
25 | |||
26 | Required properties: | ||
27 | - compatible: "st,spear600-ohci" | ||
28 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
29 | that services interrupts for this device | ||
30 | - interrupts: Should contain the OHCI interrupt | ||
31 | |||
32 | Example: | ||
33 | |||
34 | ohci@e1900000 { | ||
35 | compatible = "st,spear600-ohci", "usb-ohci"; | ||
36 | reg = <0xe1800000 0x1000>; | ||
37 | interrupt-parent = <&vic1>; | ||
38 | interrupts = <26>; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt b/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt deleted file mode 100644 index 36b9aede3f4..00000000000 --- a/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | USB COMPARATOR OF TWL CHIPS | ||
2 | |||
3 | TWL6030 USB COMPARATOR | ||
4 | - compatible : Should be "ti,twl6030-usb" | ||
5 | - interrupts : Two interrupt numbers to the cpu should be specified. First | ||
6 | interrupt number is the otg interrupt number that raises ID interrupts when | ||
7 | the controller has to act as host and the second interrupt number is the | ||
8 | usb interrupt number that raises VBUS interrupts when the controller has to | ||
9 | act as device | ||
10 | - usb-supply : phandle to the regulator device tree node. It should be vusb | ||
11 | if it is twl6030 or ldousb if it is twl6025 subclass. | ||
12 | |||
13 | twl6030-usb { | ||
14 | compatible = "ti,twl6030-usb"; | ||
15 | interrupts = < 4 10 >; | ||
16 | }; | ||
17 | |||
18 | Board specific device node entry | ||
19 | &twl6030-usb { | ||
20 | usb-supply = <&vusb>; | ||
21 | }; | ||
22 | |||
23 | TWL4030 USB PHY AND COMPARATOR | ||
24 | - compatible : Should be "ti,twl4030-usb" | ||
25 | - interrupts : The interrupt numbers to the cpu should be specified. First | ||
26 | interrupt number is the otg interrupt number that raises ID interrupts | ||
27 | and VBUS interrupts. The second interrupt number is optional. | ||
28 | - <supply-name>-supply : phandle to the regulator device tree node. | ||
29 | <supply-name> should be vusb1v5, vusb1v8 and vusb3v1 | ||
30 | - usb_mode : The mode used by the phy to connect to the controller. "1" | ||
31 | specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode. | ||
32 | |||
33 | twl4030-usb { | ||
34 | compatible = "ti,twl4030-usb"; | ||
35 | interrupts = < 10 4 >; | ||
36 | usb1v5-supply = <&vusb1v5>; | ||
37 | usb1v8-supply = <&vusb1v8>; | ||
38 | usb3v1-supply = <&vusb3v1>; | ||
39 | usb_mode = <1>; | ||
40 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt b/Documentation/devicetree/bindings/usb/usb-phy.txt deleted file mode 100644 index 80d4148cb66..00000000000 --- a/Documentation/devicetree/bindings/usb/usb-phy.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | USB PHY | ||
2 | |||
3 | OMAP USB2 PHY | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: Should be "ti,omap-usb2" | ||
7 | - reg : Address and length of the register set for the device. Also | ||
8 | add the address of control module dev conf register until a driver for | ||
9 | control module is added | ||
10 | |||
11 | This is usually a subnode of ocp2scp to which it is connected. | ||
12 | |||
13 | usb2phy@4a0ad080 { | ||
14 | compatible = "ti,omap-usb2"; | ||
15 | reg = <0x4a0ad080 0x58>, | ||
16 | <0x4a002300 0x4>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt deleted file mode 100644 index 97ce94e1a6c..00000000000 --- a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * Freescale i.MX non-core registers | ||
2 | |||
3 | Required properties: | ||
4 | - #index-cells: Cells used to descibe usb controller index. Should be <1> | ||
5 | - compatible: Should be one of below: | ||
6 | "fsl,imx6q-usbmisc" for imx6q | ||
7 | - reg: Should contain registers location and length | ||
8 | |||
9 | Examples: | ||
10 | usbmisc@02184800 { | ||
11 | #index-cells = <1>; | ||
12 | compatible = "fsl,imx6q-usbmisc"; | ||
13 | reg = <0x02184800 0x200>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt deleted file mode 100644 index 17b3ad1d97e..00000000000 --- a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500 EHCI Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "via,vt8500-ehci" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | - interrupts : ehci controller interrupt | ||
8 | |||
9 | Example: | ||
10 | |||
11 | ehci@d8007900 { | ||
12 | compatible = "via,vt8500-ehci"; | ||
13 | reg = <0xd8007900 0x200>; | ||
14 | interrupts = <43>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/vt8500-ehci.txt deleted file mode 100644 index 5fb8fd6e250..00000000000 --- a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | VIA VT8500 and Wondermedia WM8xxx SoC USB controllers. | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci". | ||
5 | - reg: Address range of the ehci registers. size should be 0x200 | ||
6 | - interrupts: Should contain the ehci interrupt. | ||
7 | |||
8 | usb: ehci@D8007100 { | ||
9 | compatible = "wm,prizm-ehci", "usb-ehci"; | ||
10 | reg = <0xD8007100 0x200>; | ||
11 | interrupts = <1>; | ||
12 | }; | ||
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt deleted file mode 100644 index 902b1b1f568..00000000000 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ /dev/null | |||
@@ -1,59 +0,0 @@ | |||
1 | Device tree binding vendor prefix registry. Keep list in alphabetical order. | ||
2 | |||
3 | This isn't an exhaustive list, but you should add new prefixes to it before | ||
4 | using them to avoid name-space collisions. | ||
5 | |||
6 | ad Avionic Design GmbH | ||
7 | adi Analog Devices, Inc. | ||
8 | ak Asahi Kasei Corp. | ||
9 | amcc Applied Micro Circuits Corporation (APM, formally AMCC) | ||
10 | apm Applied Micro Circuits Corporation (APM) | ||
11 | arm ARM Ltd. | ||
12 | atmel Atmel Corporation | ||
13 | bosch Bosch Sensortec GmbH | ||
14 | brcm Broadcom Corporation | ||
15 | cavium Cavium, Inc. | ||
16 | chrp Common Hardware Reference Platform | ||
17 | cortina Cortina Systems, Inc. | ||
18 | dallas Maxim Integrated Products (formerly Dallas Semiconductor) | ||
19 | denx Denx Software Engineering | ||
20 | emmicro EM Microelectronic | ||
21 | epson Seiko Epson Corp. | ||
22 | est ESTeem Wireless Modems | ||
23 | fsl Freescale Semiconductor | ||
24 | GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. | ||
25 | gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. | ||
26 | hp Hewlett Packard | ||
27 | ibm International Business Machines (IBM) | ||
28 | idt Integrated Device Technologies, Inc. | ||
29 | img Imagination Technologies Ltd. | ||
30 | intercontrol Inter Control Group | ||
31 | linux Linux-specific binding | ||
32 | marvell Marvell Technology Group Ltd. | ||
33 | maxim Maxim Integrated Products | ||
34 | mosaixtech Mosaix Technologies, Inc. | ||
35 | national National Semiconductor | ||
36 | nintendo Nintendo | ||
37 | nvidia NVIDIA | ||
38 | nxp NXP Semiconductors | ||
39 | onnn ON Semiconductor Corp. | ||
40 | picochip Picochip Ltd | ||
41 | powervr PowerVR (deprecated, use img) | ||
42 | qcom Qualcomm, Inc. | ||
43 | ramtron Ramtron International | ||
44 | realtek Realtek Semiconductor Corp. | ||
45 | samsung Samsung Semiconductor | ||
46 | sbs Smart Battery System | ||
47 | schindler Schindler | ||
48 | sil Silicon Image | ||
49 | simtek | ||
50 | sirf SiRF Technology, Inc. | ||
51 | snps Synopsys, Inc. | ||
52 | st STMicroelectronics | ||
53 | stericsson ST-Ericsson | ||
54 | ti Texas Instruments | ||
55 | via VIA Technologies, Inc. | ||
56 | wlf Wolfson Microelectronics | ||
57 | wm Wondermedia Technologies, Inc. | ||
58 | winbond Winbond Electronics corp. | ||
59 | xlnx Xilinx | ||
diff --git a/Documentation/devicetree/bindings/video/backlight/88pm860x.txt b/Documentation/devicetree/bindings/video/backlight/88pm860x.txt deleted file mode 100644 index 261df279931..00000000000 --- a/Documentation/devicetree/bindings/video/backlight/88pm860x.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | 88pm860x-backlight bindings | ||
2 | |||
3 | Optional properties: | ||
4 | - marvell,88pm860x-iset: Current supplies on backlight device. | ||
5 | - marvell,88pm860x-pwm: PWM frequency on backlight device. | ||
6 | |||
7 | Example: | ||
8 | |||
9 | backlights { | ||
10 | backlight-0 { | ||
11 | marvell,88pm860x-iset = <4>; | ||
12 | marvell,88pm860x-pwm = <3>; | ||
13 | }; | ||
14 | backlight-2 { | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt b/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt deleted file mode 100644 index 1e4fc727f3b..00000000000 --- a/Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | pwm-backlight bindings | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "pwm-backlight" | ||
5 | - pwms: OF device-tree PWM specification (see PWM binding[0]) | ||
6 | - brightness-levels: Array of distinct brightness levels. Typically these | ||
7 | are in the range from 0 to 255, but any range starting at 0 will do. | ||
8 | The actual brightness level (PWM duty cycle) will be interpolated | ||
9 | from these values. 0 means a 0% duty cycle (darkest/off), while the | ||
10 | last value in the array represents a 100% duty cycle (brightest). | ||
11 | - default-brightness-level: the default brightness level (index into the | ||
12 | array defined by the "brightness-levels" property) | ||
13 | |||
14 | Optional properties: | ||
15 | - pwm-names: a list of names for the PWM devices specified in the | ||
16 | "pwms" property (see PWM binding[0]) | ||
17 | |||
18 | [0]: Documentation/devicetree/bindings/pwm/pwm.txt | ||
19 | |||
20 | Example: | ||
21 | |||
22 | backlight { | ||
23 | compatible = "pwm-backlight"; | ||
24 | pwms = <&pwm 0 5000000>; | ||
25 | |||
26 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
27 | default-brightness-level = <6>; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt deleted file mode 100644 index c60da67a5d7..00000000000 --- a/Documentation/devicetree/bindings/video/exynos_dp.txt +++ /dev/null | |||
@@ -1,80 +0,0 @@ | |||
1 | The Exynos display port interface should be configured based on | ||
2 | the type of panel connected to it. | ||
3 | |||
4 | We use two nodes: | ||
5 | -dp-controller node | ||
6 | -dptx-phy node(defined inside dp-controller node) | ||
7 | |||
8 | For the DP-PHY initialization, we use the dptx-phy node. | ||
9 | Required properties for dptx-phy: | ||
10 | -reg: | ||
11 | Base address of DP PHY register. | ||
12 | -samsung,enable-mask: | ||
13 | The bit-mask used to enable/disable DP PHY. | ||
14 | |||
15 | For the Panel initialization, we read data from dp-controller node. | ||
16 | Required properties for dp-controller: | ||
17 | -compatible: | ||
18 | should be "samsung,exynos5-dp". | ||
19 | -reg: | ||
20 | physical base address of the controller and length | ||
21 | of memory mapped region. | ||
22 | -interrupts: | ||
23 | interrupt combiner values. | ||
24 | -interrupt-parent: | ||
25 | phandle to Interrupt combiner node. | ||
26 | -samsung,color-space: | ||
27 | input video data format. | ||
28 | COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 | ||
29 | -samsung,dynamic-range: | ||
30 | dynamic range for input video data. | ||
31 | VESA = 0, CEA = 1 | ||
32 | -samsung,ycbcr-coeff: | ||
33 | YCbCr co-efficients for input video. | ||
34 | COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1 | ||
35 | -samsung,color-depth: | ||
36 | number of bits per colour component. | ||
37 | COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3 | ||
38 | -samsung,link-rate: | ||
39 | link rate supported by the panel. | ||
40 | LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A | ||
41 | -samsung,lane-count: | ||
42 | number of lanes supported by the panel. | ||
43 | LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4 | ||
44 | |||
45 | Optional properties for dp-controller: | ||
46 | -interlaced: | ||
47 | interlace scan mode. | ||
48 | Progressive if defined, Interlaced if not defined | ||
49 | -vsync-active-high: | ||
50 | VSYNC polarity configuration. | ||
51 | High if defined, Low if not defined | ||
52 | -hsync-active-high: | ||
53 | HSYNC polarity configuration. | ||
54 | High if defined, Low if not defined | ||
55 | |||
56 | Example: | ||
57 | |||
58 | SOC specific portion: | ||
59 | dp-controller { | ||
60 | compatible = "samsung,exynos5-dp"; | ||
61 | reg = <0x145b0000 0x10000>; | ||
62 | interrupts = <10 3>; | ||
63 | interrupt-parent = <&combiner>; | ||
64 | |||
65 | dptx-phy { | ||
66 | reg = <0x10040720>; | ||
67 | samsung,enable-mask = <1>; | ||
68 | }; | ||
69 | |||
70 | }; | ||
71 | |||
72 | Board Specific portion: | ||
73 | dp-controller { | ||
74 | samsung,color-space = <0>; | ||
75 | samsung,dynamic-range = <0>; | ||
76 | samsung,ycbcr-coeff = <0>; | ||
77 | samsung,color-depth = <1>; | ||
78 | samsung,link-rate = <0x0a>; | ||
79 | samsung,lane-count = <4>; | ||
80 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt b/Documentation/devicetree/bindings/video/ssd1307fb.txt deleted file mode 100644 index 3d0060cff06..00000000000 --- a/Documentation/devicetree/bindings/video/ssd1307fb.txt +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | * Solomon SSD1307 Framebuffer Driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "solomon,ssd1307fb-<bus>". The only supported bus for | ||
5 | now is i2c. | ||
6 | - reg: Should contain address of the controller on the I2C bus. Most likely | ||
7 | 0x3c or 0x3d | ||
8 | - pwm: Should contain the pwm to use according to the OF device tree PWM | ||
9 | specification [0] | ||
10 | - reset-gpios: Should contain the GPIO used to reset the OLED display | ||
11 | |||
12 | Optional properties: | ||
13 | - reset-active-low: Is the reset gpio is active on physical low? | ||
14 | |||
15 | [0]: Documentation/devicetree/bindings/pwm/pwm.txt | ||
16 | |||
17 | Examples: | ||
18 | ssd1307: oled@3c { | ||
19 | compatible = "solomon,ssd1307fb-i2c"; | ||
20 | reg = <0x3c>; | ||
21 | pwms = <&pwm 4 3000>; | ||
22 | reset-gpios = <&gpio2 7>; | ||
23 | reset-active-low; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt deleted file mode 100644 index c870b6478ec..00000000000 --- a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt +++ /dev/null | |||
@@ -1,62 +0,0 @@ | |||
1 | VIA VT8500 Framebuffer | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "via,vt8500-fb" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | - interrupts : framebuffer controller interrupt | ||
8 | - display: a phandle pointing to the display node | ||
9 | |||
10 | Required nodes: | ||
11 | - display: a display node is required to initialize the lcd panel | ||
12 | This should be in the board dts. | ||
13 | - default-mode: a videomode within the display with timing parameters | ||
14 | as specified below. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | fb@d800e400 { | ||
19 | compatible = "via,vt8500-fb"; | ||
20 | reg = <0xd800e400 0x400>; | ||
21 | interrupts = <12>; | ||
22 | display = <&display>; | ||
23 | default-mode = <&mode0>; | ||
24 | }; | ||
25 | |||
26 | VIA VT8500 Display | ||
27 | ----------------------------------------------------- | ||
28 | Required properties (as per of_videomode_helper): | ||
29 | |||
30 | - hactive, vactive: Display resolution | ||
31 | - hfront-porch, hback-porch, hsync-len: Horizontal Display timing parameters | ||
32 | in pixels | ||
33 | vfront-porch, vback-porch, vsync-len: Vertical display timing parameters in | ||
34 | lines | ||
35 | - clock: displayclock in Hz | ||
36 | - bpp: lcd panel bit-depth. | ||
37 | <16> for RGB565, <32> for RGB888 | ||
38 | |||
39 | Optional properties (as per of_videomode_helper): | ||
40 | - width-mm, height-mm: Display dimensions in mm | ||
41 | - hsync-active-high (bool): Hsync pulse is active high | ||
42 | - vsync-active-high (bool): Vsync pulse is active high | ||
43 | - interlaced (bool): This is an interlaced mode | ||
44 | - doublescan (bool): This is a doublescan mode | ||
45 | |||
46 | Example: | ||
47 | display: display@0 { | ||
48 | modes { | ||
49 | mode0: mode@0 { | ||
50 | hactive = <800>; | ||
51 | vactive = <480>; | ||
52 | hback-porch = <88>; | ||
53 | hfront-porch = <40>; | ||
54 | hsync-len = <0>; | ||
55 | vback-porch = <32>; | ||
56 | vfront-porch = <11>; | ||
57 | vsync-len = <1>; | ||
58 | clock = <0>; /* unused but required */ | ||
59 | bpp = <16>; /* non-standard but required */ | ||
60 | }; | ||
61 | }; | ||
62 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt deleted file mode 100644 index a850fa011f0..00000000000 --- a/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | VIA/Wondermedia Graphics Engine Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "wm,prizm-ge-rops" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | |||
8 | Example: | ||
9 | |||
10 | ge_rops@d8050400 { | ||
11 | compatible = "wm,prizm-ge-rops"; | ||
12 | reg = <0xd8050400 0x100>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt deleted file mode 100644 index 3d325e1d11e..00000000000 --- a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | Wondermedia WM8505 Framebuffer | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "wm,wm8505-fb" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | - via,display: a phandle pointing to the display node | ||
8 | |||
9 | Required nodes: | ||
10 | - display: a display node is required to initialize the lcd panel | ||
11 | This should be in the board dts. See definition in | ||
12 | Documentation/devicetree/bindings/video/via,vt8500-fb.txt | ||
13 | - default-mode: a videomode node as specified in | ||
14 | Documentation/devicetree/bindings/video/via,vt8500-fb.txt | ||
15 | |||
16 | Example: | ||
17 | |||
18 | fb@d8050800 { | ||
19 | compatible = "wm,wm8505-fb"; | ||
20 | reg = <0xd8050800 0x200>; | ||
21 | display = <&display>; | ||
22 | default-mode = <&mode0>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/virtio/mmio.txt b/Documentation/devicetree/bindings/virtio/mmio.txt deleted file mode 100644 index 5069c1b8e19..00000000000 --- a/Documentation/devicetree/bindings/virtio/mmio.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | * virtio memory mapped device | ||
2 | |||
3 | See http://ozlabs.org/~rusty/virtio-spec/ for more details. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible: "virtio,mmio" compatibility string | ||
8 | - reg: control registers base address and size including configuration space | ||
9 | - interrupts: interrupt generated by the device | ||
10 | |||
11 | Example: | ||
12 | |||
13 | virtio_block@3000 { | ||
14 | compatible = "virtio,mmio"; | ||
15 | reg = <0x3000 0x100>; | ||
16 | interrupts = <41>; | ||
17 | } | ||
diff --git a/Documentation/devicetree/bindings/w1/w1-gpio.txt b/Documentation/devicetree/bindings/w1/w1-gpio.txt deleted file mode 100644 index 6e09c35d9f1..00000000000 --- a/Documentation/devicetree/bindings/w1/w1-gpio.txt +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | w1-gpio devicetree bindings | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible: "w1-gpio" | ||
6 | - gpios: one or two GPIO specs: | ||
7 | - the first one is used as data I/O pin | ||
8 | - the second one is optional. If specified, it is used as | ||
9 | enable pin for an external pin pullup. | ||
10 | |||
11 | Optional properties: | ||
12 | |||
13 | - linux,open-drain: if specified, the data pin is considered in | ||
14 | open-drain mode. | ||
15 | |||
16 | Examples: | ||
17 | |||
18 | onewire@0 { | ||
19 | compatible = "w1-gpio"; | ||
20 | gpios = <&gpio 126 0>, <&gpio 105 0>; | ||
21 | }; | ||
22 | |||
diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt deleted file mode 100644 index 2957ebb5aa7..00000000000 --- a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | * Atmel Watchdog Timers | ||
2 | |||
3 | ** at91sam9-wdt | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: must be "atmel,at91sam9260-wdt". | ||
7 | - reg: physical base address of the controller and length of memory mapped | ||
8 | region. | ||
9 | |||
10 | Example: | ||
11 | |||
12 | watchdog@fffffd40 { | ||
13 | compatible = "atmel,at91sam9260-wdt"; | ||
14 | reg = <0xfffffd40 0x10>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt b/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt deleted file mode 100644 index d209366b4a6..00000000000 --- a/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | BCM2835 Watchdog timer | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "brcm,bcm2835-pm-wdt" | ||
6 | - reg : Specifies base physical address and size of the registers. | ||
7 | |||
8 | Example: | ||
9 | |||
10 | watchdog { | ||
11 | compatible = "brcm,bcm2835-pm-wdt"; | ||
12 | reg = <0x7e100000 0x28>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt b/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt deleted file mode 100644 index 75558ccd9a0..00000000000 --- a/Documentation/devicetree/bindings/watchdog/davinci-wdt.txt +++ /dev/null | |||
@@ -1,12 +0,0 @@ | |||
1 | DaVinci Watchdog Timer (WDT) Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "ti,davinci-wdt" | ||
5 | - reg : Should contain WDT registers location and length | ||
6 | |||
7 | Examples: | ||
8 | |||
9 | wdt: wdt@2320000 { | ||
10 | compatible = "ti,davinci-wdt"; | ||
11 | reg = <0x02320000 0x80>; | ||
12 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/marvel.txt b/Documentation/devicetree/bindings/watchdog/marvel.txt deleted file mode 100644 index 0b2503ab0a0..00000000000 --- a/Documentation/devicetree/bindings/watchdog/marvel.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | * Marvell Orion Watchdog Time | ||
2 | |||
3 | Required Properties: | ||
4 | |||
5 | - Compatibility : "marvell,orion-wdt" | ||
6 | - reg : Address of the timer registers | ||
7 | |||
8 | Example: | ||
9 | |||
10 | wdt@20300 { | ||
11 | compatible = "marvell,orion-wdt"; | ||
12 | reg = <0x20300 0x28>; | ||
13 | status = "okay"; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt b/Documentation/devicetree/bindings/watchdog/omap-wdt.txt deleted file mode 100644 index c227970671e..00000000000 --- a/Documentation/devicetree/bindings/watchdog/omap-wdt.txt +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | TI Watchdog Timer (WDT) Controller for OMAP | ||
2 | |||
3 | Required properties: | ||
4 | compatible: | ||
5 | - "ti,omap3-wdt" for OMAP3 | ||
6 | - "ti,omap4-wdt" for OMAP4 | ||
7 | - ti,hwmods: Name of the hwmod associated to the WDT | ||
8 | |||
9 | Examples: | ||
10 | |||
11 | wdt2: wdt@4a314000 { | ||
12 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; | ||
13 | ti,hwmods = "wd_timer2"; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt b/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt deleted file mode 100644 index 7c7f6887c79..00000000000 --- a/Documentation/devicetree/bindings/watchdog/pnx4008-wdt.txt +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | * NXP PNX watchdog timer | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "nxp,pnx4008-wdt" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | |||
8 | Example: | ||
9 | |||
10 | watchdog@4003C000 { | ||
11 | compatible = "nxp,pnx4008-wdt"; | ||
12 | reg = <0x4003C000 0x1000>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt deleted file mode 100644 index 0b271777560..00000000000 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | Allwinner sunXi Watchdog timer | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "allwinner,sunxi-wdt" | ||
6 | - reg : Specifies base physical address and size of the registers. | ||
7 | |||
8 | Example: | ||
9 | |||
10 | wdt: watchdog@01c20c90 { | ||
11 | compatible = "allwinner,sunxi-wdt"; | ||
12 | reg = <0x01c20c90 0x10>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt b/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt deleted file mode 100644 index 80a37193c0b..00000000000 --- a/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt +++ /dev/null | |||
@@ -1,10 +0,0 @@ | |||
1 | Device tree bindings for twl4030-wdt driver (TWL4030 watchdog) | ||
2 | |||
3 | Required properties: | ||
4 | compatible = "ti,twl4030-wdt"; | ||
5 | |||
6 | Example: | ||
7 | |||
8 | watchdog { | ||
9 | compatible = "ti,twl4030-wdt"; | ||
10 | }; | ||
diff --git a/Documentation/devicetree/booting-without-of.txt b/Documentation/devicetree/booting-without-of.txt index d4d66757354..7c1329de059 100644 --- a/Documentation/devicetree/booting-without-of.txt +++ b/Documentation/devicetree/booting-without-of.txt | |||
@@ -169,7 +169,7 @@ it with special cases. | |||
169 | 169 | ||
170 | b) Entry with a flattened device-tree block. Firmware loads the | 170 | b) Entry with a flattened device-tree block. Firmware loads the |
171 | physical address of the flattened device tree block (dtb) into r2, | 171 | physical address of the flattened device tree block (dtb) into r2, |
172 | r1 is not used, but it is considered good practice to use a valid | 172 | r1 is not used, but it is considered good practise to use a valid |
173 | machine number as described in Documentation/arm/Booting. | 173 | machine number as described in Documentation/arm/Booting. |
174 | 174 | ||
175 | r0 : 0 | 175 | r0 : 0 |
@@ -551,13 +551,12 @@ Here is an example of a simple device-tree. In this example, an "o" | |||
551 | designates a node followed by the node unit name. Properties are | 551 | designates a node followed by the node unit name. Properties are |
552 | presented with their name followed by their content. "content" | 552 | presented with their name followed by their content. "content" |
553 | represents an ASCII string (zero terminated) value, while <content> | 553 | represents an ASCII string (zero terminated) value, while <content> |
554 | represents a 32-bit value, specified in decimal or hexadecimal (the | 554 | represents a 32-bit hexadecimal value. The various nodes in this |
555 | latter prefixed 0x). The various nodes in this example will be | 555 | example will be discussed in a later chapter. At this point, it is |
556 | discussed in a later chapter. At this point, it is only meant to give | 556 | only meant to give you a idea of what a device-tree looks like. I have |
557 | you a idea of what a device-tree looks like. I have purposefully kept | 557 | purposefully kept the "name" and "linux,phandle" properties which |
558 | the "name" and "linux,phandle" properties which aren't necessary in | 558 | aren't necessary in order to give you a better idea of what the tree |
559 | order to give you a better idea of what the tree looks like in | 559 | looks like in practice. |
560 | practice. | ||
561 | 560 | ||
562 | / o device-tree | 561 | / o device-tree |
563 | |- name = "device-tree" | 562 | |- name = "device-tree" |
@@ -577,14 +576,14 @@ practice. | |||
577 | | |- name = "PowerPC,970" | 576 | | |- name = "PowerPC,970" |
578 | | |- device_type = "cpu" | 577 | | |- device_type = "cpu" |
579 | | |- reg = <0> | 578 | | |- reg = <0> |
580 | | |- clock-frequency = <0x5f5e1000> | 579 | | |- clock-frequency = <5f5e1000> |
581 | | |- 64-bit | 580 | | |- 64-bit |
582 | | |- linux,phandle = <2> | 581 | | |- linux,phandle = <2> |
583 | | | 582 | | |
584 | o memory@0 | 583 | o memory@0 |
585 | | |- name = "memory" | 584 | | |- name = "memory" |
586 | | |- device_type = "memory" | 585 | | |- device_type = "memory" |
587 | | |- reg = <0x00000000 0x00000000 0x00000000 0x20000000> | 586 | | |- reg = <00000000 00000000 00000000 20000000> |
588 | | |- linux,phandle = <3> | 587 | | |- linux,phandle = <3> |
589 | | | 588 | | |
590 | o chosen | 589 | o chosen |
@@ -1011,8 +1010,8 @@ compatibility. | |||
1011 | #size-cells = <1>; | 1010 | #size-cells = <1>; |
1012 | #interrupt-cells = <2>; | 1011 | #interrupt-cells = <2>; |
1013 | device_type = "soc"; | 1012 | device_type = "soc"; |
1014 | ranges = <0x00000000 0xe0000000 0x00100000> | 1013 | ranges = <00000000 e0000000 00100000> |
1015 | reg = <0xe0000000 0x00003000>; | 1014 | reg = <e0000000 00003000>; |
1016 | bus-frequency = <0>; | 1015 | bus-frequency = <0>; |
1017 | } | 1016 | } |
1018 | 1017 | ||
@@ -1086,16 +1085,16 @@ supported currently at the toplevel. | |||
1086 | * terminated string | 1085 | * terminated string |
1087 | */ | 1086 | */ |
1088 | 1087 | ||
1089 | property2 = <0x1234abcd>; /* define a property containing a | 1088 | property2 = <1234abcd>; /* define a property containing a |
1090 | * numerical 32-bit value (hexadecimal) | 1089 | * numerical 32-bit value (hexadecimal) |
1091 | */ | 1090 | */ |
1092 | 1091 | ||
1093 | property3 = <0x12345678 0x12345678 0xdeadbeef>; | 1092 | property3 = <12345678 12345678 deadbeef>; |
1094 | /* define a property containing 3 | 1093 | /* define a property containing 3 |
1095 | * numerical 32-bit values (cells) in | 1094 | * numerical 32-bit values (cells) in |
1096 | * hexadecimal | 1095 | * hexadecimal |
1097 | */ | 1096 | */ |
1098 | property4 = [0x0a 0x0b 0x0c 0x0d 0xde 0xea 0xad 0xbe 0xef]; | 1097 | property4 = [0a 0b 0c 0d de ea ad be ef]; |
1099 | /* define a property whose content is | 1098 | /* define a property whose content is |
1100 | * an arbitrary array of bytes | 1099 | * an arbitrary array of bytes |
1101 | */ | 1100 | */ |
@@ -1351,10 +1350,10 @@ Appendix A - Sample SOC node for MPC8540 | |||
1351 | model = "TSEC"; | 1350 | model = "TSEC"; |
1352 | compatible = "gianfar", "simple-bus"; | 1351 | compatible = "gianfar", "simple-bus"; |
1353 | reg = <0x24000 0x1000>; | 1352 | reg = <0x24000 0x1000>; |
1354 | local-mac-address = [ 0x00 0xE0 0x0C 0x00 0x73 0x00 ]; | 1353 | local-mac-address = [ 00 E0 0C 00 73 00 ]; |
1355 | interrupts = <0x29 2 0x30 2 0x34 2>; | 1354 | interrupts = <29 2 30 2 34 2>; |
1356 | phy-handle = <&phy0>; | 1355 | phy-handle = <&phy0>; |
1357 | sleep = <&pmc 0x00000080>; | 1356 | sleep = <&pmc 00000080>; |
1358 | ranges; | 1357 | ranges; |
1359 | 1358 | ||
1360 | mdio@24520 { | 1359 | mdio@24520 { |
@@ -1386,10 +1385,10 @@ Appendix A - Sample SOC node for MPC8540 | |||
1386 | model = "TSEC"; | 1385 | model = "TSEC"; |
1387 | compatible = "gianfar"; | 1386 | compatible = "gianfar"; |
1388 | reg = <0x25000 0x1000>; | 1387 | reg = <0x25000 0x1000>; |
1389 | local-mac-address = [ 0x00 0xE0 0x0C 0x00 0x73 0x01 ]; | 1388 | local-mac-address = [ 00 E0 0C 00 73 01 ]; |
1390 | interrupts = <0x13 2 0x14 2 0x18 2>; | 1389 | interrupts = <13 2 14 2 18 2>; |
1391 | phy-handle = <&phy1>; | 1390 | phy-handle = <&phy1>; |
1392 | sleep = <&pmc 0x00000040>; | 1391 | sleep = <&pmc 00000040>; |
1393 | }; | 1392 | }; |
1394 | 1393 | ||
1395 | ethernet@26000 { | 1394 | ethernet@26000 { |
@@ -1397,17 +1396,17 @@ Appendix A - Sample SOC node for MPC8540 | |||
1397 | model = "FEC"; | 1396 | model = "FEC"; |
1398 | compatible = "gianfar"; | 1397 | compatible = "gianfar"; |
1399 | reg = <0x26000 0x1000>; | 1398 | reg = <0x26000 0x1000>; |
1400 | local-mac-address = [ 0x00 0xE0 0x0C 0x00 0x73 0x02 ]; | 1399 | local-mac-address = [ 00 E0 0C 00 73 02 ]; |
1401 | interrupts = <0x41 2>; | 1400 | interrupts = <41 2>; |
1402 | phy-handle = <&phy3>; | 1401 | phy-handle = <&phy3>; |
1403 | sleep = <&pmc 0x00000020>; | 1402 | sleep = <&pmc 00000020>; |
1404 | }; | 1403 | }; |
1405 | 1404 | ||
1406 | serial@4500 { | 1405 | serial@4500 { |
1407 | #address-cells = <1>; | 1406 | #address-cells = <1>; |
1408 | #size-cells = <1>; | 1407 | #size-cells = <1>; |
1409 | compatible = "fsl,mpc8540-duart", "simple-bus"; | 1408 | compatible = "fsl,mpc8540-duart", "simple-bus"; |
1410 | sleep = <&pmc 0x00000002>; | 1409 | sleep = <&pmc 00000002>; |
1411 | ranges; | 1410 | ranges; |
1412 | 1411 | ||
1413 | serial@4500 { | 1412 | serial@4500 { |
@@ -1415,7 +1414,7 @@ Appendix A - Sample SOC node for MPC8540 | |||
1415 | compatible = "ns16550"; | 1414 | compatible = "ns16550"; |
1416 | reg = <0x4500 0x100>; | 1415 | reg = <0x4500 0x100>; |
1417 | clock-frequency = <0>; | 1416 | clock-frequency = <0>; |
1418 | interrupts = <0x42 2>; | 1417 | interrupts = <42 2>; |
1419 | }; | 1418 | }; |
1420 | 1419 | ||
1421 | serial@4600 { | 1420 | serial@4600 { |
@@ -1423,7 +1422,7 @@ Appendix A - Sample SOC node for MPC8540 | |||
1423 | compatible = "ns16550"; | 1422 | compatible = "ns16550"; |
1424 | reg = <0x4600 0x100>; | 1423 | reg = <0x4600 0x100>; |
1425 | clock-frequency = <0>; | 1424 | clock-frequency = <0>; |
1426 | interrupts = <0x42 2>; | 1425 | interrupts = <42 2>; |
1427 | }; | 1426 | }; |
1428 | }; | 1427 | }; |
1429 | 1428 | ||
@@ -1437,11 +1436,11 @@ Appendix A - Sample SOC node for MPC8540 | |||
1437 | }; | 1436 | }; |
1438 | 1437 | ||
1439 | i2c@3000 { | 1438 | i2c@3000 { |
1440 | interrupts = <0x43 2>; | 1439 | interrupts = <43 2>; |
1441 | reg = <0x3000 0x100>; | 1440 | reg = <0x3000 0x100>; |
1442 | compatible = "fsl-i2c"; | 1441 | compatible = "fsl-i2c"; |
1443 | dfsrr; | 1442 | dfsrr; |
1444 | sleep = <&pmc 0x00000004>; | 1443 | sleep = <&pmc 00000004>; |
1445 | }; | 1444 | }; |
1446 | 1445 | ||
1447 | pmc: power@e0070 { | 1446 | pmc: power@e0070 { |
diff --git a/Documentation/devicetree/usage-model.txt b/Documentation/devicetree/usage-model.txt deleted file mode 100644 index ef9d06c9f8f..00000000000 --- a/Documentation/devicetree/usage-model.txt +++ /dev/null | |||
@@ -1,412 +0,0 @@ | |||
1 | Linux and the Device Tree | ||
2 | ------------------------- | ||
3 | The Linux usage model for device tree data | ||
4 | |||
5 | Author: Grant Likely <grant.likely@secretlab.ca> | ||
6 | |||
7 | This article describes how Linux uses the device tree. An overview of | ||
8 | the device tree data format can be found on the device tree usage page | ||
9 | at devicetree.org[1]. | ||
10 | |||
11 | [1] http://devicetree.org/Device_Tree_Usage | ||
12 | |||
13 | The "Open Firmware Device Tree", or simply Device Tree (DT), is a data | ||
14 | structure and language for describing hardware. More specifically, it | ||
15 | is a description of hardware that is readable by an operating system | ||
16 | so that the operating system doesn't need to hard code details of the | ||
17 | machine. | ||
18 | |||
19 | Structurally, the DT is a tree, or acyclic graph with named nodes, and | ||
20 | nodes may have an arbitrary number of named properties encapsulating | ||
21 | arbitrary data. A mechanism also exists to create arbitrary | ||
22 | links from one node to another outside of the natural tree structure. | ||
23 | |||
24 | Conceptually, a common set of usage conventions, called 'bindings', | ||
25 | is defined for how data should appear in the tree to describe typical | ||
26 | hardware characteristics including data busses, interrupt lines, GPIO | ||
27 | connections, and peripheral devices. | ||
28 | |||
29 | As much as possible, hardware is described using existing bindings to | ||
30 | maximize use of existing support code, but since property and node | ||
31 | names are simply text strings, it is easy to extend existing bindings | ||
32 | or create new ones by defining new nodes and properties. Be wary, | ||
33 | however, of creating a new binding without first doing some homework | ||
34 | about what already exists. There are currently two different, | ||
35 | incompatible, bindings for i2c busses that came about because the new | ||
36 | binding was created without first investigating how i2c devices were | ||
37 | already being enumerated in existing systems. | ||
38 | |||
39 | 1. History | ||
40 | ---------- | ||
41 | The DT was originally created by Open Firmware as part of the | ||
42 | communication method for passing data from Open Firmware to a client | ||
43 | program (like to an operating system). An operating system used the | ||
44 | Device Tree to discover the topology of the hardware at runtime, and | ||
45 | thereby support a majority of available hardware without hard coded | ||
46 | information (assuming drivers were available for all devices). | ||
47 | |||
48 | Since Open Firmware is commonly used on PowerPC and SPARC platforms, | ||
49 | the Linux support for those architectures has for a long time used the | ||
50 | Device Tree. | ||
51 | |||
52 | In 2005, when PowerPC Linux began a major cleanup and to merge 32-bit | ||
53 | and 64-bit support, the decision was made to require DT support on all | ||
54 | powerpc platforms, regardless of whether or not they used Open | ||
55 | Firmware. To do this, a DT representation called the Flattened Device | ||
56 | Tree (FDT) was created which could be passed to the kernel as a binary | ||
57 | blob without requiring a real Open Firmware implementation. U-Boot, | ||
58 | kexec, and other bootloaders were modified to support both passing a | ||
59 | Device Tree Binary (dtb) and to modify a dtb at boot time. DT was | ||
60 | also added to the PowerPC boot wrapper (arch/powerpc/boot/*) so that | ||
61 | a dtb could be wrapped up with the kernel image to support booting | ||
62 | existing non-DT aware firmware. | ||
63 | |||
64 | Some time later, FDT infrastructure was generalized to be usable by | ||
65 | all architectures. At the time of this writing, 6 mainlined | ||
66 | architectures (arm, microblaze, mips, powerpc, sparc, and x86) and 1 | ||
67 | out of mainline (nios) have some level of DT support. | ||
68 | |||
69 | 2. Data Model | ||
70 | ------------- | ||
71 | If you haven't already read the Device Tree Usage[1] page, | ||
72 | then go read it now. It's okay, I'll wait.... | ||
73 | |||
74 | 2.1 High Level View | ||
75 | ------------------- | ||
76 | The most important thing to understand is that the DT is simply a data | ||
77 | structure that describes the hardware. There is nothing magical about | ||
78 | it, and it doesn't magically make all hardware configuration problems | ||
79 | go away. What it does do is provide a language for decoupling the | ||
80 | hardware configuration from the board and device driver support in the | ||
81 | Linux kernel (or any other operating system for that matter). Using | ||
82 | it allows board and device support to become data driven; to make | ||
83 | setup decisions based on data passed into the kernel instead of on | ||
84 | per-machine hard coded selections. | ||
85 | |||
86 | Ideally, data driven platform setup should result in less code | ||
87 | duplication and make it easier to support a wide range of hardware | ||
88 | with a single kernel image. | ||
89 | |||
90 | Linux uses DT data for three major purposes: | ||
91 | 1) platform identification, | ||
92 | 2) runtime configuration, and | ||
93 | 3) device population. | ||
94 | |||
95 | 2.2 Platform Identification | ||
96 | --------------------------- | ||
97 | First and foremost, the kernel will use data in the DT to identify the | ||
98 | specific machine. In a perfect world, the specific platform shouldn't | ||
99 | matter to the kernel because all platform details would be described | ||
100 | perfectly by the device tree in a consistent and reliable manner. | ||
101 | Hardware is not perfect though, and so the kernel must identify the | ||
102 | machine during early boot so that it has the opportunity to run | ||
103 | machine-specific fixups. | ||
104 | |||
105 | In the majority of cases, the machine identity is irrelevant, and the | ||
106 | kernel will instead select setup code based on the machine's core | ||
107 | CPU or SoC. On ARM for example, setup_arch() in | ||
108 | arch/arm/kernel/setup.c will call setup_machine_fdt() in | ||
109 | arch/arm/kernel/devicetree.c which searches through the machine_desc | ||
110 | table and selects the machine_desc which best matches the device tree | ||
111 | data. It determines the best match by looking at the 'compatible' | ||
112 | property in the root device tree node, and comparing it with the | ||
113 | dt_compat list in struct machine_desc. | ||
114 | |||
115 | The 'compatible' property contains a sorted list of strings starting | ||
116 | with the exact name of the machine, followed by an optional list of | ||
117 | boards it is compatible with sorted from most compatible to least. For | ||
118 | example, the root compatible properties for the TI BeagleBoard and its | ||
119 | successor, the BeagleBoard xM board might look like: | ||
120 | |||
121 | compatible = "ti,omap3-beagleboard", "ti,omap3450", "ti,omap3"; | ||
122 | compatible = "ti,omap3-beagleboard-xm", "ti,omap3450", "ti,omap3"; | ||
123 | |||
124 | Where "ti,omap3-beagleboard-xm" specifies the exact model, it also | ||
125 | claims that it compatible with the OMAP 3450 SoC, and the omap3 family | ||
126 | of SoCs in general. You'll notice that the list is sorted from most | ||
127 | specific (exact board) to least specific (SoC family). | ||
128 | |||
129 | Astute readers might point out that the Beagle xM could also claim | ||
130 | compatibility with the original Beagle board. However, one should be | ||
131 | cautioned about doing so at the board level since there is typically a | ||
132 | high level of change from one board to another, even within the same | ||
133 | product line, and it is hard to nail down exactly what is meant when one | ||
134 | board claims to be compatible with another. For the top level, it is | ||
135 | better to err on the side of caution and not claim one board is | ||
136 | compatible with another. The notable exception would be when one | ||
137 | board is a carrier for another, such as a CPU module attached to a | ||
138 | carrier board. | ||
139 | |||
140 | One more note on compatible values. Any string used in a compatible | ||
141 | property must be documented as to what it indicates. Add | ||
142 | documentation for compatible strings in Documentation/devicetree/bindings. | ||
143 | |||
144 | Again on ARM, for each machine_desc, the kernel looks to see if | ||
145 | any of the dt_compat list entries appear in the compatible property. | ||
146 | If one does, then that machine_desc is a candidate for driving the | ||
147 | machine. After searching the entire table of machine_descs, | ||
148 | setup_machine_fdt() returns the 'most compatible' machine_desc based | ||
149 | on which entry in the compatible property each machine_desc matches | ||
150 | against. If no matching machine_desc is found, then it returns NULL. | ||
151 | |||
152 | The reasoning behind this scheme is the observation that in the majority | ||
153 | of cases, a single machine_desc can support a large number of boards | ||
154 | if they all use the same SoC, or same family of SoCs. However, | ||
155 | invariably there will be some exceptions where a specific board will | ||
156 | require special setup code that is not useful in the generic case. | ||
157 | Special cases could be handled by explicitly checking for the | ||
158 | troublesome board(s) in generic setup code, but doing so very quickly | ||
159 | becomes ugly and/or unmaintainable if it is more than just a couple of | ||
160 | cases. | ||
161 | |||
162 | Instead, the compatible list allows a generic machine_desc to provide | ||
163 | support for a wide common set of boards by specifying "less | ||
164 | compatible" value in the dt_compat list. In the example above, | ||
165 | generic board support can claim compatibility with "ti,omap3" or | ||
166 | "ti,omap3450". If a bug was discovered on the original beagleboard | ||
167 | that required special workaround code during early boot, then a new | ||
168 | machine_desc could be added which implements the workarounds and only | ||
169 | matches on "ti,omap3-beagleboard". | ||
170 | |||
171 | PowerPC uses a slightly different scheme where it calls the .probe() | ||
172 | hook from each machine_desc, and the first one returning TRUE is used. | ||
173 | However, this approach does not take into account the priority of the | ||
174 | compatible list, and probably should be avoided for new architecture | ||
175 | support. | ||
176 | |||
177 | 2.3 Runtime configuration | ||
178 | ------------------------- | ||
179 | In most cases, a DT will be the sole method of communicating data from | ||
180 | firmware to the kernel, so also gets used to pass in runtime and | ||
181 | configuration data like the kernel parameters string and the location | ||
182 | of an initrd image. | ||
183 | |||
184 | Most of this data is contained in the /chosen node, and when booting | ||
185 | Linux it will look something like this: | ||
186 | |||
187 | chosen { | ||
188 | bootargs = "console=ttyS0,115200 loglevel=8"; | ||
189 | initrd-start = <0xc8000000>; | ||
190 | initrd-end = <0xc8200000>; | ||
191 | }; | ||
192 | |||
193 | The bootargs property contains the kernel arguments, and the initrd-* | ||
194 | properties define the address and size of an initrd blob. The | ||
195 | chosen node may also optionally contain an arbitrary number of | ||
196 | additional properties for platform-specific configuration data. | ||
197 | |||
198 | During early boot, the architecture setup code calls of_scan_flat_dt() | ||
199 | several times with different helper callbacks to parse device tree | ||
200 | data before paging is setup. The of_scan_flat_dt() code scans through | ||
201 | the device tree and uses the helpers to extract information required | ||
202 | during early boot. Typically the early_init_dt_scan_chosen() helper | ||
203 | is used to parse the chosen node including kernel parameters, | ||
204 | early_init_dt_scan_root() to initialize the DT address space model, | ||
205 | and early_init_dt_scan_memory() to determine the size and | ||
206 | location of usable RAM. | ||
207 | |||
208 | On ARM, the function setup_machine_fdt() is responsible for early | ||
209 | scanning of the device tree after selecting the correct machine_desc | ||
210 | that supports the board. | ||
211 | |||
212 | 2.4 Device population | ||
213 | --------------------- | ||
214 | After the board has been identified, and after the early configuration data | ||
215 | has been parsed, then kernel initialization can proceed in the normal | ||
216 | way. At some point in this process, unflatten_device_tree() is called | ||
217 | to convert the data into a more efficient runtime representation. | ||
218 | This is also when machine-specific setup hooks will get called, like | ||
219 | the machine_desc .init_early(), .init_irq() and .init_machine() hooks | ||
220 | on ARM. The remainder of this section uses examples from the ARM | ||
221 | implementation, but all architectures will do pretty much the same | ||
222 | thing when using a DT. | ||
223 | |||
224 | As can be guessed by the names, .init_early() is used for any machine- | ||
225 | specific setup that needs to be executed early in the boot process, | ||
226 | and .init_irq() is used to set up interrupt handling. Using a DT | ||
227 | doesn't materially change the behaviour of either of these functions. | ||
228 | If a DT is provided, then both .init_early() and .init_irq() are able | ||
229 | to call any of the DT query functions (of_* in include/linux/of*.h) to | ||
230 | get additional data about the platform. | ||
231 | |||
232 | The most interesting hook in the DT context is .init_machine() which | ||
233 | is primarily responsible for populating the Linux device model with | ||
234 | data about the platform. Historically this has been implemented on | ||
235 | embedded platforms by defining a set of static clock structures, | ||
236 | platform_devices, and other data in the board support .c file, and | ||
237 | registering it en-masse in .init_machine(). When DT is used, then | ||
238 | instead of hard coding static devices for each platform, the list of | ||
239 | devices can be obtained by parsing the DT, and allocating device | ||
240 | structures dynamically. | ||
241 | |||
242 | The simplest case is when .init_machine() is only responsible for | ||
243 | registering a block of platform_devices. A platform_device is a concept | ||
244 | used by Linux for memory or I/O mapped devices which cannot be detected | ||
245 | by hardware, and for 'composite' or 'virtual' devices (more on those | ||
246 | later). While there is no 'platform device' terminology for the DT, | ||
247 | platform devices roughly correspond to device nodes at the root of the | ||
248 | tree and children of simple memory mapped bus nodes. | ||
249 | |||
250 | About now is a good time to lay out an example. Here is part of the | ||
251 | device tree for the NVIDIA Tegra board. | ||
252 | |||
253 | /{ | ||
254 | compatible = "nvidia,harmony", "nvidia,tegra20"; | ||
255 | #address-cells = <1>; | ||
256 | #size-cells = <1>; | ||
257 | interrupt-parent = <&intc>; | ||
258 | |||
259 | chosen { }; | ||
260 | aliases { }; | ||
261 | |||
262 | memory { | ||
263 | device_type = "memory"; | ||
264 | reg = <0x00000000 0x40000000>; | ||
265 | }; | ||
266 | |||
267 | soc { | ||
268 | compatible = "nvidia,tegra20-soc", "simple-bus"; | ||
269 | #address-cells = <1>; | ||
270 | #size-cells = <1>; | ||
271 | ranges; | ||
272 | |||
273 | intc: interrupt-controller@50041000 { | ||
274 | compatible = "nvidia,tegra20-gic"; | ||
275 | interrupt-controller; | ||
276 | #interrupt-cells = <1>; | ||
277 | reg = <0x50041000 0x1000>, < 0x50040100 0x0100 >; | ||
278 | }; | ||
279 | |||
280 | serial@70006300 { | ||
281 | compatible = "nvidia,tegra20-uart"; | ||
282 | reg = <0x70006300 0x100>; | ||
283 | interrupts = <122>; | ||
284 | }; | ||
285 | |||
286 | i2s1: i2s@70002800 { | ||
287 | compatible = "nvidia,tegra20-i2s"; | ||
288 | reg = <0x70002800 0x100>; | ||
289 | interrupts = <77>; | ||
290 | codec = <&wm8903>; | ||
291 | }; | ||
292 | |||
293 | i2c@7000c000 { | ||
294 | compatible = "nvidia,tegra20-i2c"; | ||
295 | #address-cells = <1>; | ||
296 | #size-cells = <0>; | ||
297 | reg = <0x7000c000 0x100>; | ||
298 | interrupts = <70>; | ||
299 | |||
300 | wm8903: codec@1a { | ||
301 | compatible = "wlf,wm8903"; | ||
302 | reg = <0x1a>; | ||
303 | interrupts = <347>; | ||
304 | }; | ||
305 | }; | ||
306 | }; | ||
307 | |||
308 | sound { | ||
309 | compatible = "nvidia,harmony-sound"; | ||
310 | i2s-controller = <&i2s1>; | ||
311 | i2s-codec = <&wm8903>; | ||
312 | }; | ||
313 | }; | ||
314 | |||
315 | At .init_machine() time, Tegra board support code will need to look at | ||
316 | this DT and decide which nodes to create platform_devices for. | ||
317 | However, looking at the tree, it is not immediately obvious what kind | ||
318 | of device each node represents, or even if a node represents a device | ||
319 | at all. The /chosen, /aliases, and /memory nodes are informational | ||
320 | nodes that don't describe devices (although arguably memory could be | ||
321 | considered a device). The children of the /soc node are memory mapped | ||
322 | devices, but the codec@1a is an i2c device, and the sound node | ||
323 | represents not a device, but rather how other devices are connected | ||
324 | together to create the audio subsystem. I know what each device is | ||
325 | because I'm familiar with the board design, but how does the kernel | ||
326 | know what to do with each node? | ||
327 | |||
328 | The trick is that the kernel starts at the root of the tree and looks | ||
329 | for nodes that have a 'compatible' property. First, it is generally | ||
330 | assumed that any node with a 'compatible' property represents a device | ||
331 | of some kind, and second, it can be assumed that any node at the root | ||
332 | of the tree is either directly attached to the processor bus, or is a | ||
333 | miscellaneous system device that cannot be described any other way. | ||
334 | For each of these nodes, Linux allocates and registers a | ||
335 | platform_device, which in turn may get bound to a platform_driver. | ||
336 | |||
337 | Why is using a platform_device for these nodes a safe assumption? | ||
338 | Well, for the way that Linux models devices, just about all bus_types | ||
339 | assume that its devices are children of a bus controller. For | ||
340 | example, each i2c_client is a child of an i2c_master. Each spi_device | ||
341 | is a child of an SPI bus. Similarly for USB, PCI, MDIO, etc. The | ||
342 | same hierarchy is also found in the DT, where I2C device nodes only | ||
343 | ever appear as children of an I2C bus node. Ditto for SPI, MDIO, USB, | ||
344 | etc. The only devices which do not require a specific type of parent | ||
345 | device are platform_devices (and amba_devices, but more on that | ||
346 | later), which will happily live at the base of the Linux /sys/devices | ||
347 | tree. Therefore, if a DT node is at the root of the tree, then it | ||
348 | really probably is best registered as a platform_device. | ||
349 | |||
350 | Linux board support code calls of_platform_populate(NULL, NULL, NULL, NULL) | ||
351 | to kick off discovery of devices at the root of the tree. The | ||
352 | parameters are all NULL because when starting from the root of the | ||
353 | tree, there is no need to provide a starting node (the first NULL), a | ||
354 | parent struct device (the last NULL), and we're not using a match | ||
355 | table (yet). For a board that only needs to register devices, | ||
356 | .init_machine() can be completely empty except for the | ||
357 | of_platform_populate() call. | ||
358 | |||
359 | In the Tegra example, this accounts for the /soc and /sound nodes, but | ||
360 | what about the children of the SoC node? Shouldn't they be registered | ||
361 | as platform devices too? For Linux DT support, the generic behaviour | ||
362 | is for child devices to be registered by the parent's device driver at | ||
363 | driver .probe() time. So, an i2c bus device driver will register a | ||
364 | i2c_client for each child node, an SPI bus driver will register | ||
365 | its spi_device children, and similarly for other bus_types. | ||
366 | According to that model, a driver could be written that binds to the | ||
367 | SoC node and simply registers platform_devices for each of its | ||
368 | children. The board support code would allocate and register an SoC | ||
369 | device, a (theoretical) SoC device driver could bind to the SoC device, | ||
370 | and register platform_devices for /soc/interrupt-controller, /soc/serial, | ||
371 | /soc/i2s, and /soc/i2c in its .probe() hook. Easy, right? | ||
372 | |||
373 | Actually, it turns out that registering children of some | ||
374 | platform_devices as more platform_devices is a common pattern, and the | ||
375 | device tree support code reflects that and makes the above example | ||
376 | simpler. The second argument to of_platform_populate() is an | ||
377 | of_device_id table, and any node that matches an entry in that table | ||
378 | will also get its child nodes registered. In the tegra case, the code | ||
379 | can look something like this: | ||
380 | |||
381 | static void __init harmony_init_machine(void) | ||
382 | { | ||
383 | /* ... */ | ||
384 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
385 | } | ||
386 | |||
387 | "simple-bus" is defined in the ePAPR 1.0 specification as a property | ||
388 | meaning a simple memory mapped bus, so the of_platform_populate() code | ||
389 | could be written to just assume simple-bus compatible nodes will | ||
390 | always be traversed. However, we pass it in as an argument so that | ||
391 | board support code can always override the default behaviour. | ||
392 | |||
393 | [Need to add discussion of adding i2c/spi/etc child devices] | ||
394 | |||
395 | Appendix A: AMBA devices | ||
396 | ------------------------ | ||
397 | |||
398 | ARM Primecells are a certain kind of device attached to the ARM AMBA | ||
399 | bus which include some support for hardware detection and power | ||
400 | management. In Linux, struct amba_device and the amba_bus_type is | ||
401 | used to represent Primecell devices. However, the fiddly bit is that | ||
402 | not all devices on an AMBA bus are Primecells, and for Linux it is | ||
403 | typical for both amba_device and platform_device instances to be | ||
404 | siblings of the same bus segment. | ||
405 | |||
406 | When using the DT, this creates problems for of_platform_populate() | ||
407 | because it must decide whether to register each node as either a | ||
408 | platform_device or an amba_device. This unfortunately complicates the | ||
409 | device creation model a little bit, but the solution turns out not to | ||
410 | be too invasive. If a node is compatible with "arm,amba-primecell", then | ||
411 | of_platform_populate() will register it as an amba_device instead of a | ||
412 | platform_device. | ||